Archived
94 lines
2.5 KiB
Verilog
94 lines
2.5 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2023/03/06 16:15:00
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// Design Name:
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// Module Name: tx_control
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tx_control
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(
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input clk ,
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input rst ,
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output [11:0] tx_data_i ,
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output [11:0] tx_data_q ,
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// debug ports
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input [ 2:0] waveform_sel,
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input sweep_on ,
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input [31:0] freq_set ,
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input [ 1:0] iq_sel ,
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input [ 3:0] bb_rshift
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);
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wire [11:0] gmsk_12m_i, gmsk_12m_q;
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wire [11:0] gmsk_1p5m_i, gmsk_1p5m_q;
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wire [11:0] qpsk_i, qpsk_q;
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GMSK_send u_GMSK_send
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(
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.clk_48M (clk ),
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.rst (rst ),
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.gmsk_12M_i (gmsk_12m_i ),
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.gmsk_12M_q (gmsk_12m_q ),
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.gmsk_1p5m_i (gmsk_1p5m_i ),
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.gmsk_1p5m_q (gmsk_1p5m_q )
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);
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tx_qpsk u_tx_qpsk
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(
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.clk (clk ), // input clk
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.rst (rst ), // input rst
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.tx_data_i (qpsk_i ), // output [11:0] tx_data_i
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.tx_data_q (qpsk_q ), // output [11:0] tx_data_q
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// debug ports
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.waveform_sel (waveform_sel[1:0] ), // input [ 1:0] waveform_sel
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.sweep_on (sweep_on ), // input sweep_on
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.freq_set (freq_set ), // input [31:0] freq_set
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.iq_sel (iq_sel ), // input [ 1:0] iq_sel
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.bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift
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);
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// tx buf
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reg [11:0] tx_data_i_buf = 'b0;
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reg [11:0] tx_data_q_buf = 'b0;
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assign tx_data_i = tx_data_i_buf;
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assign tx_data_q = tx_data_q_buf;
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always @(posedge clk) begin
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if (rst) begin
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tx_data_i_buf <= 'b0;
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tx_data_q_buf <= 'b0;
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end
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else casex (waveform_sel)
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3'b10x: begin
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tx_data_i_buf <= gmsk_12m_i;
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tx_data_q_buf <= gmsk_12m_q;
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end
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3'b11x: begin
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tx_data_i_buf <= gmsk_1p5m_i;
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tx_data_q_buf <= gmsk_1p5m_q;
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end
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default: begin
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tx_data_i_buf <= qpsk_i;
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tx_data_q_buf <= qpsk_q;
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end
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endcase
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end
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endmodule
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