Archived
141 lines
4.6 KiB
Verilog
141 lines
4.6 KiB
Verilog
//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact [email protected] for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module jesd204_rx_ctrl_64b #(
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parameter NUM_LANES = 1
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) (
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input clk,
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input reset,
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input [NUM_LANES-1:0] cfg_lanes_disable,
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input [NUM_LANES-1:0] phy_block_sync,
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input [NUM_LANES-1:0] emb_lock,
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output all_emb_lock,
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input buffer_release_n,
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output [1:0] status_state,
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output reg event_unexpected_lane_state_error
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);
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localparam STATE_RESET = 2'b00;
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localparam STATE_WAIT_BS = 2'b01;
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localparam STATE_BLOCK_SYNC = 2'b10;
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localparam STATE_DATA = 2'b11;
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reg [1:0] state = STATE_RESET;
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reg [1:0] next_state;
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reg [5:0] good_cnt;
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reg rst_good_cnt;
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wire [NUM_LANES-1:0] phy_block_sync_masked;
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wire [NUM_LANES-1:0] emb_lock_masked;
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wire all_block_sync;
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assign phy_block_sync_masked = phy_block_sync | cfg_lanes_disable;
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assign emb_lock_masked = emb_lock | cfg_lanes_disable;
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assign all_block_sync = &phy_block_sync_masked;
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assign all_emb_lock = &emb_lock_masked;
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always @(*) begin
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next_state = state;
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rst_good_cnt = 1'b1;
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event_unexpected_lane_state_error = 1'b0;
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case (state)
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STATE_RESET:
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next_state = STATE_WAIT_BS;
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STATE_WAIT_BS:
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if (all_block_sync) begin
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rst_good_cnt = 1'b0;
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if (&good_cnt) begin
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next_state = STATE_BLOCK_SYNC;
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end
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end
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STATE_BLOCK_SYNC:
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if (~all_block_sync) begin
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next_state = STATE_WAIT_BS;
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end else if (all_emb_lock & ~buffer_release_n) begin
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rst_good_cnt = 1'b0;
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if (&good_cnt) begin
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next_state = STATE_DATA;
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end
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end
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STATE_DATA:
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if (~all_block_sync) begin
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next_state = STATE_WAIT_BS;
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event_unexpected_lane_state_error = 1'b1;
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end else if (~all_emb_lock | buffer_release_n) begin
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next_state = STATE_BLOCK_SYNC;
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event_unexpected_lane_state_error = 1'b1;
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end
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endcase
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end
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// Wait n consecutive valid cycles before jumping into next state
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always @(posedge clk) begin
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if (reset || rst_good_cnt) begin
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good_cnt <= 'h0;
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end else begin
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good_cnt <= good_cnt + 1;
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end
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end
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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state <= STATE_RESET;
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end else begin
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state <= next_state;
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end
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end
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assign status_state = state;
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endmodule
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