Archived
josh
c32d684223
修改了在线捕获程序的PN码长和频偏搜索步进,修改了地检发送程序的PN码长,使用对飞相控阵进行了测试,得到正确结果;将程序移植到814平台,同样能够正常工作;对地检程序(20230512),对飞程序(20230512)和814程序(20230415)进行归档
104 lines
3.4 KiB
Verilog
104 lines
3.4 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2023/03/21 18:35:38
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// Design Name:
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// Module Name: tx_control
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tx_control
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(
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input sys_clk , // 122.88MHz
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input sys_rst ,
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input sig_clk , // 48MHz
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input sig_rst ,
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output [15:0] tx_data_i ,
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output [15:0] tx_data_q ,
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// debug ports
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input [ 2:0] waveform_sel ,
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input sweep_on ,
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input [31:0] freq_set ,
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input [ 1:0] iq_sel ,
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input [ 3:0] bb_rshift
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);
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// pn seq
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wire [15:0] tx_pn_seq_i;
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wire [15:0] tx_pn_seq_q;
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tx_pn_seq_6mcps #(
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.DATA_WIDTH (16),
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.BIT_DATA (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001),
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.BIT_DATA_LEN (1024)
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) u_tx_pn_seq
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(
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.sys_clk (sys_clk ), // 122.88MHz
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.sys_rst (sys_rst ),
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.sig_clk (sig_clk ), // 48MHz
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.sig_rst (sig_rst ),
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.tx_data_i (tx_pn_seq_i),
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.tx_data_q (tx_pn_seq_q)
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);
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// qpsk
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wire [15:0] tx_qpsk_i;
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wire [15:0] tx_qpsk_q;
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tx_qpsk #(
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.DATA_WIDTH (16 ),
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.SQUARE_INTERP (32 ),
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.CLK_FREQ (122880000 )
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) u_tx_qpsk
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(
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.clk (sys_clk ),
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.rst (sys_rst ),
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.tx_data_i (tx_qpsk_i ),
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.tx_data_q (tx_qpsk_q ),
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// debug ports
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.waveform_sel (waveform_sel[1:0] ),
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.sweep_on (sweep_on ),
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.freq_set (freq_set ),
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.iq_sel (iq_sel ),
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.bb_rshift (bb_rshift )
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);
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// output
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reg [15:0] tx_data_buf_i = 'b0;
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reg [15:0] tx_data_buf_q = 'b0;
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assign tx_data_i = tx_data_buf_i;
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assign tx_data_q = tx_data_buf_q;
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always @(posedge sys_clk) begin
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if (sys_rst) begin
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tx_data_buf_i <= 'b0;
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tx_data_buf_q <= 'b0;
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end
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else if (waveform_sel[2]) begin
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tx_data_buf_i <= tx_pn_seq_i;
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tx_data_buf_q <= tx_pn_seq_q;
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end
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else begin
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tx_data_buf_i <= tx_qpsk_i;
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tx_data_buf_q <= tx_qpsk_q;
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end
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end
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endmodule
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