Archived
213 lines
6.0 KiB
Verilog
213 lines
6.0 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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// _ _ ____
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// | | ___ ___| |__ / ___| __ _ ___
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// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
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// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
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// \___/ \___/|___/_| |_| \____|\__,_|\___/
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//
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// Create Date: 06/11/2023 02:41:47 PM
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// Design Name:
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// Module Name: var_cal
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module var_cal
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#(
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parameter ACCUM_NUM = 16384,
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parameter DATA_I_WIDTH = 30,
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parameter DATA_O_WIDTH = 32,
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parameter CMPY_WIDTH = 18
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)
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(
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input clk ,
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input rst ,
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input cal_start ,
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input cal_auto_en ,
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output cal_busy ,
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input din_valid ,
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input [DATA_I_WIDTH-1 : 0] din_real ,
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input [DATA_I_WIDTH-1 : 0] din_imag ,
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output var_valid ,
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output [DATA_O_WIDTH-1 : 0] var
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);
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integer i;
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localparam CMPY_VALID_WIDTH = CMPY_WIDTH-1; // 17-bit valid data to protect cmpy from overflow
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localparam DATA_MULT_FULL_WIDTH = 2*CMPY_VALID_WIDTH+1;
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localparam DATA_MULT_VALID_WIDTH = 2*CMPY_VALID_WIDTH;
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localparam AXIS_DATA_I_WIDTH = 8*((CMPY_VALID_WIDTH-1)/8+1) ; // axis data width of input real/image data
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localparam AXIS_DATA_P_WIDTH = 8*((DATA_MULT_FULL_WIDTH-1)/8+1); // axis data width of cmpy output real/image data
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// status control
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reg cal_start_auto = 'b0;
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reg cal_start_d1 = 'b0;
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reg cal_start_d2 = 'b0;
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reg cal_busy_buf = 'b0;
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reg [$clog2(ACCUM_NUM)-1 : 0] cnt_accum = 'b0;
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reg last_data = 'b0;
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reg last_data_d [0:6]; // 6 for cmpy, 1 for register output
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assign cal_busy = cal_busy_buf;
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assign var_valid = last_data_d[6];
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always @(posedge clk) begin
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if (rst) begin
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cal_start_auto <= 'b0;
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end
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else begin
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if (~cal_busy_buf) begin
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cal_start_auto = ~cal_start_auto;
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end
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else begin
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cal_start_auto <= cal_start_auto;
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end
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end
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end
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always @(posedge clk) begin
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cal_start_d1 <= cal_auto_en ? cal_start_auto : cal_start;
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cal_start_d2 <= cal_start_d1;
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end
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always @(posedge clk) begin
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if (rst) begin
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cal_busy_buf <= 'b0;
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end
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else begin
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if ((cal_start_d1 ^ cal_start_d2) && din_valid) begin
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cal_busy_buf <= 1'b1;
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end
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else if (cnt_accum == ACCUM_NUM-1) begin
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cal_busy_buf <= 'b0;
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end
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else begin
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cal_busy_buf <= cal_busy_buf;
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end
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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cnt_accum <= 'b0;
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end
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else begin
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cnt_accum <= cal_busy ? (cnt_accum + 1'b1) : 'b0;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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last_data <= 'b0;
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end
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else begin
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last_data <= (cnt_accum == ACCUM_NUM-1) ? 1'b1 : 1'b0;
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end
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end
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always @(posedge clk) begin
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last_data_d[0] <= last_data;
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for (i = 0; i < 6; i = i + 1) begin
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last_data_d[i+1] <= last_data_d[i];
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end
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end
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// cmpy
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wire [AXIS_DATA_I_WIDTH-1 : 0] cmpy_i_real;
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wire [AXIS_DATA_I_WIDTH-1 : 0] cmpy_i_imag;
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wire [AXIS_DATA_P_WIDTH-1 : 0] cmpy_p_raw_real;
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wire [AXIS_DATA_P_WIDTH-1 : 0] cmpy_p_raw_imag;
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wire [DATA_O_WIDTH-1 : 0] cmpy_p_real;
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wire [DATA_O_WIDTH-1 : 0] cmpy_p_imag;
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if (CMPY_WIDTH > DATA_I_WIDTH) begin
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// append zeros
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assign cmpy_i_real = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real,{(CMPY_VALID_WIDTH-DATA_I_WIDTH){1'b0}}};
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assign cmpy_i_imag = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag,{(CMPY_VALID_WIDTH-DATA_I_WIDTH){1'b0}}};
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end
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else begin
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// truncate msb
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assign cmpy_i_real = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_VALID_WIDTH]};
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assign cmpy_i_imag = {{(AXIS_DATA_I_WIDTH-CMPY_VALID_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_VALID_WIDTH]};
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end
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if (DATA_O_WIDTH > DATA_MULT_VALID_WIDTH) begin
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// append zeros
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assign cmpy_p_real = {cmpy_p_raw_real[0 +: DATA_MULT_VALID_WIDTH],{(DATA_O_WIDTH-DATA_MULT_VALID_WIDTH){1'b0}}};
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assign cmpy_p_imag = {cmpy_p_raw_imag[0 +: DATA_MULT_VALID_WIDTH],{(DATA_O_WIDTH-DATA_MULT_VALID_WIDTH){1'b0}}};
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end
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else begin
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// truncate msb
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assign cmpy_p_real = cmpy_p_raw_real[DATA_MULT_VALID_WIDTH-1 -: DATA_O_WIDTH];
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assign cmpy_p_imag = cmpy_p_raw_imag[DATA_MULT_VALID_WIDTH-1 -: DATA_O_WIDTH];
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end
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wire [2*AXIS_DATA_I_WIDTH-1:0] cmpy_a;
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wire [2*AXIS_DATA_I_WIDTH-1:0] cmpy_b;
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wire [2*AXIS_DATA_P_WIDTH-1:0] cmpy_p;
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wire cmpy_p_vld;
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assign cmpy_a = {cmpy_i_imag,cmpy_i_real};
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assign cmpy_b = {-cmpy_i_imag,cmpy_i_real};
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assign {cmpy_p_raw_imag,cmpy_p_raw_real} = cmpy_p;
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cmpy_18x18_mult u_cmpy_18x18
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(
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.aclk (clk ), // input wire aclk
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.s_axis_a_tvalid (cal_busy ), // input wire s_axis_a_tvalid
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.s_axis_a_tdata (cmpy_a ), // input wire [31 : 0] s_axis_a_tdata
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.s_axis_b_tvalid (cal_busy ), // input wire s_axis_b_tvalid
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.s_axis_b_tdata (cmpy_b ), // input wire [31 : 0] s_axis_b_tdata
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.m_axis_dout_tvalid (cmpy_p_vld ), // output wire m_axis_dout_tvalid
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.m_axis_dout_tdata (cmpy_p ) // output wire [63 : 0] m_axis_dout_tdata
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);
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// accumulation
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reg [DATA_O_WIDTH+$clog2(ACCUM_NUM) : 0] accum = 'b0;
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reg [DATA_O_WIDTH-1 : 0] var_buf = 'b0;
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assign var = var_buf;
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always @(posedge clk) begin
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if (rst) begin
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accum <= 'b0;
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end
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else begin
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if (cmpy_p_vld) begin
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accum <= accum + cmpy_p_real;
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end
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else begin
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accum <= 'b0;
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end
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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var_buf <= 'b0;
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end
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else if (last_data_d[5]) begin
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var_buf <= accum[DATA_O_WIDTH+$clog2(ACCUM_NUM) -: DATA_O_WIDTH];
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end
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end
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endmodule
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