Archived
197 lines
7.7 KiB
Verilog
Executable File
197 lines
7.7 KiB
Verilog
Executable File
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 2023/05/16 02:00:43
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// Design Name:
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// Module Name: phase_compensate
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module phase_compensate(
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input clk ,
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input rst ,
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input [11:0] vio_sin_0 ,
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input [11:0] vio_sin_1 ,
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input [11:0] vio_sin_2 ,
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input [11:0] vio_sin_3 ,
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input [11:0] vio_cos_0 ,
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input [11:0] vio_cos_1 ,
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input [11:0] vio_cos_2 ,
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input [11:0] vio_cos_3 ,
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input [11:0] din_i_0 ,
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input [11:0] din_i_1 ,
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input [11:0] din_i_2 ,
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input [11:0] din_i_3 ,
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input [11:0] din_q_0 ,
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input [11:0] din_q_1 ,
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input [11:0] din_q_2 ,
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input [11:0] din_q_3 ,
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input [4:0] vio_trunc ,
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output [15:0] dout_i ,
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output [15:0] dout_q ,
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output trunc_overflow
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);
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wire [63:0] dout_comp_0;
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wire [63:0] dout_comp_1;
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wire [63:0] dout_comp_2;
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wire [63:0] dout_comp_3;
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cmpy_12_12 cmpy_12_12_0 (
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.aclk(clk), // input wire aclk
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.s_axis_a_tvalid(1'd1), // input wire s_axis_a_tvalid
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.s_axis_a_tdata({{4{vio_sin_0[11]}},vio_sin_0[11:0],{4{vio_cos_0[11]}},vio_cos_0[11:0]}), // input wire [31 : 0] s_axis_a_tdata
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.s_axis_b_tvalid(1'd1), // input wire s_axis_b_tvalid
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.s_axis_b_tdata({{4{din_q_0[11]}},din_q_0[11:0],{4{din_i_0[11]}},din_i_0[11:0]}), // input wire [31 : 0] s_axis_b_tdata
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.m_axis_dout_tvalid(), // output wire m_axis_dout_tvalid
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.m_axis_dout_tdata(dout_comp_0) // output wire [63 : 0] m_axis_dout_tdata
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);
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cmpy_12_12 cmpy_12_12_1 (
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.aclk(clk), // input wire aclk
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.s_axis_a_tvalid(1'd1), // input wire s_axis_a_tvalid
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.s_axis_a_tdata({{4{vio_sin_1[11]}},vio_sin_1[11:0],{4{vio_cos_1[11]}},vio_cos_1[11:0]}), // input wire [31 : 0] s_axis_a_tdata
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.s_axis_b_tvalid(1'd1), // input wire s_axis_b_tvalid
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.s_axis_b_tdata({{4{din_q_1[11]}},din_q_1[11:0],{4{din_i_1[11]}},din_i_1[11:0]}), // input wire [31 : 0] s_axis_b_tdata
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.m_axis_dout_tvalid(), // output wire m_axis_dout_tvalid
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.m_axis_dout_tdata(dout_comp_1) // output wire [63 : 0] m_axis_dout_tdata
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);
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cmpy_12_12 cmpy_12_12_2 (
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.aclk(clk), // input wire aclk
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.s_axis_a_tvalid(1'd1), // input wire s_axis_a_tvalid
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.s_axis_a_tdata({{4{vio_sin_2[11]}},vio_sin_2[11:0],{4{vio_cos_2[11]}},vio_cos_2[11:0]}), // input wire [31 : 0] s_axis_a_tdata
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.s_axis_b_tvalid(1'd1), // input wire s_axis_b_tvalid
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.s_axis_b_tdata({{4{din_q_2[11]}},din_q_2[11:0],{4{din_i_2[11]}},din_i_2[11:0]}), // input wire [31 : 0] s_axis_b_tdata
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.m_axis_dout_tvalid(), // output wire m_axis_dout_tvalid
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.m_axis_dout_tdata(dout_comp_2) // output wire [63 : 0] m_axis_dout_tdata
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);
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cmpy_12_12 cmpy_12_12_3 (
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.aclk(clk), // input wire aclk
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.s_axis_a_tvalid(1'd1), // input wire s_axis_a_tvalid
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.s_axis_a_tdata({{4{vio_sin_3[11]}},vio_sin_3[11:0],{4{vio_cos_3[11]}},vio_cos_3[11:0]}), // input wire [31 : 0] s_axis_a_tdata
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.s_axis_b_tvalid(1'd1), // input wire s_axis_b_tvalid
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.s_axis_b_tdata({{4{din_q_3[11]}},din_q_3[11:0],{4{din_i_3[11]}},din_i_3[11:0]}), // input wire [31 : 0] s_axis_b_tdata
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.m_axis_dout_tvalid(), // output wire m_axis_dout_tvalid
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.m_axis_dout_tdata(dout_comp_3) // output wire [63 : 0] m_axis_dout_tdata
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);
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wire [11:0] dout_trunc_0i, dout_trunc_0q;
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wire [11:0] dout_trunc_1i, dout_trunc_1q;
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wire [11:0] dout_trunc_2i, dout_trunc_2q;
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wire [11:0] dout_trunc_3i, dout_trunc_3q;
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wire [11:0] trunc_overflow_0i, trunc_overflow_0q;
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wire [11:0] trunc_overflow_1i, trunc_overflow_1q;
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wire [11:0] trunc_overflow_2i, trunc_overflow_2q;
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wire [11:0] trunc_overflow_3i, trunc_overflow_3q;
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trunc_32bit_to_12bit trunc_32bit_to_12bit_0i(
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.clk(clk),
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.rst(rst),
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.trunc_32bit_in({{7{dout_comp_0[24]}},dout_comp_0[24:0]}),
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.vio_trunc(vio_trunc),
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.trunc_12bit_out(dout_trunc_0i),
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.trunc_overflow(trunc_overflow_0i)
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);
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trunc_32bit_to_12bit trunc_32bit_to_12bit_0q(
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.clk(clk),
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.rst(rst),
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.trunc_32bit_in({{7{dout_comp_0[56]}},dout_comp_0[56:32]}),
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.vio_trunc(vio_trunc),
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.trunc_12bit_out(dout_trunc_0q),
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.trunc_overflow(trunc_overflow_0q)
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);
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trunc_32bit_to_12bit trunc_32bit_to_12bit_1i(
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.clk(clk),
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.rst(rst),
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.trunc_32bit_in({{7{dout_comp_1[24]}},dout_comp_1[24:0]}),
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.vio_trunc(vio_trunc),
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.trunc_12bit_out(dout_trunc_1i),
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.trunc_overflow(trunc_overflow_1i)
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);
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trunc_32bit_to_12bit trunc_32bit_to_12bit_1q(
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.clk(clk),
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.rst(rst),
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.trunc_32bit_in({{7{dout_comp_1[56]}},dout_comp_1[56:32]}),
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.vio_trunc(vio_trunc),
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.trunc_12bit_out(dout_trunc_1q),
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.trunc_overflow(trunc_overflow_1q)
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);
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trunc_32bit_to_12bit trunc_32bit_to_12bit_2i(
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.clk(clk),
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.rst(rst),
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.trunc_32bit_in({{7{dout_comp_2[24]}},dout_comp_2[24:0]}),
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.vio_trunc(vio_trunc),
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.trunc_12bit_out(dout_trunc_2i),
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.trunc_overflow(trunc_overflow_2i)
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);
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trunc_32bit_to_12bit trunc_32bit_to_12bit_2q(
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.clk(clk),
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.rst(rst),
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.trunc_32bit_in({{7{dout_comp_2[56]}},dout_comp_2[56:32]}),
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.vio_trunc(vio_trunc),
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.trunc_12bit_out(dout_trunc_2q),
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.trunc_overflow(trunc_overflow_2q)
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);
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trunc_32bit_to_12bit trunc_32bit_to_12bit_3i(
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.clk(clk),
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.rst(rst),
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.trunc_32bit_in({{7{dout_comp_3[24]}},dout_comp_3[24:0]}),
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.vio_trunc(vio_trunc),
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.trunc_12bit_out(dout_trunc_3i),
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.trunc_overflow(trunc_overflow_3i)
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);
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trunc_32bit_to_12bit trunc_32bit_to_12bit_3q(
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.clk(clk),
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.rst(rst),
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.trunc_32bit_in({{7{dout_comp_3[56]}},dout_comp_3[56:32]}),
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.vio_trunc(vio_trunc),
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.trunc_12bit_out(dout_trunc_3q),
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.trunc_overflow(trunc_overflow_3q)
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);
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reg [15:0] data_i_combine = 16'd0;
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reg [15:0] data_q_combine = 16'd0;
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always @ (posedge clk) begin
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if(rst) begin
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data_i_combine[15:0] <= 16'd0;
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data_q_combine[15:0] <= 16'd0;
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end
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else begin
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data_i_combine[15:0] <= {{4{dout_trunc_0i[11]}},dout_trunc_0i[11:0]} + {{4{dout_trunc_1i[11]}},dout_trunc_1i[11:0]} + {{4{dout_trunc_2i[11]}},dout_trunc_2i[11:0]} + {{4{dout_trunc_3i[11]}},dout_trunc_3i[11:0]};
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data_q_combine[15:0] <= {{4{dout_trunc_0q[11]}},dout_trunc_0q[11:0]} + {{4{dout_trunc_1q[11]}},dout_trunc_1q[11:0]} + {{4{dout_trunc_2q[11]}},dout_trunc_2q[11:0]} + {{4{dout_trunc_3q[11]}},dout_trunc_3q[11:0]};
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end
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end
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assign dout_i[15:0] = data_i_combine[15:0];
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assign dout_q[15:0] = data_q_combine[15:0];
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assign trunc_overflow = trunc_overflow_3q || trunc_overflow_2q || trunc_overflow_1q || trunc_overflow_0q || trunc_overflow_3i || trunc_overflow_2i || trunc_overflow_1i || trunc_overflow_0i;
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endmodule
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