Archived
1088 lines
55 KiB
Verilog
1088 lines
55 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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// _ _ ____
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// | | ___ ___| |__ / ___| __ _ ___
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// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
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// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
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// \___/ \___/|___/_| |_| \____|\__,_|\___/
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//
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// Create Date: 2021/12/14 15:54:11
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// Design Name:
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// Module Name: system_top
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module system_top
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(
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/***************************************************************************
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* Contents
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* 01. Clocks
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* 02. HMC7044 Interface
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* 03. AD9361-1 Interface
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* 04. AD9361-2 Interface
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* 05. Phased-Array Control
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* 06. RF Synthesizer Control
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* 07. Debug IO
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* 08. DDR and Fixed-io (Do NOT Modify)
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**************************************************************************/
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// *************************************************************************
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// ******************************** Clocks *********************************
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// *************************************************************************
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// fpga logic clock
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input clk_250m_p , // generated by hmc7044, 250mhz
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input clk_250m_n ,
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// ad9361 buffered clock
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input ad9361_1_buffer_clk , // derived from ad9361 input clock
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input ad9361_2_buffer_clk , // derived from ad9361 input clock
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// *************************************************************************
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// *************************** HMC7044 Interface ***************************
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// *************************************************************************
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// spi interface
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output hmc7044_spi_clk ,
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output hmc7044_spi_csn ,
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inout hmc7044_spi_sdio ,
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// control signals
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output hmc7044_reset , // hmc7044 active-high reset signal, set to 0 in normal operation
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output hmc7044_sync , // hmc7044 multichip synchronization signal, set to 0 if not used
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// gpio
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inout [ 3:0] hmc7044_gpio ,
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// *************************************************************************
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// ************************** AD9361-1 Interface ***************************
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// *************************************************************************
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// rx data (rx channels are tied to ground physically)
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input ad9361_1_rx_data_clk, // ad9361 rx data clock, 96mhz
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input ad9361_1_rx_frame ,
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input [11:0] ad9361_1_rx_data ,
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// tx data
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output ad9361_1_tx_fb_clk ,
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output ad9361_1_tx_frame ,
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output [11:0] ad9361_1_tx_data ,
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// spi interface
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output ad9361_1_spi_clk ,
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output ad9361_1_spi_csn ,
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output ad9361_1_spi_mosi ,
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input ad9361_1_spi_miso ,
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// control signals
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output ad9361_1_reset_b , // ad9361 active-low reset control
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output ad9361_1_en_agc , // ad9361 manual agc control
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output ad9361_1_enable , // ad9361 enable state machine pin control (spi control is also allowed)
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output ad9361_1_txnrx , // ad9361 enable state machine pin control (spi control is also allowed)
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input [ 3:0] ad9361_1_ctrl_in ,
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output [ 7:0] ad9361_1_ctrl_out ,
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output ad9361_sync ,
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// *************************************************************************
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// ************************** AD9361-2 Interface ***************************
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// *************************************************************************
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// rx data (rx channels are tied to ground physically)
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input ad9361_2_rx_data_clk,
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input ad9361_2_rx_frame ,
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input [11:0] ad9361_2_rx_data ,
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// tx data
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output ad9361_2_tx_fb_clk ,
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output ad9361_2_tx_frame ,
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output [11:0] ad9361_2_tx_data ,
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// spi interface
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output ad9361_2_spi_clk ,
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output ad9361_2_spi_csn ,
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output ad9361_2_spi_mosi ,
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input ad9361_2_spi_miso ,
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// control signals
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output ad9361_2_reset_b , // ad9361 active-low reset control
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output ad9361_2_en_agc , // ad9361 manual agc control
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output ad9361_2_enable , // ad9361 enable state machine pin control (spi control is also allowed)
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output ad9361_2_txnrx , // ad9361 enable state machine pin control (spi control is also allowed)
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input [ 3:0] ad9361_2_ctrl_in ,
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output [ 7:0] ad9361_2_ctrl_out ,
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// *************************************************************************
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// ************************* Phased-Array Control **************************
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// *************************************************************************
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output ant_clk ,
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output ant_en ,
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output ant_data ,
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output ant_tr ,
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output ant_dary ,
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input ant_dout ,
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// *************************************************************************
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// ************************ RF Synthesizer Control *************************
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// *************************************************************************
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output rf_standby ,
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output rf_sw_pll ,
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output rf_t ,
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output rf_r ,
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output rf_sw_bpf ,
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output rf_sclk1 ,
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output rf_sdio1 ,
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output rf_cs1 ,
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input rf_ld1 ,
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output rf_sclk2 ,
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output rf_sdio2 ,
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output rf_cs2 ,
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input rf_ld2 ,
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output rf_sclk3 ,
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output rf_sdio3 ,
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output rf_cs3 ,
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input rf_ld3 ,
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output rf_tmgc_16 ,
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output rf_tmgc_8 ,
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output rf_tmgc_4 ,
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output rf_tmgc_2 ,
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output rf_tmgc_1 ,
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output rf_rmgc_16 ,
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output rf_rmgc_8 ,
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output rf_rmgc_4 ,
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output rf_rmgc_2 ,
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output rf_rmgc_1 ,
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output rf_enable ,
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output rf_sc ,
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output rf_sd ,
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output rf_endsyn ,
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input rf_sdout ,
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inout rf_dq_wd ,
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output rf_sw_rx ,
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// *************************************************************************
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// ******************************* Debug IO ********************************
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// *************************************************************************
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// 3.3v ports
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output uart1_txd ,
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input uart1_rxd ,
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output uart2_txd ,
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input uart2_rxd ,
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output uart3_txd ,
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input uart3_rxd ,
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// 1.8v ports
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inout debug_io_1 ,
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inout debug_io_2 ,
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// 3.3v ports
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input debug_io_3 ,
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inout debug_io_4 ,
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inout debug_io_5 ,
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inout debug_io_6 ,
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inout debug_io_7 ,
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// *************************************************************************
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// ******************* DDR and Fixed-io (Do NOT Modify) ********************
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// *************************************************************************
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// ddr
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inout [14:0] ddr_addr ,
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inout [ 2:0] ddr_ba ,
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inout ddr_cas_n ,
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inout ddr_ck_n ,
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inout ddr_ck_p ,
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inout ddr_cke ,
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inout ddr_cs_n ,
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inout [ 3:0] ddr_dm ,
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inout [31:0] ddr_dq ,
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inout [ 3:0] ddr_dqs_n ,
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inout [ 3:0] ddr_dqs_p ,
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inout ddr_odt ,
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inout ddr_ras_n ,
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inout ddr_reset_n ,
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inout ddr_we_n ,
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// fixed-io
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inout fixed_io_ddr_vrn ,
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inout fixed_io_ddr_vrp ,
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inout [53:0] fixed_io_mio ,
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inout fixed_io_ps_clk ,
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inout fixed_io_ps_porb ,
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inout fixed_io_ps_srstb
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);
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////////////////////////////////////////////////////////////////////////////////
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/////////////////////////// System Clock Generation ////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// global reset
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wire sys_rst ; // global reset signal, active high
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wire ant_rst ; // phased-array & rf control reset signal, active high
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// pl signal processing clock
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wire sys_clk ; // 48MHz 41.6667MHz
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wire sys_clk_2x ; // 96MHz 83.3333MHz
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wire sys_clk_3x ; // 144MHz 125MHz
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wire sys_clk_4x ; // 192MHz 166.6667MHz
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wire sys_clk_ld ; // system main clock locked indicator
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// ad9361-1 clocks
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wire ad9361_1_clk ; // 48MHz 41.6667MHz
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wire ad9361_1_clk_2x ; // 96MHz 83.3333MHz
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wire ad9361_1_clk_3x ; // 144MHz 125MHz
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wire ad9361_1_clk_4x ; // 192MHz 166.6667MHz
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wire ad9361_1_clk_ld ; // ad9361-1 clock group locked indicator
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// ad9361-2 clocks
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wire ad9361_2_clk ; // 48MHz 41.6667MHz
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wire ad9361_2_clk_2x ; // 96MHz 83.3333MHz
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wire ad9361_2_clk_3x ; // 144MHz 125MHz
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wire ad9361_2_clk_4x ; // 192MHz 166.6667MHz
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wire ad9361_2_clk_ld ; // ad9361-2 clock group locked indicator
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// phased-array & rf control clocks
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wire clk_96m ;
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wire clk_48m ;
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wire clk_32m ;
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wire clk_19p2m ;
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clk_dist u_clk_dist
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(
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// input clocks
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.clk_250m_p (clk_250m_p ), // generated by ad9516, 250mhz
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.clk_250m_n (clk_250m_n ),
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.ad9361_1_rx_data_clk(ad9361_1_rx_data_clk), // ad9361 rx data clock, 83.3333mhz
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.ad9361_2_rx_data_clk(ad9361_2_rx_data_clk), // ad9361 rx data clock, 83.3333mhz
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// output clocks & reset
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// global reset
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.sys_rst (sys_rst ), // global reset signal, active high
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.ant_rst (ant_rst ), // phased-array & rf control reset signal, active high
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// pl signal processing clock
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.sys_clk (sys_clk ), // 48MHz 41.6667MHz
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.sys_clk_2x (sys_clk_2x ), // 96MHz 83.3333MHz
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.sys_clk_3x (sys_clk_3x ), // 144MHz 125MHz
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.sys_clk_4x (sys_clk_4x ), // 192MHz 166.6667MHz
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.sys_clk_ld (sys_clk_ld ), // system main clock locked indicator
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// ad9361-1 clocks
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.ad9361_1_clk (ad9361_1_clk ), // 48MHz 41.6667MHz
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.ad9361_1_clk_2x (ad9361_1_clk_2x ), // 96MHz 83.3333MHz
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.ad9361_1_clk_3x (ad9361_1_clk_3x ), // 144MHz 125MHz
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.ad9361_1_clk_4x (ad9361_1_clk_4x ), // 192MHz 166.6667MHz
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.ad9361_1_clk_ld (ad9361_1_clk_ld ), // ad9361-1 clock group locked indicator
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// ad9361-2 clocks
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.ad9361_2_clk (ad9361_2_clk ), // 48MHz 41.6667MHz
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.ad9361_2_clk_2x (ad9361_2_clk_2x ), // 96MHz 83.3333MHz
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.ad9361_2_clk_3x (ad9361_2_clk_3x ), // 144MHz 125MHz
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.ad9361_2_clk_4x (ad9361_2_clk_4x ), // 192MHz 166.6667MHz
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.ad9361_2_clk_ld (ad9361_2_clk_ld ), // ad9361-2 clock group locked indicator
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// phased-array & rf control clocks
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.clk_96m (clk_96m ),
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.clk_48m (clk_48m ),
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.clk_32m (clk_32m ),
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.clk_19p2m (clk_19p2m )
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);
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////////////////////////////////////////////////////////////////////////////////
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//////////////////////////// Block Design Interface ////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// gpio
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wire [47:0] gpio_i;
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wire [47:0] gpio_o;
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wire [47:0] gpio_t;
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wire ad9361_rx_fifo_rst;
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wire ad9361_1_cal_start;
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wire ad9361_1_cal_done;
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wire ad9361_2_cal_start;
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wire ad9361_2_cal_done;
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wire ad9361_cal_result;
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wire ad9361_recal;
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assign gpio_i[47:47] = gpio_o[47:47];
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// hmc7044
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assign hmc7044_reset = gpio_o[ 0]; // hmc7044 reset
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assign hmc7044_sync = gpio_o[ 1]; // hmc7044 multichip synchronization
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assign hmc7044_gpio[0] = gpio_t[ 2] ? gpio_i[ 2] : gpio_o[ 2];
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assign hmc7044_gpio[1] = gpio_t[ 3] ? gpio_i[ 3] : gpio_o[ 3];
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assign hmc7044_gpio[2] = gpio_t[ 4] ? gpio_i[ 4] : gpio_o[ 4];
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assign hmc7044_gpio[3] = gpio_t[ 5] ? gpio_i[ 5] : gpio_o[ 5];
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// ad9361-1
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assign ad9361_1_txnrx = gpio_o[ 6]; // ad9361 enable state machine control
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assign ad9361_1_enable = gpio_o[ 7]; // ad9361 enable state machine control
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assign ad9361_1_en_agc = gpio_o[ 8]; // ad9361 agc control
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assign ad9361_1_reset_b = gpio_o[ 9]; // ad9361 reset
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assign ad9361_1_ctrl_out = gpio_o[17:10];
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assign gpio_i[21:18] = ad9361_1_ctrl_in;
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// ad9361-2
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assign ad9361_2_txnrx = gpio_o[22]; // ad9361 enable state machine control
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assign ad9361_2_enable = gpio_o[23]; // ad9361 enable state machine control
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assign ad9361_2_en_agc = gpio_o[24]; // ad9361 agc control
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assign ad9361_2_reset_b = gpio_o[25]; // ad9361 reset
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assign ad9361_2_ctrl_out = gpio_o[33:26];
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assign gpio_i[37:34] = ad9361_2_ctrl_in;
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// ad9361 multichip sync
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assign ad9361_sync = gpio_o[38];
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assign ad9361_rx_fifo_rst = gpio_o[39];
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assign ad9361_1_cal_start = gpio_o[40];
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assign ad9361_2_cal_start = gpio_o[41];
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assign ad9361_recal = gpio_o[42];
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assign ad9361_tx_switch = gpio_o[43];
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assign gpio_i[44] = ad9361_1_cal_done;
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assign gpio_i[45] = ad9361_2_cal_done;
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assign gpio_i[46] = ad9361_cal_result;
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// spi interface
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wire spi_sclk ;
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wire [ 2:0] spi_cs ;
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reg spi_sdi ;
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wire spi_sdo ;
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wire spi_sdo_t ;
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wire spi_three_wire;
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wire spi_active ;
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// hmc7044 - three-wire spi
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assign hmc7044_spi_clk = spi_sclk;
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assign hmc7044_spi_csn = spi_cs[0];
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assign hmc7044_spi_sdio = spi_sdo_t ? 1'bz : spi_sdo;
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// ad9361-1 - three-wire spi or four-wire spi
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assign ad9361_1_spi_clk = spi_sclk;
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assign ad9361_1_spi_csn = spi_cs[1];
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assign ad9361_1_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
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// ad9361-2 - three-wire spi or four-wire spi
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assign ad9361_2_spi_clk = spi_sclk;
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assign ad9361_2_spi_csn = spi_cs[2];
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assign ad9361_2_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
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// select sdi signal
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always @(*) begin
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if (~hmc7044_spi_csn)
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spi_sdi = hmc7044_spi_sdio;
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else if (~ad9361_1_spi_csn)
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spi_sdi = spi_three_wire ? ad9361_1_spi_mosi : ad9361_1_spi_miso;
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else if (~ad9361_2_spi_csn)
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spi_sdi = spi_three_wire ? ad9361_2_spi_mosi : ad9361_2_spi_miso;
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else
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spi_sdi = 1'bz;
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end
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// ps clock
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wire ps_clk_50M;
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wire ps_clk_200M;
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system_bd_wrapper u_system_bd_wrapper
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(
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// ddr
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.ddr_addr (ddr_addr ), // inout [14:0]ddr_addr
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.ddr_ba (ddr_ba ), // inout [2:0]ddr_ba
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.ddr_cas_n (ddr_cas_n ), // inout ddr_cas_n
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.ddr_ck_n (ddr_ck_n ), // inout ddr_ck_n
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.ddr_ck_p (ddr_ck_p ), // inout ddr_ck_p
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.ddr_cke (ddr_cke ), // inout ddr_cke
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.ddr_cs_n (ddr_cs_n ), // inout ddr_cs_n
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.ddr_dm (ddr_dm ), // inout [3:0]ddr_dm
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.ddr_dq (ddr_dq ), // inout [31:0]ddr_dq
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.ddr_dqs_n (ddr_dqs_n ), // inout [3:0]ddr_dqs_n
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.ddr_dqs_p (ddr_dqs_p ), // inout [3:0]ddr_dqs_p
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.ddr_odt (ddr_odt ), // inout ddr_odt
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.ddr_ras_n (ddr_ras_n ), // inout ddr_ras_n
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.ddr_reset_n (ddr_reset_n ), // inout ddr_reset_n
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.ddr_we_n (ddr_we_n ), // inout ddr_we_n
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// fixed-io
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn ), // inout fixed_io_ddr_vrn
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp ), // inout fixed_io_ddr_vrp
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.fixed_io_mio (fixed_io_mio ), // inout [53:0]fixed_io_mio
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.fixed_io_ps_clk (fixed_io_ps_clk ), // inout fixed_io_ps_clk
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.fixed_io_ps_porb (fixed_io_ps_porb ), // inout fixed_io_ps_porb
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.fixed_io_ps_srstb (fixed_io_ps_srstb ), // inout fixed_io_ps_srstb
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// gpio, for control signals
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.gpio_i (gpio_i ), // input [47:0]gpio_i
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.gpio_o (gpio_o ), // output [47:0]gpio_o
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.gpio_t (gpio_t ), // output [47:0]gpio_t
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// spi interface
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.spi_sclk (spi_sclk ), // output spi_sclk
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.spi_cs (spi_cs ), // output [2:0]spi_cs
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.spi_sdi (spi_sdi ), // input [0:0]spi_sdi
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.spi_sdo (spi_sdo ), // output spi_sdo
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.spi_sdo_t (spi_sdo_t ), // output spi_sdo_t
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.spi_three_wire (spi_three_wire ), // output spi_three_wire
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.spi_active (spi_active ), // output spi_active
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// ps clock
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.ps_clk_50M (ps_clk_50M ), // output ps_clk_50M
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.ps_clk_200M (ps_clk_200M ) // output ps_clk_200M
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);
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////// RF control //////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// rf auto switch frequency function
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wire rf_auto_start_vio ;
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wire rf_ctrl_mode_vio ;
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wire switch_next_freq_vio;
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wire switch_last_freq_vio;
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wire [31:0] cnt_valid_to_switch_vio;
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wire [31:0] cnt_switch_to_freq_start_vio;
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wire [31:0] cnt_sync_in_vio;
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wire [31:0] cnt_sync_in_high_vio;
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(*dont_touch = "true"*) wire vio_switch;
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(*dont_touch = "true"*) wire vio_switch_auto;
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(*dont_touch = "true"*) wire [15:0] vio_frequency;
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(*dont_touch = "true"*) wire [15:0] vio_frequency_auto;
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wire hop_words_valid_auto;
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wire freq_comp_start_auto ;
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rf_auto_switch_freq u_rf_auto_switch_freq(
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.clk (clk_48m ),
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.rst (sys_rst ),
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// vio control
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.start (rf_auto_start_vio ), // rise-edge active, if start, change freq word to the first
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.rf_ctrl_mode (rf_ctrl_mode_vio ), // 1 : auto switch, 0 : manual switch
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.switch_next_freq (switch_next_freq_vio ), // rise-edge active
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.switch_last_freq (switch_last_freq_vio ), // rise-edge active
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.cnt_valid_to_switch (cnt_valid_to_switch_vio ),
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.cnt_switch_to_freq_start (cnt_switch_to_freq_start_vio ),
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.cnt_sync_in (cnt_sync_in_vio[31:0] ),
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.cnt_sync_in_high (cnt_sync_in_high_vio[31:0] ),
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// input
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.sync_in (debug_io_3 ),
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.freq_hop_words_vio (vio_frequency[15:0] ),
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.hop_words_valid_vio (1'b0 ),
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.freq_hop_switch_vio (vio_switch ),
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// output
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.freq_hop_words_auto (vio_frequency_auto[15:0] ),
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.hop_words_valid_auto (hop_words_valid_auto ),
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.freq_hop_switch_auto (vio_switch_auto ),
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.freq_comp_start (freq_comp_start_auto )
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);
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ant_rf_ctrl u_ant_rf_ctrl
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(
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.clk_48m (clk_48m ), // input clk_48m
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.clk_96m (clk_96m ), // input clk_96m
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.clk_32m (clk_32m ), // input clk_32m
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.clk_19p2m (clk_19p2m ), // input clk_19p2m
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.sys_rst (ant_rst ), // input sys_rst
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.ant_clk (ant_clk ), // output ant_clk
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.ant_en (ant_en ), // output ant_en
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.ant_data (ant_data ), // output ant_data
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.ant_tr (ant_tr ), // output ant_tr
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.ant_dary (ant_dary ), // output ant_dary
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.ant_dout (ant_dout ), // input ant_dout
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.rf_standby (rf_standby ), // output rf_standby
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.rf_sw_pll (rf_sw_pll ), // output rf_sw_pll
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.rf_t (rf_t ), // output rf_t
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.rf_r (rf_r ), // output rf_r
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.rf_sw_bpf (rf_sw_bpf ), // output rf_sw_bpf
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.rf_sclk1 (rf_sclk1 ), // output rf_sclk1
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.rf_sdio1 (rf_sdio1 ), // output rf_sdio1
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.rf_cs1 (rf_cs1 ), // output rf_cs1
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.rf_ld1 (rf_ld1 ), // input rf_ld1
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.rf_sclk2 (rf_sclk2 ), // output rf_sclk2
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.rf_sdio2 (rf_sdio2 ), // output rf_sdio2
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.rf_cs2 (rf_cs2 ), // output rf_cs2
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.rf_ld2 (rf_ld2 ), // input rf_ld2
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.rf_sclk3 (rf_sclk3 ), // output rf_sclk3
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.rf_sdio3 (rf_sdio3 ), // output rf_sdio3
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.rf_cs3 (rf_cs3 ), // output rf_cs3
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.rf_ld3 (rf_ld3 ), // input rf_ld3
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.rf_tmgc_16 (rf_tmgc_16 ), // output rf_tmgc_16
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.rf_tmgc_8 (rf_tmgc_8 ), // output rf_tmgc_8
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.rf_tmgc_4 (rf_tmgc_4 ), // output rf_tmgc_4
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.rf_tmgc_2 (rf_tmgc_2 ), // output rf_tmgc_2
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.rf_tmgc_1 (rf_tmgc_1 ), // output rf_tmgc_1
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.rf_rmgc_16 (rf_rmgc_16 ), // output rf_rmgc_16
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.rf_rmgc_8 (rf_rmgc_8 ), // output rf_rmgc_8
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.rf_rmgc_4 (rf_rmgc_4 ), // output rf_rmgc_4
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.rf_rmgc_2 (rf_rmgc_2 ), // output rf_rmgc_2
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.rf_rmgc_1 (rf_rmgc_1 ), // output rf_rmgc_1
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.rf_enable (rf_enable ), // output rf_enable
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.rf_sc (rf_sc ), // output rf_sc
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.rf_sd (rf_sd ), // output rf_sd
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.rf_endsyn (rf_endsyn ), // output rf_endsyn
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.rf_sdout (rf_sdout ), // input rf_sdout
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.rf_dq_wd (rf_dq_wd ), // inout rf_dq_wd
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.rf_sw_rx (rf_sw_rx ) // output rf_sw_rx
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);
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assign u_ant_rf_ctrl.vio_switch = vio_switch_auto ;
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assign u_ant_rf_ctrl.vio_frequency = vio_frequency_auto;
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////// Tx Signal ///////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// baseband signal
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wire [11:0] tx_data_i;
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wire [11:0] tx_data_q;
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wire [11:0] tx_ch1_i;
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wire [11:0] tx_ch1_q;
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wire [11:0] tx_ch2_i;
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wire [11:0] tx_ch2_q;
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ad9361_tx_map_cmos_dual u_ad9361_tx_map
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(
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.clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in
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.clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst
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.tx_data_clk (sys_clk ), // input tx_data_clk
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.tx_data_clk_rst(sys_rst ), // input tx_data_clk_rst
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.tx_ch1_i (tx_ch1_i ), // input [11:0] tx_ch1_i
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.tx_ch1_q (tx_ch1_q ), // input [11:0] tx_ch1_q
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.tx_ch2_i (tx_ch2_i ), // input [11:0] tx_ch2_i
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.tx_ch2_q (tx_ch2_q ), // input [11:0] tx_ch2_q
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.clk_out (ad9361_1_tx_fb_clk ), // output clk_out
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.tx_frame (ad9361_1_tx_frame ), // output tx_frame
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.tx_data (ad9361_1_tx_data ) // output [11:0] tx_data
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);
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assign ad9361_2_tx_fb_clk = ad9361_1_tx_fb_clk;
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// assign ad9361_2_tx_frame = ad9361_1_tx_frame ;
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// assign ad9361_2_tx_data = ad9361_1_tx_data ;
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tx_pre_process #(
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.CAL_MOD_FINE (0)
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) u_tx_pre_process
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(
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// clock & reset
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.clk (sys_clk ),
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.rst (sys_rst ),
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// input data
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.tx_data_ch1_i (tx_data_i ),
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.tx_data_ch1_q (tx_data_q ),
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.tx_data_ch2_i (tx_data_i ),
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.tx_data_ch2_q (tx_data_q ),
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// ad9361 calibration interface
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.ad9361_tx_switch (ad9361_tx_switch ),
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//
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.bb_rshift (1'b0 ),
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// output data
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.tx_ch1_i (tx_ch1_i ),
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.tx_ch1_q (tx_ch1_q ),
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.tx_ch2_i (tx_ch2_i ),
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.tx_ch2_q (tx_ch2_q )
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);
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// <--------------------------------------------------------------------------->
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// <--------------------- insert transmitter logic below ---------------------->
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// <--------------------------------------------------------------------------->
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wire [ 1:0] waveform_sel;
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wire sweep_on ;
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wire [31:0] freq_set ;
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wire [ 1:0] iq_sel ;
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wire [ 3:0] bb_rshift ;
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tx_qpsk #(
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.BIT_DATA (1024'b0000000100100010000011001001101000010010101000011110101110101101101100000000110000011011001100001010110101110001101111110001000111100111101101101000000010100001011010101000111110111100100101100000100110010001010001101101110000001111000111011111110010000110001011011101000011010101100111100101101100100000100010010011000000101100010100111011001110001011111101010001011101101011000011001101101010000011101001111010011010100100111000001111100111001101111010001010101101111100001001110100011101011111011010010000100001010010101100011100111111101100001000110100111001001111000011011101100011000111101111101001001010000001101000110010111010010110100010001011001101001010010001100001110110111100000101110010101110011101110111001100111010101110111101100101000100110110001000011100101111100101001100110010101010011111100110001101011110011010110100110001001011100001011110101010101111111101000001010100101111000101011110111010100110111001000111000111111111100000001110000111111011100010011111000110011111010110010110010010010000000001),
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.BIT_DATA_LEN (1024),
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.CLK_FREQ (48000000)
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) u_tx_qpsk
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(
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.clk (sys_clk ), // input clk
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.rst (sys_rst ), // input rst
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.tx_data_i (tx_data_i ), // output [11:0] tx_data_i
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.tx_data_q (tx_data_q ), // output [11:0] tx_data_q
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// debug ports
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.waveform_sel (waveform_sel[1:0] ), // input [ 1:0] waveform_sel
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.sweep_on (sweep_on ), // input sweep_on
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.freq_set (freq_set ), // input [31:0] freq_set
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.iq_sel (iq_sel ), // input [ 1:0] iq_sel
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.bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift
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);
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////// Rx Signals //////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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wire [11:0] rx_ch1_i, rx_ch1_q;
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wire [11:0] rx_ch2_i, rx_ch2_q;
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wire [11:0] rx_ch3_i, rx_ch3_q;
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wire [11:0] rx_ch4_i, rx_ch4_q;
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wire [11:0] rx_cal_ch1_i, rx_cal_ch1_q;
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wire [11:0] rx_cal_ch2_i, rx_cal_ch2_q;
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wire [11:0] rx_cal_ch3_i, rx_cal_ch3_q;
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wire [11:0] rx_cal_ch4_i, rx_cal_ch4_q;
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ad9361_rx_map_cmos_dual u_ad9361_1_rx_map
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(
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.clk_2x_in (ad9361_1_clk_2x ), // input clk_2x_in
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.clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst
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.rx_data_clk (sys_clk ), // input rx_data_clk
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.rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst
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.rx_fifo_rst (ad9361_rx_fifo_rst ), // input rx_fifo_rst
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.rx_frame (ad9361_1_rx_frame ), // input rx_frame
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.rx_data (ad9361_1_rx_data ), // input [11:0] rx_data
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.rx_ch1_i (rx_ch1_i ), // output [11:0] rx_ch1_i
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.rx_ch1_q (rx_ch1_q ), // output [11:0] rx_ch1_q
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.rx_ch2_i (rx_ch2_i ), // output [11:0] rx_ch2_i
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.rx_ch2_q (rx_ch2_q ) // output [11:0] rx_ch2_q
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);
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ad9361_rx_map_cmos_dual u_ad9361_2_rx_map
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(
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.clk_2x_in (ad9361_2_clk_2x ), // input clk_2x_in
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.clk_in_rst (~ad9361_2_clk_ld ), // input clk_in_rst
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.rx_data_clk (sys_clk ), // input rx_data_clk
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.rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst
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.rx_fifo_rst (ad9361_rx_fifo_rst ), // input rx_fifo_rst
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.rx_frame (ad9361_2_rx_frame ), // input rx_frame
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.rx_data (ad9361_2_rx_data ), // input [11:0] rx_data
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.rx_ch1_i (rx_ch3_i ), // output [11:0] rx_ch1_i
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.rx_ch1_q (rx_ch3_q ), // output [11:0] rx_ch1_q
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.rx_ch2_i (rx_ch4_i ), // output [11:0] rx_ch2_i
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.rx_ch2_q (rx_ch4_q ) // output [11:0] rx_ch2_q
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);
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ad9361_phase_cal_coarse u_ad9361_phase_cal
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(
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// clock & reset
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.clk (sys_clk ), // input clk
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.rst (sys_rst ), // input rst
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// control interface
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.ad9361_1_cal_start (ad9361_1_cal_start ), // input ad9361_1_cal_start
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.ad9361_1_cal_done (ad9361_1_cal_done ), // output ad9361_1_cal_done
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.ad9361_2_cal_start (ad9361_2_cal_start ), // input ad9361_2_cal_start
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.ad9361_2_cal_done (ad9361_2_cal_done ), // output ad9361_2_cal_done
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.ad9361_cal_result (ad9361_cal_result ), // output ad9361_cal_result
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.ad9361_cal_valid (ad9361_cal_valid ), // output ad9361_cal_valid
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.ad9361_recal (ad9361_recal ), // input ad9361_recal
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// input data interface
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.rx_ch1_i (rx_ch1_i ), // input [ADC_DATA_WIDTH-1:0] rx_ch1_i
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.rx_ch1_q (rx_ch1_q ), // input [ADC_DATA_WIDTH-1:0] rx_ch1_q
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.rx_ch2_i (rx_ch2_i ), // input [ADC_DATA_WIDTH-1:0] rx_ch2_i
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.rx_ch2_q (rx_ch2_q ), // input [ADC_DATA_WIDTH-1:0] rx_ch2_q
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.rx_ch3_i (rx_ch3_i ), // input [ADC_DATA_WIDTH-1:0] rx_ch3_i
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.rx_ch3_q (rx_ch3_q ), // input [ADC_DATA_WIDTH-1:0] rx_ch3_q
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.rx_ch4_i (rx_ch4_i ), // input [ADC_DATA_WIDTH-1:0] rx_ch4_i
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.rx_ch4_q (rx_ch4_q ), // input [ADC_DATA_WIDTH-1:0] rx_ch4_q
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// output data interface
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.rx_cal_ch1_i (rx_cal_ch1_i ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch1_i
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.rx_cal_ch1_q (rx_cal_ch1_q ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch1_q
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.rx_cal_ch2_i (rx_cal_ch2_i ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch2_i
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.rx_cal_ch2_q (rx_cal_ch2_q ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch2_q
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.rx_cal_ch3_i (rx_cal_ch3_i ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch3_i
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.rx_cal_ch3_q (rx_cal_ch3_q ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch3_q
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.rx_cal_ch4_i (rx_cal_ch4_i ), // output [ADC_DATA_WIDTH-1:0] rx_cal_ch4_i
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.rx_cal_ch4_q (rx_cal_ch4_q ) // output [ADC_DATA_WIDTH-1:0] rx_cal_ch4_q
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);
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// <--------------------------------------------------------------------------->
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// <----------------------- insert receiver logic below ----------------------->
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// <--------------------------------------------------------------------------->
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// weighted summation
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wire [11:0] vio_sin_0;
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wire [11:0] vio_sin_1;
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wire [11:0] vio_sin_2;
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wire [11:0] vio_sin_3;
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wire [11:0] vio_cos_0;
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wire [11:0] vio_cos_1;
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wire [11:0] vio_cos_2;
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wire [11:0] vio_cos_3;
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wire [4:0] vio_trunc;
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wire trunc_overflow;
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wire [15:0] dout_i;
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wire [15:0] dout_q;
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phase_compensate u_phase_compensate
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(
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.clk (sys_clk ), // input clk
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.rst (sys_rst ), // input rst
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.vio_sin_0 (vio_sin_0 ), // input [11:0] vio_sin_0
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.vio_sin_1 (vio_sin_1 ), // input [11:0] vio_sin_1
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.vio_sin_2 (vio_sin_2 ), // input [11:0] vio_sin_2
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.vio_sin_3 (vio_sin_3 ), // input [11:0] vio_sin_3
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.vio_cos_0 (vio_cos_0 ), // input [11:0] vio_cos_0
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.vio_cos_1 (vio_cos_1 ), // input [11:0] vio_cos_1
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.vio_cos_2 (vio_cos_2 ), // input [11:0] vio_cos_2
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.vio_cos_3 (vio_cos_3 ), // input [11:0] vio_cos_3
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.din_i_0 (rx_cal_ch1_i ), // input [11:0] din_i_0
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.din_i_1 (rx_cal_ch2_i ), // input [11:0] din_i_1
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.din_i_2 (rx_cal_ch3_i ), // input [11:0] din_i_2
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.din_i_3 (rx_cal_ch4_i ), // input [11:0] din_i_3
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.din_q_0 (rx_cal_ch1_q ), // input [11:0] din_q_0
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.din_q_1 (rx_cal_ch2_q ), // input [11:0] din_q_1
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.din_q_2 (rx_cal_ch3_q ), // input [11:0] din_q_2
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.din_q_3 (rx_cal_ch4_q ), // input [11:0] din_q_3
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.vio_trunc (vio_trunc ), // input [4:0] vio_trunc
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.dout_i (dout_i ), // output [15:0] dout_i
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.dout_q (dout_q ), // output [15:0] dout_q
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.trunc_overflow (trunc_overflow ) // output trunc_overflow
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);
|
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|
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// online acquisition
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wire freq_comp_start ;
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wire freq_comp_auto_enable_vio;
|
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wire freq_comp_start_vio;
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wire freq_comp_busy ;
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wire [7:0] dmf_num_per_ch ;
|
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wire dmf_continuous ;
|
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wire [31:0] freq_manual ;
|
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wire freq_manual_en ;
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wire [31:0] freq_target ;
|
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wire freq_target_valid;
|
|
|
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wire ch_peak_valid ;
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wire [17:0] ch1_peak_value_abs ;
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wire [17:0] ch1_peak_value_i ;
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wire [17:0] ch1_peak_value_q ;
|
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wire [10:0] ch1_peak_index ;
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wire [17:0] ch2_peak_value_abs ;
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wire [17:0] ch2_peak_value_i ;
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wire [17:0] ch2_peak_value_q ;
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wire [10:0] ch2_peak_index ;
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wire [17:0] ch3_peak_value_abs ;
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wire [17:0] ch3_peak_value_i ;
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wire [17:0] ch3_peak_value_q ;
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wire [10:0] ch3_peak_index ;
|
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wire [17:0] ch4_peak_value_abs ;
|
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wire [17:0] ch4_peak_value_i ;
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wire [17:0] ch4_peak_value_q ;
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wire [10:0] ch4_peak_index ;
|
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|
assign freq_comp_start = (freq_comp_auto_enable_vio == 1'b1) ? freq_comp_start_auto : freq_comp_start_vio;
|
|
|
|
freq_comp #(
|
|
.FREQ_WORD_LOWER (-1048576 ),
|
|
.FREQ_WORD_UPPER (1048575 ),
|
|
.FREQ_WORD_STEP (1024 )
|
|
) u_freq_comp
|
|
(
|
|
// clock & reset
|
|
.clk (sys_clk ), // input clk
|
|
.clk_4x (sys_clk_4x ), // input clk_4x
|
|
.rst (sys_rst ), // input rst
|
|
|
|
// input data
|
|
.freq_comp_start (freq_comp_start ), // input freq_comp_start
|
|
.freq_comp_busy (freq_comp_busy ), // output freq_comp_busy
|
|
|
|
.rx_data_valid (ad9361_cal_valid ), // input rx_data_valid
|
|
.rx_ch1_i (rx_cal_ch1_i ), // input [DATA_I_WIDTH-1 : 0] rx_ch1_i
|
|
.rx_ch1_q (rx_cal_ch1_q ), // input [DATA_I_WIDTH-1 : 0] rx_ch1_q
|
|
.rx_ch2_i (rx_cal_ch2_i ), // input [DATA_I_WIDTH-1 : 0] rx_ch2_i
|
|
.rx_ch2_q (rx_cal_ch2_q ), // input [DATA_I_WIDTH-1 : 0] rx_ch2_q
|
|
.rx_ch3_i (rx_cal_ch3_i ), // input [DATA_I_WIDTH-1 : 0] rx_ch3_i
|
|
.rx_ch3_q (rx_cal_ch3_q ), // input [DATA_I_WIDTH-1 : 0] rx_ch3_q
|
|
.rx_ch4_i (rx_cal_ch4_i ), // input [DATA_I_WIDTH-1 : 0] rx_ch4_i
|
|
.rx_ch4_q (rx_cal_ch4_q ), // input [DATA_I_WIDTH-1 : 0] rx_ch4_q
|
|
|
|
// configuration
|
|
.dmf_num_per_ch (dmf_num_per_ch ), // input [$clog2(MAX_DMF_NUM)-1 : 0] dmf_num_per_ch
|
|
.dmf_continuous (dmf_continuous ),
|
|
|
|
.freq_manual (freq_manual ), // input [FREQ_WORD_WIDTH-1 : 0] freq_manual
|
|
.freq_manual_en (freq_manual_en ), // input freq_manual_en
|
|
|
|
// output frequency result
|
|
.freq_target (freq_target ), // output [FREQ_WORD_WIDTH-1 : 0] freq_target
|
|
.freq_target_valid (freq_target_valid ), // output freq_target_valid
|
|
|
|
// output dmf result
|
|
.ch_peak_valid (ch_peak_valid ), // output ch_peak_valid
|
|
|
|
.ch1_peak_value_abs (ch1_peak_value_abs ), // output reg [DATA_O_WIDTH-1 : 0] ch1_peak_value_abs
|
|
.ch1_peak_value_i (ch1_peak_value_i ), // output reg [DATA_O_WIDTH-1 : 0] ch1_peak_value_i
|
|
.ch1_peak_value_q (ch1_peak_value_q ), // output reg [DATA_O_WIDTH-1 : 0] ch1_peak_value_q
|
|
.ch1_peak_index (ch1_peak_index ), // output reg [$clog2(PRBS_POS-1) : 0] ch1_peak_index
|
|
|
|
.ch2_peak_value_abs (ch2_peak_value_abs ), // output reg [DATA_O_WIDTH-1 : 0] ch2_peak_value_abs
|
|
.ch2_peak_value_i (ch2_peak_value_i ), // output reg [DATA_O_WIDTH-1 : 0] ch2_peak_value_i
|
|
.ch2_peak_value_q (ch2_peak_value_q ), // output reg [DATA_O_WIDTH-1 : 0] ch2_peak_value_q
|
|
.ch2_peak_index (ch2_peak_index ), // output reg [$clog2(PRBS_POS-1) : 0] ch2_peak_index
|
|
|
|
.ch3_peak_value_abs (ch3_peak_value_abs ), // output reg [DATA_O_WIDTH-1 : 0] ch3_peak_value_abs
|
|
.ch3_peak_value_i (ch3_peak_value_i ), // output reg [DATA_O_WIDTH-1 : 0] ch3_peak_value_i
|
|
.ch3_peak_value_q (ch3_peak_value_q ), // output reg [DATA_O_WIDTH-1 : 0] ch3_peak_value_q
|
|
.ch3_peak_index (ch3_peak_index ), // output reg [$clog2(PRBS_POS-1) : 0] ch3_peak_index
|
|
|
|
.ch4_peak_value_abs (ch4_peak_value_abs ), // output reg [DATA_O_WIDTH-1 : 0] ch4_peak_value_abs
|
|
.ch4_peak_value_i (ch4_peak_value_i ), // output reg [DATA_O_WIDTH-1 : 0] ch4_peak_value_i
|
|
.ch4_peak_value_q (ch4_peak_value_q ), // output reg [DATA_O_WIDTH-1 : 0] ch4_peak_value_q
|
|
.ch4_peak_index (ch4_peak_index ) // output reg [$clog2(PRBS_POS-1) : 0] ch4_peak_index
|
|
);
|
|
|
|
reg [12:0] chip_cnt = 'b0;
|
|
|
|
always @(posedge sys_clk) begin
|
|
if (sys_rst) begin
|
|
chip_cnt <= 'b0;
|
|
end
|
|
else begin
|
|
chip_cnt <= chip_cnt + 1'b1;
|
|
end
|
|
end
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
//////////////////////////////// ILAs and VIOs /////////////////////////////////
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
vio_clk_ld_rd u_vio_clk_ld_rd
|
|
(
|
|
.clk (sys_clk ),
|
|
.probe_in0 (ad9361_1_clk_ld),
|
|
.probe_in1 (ad9361_2_clk_ld)
|
|
);
|
|
|
|
vio_rfcontrl u_vio_rfcontrl
|
|
(
|
|
.clk (clk_48m ), // input wire clk
|
|
.probe_out0 (vio_switch ), // output wire [0 : 0] probe_out0
|
|
.probe_out1 (u_ant_rf_ctrl.vio_trdirection ), // output wire [0 : 0] probe_out1
|
|
.probe_out2 (vio_frequency[15:0] ), // output wire [15 : 0] probe_out2
|
|
.probe_out3 (u_ant_rf_ctrl.vio_emitMGC[7:0] ), // output wire [7 : 0] probe_out3
|
|
.probe_out4 (u_ant_rf_ctrl.vio_ch01MGC[3:0] ), // output wire [3 : 0] probe_out4
|
|
.probe_out5 (u_ant_rf_ctrl.vio_ch02MGC[3:0] ), // output wire [3 : 0] probe_out5
|
|
.probe_out6 (u_ant_rf_ctrl.vio_ch03MGC[3:0] ), // output wire [3 : 0] probe_out6
|
|
.probe_out7 (u_ant_rf_ctrl.vio_ch04MGC[3:0] ), // output wire [3 : 0] probe_out7
|
|
.probe_out8 (u_ant_rf_ctrl.vio_recvMGC[7:0] ), // output wire [7 : 0] probe_out8
|
|
.probe_out9 (u_ant_rf_ctrl.vio_AntMod[7:0] ), // output wire [7 : 0] probe_out9
|
|
.probe_out10(u_ant_rf_ctrl.vio_AntOffAxis[15:0] ), // output wire [15 : 0] probe_out10
|
|
.probe_out11(u_ant_rf_ctrl.vio_AntYaw[15:0] ), // output wire [15 : 0] probe_out11
|
|
.probe_out12(u_ant_rf_ctrl.vio_PrecessTime[15:0] ), // output wire [15 : 0] probe_out12
|
|
.probe_out13(rf_auto_start_vio ), // output wire [0 : 0] probe_out13
|
|
.probe_out14(rf_ctrl_mode_vio ), // output wire [0 : 0] probe_out14
|
|
.probe_out15(switch_next_freq_vio ), // output wire [0 : 0] probe_out15
|
|
.probe_out16(switch_last_freq_vio ), // output wire [0 : 0] probe_out16
|
|
.probe_out17(cnt_valid_to_switch_vio[31:0] ), // output wire [15: 0] probe_out17
|
|
.probe_out18(cnt_switch_to_freq_start_vio[31:0] ), // output wire [15: 0] probe_out18
|
|
.probe_out19(cnt_sync_in_vio[31:0] ), // output wire [31: 0] probe_out19
|
|
.probe_out20(cnt_sync_in_high_vio[31:0] ), // output wire [31: 0] probe_out20
|
|
.probe_in0 (vio_frequency_auto[15:0] ), // input wire [15: 0] probe_in0
|
|
.probe_in1 (debug_io_3 ) // input wire [0: 0] probe_in1
|
|
);
|
|
|
|
vio_ant_test u_vio_ant_test
|
|
(
|
|
.clk (clk_48m ),
|
|
.probe_out0 (u_ant_rf_ctrl.vio_mode_ant ),
|
|
.probe_out1 (u_ant_rf_ctrl.vio_hop_start ),
|
|
.probe_out2 (u_ant_rf_ctrl.vio_standby ),
|
|
.probe_out3 (u_ant_rf_ctrl.vio_hoptime[15:0] )
|
|
);
|
|
|
|
// ila_rfcontrl u_ila_rfcontrl
|
|
// (
|
|
// .clk (clk_48m ), // input wire clk
|
|
// .probe0 (u_ant_rf_ctrl.SPI_MOSI_F ), // input wire [0:0]
|
|
// .probe1 (u_ant_rf_ctrl.SPI_MISO_F ), // input wire [0:0]
|
|
// .probe2 (u_ant_rf_ctrl.SPI_SYN_F ), // input wire [0:0]
|
|
// .probe3 (u_ant_rf_ctrl.TP_EN_F ), // input wire [0:0]
|
|
// .probe4 (u_ant_rf_ctrl.TR_MGC_F ), // input wire [0:0]
|
|
// .probe5 (u_ant_rf_ctrl.CAL_F ), // input wire [0:0]
|
|
// .probe6 (u_ant_rf_ctrl.PRF ), // input wire [0:0]
|
|
// .probe7 (u_ant_rf_ctrl.rf_standby ), // input wire [0:0]
|
|
// .probe8 (u_ant_rf_ctrl.rf_sw_pll ), // input wire [0:0]
|
|
// .probe9 (u_ant_rf_ctrl.rf_t ), // input wire [0:0]
|
|
// .probe10(u_ant_rf_ctrl.rf_r ), // input wire [0:0]
|
|
// .probe11(u_ant_rf_ctrl.rf_sw_bpf ), // input wire [0:0]
|
|
// .probe12(u_ant_rf_ctrl.rf_sclk1 ), // input wire [0:0]
|
|
// .probe13(u_ant_rf_ctrl.rf_sdio1 ), // input wire [0:0]
|
|
// .probe14(u_ant_rf_ctrl.rf_cs1 ), // input wire [0:0]
|
|
// .probe15(u_ant_rf_ctrl.rf_ld1 ), // input wire [0:0]
|
|
// .probe16(u_ant_rf_ctrl.rf_sclk2 ), // input wire [0:0]
|
|
// .probe17(u_ant_rf_ctrl.rf_sdio2 ), // input wire [0:0]
|
|
// .probe18(u_ant_rf_ctrl.rf_cs2 ), // input wire [0:0]
|
|
// .probe19(u_ant_rf_ctrl.rf_ld2 ), // input wire [0:0]
|
|
// .probe20(u_ant_rf_ctrl.rf_sclk3 ), // input wire [0:0]
|
|
// .probe21(u_ant_rf_ctrl.rf_sdio3 ), // input wire [0:0]
|
|
// .probe22(u_ant_rf_ctrl.rf_cs3 ), // input wire [0:0]
|
|
// .probe23(u_ant_rf_ctrl.rf_ld3 ), // input wire [0:0]
|
|
// .probe24(u_ant_rf_ctrl.rf_tmgc_16 ), // input wire [0:0]
|
|
// .probe25(u_ant_rf_ctrl.rf_tmgc_8 ), // input wire [0:0]
|
|
// .probe26(u_ant_rf_ctrl.rf_tmgc_4 ), // input wire [0:0]
|
|
// .probe27(u_ant_rf_ctrl.rf_tmgc_2 ), // input wire [0:0]
|
|
// .probe28(u_ant_rf_ctrl.rf_tmgc_1 ), // input wire [0:0]
|
|
// .probe29(u_ant_rf_ctrl.rf_rmgc_16 ), // input wire [0:0]
|
|
// .probe30(u_ant_rf_ctrl.rf_rmgc_8 ), // input wire [0:0]
|
|
// .probe31(u_ant_rf_ctrl.rf_rmgc_4 ), // input wire [0:0]
|
|
// .probe32(u_ant_rf_ctrl.rf_rmgc_2 ), // input wire [0:0]
|
|
// .probe33(u_ant_rf_ctrl.rf_rmgc_1 ), // input wire [0:0]
|
|
// .probe34(u_ant_rf_ctrl.rf_enable ), // input wire [0:0]
|
|
// .probe35(u_ant_rf_ctrl.rf_sc ), // input wire [0:0]
|
|
// .probe36(u_ant_rf_ctrl.rf_sd ), // input wire [0:0]
|
|
// .probe37(u_ant_rf_ctrl.rf_endsyn ), // input wire [0:0]
|
|
// .probe38(u_ant_rf_ctrl.rf_sdout ), // input wire [0:0]
|
|
// .probe39(u_ant_rf_ctrl.state_rfdata[1:0] ), // input wire [0:0]
|
|
// .probe40(u_ant_rf_ctrl.RF_temperature[7:0] ), // input wire [0:0]
|
|
// .probe41(u_ant_rf_ctrl.RF_IFlocked[7:0] ), // input wire [0:0]
|
|
// .probe42(u_ant_rf_ctrl.RF_RFAlocked[7:0] ), // input wire [0:0]
|
|
// .probe43(u_ant_rf_ctrl.RF_RFBlocked[7:0] ), // input wire [0:0]
|
|
// .probe44(u_ant_rf_ctrl.RF_ch1mgc[3:0] ), // input wire [0:0]
|
|
// .probe45(u_ant_rf_ctrl.RF_ch2mgc[3:0] ), // input wire [0:0]
|
|
// .probe46(u_ant_rf_ctrl.RF_ch3mgc[3:0] ), // input wire [0:0]
|
|
// .probe47(u_ant_rf_ctrl.RF_ch4mgc[3:0] ), // input wire [0:0]
|
|
// .probe48(u_ant_rf_ctrl.RF_Framecount[31:0] ), // input wire [0:0]
|
|
// .probe49(u_ant_rf_ctrl.RF_RecvWord[95:0] ) // input wire [0:0]
|
|
// );
|
|
|
|
ila_rf_auto_control u_ila_rf_auto_control
|
|
(
|
|
.clk (clk_48m ),
|
|
.probe0 (u_rf_auto_switch_freq.sync_in ),
|
|
.probe1 (u_rf_auto_switch_freq.sync_in_cnt ), // 32
|
|
.probe2 (u_rf_auto_switch_freq.sync_in_high_cnt ), // 32
|
|
.probe3 (u_rf_auto_switch_freq.sync_in_reg ),
|
|
.probe4 (u_rf_auto_switch_freq.sync_in_valid ),
|
|
.probe5 (u_rf_auto_switch_freq.freq_word_cnt ) // 8
|
|
);
|
|
|
|
// ila_AntCtrl u_ila_AntCtrl
|
|
// (
|
|
// .clk (clk_96m ), // input wire clk
|
|
// .probe0 (u_ant_rf_ctrl.ant_clk ), // input wire [0:0] probe0
|
|
// .probe1 (u_ant_rf_ctrl.ant_en ), // input wire [0:0] probe1
|
|
// .probe2 (u_ant_rf_ctrl.ant_data ), // input wire [0:0] probe2
|
|
// .probe3 (u_ant_rf_ctrl.ant_tr ), // input wire [0:0] probe3
|
|
// .probe4 (u_ant_rf_ctrl.ant_dary ), // input wire [0:0] probe4
|
|
// .probe5 (u_ant_rf_ctrl.ant_dout ), // input wire [0:0] probe5
|
|
// .probe6 (u_ant_rf_ctrl.state_antdata[1:0] ), // input wire [0:0] probe5
|
|
// .probe7 (u_ant_rf_ctrl.Ant_Ant_Volt[7:0] ), // input wire [0:0] probe5
|
|
// .probe8 (u_ant_rf_ctrl.Ant_RF_Volt[7:0] ), // input wire [0:0] probe5
|
|
// .probe9 (u_ant_rf_ctrl.Ant_IF_Volt[7:0] ), // input wire [0:0] probe5
|
|
// .probe10(u_ant_rf_ctrl.Ant_state[7:0] ), // input wire [0:0] probe5
|
|
// .probe11(u_ant_rf_ctrl.Ant_Framecount[31:0] ), // input wire [0:0] probe5
|
|
// .probe12(u_ant_rf_ctrl.Ant_RecvWord[95:0] ) // input wire [0:0] probe5
|
|
// );
|
|
|
|
vio_rf_rd u_vio_rf_rd (
|
|
.clk (clk_96m ), // input wire clk
|
|
.probe_in0 (u_ant_rf_ctrl.RF_temperature[7:0] ), // input wire [7 : 0] probe_in0
|
|
.probe_in1 (u_ant_rf_ctrl.RF_IFlocked[7:0] ), // input wire [7 : 0] probe_in1
|
|
.probe_in2 (u_ant_rf_ctrl.RF_RFAlocked[7:0] ), // input wire [7 : 0] probe_in2
|
|
.probe_in3 (u_ant_rf_ctrl.RF_RFBlocked[7:0] ), // input wire [7 : 0] probe_in3
|
|
.probe_in4 (u_ant_rf_ctrl.RF_ch1mgc[3:0] ), // input wire [3 : 0] probe_in4
|
|
.probe_in5 (u_ant_rf_ctrl.RF_ch2mgc[3:0] ), // input wire [3 : 0] probe_in5
|
|
.probe_in6 (u_ant_rf_ctrl.RF_ch3mgc[3:0] ), // input wire [3 : 0] probe_in6
|
|
.probe_in7 (u_ant_rf_ctrl.RF_ch4mgc[3:0] ), // input wire [3 : 0] probe_in7
|
|
.probe_in8 (u_ant_rf_ctrl.RF_Framecount[31:0] ), // input wire [31 : 0] probe_in8
|
|
.probe_in9 (u_ant_rf_ctrl.RF_RecvWord_last ) // input wire [95 : 0] probe_in9
|
|
);
|
|
|
|
vio_ant_rd u_vio_ant_rd (
|
|
.clk (clk_96m ), // input wire clk
|
|
.probe_in0 (u_ant_rf_ctrl.Ant_Ant_Volt[7:0] ), // input wire [7 : 0] probe_in0
|
|
.probe_in1 (u_ant_rf_ctrl.Ant_RF_Volt[7:0] ), // input wire [7 : 0] probe_in1
|
|
.probe_in2 (u_ant_rf_ctrl.Ant_IF_Volt[7:0] ), // input wire [7 : 0] probe_in2
|
|
.probe_in3 (u_ant_rf_ctrl.Ant_state[7:0] ), // input wire [7 : 0] probe_in3
|
|
.probe_in4 (u_ant_rf_ctrl.Ant_Framecount[31:0] ), // input wire [31 : 0] probe_in4
|
|
.probe_in5 (u_ant_rf_ctrl.Ant_RecvWord_last ) // input wire [95 : 0] probe_in5
|
|
);
|
|
|
|
ila_2x12x1024 u_ila_tx
|
|
(
|
|
.clk (sys_clk ), // input wire clk
|
|
.probe0 (tx_ch1_i ), // input wire [11:0] probe0
|
|
.probe1 (tx_ch1_q ) // input wire [11:0] probe1
|
|
);
|
|
|
|
ila_rx_data_cnt u_ila_rx
|
|
(
|
|
.clk (sys_clk ), // input wire clk
|
|
.probe0 (rx_cal_ch1_i ), // input wire [11:0] probe0
|
|
.probe1 (rx_cal_ch1_q ), // input wire [11:0] probe1
|
|
.probe2 (rx_cal_ch2_i ), // input wire [11:0] probe2
|
|
.probe3 (rx_cal_ch2_q ), // input wire [11:0] probe3
|
|
.probe4 (rx_cal_ch3_i ), // input wire [11:0] probe4
|
|
.probe5 (rx_cal_ch3_q ), // input wire [11:0] probe5
|
|
.probe6 (rx_cal_ch4_i ), // input wire [11:0] probe6
|
|
.probe7 (rx_cal_ch4_q ), // input wire [11:0] probe7
|
|
.probe8 (vio_frequency_auto[11:0] ), // input wire [11:0] probe8
|
|
.probe9 (chip_cnt ), // input wire [9:0] probe9
|
|
.probe10(dout_i ), // input wire [15:0] probe10
|
|
.probe11(dout_q ) // input wire [15:0] probe11
|
|
);
|
|
|
|
ila_cal u_ila_cal
|
|
(
|
|
.clk (sys_clk ), // input wire clk
|
|
.probe0 (u_ad9361_phase_cal.ad9361_1_cal_start_d2 ), // input wire [0:0] probe0
|
|
.probe1 (u_ad9361_phase_cal.ad9361_1_cal_done ), // input wire [0:0] probe1
|
|
.probe2 (u_ad9361_phase_cal.ad9361_2_cal_start_d2 ), // input wire [0:0] probe2
|
|
.probe3 (u_ad9361_phase_cal.ad9361_2_cal_done ), // input wire [0:0] probe3
|
|
.probe4 (u_ad9361_phase_cal.ad9361_cal_result ), // input wire [0:0] probe4
|
|
.probe5 (u_ad9361_phase_cal.ad9361_recal_d2 ), // input wire [0:0] probe5
|
|
.probe6 (u_ad9361_phase_cal.curr_state ), // input wire [1:0] probe6
|
|
.probe7 (rx_ch2_i ), // input wire [11:0] probe7
|
|
.probe8 (rx_ch2_q ), // input wire [11:0] probe8
|
|
.probe9 (rx_ch4_i ), // input wire [11:0] probe9
|
|
.probe10(rx_ch4_q ), // input wire [11:0] probe10
|
|
.probe11(rx_cal_ch2_i ), // input wire [11:0] probe11
|
|
.probe12(rx_cal_ch2_q ), // input wire [11:0] probe12
|
|
.probe13(rx_cal_ch4_i ), // input wire [11:0] probe13
|
|
.probe14(rx_cal_ch4_q ) // input wire [11:0] probe14
|
|
);
|
|
|
|
vio_manual_ctrl u_vio_manual_ctrl
|
|
(
|
|
.clk (sys_clk ), // input wire clk
|
|
.probe_out0 (waveform_sel[1:0] ), // output wire [1 : 0] probe_out0
|
|
.probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1
|
|
.probe_out2 (freq_set[31:0] ), // output wire [31 : 0] probe_out2
|
|
.probe_out3 (iq_sel[1:0] ), // output wire [1 : 0] probe_out3
|
|
.probe_out4 (bb_rshift[3:0] ) // output wire [3 : 0] probe_out4
|
|
);
|
|
|
|
vio_freq_comp u_vio_freq_comp
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(
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.clk (sys_clk_4x ), // input wire clk
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.probe_in0 (freq_comp_busy ), // input wire [0 : 0] probe_in0
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.probe_out0 (freq_comp_start_vio ), // output wire [0 : 0] probe_out0
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.probe_out1 (dmf_num_per_ch ), // output wire [7 : 0] probe_out1
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.probe_out2 (freq_manual_en ), // output wire [0 : 0] probe_out2
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.probe_out3 (freq_manual ), // output wire [31 : 0] probe_out3
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.probe_out4 (freq_comp_auto_enable_vio ), // output wire [0 : 0] probe_out4
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.probe_out5 (dmf_continuous ) // output wire [0 : 0] probe_out5
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);
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ila_freq_comp u_ila_freq_comp
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(
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.clk (sys_clk_4x ), // input wire clk
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.probe0 (ch_peak_valid ), // input wire [0:0] probe0
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.probe1 (ch1_peak_value_i ), // input wire [17:0] probe1
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.probe2 (ch1_peak_value_q ), // input wire [17:0] probe2
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.probe3 (ch2_peak_value_i ), // input wire [17:0] probe3
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.probe4 (ch2_peak_value_q ), // input wire [17:0] probe4
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.probe5 (ch3_peak_value_i ), // input wire [17:0] probe5
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.probe6 (ch3_peak_value_q ), // input wire [17:0] probe6
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.probe7 (ch4_peak_value_i ), // input wire [17:0] probe7
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.probe8 (ch4_peak_value_q ), // input wire [17:0] probe8
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.probe9 (ch1_peak_index ), // input wire [10:0] probe9
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.probe10(ch2_peak_index ), // input wire [10:0] probe10
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.probe11(ch3_peak_index ), // input wire [10:0] probe11
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.probe12(ch4_peak_index ), // input wire [10:0] probe12
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.probe13(freq_comp_start ), // input wire [0:0] probe13
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.probe14(u_freq_comp.state_curr ), // input wire [2:0] probe14
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.probe15(u_freq_comp.din_freq_cxr_real ), // input wire [11:0] probe15
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.probe16(u_freq_comp.din_freq_cxr_imag ), // input wire [11:0] probe16
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.probe17(u_freq_comp.dmf_freq_moduli_abs ), // input wire [17:0] probe17
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.probe18(u_freq_comp.dmf_ch_moduli_abs[0] ), // input wire [17:0] probe18
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.probe19(u_freq_comp.freq_word ), // input wire [31:0] probe19
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.probe20(vio_frequency_auto[11:0] ) // input wire [11:0] probe20
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);
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vio_phase_comp u_vio_phase_comp
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(
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.clk (sys_clk ), // input wire clk
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.probe_in0 (trunc_overflow ), // input wire [0 : 0] probe_in0
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.probe_out0 (vio_sin_0 ), // output wire [11 : 0] probe_out0
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.probe_out1 (vio_sin_1 ), // output wire [11 : 0] probe_out1
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.probe_out2 (vio_sin_2 ), // output wire [11 : 0] probe_out2
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.probe_out3 (vio_sin_3 ), // output wire [11 : 0] probe_out3
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.probe_out4 (vio_cos_0 ), // output wire [11 : 0] probe_out4
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.probe_out5 (vio_cos_1 ), // output wire [11 : 0] probe_out5
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.probe_out6 (vio_cos_2 ), // output wire [11 : 0] probe_out6
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.probe_out7 (vio_cos_3 ), // output wire [11 : 0] probe_out7
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.probe_out8 (vio_trunc ) // output wire [4 : 0] probe_out8
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);
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endmodule
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