Archived
139 lines
6.3 KiB
Tcl
139 lines
6.3 KiB
Tcl
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package require qsys
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source ../../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
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ad_ip_create intel_serdes {Intel SERDES}
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set_module_property COMPOSITION_CALLBACK p_intel_serdes
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# parameters
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ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
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ad_ip_parameter MODE STRING "CLK" false
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ad_ip_parameter DDR_OR_SDR_N INTEGER 1 false
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ad_ip_parameter SERDES_FACTOR INTEGER 8 false
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ad_ip_parameter CLKIN_FREQUENCY FLOAT 500.0 false
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set_parameter_property MODE ALLOWED_RANGES {"CLK" "IN" "IN_NODPA" "OUT"}
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set_parameter_property DDR_OR_SDR_N ALLOWED_RANGES {0 1}
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set_parameter_property SERDES_FACTOR ALLOWED_RANGES {4 8}
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set_parameter_property CLKIN_FREQUENCY DISPLAY_UNITS "MHz"
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proc p_intel_serdes {} {
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set m_mode [get_parameter_value "MODE"]
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set m_ddr_or_sdr_n [get_parameter_value "DDR_OR_SDR_N"]
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set m_serdes_factor [get_parameter_value "SERDES_FACTOR"]
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set m_clkin_frequency [get_parameter_value "CLKIN_FREQUENCY"]
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set m_hs_data_rate [expr ($m_clkin_frequency * ($m_ddr_or_sdr_n + 1))]
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set m_ls_data_rate [expr ($m_hs_data_rate/$m_serdes_factor)]
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set m_ls_phase 22.5
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set m_ld_phase 315.0
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set m_ld_duty_cycle 12.5
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if {$m_serdes_factor == 4} {
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set m_ls_phase 45
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set m_ld_phase 270.0
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set m_ld_duty_cycle 25.0
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}
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## arria 10 only
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if {$m_mode == "CLK"} {
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add_instance intel_serdes_pll altera_iopll 19.1
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set_instance_parameter_value intel_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency
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set_instance_parameter_value intel_serdes_pll {gui_use_locked} {1}
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set_instance_parameter_value intel_serdes_pll {gui_operation_mode} {lvds}
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set_instance_parameter_value intel_serdes_pll {gui_number_of_clocks} {3}
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set_instance_parameter_value intel_serdes_pll {gui_en_lvds_ports} {Enable LVDS_CLK/LOADEN 0}
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set_instance_parameter_value intel_serdes_pll {gui_en_phout_ports} {true}
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set_instance_parameter_value intel_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate
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set_instance_parameter_value intel_serdes_pll {gui_ps_units0} {degrees}
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set_instance_parameter_value intel_serdes_pll {gui_phase_shift_deg0} {180.0}
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set_instance_parameter_value intel_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate
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set_instance_parameter_value intel_serdes_pll {gui_ps_units1} {degrees}
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set_instance_parameter_value intel_serdes_pll {gui_phase_shift_deg1} $m_ld_phase
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set_instance_parameter_value intel_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle
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set_instance_parameter_value intel_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate
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set_instance_parameter_value intel_serdes_pll {gui_phase_shift_deg2} $m_ls_phase
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set_instance_parameter_value intel_serdes_pll {gui_ps_units2} {degrees}
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add_interface rst reset sink
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set_interface_property rst EXPORT_OF intel_serdes_pll.reset
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add_interface ref_clk clock sink
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set_interface_property ref_clk EXPORT_OF intel_serdes_pll.refclk
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add_interface locked conduit end
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set_interface_property locked EXPORT_OF intel_serdes_pll.locked
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add_interface hs_phase conduit end
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set_interface_property hs_phase EXPORT_OF intel_serdes_pll.phout
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add_interface hs_clk conduit end
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set_interface_property hs_clk EXPORT_OF intel_serdes_pll.lvds_clk
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add_interface loaden conduit end
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set_interface_property loaden EXPORT_OF intel_serdes_pll.loaden
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add_interface ls_clk clock source
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set_interface_property ls_clk EXPORT_OF intel_serdes_pll.outclk2
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return
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}
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if {$m_mode == "IN" || $m_mode == "IN_NODPA"} {
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add_instance intel_serdes_in altera_lvds 19.1
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if {$m_mode == "IN"} {
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set_instance_parameter_value intel_serdes_in {MODE} {RX_DPA-FIFO}
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} else {
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set_instance_parameter_value intel_serdes_in {MODE} {RX_Non-DPA}
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}
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set_instance_parameter_value intel_serdes_in {NUM_CHANNELS} {1}
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set_instance_parameter_value intel_serdes_in {DATA_RATE} $m_hs_data_rate
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set_instance_parameter_value intel_serdes_in {J_FACTOR} $m_serdes_factor
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set_instance_parameter_value intel_serdes_in {USE_EXTERNAL_PLL} {true}
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set_instance_parameter_value intel_serdes_in {INCLOCK_FREQUENCY} $m_clkin_frequency
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set_instance_parameter_value intel_serdes_in {PLL_USE_RESET} {false}
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add_interface data_in conduit end
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set_interface_property data_in EXPORT_OF intel_serdes_in.rx_in
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add_interface clk conduit end
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set_interface_property clk EXPORT_OF intel_serdes_in.ext_fclk
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add_interface loaden conduit end
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set_interface_property loaden EXPORT_OF intel_serdes_in.ext_loaden
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add_interface div_clk conduit end
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set_interface_property div_clk EXPORT_OF intel_serdes_in.ext_coreclock
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if {$m_mode == "IN"} {
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add_interface hs_phase conduit end
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set_interface_property hs_phase EXPORT_OF intel_serdes_in.ext_vcoph
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add_interface locked conduit end
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set_interface_property locked EXPORT_OF intel_serdes_in.ext_pll_locked
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add_interface delay_locked conduit end
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set_interface_property delay_locked EXPORT_OF intel_serdes_in.rx_dpa_locked
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}
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add_interface data_s conduit end
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set_interface_property data_s EXPORT_OF intel_serdes_in.rx_out
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return
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}
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if {$m_mode == "OUT"} {
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add_instance intel_serdes_out altera_lvds 19.1
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set_instance_parameter_value intel_serdes_out {MODE} {TX}
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set_instance_parameter_value intel_serdes_out {NUM_CHANNELS} {1}
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set_instance_parameter_value intel_serdes_out {DATA_RATE} $m_hs_data_rate
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set_instance_parameter_value intel_serdes_out {J_FACTOR} $m_serdes_factor
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set_instance_parameter_value intel_serdes_out {TX_EXPORT_CORECLOCK} {false}
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set_instance_parameter_value intel_serdes_out {TX_USE_OUTCLOCK} {false}
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set_instance_parameter_value intel_serdes_out {USE_EXTERNAL_PLL} {true}
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set_instance_parameter_value intel_serdes_out {INCLOCK_FREQUENCY} $m_clkin_frequency
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set_instance_parameter_value intel_serdes_out {PLL_USE_RESET} {false}
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add_interface data_out conduit end
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set_interface_property data_out EXPORT_OF intel_serdes_out.tx_out
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add_interface clk conduit end
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set_interface_property clk EXPORT_OF intel_serdes_out.ext_fclk
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add_interface loaden conduit end
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set_interface_property loaden EXPORT_OF intel_serdes_out.ext_loaden
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add_interface div_clk conduit end
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set_interface_property div_clk EXPORT_OF intel_serdes_out.ext_coreclock
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add_interface data_s conduit end
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set_interface_property data_s EXPORT_OF intel_serdes_out.tx_in
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return
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}
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}
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