Archived
367 lines
10 KiB
Verilog
367 lines
10 KiB
Verilog
//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact [email protected] for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module axi_jesd204_tx_regmap_tb;
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parameter VCD_FILE = "axi_jesd204_tx_regmap_tb.vcd";
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parameter NUM_LANES = 2;
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parameter NUM_LINKS = 2;
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`define TIMEOUT 1000000
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`include "tb_base.v"
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reg [1:0] core_status_state = 2'b00;
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reg [NUM_LINKS-1:0] core_status_sync = {NUM_LINKS{1'b0}};
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wire s_axi_aclk = clk;
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wire s_axi_aresetn = ~reset;
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reg s_axi_awvalid = 1'b0;
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reg s_axi_wvalid = 1'b0;
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reg [13:0] s_axi_awaddr = 'h00;
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reg [31:0] s_axi_wdata = 'h00;
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wire [1:0] s_axi_bresp;
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wire s_axi_awready;
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wire s_axi_wready;
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wire s_axi_bready = 1'b1;
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wire [3:0] s_axi_wstrb = 4'b1111;
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wire [2:0] s_axi_awprot = 3'b000;
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wire [2:0] s_axi_arprot = 3'b000;
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wire [1:0] s_axi_rresp;
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wire [31:0] s_axi_rdata;
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reg [31:0] expected_reg_mem[0:1023];
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task write_reg;
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input [31:0] addr;
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input [31:0] value;
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begin
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@(posedge s_axi_aclk)
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s_axi_awvalid <= 1'b1;
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s_axi_wvalid <= 1'b1;
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s_axi_awaddr <= addr;
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s_axi_wdata <= value;
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@(posedge s_axi_aclk)
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while (s_axi_awvalid || s_axi_wvalid) begin
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@(posedge s_axi_aclk)
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if (s_axi_awready)
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s_axi_awvalid <= 1'b0;
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if (s_axi_wready)
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s_axi_wvalid <= 1'b0;
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end
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end
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endtask
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reg [13:0] s_axi_araddr = 'h0;
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reg s_axi_arvalid = 'h0;
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reg s_axi_rready = 'h0;
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wire s_axi_arready;
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wire s_axi_rvalid;
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task read_reg;
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input [31:0] addr;
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output [31:0] value;
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begin
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s_axi_arvalid <= 1'b1;
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s_axi_araddr <= addr;
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s_axi_rready <= 1'b1;
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@(posedge s_axi_aclk) #0;
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while (s_axi_arvalid) begin
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if (s_axi_arready == 1'b1) begin
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s_axi_arvalid <= 1'b0;
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end
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@(posedge s_axi_aclk) #0;
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end
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while (s_axi_rready) begin
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if (s_axi_rvalid == 1'b1) begin
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value <= s_axi_rdata;
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s_axi_rready <= 1'b0;
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end
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@(posedge s_axi_aclk) #0;
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end
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end
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endtask
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task read_reg_check;
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input [31:0] addr;
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output match;
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reg [31:0] value;
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reg [31:0] expected;
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begin
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read_reg(addr, value);
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expected = expected_reg_mem[addr[13:2]];
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match <= value === expected;
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end
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endtask
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reg read_match = 1'b1;
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always @(posedge clk) begin
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if (read_match == 1'b0) begin
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failed <= 1'b1;
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end
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end
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task set_reset_reg_value;
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input [31:0] addr;
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input [31:0] value;
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begin
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expected_reg_mem[addr[13:2]] <= value;
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end
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endtask
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task initialize_expected_reg_mem;
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integer i;
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begin
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for (i = 0; i < 1024; i = i + 1)
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expected_reg_mem[i] <= 'h00;
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/* Non zero power-on-reset values */
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set_reset_reg_value('h00, 32'h00010161); /* PCORE version register */
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set_reset_reg_value('h0c, 32'h32303454); /* PCORE magic register */
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set_reset_reg_value('h10, NUM_LANES); /* Number of lanes */
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set_reset_reg_value('h14, 'h2); /* Datapath width */
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set_reset_reg_value('h18, NUM_LINKS); /* Number of links */
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set_reset_reg_value('hc0, 'h1); /* Link disable */
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set_reset_reg_value('hc4, 'h1); /* Core state */
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// set_reset_reg_value('hc8, 'h80000); /* clock monitor */
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set_reset_reg_value('h210, 'h3); /* OCTETS_PER_MULTIFRAME */
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set_reset_reg_value('h244, 'h3); /* MFRAMES_PER_ILAS */
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end
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endtask
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task check_all_registers;
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integer i;
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begin
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for (i = 0; i < 'h400; i = i + 4) begin
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read_reg_check(i, read_match);
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end
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end
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endtask
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task write_reg_and_update;
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input [31:0] addr;
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input [31:0] value;
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integer i;
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begin
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write_reg(addr, value);
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expected_reg_mem[addr[13:2]] <= value;
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/* Special case for ILAS */
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if (addr >= 'h310 && addr < 'h310 + 32 * NUM_LANES) begin
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for (i = 0; i < NUM_LANES; i = i + 1) begin
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case (addr[3:2])
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2'b01: expected_reg_mem['h310/4 + i * 8 + 1][31:5] <= value[31:5];
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2'b11: expected_reg_mem['h310/4 + i * 8 + 3][23:0] <= value[23:0];
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default: expected_reg_mem['h310/4 + i * 8 + addr[3:2]] <= value;
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endcase
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end
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end
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if (addr == 'hc0) begin
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expected_reg_mem['hc4/4][0] <= value[0];
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end
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end
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endtask
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task invert_register;
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input [31:0] addr;
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reg [31:0] value;
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begin
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read_reg(addr, value);
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write_reg(addr, ~value);
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end
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endtask
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task invert_all_registers;
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integer i;
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begin
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for (i = 0; i < 'h400; i = i + 4) begin
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invert_register(i);
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end
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end
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endtask
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integer i;
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initial begin
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initialize_expected_reg_mem();
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@(posedge s_axi_aresetn)
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check_all_registers();
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/* Check scratch */
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write_reg_and_update('h08, 32'h12345678);
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check_all_registers();
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/* Check IRQ mask */
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write_reg_and_update('h80, 32'h0);
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check_all_registers();
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/* Check lanes disable */
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write_reg_and_update('h200, {NUM_LANES{1'b1}});
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check_all_registers();
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/* Check JESD common config */
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write_reg_and_update('h210, 32'hff03ff);
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check_all_registers();
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write_reg_and_update('h214, 32'h03);
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check_all_registers();
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/* Check links disable */
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write_reg_and_update('h218, {NUM_LINKS{1'b1}});
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check_all_registers();
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/* Check JESD TX configuration */
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write_reg_and_update('h240, 32'h07);
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check_all_registers();
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/* Check mframes per ILAS - RO at the moment */
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write_reg('h244, 32'hff);
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check_all_registers();
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/* Check status register */
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core_status_state = 2'b01; /* CGS */
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set_reset_reg_value('h280, 32'h00000001);
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check_all_registers();
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core_status_state = 2'b10; /* ILAS */
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set_reset_reg_value('h280, 32'h00000002);
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check_all_registers();
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core_status_state = 2'b11; /* DATA */
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set_reset_reg_value('h280, 32'h00000003);
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check_all_registers();
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core_status_state = 2'b00; /* WAIT */
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set_reset_reg_value('h280, 32'h00000000);
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check_all_registers();
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core_status_sync = {NUM_LINKS{1'b1}}; /* SYNC deasserted */
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set_reset_reg_value('h280, ({NUM_LINKS{1'b1}} << 4));
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check_all_registers();
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core_status_sync = {NUM_LINKS{1'b0}}; /* SYNC asserted */
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set_reset_reg_value('h280, 32'h00000000);
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check_all_registers();
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/* ILAS register */
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for (i = 0; i < NUM_LANES; i = i + 1) begin
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write_reg_and_update('h310 + i * 32, 32'h0fff0000);
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write_reg_and_update('h314 + i * 32, 32'h1fff9f1f ^ i);
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write_reg_and_update('h318 + i * 32, 32'hffffdfff ^ i);
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write_reg_and_update('h31c + i * 32, 32'h0f00009f ^ (2 << 24));
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end
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check_all_registers();
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/* Reset core */
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write_reg_and_update('hc0, 32'h0);
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check_all_registers();
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/* Should be read-only when core is out of reset */
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invert_register('h200);
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invert_register('h210);
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invert_register('h214);
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invert_register('h218);
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invert_register('h240);
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invert_register('h244);
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for (i = 0; i < NUM_LANES; i = i + 1) begin
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invert_register('h310 + i * 32);
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invert_register('h314 + i * 32);
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invert_register('h318 + i * 32);
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invert_register('h31c + i * 32);
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end
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check_all_registers();
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/* Check that reset works for all registers */
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do_trigger_reset();
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initialize_expected_reg_mem();
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check_all_registers();
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invert_all_registers();
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do_trigger_reset();
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check_all_registers();
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end
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reg core_clk = 1'b0;
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always @(*) #4 core_clk <= ~core_clk;
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axi_jesd204_tx #(
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.NUM_LANES(NUM_LANES),
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.NUM_LINKS(NUM_LINKS)
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) i_axi (
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.s_axi_aclk(s_axi_aclk),
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.s_axi_aresetn(s_axi_aresetn),
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.s_axi_awvalid(s_axi_awvalid),
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.s_axi_awaddr(s_axi_awaddr),
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.s_axi_awready(s_axi_awready),
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.s_axi_awprot(s_axi_awprot),
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.s_axi_wvalid(s_axi_wvalid),
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.s_axi_wdata(s_axi_wdata),
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.s_axi_wstrb(s_axi_wstrb),
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.s_axi_wready(s_axi_wready),
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.s_axi_bvalid(s_axi_bvalid),
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.s_axi_bresp(s_axi_bresp),
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.s_axi_bready(s_axi_bready),
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.s_axi_arvalid(s_axi_arvalid),
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.s_axi_araddr(s_axi_araddr),
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.s_axi_arready(s_axi_arready),
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.s_axi_arprot(s_axi_arprot),
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.s_axi_rvalid(s_axi_rvalid),
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.s_axi_rready(s_axi_rready),
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.s_axi_rresp(s_axi_rresp),
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.s_axi_rdata(s_axi_rdata),
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.core_clk(core_clk),
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.core_reset_ext(1'b0),
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.core_ilas_config_rd(1'b1),
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.core_ilas_config_addr(2'b00),
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.core_event_sysref_alignment_error(1'b0),
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.core_event_sysref_edge(1'b0),
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.core_status_state(core_status_state),
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.core_status_sync(core_status_sync)
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);
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endmodule
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