Archived
306 lines
9.5 KiB
Verilog
306 lines
9.5 KiB
Verilog
//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact [email protected] for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module jesd204_up_tx # (
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parameter NUM_LANES = 1,
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parameter NUM_LINKS = 1
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) (
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input up_clk,
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input up_reset,
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input [11:0] up_raddr,
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output reg [31:0] up_rdata,
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input up_wreq,
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input [11:0] up_waddr,
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input [31:0] up_wdata,
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input up_cfg_is_writeable,
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output reg up_cfg_skip_ilas,
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output reg up_cfg_continuous_ilas,
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output reg up_cfg_continuous_cgs,
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output reg [7:0] up_cfg_mframes_per_ilas,
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input core_clk,
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input core_ilas_config_rd,
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input [1:0] core_ilas_config_addr,
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output reg [32*NUM_LANES-1:0] core_ilas_config_data,
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output core_ctrl_manual_sync_request,
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input [1:0] core_status_state,
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input [NUM_LINKS-1:0] core_status_sync
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);
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reg [31:0] up_cfg_ilas_data[0:NUM_LANES-1][0:3];
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reg up_ctrl_manual_sync_request = 1'b0;
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wire [1:0] up_status_state;
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wire [NUM_LINKS-1:0] up_status_sync;
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sync_bits #(
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.NUM_OF_BITS (NUM_LINKS))
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i_cdc_sync (
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.in_bits(core_status_sync),
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.out_clk(up_clk),
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.out_resetn(1'b1),
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.out_bits(up_status_sync)
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);
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sync_data #(
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.NUM_OF_BITS(2)
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) i_cdc_status (
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.in_clk(core_clk),
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.in_data(core_status_state),
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.out_clk(up_clk),
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.out_data(up_status_state)
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);
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sync_event #(
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.NUM_OF_EVENTS(1),
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.ASYNC_CLK(1)
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) i_cdc_manual_sync_request (
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.in_clk(up_clk),
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.in_event(up_ctrl_manual_sync_request),
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.out_clk(core_clk),
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.out_event(core_ctrl_manual_sync_request)
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);
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integer i;
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always @(*) begin
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case (up_raddr)
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/* JESD TX configuration */
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12'h090: up_rdata = {
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/* 03-31 */ 29'h00, /* Reserved for future additions */
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/* 02 */ up_cfg_skip_ilas, /* Don't send ILAS, go directly from CGS to DATA */
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/* 01 */ up_cfg_continuous_ilas, /* Continuously send ILAS sequence */
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/* 00 */ up_cfg_continuous_cgs /* Continuously send CGS characters */
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};
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12'h091: up_rdata = {
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/* 08-31 */ 24'h00, /* Reserved for future additions */
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/* 00-07 */ up_cfg_mframes_per_ilas /* Number of multiframes send during the ILAS */
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};
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/* JESD TX status */
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12'ha0: up_rdata = {
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/* 12-31 */ 20'h00, /* Reserved for future additions */
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/* 04-11 */ up_status_sync, /* Raw value of the SYNC pin */
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/* 02-03 */ 2'b0, /* Reserved fo future extension of the status_state field */
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/* 00-01 */ up_status_state /* State of the internal state machine (0=CGS, 1=ILAS, 2=DATA) */
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};
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default: begin
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if (up_raddr[10:3] >= ('h300/32) &&
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up_raddr[10:3] < (('h300/32) + NUM_LANES) &&
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up_raddr[2] == 1'b1) begin
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up_rdata = up_cfg_ilas_data[up_raddr[5:3]][up_raddr[1:0]];
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end else begin
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up_rdata = 32'h00000000;
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end
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end
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endcase
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end
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always @(posedge up_clk) begin
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if (up_reset == 1'b1) begin
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up_cfg_skip_ilas <= 1'b0;
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up_cfg_continuous_ilas <= 1'b0;
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up_cfg_continuous_cgs <= 1'b0;
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up_cfg_mframes_per_ilas <= 'h3;
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end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin
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case (up_waddr)
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/* JESD TX configuraton */
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12'h090: begin
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up_cfg_skip_ilas <= up_wdata[2];
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up_cfg_continuous_ilas <= up_wdata[1];
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up_cfg_continuous_cgs <= up_wdata[0];
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end
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12'h091: begin
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// We'll enable this if we ever have a usecase
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// cfg_mframes_per_ilas <= up_wdata[7:0];
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end
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endcase
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end
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end
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always @(posedge up_clk) begin
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if (up_reset == 1'b1) begin
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up_ctrl_manual_sync_request <= 1'b0;
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end else if (up_wreq == 1'b1 && up_waddr == 12'h092) begin
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up_ctrl_manual_sync_request <= up_wdata[0];
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end else begin
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up_ctrl_manual_sync_request <= 1'b0;
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end
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end
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/* Shared ILAS data can be access through any lane register map window */
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/* Shared ILAS data */
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reg [7:0] up_cfg_ilas_data_did = 'h00;
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reg [3:0] up_cfg_ilas_data_bid = 'h00;
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reg [4:0] up_cfg_ilas_data_l = 'h00;
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reg up_cfg_ilas_data_scr = 'h00;
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reg [7:0] up_cfg_ilas_data_f = 'h00;
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reg [4:0] up_cfg_ilas_data_k = 'h00;
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reg [7:0] up_cfg_ilas_data_m = 'h00;
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reg [4:0] up_cfg_ilas_data_n = 'h00;
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reg [1:0] up_cfg_ilas_data_cs = 'h00;
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reg [4:0] up_cfg_ilas_data_np = 'h00;
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reg [2:0] up_cfg_ilas_data_subclassv = 'h00;
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reg [4:0] up_cfg_ilas_data_s = 'h00;
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reg [2:0] up_cfg_ilas_data_jesdv = 'h00;
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reg [4:0] up_cfg_ilas_data_cf = 'h00;
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reg up_cfg_ilas_data_hd = 'h00;
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/* Per lane ILAS data */
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reg [4:0] up_cfg_ilas_data_lid[0:NUM_LANES-1];
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reg [7:0] up_cfg_ilas_data_fchk[0:NUM_LANES-1];
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always @(*) begin
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for (i = 0; i < NUM_LANES; i = i + 1) begin
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up_cfg_ilas_data[i][0] = {
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4'b0000,
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up_cfg_ilas_data_bid,
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up_cfg_ilas_data_did,
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16'h00
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};
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up_cfg_ilas_data[i][1] = {
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3'b000,
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up_cfg_ilas_data_k,
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up_cfg_ilas_data_f,
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up_cfg_ilas_data_scr,
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2'b00,
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up_cfg_ilas_data_l,
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3'b000,
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up_cfg_ilas_data_lid[i]
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};
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up_cfg_ilas_data[i][2] = {
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up_cfg_ilas_data_jesdv,
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up_cfg_ilas_data_s,
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up_cfg_ilas_data_subclassv,
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up_cfg_ilas_data_np,
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up_cfg_ilas_data_cs,
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1'b0,
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up_cfg_ilas_data_n,
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up_cfg_ilas_data_m
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};
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up_cfg_ilas_data[i][3] = {
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up_cfg_ilas_data_fchk[i],
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16'h0000,
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up_cfg_ilas_data_hd,
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2'b00,
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up_cfg_ilas_data_cf
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};
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end
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end
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always @(posedge up_clk) begin
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if (up_reset == 1'b1) begin
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up_cfg_ilas_data_did <= 'h00;
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up_cfg_ilas_data_bid <= 'h00;
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up_cfg_ilas_data_scr <= 'h00;
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up_cfg_ilas_data_f <= 'h00;
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up_cfg_ilas_data_k <= 'h00;
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up_cfg_ilas_data_m <= 'h00;
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up_cfg_ilas_data_n <= 'h00;
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up_cfg_ilas_data_cs <= 'h00;
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up_cfg_ilas_data_np <= 'h00;
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up_cfg_ilas_data_subclassv <= 'h00;
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up_cfg_ilas_data_s <= 'h00;
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up_cfg_ilas_data_jesdv <= 'h00;
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up_cfg_ilas_data_cf <= 'h00;
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up_cfg_ilas_data_hd <= 'h00;
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up_cfg_ilas_data_l <= 'h00;
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for (i = 0; i < NUM_LANES; i = i + 1) begin
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up_cfg_ilas_data_lid[i] <= 'h00;
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up_cfg_ilas_data_fchk[i] <= 'h00;
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end
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end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin
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for (i = 0; i < NUM_LANES; i = i + 1) begin
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if (up_waddr[10:2] == ('h310 / 16) + i*2) begin
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case (up_waddr[1:0])
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2'h0: begin
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up_cfg_ilas_data_bid <= up_wdata[27:24];
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up_cfg_ilas_data_did <= up_wdata[23:16];
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end
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2'h1: begin
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up_cfg_ilas_data_k <= up_wdata[28:24];
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up_cfg_ilas_data_f <= up_wdata[23:16];
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up_cfg_ilas_data_scr <= up_wdata[15];
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up_cfg_ilas_data_l <= up_wdata[12:8];
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up_cfg_ilas_data_lid[i] <= up_wdata[4:0];
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end
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2'h2: begin
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up_cfg_ilas_data_jesdv <= up_wdata[31:29];
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up_cfg_ilas_data_s <= up_wdata[28:24];
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up_cfg_ilas_data_subclassv <= up_wdata[23:21];
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up_cfg_ilas_data_np <= up_wdata[20:16];
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up_cfg_ilas_data_cs <= up_wdata[15:14];
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up_cfg_ilas_data_n <= up_wdata[12:8];
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up_cfg_ilas_data_m <= up_wdata[7:0];
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end
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2'h3: begin
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up_cfg_ilas_data_fchk[i] <= up_wdata[31:24];
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up_cfg_ilas_data_hd <= up_wdata[7];
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up_cfg_ilas_data_cf <= up_wdata[4:0];
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end
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endcase
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end
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end
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end
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end
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always @(posedge core_clk) begin
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if (core_ilas_config_rd == 1'b1) begin
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for (i = 0; i < NUM_LANES; i = i + 1) begin
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core_ilas_config_data[i*32+:32] <= up_cfg_ilas_data[i][core_ilas_config_addr];
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end
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end
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end
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endmodule
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