Archived
89 lines
2.1 KiB
Verilog
89 lines
2.1 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 05/06/2023 03:39:20 PM
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// Design Name:
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// Module Name: tb_freq_comp
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tb_freq_comp;
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reg clk = 1'b1;
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reg rst = 1'b1;
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reg freq_comp_start = 'b0;
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wire [11:0] tx_data_i, tx_data_q;
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wire [31:0] freq_target;
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wire freq_target_valid;
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initial begin
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#102;
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rst = 1'b0;
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#1000;
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freq_comp_start = ~freq_comp_start;
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end
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always #10 clk = ~clk;
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tx_qpsk u_tx_qpsk
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(
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.clk (clk ),
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.rst (rst ),
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.tx_data_i (tx_data_i ),
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.tx_data_q (tx_data_q ),
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// debug ports
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.waveform_sel (2'd1 ),
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.sweep_on (1'b0 ),
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.freq_set ('b0 ),
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.iq_sel (2'b11 ),
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.bb_rshift (4'd0 )
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);
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freq_comp #(
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.FREQ_WORD_LOWER(-1024 ),
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.FREQ_WORD_UPPER(10000 ),
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.FREQ_WORD_STEP (1024 )
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)u_freq_comp
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(
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.clk (clk ),
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.rst (rst ),
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.freq_comp_start (freq_comp_start ),
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.freq_comp_busy (freq_comp_busy ),
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.rx_data_valid (~rst ),
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.rx_ch1_i (tx_data_i ),
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.rx_ch1_q (tx_data_q ),
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.rx_ch2_i (tx_data_q ),
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.rx_ch2_q (tx_data_i ),
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.rx_ch3_i (tx_data_i ),
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.rx_ch3_q (tx_data_i ),
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.rx_ch4_i (tx_data_q ),
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.rx_ch4_q (tx_data_q ),
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.dmf_num_per_ch (2 ),
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.freq_manual (327680 ),
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.freq_manual_en (1'b0 ),
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.freq_target (freq_target ),
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.freq_target_valid (freq_target_valid )
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);
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endmodule
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