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"isBus": true, + "subnets": [ + { + "name": "freq_set[31]" + }, + { + "name": "freq_set[30]" + }, + { + "name": "freq_set[29]" + }, + { + "name": "freq_set[28]" + }, + { + "name": "freq_set[27]" + }, + { + "name": "freq_set[26]" + }, + { + "name": "freq_set[25]" + }, + { + "name": "freq_set[24]" + }, + { + "name": "freq_set[23]" + }, + { + "name": "freq_set[22]" + }, + { + "name": "freq_set[21]" + }, + { + "name": "freq_set[20]" + }, + { + "name": "freq_set[19]" + }, + { + "name": "freq_set[18]" + }, + { + "name": "freq_set[17]" + }, + { + "name": "freq_set[16]" + }, + { + "name": "freq_set[15]" + }, + { + "name": "freq_set[14]" + }, + { + "name": "freq_set[13]" + }, + { + "name": "freq_set[12]" + }, + { + "name": "freq_set[11]" + }, + { + "name": "freq_set[10]" + }, + { + "name": "freq_set[9]" + }, + { + "name": "freq_set[8]" + }, + { + "name": "freq_set[7]" + }, + { + "name": "freq_set[6]" + }, + { + "name": "freq_set[5]" + }, + { + "name": "freq_set[4]" + }, + { + "name": "freq_set[3]" + }, + { + "name": "freq_set[2]" + }, + { + "name": "freq_set[1]" + }, + { + "name": "freq_set[0]" + } + ] + } + ] + }, + { + "name": "probe_out3", + "id": 9, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 1, + "portIndex": 3, + "nets": [ + { + "name": "iq_sel", + "isBus": true, + "subnets": [ + { + "name": "iq_sel[1]" + }, + { + "name": "iq_sel[0]" + } + ] + } + ] + }, + { + "name": "probe_out4", + "id": 10, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 3, + "portIndex": 4, + "nets": [ + { + "name": "bb_rshift", + "isBus": true, + "subnets": [ + { + "name": "bb_rshift[3]" + }, + { + "name": "bb_rshift[2]" + }, + { + "name": "bb_rshift[1]" + }, + { + "name": "bb_rshift[0]" + } + ] + } + ] + } + ] + } + ] + } + ] + } +} \ No newline at end of file diff --git a/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/constrs_1/new/z7100_hmc7044_2ad9361.xdc b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/constrs_1/new/z7100_hmc7044_2ad9361.xdc new file mode 100644 index 0000000..baab13d --- /dev/null +++ b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/constrs_1/new/z7100_hmc7044_2ad9361.xdc @@ -0,0 +1,192 @@ +# df_z7100_2ad9361 + +## Timing Assertions Section + +## Physical Constraints Section + +# Clocks +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVDS } [get_ports clk_250m_p ] ;# FPGA_DAC_LOGIC_CLK_C_P +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_buffer_clk ] ;# AD9361_CLK_OUT +set_property -dict {PACKAGE_PIN F4 IOSTANDARD LVCMOS18} [get_ports ad9361_2_buffer_clk ] ;# B_AD9361_CLK_OUT + +# HMC7044-1 Interface +set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS33} [get_ports hmc7044_spi_clk ] ;# HMC7044_1_SCLK +set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS33} [get_ports hmc7044_spi_csn ] ;# HMC7044_1_SLEN +set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVCMOS33} [get_ports hmc7044_spi_sdio ] ;# HMC7044_1_DATA + +set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS33} [get_ports hmc7044_reset ] ;# HMC7044_1_RESET +set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS33} [get_ports hmc7044_sync ] ;# HMC7044_1_SYNC + +set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVCMOS33} [get_ports hmc7044_gpio[0] ] ;# HMC7044_1_GPIO1 +set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS33} [get_ports hmc7044_gpio[1] ] ;# HMC7044_1_GPIO2 +set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS33} [get_ports hmc7044_gpio[2] ] ;# HMC7044_1_GPIO3 +set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVCMOS33} [get_ports hmc7044_gpio[3] ] ;# HMC7044_1_GPIO4 + +# AD9361-1 Interface +set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data_clk ] ;# AD9361_DATA_CLK_P +set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_frame ] ;# AD9361_RX_FRAME_P +set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[0] ] ;# AD9361_TX_00_D0_N +set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[1] ] ;# AD9361_TX_01_D0_P +set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[2] ] ;# AD9361_TX_02_D1_N +set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[3] ] ;# AD9361_TX_03_D1_P +set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[4] ] ;# AD9361_TX_04_D2_N +set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[5] ] ;# AD9361_TX_05_D2_P +set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[6] ] ;# AD9361_TX_06_D3_N +set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[7] ] ;# AD9361_TX_07_D3_P +set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[8] ] ;# AD9361_TX_08_D4_N +set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[9] ] ;# AD9361_TX_09_D4_P +set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[10] ] ;# AD9361_TX_10_D5_N +set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[11] ] ;# AD9361_TX_11_D5_P + +set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_fb_clk ] ;# AD9361_FB_CLK_P +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_frame ] ;# AD9361_TX_FRAME_P +set_property -dict {PACKAGE_PIN A2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[0] ] ;# AD9361_RX_00_D0_N +set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[1] ] ;# AD9361_RX_01_D0_P +set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[2] ] ;# AD9361_RX_02_D1_N +set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[3] ] ;# AD9361_RX_03_D1_P +set_property -dict {PACKAGE_PIN B7 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[4] ] ;# AD9361_RX_04_D2_N +set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[5] ] ;# AD9361_RX_05_D2_P +set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[6] ] ;# AD9361_RX_06_D3_N +set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[7] ] ;# AD9361_RX_07_D3_P +set_property -dict {PACKAGE_PIN A7 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[8] ] ;# AD9361_RX_08_D4_N +set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[9] ] ;# AD9361_RX_09_D4_P +set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[10] ] ;# AD9361_RX_10_D5_N +set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[11] ] ;# AD9361_RX_11_D5_P + +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_clk ] ;# AD9361_SPI_CLK +set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_csn ] ;# AD9361_SPI_ENB +set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_mosi ] ;# AD9361_SPI_DI +set_property -dict {PACKAGE_PIN D14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_miso ] ;# AD9361_SPI_DO + +set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_reset_b ] ;# AD9361_RESETB +set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_en_agc ] ;# AD9361_EN_AGC +set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_enable ] ;# AD9361_ENABLE +set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_txnrx ] ;# AD9361_TXNRX + +set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[0] ] ;# AD9361_CTRL_IN0 +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[1] ] ;# AD9361_CTRL_IN1 +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[2] ] ;# AD9361_CTRL_IN2 +set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[3] ] ;# AD9361_CTRL_IN3 + +set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[0] ] ;# AD9361_CTRL_OUT0 +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[1] ] ;# AD9361_CTRL_OUT1 +set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[2] ] ;# AD9361_CTRL_OUT2 +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[3] ] ;# AD9361_CTRL_OUT3 +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[4] ] ;# AD9361_CTRL_OUT4 +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[5] ] ;# AD9361_CTRL_OUT5 +set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[6] ] ;# AD9361_CTRL_OUT6 +set_property -dict {PACKAGE_PIN M12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[7] ] ;# AD9361_CTRL_OUT7 + +# AD9361-2 Interface +set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data_clk ] ;# B_AD9361_DATA_CLK_P +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_frame ] ;# B_AD9361_RX_FRAME_P +set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[0] ] ;# B_AD9361_TX_00_D0_N +set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[1] ] ;# B_AD9361_TX_01_D0_P +set_property -dict {PACKAGE_PIN H3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[2] ] ;# B_AD9361_TX_02_D1_N +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[3] ] ;# B_AD9361_TX_03_D1_P +set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[4] ] ;# B_AD9361_TX_04_D2_N +set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[5] ] ;# B_AD9361_TX_05_D2_P +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[6] ] ;# B_AD9361_TX_06_D3_N +set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[7] ] ;# B_AD9361_TX_07_D3_P +set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[8] ] ;# B_AD9361_TX_08_D4_N +set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[9] ] ;# B_AD9361_TX_09_D4_P +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[10] ] ;# B_AD9361_TX_10_D5_N +set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[11] ] ;# B_AD9361_TX_11_D5_P + +set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_fb_clk ] ;# B_AD9361_FB_CLK_P +set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_frame ] ;# B_AD9361_TX_FRAME_P +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[0] ] ;# B_AD9361_RX_00_D0_N +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[1] ] ;# B_AD9361_RX_01_D0_P +set_property -dict {PACKAGE_PIN F2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[2] ] ;# B_AD9361_RX_02_D1_N +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[3] ] ;# B_AD9361_RX_03_D1_P +set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[4] ] ;# B_AD9361_RX_04_D2_N +set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[5] ] ;# B_AD9361_RX_05_D2_P +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[6] ] ;# B_AD9361_RX_06_D3_N +set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[7] ] ;# B_AD9361_RX_07_D3_P +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[8] ] ;# B_AD9361_RX_08_D4_N +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[9] ] ;# B_AD9361_RX_09_D4_P +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[10] ] ;# B_AD9361_RX_10_D5_N +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[11] ] ;# B_AD9361_RX_11_D5_P + +set_property -dict {PACKAGE_PIN L9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_clk ] ;# B_AD9361_SPI_CLK +set_property -dict {PACKAGE_PIN M10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_csn ] ;# B_AD9361_SPI_ENB +set_property -dict {PACKAGE_PIN L12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_mosi ] ;# B_AD9361_SPI_DI +set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_miso ] ;# B_AD9361_SPI_DO + +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_reset_b ] ;# B_AD9361_RESETB +set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18} [get_ports ad9361_2_en_agc ] ;# B_AD9361_EN_AGC +set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS18} [get_ports ad9361_2_enable ] ;# B_AD9361_ENABLE +set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_txnrx ] ;# B_AD9361_TXNRX + +set_property -dict {PACKAGE_PIN L10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[0] ] ;# B_AD9361_CTRL_IN0 +set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[1] ] ;# B_AD9361_CTRL_IN1 +set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[2] ] ;# B_AD9361_CTRL_IN2 +set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[3] ] ;# B_AD9361_CTRL_IN3 + +set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[0] ] ;# B_AD9361_CTRL_OUT0 +set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[1] ] ;# B_AD9361_CTRL_OUT1 +set_property -dict {PACKAGE_PIN K7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[2] ] ;# B_AD9361_CTRL_OUT2 +set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[3] ] ;# B_AD9361_CTRL_OUT3 +set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[4] ] ;# B_AD9361_CTRL_OUT4 +set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[5] ] ;# B_AD9361_CTRL_OUT5 +set_property -dict {PACKAGE_PIN K10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[6] ] ;# B_AD9361_CTRL_OUT6 +set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[7] ] ;# B_AD9361_CTRL_OUT7 + +# Phased-Array Control +set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVTTL } [get_ports ant_clk ] ;# ANT_CLK +set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVTTL } [get_ports ant_en ] ;# ANT_EN +set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVTTL } [get_ports ant_data ] ;# ANT_DATA +set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVTTL } [get_ports ant_tr ] ;# ANT_TR +set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVTTL } [get_ports ant_dary ] ;# ANT_DARY +set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVTTL } [get_ports ant_dout ] ;# ANT_DOUT + +# RF Synthesizer Control +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS33} [get_ports rf_standby ] ;# ANT_standby_R +set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS33} [get_ports rf_sw_pll ] ;# ANT_SW_PLL_R +set_property -dict {PACKAGE_PIN T23 IOSTANDARD LVCMOS33} [get_ports rf_t ] ;# ANT_T_R +set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS33} [get_ports rf_r ] ;# ANT_R_R +set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS33} [get_ports rf_sw_bpf ] ;# ANT_SW_BPF_R +set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS33} [get_ports rf_sclk1 ] ;# ANT_SCLK1_R +set_property -dict {PACKAGE_PIN T27 IOSTANDARD LVCMOS33} [get_ports rf_sdio1 ] ;# ANT_SDIO1_R +set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS33} [get_ports rf_cs1 ] ;# ANT_CS1_R +set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS33} [get_ports rf_ld1 ] ;# ANT_LD1_R +set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS33} [get_ports rf_sclk2 ] ;# ANT_SCLK2_R +set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS33} [get_ports rf_sdio2 ] ;# ANT_SDIO2_R +set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS33} [get_ports rf_cs2 ] ;# ANT_CS2_R +set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS33} [get_ports rf_ld2 ] ;# ANT_LD2_R +set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVCMOS33} [get_ports rf_sclk3 ] ;# ANT_SCLK3_R +set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS33} [get_ports rf_sdio3 ] ;# ANT_SDIO3_R +set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS33} [get_ports rf_cs3 ] ;# ANT_CS3_R +set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS33} [get_ports rf_ld3 ] ;# ANT_LD3_R +set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_16 ] ;# ANT_TMGC_16_R +set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_8 ] ;# ANT_TMGC_8_R +set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_4 ] ;# ANT_TMGC_4_R +set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_2 ] ;# ANT_TMGC_2_R +set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVCMOS33} [get_ports rf_tmgc_1 ] ;# ANT_TMGC_1_R +set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_16 ] ;# ANT_RMGC_16_R +set_property -dict {PACKAGE_PIN AF28 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_8 ] ;# ANT_RMGC_8_R +set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_4 ] ;# ANT_RMGC_4_R +set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_2 ] ;# ANT_RMGC_2_R +set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS33} [get_ports rf_rmgc_1 ] ;# ANT_RMGC_1_R +set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVCMOS33} [get_ports rf_enable ] ;# ANT_ENABLE_R +set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVCMOS33} [get_ports rf_sc ] ;# ANT_SC_R +set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS33} [get_ports rf_sd ] ;# ANT_SD_R +set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS33} [get_ports rf_endsyn ] ;# ANT_END/SYN_R +set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVCMOS33} [get_ports rf_sdout ] ;# ANT_SDOUT_R +set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS33} [get_ports rf_dq_wd ] ;# ANT_DQ-WD_R 15 +set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVCMOS33} [get_ports rf_sw_rx ] ;# ANT_SW_RX_R + +# Debug IO +set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports uart1_txd ] ;# UART1_TXD +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS33} [get_ports uart1_rxd ] ;# UART1_RXD +set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS33} [get_ports uart2_txd ] ;# UART2_TXD +set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS33} [get_ports uart2_rxd ] ;# UART2_RXD +set_property -dict {PACKAGE_PIN AD18 IOSTANDARD LVCMOS33} [get_ports uart3_txd ] ;# UART3_TXD +set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS33} [get_ports uart3_rxd ] ;# UART3_RXD +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports debug_io_1 ] ;# DEBUG_IO_1 +set_property -dict {PACKAGE_PIN K16 IOSTANDARD LVCMOS18} [get_ports debug_io_2 ] ;# DEBUG_IO_2 +set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVCMOS33} [get_ports debug_io_3 ] ;# DEBUG_IO_3 +set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVCMOS33} [get_ports debug_io_4 ] ;# DEBUG_IO_4 +set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVCMOS33} [get_ports debug_io_5 ] ;# DEBUG_IO_5 +set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVCMOS33} [get_ports debug_io_6 ] ;# DEBUG_IO_6 +set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVCMOS33} [get_ports debug_io_7 ] ;# DEBUG_IO_7 diff --git a/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/constrs_1/new/z7100_hmc7044_2ad9361_timing.xdc b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/constrs_1/new/z7100_hmc7044_2ad9361_timing.xdc new file mode 100644 index 0000000..8028ec4 --- /dev/null +++ b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/constrs_1/new/z7100_hmc7044_2ad9361_timing.xdc @@ -0,0 +1 @@ +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets u_clk_dist/u_ad9361_2_clk_gen/inst/clk_in1_ad9361_clk_gen_cmos_1t1r] diff --git a/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci new file mode 100644 index 0000000..372ecd0 --- /dev/null +++ b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci @@ -0,0 +1,301 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "system_bd_auto_pc_0", + "cell_name": "ps7_axi_periph/s00_couplers/auto_pc", + "component_reference": "xilinx.com:ip:axi_protocol_converter:2.1", + "ip_revision": "30", + "gen_directory": "../../../../../../duifei_cmos_1t1r.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0", + "parameters": { + "component_parameters": { + "SI_PROTOCOL": [ { "value": "AXI3", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], + "MI_PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], + "TRANSLATION_MODE": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ID_WIDTH": [ { "value": "12", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Component_Name": [ { "value": "system_bd_auto_pc_0", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ], + "C_M_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXI_PROTOCOL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_IGNORE_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_ID_WIDTH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_SUPPORTS_WRITE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_SUPPORTS_READ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TRANSLATION_MODE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z100" } ], + "PACKAGE": [ { "value": "ffg900" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "30" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../duifei_cmos_1t1r.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0" } ], + "SELECTEDSIMMODEL": [ { "value": "rtl" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2023.2.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "aclk": [ { "direction": "in" } ], + "aresetn": [ { "direction": "in" } ], + "s_axi_awid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ], + "s_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ], + "s_axi_awlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ], + "s_axi_awlock": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ], + "s_axi_awready": [ { "direction": "out" } ], + "s_axi_wid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ], + "s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ], + "s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0xF" } ], + "s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ], + "s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ], + "s_axi_wready": [ { "direction": "out" } ], + "s_axi_bid": [ { "direction": "out", "size_left": "11", "size_right": "0" } ], + "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], + "s_axi_bvalid": [ { "direction": "out" } ], + "s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ], + "s_axi_arid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ], + "s_axi_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ], + "s_axi_arlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ], + "s_axi_arlock": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_arqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_arvalid": [ { "direction": "in", "driver_value": "0x0" } ], + "s_axi_arready": [ { "direction": "out" } ], + "s_axi_rid": [ { "direction": "out", "size_left": "11", "size_right": "0" } ], + "s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], + "s_axi_rlast": [ { "direction": "out" } ], + "s_axi_rvalid": [ { "direction": "out" } ], + "s_axi_rready": [ { "direction": "in", "driver_value": "0x0" } ], + "m_axi_awaddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ], + "m_axi_awvalid": [ { "direction": "out" } ], + "m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ], + "m_axi_wdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "m_axi_wstrb": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], + "m_axi_wvalid": [ { "direction": "out" } ], + "m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ], + "m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ], + "m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ], + "m_axi_bready": [ { "direction": "out" } ], + "m_axi_araddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "m_axi_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ], + "m_axi_arvalid": [ { "direction": "out" } ], + "m_axi_arready": [ { "direction": "in", "driver_value": "0x0" } ], + "m_axi_rdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ], + "m_axi_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ], + "m_axi_rvalid": [ { "direction": "in", "driver_value": "0x0" } ], + "m_axi_rready": [ { "direction": "out" } ] + }, + "interfaces": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm:1.0", + "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "slave", + "parameters": { + "DATA_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI3", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "12", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BURST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "16", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, 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b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci @@ -0,0 +1,1288 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "system_bd_processing_system7_0_0", + "cell_name": "processing_system7", + "component_reference": "xilinx.com:ip:processing_system7:5.5", + "ip_revision": "6", + "gen_directory": "../../../../../../duifei_cmos_1t1r.gen/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0", + "parameters": { + "component_parameters": { + "PCW_DDR_RAM_BASEADDR": [ { "value": "0x00100000", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_DDR_RAM_HIGHADDR": [ { "value": "0x1FFFFFFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_UART0_BASEADDR": [ { "value": "0xE0000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_UART0_HIGHADDR": [ { "value": "0xE0000FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_UART1_BASEADDR": [ { "value": "0xE0001000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_UART1_HIGHADDR": [ { "value": "0xE0001FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_I2C0_BASEADDR": [ { "value": "0xE0004000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_I2C0_HIGHADDR": [ { "value": "0xE0004FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_I2C1_BASEADDR": [ { "value": "0xE0005000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_I2C1_HIGHADDR": [ { "value": "0xE0005FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SPI0_BASEADDR": [ { "value": "0xE0006000", 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{ + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "5" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../duifei_cmos_1t1r.gen/sources_1/bd/system_bd/ip/system_bd_xlconcat_0_0" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2023.2.1" } ], + "SYNTHESISFLOW": [ { "value": "GLOBAL" } ] + } + }, + "boundary": { + "ports": { + "In0": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0" } ], + "dout": [ { "direction": "out", "size_left": "0", "size_right": "0" } ] + } + } + } +} \ No newline at end of file diff --git a/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/bd/system_bd/system_bd.bd b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/bd/system_bd/system_bd.bd new file mode 100644 index 0000000..7d08051 --- /dev/null +++ b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/bd/system_bd/system_bd.bd @@ -0,0 +1,1087 @@ +{ + "design": { + "design_info": { + "boundary_crc": "0x5FBD1CCA8A8679DB", + "device": "xc7z100ffg900-2", + "gen_directory": "../../../../duifei_cmos_1t1r.gen/sources_1/bd/system_bd", + "name": "system_bd", + "rev_ctrl_bd_flag": "RevCtrlBdOff", + "synth_flow_mode": "Hierarchical", + "tool_version": "2023.2.1", + "validated": "true" + }, + "design_tree": { + "processing_system7": "", + "axi_spi_engine": { + "axi_spi_engine": "", + "spi_engine_execution": "" + }, + "ps7_axi_periph": { + "s00_couplers": { + "auto_pc": "" + } + }, + "rst_ps7_100M": "", + "xlconcat_irq": "" + }, + "interface_ports": { + "DDR": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:ddrx:1.0", + "vlnv": "xilinx.com:interface:ddrx_rtl:1.0", + "parameters": { + "AXI_ARBITRATION_SCHEME": { + "value": "TDM", + "value_src": "default" + }, + "BURST_LENGTH": { + "value": "8", + "value_src": "default" + }, + "CAN_DEBUG": { + "value": "false", + "value_src": "default" + }, + "CAS_LATENCY": { + "value": "11", + "value_src": "default" + }, + "CAS_WRITE_LATENCY": { + "value": "11", + "value_src": "default" + }, + "CS_ENABLED": { + "value": "true", + "value_src": "default" + }, + "DATA_MASK_ENABLED": { + "value": "true", + "value_src": "default" + }, + "DATA_WIDTH": { + "value": "8", + "value_src": "default" + }, + "MEMORY_TYPE": { + "value": "COMPONENTS", + "value_src": "default" + }, + "MEM_ADDR_MAP": { + "value": "ROW_COLUMN_BANK", + "value_src": "default" + }, + "SLOT": { + "value": "Single", + "value_src": "default" + }, + "TIMEPERIOD_PS": { + "value": "1250", + "value_src": "default" + } + }, + "port_maps": { + "CAS_N": { + "physical_name": "DDR_cas_n", + "direction": "IO" + }, + "CKE": { + "physical_name": "DDR_cke", + "direction": "IO" + }, + "CK_N": { + "physical_name": "DDR_ck_n", + "direction": "IO" + }, + "CK_P": { + "physical_name": "DDR_ck_p", + "direction": "IO" + }, + "CS_N": { + "physical_name": "DDR_cs_n", + "direction": "IO" + }, + "RESET_N": { + "physical_name": "DDR_reset_n", + "direction": "IO" + }, + "ODT": { + "physical_name": "DDR_odt", + "direction": "IO" + }, + "RAS_N": { + "physical_name": "DDR_ras_n", + "direction": "IO" + }, + "WE_N": { + "physical_name": "DDR_we_n", + "direction": "IO" + }, + "BA": { + "physical_name": "DDR_ba", + "direction": "IO", + "left": "2", + "right": "0" + }, + "ADDR": { + "physical_name": "DDR_addr", + "direction": "IO", + "left": "14", + "right": "0" + }, + "DM": { + "physical_name": "DDR_dm", + "direction": "IO", + "left": "3", + "right": "0" + }, + "DQ": { + "physical_name": "DDR_dq", + "direction": "IO", + "left": "31", + "right": "0" + }, + "DQS_N": { + "physical_name": "DDR_dqs_n", + "direction": "IO", + "left": "3", + "right": "0" + }, + "DQS_P": { + "physical_name": "DDR_dqs_p", + "direction": "IO", + "left": "3", + "right": "0" + } + } + }, + "FIXED_IO": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:display_processing_system7:fixedio:1.0", + "vlnv": "xilinx.com:display_processing_system7:fixedio_rtl:1.0", + "parameters": { + "CAN_DEBUG": { + "value": "false", + "value_src": "default" + } + }, + "port_maps": { + "MIO": { + "physical_name": "FIXED_IO_mio", + "direction": "IO", + "left": "53", + "right": "0" + }, + "DDR_VRN": { + "physical_name": "FIXED_IO_ddr_vrn", + "direction": "IO" + }, + "DDR_VRP": { + "physical_name": "FIXED_IO_ddr_vrp", + "direction": "IO" + }, + "PS_SRSTB": { + "physical_name": "FIXED_IO_ps_srstb", + "direction": "IO" + }, + "PS_CLK": { + "physical_name": "FIXED_IO_ps_clk", + "direction": "IO" + }, + "PS_PORB": { + "physical_name": "FIXED_IO_ps_porb", + "direction": "IO" + } + } + }, + "spi": { + "mode": "Master", + "vlnv_bus_definition": "analog.com:interface:spi_master:1.0", + "vlnv": "analog.com:interface:spi_master_rtl:1.0", + "port_maps": { + "SCLK": { + "physical_name": "spi_sclk", + "direction": "O" + }, + "SDI": { + "physical_name": "spi_sdi", + "direction": "I", + "left": "0", + "right": "0" + }, + "SDO": { + "physical_name": "spi_sdo", + "direction": "O" + }, + "SDO_T": { + "physical_name": "spi_sdo_t", + "direction": "O" + }, + "THREE_WIRE": { + "physical_name": "spi_three_wire", + "direction": "O" + }, + "CS": { + "physical_name": "spi_cs", + "direction": "O", + "left": "2", + "right": "0" + } + } + } + }, + "ports": { + "GPIO_O": { + "direction": "O", + "left": "47", + "right": "0" + }, + "GPIO_I": { + "direction": "I", + "left": "47", + "right": "0" + }, + "GPIO_T": { + "direction": "O", + "left": "47", + "right": "0" + }, + "spi_active": { + "direction": "O" + } + }, + "components": { + "processing_system7": { + "vlnv": "xilinx.com:ip:processing_system7:5.5", + "ip_revision": "6", + "xci_name": "system_bd_processing_system7_0_0", + "xci_path": "ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci", + "inst_hier_path": "processing_system7", + "parameters": { + "PCW_ACT_APU_PERIPHERAL_FREQMHZ": { + "value": "666.666687" + }, + "PCW_ACT_CAN_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_DCI_PERIPHERAL_FREQMHZ": { + "value": "10.158730" + }, + "PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": { + "value": "100.000000" + }, + "PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_SMC_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_SPI_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": { + "value": "200.000000" + }, + "PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_ACT_UART_PERIPHERAL_FREQMHZ": { + "value": "10.000000" + }, + "PCW_ACT_WDT_PERIPHERAL_FREQMHZ": { + "value": "111.111115" + }, + "PCW_CLK0_FREQ": { + "value": "100000000" + }, + "PCW_CLK1_FREQ": { + "value": "10000000" + }, + "PCW_CLK2_FREQ": { + "value": "10000000" + }, + "PCW_CLK3_FREQ": { + "value": "10000000" + }, + "PCW_DDR_RAM_HIGHADDR": { + "value": "0x1FFFFFFF" + }, + "PCW_EN_EMIO_CD_SDIO1": { + "value": "0" + }, + "PCW_EN_EMIO_GPIO": { + "value": "1" + }, + "PCW_EN_EMIO_SDIO1": { + "value": "0" + }, + "PCW_EN_EMIO_SPI0": { + "value": "0" + }, + "PCW_EN_EMIO_WP_SDIO1": { + "value": "0" + }, + "PCW_EN_QSPI": { + "value": "1" + }, + "PCW_EN_SDIO1": { + "value": "0" + }, + "PCW_EN_SPI0": { + "value": "0" + }, + "PCW_FPGA0_PERIPHERAL_FREQMHZ": { + "value": "100" + }, + "PCW_FPGA_FCLK0_ENABLE": { + "value": "1" + }, + "PCW_GPIO_EMIO_GPIO_ENABLE": { + "value": "1" + }, + "PCW_GPIO_EMIO_GPIO_IO": { + "value": "48" + }, + "PCW_GPIO_EMIO_GPIO_WIDTH": { + "value": "48" + }, + "PCW_IRQ_F2P_INTR": { + "value": "1" + }, + "PCW_MIO_1_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_1_PULLUP": { + "value": "enabled" + }, + "PCW_MIO_1_SLEW": { + "value": "slow" + }, + "PCW_MIO_2_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_2_SLEW": { + "value": "slow" + }, + "PCW_MIO_3_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_3_SLEW": { + "value": "slow" + }, + "PCW_MIO_4_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_4_SLEW": { + "value": "slow" + }, + "PCW_MIO_5_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_5_SLEW": { + "value": "slow" + }, + "PCW_MIO_6_IOTYPE": { + "value": "LVCMOS 3.3V" + }, + "PCW_MIO_6_SLEW": { + "value": "slow" + }, + "PCW_MIO_TREE_PERIPHERALS": { + "value": [ + "unassigned#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI", + "Flash#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned" + ] + }, + "PCW_MIO_TREE_SIGNALS": { + "value": "unassigned#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned#unassigned" + }, + "PCW_QSPI_GRP_FBCLK_ENABLE": { + "value": "0" + }, + "PCW_QSPI_GRP_IO1_ENABLE": { + "value": "0" + }, + "PCW_QSPI_GRP_SINGLE_SS_ENABLE": { + "value": "1" + }, + "PCW_QSPI_GRP_SINGLE_SS_IO": { + "value": "MIO 1 .. 6" + }, + "PCW_QSPI_GRP_SS1_ENABLE": { + "value": "0" + }, + "PCW_QSPI_PERIPHERAL_ENABLE": { + "value": "1" + }, + "PCW_QSPI_PERIPHERAL_FREQMHZ": { + "value": "200" + }, + "PCW_QSPI_QSPI_IO": { + "value": "MIO 1 .. 6" + }, + "PCW_SD1_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_SDIO_PERIPHERAL_VALID": { + "value": "0" + }, + "PCW_SINGLE_QSPI_DATA_MODE": { + "value": "x4" + }, + "PCW_SPI0_PERIPHERAL_ENABLE": { + "value": "0" + }, + "PCW_SPI_PERIPHERAL_FREQMHZ": { + "value": "166.666666" + }, + "PCW_SPI_PERIPHERAL_VALID": { + "value": "0" + }, + "PCW_UIPARAM_ACT_DDR_FREQ_MHZ": { + "value": "533.333374" + }, + "PCW_UIPARAM_DDR_BUS_WIDTH": { + "value": "16 Bit" + }, + "PCW_UIPARAM_DDR_ECC": { + "value": "Disabled" + }, + "PCW_UIPARAM_DDR_PARTNO": { + "value": "MT41J256M16 RE-125" + }, + "PCW_USE_FABRIC_INTERRUPT": { + "value": "1" + }, + "PCW_USE_M_AXI_GP0": { + "value": "1" + } + }, + "interface_ports": { + "M_AXI_GP0": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Master", + "address_space_ref": "Data", + "base_address": { + "minimum": "0x40000000", + "maximum": "0x7FFFFFFF", + "width": "32" + } + } + }, + "addressing": { + "address_spaces": { + "Data": { + "range": "4G", + "width": "32", + "local_memory_map": { + "name": "Data", + "description": "Address Space Segments", + "address_blocks": { + "segment1": { + "name": "segment1", + "display_name": "segment1", + "base_address": "0x00000000", + "range": "256K", + "width": "18", + "usage": "register" + }, + "segment2": { + "name": "segment2", + "display_name": "segment2", + "base_address": "0x00040000", + "range": "256K", + "width": "19", + "usage": "register" + }, + "segment3": { + "name": "segment3", + "display_name": "segment3", + "base_address": "0x00080000", + "range": "512K", + "width": "20", + "usage": "register" + }, + "segment4": { + "name": "segment4", + "display_name": "segment4", + "base_address": "0x00100000", + "range": "1023M", + "width": "30", + "usage": "register" + }, + "M_AXI_GP0": { + "name": "M_AXI_GP0", + "display_name": "M_AXI_GP0", + "base_address": "0x40000000", + "range": "1G", + "width": "31", + "usage": "register" + }, + "M_AXI_GP1": { + "name": "M_AXI_GP1", + "display_name": "M_AXI_GP1", + "base_address": "0x80000000", + "range": "1G", + "width": "32", + "usage": "register" + }, + "IO_Peripheral_Registers": { + "name": "IO_Peripheral_Registers", + "display_name": "IO Peripheral Registers", + "base_address": "0xE0000000", + "range": "3M", + "width": "32", + "usage": "register" + }, + "SMC_Memories": { + "name": "SMC_Memories", + "display_name": "SMC Memories", + "base_address": "0xE1000000", + "range": "80M", + "width": "32", + "usage": "register" + }, + "SLCR_Registers": { + "name": "SLCR_Registers", + "display_name": "SLCR Registers", + "base_address": "0xF8000000", + "range": "3K", + "width": "32", + "usage": "register" + }, + "PS_System_Registers": { + "name": "PS_System_Registers", + "display_name": "PS System Registers", + "base_address": "0xF8001000", + "range": "8252K", + "width": "32", + "usage": "register" + }, + "CPU_Private_Registers": { + "name": "CPU_Private_Registers", + "display_name": "CPU Private Registers", + "base_address": "0xF8900000", + "range": "6156K", + "width": "32", + "usage": "register" + }, + "segment5": { + "name": "segment5", + "display_name": "segment5", + "base_address": "0xFC000000", + "range": "32M", + "width": "32", + "usage": "register" + }, + "segment6": { + "name": "segment6", + "display_name": "segment6", + "base_address": "0xFFFC0000", + "range": "256K", + "width": "32", + "usage": "register" + } + } + } + } + } + } + }, + "axi_spi_engine": { + "interface_ports": { + "s_axi": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "spi": { + "mode": "Master", + "vlnv_bus_definition": "analog.com:interface:spi_master:1.0", + "vlnv": "analog.com:interface:spi_master_rtl:1.0" + } + }, + "ports": { + "irq": { + "direction": "O" + }, + "s_axi_aclk": { + "type": "clk", + "direction": "I" + }, + "s_axi_aresetn": { + "type": "rst", + "direction": "I" + }, + "spi_clk": { + "type": "clk", + "direction": "I" + }, + "active": { + "direction": "O" + } + }, + "components": { + "axi_spi_engine": { + "vlnv": "analog.com:user:axi_spi_engine:1.0", + "ip_revision": "1", + "xci_name": "system_bd_axi_spi_engine_0_0", + "xci_path": "ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci", + "inst_hier_path": "axi_spi_engine/axi_spi_engine" + }, + "spi_engine_execution": { + "vlnv": "analog.com:user:spi_engine_execution:1.0", + "ip_revision": "1", + "xci_name": "system_bd_spi_engine_execution_0_0", + "xci_path": "ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci", + "inst_hier_path": "axi_spi_engine/spi_engine_execution", + "parameters": { + "NUM_OF_CS": { + "value": "3" + } + } + } + }, + "interface_nets": { + "Conn1": { + "interface_ports": [ + "axi_spi_engine/s_axi", + "s_axi" + ] + }, + "Conn2": { + "interface_ports": [ + "spi_engine_execution/spi", + "spi" + ] + }, + "axi_spi_engine_spi_engine_ctrl": { + "interface_ports": [ + "axi_spi_engine/spi_engine_ctrl", + "spi_engine_execution/ctrl" + ] + } + }, + "nets": { + "axi_spi_engine_irq": { + "ports": [ + "axi_spi_engine/irq", + "irq" + ] + }, + "axi_spi_engine_spi_resetn": { + "ports": [ + "axi_spi_engine/spi_resetn", + "spi_engine_execution/resetn" + ] + }, + "s_axi_aclk_0_1": { + "ports": [ + "s_axi_aclk", + "axi_spi_engine/s_axi_aclk" + ] + }, + "s_axi_aresetn_1": { + "ports": [ + "s_axi_aresetn", + "axi_spi_engine/s_axi_aresetn" + ] + }, + "spi_clk_0_1": { + "ports": [ + "spi_clk", + "axi_spi_engine/spi_clk", + "spi_engine_execution/clk" + ] + }, + "spi_engine_execution_active": { + "ports": [ + "spi_engine_execution/active", + "active" + ] + } + } + }, + "ps7_axi_periph": { + "vlnv": "xilinx.com:ip:axi_interconnect:2.1", + "xci_path": "ip/system_bd_ps7_axi_periph_0/system_bd_ps7_axi_periph_0.xci", + "inst_hier_path": "ps7_axi_periph", + "xci_name": "system_bd_ps7_axi_periph_0", + "parameters": { + "NUM_MI": { + "value": "1" + } + }, + "interface_ports": { + "S00_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "M00_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_RESET": { + "value": "ARESETN" + } + } + }, + "ARESETN": { + "type": "rst", + "direction": "I" + }, + "S00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S00_ARESETN" + } + } + }, + "S00_ARESETN": { + "type": "rst", + "direction": "I" + }, + "M00_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M00_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M00_ARESETN" + } + } + }, + "M00_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "s00_couplers": { + "interface_ports": { + "M_AXI": { + "mode": "Master", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + }, + "S_AXI": { + "mode": "Slave", + "vlnv_bus_definition": "xilinx.com:interface:aximm:1.0", + "vlnv": "xilinx.com:interface:aximm_rtl:1.0" + } + }, + "ports": { + "M_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "M_AXI" + }, + "ASSOCIATED_RESET": { + "value": "M_ARESETN" + } + } + }, + "M_ARESETN": { + "type": "rst", + "direction": "I" + }, + "S_ACLK": { + "type": "clk", + "direction": "I", + "parameters": { + "ASSOCIATED_BUSIF": { + "value": "S_AXI" + }, + "ASSOCIATED_RESET": { + "value": "S_ARESETN" + } + } + }, + "S_ARESETN": { + "type": "rst", + "direction": "I" + } + }, + "components": { + "auto_pc": { + "vlnv": "xilinx.com:ip:axi_protocol_converter:2.1", + "ip_revision": "30", + "xci_name": "system_bd_auto_pc_0", + "xci_path": "ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci", + "inst_hier_path": "ps7_axi_periph/s00_couplers/auto_pc", + "parameters": { + "MI_PROTOCOL": { + "value": "AXI4LITE" + }, + "SI_PROTOCOL": { + "value": "AXI3" + } + }, + "interface_ports": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "Slave", + "bridges": [ + "M_AXI" + ] + } + } + } + }, + "interface_nets": { + "auto_pc_to_s00_couplers": { + "interface_ports": [ + "M_AXI", + "auto_pc/M_AXI" + ] + }, + "s00_couplers_to_auto_pc": { + "interface_ports": [ + "S_AXI", + "auto_pc/S_AXI" + ] + } + }, + "nets": { + "S_ACLK_1": { + "ports": [ + "S_ACLK", + "auto_pc/aclk" + ] + }, + "S_ARESETN_1": { + "ports": [ + "S_ARESETN", + "auto_pc/aresetn" + ] + } + } + } + }, + "interface_nets": { + "ps7_axi_periph_to_s00_couplers": { + "interface_ports": [ + "S00_AXI", + "s00_couplers/S_AXI" + ] + }, + "s00_couplers_to_ps7_axi_periph": { + "interface_ports": [ + "s00_couplers/M_AXI", + "M00_AXI" + ] + } + }, + "nets": { + "S00_ACLK_1": { + "ports": [ + "S00_ACLK", + "s00_couplers/S_ACLK" + ] + }, + "S00_ARESETN_1": { + "ports": [ + "S00_ARESETN", + "s00_couplers/S_ARESETN" + ] + }, + "ps7_axi_periph_ACLK_net": { + "ports": [ + "M00_ACLK", + "s00_couplers/M_ACLK" + ] + }, + "ps7_axi_periph_ARESETN_net": { + "ports": [ + "M00_ARESETN", + "s00_couplers/M_ARESETN" + ] + } + } + }, + "rst_ps7_100M": { + "vlnv": "xilinx.com:ip:proc_sys_reset:5.0", + "ip_revision": "14", + "xci_name": "system_bd_rst_ps7_100M_0", + "xci_path": "ip/system_bd_rst_ps7_100M_0/system_bd_rst_ps7_100M_0.xci", + "inst_hier_path": "rst_ps7_100M" + }, + "xlconcat_irq": { + "vlnv": "xilinx.com:ip:xlconcat:2.1", + "ip_revision": "5", + "xci_name": "system_bd_xlconcat_0_0", + "xci_path": "ip/system_bd_xlconcat_0_0/system_bd_xlconcat_0_0.xci", + "inst_hier_path": "xlconcat_irq", + "parameters": { + "NUM_PORTS": { + "value": "1" + } + } + } + }, + "interface_nets": { + "axi_spi_engine_spi": { + "interface_ports": [ + "spi", + "axi_spi_engine/spi" + ] + }, + "processing_system7_0_DDR": { + "interface_ports": [ + "DDR", + "processing_system7/DDR" + ] + }, + "processing_system7_0_FIXED_IO": { + "interface_ports": [ + "FIXED_IO", + "processing_system7/FIXED_IO" + ] + }, + "processing_system7_M_AXI_GP0": { + "interface_ports": [ + "processing_system7/M_AXI_GP0", + "ps7_axi_periph/S00_AXI" + ] + }, + "ps7_axi_periph_M00_AXI": { + "interface_ports": [ + "ps7_axi_periph/M00_AXI", + "axi_spi_engine/s_axi" + ] + } + }, + "nets": { + "GPIO_I_0_1": { + "ports": [ + "GPIO_I", + "processing_system7/GPIO_I" + ] + }, + "axi_spi_engine_active": { + "ports": [ + "axi_spi_engine/active", + "spi_active" + ] + }, + "axi_spi_engine_irq": { + "ports": [ + "axi_spi_engine/irq", + "xlconcat_irq/In0" + ] + }, + "processing_system7_0_GPIO_O": { + "ports": [ + "processing_system7/GPIO_O", + "GPIO_O" + ] + }, + "processing_system7_0_GPIO_T": { + "ports": [ + "processing_system7/GPIO_T", + "GPIO_T" + ] + }, + "processing_system7_FCLK_CLK0": { + "ports": [ + "processing_system7/FCLK_CLK0", + "processing_system7/M_AXI_GP0_ACLK", + "ps7_axi_periph/S00_ACLK", + "rst_ps7_100M/slowest_sync_clk", + "axi_spi_engine/s_axi_aclk", + "ps7_axi_periph/M00_ACLK", + "ps7_axi_periph/ACLK", + "axi_spi_engine/spi_clk" + ] + }, + "processing_system7_FCLK_RESET0_N": { + "ports": [ + "processing_system7/FCLK_RESET0_N", + "rst_ps7_100M/ext_reset_in" + ] + }, + "rst_ps7_100M_peripheral_aresetn": { + "ports": [ + "rst_ps7_100M/peripheral_aresetn", + "ps7_axi_periph/S00_ARESETN", + "axi_spi_engine/s_axi_aresetn", + "ps7_axi_periph/M00_ARESETN", + "ps7_axi_periph/ARESETN" + ] + }, + "xlconcat_irq_dout": { + "ports": [ + "xlconcat_irq/dout", + "processing_system7/IRQ_F2P" + ] + } + }, + "addressing": { + "/processing_system7": { + "address_spaces": { + "Data": { + "segments": { + "SEG_axi_spi_engine_axi_lite": { + "address_block": "/axi_spi_engine/axi_spi_engine/s_axi/axi_lite", + "offset": "0x43C00000", + "range": "64K" + } + } + } + } + } + } + } +} \ No newline at end of file diff --git a/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/bd/system_bd/system_bd.bda b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/bd/system_bd/system_bd.bda new file mode 100644 index 0000000..c4216d3 --- /dev/null +++ b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/bd/system_bd/system_bd.bda @@ -0,0 +1,226 @@ +{ + "graphjs": { + "version": "1.0", + "keys": [ + { + "abrv": "VH", + "name": "vert_hid", + "type": "int", + "for": "node" + }, + { + "abrv": "VM", + "name": "vert_name", + "type": "string", + "for": "node" + }, + { + "abrv": "VT", + "name": "vert_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BA", + "name": "base_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "HA", + "name": "high_addr", + "type": "string", + "for": "node" + }, + { + "abrv": "BP", + "name": "base_param", + "type": "string", + "for": "node" + }, + { + "abrv": "HP", + "name": "high_param", + "type": "string", + "for": "node" + }, + { + "abrv": "MA", + "name": "master_addrspace", + "type": "string", + "for": "node" + }, + { + "abrv": "MX", + "name": "master_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "MI", + "name": "master_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MS", + "name": "master_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "MV", + "name": "master_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "SX", + "name": "slave_instance", + "type": "string", + "for": "node" + }, + { + "abrv": "SI", + "name": "slave_interface", + "type": "string", + "for": "node" + }, + { + "abrv": "MM", + "name": "slave_memmap", + "type": "string", + "for": "node" + }, + { + "abrv": "SS", + "name": "slave_segment", + "type": "string", + "for": "node" + }, + { + "abrv": "SV", + "name": "slave_vlnv", + "type": "string", + "for": "node" + }, + { + "abrv": "TM", + "name": "memory_type", + "type": "string", + "for": "node" + }, + { + "abrv": "TU", + "name": "usage_type", + "type": "string", + "for": "node" + }, + { + "abrv": "LT", + "name": "lock_type", + "type": "string", + "for": "node" + }, + { + "abrv": "BT", + "name": "boot_type", + "type": "string", + "for": "node" + }, + { + "abrv": "EH", + "name": "edge_hid", + "type": "int", + "for": "edge" + } + ], + "vertice_type_order": [ + { + "abrv": "BC", + "desc": "Block Container" + }, + { + "abrv": "PR", + "desc": "Parital Reference" + }, + { + "abrv": "VR", + "desc": "Variant" + }, + { + "abrv": "PM", + "desc": "Variant Permutations" + }, + { + "abrv": "CX", + "desc": "Boundary Connection" + }, + { + "abrv": "AC", + "desc": "Assignment Coordinate" + }, + { + "abrv": "ACE", + "desc": "Excluded Assign Coordinate" + }, + { + "abrv": "APX", + "desc": "Boundary Aperture" + }, + { + "abrv": "CIP", + "desc": "High level Processing System" + } + ], + "vertices": { + "V0": { + "VM": "system_bd", + "VT": "BC" + }, + "V1": { + "VH": "2", + "VM": "system_bd", + "VT": "VR" + }, + "V2": { + "VH": "2", + "VT": "PM", + "TU": "active" + }, + "V3": { + "VT": "AC", + "BA": "0x43C00000", + "HA": "0x43C0FFFF", + "BP": "C_BASEADDR", + "HP": "C_HIGHADDR", + "MA": "Data", + "MX": "/processing_system7", + "MI": "M_AXI_GP0", + "MS": "SEG_axi_spi_engine_axi_lite", + "MV": "xilinx.com:ip:processing_system7:5.5", + "SX": "/axi_spi_engine/axi_spi_engine", + "SI": "s_axi", + "SS": "axi_lite", + "SV": "analog.com:user:axi_spi_engine:1.0", + "TM": "both", + "TU": "register" + } + }, + "edges": [ + { + "src": "V0", + "trg": "V1" + }, + { + "src": "V1", + "trg": "V2" + }, + { + "src": "V3", + "trg": "V2", + "EH": "2" + } + ] + } +} diff --git a/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui new file mode 100644 index 0000000..e3a180c --- /dev/null +++ b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui @@ -0,0 +1,41 @@ +{ + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.0", + "Default View_TopLeft":"-393,-47", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS +# -string -flagsOSRD +preplace port DDR -pg 1 -lvl 3 -x 870 -y 180 -defaultsOSRD +preplace port FIXED_IO -pg 1 -lvl 3 -x 870 -y 200 -defaultsOSRD +preplace port spi -pg 1 -lvl 3 -x 870 -y 590 -defaultsOSRD +preplace port port-id_spi_active -pg 1 -lvl 3 -x 870 -y 630 -defaultsOSRD +preplace portBus GPIO_O -pg 1 -lvl 3 -x 870 -y 140 -defaultsOSRD +preplace portBus GPIO_I -pg 1 -lvl 3 -x 870 -y 120 -defaultsOSRD -right +preplace portBus GPIO_T -pg 1 -lvl 3 -x 870 -y 160 -defaultsOSRD +preplace inst processing_system7 -pg 1 -lvl 1 -x 270 -y 180 -defaultsOSRD +preplace inst axi_spi_engine -pg 1 -lvl 1 -x 270 -y 610 -defaultsOSRD +preplace inst ps7_axi_periph -pg 1 -lvl 1 -x 270 -y 420 -defaultsOSRD +preplace inst rst_ps7_100M -pg 1 -lvl 2 -x 670 -y 300 -defaultsOSRD +preplace inst xlconcat_irq -pg 1 -lvl 2 -x 670 -y 530 -defaultsOSRD -orient R180 +preplace netloc GPIO_I_0_1 1 1 2 N 120 N +preplace netloc axi_spi_engine_active 1 1 2 NJ 630 NJ +preplace netloc axi_spi_engine_irq 1 1 2 N 610 840 +preplace netloc processing_system7_0_GPIO_O 1 1 2 N 140 N +preplace netloc processing_system7_0_GPIO_T 1 1 2 N 160 N +preplace netloc processing_system7_FCLK_CLK0 1 0 2 70 30 470 +preplace netloc processing_system7_FCLK_RESET0_N 1 1 1 460 260n +preplace netloc rst_ps7_100M_peripheral_aresetn 1 0 3 50 20 NJ 20 840 +preplace netloc xlconcat_irq_dout 1 0 2 60 700 470 +preplace netloc axi_spi_engine_spi 1 1 2 NJ 590 NJ +preplace netloc processing_system7_0_DDR 1 1 2 NJ 180 N +preplace netloc processing_system7_0_FIXED_IO 1 1 2 NJ 200 N +preplace netloc processing_system7_M_AXI_GP0 1 0 2 80 40 460J +preplace netloc ps7_axi_periph_M00_AXI 1 0 2 80 690 460J +levelinfo -pg 1 0 270 670 870 +pagesize -pg 1 -db -bbox -sgen 0 0 1020 710 +" +} +{ + "da_axi4_cnt":"1", + "da_ps7_cnt":"1" +} diff --git a/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/bd/system_bd/ui/bd_e4e34314.ui b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/bd/system_bd/ui/bd_e4e34314.ui new file mode 100644 index 0000000..53e91b2 --- /dev/null +++ b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/bd/system_bd/ui/bd_e4e34314.ui @@ -0,0 +1,30 @@ +{ + "ActiveEmotionalView":"Default View", + "Default View_ScaleFactor":"1.0", + "Default View_TopLeft":"-778,-240", + "ExpandedHierarchyInLayout":"", + "guistr":"# # String gsaved with Nlview 7.5.8 2022-09-21 7111 VDI=41 GEI=38 GUI=JA:10.0 TLS +# -string -flagsOSRD +preplace port s_axi -pg 1 -lvl 0 -x 0 -y 70 -defaultsOSRD +preplace port spi -pg 1 -lvl 2 -x 340 -y 230 -defaultsOSRD +preplace port port-id_irq -pg 1 -lvl 2 -x 340 -y 100 -defaultsOSRD +preplace port port-id_s_axi_aclk -pg 1 -lvl 0 -x 0 -y 90 -defaultsOSRD +preplace port port-id_s_axi_aresetn -pg 1 -lvl 0 -x 0 -y 110 -defaultsOSRD +preplace port port-id_spi_clk -pg 1 -lvl 0 -x 0 -y 130 -defaultsOSRD +preplace port port-id_active -pg 1 -lvl 2 -x 340 -y 250 -defaultsOSRD +preplace inst axi_spi_engine -pg 1 -lvl 1 -x 180 -y 90 -defaultsOSRD +preplace inst spi_engine_execution -pg 1 -lvl 1 -x 180 -y 240 -defaultsOSRD +preplace netloc axi_spi_engine_spi_resetn 1 0 2 40 320 320 +preplace netloc axi_spi_engine_irq 1 1 1 320J 90n +preplace netloc s_axi_aclk_0_1 1 0 1 20 80n +preplace netloc spi_clk_0_1 1 0 1 30 120n +preplace netloc spi_engine_execution_active 1 1 1 N 250 +preplace netloc s_axi_aresetn_1 1 0 1 20 100n +preplace netloc axi_spi_engine_spi_engine_ctrl 1 0 2 40 0 320 +preplace netloc Conn1 1 0 1 20 60n +preplace netloc Conn2 1 1 1 N 230 +levelinfo -pg 1 0 180 340 +pagesize -pg 1 -db -bbox -sgen -150 -10 440 350 +" +} + diff --git a/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/ip/ad9361_clk_gen_cmos_1t1r/ad9361_clk_gen_cmos_1t1r.xci b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/ip/ad9361_clk_gen_cmos_1t1r/ad9361_clk_gen_cmos_1t1r.xci new file mode 100644 index 0000000..7b248c5 --- /dev/null +++ b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/ip/ad9361_clk_gen_cmos_1t1r/ad9361_clk_gen_cmos_1t1r.xci @@ -0,0 +1,713 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "ad9361_clk_gen_cmos_1t1r", + "component_reference": "xilinx.com:ip:clk_wiz:6.0", + "ip_revision": "13", + "gen_directory": "../../../../duifei_cmos_1t1r.gen/sources_1/ip/ad9361_clk_gen_cmos_1t1r", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "ad9361_clk_gen_cmos_1t1r", "resolve_type": "user", "usage": "all" } ], + "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ], + "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ], + "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ], + "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ], + "PRIM_IN_FREQ": [ { "value": "48", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ], + "PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ], + "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ], + "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ], + "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ], + "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ], + "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ], + "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN1_JITTER_PS": [ { "value": "208.32999999999998", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_USED": [ { "value": "true", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "NUM_OUT_CLKS": [ { "value": "4", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ], + "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ], + "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ], + "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ], + "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ], + "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ], + "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ], + "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ], + "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ], + "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ], + "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ], + "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "48", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "96", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "144", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "192", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ], + "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ], + "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ], + "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ], + "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ], + "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ], + "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ], + "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ], + "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ], + "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ], + "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ], + "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ], + "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "MMCM_CLKFBOUT_MULT_F": [ { "value": "24.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKIN1_PERIOD": [ { "value": "20.833", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ], + "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "24.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT1_DIVIDE": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT2_DIVIDE": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT3_DIVIDE": [ { "value": "6", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": 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"resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ], + "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ], + "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ], + "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "JITTER_SEL": [ { "value": "No_Jitter", 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"value": "clk_in2", "resolve_type": "user", "usage": "all" } ], + "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ], + "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ], + "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN1_JITTER_PS": [ { "value": "40.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ], + "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ], + "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ], + "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ], + "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ], + "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ], + "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ], + "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ], + "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ], + "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ], + "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ], + "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ], + "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "96", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PRIM_SOURCE": [ { "value": "Differential_clock_capable_pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ], + "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ], + "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ], + "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ], + "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ], + "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ], + "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ], + "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ], + "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ], + "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ], + "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ], + "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ], + "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ], + "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "MMCM_DIVCLK_DIVIDE": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "MMCM_CLKFBOUT_MULT_F": [ { "value": "18.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKIN1_PERIOD": [ { "value": "4.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKIN2_PERIOD": [ { "value": "10.0", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ], + "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "9.375", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ], + "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ], + "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } 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"port_maps": { + "CLK_OUT1": [ { "physical_name": "clk_out1" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/ip/ant_clk_gen_stg2/ant_clk_gen_stg2.xci b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/ip/ant_clk_gen_stg2/ant_clk_gen_stg2.xci new file mode 100644 index 0000000..b1f0b97 --- /dev/null +++ b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/ip/ant_clk_gen_stg2/ant_clk_gen_stg2.xci @@ -0,0 +1,713 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "ant_clk_gen_stg2", + "component_reference": "xilinx.com:ip:clk_wiz:6.0", + "ip_revision": "13", + "gen_directory": "../../../../duifei_cmos_1t1r.gen/sources_1/ip/ant_clk_gen_stg2", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "ant_clk_gen_stg2", "resolve_type": "user", "usage": "all" } ], + "USER_CLK_FREQ0": [ { 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"CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ], + "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ], + "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ], + "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ], + "USE_RESET": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ], + "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ], + "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ], + "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ], + "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ], + "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ], + "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ], + "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ], + "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ], + "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ], + "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ], + "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "MMCM_CLKFBOUT_MULT_F": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKIN1_PERIOD": [ { "value": "10.417", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ], + "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT1_DIVIDE": [ { "value": "20", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT2_DIVIDE": [ { "value": "30", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT3_DIVIDE": [ { "value": "50", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ], + "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ], + "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ], + "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ], + "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ], + "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ], + "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ], + "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_JITTER": [ { "value": "136.435", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT1_PHASE_ERROR": [ { "value": "101.715", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_JITTER": [ { "value": "158.351", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT2_PHASE_ERROR": [ { "value": "101.715", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_JITTER": [ { "value": "172.426", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT3_PHASE_ERROR": [ { "value": "101.715", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_JITTER": [ { "value": "190.665", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT4_PHASE_ERROR": [ { "value": "101.715", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ], + "INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ], + "AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ] + }, + "model_parameters": { + "C_CLKOUT2_USED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ], + "C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ], + "C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + 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+////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/11/01 11:15:25 +// Design Name: +// Module Name: clk_dist +// Project Name: +// Target Devices: +// Tool Versions: +// Description: Clock distribution module +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module clk_dist +( + // input clocks + input clk_250m_p , // generated by ad9516, 250mhz + input clk_250m_n , + input ad9361_1_rx_data_clk, // ad9361 rx data clock, 83.3333mhz + input ad9361_2_rx_data_clk, // ad9361 rx data clock, 83.3333mhz + + // output clocks & reset + // global reset + output sys_rst , // global reset signal, active high + output ant_rst , // phased-array & rf control reset signal, active high + + // pl signal processing clock + output sys_clk , // 41.6667mhz + output sys_clk_2x , // 83.3333mhz + output sys_clk_3x , // 125mhz + output sys_clk_4x , // 166.6667mhz + output sys_clk_ld , // system main clock locked indicator + + // ad9361-1 clocks + output ad9361_1_clk , // 41.6667mhz + output ad9361_1_clk_2x , // 83.3333mhz + output ad9361_1_clk_3x , // 125mhz + output ad9361_1_clk_4x , // 166.6667mhz + output ad9361_1_clk_ld , // ad9361-1 clock group locked indicator + + // ad9361-2 clocks + output ad9361_2_clk , // 41.6667mhz + output ad9361_2_clk_2x , // 83.3333mhz + output ad9361_2_clk_3x , // 125mhz + output ad9361_2_clk_4x , // 166.6667mhz + output ad9361_2_clk_ld , // ad9361-2 clock group locked indicator + + // phased-array & rf control clocks + output clk_96m , + output clk_48m , + output clk_32m , + output clk_19p2m +); + +assign sys_clk = ad9361_1_clk ; +assign sys_clk_2x = ad9361_1_clk_2x; +assign sys_clk_3x = ad9361_1_clk_3x; +assign sys_clk_4x = ad9361_1_clk_4x; +assign sys_clk_ld = ad9361_1_clk_ld; + +assign sys_rst = ~sys_clk_ld; + +ad9361_clk_gen_cmos_1t1r u_ad9361_1_clk_gen +( + // Clock out ports + .clk_out1 (ad9361_1_clk ), // output clk_out1 + .clk_out2 (ad9361_1_clk_2x ), // output clk_out2 + .clk_out3 (ad9361_1_clk_3x ), // output clk_out3 + .clk_out4 (ad9361_1_clk_4x ), // output clk_out4 + // Status and control signals + .locked (ad9361_1_clk_ld ), // output locked + // Clock in ports + .clk_in1 (ad9361_1_rx_data_clk ) // input clk_in1 +); + +ad9361_clk_gen_cmos_1t1r u_ad9361_2_clk_gen +( + // Clock out ports + .clk_out1 (ad9361_2_clk ), // output clk_out1 + .clk_out2 (ad9361_2_clk_2x ), // output clk_out2 + .clk_out3 (ad9361_2_clk_3x ), // output clk_out3 + .clk_out4 (ad9361_2_clk_4x ), // output clk_out4 + // Status and control signals + .locked (ad9361_2_clk_ld ), // output locked + // Clock in ports + .clk_in1 (ad9361_2_rx_data_clk ) // input clk_in1 +); + +wire ant_clk_stg1_96m; +wire ant_clk_stg1_ld; +wire ant_clk_stg2_ld; + +assign ant_rst = ~ant_clk_stg2_ld; + +ant_clk_gen_stg1 u_ant_clk_gen_stg1 +( + // Clock out ports + .clk_out1 (ant_clk_stg1_96m ), // output clk_out1 + // Status and control signals + .locked (ant_clk_stg1_ld ), // output locked + // Clock in ports + .clk_in1_p (clk_250m_p ), // input clk_in1_p + .clk_in1_n (clk_250m_n ) // input clk_in1_n +); + +ant_clk_gen_stg2 u_ant_clk_gen_stg2 +( + // Clock out ports + .clk_out1 (clk_96m ), // output clk_out1 + .clk_out2 (clk_48m ), // output clk_out2 + .clk_out3 (clk_32m ), // output clk_out3 + .clk_out4 (clk_19p2m ), // output clk_out4 + // Status and control signals + .locked (ant_clk_stg2_ld ), // output locked + // Clock in ports + .clk_in1 (ant_clk_stg1_96m ) // input clk_in1 +); + +endmodule diff --git a/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/new/system_top.v b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/new/system_top.v new file mode 100644 index 0000000..9a29566 --- /dev/null +++ b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/sources_1/new/system_top.v @@ -0,0 +1,519 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2021/12/14 15:54:11 +// Design Name: +// Module Name: system_top +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module system_top +( + /*************************************************************************** + * Contents + * 01. Clocks + * 02. HMC7044 Interface + * 03. AD9361-1 Interface + * 04. AD9361-2 Interface + * 05. Phased-Array Control + * 06. RF Synthesizer Control + * 07. Debug IO + * 08. DDR and Fixed-io (Do NOT Modify) + **************************************************************************/ + + // ************************************************************************* + // ******************************** Clocks ********************************* + // ************************************************************************* + // fpga logic clock + input clk_250m_p , // generated by hmc7044, 250mhz + input clk_250m_n , + // ad9361 buffered clock + input ad9361_1_buffer_clk , // derived from ad9361 input clock + input ad9361_2_buffer_clk , // derived from ad9361 input clock + // ************************************************************************* + // *************************** HMC7044 Interface *************************** + // ************************************************************************* + // spi interface + output hmc7044_spi_clk , + output hmc7044_spi_csn , + inout hmc7044_spi_sdio , + // control signals + output hmc7044_reset , // hmc7044 active-high reset signal, set to 0 in normal operation + output hmc7044_sync , // hmc7044 multichip synchronization signal, set to 0 if not used + // gpio + inout [ 3:0] hmc7044_gpio , + // ************************************************************************* + // ************************** AD9361-1 Interface *************************** + // ************************************************************************* + // rx data (rx channels are tied to ground physically) + input ad9361_1_rx_data_clk, // ad9361 rx data clock, 96mhz + input ad9361_1_rx_frame , + input [11:0] ad9361_1_rx_data , + // tx data + output ad9361_1_tx_fb_clk , + output ad9361_1_tx_frame , + output [11:0] ad9361_1_tx_data , + // spi interface + output ad9361_1_spi_clk , + output ad9361_1_spi_csn , + output ad9361_1_spi_mosi , + input ad9361_1_spi_miso , + // control signals + output ad9361_1_reset_b , // ad9361 active-low reset control + output ad9361_1_en_agc , // ad9361 manual agc control + output ad9361_1_enable , // ad9361 enable state machine pin control (spi control is also allowed) + output ad9361_1_txnrx , // ad9361 enable state machine pin control (spi control is also allowed) + input [ 3:0] ad9361_1_ctrl_in , + output [ 7:0] ad9361_1_ctrl_out , + // ************************************************************************* + // ************************** AD9361-2 Interface *************************** + // ************************************************************************* + // rx data (rx channels are tied to ground physically) + input ad9361_2_rx_data_clk, + input ad9361_2_rx_frame , + input [11:0] ad9361_2_rx_data , + // tx data + output ad9361_2_tx_fb_clk , + output ad9361_2_tx_frame , + output [11:0] ad9361_2_tx_data , + // spi interface + output ad9361_2_spi_clk , + output ad9361_2_spi_csn , + output ad9361_2_spi_mosi , + input ad9361_2_spi_miso , + // control signals + output ad9361_2_reset_b , // ad9361 active-low reset control + output ad9361_2_en_agc , // ad9361 manual agc control + output ad9361_2_enable , // ad9361 enable state machine pin control (spi control is also allowed) + output ad9361_2_txnrx , // ad9361 enable state machine pin control (spi control is also allowed) + input [ 3:0] ad9361_2_ctrl_in , + output [ 7:0] ad9361_2_ctrl_out , + // ************************************************************************* + // ************************* Phased-Array Control ************************** + // ************************************************************************* + output ant_clk , + output ant_en , + output ant_data , + output ant_tr , + output ant_dary , + input ant_dout , + // ************************************************************************* + // ************************ RF Synthesizer Control ************************* + // ************************************************************************* + output rf_standby , + output rf_sw_pll , + output rf_t , + output rf_r , + output rf_sw_bpf , + output rf_sclk1 , + output rf_sdio1 , + output rf_cs1 , + input rf_ld1 , + output rf_sclk2 , + output rf_sdio2 , + output rf_cs2 , + input rf_ld2 , + output rf_sclk3 , + output rf_sdio3 , + output rf_cs3 , + input rf_ld3 , + output rf_tmgc_16 , + output rf_tmgc_8 , + output rf_tmgc_4 , + output rf_tmgc_2 , + output rf_tmgc_1 , + output rf_rmgc_16 , + output rf_rmgc_8 , + output rf_rmgc_4 , + output rf_rmgc_2 , + output rf_rmgc_1 , + output rf_enable , + output rf_sc , + output rf_sd , + output rf_endsyn , + input rf_sdout , + inout rf_dq_wd , + output rf_sw_rx , + // ************************************************************************* + // ******************************* Debug IO ******************************** + // ************************************************************************* + // 3.3v ports + output uart1_txd , + input uart1_rxd , + output uart2_txd , + input uart2_rxd , + output uart3_txd , + input uart3_rxd , + // 1.8v ports + inout debug_io_1 , + inout debug_io_2 , + // 3.3v ports + inout debug_io_3 , + inout debug_io_4 , + inout debug_io_5 , + inout debug_io_6 , + inout debug_io_7 , + // ************************************************************************* + // ******************* DDR and Fixed-io (Do NOT Modify) ******************** + // ************************************************************************* + // ddr + inout [14:0] ddr_addr , + inout [ 2:0] ddr_ba , + inout ddr_cas_n , + inout ddr_ck_n , + inout ddr_ck_p , + inout ddr_cke , + inout ddr_cs_n , + inout [ 3:0] ddr_dm , + inout [31:0] ddr_dq , + inout [ 3:0] ddr_dqs_n , + inout [ 3:0] ddr_dqs_p , + inout ddr_odt , + inout ddr_ras_n , + inout ddr_reset_n , + inout ddr_we_n , + // fixed-io + inout fixed_io_ddr_vrn , + inout fixed_io_ddr_vrp , + inout [53:0] fixed_io_mio , + inout fixed_io_ps_clk , + inout fixed_io_ps_porb , + inout fixed_io_ps_srstb +); + + +//////////////////////////////////////////////////////////////////////////////// +/////////////////////////// System Clock Generation //////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// global reset +wire sys_rst ; // global reset signal, active high +wire ant_rst ; // phased-array & rf control reset signal, active high + +// pl signal processing clock +wire sys_clk ; // 48MHz 41.6667MHz +wire sys_clk_2x ; // 96MHz 83.3333MHz +wire sys_clk_3x ; // 144MHz 125MHz +wire sys_clk_4x ; // 192MHz 166.6667MHz +wire sys_clk_ld ; // system main clock locked indicator + +// ad9361-1 clocks +wire ad9361_1_clk ; // 48MHz 41.6667MHz +wire ad9361_1_clk_2x ; // 96MHz 83.3333MHz +wire ad9361_1_clk_3x ; // 144MHz 125MHz +wire ad9361_1_clk_4x ; // 192MHz 166.6667MHz +wire ad9361_1_clk_ld ; // ad9361-1 clock group locked indicator + +// ad9361-2 clocks +wire ad9361_2_clk ; // 48MHz 41.6667MHz +wire ad9361_2_clk_2x ; // 96MHz 83.3333MHz +wire ad9361_2_clk_3x ; // 144MHz 125MHz +wire ad9361_2_clk_4x ; // 192MHz 166.6667MHz +wire ad9361_2_clk_ld ; // ad9361-2 clock group locked indicator + +// phased-array & rf control clocks +wire clk_96m ; +wire clk_48m ; +wire clk_32m ; +wire clk_19p2m ; + +clk_dist u_clk_dist +( + // input clocks + .clk_250m_p (clk_250m_p ), // generated by ad9516, 250mhz + .clk_250m_n (clk_250m_n ), + .ad9361_1_rx_data_clk(ad9361_1_rx_data_clk), // ad9361 rx data clock, 83.3333mhz + .ad9361_2_rx_data_clk(ad9361_2_rx_data_clk), // ad9361 rx data clock, 83.3333mhz + + // output clocks & reset + // global reset + .sys_rst (sys_rst ), // global reset signal, active high + .ant_rst (ant_rst ), // phased-array & rf control reset signal, active high + + // pl signal processing clock + .sys_clk (sys_clk ), // 48MHz 41.6667MHz + .sys_clk_2x (sys_clk_2x ), // 96MHz 83.3333MHz + .sys_clk_3x (sys_clk_3x ), // 144MHz 125MHz + .sys_clk_4x (sys_clk_4x ), // 192MHz 166.6667MHz + .sys_clk_ld (sys_clk_ld ), // system main clock locked indicator + + // ad9361-1 clocks + .ad9361_1_clk (ad9361_1_clk ), // 48MHz 41.6667MHz + .ad9361_1_clk_2x (ad9361_1_clk_2x ), // 96MHz 83.3333MHz + .ad9361_1_clk_3x (ad9361_1_clk_3x ), // 144MHz 125MHz + .ad9361_1_clk_4x (ad9361_1_clk_4x ), // 192MHz 166.6667MHz + .ad9361_1_clk_ld (ad9361_1_clk_ld ), // ad9361-1 clock group locked indicator + + // ad9361-2 clocks + .ad9361_2_clk (ad9361_2_clk ), // 48MHz 41.6667MHz + .ad9361_2_clk_2x (ad9361_2_clk_2x ), // 96MHz 83.3333MHz + .ad9361_2_clk_3x (ad9361_2_clk_3x ), // 144MHz 125MHz + .ad9361_2_clk_4x (ad9361_2_clk_4x ), // 192MHz 166.6667MHz + .ad9361_2_clk_ld (ad9361_2_clk_ld ), // ad9361-2 clock group locked indicator + + // phased-array & rf control clocks + .clk_96m (clk_96m ), + .clk_48m (clk_48m ), + .clk_32m (clk_32m ), + .clk_19p2m (clk_19p2m ) +); + + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////// Block Design Interface //////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// gpio +wire [47:0] gpio_i; +wire [47:0] gpio_o; +wire [47:0] gpio_t; +wire ad9361_rx_fifo_rst; + +assign gpio_i[47:39] = gpio_o[47:39]; + +// hmc7044 +assign hmc7044_reset = gpio_o[ 0]; // hmc7044 reset +assign hmc7044_sync = gpio_o[ 1]; // hmc7044 multichip synchronization +assign hmc7044_gpio[0] = gpio_t[ 2] ? gpio_i[ 2] : gpio_o[ 2]; +assign hmc7044_gpio[1] = gpio_t[ 3] ? gpio_i[ 3] : gpio_o[ 3]; +assign hmc7044_gpio[2] = gpio_t[ 4] ? gpio_i[ 4] : gpio_o[ 4]; +assign hmc7044_gpio[3] = gpio_t[ 5] ? gpio_i[ 5] : gpio_o[ 5]; +// ad9361-1 +assign ad9361_1_txnrx = gpio_o[ 6]; // ad9361 enable state machine control +assign ad9361_1_enable = gpio_o[ 7]; // ad9361 enable state machine control +assign ad9361_1_en_agc = gpio_o[ 8]; // ad9361 agc control +assign ad9361_1_reset_b = gpio_o[ 9]; // ad9361 reset +assign ad9361_1_ctrl_out = gpio_o[17:10]; +assign gpio_i[21:18] = ad9361_1_ctrl_in; +// ad9361-2 +assign ad9361_2_txnrx = gpio_o[22]; // ad9361 enable state machine control +assign ad9361_2_enable = gpio_o[23]; // ad9361 enable state machine control +assign ad9361_2_en_agc = gpio_o[24]; // ad9361 agc control +assign ad9361_2_reset_b = gpio_o[25]; // ad9361 reset +assign ad9361_2_ctrl_out = gpio_o[33:26]; +assign gpio_i[37:34] = ad9361_2_ctrl_in; +// ad9361 rx fifo reset +assign ad9361_rx_fifo_rst= gpio_o[38]; + +// spi interface +wire spi_sclk ; +wire [ 2:0] spi_cs ; +reg spi_sdi ; +wire spi_sdo ; +wire spi_sdo_t ; +wire spi_three_wire; +wire spi_active ; + +// hmc7044 - three-wire spi +assign hmc7044_spi_clk = spi_sclk; +assign hmc7044_spi_csn = spi_cs[0]; +assign hmc7044_spi_sdio = spi_sdo_t ? 1'bz : spi_sdo; +// ad9361-1 - three-wire spi or four-wire spi +assign ad9361_1_spi_clk = spi_sclk; +assign ad9361_1_spi_csn = spi_cs[1]; +assign ad9361_1_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo; +// ad9361-2 - three-wire spi or four-wire spi +assign ad9361_2_spi_clk = spi_sclk; +assign ad9361_2_spi_csn = spi_cs[2]; +assign ad9361_2_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo; +// select sdi signal +always @(*) begin + if (~hmc7044_spi_csn) + spi_sdi = hmc7044_spi_sdio; + else if (~ad9361_1_spi_csn) + spi_sdi = spi_three_wire ? ad9361_1_spi_mosi : ad9361_1_spi_miso; + else if (~ad9361_2_spi_csn) + spi_sdi = spi_three_wire ? ad9361_2_spi_mosi : ad9361_2_spi_miso; + else + spi_sdi = 1'bz; +end + +system_bd_wrapper u_system_bd_wrapper +( + // ddr + .DDR_addr (ddr_addr ), // inout [14:0]DDR_addr + .DDR_ba (ddr_ba ), // inout [2:0]DDR_ba + .DDR_cas_n (ddr_cas_n ), // inout DDR_cas_n + .DDR_ck_n (ddr_ck_n ), // inout DDR_ck_n + .DDR_ck_p (ddr_ck_p ), // inout DDR_ck_p + .DDR_cke (ddr_cke ), // inout DDR_cke + .DDR_cs_n (ddr_cs_n ), // inout DDR_cs_n + .DDR_dm (ddr_dm ), // inout [3:0]DDR_dm + .DDR_dq (ddr_dq ), // inout [31:0]DDR_dq + .DDR_dqs_n (ddr_dqs_n ), // inout [3:0]DDR_dqs_n + .DDR_dqs_p (ddr_dqs_p ), // inout [3:0]DDR_dqs_p + .DDR_odt (ddr_odt ), // inout DDR_odt + .DDR_ras_n (ddr_ras_n ), // inout DDR_ras_n + .DDR_reset_n (ddr_reset_n ), // inout DDR_reset_n + .DDR_we_n (ddr_we_n ), // inout DDR_we_n + + // fixed-io + .FIXED_IO_ddr_vrn (fixed_io_ddr_vrn ), // inout FIXED_IO_ddr_vrn + .FIXED_IO_ddr_vrp (fixed_io_ddr_vrp ), // inout FIXED_IO_ddr_vrp + .FIXED_IO_mio (fixed_io_mio ), // inout [53:0]FIXED_IO_mio + .FIXED_IO_ps_clk (fixed_io_ps_clk ), // inout FIXED_IO_ps_clk + .FIXED_IO_ps_porb (fixed_io_ps_porb ), // inout FIXED_IO_ps_porb + .FIXED_IO_ps_srstb (fixed_io_ps_srstb ), // inout FIXED_IO_ps_srstb + + // gpio, for control signals + .GPIO_I (gpio_i ), // input [47:0]GPIO_I_0 + .GPIO_O (gpio_o ), // output [47:0]GPIO_O_0 + .GPIO_T (gpio_t ), // output [47:0]GPIO_T_0 + + // spi interface + .spi_sclk (spi_sclk ), // output spi_sclk + .spi_cs (spi_cs ), // output [2:0]spi_cs + .spi_sdi (spi_sdi ), // input [0:0]spi_sdi + .spi_sdo (spi_sdo ), // output spi_sdo + .spi_sdo_t (spi_sdo_t ), // output spi_sdo_t + .spi_three_wire (spi_three_wire ), // output spi_three_wire + .spi_active (spi_active ) // output spi_active +); + + +//////////////////////////////////////////////////////////////////////////////// +////////////////////////////////// Tx Signal /////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// baseband signal +wire [11:0] tx_data_i; +wire [11:0] tx_data_q; + +ad9361_tx_map_cmos_single u_ad9361_tx_map +( + .clk_in (ad9361_1_clk ), // input clk_in + .clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst + + .tx_data_clk (sys_clk ), // input tx_data_clk + .tx_data_clk_rst(sys_rst ), // input tx_data_clk_rst + + .tx_data_i (tx_data_i ), // input [11:0] tx_data_i + .tx_data_q (tx_data_q ), // input [11:0] tx_data_q + .clk_out (ad9361_1_tx_fb_clk ), // output clk_out + .tx_frame (ad9361_1_tx_frame ), // output tx_frame + .tx_data (ad9361_1_tx_data ) // output [11:0] tx_data +); + +assign ad9361_2_tx_fb_clk = ad9361_1_tx_fb_clk; +// assign ad9361_2_tx_frame = ad9361_1_tx_frame ; +// assign ad9361_2_tx_data = ad9361_1_tx_data ; + +// <---------------------------------------------------------------------------> +// <--------------------- insert transmitter logic below ----------------------> +// <---------------------------------------------------------------------------> +wire [ 1:0] waveform_sel; +wire sweep_on ; +wire [31:0] freq_set ; +wire [ 1:0] iq_sel ; +wire [ 3:0] bb_rshift ; + +tx_qpsk u_tx_qpsk +( + .clk (sys_clk ), // input clk + .rst (sys_rst ), // input rst + .tx_data_i (tx_data_i ), // output [11:0] tx_data_i + .tx_data_q (tx_data_q ), // output [11:0] tx_data_q + // debug ports + .waveform_sel (waveform_sel[1:0] ), // input [ 1:0] waveform_sel + .sweep_on (sweep_on ), // input sweep_on + .freq_set (freq_set ), // input [31:0] freq_set + .iq_sel (iq_sel ), // input [ 1:0] iq_sel + .bb_rshift (bb_rshift ) // input [ 3:0] bb_rshift +); + + +//////////////////////////////////////////////////////////////////////////////// +////////////////////////////////// RF control ////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////////// +////////////////////////////////// Rx Signals ////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +wire [11:0] rx_ch1_i, rx_ch1_q; +wire [11:0] rx_ch2_i, rx_ch2_q; +wire [11:0] rx_ch3_i, rx_ch3_q; +wire [11:0] rx_ch4_i, rx_ch4_q; + +ad9361_rx_map_cmos_single u_ad9361_1_rx_map +( + .clk_in (ad9361_1_clk ), // input clk_in + .clk_in_rst (~ad9361_1_clk_ld ), // input clk_in_rst + + .rx_data_clk (sys_clk ), // input rx_data_clk + .rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst + + .rx_fifo_rst (ad9361_rx_fifo_rst ), // input rx_fifo_rst + + .rx_frame (ad9361_1_rx_frame ), // input rx_frame + .rx_data (ad9361_1_rx_data ), // input [11:0] rx_data + .rx_data_i (rx_ch1_i ), // output [11:0] rx_data_i + .rx_data_q (rx_ch1_q ) // output [11:0] rx_data_q +); + +ad9361_rx_map_cmos_single u_ad9361_2_rx_map +( + .clk_in (ad9361_2_clk ), // input clk_in + .clk_in_rst (~ad9361_2_clk_ld ), // input clk_in_rst + + .rx_data_clk (sys_clk ), // input rx_data_clk + .rx_data_clk_rst(sys_rst ), // input rx_data_clk_rst + + .rx_fifo_rst (ad9361_rx_fifo_rst ), // input rx_fifo_rst + + .rx_frame (ad9361_2_rx_frame ), // input rx_frame + .rx_data (ad9361_2_rx_data ), // input [11:0] rx_data + .rx_data_i (rx_ch2_i ), // output [11:0] rx_data_i + .rx_data_q (rx_ch2_q ) // output [11:0] rx_data_q +); + +// <---------------------------------------------------------------------------> +// <----------------------- insert receiver logic below -----------------------> +// <---------------------------------------------------------------------------> + + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////////// ILAs and VIOs ///////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +ila_2x12x131072 u_ila_tx +( + .clk (sys_clk ), // input wire clk + .probe0 (tx_data_i ), // input wire [11:0] probe0 + .probe1 (tx_data_q ) // input wire [11:0] probe1 +); + +ila_4x12x131072 u_ila_rx +( + .clk (sys_clk ), // input wire clk + .probe0 (rx_ch1_i ), // input wire [11:0] probe0 + .probe1 (rx_ch1_q ), // input wire [11:0] probe1 + .probe2 (rx_ch2_i ), // input wire [11:0] probe2 + .probe3 (rx_ch2_q ) // input wire [11:0] probe3 +); + +vio_manual_ctrl u_vio_manual_ctrl +( + .clk (sys_clk ), // input wire clk + .probe_out0 (waveform_sel ), // output wire [1 : 0] probe_out0 + .probe_out1 (sweep_on ), // output wire [0 : 0] probe_out1 + .probe_out2 (freq_set ), // output wire [31 : 0] probe_out2 + .probe_out3 (iq_sel ), // output wire [1 : 0] probe_out3 + .probe_out4 (bb_rshift ) // output wire [3 : 0] probe_out4 +); + +endmodule diff --git a/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/utils_1/imports/synth_1/system_top.dcp b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/utils_1/imports/synth_1/system_top.dcp new file mode 100755 index 0000000..a3fa6ea --- /dev/null +++ b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.srcs/utils_1/imports/synth_1/system_top.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:4245b01bbe5a506088214e581a5e680bd83c9dffc542487b1fbf521b618c0b95 +size 245297 diff --git a/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.xpr b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.xpr new file mode 100644 index 0000000..2b463aa --- /dev/null +++ b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/duifei_cmos_1t1r.xpr @@ -0,0 +1,749 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/vivado_pvt/projects/duifei/duifei_cmos_1t1r/system_top.xsa b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/system_top.xsa new file mode 100644 index 0000000..72d149f --- /dev/null +++ b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/system_top.xsa @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:82ff162184b2ea7e66d2b3e20b61ca06a27008f564737c2534de7f1cd788639c +size 777901 diff --git a/vivado_pvt/projects/duifei/duifei_cmos_1t1r/vitis/duifei_cmos_1t1r/.cproject b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/vitis/duifei_cmos_1t1r/.cproject new file mode 100644 index 0000000..bd8325a --- /dev/null +++ b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/vitis/duifei_cmos_1t1r/.cproject @@ -0,0 +1,336 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/vivado_pvt/projects/duifei/duifei_cmos_1t1r/vitis/duifei_cmos_1t1r/.gitignore b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/vitis/duifei_cmos_1t1r/.gitignore new file mode 100644 index 0000000..ac01e66 --- /dev/null +++ b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/vitis/duifei_cmos_1t1r/.gitignore @@ -0,0 +1,2 @@ +/Debug/ +/Release/ diff --git a/vivado_pvt/projects/duifei/duifei_cmos_1t1r/vitis/duifei_cmos_1t1r/.project b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/vitis/duifei_cmos_1t1r/.project new file mode 100644 index 0000000..a5152bb --- /dev/null +++ b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/vitis/duifei_cmos_1t1r/.project @@ -0,0 +1,27 @@ + + + duifei_cmos_1t1r + Created by Vitis v2023.2 + + duifei_platform + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.xilinx.sdx.sdk.core.SdkProjectNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/vivado_pvt/projects/duifei/duifei_cmos_1t1r/vitis/duifei_cmos_1t1r/_ide/bitstream/system_top.bit b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/vitis/duifei_cmos_1t1r/_ide/bitstream/system_top.bit new file mode 100644 index 0000000..3831ccb --- /dev/null +++ b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/vitis/duifei_cmos_1t1r/_ide/bitstream/system_top.bit @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:597e925fca2b67796a1fa956071457cccddcb220e9e03c2c9743cff8e77fc325 +size 17416456 diff --git a/vivado_pvt/projects/duifei/duifei_cmos_1t1r/vitis/duifei_cmos_1t1r/_ide/hwspec.checksum b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/vitis/duifei_cmos_1t1r/_ide/hwspec.checksum new file mode 100644 index 0000000..92eb972 --- /dev/null +++ b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/vitis/duifei_cmos_1t1r/_ide/hwspec.checksum @@ -0,0 +1 @@ +1040634826 \ No newline at end of file diff --git a/vivado_pvt/projects/duifei/duifei_cmos_1t1r/vitis/duifei_cmos_1t1r/_ide/psinit/ps7_init.tcl b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/vitis/duifei_cmos_1t1r/_ide/psinit/ps7_init.tcl new file mode 100644 index 0000000..3cb29ee --- /dev/null +++ b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/vitis/duifei_cmos_1t1r/_ide/psinit/ps7_init.tcl @@ -0,0 +1,643 @@ +proc ps7_pll_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x000FA240 + mask_write 0XF8000108 0x0007F000 0x00036000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF800014C 0x00003F31 0x00000901 + mask_write 0XF8000168 0x00003F31 0x00000901 + mask_write 0XF8000170 0x03F03F30 0x00300600 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01CC000D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000084 + mask_write 0XF8006004 0x0007FFFF 0x00001082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0x7FDFFFFC 0x270872D0 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000666 + mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F555555 + mask_write 0XF8006048 0x0003F03F 0x0003C008 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000000 + mask_write 0XF8006124 0x7FFFFFCF 0x40000000 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000085 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000800 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000800 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000220 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000000 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000000 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_3_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_3_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x000FA240 + mask_write 0XF8000108 0x0007F000 0x00036000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF800014C 0x00003F31 0x00000901 + mask_write 0XF8000168 0x00003F31 0x00000901 + mask_write 0XF8000170 0x03F03F30 0x00300600 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01CC000D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000084 + mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000666 + mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F555555 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000000 + mask_write 0XF8006124 0x7FFFFFFF 0x40000000 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000085 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000800 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000800 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000220 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000000 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000000 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_2_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_2_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x000FA240 + mask_write 0XF8000108 0x0007F000 0x00036000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00700F01 + mask_write 0XF800014C 0x00003F31 0x00000901 + mask_write 0XF8000168 0x00003F31 0x00000901 + mask_write 0XF8000170 0x03F03F30 0x00300600 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01CC000D + mwr -force 0XF8000004 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000084 + mask_write 0XF8006004 0x1FFFFFFF 0x00081082 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004285B + mask_write 0XF8006018 0xF7FFFFFF 0x44E458D3 + mask_write 0XF800601C 0xFFFFFFFF 0x7282BCE5 + mask_write 0XF8006020 0xFFFFFFFC 0x272872D0 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040B30 + mask_write 0XF8006034 0x13FF3FFF 0x000116D4 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000666 + mask_write 0XF8006040 0xFFFFFFFF 0xFFFF0000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F555555 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000000 + mask_write 0XF8006124 0x7FFFFFFF 0x40000000 + mask_write 0XF800612C 0x000FFFFF 0x00029000 + mask_write 0XF8006130 0x000FFFFF 0x00029000 + mask_write 0XF8006134 0x000FFFFF 0x00029000 + mask_write 0XF8006138 0x000FFFFF 0x00029000 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x00000080 + mask_write 0XF8006158 0x000FFFFF 0x00000080 + mask_write 0XF800615C 0x000FFFFF 0x00000080 + mask_write 0XF8006160 0x000FFFFF 0x00000080 + mask_write 0XF8006168 0x001FFFFF 0x000000F9 + mask_write 0XF800616C 0x001FFFFF 0x000000F9 + mask_write 0XF8006170 0x001FFFFF 0x000000F9 + mask_write 0XF8006174 0x001FFFFF 0x000000F9 + mask_write 0XF800617C 0x000FFFFF 0x000000C0 + mask_write 0XF8006180 0x000FFFFF 0x000000C0 + mask_write 0XF8006184 0x000FFFFF 0x000000C0 + mask_write 0XF8006188 0x000FFFFF 0x000000C0 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000085 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000800 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000800 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x000073FF 0x00000220 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000704 0x00003FFF 0x00001602 + mask_write 0XF8000708 0x00003FFF 0x00000602 + mask_write 0XF800070C 0x00003FFF 0x00000602 + mask_write 0XF8000710 0x00003FFF 0x00000602 + mask_write 0XF8000714 0x00003FFF 0x00000602 + mask_write 0XF8000718 0x00003FFF 0x00000602 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000000 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000000 + mwr -force 0XF8000004 0x0000767B + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 +} +proc ps7_post_config_1_0 {} { + mwr -force 0XF8000008 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mwr -force 0XF8000004 0x0000767B +} +proc ps7_debug_1_0 {} { + mwr -force 0XF8898FB0 0xC5ACCE55 + mwr -force 0XF8899FB0 0xC5ACCE55 + mwr -force 0XF8809FB0 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 666666666 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + set saved_mode [configparams force-mem-accesses] + configparams force-mem-accesses 1 + + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } + configparams force-mem-accesses $saved_mode +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/vivado_pvt/projects/duifei/duifei_cmos_1t1r/vitis/duifei_cmos_1t1r/duifei_cmos_1t1r.prj b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/vitis/duifei_cmos_1t1r/duifei_cmos_1t1r.prj new file mode 100644 index 0000000..3351906 --- /dev/null +++ b/vivado_pvt/projects/duifei/duifei_cmos_1t1r/vitis/duifei_cmos_1t1r/duifei_cmos_1t1r.prj @@ -0,0 +1,11 @@ + + + + + + + + + +