diff --git a/vivado_pvt/.gitignore b/vivado_pvt/.gitignore index 548261c..93d6bad 100644 --- a/vivado_pvt/.gitignore +++ b/vivado_pvt/.gitignore @@ -57,37 +57,37 @@ ################################################################################ # include sdk directory and everything in it -!/projects/*/*/vitis/ -!/projects/*/*/vitis/** -/projects/*/*/vitis/**.log -/projects/*/*/vitis/.analytics +!/projects/*/*/vitis*/ +!/projects/*/*/vitis*/** +/projects/*/*/vitis*/**.log +/projects/*/*/vitis*/.analytics # exclude some obscure hidden SDK folders -/projects/*/*/vitis/.metadata/ -/projects/*/*/vitis/.sdk/ -/projects/*/*/vitis/RemoteSystemsTempFiles/ -/projects/*/*/vitis/webtalk/ +/projects/*/*/vitis*/.metadata/ +/projects/*/*/vitis*/.sdk/ +/projects/*/*/vitis*/RemoteSystemsTempFiles/ +/projects/*/*/vitis*/webtalk/ # hw_platform: exclude the entire hw_platform folder, as everything can be # generated from the .hdf file. Make sure to include the bitstream in the .hdf # file when exporting from Vivado! -/projects/*/*/vitis/*_hw_platform_*/ +/projects/*/*/vitis*/*_hw_platform_*/ # BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and # Makefile, ps lib files are regenerated automatically -/projects/*/*/vitis/*_bsp/* -!/projects/*/*/vitis/*_bsp/*.cproject -!/projects/*/*/vitis/*_bsp/*.project -!/projects/*/*/vitis/*_bsp/*.sdkproject -!/projects/*/*/vitis/*_bsp/system.mss -!/projects/*/*/vitis/*_bsp/Makefile +/projects/*/*/vitis*/*_bsp/* +!/projects/*/*/vitis*/*_bsp/*.cproject +!/projects/*/*/vitis*/*_bsp/*.project +!/projects/*/*/vitis*/*_bsp/*.sdkproject +!/projects/*/*/vitis*/*_bsp/system.mss +!/projects/*/*/vitis*/*_bsp/Makefile # Application: ignored file patterns, exclude Debug & Release folders -/projects/*/*/vitis/**/*.o -/projects/*/*/vitis/**/*.d -/projects/*/*/vitis/**/*.a -/projects/*/*/vitis/*/Debug/ -/projects/*/*/vitis/*/Release/ +/projects/*/*/vitis*/**/*.o +/projects/*/*/vitis*/**/*.d +/projects/*/*/vitis*/**/*.a +/projects/*/*/vitis*/*/Debug/ +/projects/*/*/vitis*/*/Release/ ################################################################################ diff --git a/vivado_pvt/projects/dx_sig/dx_sig_basic/README.md b/vivado_pvt/projects/dx_sig/dx_sig_basic/README.md new file mode 100644 index 0000000..b88c9d3 --- /dev/null +++ b/vivado_pvt/projects/dx_sig/dx_sig_basic/README.md @@ -0,0 +1,47 @@ +# README.md + +> Board: DX_2Z7100_AD9528_2AD9361_V1.0 +> +> Device: xc7z100ffg900-2 (U1), ad9528 (U7), ad9361 (u8), ad9361 (u9) +> +> Archiver: Josh Gao + +## 2024-09-26 + +- PL 增加编译选项，可以在 `system_top.v` 中定义 `AD9361_1_2T2R` 和 `AD9361_2_2T2R` 来启用 2T2R 时序，默认设置为 1T1R 模式。 + +- PL 的时钟基频改为 60 MHz，考虑到 GW 采样率为 56 Msps；但是可能造成 TT 工作时钟过快，需要使用时进行相应调整。 + +- PL 更改部分数据端口的命名。 + +- PS 按照最新的对飞 PS 架构进行修改，需要 Include `include` 文件夹。 + +- 修改 AD9361 的输入时钟为 40 MHz，二倍频接近 80 MHz 可以获得更好性能。 + +- 两片 AD9361 的频点分别按照 TT 和 GW 修改，均仅启用一个收发通道。 + +- 测试发送 EVM 约为 2%。 + +## 2024-09-12 + +1. 使用 PS 配置 AD9528 和两片 AD9361。 + +2. AD9528 相关 + + - 使用板上 50 MHz 晶振同时供给 VCO 和 REFA。 + + - AD9361 时钟为 25 MHz，其他时钟均为 200 MHz。 + +3. AD9361 配置相关 + + - 默认启用 Rx2A 和 Tx2A，因此接收通道仅 `rx_ch2_i/q` 和 `rx_ch4_i/q` 有数据，具体请结合原理图。 + + - 使用 25 MHz 时钟输入，采样率为 48 Msps，发送频率为 4125 MHz，接收频率为 125 MHz。 + +4. PL 相关 + + - PL 信号处理时钟 `sys_clk` 在 Clock Wizard 中为 50 MHz，但实际由 AD9361 输入随路时钟生成，频率为 48 MHz。 + +## 2024-09-11 + +- 初始版本，AD9361 使用 2T2R 模式。 diff --git a/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.runs/impl_1/debug_nets.ltx b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.runs/impl_1/debug_nets.ltx new file mode 100644 index 0000000..92414cb --- /dev/null +++ b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.runs/impl_1/debug_nets.ltx @@ -0,0 +1,796 @@ +{ + "ltx_root": { + "version": 4, + "minor": 0, + "ltx_data": [ + { + "name": "EDA_PROBESET", + "active": true, + "debug_cores": [ + { + "type": "XSDB_V3", + "name": "dbg_hub", + "spec": "labtools_xsdbm_v3", + "clk_input_freq_hz": "59998799" + }, + { + "type": "ILA_V3", + "name": "u_ila_trx", + "spec": "labtools_ila_v6", + "ipName": "ila", + "core_location": { + "user_chain": 1, + "slave_index": 0, + "bscan_switch_index": 0 + }, + "uuid": "B4AD3E48EFE85668933E662B3D102FF2", + "pins": [ + { + "name": "probe0", + "id": 0, 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+ { + "name": "tx_data_i[10]" + }, + { + "name": "tx_data_i[9]" + }, + { + "name": "tx_data_i[8]" + }, + { + "name": "tx_data_i[7]" + }, + { + "name": "tx_data_i[6]" + }, + { + "name": "tx_data_i[5]" + }, + { + "name": "tx_data_i[4]" + }, + { + "name": "tx_data_i[3]" + }, + { + "name": "tx_data_i[2]" + }, + { + "name": "tx_data_i[1]" + }, + { + "name": "tx_data_i[0]" + } + ] + } + ] + }, + { + "name": "probe1", + "id": 1, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 1, + "nets": [ + { + "name": "tx_data_q", + "isBus": true, + "subnets": [ + { + "name": "tx_data_q[11]" + }, + { + "name": "tx_data_q[10]" + }, + { + "name": "tx_data_q[9]" + }, + { + "name": "tx_data_q[8]" + }, + { + "name": "tx_data_q[7]" + }, + { + "name": "tx_data_q[6]" + }, + { + "name": "tx_data_q[5]" + }, + { + "name": "tx_data_q[4]" + }, + { + "name": "tx_data_q[3]" + }, + { + "name": "tx_data_q[2]" + }, + { + "name": "tx_data_q[1]" + }, + { + "name": "tx_data_q[0]" + } + ] + } + ] + }, + { + "name": "probe2", + "id": 2, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 2, + "nets": [ + { + "name": "rx1_ch1_i", + "isBus": true, + "subnets": [ + { + "name": "rx1_ch1_i[11]" + }, + { + "name": "rx1_ch1_i[10]" + }, + { + "name": "rx1_ch1_i[9]" + }, + { + "name": "rx1_ch1_i[8]" + }, + { + "name": "rx1_ch1_i[7]" + }, + { + "name": "rx1_ch1_i[6]" + }, + { + "name": "rx1_ch1_i[5]" + }, + { + "name": "rx1_ch1_i[4]" + }, + { + "name": "rx1_ch1_i[3]" + }, + { + "name": "rx1_ch1_i[2]" + }, + { + "name": "rx1_ch1_i[1]" + }, + { + "name": "rx1_ch1_i[0]" + } + ] + } + ] + }, + { + "name": "probe3", + "id": 3, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 3, + "nets": [ + { + "name": "rx1_ch1_q", + "isBus": true, + "subnets": [ + { + "name": "rx1_ch1_q[11]" + }, + { + "name": "rx1_ch1_q[10]" + }, + { + "name": "rx1_ch1_q[9]" + }, + { + "name": "rx1_ch1_q[8]" + }, + { + "name": "rx1_ch1_q[7]" + }, + { + "name": "rx1_ch1_q[6]" + }, + { + "name": "rx1_ch1_q[5]" + }, + { + "name": "rx1_ch1_q[4]" + }, + { + "name": "rx1_ch1_q[3]" + }, + { + "name": "rx1_ch1_q[2]" + }, + { + "name": "rx1_ch1_q[1]" + }, + { + "name": "rx1_ch1_q[0]" + } + ] + } + ] + }, + { + "name": "probe4", + "id": 4, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 4, + "nets": [ + { + "name": "rx1_ch2_i", + "isBus": true, + "subnets": [ + { + "name": "rx1_ch2_i[11]" + }, + { + "name": "rx1_ch2_i[10]" + }, + { + "name": "rx1_ch2_i[9]" + }, + { + "name": "rx1_ch2_i[8]" + }, + { + "name": "rx1_ch2_i[7]" + }, + { + "name": "rx1_ch2_i[6]" + }, + { + "name": "rx1_ch2_i[5]" + }, + { + "name": "rx1_ch2_i[4]" + }, + { + "name": "rx1_ch2_i[3]" + }, + { + "name": "rx1_ch2_i[2]" + }, + { + "name": "rx1_ch2_i[1]" + }, + { + "name": "rx1_ch2_i[0]" + } + ] + } + ] + }, + { + "name": "probe5", + "id": 5, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 5, + "nets": [ + { + "name": "rx1_ch2_q", + "isBus": true, + "subnets": [ + { + "name": "rx1_ch2_q[11]" + }, + { + "name": "rx1_ch2_q[10]" + }, + { + "name": "rx1_ch2_q[9]" + }, + { + "name": "rx1_ch2_q[8]" + }, + { + "name": "rx1_ch2_q[7]" + }, + { + "name": "rx1_ch2_q[6]" + }, + { + "name": "rx1_ch2_q[5]" + }, + { + "name": "rx1_ch2_q[4]" + }, + { + "name": "rx1_ch2_q[3]" + }, + { + "name": "rx1_ch2_q[2]" + }, + { + "name": "rx1_ch2_q[1]" + }, + { + "name": "rx1_ch2_q[0]" + } + ] + } + ] + }, + { + "name": "probe6", + "id": 6, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 6, + "nets": [ + { + "name": "rx2_ch1_i", + "isBus": true, + "subnets": [ + { + "name": "rx2_ch1_i[11]" + }, + { + "name": "rx2_ch1_i[10]" + }, + { + "name": "rx2_ch1_i[9]" + }, + { + "name": "rx2_ch1_i[8]" + }, + { + "name": "rx2_ch1_i[7]" + }, + { + "name": "rx2_ch1_i[6]" + }, + { + "name": "rx2_ch1_i[5]" + }, + { + "name": "rx2_ch1_i[4]" + }, + { + "name": "rx2_ch1_i[3]" + }, + { + "name": "rx2_ch1_i[2]" + }, + { + "name": "rx2_ch1_i[1]" + }, + { + "name": "rx2_ch1_i[0]" + } + ] + } + ] + }, + { + "name": "probe7", + "id": 7, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 7, + "nets": [ + { + "name": "rx2_ch1_q", + "isBus": true, + "subnets": [ + { + "name": "rx2_ch1_q[11]" + }, + { + "name": "rx2_ch1_q[10]" + }, + { + "name": "rx2_ch1_q[9]" + }, + { + "name": "rx2_ch1_q[8]" + }, + { + "name": "rx2_ch1_q[7]" + }, + { + "name": "rx2_ch1_q[6]" + }, + { + "name": "rx2_ch1_q[5]" + }, + { + "name": "rx2_ch1_q[4]" + }, + { + "name": "rx2_ch1_q[3]" + }, + { + "name": "rx2_ch1_q[2]" + }, + { + "name": "rx2_ch1_q[1]" + }, + { + "name": "rx2_ch1_q[0]" + } + ] + } + ] + }, + { + "name": "probe8", + "id": 8, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 8, + "nets": [ + { + "name": "rx2_ch2_i", + "isBus": true, + "subnets": [ + { + "name": "rx2_ch2_i[11]" + }, + { + "name": "rx2_ch2_i[10]" + }, + { + "name": "rx2_ch2_i[9]" + }, + { + "name": "rx2_ch2_i[8]" + }, + { + "name": "rx2_ch2_i[7]" + }, + { + "name": "rx2_ch2_i[6]" + }, + { + "name": "rx2_ch2_i[5]" + }, + { + "name": "rx2_ch2_i[4]" + }, + { + "name": "rx2_ch2_i[3]" + }, + { + "name": "rx2_ch2_i[2]" + }, + { + "name": "rx2_ch2_i[1]" + }, + { + "name": "rx2_ch2_i[0]" + } + ] + } + ] + }, + { + "name": "probe9", + "id": 9, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 9, + "nets": [ + { + "name": "rx2_ch2_q", + "isBus": true, + "subnets": [ + { + "name": "rx2_ch2_q[11]" + }, + { + "name": "rx2_ch2_q[10]" + }, + { + "name": "rx2_ch2_q[9]" + }, + { + "name": "rx2_ch2_q[8]" + }, + { + "name": "rx2_ch2_q[7]" + }, + { + "name": "rx2_ch2_q[6]" + }, + { + "name": "rx2_ch2_q[5]" + }, + { + "name": "rx2_ch2_q[4]" + }, + { + "name": "rx2_ch2_q[3]" + }, + { + "name": "rx2_ch2_q[2]" + }, + { + "name": "rx2_ch2_q[1]" + }, + { + "name": "rx2_ch2_q[0]" + } + ] + } + ] + } + ] + }, + { + "type": "VIO_V2", + "name": "u_vio_manual_ctrl", + "spec": "labtools_vio_v3", + "ipName": "vio", + "core_location": { + "user_chain": 1, + "slave_index": 1, + "bscan_switch_index": 0 + }, + "uuid": "6DFBBD640CB857419C054C66C7EA7B27", + "pins": [ + { + "name": "probe_out0", + "id": 10, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 1, + "portIndex": 0, + "nets": [ + { + "name": "waveform_sel", + "isBus": true, + "subnets": [ + { + "name": "waveform_sel[1]" + }, + { + "name": "waveform_sel[0]" + } + ] + } + ] + }, + { + "name": "probe_out1", + "id": 11, + "type": "DATA", + "direction": "OUT", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 1, + "nets": [ + { + "name": "sweep_on", + "isBus": false + } + ] + }, + { + "name": "probe_out2", + "id": 12, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 31, + "portIndex": 2, + "nets": [ + { + "name": "freq_set", + "isBus": true, + "subnets": [ + { + "name": "freq_set[31]" + }, + { + "name": "freq_set[30]" + }, + { + "name": "freq_set[29]" + }, + { + "name": "freq_set[28]" + }, + { + "name": "freq_set[27]" + }, + { + "name": "freq_set[26]" + }, + { + "name": "freq_set[25]" + }, + { + "name": "freq_set[24]" + }, + { + "name": "freq_set[23]" + }, + { + "name": "freq_set[22]" + }, + { + "name": "freq_set[21]" + }, + { + "name": "freq_set[20]" + }, + { + "name": "freq_set[19]" + }, + { + "name": "freq_set[18]" + }, + { + "name": "freq_set[17]" + }, + { + "name": "freq_set[16]" + }, + { + "name": "freq_set[15]" + }, + { + "name": "freq_set[14]" + }, + { + "name": "freq_set[13]" + }, + { + "name": "freq_set[12]" + }, + { + "name": "freq_set[11]" + }, + { + "name": "freq_set[10]" + }, + { + "name": "freq_set[9]" + }, + { + "name": "freq_set[8]" + }, + { + "name": "freq_set[7]" + }, + { + "name": "freq_set[6]" + }, + { + "name": "freq_set[5]" + }, + { + "name": "freq_set[4]" + }, + { + "name": "freq_set[3]" + }, + { + "name": "freq_set[2]" + }, + { + "name": "freq_set[1]" + }, + { + "name": "freq_set[0]" + } + ] + } + ] + }, + { + "name": "probe_out3", + "id": 13, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 1, + "portIndex": 3, + "nets": [ + { + "name": "iq_sel", + "isBus": true, + "subnets": [ + { + "name": "iq_sel[1]" + }, + { + "name": "iq_sel[0]" + } + ] + } + ] + }, + { + "name": "probe_out4", + "id": 14, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 3, + "portIndex": 4, + "nets": [ + { + "name": "bb_rshift", + "isBus": true, + "subnets": [ + { + "name": "bb_rshift[3]" + }, + { + "name": "bb_rshift[2]" + }, + { + "name": "bb_rshift[1]" + }, + { + "name": "bb_rshift[0]" + } + ] + } + ] + } + ] + } + ] + } + ] + } +} \ No newline at end of file diff --git a/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/constrs_1/new/dx_z7100_ad9528_2ad9361_physical.xdc b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/constrs_1/new/dx_z7100_ad9528_2ad9361_physical.xdc new file mode 100644 index 0000000..8f982ab --- /dev/null +++ b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/constrs_1/new/dx_z7100_ad9528_2ad9361_physical.xdc @@ -0,0 +1,229 @@ +# dx_2z7100_ad9528_2ad9361 + +## Timing Assertions Section + +## Physical Constraints Section + +# Clocks +set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVDS_25 } [get_ports refclk_1_p ] ;# F1_REFCLK1_P +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVDS } [get_ports refclk_2_p ] ;# F1_REFCLK2_P +set_property -dict {PACKAGE_PIN AD10 } [get_ports gtclk_109_p ] ;# F1_GTCLK0_P +set_property -dict {PACKAGE_PIN AA8 } [get_ports gtclk_110_p ] ;# F1_GTCLK1_P +set_property -dict {PACKAGE_PIN N8 } [get_ports gtclk_112_p ] ;# F1_GTCLK2_P +set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_buffer_clk ] ;# AD9361_1_CLK_OUT +set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_buffer_clk ] ;# AD9361_2_CLK_OUT + +# AD9528 Interface +set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS33} [get_ports ad9528_spi_csn ] ;# AD9528_SPI_CSB +set_property -dict {PACKAGE_PIN AJ25 IOSTANDARD LVCMOS33} [get_ports ad9528_spi_clk ] ;# AD9528_SPI_SCLK +set_property -dict {PACKAGE_PIN AK25 IOSTANDARD LVCMOS33} [get_ports ad9528_spi_mosi ] ;# AD9528_SPI_SDI +set_property -dict {PACKAGE_PIN AK22 IOSTANDARD LVCMOS33} [get_ports ad9528_spi_miso ] ;# AD9528_SPI_SDO + +set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS33} [get_ports ad9528_status[0] ] ;# AD9528_STATUS0 +set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS33} [get_ports ad9528_status[1] ] ;# AD9528_STATUS1 +set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS33} [get_ports ad9528_reset_b ] ;# AD9528_RESETB +set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS33} [get_ports ad9528_sysref_req ] ;# AD9528_SYSREF_REQ + +# AD9361-1 Interface +set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data_clk ] ;# AD9361_1_DATA_CLK_P +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_frame ] ;# AD9361_1_RX_FRAME_P +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[0] ] ;# AD9361_1_P0D00_TXD0_N +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[1] ] ;# AD9361_1_P0D01_TXD0_P +set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[2] ] ;# AD9361_1_P0D02_TXD1_N +set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[3] ] ;# AD9361_1_P0D03_TXD1_P +set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[4] ] ;# AD9361_1_P0D04_TXD2_N +set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[5] ] ;# AD9361_1_P0D05_TXD2_P +set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[6] ] ;# AD9361_1_P0D06_TXD3_N +set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[7] ] ;# AD9361_1_P0D07_TXD3_P +set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[8] ] ;# AD9361_1_P0D08_TXD4_N +set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[9] ] ;# AD9361_1_P0D09_TXD4_P +set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[10] ] ;# AD9361_1_P0D10_TXD5_N +set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[11] ] ;# AD9361_1_P0D11_TXD5_P + +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_fb_clk ] ;# AD9361_1_FB_CLK_P +set_property -dict {PACKAGE_PIN L1 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_frame ] ;# AD9361_1_TX_FRAME_P +set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[0] ] ;# AD9361_1_P1D00_RXD0_N +set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[1] ] ;# AD9361_1_P1D01_RXD0_P +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[2] ] ;# AD9361_1_P1D02_RXD1_N +set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[3] ] ;# AD9361_1_P1D03_RXD1_P +set_property -dict {PACKAGE_PIN F2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[4] ] ;# AD9361_1_P1D04_RXD2_N +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[5] ] ;# AD9361_1_P1D05_RXD2_P +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[6] ] ;# AD9361_1_P1D06_RXD3_N +set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[7] ] ;# AD9361_1_P1D07_RXD3_P +set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[8] ] ;# AD9361_1_P1D08_RXD4_N +set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[9] ] ;# AD9361_1_P1D09_RXD4_P +set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[10] ] ;# AD9361_1_P1D10_RXD5_N +set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[11] ] ;# AD9361_1_P1D11_RXD5_P + +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_clk ] ;# AD9361_1_SPI_CLK +set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_csn ] ;# AD9361_1_SPI_ENB +set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_mosi ] ;# AD9361_1_SPI_DI +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_miso ] ;# AD9361_1_SPI_DO + +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_reset_b ] ;# AD9361_1_RESETB +set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_en_agc ] ;# AD9361_1_EN_AGC +set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_enable ] ;# AD9361_1_ENABLE +set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_txnrx ] ;# AD9361_1_TXNRX + +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[0] ] ;# AD9361_1_CTRL_IN0 +set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[1] ] ;# AD9361_1_CTRL_IN1 +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[2] ] ;# AD9361_1_CTRL_IN2 +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[3] ] ;# AD9361_1_CTRL_IN3 + +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[0] ] ;# AD9361_1_CTRL_OUT0 +set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[1] ] ;# AD9361_1_CTRL_OUT1 +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[2] ] ;# AD9361_1_CTRL_OUT2 +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[3] ] ;# AD9361_1_CTRL_OUT3 +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[4] ] ;# AD9361_1_CTRL_OUT4 +set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[5] ] ;# AD9361_1_CTRL_OUT5 +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[6] ] ;# AD9361_1_CTRL_OUT6 +set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[7] ] ;# AD9361_1_CTRL_OUT7 + +# AD9361-2 Interface +set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data_clk ] ;# AD9361_2_DATA_CLK_P +set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_frame ] ;# AD9361_2_RX_FRAME_P +set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[0] ] ;# AD9361_2_P0D00_TXD0_N +set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[1] ] ;# AD9361_2_P0D01_TXD0_P +set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[2] ] ;# AD9361_2_P0D02_TXD1_N +set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[3] ] ;# AD9361_2_P0D03_TXD1_P +set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[4] ] ;# AD9361_2_P0D04_TXD2_N +set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[5] ] ;# AD9361_2_P0D05_TXD2_P +set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[6] ] ;# AD9361_2_P0D06_TXD3_N +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[7] ] ;# AD9361_2_P0D07_TXD3_P +set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[8] ] ;# AD9361_2_P0D08_TXD4_N +set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[9] ] ;# AD9361_2_P0D09_TXD4_P +set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[10] ] ;# AD9361_2_P0D10_TXD5_N +set_property -dict {PACKAGE_PIN L8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[11] ] ;# AD9361_2_P0D11_TXD5_P + +set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_fb_clk ] ;# AD9361_2_FB_CLK_P +set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_frame ] ;# AD9361_2_TX_FRAME_P +set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[0] ] ;# AD9361_2_P1D00_RXD0_N +set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[1] ] ;# AD9361_2_P1D01_RXD0_P +set_property -dict {PACKAGE_PIN F7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[2] ] ;# AD9361_2_P1D02_RXD1_N +set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[3] ] ;# AD9361_2_P1D03_RXD1_P +set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[4] ] ;# AD9361_2_P1D04_RXD2_N +set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[5] ] ;# AD9361_2_P1D05_RXD2_P +set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[6] ] ;# AD9361_2_P1D06_RXD3_N +set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[7] ] ;# AD9361_2_P1D07_RXD3_P +set_property -dict {PACKAGE_PIN K7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[8] ] ;# AD9361_2_P1D08_RXD4_N +set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[9] ] ;# AD9361_2_P1D09_RXD4_P +set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[10] ] ;# AD9361_2_P1D10_RXD5_N +set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[11] ] ;# AD9361_2_P1D11_RXD5_P + +set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_clk ] ;# AD9361_2_SPI_CLK +set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_csn ] ;# AD9361_2_SPI_ENB +set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_mosi ] ;# AD9361_2_SPI_DI +set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_miso ] ;# AD9361_2_SPI_DO + +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_reset_b ] ;# AD9361_2_RESETB +set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_en_agc ] ;# AD9361_2_EN_AGC +set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_enable ] ;# AD9361_2_ENABLE +set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_txnrx ] ;# AD9361_2_TXNRX + +set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[0] ] ;# AD9361_2_CTRL_IN0 +set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[1] ] ;# AD9361_2_CTRL_IN1 +set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[2] ] ;# AD9361_2_CTRL_IN2 +set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[3] ] ;# AD9361_2_CTRL_IN3 + +set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[0] ] ;# AD9361_2_CTRL_OUT0 +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[1] ] ;# AD9361_2_CTRL_OUT1 +set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[2] ] ;# AD9361_2_CTRL_OUT2 +set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[3] ] ;# AD9361_2_CTRL_OUT3 +set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[4] ] ;# AD9361_2_CTRL_OUT4 +set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[5] ] ;# AD9361_2_CTRL_OUT5 +set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[6] ] ;# AD9361_2_CTRL_OUT6 +set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[7] ] ;# AD9361_2_CTRL_OUT7 + +# Inter-FPGA Ports +set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[0] ] ;# LVDS_IO_GRP0_00P +set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[1] ] ;# LVDS_IO_GRP0_01P +set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[2] ] ;# LVDS_IO_GRP0_02P +set_property -dict {PACKAGE_PIN Y28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[3] ] ;# LVDS_IO_GRP0_03P +set_property -dict {PACKAGE_PIN AA27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[4] ] ;# LVDS_IO_GRP0_04P +set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[5] ] ;# LVDS_IO_GRP0_05P +set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[6] ] ;# LVDS_IO_GRP0_06P +set_property -dict {PACKAGE_PIN AD30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[7] ] ;# LVDS_IO_GRP0_07P +set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[8] ] ;# LVDS_IO_GRP0_08P +set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[9] ] ;# LVDS_IO_GRP0_09P +set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[10] ] ;# LVDS_IO_GRP0_10P +set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[11] ] ;# LVDS_IO_GRP0_11P +set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[12] ] ;# LVDS_IO_GRP0_12P +set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[13] ] ;# LVDS_IO_GRP0_13P +set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[14] ] ;# LVDS_IO_GRP0_14P +set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[15] ] ;# LVDS_IO_GRP0_15P +set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[16] ] ;# LVDS_IO_GRP0_16P +set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[17] ] ;# LVDS_IO_GRP0_17P +set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[18] ] ;# LVDS_IO_GRP0_18P +set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[19] ] ;# LVDS_IO_GRP0_19P +set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[20] ] ;# LVDS_IO_GRP0_20P +set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[21] ] ;# LVDS_IO_GRP0_21P +set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[22] ] ;# LVDS_IO_GRP0_22P + +set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[0] ] ;# LVDS_IO_GRP1_00P +set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[1] ] ;# LVDS_IO_GRP1_01P +set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[2] ] ;# LVDS_IO_GRP1_02P +set_property -dict {PACKAGE_PIN N28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[3] ] ;# LVDS_IO_GRP1_03P +set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[4] ] ;# LVDS_IO_GRP1_04P +set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[5] ] ;# LVDS_IO_GRP1_05P +set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[6] ] ;# LVDS_IO_GRP1_06P +set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[7] ] ;# LVDS_IO_GRP1_07P +set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[8] ] ;# LVDS_IO_GRP1_08P +set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[9] ] ;# LVDS_IO_GRP1_09P +set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[10] ] ;# LVDS_IO_GRP1_10P +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[11] ] ;# LVDS_IO_GRP1_11P +set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[12] ] ;# LVDS_IO_GRP1_12P +set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[13] ] ;# LVDS_IO_GRP1_13P +set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[14] ] ;# LVDS_IO_GRP1_14P +set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[15] ] ;# LVDS_IO_GRP1_15P +set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[16] ] ;# LVDS_IO_GRP1_16P +set_property -dict {PACKAGE_PIN R27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[17] ] ;# LVDS_IO_GRP1_17P +set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[18] ] ;# LVDS_IO_GRP1_18P +set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[19] ] ;# LVDS_IO_GRP1_19P +set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[20] ] ;# LVDS_IO_GRP1_20P +set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[21] ] ;# LVDS_IO_GRP1_21P +set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[22] ] ;# LVDS_IO_GRP1_22P + +set_property -dict {PACKAGE_PIN AH10 } [get_ports if_gtx_rxp[0] ] ;# GTX_F1R_F2T_00P +set_property -dict {PACKAGE_PIN AJ8 } [get_ports if_gtx_rxp[1] ] ;# GTX_F1R_F2T_01P +set_property -dict {PACKAGE_PIN AG8 } [get_ports if_gtx_rxp[2] ] ;# GTX_F1R_F2T_02P +set_property -dict {PACKAGE_PIN AE8 } [get_ports if_gtx_rxp[3] ] ;# GTX_F1R_F2T_03P +set_property -dict {PACKAGE_PIN AH6 } [get_ports if_gtx_rxp[4] ] ;# GTX_F1R_F2T_04P +set_property -dict {PACKAGE_PIN AG4 } [get_ports if_gtx_rxp[5] ] ;# GTX_F1R_F2T_05P +set_property -dict {PACKAGE_PIN AF6 } [get_ports if_gtx_rxp[6] ] ;# GTX_F1R_F2T_06P +set_property -dict {PACKAGE_PIN AD6 } [get_ports if_gtx_rxp[7] ] ;# GTX_F1R_F2T_07P + +# set_property -dict {PACKAGE_PIN AK10 } [get_ports if_gtx_txp[0] ] ;# GTX_F1T_F2R_00P +# set_property -dict {PACKAGE_PIN AK6 } [get_ports if_gtx_txp[1] ] ;# GTX_F1T_F2R_01P +# set_property -dict {PACKAGE_PIN AJ4 } [get_ports if_gtx_txp[2] ] ;# GTX_F1T_F2R_02P +# set_property -dict {PACKAGE_PIN AK2 } [get_ports if_gtx_txp[3] ] ;# GTX_F1T_F2R_03P +# set_property -dict {PACKAGE_PIN AH2 } [get_ports if_gtx_txp[4] ] ;# GTX_F1T_F2R_04P +# set_property -dict {PACKAGE_PIN AF2 } [get_ports if_gtx_txp[5] ] ;# GTX_F1T_F2R_05P +# set_property -dict {PACKAGE_PIN AE4 } [get_ports if_gtx_txp[6] ] ;# GTX_F1T_F2R_06P +# set_property -dict {PACKAGE_PIN AD2 } [get_ports if_gtx_txp[7] ] ;# GTX_F1T_F2R_07P + +# Inter-board Ports +set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVDS_25 } [get_ports ib_lvds_io_p[0] ] ;# F1_LVDS_IO1P +set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVDS_25 } [get_ports ib_lvds_io_p[1] ] ;# F1_LVDS_IO2P +set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25 } [get_ports ib_lvds_io_p[2] ] ;# F1_LVDS_IO3P +set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25 } [get_ports ib_lvds_io_p[3] ] ;# F1_LVDS_IO4P +set_property -dict {PACKAGE_PIN AH18 IOSTANDARD LVDS_25 } [get_ports ib_lvds_io_p[4] ] ;# F1_LVDS_IO5P + +set_property -dict {PACKAGE_PIN T2 } [get_ports ib_gtx_s2p_p[0] ] ;# F1_GTX0_S2P_P +set_property -dict {PACKAGE_PIN R4 } [get_ports ib_gtx_s2p_p[1] ] ;# F1_GTX1_S2P_P +set_property -dict {PACKAGE_PIN P2 } [get_ports ib_gtx_s2p_p[2] ] ;# F1_GTX2_S2P_P +set_property -dict {PACKAGE_PIN N4 } [get_ports ib_gtx_s2p_p[3] ] ;# F1_GTX3_S2P_P + +# set_property -dict {PACKAGE_PIN V6 } [get_ports ib_gtx_p2s_p[0] ] ;# F1_GTX0_P2S_P +# set_property -dict {PACKAGE_PIN U4 } [get_ports ib_gtx_p2s_p[1] ] ;# F1_GTX1_P2S_P +# set_property -dict {PACKAGE_PIN T6 } [get_ports ib_gtx_p2s_p[2] ] ;# F1_GTX2_P2S_P +# set_property -dict {PACKAGE_PIN P6 } [get_ports ib_gtx_p2s_p[3] ] ;# F1_GTX3_P2S_P + +# 3.3V Debug IO +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS33} [get_ports uart_rxd ] ;# PL1_UART_RXD +set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports uart_txd ] ;# PL1_UART_TXD + +set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS33} [get_ports debug_io_1 ] ;# PL1_DEBUG_IO_1 +set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS33} [get_ports debug_io_2 ] ;# PL1_DEBUG_IO_2 +set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS33} [get_ports debug_io_3 ] ;# PL1_DEBUG_IO_3 +set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS33} [get_ports debug_io_4 ] ;# PL1_DEBUG_IO_4 +set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS33} [get_ports debug_io_5 ] ;# PL1_DEBUG_IO_5 diff --git a/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/common/ad_rst.v b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/common/ad_rst.v new file mode 100644 index 0000000..4310963 --- /dev/null +++ b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/common/ad_rst.v @@ -0,0 +1,77 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_rst ( + + // clock reset + + input rst_async, + input clk, + output rstn, + output reg rst); + + // internal registers + reg rst_async_d1 = 1'd1; + reg rst_async_d2 = 1'd1; + reg rst_sync = 1'd1; + reg rst_sync_d = 1'd1; + + // simple reset synchronizer + always @(posedge clk or posedge rst_async) begin + if (rst_async) begin + rst_async_d1 <= 1'b1; + rst_async_d2 <= 1'b1; + rst_sync <= 1'b1; + end else begin + rst_async_d1 <= 1'b0; + rst_async_d2 <= rst_async_d1; + rst_sync <= rst_async_d2; + end + end + + // two-stage synchronizer to prevent metastability on the falling edge + always @(posedge clk) begin + rst_sync_d <= rst_sync; + rst <= rst_sync_d; + end + + assign rstn = ~rst; + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/common/up_axi.v b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/common/up_axi.v new file mode 100644 index 0000000..40acb17 --- /dev/null +++ b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/common/up_axi.v @@ -0,0 +1,239 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module up_axi #( + + parameter AXI_ADDRESS_WIDTH = 16) ( + + // reset and clocks + + input up_rstn, + input up_clk, + + // axi4 interface + + input up_axi_awvalid, + input [(AXI_ADDRESS_WIDTH-1):0] up_axi_awaddr, + output up_axi_awready, + input up_axi_wvalid, + input [31:0] up_axi_wdata, + input [ 3:0] up_axi_wstrb, + output up_axi_wready, + output up_axi_bvalid, + output [ 1:0] up_axi_bresp, + input up_axi_bready, + input up_axi_arvalid, + input [(AXI_ADDRESS_WIDTH-1):0] up_axi_araddr, + output up_axi_arready, + output up_axi_rvalid, + output [ 1:0] up_axi_rresp, + output [31:0] up_axi_rdata, + input up_axi_rready, + + // pcore interface + + output up_wreq, + output [(AXI_ADDRESS_WIDTH-3):0] up_waddr, + output [31:0] up_wdata, + input up_wack, + output up_rreq, + output [(AXI_ADDRESS_WIDTH-3):0] up_raddr, + input [31:0] up_rdata, + input up_rack); + + // internal registers + + reg up_axi_awready_int = 'd0; + reg up_axi_wready_int = 'd0; + reg up_axi_bvalid_int = 'd0; + reg up_wack_d = 'd0; + reg up_wsel = 'd0; + reg up_wreq_int = 'd0; + reg [(AXI_ADDRESS_WIDTH-3):0] up_waddr_int = 'd0; + reg [31:0] up_wdata_int = 'd0; + reg [ 4:0] up_wcount = 'd0; + reg up_axi_arready_int = 'd0; + reg up_axi_rvalid_int = 'd0; + reg [31:0] up_axi_rdata_int = 'd0; + reg up_rack_d = 'd0; + reg [31:0] up_rdata_d = 'd0; + reg up_rsel = 'd0; + reg up_rreq_int = 'd0; + reg [(AXI_ADDRESS_WIDTH-3):0] up_raddr_int = 'd0; + reg [ 4:0] up_rcount = 'd0; + + // internal signals + + wire up_wack_s; + wire up_rack_s; + wire [31:0] up_rdata_s; + + // write channel interface + + assign up_axi_awready = up_axi_awready_int; + assign up_axi_wready = up_axi_wready_int; + assign up_axi_bvalid = up_axi_bvalid_int; + assign up_axi_bresp = 2'd0; + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_axi_awready_int <= 'd0; + up_axi_wready_int <= 'd0; + up_axi_bvalid_int <= 'd0; + end else begin + if (up_axi_awready_int == 1'b1) begin + up_axi_awready_int <= 1'b0; + end else if (up_wack_s == 1'b1) begin + up_axi_awready_int <= 1'b1; + end + if (up_axi_wready_int == 1'b1) begin + up_axi_wready_int <= 1'b0; + end else if (up_wack_s == 1'b1) begin + up_axi_wready_int <= 1'b1; + end + if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin + up_axi_bvalid_int <= 1'b0; + end else if (up_wack_d == 1'b1) begin + up_axi_bvalid_int <= 1'b1; + end + end + end + + assign up_wreq = up_wreq_int; + assign up_waddr = up_waddr_int; + assign up_wdata = up_wdata_int; + assign up_wack_s = (up_wcount == 5'h1f) ? 1'b1 : (up_wcount[4] & up_wack); + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_wack_d <= 'd0; + up_wsel <= 'd0; + up_wreq_int <= 'd0; + up_waddr_int <= 'd0; + up_wdata_int <= 'd0; + up_wcount <= 'd0; + end else begin + up_wack_d <= up_wack_s; + if (up_wsel == 1'b1) begin + if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin + up_wsel <= 1'b0; + end + up_wreq_int <= 1'b0; + end else begin + up_wsel <= up_axi_awvalid & up_axi_wvalid; + up_wreq_int <= up_axi_awvalid & up_axi_wvalid; + up_waddr_int <= up_axi_awaddr[(AXI_ADDRESS_WIDTH-1):2]; + up_wdata_int <= up_axi_wdata; + end + if (up_wack_s == 1'b1) begin + up_wcount <= 5'h00; + end else if (up_wcount[4] == 1'b1) begin + up_wcount <= up_wcount + 1'b1; + end else if (up_wreq_int == 1'b1) begin + up_wcount <= 5'h10; + end + end + end + + // read channel interface + + assign up_axi_arready = up_axi_arready_int; + assign up_axi_rvalid = up_axi_rvalid_int; + assign up_axi_rdata = up_axi_rdata_int; + assign up_axi_rresp = 2'd0; + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_axi_arready_int <= 'd0; + up_axi_rvalid_int <= 'd0; + up_axi_rdata_int <= 'd0; + end else begin + if (up_axi_arready_int == 1'b1) begin + up_axi_arready_int <= 1'b0; + end else if (up_rack_s == 1'b1) begin + up_axi_arready_int <= 1'b1; + end + if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin + up_axi_rvalid_int <= 1'b0; + up_axi_rdata_int <= 32'd0; + end else if (up_rack_d == 1'b1) begin + up_axi_rvalid_int <= 1'b1; + up_axi_rdata_int <= up_rdata_d; + end + end + end + + assign up_rreq = up_rreq_int; + assign up_raddr = up_raddr_int; + assign up_rack_s = (up_rcount == 5'h1f) ? 1'b1 : (up_rcount[4] & up_rack); + assign up_rdata_s = (up_rcount == 5'h1f) ? {2{16'hdead}} : up_rdata; + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_rack_d <= 'd0; + up_rdata_d <= 'd0; + up_rsel <= 'd0; + up_rreq_int <= 'd0; + up_raddr_int <= 'd0; + up_rcount <= 'd0; + end else begin + up_rack_d <= up_rack_s; + up_rdata_d <= up_rdata_s; + if (up_rsel == 1'b1) begin + if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin + up_rsel <= 1'b0; + end + up_rreq_int <= 1'b0; + end else begin + up_rsel <= up_axi_arvalid; + up_rreq_int <= up_axi_arvalid; + up_raddr_int <= up_axi_araddr[(AXI_ADDRESS_WIDTH-1):2]; + end + if (up_rack_s == 1'b1) begin + up_rcount <= 5'h00; + end else if (up_rcount[4] == 1'b1) begin + up_rcount <= up_rcount + 1'b1; + end else if (up_rreq_int == 1'b1) begin + up_rcount <= 5'h10; + end + end + end + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci new file mode 100644 index 0000000..aa665df --- /dev/null +++ b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci @@ -0,0 +1,302 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "system_bd_auto_pc_0", + "cell_name": "axi_interconnect/s00_couplers/auto_pc", + "component_reference": "xilinx.com:ip:axi_protocol_converter:2.1", + "ip_revision": "31", + "gen_directory": "../../../../../../dx_sig_basic.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0", + "parameters": { + "component_parameters": { + "SI_PROTOCOL": [ { "value": "AXI3", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], + "MI_PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": 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a/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci new file mode 100644 index 0000000..7d84313 --- /dev/null +++ b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci @@ -0,0 +1,1302 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "system_bd_processing_system7_0_0", + "cell_name": "processing_system7_0", + "component_reference": "xilinx.com:ip:processing_system7:5.5", + "ip_revision": "6", + "gen_directory": "../../../../../../dx_sig_basic.gen/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0", + "parameters": { + "component_parameters": { + "PCW_DDR_RAM_BASEADDR": [ { "value": "0x00100000", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_DDR_RAM_HIGHADDR": [ { "value": "0x1FFFFFFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_UART0_BASEADDR": [ { "value": "0xE0000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_UART0_HIGHADDR": [ { "value": "0xE0000FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_UART1_BASEADDR": [ { "value": "0xE0001000", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_UART1_HIGHADDR": [ { "value": "0xE0001FFF", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_I2C0_BASEADDR": [ { "value": "0xE0004000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_I2C0_HIGHADDR": [ { "value": "0xE0004FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_I2C1_BASEADDR": [ { "value": "0xE0005000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_I2C1_HIGHADDR": [ { "value": "0xE0005FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SPI0_BASEADDR": [ { "value": "0xE0006000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SPI0_HIGHADDR": [ { "value": "0xE0006FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SPI1_BASEADDR": [ { "value": "0xE0007000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SPI1_HIGHADDR": [ { "value": "0xE0007FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_CAN0_BASEADDR": [ { "value": "0xE0008000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_CAN0_HIGHADDR": [ { "value": "0xE0008FFF", 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"PCW_USB1_BASEADDR": [ { "value": "0xE0103000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_USB1_HIGHADDR": [ { "value": "0xE0103fff", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_TTC0_BASEADDR": [ { "value": "0xE0104000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_TTC0_HIGHADDR": [ { "value": "0xE0104fff", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_TTC1_BASEADDR": [ { "value": "0xE0105000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_TTC1_HIGHADDR": [ { "value": "0xE0105fff", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_FCLK_CLK0_BUF": [ { "value": "TRUE", "resolve_type": "user", "usage": "all" } ], + "PCW_FCLK_CLK1_BUF": [ { "value": "FALSE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_FCLK_CLK2_BUF": [ { "value": "FALSE", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_FCLK_CLK3_BUF": [ { "value": "FALSE", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_FREQ_MHZ": [ { "value": "533.333333", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_BANK_ADDR_COUNT": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_ROW_ADDR_COUNT": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_COL_ADDR_COUNT": [ { "value": "10", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_CL": [ { "value": "7", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_CWL": [ { "value": "6", "value_src": "user", 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