From e93815c8b0c2eccd23f46bf40e5abc6333b0004c Mon Sep 17 00:00:00 2001 From: Josh Gao Date: Wed, 16 Oct 2024 18:58:44 +0800 Subject: [PATCH] add dx_sig_basic, update .gitignore --- vivado_pvt/.gitignore | 40 +- .../projects/dx_sig/dx_sig_basic/README.md | 47 + .../dx_sig_basic.runs/impl_1/debug_nets.ltx | 796 + .../dx_sig_basic.runs/impl_1/system_top.bit | 3 + .../dx_sig_basic.runs/impl_1/system_top.ltx | 796 + .../new/dx_z7100_ad9528_2ad9361_physical.xdc | 229 + .../sources_1/bd/system_bd/common/ad_rst.v | 77 + .../sources_1/bd/system_bd/common/up_axi.v | 239 + .../system_bd_auto_pc_0.xci | 302 + .../system_bd_axi_interconnect_0_0.xci | 353 + .../system_bd_axi_spi_engine_0_0.xci | 280 + .../ps7_parameters.xml | 643 + .../system_bd_processing_system7_0_0.xci | 1302 + .../system_bd_rst_ps7_0_50M_0.xci | 196 + .../system_bd_spi_engine_execution_0_0.xci | 170 + .../system_bd_xlconcat_0_0.xci | 307 + .../sources_1/bd/system_bd/system_bd.bd | 1224 + .../sources_1/bd/system_bd/system_bd.bda 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.../src/arm/ARMv8/64bit/xil_cache.h | 76 + .../src/arm/ARMv8/64bit/xil_errata.h | 67 + .../src/arm/ARMv8/64bit/xil_mmu.c | 185 + .../src/arm/ARMv8/64bit/xil_mmu.h | 97 + .../src/arm/ARMv8/64bit/xil_smc.c | 84 + .../src/arm/ARMv8/64bit/xil_smc.h | 120 + .../src/arm/ARMv8/64bit/xpm_counter.h | 287 + .../src/arm/ARMv8/64bit/xpseudo_asm.h | 56 + .../arm/ARMv8/64bit/xpvxenconsole/arm64_ops.h | 207 + .../arm/ARMv8/64bit/xpvxenconsole/hypercall.S | 49 + .../arm/ARMv8/64bit/xpvxenconsole/hypercall.h | 29 + .../src/arm/ARMv8/64bit/xpvxenconsole/xen.h | 131 + .../ARMv8/64bit/xpvxenconsole/xen_console.c | 420 + .../ARMv8/64bit/xpvxenconsole/xen_console.h | 39 + .../ARMv8/64bit/xpvxenconsole/xen_events.c | 191 + .../ARMv8/64bit/xpvxenconsole/xen_events.h | 58 + .../src/arm/ARMv8/64bit/xreg_cortexa53.h | 174 + .../src/arm/ARMv8/64bit/xtime_l.c | 116 + .../src/arm/ARMv8/64bit/xtime_l.h | 101 + .../src/arm/ARMv8/CMakeLists.txt | 12 + .../src/arm/ARMv8/includes_ps/CMakeLists.txt | 3 + .../ARMv8/includes_ps/platform/CMakeLists.txt | 3 + .../platform/Versal/xfpd_slave_xmpu.h | 1667 + .../includes_ps/platform/Versal/xfpd_slcr.h | 147 + .../platform/Versal/xfpd_slcr_secure.h | 197 + .../platform/Versal/xlpd_iou_secure_slcr.h | 164 + .../platform/Versal/xlpd_iou_slcr.h | 2202 + .../includes_ps/platform/Versal/xlpd_slcr.h | 501 + .../platform/Versal/xlpd_slcr_secure.h | 328 + .../includes_ps/platform/Versal/xlpd_xppu.h | 6769 ++ .../includes_ps/platform/Versal/xocm_xmpu.h | 1667 + .../platform/Versal/xpmc_iou_secure_slcr.h | 175 + .../platform/Versal/xpmc_iou_slcr.h | 3797 + .../includes_ps/platform/Versal/xpmc_xmpu.h | 1667 + .../includes_ps/platform/Versal/xpmc_xppu.h | 6769 ++ .../platform/ZynqMP/CMakeLists.txt | 19 + .../platform/ZynqMP/xddr_xmpu0_cfg.h | 1315 + .../platform/ZynqMP/xddr_xmpu1_cfg.h | 1314 + .../platform/ZynqMP/xddr_xmpu2_cfg.h | 1313 + .../platform/ZynqMP/xddr_xmpu3_cfg.h | 1315 + .../platform/ZynqMP/xddr_xmpu4_cfg.h | 1315 + .../platform/ZynqMP/xddr_xmpu5_cfg.h | 1315 + .../includes_ps/platform/ZynqMP/xfpd_slcr.h | 393 + .../platform/ZynqMP/xfpd_slcr_secure.h | 288 + .../platform/ZynqMP/xfpd_xmpu_cfg.h | 1314 + .../platform/ZynqMP/xfpd_xmpu_sink.h | 92 + .../platform/ZynqMP/xiou_secure_slcr.h | 185 + .../includes_ps/platform/ZynqMP/xiou_slcr.h | 4040 + .../includes_ps/platform/ZynqMP/xlpd_slcr.h | 5678 + .../platform/ZynqMP/xlpd_slcr_secure.h | 152 + .../includes_ps/platform/ZynqMP/xlpd_xppu.h | 869 + .../platform/ZynqMP/xlpd_xppu_sink.h | 92 + .../platform/ZynqMP/xocm_xmpu_cfg.h | 1315 + .../standalone_v9_1/src/arm/ARMv8/xarmv8.h | 19 + .../src/arm/ARMv8/xarmv8_config.h | 20 + .../standalone_v9_1/src/arm/CMakeLists.txt | 21 + .../src/arm/common/CMakeLists.txt | 13 + .../src/arm/common/armclang/_sys_close.c | 13 + .../src/arm/common/armclang/_sys_exit.c | 15 + .../src/arm/common/armclang/_sys_iserror.c | 17 + .../src/arm/common/armclang/_sys_istty.c | 14 + .../src/arm/common/armclang/_sys_open.c | 14 + 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.../libsrc/scuwdt_v2_5/src/CMakeLists.txt | 18 + .../libsrc/scuwdt_v2_5/src/Makefile | 39 + .../libsrc/scuwdt_v2_5/src/xscuwdt.c | 194 + .../libsrc/scuwdt_v2_5/src/xscuwdt.h | 382 + .../libsrc/scuwdt_v2_5/src/xscuwdt_g.c | 31 + .../libsrc/scuwdt_v2_5/src/xscuwdt_hw.h | 157 + .../libsrc/scuwdt_v2_5/src/xscuwdt_selftest.c | 105 + .../libsrc/scuwdt_v2_5/src/xscuwdt_sinit.c | 90 + .../libsrc/standalone_v9_1/src/CMakeLists.txt | 9 + .../libsrc/standalone_v9_1/src/Makefile | 83 + .../libsrc/standalone_v9_1/src/_exit.c | 18 + .../libsrc/standalone_v9_1/src/_open.c | 32 + .../libsrc/standalone_v9_1/src/_sbrk.c | 43 + .../libsrc/standalone_v9_1/src/abort.c | 16 + .../src/arm/ARMv8/32bit/gcc/Makefile | 79 + .../src/arm/ARMv8/32bit/gcc/asm_vectors.S | 154 + .../src/arm/ARMv8/32bit/gcc/boot.S | 277 + .../src/arm/ARMv8/32bit/gcc/cpu_init.S | 50 + .../src/arm/ARMv8/32bit/gcc/xil-crt0.S | 103 + .../32bit/platform/ZynqMP/CMakeLists.txt | 3 + .../32bit/platform/ZynqMP/translation_table.S | 155 + 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+ .../src/arm/ARMv8/64bit/xil_mmu.c | 185 + .../src/arm/ARMv8/64bit/xil_mmu.h | 97 + .../src/arm/ARMv8/64bit/xil_smc.c | 84 + .../src/arm/ARMv8/64bit/xil_smc.h | 120 + .../src/arm/ARMv8/64bit/xpm_counter.h | 287 + .../src/arm/ARMv8/64bit/xpseudo_asm.h | 56 + .../arm/ARMv8/64bit/xpvxenconsole/arm64_ops.h | 207 + .../arm/ARMv8/64bit/xpvxenconsole/hypercall.S | 49 + .../arm/ARMv8/64bit/xpvxenconsole/hypercall.h | 29 + .../src/arm/ARMv8/64bit/xpvxenconsole/xen.h | 131 + .../ARMv8/64bit/xpvxenconsole/xen_console.c | 420 + .../ARMv8/64bit/xpvxenconsole/xen_console.h | 39 + .../ARMv8/64bit/xpvxenconsole/xen_events.c | 191 + .../ARMv8/64bit/xpvxenconsole/xen_events.h | 58 + .../src/arm/ARMv8/64bit/xreg_cortexa53.h | 174 + .../src/arm/ARMv8/64bit/xtime_l.c | 116 + .../src/arm/ARMv8/64bit/xtime_l.h | 101 + .../src/arm/ARMv8/CMakeLists.txt | 12 + .../src/arm/ARMv8/includes_ps/CMakeLists.txt | 3 + .../ARMv8/includes_ps/platform/CMakeLists.txt | 3 + .../platform/Versal/xfpd_slave_xmpu.h | 1667 + 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vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/common/ad_rst.v create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/common/up_axi.v create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_axi_interconnect_0_0/system_bd_axi_interconnect_0_0.xci create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/ps7_parameters.xml create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_rst_ps7_0_50M_0/system_bd_rst_ps7_0_50M_0.xci create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_xlconcat_0_0/system_bd_xlconcat_0_0.xci create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/system_bd.bd create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/system_bd.bda create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ui/bd_e4e34314.ui create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/xilinx/common/ad_rst_constr.xdc create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/ip/ad9361_clk_gen_cmos_1t1r/ad9361_clk_gen_cmos_1t1r.xci create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/ip/ad9361_clk_gen_cmos_2t2r/ad9361_clk_gen_cmos_2t2r.xci create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/ip/ad9361_fifo/ad9361_fifo.xci create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/ip/cmpy_18x8/cmpy_18x8.xci create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/ip/coe/hrc_64_12_025.coe create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/ip/coe/sweep_freq.coe create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/ip/dds_32b_8b/dds_32b_8b.xci create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/ip/hop_rom/hop_rom.xci create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/ip/hrc_64_12_025/hrc_64_12_025.xci create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/ip/ila_trx/ila_trx.xci create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/ip/vio_manual_ctrl/vio_manual_ctrl.xci create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/new/ad9361_rx_map_cmos_dual.v create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/new/ad9361_rx_map_cmos_single.v create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/new/ad9361_tx_map_cmos_dual.v create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/new/ad9361_tx_map_cmos_single.v create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/new/clk_dist.v create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/new/system_top.v create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/new/tx_qpsk.v create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.xpr create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/system_top.xsa create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/.cproject create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/.gitignore create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/.project create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/_ide/bitstream/system_top.bit create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/_ide/hwspec.checksum create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/_ide/psinit/ps7_init.tcl create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/dx_sig_hdwr.prj create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/README.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/Xilinx.spec create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/config/app_config.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/dev_profile/ad9361_1_reg_profile.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/dev_profile/ad9361_2_reg_profile.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/dev_profile/ad9361_profile.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/dev_profile/ad9528_profile.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/dev_profile/dev_profile.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/dev_profile/global_timer_profile.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/dev_profile/hmc7044_profile.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/dev_profile/intc_profile.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/dev_profile/timer_profile.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/adc/ad9694/ad9694.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/adc/ad9694/ad9694.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/api/gpio.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/api/i2c.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/api/irq.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/api/spi.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/api/timer.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/api/trng.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/axi_core/axi_dmac/axi_dmac.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/axi_core/axi_dmac/axi_dmac.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/axi_core/spi_engine/spi_engine.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/axi_core/spi_engine/spi_engine.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/axi_core/spi_engine/spi_engine_private.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/frequency/ad9528/ad9528.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/frequency/ad9528/ad9528.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/frequency/hmc7044/hmc7044.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/frequency/hmc7044/hmc7044.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/platform/xilinx_axi_io.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/platform/xilinx_delay.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/platform/xilinx_gpio.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/platform/xilinx_gpio.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/platform/xilinx_gpio_irq.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/platform/xilinx_gpio_irq.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/platform/xilinx_i2c.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/platform/xilinx_i2c.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/platform/xilinx_irq.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/platform/xilinx_irq.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/platform/xilinx_spi.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/platform/xilinx_spi.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/platform/xilinx_spi_pl.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/platform/xilinx_timer.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/platform/xilinx_timer.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/rf-transceiver/ad9361/ad9361.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/rf-transceiver/ad9361/ad9361.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/rf-transceiver/ad9361/ad9361_api.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/rf-transceiver/ad9361/ad9361_api.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/rf-transceiver/ad9361/ad9361_conv.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/rf-transceiver/ad9361/ad9361_util.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/rf-transceiver/ad9361/ad9361_util.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/rf-transceiver/ad9361/common.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/rf-transceiver/ad9361_reg/ad9361_reg.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/drivers/rf-transceiver/ad9361_reg/ad9361_reg.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/hwconfig.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/hwconfig.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/include/axi_io.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/include/circ_queue.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/include/clist.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/include/common.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/include/delay.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/include/error.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/include/global_timer.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/include/gpio.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/include/i2c.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/include/irq.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/include/list.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/include/spi.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/include/timer.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/include/trng.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/include/util.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/lscript.ld create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/main.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/system_monitor.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/system_monitor.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/util/circ_queue.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/util/clist.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/util/common.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/util/crc.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/util/list.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/util/tables.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr/src/util/util.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr_system/.cproject create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr_system/.gitignore create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr_system/.project create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_hdwr_system/dx_sig_hdwr_system.sprj create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/.cproject create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/.gitignore create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/.project create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/hw/ps7_init.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/hw/ps7_init.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/hw/ps7_init.html create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/hw/ps7_init.tcl create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/hw/ps7_init_gpl.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/hw/ps7_init_gpl.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/hw/system_top.bit create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/hw/system_top.xsa create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/platform.spr create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/platform.tcl create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/dep.mk create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/_profile_timer_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/bspconfig.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/mblaze_nt_types.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/pm_api_version.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/profile.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/sleep.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/smc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/vectors.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xadcps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xadcps_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xbasic_types.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xcortexa9.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xcortexa9_config.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xddrps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xdebug.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xdevcfg.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xdevcfg_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xdmaps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xdmaps_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xenv.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xenv_standalone.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xgpiops.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xgpiops_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_assert.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_cache.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_cache_l.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_clocking.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_cryptoalginfo.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_errata.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_exception.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_hal.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_io.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_macroback.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_mem.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_mmu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_printf.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_sleeptimer.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_spinlock.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_testcache.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_testio.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_testmem.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_types.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xil_util.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xinterrupt_wrap.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xl2cc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xl2cc_counter.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xparameters.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xparameters_ps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xplatform_info.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xpm_counter.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xpm_init.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xpseudo_asm.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xqspips.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xqspips_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xreg_cortexa9.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xscugic.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xscugic_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xscutimer.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xscutimer_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xscuwdt.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xscuwdt_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xstatus.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xtime_l.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xuartps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/include/xuartps_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_10/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_10/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_10/src/xcoresightpsdcc.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_10/src/xcoresightpsdcc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src/xcpu_cortexa9.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/ddrps_v1_2/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/ddrps_v1_2/src/xddrps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_g.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_hw.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_intr.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_selftest.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_sinit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_10/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_10/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_10/src/xdmaps.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_10/src/xdmaps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_10/src/xdmaps_g.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_10/src/xdmaps_hw.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_10/src/xdmaps_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_10/src/xdmaps_selftest.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/dmaps_v2_10/src/xdmaps_sinit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_13/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_13/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_13/src/xgpiops.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_13/src/xgpiops.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_13/src/xgpiops_g.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_13/src/xgpiops_hw.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_13/src/xgpiops_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_13/src/xgpiops_intr.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_13/src/xgpiops_selftest.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/gpiops_v3_13/src/xgpiops_sinit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_12/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_12/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_12/src/xqspips.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_12/src/xqspips.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_12/src/xqspips_g.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_12/src/xqspips_hw.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_12/src/xqspips_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_12/src/xqspips_options.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_12/src/xqspips_selftest.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/qspips_v3_12/src/xqspips_sinit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_3/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_3/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_3/src/xscugic.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_3/src/xscugic.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_3/src/xscugic_g.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_3/src/xscugic_hw.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_3/src/xscugic_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_3/src/xscugic_intr.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_3/src/xscugic_selftest.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scugic_v5_3/src/xscugic_sinit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_6/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_6/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_6/src/xscutimer.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_6/src/xscutimer.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_6/src/xscutimer_g.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_6/src/xscutimer_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_6/src/xscutimer_selftest.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scutimer_v2_6/src/xscutimer_sinit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_g.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_selftest.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_sinit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/_exit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/_open.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/_sbrk.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/abort.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/gcc/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/gcc/asm_vectors.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/gcc/boot.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/gcc/cpu_init.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/gcc/xil-crt0.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/platform/ZynqMP/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/platform/ZynqMP/translation_table.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/platform/ZynqMP/xparameters_ps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/platform/versal/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/platform/versal/xparameters_ps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/sleep.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/usleep.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/xil_cache.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/xil_cache.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/xil_cache_l.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/xil_mmu.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/xil_mmu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/xparameters_ps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/xpseudo_asm.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/xreg_cortexa53.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/xtime_l.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/xtime_l.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/armclang/ARM_argv_veneer.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/armclang/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/armclang/asm_vectors.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/armclang/boot.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/armclang/xpseudo_asm_armclang.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/gcc/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/gcc/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/gcc/asm_vectors.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/gcc/boot.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/gcc/initialise_monitor_handles.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/gcc/xil-crt0.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/platform/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/platform/ZynqMP/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/platform/ZynqMP/armclang/translation_table.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/platform/ZynqMP/gcc/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/platform/ZynqMP/gcc/translation_table.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/platform/ZynqMP/xparameters_ps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/platform/versal/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/platform/versal/armclang/translation_table.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/platform/versal/gcc/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/platform/versal/gcc/translation_table.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/platform/versal/xparameters_ps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/sleep.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xil_cache.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xil_cache.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xil_errata.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xil_mmu.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xil_mmu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xil_smc.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xil_smc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xpm_counter.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xpseudo_asm.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xpvxenconsole/arm64_ops.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xpvxenconsole/hypercall.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xpvxenconsole/hypercall.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xpvxenconsole/xen.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xpvxenconsole/xen_console.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xpvxenconsole/xen_console.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xpvxenconsole/xen_events.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xpvxenconsole/xen_events.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xreg_cortexa53.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xtime_l.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xtime_l.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xfpd_slave_xmpu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xfpd_slcr.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xfpd_slcr_secure.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_iou_secure_slcr.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_iou_slcr.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_slcr.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_slcr_secure.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_xppu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xocm_xmpu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_iou_secure_slcr.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_iou_slcr.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_xmpu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_xppu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu0_cfg.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu1_cfg.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu2_cfg.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu3_cfg.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu4_cfg.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu5_cfg.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_slcr.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_slcr_secure.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_xmpu_cfg.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_xmpu_sink.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xiou_secure_slcr.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xiou_slcr.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_slcr.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_slcr_secure.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_xppu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_xppu_sink.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xocm_xmpu_cfg.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/xarmv8.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/xarmv8_config.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/armclang/_sys_close.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/armclang/_sys_exit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/armclang/_sys_iserror.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/armclang/_sys_istty.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/armclang/_sys_open.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/armclang/_sys_read.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/armclang/_sys_time.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/armclang/_sys_write.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/_exit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/_open.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/_sbrk.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/abort.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/close.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/cpputest_time.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/errno.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/fcntl.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/fstat.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/getentropy.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/getpid.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/isatty.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/kill.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/lseek.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/open.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/read.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/sbrk.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/time.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/unlink.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/write.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/xpseudo_asm_gcc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/abort.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/clock.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/close.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/exit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/low_level_init.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/lseek.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/open.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/read.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/remove.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/write.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/xpseudo_asm_iccarm.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/xpseudo_asm_iccarm.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/putnum.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/vectors.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/vectors.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/xil_exception.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/xil_exception.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/xil_sleeptimer.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/xil_sleeptimer.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/xil_spinlock.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/xil_spinlock.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/xpm_counter.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/ARM_argv_veneer.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/_sys_close.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/_sys_exit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/_sys_iserror.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/_sys_istty.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/_sys_open.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/_sys_read.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/_sys_time.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/_sys_write.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/asm_vectors.s create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/boot.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/translation_table.s create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/xpseudo_asm_rvct.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/xpseudo_asm_rvct.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/gcc/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/gcc/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/gcc/asm_vectors.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/gcc/boot.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/gcc/cpu_init.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/gcc/translation_table.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/gcc/xil-crt0.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/iccarm/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/iccarm/asm_vectors.s create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/iccarm/boot.s create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/iccarm/translation_table.s create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/sleep.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/smc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/usleep.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xcortexa9.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xcortexa9_config.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xil_cache.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xil_cache.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xil_cache_l.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xil_errata.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xil_misc_psreset_api.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xil_misc_psreset_api.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xil_mmu.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xil_mmu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xl2cc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xl2cc_counter.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xl2cc_counter.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xparameters_ps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xpm_counter.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xpseudo_asm.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xreg_cortexa9.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xtime_l.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xtime_l.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/armclang/ARM_argv_veneer.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/armclang/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/armclang/asm_vectors.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/armclang/boot.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/armclang/cpu_init.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/armclang/xil-crt0.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/armclang/xpseudo_asm_armclang.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/gcc/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/gcc/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/gcc/asm_vectors.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/gcc/boot.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/gcc/cpu_init.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/gcc/xil-crt0.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/iccarm/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/iccarm/asm_vectors.s create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/iccarm/boot.s create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/CortexR5/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/CortexR5/xcortexr5.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/CortexR5/xcortexr5_config.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/CortexR5/xil_mpu_r5.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/CortexR5/xil_mpu_r5.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/CortexR52/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/CortexR52/xcortexr52.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/CortexR52/xcortexr52_config.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/CortexR52/xil_mpu_r52.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/CortexR52/xil_mpu_r52.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/ZynqMP/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/ZynqMP/mpu_r5.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/ZynqMP/xparameters_ps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/versal-net/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/versal-net/mpu_r52.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/versal/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/versal/mpu_r5.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/versal/xparameters_ps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/sleep.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/usleep.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/xil_cache.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/xil_cache.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/xil_mmu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/xpm_counter.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/xpseudo_asm.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/xreg_cortexr5.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/xtime_l.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/xtime_l.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/platform/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/platform/versal_net/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/platform/versal_net/xparameters_ps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/asm_vectors.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/boot.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/bspconfig.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/bspconfig.h.in create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/changelog.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/clocking/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/clocking/xil_clocking.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/clocking/xil_clocking.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/close.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/clocking/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/clocking/xil_clocking.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/clocking/xil_clocking.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/inbyte.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/intr/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/intr/xinterrupt_wrap.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/intr/xinterrupt_wrap.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/outbyte.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/pm_api_version.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/print.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/sleep.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/versal/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/versal/xil_error_node.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/versal/xil_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/versal_net/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/versal_net/xil_error_node.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/versal_net/xil_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xbasic_types.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xdebug.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xenv.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xenv_standalone.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_assert.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_assert.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_cache_vxworks.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_cryptoalginfo.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_hal.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_io.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_macroback.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_mem.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_mem.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_printf.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_printf.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_sleepcommon.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_testcache.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_testcache.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_testio.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_testio.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_testmem.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_testmem.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_types.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_util.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_util.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xplatform_info.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xplatform_info.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xpm_init.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xpm_init.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xstatus.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/config.make create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/cpputest_time.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/cpu_init.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/errno.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/fcntl.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/fstat.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/getentropy.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/getpid.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/inbyte.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/intr/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/intr/xinterrupt_wrap.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/intr/xinterrupt_wrap.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/isatty.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/kill.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/lseek.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/_exit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/errno.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/fcntl.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/fsl.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/hw_exception_handler.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/mb_interface.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_disable_dcache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_disable_exceptions.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_disable_icache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_disable_interrupts.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_enable_dcache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_enable_exceptions.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_enable_icache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_enable_interrupts.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_exception_handler.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_exceptions_g.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_exceptions_i.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_flush_cache_ext.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_flush_cache_ext_range.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_flush_dcache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_flush_dcache_range.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_init_dcache_range.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_init_icache_range.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_instructions.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_interrupt_handler.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_interrupts_g.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_interrupts_i.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_invalidate_cache_ext.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_invalidate_cache_ext_range.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_invalidate_dcache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_invalidate_dcache_range.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_invalidate_icache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_invalidate_icache_range.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_scrub.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_selftest.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_sleep.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_sleep.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_update_dcache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_update_icache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/pvr.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/pvr.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/xil_cache.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/xil_cache.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/xil_exception.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/xil_exception.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/xil_misc_psreset_api.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/xil_misc_psreset_api.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/xio.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/xio.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/xmicroblaze.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/xmicroblaze_config.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/open.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/outbyte.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/pm_api_version.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/print.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/_profile_clean.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/_profile_init.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/_profile_timer_hw.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/_profile_timer_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/dummy.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/mblaze_nt_types.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/profile.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/profile_cg.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/profile_config.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/profile_hist.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/profile_mcount_arm.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/profile_mcount_mb.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/profile_mcount_ppc.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/putnum.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/read.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/_exit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/_open.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/_sbrk.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/boot.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/close.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/errno.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/fcntl.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/fsl.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/fstat.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/read.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_disable_interrupts.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_enable_interrupts.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_exceptions_g.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_flush_dcache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_flush_dcache_range.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_flush_icache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_flush_icache_range.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_interface.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_interrupt_handler.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_invalidate_dcache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_invalidate_dcache_range.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_invalidate_icache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_invalidate_icache_range.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_scrub.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_sleep.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_sleep.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/trap_handler.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/write.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/xil_cache.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/xil_exception.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/xil_exception.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/xmicroblaze_riscv.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/xmicroblaze_riscv_config.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/xpseudo_asm.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/xpseudo_asm_gcc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/xreg_riscv.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/sbrk.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/sleep.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/sleep.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/smc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/time.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/translation_table.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/unlink.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/usleep.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/vectors.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/vectors.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/versal/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/versal/xil_error_node.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/versal/xil_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/versal_net/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/versal_net/xil_error_node.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/versal_net/xil_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/write.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xbasic_types.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xcortexa9.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xcortexa9_config.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xdebug.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xenv.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xenv_standalone.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil-crt0.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_assert.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_assert.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_cache.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_cache.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_cache_l.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_cache_vxworks.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_clocking.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_clocking.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_cryptoalginfo.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_errata.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_exception.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_exception.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_hal.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_io.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_macroback.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_mem.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_mem.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_misc_psreset_api.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_misc_psreset_api.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_mmu.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_mmu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_printf.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_printf.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_sleepcommon.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_sleeptimer.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_sleeptimer.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_spinlock.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_spinlock.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_testcache.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_testcache.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_testio.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_testio.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_testmem.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_testmem.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_types.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_util.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_util.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xilstandalone.cmake create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xinterrupt_wrap.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xinterrupt_wrap.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xl2cc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xl2cc_counter.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xl2cc_counter.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xparameters_ps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xplatform_info.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xplatform_info.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xpm_counter.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xpm_counter.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xpm_init.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xpm_init.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xpseudo_asm.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xpseudo_asm_gcc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xreg_cortexa9.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xstatus.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xtime_l.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xtime_l.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_14/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_14/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_14/src/xuartps.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_14/src/xuartps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_14/src/xuartps_g.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_14/src/xuartps_hw.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_14/src/xuartps_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_14/src/xuartps_intr.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_14/src/xuartps_options.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_14/src/xuartps_selftest.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/uartps_v3_14/src/xuartps_sinit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_g.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_intr.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_selftest.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_sinit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/ps7_cortexa9_0/standalone_domain/bsp/system.mss create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/resources/dx_sig_platform/standalone_domain/qemu/qemu_args.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/resources/dx_sig_platform/standalone_domain/qemu_args.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/Xilinx.spec create mode 100755 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/fsbl.elf create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/fsbl.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/fsbl_debug.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/fsbl_handoff.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/fsbl_hooks.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/fsbl_hooks.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/image_mover.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/image_mover.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/lscript.ld create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/main.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/md5.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/md5.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/nand.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/nand.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/nor.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/nor.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/pcap.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/pcap.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/ps7_init.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/ps7_init.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/ps7_parameters.xml create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/qspi.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/qspi.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/rsa.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/rsa.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/sd.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/sd.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/dep.mk create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/_profile_timer_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/bspconfig.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/diskio.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/ff.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/ffconf.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/mblaze_nt_types.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/pm_api_version.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/profile.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/sleep.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/smc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/vectors.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xadcps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xadcps_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xbasic_types.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcoresightpsdcc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcortexa9.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcortexa9_config.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xcpu_cortexa9.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xddrps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdebug.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdevcfg.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdevcfg_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdmaps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xdmaps_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xenv.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xenv_standalone.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xgpiops.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xgpiops_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_assert.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache_l.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cache_vxworks.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_clocking.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_cryptoalginfo.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_errata.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_exception.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_hal.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_io.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_macroback.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_mem.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_misc_psreset_api.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_mmu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_printf.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_sleeptimer.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_spinlock.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testcache.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testio.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_testmem.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_types.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xil_util.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xilffs.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xilrsa.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xinterrupt_wrap.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xl2cc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xl2cc_counter.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xparameters.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xparameters_ps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xplatform_info.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpm_counter.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpm_init.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpseudo_asm.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xpseudo_asm_gcc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xqspips.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xqspips_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xreg_cortexa9.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscugic.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscugic_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscutimer.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscutimer_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscuwdt.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xscuwdt_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xstatus.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xtime_l.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xuartps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/include/xuartps_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_10/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_10/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_10/src/xcoresightpsdcc.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/coresightps_dcc_v1_10/src/xcoresightpsdcc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/cpu_cortexa9_v2_12/src/xcpu_cortexa9.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_2/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/ddrps_v1_2/src/xddrps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_g.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_hw.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_intr.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_selftest.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/devcfg_v3_8/src/xdevcfg_sinit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_10/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_10/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_10/src/xdmaps.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_10/src/xdmaps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_10/src/xdmaps_g.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_10/src/xdmaps_hw.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_10/src/xdmaps_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_10/src/xdmaps_selftest.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/dmaps_v2_10/src/xdmaps_sinit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_13/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_13/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_13/src/xgpiops.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_13/src/xgpiops.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_13/src/xgpiops_g.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_13/src/xgpiops_hw.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_13/src/xgpiops_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_13/src/xgpiops_intr.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_13/src/xgpiops_selftest.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/gpiops_v3_13/src/xgpiops_sinit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_12/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_12/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_12/src/xqspips.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_12/src/xqspips.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_12/src/xqspips_g.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_12/src/xqspips_hw.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_12/src/xqspips_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_12/src/xqspips_options.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_12/src/xqspips_selftest.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/qspips_v3_12/src/xqspips_sinit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_3/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_3/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_3/src/xscugic.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_3/src/xscugic.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_3/src/xscugic_g.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_3/src/xscugic_hw.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_3/src/xscugic_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_3/src/xscugic_intr.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_3/src/xscugic_selftest.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scugic_v5_3/src/xscugic_sinit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_6/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_6/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_6/src/xscutimer.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_6/src/xscutimer.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_6/src/xscutimer_g.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_6/src/xscutimer_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_6/src/xscutimer_selftest.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scutimer_v2_6/src/xscutimer_sinit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_g.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_selftest.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/scuwdt_v2_5/src/xscuwdt_sinit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/_exit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/_open.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/_sbrk.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/abort.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/gcc/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/gcc/asm_vectors.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/gcc/boot.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/gcc/cpu_init.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/gcc/xil-crt0.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/platform/ZynqMP/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/platform/ZynqMP/translation_table.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/platform/ZynqMP/xparameters_ps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/platform/versal/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/platform/versal/xparameters_ps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/sleep.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/usleep.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/xil_cache.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/xil_cache.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/xil_cache_l.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/xil_mmu.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/xil_mmu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/xparameters_ps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/xpseudo_asm.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/xreg_cortexa53.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/xtime_l.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/32bit/xtime_l.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/armclang/ARM_argv_veneer.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/armclang/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/armclang/asm_vectors.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/armclang/boot.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/armclang/xpseudo_asm_armclang.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/gcc/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/gcc/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/gcc/asm_vectors.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/gcc/boot.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/gcc/initialise_monitor_handles.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/gcc/xil-crt0.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/platform/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/platform/ZynqMP/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/platform/ZynqMP/armclang/translation_table.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/platform/ZynqMP/gcc/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/platform/ZynqMP/gcc/translation_table.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/platform/ZynqMP/xparameters_ps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/platform/versal/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/platform/versal/armclang/translation_table.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/platform/versal/gcc/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/platform/versal/gcc/translation_table.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/platform/versal/xparameters_ps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/sleep.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xil_cache.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xil_cache.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xil_errata.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xil_mmu.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xil_mmu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xil_smc.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xil_smc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xpm_counter.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xpseudo_asm.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xpvxenconsole/arm64_ops.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xpvxenconsole/hypercall.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xpvxenconsole/hypercall.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xpvxenconsole/xen.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xpvxenconsole/xen_console.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xpvxenconsole/xen_console.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xpvxenconsole/xen_events.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xpvxenconsole/xen_events.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xreg_cortexa53.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xtime_l.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/64bit/xtime_l.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xfpd_slave_xmpu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xfpd_slcr.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xfpd_slcr_secure.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_iou_secure_slcr.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_iou_slcr.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_slcr.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_slcr_secure.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xlpd_xppu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xocm_xmpu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_iou_secure_slcr.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_iou_slcr.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_xmpu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/Versal/xpmc_xppu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu0_cfg.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu1_cfg.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu2_cfg.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu3_cfg.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu4_cfg.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xddr_xmpu5_cfg.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_slcr.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_slcr_secure.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_xmpu_cfg.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xfpd_xmpu_sink.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xiou_secure_slcr.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xiou_slcr.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_slcr.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_slcr_secure.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_xppu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xlpd_xppu_sink.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/includes_ps/platform/ZynqMP/xocm_xmpu_cfg.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/xarmv8.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/ARMv8/xarmv8_config.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/armclang/_sys_close.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/armclang/_sys_exit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/armclang/_sys_iserror.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/armclang/_sys_istty.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/armclang/_sys_open.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/armclang/_sys_read.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/armclang/_sys_time.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/armclang/_sys_write.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/_exit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/_open.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/_sbrk.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/abort.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/close.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/cpputest_time.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/errno.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/fcntl.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/fstat.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/getentropy.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/getpid.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/isatty.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/kill.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/lseek.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/open.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/read.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/sbrk.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/time.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/unlink.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/write.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/gcc/xpseudo_asm_gcc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/abort.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/clock.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/close.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/exit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/low_level_init.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/lseek.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/open.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/read.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/remove.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/write.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/xpseudo_asm_iccarm.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/iccarm/xpseudo_asm_iccarm.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/putnum.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/vectors.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/vectors.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/xil_exception.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/xil_exception.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/xil_sleeptimer.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/xil_sleeptimer.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/xil_spinlock.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/xil_spinlock.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/common/xpm_counter.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/ARM_argv_veneer.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/_sys_close.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/_sys_exit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/_sys_iserror.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/_sys_istty.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/_sys_open.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/_sys_read.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/_sys_time.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/_sys_write.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/asm_vectors.s create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/boot.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/translation_table.s create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/xpseudo_asm_rvct.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/armcc/xpseudo_asm_rvct.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/gcc/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/gcc/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/gcc/asm_vectors.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/gcc/boot.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/gcc/cpu_init.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/gcc/translation_table.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/gcc/xil-crt0.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/iccarm/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/iccarm/asm_vectors.s create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/iccarm/boot.s create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/iccarm/translation_table.s create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/sleep.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/smc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/usleep.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xcortexa9.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xcortexa9_config.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xil_cache.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xil_cache.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xil_cache_l.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xil_errata.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xil_misc_psreset_api.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xil_misc_psreset_api.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xil_mmu.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xil_mmu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xl2cc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xl2cc_counter.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xl2cc_counter.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xparameters_ps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xpm_counter.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xpseudo_asm.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xreg_cortexa9.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xtime_l.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexa9/xtime_l.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/armclang/ARM_argv_veneer.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/armclang/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/armclang/asm_vectors.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/armclang/boot.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/armclang/cpu_init.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/armclang/xil-crt0.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/armclang/xpseudo_asm_armclang.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/gcc/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/gcc/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/gcc/asm_vectors.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/gcc/boot.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/gcc/cpu_init.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/gcc/xil-crt0.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/iccarm/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/iccarm/asm_vectors.s create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/iccarm/boot.s create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/CortexR5/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/CortexR5/xcortexr5.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/CortexR5/xcortexr5_config.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/CortexR5/xil_mpu_r5.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/CortexR5/xil_mpu_r5.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/CortexR52/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/CortexR52/xcortexr52.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/CortexR52/xcortexr52_config.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/CortexR52/xil_mpu_r52.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/CortexR52/xil_mpu_r52.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/ZynqMP/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/ZynqMP/mpu_r5.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/ZynqMP/xparameters_ps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/versal-net/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/versal-net/mpu_r52.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/versal/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/versal/mpu_r5.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/platform/versal/xparameters_ps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/sleep.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/usleep.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/xil_cache.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/xil_cache.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/xil_mmu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/xpm_counter.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/xpseudo_asm.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/xreg_cortexr5.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/xtime_l.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/cortexr5/xtime_l.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/platform/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/platform/versal_net/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/arm/platform/versal_net/xparameters_ps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/asm_vectors.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/boot.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/bspconfig.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/bspconfig.h.in create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/changelog.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/clocking/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/clocking/xil_clocking.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/clocking/xil_clocking.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/close.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/clocking/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/clocking/xil_clocking.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/clocking/xil_clocking.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/inbyte.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/intr/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/intr/xinterrupt_wrap.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/intr/xinterrupt_wrap.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/outbyte.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/pm_api_version.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/print.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/sleep.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/versal/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/versal/xil_error_node.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/versal/xil_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/versal_net/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/versal_net/xil_error_node.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/versal_net/xil_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xbasic_types.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xdebug.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xenv.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xenv_standalone.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_assert.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_assert.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_cache_vxworks.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_cryptoalginfo.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_hal.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_io.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_macroback.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_mem.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_mem.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_printf.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_printf.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_sleepcommon.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_testcache.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_testcache.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_testio.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_testio.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_testmem.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_testmem.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_types.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_util.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xil_util.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xplatform_info.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xplatform_info.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xpm_init.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xpm_init.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/common/xstatus.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/config.make create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/cpputest_time.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/cpu_init.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/errno.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/fcntl.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/fstat.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/getentropy.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/getpid.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/inbyte.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/intr/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/intr/xinterrupt_wrap.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/intr/xinterrupt_wrap.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/isatty.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/kill.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/lseek.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/_exit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/errno.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/fcntl.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/fsl.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/hw_exception_handler.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/mb_interface.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_disable_dcache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_disable_exceptions.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_disable_icache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_disable_interrupts.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_enable_dcache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_enable_exceptions.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_enable_icache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_enable_interrupts.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_exception_handler.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_exceptions_g.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_exceptions_i.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_flush_cache_ext.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_flush_cache_ext_range.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_flush_dcache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_flush_dcache_range.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_init_dcache_range.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_init_icache_range.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_instructions.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_interrupt_handler.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_interrupts_g.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_interrupts_i.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_invalidate_cache_ext.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_invalidate_cache_ext_range.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_invalidate_dcache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_invalidate_dcache_range.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_invalidate_icache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_invalidate_icache_range.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_scrub.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_selftest.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_sleep.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_sleep.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_update_dcache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/microblaze_update_icache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/pvr.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/pvr.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/xil_cache.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/xil_cache.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/xil_exception.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/xil_exception.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/xil_misc_psreset_api.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/xil_misc_psreset_api.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/xio.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/xio.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/xmicroblaze.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/microblaze/xmicroblaze_config.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/open.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/outbyte.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/pm_api_version.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/print.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/_profile_clean.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/_profile_init.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/_profile_timer_hw.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/_profile_timer_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/dummy.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/mblaze_nt_types.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/profile.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/profile_cg.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/profile_config.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/profile_hist.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/profile_mcount_arm.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/profile_mcount_mb.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/profile/profile_mcount_ppc.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/putnum.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/read.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/_exit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/_open.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/_sbrk.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/boot.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/close.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/errno.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/fcntl.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/fsl.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/fstat.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/read.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_disable_interrupts.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_enable_interrupts.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_exceptions_g.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_flush_dcache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_flush_dcache_range.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_flush_icache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_flush_icache_range.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_interface.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_interrupt_handler.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_invalidate_dcache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_invalidate_dcache_range.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_invalidate_icache.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_invalidate_icache_range.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_scrub.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_sleep.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/riscv_sleep.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/trap_handler.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/write.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/xil_cache.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/xil_exception.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/xil_exception.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/xmicroblaze_riscv.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/xmicroblaze_riscv_config.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/xpseudo_asm.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/xpseudo_asm_gcc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/riscv/xreg_riscv.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/sbrk.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/sleep.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/sleep.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/smc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/time.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/translation_table.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/unlink.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/usleep.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/vectors.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/vectors.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/versal/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/versal/xil_error_node.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/versal/xil_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/versal_net/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/versal_net/xil_error_node.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/versal_net/xil_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/write.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xbasic_types.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xcortexa9.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xcortexa9_config.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xdebug.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xenv.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xenv_standalone.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil-crt0.S create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_assert.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_assert.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_cache.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_cache.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_cache_l.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_cache_vxworks.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_clocking.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_clocking.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_cryptoalginfo.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_errata.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_exception.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_exception.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_hal.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_io.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_macroback.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_mem.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_mem.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_misc_psreset_api.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_misc_psreset_api.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_mmu.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_mmu.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_printf.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_printf.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_sleepcommon.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_sleeptimer.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_sleeptimer.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_spinlock.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_spinlock.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_testcache.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_testcache.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_testio.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_testio.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_testmem.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_testmem.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_types.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_util.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xil_util.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xilstandalone.cmake create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xinterrupt_wrap.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xinterrupt_wrap.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xl2cc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xl2cc_counter.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xl2cc_counter.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xparameters_ps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xplatform_info.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xplatform_info.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xpm_counter.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xpm_counter.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xpm_init.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xpm_init.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xpseudo_asm.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xpseudo_asm_gcc.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xreg_cortexa9.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xstatus.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xtime_l.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/standalone_v9_1/src/xtime_l.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_14/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_14/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_14/src/xuartps.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_14/src/xuartps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_14/src/xuartps_g.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_14/src/xuartps_hw.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_14/src/xuartps_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_14/src/xuartps_intr.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_14/src/xuartps_options.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_14/src/xuartps_selftest.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/uartps_v3_14/src/xuartps_sinit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_g.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_hw.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_intr.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_selftest.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xadcps_v2_7/src/xadcps_sinit.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_2/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_2/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_2/src/diskio.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_2/src/ff.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_2/src/ffsystem.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_2/src/ffunicode.c create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_2/src/include/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_2/src/include/diskio.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_2/src/include/ff.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_2/src/include/ffconf.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_2/src/include/xilffs.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_2/src/xilffs.cmake create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilffs_v5_2/src/xilffs_config.h.in create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilrsa_v1_8/src/CMakeLists.txt create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilrsa_v1_8/src/Makefile create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/ps7_cortexa9_0/libsrc/xilrsa_v1_8/src/include/xilrsa.h create mode 100644 vivado_pvt/projects/dx_sig/dx_sig_basic/vitis_classic/dx_sig_platform/zynq_fsbl/zynq_fsbl_bsp/system.mss diff --git a/vivado_pvt/.gitignore b/vivado_pvt/.gitignore index 548261c..93d6bad 100644 --- a/vivado_pvt/.gitignore +++ b/vivado_pvt/.gitignore @@ -57,37 +57,37 @@ ################################################################################ # include sdk directory and everything in it -!/projects/*/*/vitis/ -!/projects/*/*/vitis/** -/projects/*/*/vitis/**.log -/projects/*/*/vitis/.analytics +!/projects/*/*/vitis*/ +!/projects/*/*/vitis*/** +/projects/*/*/vitis*/**.log +/projects/*/*/vitis*/.analytics # exclude some obscure hidden SDK folders -/projects/*/*/vitis/.metadata/ -/projects/*/*/vitis/.sdk/ -/projects/*/*/vitis/RemoteSystemsTempFiles/ -/projects/*/*/vitis/webtalk/ +/projects/*/*/vitis*/.metadata/ +/projects/*/*/vitis*/.sdk/ +/projects/*/*/vitis*/RemoteSystemsTempFiles/ +/projects/*/*/vitis*/webtalk/ # hw_platform: exclude the entire hw_platform folder, as everything can be # generated from the .hdf file. Make sure to include the bitstream in the .hdf # file when exporting from Vivado! -/projects/*/*/vitis/*_hw_platform_*/ +/projects/*/*/vitis*/*_hw_platform_*/ # BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and # Makefile, ps lib files are regenerated automatically -/projects/*/*/vitis/*_bsp/* -!/projects/*/*/vitis/*_bsp/*.cproject -!/projects/*/*/vitis/*_bsp/*.project -!/projects/*/*/vitis/*_bsp/*.sdkproject -!/projects/*/*/vitis/*_bsp/system.mss -!/projects/*/*/vitis/*_bsp/Makefile +/projects/*/*/vitis*/*_bsp/* +!/projects/*/*/vitis*/*_bsp/*.cproject +!/projects/*/*/vitis*/*_bsp/*.project +!/projects/*/*/vitis*/*_bsp/*.sdkproject +!/projects/*/*/vitis*/*_bsp/system.mss +!/projects/*/*/vitis*/*_bsp/Makefile # Application: ignored file patterns, exclude Debug & Release folders -/projects/*/*/vitis/**/*.o -/projects/*/*/vitis/**/*.d -/projects/*/*/vitis/**/*.a -/projects/*/*/vitis/*/Debug/ -/projects/*/*/vitis/*/Release/ +/projects/*/*/vitis*/**/*.o +/projects/*/*/vitis*/**/*.d +/projects/*/*/vitis*/**/*.a +/projects/*/*/vitis*/*/Debug/ +/projects/*/*/vitis*/*/Release/ ################################################################################ diff --git a/vivado_pvt/projects/dx_sig/dx_sig_basic/README.md b/vivado_pvt/projects/dx_sig/dx_sig_basic/README.md new file mode 100644 index 0000000..b88c9d3 --- /dev/null +++ b/vivado_pvt/projects/dx_sig/dx_sig_basic/README.md @@ -0,0 +1,47 @@ +# README.md + +> Board: DX_2Z7100_AD9528_2AD9361_V1.0 +> +> Device: xc7z100ffg900-2 (U1), ad9528 (U7), ad9361 (u8), ad9361 (u9) +> +> Archiver: Josh Gao + +## 2024-09-26 + +- PL 增加编译选项，可以在 `system_top.v` 中定义 `AD9361_1_2T2R` 和 `AD9361_2_2T2R` 来启用 2T2R 时序，默认设置为 1T1R 模式。 + +- PL 的时钟基频改为 60 MHz，考虑到 GW 采样率为 56 Msps；但是可能造成 TT 工作时钟过快，需要使用时进行相应调整。 + +- PL 更改部分数据端口的命名。 + +- PS 按照最新的对飞 PS 架构进行修改，需要 Include `include` 文件夹。 + +- 修改 AD9361 的输入时钟为 40 MHz，二倍频接近 80 MHz 可以获得更好性能。 + +- 两片 AD9361 的频点分别按照 TT 和 GW 修改，均仅启用一个收发通道。 + +- 测试发送 EVM 约为 2%。 + +## 2024-09-12 + +1. 使用 PS 配置 AD9528 和两片 AD9361。 + +2. AD9528 相关 + + - 使用板上 50 MHz 晶振同时供给 VCO 和 REFA。 + + - AD9361 时钟为 25 MHz，其他时钟均为 200 MHz。 + +3. AD9361 配置相关 + + - 默认启用 Rx2A 和 Tx2A，因此接收通道仅 `rx_ch2_i/q` 和 `rx_ch4_i/q` 有数据，具体请结合原理图。 + + - 使用 25 MHz 时钟输入，采样率为 48 Msps，发送频率为 4125 MHz，接收频率为 125 MHz。 + +4. PL 相关 + + - PL 信号处理时钟 `sys_clk` 在 Clock Wizard 中为 50 MHz，但实际由 AD9361 输入随路时钟生成，频率为 48 MHz。 + +## 2024-09-11 + +- 初始版本，AD9361 使用 2T2R 模式。 diff --git a/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.runs/impl_1/debug_nets.ltx b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.runs/impl_1/debug_nets.ltx new file mode 100644 index 0000000..92414cb --- /dev/null +++ b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.runs/impl_1/debug_nets.ltx @@ -0,0 +1,796 @@ +{ + "ltx_root": { + "version": 4, + "minor": 0, + "ltx_data": [ + { + "name": "EDA_PROBESET", + "active": true, + "debug_cores": [ + { + "type": "XSDB_V3", + "name": "dbg_hub", + "spec": "labtools_xsdbm_v3", + "clk_input_freq_hz": "59998799" + }, + { + "type": "ILA_V3", + "name": "u_ila_trx", + "spec": "labtools_ila_v6", + "ipName": "ila", + "core_location": { + "user_chain": 1, + "slave_index": 0, + "bscan_switch_index": 0 + }, + "uuid": "B4AD3E48EFE85668933E662B3D102FF2", + "pins": [ + { + "name": "probe0", + "id": 0, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 0, + "nets": [ + { + "name": "tx_data_i", + "isBus": true, + "subnets": [ + { + "name": "tx_data_i[11]" + }, + { + "name": "tx_data_i[10]" + }, + { + "name": "tx_data_i[9]" + }, + { + "name": "tx_data_i[8]" + }, + { + "name": "tx_data_i[7]" + }, + { + "name": "tx_data_i[6]" + }, + { + "name": "tx_data_i[5]" + }, + { + "name": "tx_data_i[4]" + }, + { + "name": "tx_data_i[3]" + }, + { + "name": "tx_data_i[2]" + }, + { + "name": "tx_data_i[1]" + }, + { + "name": "tx_data_i[0]" + } + ] + } + ] + }, + { + "name": "probe1", + "id": 1, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 1, + "nets": [ + { + "name": "tx_data_q", + "isBus": true, + "subnets": [ + { + "name": "tx_data_q[11]" + }, + { + "name": "tx_data_q[10]" + }, + { + "name": "tx_data_q[9]" + }, + { + "name": "tx_data_q[8]" + }, + { + "name": "tx_data_q[7]" + }, + { + "name": "tx_data_q[6]" + }, + { + "name": "tx_data_q[5]" + }, + { + "name": "tx_data_q[4]" + }, + { + "name": "tx_data_q[3]" + }, + { + "name": "tx_data_q[2]" + }, + { + "name": "tx_data_q[1]" + }, + { + "name": "tx_data_q[0]" + } + ] + } + ] + }, + { + "name": "probe2", + "id": 2, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 2, + "nets": [ + { + "name": "rx1_ch1_i", + "isBus": true, + "subnets": [ + { + "name": "rx1_ch1_i[11]" + }, + { + "name": "rx1_ch1_i[10]" + }, + { + "name": "rx1_ch1_i[9]" + }, + { + "name": "rx1_ch1_i[8]" + }, + { + "name": "rx1_ch1_i[7]" + }, + { + "name": "rx1_ch1_i[6]" + }, + { + "name": "rx1_ch1_i[5]" + }, + { + "name": "rx1_ch1_i[4]" + }, + { + "name": "rx1_ch1_i[3]" + }, + { + "name": "rx1_ch1_i[2]" + }, + { + "name": "rx1_ch1_i[1]" + }, + { + "name": "rx1_ch1_i[0]" + } + ] + } + ] + }, + { + "name": "probe3", + "id": 3, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 3, + "nets": [ + { + "name": "rx1_ch1_q", + "isBus": true, + "subnets": [ + { + "name": "rx1_ch1_q[11]" + }, + { + "name": "rx1_ch1_q[10]" + }, + { + "name": "rx1_ch1_q[9]" + }, + { + "name": "rx1_ch1_q[8]" + }, + { + "name": "rx1_ch1_q[7]" + }, + { + "name": "rx1_ch1_q[6]" + }, + { + "name": "rx1_ch1_q[5]" + }, + { + "name": "rx1_ch1_q[4]" + }, + { + "name": "rx1_ch1_q[3]" + }, + { + "name": "rx1_ch1_q[2]" + }, + { + "name": "rx1_ch1_q[1]" + }, + { + "name": "rx1_ch1_q[0]" + } + ] + } + ] + }, + { + "name": "probe4", + "id": 4, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 4, + "nets": [ + { + "name": "rx1_ch2_i", + "isBus": true, + "subnets": [ + { + "name": "rx1_ch2_i[11]" + }, + { + "name": "rx1_ch2_i[10]" + }, + { + "name": "rx1_ch2_i[9]" + }, + { + "name": "rx1_ch2_i[8]" + }, + { + "name": "rx1_ch2_i[7]" + }, + { + "name": "rx1_ch2_i[6]" + }, + { + "name": "rx1_ch2_i[5]" + }, + { + "name": "rx1_ch2_i[4]" + }, + { + "name": "rx1_ch2_i[3]" + }, + { + "name": "rx1_ch2_i[2]" + }, + { + "name": "rx1_ch2_i[1]" + }, + { + "name": "rx1_ch2_i[0]" + } + ] + } + ] + }, + { + "name": "probe5", + "id": 5, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 5, + "nets": [ + { + "name": "rx1_ch2_q", + "isBus": true, + "subnets": [ + { + "name": "rx1_ch2_q[11]" + }, + { + "name": "rx1_ch2_q[10]" + }, + { + "name": "rx1_ch2_q[9]" + }, + { + "name": "rx1_ch2_q[8]" + }, + { + "name": "rx1_ch2_q[7]" + }, + { + "name": "rx1_ch2_q[6]" + }, + { + "name": "rx1_ch2_q[5]" + }, + { + "name": "rx1_ch2_q[4]" + }, + { + "name": "rx1_ch2_q[3]" + }, + { + "name": "rx1_ch2_q[2]" + }, + { + "name": "rx1_ch2_q[1]" + }, + { + "name": "rx1_ch2_q[0]" + } + ] + } + ] + }, + { + "name": "probe6", + "id": 6, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 6, + "nets": [ + { + "name": "rx2_ch1_i", + "isBus": true, + "subnets": [ + { + "name": "rx2_ch1_i[11]" + }, + { + "name": "rx2_ch1_i[10]" + }, + { + "name": "rx2_ch1_i[9]" + }, + { + "name": "rx2_ch1_i[8]" + }, + { + "name": "rx2_ch1_i[7]" + }, + { + "name": "rx2_ch1_i[6]" + }, + { + "name": "rx2_ch1_i[5]" + }, + { + "name": "rx2_ch1_i[4]" + }, + { + "name": "rx2_ch1_i[3]" + }, + { + "name": "rx2_ch1_i[2]" + }, + { + "name": "rx2_ch1_i[1]" + }, + { + "name": "rx2_ch1_i[0]" + } + ] + } + ] + }, + { + "name": "probe7", + "id": 7, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 7, + "nets": [ + { + "name": "rx2_ch1_q", + "isBus": true, + "subnets": [ + { + "name": "rx2_ch1_q[11]" + }, + { + "name": "rx2_ch1_q[10]" + }, + { + "name": "rx2_ch1_q[9]" + }, + { + "name": "rx2_ch1_q[8]" + }, + { + "name": "rx2_ch1_q[7]" + }, + { + "name": "rx2_ch1_q[6]" + }, + { + "name": "rx2_ch1_q[5]" + }, + { + "name": "rx2_ch1_q[4]" + }, + { + "name": "rx2_ch1_q[3]" + }, + { + "name": "rx2_ch1_q[2]" + }, + { + "name": "rx2_ch1_q[1]" + }, + { + "name": "rx2_ch1_q[0]" + } + ] + } + ] + }, + { + "name": "probe8", + "id": 8, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 8, + "nets": [ + { + "name": "rx2_ch2_i", + "isBus": true, + "subnets": [ + { + "name": "rx2_ch2_i[11]" + }, + { + "name": "rx2_ch2_i[10]" + }, + { + "name": "rx2_ch2_i[9]" + }, + { + "name": "rx2_ch2_i[8]" + }, + { + "name": "rx2_ch2_i[7]" + }, + { + "name": "rx2_ch2_i[6]" + }, + { + "name": "rx2_ch2_i[5]" + }, + { + "name": "rx2_ch2_i[4]" + }, + { + "name": "rx2_ch2_i[3]" + }, + { + "name": "rx2_ch2_i[2]" + }, + { + "name": "rx2_ch2_i[1]" + }, + { + "name": "rx2_ch2_i[0]" + } + ] + } + ] + }, + { + "name": "probe9", + "id": 9, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 9, + "nets": [ + { + "name": "rx2_ch2_q", + "isBus": true, + "subnets": [ + { + "name": "rx2_ch2_q[11]" + }, + { + "name": "rx2_ch2_q[10]" + }, + { + "name": "rx2_ch2_q[9]" + }, + { + "name": "rx2_ch2_q[8]" + }, + { + "name": "rx2_ch2_q[7]" + }, + { + "name": "rx2_ch2_q[6]" + }, + { + "name": "rx2_ch2_q[5]" + }, + { + "name": "rx2_ch2_q[4]" + }, + { + "name": "rx2_ch2_q[3]" + }, + { + "name": "rx2_ch2_q[2]" + }, + { + "name": "rx2_ch2_q[1]" + }, + { + "name": "rx2_ch2_q[0]" + } + ] + } + ] + } + ] + }, + { + "type": "VIO_V2", + "name": "u_vio_manual_ctrl", + "spec": "labtools_vio_v3", + "ipName": "vio", + "core_location": { + "user_chain": 1, + "slave_index": 1, + "bscan_switch_index": 0 + }, + "uuid": "6DFBBD640CB857419C054C66C7EA7B27", + "pins": [ + { + "name": "probe_out0", + "id": 10, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 1, + "portIndex": 0, + "nets": [ + { + "name": "waveform_sel", + "isBus": true, + "subnets": [ + { + "name": "waveform_sel[1]" + }, + { + "name": "waveform_sel[0]" + } + ] + } + ] + }, + { + "name": "probe_out1", + "id": 11, + "type": "DATA", + "direction": "OUT", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 1, + "nets": [ + { + "name": "sweep_on", + "isBus": false + } + ] + }, + { + "name": "probe_out2", + "id": 12, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 31, + "portIndex": 2, + "nets": [ + { + "name": "freq_set", + "isBus": true, + "subnets": [ + { + "name": "freq_set[31]" + }, + { + "name": "freq_set[30]" + }, + { + "name": "freq_set[29]" + }, + { + "name": "freq_set[28]" + }, + { + "name": "freq_set[27]" + }, + { + "name": "freq_set[26]" + }, + { + "name": "freq_set[25]" + }, + { + "name": "freq_set[24]" + }, + { + "name": "freq_set[23]" + }, + { + "name": "freq_set[22]" + }, + { + "name": "freq_set[21]" + }, + { + "name": "freq_set[20]" + }, + { + "name": "freq_set[19]" + }, + { + "name": "freq_set[18]" + }, + { + "name": "freq_set[17]" + }, + { + "name": "freq_set[16]" + }, + { + "name": "freq_set[15]" + }, + { + "name": "freq_set[14]" + }, + { + "name": "freq_set[13]" + }, + { + "name": "freq_set[12]" + }, + { + "name": "freq_set[11]" + }, + { + "name": "freq_set[10]" + }, + { + "name": "freq_set[9]" + }, + { + "name": "freq_set[8]" + }, + { + "name": "freq_set[7]" + }, + { + "name": "freq_set[6]" + }, + { + "name": "freq_set[5]" + }, + { + "name": "freq_set[4]" + }, + { + "name": "freq_set[3]" + }, + { + "name": "freq_set[2]" + }, + { + "name": "freq_set[1]" + }, + { + "name": "freq_set[0]" + } + ] + } + ] + }, + { + "name": "probe_out3", + "id": 13, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 1, + "portIndex": 3, + "nets": [ + { + "name": "iq_sel", + "isBus": true, + "subnets": [ + { + "name": "iq_sel[1]" + }, + { + "name": "iq_sel[0]" + } + ] + } + ] + }, + { + "name": "probe_out4", + "id": 14, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 3, + "portIndex": 4, + "nets": [ + { + "name": "bb_rshift", + "isBus": true, + "subnets": [ + { + "name": "bb_rshift[3]" + }, + { + "name": "bb_rshift[2]" + }, + { + "name": "bb_rshift[1]" + }, + { + "name": "bb_rshift[0]" + } + ] + } + ] + } + ] + } + ] + } + ] + } +} \ No newline at end of file diff --git a/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.runs/impl_1/system_top.bit b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.runs/impl_1/system_top.bit new file mode 100644 index 0000000..ba340c2 --- /dev/null +++ b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.runs/impl_1/system_top.bit @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:739e83a950fd5f682d27c15baf60726bda36cee544280aea3a1e9ea112620e7c +size 17416454 diff --git a/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.runs/impl_1/system_top.ltx b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.runs/impl_1/system_top.ltx new file mode 100644 index 0000000..92414cb --- /dev/null +++ b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.runs/impl_1/system_top.ltx @@ -0,0 +1,796 @@ +{ + "ltx_root": { + "version": 4, + "minor": 0, + "ltx_data": [ + { + "name": "EDA_PROBESET", + "active": true, + "debug_cores": [ + { + "type": "XSDB_V3", + "name": "dbg_hub", + "spec": "labtools_xsdbm_v3", + "clk_input_freq_hz": "59998799" + }, + { + "type": "ILA_V3", + "name": "u_ila_trx", + "spec": "labtools_ila_v6", + "ipName": "ila", + "core_location": { + "user_chain": 1, + "slave_index": 0, + "bscan_switch_index": 0 + }, + "uuid": "B4AD3E48EFE85668933E662B3D102FF2", + "pins": [ + { + "name": "probe0", + "id": 0, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 0, + "nets": [ + { + "name": "tx_data_i", + "isBus": true, + "subnets": [ + { + "name": "tx_data_i[11]" + }, + { + "name": "tx_data_i[10]" + }, + { + "name": "tx_data_i[9]" + }, + { + "name": "tx_data_i[8]" + }, + { + "name": "tx_data_i[7]" + }, + { + "name": "tx_data_i[6]" + }, + { + "name": "tx_data_i[5]" + }, + { + "name": "tx_data_i[4]" + }, + { + "name": "tx_data_i[3]" + }, + { + "name": "tx_data_i[2]" + }, + { + "name": "tx_data_i[1]" + }, + { + "name": "tx_data_i[0]" + } + ] + } + ] + }, + { + "name": "probe1", + "id": 1, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 1, + "nets": [ + { + "name": "tx_data_q", + "isBus": true, + "subnets": [ + { + "name": "tx_data_q[11]" + }, + { + "name": "tx_data_q[10]" + }, + { + "name": "tx_data_q[9]" + }, + { + "name": "tx_data_q[8]" + }, + { + "name": "tx_data_q[7]" + }, + { + "name": "tx_data_q[6]" + }, + { + "name": "tx_data_q[5]" + }, + { + "name": "tx_data_q[4]" + }, + { + "name": "tx_data_q[3]" + }, + { + "name": "tx_data_q[2]" + }, + { + "name": "tx_data_q[1]" + }, + { + "name": "tx_data_q[0]" + } + ] + } + ] + }, + { + "name": "probe2", + "id": 2, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 2, + "nets": [ + { + "name": "rx1_ch1_i", + "isBus": true, + "subnets": [ + { + "name": "rx1_ch1_i[11]" + }, + { + "name": "rx1_ch1_i[10]" + }, + { + "name": "rx1_ch1_i[9]" + }, + { + "name": "rx1_ch1_i[8]" + }, + { + "name": "rx1_ch1_i[7]" + }, + { + "name": "rx1_ch1_i[6]" + }, + { + "name": "rx1_ch1_i[5]" + }, + { + "name": "rx1_ch1_i[4]" + }, + { + "name": "rx1_ch1_i[3]" + }, + { + "name": "rx1_ch1_i[2]" + }, + { + "name": "rx1_ch1_i[1]" + }, + { + "name": "rx1_ch1_i[0]" + } + ] + } + ] + }, + { + "name": "probe3", + "id": 3, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 3, + "nets": [ + { + "name": "rx1_ch1_q", + "isBus": true, + "subnets": [ + { + "name": "rx1_ch1_q[11]" + }, + { + "name": "rx1_ch1_q[10]" + }, + { + "name": "rx1_ch1_q[9]" + }, + { + "name": "rx1_ch1_q[8]" + }, + { + "name": "rx1_ch1_q[7]" + }, + { + "name": "rx1_ch1_q[6]" + }, + { + "name": "rx1_ch1_q[5]" + }, + { + "name": "rx1_ch1_q[4]" + }, + { + "name": "rx1_ch1_q[3]" + }, + { + "name": "rx1_ch1_q[2]" + }, + { + "name": "rx1_ch1_q[1]" + }, + { + "name": "rx1_ch1_q[0]" + } + ] + } + ] + }, + { + "name": "probe4", + "id": 4, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 4, + "nets": [ + { + "name": "rx1_ch2_i", + "isBus": true, + "subnets": [ + { + "name": "rx1_ch2_i[11]" + }, + { + "name": "rx1_ch2_i[10]" + }, + { + "name": "rx1_ch2_i[9]" + }, + { + "name": "rx1_ch2_i[8]" + }, + { + "name": "rx1_ch2_i[7]" + }, + { + "name": "rx1_ch2_i[6]" + }, + { + "name": "rx1_ch2_i[5]" + }, + { + "name": "rx1_ch2_i[4]" + }, + { + "name": "rx1_ch2_i[3]" + }, + { + "name": "rx1_ch2_i[2]" + }, + { + "name": "rx1_ch2_i[1]" + }, + { + "name": "rx1_ch2_i[0]" + } + ] + } + ] + }, + { + "name": "probe5", + "id": 5, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 5, + "nets": [ + { + "name": "rx1_ch2_q", + "isBus": true, + "subnets": [ + { + "name": "rx1_ch2_q[11]" + }, + { + "name": "rx1_ch2_q[10]" + }, + { + "name": "rx1_ch2_q[9]" + }, + { + "name": "rx1_ch2_q[8]" + }, + { + "name": "rx1_ch2_q[7]" + }, + { + "name": "rx1_ch2_q[6]" + }, + { + "name": "rx1_ch2_q[5]" + }, + { + "name": "rx1_ch2_q[4]" + }, + { + "name": "rx1_ch2_q[3]" + }, + { + "name": "rx1_ch2_q[2]" + }, + { + "name": "rx1_ch2_q[1]" + }, + { + "name": "rx1_ch2_q[0]" + } + ] + } + ] + }, + { + "name": "probe6", + "id": 6, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 6, + "nets": [ + { + "name": "rx2_ch1_i", + "isBus": true, + "subnets": [ + { + "name": "rx2_ch1_i[11]" + }, + { + "name": "rx2_ch1_i[10]" + }, + { + "name": "rx2_ch1_i[9]" + }, + { + "name": "rx2_ch1_i[8]" + }, + { + "name": "rx2_ch1_i[7]" + }, + { + "name": "rx2_ch1_i[6]" + }, + { + "name": "rx2_ch1_i[5]" + }, + { + "name": "rx2_ch1_i[4]" + }, + { + "name": "rx2_ch1_i[3]" + }, + { + "name": "rx2_ch1_i[2]" + }, + { + "name": "rx2_ch1_i[1]" + }, + { + "name": "rx2_ch1_i[0]" + } + ] + } + ] + }, + { + "name": "probe7", + "id": 7, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 7, + "nets": [ + { + "name": "rx2_ch1_q", + "isBus": true, + "subnets": [ + { + "name": "rx2_ch1_q[11]" + }, + { + "name": "rx2_ch1_q[10]" + }, + { + "name": "rx2_ch1_q[9]" + }, + { + "name": "rx2_ch1_q[8]" + }, + { + "name": "rx2_ch1_q[7]" + }, + { + "name": "rx2_ch1_q[6]" + }, + { + "name": "rx2_ch1_q[5]" + }, + { + "name": "rx2_ch1_q[4]" + }, + { + "name": "rx2_ch1_q[3]" + }, + { + "name": "rx2_ch1_q[2]" + }, + { + "name": "rx2_ch1_q[1]" + }, + { + "name": "rx2_ch1_q[0]" + } + ] + } + ] + }, + { + "name": "probe8", + "id": 8, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 8, + "nets": [ + { + "name": "rx2_ch2_i", + "isBus": true, + "subnets": [ + { + "name": "rx2_ch2_i[11]" + }, + { + "name": "rx2_ch2_i[10]" + }, + { + "name": "rx2_ch2_i[9]" + }, + { + "name": "rx2_ch2_i[8]" + }, + { + "name": "rx2_ch2_i[7]" + }, + { + "name": "rx2_ch2_i[6]" + }, + { + "name": "rx2_ch2_i[5]" + }, + { + "name": "rx2_ch2_i[4]" + }, + { + "name": "rx2_ch2_i[3]" + }, + { + "name": "rx2_ch2_i[2]" + }, + { + "name": "rx2_ch2_i[1]" + }, + { + "name": "rx2_ch2_i[0]" + } + ] + } + ] + }, + { + "name": "probe9", + "id": 9, + "type": "DATA_TRIGGER", + "direction": "IN", + "isVector": true, + "leftIndex": 0, + "rightIndex": 11, + "portIndex": 9, + "nets": [ + { + "name": "rx2_ch2_q", + "isBus": true, + "subnets": [ + { + "name": "rx2_ch2_q[11]" + }, + { + "name": "rx2_ch2_q[10]" + }, + { + "name": "rx2_ch2_q[9]" + }, + { + "name": "rx2_ch2_q[8]" + }, + { + "name": "rx2_ch2_q[7]" + }, + { + "name": "rx2_ch2_q[6]" + }, + { + "name": "rx2_ch2_q[5]" + }, + { + "name": "rx2_ch2_q[4]" + }, + { + "name": "rx2_ch2_q[3]" + }, + { + "name": "rx2_ch2_q[2]" + }, + { + "name": "rx2_ch2_q[1]" + }, + { + "name": "rx2_ch2_q[0]" + } + ] + } + ] + } + ] + }, + { + "type": "VIO_V2", + "name": "u_vio_manual_ctrl", + "spec": "labtools_vio_v3", + "ipName": "vio", + "core_location": { + "user_chain": 1, + "slave_index": 1, + "bscan_switch_index": 0 + }, + "uuid": "6DFBBD640CB857419C054C66C7EA7B27", + "pins": [ + { + "name": "probe_out0", + "id": 10, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 1, + "portIndex": 0, + "nets": [ + { + "name": "waveform_sel", + "isBus": true, + "subnets": [ + { + "name": "waveform_sel[1]" + }, + { + "name": "waveform_sel[0]" + } + ] + } + ] + }, + { + "name": "probe_out1", + "id": 11, + "type": "DATA", + "direction": "OUT", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 1, + "nets": [ + { + "name": "sweep_on", + "isBus": false + } + ] + }, + { + "name": "probe_out2", + "id": 12, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 31, + "portIndex": 2, + "nets": [ + { + "name": "freq_set", + "isBus": true, + "subnets": [ + { + "name": "freq_set[31]" + }, + { + "name": "freq_set[30]" + }, + { + "name": "freq_set[29]" + }, + { + "name": "freq_set[28]" + }, + { + "name": "freq_set[27]" + }, + { + "name": "freq_set[26]" + }, + { + "name": "freq_set[25]" + }, + { + "name": "freq_set[24]" + }, + { + "name": "freq_set[23]" + }, + { + "name": "freq_set[22]" + }, + { + "name": "freq_set[21]" + }, + { + "name": "freq_set[20]" + }, + { + "name": "freq_set[19]" + }, + { + "name": "freq_set[18]" + }, + { + "name": "freq_set[17]" + }, + { + "name": "freq_set[16]" + }, + { + "name": "freq_set[15]" + }, + { + "name": "freq_set[14]" + }, + { + "name": "freq_set[13]" + }, + { + "name": "freq_set[12]" + }, + { + "name": "freq_set[11]" + }, + { + "name": "freq_set[10]" + }, + { + "name": "freq_set[9]" + }, + { + "name": "freq_set[8]" + }, + { + "name": "freq_set[7]" + }, + { + "name": "freq_set[6]" + }, + { + "name": "freq_set[5]" + }, + { + "name": "freq_set[4]" + }, + { + "name": "freq_set[3]" + }, + { + "name": "freq_set[2]" + }, + { + "name": "freq_set[1]" + }, + { + "name": "freq_set[0]" + } + ] + } + ] + }, + { + "name": "probe_out3", + "id": 13, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 1, + "portIndex": 3, + "nets": [ + { + "name": "iq_sel", + "isBus": true, + "subnets": [ + { + "name": "iq_sel[1]" + }, + { + "name": "iq_sel[0]" + } + ] + } + ] + }, + { + "name": "probe_out4", + "id": 14, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 3, + "portIndex": 4, + "nets": [ + { + "name": "bb_rshift", + "isBus": true, + "subnets": [ + { + "name": "bb_rshift[3]" + }, + { + "name": "bb_rshift[2]" + }, + { + "name": "bb_rshift[1]" + }, + { + "name": "bb_rshift[0]" + } + ] + } + ] + } + ] + } + ] + } + ] + } +} \ No newline at end of file diff --git a/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/constrs_1/new/dx_z7100_ad9528_2ad9361_physical.xdc b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/constrs_1/new/dx_z7100_ad9528_2ad9361_physical.xdc new file mode 100644 index 0000000..8f982ab --- /dev/null +++ b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/constrs_1/new/dx_z7100_ad9528_2ad9361_physical.xdc @@ -0,0 +1,229 @@ +# dx_2z7100_ad9528_2ad9361 + +## Timing Assertions Section + +## Physical Constraints Section + +# Clocks +set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVDS_25 } [get_ports refclk_1_p ] ;# F1_REFCLK1_P +set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVDS } [get_ports refclk_2_p ] ;# F1_REFCLK2_P +set_property -dict {PACKAGE_PIN AD10 } [get_ports gtclk_109_p ] ;# F1_GTCLK0_P +set_property -dict {PACKAGE_PIN AA8 } [get_ports gtclk_110_p ] ;# F1_GTCLK1_P +set_property -dict {PACKAGE_PIN N8 } [get_ports gtclk_112_p ] ;# F1_GTCLK2_P +set_property -dict {PACKAGE_PIN F5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_buffer_clk ] ;# AD9361_1_CLK_OUT +set_property -dict {PACKAGE_PIN H9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_buffer_clk ] ;# AD9361_2_CLK_OUT + +# AD9528 Interface +set_property -dict {PACKAGE_PIN W23 IOSTANDARD LVCMOS33} [get_ports ad9528_spi_csn ] ;# AD9528_SPI_CSB +set_property -dict {PACKAGE_PIN AJ25 IOSTANDARD LVCMOS33} [get_ports ad9528_spi_clk ] ;# AD9528_SPI_SCLK +set_property -dict {PACKAGE_PIN AK25 IOSTANDARD LVCMOS33} [get_ports ad9528_spi_mosi ] ;# AD9528_SPI_SDI +set_property -dict {PACKAGE_PIN AK22 IOSTANDARD LVCMOS33} [get_ports ad9528_spi_miso ] ;# AD9528_SPI_SDO + +set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS33} [get_ports ad9528_status[0] ] ;# AD9528_STATUS0 +set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS33} [get_ports ad9528_status[1] ] ;# AD9528_STATUS1 +set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS33} [get_ports ad9528_reset_b ] ;# AD9528_RESETB +set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS33} [get_ports ad9528_sysref_req ] ;# AD9528_SYSREF_REQ + +# AD9361-1 Interface +set_property -dict {PACKAGE_PIN G5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data_clk ] ;# AD9361_1_DATA_CLK_P +set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_frame ] ;# AD9361_1_RX_FRAME_P +set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[0] ] ;# AD9361_1_P0D00_TXD0_N +set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[1] ] ;# AD9361_1_P0D01_TXD0_P +set_property -dict {PACKAGE_PIN D5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[2] ] ;# AD9361_1_P0D02_TXD1_N +set_property -dict {PACKAGE_PIN E6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[3] ] ;# AD9361_1_P0D03_TXD1_P +set_property -dict {PACKAGE_PIN D3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[4] ] ;# AD9361_1_P0D04_TXD2_N +set_property -dict {PACKAGE_PIN D4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[5] ] ;# AD9361_1_P0D05_TXD2_P +set_property -dict {PACKAGE_PIN B4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[6] ] ;# AD9361_1_P0D06_TXD3_N +set_property -dict {PACKAGE_PIN B5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[7] ] ;# AD9361_1_P0D07_TXD3_P +set_property -dict {PACKAGE_PIN C3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[8] ] ;# AD9361_1_P0D08_TXD4_N +set_property -dict {PACKAGE_PIN C4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[9] ] ;# AD9361_1_P0D09_TXD4_P +set_property -dict {PACKAGE_PIN A4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[10] ] ;# AD9361_1_P0D10_TXD5_N +set_property -dict {PACKAGE_PIN A5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_rx_data[11] ] ;# AD9361_1_P0D11_TXD5_P + +set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_fb_clk ] ;# AD9361_1_FB_CLK_P +set_property -dict {PACKAGE_PIN L1 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_frame ] ;# AD9361_1_TX_FRAME_P +set_property -dict {PACKAGE_PIN J6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[0] ] ;# AD9361_1_P1D00_RXD0_N +set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[1] ] ;# AD9361_1_P1D01_RXD0_P +set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[2] ] ;# AD9361_1_P1D02_RXD1_N +set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[3] ] ;# AD9361_1_P1D03_RXD1_P +set_property -dict {PACKAGE_PIN F2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[4] ] ;# AD9361_1_P1D04_RXD2_N +set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[5] ] ;# AD9361_1_P1D05_RXD2_P +set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[6] ] ;# AD9361_1_P1D06_RXD3_N +set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[7] ] ;# AD9361_1_P1D07_RXD3_P +set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[8] ] ;# AD9361_1_P1D08_RXD4_N +set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[9] ] ;# AD9361_1_P1D09_RXD4_P +set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[10] ] ;# AD9361_1_P1D10_RXD5_N +set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS18} [get_ports ad9361_1_tx_data[11] ] ;# AD9361_1_P1D11_RXD5_P + +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_clk ] ;# AD9361_1_SPI_CLK +set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_csn ] ;# AD9361_1_SPI_ENB +set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_mosi ] ;# AD9361_1_SPI_DI +set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_spi_miso ] ;# AD9361_1_SPI_DO + +set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_reset_b ] ;# AD9361_1_RESETB +set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_en_agc ] ;# AD9361_1_EN_AGC +set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_enable ] ;# AD9361_1_ENABLE +set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS18} [get_ports ad9361_1_txnrx ] ;# AD9361_1_TXNRX + +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[0] ] ;# AD9361_1_CTRL_IN0 +set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[1] ] ;# AD9361_1_CTRL_IN1 +set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[2] ] ;# AD9361_1_CTRL_IN2 +set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_in[3] ] ;# AD9361_1_CTRL_IN3 + +set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[0] ] ;# AD9361_1_CTRL_OUT0 +set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[1] ] ;# AD9361_1_CTRL_OUT1 +set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[2] ] ;# AD9361_1_CTRL_OUT2 +set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[3] ] ;# AD9361_1_CTRL_OUT3 +set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[4] ] ;# AD9361_1_CTRL_OUT4 +set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[5] ] ;# AD9361_1_CTRL_OUT5 +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[6] ] ;# AD9361_1_CTRL_OUT6 +set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS18} [get_ports ad9361_1_ctrl_out[7] ] ;# AD9361_1_CTRL_OUT7 + +# AD9361-2 Interface +set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data_clk ] ;# AD9361_2_DATA_CLK_P +set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_frame ] ;# AD9361_2_RX_FRAME_P +set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[0] ] ;# AD9361_2_P0D00_TXD0_N +set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[1] ] ;# AD9361_2_P0D01_TXD0_P +set_property -dict {PACKAGE_PIN H8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[2] ] ;# AD9361_2_P0D02_TXD1_N +set_property -dict {PACKAGE_PIN J8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[3] ] ;# AD9361_2_P0D03_TXD1_P +set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[4] ] ;# AD9361_2_P0D04_TXD2_N +set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[5] ] ;# AD9361_2_P0D05_TXD2_P +set_property -dict {PACKAGE_PIN J9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[6] ] ;# AD9361_2_P0D06_TXD3_N +set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[7] ] ;# AD9361_2_P0D07_TXD3_P +set_property -dict {PACKAGE_PIN G7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[8] ] ;# AD9361_2_P0D08_TXD4_N +set_property -dict {PACKAGE_PIN H7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[9] ] ;# AD9361_2_P0D09_TXD4_P +set_property -dict {PACKAGE_PIN K8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[10] ] ;# AD9361_2_P0D10_TXD5_N +set_property -dict {PACKAGE_PIN L8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_rx_data[11] ] ;# AD9361_2_P0D11_TXD5_P + +set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_fb_clk ] ;# AD9361_2_FB_CLK_P +set_property -dict {PACKAGE_PIN C7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_frame ] ;# AD9361_2_TX_FRAME_P +set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[0] ] ;# AD9361_2_P1D00_RXD0_N +set_property -dict {PACKAGE_PIN B9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[1] ] ;# AD9361_2_P1D01_RXD0_P +set_property -dict {PACKAGE_PIN F7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[2] ] ;# AD9361_2_P1D02_RXD1_N +set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[3] ] ;# AD9361_2_P1D03_RXD1_P +set_property -dict {PACKAGE_PIN C8 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[4] ] ;# AD9361_2_P1D04_RXD2_N +set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[5] ] ;# AD9361_2_P1D05_RXD2_P +set_property -dict {PACKAGE_PIN D6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[6] ] ;# AD9361_2_P1D06_RXD3_N +set_property -dict {PACKAGE_PIN E7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[7] ] ;# AD9361_2_P1D07_RXD3_P +set_property -dict {PACKAGE_PIN K7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[8] ] ;# AD9361_2_P1D08_RXD4_N +set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[9] ] ;# AD9361_2_P1D09_RXD4_P +set_property -dict {PACKAGE_PIN B6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[10] ] ;# AD9361_2_P1D10_RXD5_N +set_property -dict {PACKAGE_PIN C6 IOSTANDARD LVCMOS18} [get_ports ad9361_2_tx_data[11] ] ;# AD9361_2_P1D11_RXD5_P + +set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_clk ] ;# AD9361_2_SPI_CLK +set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_csn ] ;# AD9361_2_SPI_ENB +set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_mosi ] ;# AD9361_2_SPI_DI +set_property -dict {PACKAGE_PIN A12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_spi_miso ] ;# AD9361_2_SPI_DO + +set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_reset_b ] ;# AD9361_2_RESETB +set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_en_agc ] ;# AD9361_2_EN_AGC +set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports ad9361_2_enable ] ;# AD9361_2_ENABLE +set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS18} [get_ports ad9361_2_txnrx ] ;# AD9361_2_TXNRX + +set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[0] ] ;# AD9361_2_CTRL_IN0 +set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[1] ] ;# AD9361_2_CTRL_IN1 +set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[2] ] ;# AD9361_2_CTRL_IN2 +set_property -dict {PACKAGE_PIN C16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_in[3] ] ;# AD9361_2_CTRL_IN3 + +set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[0] ] ;# AD9361_2_CTRL_OUT0 +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[1] ] ;# AD9361_2_CTRL_OUT1 +set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[2] ] ;# AD9361_2_CTRL_OUT2 +set_property -dict {PACKAGE_PIN C14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[3] ] ;# AD9361_2_CTRL_OUT3 +set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[4] ] ;# AD9361_2_CTRL_OUT4 +set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[5] ] ;# AD9361_2_CTRL_OUT5 +set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[6] ] ;# AD9361_2_CTRL_OUT6 +set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS18} [get_ports ad9361_2_ctrl_out[7] ] ;# AD9361_2_CTRL_OUT7 + +# Inter-FPGA Ports +set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[0] ] ;# LVDS_IO_GRP0_00P +set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[1] ] ;# LVDS_IO_GRP0_01P +set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[2] ] ;# LVDS_IO_GRP0_02P +set_property -dict {PACKAGE_PIN Y28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[3] ] ;# LVDS_IO_GRP0_03P +set_property -dict {PACKAGE_PIN AA27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[4] ] ;# LVDS_IO_GRP0_04P +set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[5] ] ;# LVDS_IO_GRP0_05P +set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[6] ] ;# LVDS_IO_GRP0_06P +set_property -dict {PACKAGE_PIN AD30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[7] ] ;# LVDS_IO_GRP0_07P +set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[8] ] ;# LVDS_IO_GRP0_08P +set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[9] ] ;# LVDS_IO_GRP0_09P +set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[10] ] ;# LVDS_IO_GRP0_10P +set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[11] ] ;# LVDS_IO_GRP0_11P +set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[12] ] ;# LVDS_IO_GRP0_12P +set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[13] ] ;# LVDS_IO_GRP0_13P +set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[14] ] ;# LVDS_IO_GRP0_14P +set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[15] ] ;# LVDS_IO_GRP0_15P +set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[16] ] ;# LVDS_IO_GRP0_16P +set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[17] ] ;# LVDS_IO_GRP0_17P +set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[18] ] ;# LVDS_IO_GRP0_18P +set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[19] ] ;# LVDS_IO_GRP0_19P +set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[20] ] ;# LVDS_IO_GRP0_20P +set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[21] ] ;# LVDS_IO_GRP0_21P +set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_1_p[22] ] ;# LVDS_IO_GRP0_22P + +set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[0] ] ;# LVDS_IO_GRP1_00P +set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[1] ] ;# LVDS_IO_GRP1_01P +set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[2] ] ;# LVDS_IO_GRP1_02P +set_property -dict {PACKAGE_PIN N28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[3] ] ;# LVDS_IO_GRP1_03P +set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[4] ] ;# LVDS_IO_GRP1_04P +set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[5] ] ;# LVDS_IO_GRP1_05P +set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[6] ] ;# LVDS_IO_GRP1_06P +set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[7] ] ;# LVDS_IO_GRP1_07P +set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[8] ] ;# LVDS_IO_GRP1_08P +set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[9] ] ;# LVDS_IO_GRP1_09P +set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[10] ] ;# LVDS_IO_GRP1_10P +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[11] ] ;# LVDS_IO_GRP1_11P +set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[12] ] ;# LVDS_IO_GRP1_12P +set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[13] ] ;# LVDS_IO_GRP1_13P +set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[14] ] ;# LVDS_IO_GRP1_14P +set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[15] ] ;# LVDS_IO_GRP1_15P +set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[16] ] ;# LVDS_IO_GRP1_16P +set_property -dict {PACKAGE_PIN R27 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[17] ] ;# LVDS_IO_GRP1_17P +set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[18] ] ;# LVDS_IO_GRP1_18P +set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[19] ] ;# LVDS_IO_GRP1_19P +set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[20] ] ;# LVDS_IO_GRP1_20P +set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[21] ] ;# LVDS_IO_GRP1_21P +set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVDS_25 } [get_ports if_lvds_io_2_p[22] ] ;# LVDS_IO_GRP1_22P + +set_property -dict {PACKAGE_PIN AH10 } [get_ports if_gtx_rxp[0] ] ;# GTX_F1R_F2T_00P +set_property -dict {PACKAGE_PIN AJ8 } [get_ports if_gtx_rxp[1] ] ;# GTX_F1R_F2T_01P +set_property -dict {PACKAGE_PIN AG8 } [get_ports if_gtx_rxp[2] ] ;# GTX_F1R_F2T_02P +set_property -dict {PACKAGE_PIN AE8 } [get_ports if_gtx_rxp[3] ] ;# GTX_F1R_F2T_03P +set_property -dict {PACKAGE_PIN AH6 } [get_ports if_gtx_rxp[4] ] ;# GTX_F1R_F2T_04P +set_property -dict {PACKAGE_PIN AG4 } [get_ports if_gtx_rxp[5] ] ;# GTX_F1R_F2T_05P +set_property -dict {PACKAGE_PIN AF6 } [get_ports if_gtx_rxp[6] ] ;# GTX_F1R_F2T_06P +set_property -dict {PACKAGE_PIN AD6 } [get_ports if_gtx_rxp[7] ] ;# GTX_F1R_F2T_07P + +# set_property -dict {PACKAGE_PIN AK10 } [get_ports if_gtx_txp[0] ] ;# GTX_F1T_F2R_00P +# set_property -dict {PACKAGE_PIN AK6 } [get_ports if_gtx_txp[1] ] ;# GTX_F1T_F2R_01P +# set_property -dict {PACKAGE_PIN AJ4 } [get_ports if_gtx_txp[2] ] ;# GTX_F1T_F2R_02P +# set_property -dict {PACKAGE_PIN AK2 } [get_ports if_gtx_txp[3] ] ;# GTX_F1T_F2R_03P +# set_property -dict {PACKAGE_PIN AH2 } [get_ports if_gtx_txp[4] ] ;# GTX_F1T_F2R_04P +# set_property -dict {PACKAGE_PIN AF2 } [get_ports if_gtx_txp[5] ] ;# GTX_F1T_F2R_05P +# set_property -dict {PACKAGE_PIN AE4 } [get_ports if_gtx_txp[6] ] ;# GTX_F1T_F2R_06P +# set_property -dict {PACKAGE_PIN AD2 } [get_ports if_gtx_txp[7] ] ;# GTX_F1T_F2R_07P + +# Inter-board Ports +set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVDS_25 } [get_ports ib_lvds_io_p[0] ] ;# F1_LVDS_IO1P +set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVDS_25 } [get_ports ib_lvds_io_p[1] ] ;# F1_LVDS_IO2P +set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25 } [get_ports ib_lvds_io_p[2] ] ;# F1_LVDS_IO3P +set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25 } [get_ports ib_lvds_io_p[3] ] ;# F1_LVDS_IO4P +set_property -dict {PACKAGE_PIN AH18 IOSTANDARD LVDS_25 } [get_ports ib_lvds_io_p[4] ] ;# F1_LVDS_IO5P + +set_property -dict {PACKAGE_PIN T2 } [get_ports ib_gtx_s2p_p[0] ] ;# F1_GTX0_S2P_P +set_property -dict {PACKAGE_PIN R4 } [get_ports ib_gtx_s2p_p[1] ] ;# F1_GTX1_S2P_P +set_property -dict {PACKAGE_PIN P2 } [get_ports ib_gtx_s2p_p[2] ] ;# F1_GTX2_S2P_P +set_property -dict {PACKAGE_PIN N4 } [get_ports ib_gtx_s2p_p[3] ] ;# F1_GTX3_S2P_P + +# set_property -dict {PACKAGE_PIN V6 } [get_ports ib_gtx_p2s_p[0] ] ;# F1_GTX0_P2S_P +# set_property -dict {PACKAGE_PIN U4 } [get_ports ib_gtx_p2s_p[1] ] ;# F1_GTX1_P2S_P +# set_property -dict {PACKAGE_PIN T6 } [get_ports ib_gtx_p2s_p[2] ] ;# F1_GTX2_P2S_P +# set_property -dict {PACKAGE_PIN P6 } [get_ports ib_gtx_p2s_p[3] ] ;# F1_GTX3_P2S_P + +# 3.3V Debug IO +set_property -dict {PACKAGE_PIN AA20 IOSTANDARD LVCMOS33} [get_ports uart_rxd ] ;# PL1_UART_RXD +set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports uart_txd ] ;# PL1_UART_TXD + +set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS33} [get_ports debug_io_1 ] ;# PL1_DEBUG_IO_1 +set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS33} [get_ports debug_io_2 ] ;# PL1_DEBUG_IO_2 +set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS33} [get_ports debug_io_3 ] ;# PL1_DEBUG_IO_3 +set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS33} [get_ports debug_io_4 ] ;# PL1_DEBUG_IO_4 +set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS33} [get_ports debug_io_5 ] ;# PL1_DEBUG_IO_5 diff --git a/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/common/ad_rst.v b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/common/ad_rst.v new file mode 100644 index 0000000..4310963 --- /dev/null +++ b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/common/ad_rst.v @@ -0,0 +1,77 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_rst ( + + // clock reset + + input rst_async, + input clk, + output rstn, + output reg rst); + + // internal registers + reg rst_async_d1 = 1'd1; + reg rst_async_d2 = 1'd1; + reg rst_sync = 1'd1; + reg rst_sync_d = 1'd1; + + // simple reset synchronizer + always @(posedge clk or posedge rst_async) begin + if (rst_async) begin + rst_async_d1 <= 1'b1; + rst_async_d2 <= 1'b1; + rst_sync <= 1'b1; + end else begin + rst_async_d1 <= 1'b0; + rst_async_d2 <= rst_async_d1; + rst_sync <= rst_async_d2; + end + end + + // two-stage synchronizer to prevent metastability on the falling edge + always @(posedge clk) begin + rst_sync_d <= rst_sync; + rst <= rst_sync_d; + end + + assign rstn = ~rst; + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/common/up_axi.v b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/common/up_axi.v new file mode 100644 index 0000000..40acb17 --- /dev/null +++ b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/common/up_axi.v @@ -0,0 +1,239 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module up_axi #( + + parameter AXI_ADDRESS_WIDTH = 16) ( + + // reset and clocks + + input up_rstn, + input up_clk, + + // axi4 interface + + input up_axi_awvalid, + input [(AXI_ADDRESS_WIDTH-1):0] up_axi_awaddr, + output up_axi_awready, + input up_axi_wvalid, + input [31:0] up_axi_wdata, + input [ 3:0] up_axi_wstrb, + output up_axi_wready, + output up_axi_bvalid, + output [ 1:0] up_axi_bresp, + input up_axi_bready, + input up_axi_arvalid, + input [(AXI_ADDRESS_WIDTH-1):0] up_axi_araddr, + output up_axi_arready, + output up_axi_rvalid, + output [ 1:0] up_axi_rresp, + output [31:0] up_axi_rdata, + input up_axi_rready, + + // pcore interface + + output up_wreq, + output [(AXI_ADDRESS_WIDTH-3):0] up_waddr, + output [31:0] up_wdata, + input up_wack, + output up_rreq, + output [(AXI_ADDRESS_WIDTH-3):0] up_raddr, + input [31:0] up_rdata, + input up_rack); + + // internal registers + + reg up_axi_awready_int = 'd0; + reg up_axi_wready_int = 'd0; + reg up_axi_bvalid_int = 'd0; + reg up_wack_d = 'd0; + reg up_wsel = 'd0; + reg up_wreq_int = 'd0; + reg [(AXI_ADDRESS_WIDTH-3):0] up_waddr_int = 'd0; + reg [31:0] up_wdata_int = 'd0; + reg [ 4:0] up_wcount = 'd0; + reg up_axi_arready_int = 'd0; + reg up_axi_rvalid_int = 'd0; + reg [31:0] up_axi_rdata_int = 'd0; + reg up_rack_d = 'd0; + reg [31:0] up_rdata_d = 'd0; + reg up_rsel = 'd0; + reg up_rreq_int = 'd0; + reg [(AXI_ADDRESS_WIDTH-3):0] up_raddr_int = 'd0; + reg [ 4:0] up_rcount = 'd0; + + // internal signals + + wire up_wack_s; + wire up_rack_s; + wire [31:0] up_rdata_s; + + // write channel interface + + assign up_axi_awready = up_axi_awready_int; + assign up_axi_wready = up_axi_wready_int; + assign up_axi_bvalid = up_axi_bvalid_int; + assign up_axi_bresp = 2'd0; + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_axi_awready_int <= 'd0; + up_axi_wready_int <= 'd0; + up_axi_bvalid_int <= 'd0; + end else begin + if (up_axi_awready_int == 1'b1) begin + up_axi_awready_int <= 1'b0; + end else if (up_wack_s == 1'b1) begin + up_axi_awready_int <= 1'b1; + end + if (up_axi_wready_int == 1'b1) begin + up_axi_wready_int <= 1'b0; + end else if (up_wack_s == 1'b1) begin + up_axi_wready_int <= 1'b1; + end + if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin + up_axi_bvalid_int <= 1'b0; + end else if (up_wack_d == 1'b1) begin + up_axi_bvalid_int <= 1'b1; + end + end + end + + assign up_wreq = up_wreq_int; + assign up_waddr = up_waddr_int; + assign up_wdata = up_wdata_int; + assign up_wack_s = (up_wcount == 5'h1f) ? 1'b1 : (up_wcount[4] & up_wack); + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_wack_d <= 'd0; + up_wsel <= 'd0; + up_wreq_int <= 'd0; + up_waddr_int <= 'd0; + up_wdata_int <= 'd0; + up_wcount <= 'd0; + end else begin + up_wack_d <= up_wack_s; + if (up_wsel == 1'b1) begin + if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin + up_wsel <= 1'b0; + end + up_wreq_int <= 1'b0; + end else begin + up_wsel <= up_axi_awvalid & up_axi_wvalid; + up_wreq_int <= up_axi_awvalid & up_axi_wvalid; + up_waddr_int <= up_axi_awaddr[(AXI_ADDRESS_WIDTH-1):2]; + up_wdata_int <= up_axi_wdata; + end + if (up_wack_s == 1'b1) begin + up_wcount <= 5'h00; + end else if (up_wcount[4] == 1'b1) begin + up_wcount <= up_wcount + 1'b1; + end else if (up_wreq_int == 1'b1) begin + up_wcount <= 5'h10; + end + end + end + + // read channel interface + + assign up_axi_arready = up_axi_arready_int; + assign up_axi_rvalid = up_axi_rvalid_int; + assign up_axi_rdata = up_axi_rdata_int; + assign up_axi_rresp = 2'd0; + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_axi_arready_int <= 'd0; + up_axi_rvalid_int <= 'd0; + up_axi_rdata_int <= 'd0; + end else begin + if (up_axi_arready_int == 1'b1) begin + up_axi_arready_int <= 1'b0; + end else if (up_rack_s == 1'b1) begin + up_axi_arready_int <= 1'b1; + end + if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin + up_axi_rvalid_int <= 1'b0; + up_axi_rdata_int <= 32'd0; + end else if (up_rack_d == 1'b1) begin + up_axi_rvalid_int <= 1'b1; + up_axi_rdata_int <= up_rdata_d; + end + end + end + + assign up_rreq = up_rreq_int; + assign up_raddr = up_raddr_int; + assign up_rack_s = (up_rcount == 5'h1f) ? 1'b1 : (up_rcount[4] & up_rack); + assign up_rdata_s = (up_rcount == 5'h1f) ? {2{16'hdead}} : up_rdata; + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_rack_d <= 'd0; + up_rdata_d <= 'd0; + up_rsel <= 'd0; + up_rreq_int <= 'd0; + up_raddr_int <= 'd0; + up_rcount <= 'd0; + end else begin + up_rack_d <= up_rack_s; + up_rdata_d <= up_rdata_s; + if (up_rsel == 1'b1) begin + if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin + up_rsel <= 1'b0; + end + up_rreq_int <= 1'b0; + end else begin + up_rsel <= up_axi_arvalid; + up_rreq_int <= up_axi_arvalid; + up_raddr_int <= up_axi_araddr[(AXI_ADDRESS_WIDTH-1):2]; + end + if (up_rack_s == 1'b1) begin + up_rcount <= 5'h00; + end else if (up_rcount[4] == 1'b1) begin + up_rcount <= up_rcount + 1'b1; + end else if (up_rreq_int == 1'b1) begin + up_rcount <= 5'h10; + end + end + end + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci new file mode 100644 index 0000000..aa665df --- /dev/null +++ b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci @@ -0,0 +1,302 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "system_bd_auto_pc_0", + "cell_name": "axi_interconnect/s00_couplers/auto_pc", + "component_reference": "xilinx.com:ip:axi_protocol_converter:2.1", + "ip_revision": "31", + "gen_directory": "../../../../../../dx_sig_basic.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0", + "parameters": { + "component_parameters": { + "SI_PROTOCOL": [ { "value": "AXI3", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], + "MI_PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], + "TRANSLATION_MODE": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ID_WIDTH": [ { "value": "12", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Component_Name": [ { "value": "system_bd_auto_pc_0", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ], + "C_M_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXI_PROTOCOL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_IGNORE_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_ID_WIDTH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_SUPPORTS_WRITE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_SUPPORTS_READ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TRANSLATION_MODE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z100" } ], + "NEXTGEN_VERSAL": [ { "value": "0" } ], + "PACKAGE": [ { "value": "ffg900" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "31" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../dx_sig_basic.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0" } ], + "SELECTEDSIMMODEL": [ { "value": "rtl" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2024.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "aclk": [ { "direction": "in" } ], + "aresetn": [ { "direction": "in" } ], + "s_axi_awid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ], + "s_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ], + "s_axi_awlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ], + "s_axi_awlock": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ], + "s_axi_awready": [ { "direction": "out" } ], + "s_axi_wid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ], + "s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ], + "s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0xF" } ], + "s_axi_wlast": [ { "direction": "in", "driver_value": "0x1" } ], + "s_axi_wvalid": [ { "direction": "in", "driver_value": "0x0" } ], + "s_axi_wready": [ { "direction": "out" } ], + "s_axi_bid": [ { "direction": "out", "size_left": "11", "size_right": "0" } ], + "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], + "s_axi_bvalid": [ { "direction": "out" } ], + "s_axi_bready": [ { "direction": "in", "driver_value": "0x0" } ], + "s_axi_arid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ], + "s_axi_araddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ], + "s_axi_arlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_arburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ], + "s_axi_arlock": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_arcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_arqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_arvalid": [ { "direction": "in", "driver_value": "0x0" } ], + "s_axi_arready": [ { "direction": "out" } ], + "s_axi_rid": [ { "direction": "out", "size_left": "11", "size_right": "0" } ], + "s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], + "s_axi_rlast": [ { "direction": "out" } ], + "s_axi_rvalid": [ { "direction": "out" } ], + "s_axi_rready": [ { "direction": "in", "driver_value": "0x0" } ], + "m_axi_awaddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "m_axi_awprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ], + "m_axi_awvalid": [ { "direction": "out" } ], + "m_axi_awready": [ { "direction": "in", "driver_value": "0x0" } ], + "m_axi_wdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "m_axi_wstrb": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], + "m_axi_wvalid": [ { "direction": "out" } ], + "m_axi_wready": [ { "direction": "in", "driver_value": "0x0" } ], + "m_axi_bresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ], + "m_axi_bvalid": [ { "direction": "in", "driver_value": "0x0" } ], + "m_axi_bready": [ { "direction": "out" } ], + "m_axi_araddr": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "m_axi_arprot": [ { "direction": "out", "size_left": "2", "size_right": "0" } ], + "m_axi_arvalid": [ { "direction": "out" } ], + "m_axi_arready": [ { "direction": "in", "driver_value": "0x0" } ], + "m_axi_rdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ], + "m_axi_rresp": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ], + "m_axi_rvalid": [ { "direction": "in", "driver_value": "0x0" } ], + "m_axi_rready": [ { "direction": "out" } ] + }, + "interfaces": { + "S_AXI": { + "vlnv": "xilinx.com:interface:aximm:1.0", + "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "slave", + "parameters": { + "DATA_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI3", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "12", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "32", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BURST": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "16", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "AWID": [ { "physical_name": "s_axi_awid" } ], + "AWADDR": [ { "physical_name": "s_axi_awaddr" } ], + "AWLEN": [ { "physical_name": "s_axi_awlen" } ], + "AWSIZE": [ { "physical_name": "s_axi_awsize" } ], + "AWBURST": [ { "physical_name": "s_axi_awburst" } ], + "AWLOCK": [ { "physical_name": "s_axi_awlock" } ], + "AWCACHE": [ { "physical_name": "s_axi_awcache" } ], + "AWPROT": [ { "physical_name": "s_axi_awprot" } ], + "AWQOS": [ { "physical_name": "s_axi_awqos" } ], + "AWVALID": [ { "physical_name": "s_axi_awvalid" } ], + "AWREADY": [ { "physical_name": "s_axi_awready" } ], + "WID": [ { "physical_name": "s_axi_wid" } ], + "WDATA": [ { "physical_name": "s_axi_wdata" } ], + "WSTRB": [ { "physical_name": "s_axi_wstrb" } ], + "WLAST": [ { "physical_name": "s_axi_wlast" } ], + "WVALID": [ { "physical_name": "s_axi_wvalid" } ], + "WREADY": [ { "physical_name": "s_axi_wready" } ], + "BID": [ { "physical_name": "s_axi_bid" } ], + "BRESP": [ { "physical_name": "s_axi_bresp" } ], + "BVALID": [ { "physical_name": "s_axi_bvalid" } ], + "BREADY": [ { "physical_name": "s_axi_bready" } ], + "ARID": [ { "physical_name": "s_axi_arid" } ], + "ARADDR": [ { "physical_name": "s_axi_araddr" } ], + "ARLEN": [ { "physical_name": "s_axi_arlen" } ], + "ARSIZE": [ { "physical_name": "s_axi_arsize" } ], + "ARBURST": [ { "physical_name": "s_axi_arburst" } ], + "ARLOCK": [ { "physical_name": "s_axi_arlock" } ], + "ARCACHE": [ { "physical_name": "s_axi_arcache" } ], + "ARPROT": [ { "physical_name": "s_axi_arprot" } ], + "ARQOS": [ { "physical_name": "s_axi_arqos" } ], + "ARVALID": [ { "physical_name": "s_axi_arvalid" } ], + "ARREADY": [ { "physical_name": "s_axi_arready" } ], + "RID": [ { "physical_name": "s_axi_rid" } ], + "RDATA": [ { "physical_name": "s_axi_rdata" } ], + "RRESP": [ { "physical_name": "s_axi_rresp" } ], + "RLAST": [ { "physical_name": "s_axi_rlast" } ], + "RVALID": [ { "physical_name": "s_axi_rvalid" } ], + "RREADY": [ { "physical_name": "s_axi_rready" } ] + } + }, + "M_AXI": { + "vlnv": "xilinx.com:interface:aximm:1.0", + "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "master", + "parameters": { + "DATA_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "32", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BURST": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_PROT": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "AWADDR": [ { "physical_name": "m_axi_awaddr" } ], + "AWPROT": [ { "physical_name": "m_axi_awprot" } ], + "AWVALID": [ { "physical_name": "m_axi_awvalid" } ], + "AWREADY": [ { "physical_name": "m_axi_awready" } ], + "WDATA": [ { "physical_name": "m_axi_wdata" } ], + "WSTRB": [ { "physical_name": "m_axi_wstrb" } ], + "WVALID": [ { "physical_name": "m_axi_wvalid" } ], + "WREADY": [ { "physical_name": "m_axi_wready" } ], + "BRESP": [ { "physical_name": "m_axi_bresp" } ], + "BVALID": [ { "physical_name": "m_axi_bvalid" } ], + "BREADY": [ { "physical_name": "m_axi_bready" } ], + "ARADDR": [ { "physical_name": "m_axi_araddr" } ], + "ARPROT": [ { "physical_name": "m_axi_arprot" } ], + "ARVALID": [ { "physical_name": "m_axi_arvalid" } ], + "ARREADY": [ { "physical_name": "m_axi_arready" } ], + "RDATA": [ { "physical_name": "m_axi_rdata" } ], + "RRESP": [ { "physical_name": "m_axi_rresp" } ], + "RVALID": [ { "physical_name": "m_axi_rvalid" } ], + "RREADY": [ { "physical_name": "m_axi_rready" } ] + } + }, + "CLK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.000", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "aclk" } ] + } + }, + "RST": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ], + "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "aresetn" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_axi_interconnect_0_0/system_bd_axi_interconnect_0_0.xci b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_axi_interconnect_0_0/system_bd_axi_interconnect_0_0.xci new file mode 100644 index 0000000..29a4d53 --- /dev/null +++ b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_axi_interconnect_0_0/system_bd_axi_interconnect_0_0.xci @@ -0,0 +1,353 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "system_bd_axi_interconnect_0_0", + "cell_name": "axi_interconnect", + "component_reference": "xilinx.com:ip:axi_interconnect:2.1", + "ip_revision": "32", + "gen_directory": "../../../../../../dx_sig_basic.gen/sources_1/bd/system_bd/ip/system_bd_axi_interconnect_0_0", + "parameters": { + "component_parameters": { + "NUM_SI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "NUM_MI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "STRATEGY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ENABLE_ADVANCED_OPTIONS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ENABLE_PROTOCOL_CHECKERS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "XBAR_DATA_WIDTH": [ { "value": "32", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCHK_WAITS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCHK_MAX_RD_BURSTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCHK_MAX_WR_BURSTS": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ], + "SYNCHRONIZATION_STAGES": [ { "value": "3", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M00_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M01_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M02_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M03_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M04_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M05_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M06_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M07_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M08_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M09_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M10_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M11_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M12_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M13_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M14_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M15_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M16_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M17_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M18_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M19_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M20_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M21_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M22_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M23_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M24_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M25_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M26_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M27_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M28_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M29_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M30_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M31_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M32_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M33_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M34_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M35_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M36_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M37_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M38_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M39_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M40_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M41_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M42_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M43_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M44_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M45_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M46_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M47_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M48_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M49_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M50_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M51_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M52_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M53_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M54_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M55_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M56_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M57_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M58_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M59_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M60_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M61_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M62_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M63_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M00_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M01_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M02_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M03_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M04_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M05_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M06_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M07_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M08_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M09_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M10_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M11_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M12_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M13_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M14_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M15_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M16_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M17_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M18_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M19_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M20_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M21_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M22_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M23_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M24_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M25_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M26_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M27_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M28_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M29_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M30_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M31_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M32_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M33_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M34_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M35_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M36_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M37_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M38_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M39_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M40_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M41_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M42_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M43_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M44_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M45_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M46_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M47_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M48_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M49_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M50_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M51_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M52_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M53_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M54_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M55_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M56_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M57_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M58_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M59_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M60_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M61_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M62_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M63_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S00_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S01_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S02_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S03_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S04_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S05_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S06_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S07_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S08_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S09_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S10_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S11_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S12_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S13_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S14_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S15_HAS_REGSLICE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S00_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S01_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S02_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S03_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S04_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S05_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S06_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S07_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S08_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S09_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S10_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S11_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S12_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S13_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S14_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S15_HAS_DATA_FIFO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M00_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M01_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M02_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M03_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M04_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M05_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M06_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M07_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M08_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M09_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M10_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M11_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M12_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M13_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M14_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M15_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M16_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M17_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M18_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M19_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M20_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M21_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M22_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M23_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M24_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M25_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M26_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M27_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M28_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M29_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M30_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M31_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M32_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M33_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M34_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M35_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M36_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M37_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M38_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M39_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M40_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M41_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M42_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M43_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M44_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M45_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M46_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M47_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M48_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M49_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M50_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M51_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M52_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M53_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M54_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M55_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M56_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M57_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M58_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M59_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M60_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M61_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M62_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M63_ISSUANCE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M00_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M01_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M02_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M03_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M04_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M05_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M06_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M07_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M08_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M09_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M10_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M11_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M12_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M13_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M14_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M15_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M16_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M17_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M18_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M19_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M20_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M21_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M22_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M23_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M24_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M25_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M26_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M27_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M28_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M29_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M30_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M31_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M32_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M33_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M34_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M35_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M36_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M37_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M38_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M39_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M40_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M41_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M42_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M43_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M44_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M45_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M46_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M47_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M48_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M49_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M50_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M51_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M52_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M53_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M54_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M55_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M56_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M57_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M58_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M59_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M60_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M61_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M62_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M63_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S00_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S01_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S02_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S03_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S04_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S05_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S06_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S07_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S08_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S09_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S10_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S11_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S12_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S13_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S14_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S15_ARB_PRIORITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Component_Name": [ { "value": "system_bd_axi_interconnect_0_0", "resolve_type": "user", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z100" } ], + "NEXTGEN_VERSAL": [ { "value": "0" } ], + "PACKAGE": [ { "value": "ffg900" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator_AppCore" } ], + "IPREVISION": [ { "value": "32" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../dx_sig_basic.gen/sources_1/bd/system_bd/ip/system_bd_axi_interconnect_0_0" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2024.1" } ], + "SYNTHESISFLOW": [ { "value": "GLOBAL" } ] + } + } + } +} \ No newline at end of file diff --git a/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci new file mode 100644 index 0000000..9a38b97 --- /dev/null +++ b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci @@ -0,0 +1,280 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "system_bd_axi_spi_engine_0_0", + "cell_name": "axi_spi_engine/axi_spi_engine", + "component_reference": "analog.com:user:axi_spi_engine:1.0", + "ip_revision": "1", + "gen_directory": "../../../../../../dx_sig_basic.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0", + "parameters": { + "component_parameters": { + "CMD_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "SYNC_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "SDO_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ], + "SDI_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MM_IF_TYPE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ASYNC_SPI_CLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "NUM_OFFLOAD": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "ID": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ], + "NUM_OF_SDI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Component_Name": [ { "value": "system_bd_axi_spi_engine_0_0", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "CMD_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "SYNC_FIFO_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "SDO_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "SDI_FIFO_ADDRESS_WIDTH": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "MM_IF_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "ASYNC_SPI_CLK": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ], + "NUM_OFFLOAD": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "enabled": false, "usage": "all" } ], + "ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z100" } ], + "NEXTGEN_VERSAL": [ { "value": "0" } ], + "PACKAGE": [ { "value": "ffg900" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "1" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../dx_sig_basic.gen/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2024.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "s_axi_aclk": [ { "direction": "in", "driver_value": "0" } ], + "s_axi_aresetn": [ { "direction": "in", "driver_value": "0" } ], + "s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ], + "s_axi_awaddr": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "s_axi_awready": [ { "direction": "out", "driver_value": "0" } ], + "s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ], + "s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ], + "s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ], + "s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ], + "s_axi_wready": [ { "direction": "out", "driver_value": "0" } ], + "s_axi_bvalid": [ { "direction": "out", "driver_value": "0" } ], + "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ], + "s_axi_bready": [ { "direction": "in", "driver_value": "0" } ], + "s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ], + "s_axi_araddr": [ { "direction": "in", "size_left": "15", "size_right": "0", "driver_value": "0" } ], + "s_axi_arready": [ { "direction": "out", "driver_value": "0" } ], + "s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ], + "s_axi_rvalid": [ { "direction": "out", "driver_value": "0" } ], + "s_axi_rready": [ { "direction": "in", "driver_value": "0" } ], + "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0", "driver_value": "0" } ], + "s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ], + "irq": [ { "direction": "out" } ], + "spi_clk": [ { "direction": "in" } ], + "spi_resetn": [ { "direction": "out" } ], + "cmd_ready": [ { "direction": "in" } ], + "cmd_valid": [ { "direction": "out" } ], + "cmd_data": [ { "direction": "out", "size_left": "15", "size_right": "0" } ], + "sdo_data_ready": [ { "direction": "in", "driver_value": "0" } ], + "sdo_data_valid": [ { "direction": "out" } ], + "sdo_data": [ { "direction": "out", "size_left": "7", "size_right": "0" } ], + "sdi_data_ready": [ { "direction": "out" } ], + "sdi_data_valid": [ { "direction": "in", "driver_value": "0" } ], + "sdi_data": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ], + "sync_ready": [ { "direction": "out" } ], + "sync_valid": [ { "direction": "in" } ], + "sync_data": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ] + }, + "interfaces": { + "s_axi": { + "vlnv": "xilinx.com:interface:aximm:1.0", + "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "slave", + "memory_map_ref": "s_axi", + "parameters": { + "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ], + "FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], + "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_CACHE": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "4", "value_src": "constant_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] + }, + "port_maps": { + "AWADDR": [ { "physical_name": "s_axi_awaddr" } ], + "AWPROT": [ { "physical_name": "s_axi_awprot" } ], + "AWVALID": [ { "physical_name": "s_axi_awvalid" } ], + "AWREADY": [ { "physical_name": "s_axi_awready" } ], + "WDATA": [ { "physical_name": "s_axi_wdata" } ], + "WSTRB": [ { "physical_name": "s_axi_wstrb" } ], + "WVALID": [ { "physical_name": "s_axi_wvalid" } ], + "WREADY": [ { "physical_name": "s_axi_wready" } ], + "BRESP": [ { "physical_name": "s_axi_bresp" } ], + "BVALID": [ { "physical_name": "s_axi_bvalid" } ], + "BREADY": [ { "physical_name": "s_axi_bready" } ], + "ARADDR": [ { "physical_name": "s_axi_araddr" } ], + "ARPROT": [ { "physical_name": "s_axi_arprot" } ], + "ARVALID": [ { "physical_name": "s_axi_arvalid" } ], + "ARREADY": [ { "physical_name": "s_axi_arready" } ], + "RDATA": [ { "physical_name": "s_axi_rdata" } ], + "RRESP": [ { "physical_name": "s_axi_rresp" } ], + "RVALID": [ { "physical_name": "s_axi_rvalid" } ], + "RREADY": [ { "physical_name": "s_axi_rready" } ] + } + }, + "s_axi_aclk": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "s_axi_aclk" } ] + } + }, + "s_axi_aresetn": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "s_axi_aresetn" } ] + } + }, + "spi_engine_ctrl": { + "vlnv": "analog.com:interface:spi_engine_ctrl:1.0", + "abstraction_type": "analog.com:interface:spi_engine_ctrl_rtl:1.0", + "mode": "master", + "port_maps": { + "CMD_READY": [ { "physical_name": "cmd_ready" } ], + "CMD_VALID": [ { "physical_name": "cmd_valid" } ], + "CMD_DATA": [ { "physical_name": "cmd_data" } ], + "SDO_READY": [ { "physical_name": "sdo_data_ready" } ], + "SDO_VALID": [ { "physical_name": "sdo_data_valid" } ], + "SDO_DATA": [ { "physical_name": "sdo_data" } ], + "SDI_READY": [ { "physical_name": "sdi_data_ready" } ], + "SDI_VALID": [ { "physical_name": "sdi_data_valid" } ], + "SDI_DATA": [ { "physical_name": "sdi_data" } ], + "SYNC_READY": [ { "physical_name": "sync_ready" } ], + "SYNC_VALID": [ { "physical_name": "sync_valid" } ], + "SYNC_DATA": [ { "physical_name": "sync_data" } ] + } + }, + "spi_engine_ctrl_signal_clock": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "spi_engine_ctrl", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "spi_resetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "spi_clk" } ] + } + }, + "spi_engine_ctrl_signal_reset": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "master", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "spi_resetn" } ] + } + }, + "spi_engine_offload_ctrl0_s_axi_signal_clock": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "spi_engine_offload_ctrl0:s_axi", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "FREQ_HZ": [ { "value": "50000000", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "PHASE": [ { "value": "0.000", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "s_axi_aclk" } ] + } + }, + "spi_engine_offload_ctrl0_s_axi_signal_reset": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "s_axi_aresetn" } ] + } + } + }, + "memory_maps": { + "s_axi": { + "address_blocks": { + "axi_lite": { + "base_address": "0", + "range": "65536" + } + } + } + } + } + } +} \ No newline at end of file diff --git a/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/ps7_parameters.xml b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/ps7_parameters.xml new file mode 100644 index 0000000..b364cdc --- /dev/null +++ b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/ps7_parameters.xml @@ -0,0 +1,643 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci new file mode 100644 index 0000000..7d84313 --- /dev/null +++ b/vivado_pvt/projects/dx_sig/dx_sig_basic/dx_sig_basic.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci @@ -0,0 +1,1302 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "system_bd_processing_system7_0_0", + "cell_name": "processing_system7_0", + "component_reference": "xilinx.com:ip:processing_system7:5.5", + "ip_revision": "6", + "gen_directory": "../../../../../../dx_sig_basic.gen/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0", + "parameters": { + "component_parameters": { + "PCW_DDR_RAM_BASEADDR": [ { "value": "0x00100000", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_DDR_RAM_HIGHADDR": [ { "value": "0x1FFFFFFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_UART0_BASEADDR": [ { "value": "0xE0000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_UART0_HIGHADDR": [ { "value": "0xE0000FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_UART1_BASEADDR": [ { "value": "0xE0001000", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_UART1_HIGHADDR": [ { "value": "0xE0001FFF", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_I2C0_BASEADDR": [ { "value": "0xE0004000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_I2C0_HIGHADDR": [ { "value": "0xE0004FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_I2C1_BASEADDR": [ { "value": "0xE0005000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_I2C1_HIGHADDR": [ { "value": "0xE0005FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SPI0_BASEADDR": [ { "value": "0xE0006000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SPI0_HIGHADDR": [ { "value": "0xE0006FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SPI1_BASEADDR": [ { "value": "0xE0007000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SPI1_HIGHADDR": [ { "value": "0xE0007FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_CAN0_BASEADDR": [ { "value": "0xE0008000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_CAN0_HIGHADDR": [ { "value": "0xE0008FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_CAN1_BASEADDR": [ { "value": "0xE0009000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_CAN1_HIGHADDR": [ { "value": "0xE0009FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_GPIO_BASEADDR": [ { "value": "0xE000A000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_GPIO_HIGHADDR": [ { "value": "0xE000AFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_ENET0_BASEADDR": [ { "value": "0xE000B000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_ENET0_HIGHADDR": [ { "value": "0xE000BFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_ENET1_BASEADDR": [ { "value": "0xE000C000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_ENET1_HIGHADDR": [ { "value": "0xE000CFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SDIO0_BASEADDR": [ { "value": "0xE0100000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SDIO0_HIGHADDR": [ { "value": "0xE0100FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SDIO1_BASEADDR": [ { "value": "0xE0101000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SDIO1_HIGHADDR": [ { "value": "0xE0101FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_USB0_BASEADDR": [ { "value": "0xE0102000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_USB0_HIGHADDR": [ { "value": "0xE0102fff", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_USB1_BASEADDR": [ { "value": "0xE0103000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_USB1_HIGHADDR": [ { "value": "0xE0103fff", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_TTC0_BASEADDR": [ { "value": "0xE0104000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_TTC0_HIGHADDR": [ { "value": "0xE0104fff", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_TTC1_BASEADDR": [ { "value": "0xE0105000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_TTC1_HIGHADDR": [ { "value": "0xE0105fff", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_FCLK_CLK0_BUF": [ { "value": "TRUE", "resolve_type": "user", "usage": "all" } ], + "PCW_FCLK_CLK1_BUF": [ { "value": "FALSE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_FCLK_CLK2_BUF": [ { "value": "FALSE", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_FCLK_CLK3_BUF": [ { "value": "FALSE", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_FREQ_MHZ": [ { "value": "533.333333", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_BANK_ADDR_COUNT": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_ROW_ADDR_COUNT": [ { "value": "15", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_COL_ADDR_COUNT": [ { "value": "10", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_CL": [ { "value": "7", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_CWL": [ { "value": "6", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_T_RCD": [ { "value": "7", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_T_RP": [ { "value": "7", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_T_RC": [ { "value": "48.91", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_T_RAS_MIN": [ { "value": "35.0", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_T_FAW": [ { "value": "40.0", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_AL": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_BOARD_DELAY0": [ { "value": "0.25", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_BOARD_DELAY1": [ { "value": "0.25", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_BOARD_DELAY2": [ { "value": "0.25", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_BOARD_DELAY3": [ { "value": "0.25", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_0_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_1_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_2_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_3_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQ_0_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQ_1_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQ_2_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQ_3_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM": [ { "value": "0", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH": [ { "value": "133.8645", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH": [ { "value": "119.997", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH": [ { "value": "121.146", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH": [ { "value": "90.125", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH": [ { "value": "111.7605", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH": [ { "value": "123.5525", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH": [ { "value": "120.714", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH": [ { "value": "100.836", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH": [ { "value": "80.0515", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH": [ { "value": "80.0515", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH": [ { "value": "80.0515", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH": [ { "value": "80.0515", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY": [ { "value": "160", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY": [ { "value": "160", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY": [ { "value": "160", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY": [ { "value": "160", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY": [ { "value": "160", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY": [ { "value": "160", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY": [ { "value": "160", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY": [ { "value": "160", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY": [ { "value": "160", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY": [ { "value": "160", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY": [ { "value": "160", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY": [ { "value": "160", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0": [ { "value": "-0.054", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1": [ { "value": "-0.040", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2": [ { "value": "-0.041", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3": [ { "value": "-0.010", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_PACKAGE_DDR_BOARD_DELAY0": [ { "value": "0.096", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_PACKAGE_DDR_BOARD_DELAY1": [ { "value": "0.102", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_PACKAGE_DDR_BOARD_DELAY2": [ { "value": "0.100", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_PACKAGE_DDR_BOARD_DELAY3": [ { "value": "0.090", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_CPU_CPU_6X4X_MAX_RANGE": [ { "value": "800", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_CRYSTAL_PERIPHERAL_FREQMHZ": [ { "value": "33.333333", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_APU_PERIPHERAL_FREQMHZ": [ { "value": "666.666666", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_DCI_PERIPHERAL_FREQMHZ": [ { "value": "10.159", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_QSPI_PERIPHERAL_FREQMHZ": [ { "value": "200", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_SMC_PERIPHERAL_FREQMHZ": [ { "value": "100", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_USB0_PERIPHERAL_FREQMHZ": [ { "value": "60", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_USB1_PERIPHERAL_FREQMHZ": [ { "value": "60", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_SDIO_PERIPHERAL_FREQMHZ": [ { "value": "100", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_UART_PERIPHERAL_FREQMHZ": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_SPI_PERIPHERAL_FREQMHZ": [ { "value": "166.666666", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_CAN_PERIPHERAL_FREQMHZ": [ { "value": "100", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_CAN0_PERIPHERAL_FREQMHZ": [ { "value": "-1", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_CAN1_PERIPHERAL_FREQMHZ": [ { "value": "-1", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_I2C_PERIPHERAL_FREQMHZ": [ { "value": "25", "value_src": "user", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_WDT_PERIPHERAL_FREQMHZ": [ { "value": "133.333333", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_TTC_PERIPHERAL_FREQMHZ": [ { "value": "50", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ": [ { "value": "133.333333", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ": [ { "value": "133.333333", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ": [ { "value": "133.333333", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ": [ { "value": "133.333333", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ": [ { "value": "133.333333", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ": [ { "value": "133.333333", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_PCAP_PERIPHERAL_FREQMHZ": [ { "value": "200", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_TPIU_PERIPHERAL_FREQMHZ": [ { "value": "200", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_FPGA0_PERIPHERAL_FREQMHZ": [ { "value": "50", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_FPGA1_PERIPHERAL_FREQMHZ": [ { "value": "100", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_FPGA2_PERIPHERAL_FREQMHZ": [ { "value": "50", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_FPGA3_PERIPHERAL_FREQMHZ": [ { "value": "50", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_APU_PERIPHERAL_FREQMHZ": [ { "value": "666.666687", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_UIPARAM_ACT_DDR_FREQ_MHZ": [ { "value": "533.333374", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_DCI_PERIPHERAL_FREQMHZ": [ { "value": "10.158730", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_QSPI_PERIPHERAL_FREQMHZ": [ { "value": "200.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_SMC_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_ENET0_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_ENET1_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_USB0_PERIPHERAL_FREQMHZ": [ { "value": "60", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_USB1_PERIPHERAL_FREQMHZ": [ { "value": "60", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_SDIO_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_UART_PERIPHERAL_FREQMHZ": [ { "value": "100.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_SPI_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_CAN_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_CAN0_PERIPHERAL_FREQMHZ": [ { "value": "23.8095", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_CAN1_PERIPHERAL_FREQMHZ": [ { "value": "23.8095", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_I2C_PERIPHERAL_FREQMHZ": [ { "value": "50", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_WDT_PERIPHERAL_FREQMHZ": [ { "value": "111.111115", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_TTC_PERIPHERAL_FREQMHZ": [ { "value": "50", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_PCAP_PERIPHERAL_FREQMHZ": [ { "value": "200.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_TPIU_PERIPHERAL_FREQMHZ": [ { "value": "200.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ": [ { "value": "50.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ": [ { "value": "100.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ": [ { "value": "10.000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ": [ { "value": "111.111115", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ": [ { "value": "111.111115", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ": [ { "value": "111.111115", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ": [ { "value": "111.111115", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ": [ { "value": "111.111115", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ": [ { "value": "111.111115", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_CLK0_FREQ": [ { "value": "50000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_CLK1_FREQ": [ { "value": "100000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_CLK2_FREQ": [ { "value": "10000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_CLK3_FREQ": [ { "value": "10000000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PCW_OVERRIDE_BASIC_CLOCK": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_CPU_PERIPHERAL_DIVISOR0": [ { "value": "2", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_PERIPHERAL_DIVISOR0": [ { "value": "2", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SMC_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_QSPI_PERIPHERAL_DIVISOR0": [ { "value": "9", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SDIO_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UART_PERIPHERAL_DIVISOR0": [ { "value": "18", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SPI_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_CAN_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_CAN_PERIPHERAL_DIVISOR1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_FCLK0_PERIPHERAL_DIVISOR0": [ { "value": "6", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_FCLK1_PERIPHERAL_DIVISOR0": [ { "value": "6", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_FCLK2_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_FCLK3_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_FCLK0_PERIPHERAL_DIVISOR1": [ { "value": "6", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_FCLK1_PERIPHERAL_DIVISOR1": [ { "value": "3", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_FCLK2_PERIPHERAL_DIVISOR1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_FCLK3_PERIPHERAL_DIVISOR1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_ENET0_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_ENET1_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_ENET0_PERIPHERAL_DIVISOR1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_ENET1_PERIPHERAL_DIVISOR1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_TPIU_PERIPHERAL_DIVISOR0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DCI_PERIPHERAL_DIVISOR0": [ { "value": "15", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DCI_PERIPHERAL_DIVISOR1": [ { "value": "7", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_PCAP_PERIPHERAL_DIVISOR0": [ { "value": "9", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], + "PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], + "PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], + "PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], + "PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], + "PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], + "PCW_WDT_PERIPHERAL_DIVISOR0": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], + "PCW_ARMPLL_CTRL_FBDIV": [ { "value": "40", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_IOPLL_CTRL_FBDIV": [ { "value": "54", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDRPLL_CTRL_FBDIV": [ { "value": "32", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_CPU_CPU_PLL_FREQMHZ": [ { "value": "1333.333", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_IO_IO_PLL_FREQMHZ": [ { "value": "1800.000", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_DDR_PLL_FREQMHZ": [ { "value": "1066.667", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SMC_PERIPHERAL_VALID": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_SDIO_PERIPHERAL_VALID": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_SPI_PERIPHERAL_VALID": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_CAN_PERIPHERAL_VALID": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_UART_PERIPHERAL_VALID": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_CAN0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_CAN1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_ENET0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_ENET1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_PTP_ENET0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_PTP_ENET1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_GPIO": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_I2C0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_I2C1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_PJTAG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_SDIO0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_CD_SDIO0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_WP_SDIO0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_SDIO1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_CD_SDIO1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_WP_SDIO1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_SPI0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_SPI1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_UART0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_UART1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_MODEM_UART0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_MODEM_UART1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_TTC0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_TTC1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_WDT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_TRACE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_AXI_NONSECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_M_AXI_GP0": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_M_AXI_GP1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_S_AXI_GP0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_S_AXI_GP1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_S_AXI_ACP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_S_AXI_HP0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_S_AXI_HP1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_S_AXI_HP2": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_S_AXI_HP3": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_M_AXI_GP0_FREQMHZ": [ { "value": "50", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_M_AXI_GP1_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_S_AXI_GP0_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_S_AXI_GP1_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_S_AXI_ACP_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_S_AXI_HP0_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_S_AXI_HP1_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_S_AXI_HP2_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_S_AXI_HP3_FREQMHZ": [ { "value": "10", "value_permission": "bd", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_USE_DMA0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_DMA1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_DMA2": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_DMA3": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_TRACE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_TRACE_PIPELINE_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_INCLUDE_TRACE_BUFFER": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_TRACE_BUFFER_FIFO_SIZE": [ { "value": "128", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_USE_TRACE_DATA_EDGE_DETECTOR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_TRACE_BUFFER_CLOCK_DELAY": [ { "value": "12", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_USE_CROSS_TRIGGER": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_FTM_CTI_IN0": [ { "value": "DISABLED", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_FTM_CTI_IN1": [ { "value": "DISABLED", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_FTM_CTI_IN2": [ { "value": "DISABLED", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_FTM_CTI_IN3": [ { "value": "DISABLED", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_FTM_CTI_OUT0": [ { "value": "DISABLED", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_FTM_CTI_OUT1": [ { "value": "DISABLED", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_FTM_CTI_OUT2": [ { "value": "DISABLED", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_FTM_CTI_OUT3": [ { "value": "DISABLED", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_USE_DEBUG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_CR_FABRIC": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_AXI_FABRIC_IDLE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_DDR_BYPASS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_FABRIC_INTERRUPT": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_PROC_EVENT_BUS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_EXPANDED_IOP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_HIGH_OCM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_PS_SLCR_REGISTERS": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_EXPANDED_PS_SLCR_REGISTERS": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_USE_CORESIGHT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_EMIO_SRAM_INT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_GPIO_EMIO_GPIO_WIDTH": [ { "value": "48", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_GP0_NUM_WRITE_THREADS": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_GP0_NUM_READ_THREADS": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_GP1_NUM_WRITE_THREADS": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_GP1_NUM_READ_THREADS": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_UART0_BAUD_RATE": [ { "value": "115200", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_UART1_BAUD_RATE": [ { "value": "115200", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_4K_TIMER": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_M_AXI_GP0_ID_WIDTH": [ { "value": "12", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_M_AXI_GP0_ENABLE_STATIC_REMAP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_M_AXI_GP0_SUPPORT_NARROW_BURST": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_M_AXI_GP0_THREAD_ID_WIDTH": [ { "value": "12", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_M_AXI_GP1_ID_WIDTH": [ { "value": "12", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_M_AXI_GP1_ENABLE_STATIC_REMAP": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_M_AXI_GP1_SUPPORT_NARROW_BURST": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_M_AXI_GP1_THREAD_ID_WIDTH": [ { "value": "12", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_S_AXI_GP0_ID_WIDTH": [ { "value": "6", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_S_AXI_GP1_ID_WIDTH": [ { "value": "6", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_S_AXI_ACP_ID_WIDTH": [ { "value": "3", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_INCLUDE_ACP_TRANS_CHECK": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_USE_DEFAULT_ACP_USER_VAL": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_S_AXI_ACP_ARUSER_VAL": [ { "value": "31", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_S_AXI_ACP_AWUSER_VAL": [ { "value": "31", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_S_AXI_HP0_ID_WIDTH": [ { "value": "6", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_S_AXI_HP0_DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_S_AXI_HP1_ID_WIDTH": [ { "value": "6", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_S_AXI_HP1_DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_S_AXI_HP2_ID_WIDTH": [ { "value": "6", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_S_AXI_HP2_DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_S_AXI_HP3_ID_WIDTH": [ { "value": "6", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_S_AXI_HP3_DATA_WIDTH": [ { "value": "64", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_NUM_F2P_INTR_INPUTS": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_DDR": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_SMC": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_QSPI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CAN0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CAN1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_ENET0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_ENET1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_GPIO": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_I2C0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_I2C1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_PJTAG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_SDIO0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_SDIO1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_SPI0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_SPI1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_UART0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_UART1": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_MODEM_UART0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_MODEM_UART1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_TTC0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_TTC1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_WDT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_TRACE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_USB0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_USB1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_DQ_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_DQS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_DM_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_MIO_PRIMITIVE": [ { "value": "54", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CLK0_PORT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CLK1_PORT": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CLK2_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CLK3_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_RST0_PORT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_RST1_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_RST2_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_RST3_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CLKTRIG0_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CLKTRIG1_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CLKTRIG2_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CLKTRIG3_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_P2F_DMAC_ABORT_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC2_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC3_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC4_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC5_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC6_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC7_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_SMC_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_QSPI_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_P2F_CTI_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_GPIO_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_USB0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_ENET0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_SDIO0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_I2C0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_SPI0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_UART0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_CAN0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_USB1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_ENET1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_SDIO1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_I2C1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_SPI1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_UART1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_P2F_CAN1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_IRQ_F2P_INTR": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_IRQ_F2P_MODE": [ { "value": "DIRECT", "resolve_type": "user", "usage": "all" } ], + "PCW_CORE0_FIQ_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_CORE0_IRQ_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_CORE1_FIQ_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_CORE1_IRQ_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_VALUE_SILVERSION": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_GP0_EN_MODIFIABLE_TXN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_GP1_EN_MODIFIABLE_TXN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_IMPORT_BOARD_PRESET": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "PCW_PERIPHERAL_BOARD_PRESET": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "PCW_PRESET_BANK0_VOLTAGE": [ { "value": "LVCMOS 3.3V", "resolve_type": "user", "usage": "all" } ], + "PCW_PRESET_BANK1_VOLTAGE": [ { "value": "LVCMOS 3.3V", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_ENABLE": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_ADV_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_MEMORY_TYPE": [ { "value": "DDR 3", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_ECC": [ { "value": "Disabled", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_BUS_WIDTH": [ { "value": "16 Bit", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_BL": [ { "value": "8", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_HIGH_TEMP": [ { "value": "Normal (0-85)", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_PARTNO": [ { "value": "MT41J256M16 RE-125", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_DRAM_WIDTH": [ { "value": "16 Bits", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_DEVICE_CAPACITY": [ { "value": "4096 MBits", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_SPEED_BIN": [ { "value": "DDR3_1066F", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_TRAIN_READ_GATE": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_TRAIN_DATA_EYE": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_CLOCK_STOP_EN": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_USE_INTERNAL_VREF": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_DDR_PRIORITY_WRITEPORT_0": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_PRIORITY_WRITEPORT_2": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_PRIORITY_READPORT_0": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_PRIORITY_READPORT_2": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_PORT0_HPR_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_PORT1_HPR_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_PORT2_HPR_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_PORT3_HPR_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_HPRLPR_QUEUE_PARTITION": [ { "value": "HPR(0)/LPR(32)", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL": [ { "value": "2", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL": [ { "value": "15", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL": [ { "value": "2", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_NAND_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NAND_NAND_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_NOR_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_GRP_CS0_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_GRP_CS0_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_GRP_CS1_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_GRP_CS1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_GRP_SRAM_INT_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_GRP_SRAM_INT_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SINGLE_QSPI_DATA_MODE": [ { "value": "x4", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_DUAL_STACK_QSPI_DATA_MODE": [ { "value": "", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_QSPI_GRP_IO1_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_QSPI_GRP_IO1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_QSPI_INTERNAL_HIGHADDRESS": [ { "value": "0xFDFFFFFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_ENET0_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_ENET0_ENET0_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_ENET_RESET_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_ENET_RESET_SELECT": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_ENET1_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_ENET1_ENET1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_ENET1_RESET_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_ENET1_RESET_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SD0_GRP_CD_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SD0_GRP_CD_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SD0_GRP_POW_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SD0_GRP_POW_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SD1_GRP_CD_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SD1_GRP_CD_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SD1_GRP_POW_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SD1_GRP_POW_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UART0_GRP_FULL_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UART0_GRP_FULL_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SPI0_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_SPI0_SPI0_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SPI0_GRP_SS1_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SPI0_GRP_SS1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SPI1_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_SPI1_SPI1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SPI1_GRP_SS1_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SPI1_GRP_SS1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_CAN0_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_CAN0_CAN0_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_CAN1_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_CAN1_CAN1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_TRACE_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_TRACE_TRACE_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_TRACE_GRP_4BIT_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_TRACE_GRP_4BIT_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_TRACE_GRP_16BIT_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_TRACE_GRP_16BIT_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_TRACE_INTERNAL_WIDTH": [ { "value": "2", "resolve_type": "user", "usage": "all" } ], + "PCW_WDT_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_WDT_WDT_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_TTC1_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_TTC1_TTC1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_USB0_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_USB0_USB0_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_USB0_RESET_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_USB0_RESET_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_USB1_RESET_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_USB1_RESET_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C0_GRP_INT_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C0_GRP_INT_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C1_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_I2C1_I2C1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C_RESET_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C_RESET_SELECT": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_GPIO_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_GPIO_MIO_GPIO_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_GPIO_MIO_GPIO_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_7_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_7_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_8_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_8_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_14_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_14_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_15_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_15_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_16_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_16_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_17_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_17_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_18_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_18_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_19_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_19_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_20_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_20_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_21_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_21_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_22_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_22_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_23_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_23_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_24_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_24_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_25_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_25_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_26_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_26_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_27_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_27_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_28_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_28_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_29_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_29_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_30_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_30_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_31_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_31_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_32_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_32_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_33_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_33_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_34_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_34_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_35_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_35_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_36_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_36_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_37_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_37_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_38_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_38_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_39_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_39_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_40_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_40_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_41_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_41_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_42_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_42_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_43_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_43_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_44_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_44_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_45_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_45_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_46_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_46_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_47_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_47_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_50_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_50_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_51_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_51_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_52_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_52_SLEW": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_53_IOTYPE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_MIO_53_SLEW": [ { "value": "