axi4stream_vip_axi4streampc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2019.1/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv,incdir="../../../../dx_pwr_basic.srcs/sources_1/ip/ila_cnt/hdl/verilog"
axi_vip_axi4pc.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2019.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv,incdir="../../../../dx_pwr_basic.srcs/sources_1/ip/ila_cnt/hdl/verilog"
xil_common_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2019.1/data/xilinx_vip/hdl/xil_common_vip_pkg.sv,incdir="../../../../dx_pwr_basic.srcs/sources_1/ip/ila_cnt/hdl/verilog"
axi4stream_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2019.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv,incdir="../../../../dx_pwr_basic.srcs/sources_1/ip/ila_cnt/hdl/verilog"
axi_vip_pkg.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2019.1/data/xilinx_vip/hdl/axi_vip_pkg.sv,incdir="../../../../dx_pwr_basic.srcs/sources_1/ip/ila_cnt/hdl/verilog"
axi4stream_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2019.1/data/xilinx_vip/hdl/axi4stream_vip_if.sv,incdir="../../../../dx_pwr_basic.srcs/sources_1/ip/ila_cnt/hdl/verilog"
axi_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2019.1/data/xilinx_vip/hdl/axi_vip_if.sv,incdir="../../../../dx_pwr_basic.srcs/sources_1/ip/ila_cnt/hdl/verilog"
clk_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2019.1/data/xilinx_vip/hdl/clk_vip_if.sv,incdir="../../../../dx_pwr_basic.srcs/sources_1/ip/ila_cnt/hdl/verilog"
rst_vip_if.sv,systemverilog,xilinx_vip,../../../../../tools/Xilinx/Vivado/2019.1/data/xilinx_vip/hdl/rst_vip_if.sv,incdir="../../../../dx_pwr_basic.srcs/sources_1/ip/ila_cnt/hdl/verilog"
xpm_cdc.sv,systemverilog,xil_defaultlib,../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../dx_pwr_basic.srcs/sources_1/ip/ila_cnt/hdl/verilog"
xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../dx_pwr_basic.srcs/sources_1/ip/ila_cnt/hdl/verilog"
xpm_VCOMP.vhd,vhdl,xpm,../../../../../tools/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../dx_pwr_basic.srcs/sources_1/ip/ila_cnt/hdl/verilog"
ila_cnt.v,verilog,xil_defaultlib,../../../../dx_pwr_basic.srcs/sources_1/ip/ila_cnt/sim/ila_cnt.v,incdir="../../../../dx_pwr_basic.srcs/sources_1/ip/ila_cnt/hdl/verilog"
glbl.v,Verilog,xil_defaultlib,glbl.v
