add ax7020 pl project, including mpsoc bd core only
This commit is contained in:
+1287
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{
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"graphjs": {
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"version": "1.0",
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||||||
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"keys": [
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{
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||||||
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"abrv": "VH",
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||||||
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"name": "vert_hid",
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||||||
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"type": "int",
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||||||
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"for": "node"
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||||||
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},
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||||||
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{
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||||||
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"abrv": "VM",
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||||||
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"name": "vert_name",
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||||||
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"type": "string",
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||||||
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"for": "node"
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||||||
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},
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||||||
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{
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||||||
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"abrv": "VT",
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||||||
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"name": "vert_type",
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||||||
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"type": "string",
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||||||
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"for": "node"
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||||||
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},
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||||||
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{
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||||||
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"abrv": "BA",
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||||||
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"name": "base_addr",
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||||||
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"type": "string",
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||||||
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"for": "node"
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||||||
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},
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||||||
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{
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||||||
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"abrv": "HA",
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||||||
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"name": "high_addr",
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||||||
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"type": "string",
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||||||
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"for": "node"
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},
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{
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"abrv": "BP",
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"name": "base_param",
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||||||
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"type": "string",
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||||||
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"for": "node"
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||||||
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},
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||||||
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{
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||||||
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"abrv": "HP",
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"name": "high_param",
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"type": "string",
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||||||
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"for": "node"
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},
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{
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||||||
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"abrv": "MA",
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||||||
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"name": "master_addrspace",
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||||||
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"type": "string",
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||||||
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"for": "node"
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||||||
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},
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||||||
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{
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||||||
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"abrv": "MX",
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||||||
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"name": "master_instance",
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"type": "string",
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||||||
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"for": "node"
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},
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||||||
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{
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||||||
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"abrv": "MI",
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||||||
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"name": "master_interface",
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"type": "string",
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||||||
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"for": "node"
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},
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{
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"abrv": "MS",
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"name": "master_segment",
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"type": "string",
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||||||
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"for": "node"
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},
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{
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"abrv": "MV",
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"name": "master_vlnv",
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"type": "string",
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"for": "node"
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},
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{
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"abrv": "SX",
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"name": "slave_instance",
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"type": "string",
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"for": "node"
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},
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{
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"abrv": "SI",
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"name": "slave_interface",
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"type": "string",
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||||||
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"for": "node"
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||||||
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},
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||||||
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{
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"abrv": "MM",
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"name": "slave_memmap",
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"type": "string",
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||||||
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"for": "node"
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},
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{
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"abrv": "SS",
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"name": "slave_segment",
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"type": "string",
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"for": "node"
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},
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{
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||||||
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"abrv": "SV",
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"name": "slave_vlnv",
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"type": "string",
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"for": "node"
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},
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||||||
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{
|
||||||
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"abrv": "TM",
|
||||||
|
"name": "memory_type",
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||||||
|
"type": "string",
|
||||||
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"for": "node"
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||||||
|
},
|
||||||
|
{
|
||||||
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"abrv": "TU",
|
||||||
|
"name": "usage_type",
|
||||||
|
"type": "string",
|
||||||
|
"for": "node"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"abrv": "LT",
|
||||||
|
"name": "lock_type",
|
||||||
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"type": "string",
|
||||||
|
"for": "node"
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||||||
|
},
|
||||||
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{
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||||||
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"abrv": "BT",
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||||||
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"name": "boot_type",
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||||||
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"type": "string",
|
||||||
|
"for": "node"
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||||||
|
},
|
||||||
|
{
|
||||||
|
"abrv": "EH",
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||||||
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"name": "edge_hid",
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||||||
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"type": "int",
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||||||
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"for": "edge"
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||||||
|
}
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||||||
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],
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||||||
|
"vertice_type_order": [
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|
{
|
||||||
|
"abrv": "BC",
|
||||||
|
"desc": "Block Container"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"abrv": "PR",
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||||||
|
"desc": "Parital Reference"
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|
},
|
||||||
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{
|
||||||
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"abrv": "VR",
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||||||
|
"desc": "Variant"
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||||||
|
},
|
||||||
|
{
|
||||||
|
"abrv": "PM",
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||||||
|
"desc": "Variant Permutations"
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||||||
|
},
|
||||||
|
{
|
||||||
|
"abrv": "CX",
|
||||||
|
"desc": "Boundary Connection"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"abrv": "AC",
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||||||
|
"desc": "Assignment Coordinate"
|
||||||
|
},
|
||||||
|
{
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||||||
|
"abrv": "ACE",
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||||||
|
"desc": "Excluded Assign Coordinate"
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},
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||||||
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{
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||||||
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"abrv": "APX",
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||||||
|
"desc": "Boundary Aperture"
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},
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{
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||||||
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"abrv": "CIP",
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||||||
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"desc": "High level Processing System"
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}
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],
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"vertices": {
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"V0": {
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"VM": "system_bd",
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"VT": "BC"
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},
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"V1": {
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"VH": "2",
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"VM": "system_bd",
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"VT": "VR"
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},
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"V2": {
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"VH": "2",
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"VT": "PM",
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"TU": "active"
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}
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},
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"edges": [
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{
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"src": "V0",
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"trg": "V1"
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},
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{
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||||||
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"src": "V1",
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||||||
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"trg": "V2"
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||||||
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}
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||||||
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]
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||||||
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}
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||||||
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}
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+20
@@ -0,0 +1,20 @@
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{
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||||||
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"ActiveEmotionalView":"Default View",
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"Default View_ScaleFactor":"1.0",
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"Default View_TopLeft":"-634,-314",
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"ExpandedHierarchyInLayout":"",
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"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
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# -string -flagsOSRD
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preplace port DDR -pg 1 -lvl 2 -x 440 -y 60 -defaultsOSRD
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preplace port FIXED_IO -pg 1 -lvl 2 -x 440 -y 80 -defaultsOSRD
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preplace inst processing_system7 -pg 1 -lvl 1 -x 220 -y 90 -defaultsOSRD
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preplace netloc processing_system7_FCLK_CLK0 1 0 2 20 180 420
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preplace netloc processing_system7_DDR 1 1 1 NJ 60
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preplace netloc processing_system7_FIXED_IO 1 1 1 NJ 80
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levelinfo -pg 1 0 220 440
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pagesize -pg 1 -db -bbox -sgen 0 0 560 190
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"
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}
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||||||
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{
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||||||
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"da_ps7_cnt":"1"
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}
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@@ -0,0 +1,264 @@
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2024.1 (64-bit) -->
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<!-- -->
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||||||
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<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
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||||||
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<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. -->
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||||||
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<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Workspace/vivado/vivado_pub/projects/ax7020/ax7020_basic/ax7020_basic.xpr">
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||||||
|
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||||
|
<Configuration>
|
||||||
|
<Option Name="Id" Val="b90538f38420416783434bce07863111"/>
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||||||
|
<Option Name="Part" Val="xc7z020clg400-2"/>
|
||||||
|
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||||
|
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||||
|
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||||
|
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||||
|
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||||
|
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||||
|
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||||
|
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||||
|
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||||
|
<Option Name="SimulatorVersionXsim" Val="2024.1"/>
|
||||||
|
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||||
|
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||||
|
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||||
|
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||||
|
<Option Name="SimulatorVersionRiviera" Val="2023.04"/>
|
||||||
|
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||||
|
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||||
|
<Option Name="BoardPart" Val=""/>
|
||||||
|
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||||
|
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="ProjectType" Val="Default"/>
|
||||||
|
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||||
|
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||||
|
<Option Name="IPCachePermission" Val="read"/>
|
||||||
|
<Option Name="IPCachePermission" Val="write"/>
|
||||||
|
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||||
|
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||||
|
<Option Name="SimCompileState" Val="TRUE"/>
|
||||||
|
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||||
|
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||||
|
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||||
|
<Option Name="EnableBDX" Val="FALSE"/>
|
||||||
|
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTXSimExportSim" Val="1"/>
|
||||||
|
<Option Name="WTModelSimExportSim" Val="1"/>
|
||||||
|
<Option Name="WTQuestaExportSim" Val="1"/>
|
||||||
|
<Option Name="WTIesExportSim" Val="0"/>
|
||||||
|
<Option Name="WTVcsExportSim" Val="1"/>
|
||||||
|
<Option Name="WTRivieraExportSim" Val="1"/>
|
||||||
|
<Option Name="WTActivehdlExportSim" Val="1"/>
|
||||||
|
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||||
|
<Option Name="XSimRadix" Val="hex"/>
|
||||||
|
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||||
|
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||||
|
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||||
|
<Option Name="SimTypes" Val="rtl"/>
|
||||||
|
<Option Name="SimTypes" Val="bfm"/>
|
||||||
|
<Option Name="SimTypes" Val="tlm"/>
|
||||||
|
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||||
|
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||||
|
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||||
|
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||||
|
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||||
|
</Configuration>
|
||||||
|
<FileSets Version="1" Minor="32">
|
||||||
|
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||||
|
<Filter Type="Srcs"/>
|
||||||
|
<File Path="$PSRCDIR/sources_1/bd/system_bd/system_bd.bd">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_processing_system7_0_0/system_bd_processing_system7_0_0.xci">
|
||||||
|
<Proxy FileSetName="system_bd_processing_system7_0_0"/>
|
||||||
|
</CompFileExtendedInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PGENDIR/sources_1/bd/system_bd/hdl/system_bd_wrapper.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="system_bd_wrapper"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||||
|
<Filter Type="Constrs"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="ConstrsType" Val="XDC"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="system_bd_wrapper"/>
|
||||||
|
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
<Option Name="TransportPathDelay" Val="0"/>
|
||||||
|
<Option Name="TransportIntDelay" Val="0"/>
|
||||||
|
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||||
|
<Option Name="PamDesignTestbench" Val=""/>
|
||||||
|
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||||
|
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||||
|
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||||
|
<Option Name="SrcSet" Val="sources_1"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||||
|
<Filter Type="Utils"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="system_bd_processing_system7_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_processing_system7_0_0" RelGenDir="$PGENDIR/system_bd_processing_system7_0_0">
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopModule" Val="system_bd_processing_system7_0_0"/>
|
||||||
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
</FileSets>
|
||||||
|
<Simulators>
|
||||||
|
<Simulator Name="XSim">
|
||||||
|
<Option Name="Description" Val="Vivado Simulator"/>
|
||||||
|
<Option Name="CompiledLib" Val="0"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="ModelSim">
|
||||||
|
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Questa">
|
||||||
|
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Xcelium">
|
||||||
|
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="VCS">
|
||||||
|
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Riviera">
|
||||||
|
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
</Simulators>
|
||||||
|
<Runs Version="1" Minor="22">
|
||||||
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="system_bd_processing_system7_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_processing_system7_0_0" Part="xc7z020clg400-2" ConstrsSet="system_bd_processing_system7_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_processing_system7_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_synth_1" ParallelReportGen="true">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="system_bd_processing_system7_0_0_impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-2" ConstrsSet="system_bd_processing_system7_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_processing_system7_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_processing_system7_0_0_impl_1" ParallelReportGen="true">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
</Runs>
|
||||||
|
<Board/>
|
||||||
|
<DashboardSummary Version="1" Minor="0">
|
||||||
|
<Dashboards>
|
||||||
|
<Dashboard Name="default_dashboard">
|
||||||
|
<Gadgets>
|
||||||
|
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||||
|
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||||
|
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
</Gadgets>
|
||||||
|
</Dashboard>
|
||||||
|
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||||
|
</Dashboards>
|
||||||
|
</DashboardSummary>
|
||||||
|
</Project>
|
||||||
@@ -0,0 +1,3 @@
|
|||||||
|
version https://git-lfs.github.com/spec/v1
|
||||||
|
oid sha256:c02be7f3d3efe5ae730ed5de72670196369f3883224393a22e41929c14ca9e59
|
||||||
|
size 301424
|
||||||
Reference in New Issue
Block a user