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"physical_name": "rd_clk" } ] + } + }, + "FIFO_WRITE": { + "vlnv": "xilinx.com:interface:fifo_write:1.0", + "abstraction_type": "xilinx.com:interface:fifo_write_rtl:1.0", + "mode": "slave", + "port_maps": { + "FULL": [ { "physical_name": "full" } ], + "WR_DATA": [ { "physical_name": "din" } ], + "WR_EN": [ { "physical_name": "wr_en" } ] + } + }, + "FIFO_READ": { + "vlnv": "xilinx.com:interface:fifo_read:1.0", + "abstraction_type": "xilinx.com:interface:fifo_read_rtl:1.0", + "mode": "slave", + "port_maps": { + "EMPTY": [ { "physical_name": "empty" } ], + "RD_DATA": [ { "physical_name": "dout" } ], + "RD_EN": [ { "physical_name": "rd_en" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_dual.v b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_dual.v new file mode 100644 index 00000000..5e308fa1 --- /dev/null +++ b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_dual.v @@ -0,0 +1,196 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/07/01 17:37:27 +// Last Modified Date: 2023/03/06 11:26 +// Design Name: +// Module Name: ad9361_rx_map_cmos_dual +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ad9361_rx_map_cmos_dual +( + input clk_2x_in , + input clk_in_rst , + + input rx_data_clk , // sync to output data + input rx_data_clk_rst , + + input rx_fifo_rst , // async fifo reset + + input rx_frame , + input [11:0] rx_data , + + output [11:0] rx_ch1_i , + output [11:0] rx_ch1_q , + output [11:0] rx_ch2_i , + output [11:0] rx_ch2_q +); + +genvar m; + +// rx data +wire [11:0] rx_data_i, rx_data_q; + +generate +for (m=0; m<12; m=m+1) begin : rx_data_iddr + +IDDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT_Q1 (1'b0 ), + .INIT_Q2 (1'b0 ), + .SRTYPE ("ASYNC" ) +) i_rx_data_iddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_2x_in ), + .D (rx_data[m] ), + .Q1 (rx_data_q[m] ), + .Q2 (rx_data_i[m] ) +); + +end +endgenerate + +// rx frame +wire rx_frame_i; +wire rx_frame_q; + +IDDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT_Q1 (1'b0 ), + .INIT_Q2 (1'b0 ), + .SRTYPE ("ASYNC" ) +) i_rx_frame_iddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_2x_in ), + .D (rx_frame ), + .Q1 (rx_frame_q ), + .Q2 (rx_frame_i ) +); + +// divide rx_data to dual channel +reg [11:0] rx1_data_i = 'b0; +reg [11:0] rx1_data_q = 'b0; +reg [11:0] rx2_data_i = 'b0; +reg [11:0] rx2_data_q = 'b0; + +wire rx_fifo_wr_en; +reg rx_fifo_rd_en = 'b0; + +wire rx_fifo_empty_1; +wire rx_fifo_empty_2; +wire rx_fifo_empty_3; +wire rx_fifo_empty_4; + +assign rx_fifo_wr_en = rx_frame_i; // align data & write enable + +always @ (posedge clk_2x_in) begin + if (clk_in_rst) begin + rx1_data_i <= 'b0; + rx2_data_i <= 'b0; + end + else if(rx_frame_i) begin + rx1_data_i <= rx_data_i; + end + else begin + rx2_data_i <= rx_data_i; + end +end + +always @ (posedge clk_2x_in) begin + if (clk_in_rst) begin + rx1_data_q <= 'b0; + rx2_data_q <= 'b0; + end + else if(rx_frame_q) begin + rx1_data_q <= rx_data_q; + end + else begin + rx2_data_q <= rx_data_q; + end +end + +always @(posedge rx_data_clk) begin + if (rx_data_clk_rst) begin + rx_fifo_rd_en <= 'b0; + end + else begin + rx_fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4}; + end +end + +ad9361_fifo u_rx_fifo_ch1_i +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_2x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx1_data_i ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_ch1_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_1) // output wire empty +); + +ad9361_fifo u_rx_fifo_ch1_q +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_2x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx1_data_q ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_ch1_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_2) // output wire empty +); + +ad9361_fifo u_rx_fifo_ch2_i +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_2x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx2_data_i ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_ch2_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_3) // output wire empty +); + +ad9361_fifo u_rx_fifo_ch2_q +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_2x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx2_data_q ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_ch2_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_4) // output wire empty +); + +endmodule diff --git a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_single.v b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_single.v new file mode 100644 index 00000000..c5bb387a --- /dev/null +++ b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_single.v @@ -0,0 +1,124 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/07/01 17:37:27 +// Last Modified Date: 2023/03/03 13:01 +// Design Name: +// Module Name: ad9361_rx_map_cmos_single +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ad9361_rx_map_cmos_single +( + input clk_in , + input clk_in_rst , + + input rx_data_clk , + input rx_data_clk_rst , + + input rx_fifo_rst , + + input rx_frame , + input [11:0] rx_data , + + output [11:0] rx_data_i , + output [11:0] rx_data_q +); + +genvar m; + +// rx data +wire [11:0] rx_raw_i, rx_raw_q; + +generate +for (m=0; m<12; m=m+1) begin : rx_data_iddr + +IDDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT_Q1 (1'b0 ), + .INIT_Q2 (1'b0 ), + .SRTYPE ("ASYNC" ) +) i_rx_data_iddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_in ), + .D (rx_data[m] ), + .Q1 (rx_raw_q[m] ), + .Q2 (rx_raw_i[m] ) +); + +end +endgenerate + + +// divide rx_data to dual channel +reg rx_fifo_wr_en = 1'b0; +reg rx_fifo_rd_en = 'b0; + +wire rx_fifo_empty_1; +wire rx_fifo_empty_2; + +always @(posedge clk_in) begin + if (clk_in_rst) begin + rx_fifo_wr_en <= 1'b0; + end + else begin + rx_fifo_wr_en <= 1'b1; + end +end + +always @(posedge rx_data_clk) begin + if (rx_data_clk_rst) begin + rx_fifo_rd_en <= 'b0; + end + else begin + rx_fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2}; + end +end + +ad9361_fifo u_rx_fifo_i +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx_raw_i ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_data_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_1) // output wire empty +); + +ad9361_fifo u_rx_fifo_q +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx_raw_q ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_data_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_2) // output wire empty +); + +endmodule diff --git a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_lvds_dual.v b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_lvds_dual.v new file mode 100644 index 00000000..026330d0 --- /dev/null +++ b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_lvds_dual.v @@ -0,0 +1,277 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/07/01 17:37:27 +// Last Modified Date: 2023/03/06 10:54 +// Design Name: +// Module Name: ad9361_rx_mapping_dual +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ad9361_rx_map_lvds_dual +( + input clk_4x_in , // sync to input data + input clk_in_rst , + + input rx_data_clk , // sync to output data + input rx_data_clk_rst , + + input rx_fifo_rst , // async fifo reset + + input rx_frame_p , + input rx_frame_n , + input [ 5:0] rx_data_p , // data from ad9361 p1 port + input [ 5:0] rx_data_n , + + output [11:0] rx_ch1_i , + output [11:0] rx_ch1_q , + output [11:0] rx_ch2_i , + output [11:0] rx_ch2_q +); + +genvar m; + +// rx data +wire [5:0] rx_data; +wire [5:0] rx_data_i, rx_data_q; + +generate +for (m=0; m<6; m=m+1) begin : rx_data_iddr + +IBUFDS #( + .DIFF_TERM ("TRUE" ) +) u_ibufds_rx_data +( + .I (rx_data_p[m] ), + .IB (rx_data_n[m] ), + .O (rx_data[m] ) +); + +IDDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT_Q1 (1'b0 ), + .INIT_Q2 (1'b0 ), + .SRTYPE ("ASYNC" ) +) u_rx_data_iddr ( + .CE (1'b1 ), // clock enable + .R (1'b0 ), // iddr reset + .S (1'b0 ), // iddr set + .C (clk_4x_in ), // iddr clock + .D (rx_data[m] ), // ddr data + .Q1 (rx_data_q[m] ), // sdr data at rising edge + .Q2 (rx_data_i[m] ) // sdr data at falling edge +); + +end +endgenerate + +// rx frame +wire rx_frame; +wire rx_frame_i; +wire rx_frame_q; + +IBUFDS #( + .DIFF_TERM ("TRUE" ) +) u_ibufds_rx_frame +( + .I (rx_frame_p ), + .IB (rx_frame_n ), + .O (rx_frame ) +); + +IDDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT_Q1 (1'b0 ), + .INIT_Q2 (1'b0 ), + .SRTYPE ("ASYNC" ) +) u_rx_frame_iddr ( + .CE (1'b1 ), // clock enable + .R (1'b0 ), // iddr reset + .S (1'b0 ), // iddr set + .C (clk_4x_in ), // iddr clock + .D (rx_frame ), // ddr data + .Q1 (rx_frame_q ), // sdr data at rising edge + .Q2 (rx_frame_i ) // sdr data at falling edge +); + +// unpack rx frame & data +reg rx_frame_i_d1 = 'b0; +reg [ 5:0] rx_data_i_d1 = 'b0; +reg [ 5:0] rx_data_q_d1 = 'b0; +reg rx_flag = 'b0; // rx frame rising edge indicator +reg [ 1:0] rx_cnt = 'b0; // unpack stage counter + +always @(posedge clk_4x_in) begin + // wait for [rx_flag] + rx_frame_i_d1 <= rx_frame_i; + rx_data_i_d1 <= rx_data_i; + rx_data_q_d1 <= rx_data_q; +end + +always @(posedge clk_4x_in) begin + if (clk_in_rst) begin + rx_flag <= 'b0; + end + else if (~rx_frame_i_d1 & rx_frame_i) begin + // assert when rising edge of rx frame is detected + rx_flag <= 'b1; + end + else begin + rx_flag <= rx_flag; + end +end + +always @(posedge clk_4x_in) begin + if (clk_in_rst) begin + rx_cnt <= 'b0; + end + else begin + rx_cnt <= (rx_flag) ? rx_cnt + 1'b1 : rx_cnt; + end +end + +reg [11:0] rx1_data_i = 'b0; +reg [11:0] rx1_data_q = 'b0; +reg [11:0] rx2_data_i = 'b0; +reg [11:0] rx2_data_q = 'b0; + +always @(posedge clk_4x_in) begin + if (clk_in_rst) begin + rx1_data_i <= 'b0; + rx1_data_q <= 'b0; + rx2_data_i <= 'b0; + rx2_data_q <= 'b0; + end + else begin + case (rx_cnt) + 3'd0: begin + // 1st clock cycle: upper 6-bit of rx ch1 inphase/quadrature data + rx1_data_i[11:6] <= rx_data_i_d1; + rx1_data_q[11:6] <= rx_data_q_d1; + end + 3'd1: begin + // 2nd clock cycle: lower 6-bit of rx ch1 inphase/quadrature data + rx1_data_i[ 5:0] <= rx_data_i_d1; + rx1_data_q[ 5:0] <= rx_data_q_d1; + end + 3'd2: begin + // 3rd clock cycle: upper 6-bit of rx ch2 inphase/quadrature data + rx2_data_i[11:6] <= rx_data_i_d1; + rx2_data_q[11:6] <= rx_data_q_d1; + end + 3'd3: begin + // 4th clock cycle: lower 6-bit of rx ch2 inphase/quadrature data + rx2_data_i[ 5:0] <= rx_data_i_d1; + rx2_data_q[ 5:0] <= rx_data_q_d1; + end + default: begin + rx1_data_i <= 'b0; + rx1_data_q <= 'b0; + rx2_data_i <= 'b0; + rx2_data_q <= 'b0; + end + endcase + end +end + +// write fifo when rx1/2_data_i/q are all prepared with 192MHz clock +// read fifo at every clock cycle with 48MHz clock +reg fifo_wr_en = 'b0; +reg fifo_rd_en = 'b0; +wire rx_fifo_empty_1; +wire rx_fifo_empty_2; +wire rx_fifo_empty_3; +wire rx_fifo_empty_4; + +always @(posedge clk_4x_in) begin + if (clk_in_rst) begin + fifo_wr_en <= 'b0; + end + else if (rx_cnt == 2'd3) begin + fifo_wr_en <= 1'b1; + end + else begin + fifo_wr_en <= 'b0; + end +end + +always @(posedge rx_data_clk) begin + if (rx_data_clk_rst) begin + fifo_rd_en <= 1'b0; + end + else begin + fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4}; + end +end + +ad9361_fifo u_rx_fifo_ch1_i +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_4x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx1_data_i ), // input wire [11 : 0] din + .wr_en (fifo_wr_en ), // input wire wr_en + .rd_en (fifo_rd_en ), // input wire rd_en + .dout (rx_ch1_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_1) // output wire empty +); + +ad9361_fifo u_rx_fifo_ch1_q +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_4x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx1_data_q ), // input wire [11 : 0] din + .wr_en (fifo_wr_en ), // input wire wr_en + .rd_en (fifo_rd_en ), // input wire rd_en + .dout (rx_ch1_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_2) // output wire empty +); + +ad9361_fifo u_rx_fifo_ch2_i +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_4x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx2_data_i ), // input wire [11 : 0] din + .wr_en (fifo_wr_en ), // input wire wr_en + .rd_en (fifo_rd_en ), // input wire rd_en + .dout (rx_ch2_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_3) // output wire empty +); + +ad9361_fifo u_rx_fifo_ch2_q +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_4x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx2_data_q ), // input wire [11 : 0] din + .wr_en (fifo_wr_en ), // input wire wr_en + .rd_en (fifo_rd_en ), // input wire rd_en + .dout (rx_ch2_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_4) // output wire empty +); + +endmodule diff --git a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_dual.v b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_dual.v new file mode 100644 index 00000000..7fb0b8a8 --- /dev/null +++ b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_dual.v @@ -0,0 +1,183 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/07/01 16:39:19 +// Last Modified Date: 2023/03/06 11:45 +// Design Name: +// Module Name: ad9361_tx_map_cmos_dual +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ad9361_tx_map_cmos_dual +( + input clk_2x_in , + input clk_in_rst , + + input tx_data_clk , + input tx_data_clk_rst , + + input [11:0] tx_ch1_i , + input [11:0] tx_ch1_q , + input [11:0] tx_ch2_i , + input [11:0] tx_ch2_q , + + output clk_out , + output tx_frame , + output [11:0] tx_data +); + +genvar m; + +// input data fifo +reg rx_fifo_rd_en = 'b0; +wire [11:0] tx_fifo_ch1_i; +wire [11:0] tx_fifo_ch1_q; +wire [11:0] tx_fifo_ch2_i; +wire [11:0] tx_fifo_ch2_q; + +always @(posedge clk_2x_in) begin + if (clk_in_rst) begin + rx_fifo_rd_en <= 'b0; + end + else begin + rx_fifo_rd_en <= ~rx_fifo_rd_en; + end +end + +ad9361_fifo u_tx_fifo_ch1_i +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_2x_in ), // input wire rd_clk + .din (tx_ch1_i ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (tx_fifo_ch1_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +ad9361_fifo u_tx_fifo_ch1_q +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_2x_in ), // input wire rd_clk + .din (tx_ch1_q ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (tx_fifo_ch1_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +ad9361_fifo u_tx_fifo_ch2_i +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_2x_in ), // input wire rd_clk + .din (tx_ch2_i ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (tx_fifo_ch2_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +ad9361_fifo u_tx_fifo_ch2_q +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_2x_in ), // input wire rd_clk + .din (tx_ch2_q ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (tx_fifo_ch2_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +// frame and data control +reg tx_frame_i = 'b0; +reg tx_frame_q = 'b0; +reg [11:0] tx_data_i = 'b0; +reg [11:0] tx_data_q = 'b0; + +always @(posedge clk_2x_in) begin + if (clk_in_rst) begin + tx_frame_i <= 'b0; + tx_frame_q <= 'b0; + tx_data_i <= 'b0; + tx_data_q <= 'b0; + end + else if (rx_fifo_rd_en == 1'b0) begin + tx_frame_i <= 1'b1; + tx_frame_q <= 1'b1; + tx_data_i <= tx_fifo_ch1_i; + tx_data_q <= tx_fifo_ch1_q; + end + else begin + tx_frame_i <= 1'b0; + tx_frame_q <= 1'b0; + tx_data_i <= tx_fifo_ch2_i; + tx_data_q <= tx_fifo_ch2_q; + end +end + +// output clock to port +assign clk_out = clk_2x_in; + +// output tx frame to port +ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT (1'b0 ), + .SRTYPE ("ASYNC" ) +) u_tx_frame_oddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_2x_in ), + .D1 (tx_frame_i ), + .D2 (tx_frame_q ), + .Q (tx_frame ) +); + +// output tx data to port +generate +for (m=0; m<12; m=m+1) begin: tx_data_oddr + +ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT (1'b0 ), + .SRTYPE ("ASYNC" ) +) u_tx_data_oddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_2x_in ), + .D1 (tx_data_i[m] ), + .D2 (tx_data_q[m] ), + .Q (tx_data[m] ) +); + +end +endgenerate + +endmodule diff --git a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_single.v b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_single.v new file mode 100644 index 00000000..ad614384 --- /dev/null +++ b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_single.v @@ -0,0 +1,119 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/07/01 16:39:19 +// Design Name: +// Module Name: ad9361_tx_mapping_single +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ad9361_tx_map_cmos_single +( + input clk_in , + input clk_in_rst , + + input tx_data_clk , + input tx_data_clk_rst , + + input [11:0] tx_data_i , + input [11:0] tx_data_q , + + output clk_out , + output tx_frame , + output [11:0] tx_data +); + +genvar m; + +// inout data fifo +wire [11:0] tx_fifo_i; +wire [11:0] tx_fifo_q; + +ad9361_fifo u_tx_fifo_i +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_in ), // input wire rd_clk + .din (tx_data_i ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (1'b1 ), // input wire rd_en + .dout (tx_fifo_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +ad9361_fifo u_tx_fifo_q +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_in ), // input wire rd_clk + .din (tx_data_q ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (1'b1 ), // input wire rd_en + .dout (tx_fifo_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +// frame and data control +assign tx_frame_i = 1'b1; +assign tx_frame_q = 1'b0; + +// output clock to port +assign clk_out = clk_in; + +// output tx frame to port +ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT (1'b0 ), + .SRTYPE ("ASYNC" ) +) u_tx_frame_oddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_in ), + .D1 (tx_frame_i ), + .D2 (tx_frame_q ), + .Q (tx_frame ) +); + +// output tx data to port +generate +for (m=0; m<12; m=m+1) begin: tx_data_oddr + +ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT (1'b0 ), + .SRTYPE ("ASYNC" ) +) u_tx_data_oddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_in ), + .D1 (tx_fifo_i[m] ), + .D2 (tx_fifo_q[m] ), + .Q (tx_data[m] ) +); + +end +endgenerate + +endmodule diff --git a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_lvds_dual.v b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_lvds_dual.v new file mode 100644 index 00000000..0775eb88 --- /dev/null +++ b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_lvds_dual.v @@ -0,0 +1,246 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2023/03/05 23:21:27 +// Last Modified Date: 2023/03/06 11:01 +// Design Name: +// Module Name: ad9361_tx_map_lvds_dual +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ad9361_tx_map_lvds_dual +( + input clk_4x_in , + input clk_in_rst , + + input tx_data_clk , + input tx_data_clk_rst , + + input [11:0] tx_ch1_i , + input [11:0] tx_ch1_q , + input [11:0] tx_ch2_i , + input [11:0] tx_ch2_q , + + output clk_out_p , + output clk_out_n , + output tx_frame_p , + output tx_frame_n , + output [ 5:0] tx_data_p , + output [ 5:0] tx_data_n +); + +genvar m; + +// input data fifo +reg [1:0] tx_control_cnt = 'b0; +reg rx_fifo_rd_en = 'b0; +wire [11:0] tx_fifo_ch1_i; +wire [11:0] tx_fifo_ch1_q; +wire [11:0] tx_fifo_ch2_i; +wire [11:0] tx_fifo_ch2_q; + +always @(posedge clk_4x_in) begin + if (clk_in_rst) begin + tx_control_cnt <= 'b0; + end + else begin + tx_control_cnt <= tx_control_cnt + 1'b1; + end +end + +always @(posedge clk_4x_in) begin + if (clk_in_rst) begin + rx_fifo_rd_en <= 'b0; + end + else if (tx_control_cnt == 2'd2) begin + rx_fifo_rd_en <= 1'b1; + end + else begin + rx_fifo_rd_en <= 'b0; + end +end + +ad9361_fifo u_tx_fifo_ch1_i +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_4x_in ), // input wire rd_clk + .din (tx_ch1_i ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (tx_fifo_ch1_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +ad9361_fifo u_tx_fifo_ch1_q +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_4x_in ), // input wire rd_clk + .din (tx_ch1_q ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (tx_fifo_ch1_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +ad9361_fifo u_tx_fifo_ch2_i +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_4x_in ), // input wire rd_clk + .din (tx_ch2_i ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (tx_fifo_ch2_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +ad9361_fifo u_tx_fifo_ch2_q +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_4x_in ), // input wire rd_clk + .din (tx_ch2_q ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (tx_fifo_ch2_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + + +// frame and data control +reg tx_frame_r = 'b0; // rising edge data +reg tx_frame_f = 'b0; // falling edge data +reg [5:0] tx_data_r = 'b0; +reg [5:0] tx_data_f = 'b0; + +always @(posedge clk_4x_in) begin + if (clk_in_rst) begin + tx_frame_r <= 'b0; + tx_frame_f <= 'b0; + tx_data_r <= 'b0; + tx_data_f <= 'b0; + end + else begin + case (tx_control_cnt) + 2'd0: begin + tx_frame_r <= 1'b1; + tx_frame_f <= 1'b1; + tx_data_r <= tx_fifo_ch1_i[11: 6]; + tx_data_f <= tx_fifo_ch1_q[11: 6]; + end + 2'd1: begin + tx_frame_r <= 1'b1; + tx_frame_f <= 1'b1; + tx_data_r <= tx_fifo_ch1_i[5:0]; + tx_data_f <= tx_fifo_ch1_q[5:0]; + end + 2'd2: begin + tx_frame_r <= 1'b0; + tx_frame_f <= 1'b0; + tx_data_r <= tx_fifo_ch2_i[11:6]; + tx_data_f <= tx_fifo_ch2_q[11:6]; + end + 2'd3: begin + tx_frame_r <= 1'b0; + tx_frame_f <= 1'b0; + tx_data_r <= tx_fifo_ch2_i[5:0]; + tx_data_f <= tx_fifo_ch2_q[5:0]; + end + default: begin + tx_frame_r <= 'b0; + tx_frame_f <= 'b0; + tx_data_r <= 'b0; + tx_data_f <= 'b0; + end + endcase + end +end + +// output clock to port +wire clk_out; +assign clk_out = clk_4x_in; + +OBUFDS u_obufds_clk_out +( + .I (clk_out ), + .O (clk_out_p ), + .OB (clk_out_n ) +); + +// output tx frame to port +ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT (1'b0 ), + .SRTYPE ("ASYNC" ) +) u_tx_frame_oddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_4x_in ), + .D1 (tx_frame_r ), + .D2 (tx_frame_f ), + .Q (tx_frame ) +); + +OBUFDS u_obufds_tx_frame +( + .I (tx_frame ), + .O (tx_frame_p ), + .OB (tx_frame_n ) +); + +// output tx data to port +wire [5:0] tx_data; + +generate +for (m=0; m<6; m=m+1) begin: tx_data_oddr + +ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT (1'b0 ), + .SRTYPE ("ASYNC" ) +) u_tx_data_oddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_4x_in ), + .D1 (tx_data_r[m] ), + .D2 (tx_data_f[m] ), + .Q (tx_data[m] ) +); + +OBUFDS u_obufds_tx_data +( + .I (tx_data[m] ), + .O (tx_data_p[m] ), + .OB (tx_data_n[m] ) +); + +end +endgenerate + +endmodule diff --git a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.xpr b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.xpr new file mode 100644 index 00000000..ab7f5d95 --- /dev/null +++ b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.xpr @@ -0,0 +1,303 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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100644 index 00000000..64167ba1 --- /dev/null +++ b/modules/xc7z100ffg900-2/tx_qpsk/tx_qpsk.srcs/sources_1/ip/coe/hrc_64_12_025.coe @@ -0,0 +1,771 @@ +RADIX = 10; +COEFDATA = +-47, +-30, +-13, +4, +21, +38, +56, +73, +89, +106, +122, +138, +153, +168, +182, +196, +209, +221, +232, +243, +252, +261, +268, +275, +281, +285, +289, +291, +292, +292, +291, +288, +285, +280, +274, +267, +259, +249, +239, +228, +215, +202, +187, +172, +156, +139, +122, +104, +85, +66, +46, +26, +5, +-15, +-36, +-56, +-77, +-98, +-118, +-138, +-158, +-177, +-195, +-213, +-231, +-247, +-263, +-277, +-291, +-303, +-314, +-325, +-333, +-341, +-347, +-351, +-354, +-356, +-356, +-354, +-351, +-346, +-340, +-332, +-322, +-311, +-298, +-284, +-268, +-250, +-231, +-211, +-189, +-166, +-142, +-117, +-90, +-63, +-35, +-6, +24, +54, +85, +116, +147, +179, +210, +242, +273, +304, +334, +363, +392, +420, +447, +473, +497, +520, +542, +562, +580, +596, +611, +623, +633, +641, +647, +650, +650, +649, +644, +637, +627, +615, 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\____|\__,_|\___/ +// +// Create Date: 2022/03/23 20:17:56 +// Last Modified Date: 2023/03/10 15:41 +// Design Name: +// Module Name: tx_qpsk +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// 20230228-1541 - 修改不扫频、无基带频偏时 [baseband_i/q] 的数据输出，原来从 +// 乘法器引出，会导致频率为 0 时输出数据错误，现在直接从基带数据引出。 +// 20230310-1542 - 增加输入参数，发送数据更改为直接由参数输入，发送方波改为 8 +// 倍过采样，发送双音信号中 1MHz 信号的频率控制字可以根据参数中的时钟频率计 +// 算得出。 +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tx_qpsk +#( + parameter DATA_WIDTH = 12, // need to be <= 16 + parameter BIT_DATA = 128'b00000011000010100011110010001011001110101001111101000011100010010011011010110111101100011010010111011100110010101011111110000001, // inverse pseudorandom bit sequence, [0,flip(PRSB7)] + parameter BIT_DATA_LEN = 128, + parameter SQUARE_INTERP = 8, + parameter CLK_FREQ = 245760000 // in Hertz +) +( + input clk , + input rst , + output [DATA_WIDTH-1:0] tx_data_i , + output [DATA_WIDTH-1:0] tx_data_q , + // debug ports + input [ 1:0] waveform_sel , + input sweep_on , + input [31:0] freq_set , + input [ 1:0] iq_sel , + input [ 3:0] bb_rshift +); + +localparam RCOS_INTERP = 64; +localparam INTERP = (RCOS_INTERP > SQUARE_INTERP) ? RCOS_INTERP : SQUARE_INTERP; +localparam FREQ_WORD_1M = 64'd2**64'd32*64'd1000000/CLK_FREQ; + +//////////////////////////////////////////////////////////////////////////////// +///////////////////////////////// Data Counter ///////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// symbol & interpolation counter +reg [$clog2(INTERP*BIT_DATA_LEN)-1 : 0] cnt = 'b0; + +always @(posedge clk) begin + if (rst) begin + cnt <= 'b0; + end + else begin + cnt <= (cnt == INTERP*BIT_DATA_LEN - 1) ? 'b0 : cnt + 16'b1; + end +end + +//////////////////////////////////////////////////////////////////////////////// +////////////////////// Root-Rasied Cosine Shaping Filter /////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// address +reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_i = 'b0; +reg [$clog2(BIT_DATA_LEN)-1 : 0] hrc_data_addr_q = 'b1; + +always @(posedge clk) begin + if (rst) begin + hrc_data_addr_i <= 'b0; + hrc_data_addr_q <= 'b1; + end + else begin + hrc_data_addr_i <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b0}; + hrc_data_addr_q <= {cnt[$clog2(RCOS_INTERP) +: ($clog2(BIT_DATA_LEN)-1)],1'b1}; + end +end + +// bit data +reg hrc_data_i = 'b0; +reg hrc_data_q = 'b0; + +always @(posedge clk) begin + if (rst) begin + hrc_data_i <= 'b0; + hrc_data_q <= 'b0; + end + else begin + hrc_data_i <= BIT_DATA[hrc_data_addr_i]; + hrc_data_q <= BIT_DATA[hrc_data_addr_q]; + end +end + +// polarization +wire [ 7:0] hrc_data_polar_i; +wire [ 7:0] hrc_data_polar_q; + +assign hrc_data_polar_i = {{7{hrc_data_i}},1'b1}; +assign hrc_data_polar_q = {{7{hrc_data_q}},1'b1}; + +// root raised cosine shaping-filter +wire [23:0] hrc_wave_i; +wire [23:0] hrc_wave_q; + +hrc_64_12_025 u_hrc_i ( + .aclk (clk ), // input wire aclk + .s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid + .s_axis_data_tready ( ), // output wire s_axis_data_tready + .s_axis_data_tdata (hrc_data_polar_i ), // input wire [7 : 0] s_axis_data_tdata + .m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid + .m_axis_data_tdata (hrc_wave_i ) // output wire [23 : 0] m_axis_data_tdata +); + +hrc_64_12_025 u_hrc_q ( + .aclk (clk ), // input wire aclk + .s_axis_data_tvalid (~rst ), // input wire s_axis_data_tvalid + .s_axis_data_tready ( ), // output wire s_axis_data_tready + .s_axis_data_tdata (hrc_data_polar_q ), // input wire [7 : 0] s_axis_data_tdata + .m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid + .m_axis_data_tdata (hrc_wave_q ) // output wire [23 : 0] m_axis_data_tdata +); + + +//////////////////////////////////////////////////////////////////////////////// +//////////////////////////// Square Shaping Filter ///////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// address +reg [$clog2(BIT_DATA_LEN)-1 : 0] hsq_data_addr = 'b0; + +always @(posedge clk) begin + if (rst) begin + hsq_data_addr <= 'b0; + end + else + hsq_data_addr <= {cnt[$clog2(SQUARE_INTERP) +: $clog2(BIT_DATA_LEN)]}; +end + +// bit data +reg hsq_data = 'b0; + +always @(posedge clk) begin + if (rst) begin + hsq_data <= 'b0; + end + else begin + hsq_data <= BIT_DATA[hsq_data_addr]; + end +end + +// square shaping-filter +reg [17:0] hsq_wave_i ='b0; +reg [17:0] hsq_wave_q ='b0; + +always @(posedge clk) begin + if (rst) begin + hsq_wave_i <= 'b0; + hsq_wave_q <= 'b0; + end + else begin + hsq_wave_i <= hsq_data ? 18'b01_1111_1111_1111_1111 : 18'b10_0000_0000_0000_0001; + hsq_wave_q <= hsq_data ? 18'b10_0000_0000_0000_0001 : 18'b01_1111_1111_1111_1111; + end +end + + +//////////////////////////////////////////////////////////////////////////////// +/////////////////////////////// Two Tone Siganl //////////////////////////////// +//////////////////////////////////////////////////////////////////////////////// +// cosine wave with freq of 1 MHz +wire signed [7:0] cos_1m; +wire signed [7:0] sin_1m; + +dds_32b_8b u_dds_1m +( + .aclk (clk ), // input wire aclk + .s_axis_config_tvalid (1'b1 ), // input wire s_axis_config_tvalid + .s_axis_config_tdata (FREQ_WORD_1M[31:0] ), // input wire [31 : 0] s_axis_config_tdata + .m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid + .m_axis_data_tdata ({sin_1m,cos_1m} ) // output wire [15 : 0] m_axis_data_tdata +); + +// two-tone signal +reg signed [16:0] two_tone_wave_i = 'b0; +reg signed [16:0] two_tone_wave_q = 'b0; + +always @(posedge clk) begin + if (rst) begin + two_tone_wave_i <= 'b0; + two_tone_wave_q <= 'b0; + end + else begin + two_tone_wave_i <= 17'b0_0111_1111_1111_1111 + {cos_1m[7],cos_1m,8'd0}; + two_tone_wave_q <= 17'b0 + {sin_1m[7],sin_1m,8'd0}; + end +end + + +//////////////////////////////////////////////////////////////////////////////// +///////////////////// Waveform Selection & Hopping Control ///////////////////// +//////////////////////////////////////////////////////////////////////////////// +// baseband signal select +reg [17:0] baseband_sel_i = 'b0; +reg [17:0] baseband_sel_q = 'b0; + +always @(posedge clk) begin + if (rst) begin + baseband_sel_i <= 'b0; + baseband_sel_q <= 'b0; + end + else begin + case (waveform_sel[1:0]) + 2'd0: begin + baseband_sel_i <= {hrc_wave_i[16:0],1'b0}; + baseband_sel_q <= {hrc_wave_q[16:0],1'b0}; + end + 2'd1: begin + baseband_sel_i <= hsq_wave_i[17:0]; + baseband_sel_q <= hsq_wave_q[17:0]; + end + 2'd2: begin + baseband_sel_i <= 18'b01_1111_1111_1111_1111; + baseband_sel_q <= 18'b0; + end + 2'd3: begin + baseband_sel_i <= {two_tone_wave_i[16:0],1'b0}; + baseband_sel_q <= {two_tone_wave_q[16:0],1'b0}; + end + default: begin + baseband_sel_i <= {hrc_wave_i[16:0],1'b0}; + baseband_sel_q <= {hrc_wave_q[16:0],1'b0}; + end + endcase + end +end + +// hopping control, 3750hop/s +reg [23:0] sweep_rom_addr = 'b0; +wire [31:0] freq_sweep; + +always @(posedge clk) begin + if (rst) begin + sweep_rom_addr <= 'b0; + end + else if (sweep_on) begin + sweep_rom_addr <= sweep_rom_addr + 24'b1; + end + else begin + sweep_rom_addr <= 'b0; + end +end + +hop_rom u_sweep_rom +( + .clka (clk ), // input wire clka + .addra (sweep_rom_addr[23:16] ), // input wire [7 : 0] addra + .douta (freq_sweep ) // output wire [31 : 0] douta +); + +// choose the actual frequency word +reg [31:0] freq_word = 'b0; + +always @(posedge clk) begin + if (rst) begin + freq_word <= 'b0; + end + else if (sweep_on) begin + // frequency sweep + freq_word <= freq_sweep; + end + else begin + // normal operation + freq_word <= freq_set; + end +end + +// baseband frequency shift carrier generation +wire [ 7:0] cos_dds; +wire [ 7:0] sin_dds; +reg [ 7:0] cos = 'b0; +reg [ 7:0] sin = 'b0; + +dds_32b_8b u_dds_bb_shift ( + .aclk (clk ), // input wire aclk + .s_axis_config_tvalid (~rst ), // input wire s_axis_config_tvalid + .s_axis_config_tdata (freq_word ), // input wire [31 : 0] s_axis_config_tdata + .m_axis_data_tvalid ( ), // output wire m_axis_data_tvalid + .m_axis_data_tdata ({sin_dds,cos_dds}) // output wire [31 : 0] m_axis_data_tdata +); + +always @(posedge clk) begin + if (rst) begin + cos <= 'b0; + sin <= 'b0; + end + else if (freq_word == 'b0) begin + // to make sure the carriers stay at the right position when freq = 0 + cos <= 8'b0111_1111; + sin <= 8'b0111_1111; + end + else begin + cos <= cos_dds; + sin <= sin_dds; + end +end + +// baseband frequency shift modulation +wire [47:0] mod_cmpy_a; +wire [15:0] mod_cmpy_b; +wire [63:0] mod_cmpy_out; + +wire [26:0] baseband_mult_i; +wire [26:0] baseband_mult_q; + +assign mod_cmpy_a = {6'b0,baseband_sel_q,6'b0,baseband_sel_i}; +assign mod_cmpy_b = {-sin,cos}; + +assign baseband_mult_i = mod_cmpy_out[58:32]; +assign baseband_mult_q = mod_cmpy_out[26: 0]; + +cmpy_18x8 u_cmpy_18x8 +( + .aclk (clk ), // input wire aclk + .s_axis_a_tvalid (1'b1 ), // input wire s_axis_a_tvalid + .s_axis_a_tdata (mod_cmpy_a ), // input wire [47 : 0] s_axis_a_tdata + .s_axis_b_tvalid (1'b1 ), // input wire s_axis_b_tvalid + .s_axis_b_tdata (mod_cmpy_b ), // input wire [15 : 0] s_axis_b_tdata + .m_axis_dout_tvalid ( ), // output wire m_axis_dout_tvalid + .m_axis_dout_tdata (mod_cmpy_out ) // output wire [63 : 0] m_axis_dout_tdata +); + +// truncate to 16-bit +reg signed [15:0] baseband_i = 'b0; +reg signed [15:0] baseband_q = 'b0; + +always @(posedge clk) begin + if (rst) begin + baseband_i <= 'b0; + baseband_q <= 'b0; + end + else begin + case (waveform_sel[1:0]) + 2'd0: begin + // scale rasied-cosine-shaped bpsk signal by 1.125 or 1.625 + baseband_i <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_i[17 -: 16] + {{3{baseband_sel_i[17]}},baseband_sel_i[17 -: 13]}) : (baseband_mult_i[25:10] + {baseband_mult_i[25],baseband_mult_i[25:11]} + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]}); + baseband_q <= (sweep_on == 0 && freq_set == 0) ? (baseband_sel_q[17 -: 16] + {{3{baseband_sel_q[17]}},baseband_sel_q[17 -: 13]}) : (baseband_mult_q[25:10] + {baseband_mult_q[25],baseband_mult_q[25:11]} + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]}); + end + 2'd1: begin + baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : (baseband_mult_i[25:10] + {{2{baseband_mult_i[25]}},baseband_mult_i[25:12]}); + baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : (baseband_mult_q[25:10] + {{2{baseband_mult_q[25]}},baseband_mult_q[25:12]}); + end + 2'd2: begin + baseband_i <= baseband_mult_i[24:9]; + baseband_q <= baseband_mult_q[24:9]; + end + 2'd3: begin + baseband_i <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_i[17 -: 16] : baseband_mult_i[24:9]; + baseband_q <= (sweep_on == 0 && freq_set == 0) ? baseband_sel_q[17 -: 16] : baseband_mult_q[24:9]; + end + default: begin + // scale rasied-cosine-shaped bpsk signal by 1.125 + baseband_i <= baseband_mult_i[25:10] + {{3{baseband_mult_i[25]}},baseband_mult_i[25:13]}; + baseband_q <= baseband_mult_q[25:10] + {{3{baseband_mult_q[25]}},baseband_mult_q[25:13]}; + end + endcase + end +end + +// iq selection & baseband right shift +reg signed [15:0] baseband_data_i = 'b0; +reg signed [15:0] baseband_data_q = 'b0; + +always @(posedge clk) begin + if (rst) begin + baseband_data_i <= 'b0; + baseband_data_q <= 'b0; + end + else begin + // inphase selection + if (iq_sel[1]) begin + baseband_data_i <= baseband_i >>> bb_rshift; + end + else begin + baseband_data_i <= 'b0; + end + // quadrature selection + if (iq_sel[0]) begin + baseband_data_q <= baseband_q >>> bb_rshift; + end + else begin + baseband_data_q <= 'b0; + end + end +end + +// output data to ports +assign tx_data_i = baseband_data_i[15 -: DATA_WIDTH]; +assign tx_data_q = baseband_data_q[15 -: DATA_WIDTH]; + +endmodule + + +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2020/12/08 12:43:46 +// Design Name: +// Module Name: tb_tx_qpsk +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +// module tb_tx_qpsk; + +// reg clk = 1'b0 ; +// reg rst = 1'b1 ; +// reg tx_on = 1'b1 ; +// reg [31:0] freq_set ; +// reg [ 1:0] waveform_sel = 2'b00; +// reg [ 1:0] iq_sel = 2'b11 ; +// wire [11:0] tx_data_i ; +// wire [11:0] tx_data_q ; +// reg [ 3:0] bb_rshift = 5'b0 ; + +// tx_qpsk u_tx_qpsk +// ( +// .clk (clk ), +// .rst (rst ), +// .tx_data_i (tx_data_i ), +// .tx_data_q (tx_data_q ), +// .waveform_sel (waveform_sel ), +// .sweep_on (1'b0 ), +// // .freq_set (32'd447392426 ), +// .freq_set (32'd0 ), +// .iq_sel (iq_sel ), +// .bb_rshift (bb_rshift ) +// ); + +// initial begin +// #102 +// rst = 1'b0; +// // freq_set = 32'd873813333; +// // waveform_sel = 2'b00; +// // bb_rshift = 5'd0; +// // #5000 +// // bb_rshift = 5'd1; +// // #5000 +// // bb_rshift = 5'd2; +// // #5000 +// // bb_rshift = 5'd3; +// // #5000 +// // bb_rshift = 5'd4; +// // #5000 +// // bb_rshift = 5'd5; +// // #5000 +// // bb_rshift = 5'd6; +// // #5000 +// // bb_rshift = 5'd7; +// // #5000 +// // bb_rshift = 5'd8; +// // #5000 +// // bb_rshift = 5'd9; +// // #5000 +// // bb_rshift = 5'd14; +// // #5000 +// // bb_rshift = 5'd15; +// // #5000 +// // bb_rshift = 5'd16; +// // freq_set = 32'd0; +// // func_sel = 3'b010; +// // #7777 +// // freq_set = 32'd536870912; +// // func_sel = 3'b100; +// // #7777 +// // freq_set = 32'd0; +// // func_sel = 3'b100; +// // #7777 +// // freq_set = 32'd536870912; +// // func_sel = 3'b010; +// // #7777 +// // freq_set = 32'd0; +// // func_sel = 3'b010; +// // freq_set = 32'd536870912; +// // iq_sel = 2'b00; +// // #7777 +// // freq_set = 32'd536870912; +// // iq_sel = 2'b01; +// // #7777 +// // freq_set = 32'd536870912; +// // iq_sel = 2'b10; +// // #7777 +// // freq_set = 32'd536870912; +// // iq_sel = 2'b11; +// end + +// always #5 clk = ~clk; + +// // integer i; +// // integer w_file; + +// // initial begin +// // w_file = $fopen("D:\\qpsk_josh.txt","w"); +// // for (i = 0; i <= 35000; i = i + 1) begin +// // wait(clk); +// // #10; +// // $fdisplay(w_file,"%d %d",$signed(tx_data_i), +// // $signed(tx_data_q)); +// // if (i == 35000) begin +// // $fclose(w_file); +// // $stop; +// // end +// // end +// // end + +// endmodule diff --git a/modules/xc7z100ffg900-2/tx_qpsk/tx_qpsk.xpr b/modules/xc7z100ffg900-2/tx_qpsk/tx_qpsk.xpr new file mode 100644 index 00000000..cff23427 --- /dev/null +++ b/modules/xc7z100ffg900-2/tx_qpsk/tx_qpsk.xpr @@ -0,0 +1,407 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + +