diff --git a/adi_library/ad463x_data_capture/ad463x_data_capture.v b/adi_library/ad463x_data_capture/ad463x_data_capture.v
index 066c3355..83e4d1bc 100644
--- a/adi_library/ad463x_data_capture/ad463x_data_capture.v
+++ b/adi_library/ad463x_data_capture/ad463x_data_capture.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/ad463x_data_capture/ad463x_data_capture.xpr b/adi_library/ad463x_data_capture/ad463x_data_capture.xpr
index 3dbf165a..05979d07 100644
--- a/adi_library/ad463x_data_capture/ad463x_data_capture.xpr
+++ b/adi_library/ad463x_data_capture/ad463x_data_capture.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/ad463x_data_capture/ad463x_data_capture.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/ad463x_data_capture/ad463x_data_capture.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="f42ccf7b5230472aa58a5db11951bd4e"/>
+    <Option Name="Id" Val="d23ebce51bfc492dbfe31cce812fa48e"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -154,21 +153,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -181,7 +180,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/ad463x_data_capture/component.xml b/adi_library/ad463x_data_capture/component.xml
index 3a2dd033..60918047 100644
--- a/adi_library/ad463x_data_capture/component.xml
+++ b/adi_library/ad463x_data_capture/component.xml
@@ -75,7 +75,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>8bb59c43</spirit:value>
+            <spirit:value>345b66ae</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -91,7 +91,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>8bb59c43</spirit:value>
+            <spirit:value>345b66ae</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -235,7 +235,7 @@
       <spirit:file>
         <spirit:name>ad463x_data_capture.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_8bb59c43</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_345b66ae</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -315,11 +315,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:37:32Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T02:52:57Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="6613ab63"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="e1a8d123"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="b1e61ed1"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="d9a2fdd9"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="4efac9f5"/>
diff --git a/adi_library/axi_ad3552r/axi_ad3552r.v b/adi_library/axi_ad3552r/axi_ad3552r.v
index 2f4c4e20..0685c511 100755
--- a/adi_library/axi_ad3552r/axi_ad3552r.v
+++ b/adi_library/axi_ad3552r/axi_ad3552r.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad3552r/axi_ad3552r.xpr b/adi_library/axi_ad3552r/axi_ad3552r.xpr
index e0150b1c..b6f2d24f 100644
--- a/adi_library/axi_ad3552r/axi_ad3552r.xpr
+++ b/adi_library/axi_ad3552r/axi_ad3552r.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ad3552r/axi_ad3552r.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_ad3552r/axi_ad3552r.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="8678bf6b3e38452fbffeffe36cad4bce"/>
+    <Option Name="Id" Val="1536288f7d6543de8356baa7b24c483c"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -312,21 +311,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -339,7 +338,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_ad3552r/axi_ad3552r_channel.v b/adi_library/axi_ad3552r/axi_ad3552r_channel.v
index 0a73e9d0..542806f8 100755
--- a/adi_library/axi_ad3552r/axi_ad3552r_channel.v
+++ b/adi_library/axi_ad3552r/axi_ad3552r_channel.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad3552r/axi_ad3552r_core.v b/adi_library/axi_ad3552r/axi_ad3552r_core.v
index a0fadfdd..583f79b1 100755
--- a/adi_library/axi_ad3552r/axi_ad3552r_core.v
+++ b/adi_library/axi_ad3552r/axi_ad3552r_core.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad3552r/axi_ad3552r_if.v b/adi_library/axi_ad3552r/axi_ad3552r_if.v
index 0b67b64c..cf4fa618 100755
--- a/adi_library/axi_ad3552r/axi_ad3552r_if.v
+++ b/adi_library/axi_ad3552r/axi_ad3552r_if.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad3552r/axi_ad3552r_if_tb.v b/adi_library/axi_ad3552r/axi_ad3552r_if_tb.v
index 16521acc..bd03178e 100755
--- a/adi_library/axi_ad3552r/axi_ad3552r_if_tb.v
+++ b/adi_library/axi_ad3552r/axi_ad3552r_if_tb.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad3552r/component.xml b/adi_library/axi_ad3552r/component.xml
index 7e084116..9393569a 100644
--- a/adi_library/axi_ad3552r/component.xml
+++ b/adi_library/axi_ad3552r/component.xml
@@ -257,7 +257,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>96287bb0</spirit:value>
+            <spirit:value>b9a68d5c</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -273,7 +273,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>abc33695</spirit:value>
+            <spirit:value>a36d9abe</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -971,30 +971,6 @@
       <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
       <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
     </spirit:choice>
-    <spirit:choice>
-      <spirit:name>choice_pairs_00ecfe9a</spirit:name>
-      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
-      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
-      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
-      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
-      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
-      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
-      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
-      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
-      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
-      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
-      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
-      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
-      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
-      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
-      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
-      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
-      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
-      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
-      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
-      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
-      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
-    </spirit:choice>
     <spirit:choice>
       <spirit:name>choice_pairs_19f99f31</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
@@ -1020,7 +996,32 @@
       <spirit:enumeration spirit:text="versal">4</spirit:enumeration>
     </spirit:choice>
     <spirit:choice>
-      <spirit:name>choice_pairs_fc01a186</spirit:name>
+      <spirit:name>choice_pairs_a6e6e044</spirit:name>
+      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
+      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
+      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
+      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
+      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
+      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
+      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
+      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
+      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
+      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
+      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
+      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
+      <spirit:enumeration spirit:text="ls">21</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a897e79d</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
       <spirit:enumeration spirit:text="artix">1</spirit:enumeration>
       <spirit:enumeration spirit:text="kintex">2</spirit:enumeration>
@@ -1028,6 +1029,7 @@
       <spirit:enumeration spirit:text="zynq">4</spirit:enumeration>
       <spirit:enumeration spirit:text="versalprime">5</spirit:enumeration>
       <spirit:enumeration spirit:text="versalaicore">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="versalpremium">7</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
   <spirit:fileSets>
@@ -1120,7 +1122,7 @@
       <spirit:file>
         <spirit:name>axi_ad3552r.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_6bd0b0d1</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_ab80c037</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1230,7 +1232,7 @@
     <spirit:parameter>
       <spirit:name>FPGA_FAMILY</spirit:name>
       <spirit:displayName>Fpga Family</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_fc01a186">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_a897e79d">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>SPEED_GRADE</spirit:name>
@@ -1240,7 +1242,7 @@
     <spirit:parameter>
       <spirit:name>DEV_PACKAGE</spirit:name>
       <spirit:displayName>Dev Package</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_00ecfe9a">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_a6e6e044">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>DDS_DISABLE</spirit:name>
@@ -1305,11 +1307,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_ad3552r</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:37:52Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T02:53:18Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="b2efe47f"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="90fda69c"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="81a2ebd8"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="bafdc4f5"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="487fc7db"/>
diff --git a/adi_library/axi_ad4858/axi_ad4858.v b/adi_library/axi_ad4858/axi_ad4858.v
index 75e56834..baee2bcd 100644
--- a/adi_library/axi_ad4858/axi_ad4858.v
+++ b/adi_library/axi_ad4858/axi_ad4858.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad4858/axi_ad4858.xpr b/adi_library/axi_ad4858/axi_ad4858.xpr
index 794e44c7..cc4a5fb7 100644
--- a/adi_library/axi_ad4858/axi_ad4858.xpr
+++ b/adi_library/axi_ad4858/axi_ad4858.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ad4858/axi_ad4858.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_ad4858/axi_ad4858.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="7acdf62ce3f947118656336a8f9c9a61"/>
+    <Option Name="Id" Val="e8b8ff13c1f44e3eac548cfacd11aed1"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -307,21 +306,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -334,7 +333,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_ad4858/axi_ad4858_channel.v b/adi_library/axi_ad4858/axi_ad4858_channel.v
index 9904f0cd..5cfa7c14 100644
--- a/adi_library/axi_ad4858/axi_ad4858_channel.v
+++ b/adi_library/axi_ad4858/axi_ad4858_channel.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad4858/axi_ad4858_cmos.v b/adi_library/axi_ad4858/axi_ad4858_cmos.v
index 91d01bd6..935ff00d 100644
--- a/adi_library/axi_ad4858/axi_ad4858_cmos.v
+++ b/adi_library/axi_ad4858/axi_ad4858_cmos.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad4858/axi_ad4858_crc.v b/adi_library/axi_ad4858/axi_ad4858_crc.v
index 4628a776..19dc27be 100644
--- a/adi_library/axi_ad4858/axi_ad4858_crc.v
+++ b/adi_library/axi_ad4858/axi_ad4858_crc.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad4858/axi_ad4858_lvds.v b/adi_library/axi_ad4858/axi_ad4858_lvds.v
index de8668ac..2426c5c0 100644
--- a/adi_library/axi_ad4858/axi_ad4858_lvds.v
+++ b/adi_library/axi_ad4858/axi_ad4858_lvds.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad4858/component.xml b/adi_library/axi_ad4858/component.xml
index d1dd0548..8569eeca 100644
--- a/adi_library/axi_ad4858/component.xml
+++ b/adi_library/axi_ad4858/component.xml
@@ -241,7 +241,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>bc5d0f91</spirit:value>
+            <spirit:value>7f2fbafb</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -257,7 +257,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>bae8e501</spirit:value>
+            <spirit:value>ba51c525</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1606,7 +1606,7 @@
       <spirit:file>
         <spirit:name>axi_ad4858.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_ec735744</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_86ad6d10</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1852,11 +1852,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_ad4858</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:38:12Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T02:53:40Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="bfd99ec0"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="6bc8624e"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="7a5cc8f5"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="f69ae847"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="ba19687a"/>
diff --git a/adi_library/axi_ad5766/Makefile b/adi_library/axi_ad5766/Makefile
index e8003a62..c38a5167 100644
--- a/adi_library/axi_ad5766/Makefile
+++ b/adi_library/axi_ad5766/Makefile
@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################
@@ -25,4 +25,6 @@ XILINX_DEPS += ../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
 
 XILINX_LIB_DEPS += util_cdc
 
+XILINX_INTERFACE_DEPS += spi_engine/interfaces
+
 include ../scripts/library.mk
diff --git a/adi_library/axi_ad5766/axi_ad5766.v b/adi_library/axi_ad5766/axi_ad5766.v
index 172eabee..17bd390d 100644
--- a/adi_library/axi_ad5766/axi_ad5766.v
+++ b/adi_library/axi_ad5766/axi_ad5766.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad5766/axi_ad5766.xpr b/adi_library/axi_ad5766/axi_ad5766.xpr
index bac32314..52ec9f91 100644
--- a/adi_library/axi_ad5766/axi_ad5766.xpr
+++ b/adi_library/axi_ad5766/axi_ad5766.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ad5766/axi_ad5766.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_ad5766/axi_ad5766.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="099ae3f8fc184560a374a4d0cb4961a3"/>
+    <Option Name="Id" Val="48f3f85534574085ad205fa349437dc9"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -217,21 +216,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -244,7 +243,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_ad5766/component.xml b/adi_library/axi_ad5766/component.xml
index e377d40d..fe2cf36e 100644
--- a/adi_library/axi_ad5766/component.xml
+++ b/adi_library/axi_ad5766/component.xml
@@ -492,7 +492,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>effc7a98</spirit:value>
+            <spirit:value>1489dbfa</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -511,7 +511,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>effc7a98</spirit:value>
+            <spirit:value>1489dbfa</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1315,30 +1315,6 @@
       <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
       <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
     </spirit:choice>
-    <spirit:choice>
-      <spirit:name>choice_pairs_00ecfe9a</spirit:name>
-      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
-      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
-      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
-      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
-      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
-      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
-      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
-      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
-      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
-      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
-      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
-      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
-      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
-      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
-      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
-      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
-      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
-      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
-      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
-      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
-      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
-    </spirit:choice>
     <spirit:choice>
       <spirit:name>choice_pairs_19f99f31</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
@@ -1364,7 +1340,32 @@
       <spirit:enumeration spirit:text="versal">4</spirit:enumeration>
     </spirit:choice>
     <spirit:choice>
-      <spirit:name>choice_pairs_fc01a186</spirit:name>
+      <spirit:name>choice_pairs_a6e6e044</spirit:name>
+      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
+      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
+      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
+      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
+      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
+      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
+      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
+      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
+      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
+      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
+      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
+      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
+      <spirit:enumeration spirit:text="ls">21</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a897e79d</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
       <spirit:enumeration spirit:text="artix">1</spirit:enumeration>
       <spirit:enumeration spirit:text="kintex">2</spirit:enumeration>
@@ -1372,6 +1373,7 @@
       <spirit:enumeration spirit:text="zynq">4</spirit:enumeration>
       <spirit:enumeration spirit:text="versalprime">5</spirit:enumeration>
       <spirit:enumeration spirit:text="versalaicore">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="versalpremium">7</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
   <spirit:fileSets>
@@ -1412,7 +1414,7 @@
       <spirit:file>
         <spirit:name>axi_ad5766.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_285d8cd9</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_5cb4b6c6</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1517,7 +1519,7 @@
     <spirit:parameter>
       <spirit:name>FPGA_FAMILY</spirit:name>
       <spirit:displayName>Fpga Family</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_fc01a186">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_a897e79d">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>SPEED_GRADE</spirit:name>
@@ -1527,7 +1529,7 @@
     <spirit:parameter>
       <spirit:name>DEV_PACKAGE</spirit:name>
       <spirit:displayName>Dev Package</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_00ecfe9a">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_a6e6e044">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>ASYNC_SPI_CLK</spirit:name>
@@ -1587,11 +1589,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:38:31Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T02:54:07Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="37b737cf"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="9c590714"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="282d6a1d"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="446dad02"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="89a6278e"/>
diff --git a/adi_library/axi_ad5766/up_ad5766_sequencer.v b/adi_library/axi_ad5766/up_ad5766_sequencer.v
index a9ccb7e0..55f1dcc9 100644
--- a/adi_library/axi_ad5766/up_ad5766_sequencer.v
+++ b/adi_library/axi_ad5766/up_ad5766_sequencer.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad7606x/axi_ad7606x.v b/adi_library/axi_ad7606x/axi_ad7606x.v
index d458ce9a..b1c3460f 100644
--- a/adi_library/axi_ad7606x/axi_ad7606x.v
+++ b/adi_library/axi_ad7606x/axi_ad7606x.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -37,142 +37,142 @@
 
 module axi_ad7606x #(
 
-  parameter       ID = 0,
-  parameter       DEV_CONFIG = 0,
-  parameter       ADC_CH_DW = 16,
-  parameter       ADC_N_BITS = 16,
-  parameter       EXTERNAL_CLK = 0
+  parameter ID = 0,
+  parameter DEV_CONFIG = 0,
+  parameter ADC_TO_DMA_N_BITS = 16,
+  parameter ADC_N_BITS = 16,
+  parameter EXTERNAL_CLK = 0
 ) (
 
   // physical data interface
 
-  output                  rx_cs_n,
-  output      [15:0]      rx_db_o,
-  input       [15:0]      rx_db_i,
-  output                  rx_db_t,
-  output                  rx_rd_n,
-  output                  rx_wr_n,
-  input                   external_clk,
+  output        rx_cs_n,
+  output [15:0] rx_db_o,
+  input  [15:0] rx_db_i,
+  output        rx_db_t,
+  output        rx_rd_n,
+  output        rx_wr_n,
+  input         external_clk,
 
   // physical control interface
 
-  input                   rx_busy,
-  input                   first_data,
+  input         rx_busy,
+  input         first_data,
 
   // AXI Slave Memory Map
 
-  input                   s_axi_aclk,
-  input                   s_axi_aresetn,
-  input                   s_axi_awvalid,
-  input       [15:0]      s_axi_awaddr,
-  input       [ 2:0]      s_axi_awprot,
-  output                  s_axi_awready,
-  input                   s_axi_wvalid,
-  input       [31:0]      s_axi_wdata,
-  input       [ 3:0]      s_axi_wstrb,
-  output                  s_axi_wready,
-  output                  s_axi_bvalid,
-  output      [ 1:0]      s_axi_bresp,
-  input                   s_axi_bready,
-  input                   s_axi_arvalid,
-  input       [15:0]      s_axi_araddr,
-  input       [ 2:0]      s_axi_arprot,
-  output                  s_axi_arready,
-  output                  s_axi_rvalid,
-  output      [ 1:0]      s_axi_rresp,
-  output      [31:0]      s_axi_rdata,
-  input                   s_axi_rready,
+  input         s_axi_aclk,
+  input         s_axi_aresetn,
+  input         s_axi_awvalid,
+  input  [15:0] s_axi_awaddr,
+  input  [ 2:0] s_axi_awprot,
+  output        s_axi_awready,
+  input         s_axi_wvalid,
+  input  [31:0] s_axi_wdata,
+  input  [ 3:0] s_axi_wstrb,
+  output        s_axi_wready,
+  output        s_axi_bvalid,
+  output [ 1:0] s_axi_bresp,
+  input         s_axi_bready,
+  input         s_axi_arvalid,
+  input  [15:0] s_axi_araddr,
+  input  [ 2:0] s_axi_arprot,
+  output        s_axi_arready,
+  output        s_axi_rvalid,
+  output [ 1:0] s_axi_rresp,
+  output [31:0] s_axi_rdata,
+  input         s_axi_rready,
 
-  input                   adc_dovf,
-  output                  adc_clk,
+  input         adc_dovf,
+  output        adc_clk,
 
-  output                  adc_valid,
-  output [ADC_CH_DW-1:0]  adc_data_0,
-  output [ADC_CH_DW-1:0]  adc_data_1,
-  output [ADC_CH_DW-1:0]  adc_data_2,
-  output [ADC_CH_DW-1:0]  adc_data_3,
-  output [ADC_CH_DW-1:0]  adc_data_4,
-  output [ADC_CH_DW-1:0]  adc_data_5,
-  output [ADC_CH_DW-1:0]  adc_data_6,
-  output [ADC_CH_DW-1:0]  adc_data_7,
-  output                  adc_enable_0,
-  output                  adc_enable_1,
-  output                  adc_enable_2,
-  output                  adc_enable_3,
-  output                  adc_enable_4,
-  output                  adc_enable_5,
-  output                  adc_enable_6,
-  output                  adc_enable_7,
-  output                  adc_reset
+  output        adc_valid,
+  output [ADC_TO_DMA_N_BITS-1:0] adc_data_0,
+  output [ADC_TO_DMA_N_BITS-1:0] adc_data_1,
+  output [ADC_TO_DMA_N_BITS-1:0] adc_data_2,
+  output [ADC_TO_DMA_N_BITS-1:0] adc_data_3,
+  output [ADC_TO_DMA_N_BITS-1:0] adc_data_4,
+  output [ADC_TO_DMA_N_BITS-1:0] adc_data_5,
+  output [ADC_TO_DMA_N_BITS-1:0] adc_data_6,
+  output [ADC_TO_DMA_N_BITS-1:0] adc_data_7,
+  output        adc_enable_0,
+  output        adc_enable_1,
+  output        adc_enable_2,
+  output        adc_enable_3,
+  output        adc_enable_4,
+  output        adc_enable_5,
+  output        adc_enable_6,
+  output        adc_enable_7,
+  output        adc_reset
 );
 
-  localparam     [31:0]             RD_RAW_CAP = 32'h2000;
-  localparam                        AD7606B = 1'b0;
-  localparam                        AD7606C_16 = 1'b1;
+  localparam [31:0] RD_RAW_CAP = 32'h2000;
+  localparam        AD7606B = 1'b0;
+  localparam        AD7606C_16 = 1'b1;
 
   // internal registers
 
-  reg                               up_wack = 1'b0;
-  reg                               up_rack = 1'b0;
-  reg     [31:0]                    up_rdata = 32'b0;
-  reg     [31:0]                    up_rdata_r;
-  reg                               up_rack_r;
-  reg                               up_wack_r;
+  reg         up_wack = 1'b0;
+  reg         up_rack = 1'b0;
+  reg  [31:0] up_rdata = 32'b0;
+  reg  [31:0] up_rdata_r;
+  reg         up_rack_r;
+  reg         up_wack_r;
 
   // internal signals
 
-  wire    [ADC_N_BITS-1:0]          adc_data_0_s;
-  wire    [ADC_N_BITS-1:0]          adc_data_1_s;
-  wire    [ADC_N_BITS-1:0]          adc_data_2_s;
-  wire    [ADC_N_BITS-1:0]          adc_data_3_s;
-  wire    [ADC_N_BITS-1:0]          adc_data_4_s;
-  wire    [ADC_N_BITS-1:0]          adc_data_5_s;
-  wire    [ADC_N_BITS-1:0]          adc_data_6_s;
-  wire    [ADC_N_BITS-1:0]          adc_data_7_s;
-  wire    [(8*ADC_N_BITS)-1:0]      adc_data_s;
-  wire    [ 7:0]                    adc_status_header[0:7];
-  wire                              adc_status;
-  wire    [15:0]                    adc_crc;
-  wire    [15:0]                    adc_crc_res;
-  wire                              adc_crc_err;
-  wire                              adc_mode_en;
-  wire    [ 7:0]                    adc_custom_control;
+  wire [ADC_N_BITS-1:0] adc_data_0_s;
+  wire [ADC_N_BITS-1:0] adc_data_1_s;
+  wire [ADC_N_BITS-1:0] adc_data_2_s;
+  wire [ADC_N_BITS-1:0] adc_data_3_s;
+  wire [ADC_N_BITS-1:0] adc_data_4_s;
+  wire [ADC_N_BITS-1:0] adc_data_5_s;
+  wire [ADC_N_BITS-1:0] adc_data_6_s;
+  wire [ADC_N_BITS-1:0] adc_data_7_s;
+  wire [(8*ADC_N_BITS)-1:0] adc_data_s;
+  wire [ 7:0]           adc_status_header[0:7];
+  wire                  adc_status;
+  wire [15:0]           adc_crc;
+  wire [15:0]           adc_crc_res;
+  wire                  adc_crc_err;
+  wire                  adc_mode_en;
+  wire [ 7:0]           adc_custom_control;
 
-  wire                              adc_dfmt_enable_s[0:7];
-  wire                              adc_dfmt_type_s[0:7];
-  wire                              adc_dfmt_se_s[0:7];
+  wire                  adc_dfmt_enable_s[0:7];
+  wire                  adc_dfmt_type_s[0:7];
+  wire                  adc_dfmt_se_s[0:7];
 
-  wire                              adc_clk_s;
-  wire    [ 7:0]                    adc_enable;
-  wire                              adc_reset_s;
+  wire                  adc_clk_s;
+  wire [ 7:0]           adc_enable;
+  wire                  adc_reset_s;
 
-  wire    [(8*ADC_CH_DW)-1:0]       dma_data;
-  wire                              dma_dvalid;
+  wire [(8*ADC_TO_DMA_N_BITS)-1:0] dma_data;
+  wire                  dma_dvalid;
 
-  wire                              up_clk;
-  wire                              up_rstn;
-  wire                              up_rreq_s;
-  wire    [13:0]                    up_raddr_s;
-  wire                              up_wreq_s;
-  wire    [13:0]                    up_waddr_s;
-  wire    [31:0]                    up_wdata_s;
-  wire    [31:0]                    up_rdata_s[0:8];
-  wire    [8:0]                     up_rack_s;
-  wire    [8:0]                     up_wack_s;
+  wire                  up_clk;
+  wire                  up_rstn;
+  wire                  up_rreq_s;
+  wire [13:0]           up_raddr_s;
+  wire                  up_wreq_s;
+  wire [13:0]           up_waddr_s;
+  wire [31:0]           up_wdata_s;
+  wire [31:0]           up_rdata_s[0:8];
+  wire [8:0]            up_rack_s;
+  wire [8:0]            up_wack_s;
 
-  wire                              up_wack_cntrl_s;
-  wire                              up_rack_cntrl_s;
-  wire    [31:0]                    up_rdata_cntrl_s;
+  wire                  up_wack_cntrl_s;
+  wire                  up_rack_cntrl_s;
+  wire [31:0]           up_rdata_cntrl_s;
 
-  wire    [31:0]                    wr_data_s;
-  wire    [15:0]                    rd_data_s;
-  wire                              rd_valid_s;
-  wire    [31:0]                    adc_config_ctrl_s;
-  wire                              adc_ctrl_status_s;
-  wire                              m_axis_ready_s;
-  wire                              m_axis_valid_s;
-  wire    [15:0]                    m_axis_data_s;
-  wire                              m_axis_xfer_req_s;
+  wire [31:0]           wr_data_s;
+  wire [15:0]           rd_data_s;
+  wire                  rd_valid_s;
+  wire [31:0]           adc_config_ctrl_s;
+  wire                  adc_ctrl_status_s;
+  wire                  m_axis_ready_s;
+  wire                  m_axis_valid_s;
+  wire [15:0]           m_axis_data_s;
+  wire                  m_axis_xfer_req_s;
 
   // defaults
 
@@ -287,13 +287,13 @@ module axi_ad7606x #(
     for (k = 0;k < 8;k = k + 1) begin
       ad_datafmt #(
         .DATA_WIDTH (ADC_N_BITS),
-        .BITS_PER_SAMPLE (ADC_CH_DW)
+        .BITS_PER_SAMPLE (ADC_TO_DMA_N_BITS)
       ) i_datafmt (
         .clk (adc_clk),
         .valid (1'b1),
         .data (adc_data_s[k*ADC_N_BITS+(ADC_N_BITS-1):k*ADC_N_BITS]),
         .valid_out (dma_dvalid),
-        .data_out (dma_data[k*ADC_CH_DW+(ADC_CH_DW-1):k*ADC_CH_DW]),
+        .data_out (dma_data[k*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):k*ADC_TO_DMA_N_BITS]),
         .dfmt_enable (adc_dfmt_enable_s[k]),
         .dfmt_type (adc_dfmt_type_s[k]),
         .dfmt_se (adc_dfmt_se_s[k]));
@@ -385,14 +385,14 @@ module axi_ad7606x #(
   endgenerate
 
   assign adc_data_s = {adc_data_0_s,adc_data_1_s,adc_data_2_s,adc_data_3_s,adc_data_4_s,adc_data_5_s,adc_data_6_s,adc_data_7_s};
-  assign adc_data_7 = dma_data[0*ADC_CH_DW+(ADC_CH_DW-1):0*ADC_CH_DW];
-  assign adc_data_6 = dma_data[1*ADC_CH_DW+(ADC_CH_DW-1):1*ADC_CH_DW];
-  assign adc_data_5 = dma_data[2*ADC_CH_DW+(ADC_CH_DW-1):2*ADC_CH_DW];
-  assign adc_data_4 = dma_data[3*ADC_CH_DW+(ADC_CH_DW-1):3*ADC_CH_DW];
-  assign adc_data_3 = dma_data[4*ADC_CH_DW+(ADC_CH_DW-1):4*ADC_CH_DW];
-  assign adc_data_2 = dma_data[5*ADC_CH_DW+(ADC_CH_DW-1):5*ADC_CH_DW];
-  assign adc_data_1 = dma_data[6*ADC_CH_DW+(ADC_CH_DW-1):6*ADC_CH_DW];
-  assign adc_data_0 = dma_data[7*ADC_CH_DW+(ADC_CH_DW-1):7*ADC_CH_DW];
+  assign adc_data_7 = dma_data[0*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):0*ADC_TO_DMA_N_BITS];
+  assign adc_data_6 = dma_data[1*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):1*ADC_TO_DMA_N_BITS];
+  assign adc_data_5 = dma_data[2*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):2*ADC_TO_DMA_N_BITS];
+  assign adc_data_4 = dma_data[3*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):3*ADC_TO_DMA_N_BITS];
+  assign adc_data_3 = dma_data[4*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):4*ADC_TO_DMA_N_BITS];
+  assign adc_data_2 = dma_data[5*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):5*ADC_TO_DMA_N_BITS];
+  assign adc_data_1 = dma_data[6*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):6*ADC_TO_DMA_N_BITS];
+  assign adc_data_0 = dma_data[7*ADC_TO_DMA_N_BITS+(ADC_TO_DMA_N_BITS-1):7*ADC_TO_DMA_N_BITS];
 
   up_adc_common #(
     .ID (ID),
diff --git a/adi_library/axi_ad7606x/axi_ad7606x.xpr b/adi_library/axi_ad7606x/axi_ad7606x.xpr
index a8b5ba8c..099906c6 100644
--- a/adi_library/axi_ad7606x/axi_ad7606x.xpr
+++ b/adi_library/axi_ad7606x/axi_ad7606x.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ad7606x/axi_ad7606x.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_ad7606x/axi_ad7606x.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="f98c19d8f31b4047a3ade4396f117f50"/>
+    <Option Name="Id" Val="40df9cdf569447488e830fd95f23701b"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -271,21 +270,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -298,7 +297,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_ad7606x/axi_ad7606x_16b_pif.v b/adi_library/axi_ad7606x/axi_ad7606x_16b_pif.v
index a1fbf90a..37c7f4e0 100644
--- a/adi_library/axi_ad7606x/axi_ad7606x_16b_pif.v
+++ b/adi_library/axi_ad7606x/axi_ad7606x_16b_pif.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad7606x/axi_ad7606x_18b_pif.v b/adi_library/axi_ad7606x/axi_ad7606x_18b_pif.v
index 76cdf702..d98b6523 100644
--- a/adi_library/axi_ad7606x/axi_ad7606x_18b_pif.v
+++ b/adi_library/axi_ad7606x/axi_ad7606x_18b_pif.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad7606x/component.xml b/adi_library/axi_ad7606x/component.xml
index 2616960a..a03c248a 100644
--- a/adi_library/axi_ad7606x/component.xml
+++ b/adi_library/axi_ad7606x/component.xml
@@ -301,7 +301,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>499fbfb9</spirit:value>
+            <spirit:value>a633c222</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -317,7 +317,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>b5e2e2ed</spirit:value>
+            <spirit:value>630b2c18</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -331,7 +331,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>c7c7b169</spirit:value>
+            <spirit:value>3717393a</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -861,7 +861,7 @@
         <spirit:wire>
           <spirit:direction>out</spirit:direction>
           <spirit:vector>
-            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_CH_DW&apos;)) - 1)">15</spirit:left>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_TO_DMA_N_BITS&apos;)) - 1)">15</spirit:left>
             <spirit:right spirit:format="long">0</spirit:right>
           </spirit:vector>
           <spirit:wireTypeDefs>
@@ -878,7 +878,7 @@
         <spirit:wire>
           <spirit:direction>out</spirit:direction>
           <spirit:vector>
-            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_CH_DW&apos;)) - 1)">15</spirit:left>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_TO_DMA_N_BITS&apos;)) - 1)">15</spirit:left>
             <spirit:right spirit:format="long">0</spirit:right>
           </spirit:vector>
           <spirit:wireTypeDefs>
@@ -895,7 +895,7 @@
         <spirit:wire>
           <spirit:direction>out</spirit:direction>
           <spirit:vector>
-            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_CH_DW&apos;)) - 1)">15</spirit:left>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_TO_DMA_N_BITS&apos;)) - 1)">15</spirit:left>
             <spirit:right spirit:format="long">0</spirit:right>
           </spirit:vector>
           <spirit:wireTypeDefs>
@@ -912,7 +912,7 @@
         <spirit:wire>
           <spirit:direction>out</spirit:direction>
           <spirit:vector>
-            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_CH_DW&apos;)) - 1)">15</spirit:left>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_TO_DMA_N_BITS&apos;)) - 1)">15</spirit:left>
             <spirit:right spirit:format="long">0</spirit:right>
           </spirit:vector>
           <spirit:wireTypeDefs>
@@ -929,7 +929,7 @@
         <spirit:wire>
           <spirit:direction>out</spirit:direction>
           <spirit:vector>
-            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_CH_DW&apos;)) - 1)">15</spirit:left>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_TO_DMA_N_BITS&apos;)) - 1)">15</spirit:left>
             <spirit:right spirit:format="long">0</spirit:right>
           </spirit:vector>
           <spirit:wireTypeDefs>
@@ -946,7 +946,7 @@
         <spirit:wire>
           <spirit:direction>out</spirit:direction>
           <spirit:vector>
-            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_CH_DW&apos;)) - 1)">15</spirit:left>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_TO_DMA_N_BITS&apos;)) - 1)">15</spirit:left>
             <spirit:right spirit:format="long">0</spirit:right>
           </spirit:vector>
           <spirit:wireTypeDefs>
@@ -963,7 +963,7 @@
         <spirit:wire>
           <spirit:direction>out</spirit:direction>
           <spirit:vector>
-            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_CH_DW&apos;)) - 1)">15</spirit:left>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_TO_DMA_N_BITS&apos;)) - 1)">15</spirit:left>
             <spirit:right spirit:format="long">0</spirit:right>
           </spirit:vector>
           <spirit:wireTypeDefs>
@@ -980,7 +980,7 @@
         <spirit:wire>
           <spirit:direction>out</spirit:direction>
           <spirit:vector>
-            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_CH_DW&apos;)) - 1)">15</spirit:left>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.ADC_TO_DMA_N_BITS&apos;)) - 1)">15</spirit:left>
             <spirit:right spirit:format="long">0</spirit:right>
           </spirit:vector>
           <spirit:wireTypeDefs>
@@ -1122,9 +1122,9 @@
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.DEV_CONFIG">0</spirit:value>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
-        <spirit:name>ADC_CH_DW</spirit:name>
-        <spirit:displayName>Adc Ch Dw</spirit:displayName>
-        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ADC_CH_DW">16</spirit:value>
+        <spirit:name>ADC_TO_DMA_N_BITS</spirit:name>
+        <spirit:displayName>Adc To Dma N Bits</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ADC_TO_DMA_N_BITS">16</spirit:value>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>ADC_N_BITS</spirit:name>
@@ -1217,7 +1217,7 @@
       <spirit:file>
         <spirit:name>axi_ad7606x.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_461f9622</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_32b3b7fc</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1276,7 +1276,7 @@
       <spirit:file>
         <spirit:name>xgui/axi_ad7606x_v1_0.tcl</spirit:name>
         <spirit:fileType>tclSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_3f71ec0b</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_b9f13221</spirit:userFileType>
         <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
@@ -1294,9 +1294,9 @@
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_CONFIG" spirit:choiceRef="choice_pairs_5f95957e">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
-      <spirit:name>ADC_CH_DW</spirit:name>
-      <spirit:displayName>Adc Ch Dw</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ADC_CH_DW">16</spirit:value>
+      <spirit:name>ADC_TO_DMA_N_BITS</spirit:name>
+      <spirit:displayName>Adc To Dma N Bits</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ADC_TO_DMA_N_BITS">16</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>ADC_N_BITS</spirit:name>
@@ -1351,14 +1351,14 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_ad7606x</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:38:47Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T02:54:24Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="d8c51c8e"/>
-      <xilinx:checksum xilinx:scope="ports" xilinx:value="ca30ecb6"/>
-      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="e88a6568"/>
-      <xilinx:checksum xilinx:scope="parameters" xilinx:value="5ea7cf2e"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="ee06b4eb"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="52e2ee87"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="8453a226"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="2909d2ed"/>
     </xilinx:packagingInfo>
   </spirit:vendorExtensions>
 </spirit:component>
diff --git a/adi_library/axi_ad7606x/xgui/axi_ad7606x_v1_0.tcl b/adi_library/axi_ad7606x/xgui/axi_ad7606x_v1_0.tcl
index 1e935d3d..bf93ac3f 100644
--- a/adi_library/axi_ad7606x/xgui/axi_ad7606x_v1_0.tcl
+++ b/adi_library/axi_ad7606x/xgui/axi_ad7606x_v1_0.tcl
@@ -10,15 +10,6 @@ proc init_gui { IPINST } {
 
 }
 
-proc update_PARAM_VALUE.ADC_CH_DW { PARAM_VALUE.ADC_CH_DW } {
-	# Procedure called to update ADC_CH_DW when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.ADC_CH_DW { PARAM_VALUE.ADC_CH_DW } {
-	# Procedure called to validate ADC_CH_DW
-	return true
-}
-
 proc update_PARAM_VALUE.ADC_N_BITS { PARAM_VALUE.ADC_N_BITS } {
 	# Procedure called to update ADC_N_BITS when any of the dependent parameters in the arguments change
 }
@@ -28,6 +19,15 @@ proc validate_PARAM_VALUE.ADC_N_BITS { PARAM_VALUE.ADC_N_BITS } {
 	return true
 }
 
+proc update_PARAM_VALUE.ADC_TO_DMA_N_BITS { PARAM_VALUE.ADC_TO_DMA_N_BITS } {
+	# Procedure called to update ADC_TO_DMA_N_BITS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.ADC_TO_DMA_N_BITS { PARAM_VALUE.ADC_TO_DMA_N_BITS } {
+	# Procedure called to validate ADC_TO_DMA_N_BITS
+	return true
+}
+
 proc update_PARAM_VALUE.DEV_CONFIG { PARAM_VALUE.DEV_CONFIG } {
 	# Procedure called to update DEV_CONFIG when any of the dependent parameters in the arguments change
 }
@@ -66,9 +66,9 @@ proc update_MODELPARAM_VALUE.DEV_CONFIG { MODELPARAM_VALUE.DEV_CONFIG PARAM_VALU
 	set_property value [get_property value ${PARAM_VALUE.DEV_CONFIG}] ${MODELPARAM_VALUE.DEV_CONFIG}
 }
 
-proc update_MODELPARAM_VALUE.ADC_CH_DW { MODELPARAM_VALUE.ADC_CH_DW PARAM_VALUE.ADC_CH_DW } {
+proc update_MODELPARAM_VALUE.ADC_TO_DMA_N_BITS { MODELPARAM_VALUE.ADC_TO_DMA_N_BITS PARAM_VALUE.ADC_TO_DMA_N_BITS } {
 	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
-	set_property value [get_property value ${PARAM_VALUE.ADC_CH_DW}] ${MODELPARAM_VALUE.ADC_CH_DW}
+	set_property value [get_property value ${PARAM_VALUE.ADC_TO_DMA_N_BITS}] ${MODELPARAM_VALUE.ADC_TO_DMA_N_BITS}
 }
 
 proc update_MODELPARAM_VALUE.ADC_N_BITS { MODELPARAM_VALUE.ADC_N_BITS PARAM_VALUE.ADC_N_BITS } {
diff --git a/adi_library/axi_ad7616/axi_ad7616.v b/adi_library/axi_ad7616/axi_ad7616.v
index 6b69f1c7..f93ff540 100644
--- a/adi_library/axi_ad7616/axi_ad7616.v
+++ b/adi_library/axi_ad7616/axi_ad7616.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad7616/axi_ad7616.xpr b/adi_library/axi_ad7616/axi_ad7616.xpr
index aae0d225..5025a4fc 100644
--- a/adi_library/axi_ad7616/axi_ad7616.xpr
+++ b/adi_library/axi_ad7616/axi_ad7616.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ad7616/axi_ad7616.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_ad7616/axi_ad7616.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="4b81a98c2c4b499bb28073a92284c269"/>
+    <Option Name="Id" Val="2a16dcbbaaba4f99b114dd9d3871343c"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -175,21 +174,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -202,7 +201,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_ad7616/axi_ad7616_control.v b/adi_library/axi_ad7616/axi_ad7616_control.v
index 6c842ce4..3283922a 100644
--- a/adi_library/axi_ad7616/axi_ad7616_control.v
+++ b/adi_library/axi_ad7616/axi_ad7616_control.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad7616/axi_ad7616_pif.v b/adi_library/axi_ad7616/axi_ad7616_pif.v
index 7e131db0..4ad8a4a4 100644
--- a/adi_library/axi_ad7616/axi_ad7616_pif.v
+++ b/adi_library/axi_ad7616/axi_ad7616_pif.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad7616/component.xml b/adi_library/axi_ad7616/component.xml
index 24548d5f..c8a09f41 100644
--- a/adi_library/axi_ad7616/component.xml
+++ b/adi_library/axi_ad7616/component.xml
@@ -241,7 +241,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>c191877d</spirit:value>
+            <spirit:value>a15f1752</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -257,7 +257,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>c191877d</spirit:value>
+            <spirit:value>a15f1752</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -798,7 +798,7 @@
       <spirit:file>
         <spirit:name>axi_ad7616.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_2739560c</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_b233ad5c</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -880,11 +880,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_ad7616</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:38:56Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T02:54:34Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="ac532484"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="ed2489c8"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="6614b440"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="3313f287"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="1d0290c9"/>
diff --git a/adi_library/axi_ad7768/axi_ad7768.v b/adi_library/axi_ad7768/axi_ad7768.v
index 0e27f0d5..2e8c700b 100644
--- a/adi_library/axi_ad7768/axi_ad7768.v
+++ b/adi_library/axi_ad7768/axi_ad7768.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad7768/axi_ad7768.xpr b/adi_library/axi_ad7768/axi_ad7768.xpr
index 99fea34f..db4eaddf 100644
--- a/adi_library/axi_ad7768/axi_ad7768.xpr
+++ b/adi_library/axi_ad7768/axi_ad7768.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ad7768/axi_ad7768.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_ad7768/axi_ad7768.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="884f6cf47a34466d8843a15b819687b9"/>
+    <Option Name="Id" Val="2f52f28e8fa44b5481ed2bea71d9a803"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -281,21 +280,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -308,7 +307,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_ad7768/axi_ad7768_if.v b/adi_library/axi_ad7768/axi_ad7768_if.v
index a59c898c..fcc4514d 100644
--- a/adi_library/axi_ad7768/axi_ad7768_if.v
+++ b/adi_library/axi_ad7768/axi_ad7768_if.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad7768/component.xml b/adi_library/axi_ad7768/component.xml
index f4c287a7..62848eac 100644
--- a/adi_library/axi_ad7768/component.xml
+++ b/adi_library/axi_ad7768/component.xml
@@ -301,7 +301,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>0214c281</spirit:value>
+            <spirit:value>55f5cc13</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -317,7 +317,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>baa268ac</spirit:value>
+            <spirit:value>5e795ebb</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1446,7 +1446,7 @@
       <spirit:file>
         <spirit:name>axi_ad7768.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_54865af8</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_6ab55465</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1560,11 +1560,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/ad7768</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:39:13Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T02:54:52Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="9f42b3c7"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="46450196"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="4bc981f3"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="e4476123"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="2a4b4927"/>
diff --git a/adi_library/axi_ad777x/axi_ad777x.v b/adi_library/axi_ad777x/axi_ad777x.v
index d8f1d46e..b311b762 100644
--- a/adi_library/axi_ad777x/axi_ad777x.v
+++ b/adi_library/axi_ad777x/axi_ad777x.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad777x/axi_ad777x.xpr b/adi_library/axi_ad777x/axi_ad777x.xpr
index 76797772..10e0d20d 100644
--- a/adi_library/axi_ad777x/axi_ad777x.xpr
+++ b/adi_library/axi_ad777x/axi_ad777x.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ad777x/axi_ad777x.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_ad777x/axi_ad777x.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="8bfd791aa93e490599f044d131bc75bd"/>
+    <Option Name="Id" Val="57933d42906c4e68b3c22cfabdeafd31"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -265,21 +264,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -292,7 +291,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_ad777x/axi_ad777x_if.v b/adi_library/axi_ad777x/axi_ad777x_if.v
index c260b82e..e9511631 100644
--- a/adi_library/axi_ad777x/axi_ad777x_if.v
+++ b/adi_library/axi_ad777x/axi_ad777x_if.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad777x/component.xml b/adi_library/axi_ad777x/component.xml
index f1120c2e..cde138e7 100644
--- a/adi_library/axi_ad777x/component.xml
+++ b/adi_library/axi_ad777x/component.xml
@@ -301,7 +301,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>7b5d4a4d</spirit:value>
+            <spirit:value>1cd74629</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -317,7 +317,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>c5473c1f</spirit:value>
+            <spirit:value>ab4a21cf</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1242,7 +1242,7 @@
       <spirit:file>
         <spirit:name>axi_ad777x.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_c058d44e</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_55d3d8cc</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1351,11 +1351,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/ad777x</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:39:29Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T02:55:09Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="6c8ab4b4"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="bc6ae9a9"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="ae899c3e"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="3313f287"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="dbd96ef0"/>
diff --git a/adi_library/axi_ad9122/axi_ad9122.v b/adi_library/axi_ad9122/axi_ad9122.v
index 14952afe..799738e2 100644
--- a/adi_library/axi_ad9122/axi_ad9122.v
+++ b/adi_library/axi_ad9122/axi_ad9122.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9122/axi_ad9122.xpr b/adi_library/axi_ad9122/axi_ad9122.xpr
index 1f428c6f..01728cd3 100644
--- a/adi_library/axi_ad9122/axi_ad9122.xpr
+++ b/adi_library/axi_ad9122/axi_ad9122.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ad9122/axi_ad9122.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_ad9122/axi_ad9122.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="d9c2ae66cf6c4634bc3fcad381d3a4d9"/>
+    <Option Name="Id" Val="5e399289b1214b2ab233f4ae4544ffb5"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -331,21 +330,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -358,7 +357,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_ad9122/axi_ad9122_channel.v b/adi_library/axi_ad9122/axi_ad9122_channel.v
index 7fecc676..a092d3a7 100644
--- a/adi_library/axi_ad9122/axi_ad9122_channel.v
+++ b/adi_library/axi_ad9122/axi_ad9122_channel.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9122/axi_ad9122_core.v b/adi_library/axi_ad9122/axi_ad9122_core.v
index 4b701488..f327ad39 100644
--- a/adi_library/axi_ad9122/axi_ad9122_core.v
+++ b/adi_library/axi_ad9122/axi_ad9122_core.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9122/axi_ad9122_if.v b/adi_library/axi_ad9122/axi_ad9122_if.v
index 4f9ba61d..2f2e4eb9 100644
--- a/adi_library/axi_ad9122/axi_ad9122_if.v
+++ b/adi_library/axi_ad9122/axi_ad9122_if.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9122/component.xml b/adi_library/axi_ad9122/component.xml
index dc3776d4..88b49fe3 100644
--- a/adi_library/axi_ad9122/component.xml
+++ b/adi_library/axi_ad9122/component.xml
@@ -321,7 +321,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>95d72be9</spirit:value>
+            <spirit:value>1b76da3a</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -337,7 +337,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>c583edc2</spirit:value>
+            <spirit:value>a269442d</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1058,30 +1058,6 @@
       <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
       <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
     </spirit:choice>
-    <spirit:choice>
-      <spirit:name>choice_pairs_00ecfe9a</spirit:name>
-      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
-      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
-      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
-      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
-      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
-      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
-      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
-      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
-      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
-      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
-      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
-      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
-      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
-      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
-      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
-      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
-      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
-      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
-      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
-      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
-      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
-    </spirit:choice>
     <spirit:choice>
       <spirit:name>choice_pairs_19f99f31</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
@@ -1107,7 +1083,32 @@
       <spirit:enumeration spirit:text="versal">4</spirit:enumeration>
     </spirit:choice>
     <spirit:choice>
-      <spirit:name>choice_pairs_fc01a186</spirit:name>
+      <spirit:name>choice_pairs_a6e6e044</spirit:name>
+      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
+      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
+      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
+      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
+      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
+      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
+      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
+      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
+      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
+      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
+      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
+      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
+      <spirit:enumeration spirit:text="ls">21</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a897e79d</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
       <spirit:enumeration spirit:text="artix">1</spirit:enumeration>
       <spirit:enumeration spirit:text="kintex">2</spirit:enumeration>
@@ -1115,6 +1116,7 @@
       <spirit:enumeration spirit:text="zynq">4</spirit:enumeration>
       <spirit:enumeration spirit:text="versalprime">5</spirit:enumeration>
       <spirit:enumeration spirit:text="versalaicore">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="versalpremium">7</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
   <spirit:fileSets>
@@ -1223,7 +1225,7 @@
       <spirit:file>
         <spirit:name>axi_ad9122.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_27052783</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_117d2bdf</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1345,7 +1347,7 @@
     <spirit:parameter>
       <spirit:name>FPGA_FAMILY</spirit:name>
       <spirit:displayName>Fpga Family</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_fc01a186">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_a897e79d">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>SPEED_GRADE</spirit:name>
@@ -1355,7 +1357,7 @@
     <spirit:parameter>
       <spirit:name>DEV_PACKAGE</spirit:name>
       <spirit:displayName>Dev Package</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_00ecfe9a">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_a6e6e044">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>SERDES_OR_DDR_N</spirit:name>
@@ -1460,11 +1462,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:39:49Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T02:55:31Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="988ce6ed"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4b0d0aa5"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="95c116c1"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ef9a7a32"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="1acdfef7"/>
diff --git a/adi_library/axi_ad9250/axi_ad9250.v b/adi_library/axi_ad9250/axi_ad9250.v
index 7c8f1e0e..39c79c3f 100644
--- a/adi_library/axi_ad9250/axi_ad9250.v
+++ b/adi_library/axi_ad9250/axi_ad9250.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9250/axi_ad9250.xpr b/adi_library/axi_ad9250/axi_ad9250.xpr
index 37fa40c1..58cdebd5 100644
--- a/adi_library/axi_ad9250/axi_ad9250.xpr
+++ b/adi_library/axi_ad9250/axi_ad9250.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ad9250/axi_ad9250.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_ad9250/axi_ad9250.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="09dab988e46943cc9ad0a47f5b3001f8"/>
+    <Option Name="Id" Val="50bf6457f7a645a799cda399a6ba6657"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -161,21 +160,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -188,7 +187,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_ad9250/component.xml b/adi_library/axi_ad9250/component.xml
index 73eb7a71..f420cf16 100644
--- a/adi_library/axi_ad9250/component.xml
+++ b/adi_library/axi_ad9250/component.xml
@@ -276,7 +276,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>8673dcf2</spirit:value>
+            <spirit:value>a7df7a0f</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -295,7 +295,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>8673dcf2</spirit:value>
+            <spirit:value>a7df7a0f</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -900,30 +900,6 @@
       <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
       <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
     </spirit:choice>
-    <spirit:choice>
-      <spirit:name>choice_pairs_00ecfe9a</spirit:name>
-      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
-      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
-      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
-      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
-      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
-      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
-      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
-      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
-      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
-      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
-      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
-      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
-      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
-      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
-      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
-      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
-      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
-      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
-      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
-      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
-      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
-    </spirit:choice>
     <spirit:choice>
       <spirit:name>choice_pairs_19f99f31</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
@@ -949,7 +925,32 @@
       <spirit:enumeration spirit:text="versal">4</spirit:enumeration>
     </spirit:choice>
     <spirit:choice>
-      <spirit:name>choice_pairs_fc01a186</spirit:name>
+      <spirit:name>choice_pairs_a6e6e044</spirit:name>
+      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
+      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
+      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
+      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
+      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
+      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
+      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
+      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
+      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
+      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
+      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
+      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
+      <spirit:enumeration spirit:text="ls">21</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a897e79d</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
       <spirit:enumeration spirit:text="artix">1</spirit:enumeration>
       <spirit:enumeration spirit:text="kintex">2</spirit:enumeration>
@@ -957,6 +958,7 @@
       <spirit:enumeration spirit:text="zynq">4</spirit:enumeration>
       <spirit:enumeration spirit:text="versalprime">5</spirit:enumeration>
       <spirit:enumeration spirit:text="versalaicore">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="versalpremium">7</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
   <spirit:fileSets>
@@ -965,7 +967,7 @@
       <spirit:file>
         <spirit:name>axi_ad9250.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_8673dcf2</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_a7df7a0f</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1043,7 +1045,7 @@
     <spirit:parameter>
       <spirit:name>FPGA_FAMILY</spirit:name>
       <spirit:displayName>Fpga Family</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_fc01a186">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_a897e79d">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>SPEED_GRADE</spirit:name>
@@ -1053,7 +1055,7 @@
     <spirit:parameter>
       <spirit:name>DEV_PACKAGE</spirit:name>
       <spirit:displayName>Dev Package</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_00ecfe9a">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_a6e6e044">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>Component_Name</spirit:name>
@@ -1098,11 +1100,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:40:16Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T02:56:00Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="86648ed2"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="d5b002dc"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="c911b6ce"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ce5c6c35"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="ec3d6140"/>
diff --git a/adi_library/axi_ad9265/axi_ad9265.v b/adi_library/axi_ad9265/axi_ad9265.v
index 92b5b164..2d2014e7 100644
--- a/adi_library/axi_ad9265/axi_ad9265.v
+++ b/adi_library/axi_ad9265/axi_ad9265.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9265/axi_ad9265.xpr b/adi_library/axi_ad9265/axi_ad9265.xpr
index 2592d63b..61e59d8f 100644
--- a/adi_library/axi_ad9265/axi_ad9265.xpr
+++ b/adi_library/axi_ad9265/axi_ad9265.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ad9265/axi_ad9265.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_ad9265/axi_ad9265.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="8ad18344dbd04b769f94c3942194800a"/>
+    <Option Name="Id" Val="a7ee41a31cf8462f9a6af9e11383e922"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -297,21 +296,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -324,7 +323,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_ad9265/axi_ad9265_channel.v b/adi_library/axi_ad9265/axi_ad9265_channel.v
index 9eb736fe..a29e75a1 100644
--- a/adi_library/axi_ad9265/axi_ad9265_channel.v
+++ b/adi_library/axi_ad9265/axi_ad9265_channel.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9265/axi_ad9265_if.v b/adi_library/axi_ad9265/axi_ad9265_if.v
index abeb2c74..cb24387b 100644
--- a/adi_library/axi_ad9265/axi_ad9265_if.v
+++ b/adi_library/axi_ad9265/axi_ad9265_if.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9265/axi_ad9265_pnmon.v b/adi_library/axi_ad9265/axi_ad9265_pnmon.v
index 3b51442c..11a83c9b 100644
--- a/adi_library/axi_ad9265/axi_ad9265_pnmon.v
+++ b/adi_library/axi_ad9265/axi_ad9265_pnmon.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9265/component.xml b/adi_library/axi_ad9265/component.xml
index 777a7d69..e8afc274 100644
--- a/adi_library/axi_ad9265/component.xml
+++ b/adi_library/axi_ad9265/component.xml
@@ -327,7 +327,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>3e8bc828</spirit:value>
+            <spirit:value>4aa55076</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -343,7 +343,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>d0cfa85e</spirit:value>
+            <spirit:value>7d51211a</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -948,30 +948,6 @@
       <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
       <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
     </spirit:choice>
-    <spirit:choice>
-      <spirit:name>choice_pairs_00ecfe9a</spirit:name>
-      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
-      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
-      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
-      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
-      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
-      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
-      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
-      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
-      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
-      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
-      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
-      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
-      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
-      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
-      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
-      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
-      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
-      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
-      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
-      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
-      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
-    </spirit:choice>
     <spirit:choice>
       <spirit:name>choice_pairs_19f99f31</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
@@ -997,7 +973,32 @@
       <spirit:enumeration spirit:text="versal">4</spirit:enumeration>
     </spirit:choice>
     <spirit:choice>
-      <spirit:name>choice_pairs_fc01a186</spirit:name>
+      <spirit:name>choice_pairs_a6e6e044</spirit:name>
+      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
+      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
+      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
+      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
+      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
+      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
+      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
+      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
+      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
+      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
+      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
+      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
+      <spirit:enumeration spirit:text="ls">21</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a897e79d</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
       <spirit:enumeration spirit:text="artix">1</spirit:enumeration>
       <spirit:enumeration spirit:text="kintex">2</spirit:enumeration>
@@ -1005,6 +1006,7 @@
       <spirit:enumeration spirit:text="zynq">4</spirit:enumeration>
       <spirit:enumeration spirit:text="versalprime">5</spirit:enumeration>
       <spirit:enumeration spirit:text="versalaicore">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="versalpremium">7</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
   <spirit:fileSets>
@@ -1093,7 +1095,7 @@
       <spirit:file>
         <spirit:name>axi_ad9265.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_e418fdd8</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_28e744c7</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1199,7 +1201,7 @@
     <spirit:parameter>
       <spirit:name>FPGA_FAMILY</spirit:name>
       <spirit:displayName>Fpga Family</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_fc01a186">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_a897e79d">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>SPEED_GRADE</spirit:name>
@@ -1209,7 +1211,7 @@
     <spirit:parameter>
       <spirit:name>DEV_PACKAGE</spirit:name>
       <spirit:displayName>Dev Package</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_00ecfe9a">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_a6e6e044">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>ADC_DATAPATH_DISABLE</spirit:name>
@@ -1264,11 +1266,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_ad9265</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:40:37Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T02:56:19Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="9cbcdf10"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="56f37a0a"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="269205b6"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="84e52892"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="71f5d1d4"/>
diff --git a/adi_library/axi_ad9361/axi_ad9361.v b/adi_library/axi_ad9361/axi_ad9361.v
index 01c7ef76..709e5760 100644
--- a/adi_library/axi_ad9361/axi_ad9361.v
+++ b/adi_library/axi_ad9361/axi_ad9361.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9361/axi_ad9361.xpr b/adi_library/axi_ad9361/axi_ad9361.xpr
index c400e6aa..22bda2a5 100644
--- a/adi_library/axi_ad9361/axi_ad9361.xpr
+++ b/adi_library/axi_ad9361/axi_ad9361.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ad9361/axi_ad9361.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_ad9361/axi_ad9361.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="0e2af205f40244a6b02e93f5d878d6c0"/>
+    <Option Name="Id" Val="a9ebb0d97cc24ed68b232de075997d67"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -451,21 +450,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -478,7 +477,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_ad9361/axi_ad9361_rx.v b/adi_library/axi_ad9361/axi_ad9361_rx.v
index 0e94f63c..ccf3a24b 100644
--- a/adi_library/axi_ad9361/axi_ad9361_rx.v
+++ b/adi_library/axi_ad9361/axi_ad9361_rx.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9361/axi_ad9361_rx_channel.v b/adi_library/axi_ad9361/axi_ad9361_rx_channel.v
index 4ed32492..35a27b51 100644
--- a/adi_library/axi_ad9361/axi_ad9361_rx_channel.v
+++ b/adi_library/axi_ad9361/axi_ad9361_rx_channel.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9361/axi_ad9361_rx_pnmon.v b/adi_library/axi_ad9361/axi_ad9361_rx_pnmon.v
index fb90cd85..07636370 100644
--- a/adi_library/axi_ad9361/axi_ad9361_rx_pnmon.v
+++ b/adi_library/axi_ad9361/axi_ad9361_rx_pnmon.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9361/axi_ad9361_tdd.v b/adi_library/axi_ad9361/axi_ad9361_tdd.v
index 6392bdf2..405819a8 100644
--- a/adi_library/axi_ad9361/axi_ad9361_tdd.v
+++ b/adi_library/axi_ad9361/axi_ad9361_tdd.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9361/axi_ad9361_tdd_if.v b/adi_library/axi_ad9361/axi_ad9361_tdd_if.v
index 3583ceb1..0c5a847a 100644
--- a/adi_library/axi_ad9361/axi_ad9361_tdd_if.v
+++ b/adi_library/axi_ad9361/axi_ad9361_tdd_if.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9361/axi_ad9361_tx.v b/adi_library/axi_ad9361/axi_ad9361_tx.v
index 07c3008d..1ddc4395 100644
--- a/adi_library/axi_ad9361/axi_ad9361_tx.v
+++ b/adi_library/axi_ad9361/axi_ad9361_tx.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9361/axi_ad9361_tx_channel.v b/adi_library/axi_ad9361/axi_ad9361_tx_channel.v
index 82ea69d7..c8d0f0c0 100644
--- a/adi_library/axi_ad9361/axi_ad9361_tx_channel.v
+++ b/adi_library/axi_ad9361/axi_ad9361_tx_channel.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9361/component.xml b/adi_library/axi_ad9361/component.xml
index 08644253..3c52811e 100644
--- a/adi_library/axi_ad9361/component.xml
+++ b/adi_library/axi_ad9361/component.xml
@@ -339,7 +339,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>2de5525c</spirit:value>
+            <spirit:value>f7a7554b</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -355,7 +355,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>93e7a57e</spirit:value>
+            <spirit:value>a509c859</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1995,30 +1995,6 @@
       <spirit:enumeration>EDGE_RISING</spirit:enumeration>
       <spirit:enumeration>EDGE_FALLING</spirit:enumeration>
     </spirit:choice>
-    <spirit:choice>
-      <spirit:name>choice_pairs_00ecfe9a</spirit:name>
-      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
-      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
-      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
-      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
-      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
-      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
-      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
-      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
-      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
-      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
-      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
-      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
-      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
-      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
-      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
-      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
-      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
-      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
-      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
-      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
-      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
-    </spirit:choice>
     <spirit:choice>
       <spirit:name>choice_pairs_19f99f31</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
@@ -2044,7 +2020,32 @@
       <spirit:enumeration spirit:text="versal">4</spirit:enumeration>
     </spirit:choice>
     <spirit:choice>
-      <spirit:name>choice_pairs_fc01a186</spirit:name>
+      <spirit:name>choice_pairs_a6e6e044</spirit:name>
+      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
+      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
+      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
+      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
+      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
+      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
+      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
+      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
+      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
+      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
+      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
+      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
+      <spirit:enumeration spirit:text="ls">21</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a897e79d</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
       <spirit:enumeration spirit:text="artix">1</spirit:enumeration>
       <spirit:enumeration spirit:text="kintex">2</spirit:enumeration>
@@ -2052,6 +2053,7 @@
       <spirit:enumeration spirit:text="zynq">4</spirit:enumeration>
       <spirit:enumeration spirit:text="versalprime">5</spirit:enumeration>
       <spirit:enumeration spirit:text="versalaicore">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="versalpremium">7</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
   <spirit:fileSets>
@@ -2232,7 +2234,7 @@
       <spirit:file>
         <spirit:name>axi_ad9361.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_c067097f</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_dc8f7194</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -2427,7 +2429,7 @@
     <spirit:parameter>
       <spirit:name>FPGA_FAMILY</spirit:name>
       <spirit:displayName>Fpga Family</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_fc01a186">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_a897e79d">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>SPEED_GRADE</spirit:name>
@@ -2437,7 +2439,7 @@
     <spirit:parameter>
       <spirit:name>DEV_PACKAGE</spirit:name>
       <spirit:displayName>Dev Package</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_00ecfe9a">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_a6e6e044">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>TDD_DISABLE</spirit:name>
@@ -2588,11 +2590,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_ad9361</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:41:10Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T02:56:54Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="1c6d0847"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="8aef4f29"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="16977efc"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="709878f9"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="c64fb77e"/>
diff --git a/adi_library/axi_ad9361/intel/axi_ad9361_alt_lvds_rx.v b/adi_library/axi_ad9361/intel/axi_ad9361_alt_lvds_rx.v
index a73f6a74..a12341f7 100644
--- a/adi_library/axi_ad9361/intel/axi_ad9361_alt_lvds_rx.v
+++ b/adi_library/axi_ad9361/intel/axi_ad9361_alt_lvds_rx.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9361/intel/axi_ad9361_alt_lvds_tx.v b/adi_library/axi_ad9361/intel/axi_ad9361_alt_lvds_tx.v
index eebb11fb..699c3e37 100644
--- a/adi_library/axi_ad9361/intel/axi_ad9361_alt_lvds_tx.v
+++ b/adi_library/axi_ad9361/intel/axi_ad9361_alt_lvds_tx.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9361/intel/axi_ad9361_cmos_if.v b/adi_library/axi_ad9361/intel/axi_ad9361_cmos_if.v
index a3b02fa1..562bf850 100644
--- a/adi_library/axi_ad9361/intel/axi_ad9361_cmos_if.v
+++ b/adi_library/axi_ad9361/intel/axi_ad9361_cmos_if.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9361/intel/axi_ad9361_lvds_if.v b/adi_library/axi_ad9361/intel/axi_ad9361_lvds_if.v
index 78eb16fd..b7d5b003 100644
--- a/adi_library/axi_ad9361/intel/axi_ad9361_lvds_if.v
+++ b/adi_library/axi_ad9361/intel/axi_ad9361_lvds_if.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9361/intel/axi_ad9361_lvds_if_10.v b/adi_library/axi_ad9361/intel/axi_ad9361_lvds_if_10.v
index 1e35d129..d2adf490 100644
--- a/adi_library/axi_ad9361/intel/axi_ad9361_lvds_if_10.v
+++ b/adi_library/axi_ad9361/intel/axi_ad9361_lvds_if_10.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9361/intel/axi_ad9361_lvds_if_c5.v b/adi_library/axi_ad9361/intel/axi_ad9361_lvds_if_c5.v
index a01980ad..dc7cbbdd 100644
--- a/adi_library/axi_ad9361/intel/axi_ad9361_lvds_if_c5.v
+++ b/adi_library/axi_ad9361/intel/axi_ad9361_lvds_if_c5.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v b/adi_library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v
index 9e9f47b9..dda82a5d 100644
--- a/adi_library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v
+++ b/adi_library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v b/adi_library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
index ee5ca7ce..89b8854d 100644
--- a/adi_library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
+++ b/adi_library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9434/axi_ad9434.v b/adi_library/axi_ad9434/axi_ad9434.v
index cb3da79a..a2c363c9 100644
--- a/adi_library/axi_ad9434/axi_ad9434.v
+++ b/adi_library/axi_ad9434/axi_ad9434.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9434/axi_ad9434.xpr b/adi_library/axi_ad9434/axi_ad9434.xpr
index d6209d34..8c86c029 100644
--- a/adi_library/axi_ad9434/axi_ad9434.xpr
+++ b/adi_library/axi_ad9434/axi_ad9434.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ad9434/axi_ad9434.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_ad9434/axi_ad9434.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="101e4827ee7146f08f153b4e65ff4d83"/>
+    <Option Name="Id" Val="a17ad77cfe3f41ed991d6ab2a8ba1f05"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -303,21 +302,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -330,7 +329,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_ad9434/axi_ad9434_core.v b/adi_library/axi_ad9434/axi_ad9434_core.v
index 7132f74e..9c5f8552 100644
--- a/adi_library/axi_ad9434/axi_ad9434_core.v
+++ b/adi_library/axi_ad9434/axi_ad9434_core.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9434/axi_ad9434_if.v b/adi_library/axi_ad9434/axi_ad9434_if.v
index b27e5990..1c5fccd5 100644
--- a/adi_library/axi_ad9434/axi_ad9434_if.v
+++ b/adi_library/axi_ad9434/axi_ad9434_if.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9434/axi_ad9434_pnmon.v b/adi_library/axi_ad9434/axi_ad9434_pnmon.v
index a7c645d0..b7453cb3 100644
--- a/adi_library/axi_ad9434/axi_ad9434_pnmon.v
+++ b/adi_library/axi_ad9434/axi_ad9434_pnmon.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9434/component.xml b/adi_library/axi_ad9434/component.xml
index 77341550..e95c8841 100644
--- a/adi_library/axi_ad9434/component.xml
+++ b/adi_library/axi_ad9434/component.xml
@@ -273,7 +273,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>fe8e998e</spirit:value>
+            <spirit:value>20b351d1</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -289,7 +289,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>56668191</spirit:value>
+            <spirit:value>44d67266</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -881,30 +881,6 @@
       <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
       <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
     </spirit:choice>
-    <spirit:choice>
-      <spirit:name>choice_pairs_00ecfe9a</spirit:name>
-      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
-      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
-      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
-      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
-      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
-      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
-      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
-      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
-      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
-      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
-      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
-      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
-      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
-      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
-      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
-      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
-      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
-      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
-      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
-      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
-      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
-    </spirit:choice>
     <spirit:choice>
       <spirit:name>choice_pairs_19f99f31</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
@@ -930,7 +906,32 @@
       <spirit:enumeration spirit:text="versal">4</spirit:enumeration>
     </spirit:choice>
     <spirit:choice>
-      <spirit:name>choice_pairs_fc01a186</spirit:name>
+      <spirit:name>choice_pairs_a6e6e044</spirit:name>
+      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
+      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
+      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
+      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
+      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
+      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
+      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
+      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
+      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
+      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
+      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
+      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
+      <spirit:enumeration spirit:text="ls">21</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a897e79d</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
       <spirit:enumeration spirit:text="artix">1</spirit:enumeration>
       <spirit:enumeration spirit:text="kintex">2</spirit:enumeration>
@@ -938,6 +939,7 @@
       <spirit:enumeration spirit:text="zynq">4</spirit:enumeration>
       <spirit:enumeration spirit:text="versalprime">5</spirit:enumeration>
       <spirit:enumeration spirit:text="versalaicore">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="versalpremium">7</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
   <spirit:fileSets>
@@ -1030,7 +1032,7 @@
       <spirit:file>
         <spirit:name>axi_ad9434.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_abffd711</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_1da28368</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1136,7 +1138,7 @@
     <spirit:parameter>
       <spirit:name>FPGA_FAMILY</spirit:name>
       <spirit:displayName>Fpga Family</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_fc01a186">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_a897e79d">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>SPEED_GRADE</spirit:name>
@@ -1146,7 +1148,7 @@
     <spirit:parameter>
       <spirit:name>DEV_PACKAGE</spirit:name>
       <spirit:displayName>Dev Package</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_00ecfe9a">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_a6e6e044">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>IODELAY_ENABLE</spirit:name>
@@ -1201,11 +1203,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:41:27Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T02:57:13Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="ac5de1aa"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="fbc57ac1"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="e578f71b"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="d9b67764"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="4f89d200"/>
diff --git a/adi_library/axi_ad9467/axi_ad9467.v b/adi_library/axi_ad9467/axi_ad9467.v
index b6dc9bfd..d7ef0056 100644
--- a/adi_library/axi_ad9467/axi_ad9467.v
+++ b/adi_library/axi_ad9467/axi_ad9467.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9467/axi_ad9467.xpr b/adi_library/axi_ad9467/axi_ad9467.xpr
index 8e6add71..5af3cc27 100644
--- a/adi_library/axi_ad9467/axi_ad9467.xpr
+++ b/adi_library/axi_ad9467/axi_ad9467.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ad9467/axi_ad9467.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_ad9467/axi_ad9467.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="9154f683a44a4e9d90ee17fa6aa1f5b5"/>
+    <Option Name="Id" Val="78853f00e64648e4aa40a722f08679f8"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -290,21 +289,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -317,7 +316,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_ad9467/axi_ad9467_channel.v b/adi_library/axi_ad9467/axi_ad9467_channel.v
index a64d8f66..90cc1cfb 100644
--- a/adi_library/axi_ad9467/axi_ad9467_channel.v
+++ b/adi_library/axi_ad9467/axi_ad9467_channel.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9467/axi_ad9467_if.v b/adi_library/axi_ad9467/axi_ad9467_if.v
index b804b464..18b33a8b 100644
--- a/adi_library/axi_ad9467/axi_ad9467_if.v
+++ b/adi_library/axi_ad9467/axi_ad9467_if.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9467/axi_ad9467_pnmon.v b/adi_library/axi_ad9467/axi_ad9467_pnmon.v
index 8f0ec793..d91f66f8 100644
--- a/adi_library/axi_ad9467/axi_ad9467_pnmon.v
+++ b/adi_library/axi_ad9467/axi_ad9467_pnmon.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9467/component.xml b/adi_library/axi_ad9467/component.xml
index a4e1f690..77fce6e6 100644
--- a/adi_library/axi_ad9467/component.xml
+++ b/adi_library/axi_ad9467/component.xml
@@ -305,7 +305,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>565f585b</spirit:value>
+            <spirit:value>621abec9</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -321,7 +321,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>4cefe2bf</spirit:value>
+            <spirit:value>11495b81</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -913,30 +913,6 @@
       <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
       <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
     </spirit:choice>
-    <spirit:choice>
-      <spirit:name>choice_pairs_00ecfe9a</spirit:name>
-      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
-      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
-      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
-      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
-      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
-      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
-      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
-      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
-      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
-      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
-      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
-      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
-      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
-      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
-      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
-      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
-      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
-      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
-      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
-      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
-      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
-    </spirit:choice>
     <spirit:choice>
       <spirit:name>choice_pairs_19f99f31</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
@@ -962,7 +938,32 @@
       <spirit:enumeration spirit:text="versal">4</spirit:enumeration>
     </spirit:choice>
     <spirit:choice>
-      <spirit:name>choice_pairs_fc01a186</spirit:name>
+      <spirit:name>choice_pairs_a6e6e044</spirit:name>
+      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
+      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
+      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
+      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
+      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
+      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
+      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
+      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
+      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
+      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
+      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
+      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
+      <spirit:enumeration spirit:text="ls">21</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a897e79d</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
       <spirit:enumeration spirit:text="artix">1</spirit:enumeration>
       <spirit:enumeration spirit:text="kintex">2</spirit:enumeration>
@@ -970,6 +971,7 @@
       <spirit:enumeration spirit:text="zynq">4</spirit:enumeration>
       <spirit:enumeration spirit:text="versalprime">5</spirit:enumeration>
       <spirit:enumeration spirit:text="versalaicore">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="versalpremium">7</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
   <spirit:fileSets>
@@ -1054,7 +1056,7 @@
       <spirit:file>
         <spirit:name>axi_ad9467.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_f69b9b05</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_1726d5bd</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1156,7 +1158,7 @@
     <spirit:parameter>
       <spirit:name>FPGA_FAMILY</spirit:name>
       <spirit:displayName>Fpga Family</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_fc01a186">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_a897e79d">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>SPEED_GRADE</spirit:name>
@@ -1166,7 +1168,7 @@
     <spirit:parameter>
       <spirit:name>DEV_PACKAGE</spirit:name>
       <spirit:displayName>Dev Package</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_00ecfe9a">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_a6e6e044">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>IO_DELAY_GROUP</spirit:name>
@@ -1221,11 +1223,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_ad9467</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:41:45Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T02:57:32Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="bf549e79"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="7b02f07a"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="7ae9c1bf"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="464ea88e"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="c1c8014a"/>
diff --git a/adi_library/axi_ad9625/axi_ad9625.v b/adi_library/axi_ad9625/axi_ad9625.v
index 7aee8070..2b2bc969 100644
--- a/adi_library/axi_ad9625/axi_ad9625.v
+++ b/adi_library/axi_ad9625/axi_ad9625.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9625/axi_ad9625.xpr b/adi_library/axi_ad9625/axi_ad9625.xpr
index 12ce751d..06c20a90 100644
--- a/adi_library/axi_ad9625/axi_ad9625.xpr
+++ b/adi_library/axi_ad9625/axi_ad9625.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ad9625/axi_ad9625.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_ad9625/axi_ad9625.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="efe6639b30544af796eb52e6f433f60e"/>
+    <Option Name="Id" Val="1d39e2676c5245c6b25845b85620fb53"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -283,21 +282,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -310,7 +309,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_ad9625/axi_ad9625_channel.v b/adi_library/axi_ad9625/axi_ad9625_channel.v
index cd6921b5..fdd26b64 100644
--- a/adi_library/axi_ad9625/axi_ad9625_channel.v
+++ b/adi_library/axi_ad9625/axi_ad9625_channel.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9625/axi_ad9625_if.v b/adi_library/axi_ad9625/axi_ad9625_if.v
index 0ccf1e39..16c5455b 100644
--- a/adi_library/axi_ad9625/axi_ad9625_if.v
+++ b/adi_library/axi_ad9625/axi_ad9625_if.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9625/axi_ad9625_pnmon.v b/adi_library/axi_ad9625/axi_ad9625_pnmon.v
index 3ffeb058..fdbdbf61 100644
--- a/adi_library/axi_ad9625/axi_ad9625_pnmon.v
+++ b/adi_library/axi_ad9625/axi_ad9625_pnmon.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9625/component.xml b/adi_library/axi_ad9625/component.xml
index 515f9866..6c990570 100644
--- a/adi_library/axi_ad9625/component.xml
+++ b/adi_library/axi_ad9625/component.xml
@@ -295,7 +295,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>195caded</spirit:value>
+            <spirit:value>69ef1960</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -311,7 +311,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>881c06b9</spirit:value>
+            <spirit:value>52bfbe75</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -939,30 +939,6 @@
       <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
       <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
     </spirit:choice>
-    <spirit:choice>
-      <spirit:name>choice_pairs_00ecfe9a</spirit:name>
-      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
-      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
-      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
-      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
-      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
-      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
-      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
-      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
-      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
-      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
-      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
-      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
-      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
-      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
-      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
-      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
-      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
-      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
-      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
-      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
-      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
-    </spirit:choice>
     <spirit:choice>
       <spirit:name>choice_pairs_19f99f31</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
@@ -988,7 +964,32 @@
       <spirit:enumeration spirit:text="versal">4</spirit:enumeration>
     </spirit:choice>
     <spirit:choice>
-      <spirit:name>choice_pairs_fc01a186</spirit:name>
+      <spirit:name>choice_pairs_a6e6e044</spirit:name>
+      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
+      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
+      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
+      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
+      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
+      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
+      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
+      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
+      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
+      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
+      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
+      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
+      <spirit:enumeration spirit:text="ls">21</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a897e79d</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
       <spirit:enumeration spirit:text="artix">1</spirit:enumeration>
       <spirit:enumeration spirit:text="kintex">2</spirit:enumeration>
@@ -996,6 +997,7 @@
       <spirit:enumeration spirit:text="zynq">4</spirit:enumeration>
       <spirit:enumeration spirit:text="versalprime">5</spirit:enumeration>
       <spirit:enumeration spirit:text="versalaicore">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="versalpremium">7</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
   <spirit:fileSets>
@@ -1076,7 +1078,7 @@
       <spirit:file>
         <spirit:name>axi_ad9625.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_2272f51d</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_96270da9</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1174,7 +1176,7 @@
     <spirit:parameter>
       <spirit:name>FPGA_FAMILY</spirit:name>
       <spirit:displayName>Fpga Family</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_fc01a186">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_a897e79d">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>SPEED_GRADE</spirit:name>
@@ -1184,7 +1186,7 @@
     <spirit:parameter>
       <spirit:name>DEV_PACKAGE</spirit:name>
       <spirit:displayName>Dev Package</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_00ecfe9a">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_a6e6e044">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>DELAY_REFCLK_FREQUENCY</spirit:name>
@@ -1234,11 +1236,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:42:01Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T02:57:50Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="09f82cb1"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="a78cd55b"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="a6bcbdf3"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="57bcb657"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="a2beb0a2"/>
diff --git a/adi_library/axi_ad9671/axi_ad9671.v b/adi_library/axi_ad9671/axi_ad9671.v
index 1872d7a3..4ab93f09 100644
--- a/adi_library/axi_ad9671/axi_ad9671.v
+++ b/adi_library/axi_ad9671/axi_ad9671.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9671/axi_ad9671.xpr b/adi_library/axi_ad9671/axi_ad9671.xpr
index 94f3234a..909e9f36 100644
--- a/adi_library/axi_ad9671/axi_ad9671.xpr
+++ b/adi_library/axi_ad9671/axi_ad9671.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ad9671/axi_ad9671.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_ad9671/axi_ad9671.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="83fa3bc6a0c64a17864db5ab0aac6807"/>
+    <Option Name="Id" Val="1d25ff68992242da8223a1638403aeca"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -283,21 +282,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -310,7 +309,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_ad9671/axi_ad9671_channel.v b/adi_library/axi_ad9671/axi_ad9671_channel.v
index 5ecb0c0d..d4ba7394 100644
--- a/adi_library/axi_ad9671/axi_ad9671_channel.v
+++ b/adi_library/axi_ad9671/axi_ad9671_channel.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9671/axi_ad9671_if.v b/adi_library/axi_ad9671/axi_ad9671_if.v
index 7644f339..d9aa6374 100644
--- a/adi_library/axi_ad9671/axi_ad9671_if.v
+++ b/adi_library/axi_ad9671/axi_ad9671_if.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9671/axi_ad9671_pnmon.v b/adi_library/axi_ad9671/axi_ad9671_pnmon.v
index 6132b787..fcbcde50 100644
--- a/adi_library/axi_ad9671/axi_ad9671_pnmon.v
+++ b/adi_library/axi_ad9671/axi_ad9671_pnmon.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9671/component.xml b/adi_library/axi_ad9671/component.xml
index d904c52d..633d3a23 100644
--- a/adi_library/axi_ad9671/component.xml
+++ b/adi_library/axi_ad9671/component.xml
@@ -241,7 +241,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>9d552b9e</spirit:value>
+            <spirit:value>502399df</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -257,7 +257,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>d3400fb9</spirit:value>
+            <spirit:value>07cb76b6</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -892,30 +892,6 @@
       <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
       <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
     </spirit:choice>
-    <spirit:choice>
-      <spirit:name>choice_pairs_00ecfe9a</spirit:name>
-      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
-      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
-      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
-      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
-      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
-      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
-      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
-      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
-      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
-      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
-      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
-      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
-      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
-      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
-      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
-      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
-      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
-      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
-      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
-      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
-      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
-    </spirit:choice>
     <spirit:choice>
       <spirit:name>choice_pairs_19f99f31</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
@@ -941,7 +917,32 @@
       <spirit:enumeration spirit:text="versal">4</spirit:enumeration>
     </spirit:choice>
     <spirit:choice>
-      <spirit:name>choice_pairs_fc01a186</spirit:name>
+      <spirit:name>choice_pairs_a6e6e044</spirit:name>
+      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
+      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
+      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
+      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
+      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
+      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
+      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
+      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
+      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
+      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
+      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
+      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
+      <spirit:enumeration spirit:text="ls">21</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a897e79d</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
       <spirit:enumeration spirit:text="artix">1</spirit:enumeration>
       <spirit:enumeration spirit:text="kintex">2</spirit:enumeration>
@@ -949,6 +950,7 @@
       <spirit:enumeration spirit:text="zynq">4</spirit:enumeration>
       <spirit:enumeration spirit:text="versalprime">5</spirit:enumeration>
       <spirit:enumeration spirit:text="versalaicore">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="versalpremium">7</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
   <spirit:fileSets>
@@ -1029,7 +1031,7 @@
       <spirit:file>
         <spirit:name>axi_ad9671.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_8448a1fc</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_68264b06</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1127,7 +1129,7 @@
     <spirit:parameter>
       <spirit:name>FPGA_FAMILY</spirit:name>
       <spirit:displayName>Fpga Family</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_fc01a186">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_a897e79d">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>SPEED_GRADE</spirit:name>
@@ -1137,7 +1139,7 @@
     <spirit:parameter>
       <spirit:name>DEV_PACKAGE</spirit:name>
       <spirit:displayName>Dev Package</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_00ecfe9a">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_a6e6e044">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>QUAD_OR_DUAL_N</spirit:name>
@@ -1187,11 +1189,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_ad9671</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:42:18Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T02:58:08Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="fcaaa44c"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="d6713915"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="b25aeb89"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ab8069cd"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="cae3341b"/>
diff --git a/adi_library/axi_ad9684/axi_ad9684.v b/adi_library/axi_ad9684/axi_ad9684.v
index ce9ac84a..f084ff19 100644
--- a/adi_library/axi_ad9684/axi_ad9684.v
+++ b/adi_library/axi_ad9684/axi_ad9684.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9684/axi_ad9684.xpr b/adi_library/axi_ad9684/axi_ad9684.xpr
index d885a276..211f5a60 100644
--- a/adi_library/axi_ad9684/axi_ad9684.xpr
+++ b/adi_library/axi_ad9684/axi_ad9684.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ad9684/axi_ad9684.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_ad9684/axi_ad9684.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="80d64ccf9ba3428bb45c8132f00d00a7"/>
+    <Option Name="Id" Val="b69fc401a57e415c95841e91fc2c2bad"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -303,21 +302,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -330,7 +329,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_ad9684/axi_ad9684_channel.v b/adi_library/axi_ad9684/axi_ad9684_channel.v
index c6d87688..23e40a62 100644
--- a/adi_library/axi_ad9684/axi_ad9684_channel.v
+++ b/adi_library/axi_ad9684/axi_ad9684_channel.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9684/axi_ad9684_if.v b/adi_library/axi_ad9684/axi_ad9684_if.v
index 41196807..8ae0eaea 100644
--- a/adi_library/axi_ad9684/axi_ad9684_if.v
+++ b/adi_library/axi_ad9684/axi_ad9684_if.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9684/axi_ad9684_pnmon.v b/adi_library/axi_ad9684/axi_ad9684_pnmon.v
index ba0c5400..45d21f56 100644
--- a/adi_library/axi_ad9684/axi_ad9684_pnmon.v
+++ b/adi_library/axi_ad9684/axi_ad9684_pnmon.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9684/component.xml b/adi_library/axi_ad9684/component.xml
index 24c9c06a..10771049 100644
--- a/adi_library/axi_ad9684/component.xml
+++ b/adi_library/axi_ad9684/component.xml
@@ -327,7 +327,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>67f60fe5</spirit:value>
+            <spirit:value>4c6a53b5</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -343,7 +343,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>738d2417</spirit:value>
+            <spirit:value>4c35e485</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1002,30 +1002,6 @@
       <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
       <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
     </spirit:choice>
-    <spirit:choice>
-      <spirit:name>choice_pairs_00ecfe9a</spirit:name>
-      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
-      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
-      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
-      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
-      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
-      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
-      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
-      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
-      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
-      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
-      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
-      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
-      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
-      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
-      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
-      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
-      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
-      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
-      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
-      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
-      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
-    </spirit:choice>
     <spirit:choice>
       <spirit:name>choice_pairs_19f99f31</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
@@ -1051,7 +1027,32 @@
       <spirit:enumeration spirit:text="versal">4</spirit:enumeration>
     </spirit:choice>
     <spirit:choice>
-      <spirit:name>choice_pairs_fc01a186</spirit:name>
+      <spirit:name>choice_pairs_a6e6e044</spirit:name>
+      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
+      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
+      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
+      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
+      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
+      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
+      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
+      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
+      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
+      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
+      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
+      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
+      <spirit:enumeration spirit:text="ls">21</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a897e79d</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
       <spirit:enumeration spirit:text="artix">1</spirit:enumeration>
       <spirit:enumeration spirit:text="kintex">2</spirit:enumeration>
@@ -1059,6 +1060,7 @@
       <spirit:enumeration spirit:text="zynq">4</spirit:enumeration>
       <spirit:enumeration spirit:text="versalprime">5</spirit:enumeration>
       <spirit:enumeration spirit:text="versalaicore">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="versalpremium">7</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
   <spirit:fileSets>
@@ -1151,7 +1153,7 @@
       <spirit:file>
         <spirit:name>axi_ad9684.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_ee771002</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_2a4b3064</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1257,7 +1259,7 @@
     <spirit:parameter>
       <spirit:name>FPGA_FAMILY</spirit:name>
       <spirit:displayName>Fpga Family</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_fc01a186">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_a897e79d">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>SPEED_GRADE</spirit:name>
@@ -1267,7 +1269,7 @@
     <spirit:parameter>
       <spirit:name>DEV_PACKAGE</spirit:name>
       <spirit:displayName>Dev Package</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_00ecfe9a">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_a6e6e044">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>IODELAY_ENABLE</spirit:name>
@@ -1327,11 +1329,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:42:36Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T02:58:28Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="770a8a47"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="16e8d0a9"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="9c533345"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="78a64a95"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="8562c2b9"/>
diff --git a/adi_library/axi_ad9739a/axi_ad9739a.v b/adi_library/axi_ad9739a/axi_ad9739a.v
index 0036a9d2..ff85f504 100644
--- a/adi_library/axi_ad9739a/axi_ad9739a.v
+++ b/adi_library/axi_ad9739a/axi_ad9739a.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9739a/axi_ad9739a.xpr b/adi_library/axi_ad9739a/axi_ad9739a.xpr
index 57567ed8..f5942777 100644
--- a/adi_library/axi_ad9739a/axi_ad9739a.xpr
+++ b/adi_library/axi_ad9739a/axi_ad9739a.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ad9739a/axi_ad9739a.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_ad9739a/axi_ad9739a.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="809f28805b554cc099a25fae83440b04"/>
+    <Option Name="Id" Val="ce5b01d0393d48039215c586b5a52de5"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -311,21 +310,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -338,7 +337,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_ad9739a/axi_ad9739a_channel.v b/adi_library/axi_ad9739a/axi_ad9739a_channel.v
index 925b942f..ce3cd310 100644
--- a/adi_library/axi_ad9739a/axi_ad9739a_channel.v
+++ b/adi_library/axi_ad9739a/axi_ad9739a_channel.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9739a/axi_ad9739a_core.v b/adi_library/axi_ad9739a/axi_ad9739a_core.v
index 3a31641f..5f7f6f4a 100644
--- a/adi_library/axi_ad9739a/axi_ad9739a_core.v
+++ b/adi_library/axi_ad9739a/axi_ad9739a_core.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9739a/axi_ad9739a_if.v b/adi_library/axi_ad9739a/axi_ad9739a_if.v
index c05c5132..3cc60954 100644
--- a/adi_library/axi_ad9739a/axi_ad9739a_if.v
+++ b/adi_library/axi_ad9739a/axi_ad9739a_if.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9739a/component.xml b/adi_library/axi_ad9739a/component.xml
index 4e21fe12..f13f9357 100644
--- a/adi_library/axi_ad9739a/component.xml
+++ b/adi_library/axi_ad9739a/component.xml
@@ -241,7 +241,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>3ef462ac</spirit:value>
+            <spirit:value>35dc9f6c</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -257,7 +257,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>b3068069</spirit:value>
+            <spirit:value>db6b67f0</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -889,30 +889,6 @@
       <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
       <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
     </spirit:choice>
-    <spirit:choice>
-      <spirit:name>choice_pairs_00ecfe9a</spirit:name>
-      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
-      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
-      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
-      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
-      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
-      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
-      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
-      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
-      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
-      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
-      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
-      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
-      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
-      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
-      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
-      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
-      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
-      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
-      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
-      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
-      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
-    </spirit:choice>
     <spirit:choice>
       <spirit:name>choice_pairs_19f99f31</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
@@ -938,7 +914,32 @@
       <spirit:enumeration spirit:text="versal">4</spirit:enumeration>
     </spirit:choice>
     <spirit:choice>
-      <spirit:name>choice_pairs_fc01a186</spirit:name>
+      <spirit:name>choice_pairs_a6e6e044</spirit:name>
+      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
+      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
+      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
+      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
+      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
+      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
+      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
+      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
+      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
+      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
+      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
+      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
+      <spirit:enumeration spirit:text="ls">21</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a897e79d</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
       <spirit:enumeration spirit:text="artix">1</spirit:enumeration>
       <spirit:enumeration spirit:text="kintex">2</spirit:enumeration>
@@ -946,6 +947,7 @@
       <spirit:enumeration spirit:text="zynq">4</spirit:enumeration>
       <spirit:enumeration spirit:text="versalprime">5</spirit:enumeration>
       <spirit:enumeration spirit:text="versalaicore">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="versalpremium">7</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
   <spirit:fileSets>
@@ -1042,7 +1044,7 @@
       <spirit:file>
         <spirit:name>axi_ad9739a.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_0cc357b1</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_54896544</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1156,7 +1158,7 @@
     <spirit:parameter>
       <spirit:name>FPGA_FAMILY</spirit:name>
       <spirit:displayName>Fpga Family</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_fc01a186">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_a897e79d">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>SPEED_GRADE</spirit:name>
@@ -1166,7 +1168,7 @@
     <spirit:parameter>
       <spirit:name>DEV_PACKAGE</spirit:name>
       <spirit:displayName>Dev Package</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_00ecfe9a">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_a6e6e044">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>SERDES_OR_DDR_N</spirit:name>
@@ -1246,11 +1248,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:42:55Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T02:58:48Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="e11433aa"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="05ae28dc"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="c5eb3dda"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="1ccdd730"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="11e58a02"/>
diff --git a/adi_library/axi_ad9783/axi_ad9783.v b/adi_library/axi_ad9783/axi_ad9783.v
index b11d66dc..ba531de6 100755
--- a/adi_library/axi_ad9783/axi_ad9783.v
+++ b/adi_library/axi_ad9783/axi_ad9783.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9783/axi_ad9783.xpr b/adi_library/axi_ad9783/axi_ad9783.xpr
index ae20dfc4..3389d739 100644
--- a/adi_library/axi_ad9783/axi_ad9783.xpr
+++ b/adi_library/axi_ad9783/axi_ad9783.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ad9783/axi_ad9783.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_ad9783/axi_ad9783.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="2da22fbc4b484875ac33a6e37faf56c8"/>
+    <Option Name="Id" Val="8e5140b522e444b9968482fd27aaef7d"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -311,21 +310,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -338,7 +337,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_ad9783/axi_ad9783_channel.v b/adi_library/axi_ad9783/axi_ad9783_channel.v
index f96a11d2..812c3122 100755
--- a/adi_library/axi_ad9783/axi_ad9783_channel.v
+++ b/adi_library/axi_ad9783/axi_ad9783_channel.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9783/axi_ad9783_core.v b/adi_library/axi_ad9783/axi_ad9783_core.v
index 749c7cb1..a2dab929 100755
--- a/adi_library/axi_ad9783/axi_ad9783_core.v
+++ b/adi_library/axi_ad9783/axi_ad9783_core.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9783/axi_ad9783_if.v b/adi_library/axi_ad9783/axi_ad9783_if.v
index b6385444..21249938 100755
--- a/adi_library/axi_ad9783/axi_ad9783_if.v
+++ b/adi_library/axi_ad9783/axi_ad9783_if.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9783/component.xml b/adi_library/axi_ad9783/component.xml
index 0be16842..2dba29aa 100644
--- a/adi_library/axi_ad9783/component.xml
+++ b/adi_library/axi_ad9783/component.xml
@@ -241,7 +241,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>9bcf1355</spirit:value>
+            <spirit:value>e3752896</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -257,7 +257,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>363a7ee4</spirit:value>
+            <spirit:value>e6389c91</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -883,30 +883,6 @@
       <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
       <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
     </spirit:choice>
-    <spirit:choice>
-      <spirit:name>choice_pairs_00ecfe9a</spirit:name>
-      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
-      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
-      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
-      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
-      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
-      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
-      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
-      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
-      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
-      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
-      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
-      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
-      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
-      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
-      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
-      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
-      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
-      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
-      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
-      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
-      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
-    </spirit:choice>
     <spirit:choice>
       <spirit:name>choice_pairs_19f99f31</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
@@ -932,7 +908,32 @@
       <spirit:enumeration spirit:text="versal">4</spirit:enumeration>
     </spirit:choice>
     <spirit:choice>
-      <spirit:name>choice_pairs_fc01a186</spirit:name>
+      <spirit:name>choice_pairs_a6e6e044</spirit:name>
+      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
+      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
+      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
+      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
+      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
+      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
+      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
+      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
+      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
+      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
+      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
+      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
+      <spirit:enumeration spirit:text="ls">21</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a897e79d</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
       <spirit:enumeration spirit:text="artix">1</spirit:enumeration>
       <spirit:enumeration spirit:text="kintex">2</spirit:enumeration>
@@ -940,6 +941,7 @@
       <spirit:enumeration spirit:text="zynq">4</spirit:enumeration>
       <spirit:enumeration spirit:text="versalprime">5</spirit:enumeration>
       <spirit:enumeration spirit:text="versalaicore">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="versalpremium">7</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
   <spirit:fileSets>
@@ -1036,7 +1038,7 @@
       <spirit:file>
         <spirit:name>axi_ad9783.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_43e249c6</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_e92256d5</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1150,7 +1152,7 @@
     <spirit:parameter>
       <spirit:name>FPGA_FAMILY</spirit:name>
       <spirit:displayName>Fpga Family</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_fc01a186">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_a897e79d">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>SPEED_GRADE</spirit:name>
@@ -1160,7 +1162,7 @@
     <spirit:parameter>
       <spirit:name>DEV_PACKAGE</spirit:name>
       <spirit:displayName>Dev Package</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_00ecfe9a">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_a6e6e044">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>DAC_DDS_TYPE</spirit:name>
@@ -1225,11 +1227,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_ad9783</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:43:14Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T02:59:09Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="096609f5"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="9bba50f4"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="1bb47078"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="c510dbc2"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="c6fe7bba"/>
diff --git a/adi_library/axi_ad9963/axi_ad9963.v b/adi_library/axi_ad9963/axi_ad9963.v
index c1b84551..9f7bd02a 100644
--- a/adi_library/axi_ad9963/axi_ad9963.v
+++ b/adi_library/axi_ad9963/axi_ad9963.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9963/axi_ad9963.xpr b/adi_library/axi_ad9963/axi_ad9963.xpr
index 1f101fd1..278ab4d5 100644
--- a/adi_library/axi_ad9963/axi_ad9963.xpr
+++ b/adi_library/axi_ad9963/axi_ad9963.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ad9963/axi_ad9963.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_ad9963/axi_ad9963.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="320406ba7c9241b7a04f0bbd2e21d0e7"/>
+    <Option Name="Id" Val="563ce312b70e4cefb36ff1e139473824"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -387,21 +386,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -414,7 +413,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_ad9963/axi_ad9963_if.v b/adi_library/axi_ad9963/axi_ad9963_if.v
index de4e4f13..ad9c614e 100644
--- a/adi_library/axi_ad9963/axi_ad9963_if.v
+++ b/adi_library/axi_ad9963/axi_ad9963_if.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -228,8 +228,8 @@ module axi_ad9963_if #(
     .R (dac_rst),
     .S (1'b0),
     .C (dac_clk),
-    .D1 (tx_data_p[l_inst]),
-    .D2 (tx_data_n[l_inst]),
+    .D1 (tx_data_n[l_inst]),
+    .D2 (tx_data_p[l_inst]),
     .Q (tx_data[l_inst]));
     end
   endgenerate
@@ -243,8 +243,8 @@ module axi_ad9963_if #(
     .R (dac_rst),
     .S (1'b0),
     .C (dac_clk),
-    .D1 (1'b1),
-    .D2 (1'b0),
+    .D1 (1'b0),
+    .D2 (1'b1),
     .Q (tx_iq));
 
 endmodule
diff --git a/adi_library/axi_ad9963/axi_ad9963_rx.v b/adi_library/axi_ad9963/axi_ad9963_rx.v
index 3fe3ecb5..eae92074 100644
--- a/adi_library/axi_ad9963/axi_ad9963_rx.v
+++ b/adi_library/axi_ad9963/axi_ad9963_rx.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9963/axi_ad9963_rx_channel.v b/adi_library/axi_ad9963/axi_ad9963_rx_channel.v
index 571056a6..97e7254f 100644
--- a/adi_library/axi_ad9963/axi_ad9963_rx_channel.v
+++ b/adi_library/axi_ad9963/axi_ad9963_rx_channel.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9963/axi_ad9963_rx_pnmon.v b/adi_library/axi_ad9963/axi_ad9963_rx_pnmon.v
index ec2f4063..336d0f15 100644
--- a/adi_library/axi_ad9963/axi_ad9963_rx_pnmon.v
+++ b/adi_library/axi_ad9963/axi_ad9963_rx_pnmon.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9963/axi_ad9963_tx.v b/adi_library/axi_ad9963/axi_ad9963_tx.v
index 0fe50071..b47480a2 100644
--- a/adi_library/axi_ad9963/axi_ad9963_tx.v
+++ b/adi_library/axi_ad9963/axi_ad9963_tx.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9963/axi_ad9963_tx_channel.v b/adi_library/axi_ad9963/axi_ad9963_tx_channel.v
index 4eb549d8..7a28898b 100644
--- a/adi_library/axi_ad9963/axi_ad9963_tx_channel.v
+++ b/adi_library/axi_ad9963/axi_ad9963_tx_channel.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ad9963/component.xml b/adi_library/axi_ad9963/component.xml
index e8102160..08b6286b 100644
--- a/adi_library/axi_ad9963/component.xml
+++ b/adi_library/axi_ad9963/component.xml
@@ -365,7 +365,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>706a8f32</spirit:value>
+            <spirit:value>177cdf67</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -381,7 +381,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>a287393e</spirit:value>
+            <spirit:value>5c7720d9</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1280,30 +1280,6 @@
       <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
       <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
     </spirit:choice>
-    <spirit:choice>
-      <spirit:name>choice_pairs_00ecfe9a</spirit:name>
-      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
-      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
-      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
-      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
-      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
-      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
-      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
-      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
-      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
-      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
-      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
-      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
-      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
-      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
-      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
-      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
-      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
-      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
-      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
-      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
-      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
-    </spirit:choice>
     <spirit:choice>
       <spirit:name>choice_pairs_19f99f31</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
@@ -1329,7 +1305,32 @@
       <spirit:enumeration spirit:text="versal">4</spirit:enumeration>
     </spirit:choice>
     <spirit:choice>
-      <spirit:name>choice_pairs_fc01a186</spirit:name>
+      <spirit:name>choice_pairs_a6e6e044</spirit:name>
+      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
+      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
+      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
+      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
+      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
+      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
+      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
+      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
+      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
+      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
+      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
+      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
+      <spirit:enumeration spirit:text="ls">21</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a897e79d</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
       <spirit:enumeration spirit:text="artix">1</spirit:enumeration>
       <spirit:enumeration spirit:text="kintex">2</spirit:enumeration>
@@ -1337,6 +1338,7 @@
       <spirit:enumeration spirit:text="zynq">4</spirit:enumeration>
       <spirit:enumeration spirit:text="versalprime">5</spirit:enumeration>
       <spirit:enumeration spirit:text="versalaicore">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="versalpremium">7</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
   <spirit:fileSets>
@@ -1477,7 +1479,7 @@
       <spirit:file>
         <spirit:name>axi_ad9963.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_a1f81693</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_0408c636</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1631,7 +1633,7 @@
     <spirit:parameter>
       <spirit:name>FPGA_FAMILY</spirit:name>
       <spirit:displayName>Fpga Family</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_fc01a186">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_a897e79d">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>SPEED_GRADE</spirit:name>
@@ -1641,7 +1643,7 @@
     <spirit:parameter>
       <spirit:name>DEV_PACKAGE</spirit:name>
       <spirit:displayName>Dev Package</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_00ecfe9a">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_a6e6e044">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>ADC_IODELAY_ENABLE</spirit:name>
@@ -1751,11 +1753,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_ad9963</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:43:40Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T02:59:37Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="5579fa8f"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="95eced92"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="fc0a6632"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="97e9c8bc"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="97321609"/>
diff --git a/adi_library/axi_adaq8092/axi_adaq8092.v b/adi_library/axi_adaq8092/axi_adaq8092.v
index 0ee7188f..5abfc77a 100644
--- a/adi_library/axi_adaq8092/axi_adaq8092.v
+++ b/adi_library/axi_adaq8092/axi_adaq8092.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adaq8092/axi_adaq8092.xpr b/adi_library/axi_adaq8092/axi_adaq8092.xpr
index 1a54758d..b9d0c366 100644
--- a/adi_library/axi_adaq8092/axi_adaq8092.xpr
+++ b/adi_library/axi_adaq8092/axi_adaq8092.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_adaq8092/axi_adaq8092.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_adaq8092/axi_adaq8092.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="1d93ffd3d14345e09d1e2572183198a6"/>
+    <Option Name="Id" Val="d1ed179b69e94c5da33e5bbe7007fba6"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -297,21 +296,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -324,7 +323,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_adaq8092/axi_adaq8092_apb_decode.v b/adi_library/axi_adaq8092/axi_adaq8092_apb_decode.v
index cc763c0d..e0db024f 100644
--- a/adi_library/axi_adaq8092/axi_adaq8092_apb_decode.v
+++ b/adi_library/axi_adaq8092/axi_adaq8092_apb_decode.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adaq8092/axi_adaq8092_channel.v b/adi_library/axi_adaq8092/axi_adaq8092_channel.v
index ff3d4940..a9b1d56d 100644
--- a/adi_library/axi_adaq8092/axi_adaq8092_channel.v
+++ b/adi_library/axi_adaq8092/axi_adaq8092_channel.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adaq8092/axi_adaq8092_if.v b/adi_library/axi_adaq8092/axi_adaq8092_if.v
index 17433b50..c6474a67 100644
--- a/adi_library/axi_adaq8092/axi_adaq8092_if.v
+++ b/adi_library/axi_adaq8092/axi_adaq8092_if.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adaq8092/axi_adaq8092_rand_decode.v b/adi_library/axi_adaq8092/axi_adaq8092_rand_decode.v
index e4e11220..2a8909ae 100644
--- a/adi_library/axi_adaq8092/axi_adaq8092_rand_decode.v
+++ b/adi_library/axi_adaq8092/axi_adaq8092_rand_decode.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adaq8092/component.xml b/adi_library/axi_adaq8092/component.xml
index b64f4f10..b2428d4b 100644
--- a/adi_library/axi_adaq8092/component.xml
+++ b/adi_library/axi_adaq8092/component.xml
@@ -333,7 +333,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>bb1a1301</spirit:value>
+            <spirit:value>b8e0c26c</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -349,7 +349,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>e3df1f91</spirit:value>
+            <spirit:value>79ba49a5</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1217,30 +1217,6 @@
       <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
       <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
     </spirit:choice>
-    <spirit:choice>
-      <spirit:name>choice_pairs_00ecfe9a</spirit:name>
-      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
-      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
-      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
-      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
-      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
-      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
-      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
-      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
-      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
-      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
-      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
-      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
-      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
-      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
-      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
-      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
-      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
-      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
-      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
-      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
-      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
-    </spirit:choice>
     <spirit:choice>
       <spirit:name>choice_pairs_092d6e3a</spirit:name>
       <spirit:enumeration spirit:text="LVDS">0</spirit:enumeration>
@@ -1271,7 +1247,32 @@
       <spirit:enumeration spirit:text="versal">4</spirit:enumeration>
     </spirit:choice>
     <spirit:choice>
-      <spirit:name>choice_pairs_fc01a186</spirit:name>
+      <spirit:name>choice_pairs_a6e6e044</spirit:name>
+      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
+      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
+      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
+      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
+      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
+      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
+      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
+      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
+      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
+      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
+      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
+      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
+      <spirit:enumeration spirit:text="ls">21</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a897e79d</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
       <spirit:enumeration spirit:text="artix">1</spirit:enumeration>
       <spirit:enumeration spirit:text="kintex">2</spirit:enumeration>
@@ -1279,6 +1280,7 @@
       <spirit:enumeration spirit:text="zynq">4</spirit:enumeration>
       <spirit:enumeration spirit:text="versalprime">5</spirit:enumeration>
       <spirit:enumeration spirit:text="versalaicore">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="versalpremium">7</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
   <spirit:fileSets>
@@ -1367,7 +1369,7 @@
       <spirit:file>
         <spirit:name>axi_adaq8092.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_4e016119</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_2cad4714</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1480,7 +1482,7 @@
     <spirit:parameter>
       <spirit:name>FPGA_FAMILY</spirit:name>
       <spirit:displayName>Fpga Family</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_fc01a186">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_a897e79d">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>SPEED_GRADE</spirit:name>
@@ -1490,7 +1492,7 @@
     <spirit:parameter>
       <spirit:name>DEV_PACKAGE</spirit:name>
       <spirit:displayName>Dev Package</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_00ecfe9a">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_a6e6e044">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>ADC_DATAPATH_DISABLE</spirit:name>
@@ -1562,11 +1564,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/adaq8092</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:43:58Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T02:59:56Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="b4e5683f"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="372f7429"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="4adac023"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="5e888c95"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="f7bc600c"/>
diff --git a/adi_library/axi_adc_decimate/axi_adc_decimate.v b/adi_library/axi_adc_decimate/axi_adc_decimate.v
index 9c216cb4..9c0e9895 100644
--- a/adi_library/axi_adc_decimate/axi_adc_decimate.v
+++ b/adi_library/axi_adc_decimate/axi_adc_decimate.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adc_decimate/axi_adc_decimate.xpr b/adi_library/axi_adc_decimate/axi_adc_decimate.xpr
index efd6d632..70479a2a 100644
--- a/adi_library/axi_adc_decimate/axi_adc_decimate.xpr
+++ b/adi_library/axi_adc_decimate/axi_adc_decimate.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_adc_decimate/axi_adc_decimate.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_adc_decimate/axi_adc_decimate.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="dffe4107c1e44d6296a3d97c94101e1c"/>
+    <Option Name="Id" Val="4c5545a055c141d1a1d8de06f8f3ff86"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -216,21 +215,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -243,7 +242,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_adc_decimate/axi_adc_decimate_filter.v b/adi_library/axi_adc_decimate/axi_adc_decimate_filter.v
index 4f21caa0..a56adbb7 100644
--- a/adi_library/axi_adc_decimate/axi_adc_decimate_filter.v
+++ b/adi_library/axi_adc_decimate/axi_adc_decimate_filter.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adc_decimate/axi_adc_decimate_reg.v b/adi_library/axi_adc_decimate/axi_adc_decimate_reg.v
index c57cfb55..45f6c191 100644
--- a/adi_library/axi_adc_decimate/axi_adc_decimate_reg.v
+++ b/adi_library/axi_adc_decimate/axi_adc_decimate_reg.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adc_decimate/cic_decim.v b/adi_library/axi_adc_decimate/cic_decim.v
index 13866099..c8853b5a 100644
--- a/adi_library/axi_adc_decimate/cic_decim.v
+++ b/adi_library/axi_adc_decimate/cic_decim.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adc_decimate/component.xml b/adi_library/axi_adc_decimate/component.xml
index 81b172f6..f8db0b7f 100644
--- a/adi_library/axi_adc_decimate/component.xml
+++ b/adi_library/axi_adc_decimate/component.xml
@@ -282,7 +282,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>8aeba977</spirit:value>
+            <spirit:value>eb88bad4</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -301,7 +301,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>5bbf0b8c</spirit:value>
+            <spirit:value>ebd17759</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -906,7 +906,7 @@
       <spirit:file>
         <spirit:name>axi_adc_decimate.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_7d514d91</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_6adb0784</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1036,11 +1036,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_adc_decimate</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:44:17Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:00:16Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="c81c764b"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="cdc38f4a"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="7dbf59e4"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="170edd38"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="f306e57c"/>
diff --git a/adi_library/axi_adc_decimate/fir_decim.v b/adi_library/axi_adc_decimate/fir_decim.v
index 7da46732..365c1a87 100644
--- a/adi_library/axi_adc_decimate/fir_decim.v
+++ b/adi_library/axi_adc_decimate/fir_decim.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adc_trigger/axi_adc_trigger.v b/adi_library/axi_adc_trigger/axi_adc_trigger.v
index 6d7274a0..0032e326 100644
--- a/adi_library/axi_adc_trigger/axi_adc_trigger.v
+++ b/adi_library/axi_adc_trigger/axi_adc_trigger.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adc_trigger/axi_adc_trigger.xpr b/adi_library/axi_adc_trigger/axi_adc_trigger.xpr
index dafb3285..f1451bc5 100644
--- a/adi_library/axi_adc_trigger/axi_adc_trigger.xpr
+++ b/adi_library/axi_adc_trigger/axi_adc_trigger.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_adc_trigger/axi_adc_trigger.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_adc_trigger/axi_adc_trigger.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="0080cdaaeb514c3ca1ef45e96eccf1c2"/>
+    <Option Name="Id" Val="fd6ace83aae944d2a91f82c743d32e19"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -187,21 +186,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -214,7 +213,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_adc_trigger/axi_adc_trigger_reg.v b/adi_library/axi_adc_trigger/axi_adc_trigger_reg.v
index a6fae39b..e1c6627c 100644
--- a/adi_library/axi_adc_trigger/axi_adc_trigger_reg.v
+++ b/adi_library/axi_adc_trigger/axi_adc_trigger_reg.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adc_trigger/component.xml b/adi_library/axi_adc_trigger/component.xml
index fcdb4ad8..a670f8b1 100644
--- a/adi_library/axi_adc_trigger/component.xml
+++ b/adi_library/axi_adc_trigger/component.xml
@@ -279,7 +279,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>d3f469cd</spirit:value>
+            <spirit:value>c8a3f62b</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -295,7 +295,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>1b9bccd7</spirit:value>
+            <spirit:value>bf1d3cce</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -957,7 +957,7 @@
       <spirit:file>
         <spirit:name>axi_adc_trigger.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_89ec07dc</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_53bfec37</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1044,11 +1044,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_adc_trigger</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:44:26Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:00:26Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="5475a3bf"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4dde3cce"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="2bf6cbe4"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="64135b49"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="fc5222a7"/>
diff --git a/adi_library/axi_adrv9001/adrv9001_aligner4.v b/adi_library/axi_adrv9001/adrv9001_aligner4.v
index 3d43f57a..4a4bc27f 100644
--- a/adi_library/axi_adrv9001/adrv9001_aligner4.v
+++ b/adi_library/axi_adrv9001/adrv9001_aligner4.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adrv9001/adrv9001_aligner8.v b/adi_library/axi_adrv9001/adrv9001_aligner8.v
index e4f41524..0240bf03 100644
--- a/adi_library/axi_adrv9001/adrv9001_aligner8.v
+++ b/adi_library/axi_adrv9001/adrv9001_aligner8.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adrv9001/adrv9001_pack.v b/adi_library/axi_adrv9001/adrv9001_pack.v
index 659c5e8e..65879ef8 100644
--- a/adi_library/axi_adrv9001/adrv9001_pack.v
+++ b/adi_library/axi_adrv9001/adrv9001_pack.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adrv9001/adrv9001_rx.v b/adi_library/axi_adrv9001/adrv9001_rx.v
index 7f9dc3f1..2705e8d5 100644
--- a/adi_library/axi_adrv9001/adrv9001_rx.v
+++ b/adi_library/axi_adrv9001/adrv9001_rx.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adrv9001/adrv9001_rx_link.v b/adi_library/axi_adrv9001/adrv9001_rx_link.v
index 467d5631..c6b89a86 100644
--- a/adi_library/axi_adrv9001/adrv9001_rx_link.v
+++ b/adi_library/axi_adrv9001/adrv9001_rx_link.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adrv9001/adrv9001_tx.v b/adi_library/axi_adrv9001/adrv9001_tx.v
index 602fc1ea..88a3194e 100644
--- a/adi_library/axi_adrv9001/adrv9001_tx.v
+++ b/adi_library/axi_adrv9001/adrv9001_tx.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adrv9001/adrv9001_tx_link.v b/adi_library/axi_adrv9001/adrv9001_tx_link.v
index d8882c12..c9923a69 100644
--- a/adi_library/axi_adrv9001/adrv9001_tx_link.v
+++ b/adi_library/axi_adrv9001/adrv9001_tx_link.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adrv9001/axi_adrv9001.v b/adi_library/axi_adrv9001/axi_adrv9001.v
index cdacf6c6..c605f742 100644
--- a/adi_library/axi_adrv9001/axi_adrv9001.v
+++ b/adi_library/axi_adrv9001/axi_adrv9001.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adrv9001/axi_adrv9001.xpr b/adi_library/axi_adrv9001/axi_adrv9001.xpr
index 9b597988..4b7ddb52 100644
--- a/adi_library/axi_adrv9001/axi_adrv9001.xpr
+++ b/adi_library/axi_adrv9001/axi_adrv9001.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_adrv9001/axi_adrv9001.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_adrv9001/axi_adrv9001.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="808014e87be8440e8d015998af274db3"/>
+    <Option Name="Id" Val="05fb0db0169348c8ba30a603f0f102ea"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -480,21 +479,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -507,7 +506,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_adrv9001/axi_adrv9001_core.v b/adi_library/axi_adrv9001/axi_adrv9001_core.v
index 279aac59..614df415 100644
--- a/adi_library/axi_adrv9001/axi_adrv9001_core.v
+++ b/adi_library/axi_adrv9001/axi_adrv9001_core.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adrv9001/axi_adrv9001_if.v b/adi_library/axi_adrv9001/axi_adrv9001_if.v
index bfe46777..23fc591e 100644
--- a/adi_library/axi_adrv9001/axi_adrv9001_if.v
+++ b/adi_library/axi_adrv9001/axi_adrv9001_if.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adrv9001/axi_adrv9001_rx.v b/adi_library/axi_adrv9001/axi_adrv9001_rx.v
index 68b4dc90..b816eaf4 100644
--- a/adi_library/axi_adrv9001/axi_adrv9001_rx.v
+++ b/adi_library/axi_adrv9001/axi_adrv9001_rx.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adrv9001/axi_adrv9001_rx_channel.v b/adi_library/axi_adrv9001/axi_adrv9001_rx_channel.v
index e8abe201..ea333df3 100644
--- a/adi_library/axi_adrv9001/axi_adrv9001_rx_channel.v
+++ b/adi_library/axi_adrv9001/axi_adrv9001_rx_channel.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adrv9001/axi_adrv9001_tdd.v b/adi_library/axi_adrv9001/axi_adrv9001_tdd.v
index 55685098..35a88c8a 100644
--- a/adi_library/axi_adrv9001/axi_adrv9001_tdd.v
+++ b/adi_library/axi_adrv9001/axi_adrv9001_tdd.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adrv9001/axi_adrv9001_tx.v b/adi_library/axi_adrv9001/axi_adrv9001_tx.v
index 00b337fe..12618f45 100644
--- a/adi_library/axi_adrv9001/axi_adrv9001_tx.v
+++ b/adi_library/axi_adrv9001/axi_adrv9001_tx.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adrv9001/axi_adrv9001_tx_channel.v b/adi_library/axi_adrv9001/axi_adrv9001_tx_channel.v
index b23a148e..80c3376a 100644
--- a/adi_library/axi_adrv9001/axi_adrv9001_tx_channel.v
+++ b/adi_library/axi_adrv9001/axi_adrv9001_tx_channel.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adrv9001/component.xml b/adi_library/axi_adrv9001/component.xml
index d2bf9f65..504e4a7c 100644
--- a/adi_library/axi_adrv9001/component.xml
+++ b/adi_library/axi_adrv9001/component.xml
@@ -436,7 +436,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>e336bf6f</spirit:value>
+            <spirit:value>cb9e5853</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -455,7 +455,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>4b659020</spirit:value>
+            <spirit:value>f220243d</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -2608,30 +2608,6 @@
       <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
       <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
     </spirit:choice>
-    <spirit:choice>
-      <spirit:name>choice_pairs_00ecfe9a</spirit:name>
-      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
-      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
-      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
-      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
-      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
-      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
-      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
-      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
-      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
-      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
-      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
-      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
-      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
-      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
-      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
-      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
-      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
-      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
-      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
-      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
-      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
-    </spirit:choice>
     <spirit:choice>
       <spirit:name>choice_pairs_19f99f31</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
@@ -2657,7 +2633,32 @@
       <spirit:enumeration spirit:text="versal">4</spirit:enumeration>
     </spirit:choice>
     <spirit:choice>
-      <spirit:name>choice_pairs_fc01a186</spirit:name>
+      <spirit:name>choice_pairs_a6e6e044</spirit:name>
+      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
+      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
+      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
+      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
+      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
+      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
+      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
+      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
+      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
+      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
+      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
+      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
+      <spirit:enumeration spirit:text="ls">21</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a897e79d</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
       <spirit:enumeration spirit:text="artix">1</spirit:enumeration>
       <spirit:enumeration spirit:text="kintex">2</spirit:enumeration>
@@ -2665,6 +2666,7 @@
       <spirit:enumeration spirit:text="zynq">4</spirit:enumeration>
       <spirit:enumeration spirit:text="versalprime">5</spirit:enumeration>
       <spirit:enumeration spirit:text="versalaicore">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="versalpremium">7</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
   <spirit:fileSets>
@@ -2849,7 +2851,7 @@
       <spirit:file>
         <spirit:name>axi_adrv9001.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_3a205996</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_bbc86102</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -3143,7 +3145,7 @@
     <spirit:parameter>
       <spirit:name>FPGA_FAMILY</spirit:name>
       <spirit:displayName>Fpga Family</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_fc01a186">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_a897e79d">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>SPEED_GRADE</spirit:name>
@@ -3153,7 +3155,7 @@
     <spirit:parameter>
       <spirit:name>DEV_PACKAGE</spirit:name>
       <spirit:displayName>Dev Package</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_00ecfe9a">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_a6e6e044">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>EXT_SYNC</spirit:name>
@@ -3211,11 +3213,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:45:00Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:01:04Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="c3c5a312"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="34361d54"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="8e0b1332"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="763f2ed9"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="0824b41b"/>
diff --git a/adi_library/axi_adrv9001/intel/adrv9001_rx.v b/adi_library/axi_adrv9001/intel/adrv9001_rx.v
index 8b01f1e4..00db3399 100644
--- a/adi_library/axi_adrv9001/intel/adrv9001_rx.v
+++ b/adi_library/axi_adrv9001/intel/adrv9001_rx.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_adrv9001/intel/adrv9001_tx.v b/adi_library/axi_adrv9001/intel/adrv9001_tx.v
index 0f466352..c5cf4c52 100644
--- a/adi_library/axi_adrv9001/intel/adrv9001_tx.v
+++ b/adi_library/axi_adrv9001/intel/adrv9001_tx.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_clkgen/axi_clkgen.v b/adi_library/axi_clkgen/axi_clkgen.v
index 80dc440f..a1301536 100644
--- a/adi_library/axi_clkgen/axi_clkgen.v
+++ b/adi_library/axi_clkgen/axi_clkgen.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_clkgen/axi_clkgen.xpr b/adi_library/axi_clkgen/axi_clkgen.xpr
index 1a213ce4..55b1709f 100644
--- a/adi_library/axi_clkgen/axi_clkgen.xpr
+++ b/adi_library/axi_clkgen/axi_clkgen.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_clkgen/axi_clkgen.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_clkgen/axi_clkgen.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="26e82b0ffa23468db83dd550853d79e4"/>
+    <Option Name="Id" Val="d88e549810fd428eb5cef5d0d84da930"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -196,21 +195,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -223,7 +222,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_clkgen/component.xml b/adi_library/axi_clkgen/component.xml
index 265aa1e5..50da35cf 100644
--- a/adi_library/axi_clkgen/component.xml
+++ b/adi_library/axi_clkgen/component.xml
@@ -305,7 +305,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>4fffa083</spirit:value>
+            <spirit:value>a880863a</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -321,7 +321,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>4fffa083</spirit:value>
+            <spirit:value>a880863a</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -874,30 +874,6 @@
       <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
       <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
     </spirit:choice>
-    <spirit:choice>
-      <spirit:name>choice_pairs_00ecfe9a</spirit:name>
-      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
-      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
-      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
-      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
-      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
-      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
-      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
-      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
-      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
-      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
-      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
-      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
-      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
-      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
-      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
-      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
-      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
-      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
-      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
-      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
-      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
-    </spirit:choice>
     <spirit:choice>
       <spirit:name>choice_pairs_19f99f31</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
@@ -923,7 +899,32 @@
       <spirit:enumeration spirit:text="versal">4</spirit:enumeration>
     </spirit:choice>
     <spirit:choice>
-      <spirit:name>choice_pairs_fc01a186</spirit:name>
+      <spirit:name>choice_pairs_a6e6e044</spirit:name>
+      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
+      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
+      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
+      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
+      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
+      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
+      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
+      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
+      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
+      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
+      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
+      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
+      <spirit:enumeration spirit:text="ls">21</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a897e79d</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
       <spirit:enumeration spirit:text="artix">1</spirit:enumeration>
       <spirit:enumeration spirit:text="kintex">2</spirit:enumeration>
@@ -931,6 +932,7 @@
       <spirit:enumeration spirit:text="zynq">4</spirit:enumeration>
       <spirit:enumeration spirit:text="versalprime">5</spirit:enumeration>
       <spirit:enumeration spirit:text="versalaicore">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="versalpremium">7</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
   <spirit:fileSets>
@@ -963,7 +965,7 @@
       <spirit:file>
         <spirit:name>axi_clkgen.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_bfbf5736</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_69c7578b</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1036,7 +1038,7 @@
     <spirit:parameter>
       <spirit:name>FPGA_FAMILY</spirit:name>
       <spirit:displayName>Fpga Family</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_fc01a186">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_a897e79d">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>SPEED_GRADE</spirit:name>
@@ -1046,7 +1048,7 @@
     <spirit:parameter>
       <spirit:name>DEV_PACKAGE</spirit:name>
       <spirit:displayName>Dev Package</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_00ecfe9a">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_a6e6e044">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>FPGA_VOLTAGE</spirit:name>
@@ -1148,11 +1150,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_clkgen</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:45:11Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:01:15Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="5f93c149"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="7b5f4507"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="6d5ca090"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="74e5f4d9"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="a9399c09"/>
diff --git a/adi_library/axi_clock_monitor/axi_clock_monitor.v b/adi_library/axi_clock_monitor/axi_clock_monitor.v
index 2128cc06..026a4768 100755
--- a/adi_library/axi_clock_monitor/axi_clock_monitor.v
+++ b/adi_library/axi_clock_monitor/axi_clock_monitor.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -112,11 +112,9 @@ module axi_clock_monitor #(
   wire         clock         [0:15];
   wire [20:0]  clk_mon_count [0:15];
 
-  wire         up_wreq_i_s;
   wire [13:0]  up_waddr_i_s;
   wire [31:0]  up_wdata_i_s;
   wire         up_wack_o_s;
-  wire         up_rreq_i_s;
   wire [13:0]  up_raddr_i_s;
   wire [31:0]  up_rdata_o_s;
   wire         up_rack_o_s;
@@ -148,11 +146,6 @@ module axi_clock_monitor #(
   assign up_rstn = s_axi_aresetn;
   assign reset = up_reset_core;
 
-  // decode block select
-
-  assign up_wreq_s = (up_waddr_i_s[13:8] == ID) ? up_wreq_i_s : 1'b0;
-  assign up_rreq_s = (up_raddr_i_s[13:8] == ID) ? up_rreq_i_s : 1'b0;
-
   // processor write interface
 
   assign up_wack_o_s = up_wack_int;
@@ -184,32 +177,32 @@ module axi_clock_monitor #(
     end else begin
       up_rack_int <= up_rreq_s;
       if (up_rreq_s == 1'b1) begin
-        case (up_raddr_i_s)
+        case (up_raddr_i_s[4:0])
           /* Standard registers */
-          14'h000: up_rdata_int <= PCORE_VERSION;
-          14'h001: up_rdata_int <= ID;
+          5'h00: up_rdata_int <= PCORE_VERSION;
+          5'h01: up_rdata_int <= ID;
 
           /* Core configuration */
-          14'h003: up_rdata_int <= NUM_OF_CLOCKS;
-          14'h004: up_rdata_int <= {31'h00, up_reset_core};
+          5'h03: up_rdata_int <= NUM_OF_CLOCKS;
+          5'h04: up_rdata_int <= {31'h00, up_reset_core};
 
           /* Clock ratios registers*/
-          14'h010: up_rdata_int <= {11'h00, clk_mon_count[ 0]};
-          14'h011: up_rdata_int <= {11'h00, clk_mon_count[ 1]};
-          14'h012: up_rdata_int <= {11'h00, clk_mon_count[ 2]};
-          14'h013: up_rdata_int <= {11'h00, clk_mon_count[ 3]};
-          14'h014: up_rdata_int <= {11'h00, clk_mon_count[ 4]};
-          14'h015: up_rdata_int <= {11'h00, clk_mon_count[ 5]};
-          14'h016: up_rdata_int <= {11'h00, clk_mon_count[ 6]};
-          14'h017: up_rdata_int <= {11'h00, clk_mon_count[ 7]};
-          14'h018: up_rdata_int <= {11'h00, clk_mon_count[ 8]};
-          14'h019: up_rdata_int <= {11'h00, clk_mon_count[ 9]};
-          14'h01a: up_rdata_int <= {11'h00, clk_mon_count[10]};
-          14'h01b: up_rdata_int <= {11'h00, clk_mon_count[11]};
-          14'h01c: up_rdata_int <= {11'h00, clk_mon_count[12]};
-          14'h01d: up_rdata_int <= {11'h00, clk_mon_count[13]};
-          14'h01e: up_rdata_int <= {11'h00, clk_mon_count[14]};
-          14'h01f: up_rdata_int <= {11'h00, clk_mon_count[15]};
+          5'h10: up_rdata_int <= {11'h00, clk_mon_count[ 0]};
+          5'h11: up_rdata_int <= {11'h00, clk_mon_count[ 1]};
+          5'h12: up_rdata_int <= {11'h00, clk_mon_count[ 2]};
+          5'h13: up_rdata_int <= {11'h00, clk_mon_count[ 3]};
+          5'h14: up_rdata_int <= {11'h00, clk_mon_count[ 4]};
+          5'h15: up_rdata_int <= {11'h00, clk_mon_count[ 5]};
+          5'h16: up_rdata_int <= {11'h00, clk_mon_count[ 6]};
+          5'h17: up_rdata_int <= {11'h00, clk_mon_count[ 7]};
+          5'h18: up_rdata_int <= {11'h00, clk_mon_count[ 8]};
+          5'h19: up_rdata_int <= {11'h00, clk_mon_count[ 9]};
+          5'h1a: up_rdata_int <= {11'h00, clk_mon_count[10]};
+          5'h1b: up_rdata_int <= {11'h00, clk_mon_count[11]};
+          5'h1c: up_rdata_int <= {11'h00, clk_mon_count[12]};
+          5'h1d: up_rdata_int <= {11'h00, clk_mon_count[13]};
+          5'h1e: up_rdata_int <= {11'h00, clk_mon_count[14]};
+          5'h1f: up_rdata_int <= {11'h00, clk_mon_count[15]};
 
           default: up_rdata_int <= 'h00;
         endcase
@@ -257,11 +250,11 @@ module axi_clock_monitor #(
     .up_axi_rresp (s_axi_rresp),
     .up_axi_rdata (s_axi_rdata),
     .up_axi_rready (s_axi_rready),
-    .up_wreq (up_wreq_i_s),
+    .up_wreq (up_wreq_s),
     .up_waddr (up_waddr_i_s),
     .up_wdata (up_wdata_i_s),
     .up_wack (up_wack_o_s),
-    .up_rreq (up_rreq_i_s),
+    .up_rreq (up_rreq_s),
     .up_raddr (up_raddr_i_s),
     .up_rdata (up_rdata_o_s),
     .up_rack (up_rack_o_s));
diff --git a/adi_library/axi_clock_monitor/axi_clock_monitor.xpr b/adi_library/axi_clock_monitor/axi_clock_monitor.xpr
index 930cf0c4..9123b273 100644
--- a/adi_library/axi_clock_monitor/axi_clock_monitor.xpr
+++ b/adi_library/axi_clock_monitor/axi_clock_monitor.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_clock_monitor/axi_clock_monitor.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_clock_monitor/axi_clock_monitor.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="697ae42879c74323ae18ea01dab35596"/>
+    <Option Name="Id" Val="421f2aaaf4104f74967bdf5a42647752"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -174,21 +173,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -201,7 +200,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_clock_monitor/component.xml b/adi_library/axi_clock_monitor/component.xml
index 25f4a23c..08e8229c 100644
--- a/adi_library/axi_clock_monitor/component.xml
+++ b/adi_library/axi_clock_monitor/component.xml
@@ -257,7 +257,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>17b5e71c</spirit:value>
+            <spirit:value>c0944db9</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -273,7 +273,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>b0e420e2</spirit:value>
+            <spirit:value>b16a94ea</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1000,7 +1000,7 @@
       <spirit:file>
         <spirit:name>axi_clock_monitor.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_3b1ac4a2</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_7a2faf0d</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1083,11 +1083,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_clock_monitor</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:45:20Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:01:25Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="c6e366c8"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="1e4179a7"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="164310c9"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="e8384fdb"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="ce8ad7eb"/>
diff --git a/adi_library/axi_dac_interpolate/axi_dac_interpolate.v b/adi_library/axi_dac_interpolate/axi_dac_interpolate.v
index 238d0e01..9fd4d34a 100644
--- a/adi_library/axi_dac_interpolate/axi_dac_interpolate.v
+++ b/adi_library/axi_dac_interpolate/axi_dac_interpolate.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dac_interpolate/axi_dac_interpolate.xpr b/adi_library/axi_dac_interpolate/axi_dac_interpolate.xpr
index e323f8c7..7d1ee7ac 100644
--- a/adi_library/axi_dac_interpolate/axi_dac_interpolate.xpr
+++ b/adi_library/axi_dac_interpolate/axi_dac_interpolate.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_dac_interpolate/axi_dac_interpolate.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_dac_interpolate/axi_dac_interpolate.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="310465cb0190479ca3545deb6a343657"/>
+    <Option Name="Id" Val="874162bf58574f43b22ce4ce8eca6d36"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -222,21 +221,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -249,7 +248,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_dac_interpolate/axi_dac_interpolate_filter.v b/adi_library/axi_dac_interpolate/axi_dac_interpolate_filter.v
index de4148bd..9a20618f 100644
--- a/adi_library/axi_dac_interpolate/axi_dac_interpolate_filter.v
+++ b/adi_library/axi_dac_interpolate/axi_dac_interpolate_filter.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -85,12 +85,10 @@ module axi_dac_interpolate_filter #(
   reg               cic_change_rate;
   reg     [31:0]    interpolation_counter;
 
-  reg               dma_data_valid = 1'b0;
-  reg               dma_data_valid_adjacent = 1'b0;
-
   reg               filter_enable = 1'b0;
   reg     [15:0]    dma_valid_m = 16'd0;
   reg               stop_transfer = 1'd0;
+  reg               clear_stop_flag = 1'd0;
 
   reg               transfer = 1'd0;
   reg     [ 1:0]    transfer_sm = 2'd0;
@@ -196,11 +194,12 @@ module axi_dac_interpolate_filter #(
   assign transfer_ready =  start_sync_channels ?
                              dma_valid & dma_valid_adjacent :
                              dma_valid;
-  assign transfer_start = !(en_start_trigger ^ trigger) & transfer_ready;
+  assign transfer_start = !(en_start_trigger ^ trigger) &
+                          transfer_ready & !dma_transfer_suspend;
 
   always @(posedge dac_clk) begin
     stop_transfer <= transfer_sm == IDLE ? 1'b0 :
-                     stop_transfer |
+                     (stop_transfer & !clear_stop_flag) |
                      dma_transfer_suspend |
                      (en_stop_trigger & trigger) |
                      (sync_stop_channels & dma_valid & dma_valid_adjacent);
@@ -211,17 +210,19 @@ module axi_dac_interpolate_filter #(
     case (transfer_sm)
       IDLE: begin
         transfer <= 1'b0;
-        if (dac_int_ready) begin
+        if (dac_int_ready & !dma_transfer_suspend) begin
           transfer_sm_next <= WAIT;
         end
       end
       WAIT: begin
         transfer <= 1'b0;
         if (transfer_start) begin
+          clear_stop_flag <= 1'b1;
           transfer_sm_next <= TRANSFER;
         end
       end
       TRANSFER: begin
+        clear_stop_flag <= 1'b0;
         transfer <= 1'b1;
         if (stop_transfer) begin
           if (flush_dma_in) begin
diff --git a/adi_library/axi_dac_interpolate/axi_dac_interpolate_reg.v b/adi_library/axi_dac_interpolate/axi_dac_interpolate_reg.v
index 512f9b00..65477973 100644
--- a/adi_library/axi_dac_interpolate/axi_dac_interpolate_reg.v
+++ b/adi_library/axi_dac_interpolate/axi_dac_interpolate_reg.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -72,7 +72,7 @@ module axi_dac_interpolate_reg(
   // internal registers
 
   reg     [31:0]  up_version = {16'h0002,     /* MAJOR */
-                                 8'h03,       /* MINOR */
+                                 8'h04,       /* MINOR */
                                  8'h00};      /* PATCH */
   reg     [31:0]  up_scratch = 32'h0;
 
diff --git a/adi_library/axi_dac_interpolate/component.xml b/adi_library/axi_dac_interpolate/component.xml
index 73375eab..d2dd8387 100644
--- a/adi_library/axi_dac_interpolate/component.xml
+++ b/adi_library/axi_dac_interpolate/component.xml
@@ -279,7 +279,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>5150ad67</spirit:value>
+            <spirit:value>ccc66952</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -295,7 +295,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>1edce4b6</spirit:value>
+            <spirit:value>68c323f6</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1005,7 +1005,7 @@
       <spirit:file>
         <spirit:name>axi_dac_interpolate.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_c33a1894</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_a7ae538e</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1107,11 +1107,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_dac_interpolate</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:45:32Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:01:38Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="431187fa"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="3a2db16c"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="2518ea2b"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="170edd38"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="f71969a3"/>
diff --git a/adi_library/axi_dmac/address_generator.v b/adi_library/axi_dmac/address_generator.v
index 8a8d7035..01d2801b 100644
--- a/adi_library/axi_dmac/address_generator.v
+++ b/adi_library/axi_dmac/address_generator.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -43,7 +43,8 @@ module address_generator #(
   parameter BEATS_PER_BURST_WIDTH = 4,
   parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8),
   parameter LENGTH_WIDTH = 8,
-  parameter CACHE_COHERENT = 0
+  parameter [3:0] AXI_AXCACHE = 4'b0011,
+  parameter [2:0] AXI_AXPROT = 3'b000
 ) (
   input                        clk,
   input                        resetn,
@@ -80,10 +81,8 @@ module address_generator #(
 `include "inc_id.vh"
 
   assign burst = 2'b01;
-  assign prot = 3'b000;
-  // If CACHE_COHERENT is set, signal downstream that this transaction must be
-  // looked up in cache. Otherwise default to "normal non-cachable bufferable".
-  assign cache = CACHE_COHERENT ? 4'b1110 : 4'b0011;
+  assign prot = AXI_AXPROT;
+  assign cache = AXI_AXCACHE;
   assign size = DMA_DATA_WIDTH == 1024 ? 3'b111 :
                 DMA_DATA_WIDTH ==  512 ? 3'b110 :
                 DMA_DATA_WIDTH ==  256 ? 3'b101 :
diff --git a/adi_library/axi_dmac/axi_dmac.v b/adi_library/axi_dmac/axi_dmac.v
index f78316f2..867650af 100644
--- a/adi_library/axi_dmac/axi_dmac.v
+++ b/adi_library/axi_dmac/axi_dmac.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -70,7 +70,9 @@ module axi_dmac #(
   parameter DISABLE_DEBUG_REGISTERS = 0,
   parameter ENABLE_DIAGNOSTICS_IF = 0,
   parameter ALLOW_ASYM_MEM = 0,
-  parameter CACHE_COHERENT_DEST = 0
+  parameter CACHE_COHERENT = 0,
+  parameter [3:0] AXI_AXCACHE = 4'b0011,
+  parameter [2:0] AXI_AXPROT = 3'b000
 ) (
 
   // Slave AXI interface
@@ -447,7 +449,9 @@ module axi_dmac #(
     .DMA_2D_TRANSFER(DMA_2D_TRANSFER),
     .DMA_SG_TRANSFER(DMA_SG_TRANSFER),
     .SYNC_TRANSFER_START(SYNC_TRANSFER_START),
-    .CACHE_COHERENT_DEST(CACHE_COHERENT_DEST)
+    .CACHE_COHERENT(CACHE_COHERENT),
+    .AXI_AXCACHE(AXI_AXCACHE),
+    .AXI_AXPROT(AXI_AXPROT)
   ) i_regmap (
     .s_axi_aclk(s_axi_aclk),
     .s_axi_aresetn(s_axi_aresetn),
@@ -537,7 +541,8 @@ module axi_dmac #(
     .AXI_LENGTH_WIDTH_SG(8-(4*DMA_AXI_PROTOCOL_SG)),
     .ENABLE_DIAGNOSTICS_IF(ENABLE_DIAGNOSTICS_IF),
     .ALLOW_ASYM_MEM(ALLOW_ASYM_MEM),
-    .CACHE_COHERENT_DEST(CACHE_COHERENT_DEST)
+    .AXI_AXCACHE(AXI_AXCACHE),
+    .AXI_AXPROT(AXI_AXPROT)
   ) i_transfer (
     .ctrl_clk(s_axi_aclk),
     .ctrl_resetn(s_axi_aresetn),
diff --git a/adi_library/axi_dmac/axi_dmac.xpr b/adi_library/axi_dmac/axi_dmac.xpr
index 3d6e5351..7f53c11e 100644
--- a/adi_library/axi_dmac/axi_dmac.xpr
+++ b/adi_library/axi_dmac/axi_dmac.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_dmac/axi_dmac.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_dmac/axi_dmac.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="9452152444d94dd49704b10ff32911da"/>
+    <Option Name="Id" Val="3e1cb6fd4c2b4f769f8b27662b0ad072"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -359,21 +358,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -386,7 +385,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_dmac/axi_dmac_burst_memory.v b/adi_library/axi_dmac/axi_dmac_burst_memory.v
index 5e0123b1..f8ac3791 100644
--- a/adi_library/axi_dmac/axi_dmac_burst_memory.v
+++ b/adi_library/axi_dmac/axi_dmac_burst_memory.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/axi_dmac_hw.tcl b/adi_library/axi_dmac/axi_dmac_hw.tcl
index b8bde93a..30bec0b1 100644
--- a/adi_library/axi_dmac/axi_dmac_hw.tcl
+++ b/adi_library/axi_dmac/axi_dmac_hw.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -92,6 +92,46 @@ set_parameter_property DMA_AXI_ADDR_WIDTH HDL_PARAMETER true
 set_parameter_property DMA_AXI_ADDR_WIDTH ALLOWED_RANGES {16:64}
 set_parameter_property DMA_AXI_ADDR_WIDTH GROUP $group
 
+add_parameter AXI_AXCACHE_AUTO BOOLEAN 1
+set_parameter_property AXI_AXCACHE_AUTO DISPLAY_NAME "ARCACHE/AWCACHE Automatically Set"
+set_parameter_property AXI_AXCACHE_AUTO HDL_PARAMETER false
+set_parameter_property AXI_AXCACHE_AUTO GROUP $group
+
+add_parameter AXI_AXPROT_AUTO BOOLEAN 1
+set_parameter_property AXI_AXPROT_AUTO DISPLAY_NAME "ARPROT/AWPROT Automatically Set"
+set_parameter_property AXI_AXPROT_AUTO HDL_PARAMETER false
+set_parameter_property AXI_AXPROT_AUTO GROUP $group
+
+add_parameter AXI_AXCACHE_MANUAL STD_LOGIC_VECTOR
+set_parameter_property AXI_AXCACHE_MANUAL WIDTH 4
+set_parameter_property AXI_AXCACHE_MANUAL DISPLAY_NAME "ARCACHE/AWCACHE"
+set_parameter_property AXI_AXCACHE_MANUAL HDL_PARAMETER false
+set_parameter_property AXI_AXCACHE_MANUAL ALLOWED_RANGES {0x0:0xF}
+set_parameter_property AXI_AXCACHE_MANUAL GROUP $group
+
+add_parameter AXI_AXPROT_MANUAL STD_LOGIC_VECTOR
+set_parameter_property AXI_AXPROT_MANUAL WIDTH 3
+set_parameter_property AXI_AXPROT_MANUAL DISPLAY_NAME "ARPROT/AWPROT"
+set_parameter_property AXI_AXPROT_MANUAL HDL_PARAMETER false
+set_parameter_property AXI_AXPROT_MANUAL ALLOWED_RANGES {0x0:0x7}
+set_parameter_property AXI_AXPROT_MANUAL GROUP $group
+
+add_parameter AXI_AXCACHE STD_LOGIC_VECTOR
+set_parameter_property AXI_AXCACHE WIDTH 4
+set_parameter_property AXI_AXCACHE DISPLAY_NAME "ARCACHE/AWCACHE"
+set_parameter_property AXI_AXCACHE HDL_PARAMETER true
+set_parameter_property AXI_AXCACHE ALLOWED_RANGES {0x0:0xF}
+set_parameter_property AXI_AXCACHE DERIVED true
+set_parameter_property AXI_AXCACHE GROUP $group
+
+add_parameter AXI_AXPROT STD_LOGIC_VECTOR
+set_parameter_property AXI_AXPROT WIDTH 3
+set_parameter_property AXI_AXPROT DISPLAY_NAME "ARPROT/AWPROT"
+set_parameter_property AXI_AXPROT HDL_PARAMETER true
+set_parameter_property AXI_AXPROT ALLOWED_RANGES {0x0:0x7}
+set_parameter_property AXI_AXPROT DERIVED true
+set_parameter_property AXI_AXPROT GROUP $group
+
 foreach {suffix group} { \
     "SRC" "Source" \
     "DEST" "Destination" \
@@ -153,24 +193,31 @@ set_parameter_property CYCLIC DISPLAY_HINT boolean
 set_parameter_property CYCLIC HDL_PARAMETER true
 set_parameter_property CYCLIC GROUP $group
 
-add_parameter DMA_2D_TRANSFER INTEGER 0
-set_parameter_property DMA_2D_TRANSFER DISPLAY_NAME "2D Transfer Support"
-set_parameter_property DMA_2D_TRANSFER DISPLAY_HINT boolean
-set_parameter_property DMA_2D_TRANSFER HDL_PARAMETER true
-set_parameter_property DMA_2D_TRANSFER GROUP $group
-
 add_parameter DMA_SG_TRANSFER INTEGER 0
 set_parameter_property DMA_SG_TRANSFER DISPLAY_NAME "SG Transfer Support"
 set_parameter_property DMA_SG_TRANSFER DISPLAY_HINT boolean
 set_parameter_property DMA_SG_TRANSFER HDL_PARAMETER true
 set_parameter_property DMA_SG_TRANSFER GROUP $group
 
+add_parameter DMA_2D_TRANSFER INTEGER 0
+set_parameter_property DMA_2D_TRANSFER DISPLAY_NAME "2D Transfer Support"
+set_parameter_property DMA_2D_TRANSFER DISPLAY_HINT boolean
+set_parameter_property DMA_2D_TRANSFER HDL_PARAMETER true
+set_parameter_property DMA_2D_TRANSFER GROUP $group
+
 add_parameter SYNC_TRANSFER_START INTEGER 0
 set_parameter_property SYNC_TRANSFER_START DISPLAY_NAME "Transfer Start Synchronization Support"
 set_parameter_property SYNC_TRANSFER_START DISPLAY_HINT boolean
 set_parameter_property SYNC_TRANSFER_START HDL_PARAMETER true
 set_parameter_property SYNC_TRANSFER_START GROUP $group
 
+add_parameter CACHE_COHERENT BOOLEAN 0
+set_parameter_property CACHE_COHERENT DISPLAY_NAME "Cache Coherent"
+set_parameter_property CACHE_COHERENT DESCRIPTION "Assume DMA ports ensure cache coherence"
+set_parameter_property CACHE_COHERENT DISPLAY_HINT boolean
+set_parameter_property CACHE_COHERENT HDL_PARAMETER true
+set_parameter_property CACHE_COHERENT GROUP $group
+
 set group "Clock Domain Configuration"
 
 add_parameter AUTO_ASYNC_CLK BOOLEAN 1
@@ -328,6 +375,26 @@ proc axi_dmac_validate {} {
   }
 
   set_parameter_property MAX_BYTES_PER_BURST ALLOWED_RANGES "1:$max_burst"
+
+  set cache_coherent [get_parameter_value CACHE_COHERENT]
+  set axcache_auto [get_parameter_value AXI_AXCACHE_AUTO]
+  set axprot_auto [get_parameter_value AXI_AXPROT_AUTO]
+  set axcache_manual [get_parameter_value AXI_AXCACHE_MANUAL]
+  set axprot_manual [get_parameter_value AXI_AXPROT_MANUAL]
+  set axcache_default [expr {$cache_coherent == true} ? 0xF : 0x3]
+  set axprot_default [expr {$cache_coherent == true} ? 0x2 : 0x0]
+
+  set_parameter_property AXI_AXCACHE_AUTO ENABLED $cache_coherent
+  set_parameter_property AXI_AXPROT_AUTO ENABLED $cache_coherent
+  set_parameter_property AXI_AXCACHE_MANUAL ENABLED $cache_coherent
+  set_parameter_property AXI_AXPROT_MANUAL ENABLED $cache_coherent
+  set_parameter_property AXI_AXCACHE_MANUAL VISIBLE [expr {$cache_coherent == true} ? [expr {$axcache_auto == true} ? false : true] : false]
+  set_parameter_property AXI_AXPROT_MANUAL VISIBLE [expr {$cache_coherent == true} ? [expr {$axprot_auto == true} ? false : true] : false]
+  set_parameter_property AXI_AXCACHE VISIBLE [expr {$cache_coherent == true} ? $axcache_auto : true]
+  set_parameter_property AXI_AXPROT VISIBLE [expr {$cache_coherent == true} ? $axprot_auto : true]
+
+  set_parameter_value AXI_AXCACHE [expr {$cache_coherent == true} ? [expr {$axcache_auto == true} ? $axcache_default : $axcache_manual] : $axcache_default]
+  set_parameter_value AXI_AXPROT [expr {$cache_coherent == true} ? [expr {$axprot_auto == true} ? $axprot_default : $axprot_manual]  : $axprot_default]
 }
 
 # conditional interfaces
diff --git a/adi_library/axi_dmac/axi_dmac_ip.tcl b/adi_library/axi_dmac/axi_dmac_ip.tcl
index d3e1cf00..83c03446 100644
--- a/adi_library/axi_dmac/axi_dmac_ip.tcl
+++ b/adi_library/axi_dmac/axi_dmac_ip.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -274,14 +274,14 @@ foreach {k v} { \
         "ASYNC_CLK_SRC_SG" "true" \
         "ASYNC_CLK_DEST_SG" "true" \
         "CYCLIC" "false" \
-        "DMA_2D_TRANSFER" "false" \
         "DMA_SG_TRANSFER" "false" \
+        "DMA_2D_TRANSFER" "false" \
         "SYNC_TRANSFER_START" "false" \
         "AXI_SLICE_SRC" "false" \
         "AXI_SLICE_DEST" "false" \
         "DISABLE_DEBUG_REGISTERS" "false" \
         "ENABLE_DIAGNOSTICS_IF" "false" \
-        "CACHE_COHERENT_DEST" "false" \
+        "CACHE_COHERENT" "false" \
 	} { \
 	set_property -dict [list \
 			"value_format" "bool" \
@@ -369,18 +369,6 @@ set_property -dict [list \
 	"enablement_tcl_expr" "\$DMA_TYPE_SRC != 0" \
 ] [ipx::get_user_parameters SYNC_TRANSFER_START -of_objects $cc]
 
-set p [ipgui::get_guiparamspec -name "CACHE_COHERENT_DEST" -component $cc]
-ipgui::move_param -component $cc -order 4 $p -parent $dest_group
-set_property -dict [list \
-	"tooltip" "Assume destination port ensures cache coherency (e.g. Ultrascale HPC port)" \
-] $p
-set_property -dict [list \
-	"display_name" "Assume cache coherent" \
-	"enablement_tcl_expr" "\$DMA_TYPE_DEST == 0 && \$DMA_AXI_PROTOCOL_DEST == 0" \
-	"value_tcl_expr" "\$DMA_TYPE_DEST == 0 && \$DMA_AXI_PROTOCOL_DEST == 0" \
-	"enablement_value" "false" \
-] [ipx::get_user_parameters CACHE_COHERENT_DEST -of_objects $cc]
-
 set p [ipgui::get_guiparamspec -name "DMA_AXI_PROTOCOL_SG" -component $cc]
 ipgui::move_param -component $cc -order 0 $p -parent $sg_group
 set_property -dict [list \
@@ -441,6 +429,24 @@ set_property -dict [list \
 	"display_name" "DMA AXI Address Width" \
 ] $p
 
+set p [ipgui::get_guiparamspec -name "AXI_AXCACHE" -component $cc]
+ipgui::move_param -component $cc -order 5 $p -parent $general_group
+set_property -dict [list \
+        "display_name" "ARCACHE/AWCACHE" \
+] $p
+set_property -dict [list \
+        "enablement_tcl_expr" "\$CACHE_COHERENT == true" \
+] [ipx::get_user_parameters AXI_AXCACHE -of_objects $cc]
+
+set p [ipgui::get_guiparamspec -name "AXI_AXPROT" -component $cc]
+ipgui::move_param -component $cc -order 6 $p -parent $general_group
+set_property -dict [list \
+        "display_name" "ARPROT/AWPROT" \
+] $p
+set_property -dict [list \
+        "enablement_tcl_expr" "\$CACHE_COHERENT == true" \
+] [ipx::get_user_parameters AXI_AXPROT -of_objects $cc]
+
 set feature_group [ipgui::add_group -name "Features" -component $cc \
 		-parent $page0 -display_name "Features"]
 
@@ -450,17 +456,27 @@ set_property -dict [list \
 	"display_name" "Cyclic Transfer Support" \
 ] $p
 
-set p [ipgui::get_guiparamspec -name "DMA_2D_TRANSFER" -component $cc]
+set p [ipgui::get_guiparamspec -name "DMA_SG_TRANSFER" -component $cc]
 ipgui::move_param -component $cc -order 1 $p -parent $feature_group
+set_property -dict [list \
+	"display_name" "SG Transfer Support" \
+] $p
+
+set p [ipgui::get_guiparamspec -name "DMA_2D_TRANSFER" -component $cc]
+ipgui::move_param -component $cc -order 2 $p -parent $feature_group
 set_property -dict [list \
 	"display_name" "2D Transfer Support" \
 ] $p
 
-set p [ipgui::get_guiparamspec -name "DMA_SG_TRANSFER" -component $cc]
-ipgui::move_param -component $cc -order 2 $p -parent $feature_group
+set p [ipgui::get_guiparamspec -name "CACHE_COHERENT" -component $cc]
+ipgui::move_param -component $cc -order 3 $p -parent $feature_group
 set_property -dict [list \
-	"display_name" "SG Transfer Support" \
+	"tooltip" "Assume DMA ports ensure cache coherence (e.g. Ultrascale HPC port)" \
 ] $p
+set_property -dict [list \
+	"display_name" "Cache Coherent" \
+	"enablement_tcl_expr" "\$DMA_TYPE_SRC == 0 || \$DMA_TYPE_DEST == 0" \
+] [ipx::get_user_parameters CACHE_COHERENT -of_objects $cc]
 
 set clk_group [ipgui::add_group -name {Clock Domain Configuration} -component $cc \
 		-parent $page0 -display_name {Clock Domain Configuration}]
diff --git a/adi_library/axi_dmac/axi_dmac_regmap.v b/adi_library/axi_dmac/axi_dmac_regmap.v
index 19c264c7..aaed7770 100644
--- a/adi_library/axi_dmac/axi_dmac_regmap.v
+++ b/adi_library/axi_dmac/axi_dmac_regmap.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -53,7 +53,9 @@ module axi_dmac_regmap #(
   parameter DMA_2D_TRANSFER = 0,
   parameter DMA_SG_TRANSFER = 0,
   parameter SYNC_TRANSFER_START = 0,
-  parameter CACHE_COHERENT_DEST = 0
+  parameter CACHE_COHERENT = 0,
+  parameter [3:0] AXI_AXCACHE = 4'b0011,
+  parameter [2:0] AXI_AXPROT = 3'b000
 ) (
 
   // Slave AXI interface
@@ -121,7 +123,7 @@ module axi_dmac_regmap #(
   input [31:0] dbg_ids1
 );
 
-  localparam PCORE_VERSION = 'h00040561;
+  localparam PCORE_VERSION = 'h00040562;
   localparam HAS_ADDR_HIGH = DMA_AXI_ADDR_WIDTH > 32;
   localparam ADDR_LOW_MSB = HAS_ADDR_HIGH ? 31 : DMA_AXI_ADDR_WIDTH-1;
 
@@ -223,7 +225,10 @@ module axi_dmac_regmap #(
                            4'b0,BYTES_PER_BURST_WIDTH[3:0],
                            2'b0,DMA_TYPE_SRC[1:0],BYTES_PER_BEAT_WIDTH_SRC[3:0],
                            2'b0,DMA_TYPE_DEST[1:0],BYTES_PER_BEAT_WIDTH_DEST[3:0]};
-      9'h005: up_rdata <= {31'd0, CACHE_COHERENT_DEST};
+      9'h005: up_rdata <= {20'b0,
+                           1'b0,AXI_AXPROT,
+                           AXI_AXCACHE,
+                           3'b0,CACHE_COHERENT};
       9'h020: up_rdata <= up_irq_mask;
       9'h021: up_rdata <= up_irq_pending;
       9'h022: up_rdata <= up_irq_source;
diff --git a/adi_library/axi_dmac/axi_dmac_regmap_request.v b/adi_library/axi_dmac/axi_dmac_regmap_request.v
index 6f1c491a..45653ec9 100644
--- a/adi_library/axi_dmac/axi_dmac_regmap_request.v
+++ b/adi_library/axi_dmac/axi_dmac_regmap_request.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/axi_dmac_reset_manager.v b/adi_library/axi_dmac/axi_dmac_reset_manager.v
index 71dd0b73..fa8922b0 100644
--- a/adi_library/axi_dmac/axi_dmac_reset_manager.v
+++ b/adi_library/axi_dmac/axi_dmac_reset_manager.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/axi_dmac_resize_dest.v b/adi_library/axi_dmac/axi_dmac_resize_dest.v
index d734c11b..0585549b 100644
--- a/adi_library/axi_dmac/axi_dmac_resize_dest.v
+++ b/adi_library/axi_dmac/axi_dmac_resize_dest.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/axi_dmac_resize_src.v b/adi_library/axi_dmac/axi_dmac_resize_src.v
index 761446f9..3e75d520 100644
--- a/adi_library/axi_dmac/axi_dmac_resize_src.v
+++ b/adi_library/axi_dmac/axi_dmac_resize_src.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/axi_dmac_response_manager.v b/adi_library/axi_dmac/axi_dmac_response_manager.v
index c51ac780..a4104a3f 100644
--- a/adi_library/axi_dmac/axi_dmac_response_manager.v
+++ b/adi_library/axi_dmac/axi_dmac_response_manager.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/axi_dmac_transfer.v b/adi_library/axi_dmac/axi_dmac_transfer.v
index b3c55bea..2fd26a54 100644
--- a/adi_library/axi_dmac/axi_dmac_transfer.v
+++ b/adi_library/axi_dmac/axi_dmac_transfer.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -64,7 +64,8 @@ module axi_dmac_transfer #(
   parameter AXI_LENGTH_WIDTH_SG = 8,
   parameter ENABLE_DIAGNOSTICS_IF = 0,
   parameter ALLOW_ASYM_MEM = 0,
-  parameter CACHE_COHERENT_DEST = 0
+  parameter [3:0] AXI_AXCACHE = 4'b0011,
+  parameter [2:0] AXI_AXPROT = 3'b000
 ) (
   input ctrl_clk,
   input ctrl_resetn,
@@ -321,7 +322,9 @@ module axi_dmac_transfer #(
     .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
     .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
     .BYTES_PER_BEAT_WIDTH_SG(BYTES_PER_BEAT_WIDTH_SG),
-    .ASYNC_CLK_REQ_SG(ASYNC_CLK_REQ_SG)
+    .ASYNC_CLK_REQ_SG(ASYNC_CLK_REQ_SG),
+    .AXI_AXCACHE(AXI_AXCACHE),
+    .AXI_AXPROT(AXI_AXPROT)
   ) i_dmac_sg (
     .req_clk(req_clk),
     .req_resetn(req_resetn),
@@ -500,7 +503,8 @@ module axi_dmac_transfer #(
     .AXI_LENGTH_WIDTH_SRC (AXI_LENGTH_WIDTH_SRC),
     .ENABLE_DIAGNOSTICS_IF(ENABLE_DIAGNOSTICS_IF),
     .ALLOW_ASYM_MEM (ALLOW_ASYM_MEM),
-    .CACHE_COHERENT_DEST(CACHE_COHERENT_DEST)
+    .AXI_AXCACHE(AXI_AXCACHE),
+    .AXI_AXPROT(AXI_AXPROT)
   ) i_request_arb (
     .req_clk (req_clk),
     .req_resetn (req_resetn),
diff --git a/adi_library/axi_dmac/axi_register_slice.v b/adi_library/axi_dmac/axi_register_slice.v
index e5712224..47e607a2 100644
--- a/adi_library/axi_dmac/axi_register_slice.v
+++ b/adi_library/axi_dmac/axi_register_slice.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/bd/bd.tcl b/adi_library/axi_dmac/bd/bd.tcl
index 85a51d82..2186ad9b 100644
--- a/adi_library/axi_dmac/bd/bd.tcl
+++ b/adi_library/axi_dmac/bd/bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -203,4 +203,11 @@ proc post_propagate {cellpath otherinfo} {
 	}
 
 	set_property "CONFIG.DMA_AXI_ADDR_WIDTH" $addr_width $ip
+
+	# AXCACHE/AXPROT configuration
+        set cache_coherent [get_property "CONFIG.CACHE_COHERENT" $ip]
+        set axcache [expr {$cache_coherent == true} ? 0b1111 : 0b0011]
+        set axprot [expr {$cache_coherent == true} ? 0b010 : 0b000]
+        set_property "CONFIG.AXI_AXCACHE" $axcache $ip
+        set_property "CONFIG.AXI_AXPROT" $axprot $ip
 }
diff --git a/adi_library/axi_dmac/component.xml b/adi_library/axi_dmac/component.xml
index c8c7f6af..698cc38c 100644
--- a/adi_library/axi_dmac/component.xml
+++ b/adi_library/axi_dmac/component.xml
@@ -1798,7 +1798,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>4406b039</spirit:value>
+            <spirit:value>13fa364a</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1820,7 +1820,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>4406b039</spirit:value>
+            <spirit:value>13fa364a</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1840,7 +1840,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>a3380b44</spirit:value>
+            <spirit:value>8b30a977</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -6184,9 +6184,33 @@
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.ALLOW_ASYM_MEM">0</spirit:value>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
-        <spirit:name>CACHE_COHERENT_DEST</spirit:name>
-        <spirit:displayName>Cache Coherent Dest</spirit:displayName>
-        <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CACHE_COHERENT_DEST">true</spirit:value>
+        <spirit:name>CACHE_COHERENT</spirit:name>
+        <spirit:displayName>Cache Coherent</spirit:displayName>
+        <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.CACHE_COHERENT">false</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>AXI_AXCACHE</spirit:name>
+        <spirit:displayName>Axi Axcache</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI_AXCACHE" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.AXI_AXCACHE">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>AXI_AXPROT</spirit:name>
+        <spirit:displayName>Axi Axprot</spirit:displayName>
+        <spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.AXI_AXPROT" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.AXI_AXPROT">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
     </spirit:modelParameters>
   </spirit:model>
@@ -6366,7 +6390,7 @@
       <spirit:file>
         <spirit:name>axi_dmac.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_b602bf53</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_9c4d9b37</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -6543,7 +6567,7 @@
       <spirit:file>
         <spirit:name>xgui/axi_dmac_v1_0.tcl</spirit:name>
         <spirit:fileType>tclSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_57e931f4</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_6f5028ec</spirit:userFileType>
         <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
@@ -6797,13 +6821,37 @@
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ALLOW_ASYM_MEM">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
-      <spirit:name>CACHE_COHERENT_DEST</spirit:name>
-      <spirit:displayName>Assume cache coherent</spirit:displayName>
-      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CACHE_COHERENT_DEST">true</spirit:value>
+      <spirit:name>CACHE_COHERENT</spirit:name>
+      <spirit:displayName>Cache Coherent</spirit:displayName>
+      <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CACHE_COHERENT">false</spirit:value>
       <spirit:vendorExtensions>
         <xilinx:parameterInfo>
           <xilinx:enablement>
-            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.CACHE_COHERENT_DEST">true</xilinx:isEnabled>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.CACHE_COHERENT">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_AXCACHE</spirit:name>
+      <spirit:displayName>ARCACHE/AWCACHE</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_AXCACHE" spirit:bitStringLength="4">&quot;0011&quot;</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.AXI_AXCACHE">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>AXI_AXPROT</spirit:name>
+      <spirit:displayName>ARPROT/AWPROT</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_AXPROT" spirit:bitStringLength="3">&quot;000&quot;</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.AXI_AXPROT">false</xilinx:isEnabled>
           </xilinx:enablement>
         </xilinx:parameterInfo>
       </spirit:vendorExtensions>
@@ -6827,15 +6875,15 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_dmac</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:46:09Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:02:18Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
       <xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="8f64214e"/>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="171a117c"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="b8e5e594"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="694663ae"/>
-      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="623ef345"/>
-      <xilinx:checksum xilinx:scope="parameters" xilinx:value="3f338230"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ab308b95"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="42e5d39a"/>
     </xilinx:packagingInfo>
   </spirit:vendorExtensions>
 </spirit:component>
diff --git a/adi_library/axi_dmac/data_mover.v b/adi_library/axi_dmac/data_mover.v
index 10980008..6bb82828 100644
--- a/adi_library/axi_dmac/data_mover.v
+++ b/adi_library/axi_dmac/data_mover.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/dest_axi_mm.v b/adi_library/axi_dmac/dest_axi_mm.v
index b826a350..0d96ecc8 100644
--- a/adi_library/axi_dmac/dest_axi_mm.v
+++ b/adi_library/axi_dmac/dest_axi_mm.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -45,7 +45,8 @@ module dest_axi_mm #(
   parameter MAX_BYTES_PER_BURST = 128,
   parameter BYTES_PER_BURST_WIDTH = $clog2(MAX_BYTES_PER_BURST),
   parameter AXI_LENGTH_WIDTH = 8,
-  parameter CACHE_COHERENT = 0
+  parameter [3:0] AXI_AXCACHE = 4'b0011,
+  parameter [2:0] AXI_AXPROT = 3'b000
 ) (
   input                               m_axi_aclk,
   input                               m_axi_aresetn,
@@ -117,7 +118,8 @@ module dest_axi_mm #(
     .DMA_DATA_WIDTH(DMA_DATA_WIDTH),
     .LENGTH_WIDTH(AXI_LENGTH_WIDTH),
     .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
-    .CACHE_COHERENT(CACHE_COHERENT)
+    .AXI_AXCACHE(AXI_AXCACHE),
+    .AXI_AXPROT(AXI_AXPROT)
   ) i_addr_gen (
     .clk(m_axi_aclk),
     .resetn(m_axi_aresetn),
diff --git a/adi_library/axi_dmac/dest_axi_stream.v b/adi_library/axi_dmac/dest_axi_stream.v
index 2f38f9e1..3be743c4 100644
--- a/adi_library/axi_dmac/dest_axi_stream.v
+++ b/adi_library/axi_dmac/dest_axi_stream.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/dest_fifo_inf.v b/adi_library/axi_dmac/dest_fifo_inf.v
index 65b9fdca..ea20ec0a 100644
--- a/adi_library/axi_dmac/dest_fifo_inf.v
+++ b/adi_library/axi_dmac/dest_fifo_inf.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/dmac_2d_transfer.v b/adi_library/axi_dmac/dmac_2d_transfer.v
index cf87ca39..1aa47c67 100644
--- a/adi_library/axi_dmac/dmac_2d_transfer.v
+++ b/adi_library/axi_dmac/dmac_2d_transfer.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/dmac_sg.v b/adi_library/axi_dmac/dmac_sg.v
index 03c676f9..48871fbc 100644
--- a/adi_library/axi_dmac/dmac_sg.v
+++ b/adi_library/axi_dmac/dmac_sg.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -43,7 +43,9 @@ module dmac_sg #(
   parameter BYTES_PER_BEAT_WIDTH_DEST = 3,
   parameter BYTES_PER_BEAT_WIDTH_SRC = 3,
   parameter BYTES_PER_BEAT_WIDTH_SG = 3,
-  parameter ASYNC_CLK_REQ_SG = 1
+  parameter ASYNC_CLK_REQ_SG = 1,
+  parameter [3:0] AXI_AXCACHE = 4'b0011,
+  parameter [2:0] AXI_AXPROT = 3'b000
 ) (
   input req_clk,
   input req_resetn,
@@ -147,8 +149,8 @@ module dmac_sg #(
 
   assign m_axi_arsize  = 3'h3;
   assign m_axi_arburst = 2'h1;
-  assign m_axi_arprot  = 3'h0;
-  assign m_axi_arcache = 4'h3;
+  assign m_axi_arprot  = AXI_AXPROT;
+  assign m_axi_arcache = AXI_AXCACHE;
   assign m_axi_arlen   = 'h5;
   assign m_axi_araddr  = {next_desc_addr, {BYTES_PER_BEAT_WIDTH_SG{1'b0}}};
 
diff --git a/adi_library/axi_dmac/gui/axi_dmac_v1_0.gtcl b/adi_library/axi_dmac/gui/axi_dmac_v1_0.gtcl
index 64e1de72..c58d470e 100644
--- a/adi_library/axi_dmac/gui/axi_dmac_v1_0.gtcl
+++ b/adi_library/axi_dmac/gui/axi_dmac_v1_0.gtcl
@@ -4,5 +4,6 @@ proc gen_USERPARAMETER_SYNC_TRANSFER_START_ENABLEMENT {DMA_TYPE_SRC } {expr $DMA
 proc gen_USERPARAMETER_DMA_AXI_PROTOCOL_DEST_ENABLEMENT {DMA_TYPE_DEST } {expr $DMA_TYPE_DEST == 0}
 proc gen_USERPARAMETER_DMA_AXI_PROTOCOL_SRC_ENABLEMENT {DMA_TYPE_SRC } {expr $DMA_TYPE_SRC == 0}
 proc gen_USERPARAMETER_DMA_AXI_PROTOCOL_SG_ENABLEMENT {DMA_SG_TRANSFER } {expr $DMA_SG_TRANSFER == true}
-proc gen_USERPARAMETER_CACHE_COHERENT_DEST_ENABLEMENT {DMA_TYPE_DEST DMA_AXI_PROTOCOL_DEST } {expr $DMA_TYPE_DEST == 0 && $DMA_AXI_PROTOCOL_DEST == 0}
-proc gen_USERPARAMETER_CACHE_COHERENT_DEST_VALUE {DMA_TYPE_DEST DMA_AXI_PROTOCOL_DEST } {expr $DMA_TYPE_DEST == 0 && $DMA_AXI_PROTOCOL_DEST == 0}
+proc gen_USERPARAMETER_CACHE_COHERENT_ENABLEMENT {DMA_TYPE_SRC DMA_TYPE_DEST } {expr $DMA_TYPE_SRC == 0 || $DMA_TYPE_DEST == 0}
+proc gen_USERPARAMETER_AXI_AXCACHE_ENABLEMENT {CACHE_COHERENT } {expr $CACHE_COHERENT == true}
+proc gen_USERPARAMETER_AXI_AXPROT_ENABLEMENT {CACHE_COHERENT } {expr $CACHE_COHERENT == true}
diff --git a/adi_library/axi_dmac/request_arb.v b/adi_library/axi_dmac/request_arb.v
index c733f4fe..5d5ddd42 100644
--- a/adi_library/axi_dmac/request_arb.v
+++ b/adi_library/axi_dmac/request_arb.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -58,7 +58,8 @@ module request_arb #(
   parameter AXI_LENGTH_WIDTH_DEST = 8,
   parameter ENABLE_DIAGNOSTICS_IF = 0,
   parameter ALLOW_ASYM_MEM = 0,
-  parameter CACHE_COHERENT_DEST = 0
+  parameter [3:0] AXI_AXCACHE = 4'b0011,
+  parameter [2:0] AXI_AXPROT = 3'b000
 ) (
   input req_clk,
   input req_resetn,
@@ -357,7 +358,8 @@ module request_arb #(
     .MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST),
     .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH),
     .AXI_LENGTH_WIDTH(AXI_LENGTH_WIDTH_DEST),
-    .CACHE_COHERENT(CACHE_COHERENT_DEST)
+    .AXI_AXCACHE(AXI_AXCACHE),
+    .AXI_AXPROT(AXI_AXPROT)
   ) i_dest_dma_mm (
     .m_axi_aclk(m_dest_axi_aclk),
     .m_axi_aresetn(dest_resetn),
@@ -619,7 +621,9 @@ module request_arb #(
     .DMA_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH),
     .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC),
     .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_SRC),
-    .AXI_LENGTH_WIDTH(AXI_LENGTH_WIDTH_SRC)
+    .AXI_LENGTH_WIDTH(AXI_LENGTH_WIDTH_SRC),
+    .AXI_AXCACHE(AXI_AXCACHE),
+    .AXI_AXPROT(AXI_AXPROT)
   ) i_src_dma_mm (
     .m_axi_aclk(m_src_axi_aclk),
     .m_axi_aresetn(src_resetn),
diff --git a/adi_library/axi_dmac/request_generator.v b/adi_library/axi_dmac/request_generator.v
index 2951e244..93771859 100644
--- a/adi_library/axi_dmac/request_generator.v
+++ b/adi_library/axi_dmac/request_generator.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/response_generator.v b/adi_library/axi_dmac/response_generator.v
index 85623361..8c2b6350 100644
--- a/adi_library/axi_dmac/response_generator.v
+++ b/adi_library/axi_dmac/response_generator.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/response_handler.v b/adi_library/axi_dmac/response_handler.v
index dae85697..51fc43c0 100644
--- a/adi_library/axi_dmac/response_handler.v
+++ b/adi_library/axi_dmac/response_handler.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/splitter.v b/adi_library/axi_dmac/splitter.v
index 93e2cfe3..71d68bc0 100644
--- a/adi_library/axi_dmac/splitter.v
+++ b/adi_library/axi_dmac/splitter.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/src_axi_mm.v b/adi_library/axi_dmac/src_axi_mm.v
index e3cd4e02..acad90ee 100644
--- a/adi_library/axi_dmac/src_axi_mm.v
+++ b/adi_library/axi_dmac/src_axi_mm.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -42,7 +42,9 @@ module src_axi_mm #(
   parameter DMA_ADDR_WIDTH = 32,
   parameter BYTES_PER_BEAT_WIDTH = 3,
   parameter BEATS_PER_BURST_WIDTH = 4,
-  parameter AXI_LENGTH_WIDTH = 8
+  parameter AXI_LENGTH_WIDTH = 8,
+  parameter [3:0] AXI_AXCACHE = 4'b0011,
+  parameter [2:0] AXI_AXPROT = 3'b000
 ) (
   input                           m_axi_aclk,
   input                           m_axi_aresetn,
@@ -148,7 +150,9 @@ module src_axi_mm #(
     .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),
     .DMA_DATA_WIDTH(DMA_DATA_WIDTH),
     .LENGTH_WIDTH(AXI_LENGTH_WIDTH),
-    .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH)
+    .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
+    .AXI_AXCACHE(AXI_AXCACHE),
+    .AXI_AXPROT(AXI_AXPROT)
   ) i_addr_gen (
     .clk(m_axi_aclk),
     .resetn(m_axi_aresetn),
diff --git a/adi_library/axi_dmac/src_axi_stream.v b/adi_library/axi_dmac/src_axi_stream.v
index d83c151c..f63078e8 100644
--- a/adi_library/axi_dmac/src_axi_stream.v
+++ b/adi_library/axi_dmac/src_axi_stream.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/src_fifo_inf.v b/adi_library/axi_dmac/src_fifo_inf.v
index b5af3bfa..af3fdd78 100644
--- a/adi_library/axi_dmac/src_fifo_inf.v
+++ b/adi_library/axi_dmac/src_fifo_inf.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/tb/axi_read_slave.v b/adi_library/axi_dmac/tb/axi_read_slave.v
index 2aa47b0e..120e398a 100644
--- a/adi_library/axi_dmac/tb/axi_read_slave.v
+++ b/adi_library/axi_dmac/tb/axi_read_slave.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/tb/axi_slave.v b/adi_library/axi_dmac/tb/axi_slave.v
index fc5199a1..81b7357d 100644
--- a/adi_library/axi_dmac/tb/axi_slave.v
+++ b/adi_library/axi_dmac/tb/axi_slave.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/tb/axi_write_slave.v b/adi_library/axi_dmac/tb/axi_write_slave.v
index 06523220..535e1cec 100644
--- a/adi_library/axi_dmac/tb/axi_write_slave.v
+++ b/adi_library/axi_dmac/tb/axi_write_slave.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/tb/dma_read_shutdown_tb.v b/adi_library/axi_dmac/tb/dma_read_shutdown_tb.v
index c7568c5d..9e84e128 100644
--- a/adi_library/axi_dmac/tb/dma_read_shutdown_tb.v
+++ b/adi_library/axi_dmac/tb/dma_read_shutdown_tb.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/tb/dma_read_tb.v b/adi_library/axi_dmac/tb/dma_read_tb.v
index 29e8ae42..df7e81a4 100644
--- a/adi_library/axi_dmac/tb/dma_read_tb.v
+++ b/adi_library/axi_dmac/tb/dma_read_tb.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/tb/dma_write_shutdown_tb.v b/adi_library/axi_dmac/tb/dma_write_shutdown_tb.v
index eaefcb2a..2686e01a 100644
--- a/adi_library/axi_dmac/tb/dma_write_shutdown_tb.v
+++ b/adi_library/axi_dmac/tb/dma_write_shutdown_tb.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/tb/dma_write_tb.v b/adi_library/axi_dmac/tb/dma_write_tb.v
index 21319135..bc10e2ba 100644
--- a/adi_library/axi_dmac/tb/dma_write_tb.v
+++ b/adi_library/axi_dmac/tb/dma_write_tb.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/tb/regmap_tb.v b/adi_library/axi_dmac/tb/regmap_tb.v
index ae34be53..c04f1490 100644
--- a/adi_library/axi_dmac/tb/regmap_tb.v
+++ b/adi_library/axi_dmac/tb/regmap_tb.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/tb/reset_manager_tb.v b/adi_library/axi_dmac/tb/reset_manager_tb.v
index b14c1c7a..dc625d4d 100644
--- a/adi_library/axi_dmac/tb/reset_manager_tb.v
+++ b/adi_library/axi_dmac/tb/reset_manager_tb.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/tb/tb_base.v b/adi_library/axi_dmac/tb/tb_base.v
index f12267d2..cf941988 100644
--- a/adi_library/axi_dmac/tb/tb_base.v
+++ b/adi_library/axi_dmac/tb/tb_base.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_dmac/xgui/axi_dmac_v1_0.tcl b/adi_library/axi_dmac/xgui/axi_dmac_v1_0.tcl
index 70acb061..eaa68f5b 100644
--- a/adi_library/axi_dmac/xgui/axi_dmac_v1_0.tcl
+++ b/adi_library/axi_dmac/xgui/axi_dmac_v1_0.tcl
@@ -25,8 +25,6 @@ proc init_gui { IPINST } {
   set DMA_DATA_WIDTH_DEST [ipgui::add_param $IPINST -name "DMA_DATA_WIDTH_DEST" -parent ${Destination}]
   set_property tooltip {Bus Width: For Memory-Mapped interface the valid range is 32-1024 bits} ${DMA_DATA_WIDTH_DEST}
   ipgui::add_param $IPINST -name "AXI_SLICE_DEST" -parent ${Destination}
-  set CACHE_COHERENT_DEST [ipgui::add_param $IPINST -name "CACHE_COHERENT_DEST" -parent ${Destination}]
-  set_property tooltip {Assume destination port ensures cache coherency (e.g. Ultrascale HPC port)} ${CACHE_COHERENT_DEST}
 
   #Adding Group
   set Scatter-Gather [ipgui::add_group $IPINST -name "Scatter-Gather" -parent ${DMA_Endpoint_Configuration}]
@@ -41,12 +39,16 @@ proc init_gui { IPINST } {
   ipgui::add_param $IPINST -name "FIFO_SIZE" -parent ${General_Configuration} -widget comboBox
   ipgui::add_param $IPINST -name "MAX_BYTES_PER_BURST" -parent ${General_Configuration}
   ipgui::add_param $IPINST -name "DMA_AXI_ADDR_WIDTH" -parent ${General_Configuration}
+  ipgui::add_param $IPINST -name "AXI_AXCACHE" -parent ${General_Configuration}
+  ipgui::add_param $IPINST -name "AXI_AXPROT" -parent ${General_Configuration}
 
   #Adding Group
   set Features [ipgui::add_group $IPINST -name "Features" -parent ${Page_0}]
   ipgui::add_param $IPINST -name "CYCLIC" -parent ${Features}
-  ipgui::add_param $IPINST -name "DMA_2D_TRANSFER" -parent ${Features}
   ipgui::add_param $IPINST -name "DMA_SG_TRANSFER" -parent ${Features}
+  ipgui::add_param $IPINST -name "DMA_2D_TRANSFER" -parent ${Features}
+  set CACHE_COHERENT [ipgui::add_param $IPINST -name "CACHE_COHERENT" -parent ${Features}]
+  set_property tooltip {Assume DMA ports ensure cache coherence (e.g. Ultrascale HPC port)} ${CACHE_COHERENT}
 
   #Adding Group
   set Clock_Domain_Configuration [ipgui::add_group $IPINST -name "Clock Domain Configuration" -parent ${Page_0}]
@@ -66,24 +68,59 @@ proc init_gui { IPINST } {
 
 }
 
-proc update_PARAM_VALUE.CACHE_COHERENT_DEST { PARAM_VALUE.CACHE_COHERENT_DEST PARAM_VALUE.DMA_TYPE_DEST PARAM_VALUE.DMA_AXI_PROTOCOL_DEST } {
-	# Procedure called to update CACHE_COHERENT_DEST when any of the dependent parameters in the arguments change
+proc update_PARAM_VALUE.AXI_AXCACHE { PARAM_VALUE.AXI_AXCACHE PARAM_VALUE.CACHE_COHERENT } {
+	# Procedure called to update AXI_AXCACHE when any of the dependent parameters in the arguments change
 	
-	set CACHE_COHERENT_DEST ${PARAM_VALUE.CACHE_COHERENT_DEST}
-	set DMA_TYPE_DEST ${PARAM_VALUE.DMA_TYPE_DEST}
-	set DMA_AXI_PROTOCOL_DEST ${PARAM_VALUE.DMA_AXI_PROTOCOL_DEST}
-	set values(DMA_TYPE_DEST) [get_property value $DMA_TYPE_DEST]
-	set values(DMA_AXI_PROTOCOL_DEST) [get_property value $DMA_AXI_PROTOCOL_DEST]
-	if { [gen_USERPARAMETER_CACHE_COHERENT_DEST_ENABLEMENT $values(DMA_TYPE_DEST) $values(DMA_AXI_PROTOCOL_DEST)] } {
-		set_property enabled true $CACHE_COHERENT_DEST
+	set AXI_AXCACHE ${PARAM_VALUE.AXI_AXCACHE}
+	set CACHE_COHERENT ${PARAM_VALUE.CACHE_COHERENT}
+	set values(CACHE_COHERENT) [get_property value $CACHE_COHERENT]
+	if { [gen_USERPARAMETER_AXI_AXCACHE_ENABLEMENT $values(CACHE_COHERENT)] } {
+		set_property enabled true $AXI_AXCACHE
 	} else {
-		set_property enabled false $CACHE_COHERENT_DEST
-		set_property value [gen_USERPARAMETER_CACHE_COHERENT_DEST_VALUE $values(DMA_TYPE_DEST) $values(DMA_AXI_PROTOCOL_DEST)] $CACHE_COHERENT_DEST
+		set_property enabled false $AXI_AXCACHE
 	}
 }
 
-proc validate_PARAM_VALUE.CACHE_COHERENT_DEST { PARAM_VALUE.CACHE_COHERENT_DEST } {
-	# Procedure called to validate CACHE_COHERENT_DEST
+proc validate_PARAM_VALUE.AXI_AXCACHE { PARAM_VALUE.AXI_AXCACHE } {
+	# Procedure called to validate AXI_AXCACHE
+	return true
+}
+
+proc update_PARAM_VALUE.AXI_AXPROT { PARAM_VALUE.AXI_AXPROT PARAM_VALUE.CACHE_COHERENT } {
+	# Procedure called to update AXI_AXPROT when any of the dependent parameters in the arguments change
+	
+	set AXI_AXPROT ${PARAM_VALUE.AXI_AXPROT}
+	set CACHE_COHERENT ${PARAM_VALUE.CACHE_COHERENT}
+	set values(CACHE_COHERENT) [get_property value $CACHE_COHERENT]
+	if { [gen_USERPARAMETER_AXI_AXPROT_ENABLEMENT $values(CACHE_COHERENT)] } {
+		set_property enabled true $AXI_AXPROT
+	} else {
+		set_property enabled false $AXI_AXPROT
+	}
+}
+
+proc validate_PARAM_VALUE.AXI_AXPROT { PARAM_VALUE.AXI_AXPROT } {
+	# Procedure called to validate AXI_AXPROT
+	return true
+}
+
+proc update_PARAM_VALUE.CACHE_COHERENT { PARAM_VALUE.CACHE_COHERENT PARAM_VALUE.DMA_TYPE_SRC PARAM_VALUE.DMA_TYPE_DEST } {
+	# Procedure called to update CACHE_COHERENT when any of the dependent parameters in the arguments change
+	
+	set CACHE_COHERENT ${PARAM_VALUE.CACHE_COHERENT}
+	set DMA_TYPE_SRC ${PARAM_VALUE.DMA_TYPE_SRC}
+	set DMA_TYPE_DEST ${PARAM_VALUE.DMA_TYPE_DEST}
+	set values(DMA_TYPE_SRC) [get_property value $DMA_TYPE_SRC]
+	set values(DMA_TYPE_DEST) [get_property value $DMA_TYPE_DEST]
+	if { [gen_USERPARAMETER_CACHE_COHERENT_ENABLEMENT $values(DMA_TYPE_SRC) $values(DMA_TYPE_DEST)] } {
+		set_property enabled true $CACHE_COHERENT
+	} else {
+		set_property enabled false $CACHE_COHERENT
+	}
+}
+
+proc validate_PARAM_VALUE.CACHE_COHERENT { PARAM_VALUE.CACHE_COHERENT } {
+	# Procedure called to validate CACHE_COHERENT
 	return true
 }
 
@@ -595,8 +632,18 @@ proc update_MODELPARAM_VALUE.ALLOW_ASYM_MEM { MODELPARAM_VALUE.ALLOW_ASYM_MEM PA
 	set_property value [get_property value ${PARAM_VALUE.ALLOW_ASYM_MEM}] ${MODELPARAM_VALUE.ALLOW_ASYM_MEM}
 }
 
-proc update_MODELPARAM_VALUE.CACHE_COHERENT_DEST { MODELPARAM_VALUE.CACHE_COHERENT_DEST PARAM_VALUE.CACHE_COHERENT_DEST } {
+proc update_MODELPARAM_VALUE.CACHE_COHERENT { MODELPARAM_VALUE.CACHE_COHERENT PARAM_VALUE.CACHE_COHERENT } {
 	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
-	set_property value [get_property value ${PARAM_VALUE.CACHE_COHERENT_DEST}] ${MODELPARAM_VALUE.CACHE_COHERENT_DEST}
+	set_property value [get_property value ${PARAM_VALUE.CACHE_COHERENT}] ${MODELPARAM_VALUE.CACHE_COHERENT}
+}
+
+proc update_MODELPARAM_VALUE.AXI_AXCACHE { MODELPARAM_VALUE.AXI_AXCACHE PARAM_VALUE.AXI_AXCACHE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.AXI_AXCACHE}] ${MODELPARAM_VALUE.AXI_AXCACHE}
+}
+
+proc update_MODELPARAM_VALUE.AXI_AXPROT { MODELPARAM_VALUE.AXI_AXPROT PARAM_VALUE.AXI_AXPROT } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.AXI_AXPROT}] ${MODELPARAM_VALUE.AXI_AXPROT}
 }
 
diff --git a/adi_library/axi_fan_control/axi_fan_control.v b/adi_library/axi_fan_control/axi_fan_control.v
index cd03f6c0..d5b668c0 100644
--- a/adi_library/axi_fan_control/axi_fan_control.v
+++ b/adi_library/axi_fan_control/axi_fan_control.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_fan_control/axi_fan_control.xpr b/adi_library/axi_fan_control/axi_fan_control.xpr
index b7f37186..16bd7bf8 100644
--- a/adi_library/axi_fan_control/axi_fan_control.xpr
+++ b/adi_library/axi_fan_control/axi_fan_control.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_fan_control/axi_fan_control.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_fan_control/axi_fan_control.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="62683cefe9ac4e41bf9fb77c886a5c9a"/>
+    <Option Name="Id" Val="40a7f0c94fdc40e9a0b322e972a5f104"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -168,21 +167,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -195,7 +194,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_fan_control/component.xml b/adi_library/axi_fan_control/component.xml
index d78c8a0b..f3dd6ec0 100644
--- a/adi_library/axi_fan_control/component.xml
+++ b/adi_library/axi_fan_control/component.xml
@@ -241,7 +241,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>5cc2597a</spirit:value>
+            <spirit:value>a5f45705</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -257,7 +257,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>5cc2597a</spirit:value>
+            <spirit:value>a5f45705</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -785,7 +785,7 @@
       <spirit:file>
         <spirit:name>axi_fan_control.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_f52f26c6</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_5cc45fc9</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -943,11 +943,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_fan_control</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:46:18Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:02:27Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="75044ed6"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="0e7adb98"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="e4cef4e9"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="e84e4824"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="0a4565b9"/>
diff --git a/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync.v b/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync.v
index e88ed496..ed2e9570 100644
--- a/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync.v
+++ b/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync.xpr b/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync.xpr
index 373bc04b..af3389f5 100644
--- a/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync.xpr
+++ b/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_fmcadc5_sync/axi_fmcadc5_sync.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_fmcadc5_sync/axi_fmcadc5_sync.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="1b8b5053dbfb405c802614592804ecbb"/>
+    <Option Name="Id" Val="910e1ee7a7c54727bd9c2411d577bce5"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -195,21 +194,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -222,7 +221,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v b/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v
index f5646531..c67ba10d 100644
--- a/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v
+++ b/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_fmcadc5_sync/component.xml b/adi_library/axi_fmcadc5_sync/component.xml
index 1a009d3a..ab48b742 100644
--- a/adi_library/axi_fmcadc5_sync/component.xml
+++ b/adi_library/axi_fmcadc5_sync/component.xml
@@ -295,7 +295,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>bc167762</spirit:value>
+            <spirit:value>b70ee2ab</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -311,7 +311,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>bb8328f0</spirit:value>
+            <spirit:value>0cbad76f</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1104,30 +1104,6 @@
       <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
       <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
     </spirit:choice>
-    <spirit:choice>
-      <spirit:name>choice_pairs_00ecfe9a</spirit:name>
-      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
-      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
-      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
-      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
-      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
-      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
-      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
-      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
-      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
-      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
-      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
-      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
-      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
-      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
-      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
-      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
-      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
-      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
-      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
-      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
-      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
-    </spirit:choice>
     <spirit:choice>
       <spirit:name>choice_pairs_19f99f31</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
@@ -1153,7 +1129,32 @@
       <spirit:enumeration spirit:text="versal">4</spirit:enumeration>
     </spirit:choice>
     <spirit:choice>
-      <spirit:name>choice_pairs_fc01a186</spirit:name>
+      <spirit:name>choice_pairs_a6e6e044</spirit:name>
+      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
+      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
+      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
+      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
+      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
+      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
+      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
+      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
+      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
+      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
+      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
+      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
+      <spirit:enumeration spirit:text="ls">21</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a897e79d</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
       <spirit:enumeration spirit:text="artix">1</spirit:enumeration>
       <spirit:enumeration spirit:text="kintex">2</spirit:enumeration>
@@ -1161,6 +1162,7 @@
       <spirit:enumeration spirit:text="zynq">4</spirit:enumeration>
       <spirit:enumeration spirit:text="versalprime">5</spirit:enumeration>
       <spirit:enumeration spirit:text="versalaicore">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="versalpremium">7</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
   <spirit:fileSets>
@@ -1189,7 +1191,7 @@
       <spirit:file>
         <spirit:name>axi_fmcadc5_sync.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_b6a370b0</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_c6ee4d90</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1247,7 +1249,7 @@
     <spirit:parameter>
       <spirit:name>FPGA_FAMILY</spirit:name>
       <spirit:displayName>Fpga Family</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_fc01a186">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_a897e79d">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>SPEED_GRADE</spirit:name>
@@ -1257,7 +1259,7 @@
     <spirit:parameter>
       <spirit:name>DEV_PACKAGE</spirit:name>
       <spirit:displayName>Dev Package</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_00ecfe9a">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_a6e6e044">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>DELAY_REFCLK_FREQUENCY</spirit:name>
@@ -1307,11 +1309,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:46:28Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:02:39Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="11db471a"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="93d08598"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="63f95c5a"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="57bcb657"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="ab5f4132"/>
diff --git a/adi_library/axi_generic_adc/axi_generic_adc.v b/adi_library/axi_generic_adc/axi_generic_adc.v
index 551d3e8b..b177f7c0 100644
--- a/adi_library/axi_generic_adc/axi_generic_adc.v
+++ b/adi_library/axi_generic_adc/axi_generic_adc.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_generic_adc/axi_generic_adc.xpr b/adi_library/axi_generic_adc/axi_generic_adc.xpr
index 7f39b0af..608ee8bf 100644
--- a/adi_library/axi_generic_adc/axi_generic_adc.xpr
+++ b/adi_library/axi_generic_adc/axi_generic_adc.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_generic_adc/axi_generic_adc.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_generic_adc/axi_generic_adc.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="4e13ee7d49f44a19ab0696716854aaf9"/>
+    <Option Name="Id" Val="b7783d6628c944f2983222513aa0cec1"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -209,21 +208,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -236,7 +235,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_generic_adc/component.xml b/adi_library/axi_generic_adc/component.xml
index 8e05c1db..70a28d38 100644
--- a/adi_library/axi_generic_adc/component.xml
+++ b/adi_library/axi_generic_adc/component.xml
@@ -257,7 +257,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>eb75f9bd</spirit:value>
+            <spirit:value>c7b5a43c</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -273,7 +273,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>daf9ad57</spirit:value>
+            <spirit:value>a46f0eb1</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -737,7 +737,7 @@
       <spirit:file>
         <spirit:name>axi_generic_adc.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_0f8af5eb</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_bfde7a16</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -840,11 +840,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_adc_ip</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:46:40Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:02:52Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="34da17ad"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="a0cfe24b"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="f1d6c584"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="1aa40838"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="6928a91d"/>
diff --git a/adi_library/axi_gpreg/axi_gpreg.v b/adi_library/axi_gpreg/axi_gpreg.v
index 7650e01f..71ae7a35 100644
--- a/adi_library/axi_gpreg/axi_gpreg.v
+++ b/adi_library/axi_gpreg/axi_gpreg.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_gpreg/axi_gpreg.xpr b/adi_library/axi_gpreg/axi_gpreg.xpr
index e0c02ecb..6d4b7489 100644
--- a/adi_library/axi_gpreg/axi_gpreg.xpr
+++ b/adi_library/axi_gpreg/axi_gpreg.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_gpreg/axi_gpreg.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_gpreg/axi_gpreg.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="40fe6489eba546618b11a8b35faa85d6"/>
+    <Option Name="Id" Val="912755638e924e20b9a0291ed793aa6c"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -196,21 +195,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -223,7 +222,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_gpreg/axi_gpreg_clock_mon.v b/adi_library/axi_gpreg/axi_gpreg_clock_mon.v
index 022aab7e..1df0cb93 100644
--- a/adi_library/axi_gpreg/axi_gpreg_clock_mon.v
+++ b/adi_library/axi_gpreg/axi_gpreg_clock_mon.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_gpreg/axi_gpreg_io.v b/adi_library/axi_gpreg/axi_gpreg_io.v
index 1483e68a..14494451 100644
--- a/adi_library/axi_gpreg/axi_gpreg_io.v
+++ b/adi_library/axi_gpreg/axi_gpreg_io.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_gpreg/component.xml b/adi_library/axi_gpreg/component.xml
index 41366da0..5792468c 100644
--- a/adi_library/axi_gpreg/component.xml
+++ b/adi_library/axi_gpreg/component.xml
@@ -241,7 +241,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>c4ab9d05</spirit:value>
+            <spirit:value>6b99083a</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -257,7 +257,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>5ca46b5b</spirit:value>
+            <spirit:value>a2da6ec6</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1509,7 +1509,7 @@
       <spirit:file>
         <spirit:name>axi_gpreg.v</spirit:name>
         <spirit:fileType>systemVerilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_eb2994e4</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_43e130a6</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1625,11 +1625,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:46:51Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:03:04Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="21347790"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="2c8a0b5b"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="b4e51815"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="fc217c5b"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="ce8be4a3"/>
diff --git a/adi_library/axi_hdmi_rx/axi_hdmi_rx.v b/adi_library/axi_hdmi_rx/axi_hdmi_rx.v
index 3640be4a..7262054b 100644
--- a/adi_library/axi_hdmi_rx/axi_hdmi_rx.v
+++ b/adi_library/axi_hdmi_rx/axi_hdmi_rx.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_hdmi_rx/axi_hdmi_rx.xpr b/adi_library/axi_hdmi_rx/axi_hdmi_rx.xpr
index 1207c764..4e96ea1e 100644
--- a/adi_library/axi_hdmi_rx/axi_hdmi_rx.xpr
+++ b/adi_library/axi_hdmi_rx/axi_hdmi_rx.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_hdmi_rx/axi_hdmi_rx.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_hdmi_rx/axi_hdmi_rx.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="cf1288efcf4a4c789148aad441498913"/>
+    <Option Name="Id" Val="c8314214cf6943a9bbbf7234277a8c68"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -262,21 +261,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -289,7 +288,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_hdmi_rx/axi_hdmi_rx_core.v b/adi_library/axi_hdmi_rx/axi_hdmi_rx_core.v
index a74e5c59..07edbec6 100644
--- a/adi_library/axi_hdmi_rx/axi_hdmi_rx_core.v
+++ b/adi_library/axi_hdmi_rx/axi_hdmi_rx_core.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_hdmi_rx/axi_hdmi_rx_es.v b/adi_library/axi_hdmi_rx/axi_hdmi_rx_es.v
index 8de1ad25..02578b24 100644
--- a/adi_library/axi_hdmi_rx/axi_hdmi_rx_es.v
+++ b/adi_library/axi_hdmi_rx/axi_hdmi_rx_es.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_hdmi_rx/axi_hdmi_rx_tpm.v b/adi_library/axi_hdmi_rx/axi_hdmi_rx_tpm.v
index 7774c885..22cf1f6f 100644
--- a/adi_library/axi_hdmi_rx/axi_hdmi_rx_tpm.v
+++ b/adi_library/axi_hdmi_rx/axi_hdmi_rx_tpm.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_hdmi_rx/component.xml b/adi_library/axi_hdmi_rx/component.xml
index 8b6f964a..6a31f8c8 100644
--- a/adi_library/axi_hdmi_rx/component.xml
+++ b/adi_library/axi_hdmi_rx/component.xml
@@ -273,7 +273,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>0b5ab183</spirit:value>
+            <spirit:value>cba65a1e</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -289,7 +289,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>e96ea91a</spirit:value>
+            <spirit:value>2bfd1c8c</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -857,7 +857,7 @@
       <spirit:file>
         <spirit:name>axi_hdmi_rx.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_2587e0a1</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_c7c76618</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -980,11 +980,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_hdmi_rx</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:47:06Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:03:20Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="50e0161d"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="b827e6a1"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="32197904"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="aafde21e"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="9caef265"/>
diff --git a/adi_library/axi_hdmi_tx/axi_hdmi_tx.v b/adi_library/axi_hdmi_tx/axi_hdmi_tx.v
index 55b60265..d0f452fb 100644
--- a/adi_library/axi_hdmi_tx/axi_hdmi_tx.v
+++ b/adi_library/axi_hdmi_tx/axi_hdmi_tx.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_hdmi_tx/axi_hdmi_tx.xpr b/adi_library/axi_hdmi_tx/axi_hdmi_tx.xpr
index 2683c9cd..5af241f8 100644
--- a/adi_library/axi_hdmi_tx/axi_hdmi_tx.xpr
+++ b/adi_library/axi_hdmi_tx/axi_hdmi_tx.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_hdmi_tx/axi_hdmi_tx.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_hdmi_tx/axi_hdmi_tx.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="a561b440aaa844d3b244c7eefd720fb0"/>
+    <Option Name="Id" Val="24838a2b6f6a497d9709481eaea216fa"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -290,21 +289,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -317,7 +316,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_hdmi_tx/axi_hdmi_tx_core.v b/adi_library/axi_hdmi_tx/axi_hdmi_tx_core.v
index ccbe3c8d..d8a962c0 100644
--- a/adi_library/axi_hdmi_tx/axi_hdmi_tx_core.v
+++ b/adi_library/axi_hdmi_tx/axi_hdmi_tx_core.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_hdmi_tx/axi_hdmi_tx_es.v b/adi_library/axi_hdmi_tx/axi_hdmi_tx_es.v
index 69e85f4d..1ad59292 100644
--- a/adi_library/axi_hdmi_tx/axi_hdmi_tx_es.v
+++ b/adi_library/axi_hdmi_tx/axi_hdmi_tx_es.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_hdmi_tx/axi_hdmi_tx_vdma.v b/adi_library/axi_hdmi_tx/axi_hdmi_tx_vdma.v
index 2308ec2c..41d00b8e 100644
--- a/adi_library/axi_hdmi_tx/axi_hdmi_tx_vdma.v
+++ b/adi_library/axi_hdmi_tx/axi_hdmi_tx_vdma.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_hdmi_tx/component.xml b/adi_library/axi_hdmi_tx/component.xml
index 4853c0b9..fa2bfbec 100644
--- a/adi_library/axi_hdmi_tx/component.xml
+++ b/adi_library/axi_hdmi_tx/component.xml
@@ -351,7 +351,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>9d6d3555</spirit:value>
+            <spirit:value>52b1f606</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -367,7 +367,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>6b939f5e</spirit:value>
+            <spirit:value>b80884c4</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1446,7 +1446,7 @@
       <spirit:file>
         <spirit:name>axi_hdmi_tx.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_cc010272</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_c41b8abb</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1595,11 +1595,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_hdmi_tx</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:47:23Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:03:39Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="74925256"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="a81ed01f"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="b2b9a1af"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ba76cc6d"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="e5e9f2ac"/>
diff --git a/adi_library/axi_i2s_adi/axi_i2s_adi.vhd b/adi_library/axi_i2s_adi/axi_i2s_adi.vhd
index b31859ea..d294d479 100644
--- a/adi_library/axi_i2s_adi/axi_i2s_adi.vhd
+++ b/adi_library/axi_i2s_adi/axi_i2s_adi.vhd
@@ -26,7 +26,7 @@
 --
 --   2. An ADI specific BSD license, which can be found in the top level directory
 --      of this repository (LICENSE_ADIBSD), and also on-line at:
---      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+--      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 --      This will allow to generate bit files and not release the source code,
 --      as long as it attaches to an ADI device.
 --
diff --git a/adi_library/axi_i2s_adi/axi_i2s_adi.xpr b/adi_library/axi_i2s_adi/axi_i2s_adi.xpr
index 5dc837ad..13bad960 100644
--- a/adi_library/axi_i2s_adi/axi_i2s_adi.xpr
+++ b/adi_library/axi_i2s_adi/axi_i2s_adi.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_i2s_adi/axi_i2s_adi.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_i2s_adi/axi_i2s_adi.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="b7e0c42c8d254bb291f446e52f63e02b"/>
+    <Option Name="Id" Val="26393f79d1d64f639315f59077505cc0"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -219,21 +218,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -246,7 +245,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_i2s_adi/component.xml b/adi_library/axi_i2s_adi/component.xml
index a650c258..b448b202 100644
--- a/adi_library/axi_i2s_adi/component.xml
+++ b/adi_library/axi_i2s_adi/component.xml
@@ -836,7 +836,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>a333f569</spirit:value>
+            <spirit:value>759f5350</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -852,7 +852,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>fcea8f7f</spirit:value>
+            <spirit:value>b7ae2d68</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -2145,7 +2145,7 @@
       <spirit:file>
         <spirit:name>axi_i2s_adi.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_e6503276</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_ddd4baa5</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -2300,11 +2300,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:47:36Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:03:54Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="245f59c8"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="dbf705db"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="4a34483c"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="e83ce3b0"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="ced4a0b5"/>
diff --git a/adi_library/axi_i2s_adi/fifo_synchronizer.vhd b/adi_library/axi_i2s_adi/fifo_synchronizer.vhd
index 336e74d9..56ba15ef 100644
--- a/adi_library/axi_i2s_adi/fifo_synchronizer.vhd
+++ b/adi_library/axi_i2s_adi/fifo_synchronizer.vhd
@@ -26,7 +26,7 @@
 --
 --   2. An ADI specific BSD license, which can be found in the top level directory
 --      of this repository (LICENSE_ADIBSD), and also on-line at:
---      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+--      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 --      This will allow to generate bit files and not release the source code,
 --      as long as it attaches to an ADI device.
 --
diff --git a/adi_library/axi_i2s_adi/i2s_clkgen.vhd b/adi_library/axi_i2s_adi/i2s_clkgen.vhd
index 9fe1bac1..3b5b7870 100644
--- a/adi_library/axi_i2s_adi/i2s_clkgen.vhd
+++ b/adi_library/axi_i2s_adi/i2s_clkgen.vhd
@@ -26,7 +26,7 @@
 --
 --   2. An ADI specific BSD license, which can be found in the top level directory
 --      of this repository (LICENSE_ADIBSD), and also on-line at:
---      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+--      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 --      This will allow to generate bit files and not release the source code,
 --      as long as it attaches to an ADI device.
 --
diff --git a/adi_library/axi_i2s_adi/i2s_controller.vhd b/adi_library/axi_i2s_adi/i2s_controller.vhd
index 9eb439bb..c03edf47 100644
--- a/adi_library/axi_i2s_adi/i2s_controller.vhd
+++ b/adi_library/axi_i2s_adi/i2s_controller.vhd
@@ -26,7 +26,7 @@
 --
 --   2. An ADI specific BSD license, which can be found in the top level directory
 --      of this repository (LICENSE_ADIBSD), and also on-line at:
---      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+--      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 --      This will allow to generate bit files and not release the source code,
 --      as long as it attaches to an ADI device.
 --
diff --git a/adi_library/axi_i2s_adi/i2s_rx.vhd b/adi_library/axi_i2s_adi/i2s_rx.vhd
index 77ab45c6..07218e81 100644
--- a/adi_library/axi_i2s_adi/i2s_rx.vhd
+++ b/adi_library/axi_i2s_adi/i2s_rx.vhd
@@ -26,7 +26,7 @@
 --
 --   2. An ADI specific BSD license, which can be found in the top level directory
 --      of this repository (LICENSE_ADIBSD), and also on-line at:
---      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+--      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 --      This will allow to generate bit files and not release the source code,
 --      as long as it attaches to an ADI device.
 --
diff --git a/adi_library/axi_i2s_adi/i2s_tx.vhd b/adi_library/axi_i2s_adi/i2s_tx.vhd
index 10ca3ce4..4cf852f7 100644
--- a/adi_library/axi_i2s_adi/i2s_tx.vhd
+++ b/adi_library/axi_i2s_adi/i2s_tx.vhd
@@ -26,7 +26,7 @@
 --
 --   2. An ADI specific BSD license, which can be found in the top level directory
 --      of this repository (LICENSE_ADIBSD), and also on-line at:
---      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+--      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 --      This will allow to generate bit files and not release the source code,
 --      as long as it attaches to an ADI device.
 --
diff --git a/adi_library/axi_intr_monitor/axi_intr_monitor.v b/adi_library/axi_intr_monitor/axi_intr_monitor.v
index 0b01628f..087091e2 100644
--- a/adi_library/axi_intr_monitor/axi_intr_monitor.v
+++ b/adi_library/axi_intr_monitor/axi_intr_monitor.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_intr_monitor/axi_intr_monitor.xpr b/adi_library/axi_intr_monitor/axi_intr_monitor.xpr
index a67f5463..bed3f925 100644
--- a/adi_library/axi_intr_monitor/axi_intr_monitor.xpr
+++ b/adi_library/axi_intr_monitor/axi_intr_monitor.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_intr_monitor/axi_intr_monitor.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_intr_monitor/axi_intr_monitor.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="9419511dbcc74c8189c1658463373f4e"/>
+    <Option Name="Id" Val="97378fefc76847e6920ccc5cebbe2b2b"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -161,21 +160,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -188,7 +187,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_intr_monitor/component.xml b/adi_library/axi_intr_monitor/component.xml
index 32eef112..5b76080f 100644
--- a/adi_library/axi_intr_monitor/component.xml
+++ b/adi_library/axi_intr_monitor/component.xml
@@ -263,7 +263,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>0f4cf392</spirit:value>
+            <spirit:value>bac48bd3</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -279,7 +279,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>0f4cf392</spirit:value>
+            <spirit:value>bac48bd3</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -687,7 +687,7 @@
       <spirit:file>
         <spirit:name>axi_intr_monitor.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_23db8f82</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_129e9f47</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -761,11 +761,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:47:44Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:04:03Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="593a80b0"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="450d62e4"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="01cdae58"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="5414f83b"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="d9cbcb22"/>
diff --git a/adi_library/axi_laser_driver/axi_laser_driver.v b/adi_library/axi_laser_driver/axi_laser_driver.v
index 1bf55198..1df9c4d7 100644
--- a/adi_library/axi_laser_driver/axi_laser_driver.v
+++ b/adi_library/axi_laser_driver/axi_laser_driver.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_laser_driver/axi_laser_driver.xpr b/adi_library/axi_laser_driver/axi_laser_driver.xpr
index e91e80b9..738432d4 100644
--- a/adi_library/axi_laser_driver/axi_laser_driver.xpr
+++ b/adi_library/axi_laser_driver/axi_laser_driver.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_laser_driver/axi_laser_driver.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_laser_driver/axi_laser_driver.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="37e97e8fbf9e44048b20b66a3b884d48"/>
+    <Option Name="Id" Val="098412c6424242d58499084a899f909c"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -180,21 +179,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -207,7 +206,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_laser_driver/axi_laser_driver_regmap.v b/adi_library/axi_laser_driver/axi_laser_driver_regmap.v
index fb84faec..19fa859d 100644
--- a/adi_library/axi_laser_driver/axi_laser_driver_regmap.v
+++ b/adi_library/axi_laser_driver/axi_laser_driver_regmap.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_laser_driver/component.xml b/adi_library/axi_laser_driver/component.xml
index f09e9988..a9240052 100644
--- a/adi_library/axi_laser_driver/component.xml
+++ b/adi_library/axi_laser_driver/component.xml
@@ -263,7 +263,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>6f3005fd</spirit:value>
+            <spirit:value>9ad4be01</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -285,7 +285,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>0bdfec18</spirit:value>
+            <spirit:value>00415fe6</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -815,7 +815,7 @@
       <spirit:file>
         <spirit:name>axi_laser_driver.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_8a5a13b8</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_8423da2b</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -964,11 +964,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_laser_driver</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:48:03Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:04:23Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="af7c6ecb"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="291ddafc"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="8e123016"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="1e6bc47d"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="606451f8"/>
diff --git a/adi_library/axi_logic_analyzer/axi_logic_analyzer.v b/adi_library/axi_logic_analyzer/axi_logic_analyzer.v
index 64be9645..f4860718 100644
--- a/adi_library/axi_logic_analyzer/axi_logic_analyzer.v
+++ b/adi_library/axi_logic_analyzer/axi_logic_analyzer.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -90,6 +90,7 @@ module axi_logic_analyzer (
   // internal registers
 
   reg     [15:0]    data_r = 'd0;
+  reg     [15:0]    data_src_select = 'd0;
   reg     [ 1:0]    trigger_m1 = 'd0;
   reg     [31:0]    downsampler_counter_la = 'd0;
   reg     [31:0]    upsampler_counter_pg = 'd0;
@@ -238,11 +239,22 @@ module axi_logic_analyzer (
   for (i = 0 ; i < 16; i = i + 1) begin
     assign data_t[i] = od_pp_n[i] ? io_selection[i] | data_o[i] : io_selection[i];
     always @(posedge clk_out) begin
-      data_o[i] <= overwrite_enable[i] ? overwrite_data[i] : data_r[i];
+      data_o[i] <= data_src_select[i] ? overwrite_data[i] : data_r[i];
     end
+
+    always @(posedge clk_out) begin
+      data_src_select[i] <= data_src_select[i] ?
+              (~dac_valid) | overwrite_enable[i]:
+              overwrite_enable[i];
+    end
+
     always @(posedge clk_out) begin
       if(dac_valid == 1'b1) begin
         data_r[i] <= dac_data[i];
+      end else begin
+        if (data_src_select[i] == 1'b1) begin
+          data_r[i] <= overwrite_data[i];
+        end
       end
       if (io_selection_s[i] == 1'b1) begin
         io_selection[i] <= 1'b1;
diff --git a/adi_library/axi_logic_analyzer/axi_logic_analyzer.xpr b/adi_library/axi_logic_analyzer/axi_logic_analyzer.xpr
index 50bbd119..15570103 100644
--- a/adi_library/axi_logic_analyzer/axi_logic_analyzer.xpr
+++ b/adi_library/axi_logic_analyzer/axi_logic_analyzer.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_logic_analyzer/axi_logic_analyzer.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_logic_analyzer/axi_logic_analyzer.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="064d702b8d7042568c313ac549b03a87"/>
+    <Option Name="Id" Val="9345d9a465ec4b098a3e959f234effac"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -220,21 +219,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -247,7 +246,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_logic_analyzer/axi_logic_analyzer_reg.v b/adi_library/axi_logic_analyzer/axi_logic_analyzer_reg.v
index 5b860b8f..ba00330d 100644
--- a/adi_library/axi_logic_analyzer/axi_logic_analyzer_reg.v
+++ b/adi_library/axi_logic_analyzer/axi_logic_analyzer_reg.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_logic_analyzer/axi_logic_analyzer_trigger.v b/adi_library/axi_logic_analyzer/axi_logic_analyzer_trigger.v
index 38293dfa..704eb4a7 100644
--- a/adi_library/axi_logic_analyzer/axi_logic_analyzer_trigger.v
+++ b/adi_library/axi_logic_analyzer/axi_logic_analyzer_trigger.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_logic_analyzer/component.xml b/adi_library/axi_logic_analyzer/component.xml
index 6223a54a..27471efd 100644
--- a/adi_library/axi_logic_analyzer/component.xml
+++ b/adi_library/axi_logic_analyzer/component.xml
@@ -273,7 +273,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>b8e921af</spirit:value>
+            <spirit:value>2ac17036</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -289,7 +289,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>ed2a0402</spirit:value>
+            <spirit:value>5175c850</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -978,7 +978,7 @@
       <spirit:file>
         <spirit:name>axi_logic_analyzer.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_27451ef3</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_71f26528</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1067,11 +1067,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_logic_analyzer</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:48:14Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:04:35Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="adb3fdb4"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="5629cfe1"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="5d21c089"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="f8c6ea90"/>
     </xilinx:packagingInfo>
diff --git a/adi_library/axi_ltc235x/axi_ltc235x.v b/adi_library/axi_ltc235x/axi_ltc235x.v
index 999be47d..d8194506 100644
--- a/adi_library/axi_ltc235x/axi_ltc235x.v
+++ b/adi_library/axi_ltc235x/axi_ltc235x.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ltc235x/axi_ltc235x_cmos.v b/adi_library/axi_ltc235x/axi_ltc235x_cmos.v
index 1eedd7ef..32c8b546 100644
--- a/adi_library/axi_ltc235x/axi_ltc235x_cmos.v
+++ b/adi_library/axi_ltc235x/axi_ltc235x_cmos.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ltc235x/axi_ltc235x_lvds.v b/adi_library/axi_ltc235x/axi_ltc235x_lvds.v
index ba5adb3a..47b10826 100644
--- a/adi_library/axi_ltc235x/axi_ltc235x_lvds.v
+++ b/adi_library/axi_ltc235x/axi_ltc235x_lvds.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ltc2387/axi_ltc2387.v b/adi_library/axi_ltc2387/axi_ltc2387.v
index 11aec198..93fa1d3a 100644
--- a/adi_library/axi_ltc2387/axi_ltc2387.v
+++ b/adi_library/axi_ltc2387/axi_ltc2387.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ltc2387/axi_ltc2387.xpr b/adi_library/axi_ltc2387/axi_ltc2387.xpr
index ad9ed70e..b33b4d1c 100644
--- a/adi_library/axi_ltc2387/axi_ltc2387.xpr
+++ b/adi_library/axi_ltc2387/axi_ltc2387.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_ltc2387/axi_ltc2387.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_ltc2387/axi_ltc2387.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="e25bfd3e41704cb68e3f927df2ba1fe6"/>
+    <Option Name="Id" Val="5c0472859f2a455c9e9178e6ccdbd6f4"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -270,21 +269,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -297,7 +296,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_ltc2387/axi_ltc2387_channel.v b/adi_library/axi_ltc2387/axi_ltc2387_channel.v
index 8bad30f6..dd2c9bcd 100644
--- a/adi_library/axi_ltc2387/axi_ltc2387_channel.v
+++ b/adi_library/axi_ltc2387/axi_ltc2387_channel.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_ltc2387/axi_ltc2387_if.v b/adi_library/axi_ltc2387/axi_ltc2387_if.v
index 0efd5e1f..62098a58 100644
--- a/adi_library/axi_ltc2387/axi_ltc2387_if.v
+++ b/adi_library/axi_ltc2387/axi_ltc2387_if.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -68,7 +68,7 @@ module axi_ltc2387_if #(
   input             db_p,
   input             db_n,
 
-  output            adc_valid,
+  output reg                  adc_valid,
   output reg [RESOLUTION-1:0] adc_data
 );
 
@@ -96,16 +96,16 @@ module axi_ltc2387_if #(
 
   // assignments
 
-  // adc_valid is 1 for the current sample that is sent
-  assign adc_valid = clk_gate_d[1] & ~clk_gate_d[0];
-
   always @(posedge clk) begin
+    adc_valid <= 1'b0;
     clk_gate_d <= {clk_gate_d[1:0], clk_gate};
     if (clk_gate_d[1] == 1'b1 && clk_gate_d[0] == 1'b0) begin
       if (RESOLUTION == 18) begin
         adc_data <= adc_data_int;
+        adc_valid <= 1'b1;
       end else begin
         adc_data <= adc_data_int[15:0];
+        adc_valid <= 1'b1;
       end
     end
   end
diff --git a/adi_library/axi_ltc2387/component.xml b/adi_library/axi_ltc2387/component.xml
index 1dc87934..09041f56 100644
--- a/adi_library/axi_ltc2387/component.xml
+++ b/adi_library/axi_ltc2387/component.xml
@@ -289,7 +289,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>d5c839f9</spirit:value>
+            <spirit:value>e5bf14d1</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -305,7 +305,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>cd03700f</spirit:value>
+            <spirit:value>8f1d332f</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -988,7 +988,7 @@
       <spirit:file>
         <spirit:name>axi_ltc2387.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_e2e76c94</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_fe622ad0</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1171,11 +1171,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:48:30Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:04:53Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="6ea2d81b"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="5f77ba11"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="1ffb8865"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="20607794"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="f17ef611"/>
diff --git a/adi_library/axi_pulsar_lvds/Makefile b/adi_library/axi_pulsar_lvds/Makefile
new file mode 100755
index 00000000..50042da0
--- /dev/null
+++ b/adi_library/axi_pulsar_lvds/Makefile
@@ -0,0 +1,30 @@
+####################################################################################
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+LIBRARY_NAME := axi_pulsar_lvds
+
+GENERIC_DEPS += ../common/ad_datafmt.v
+GENERIC_DEPS += ../common/ad_rst.v
+GENERIC_DEPS += ../common/up_adc_channel.v
+GENERIC_DEPS += ../common/up_adc_common.v
+GENERIC_DEPS += ../common/up_axi.v
+GENERIC_DEPS += ../common/up_clock_mon.v
+GENERIC_DEPS += ../common/up_delay_cntrl.v
+GENERIC_DEPS += ../common/up_xfer_cntrl.v
+GENERIC_DEPS += ../common/up_xfer_status.v
+GENERIC_DEPS += axi_pulsar_lvds.v
+GENERIC_DEPS += axi_pulsar_lvds_channel.v
+GENERIC_DEPS += axi_pulsar_lvds_if.v
+
+XILINX_DEPS += ../xilinx/common/ad_data_clk.v
+XILINX_DEPS += ../xilinx/common/ad_data_in.v
+XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
+XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
+XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
+XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
+XILINX_DEPS += axi_pulsar_lvds_ip.tcl
+
+include ../scripts/library.mk
diff --git a/adi_library/axi_pulsar_lvds/axi_pulsar_lvds.v b/adi_library/axi_pulsar_lvds/axi_pulsar_lvds.v
new file mode 100755
index 00000000..bbb77531
--- /dev/null
+++ b/adi_library/axi_pulsar_lvds/axi_pulsar_lvds.v
@@ -0,0 +1,332 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_pulsar_lvds #(
+  parameter ID = 0,
+  parameter FPGA_TECHNOLOGY = 0,
+  parameter FPGA_FAMILY = 0,
+  parameter SPEED_GRADE = 0,
+  parameter DEV_PACKAGE = 0,
+  parameter IO_DELAY_GROUP = "adc_if_delay_group",
+  parameter IODELAY_CTRL = 1,
+  parameter DELAY_REFCLK_FREQUENCY = 200,
+  parameter USERPORTS_DISABLE = 0,
+  parameter DATAFORMAT_DISABLE = 0,
+  parameter ADC_INIT_DELAY = 0,
+  parameter ADC_DATA_WIDTH = 16,
+  parameter BITS_PER_SAMPLE = 32
+) (
+  input         delay_clk,
+
+  // adc interface
+
+  input         ref_clk,
+  input         clk_gate,
+  input         dco_p,
+  input         dco_n,
+  input         d_p,
+  input         d_n,
+
+  // dma interface
+
+  output        adc_valid,
+  output [BITS_PER_SAMPLE-1:0] adc_data,
+  input         adc_dovf,
+
+  // axi interface
+
+  input         s_axi_aclk,
+  input         s_axi_aresetn,
+  input         s_axi_awvalid,
+  input  [15:0] s_axi_awaddr,
+  output        s_axi_awready,
+  input         s_axi_wvalid,
+  input  [31:0] s_axi_wdata,
+  input  [ 3:0] s_axi_wstrb,
+  output        s_axi_wready,
+  output        s_axi_bvalid,
+  output [ 1:0] s_axi_bresp,
+  input         s_axi_bready,
+  input         s_axi_arvalid,
+  input  [15:0] s_axi_araddr,
+  output        s_axi_arready,
+  output        s_axi_rvalid,
+  output [ 1:0] s_axi_rresp,
+  output [31:0] s_axi_rdata,
+  input         s_axi_rready,
+  input  [ 2:0] s_axi_awprot,
+  input  [ 2:0] s_axi_arprot
+);
+
+  // internal signals
+
+  wire [(ADC_DATA_WIDTH-1):0] adc_data_s;
+  wire        adc_or_s;
+  wire [ 1:0] up_dld_s;
+  wire [ 9:0] up_dwdata_s;
+  wire [ 9:0] up_drdata_s;
+  wire        delay_locked_s;
+  wire        up_status_pn_err_s;
+  wire        up_status_pn_oos_s;
+  wire        up_status_or_s;
+  wire        up_rreq_s;
+  wire [13:0] up_raddr_s;
+  wire [31:0] up_rdata_s[0:2];
+  wire        up_rack_s[0:2];
+  wire        up_wack_s[0:2];
+  wire        up_wreq_s;
+  wire [13:0] up_waddr_s;
+  wire [31:0] up_wdata_s;
+
+  // internal registers
+
+  reg         up_wack  = 'd0;
+  reg  [31:0] up_rdata = 'd0;
+  reg         up_rack  = 'd0;
+
+  // internal signals
+
+  wire        adc_rst;
+  wire        adc_clk;
+  wire        adc_enable;
+  wire        up_clk;
+  wire        up_rstn;
+  wire        delay_rst;
+  wire        adc_valid_ch_s;
+  wire [(ADC_DATA_WIDTH-1):0] adc_data_ch_s;
+
+  // signal name changes
+
+  assign up_clk  = s_axi_aclk;
+  assign up_rstn = s_axi_aresetn;
+  assign adc_clk = ref_clk;
+
+  // processor read interface
+
+  always @(negedge up_rstn or posedge up_clk) begin
+    if (!up_rstn) begin
+      up_rdata <= 32'd0;
+      up_rack <= 1'd0;
+      up_wack <= 1'd0;
+    end else begin
+      up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
+      up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2];
+      up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2];
+    end
+  end
+
+  // main (device interface)
+
+  axi_pulsar_lvds_if #(
+    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
+    .IO_DELAY_GROUP (IO_DELAY_GROUP),
+    .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY),
+    .IODELAY_CTRL (IODELAY_CTRL),
+    .ADC_DATA_WIDTH (ADC_DATA_WIDTH)
+  ) axi_pulsar_lvds_if_inst (
+    .up_clk(up_clk),
+    .up_dld(up_dld_s),
+    .up_dwdata(up_dwdata_s),
+    .up_drdata(up_drdata_s),
+    .delay_clk(delay_clk),
+    .delay_rst(delay_rst),
+    .delay_locked(delay_locked_s),
+    .clk(ref_clk),
+    .clk_gate(clk_gate),
+    .dco_p(dco_p),
+    .dco_n(dco_n),
+    .d_p(d_p),
+    .d_n(d_n),
+    .adc_valid(adc_valid_ch_s),
+    .adc_data(adc_data_ch_s));
+
+  // channel
+
+  axi_pulsar_lvds_channel #(
+    .USERPORTS_DISABLE (USERPORTS_DISABLE),
+    .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
+    .ADC_DATA_WIDTH (ADC_DATA_WIDTH),
+    .BITS_PER_SAMPLE (BITS_PER_SAMPLE)
+  ) i_channel (
+    .adc_clk (adc_clk),
+    .adc_rst (adc_rst),
+    .adc_data_in (adc_data_ch_s),
+    .adc_valid_in (adc_valid_ch_s),
+    .adc_enable (adc_enable),
+    .adc_valid (adc_valid),
+    .adc_data (adc_data),
+    .up_adc_pn_err (up_status_pn_err_s),
+    .up_adc_pn_oos (up_status_pn_oos_s),
+    .up_adc_or (up_status_or_s),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack_s[0]),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata_s[0]),
+    .up_rack (up_rack_s[0]));
+
+  // adc delay control
+
+  up_delay_cntrl #(
+    .INIT_DELAY (ADC_INIT_DELAY),
+    .DATA_WIDTH (2),
+    .BASE_ADDRESS (6'h02)
+  ) i_delay_cntrl (
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked (delay_locked_s),
+    .up_dld (up_dld_s),
+    .up_dwdata (up_dwdata_s),
+    .up_drdata (up_drdata_s),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack_s[2]),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata_s[2]),
+    .up_rack (up_rack_s[2]));
+
+  // common processor control
+
+  up_adc_common #(
+    .ID (ID),
+    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
+    .FPGA_FAMILY (FPGA_FAMILY),
+    .SPEED_GRADE (SPEED_GRADE),
+    .DEV_PACKAGE (DEV_PACKAGE),
+    .CONFIG (0),
+    .COMMON_ID (6'h00),
+    .DRP_DISABLE (6'h00),
+    .USERPORTS_DISABLE (USERPORTS_DISABLE),
+    .GPIO_DISABLE (0),
+    .START_CODE_DISABLE (0)
+  ) i_up_adc_common (
+    .mmcm_rst (),
+    .adc_clk (adc_clk),
+    .adc_rst (adc_rst),
+    .adc_r1_mode (),
+    .adc_ddr_edgesel (),
+    .adc_pin_mode (),
+    .adc_status (delay_locked_s),
+    .adc_sync_status (1'd0),
+    .adc_status_ovf (adc_dovf),
+    .adc_clk_ratio (32'b1),
+    .adc_start_code (),
+    .adc_sref_sync (),
+    .adc_sync (),
+    .adc_ext_sync_arm(),
+    .adc_ext_sync_disarm(),
+    .adc_ext_sync_manual_req(),
+    .adc_num_lanes (),
+    .adc_custom_control(),
+    .adc_crc_enable (),
+    .adc_sdr_ddr_n (),
+    .adc_symb_op (),
+    .adc_symb_8_16b (),
+    .up_pps_rcounter (32'd0),
+    .up_pps_status (1'd0),
+    .up_pps_irq_mask (),
+    .up_adc_r1_mode (),
+    .up_adc_ce (),
+    .up_status_pn_err (up_status_pn_err_s),
+    .up_status_pn_oos (up_status_pn_oos_s),
+    .up_status_or (up_status_or_s),
+    .up_drp_sel (),
+    .up_drp_wr (),
+    .up_drp_addr (),
+    .up_drp_wdata (),
+    .up_drp_rdata (32'b0),
+    .up_drp_ready (1'b0),
+    .up_drp_locked (1'b1),
+    .adc_config_wr (),
+    .adc_config_ctrl (),
+    .adc_config_rd ('d0),
+    .adc_ctrl_status ('d0),
+    .up_usr_chanmax_out (),
+    .up_usr_chanmax_in (8'd1),
+    .up_adc_gpio_in (32'd0),
+    .up_adc_gpio_out (),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack_s[1]),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata_s[1]),
+    .up_rack (up_rack_s[1]));
+
+  // up bus interface
+
+  up_axi i_up_axi (
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_axi_awvalid (s_axi_awvalid),
+    .up_axi_awaddr (s_axi_awaddr),
+    .up_axi_awready (s_axi_awready),
+    .up_axi_wvalid (s_axi_wvalid),
+    .up_axi_wdata (s_axi_wdata),
+    .up_axi_wstrb (s_axi_wstrb),
+    .up_axi_wready (s_axi_wready),
+    .up_axi_bvalid (s_axi_bvalid),
+    .up_axi_bresp (s_axi_bresp),
+    .up_axi_bready (s_axi_bready),
+    .up_axi_arvalid (s_axi_arvalid),
+    .up_axi_araddr (s_axi_araddr),
+    .up_axi_arready (s_axi_arready),
+    .up_axi_rvalid (s_axi_rvalid),
+    .up_axi_rresp (s_axi_rresp),
+    .up_axi_rdata (s_axi_rdata),
+    .up_axi_rready (s_axi_rready),
+    .up_wreq (up_wreq_s),
+    .up_waddr (up_waddr_s),
+    .up_wdata (up_wdata_s),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq_s),
+    .up_raddr (up_raddr_s),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+endmodule
diff --git a/adi_library/axi_pulsar_lvds/axi_pulsar_lvds.xpr b/adi_library/axi_pulsar_lvds/axi_pulsar_lvds.xpr
new file mode 100644
index 00000000..cf59dfff
--- /dev/null
+++ b/adi_library/axi_pulsar_lvds/axi_pulsar_lvds.xpr
@@ -0,0 +1,521 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
+<!--                                                                         -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_pulsar_lvds/axi_pulsar_lvds.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="1b91a4c235304c758d4818857cba9ebb"/>
+    <Option Name="Part" Val="xc7vx485tffg1157-1"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
+    <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
+    <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
+    <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
+    <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
+    <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
+    <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+    <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+    <Option Name="BoardPart" Val=""/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPRepoPath" Val="$PPRDIR/../../library"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="EnableResourceEstimation" Val="FALSE"/>
+    <Option Name="SimCompileState" Val="TRUE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+    <Option Name="ClassicSocBoot" Val="FALSE"/>
+    <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+  </Configuration>
+  <FileSets Version="1" Minor="32">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/../xilinx/common/ad_data_in.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../common/ad_datafmt.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../common/ad_rst.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/axi_pulsar_lvds_channel.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/axi_pulsar_lvds_if.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../common/up_adc_channel.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../common/up_adc_common.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../common/up_axi.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../common/up_clock_mon.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../common/up_delay_cntrl.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../common/up_xfer_cntrl.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../common/up_xfer_status.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/axi_pulsar_lvds.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../xilinx/common/ad_data_clk.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/component.xml">
+        <FileInfo SFType="IPXACT"/>
+      </File>
+      <File Path="$PPRDIR/bd/bd.tcl">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="axi_pulsar_lvds"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PPRDIR/../xilinx/common/up_xfer_cntrl_constr.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../xilinx/common/ad_rst_constr.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../xilinx/common/up_clock_mon_constr.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../xilinx/common/up_xfer_status_constr.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Xcelium">
+      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="WARNING"/>
+    <MsgAttr Name="Id" Val="Vivado 12-1790"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="1"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+    <MsgAttr Name="StringsToMatch" Val="Evaluation"/>
+    <MsgAttr Name="StringsToMatch" Val="features"/>
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+    <MsgAttr Name="StringsToMatch" Val="used"/>
+    <MsgAttr Name="StringsToMatch" Val="in"/>
+    <MsgAttr Name="StringsToMatch" Val="production"/>
+    <MsgAttr Name="StringsToMatch" Val="systems."/>
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+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="INFO"/>
+    <MsgAttr Name="Id" Val="Designutils 20-3303"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="10"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+    <MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="WARNING"/>
+    <MsgAttr Name="Id" Val="Place 30-73"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="11"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+    <MsgAttr Name="StringsToMatch" Val="axi_spi"/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="WARNING"/>
+    <MsgAttr Name="Id" Val=""/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="12"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+    <MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="WARNING"/>
+    <MsgAttr Name="Id" Val="BD 41-1343"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="2"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="WARNING"/>
+    <MsgAttr Name="Id" Val="BD 41-1306"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="3"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="ERROR"/>
+    <MsgAttr Name="Id" Val="BD 41-1276"/>
+    <MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="4"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="INFO"/>
+    <MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="5"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="INFO"/>
+    <MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="6"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="INFO"/>
+    <MsgAttr Name="Id" Val="IP_Flow 19-459"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="7"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="INFO"/>
+    <MsgAttr Name="Id" Val="Synth 8-3331"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="8"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="WARNING"/>
+    <MsgAttr Name="Id" Val="Synth 8-2490"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="9"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <Board/>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>
diff --git a/adi_library/axi_pulsar_lvds/axi_pulsar_lvds_channel.v b/adi_library/axi_pulsar_lvds/axi_pulsar_lvds_channel.v
new file mode 100755
index 00000000..742dc843
--- /dev/null
+++ b/adi_library/axi_pulsar_lvds/axi_pulsar_lvds_channel.v
@@ -0,0 +1,168 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module axi_pulsar_lvds_channel #(
+  parameter USERPORTS_DISABLE = 0,
+  parameter DATAFORMAT_DISABLE = 0,
+  parameter ADC_DATA_WIDTH = 16,
+  parameter BITS_PER_SAMPLE = 32
+) (
+
+  // adc interface
+
+  input         adc_clk,
+  input         adc_rst,
+  input         adc_valid_in,
+  input  [18:0] adc_data_in,
+
+  // dma interface
+
+  output        adc_enable,
+  output        adc_valid,
+  output [BITS_PER_SAMPLE-1:0] adc_data,
+
+  // error monitoring
+
+  output        up_adc_pn_err,
+  output        up_adc_pn_oos,
+  output        up_adc_or,
+
+  // processor interface
+
+  input         up_rstn,
+  input         up_clk,
+  input         up_wreq,
+  input  [13:0] up_waddr,
+  input  [31:0] up_wdata,
+  output        up_wack,
+  input         up_rreq,
+  input  [13:0] up_raddr,
+  output [31:0] up_rdata,
+  output        up_rack
+);
+
+  // internal signals
+
+  wire        adc_dfmt_valid_s;
+  wire [(ADC_DATA_WIDTH-1):0] adc_dfmt_data_s;
+  wire        adc_dcfilter_valid_s;
+  wire        adc_iqcor_enb_s;
+  wire        adc_dcfilt_enb_s;
+  wire        adc_dfmt_se_s;
+  wire        adc_dfmt_type_s;
+  wire        adc_dfmt_enable_s;
+  wire [15:0] adc_dcfilt_offset_s;
+  wire [15:0] adc_dcfilt_coeff_s;
+  wire [15:0] adc_iqcor_coeff_1_s;
+  wire [15:0] adc_iqcor_coeff_2_s;
+  wire [ 3:0] adc_pnseq_sel_s;
+  wire [ 3:0] adc_data_sel_s;
+
+  ad_datafmt #(
+    .DATA_WIDTH (ADC_DATA_WIDTH),
+    .BITS_PER_SAMPLE (BITS_PER_SAMPLE),
+    .DISABLE (DATAFORMAT_DISABLE)
+  ) i_ad_datafmt (
+    .clk (adc_clk),
+    .valid (adc_valid_in),
+    .data (adc_data_in),
+    .valid_out (adc_valid),
+    .data_out (adc_data),
+    .dfmt_enable (adc_dfmt_enable_s),
+    .dfmt_type (adc_dfmt_type_s),
+    .dfmt_se (adc_dfmt_se_s));
+
+  // adc channel regmap
+
+  up_adc_channel #(
+    .CHANNEL_ID (0),
+    .USERPORTS_DISABLE (USERPORTS_DISABLE),
+    .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE),
+    .DCFILTER_DISABLE (1'b1),
+    .IQCORRECTION_DISABLE (1'b1)
+  ) i_up_adc_channel (
+    .adc_clk (adc_clk),
+    .adc_rst (adc_rst),
+    .adc_enable (adc_enable),
+    .adc_iqcor_enb (adc_iqcor_enb_s),
+    .adc_dcfilt_enb (adc_dcfilt_enb_s),
+    .adc_dfmt_se (adc_dfmt_se_s),
+    .adc_dfmt_type (adc_dfmt_type_s),
+    .adc_dfmt_enable (adc_dfmt_enable_s),
+    .adc_dcfilt_offset (adc_dcfilt_offset_s),
+    .adc_dcfilt_coeff (adc_dcfilt_coeff_s),
+    .adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s),
+    .adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s),
+    .adc_pnseq_sel (adc_pnseq_sel_s),
+    .adc_data_sel (),
+    .adc_pn_err (),
+    .adc_pn_oos (1'b0),
+    .adc_or (1'b0),
+    .adc_read_data ('d0),
+    .adc_status_header ('d0),
+    .adc_crc_err ('d0),
+    .adc_softspan (),
+    .up_adc_crc_err (),
+    .up_adc_pn_err (up_adc_pn_err),
+    .up_adc_pn_oos (up_adc_pn_oos),
+    .up_adc_or (up_adc_or),
+    .up_usr_datatype_be (),
+    .up_usr_datatype_signed (),
+    .up_usr_datatype_shift (),
+    .up_usr_datatype_total_bits (),
+    .up_usr_datatype_bits (),
+    .up_usr_decimation_m (),
+    .up_usr_decimation_n (),
+    .adc_usr_datatype_be (1'b0),
+    .adc_usr_datatype_signed (1'b1),
+    .adc_usr_datatype_shift (8'd0),
+    .adc_usr_datatype_total_bits (8'd16),
+    .adc_usr_datatype_bits (8'd16),
+    .adc_usr_decimation_m (16'd1),
+    .adc_usr_decimation_n (16'd1),
+    .up_rstn (up_rstn),
+    .up_clk (up_clk),
+    .up_wreq (up_wreq),
+    .up_waddr (up_waddr),
+    .up_wdata (up_wdata),
+    .up_wack (up_wack),
+    .up_rreq (up_rreq),
+    .up_raddr (up_raddr),
+    .up_rdata (up_rdata),
+    .up_rack (up_rack));
+
+endmodule
diff --git a/adi_library/axi_pulsar_lvds/axi_pulsar_lvds_if.v b/adi_library/axi_pulsar_lvds/axi_pulsar_lvds_if.v
new file mode 100755
index 00000000..1910ff9a
--- /dev/null
+++ b/adi_library/axi_pulsar_lvds/axi_pulsar_lvds_if.v
@@ -0,0 +1,132 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+// This is the LVDS/DDR interface, note that overrange is independent of data path,
+// software will not be able to relate overrange to a specific sample!
+
+`timescale 1ns/100ps
+
+module axi_pulsar_lvds_if #(
+
+  parameter FPGA_TECHNOLOGY = 1,
+  parameter IO_DELAY_GROUP = "adc_if_delay_group",
+  parameter IODELAY_CTRL = 1,
+  parameter DELAY_REFCLK_FREQUENCY = 200,
+  parameter ADC_DATA_WIDTH = 16
+) (
+
+  // delay interface
+
+  input         up_clk,
+  input  [ 1:0] up_dld,
+  input  [ 9:0] up_dwdata,
+  output [ 9:0] up_drdata,
+  input         delay_clk,
+  input         delay_rst,
+  output        delay_locked,
+
+  // adc interface
+
+  input         clk,
+  input         clk_gate,
+  input         dco_p,
+  input         dco_n,
+  input         d_p,
+  input         d_n,
+
+  output reg                        adc_valid,
+  output reg [(ADC_DATA_WIDTH-1):0] adc_data
+);
+
+  // internal wires
+
+  wire          d_p_int_s;
+  wire          dco;
+  wire          dco_s;
+
+  // internal register
+
+  reg [ 1:0]                 clk_gate_d    = 'b0;
+  reg [(ADC_DATA_WIDTH-1):0] adc_data_int  = 'b0;
+
+  // adc_valid is 1 for the current sample that is sent
+
+  always @(posedge clk) begin
+    adc_valid <= 1'b0;
+    clk_gate_d <= {clk_gate_d[0], clk_gate};
+    if (clk_gate_d[1] == 1'b1 && clk_gate_d[0] == 1'b0) begin
+      adc_data  <= adc_data_int;
+      adc_valid <= 1'b1;
+    end
+  end
+
+  always @(posedge dco) begin
+    adc_data_int <= {adc_data_int[(ADC_DATA_WIDTH-2):0], d_p_int_s};
+  end
+
+  // data interface - differential to single ended
+
+  ad_data_in #(
+    .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
+    .IDDR_CLK_EDGE ("OPPOSITE_EDGE"),
+    .IODELAY_CTRL (IODELAY_CTRL),
+    .IODELAY_GROUP (IO_DELAY_GROUP),
+    .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY),
+    .DDR_SDR_N(0)
+  ) i_rx_da (
+    .rx_clk (dco),
+    .rx_data_in_p (d_p),
+    .rx_data_in_n (d_n),
+    .rx_data_p (d_p_int_s),
+    .rx_data_n (),
+    .up_clk (up_clk),
+    .up_dld (up_dld[0]),
+    .up_dwdata (up_dwdata[4:0]),
+    .up_drdata (up_drdata[4:0]),
+    .delay_clk (delay_clk),
+    .delay_rst (delay_rst),
+    .delay_locked (delay_locked));
+
+  // clock
+
+  IBUFDS i_rx_clk_ibuf (
+    .I (dco_p),
+    .IB(dco_n),
+    .O (dco_s));
+
+  BUFH i_clk_buf (
+    .I (dco_s),
+    .O (dco));
+
+endmodule
diff --git a/adi_library/axi_pulsar_lvds/axi_pulsar_lvds_ip.tcl b/adi_library/axi_pulsar_lvds/axi_pulsar_lvds_ip.tcl
new file mode 100755
index 00000000..0fecc6c7
--- /dev/null
+++ b/adi_library/axi_pulsar_lvds/axi_pulsar_lvds_ip.tcl
@@ -0,0 +1,55 @@
+###############################################################################
+## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source ../../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
+
+adi_ip_create axi_pulsar_lvds
+
+adi_ip_files axi_pulsar_lvds [list \
+  "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \
+  "$ad_hdl_dir/library/common/up_adc_common.v" \
+  "$ad_hdl_dir/library/common/up_adc_channel.v" \
+  "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
+  "$ad_hdl_dir/library/common/up_xfer_status.v" \
+  "$ad_hdl_dir/library/common/up_clock_mon.v" \
+  "$ad_hdl_dir/library/common/ad_datafmt.v" \
+  "$ad_hdl_dir/library/common/ad_rst.v" \
+  "$ad_hdl_dir/library/common/up_delay_cntrl.v" \
+  "$ad_hdl_dir/library/common/up_axi.v" \
+  "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
+  "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
+  "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
+  "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
+  "axi_pulsar_lvds_if.v" \
+  "axi_pulsar_lvds_channel.v" \
+  "axi_pulsar_lvds.v" ]
+
+adi_ip_properties axi_pulsar_lvds
+
+adi_add_bus "fifo_wr" "master" \
+        "analog.com:interface:fifo_wr_rtl:1.0" \
+        "analog.com:interface:fifo_wr:1.0" \
+        { \
+                {"adc_valid" "EN"} \
+                {"adc_data" "DATA"} \
+                {"adc_dovf" "OVERFLOW"} \
+        }
+adi_add_bus_clock "fifo_wr_clk" "fifo_wr"
+
+adi_init_bd_tcl
+adi_ip_bd axi_pulsar_lvds "bd/bd.tcl"
+
+set cc [ipx::current_core]
+
+ipx::infer_bus_interface ref_clk xilinx.com:signal:clock_rtl:1.0   $cc
+ipx::infer_bus_interface dco_p   xilinx.com:signal:clock_rtl:1.0   $cc
+ipx::infer_bus_interface dco_n   xilinx.com:signal:clock_rtl:1.0   $cc
+
+adi_add_auto_fpga_spec_params
+
+ipx::create_xgui_files $cc
+ipx::save_core $cc
diff --git a/adi_library/axi_pulsar_lvds/bd/bd.tcl b/adi_library/axi_pulsar_lvds/bd/bd.tcl
new file mode 100644
index 00000000..dceb9498
--- /dev/null
+++ b/adi_library/axi_pulsar_lvds/bd/bd.tcl
@@ -0,0 +1,47 @@
+# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!
+proc init {cellpath otherInfo} {
+  set ip [get_bd_cells $cellpath]
+
+  bd::mark_propagate_only $ip " \
+    DEV_PACKAGE \
+    SPEED_GRADE \
+    FPGA_FAMILY \
+    FPGA_TECHNOLOGY"
+
+  adi_auto_assign_device_spec $cellpath
+}
+
+# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)
+proc adi_auto_assign_device_spec {cellpath} {
+
+  set ip [get_bd_cells $cellpath]
+  set ip_param_list [list_property $ip]
+  set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]]
+
+  set parent_dir "../"
+  for {set x 1} {$x<=4} {incr x} {
+    set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl
+    if { [file exists $linkname] } {
+      source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl
+      break
+    }
+    append parent_dir "../"
+  }
+
+  # Find predefindes auto assignable parameters
+  foreach i $auto_set_param_list {
+    if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
+      set val [adi_device_spec $cellpath $i]
+      set_property CONFIG.$i $val $ip
+    }
+  }
+
+  # Find predefindes auto assignable/overwritable parameters
+  foreach i $auto_set_param_list_overwritable {
+    if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } {
+      set val [adi_device_spec $cellpath $i]
+      set_property CONFIG.$i $val $ip
+    }
+  }
+}
+
diff --git a/adi_library/axi_pulsar_lvds/component.xml b/adi_library/axi_pulsar_lvds/component.xml
new file mode 100644
index 00000000..e8b3d80d
--- /dev/null
+++ b/adi_library/axi_pulsar_lvds/component.xml
@@ -0,0 +1,1268 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>axi_pulsar_lvds</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>s_axi</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="s_axi"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>s_axi_aclk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_BUSIF">s_axi</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_RESET">s_axi_aresetn</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>s_axi_aresetn</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ARESETN.POLARITY" spirit:choiceRef="choice_list_74b5137e">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>fifo_wr</spirit:name>
+      <spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="fifo_wr" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="fifo_wr_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>EN</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>adc_valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>DATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>adc_data</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>OVERFLOW</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>adc_dovf</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>fifo_wr_signal_clock</spirit:name>
+      <spirit:displayName>fifo_wr_signal_clock</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>fifo_wr_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.FIFO_WR_SIGNAL_CLOCK.ASSOCIATED_BUSIF">fifo_wr</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>ref_clk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ref_clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>dco_p</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dco_p</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>dco_n</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>dco_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+  </spirit:busInterfaces>
+  <spirit:memoryMaps>
+    <spirit:memoryMap>
+      <spirit:name>s_axi</spirit:name>
+      <spirit:addressBlock>
+        <spirit:name>axi_lite</spirit:name>
+        <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+        <spirit:range spirit:format="long">65536</spirit:range>
+        <spirit:width spirit:format="long">0</spirit:width>
+      </spirit:addressBlock>
+    </spirit:memoryMap>
+  </spirit:memoryMaps>
+  <spirit:model>
+    <spirit:views>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+        <spirit:displayName>Synthesis</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+        <spirit:language>Verilog</spirit:language>
+        <spirit:modelName>axi_pulsar_lvds</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>75862dd0</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+        <spirit:displayName>Simulation</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+        <spirit:language>Verilog</spirit:language>
+        <spirit:modelName>axi_pulsar_lvds</spirit:modelName>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>2284fd30</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_xpgui</spirit:name>
+        <spirit:displayName>UI Layout</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+        <spirit:parameters>
+          <spirit:parameter>
+            <spirit:name>viewChecksum</spirit:name>
+            <spirit:value>747879b0</spirit:value>
+          </spirit:parameter>
+        </spirit:parameters>
+      </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_blockdiagram</spirit:name>
+        <spirit:displayName>Block Diagram</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:block.diagram</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_blockdiagram_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
+    </spirit:views>
+    <spirit:ports>
+      <spirit:port>
+        <spirit:name>delay_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>ref_clk</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>clk_gate</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>dco_p</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>dco_n</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>d_p</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>d_n</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>adc_valid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>std_logic</spirit:typeName>
+              <spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>adc_data</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
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+      <spirit:file>
+        <spirit:name>../xilinx/common/up_xfer_cntrl_constr.xdc</spirit:name>
+        <spirit:userFileType>xdc</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../xilinx/common/ad_rst_constr.xdc</spirit:name>
+        <spirit:userFileType>xdc</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../xilinx/common/up_clock_mon_constr.xdc</spirit:name>
+        <spirit:userFileType>xdc</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../xilinx/common/up_xfer_status_constr.xdc</spirit:name>
+        <spirit:userFileType>xdc</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../xilinx/common/ad_data_in.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../common/ad_datafmt.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../common/ad_rst.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>axi_pulsar_lvds_channel.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>axi_pulsar_lvds_if.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../common/up_adc_channel.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../common/up_adc_common.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../common/up_axi.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../common/up_clock_mon.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../common/up_delay_cntrl.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../common/up_xfer_cntrl.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../common/up_xfer_status.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>axi_pulsar_lvds.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_a103d085</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>../xilinx/common/ad_data_in.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../common/ad_datafmt.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../common/ad_rst.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>axi_pulsar_lvds_channel.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>axi_pulsar_lvds_if.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../common/up_adc_channel.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../common/up_adc_common.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../common/up_axi.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../common/up_clock_mon.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../common/up_delay_cntrl.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../common/up_xfer_cntrl.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>../common/up_xfer_status.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>axi_pulsar_lvds.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/axi_pulsar_lvds_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_7cc27ce2</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_blockdiagram_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>bd/bd.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>axi_pulsar_lvds_v1_0</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>ID</spirit:name>
+      <spirit:displayName>Id</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ID">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FPGA_TECHNOLOGY</spirit:name>
+      <spirit:displayName>Fpga Technology</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_TECHNOLOGY" spirit:choiceRef="choice_pairs_28f798a2">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FPGA_FAMILY</spirit:name>
+      <spirit:displayName>Fpga Family</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_a897e79d">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SPEED_GRADE</spirit:name>
+      <spirit:displayName>Speed Grade</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SPEED_GRADE" spirit:choiceRef="choice_pairs_19f99f31">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DEV_PACKAGE</spirit:name>
+      <spirit:displayName>Dev Package</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_a6e6e044">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IO_DELAY_GROUP</spirit:name>
+      <spirit:displayName>Io Delay Group</spirit:displayName>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.IO_DELAY_GROUP">adc_if_delay_group</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>IODELAY_CTRL</spirit:name>
+      <spirit:displayName>Iodelay Ctrl</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.IODELAY_CTRL">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DELAY_REFCLK_FREQUENCY</spirit:name>
+      <spirit:displayName>Delay Refclk Frequency</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DELAY_REFCLK_FREQUENCY">200</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>USERPORTS_DISABLE</spirit:name>
+      <spirit:displayName>Userports Disable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.USERPORTS_DISABLE">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>DATAFORMAT_DISABLE</spirit:name>
+      <spirit:displayName>Dataformat Disable</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DATAFORMAT_DISABLE">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ADC_INIT_DELAY</spirit:name>
+      <spirit:displayName>Adc Init Delay</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ADC_INIT_DELAY">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>ADC_DATA_WIDTH</spirit:name>
+      <spirit:displayName>Adc Data Width</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.ADC_DATA_WIDTH">16</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>BITS_PER_SAMPLE</spirit:name>
+      <spirit:displayName>Bits Per Sample</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.BITS_PER_SAMPLE">32</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axi_pulsar_lvds_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">akintex7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">virtexuplus58g</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">artixuplus</xilinx:family>
+        <xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>/Analog_Devices</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>axi_pulsar_lvds_v1_0</xilinx:displayName>
+      <xilinx:autoFamilySupportLevel>level_2</xilinx:autoFamilySupportLevel>
+      <xilinx:definitionSource>package_project</xilinx:definitionSource>
+      <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
+      <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
+      <xilinx:coreRevision>1</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2024-06-06T03:05:12Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="a4635454"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="16cdd6fb"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="98f009ec"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="c8b3c1c9"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>
diff --git a/adi_library/axi_pulsar_lvds/temporary_case_dependencies.mk b/adi_library/axi_pulsar_lvds/temporary_case_dependencies.mk
new file mode 100644
index 00000000..a7c71eb3
--- /dev/null
+++ b/adi_library/axi_pulsar_lvds/temporary_case_dependencies.mk
@@ -0,0 +1,2 @@
+CLEAN_TARGET += bd
+CLEAN_TARGET += temporary_case_dependencies.mk
diff --git a/adi_library/axi_pulsar_lvds/xgui/axi_pulsar_lvds_v1_0.tcl b/adi_library/axi_pulsar_lvds/xgui/axi_pulsar_lvds_v1_0.tcl
new file mode 100644
index 00000000..3957aa3a
--- /dev/null
+++ b/adi_library/axi_pulsar_lvds/xgui/axi_pulsar_lvds_v1_0.tcl
@@ -0,0 +1,208 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "ADC_DATA_WIDTH" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "ADC_INIT_DELAY" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "BITS_PER_SAMPLE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "DATAFORMAT_DISABLE" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "DELAY_REFCLK_FREQUENCY" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "IODELAY_CTRL" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "IO_DELAY_GROUP" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "USERPORTS_DISABLE" -parent ${Page_0}
+  #Adding Group
+  set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}]
+  ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox
+  ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox
+  ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox
+  ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox
+
+
+
+}
+
+proc update_PARAM_VALUE.ADC_DATA_WIDTH { PARAM_VALUE.ADC_DATA_WIDTH } {
+	# Procedure called to update ADC_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.ADC_DATA_WIDTH { PARAM_VALUE.ADC_DATA_WIDTH } {
+	# Procedure called to validate ADC_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.ADC_INIT_DELAY { PARAM_VALUE.ADC_INIT_DELAY } {
+	# Procedure called to update ADC_INIT_DELAY when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.ADC_INIT_DELAY { PARAM_VALUE.ADC_INIT_DELAY } {
+	# Procedure called to validate ADC_INIT_DELAY
+	return true
+}
+
+proc update_PARAM_VALUE.BITS_PER_SAMPLE { PARAM_VALUE.BITS_PER_SAMPLE } {
+	# Procedure called to update BITS_PER_SAMPLE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.BITS_PER_SAMPLE { PARAM_VALUE.BITS_PER_SAMPLE } {
+	# Procedure called to validate BITS_PER_SAMPLE
+	return true
+}
+
+proc update_PARAM_VALUE.DATAFORMAT_DISABLE { PARAM_VALUE.DATAFORMAT_DISABLE } {
+	# Procedure called to update DATAFORMAT_DISABLE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DATAFORMAT_DISABLE { PARAM_VALUE.DATAFORMAT_DISABLE } {
+	# Procedure called to validate DATAFORMAT_DISABLE
+	return true
+}
+
+proc update_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } {
+	# Procedure called to update DELAY_REFCLK_FREQUENCY when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } {
+	# Procedure called to validate DELAY_REFCLK_FREQUENCY
+	return true
+}
+
+proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
+	# Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } {
+	# Procedure called to validate DEV_PACKAGE
+	return true
+}
+
+proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
+	# Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } {
+	# Procedure called to validate FPGA_FAMILY
+	return true
+}
+
+proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
+	# Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } {
+	# Procedure called to validate FPGA_TECHNOLOGY
+	return true
+}
+
+proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
+	# Procedure called to update ID when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
+	# Procedure called to validate ID
+	return true
+}
+
+proc update_PARAM_VALUE.IODELAY_CTRL { PARAM_VALUE.IODELAY_CTRL } {
+	# Procedure called to update IODELAY_CTRL when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.IODELAY_CTRL { PARAM_VALUE.IODELAY_CTRL } {
+	# Procedure called to validate IODELAY_CTRL
+	return true
+}
+
+proc update_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } {
+	# Procedure called to update IO_DELAY_GROUP when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } {
+	# Procedure called to validate IO_DELAY_GROUP
+	return true
+}
+
+proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
+	# Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } {
+	# Procedure called to validate SPEED_GRADE
+	return true
+}
+
+proc update_PARAM_VALUE.USERPORTS_DISABLE { PARAM_VALUE.USERPORTS_DISABLE } {
+	# Procedure called to update USERPORTS_DISABLE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.USERPORTS_DISABLE { PARAM_VALUE.USERPORTS_DISABLE } {
+	# Procedure called to validate USERPORTS_DISABLE
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
+}
+
+proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY}
+}
+
+proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY}
+}
+
+proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE}
+}
+
+proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE}
+}
+
+proc update_MODELPARAM_VALUE.IO_DELAY_GROUP { MODELPARAM_VALUE.IO_DELAY_GROUP PARAM_VALUE.IO_DELAY_GROUP } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.IO_DELAY_GROUP}] ${MODELPARAM_VALUE.IO_DELAY_GROUP}
+}
+
+proc update_MODELPARAM_VALUE.IODELAY_CTRL { MODELPARAM_VALUE.IODELAY_CTRL PARAM_VALUE.IODELAY_CTRL } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.IODELAY_CTRL}] ${MODELPARAM_VALUE.IODELAY_CTRL}
+}
+
+proc update_MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY { MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY PARAM_VALUE.DELAY_REFCLK_FREQUENCY } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DELAY_REFCLK_FREQUENCY}] ${MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY}
+}
+
+proc update_MODELPARAM_VALUE.USERPORTS_DISABLE { MODELPARAM_VALUE.USERPORTS_DISABLE PARAM_VALUE.USERPORTS_DISABLE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.USERPORTS_DISABLE}] ${MODELPARAM_VALUE.USERPORTS_DISABLE}
+}
+
+proc update_MODELPARAM_VALUE.DATAFORMAT_DISABLE { MODELPARAM_VALUE.DATAFORMAT_DISABLE PARAM_VALUE.DATAFORMAT_DISABLE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.DATAFORMAT_DISABLE}] ${MODELPARAM_VALUE.DATAFORMAT_DISABLE}
+}
+
+proc update_MODELPARAM_VALUE.ADC_INIT_DELAY { MODELPARAM_VALUE.ADC_INIT_DELAY PARAM_VALUE.ADC_INIT_DELAY } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.ADC_INIT_DELAY}] ${MODELPARAM_VALUE.ADC_INIT_DELAY}
+}
+
+proc update_MODELPARAM_VALUE.ADC_DATA_WIDTH { MODELPARAM_VALUE.ADC_DATA_WIDTH PARAM_VALUE.ADC_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.ADC_DATA_WIDTH}] ${MODELPARAM_VALUE.ADC_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.BITS_PER_SAMPLE { MODELPARAM_VALUE.BITS_PER_SAMPLE PARAM_VALUE.BITS_PER_SAMPLE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.BITS_PER_SAMPLE}] ${MODELPARAM_VALUE.BITS_PER_SAMPLE}
+}
+
diff --git a/adi_library/axi_pulse_gen/axi_pulse_gen.v b/adi_library/axi_pulse_gen/axi_pulse_gen.v
index 3aebe0a8..09d955a2 100644
--- a/adi_library/axi_pulse_gen/axi_pulse_gen.v
+++ b/adi_library/axi_pulse_gen/axi_pulse_gen.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_pulse_gen/axi_pulse_gen.xpr b/adi_library/axi_pulse_gen/axi_pulse_gen.xpr
index f48d8491..8577303b 100644
--- a/adi_library/axi_pulse_gen/axi_pulse_gen.xpr
+++ b/adi_library/axi_pulse_gen/axi_pulse_gen.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_pulse_gen/axi_pulse_gen.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_pulse_gen/axi_pulse_gen.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="b075b929e09c444eafde6add18eaa473"/>
+    <Option Name="Id" Val="5c2e9aa74c1c40b1b9e1acf096d19c08"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -189,21 +188,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -216,7 +215,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_pulse_gen/axi_pulse_gen_regmap.v b/adi_library/axi_pulse_gen/axi_pulse_gen_regmap.v
index e276276f..0c0e12e6 100644
--- a/adi_library/axi_pulse_gen/axi_pulse_gen_regmap.v
+++ b/adi_library/axi_pulse_gen/axi_pulse_gen_regmap.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_pulse_gen/component.xml b/adi_library/axi_pulse_gen/component.xml
index e777f6fc..30992c24 100644
--- a/adi_library/axi_pulse_gen/component.xml
+++ b/adi_library/axi_pulse_gen/component.xml
@@ -260,7 +260,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>64faf65c</spirit:value>
+            <spirit:value>9efc73c7</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -279,7 +279,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>4ac547b1</spirit:value>
+            <spirit:value>d5cc837a</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -741,7 +741,7 @@
       <spirit:file>
         <spirit:name>axi_pulse_gen.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_63db955a</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_b0a7b352</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -846,11 +846,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:47:54Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:04:14Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="519e8af2"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="886aab0b"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="46248f1e"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="1e6bc47d"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="1ffac0ff"/>
diff --git a/adi_library/axi_pwm_gen/Makefile b/adi_library/axi_pwm_gen/Makefile
index e79670d4..01a7bfbf 100644
--- a/adi_library/axi_pwm_gen/Makefile
+++ b/adi_library/axi_pwm_gen/Makefile
@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################
@@ -21,6 +21,7 @@ XILINX_LIB_DEPS += util_cdc
 INTEL_DEPS += ../intel/common/up_rst_constr.sdc
 INTEL_DEPS += ../util_cdc/sync_bits.v
 INTEL_DEPS += ../util_cdc/sync_data.v
+INTEL_DEPS += ../util_cdc/sync_event.v
 INTEL_DEPS += axi_pwm_gen_constr.sdc
 INTEL_DEPS += axi_pwm_gen_hw.tcl
 
diff --git a/adi_library/axi_pwm_gen/axi_pwm_gen.sv b/adi_library/axi_pwm_gen/axi_pwm_gen.sv
index 929dfeb1..caf1f3d2 100644
--- a/adi_library/axi_pwm_gen/axi_pwm_gen.sv
+++ b/adi_library/axi_pwm_gen/axi_pwm_gen.sv
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -41,6 +41,10 @@ module axi_pwm_gen #(
   parameter  N_PWMS = 1,
   parameter  PWM_EXT_SYNC = 0,
   parameter  EXT_ASYNC_SYNC = 0,
+  parameter  SOFTWARE_BRINGUP = 1,
+  parameter  EXT_SYNC_PHASE_ALIGN = 0,
+  parameter  FORCE_ALIGN = 0,
+  parameter  START_AT_SYNC = 1,
   parameter  PULSE_0_WIDTH = 7,
   parameter  PULSE_1_WIDTH = 7,
   parameter  PULSE_2_WIDTH = 7,
@@ -139,8 +143,8 @@ module axi_pwm_gen #(
 
   localparam        PWMS = N_PWMS-1;
   localparam [31:0] CORE_VERSION = {16'h0002,     /* MAJOR */
-                                     8'h00,       /* MINOR */
-                                     8'h00};      /* PATCH */
+                                     8'h01,       /* MINOR */
+                                     8'h01};      /* PATCH */
   localparam [31:0] CORE_MAGIC = 32'h601a3471;    // PLSG
   localparam reg [31:0] PULSE_WIDTH_G[15:0] = '{PULSE_0_WIDTH,
                                                 PULSE_1_WIDTH,
@@ -197,8 +201,9 @@ module axi_pwm_gen #(
 
   reg [PWMS:0]    sync;
   reg   [31:0]    offset_cnt = 32'd0;
-  reg             offset_alignment = 1'b0;
-  reg             pause_cnt_d = 1'b0;
+  reg             offset_alignment = 1'b1;
+  reg   [31:0]    pwm_offset_d[0:PWMS];
+  reg   [31:0]    pwm_offset_read[0:PWMS];
 
   // internal signals
 
@@ -219,9 +224,17 @@ module axi_pwm_gen #(
   wire   [ 31:0]  pwm_offset_s[0:PWMS];
   wire   [ 15:0]  pwm_armed;
   wire            load_config_s;
+  wire            start_at_sync_s;
+  wire            force_align_s;
+  wire            ext_sync_align_s;
+  wire   [ 15:0]  ready_to_align_s;
+  wire   [ 15:0]  active_channel_s;
   wire            pwm_gen_resetn;
   wire            ext_sync_s;
+  wire            new_alignment;
   wire            pause_cnt;
+  wire            enable_wait;
+  wire            wait_for_all;
 
   assign up_clk = s_axi_aclk;
   assign up_rstn = s_axi_aresetn;
@@ -229,6 +242,10 @@ module axi_pwm_gen #(
   axi_pwm_gen_regmap #(
     .ID (ID),
     .ASYNC_CLK_EN (ASYNC_CLK_EN),
+    .SOFTWARE_BRINGUP (SOFTWARE_BRINGUP),
+    .EXT_SYNC_PHASE_ALIGN (EXT_SYNC_PHASE_ALIGN),
+    .FORCE_ALIGN (FORCE_ALIGN),
+    .START_AT_SYNC (START_AT_SYNC),
     .CORE_MAGIC (CORE_MAGIC),
     .CORE_VERSION (CORE_VERSION),
     .N_PWMS (PWMS),
@@ -243,6 +260,9 @@ module axi_pwm_gen #(
     .pwm_period (pwm_period_s),
     .pwm_offset (pwm_offset_s),
     .load_config (load_config_s),
+    .start_at_sync (start_at_sync_s),
+    .force_align (force_align_s),
+    .ext_sync_align (ext_sync_align_s),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
     .up_wreq (up_wreq_s),
@@ -278,45 +298,95 @@ module axi_pwm_gen #(
 
   endgenerate
 
+  assign new_alignment = load_config_s | ext_sync_s & ext_sync_align_s;
+
   // offset counter
 
   always @(posedge clk) begin
-    if (offset_alignment ==  1'b1 || pwm_gen_resetn == 1'b0) begin
+    if (offset_alignment ==  1'b1 || pwm_gen_resetn == 1'b0 || ext_sync_s == 1'b1) begin
       offset_cnt <= 32'd0;
     end else begin
       offset_cnt <= offset_cnt + 1'b1;
     end
 
     if (pwm_gen_resetn == 1'b0) begin
-      offset_alignment <= 1'b0;
+      offset_alignment <= 1'b1;
     end else begin
-      // when using external sync an offset alignment can be done only
-      // after all pwm counters are paused(load_config)/reseated
-      offset_alignment <= (load_config_s == 1'b1) ? 1'b1 :
+      // the offset alignment by external sync has two options
+      // 1. event on a faster clock(2'nd async clk) cannot be sampled on the base
+      // external clock.
+      // 2. fall edge
+      // when using external sync an offset alignment can only be done
+      // after all pwm counters are paused(load_config)/reseated while the
+      // external sync is held high
+      offset_alignment <= (new_alignment == 1'b1) ? 1'b1 :
                           offset_alignment &
-                          (ext_sync_s ? 1'b1 : !pause_cnt);
+                          (ext_sync_s ? 1'b1 : pause_cnt);
     end
   end
 
-  assign pause_cnt = ((pwm_armed[1]  |
-                       pwm_armed[2]  |
-                       pwm_armed[3]  |
-                       pwm_armed[4]  |
-                       pwm_armed[5]  |
-                       pwm_armed[6]  |
-                       pwm_armed[7]  |
-                       pwm_armed[8]  |
-                       pwm_armed[9]  |
-                       pwm_armed[10] |
-                       pwm_armed[11] |
-                       pwm_armed[12] |
-                       pwm_armed[13] |
-                       pwm_armed[14] |
-                       pwm_armed[15] ) ? 1'b1 : 1'b0);
+  assign enable_wait = ((pwm_armed[0]  & active_channel_s[0])  |
+                        (pwm_armed[1]  & active_channel_s[1])  |
+                        (pwm_armed[2]  & active_channel_s[2])  |
+                        (pwm_armed[3]  & active_channel_s[3])  |
+                        (pwm_armed[4]  & active_channel_s[4])  |
+                        (pwm_armed[5]  & active_channel_s[5])  |
+                        (pwm_armed[6]  & active_channel_s[6])  |
+                        (pwm_armed[7]  & active_channel_s[7])  |
+                        (pwm_armed[8]  & active_channel_s[8])  |
+                        (pwm_armed[9]  & active_channel_s[9])  |
+                        (pwm_armed[10] & active_channel_s[10]) |
+                        (pwm_armed[11] & active_channel_s[11]) |
+                        (pwm_armed[12] & active_channel_s[12]) |
+                        (pwm_armed[13] & active_channel_s[13]) |
+                        (pwm_armed[14] & active_channel_s[14]) |
+                        (pwm_armed[15] & active_channel_s[15]));
+
+  assign wait_for_all = (pwm_armed[0]  &
+                         pwm_armed[1]  &
+                         pwm_armed[2]  &
+                         pwm_armed[3]  &
+                         pwm_armed[4]  &
+                         pwm_armed[5]  &
+                         pwm_armed[6]  &
+                         pwm_armed[7]  &
+                         pwm_armed[8]  &
+                         pwm_armed[9]  &
+                         pwm_armed[10] &
+                         pwm_armed[11] &
+                         pwm_armed[12] &
+                         pwm_armed[13] &
+                         pwm_armed[14] &
+                         pwm_armed[15]);
+
+  assign pause_cnt = !(enable_wait & wait_for_all);
+
   genvar i;
   generate
     for (i = 0; i <= 15; i = i + 1) begin: pwm_cnt
       if (i <= PWMS) begin
+
+        // flop the desired offset
+
+        always @(posedge clk) begin
+          if (pwm_gen_resetn == 1'b0) begin
+            pwm_offset_d[i] <= pwm_offset_s[i];
+            pwm_offset_read[i] <= pwm_offset_s[i];
+          end else begin
+            // load the input period/width values
+            if (load_config_s) begin
+              pwm_offset_read[i] <= pwm_offset_s[i];
+              if (force_align_s == 1) begin
+                pwm_offset_d[i] <= pwm_offset_s[i];
+              end
+            end
+            // update the current period/width at the end of the period
+            if (ready_to_align_s[i]) begin
+              pwm_offset_d[i] <= pwm_offset_read[i];
+            end
+          end
+        end
+
         axi_pwm_gen_1  #(
           .PULSE_WIDTH (PULSE_WIDTH_G[i]),
           .PULSE_PERIOD (PULSE_PERIOD_G[i])
@@ -326,19 +396,27 @@ module axi_pwm_gen #(
           .pulse_width (pwm_width_s[i]),
           .pulse_period (pwm_period_s[i]),
           .load_config (load_config_s),
+          .start_at_sync_en (start_at_sync_s),
+          .force_align_en (force_align_s),
+          .ext_sync_align_en (ext_sync_align_s),
+          .ext_sync (ext_sync_s),
           .sync (sync[i]),
           .pulse (pwm[i]),
+          .active_channel (active_channel_s[i]),
+          .ready_to_align (ready_to_align_s[i]),
           .pulse_armed (pwm_armed[i]));
         always @(posedge clk) begin
           if (pwm_gen_resetn == 1'b0) begin
             sync[i] <= 1'b1;
           end else begin
-            sync[i] <= (offset_cnt == pwm_offset_s[i]) ? offset_alignment : 1'b1;
+            sync[i] <= (offset_cnt == pwm_offset_d[i]) ? offset_alignment : 1'b1;
           end
         end
       end else begin
        assign pwm[i] = 1'b0;
-       assign pwm_armed[i] = 1'b0;
+       assign pwm_armed[i] = 1'b1;
+       assign active_channel_s[i] = 1'b0;
+       assign ready_to_align_s[i] = 1'b1;
       end
     end
   endgenerate
diff --git a/adi_library/axi_pwm_gen/axi_pwm_gen.xpr b/adi_library/axi_pwm_gen/axi_pwm_gen.xpr
index 7f7146e1..09615014 100644
--- a/adi_library/axi_pwm_gen/axi_pwm_gen.xpr
+++ b/adi_library/axi_pwm_gen/axi_pwm_gen.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_pwm_gen/axi_pwm_gen.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_pwm_gen/axi_pwm_gen.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="c1f58724adcf46cba87c475145902d53"/>
+    <Option Name="Id" Val="4f5bf7a24ec54b409d5b2a8cfa41cf19"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -189,21 +188,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -216,7 +215,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_pwm_gen/axi_pwm_gen_1.v b/adi_library/axi_pwm_gen/axi_pwm_gen_1.v
index 8e26215f..c6dfdd0f 100644
--- a/adi_library/axi_pwm_gen/axi_pwm_gen_1.v
+++ b/adi_library/axi_pwm_gen/axi_pwm_gen_1.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -45,12 +45,21 @@ module axi_pwm_gen_1 #(
   input       [31:0]  pulse_width,
   input       [31:0]  pulse_period,
   input               load_config,
+  input               start_at_sync_en,
+  input               force_align_en,
+  input               ext_sync_align_en,
+  input               ext_sync,
   input               sync,
 
   output              pulse,
+  output              active_channel,
+  output              ready_to_align,
   output              pulse_armed
 );
 
+  localparam [0:0] ARM = 0;
+  localparam [0:0] RUN = 1;
+
   // internal registers
 
   reg     [31:0]               pulse_period_cnt = 32'h0;
@@ -60,19 +69,28 @@ module axi_pwm_gen_1 #(
   reg     [31:0]               pulse_width_d = PULSE_WIDTH;
   reg                          phase_align_armed = 1'b1;
   reg                          pulse_i = 1'b0;
-  reg                          busy = 1'b0;
+  reg                          run_sm = ARM;
+  reg                          run_sm_next = ARM;
+  reg                          pulse_start;
+  reg                          pulse_stop;
 
   // internal wires
 
+  wire                         ext_sync_align;
   wire                         phase_align;
   wire                         end_of_period;
   wire                         end_of_pulse;
   wire                         pulse_enable;
+  wire                         align_pulse;
+  wire                         align_period;
+  wire                         start_at_sync;
 
   // enable pwm
 
   assign pulse_enable = (pulse_period_d != 32'd0) ? 1'b1 : 1'b0;
 
+  assign ext_sync_align = ext_sync & ext_sync_align_en;
+
   // flop the desired period
 
   always @(posedge clk) begin
@@ -86,6 +104,10 @@ module axi_pwm_gen_1 #(
       if (load_config) begin
         pulse_period_read <= pulse_period;
         pulse_width_read <= pulse_width;
+        if (force_align_en == 1 && start_at_sync_en == 1) begin
+          pulse_period_d <= pulse_period;
+          pulse_width_d <= pulse_width;
+        end
       end
       // update the current period/width at the end of the period
       if (end_of_period | ~pulse_enable) begin
@@ -103,30 +125,47 @@ module axi_pwm_gen_1 #(
     end else begin
       if (load_config == 1'b1) begin
         phase_align_armed <= sync;
+      end else if (ext_sync_align == 1'b1) begin
+        phase_align_armed <= sync;
       end else begin
         phase_align_armed <= phase_align_armed & sync;
       end
     end
   end
 
+  // phase align SM
   always @(posedge clk) begin
     if (rstn == 1'b0) begin
-      busy <= 1'b0;
+      run_sm <= ARM;
+      run_sm_next <= ARM;
     end else begin
-      if (end_of_period) begin
-        busy <= 1'b0;
-      end else if ( ~(phase_align_armed & sync)) begin
-        busy <= 1'b1;
-      end
+      case (run_sm)
+        ARM: begin
+          if (sync == 1'b0) begin
+            run_sm_next <= RUN;
+          end
+        end
+        RUN: begin
+          if (force_align_en == 1) begin
+            if (ext_sync_align == 1'b1 || load_config == 1'b1) begin
+              run_sm_next <= ARM;
+            end
+          end else if (phase_align_armed == 1'b1 && end_of_period == 1'b1) begin
+            run_sm_next <= ARM;
+          end else if (end_of_period == 1'b1) begin
+            run_sm_next <= RUN;
+          end
+        end
+      endcase
+      run_sm <= run_sm_next;
     end
   end
 
-  assign phase_align = phase_align_armed & sync & busy;
-
-  // a free running counter
+  assign align_pulse =  ext_sync_align & force_align_en;
+  assign align_period = align_pulse == 1 || run_sm_next <= ARM || end_of_period == 1'b1;
 
   always @(posedge clk) begin
-    if (rstn == 1'b0 || phase_align == 1'b1 || end_of_period == 1'b1) begin
+    if (rstn == 1'b0 || align_period) begin
       pulse_period_cnt <= 32'd1;
     end else begin
       if (pulse_enable == 1'b1) begin
@@ -138,17 +177,32 @@ module axi_pwm_gen_1 #(
   assign end_of_period = (pulse_period_cnt == pulse_period_d) ? 1'b1 : 1'b0;
   assign end_of_pulse = (pulse_period_cnt == pulse_width_d) ? 1'b1 : 1'b0;
 
+  assign start_at_sync = start_at_sync_en == 1 ? ~run_sm & ~sync : 1'b0;
+
+  always @(posedge clk) begin
+    pulse_start <= start_at_sync == 1'b1 ||
+                   end_of_period & !phase_align_armed & |pulse_width_d;
+
+    pulse_stop <= rstn == 1'b0 ||
+                  align_pulse == 1'b1 ||
+                  pulse_enable == 1'b0 ||
+                  pulse_width_d == 32'd0 ||
+                  end_of_pulse ? !end_of_period : 1'b0;
+  end
+
   // generate pulse with a specified width
 
-  always @ (posedge clk) begin
-    if ((rstn == 1'b0) || (end_of_pulse == 1'b1)) begin
+  always @(posedge clk) begin
+    if (pulse_stop) begin
       pulse_i <= 1'b0;
-    end else if ((end_of_period == 1'b1 || phase_align == 1'b1) && pulse_enable == 1'b1) begin
+    end else if (pulse_start) begin
       pulse_i <= 1'b1;
     end
   end
 
-  assign pulse = pulse_i & !(phase_align_armed & sync);
-  assign pulse_armed = phase_align_armed;
+  assign pulse = pulse_i;
+  assign active_channel = pulse_enable;
+  assign ready_to_align = end_of_period | ~pulse_enable;
+  assign pulse_armed = phase_align_armed & ~run_sm | ~pulse_enable;
 
 endmodule
diff --git a/adi_library/axi_pwm_gen/axi_pwm_gen_constr.sdc b/adi_library/axi_pwm_gen/axi_pwm_gen_constr.sdc
index 38d4230b..ca086ba5 100644
--- a/adi_library/axi_pwm_gen/axi_pwm_gen_constr.sdc
+++ b/adi_library/axi_pwm_gen/axi_pwm_gen_constr.sdc
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
diff --git a/adi_library/axi_pwm_gen/axi_pwm_gen_constr.ttcl b/adi_library/axi_pwm_gen/axi_pwm_gen_constr.ttcl
index 91c96e4f..da0422eb 100644
--- a/adi_library/axi_pwm_gen/axi_pwm_gen_constr.ttcl
+++ b/adi_library/axi_pwm_gen/axi_pwm_gen_constr.ttcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
 # SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -34,4 +34,16 @@ set_property ASYNC_REG TRUE \
     -from [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/in_toggle_d1_reg/C}] \
     -to [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}]
 
+  set_false_path \
+    -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/cdc_hold_reg*}] \
+    -to [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/out_data_reg*}]
+
+  set_false_path \
+    -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/in_toggle_d1_reg}] \
+    -to [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/i_sync_out/cdc_sync_stage1_reg[*]}]
+
+  set_false_path \
+    -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/out_toggle_d1_reg}] \
+    -to [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/i_sync_in/cdc_sync_stage1_reg[*]}]
+
 <: } :>
diff --git a/adi_library/axi_pwm_gen/axi_pwm_gen_hw.tcl b/adi_library/axi_pwm_gen/axi_pwm_gen_hw.tcl
old mode 100644
new mode 100755
index 558e2325..faffb0d5
--- a/adi_library/axi_pwm_gen/axi_pwm_gen_hw.tcl
+++ b/adi_library/axi_pwm_gen/axi_pwm_gen_hw.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -30,6 +30,10 @@ ad_ip_parameter ASYNC_CLK_EN INTEGER 1
 ad_ip_parameter N_PWMS INTEGER 1
 ad_ip_parameter PWM_EXT_SYNC INTEGER 0
 ad_ip_parameter EXT_ASYNC_SYNC INTEGER 0
+ad_ip_parameter EXT_SYNC_PHASE_ALIGN INTEGER 0
+ad_ip_parameter SOFTWARE_BRINGUP INTEGER 1
+ad_ip_parameter FORCE_ALIGN INTEGER 0
+ad_ip_parameter START_AT_SYNC INTEGER 1
 ad_ip_parameter PULSE_0_WIDTH INTEGER 7
 ad_ip_parameter PULSE_1_WIDTH INTEGER 7
 ad_ip_parameter PULSE_2_WIDTH INTEGER 7
diff --git a/adi_library/axi_pwm_gen/axi_pwm_gen_ip.tcl b/adi_library/axi_pwm_gen/axi_pwm_gen_ip.tcl
index 7dd86435..7eb73b2e 100644
--- a/adi_library/axi_pwm_gen/axi_pwm_gen_ip.tcl
+++ b/adi_library/axi_pwm_gen/axi_pwm_gen_ip.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -67,45 +67,76 @@ ipx::save_core $cc
 ipgui::add_page -name {AXI PWM Generator} -component $cc -display_name {AXI PWM Generator}
 set page0 [ipgui::get_pagespec -name "AXI PWM Generator" -component $cc]
 
-ipgui::add_param -name "ASYNC_CLK_EN" -component $cc -parent $page0
-set_property -dict [list \
-  "display_name" "ASYNC_CLK_EN" \
-  "tooltip" "External clock for the counter" \
-  "widget" "checkBox" \
-] [ipgui::get_guiparamspec -name "ASYNC_CLK_EN" -component $cc]
-
-ipgui::add_param -name "EXT_ASYNC_SYNC" -component $cc -parent $page0
-set_property -dict [list \
-  "display_name" "External sync signal is asynchronous" \
-  "tooltip" "NOTE: If active the ext_sync will be delayed 2 clock cycles." \
-  "widget" "checkBox" \
-] [ipgui::get_guiparamspec -name "EXT_ASYNC_SYNC" -component $cc]
-
+# N_PWMs
 ipgui::add_param -name "N_PWMS" -component $cc -parent $page0
 set_property -dict [list \
   "display_name" "Number of pwms" \
 ] [ipgui::get_guiparamspec -name "N_PWMS" -component $cc]
 
+# ASYNC_CLK_EN
+ipgui::add_param -name "ASYNC_CLK_EN" -component $cc -parent $page0
+set_property -dict [list \
+  "display_name" "ASYNC_CLK_EN" \
+  "tooltip" "The logic and PWMs will be driven by ext_clk. Otherwise the axi clock will be used" \
+  "widget" "checkBox" \
+] [ipgui::get_guiparamspec -name "ASYNC_CLK_EN" -component $cc]
+
+# PWM_EXT_SYNC
 ipgui::add_param -name "PWM_EXT_SYNC" -component $cc -parent $page0
 set_property -dict [list \
   "display_name" "External sync" \
-  "tooltip" "NOTE: If active the whole pwm gen module will be waiting for the ext_sync to be set low. A load config or reset must be used before deaserting the ext_sync" \
+  "tooltip" "If active the whole pwm gen module will be waiting for the ext_sync to be set low. A load config or reset must be used before de-asserting the ext_sync to retrigger the sync process" \
   "widget" "checkBox" \
 ] [ipgui::get_guiparamspec -name "PWM_EXT_SYNC" -component $cc]
 
+# EXT_ASYNC_SYNC
 ipgui::add_param -name "EXT_ASYNC_SYNC" -component $cc -parent $page0
 set_property -dict [list \
   "display_name" "External sync signal is asynchronous" \
   "tooltip" "NOTE: If active the ext_sync will be delayed 2 clock cycles." \
   "widget" "checkBox" \
 ] [ipgui::get_guiparamspec -name "EXT_ASYNC_SYNC" -component $cc]
+  set_property enablement_tcl_expr {expr $PWM_EXT_SYNC == 1} [ipx::get_user_parameters EXT_ASYNC_SYNC -of_objects $cc]
+
+# SOFTWARE_BRINGUP
+ipgui::add_param -name "SOFTWARE_BRINGUP" -component $cc -parent $page0
+set_property -dict [list \
+  "display_name" "Require software bringup" \
+  "tooltip" "If active the software must bring the core out of soft reset, after a system reset, in order for the pwm signals to be generated" \
+  "widget" "checkBox" \
+] [ipgui::get_guiparamspec -name "SOFTWARE_BRINGUP" -component $cc]
+
+# EXT_SYNC_PHASE_ALIGN
+ipgui::add_param -name "EXT_SYNC_PHASE_ALIGN" -component $cc -parent $page0
+set_property -dict [list \
+  "display_name" "External sync enable phase align" \
+  "tooltip" "If active the ext_sync will trigger a phase align at each neg-edge. Otherwise the phase align will be armed by a load config toggle. Software over writable at runtime." \
+  "widget" "checkBox" \
+] [ipgui::get_guiparamspec -name "EXT_SYNC_PHASE_ALIGN" -component $cc]
+  set_property enablement_tcl_expr {expr $PWM_EXT_SYNC == 1} [ipx::get_user_parameters EXT_SYNC_PHASE_ALIGN -of_objects $cc]
+
+# FORCE_ALIGN
+ipgui::add_param -name "FORCE_ALIGN" -component $cc -parent $page0
+set_property -dict [list \
+  "display_name" "Force align" \
+  "tooltip" "If active the current active pulses are immediately stopped and realigned. Otherwise, the synchronized pulses will start only after all running pulse periods end. Software over writable at runtime." \
+  "widget" "checkBox" \
+] [ipgui::get_guiparamspec -name "FORCE_ALIGN" -component $cc]
+
+# START_AT_SYNC
+ipgui::add_param -name "START_AT_SYNC" -component $cc -parent $page0
+set_property -dict [list \
+  "display_name" "Start at sync" \
+  "tooltip" "If active, the pulses will start after the trigger event. Otherwise each pulse will start after a period equal to the one for which it is set. Software over writable at runtime." \
+  "widget" "checkBox" \
+] [ipgui::get_guiparamspec -name "START_AT_SYNC" -component $cc]
 
 # Maximum 16 pwms
 for {set i 0} {$i < 16} {incr i} {
   ipgui::add_param -name "PULSE_${i}_WIDTH" -component $cc -parent $page0
   set_property -dict [list \
     "display_name" "PULSE $i width" \
-    "tooltip" "PULSE width of the generated signal. The unit interval is the system or external clock period." \
+    "tooltip" "PULSE width of the generated signal. The unit interval represents a period the system or external clock period." \
   ] [ipgui::get_guiparamspec -name "PULSE_${i}_WIDTH" -component $cc]
 
   set_property -dict [list \
@@ -114,11 +145,12 @@ for {set i 0} {$i < 16} {incr i} {
     "value_validation_range_maximum" "2147483647" \
    ] \
   [ipx::get_user_parameters PULSE_${i}_WIDTH -of_objects $cc]
+  set_property enablement_tcl_expr "expr \$N_PWMS >= $i" [ipx::get_user_parameters PULSE_${i}_WIDTH -of_objects $cc]
 
   ipgui::add_param -name "PULSE_${i}_PERIOD" -component $cc -parent $page0
   set_property -dict [list \
     "display_name" "PULSE ${i} period" \
-    "tooltip" "Period of the generated signal. The unit interval is the system or external clock period." \
+    "tooltip" "Period of the generated signal. The unit interval represents a period the system or external clock period." \
   ] [ipgui::get_guiparamspec -name "PULSE_${i}_PERIOD" -component $cc]
 
   set_property -dict [list \
@@ -127,11 +159,12 @@ for {set i 0} {$i < 16} {incr i} {
     "value_validation_range_maximum" "2147483647" \
    ] \
   [ipx::get_user_parameters PULSE_${i}_PERIOD -of_objects $cc]
+  set_property enablement_tcl_expr "expr \$N_PWMS >= $i" [ipx::get_user_parameters PULSE_${i}_PERIOD -of_objects $cc]
 
   ipgui::add_param -name "PULSE_${i}_OFFSET" -component $cc -parent $page0
   set_property -dict [list \
     "display_name" "PULSE ${i} offset" \
-    "tooltip" "Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period." \
+    "tooltip" "Offset of the generated signal referenced to PULSE 1. The unit interval represents a period the system or external clock period." \
   ] [ipgui::get_guiparamspec -name "PULSE_${i}_OFFSET" -component $cc]
 
   set_property -dict [list \
@@ -140,6 +173,7 @@ for {set i 0} {$i < 16} {incr i} {
     "value_validation_range_maximum" "2147483647" \
    ] \
   [ipx::get_user_parameters PULSE_${i}_OFFSET -of_objects $cc]
+  set_property enablement_tcl_expr "expr \$N_PWMS >= $i" [ipx::get_user_parameters PULSE_${i}_OFFSET -of_objects $cc]
 }
 
 for {set i 0} {$i < 16} {incr i} {
diff --git a/adi_library/axi_pwm_gen/axi_pwm_gen_regmap.sv b/adi_library/axi_pwm_gen/axi_pwm_gen_regmap.sv
index 91a70304..b0a0f1b4 100644
--- a/adi_library/axi_pwm_gen/axi_pwm_gen_regmap.sv
+++ b/adi_library/axi_pwm_gen/axi_pwm_gen_regmap.sv
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -40,6 +40,10 @@ module axi_pwm_gen_regmap #(
   parameter            CORE_MAGIC = 0,
   parameter            CORE_VERSION = 0,
   parameter            ASYNC_CLK_EN = 1,
+  parameter            SOFTWARE_BRINGUP = 1,
+  parameter            EXT_SYNC_PHASE_ALIGN = 0,
+  parameter            FORCE_ALIGN = 0,
+  parameter            START_AT_SYNC = 1,
   parameter            N_PWMS = 0,
   parameter reg [31:0] PULSE_WIDTH_G[0:15]  = '{16{32'd0}},
   parameter reg [31:0] PULSE_PERIOD_G[0:15] = '{16{32'd0}},
@@ -58,6 +62,9 @@ module axi_pwm_gen_regmap #(
   output      [31:0]      pwm_period[0:N_PWMS],
   output      [31:0]      pwm_offset[0:N_PWMS],
   output                  load_config,
+  output                  start_at_sync,
+  output                  force_align,
+  output                  ext_sync_align,
 
   // processor interface
 
@@ -80,7 +87,16 @@ module axi_pwm_gen_regmap #(
   reg     [31:0]  up_pwm_period[0:N_PWMS] = PULSE_PERIOD_G[0:N_PWMS];
   reg     [31:0]  up_pwm_offset[0:N_PWMS] = PULSE_OFFSET_G[0:N_PWMS];
   reg             up_load_config = 1'b0;
-  reg             up_reset = 1'b1;
+  reg             up_reset = SOFTWARE_BRINGUP[0];
+  reg     [ 2:0]  up_control = {EXT_SYNC_PHASE_ALIGN[0],FORCE_ALIGN[0],START_AT_SYNC[0]};
+
+  // internal signals
+
+  wire    [ 2:0]  control;
+
+  assign start_at_sync = control[0];
+  assign force_align = control[1];
+  assign ext_sync_align = control[2];
 
   genvar n;
 
@@ -88,11 +104,12 @@ module axi_pwm_gen_regmap #(
     if (up_rstn == 0) begin
       up_wack <= 'd0;
       up_scratch <= 'd0;
-      up_pwm_width = PULSE_WIDTH_G[0:N_PWMS];
-      up_pwm_period = PULSE_PERIOD_G[0:N_PWMS];
-      up_pwm_offset = PULSE_OFFSET_G[0:N_PWMS];
+      up_pwm_width <= PULSE_WIDTH_G[0:N_PWMS];
+      up_pwm_period <= PULSE_PERIOD_G[0:N_PWMS];
+      up_pwm_offset <= PULSE_OFFSET_G[0:N_PWMS];
       up_load_config <= 1'b0;
-      up_reset <= 1'b1;
+      up_reset <= SOFTWARE_BRINGUP[0];
+      up_control <= {EXT_SYNC_PHASE_ALIGN[0],FORCE_ALIGN[0],START_AT_SYNC[0]};
     end else begin
       up_wack <= up_wreq;
       if ((up_wreq == 1'b1) && (up_waddr == 14'h2)) begin
@@ -104,6 +121,9 @@ module axi_pwm_gen_regmap #(
       end else begin
         up_load_config <= 1'b0;
       end
+      if ((up_wreq == 1'b1) && (up_waddr == 14'h6)) begin
+        up_control <= up_wdata[2:0];
+      end
       for (int i = 0; i <= N_PWMS; i++) begin
         if ((up_wreq == 1'b1) && (up_waddr == 14'h10 + i)) begin
           up_pwm_period[i] <= up_wdata;
@@ -133,6 +153,7 @@ module axi_pwm_gen_regmap #(
             14'h3: up_rdata <= CORE_MAGIC;
             14'h4: up_rdata <= up_reset;
             14'h5: up_rdata <= N_PWMS +1;
+            14'h6: up_rdata <= {29'd0, up_control};
             default: up_rdata <= 0;
           endcase
         end else if (up_raddr[3:0] > N_PWMS) begin
@@ -161,7 +182,16 @@ module axi_pwm_gen_regmap #(
       .rstn (pwm_gen_resetn),
       .rst ());
 
-    for (n = 0; n <= N_PWMS; n = n + 1) begin: up_to_adc_cdc
+    sync_data #(
+      .NUM_OF_BITS (3),
+      .ASYNC_CLK (1))
+    i_pwm_controls (
+      .in_clk (up_clk),
+      .in_data (up_control),
+      .out_clk (clk_out),
+      .out_data (control));
+
+    for (n = 0; n <= N_PWMS; n = n + 1) begin: pwm_cdc
       sync_data #(
         .NUM_OF_BITS (96),
         .ASYNC_CLK (1))
diff --git a/adi_library/axi_pwm_gen/component.xml b/adi_library/axi_pwm_gen/component.xml
index b7f6cb16..218dd174 100644
--- a/adi_library/axi_pwm_gen/component.xml
+++ b/adi_library/axi_pwm_gen/component.xml
@@ -260,7 +260,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>4382ad15</spirit:value>
+            <spirit:value>e9e1139f</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -279,7 +279,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>968239ce</spirit:value>
+            <spirit:value>f808a9db</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -296,10 +296,18 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>69a79a78</spirit:value>
+            <spirit:value>c4bc8231</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
+      <spirit:view>
+        <spirit:name>xilinx_utilityxitfiles</spirit:name>
+        <spirit:displayName>Utility XIT/TTCL</spirit:displayName>
+        <spirit:envIdentifier>:vivado.xilinx.com:xit.util</spirit:envIdentifier>
+        <spirit:fileSetRef>
+          <spirit:localName>xilinx_utilityxitfiles_view_fileset</spirit:localName>
+        </spirit:fileSetRef>
+      </spirit:view>
     </spirit:views>
     <spirit:ports>
       <spirit:port>
@@ -1042,6 +1050,40 @@
         <spirit:name>EXT_ASYNC_SYNC</spirit:name>
         <spirit:displayName>Ext Async Sync</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EXT_ASYNC_SYNC">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.EXT_ASYNC_SYNC">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>SOFTWARE_BRINGUP</spirit:name>
+        <spirit:displayName>Software Bringup</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.SOFTWARE_BRINGUP">1</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>EXT_SYNC_PHASE_ALIGN</spirit:name>
+        <spirit:displayName>Ext Sync Phase Align</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.EXT_SYNC_PHASE_ALIGN">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.EXT_SYNC_PHASE_ALIGN">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>FORCE_ALIGN</spirit:name>
+        <spirit:displayName>Force Align</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.FORCE_ALIGN">0</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>START_AT_SYNC</spirit:name>
+        <spirit:displayName>Start At Sync</spirit:displayName>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.START_AT_SYNC">1</spirit:value>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_0_WIDTH</spirit:name>
@@ -1057,71 +1099,169 @@
         <spirit:name>PULSE_2_WIDTH</spirit:name>
         <spirit:displayName>Pulse 2 Width</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_2_WIDTH">7</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_2_WIDTH">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_3_WIDTH</spirit:name>
         <spirit:displayName>Pulse 3 Width</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_3_WIDTH">7</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_3_WIDTH">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_4_WIDTH</spirit:name>
         <spirit:displayName>Pulse 4 Width</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_4_WIDTH">7</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_4_WIDTH">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_5_WIDTH</spirit:name>
         <spirit:displayName>Pulse 5 Width</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_5_WIDTH">7</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_5_WIDTH">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_6_WIDTH</spirit:name>
         <spirit:displayName>Pulse 6 Width</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_6_WIDTH">7</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_6_WIDTH">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_7_WIDTH</spirit:name>
         <spirit:displayName>Pulse 7 Width</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_7_WIDTH">7</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_7_WIDTH">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_8_WIDTH</spirit:name>
         <spirit:displayName>Pulse 8 Width</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_8_WIDTH">7</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_8_WIDTH">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_9_WIDTH</spirit:name>
         <spirit:displayName>Pulse 9 Width</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_9_WIDTH">7</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_9_WIDTH">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_10_WIDTH</spirit:name>
         <spirit:displayName>Pulse 10 Width</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_10_WIDTH">7</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_10_WIDTH">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_11_WIDTH</spirit:name>
         <spirit:displayName>Pulse 11 Width</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_11_WIDTH">7</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_11_WIDTH">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_12_WIDTH</spirit:name>
         <spirit:displayName>Pulse 12 Width</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_12_WIDTH">7</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_12_WIDTH">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_13_WIDTH</spirit:name>
         <spirit:displayName>Pulse 13 Width</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_13_WIDTH">7</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_13_WIDTH">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_14_WIDTH</spirit:name>
         <spirit:displayName>Pulse 14 Width</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_14_WIDTH">7</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_14_WIDTH">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_15_WIDTH</spirit:name>
         <spirit:displayName>Pulse 15 Width</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_15_WIDTH">7</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_15_WIDTH">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_0_PERIOD</spirit:name>
@@ -1137,71 +1277,169 @@
         <spirit:name>PULSE_2_PERIOD</spirit:name>
         <spirit:displayName>Pulse 2 Period</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_2_PERIOD">10</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_2_PERIOD">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_3_PERIOD</spirit:name>
         <spirit:displayName>Pulse 3 Period</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_3_PERIOD">10</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_3_PERIOD">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_4_PERIOD</spirit:name>
         <spirit:displayName>Pulse 4 Period</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_4_PERIOD">10</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_4_PERIOD">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_5_PERIOD</spirit:name>
         <spirit:displayName>Pulse 5 Period</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_5_PERIOD">10</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_5_PERIOD">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_6_PERIOD</spirit:name>
         <spirit:displayName>Pulse 6 Period</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_6_PERIOD">10</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_6_PERIOD">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_7_PERIOD</spirit:name>
         <spirit:displayName>Pulse 7 Period</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_7_PERIOD">10</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_7_PERIOD">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_8_PERIOD</spirit:name>
         <spirit:displayName>Pulse 8 Period</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_8_PERIOD">10</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_8_PERIOD">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_9_PERIOD</spirit:name>
         <spirit:displayName>Pulse 9 Period</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_9_PERIOD">10</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_9_PERIOD">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_10_PERIOD</spirit:name>
         <spirit:displayName>Pulse 10 Period</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_10_PERIOD">10</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_10_PERIOD">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_11_PERIOD</spirit:name>
         <spirit:displayName>Pulse 11 Period</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_11_PERIOD">10</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_11_PERIOD">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_12_PERIOD</spirit:name>
         <spirit:displayName>Pulse 12 Period</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_12_PERIOD">10</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_12_PERIOD">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_13_PERIOD</spirit:name>
         <spirit:displayName>Pulse 13 Period</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_13_PERIOD">10</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_13_PERIOD">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_14_PERIOD</spirit:name>
         <spirit:displayName>Pulse 14 Period</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_14_PERIOD">10</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_14_PERIOD">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_15_PERIOD</spirit:name>
         <spirit:displayName>Pulse 15 Period</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_15_PERIOD">10</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_15_PERIOD">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_0_OFFSET</spirit:name>
@@ -1217,71 +1455,169 @@
         <spirit:name>PULSE_2_OFFSET</spirit:name>
         <spirit:displayName>Pulse 2 Offset</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_2_OFFSET">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_2_OFFSET">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_3_OFFSET</spirit:name>
         <spirit:displayName>Pulse 3 Offset</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_3_OFFSET">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_3_OFFSET">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_4_OFFSET</spirit:name>
         <spirit:displayName>Pulse 4 Offset</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_4_OFFSET">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_4_OFFSET">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_5_OFFSET</spirit:name>
         <spirit:displayName>Pulse 5 Offset</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_5_OFFSET">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_5_OFFSET">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_6_OFFSET</spirit:name>
         <spirit:displayName>Pulse 6 Offset</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_6_OFFSET">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_6_OFFSET">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_7_OFFSET</spirit:name>
         <spirit:displayName>Pulse 7 Offset</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_7_OFFSET">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_7_OFFSET">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_8_OFFSET</spirit:name>
         <spirit:displayName>Pulse 8 Offset</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_8_OFFSET">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_8_OFFSET">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_9_OFFSET</spirit:name>
         <spirit:displayName>Pulse 9 Offset</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_9_OFFSET">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_9_OFFSET">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_10_OFFSET</spirit:name>
         <spirit:displayName>Pulse 10 Offset</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_10_OFFSET">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_10_OFFSET">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_11_OFFSET</spirit:name>
         <spirit:displayName>Pulse 11 Offset</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_11_OFFSET">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_11_OFFSET">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_12_OFFSET</spirit:name>
         <spirit:displayName>Pulse 12 Offset</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_12_OFFSET">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_12_OFFSET">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_13_OFFSET</spirit:name>
         <spirit:displayName>Pulse 13 Offset</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_13_OFFSET">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_13_OFFSET">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_14_OFFSET</spirit:name>
         <spirit:displayName>Pulse 14 Offset</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_14_OFFSET">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_14_OFFSET">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>PULSE_15_OFFSET</spirit:name>
         <spirit:displayName>Pulse 15 Offset</spirit:displayName>
         <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PULSE_15_OFFSET">0</spirit:value>
+        <spirit:vendorExtensions>
+          <xilinx:parameterInfo>
+            <xilinx:enablement>
+              <xilinx:isEnabled xilinx:id="MODELPARAM_ENABLEMENT.PULSE_15_OFFSET">false</xilinx:isEnabled>
+            </xilinx:enablement>
+          </xilinx:parameterInfo>
+        </spirit:vendorExtensions>
       </spirit:modelParameter>
     </spirit:modelParameters>
   </spirit:model>
@@ -1322,7 +1658,7 @@
       <spirit:file>
         <spirit:name>axi_pwm_gen.sv</spirit:name>
         <spirit:fileType>systemVerilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_bb2ebc50</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_ab87ef54</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1373,7 +1709,7 @@
       <spirit:file>
         <spirit:name>xgui/axi_pwm_gen_v1_0.tcl</spirit:name>
         <spirit:fileType>tclSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_1a7791fc</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_d4b1a0c8</spirit:userFileType>
         <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
@@ -1385,6 +1721,13 @@
         </xilinx:subCoreRef>
       </spirit:vendorExtensions>
     </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_utilityxitfiles_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>gui/axi_pwm_gen_v1_0.gtcl</spirit:name>
+        <spirit:userFileType>GTCL</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
   </spirit:fileSets>
   <spirit:description>ADI AXI PWM Generator</spirit:description>
   <spirit:parameters>
@@ -1412,246 +1755,616 @@
       <spirit:name>EXT_ASYNC_SYNC</spirit:name>
       <spirit:displayName>External sync signal is asynchronous</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.EXT_ASYNC_SYNC">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.EXT_ASYNC_SYNC">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>SOFTWARE_BRINGUP</spirit:name>
+      <spirit:displayName>Require software bringup</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.SOFTWARE_BRINGUP">1</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>EXT_SYNC_PHASE_ALIGN</spirit:name>
+      <spirit:displayName>External sync enable phase align</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.EXT_SYNC_PHASE_ALIGN">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.EXT_SYNC_PHASE_ALIGN">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>FORCE_ALIGN</spirit:name>
+      <spirit:displayName>Force align</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FORCE_ALIGN">0</spirit:value>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>START_AT_SYNC</spirit:name>
+      <spirit:displayName>Start at sync</spirit:displayName>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.START_AT_SYNC">1</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_0_WIDTH</spirit:name>
       <spirit:displayName>PULSE 0 width</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_0_WIDTH" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">7</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_0_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_1_WIDTH</spirit:name>
       <spirit:displayName>PULSE 1 width</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_1_WIDTH" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">7</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_1_WIDTH">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_2_WIDTH</spirit:name>
       <spirit:displayName>PULSE 2 width</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_2_WIDTH" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">7</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_2_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_3_WIDTH</spirit:name>
       <spirit:displayName>PULSE 3 width</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_3_WIDTH" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">7</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_3_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_4_WIDTH</spirit:name>
       <spirit:displayName>PULSE 4 width</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_4_WIDTH" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">7</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_4_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_5_WIDTH</spirit:name>
       <spirit:displayName>PULSE 5 width</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_5_WIDTH" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">7</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_5_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_6_WIDTH</spirit:name>
       <spirit:displayName>PULSE 6 width</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_6_WIDTH" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">7</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_6_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_7_WIDTH</spirit:name>
       <spirit:displayName>PULSE 7 width</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_7_WIDTH" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">7</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_7_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_8_WIDTH</spirit:name>
       <spirit:displayName>PULSE 8 width</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_8_WIDTH" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">7</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_8_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_9_WIDTH</spirit:name>
       <spirit:displayName>PULSE 9 width</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_9_WIDTH" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">7</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_9_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_10_WIDTH</spirit:name>
       <spirit:displayName>PULSE 10 width</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_10_WIDTH" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">7</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_10_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_11_WIDTH</spirit:name>
       <spirit:displayName>PULSE 11 width</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_11_WIDTH" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">7</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_11_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_12_WIDTH</spirit:name>
       <spirit:displayName>PULSE 12 width</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_12_WIDTH" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">7</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_12_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_13_WIDTH</spirit:name>
       <spirit:displayName>PULSE 13 width</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_13_WIDTH" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">7</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_13_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_14_WIDTH</spirit:name>
       <spirit:displayName>PULSE 14 width</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_14_WIDTH" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">7</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_14_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_15_WIDTH</spirit:name>
       <spirit:displayName>PULSE 15 width</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_15_WIDTH" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">7</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_15_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_0_PERIOD</spirit:name>
       <spirit:displayName>PULSE 0 period</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_0_PERIOD" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">10</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_0_PERIOD">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_1_PERIOD</spirit:name>
       <spirit:displayName>PULSE 1 period</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_1_PERIOD" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">10</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_1_PERIOD">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_2_PERIOD</spirit:name>
       <spirit:displayName>PULSE 2 period</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_2_PERIOD" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">10</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_2_PERIOD">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_3_PERIOD</spirit:name>
       <spirit:displayName>PULSE 3 period</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_3_PERIOD" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">10</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_3_PERIOD">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_4_PERIOD</spirit:name>
       <spirit:displayName>PULSE 4 period</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_4_PERIOD" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">10</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_4_PERIOD">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_5_PERIOD</spirit:name>
       <spirit:displayName>PULSE 5 period</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_5_PERIOD" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">10</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_5_PERIOD">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_6_PERIOD</spirit:name>
       <spirit:displayName>PULSE 6 period</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_6_PERIOD" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">10</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_6_PERIOD">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_7_PERIOD</spirit:name>
       <spirit:displayName>PULSE 7 period</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_7_PERIOD" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">10</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_7_PERIOD">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_8_PERIOD</spirit:name>
       <spirit:displayName>PULSE 8 period</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_8_PERIOD" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">10</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_8_PERIOD">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_9_PERIOD</spirit:name>
       <spirit:displayName>PULSE 9 period</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_9_PERIOD" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">10</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_9_PERIOD">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_10_PERIOD</spirit:name>
       <spirit:displayName>PULSE 10 period</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_10_PERIOD" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">10</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_10_PERIOD">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_11_PERIOD</spirit:name>
       <spirit:displayName>PULSE 11 period</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_11_PERIOD" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">10</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_11_PERIOD">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_12_PERIOD</spirit:name>
       <spirit:displayName>PULSE 12 period</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_12_PERIOD" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">10</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_12_PERIOD">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_13_PERIOD</spirit:name>
       <spirit:displayName>PULSE 13 period</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_13_PERIOD" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">10</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_13_PERIOD">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_14_PERIOD</spirit:name>
       <spirit:displayName>PULSE 14 period</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_14_PERIOD" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">10</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_14_PERIOD">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_15_PERIOD</spirit:name>
       <spirit:displayName>PULSE 15 period</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_15_PERIOD" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">10</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_15_PERIOD">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_0_OFFSET</spirit:name>
       <spirit:displayName>PULSE 0 offset</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_0_OFFSET" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_0_OFFSET">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_1_OFFSET</spirit:name>
       <spirit:displayName>PULSE 1 offset</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_1_OFFSET" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_1_OFFSET">true</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_2_OFFSET</spirit:name>
       <spirit:displayName>PULSE 2 offset</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_2_OFFSET" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_2_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_3_OFFSET</spirit:name>
       <spirit:displayName>PULSE 3 offset</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_3_OFFSET" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_3_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_4_OFFSET</spirit:name>
       <spirit:displayName>PULSE 4 offset</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_4_OFFSET" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_4_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_5_OFFSET</spirit:name>
       <spirit:displayName>PULSE 5 offset</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_5_OFFSET" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_5_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_6_OFFSET</spirit:name>
       <spirit:displayName>PULSE 6 offset</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_6_OFFSET" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_6_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_7_OFFSET</spirit:name>
       <spirit:displayName>PULSE 7 offset</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_7_OFFSET" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_7_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_8_OFFSET</spirit:name>
       <spirit:displayName>PULSE 8 offset</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_8_OFFSET" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_8_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_9_OFFSET</spirit:name>
       <spirit:displayName>PULSE 9 offset</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_9_OFFSET" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_9_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_10_OFFSET</spirit:name>
       <spirit:displayName>PULSE 10 offset</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_10_OFFSET" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_10_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_11_OFFSET</spirit:name>
       <spirit:displayName>PULSE 11 offset</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_11_OFFSET" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_11_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_12_OFFSET</spirit:name>
       <spirit:displayName>PULSE 12 offset</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_12_OFFSET" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_12_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_13_OFFSET</spirit:name>
       <spirit:displayName>PULSE 13 offset</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_13_OFFSET" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_13_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_14_OFFSET</spirit:name>
       <spirit:displayName>PULSE 14 offset</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_14_OFFSET" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_14_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>PULSE_15_OFFSET</spirit:name>
       <spirit:displayName>PULSE 15 offset</spirit:displayName>
       <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PULSE_15_OFFSET" spirit:minimum="0" spirit:maximum="2147483647" spirit:rangeType="long">0</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:resolve="generated" xilinx:id="PARAM_ENABLEMENT.PULSE_15_OFFSET">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>Component_Name</spirit:name>
@@ -1672,14 +2385,14 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:48:40Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:05:23Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="6932666f"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="17a64d95"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="751304d0"/>
-      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="b06f9917"/>
-      <xilinx:checksum xilinx:scope="parameters" xilinx:value="56075b03"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="60155404"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="c47526ac"/>
     </xilinx:packagingInfo>
   </spirit:vendorExtensions>
 </spirit:component>
diff --git a/adi_library/axi_pwm_gen/gui/axi_pwm_gen_v1_0.gtcl b/adi_library/axi_pwm_gen/gui/axi_pwm_gen_v1_0.gtcl
new file mode 100644
index 00000000..73356cc0
--- /dev/null
+++ b/adi_library/axi_pwm_gen/gui/axi_pwm_gen_v1_0.gtcl
@@ -0,0 +1,51 @@
+# This file is automatically written.  Do not modify.
+proc gen_USERPARAMETER_EXT_ASYNC_SYNC_ENABLEMENT {PWM_EXT_SYNC } {expr $PWM_EXT_SYNC == 1}
+proc gen_USERPARAMETER_EXT_SYNC_PHASE_ALIGN_ENABLEMENT {PWM_EXT_SYNC } {expr $PWM_EXT_SYNC == 1}
+proc gen_USERPARAMETER_PULSE_0_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 0}
+proc gen_USERPARAMETER_PULSE_1_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 1}
+proc gen_USERPARAMETER_PULSE_2_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 2}
+proc gen_USERPARAMETER_PULSE_3_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 3}
+proc gen_USERPARAMETER_PULSE_4_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 4}
+proc gen_USERPARAMETER_PULSE_5_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 5}
+proc gen_USERPARAMETER_PULSE_6_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 6}
+proc gen_USERPARAMETER_PULSE_7_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 7}
+proc gen_USERPARAMETER_PULSE_8_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 8}
+proc gen_USERPARAMETER_PULSE_9_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 9}
+proc gen_USERPARAMETER_PULSE_10_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 10}
+proc gen_USERPARAMETER_PULSE_11_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 11}
+proc gen_USERPARAMETER_PULSE_12_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 12}
+proc gen_USERPARAMETER_PULSE_13_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 13}
+proc gen_USERPARAMETER_PULSE_14_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 14}
+proc gen_USERPARAMETER_PULSE_15_WIDTH_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 15}
+proc gen_USERPARAMETER_PULSE_0_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 0}
+proc gen_USERPARAMETER_PULSE_1_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 1}
+proc gen_USERPARAMETER_PULSE_2_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 2}
+proc gen_USERPARAMETER_PULSE_3_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 3}
+proc gen_USERPARAMETER_PULSE_4_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 4}
+proc gen_USERPARAMETER_PULSE_5_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 5}
+proc gen_USERPARAMETER_PULSE_6_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 6}
+proc gen_USERPARAMETER_PULSE_7_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 7}
+proc gen_USERPARAMETER_PULSE_8_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 8}
+proc gen_USERPARAMETER_PULSE_9_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 9}
+proc gen_USERPARAMETER_PULSE_10_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 10}
+proc gen_USERPARAMETER_PULSE_11_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 11}
+proc gen_USERPARAMETER_PULSE_12_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 12}
+proc gen_USERPARAMETER_PULSE_13_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 13}
+proc gen_USERPARAMETER_PULSE_14_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 14}
+proc gen_USERPARAMETER_PULSE_15_PERIOD_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 15}
+proc gen_USERPARAMETER_PULSE_0_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 0}
+proc gen_USERPARAMETER_PULSE_1_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 1}
+proc gen_USERPARAMETER_PULSE_2_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 2}
+proc gen_USERPARAMETER_PULSE_3_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 3}
+proc gen_USERPARAMETER_PULSE_4_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 4}
+proc gen_USERPARAMETER_PULSE_5_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 5}
+proc gen_USERPARAMETER_PULSE_6_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 6}
+proc gen_USERPARAMETER_PULSE_7_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 7}
+proc gen_USERPARAMETER_PULSE_8_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 8}
+proc gen_USERPARAMETER_PULSE_9_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 9}
+proc gen_USERPARAMETER_PULSE_10_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 10}
+proc gen_USERPARAMETER_PULSE_11_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 11}
+proc gen_USERPARAMETER_PULSE_12_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 12}
+proc gen_USERPARAMETER_PULSE_13_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 13}
+proc gen_USERPARAMETER_PULSE_14_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 14}
+proc gen_USERPARAMETER_PULSE_15_OFFSET_ENABLEMENT {N_PWMS } {expr $N_PWMS >= 15}
diff --git a/adi_library/axi_pwm_gen/xgui/axi_pwm_gen_v1_0.tcl b/adi_library/axi_pwm_gen/xgui/axi_pwm_gen_v1_0.tcl
index 10280d1e..0543e3bd 100644
--- a/adi_library/axi_pwm_gen/xgui/axi_pwm_gen_v1_0.tcl
+++ b/adi_library/axi_pwm_gen/xgui/axi_pwm_gen_v1_0.tcl
@@ -1,115 +1,1027 @@
+
+# Loading additional proc with user specified bodies to compute parameter values.
+source [file join [file dirname [file dirname [info script]]] gui/axi_pwm_gen_v1_0.gtcl]
+
 # Definitional proc to organize widgets for parameters.
 proc init_gui { IPINST } {
   ipgui::add_param $IPINST -name "Component_Name"
   #Adding Page
   set AXI_PWM_Generator [ipgui::add_page $IPINST -name "AXI PWM Generator"]
+  ipgui::add_param $IPINST -name "N_PWMS" -parent ${AXI_PWM_Generator}
   set ASYNC_CLK_EN [ipgui::add_param $IPINST -name "ASYNC_CLK_EN" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {External clock for the counter} ${ASYNC_CLK_EN}
+  set_property tooltip {The logic and PWMs will be driven by ext_clk. Otherwise the axi clock will be used} ${ASYNC_CLK_EN}
+  set PWM_EXT_SYNC [ipgui::add_param $IPINST -name "PWM_EXT_SYNC" -parent ${AXI_PWM_Generator} -widget checkBox]
+  set_property tooltip {If active the whole pwm gen module will be waiting for the ext_sync to be set low. A load config or reset must be used before de-asserting the ext_sync to retrigger the sync process} ${PWM_EXT_SYNC}
   set EXT_ASYNC_SYNC [ipgui::add_param $IPINST -name "EXT_ASYNC_SYNC" -parent ${AXI_PWM_Generator} -widget checkBox]
   set_property tooltip {NOTE: If active the ext_sync will be delayed 2 clock cycles.} ${EXT_ASYNC_SYNC}
-  ipgui::add_param $IPINST -name "N_PWMS" -parent ${AXI_PWM_Generator}
-  set PWM_EXT_SYNC [ipgui::add_param $IPINST -name "PWM_EXT_SYNC" -parent ${AXI_PWM_Generator} -widget checkBox]
-  set_property tooltip {NOTE: If active the whole pwm gen module will be waiting for the ext_sync to be set low. A load config or reset must be used before deaserting the ext_sync} ${PWM_EXT_SYNC}
+  set SOFTWARE_BRINGUP [ipgui::add_param $IPINST -name "SOFTWARE_BRINGUP" -parent ${AXI_PWM_Generator} -widget checkBox]
+  set_property tooltip {If active the software must bring the core out of soft reset, after a system reset, in order for the pwm signals to be generated} ${SOFTWARE_BRINGUP}
+  set EXT_SYNC_PHASE_ALIGN [ipgui::add_param $IPINST -name "EXT_SYNC_PHASE_ALIGN" -parent ${AXI_PWM_Generator} -widget checkBox]
+  set_property tooltip {If active the ext_sync will trigger a phase align at each neg-edge. Otherwise the phase align will be armed by a load config toggle. Software over writable at runtime.} ${EXT_SYNC_PHASE_ALIGN}
+  set FORCE_ALIGN [ipgui::add_param $IPINST -name "FORCE_ALIGN" -parent ${AXI_PWM_Generator} -widget checkBox]
+  set_property tooltip {If active the current active pulses are immediately stopped and realigned. Otherwise, the synchronized pulses will start only after all running pulse periods end. Software over writable at runtime.} ${FORCE_ALIGN}
+  set START_AT_SYNC [ipgui::add_param $IPINST -name "START_AT_SYNC" -parent ${AXI_PWM_Generator} -widget checkBox]
+  set_property tooltip {If active, the pulses will start after the trigger event. Otherwise each pulse will start after a period equal to the one for which it is set. Software over writable at runtime.} ${START_AT_SYNC}
   set PULSE_0_WIDTH [ipgui::add_param $IPINST -name "PULSE_0_WIDTH" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_0_WIDTH}
+  set_property tooltip {PULSE width of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_0_WIDTH}
   set PULSE_0_PERIOD [ipgui::add_param $IPINST -name "PULSE_0_PERIOD" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_0_PERIOD}
+  set_property tooltip {Period of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_0_PERIOD}
   set PULSE_0_OFFSET [ipgui::add_param $IPINST -name "PULSE_0_OFFSET" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_0_OFFSET}
+  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval represents a period the system or external clock period.} ${PULSE_0_OFFSET}
   set PULSE_1_WIDTH [ipgui::add_param $IPINST -name "PULSE_1_WIDTH" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_1_WIDTH}
+  set_property tooltip {PULSE width of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_1_WIDTH}
   set PULSE_1_PERIOD [ipgui::add_param $IPINST -name "PULSE_1_PERIOD" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_1_PERIOD}
+  set_property tooltip {Period of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_1_PERIOD}
   set PULSE_1_OFFSET [ipgui::add_param $IPINST -name "PULSE_1_OFFSET" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_1_OFFSET}
+  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval represents a period the system or external clock period.} ${PULSE_1_OFFSET}
   set PULSE_2_WIDTH [ipgui::add_param $IPINST -name "PULSE_2_WIDTH" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_2_WIDTH}
+  set_property tooltip {PULSE width of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_2_WIDTH}
   set PULSE_2_PERIOD [ipgui::add_param $IPINST -name "PULSE_2_PERIOD" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_2_PERIOD}
+  set_property tooltip {Period of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_2_PERIOD}
   set PULSE_2_OFFSET [ipgui::add_param $IPINST -name "PULSE_2_OFFSET" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_2_OFFSET}
+  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval represents a period the system or external clock period.} ${PULSE_2_OFFSET}
   set PULSE_3_WIDTH [ipgui::add_param $IPINST -name "PULSE_3_WIDTH" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_3_WIDTH}
+  set_property tooltip {PULSE width of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_3_WIDTH}
   set PULSE_3_PERIOD [ipgui::add_param $IPINST -name "PULSE_3_PERIOD" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_3_PERIOD}
+  set_property tooltip {Period of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_3_PERIOD}
   set PULSE_3_OFFSET [ipgui::add_param $IPINST -name "PULSE_3_OFFSET" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_3_OFFSET}
+  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval represents a period the system or external clock period.} ${PULSE_3_OFFSET}
   set PULSE_4_WIDTH [ipgui::add_param $IPINST -name "PULSE_4_WIDTH" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_4_WIDTH}
+  set_property tooltip {PULSE width of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_4_WIDTH}
   set PULSE_4_PERIOD [ipgui::add_param $IPINST -name "PULSE_4_PERIOD" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_4_PERIOD}
+  set_property tooltip {Period of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_4_PERIOD}
   set PULSE_4_OFFSET [ipgui::add_param $IPINST -name "PULSE_4_OFFSET" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_4_OFFSET}
+  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval represents a period the system or external clock period.} ${PULSE_4_OFFSET}
   set PULSE_5_WIDTH [ipgui::add_param $IPINST -name "PULSE_5_WIDTH" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_5_WIDTH}
+  set_property tooltip {PULSE width of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_5_WIDTH}
   set PULSE_5_PERIOD [ipgui::add_param $IPINST -name "PULSE_5_PERIOD" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_5_PERIOD}
+  set_property tooltip {Period of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_5_PERIOD}
   set PULSE_5_OFFSET [ipgui::add_param $IPINST -name "PULSE_5_OFFSET" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_5_OFFSET}
+  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval represents a period the system or external clock period.} ${PULSE_5_OFFSET}
   set PULSE_6_WIDTH [ipgui::add_param $IPINST -name "PULSE_6_WIDTH" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_6_WIDTH}
+  set_property tooltip {PULSE width of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_6_WIDTH}
   set PULSE_6_PERIOD [ipgui::add_param $IPINST -name "PULSE_6_PERIOD" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_6_PERIOD}
+  set_property tooltip {Period of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_6_PERIOD}
   set PULSE_6_OFFSET [ipgui::add_param $IPINST -name "PULSE_6_OFFSET" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_6_OFFSET}
+  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval represents a period the system or external clock period.} ${PULSE_6_OFFSET}
   set PULSE_7_WIDTH [ipgui::add_param $IPINST -name "PULSE_7_WIDTH" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_7_WIDTH}
+  set_property tooltip {PULSE width of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_7_WIDTH}
   set PULSE_7_PERIOD [ipgui::add_param $IPINST -name "PULSE_7_PERIOD" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_7_PERIOD}
+  set_property tooltip {Period of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_7_PERIOD}
   set PULSE_7_OFFSET [ipgui::add_param $IPINST -name "PULSE_7_OFFSET" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_7_OFFSET}
+  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval represents a period the system or external clock period.} ${PULSE_7_OFFSET}
   set PULSE_8_WIDTH [ipgui::add_param $IPINST -name "PULSE_8_WIDTH" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_8_WIDTH}
+  set_property tooltip {PULSE width of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_8_WIDTH}
   set PULSE_8_PERIOD [ipgui::add_param $IPINST -name "PULSE_8_PERIOD" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_8_PERIOD}
+  set_property tooltip {Period of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_8_PERIOD}
   set PULSE_8_OFFSET [ipgui::add_param $IPINST -name "PULSE_8_OFFSET" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_8_OFFSET}
+  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval represents a period the system or external clock period.} ${PULSE_8_OFFSET}
   set PULSE_9_WIDTH [ipgui::add_param $IPINST -name "PULSE_9_WIDTH" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_9_WIDTH}
+  set_property tooltip {PULSE width of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_9_WIDTH}
   set PULSE_9_PERIOD [ipgui::add_param $IPINST -name "PULSE_9_PERIOD" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_9_PERIOD}
+  set_property tooltip {Period of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_9_PERIOD}
   set PULSE_9_OFFSET [ipgui::add_param $IPINST -name "PULSE_9_OFFSET" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_9_OFFSET}
+  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval represents a period the system or external clock period.} ${PULSE_9_OFFSET}
   set PULSE_10_WIDTH [ipgui::add_param $IPINST -name "PULSE_10_WIDTH" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_10_WIDTH}
+  set_property tooltip {PULSE width of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_10_WIDTH}
   set PULSE_10_PERIOD [ipgui::add_param $IPINST -name "PULSE_10_PERIOD" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_10_PERIOD}
+  set_property tooltip {Period of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_10_PERIOD}
   set PULSE_10_OFFSET [ipgui::add_param $IPINST -name "PULSE_10_OFFSET" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_10_OFFSET}
+  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval represents a period the system or external clock period.} ${PULSE_10_OFFSET}
   set PULSE_11_WIDTH [ipgui::add_param $IPINST -name "PULSE_11_WIDTH" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_11_WIDTH}
+  set_property tooltip {PULSE width of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_11_WIDTH}
   set PULSE_11_PERIOD [ipgui::add_param $IPINST -name "PULSE_11_PERIOD" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_11_PERIOD}
+  set_property tooltip {Period of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_11_PERIOD}
   set PULSE_11_OFFSET [ipgui::add_param $IPINST -name "PULSE_11_OFFSET" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_11_OFFSET}
+  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval represents a period the system or external clock period.} ${PULSE_11_OFFSET}
   set PULSE_12_WIDTH [ipgui::add_param $IPINST -name "PULSE_12_WIDTH" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_12_WIDTH}
+  set_property tooltip {PULSE width of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_12_WIDTH}
   set PULSE_12_PERIOD [ipgui::add_param $IPINST -name "PULSE_12_PERIOD" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_12_PERIOD}
+  set_property tooltip {Period of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_12_PERIOD}
   set PULSE_12_OFFSET [ipgui::add_param $IPINST -name "PULSE_12_OFFSET" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_12_OFFSET}
+  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval represents a period the system or external clock period.} ${PULSE_12_OFFSET}
   set PULSE_13_WIDTH [ipgui::add_param $IPINST -name "PULSE_13_WIDTH" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_13_WIDTH}
+  set_property tooltip {PULSE width of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_13_WIDTH}
   set PULSE_13_PERIOD [ipgui::add_param $IPINST -name "PULSE_13_PERIOD" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_13_PERIOD}
+  set_property tooltip {Period of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_13_PERIOD}
   set PULSE_13_OFFSET [ipgui::add_param $IPINST -name "PULSE_13_OFFSET" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_13_OFFSET}
+  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval represents a period the system or external clock period.} ${PULSE_13_OFFSET}
   set PULSE_14_WIDTH [ipgui::add_param $IPINST -name "PULSE_14_WIDTH" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_14_WIDTH}
+  set_property tooltip {PULSE width of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_14_WIDTH}
   set PULSE_14_PERIOD [ipgui::add_param $IPINST -name "PULSE_14_PERIOD" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_14_PERIOD}
+  set_property tooltip {Period of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_14_PERIOD}
   set PULSE_14_OFFSET [ipgui::add_param $IPINST -name "PULSE_14_OFFSET" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_14_OFFSET}
+  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval represents a period the system or external clock period.} ${PULSE_14_OFFSET}
   set PULSE_15_WIDTH [ipgui::add_param $IPINST -name "PULSE_15_WIDTH" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_15_WIDTH}
+  set_property tooltip {PULSE width of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_15_WIDTH}
   set PULSE_15_PERIOD [ipgui::add_param $IPINST -name "PULSE_15_PERIOD" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_15_PERIOD}
+  set_property tooltip {Period of the generated signal. The unit interval represents a period the system or external clock period.} ${PULSE_15_PERIOD}
   set PULSE_15_OFFSET [ipgui::add_param $IPINST -name "PULSE_15_OFFSET" -parent ${AXI_PWM_Generator}]
-  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_15_OFFSET}
+  set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval represents a period the system or external clock period.} ${PULSE_15_OFFSET}
 
 
 }
 
+proc update_PARAM_VALUE.EXT_ASYNC_SYNC { PARAM_VALUE.EXT_ASYNC_SYNC PARAM_VALUE.PWM_EXT_SYNC } {
+	# Procedure called to update EXT_ASYNC_SYNC when any of the dependent parameters in the arguments change
+	
+	set EXT_ASYNC_SYNC ${PARAM_VALUE.EXT_ASYNC_SYNC}
+	set PWM_EXT_SYNC ${PARAM_VALUE.PWM_EXT_SYNC}
+	set values(PWM_EXT_SYNC) [get_property value $PWM_EXT_SYNC]
+	if { [gen_USERPARAMETER_EXT_ASYNC_SYNC_ENABLEMENT $values(PWM_EXT_SYNC)] } {
+		set_property enabled true $EXT_ASYNC_SYNC
+	} else {
+		set_property enabled false $EXT_ASYNC_SYNC
+	}
+}
+
+proc validate_PARAM_VALUE.EXT_ASYNC_SYNC { PARAM_VALUE.EXT_ASYNC_SYNC } {
+	# Procedure called to validate EXT_ASYNC_SYNC
+	return true
+}
+
+proc update_PARAM_VALUE.EXT_SYNC_PHASE_ALIGN { PARAM_VALUE.EXT_SYNC_PHASE_ALIGN PARAM_VALUE.PWM_EXT_SYNC } {
+	# Procedure called to update EXT_SYNC_PHASE_ALIGN when any of the dependent parameters in the arguments change
+	
+	set EXT_SYNC_PHASE_ALIGN ${PARAM_VALUE.EXT_SYNC_PHASE_ALIGN}
+	set PWM_EXT_SYNC ${PARAM_VALUE.PWM_EXT_SYNC}
+	set values(PWM_EXT_SYNC) [get_property value $PWM_EXT_SYNC]
+	if { [gen_USERPARAMETER_EXT_SYNC_PHASE_ALIGN_ENABLEMENT $values(PWM_EXT_SYNC)] } {
+		set_property enabled true $EXT_SYNC_PHASE_ALIGN
+	} else {
+		set_property enabled false $EXT_SYNC_PHASE_ALIGN
+	}
+}
+
+proc validate_PARAM_VALUE.EXT_SYNC_PHASE_ALIGN { PARAM_VALUE.EXT_SYNC_PHASE_ALIGN } {
+	# Procedure called to validate EXT_SYNC_PHASE_ALIGN
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_0_OFFSET { PARAM_VALUE.PULSE_0_OFFSET PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_0_OFFSET when any of the dependent parameters in the arguments change
+	
+	set PULSE_0_OFFSET ${PARAM_VALUE.PULSE_0_OFFSET}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_0_OFFSET_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_0_OFFSET
+	} else {
+		set_property enabled false $PULSE_0_OFFSET
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_0_OFFSET { PARAM_VALUE.PULSE_0_OFFSET } {
+	# Procedure called to validate PULSE_0_OFFSET
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_0_PERIOD { PARAM_VALUE.PULSE_0_PERIOD PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_0_PERIOD when any of the dependent parameters in the arguments change
+	
+	set PULSE_0_PERIOD ${PARAM_VALUE.PULSE_0_PERIOD}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_0_PERIOD_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_0_PERIOD
+	} else {
+		set_property enabled false $PULSE_0_PERIOD
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_0_PERIOD { PARAM_VALUE.PULSE_0_PERIOD } {
+	# Procedure called to validate PULSE_0_PERIOD
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_0_WIDTH { PARAM_VALUE.PULSE_0_WIDTH PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_0_WIDTH when any of the dependent parameters in the arguments change
+	
+	set PULSE_0_WIDTH ${PARAM_VALUE.PULSE_0_WIDTH}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_0_WIDTH_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_0_WIDTH
+	} else {
+		set_property enabled false $PULSE_0_WIDTH
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_0_WIDTH { PARAM_VALUE.PULSE_0_WIDTH } {
+	# Procedure called to validate PULSE_0_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_10_OFFSET { PARAM_VALUE.PULSE_10_OFFSET PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_10_OFFSET when any of the dependent parameters in the arguments change
+	
+	set PULSE_10_OFFSET ${PARAM_VALUE.PULSE_10_OFFSET}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_10_OFFSET_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_10_OFFSET
+	} else {
+		set_property enabled false $PULSE_10_OFFSET
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_10_OFFSET { PARAM_VALUE.PULSE_10_OFFSET } {
+	# Procedure called to validate PULSE_10_OFFSET
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_10_PERIOD { PARAM_VALUE.PULSE_10_PERIOD PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_10_PERIOD when any of the dependent parameters in the arguments change
+	
+	set PULSE_10_PERIOD ${PARAM_VALUE.PULSE_10_PERIOD}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_10_PERIOD_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_10_PERIOD
+	} else {
+		set_property enabled false $PULSE_10_PERIOD
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_10_PERIOD { PARAM_VALUE.PULSE_10_PERIOD } {
+	# Procedure called to validate PULSE_10_PERIOD
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_10_WIDTH { PARAM_VALUE.PULSE_10_WIDTH PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_10_WIDTH when any of the dependent parameters in the arguments change
+	
+	set PULSE_10_WIDTH ${PARAM_VALUE.PULSE_10_WIDTH}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_10_WIDTH_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_10_WIDTH
+	} else {
+		set_property enabled false $PULSE_10_WIDTH
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_10_WIDTH { PARAM_VALUE.PULSE_10_WIDTH } {
+	# Procedure called to validate PULSE_10_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_11_OFFSET { PARAM_VALUE.PULSE_11_OFFSET PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_11_OFFSET when any of the dependent parameters in the arguments change
+	
+	set PULSE_11_OFFSET ${PARAM_VALUE.PULSE_11_OFFSET}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_11_OFFSET_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_11_OFFSET
+	} else {
+		set_property enabled false $PULSE_11_OFFSET
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_11_OFFSET { PARAM_VALUE.PULSE_11_OFFSET } {
+	# Procedure called to validate PULSE_11_OFFSET
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_11_PERIOD { PARAM_VALUE.PULSE_11_PERIOD PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_11_PERIOD when any of the dependent parameters in the arguments change
+	
+	set PULSE_11_PERIOD ${PARAM_VALUE.PULSE_11_PERIOD}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_11_PERIOD_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_11_PERIOD
+	} else {
+		set_property enabled false $PULSE_11_PERIOD
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_11_PERIOD { PARAM_VALUE.PULSE_11_PERIOD } {
+	# Procedure called to validate PULSE_11_PERIOD
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_11_WIDTH { PARAM_VALUE.PULSE_11_WIDTH PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_11_WIDTH when any of the dependent parameters in the arguments change
+	
+	set PULSE_11_WIDTH ${PARAM_VALUE.PULSE_11_WIDTH}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_11_WIDTH_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_11_WIDTH
+	} else {
+		set_property enabled false $PULSE_11_WIDTH
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_11_WIDTH { PARAM_VALUE.PULSE_11_WIDTH } {
+	# Procedure called to validate PULSE_11_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_12_OFFSET { PARAM_VALUE.PULSE_12_OFFSET PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_12_OFFSET when any of the dependent parameters in the arguments change
+	
+	set PULSE_12_OFFSET ${PARAM_VALUE.PULSE_12_OFFSET}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_12_OFFSET_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_12_OFFSET
+	} else {
+		set_property enabled false $PULSE_12_OFFSET
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_12_OFFSET { PARAM_VALUE.PULSE_12_OFFSET } {
+	# Procedure called to validate PULSE_12_OFFSET
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_12_PERIOD { PARAM_VALUE.PULSE_12_PERIOD PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_12_PERIOD when any of the dependent parameters in the arguments change
+	
+	set PULSE_12_PERIOD ${PARAM_VALUE.PULSE_12_PERIOD}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_12_PERIOD_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_12_PERIOD
+	} else {
+		set_property enabled false $PULSE_12_PERIOD
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_12_PERIOD { PARAM_VALUE.PULSE_12_PERIOD } {
+	# Procedure called to validate PULSE_12_PERIOD
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_12_WIDTH { PARAM_VALUE.PULSE_12_WIDTH PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_12_WIDTH when any of the dependent parameters in the arguments change
+	
+	set PULSE_12_WIDTH ${PARAM_VALUE.PULSE_12_WIDTH}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_12_WIDTH_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_12_WIDTH
+	} else {
+		set_property enabled false $PULSE_12_WIDTH
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_12_WIDTH { PARAM_VALUE.PULSE_12_WIDTH } {
+	# Procedure called to validate PULSE_12_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_13_OFFSET { PARAM_VALUE.PULSE_13_OFFSET PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_13_OFFSET when any of the dependent parameters in the arguments change
+	
+	set PULSE_13_OFFSET ${PARAM_VALUE.PULSE_13_OFFSET}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_13_OFFSET_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_13_OFFSET
+	} else {
+		set_property enabled false $PULSE_13_OFFSET
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_13_OFFSET { PARAM_VALUE.PULSE_13_OFFSET } {
+	# Procedure called to validate PULSE_13_OFFSET
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_13_PERIOD { PARAM_VALUE.PULSE_13_PERIOD PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_13_PERIOD when any of the dependent parameters in the arguments change
+	
+	set PULSE_13_PERIOD ${PARAM_VALUE.PULSE_13_PERIOD}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_13_PERIOD_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_13_PERIOD
+	} else {
+		set_property enabled false $PULSE_13_PERIOD
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_13_PERIOD { PARAM_VALUE.PULSE_13_PERIOD } {
+	# Procedure called to validate PULSE_13_PERIOD
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_13_WIDTH { PARAM_VALUE.PULSE_13_WIDTH PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_13_WIDTH when any of the dependent parameters in the arguments change
+	
+	set PULSE_13_WIDTH ${PARAM_VALUE.PULSE_13_WIDTH}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_13_WIDTH_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_13_WIDTH
+	} else {
+		set_property enabled false $PULSE_13_WIDTH
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_13_WIDTH { PARAM_VALUE.PULSE_13_WIDTH } {
+	# Procedure called to validate PULSE_13_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_14_OFFSET { PARAM_VALUE.PULSE_14_OFFSET PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_14_OFFSET when any of the dependent parameters in the arguments change
+	
+	set PULSE_14_OFFSET ${PARAM_VALUE.PULSE_14_OFFSET}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_14_OFFSET_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_14_OFFSET
+	} else {
+		set_property enabled false $PULSE_14_OFFSET
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_14_OFFSET { PARAM_VALUE.PULSE_14_OFFSET } {
+	# Procedure called to validate PULSE_14_OFFSET
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_14_PERIOD { PARAM_VALUE.PULSE_14_PERIOD PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_14_PERIOD when any of the dependent parameters in the arguments change
+	
+	set PULSE_14_PERIOD ${PARAM_VALUE.PULSE_14_PERIOD}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_14_PERIOD_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_14_PERIOD
+	} else {
+		set_property enabled false $PULSE_14_PERIOD
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_14_PERIOD { PARAM_VALUE.PULSE_14_PERIOD } {
+	# Procedure called to validate PULSE_14_PERIOD
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_14_WIDTH { PARAM_VALUE.PULSE_14_WIDTH PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_14_WIDTH when any of the dependent parameters in the arguments change
+	
+	set PULSE_14_WIDTH ${PARAM_VALUE.PULSE_14_WIDTH}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_14_WIDTH_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_14_WIDTH
+	} else {
+		set_property enabled false $PULSE_14_WIDTH
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_14_WIDTH { PARAM_VALUE.PULSE_14_WIDTH } {
+	# Procedure called to validate PULSE_14_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_15_OFFSET { PARAM_VALUE.PULSE_15_OFFSET PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_15_OFFSET when any of the dependent parameters in the arguments change
+	
+	set PULSE_15_OFFSET ${PARAM_VALUE.PULSE_15_OFFSET}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_15_OFFSET_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_15_OFFSET
+	} else {
+		set_property enabled false $PULSE_15_OFFSET
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_15_OFFSET { PARAM_VALUE.PULSE_15_OFFSET } {
+	# Procedure called to validate PULSE_15_OFFSET
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_15_PERIOD { PARAM_VALUE.PULSE_15_PERIOD PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_15_PERIOD when any of the dependent parameters in the arguments change
+	
+	set PULSE_15_PERIOD ${PARAM_VALUE.PULSE_15_PERIOD}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_15_PERIOD_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_15_PERIOD
+	} else {
+		set_property enabled false $PULSE_15_PERIOD
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_15_PERIOD { PARAM_VALUE.PULSE_15_PERIOD } {
+	# Procedure called to validate PULSE_15_PERIOD
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_15_WIDTH { PARAM_VALUE.PULSE_15_WIDTH PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_15_WIDTH when any of the dependent parameters in the arguments change
+	
+	set PULSE_15_WIDTH ${PARAM_VALUE.PULSE_15_WIDTH}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_15_WIDTH_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_15_WIDTH
+	} else {
+		set_property enabled false $PULSE_15_WIDTH
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_15_WIDTH { PARAM_VALUE.PULSE_15_WIDTH } {
+	# Procedure called to validate PULSE_15_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_1_OFFSET { PARAM_VALUE.PULSE_1_OFFSET PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_1_OFFSET when any of the dependent parameters in the arguments change
+	
+	set PULSE_1_OFFSET ${PARAM_VALUE.PULSE_1_OFFSET}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_1_OFFSET_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_1_OFFSET
+	} else {
+		set_property enabled false $PULSE_1_OFFSET
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_1_OFFSET { PARAM_VALUE.PULSE_1_OFFSET } {
+	# Procedure called to validate PULSE_1_OFFSET
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_1_PERIOD { PARAM_VALUE.PULSE_1_PERIOD PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_1_PERIOD when any of the dependent parameters in the arguments change
+	
+	set PULSE_1_PERIOD ${PARAM_VALUE.PULSE_1_PERIOD}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_1_PERIOD_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_1_PERIOD
+	} else {
+		set_property enabled false $PULSE_1_PERIOD
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_1_PERIOD { PARAM_VALUE.PULSE_1_PERIOD } {
+	# Procedure called to validate PULSE_1_PERIOD
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_1_WIDTH { PARAM_VALUE.PULSE_1_WIDTH PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_1_WIDTH when any of the dependent parameters in the arguments change
+	
+	set PULSE_1_WIDTH ${PARAM_VALUE.PULSE_1_WIDTH}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_1_WIDTH_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_1_WIDTH
+	} else {
+		set_property enabled false $PULSE_1_WIDTH
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_1_WIDTH { PARAM_VALUE.PULSE_1_WIDTH } {
+	# Procedure called to validate PULSE_1_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_2_OFFSET { PARAM_VALUE.PULSE_2_OFFSET PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_2_OFFSET when any of the dependent parameters in the arguments change
+	
+	set PULSE_2_OFFSET ${PARAM_VALUE.PULSE_2_OFFSET}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_2_OFFSET_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_2_OFFSET
+	} else {
+		set_property enabled false $PULSE_2_OFFSET
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_2_OFFSET { PARAM_VALUE.PULSE_2_OFFSET } {
+	# Procedure called to validate PULSE_2_OFFSET
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_2_PERIOD { PARAM_VALUE.PULSE_2_PERIOD PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_2_PERIOD when any of the dependent parameters in the arguments change
+	
+	set PULSE_2_PERIOD ${PARAM_VALUE.PULSE_2_PERIOD}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_2_PERIOD_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_2_PERIOD
+	} else {
+		set_property enabled false $PULSE_2_PERIOD
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_2_PERIOD { PARAM_VALUE.PULSE_2_PERIOD } {
+	# Procedure called to validate PULSE_2_PERIOD
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_2_WIDTH { PARAM_VALUE.PULSE_2_WIDTH PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_2_WIDTH when any of the dependent parameters in the arguments change
+	
+	set PULSE_2_WIDTH ${PARAM_VALUE.PULSE_2_WIDTH}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_2_WIDTH_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_2_WIDTH
+	} else {
+		set_property enabled false $PULSE_2_WIDTH
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_2_WIDTH { PARAM_VALUE.PULSE_2_WIDTH } {
+	# Procedure called to validate PULSE_2_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_3_OFFSET { PARAM_VALUE.PULSE_3_OFFSET PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_3_OFFSET when any of the dependent parameters in the arguments change
+	
+	set PULSE_3_OFFSET ${PARAM_VALUE.PULSE_3_OFFSET}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_3_OFFSET_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_3_OFFSET
+	} else {
+		set_property enabled false $PULSE_3_OFFSET
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_3_OFFSET { PARAM_VALUE.PULSE_3_OFFSET } {
+	# Procedure called to validate PULSE_3_OFFSET
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_3_PERIOD { PARAM_VALUE.PULSE_3_PERIOD PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_3_PERIOD when any of the dependent parameters in the arguments change
+	
+	set PULSE_3_PERIOD ${PARAM_VALUE.PULSE_3_PERIOD}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_3_PERIOD_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_3_PERIOD
+	} else {
+		set_property enabled false $PULSE_3_PERIOD
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_3_PERIOD { PARAM_VALUE.PULSE_3_PERIOD } {
+	# Procedure called to validate PULSE_3_PERIOD
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_3_WIDTH { PARAM_VALUE.PULSE_3_WIDTH PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_3_WIDTH when any of the dependent parameters in the arguments change
+	
+	set PULSE_3_WIDTH ${PARAM_VALUE.PULSE_3_WIDTH}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_3_WIDTH_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_3_WIDTH
+	} else {
+		set_property enabled false $PULSE_3_WIDTH
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_3_WIDTH { PARAM_VALUE.PULSE_3_WIDTH } {
+	# Procedure called to validate PULSE_3_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_4_OFFSET { PARAM_VALUE.PULSE_4_OFFSET PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_4_OFFSET when any of the dependent parameters in the arguments change
+	
+	set PULSE_4_OFFSET ${PARAM_VALUE.PULSE_4_OFFSET}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_4_OFFSET_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_4_OFFSET
+	} else {
+		set_property enabled false $PULSE_4_OFFSET
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_4_OFFSET { PARAM_VALUE.PULSE_4_OFFSET } {
+	# Procedure called to validate PULSE_4_OFFSET
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_4_PERIOD { PARAM_VALUE.PULSE_4_PERIOD PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_4_PERIOD when any of the dependent parameters in the arguments change
+	
+	set PULSE_4_PERIOD ${PARAM_VALUE.PULSE_4_PERIOD}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_4_PERIOD_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_4_PERIOD
+	} else {
+		set_property enabled false $PULSE_4_PERIOD
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_4_PERIOD { PARAM_VALUE.PULSE_4_PERIOD } {
+	# Procedure called to validate PULSE_4_PERIOD
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_4_WIDTH { PARAM_VALUE.PULSE_4_WIDTH PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_4_WIDTH when any of the dependent parameters in the arguments change
+	
+	set PULSE_4_WIDTH ${PARAM_VALUE.PULSE_4_WIDTH}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_4_WIDTH_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_4_WIDTH
+	} else {
+		set_property enabled false $PULSE_4_WIDTH
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_4_WIDTH { PARAM_VALUE.PULSE_4_WIDTH } {
+	# Procedure called to validate PULSE_4_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_5_OFFSET { PARAM_VALUE.PULSE_5_OFFSET PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_5_OFFSET when any of the dependent parameters in the arguments change
+	
+	set PULSE_5_OFFSET ${PARAM_VALUE.PULSE_5_OFFSET}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_5_OFFSET_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_5_OFFSET
+	} else {
+		set_property enabled false $PULSE_5_OFFSET
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_5_OFFSET { PARAM_VALUE.PULSE_5_OFFSET } {
+	# Procedure called to validate PULSE_5_OFFSET
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_5_PERIOD { PARAM_VALUE.PULSE_5_PERIOD PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_5_PERIOD when any of the dependent parameters in the arguments change
+	
+	set PULSE_5_PERIOD ${PARAM_VALUE.PULSE_5_PERIOD}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_5_PERIOD_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_5_PERIOD
+	} else {
+		set_property enabled false $PULSE_5_PERIOD
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_5_PERIOD { PARAM_VALUE.PULSE_5_PERIOD } {
+	# Procedure called to validate PULSE_5_PERIOD
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_5_WIDTH { PARAM_VALUE.PULSE_5_WIDTH PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_5_WIDTH when any of the dependent parameters in the arguments change
+	
+	set PULSE_5_WIDTH ${PARAM_VALUE.PULSE_5_WIDTH}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_5_WIDTH_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_5_WIDTH
+	} else {
+		set_property enabled false $PULSE_5_WIDTH
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_5_WIDTH { PARAM_VALUE.PULSE_5_WIDTH } {
+	# Procedure called to validate PULSE_5_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_6_OFFSET { PARAM_VALUE.PULSE_6_OFFSET PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_6_OFFSET when any of the dependent parameters in the arguments change
+	
+	set PULSE_6_OFFSET ${PARAM_VALUE.PULSE_6_OFFSET}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_6_OFFSET_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_6_OFFSET
+	} else {
+		set_property enabled false $PULSE_6_OFFSET
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_6_OFFSET { PARAM_VALUE.PULSE_6_OFFSET } {
+	# Procedure called to validate PULSE_6_OFFSET
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_6_PERIOD { PARAM_VALUE.PULSE_6_PERIOD PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_6_PERIOD when any of the dependent parameters in the arguments change
+	
+	set PULSE_6_PERIOD ${PARAM_VALUE.PULSE_6_PERIOD}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_6_PERIOD_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_6_PERIOD
+	} else {
+		set_property enabled false $PULSE_6_PERIOD
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_6_PERIOD { PARAM_VALUE.PULSE_6_PERIOD } {
+	# Procedure called to validate PULSE_6_PERIOD
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_6_WIDTH { PARAM_VALUE.PULSE_6_WIDTH PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_6_WIDTH when any of the dependent parameters in the arguments change
+	
+	set PULSE_6_WIDTH ${PARAM_VALUE.PULSE_6_WIDTH}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_6_WIDTH_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_6_WIDTH
+	} else {
+		set_property enabled false $PULSE_6_WIDTH
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_6_WIDTH { PARAM_VALUE.PULSE_6_WIDTH } {
+	# Procedure called to validate PULSE_6_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_7_OFFSET { PARAM_VALUE.PULSE_7_OFFSET PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_7_OFFSET when any of the dependent parameters in the arguments change
+	
+	set PULSE_7_OFFSET ${PARAM_VALUE.PULSE_7_OFFSET}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_7_OFFSET_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_7_OFFSET
+	} else {
+		set_property enabled false $PULSE_7_OFFSET
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_7_OFFSET { PARAM_VALUE.PULSE_7_OFFSET } {
+	# Procedure called to validate PULSE_7_OFFSET
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_7_PERIOD { PARAM_VALUE.PULSE_7_PERIOD PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_7_PERIOD when any of the dependent parameters in the arguments change
+	
+	set PULSE_7_PERIOD ${PARAM_VALUE.PULSE_7_PERIOD}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_7_PERIOD_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_7_PERIOD
+	} else {
+		set_property enabled false $PULSE_7_PERIOD
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_7_PERIOD { PARAM_VALUE.PULSE_7_PERIOD } {
+	# Procedure called to validate PULSE_7_PERIOD
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_7_WIDTH { PARAM_VALUE.PULSE_7_WIDTH PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_7_WIDTH when any of the dependent parameters in the arguments change
+	
+	set PULSE_7_WIDTH ${PARAM_VALUE.PULSE_7_WIDTH}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_7_WIDTH_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_7_WIDTH
+	} else {
+		set_property enabled false $PULSE_7_WIDTH
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_7_WIDTH { PARAM_VALUE.PULSE_7_WIDTH } {
+	# Procedure called to validate PULSE_7_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_8_OFFSET { PARAM_VALUE.PULSE_8_OFFSET PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_8_OFFSET when any of the dependent parameters in the arguments change
+	
+	set PULSE_8_OFFSET ${PARAM_VALUE.PULSE_8_OFFSET}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_8_OFFSET_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_8_OFFSET
+	} else {
+		set_property enabled false $PULSE_8_OFFSET
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_8_OFFSET { PARAM_VALUE.PULSE_8_OFFSET } {
+	# Procedure called to validate PULSE_8_OFFSET
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_8_PERIOD { PARAM_VALUE.PULSE_8_PERIOD PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_8_PERIOD when any of the dependent parameters in the arguments change
+	
+	set PULSE_8_PERIOD ${PARAM_VALUE.PULSE_8_PERIOD}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_8_PERIOD_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_8_PERIOD
+	} else {
+		set_property enabled false $PULSE_8_PERIOD
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_8_PERIOD { PARAM_VALUE.PULSE_8_PERIOD } {
+	# Procedure called to validate PULSE_8_PERIOD
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_8_WIDTH { PARAM_VALUE.PULSE_8_WIDTH PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_8_WIDTH when any of the dependent parameters in the arguments change
+	
+	set PULSE_8_WIDTH ${PARAM_VALUE.PULSE_8_WIDTH}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_8_WIDTH_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_8_WIDTH
+	} else {
+		set_property enabled false $PULSE_8_WIDTH
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_8_WIDTH { PARAM_VALUE.PULSE_8_WIDTH } {
+	# Procedure called to validate PULSE_8_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_9_OFFSET { PARAM_VALUE.PULSE_9_OFFSET PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_9_OFFSET when any of the dependent parameters in the arguments change
+	
+	set PULSE_9_OFFSET ${PARAM_VALUE.PULSE_9_OFFSET}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_9_OFFSET_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_9_OFFSET
+	} else {
+		set_property enabled false $PULSE_9_OFFSET
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_9_OFFSET { PARAM_VALUE.PULSE_9_OFFSET } {
+	# Procedure called to validate PULSE_9_OFFSET
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_9_PERIOD { PARAM_VALUE.PULSE_9_PERIOD PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_9_PERIOD when any of the dependent parameters in the arguments change
+	
+	set PULSE_9_PERIOD ${PARAM_VALUE.PULSE_9_PERIOD}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_9_PERIOD_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_9_PERIOD
+	} else {
+		set_property enabled false $PULSE_9_PERIOD
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_9_PERIOD { PARAM_VALUE.PULSE_9_PERIOD } {
+	# Procedure called to validate PULSE_9_PERIOD
+	return true
+}
+
+proc update_PARAM_VALUE.PULSE_9_WIDTH { PARAM_VALUE.PULSE_9_WIDTH PARAM_VALUE.N_PWMS } {
+	# Procedure called to update PULSE_9_WIDTH when any of the dependent parameters in the arguments change
+	
+	set PULSE_9_WIDTH ${PARAM_VALUE.PULSE_9_WIDTH}
+	set N_PWMS ${PARAM_VALUE.N_PWMS}
+	set values(N_PWMS) [get_property value $N_PWMS]
+	if { [gen_USERPARAMETER_PULSE_9_WIDTH_ENABLEMENT $values(N_PWMS)] } {
+		set_property enabled true $PULSE_9_WIDTH
+	} else {
+		set_property enabled false $PULSE_9_WIDTH
+	}
+}
+
+proc validate_PARAM_VALUE.PULSE_9_WIDTH { PARAM_VALUE.PULSE_9_WIDTH } {
+	# Procedure called to validate PULSE_9_WIDTH
+	return true
+}
+
 proc update_PARAM_VALUE.ASYNC_CLK_EN { PARAM_VALUE.ASYNC_CLK_EN } {
 	# Procedure called to update ASYNC_CLK_EN when any of the dependent parameters in the arguments change
 }
@@ -119,12 +1031,12 @@ proc validate_PARAM_VALUE.ASYNC_CLK_EN { PARAM_VALUE.ASYNC_CLK_EN } {
 	return true
 }
 
-proc update_PARAM_VALUE.EXT_ASYNC_SYNC { PARAM_VALUE.EXT_ASYNC_SYNC } {
-	# Procedure called to update EXT_ASYNC_SYNC when any of the dependent parameters in the arguments change
+proc update_PARAM_VALUE.FORCE_ALIGN { PARAM_VALUE.FORCE_ALIGN } {
+	# Procedure called to update FORCE_ALIGN when any of the dependent parameters in the arguments change
 }
 
-proc validate_PARAM_VALUE.EXT_ASYNC_SYNC { PARAM_VALUE.EXT_ASYNC_SYNC } {
-	# Procedure called to validate EXT_ASYNC_SYNC
+proc validate_PARAM_VALUE.FORCE_ALIGN { PARAM_VALUE.FORCE_ALIGN } {
+	# Procedure called to validate FORCE_ALIGN
 	return true
 }
 
@@ -146,438 +1058,6 @@ proc validate_PARAM_VALUE.N_PWMS { PARAM_VALUE.N_PWMS } {
 	return true
 }
 
-proc update_PARAM_VALUE.PULSE_0_OFFSET { PARAM_VALUE.PULSE_0_OFFSET } {
-	# Procedure called to update PULSE_0_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_0_OFFSET { PARAM_VALUE.PULSE_0_OFFSET } {
-	# Procedure called to validate PULSE_0_OFFSET
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_0_PERIOD { PARAM_VALUE.PULSE_0_PERIOD } {
-	# Procedure called to update PULSE_0_PERIOD when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_0_PERIOD { PARAM_VALUE.PULSE_0_PERIOD } {
-	# Procedure called to validate PULSE_0_PERIOD
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_0_WIDTH { PARAM_VALUE.PULSE_0_WIDTH } {
-	# Procedure called to update PULSE_0_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_0_WIDTH { PARAM_VALUE.PULSE_0_WIDTH } {
-	# Procedure called to validate PULSE_0_WIDTH
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_10_OFFSET { PARAM_VALUE.PULSE_10_OFFSET } {
-	# Procedure called to update PULSE_10_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_10_OFFSET { PARAM_VALUE.PULSE_10_OFFSET } {
-	# Procedure called to validate PULSE_10_OFFSET
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_10_PERIOD { PARAM_VALUE.PULSE_10_PERIOD } {
-	# Procedure called to update PULSE_10_PERIOD when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_10_PERIOD { PARAM_VALUE.PULSE_10_PERIOD } {
-	# Procedure called to validate PULSE_10_PERIOD
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_10_WIDTH { PARAM_VALUE.PULSE_10_WIDTH } {
-	# Procedure called to update PULSE_10_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_10_WIDTH { PARAM_VALUE.PULSE_10_WIDTH } {
-	# Procedure called to validate PULSE_10_WIDTH
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_11_OFFSET { PARAM_VALUE.PULSE_11_OFFSET } {
-	# Procedure called to update PULSE_11_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_11_OFFSET { PARAM_VALUE.PULSE_11_OFFSET } {
-	# Procedure called to validate PULSE_11_OFFSET
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_11_PERIOD { PARAM_VALUE.PULSE_11_PERIOD } {
-	# Procedure called to update PULSE_11_PERIOD when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_11_PERIOD { PARAM_VALUE.PULSE_11_PERIOD } {
-	# Procedure called to validate PULSE_11_PERIOD
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_11_WIDTH { PARAM_VALUE.PULSE_11_WIDTH } {
-	# Procedure called to update PULSE_11_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_11_WIDTH { PARAM_VALUE.PULSE_11_WIDTH } {
-	# Procedure called to validate PULSE_11_WIDTH
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_12_OFFSET { PARAM_VALUE.PULSE_12_OFFSET } {
-	# Procedure called to update PULSE_12_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_12_OFFSET { PARAM_VALUE.PULSE_12_OFFSET } {
-	# Procedure called to validate PULSE_12_OFFSET
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_12_PERIOD { PARAM_VALUE.PULSE_12_PERIOD } {
-	# Procedure called to update PULSE_12_PERIOD when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_12_PERIOD { PARAM_VALUE.PULSE_12_PERIOD } {
-	# Procedure called to validate PULSE_12_PERIOD
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_12_WIDTH { PARAM_VALUE.PULSE_12_WIDTH } {
-	# Procedure called to update PULSE_12_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_12_WIDTH { PARAM_VALUE.PULSE_12_WIDTH } {
-	# Procedure called to validate PULSE_12_WIDTH
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_13_OFFSET { PARAM_VALUE.PULSE_13_OFFSET } {
-	# Procedure called to update PULSE_13_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_13_OFFSET { PARAM_VALUE.PULSE_13_OFFSET } {
-	# Procedure called to validate PULSE_13_OFFSET
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_13_PERIOD { PARAM_VALUE.PULSE_13_PERIOD } {
-	# Procedure called to update PULSE_13_PERIOD when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_13_PERIOD { PARAM_VALUE.PULSE_13_PERIOD } {
-	# Procedure called to validate PULSE_13_PERIOD
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_13_WIDTH { PARAM_VALUE.PULSE_13_WIDTH } {
-	# Procedure called to update PULSE_13_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_13_WIDTH { PARAM_VALUE.PULSE_13_WIDTH } {
-	# Procedure called to validate PULSE_13_WIDTH
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_14_OFFSET { PARAM_VALUE.PULSE_14_OFFSET } {
-	# Procedure called to update PULSE_14_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_14_OFFSET { PARAM_VALUE.PULSE_14_OFFSET } {
-	# Procedure called to validate PULSE_14_OFFSET
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_14_PERIOD { PARAM_VALUE.PULSE_14_PERIOD } {
-	# Procedure called to update PULSE_14_PERIOD when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_14_PERIOD { PARAM_VALUE.PULSE_14_PERIOD } {
-	# Procedure called to validate PULSE_14_PERIOD
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_14_WIDTH { PARAM_VALUE.PULSE_14_WIDTH } {
-	# Procedure called to update PULSE_14_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_14_WIDTH { PARAM_VALUE.PULSE_14_WIDTH } {
-	# Procedure called to validate PULSE_14_WIDTH
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_15_OFFSET { PARAM_VALUE.PULSE_15_OFFSET } {
-	# Procedure called to update PULSE_15_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_15_OFFSET { PARAM_VALUE.PULSE_15_OFFSET } {
-	# Procedure called to validate PULSE_15_OFFSET
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_15_PERIOD { PARAM_VALUE.PULSE_15_PERIOD } {
-	# Procedure called to update PULSE_15_PERIOD when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_15_PERIOD { PARAM_VALUE.PULSE_15_PERIOD } {
-	# Procedure called to validate PULSE_15_PERIOD
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_15_WIDTH { PARAM_VALUE.PULSE_15_WIDTH } {
-	# Procedure called to update PULSE_15_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_15_WIDTH { PARAM_VALUE.PULSE_15_WIDTH } {
-	# Procedure called to validate PULSE_15_WIDTH
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_1_OFFSET { PARAM_VALUE.PULSE_1_OFFSET } {
-	# Procedure called to update PULSE_1_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_1_OFFSET { PARAM_VALUE.PULSE_1_OFFSET } {
-	# Procedure called to validate PULSE_1_OFFSET
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_1_PERIOD { PARAM_VALUE.PULSE_1_PERIOD } {
-	# Procedure called to update PULSE_1_PERIOD when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_1_PERIOD { PARAM_VALUE.PULSE_1_PERIOD } {
-	# Procedure called to validate PULSE_1_PERIOD
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_1_WIDTH { PARAM_VALUE.PULSE_1_WIDTH } {
-	# Procedure called to update PULSE_1_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_1_WIDTH { PARAM_VALUE.PULSE_1_WIDTH } {
-	# Procedure called to validate PULSE_1_WIDTH
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_2_OFFSET { PARAM_VALUE.PULSE_2_OFFSET } {
-	# Procedure called to update PULSE_2_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_2_OFFSET { PARAM_VALUE.PULSE_2_OFFSET } {
-	# Procedure called to validate PULSE_2_OFFSET
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_2_PERIOD { PARAM_VALUE.PULSE_2_PERIOD } {
-	# Procedure called to update PULSE_2_PERIOD when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_2_PERIOD { PARAM_VALUE.PULSE_2_PERIOD } {
-	# Procedure called to validate PULSE_2_PERIOD
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_2_WIDTH { PARAM_VALUE.PULSE_2_WIDTH } {
-	# Procedure called to update PULSE_2_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_2_WIDTH { PARAM_VALUE.PULSE_2_WIDTH } {
-	# Procedure called to validate PULSE_2_WIDTH
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_3_OFFSET { PARAM_VALUE.PULSE_3_OFFSET } {
-	# Procedure called to update PULSE_3_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_3_OFFSET { PARAM_VALUE.PULSE_3_OFFSET } {
-	# Procedure called to validate PULSE_3_OFFSET
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_3_PERIOD { PARAM_VALUE.PULSE_3_PERIOD } {
-	# Procedure called to update PULSE_3_PERIOD when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_3_PERIOD { PARAM_VALUE.PULSE_3_PERIOD } {
-	# Procedure called to validate PULSE_3_PERIOD
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_3_WIDTH { PARAM_VALUE.PULSE_3_WIDTH } {
-	# Procedure called to update PULSE_3_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_3_WIDTH { PARAM_VALUE.PULSE_3_WIDTH } {
-	# Procedure called to validate PULSE_3_WIDTH
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_4_OFFSET { PARAM_VALUE.PULSE_4_OFFSET } {
-	# Procedure called to update PULSE_4_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_4_OFFSET { PARAM_VALUE.PULSE_4_OFFSET } {
-	# Procedure called to validate PULSE_4_OFFSET
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_4_PERIOD { PARAM_VALUE.PULSE_4_PERIOD } {
-	# Procedure called to update PULSE_4_PERIOD when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_4_PERIOD { PARAM_VALUE.PULSE_4_PERIOD } {
-	# Procedure called to validate PULSE_4_PERIOD
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_4_WIDTH { PARAM_VALUE.PULSE_4_WIDTH } {
-	# Procedure called to update PULSE_4_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_4_WIDTH { PARAM_VALUE.PULSE_4_WIDTH } {
-	# Procedure called to validate PULSE_4_WIDTH
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_5_OFFSET { PARAM_VALUE.PULSE_5_OFFSET } {
-	# Procedure called to update PULSE_5_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_5_OFFSET { PARAM_VALUE.PULSE_5_OFFSET } {
-	# Procedure called to validate PULSE_5_OFFSET
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_5_PERIOD { PARAM_VALUE.PULSE_5_PERIOD } {
-	# Procedure called to update PULSE_5_PERIOD when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_5_PERIOD { PARAM_VALUE.PULSE_5_PERIOD } {
-	# Procedure called to validate PULSE_5_PERIOD
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_5_WIDTH { PARAM_VALUE.PULSE_5_WIDTH } {
-	# Procedure called to update PULSE_5_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_5_WIDTH { PARAM_VALUE.PULSE_5_WIDTH } {
-	# Procedure called to validate PULSE_5_WIDTH
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_6_OFFSET { PARAM_VALUE.PULSE_6_OFFSET } {
-	# Procedure called to update PULSE_6_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_6_OFFSET { PARAM_VALUE.PULSE_6_OFFSET } {
-	# Procedure called to validate PULSE_6_OFFSET
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_6_PERIOD { PARAM_VALUE.PULSE_6_PERIOD } {
-	# Procedure called to update PULSE_6_PERIOD when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_6_PERIOD { PARAM_VALUE.PULSE_6_PERIOD } {
-	# Procedure called to validate PULSE_6_PERIOD
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_6_WIDTH { PARAM_VALUE.PULSE_6_WIDTH } {
-	# Procedure called to update PULSE_6_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_6_WIDTH { PARAM_VALUE.PULSE_6_WIDTH } {
-	# Procedure called to validate PULSE_6_WIDTH
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_7_OFFSET { PARAM_VALUE.PULSE_7_OFFSET } {
-	# Procedure called to update PULSE_7_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_7_OFFSET { PARAM_VALUE.PULSE_7_OFFSET } {
-	# Procedure called to validate PULSE_7_OFFSET
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_7_PERIOD { PARAM_VALUE.PULSE_7_PERIOD } {
-	# Procedure called to update PULSE_7_PERIOD when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_7_PERIOD { PARAM_VALUE.PULSE_7_PERIOD } {
-	# Procedure called to validate PULSE_7_PERIOD
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_7_WIDTH { PARAM_VALUE.PULSE_7_WIDTH } {
-	# Procedure called to update PULSE_7_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_7_WIDTH { PARAM_VALUE.PULSE_7_WIDTH } {
-	# Procedure called to validate PULSE_7_WIDTH
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_8_OFFSET { PARAM_VALUE.PULSE_8_OFFSET } {
-	# Procedure called to update PULSE_8_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_8_OFFSET { PARAM_VALUE.PULSE_8_OFFSET } {
-	# Procedure called to validate PULSE_8_OFFSET
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_8_PERIOD { PARAM_VALUE.PULSE_8_PERIOD } {
-	# Procedure called to update PULSE_8_PERIOD when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_8_PERIOD { PARAM_VALUE.PULSE_8_PERIOD } {
-	# Procedure called to validate PULSE_8_PERIOD
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_8_WIDTH { PARAM_VALUE.PULSE_8_WIDTH } {
-	# Procedure called to update PULSE_8_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_8_WIDTH { PARAM_VALUE.PULSE_8_WIDTH } {
-	# Procedure called to validate PULSE_8_WIDTH
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_9_OFFSET { PARAM_VALUE.PULSE_9_OFFSET } {
-	# Procedure called to update PULSE_9_OFFSET when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_9_OFFSET { PARAM_VALUE.PULSE_9_OFFSET } {
-	# Procedure called to validate PULSE_9_OFFSET
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_9_PERIOD { PARAM_VALUE.PULSE_9_PERIOD } {
-	# Procedure called to update PULSE_9_PERIOD when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_9_PERIOD { PARAM_VALUE.PULSE_9_PERIOD } {
-	# Procedure called to validate PULSE_9_PERIOD
-	return true
-}
-
-proc update_PARAM_VALUE.PULSE_9_WIDTH { PARAM_VALUE.PULSE_9_WIDTH } {
-	# Procedure called to update PULSE_9_WIDTH when any of the dependent parameters in the arguments change
-}
-
-proc validate_PARAM_VALUE.PULSE_9_WIDTH { PARAM_VALUE.PULSE_9_WIDTH } {
-	# Procedure called to validate PULSE_9_WIDTH
-	return true
-}
-
 proc update_PARAM_VALUE.PWM_EXT_SYNC { PARAM_VALUE.PWM_EXT_SYNC } {
 	# Procedure called to update PWM_EXT_SYNC when any of the dependent parameters in the arguments change
 }
@@ -587,6 +1067,24 @@ proc validate_PARAM_VALUE.PWM_EXT_SYNC { PARAM_VALUE.PWM_EXT_SYNC } {
 	return true
 }
 
+proc update_PARAM_VALUE.SOFTWARE_BRINGUP { PARAM_VALUE.SOFTWARE_BRINGUP } {
+	# Procedure called to update SOFTWARE_BRINGUP when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.SOFTWARE_BRINGUP { PARAM_VALUE.SOFTWARE_BRINGUP } {
+	# Procedure called to validate SOFTWARE_BRINGUP
+	return true
+}
+
+proc update_PARAM_VALUE.START_AT_SYNC { PARAM_VALUE.START_AT_SYNC } {
+	# Procedure called to update START_AT_SYNC when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.START_AT_SYNC { PARAM_VALUE.START_AT_SYNC } {
+	# Procedure called to validate START_AT_SYNC
+	return true
+}
+
 
 proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
 	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
@@ -613,6 +1111,26 @@ proc update_MODELPARAM_VALUE.EXT_ASYNC_SYNC { MODELPARAM_VALUE.EXT_ASYNC_SYNC PA
 	set_property value [get_property value ${PARAM_VALUE.EXT_ASYNC_SYNC}] ${MODELPARAM_VALUE.EXT_ASYNC_SYNC}
 }
 
+proc update_MODELPARAM_VALUE.SOFTWARE_BRINGUP { MODELPARAM_VALUE.SOFTWARE_BRINGUP PARAM_VALUE.SOFTWARE_BRINGUP } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.SOFTWARE_BRINGUP}] ${MODELPARAM_VALUE.SOFTWARE_BRINGUP}
+}
+
+proc update_MODELPARAM_VALUE.EXT_SYNC_PHASE_ALIGN { MODELPARAM_VALUE.EXT_SYNC_PHASE_ALIGN PARAM_VALUE.EXT_SYNC_PHASE_ALIGN } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.EXT_SYNC_PHASE_ALIGN}] ${MODELPARAM_VALUE.EXT_SYNC_PHASE_ALIGN}
+}
+
+proc update_MODELPARAM_VALUE.FORCE_ALIGN { MODELPARAM_VALUE.FORCE_ALIGN PARAM_VALUE.FORCE_ALIGN } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.FORCE_ALIGN}] ${MODELPARAM_VALUE.FORCE_ALIGN}
+}
+
+proc update_MODELPARAM_VALUE.START_AT_SYNC { MODELPARAM_VALUE.START_AT_SYNC PARAM_VALUE.START_AT_SYNC } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.START_AT_SYNC}] ${MODELPARAM_VALUE.START_AT_SYNC}
+}
+
 proc update_MODELPARAM_VALUE.PULSE_0_WIDTH { MODELPARAM_VALUE.PULSE_0_WIDTH PARAM_VALUE.PULSE_0_WIDTH } {
 	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
 	set_property value [get_property value ${PARAM_VALUE.PULSE_0_WIDTH}] ${MODELPARAM_VALUE.PULSE_0_WIDTH}
diff --git a/adi_library/axi_rd_wr_combiner/axi_rd_wr_combiner.v b/adi_library/axi_rd_wr_combiner/axi_rd_wr_combiner.v
index e541891a..7f7755ca 100644
--- a/adi_library/axi_rd_wr_combiner/axi_rd_wr_combiner.v
+++ b/adi_library/axi_rd_wr_combiner/axi_rd_wr_combiner.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_rd_wr_combiner/axi_rd_wr_combiner.xpr b/adi_library/axi_rd_wr_combiner/axi_rd_wr_combiner.xpr
index 2097a8ba..8b90af4b 100644
--- a/adi_library/axi_rd_wr_combiner/axi_rd_wr_combiner.xpr
+++ b/adi_library/axi_rd_wr_combiner/axi_rd_wr_combiner.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_rd_wr_combiner/axi_rd_wr_combiner.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_rd_wr_combiner/axi_rd_wr_combiner.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="a29f4734b0aa4dc995396e0e32d12608"/>
+    <Option Name="Id" Val="8cd4ab3dd6c94d0389c9ed6d76a0ab58"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -154,21 +153,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -181,7 +180,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_rd_wr_combiner/component.xml b/adi_library/axi_rd_wr_combiner/component.xml
index f7184dce..f05f01db 100644
--- a/adi_library/axi_rd_wr_combiner/component.xml
+++ b/adi_library/axi_rd_wr_combiner/component.xml
@@ -593,7 +593,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>e6333660</spirit:value>
+            <spirit:value>48eca2d4</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -609,7 +609,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>e6333660</spirit:value>
+            <spirit:value>48eca2d4</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1621,7 +1621,7 @@
       <spirit:file>
         <spirit:name>axi_rd_wr_combiner.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_e6333660</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_48eca2d4</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1686,12 +1686,12 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:48:48Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:05:31Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
       <xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="5ce56fea"/>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="c3b1219c"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="5e2c0dc8"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="577bb2da"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="6c9e051b"/>
     </xilinx:packagingInfo>
diff --git a/adi_library/axi_spdif_rx/axi_spdif_rx.vhd b/adi_library/axi_spdif_rx/axi_spdif_rx.vhd
index 88179897..2b17abbc 100644
--- a/adi_library/axi_spdif_rx/axi_spdif_rx.vhd
+++ b/adi_library/axi_spdif_rx/axi_spdif_rx.vhd
@@ -26,7 +26,7 @@
 --
 --   2. An ADI specific BSD license, which can be found in the top level directory
 --      of this repository (LICENSE_ADIBSD), and also on-line at:
---      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+--      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 --      This will allow to generate bit files and not release the source code,
 --      as long as it attaches to an ADI device.
 --
diff --git a/adi_library/axi_spdif_rx/axi_spdif_rx.xpr b/adi_library/axi_spdif_rx/axi_spdif_rx.xpr
index 1844a6ca..31720a0e 100644
--- a/adi_library/axi_spdif_rx/axi_spdif_rx.xpr
+++ b/adi_library/axi_spdif_rx/axi_spdif_rx.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_spdif_rx/axi_spdif_rx.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_spdif_rx/axi_spdif_rx.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="4d099198a86c4d1ca1fc08751a061d1f"/>
+    <Option Name="Id" Val="f214319104cb413d9d79e4630c826101"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -201,21 +200,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -228,7 +227,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_spdif_rx/component.xml b/adi_library/axi_spdif_rx/component.xml
index d1c1c173..8a0a6f1d 100644
--- a/adi_library/axi_spdif_rx/component.xml
+++ b/adi_library/axi_spdif_rx/component.xml
@@ -498,7 +498,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>2df62c64</spirit:value>
+            <spirit:value>01729a6b</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -514,7 +514,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>2df62c64</spirit:value>
+            <spirit:value>01729a6b</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1334,7 +1334,7 @@
       <spirit:file>
         <spirit:name>axi_spdif_rx.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_9b31708f</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_e8574184</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1446,11 +1446,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:49:00Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:05:45Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="a5abba93"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="23848aca"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="1bf782e1"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="48c4d1b8"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="f0039951"/>
diff --git a/adi_library/axi_spdif_tx/axi_spdif_tx.vhd b/adi_library/axi_spdif_tx/axi_spdif_tx.vhd
index 6940c543..be89766f 100644
--- a/adi_library/axi_spdif_tx/axi_spdif_tx.vhd
+++ b/adi_library/axi_spdif_tx/axi_spdif_tx.vhd
@@ -26,7 +26,7 @@
 --
 --   2. An ADI specific BSD license, which can be found in the top level directory
 --      of this repository (LICENSE_ADIBSD), and also on-line at:
---      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+--      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 --      This will allow to generate bit files and not release the source code,
 --      as long as it attaches to an ADI device.
 --
diff --git a/adi_library/axi_spdif_tx/axi_spdif_tx.xpr b/adi_library/axi_spdif_tx/axi_spdif_tx.xpr
index aea857bb..02fda211 100644
--- a/adi_library/axi_spdif_tx/axi_spdif_tx.xpr
+++ b/adi_library/axi_spdif_tx/axi_spdif_tx.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_spdif_tx/axi_spdif_tx.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_spdif_tx/axi_spdif_tx.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="60db57f3ebdd4958a335b1908c08b8ae"/>
+    <Option Name="Id" Val="6cebc32614c44fefacfda3309ce96700"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -195,21 +194,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -222,7 +221,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_spdif_tx/component.xml b/adi_library/axi_spdif_tx/component.xml
index 9040d9e4..a01f9704 100644
--- a/adi_library/axi_spdif_tx/component.xml
+++ b/adi_library/axi_spdif_tx/component.xml
@@ -532,7 +532,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>f58934d4</spirit:value>
+            <spirit:value>6e6d7027</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -548,7 +548,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>673f3e79</spirit:value>
+            <spirit:value>45c5ed54</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1355,7 +1355,7 @@
       <spirit:file>
         <spirit:name>axi_spdif_tx.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_34e69c4c</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_93329ce2</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1464,11 +1464,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:49:11Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:05:57Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="5480febd"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="28c0fdf5"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="39025c9c"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="59d83317"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="99b3d217"/>
diff --git a/adi_library/axi_sysid/axi_sysid.v b/adi_library/axi_sysid/axi_sysid.v
index dbb52283..84b2d730 100755
--- a/adi_library/axi_sysid/axi_sysid.v
+++ b/adi_library/axi_sysid/axi_sysid.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_sysid/axi_sysid.xpr b/adi_library/axi_sysid/axi_sysid.xpr
index efdcee84..620cc04a 100644
--- a/adi_library/axi_sysid/axi_sysid.xpr
+++ b/adi_library/axi_sysid/axi_sysid.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_sysid/axi_sysid.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_sysid/axi_sysid.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="1a658c843a50464f8485481736ce0131"/>
+    <Option Name="Id" Val="2cd89f5ef6a444e181cf4a36ed07ddd2"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -161,21 +160,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -188,7 +187,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_sysid/component.xml b/adi_library/axi_sysid/component.xml
index 29996413..0ffc47ca 100644
--- a/adi_library/axi_sysid/component.xml
+++ b/adi_library/axi_sysid/component.xml
@@ -241,7 +241,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>9f64853d</spirit:value>
+            <spirit:value>672d5059</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -257,7 +257,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>9f64853d</spirit:value>
+            <spirit:value>672d5059</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -707,7 +707,7 @@
       <spirit:file>
         <spirit:name>axi_sysid.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_623df4b4</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_40eb28a8</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -786,11 +786,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_sysid</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:49:19Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:06:05Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="2fcf2326"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="118067ad"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="6ac5b408"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="e09a0d11"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="21d42340"/>
diff --git a/adi_library/axi_tdd/axi_tdd.sv b/adi_library/axi_tdd/axi_tdd.sv
index 532f1e3f..b457036c 100644
--- a/adi_library/axi_tdd/axi_tdd.sv
+++ b/adi_library/axi_tdd/axi_tdd.sv
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_tdd/axi_tdd.xpr b/adi_library/axi_tdd/axi_tdd.xpr
index bf072537..f3a2f893 100644
--- a/adi_library/axi_tdd/axi_tdd.xpr
+++ b/adi_library/axi_tdd/axi_tdd.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/axi_tdd/axi_tdd.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/axi_tdd/axi_tdd.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="49c57fb784c94eeb9b9555063479e25d"/>
+    <Option Name="Id" Val="224fb8d4a90c47a086ecb69f46a25788"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -224,21 +223,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -251,7 +250,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/axi_tdd/axi_tdd_channel.sv b/adi_library/axi_tdd/axi_tdd_channel.sv
index 668dd672..04914127 100644
--- a/adi_library/axi_tdd/axi_tdd_channel.sv
+++ b/adi_library/axi_tdd/axi_tdd_channel.sv
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_tdd/axi_tdd_counter.sv b/adi_library/axi_tdd/axi_tdd_counter.sv
index 0ba133e8..4ed26d77 100644
--- a/adi_library/axi_tdd/axi_tdd_counter.sv
+++ b/adi_library/axi_tdd/axi_tdd_counter.sv
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_tdd/axi_tdd_pkg.sv b/adi_library/axi_tdd/axi_tdd_pkg.sv
index 5546f74a..1517660f 100644
--- a/adi_library/axi_tdd/axi_tdd_pkg.sv
+++ b/adi_library/axi_tdd/axi_tdd_pkg.sv
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_tdd/axi_tdd_regmap.sv b/adi_library/axi_tdd/axi_tdd_regmap.sv
index 4dd36c95..ffaf710f 100644
--- a/adi_library/axi_tdd/axi_tdd_regmap.sv
+++ b/adi_library/axi_tdd/axi_tdd_regmap.sv
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_tdd/axi_tdd_sync_gen.sv b/adi_library/axi_tdd/axi_tdd_sync_gen.sv
index 02f955a8..5b729f9a 100644
--- a/adi_library/axi_tdd/axi_tdd_sync_gen.sv
+++ b/adi_library/axi_tdd/axi_tdd_sync_gen.sv
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/axi_tdd/component.xml b/adi_library/axi_tdd/component.xml
index 9a37683f..42bbb798 100644
--- a/adi_library/axi_tdd/component.xml
+++ b/adi_library/axi_tdd/component.xml
@@ -285,7 +285,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>11c1d0ef</spirit:value>
+            <spirit:value>c6cc528e</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -301,7 +301,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>11c1d0ef</spirit:value>
+            <spirit:value>c6cc528e</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -834,7 +834,7 @@
       <spirit:file>
         <spirit:name>axi_tdd.sv</spirit:name>
         <spirit:fileType>systemVerilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_f31068f0</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_d31ab988</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -980,11 +980,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_tdd</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:49:32Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:06:20Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="e650ae53"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="b2780fb2"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="4486eeef"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="469eb6c3"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="7e7c1c9e"/>
diff --git a/adi_library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v b/adi_library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v
index d96dc3e2..6a70b44d 100644
--- a/adi_library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v
+++ b/adi_library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.xpr b/adi_library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.xpr
index 83bbb68f..7c77efcf 100644
--- a/adi_library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.xpr
+++ b/adi_library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="c221b1d45b724733a9700019fb3b5fee"/>
+    <Option Name="Id" Val="d4cdc0ccbab142a4a6f4e426d648d759"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -154,21 +153,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -181,7 +180,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/cn0363/cn0363_dma_sequencer/component.xml b/adi_library/cn0363/cn0363_dma_sequencer/component.xml
index b28f2c4b..af19ebbd 100644
--- a/adi_library/cn0363/cn0363_dma_sequencer/component.xml
+++ b/adi_library/cn0363/cn0363_dma_sequencer/component.xml
@@ -278,7 +278,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>9089184b</spirit:value>
+            <spirit:value>a7ce4244</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -294,7 +294,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>9089184b</spirit:value>
+            <spirit:value>a7ce4244</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -678,7 +678,7 @@
       <spirit:file>
         <spirit:name>cn0363_dma_sequencer.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_9089184b</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_a7ce4244</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -743,11 +743,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:49:39Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:06:28Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="a98b848c"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="cca749d9"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="ba50a99e"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="82d8966a"/>
     </xilinx:packagingInfo>
diff --git a/adi_library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v b/adi_library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v
index ab597253..bfe9a9ce 100644
--- a/adi_library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v
+++ b/adi_library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.xpr b/adi_library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.xpr
index 03c8c67a..6383bb74 100644
--- a/adi_library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.xpr
+++ b/adi_library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="167808701e2c4d589d89580c4e170313"/>
+    <Option Name="Id" Val="f10ae141bdb745f3a89c86a56d44d34d"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -154,21 +153,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -181,7 +180,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/cn0363/cn0363_phase_data_sync/component.xml b/adi_library/cn0363/cn0363_phase_data_sync/component.xml
index d584ab91..dbfa7797 100644
--- a/adi_library/cn0363/cn0363_phase_data_sync/component.xml
+++ b/adi_library/cn0363/cn0363_phase_data_sync/component.xml
@@ -166,7 +166,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>65377e13</spirit:value>
+            <spirit:value>c791119f</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -182,7 +182,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>65377e13</spirit:value>
+            <spirit:value>c791119f</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -437,7 +437,7 @@
       <spirit:file>
         <spirit:name>cn0363_phase_data_sync.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_65377e13</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_c791119f</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -502,11 +502,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:49:46Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:06:36Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="aabf520c"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="c173931d"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="e76fdfc6"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="a5b05dc1"/>
     </xilinx:packagingInfo>
diff --git a/adi_library/common/ad_3w_spi.v b/adi_library/common/ad_3w_spi.v
index bd7cb4b4..19dad158 100644
--- a/adi_library/common/ad_3w_spi.v
+++ b/adi_library/common/ad_3w_spi.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_addsub.v b/adi_library/common/ad_addsub.v
index 8b515973..27d8ade1 100644
--- a/adi_library/common/ad_addsub.v
+++ b/adi_library/common/ad_addsub.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_adl5904_rst.v b/adi_library/common/ad_adl5904_rst.v
index 1b305f85..57fed424 100644
--- a/adi_library/common/ad_adl5904_rst.v
+++ b/adi_library/common/ad_adl5904_rst.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_axis_inf_rx.v b/adi_library/common/ad_axis_inf_rx.v
index 8da4105a..9f90ccdb 100644
--- a/adi_library/common/ad_axis_inf_rx.v
+++ b/adi_library/common/ad_axis_inf_rx.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_b2g.v b/adi_library/common/ad_b2g.v
index 5fcadfe4..8a3e0c0d 100644
--- a/adi_library/common/ad_b2g.v
+++ b/adi_library/common/ad_b2g.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_bus_mux.v b/adi_library/common/ad_bus_mux.v
index 95336bb7..55969161 100644
--- a/adi_library/common/ad_bus_mux.v
+++ b/adi_library/common/ad_bus_mux.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_csc.v b/adi_library/common/ad_csc.v
index a9aac8b3..adf0e66b 100644
--- a/adi_library/common/ad_csc.v
+++ b/adi_library/common/ad_csc.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_csc_CrYCb2RGB.v b/adi_library/common/ad_csc_CrYCb2RGB.v
index 184966e9..c55f8d30 100644
--- a/adi_library/common/ad_csc_CrYCb2RGB.v
+++ b/adi_library/common/ad_csc_CrYCb2RGB.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_csc_RGB2CrYCb.v b/adi_library/common/ad_csc_RGB2CrYCb.v
index 387bef45..82068cbd 100644
--- a/adi_library/common/ad_csc_RGB2CrYCb.v
+++ b/adi_library/common/ad_csc_RGB2CrYCb.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_datafmt.v b/adi_library/common/ad_datafmt.v
index 0859e265..f7290537 100644
--- a/adi_library/common/ad_datafmt.v
+++ b/adi_library/common/ad_datafmt.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_dds.v b/adi_library/common/ad_dds.v
index 2aa40814..5a44ed27 100644
--- a/adi_library/common/ad_dds.v
+++ b/adi_library/common/ad_dds.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_dds_1.v b/adi_library/common/ad_dds_1.v
index 59b299f4..41080539 100644
--- a/adi_library/common/ad_dds_1.v
+++ b/adi_library/common/ad_dds_1.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_dds_2.v b/adi_library/common/ad_dds_2.v
index db7801d6..7012093b 100644
--- a/adi_library/common/ad_dds_2.v
+++ b/adi_library/common/ad_dds_2.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_dds_cordic_pipe.v b/adi_library/common/ad_dds_cordic_pipe.v
index 2bff8a22..81df779c 100644
--- a/adi_library/common/ad_dds_cordic_pipe.v
+++ b/adi_library/common/ad_dds_cordic_pipe.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_dds_sine.v b/adi_library/common/ad_dds_sine.v
index 68696305..032f8d42 100644
--- a/adi_library/common/ad_dds_sine.v
+++ b/adi_library/common/ad_dds_sine.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_dds_sine_cordic.v b/adi_library/common/ad_dds_sine_cordic.v
index 33f1e10f..72e20fdd 100644
--- a/adi_library/common/ad_dds_sine_cordic.v
+++ b/adi_library/common/ad_dds_sine_cordic.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_edge_detect.v b/adi_library/common/ad_edge_detect.v
index f1cac88b..c2561b88 100644
--- a/adi_library/common/ad_edge_detect.v
+++ b/adi_library/common/ad_edge_detect.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_g2b.v b/adi_library/common/ad_g2b.v
index 373b8728..27e83d51 100644
--- a/adi_library/common/ad_g2b.v
+++ b/adi_library/common/ad_g2b.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_iobuf.v b/adi_library/common/ad_iobuf.v
index c097a3fe..718a7c59 100644
--- a/adi_library/common/ad_iobuf.v
+++ b/adi_library/common/ad_iobuf.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_iqcor.v b/adi_library/common/ad_iqcor.v
index 02d2ca45..658a9077 100644
--- a/adi_library/common/ad_iqcor.v
+++ b/adi_library/common/ad_iqcor.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_mem.v b/adi_library/common/ad_mem.v
index 2cf05d58..d4aa8d41 100644
--- a/adi_library/common/ad_mem.v
+++ b/adi_library/common/ad_mem.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_mem_asym.v b/adi_library/common/ad_mem_asym.v
index f18091ff..81c2c737 100644
--- a/adi_library/common/ad_mem_asym.v
+++ b/adi_library/common/ad_mem_asym.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_mem_dual.v b/adi_library/common/ad_mem_dual.v
new file mode 100644
index 00000000..c8722fdf
--- /dev/null
+++ b/adi_library/common/ad_mem_dual.v
@@ -0,0 +1,88 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module ad_mem_dual #(
+  parameter INITIALIZE = 0,
+  parameter DATA_WIDTH = 16,
+  parameter ADDRESS_WIDTH = 5
+) (
+  input                            clka,
+  input                            wea,
+  input                            ea,
+  input      [(ADDRESS_WIDTH-1):0] addra,
+  input      [(DATA_WIDTH-1):0]    dina,
+  output reg [(DATA_WIDTH-1):0]    douta,
+
+  input                            clkb,
+  input                            web,
+  input                            eb,
+  input      [(ADDRESS_WIDTH-1):0] addrb,
+  input      [(DATA_WIDTH-1):0]    dinb,
+  output reg [(DATA_WIDTH-1):0]    doutb
+);
+
+  (* ram_style = "block" *)
+  reg [(DATA_WIDTH-1):0] m_ram[0:((2**ADDRESS_WIDTH)-1)];
+
+  genvar i;
+  generate
+    if (INITIALIZE) begin
+      for (i = 0; i < (2**ADDRESS_WIDTH); i = i + 1) begin: gen_m_ram
+        initial m_ram[i] = 'b0;
+      end
+    end
+  endgenerate
+
+  always @(posedge clka) begin
+    if (ea == 1'b1) begin
+      if (wea == 1'b1) begin
+        m_ram[addra] <= dina;
+      end
+      douta <= m_ram[addra];
+    end
+  end
+
+  always @(posedge clkb) begin
+    if (eb == 1'b1) begin
+      if (web == 1'b1) begin
+        m_ram[addrb] <= dinb;
+      end
+      doutb <= m_ram[addrb];
+    end
+  end
+
+endmodule
diff --git a/adi_library/common/ad_mux.v b/adi_library/common/ad_mux.v
index ffcdd7ad..c5428589 100644
--- a/adi_library/common/ad_mux.v
+++ b/adi_library/common/ad_mux.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_mux_core.v b/adi_library/common/ad_mux_core.v
index d718aa72..af0c97fd 100644
--- a/adi_library/common/ad_mux_core.v
+++ b/adi_library/common/ad_mux_core.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_pack.v b/adi_library/common/ad_pack.v
index 8a7ddbb1..930f1b70 100644
--- a/adi_library/common/ad_pack.v
+++ b/adi_library/common/ad_pack.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_pngen.v b/adi_library/common/ad_pngen.v
index f7280b3d..fcb28495 100644
--- a/adi_library/common/ad_pngen.v
+++ b/adi_library/common/ad_pngen.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_pnmon.v b/adi_library/common/ad_pnmon.v
index 7a223c50..3822dd58 100644
--- a/adi_library/common/ad_pnmon.v
+++ b/adi_library/common/ad_pnmon.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_pps_receiver.v b/adi_library/common/ad_pps_receiver.v
index 095bc31a..d068f31b 100644
--- a/adi_library/common/ad_pps_receiver.v
+++ b/adi_library/common/ad_pps_receiver.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_rst.v b/adi_library/common/ad_rst.v
index 1aa10890..d4d53147 100644
--- a/adi_library/common/ad_rst.v
+++ b/adi_library/common/ad_rst.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_ss_422to444.v b/adi_library/common/ad_ss_422to444.v
index ec2f66b6..ccb9cd97 100644
--- a/adi_library/common/ad_ss_422to444.v
+++ b/adi_library/common/ad_ss_422to444.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_ss_444to422.v b/adi_library/common/ad_ss_444to422.v
index 7aa6b3c7..1888327e 100644
--- a/adi_library/common/ad_ss_444to422.v
+++ b/adi_library/common/ad_ss_444to422.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_sysref_gen.v b/adi_library/common/ad_sysref_gen.v
index 1367f5a9..c62e5fdf 100644
--- a/adi_library/common/ad_sysref_gen.v
+++ b/adi_library/common/ad_sysref_gen.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_tdd_control.v b/adi_library/common/ad_tdd_control.v
index 46d23175..bf74d35c 100644
--- a/adi_library/common/ad_tdd_control.v
+++ b/adi_library/common/ad_tdd_control.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_upack.v b/adi_library/common/ad_upack.v
index ecb62eeb..211791b8 100644
--- a/adi_library/common/ad_upack.v
+++ b/adi_library/common/ad_upack.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/ad_xcvr_rx_if.v b/adi_library/common/ad_xcvr_rx_if.v
index 8bbd3f86..e8405b6b 100644
--- a/adi_library/common/ad_xcvr_rx_if.v
+++ b/adi_library/common/ad_xcvr_rx_if.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/axi_ctrlif.vhd b/adi_library/common/axi_ctrlif.vhd
index ddf25aeb..9817b943 100644
--- a/adi_library/common/axi_ctrlif.vhd
+++ b/adi_library/common/axi_ctrlif.vhd
@@ -26,7 +26,7 @@
 --
 --   2. An ADI specific BSD license, which can be found in the top level directory
 --      of this repository (LICENSE_ADIBSD), and also on-line at:
---      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+--      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 --      This will allow to generate bit files and not release the source code,
 --      as long as it attaches to an ADI device.
 --
diff --git a/adi_library/common/axi_streaming_dma_rx_fifo.vhd b/adi_library/common/axi_streaming_dma_rx_fifo.vhd
index b0e26a89..0dc484c9 100644
--- a/adi_library/common/axi_streaming_dma_rx_fifo.vhd
+++ b/adi_library/common/axi_streaming_dma_rx_fifo.vhd
@@ -26,7 +26,7 @@
 --
 --   2. An ADI specific BSD license, which can be found in the top level directory
 --      of this repository (LICENSE_ADIBSD), and also on-line at:
---      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+--      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 --      This will allow to generate bit files and not release the source code,
 --      as long as it attaches to an ADI device.
 --
diff --git a/adi_library/common/axi_streaming_dma_tx_fifo.vhd b/adi_library/common/axi_streaming_dma_tx_fifo.vhd
index 20671b02..48cf4dd5 100644
--- a/adi_library/common/axi_streaming_dma_tx_fifo.vhd
+++ b/adi_library/common/axi_streaming_dma_tx_fifo.vhd
@@ -26,7 +26,7 @@
 --
 --   2. An ADI specific BSD license, which can be found in the top level directory
 --      of this repository (LICENSE_ADIBSD), and also on-line at:
---      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+--      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 --      This will allow to generate bit files and not release the source code,
 --      as long as it attaches to an ADI device.
 --
diff --git a/adi_library/common/dma_fifo.vhd b/adi_library/common/dma_fifo.vhd
index 7143d9cc..62f55880 100644
--- a/adi_library/common/dma_fifo.vhd
+++ b/adi_library/common/dma_fifo.vhd
@@ -26,7 +26,7 @@
 --
 --   2. An ADI specific BSD license, which can be found in the top level directory
 --      of this repository (LICENSE_ADIBSD), and also on-line at:
---      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+--      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 --      This will allow to generate bit files and not release the source code,
 --      as long as it attaches to an ADI device.
 --
diff --git a/adi_library/common/pl330_dma_fifo.vhd b/adi_library/common/pl330_dma_fifo.vhd
index 5a4f8ea9..2c5365b6 100644
--- a/adi_library/common/pl330_dma_fifo.vhd
+++ b/adi_library/common/pl330_dma_fifo.vhd
@@ -26,7 +26,7 @@
 --
 --   2. An ADI specific BSD license, which can be found in the top level directory
 --      of this repository (LICENSE_ADIBSD), and also on-line at:
---      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+--      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 --      This will allow to generate bit files and not release the source code,
 --      as long as it attaches to an ADI device.
 --
diff --git a/adi_library/common/tb/ad_mux_tb.v b/adi_library/common/tb/ad_mux_tb.v
index 08e13158..fe901937 100644
--- a/adi_library/common/tb/ad_mux_tb.v
+++ b/adi_library/common/tb/ad_mux_tb.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/tb/ad_pack_tb.v b/adi_library/common/tb/ad_pack_tb.v
index 0105cd6b..f089cca7 100644
--- a/adi_library/common/tb/ad_pack_tb.v
+++ b/adi_library/common/tb/ad_pack_tb.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/tb/ad_upack_tb.v b/adi_library/common/tb/ad_upack_tb.v
index 2289af2e..272f0f57 100644
--- a/adi_library/common/tb/ad_upack_tb.v
+++ b/adi_library/common/tb/ad_upack_tb.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/tb/tb_base.v b/adi_library/common/tb/tb_base.v
index 18ff6693..e25123ba 100644
--- a/adi_library/common/tb/tb_base.v
+++ b/adi_library/common/tb/tb_base.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/up_adc_channel.v b/adi_library/common/up_adc_channel.v
index f38c6045..35cc7fd7 100644
--- a/adi_library/common/up_adc_channel.v
+++ b/adi_library/common/up_adc_channel.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/up_adc_common.v b/adi_library/common/up_adc_common.v
index 7479f2b7..5de570db 100644
--- a/adi_library/common/up_adc_common.v
+++ b/adi_library/common/up_adc_common.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/up_axi.v b/adi_library/common/up_axi.v
index 6b071f42..abcbb092 100644
--- a/adi_library/common/up_axi.v
+++ b/adi_library/common/up_axi.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/up_clkgen.v b/adi_library/common/up_clkgen.v
index f3f3bfbb..d6f80d77 100644
--- a/adi_library/common/up_clkgen.v
+++ b/adi_library/common/up_clkgen.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/up_clock_mon.v b/adi_library/common/up_clock_mon.v
index 5c4c2107..6322762f 100644
--- a/adi_library/common/up_clock_mon.v
+++ b/adi_library/common/up_clock_mon.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/up_dac_channel.v b/adi_library/common/up_dac_channel.v
index dc02e673..2baec305 100644
--- a/adi_library/common/up_dac_channel.v
+++ b/adi_library/common/up_dac_channel.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/up_dac_common.v b/adi_library/common/up_dac_common.v
index 8053b9ac..9c86aaee 100644
--- a/adi_library/common/up_dac_common.v
+++ b/adi_library/common/up_dac_common.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/up_delay_cntrl.v b/adi_library/common/up_delay_cntrl.v
index f50be757..96bcdc48 100644
--- a/adi_library/common/up_delay_cntrl.v
+++ b/adi_library/common/up_delay_cntrl.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/up_hdmi_rx.v b/adi_library/common/up_hdmi_rx.v
index 48017956..d16e1227 100644
--- a/adi_library/common/up_hdmi_rx.v
+++ b/adi_library/common/up_hdmi_rx.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/up_hdmi_tx.v b/adi_library/common/up_hdmi_tx.v
index 009330da..4a6c998c 100644
--- a/adi_library/common/up_hdmi_tx.v
+++ b/adi_library/common/up_hdmi_tx.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/up_pmod.v b/adi_library/common/up_pmod.v
index 278200e0..0c706c7b 100644
--- a/adi_library/common/up_pmod.v
+++ b/adi_library/common/up_pmod.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/up_tdd_cntrl.v b/adi_library/common/up_tdd_cntrl.v
index bd05c386..6e1908b1 100644
--- a/adi_library/common/up_tdd_cntrl.v
+++ b/adi_library/common/up_tdd_cntrl.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/up_xfer_cntrl.v b/adi_library/common/up_xfer_cntrl.v
index 3700157c..f5b6bb37 100644
--- a/adi_library/common/up_xfer_cntrl.v
+++ b/adi_library/common/up_xfer_cntrl.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/up_xfer_status.v b/adi_library/common/up_xfer_status.v
index 715082a1..fda44583 100644
--- a/adi_library/common/up_xfer_status.v
+++ b/adi_library/common/up_xfer_status.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/util_axis_upscale.v b/adi_library/common/util_axis_upscale.v
index 499d1f86..ea279239 100644
--- a/adi_library/common/util_axis_upscale.v
+++ b/adi_library/common/util_axis_upscale.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/util_dec256sinc24b.v b/adi_library/common/util_dec256sinc24b.v
index 5754da24..9bdbe374 100644
--- a/adi_library/common/util_dec256sinc24b.v
+++ b/adi_library/common/util_dec256sinc24b.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/util_delay.v b/adi_library/common/util_delay.v
index 874049b6..c349cf83 100644
--- a/adi_library/common/util_delay.v
+++ b/adi_library/common/util_delay.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/util_ext_sync.v b/adi_library/common/util_ext_sync.v
index 8c299bac..e383bda0 100644
--- a/adi_library/common/util_ext_sync.v
+++ b/adi_library/common/util_ext_sync.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/common/util_pulse_gen.v b/adi_library/common/util_pulse_gen.v
index d323cec6..b568827d 100644
--- a/adi_library/common/util_pulse_gen.v
+++ b/adi_library/common/util_pulse_gen.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/cordic_demod/component.xml b/adi_library/cordic_demod/component.xml
index 0f767537..13c2dd05 100644
--- a/adi_library/cordic_demod/component.xml
+++ b/adi_library/cordic_demod/component.xml
@@ -134,7 +134,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>e206c42f</spirit:value>
+            <spirit:value>f299e649</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -150,7 +150,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>e206c42f</spirit:value>
+            <spirit:value>f299e649</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -293,7 +293,7 @@
       <spirit:file>
         <spirit:name>cordic_demod.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_e206c42f</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_f299e649</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -358,11 +358,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:49:54Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:06:44Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="58e3750c"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="347932e8"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="8cefffc0"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="5335b8b4"/>
     </xilinx:packagingInfo>
diff --git a/adi_library/cordic_demod/cordic_demod.v b/adi_library/cordic_demod/cordic_demod.v
index 809cabc8..98c3b53b 100644
--- a/adi_library/cordic_demod/cordic_demod.v
+++ b/adi_library/cordic_demod/cordic_demod.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/cordic_demod/cordic_demod.xpr b/adi_library/cordic_demod/cordic_demod.xpr
index 1556724f..265be6f0 100644
--- a/adi_library/cordic_demod/cordic_demod.xpr
+++ b/adi_library/cordic_demod/cordic_demod.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/cordic_demod/cordic_demod.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/cordic_demod/cordic_demod.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="b934ff2379424419b7a481005d549a50"/>
+    <Option Name="Id" Val="bcc51057b6374508b76121b4b9cd398f"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -154,21 +153,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -181,7 +180,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/data_offload/README.md b/adi_library/data_offload/README.md
deleted file mode 100644
index 1e7e77d4..00000000
--- a/adi_library/data_offload/README.md
+++ /dev/null
@@ -1,392 +0,0 @@
-
-# Data offload IP core
-
-## Description, general use cases
-
-Data offload module for high-speed converters:
-
-**NOTE**: This IP will always have a storage unit (internal or external to the FPGA) and is
-designed to handle high data rates. If your data paths will run in a lower data
-rate, and your intention is just to transfer the data to another clock domain or
-to adjust the bus width of the data path, you may want to check out the util_axis_fifo or
-util_axis_fifo_asym IPs.
-
-The initialization and data transfer looks as follows:
-
-  * in case of DAC, the DMA initialize the storage unit, after that the controller
-will push the data to the DAC interface in one-shot or cyclic way
-
-  * in case of ADC, the DMA request a transfer, the controller will save the data into
-the storage unit, after that will push it to the DMA
-
-  * BYPASS mode: simple streaming FIFO in case of clock rate or data width differences
-between source and sink interfaces (data rate MUST match in order to work); the BYPASS
-mode is used when an initially high rate path is downgraded to lower rates.
-
-## Table of content
-
-  * [Block diagrams](README.md#block-diagram)
-  * [Parameters](README.md#parameters)
-  * [Interfaces](README.md#interfaces)
-  * [Register map](README.md#register-map)
-  * [Clock tree](README.md#clock-tree)
-  * [Data path](README.md#data-path)
-  * [Control path](README.md#control-path-offload-fsm)
-
-## Generic arhitecture
-
-The main role of our data paths, is to stream data from point A to point B 
-in a particular system. There are always a SOURCE and a DESTINATION
-point, which can be a device (ADC or DAC), a DMA (for system memory) or any other
-data processing IP.
-
-In the context of Data Offload IP, we don't need to know who is the source and
-who is the destination. Both interface is a AXI4 Stream interface, which can be 
-supported in both Xilinx's an Intel's architecture, and can be connected to any device
-core or DMA.
-
-The storage unit is connected to the Data Offload controller via two FIFO interface.
-This way the same controller can be used for various storage solutions. (BRAM, 
-URAM, external memory etc.)
-
-## Block diagram
-
-![Generic Block Diagram](./docs/generic_bd.svg)
-
-## Parameters
-
-|      NAME            |   TYPE      |  DEFAULT   |            DESCRIPTION      |
-|----------------------|:-----------:|:----------:|:---------------------------:|
-|ID                    |  integer    |    0       | Instance ID number | 
-|MEM_TYPE              |  [ 0:0]     |    0       | Define the used storage type: FPGA RAM - 0; external DDR - 1 |
-|MEM_SIZE_LOG2         |  integer    |   10       | Log2 value of storage size, defines the width of transfer length control signals. |
-|TX_OR_RXN_PATH        |  [ 0:0]     |    1       | If set TX path enabled, otherwise RX |
-|SRC_DATA_WIDTH        |  integer    |    64      | The data width of the source interface |
-|DST_DATA_WIDTH        |  integer    |   124      | The data width of the destination interface |
-|DST_CYCLIC_EN         |  [ 0:0]     |     0      | Enables CYCLIC mode for destinations like DAC | 
-|AUTO_BRINGUP          |  [ 0:0]     |     1      | If enabled the IP runs automatically after bootup | 
-|SYNC_EXT_ADD_INTERNAL_CDC |  [ 0:0] |     1      | If enabled the external sync pin is synchronized to the internal clock domain with a CDC. | 
-|HAS_BYPASS            |  [ 0:0]     |     1      | If set to zero the bypass FIFO is not implemented. | 
-
-## Interfaces
-
-### AXI4 Lite Memory Mapped Slave (S_AXI4_LITE)
-
-This interface is used to access the register map.
-
-```verilog
-// interface clock -- system clock -- 100 MHz
-input                   s_axi_aclk
-// interface resetn -- synchronous reset active low
-input                   s_axi_aresetn
-
-/* write address channel */
-
-// validates the address on the bus
-input                   s_axi_awvalid
-// write address
-input       [15:0]      s_axi_awaddr
-// protection type -- not used in the core
-input       [ 2:0]      s_axi_awprot
-// write ready, indicates that the slave can accept the address
-output                  s_axi_awready
-
-/* write data channel */
-
-// validate the data on the bus
-input                   s_axi_wvalid
-// write data
-input       [31:0]      s_axi_wdata
-// write strobe, indicates which byte lanes to update
-input       [ 3:0]      s_axi_wstrb
-// write ready, indicates that the slave can accept the data
-output                  s_axi_wready
-
-/* write response channel */
-
-// validates the write response of the slave
-output                  s_axi_bvalid
-// write response, indicate the status of the transfer
-output      [ 1:0]      s_axi_bresp
-// response ready, indicates that the master can accept the data
-input                   s_axi_bready
-
-/* read address channel */
-
-// validates the address on the bus
-input                   s_axi_arvalid
-// read address
-input       [15:0]      s_axi_araddr
-// protection type -- not used in the core
-input       [ 2:0]      s_axi_arprot
-// read ready, indicates that the slave can accept the address
-output                  s_axi_arready
-
-/* read data channel */
-
-// validate the data on the bus
-output                  s_axi_rvalid
-// read response, indicate the status of the transfer
-output      [ 1:0]      s_axi_rresp
-// read data drivers by the slave
-output      [31:0]      s_axi_rdata
-// read ready, indicates that the master can accept the data
-input                   s_axi_rready
-```
-
-### Supported data interfaces
-
-**NOTE**: To simplify the design both the source and destination data interface is
-an AXI4 streaming interface. A FIFO write (ADC) interface can be treated as AXI4
-stream where only the master controls the data rate (s_axis_ready is always asserted), 
-and a FIFO read (DAC) interface can be treated as an AXI4 stream where only the slave
-controls the data rate. (m_axis_valid is always asserted).
-
-#### AXI4 Stream interface (S_AXIS | M_AXIS)
-
-* The AXI Stream Slave (S_AXIS) interface is used to receive AXI stream from
-the transmit DMA or ADC device.
-
-* The AXI Stream Master (M_AXIS) interface is used to transmit AXI stream
-to receive DMA or DAC device
-
-```verilog
-// NOTE: this reference is a master interface
-
-// interface clock -- can be device/core clock or DMA clock
-input                        m_axis_aclk
-// interface resetn -- synchronous reset with the system clock
-input                        m_axis_resetn
-// indicates that the slave can accept a transfer in the current cycle (in case of an ADC core, this will control the stream)
-input                        m_axis_ready
-// indicates that the master is driving a valid transfer
-output                       m_axis_valid
-// primary payload
-output [DATA_WIDTH-1:0]      m_axis_data
-// indicates the boundary of a packet
-output                       m_axis_last
-// byte qualifier, we need this so we can have different DMA and device data widths
-output [(DATA_WIDTH/8)-1:0]  m_axis_tkeep
-```
-
-**NOTE**: A packet will always be a full buffer. All the data beats going to be
-full beats (all the bytes of the bus are valid), except the last one. **axis_last**
-and **axis_tkeep** will be used to indicate a partial last beat. This information
-should be transferred from the source domain to the sink domain, so we can read
-back the data from memory correctly.
-
-#### AXIS source and destination interface to the storage unit
-
-This is blocking (back-pressure) interface for the storage unit,
-with similar behavior of main AXIS data interfaces.
-
-###  Initialization request interface
-
-Define a simple request interface to initialize the memory:
-
-  * The request will comes from the system and will put the data offload FSM
-into a standby/ready state.
-
-
-#### Synchronization modes
-
-  * **AUTOMATIC**
-    * ADC: The IP will start to fill up the buffer with samples as soon as possible.
-    * DAC: As the DMA will send a valid last, the FSM will start to send the
-stored data to the device.
-
-  * **HARDWARE**
-    * ADC and DAC: An external signal will trigger the write or read into or from
-the memory.
-    * **NOTE**: In case of DAC, if the DMA does not sent all the data into the
-buffer, before a hardware sync event, the unsent data will be ignored. It's the
-user/software responsibility to sync up these events accordingly.
-
-  * **SOFTWARE**
-    * The software write a RW1C register which will trigger the reads or writes
-into or from the memory.
-
-## Register Map
-
-|  WORD  |  BYTE    |   BITS   |    NAME               | TYPE  | CLOCK DOMAIN |       DESCRIPTION       |
-|-------:|:--------:|:--------:|:---------------------:|:-----:|:------------:|:-----------------------:|
-| 0x0000 |  0x0000  |          | `VERSION`             |  RO   |  SYS         |  Version number         |
-|        |          | [31:16]  | `MAJOR`               |       |              |                         |
-|        |          | [15: 8]  | `MINOR`               |       |              |                         |
-|        |          | [ 7: 0]  | `PATCH`               |       |              |                         |
-| 0x0001 |  0x0004  |          | `PERIPHERAL_ID`       |  RO   |  SYS         |  Value of the IP configuration parameter |
-| 0x0002 |  0x0008  |          | `SCRATCH`             |  RW   |  SYS         |  Scratch register       |
-| 0x0003 |  0x000C  |          | `IDENTIFICATION`      |  RO   |  SYS         |  Peripheral identification. Default value: 0x44414F46 - ('D','A','O','F') |
-| 0x0004 |  0x0010  |          | `SYNTHESIS_CONFIG`    |  RO   |  SYS         |  Core configuration registers |
-|        |          | [13: 8]  | `MEM_SIZE_LOG2`       |       |              |  Log2 of memory size in bytes |
-|        |          | [ 2: 2]  | `HAS_BYPASS`          |       |              |  If not set the bypass logic is not implemented. |
-|        |          | [ 1: 1]  | `TX_OR_RXN_PATH`      |       |              |  RX Path => 0, TX => 1  |
-|        |          | [ 0: 0]  | `MEMORY_TYPE`         |       |              |  The used storage type (embedded => 0 or external => 1) |
-| 0x0007 |  0x001C  |          | `TRANSFER_LENGTH`     |  RW   |  SRC         |  Transfer length        |
-| 0x0020 |  0x0080  |          | `MEM_PHY_STATE`       |  RO   |  DDR         |  Status bits of the memory controller IP |
-|        |          | [ 5: 5]  | `UNDERFLOW`           |  RW1C |              |  Indicates that storage could not handle data rate during play. Available when core is in TX mode.|
-|        |          | [ 4: 4]  | `OVERFLOW`            |  RW1C |              |  Indicates that storage could not handle data rate during capture. Available when core is in RX mode. |
-|        |          | [ 0: 0]  | `CALIB_COMPLETE`      |       |              |  Indicates that the memory initialization and calibration have completed successfully |
-| 0x0021 |  0x0084  |          | `RESETN_OFFLOAD`      |  RW   |  DST/SRC     |  Reset all the internal address registers and state machines |
-|        |          | [ 0: 0]  | `RESETN`              |       |              |                         |
-| 0x0022 |  0x0088  |          | `CONTROL`             |  RW   |  DST         |  A global control register |
-|        |          | [ 1: 1]  | `ONESHOT_EN`          |       |              |  By default the TX path runs on CYCLIC mode, set this bit to switch it to ONE-SHOT mode |
-|        |          | [ 0: 0]  | `OFFLOAD_BYPASS`      |       |              |  Bypass the offload storage, the data path consist just of a CDC FIFO |
-| 0x0040 |  0x0100  |          | `SYNC_TRIGGER`        |  RW1C |  SRC         |  Synchronization setup for RX and TX path |
-|        |          | [ 0: 0]  | `SYNC_TRIGGER`        |       |              |  Trigger the data capture |
-| 0x0041 |  0x0104  |          | `SYNC_CONFIG`         |  RW   |  SRC         |  Synchronization setup |
-|        |          | [ 1: 0]  | `SYNC_CONFIG`         |       |              |  Auto - '0'; hardware - '1'; software - '2' |
-| 0x0080 |  0x0200  |          | `FSM_DBG`             |  RO   |              |  Debug register for the offload FSM |
-|        |          | [11: 8]  | `FSM_STATE_READ`      |       |  SRC         |  The current state of the read-offload state machine |
-|        |          | [ 4: 0]  | `FSM_STATE_WRITE`     |       |  DST         |  The current state of the write-offload state machine |
-
-## Clock tree
-
-In general there are at least two different clock in the data offload module:
-
-  * DMA or system clock : on this clock will run all the front end interfaces
-  * Memory Controller user clock : user interface clock of the DDRx controller (**optional**)
-  * Device clock : the digital interface clock of the converter
-
-![Clocks](./docs/clocks.svg)
-
-A general frequency relationship of the above clocks are:
-
-```
-  CLKdma <= CLKddr <= CLKconverter
-```
-
-The clock domain crossing should be handled by the [util_axis_fifo](https://github.com/analogdevicesinc/hdl/tree/master/library/util_axis_fifo) module.
-  * **TODO** : Make sure that we support both AXIS and FIFO
-  * **TODO** : Add support for asymmetric aspect ratio.
-
-All the back end paths (device side) are time critical. The module must read or
-write from or into the storage at the speed of the device.
-
-```
-  DDR data rate >= Device data rate
-  DDR data rate >= ADC data rate + DAC data rate
-```
-
-## Data path
-
-![Data path](./docs/datapath.svg)
-
-  * The data path should be designed to support any kind of difference between
-the source, memory and sink data width.
-
-  * The data width adjustments will be made by the CDC_FIFO.
-
-  * In both path (ADC and DAC) the data stream at the front-end side is packatized,
-meaning there is a valid TLAS/TKEEP in the stream. While in the back-end side
-the stream is continuous. (no TLAST/TKEEP)
-    * The DAC path have to have a depacketizer to get rid of the last partial beat
-from the stream.
-    * Because the ADC path already arrive in a packed form, and we always will
-fill up the whole storage, we don't need to treat special use-cases.
-
-### Used storage elements
-
-|                       |         ZC706      |       ZCU102      |       A10SOC     |
-|:----------------------|:------------------:|:-----------------:|:----------------:|
-|          FPGA         | XC7Z045 FFG900 – 2 | XCZU9EG-2FFVB1156 | 10AS066N3F40E2SG |
-| External Memory Type  |     DDR3 SODIMM    |        DDR4       |   DDR4 HILO      |
-| External Memory Size  |         1 GB       |       512 MB      |      2 GB        |
-| Embedded Memory Type  |         BRAM       |        BRAM       |      M20K        |
-| Embedded Memory Size  |       19.1 Mb      |       32.1 Mb     |      41 Mb       |
-
-### Data width manipulation
-
-* data width differences should be treated by the CDC FIFO
-
-* the smallest granularity should be 8 bits. This constraints mainly will generate
-additional logic just in the TX path, taking the fact that the data from the ADC
-will come packed.
-
-* the gearbox main role is to improve the DDR's bandwidth, strips the padding bits
-of each samples, so the raw data could be stored into the memory.
-
-### Xilinx's MIG vs. Intel's EMIF
-
-* Incrementing burst support for 1 to 256 beats, the length of the burst should
-be defined by the internal controller
-
-* Concurrent read/write access, the external memory to be shared between an ADC
-and DAC
-* Dynamic burst length tuning: an FSM reads and writes dummy data until both
-ADC's overflow and DAC's underflow lines are de-asserted. Pre-requisites : both
-device's interface should be up and running.
-
-* **TODO**: prefetch the next transfer if it's possible, by driving the address channels ahead (e.g. Overlapping read burst in case of AXI4)
-
-* Optional gearbox to congest the samples in order to increase the maximum data rate.
-* In general we packing all samples into 16 bits. This can add a significant
-overhand to the maximum real data rate on the memory interface. The gearbox main
-role is to pack and unpack the device's samples into the required data width. (in general 512 or 1024 bit)
-
-Boards with FPGA side DDR3/4 SODIMMs/HILO: ZC706, ZCU102, A10SOC
-
-|                              |  ZC706    |  ZCU102    |   A10SOC   |
-|------------------------------|:---------:|:----------:|:----------:|
-| Max data throughputs (MT/s)  |   1600    |   2400     |    2133    |
-| DDRx reference clocks        |  200 MHz  |  300 MHz   |    133 MHz |
-| DDRx Data bus width          |    64     |   16       |     64     |
-| Memory to FPGA clock ratio   |    4:1    |   4:1      |    4:1     |
-| UI type & burst length       | AXI4-256  | AXI4-256   | Avalon Memory Map |
-| UI data width                |    512    |   128      |    512     |
-
-### Internal cyclic buffer support for the TX path
-
-![Data path with external storage](./docs/architecture_DDR.svg)
-
-* On the front end side if the TX path, a special buffer will handle the data
-width up/down conversions and run in cyclic mode if the length of the data set
-is smaller than 4/8 AXI/Avalon burst. This way we can avoid to overload the memory
-interface with small bursts.
-
-* On the back end side, because the smallest granularity can be 8 bytes, we need
-a dynamic 'depackatizer' or re-aligner, which will filter out the invalid data
-bytes from the data stream. (this module will use the tlast and tkeep signal of
-the AXI stream interface)
-
-## Control path - Offload FSM
-
-### RX control FSM for internal RAM mode
-
-![RX_control FMS for internal RAM mode](./docs/rx_bram_fsm.svg)
-
-### TX control FSM for internal RAM mode
-
-![TX_control FMS for internal RAM mode](./docs/tx_bram_fsm.svg)
-
-**TODO** FSMs for the external DDR mode
-
-## References
-
-### AMBA AXI
-  * [AMBA specification](http://infocenter.arm.com/help/topic/com.arm.doc.set.amba/index.html#specs)
-  * [UG761 AXI Reference Guide](https://www.xilinx.com/support/documentation/ip_documentation/ug761_axi_reference_guide.pdf)
-
-### Avalon
-  * [Avalon Interface Specification](https://www.altera.com/en_US/pdfs/literature/manual/mnl_avalon_spec.pdf)
-
-### Xilinx
-  * [Device Memory Interface Solutions](https://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v4_2/ds176_7Series_MIS.pdf)
-  * [Device Memory Interface Solutions User Guide](https://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v4_2/ug586_7Series_MIS.pdf)
-  * [Ultrascale Architecutre-Based FPGAs Memory IP (v1.4)](https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf)
-  * [Xilinx FIFO Generator](https://www.xilinx.com/products/intellectual-property/fifo_generator.html#documentation)
-  * [7 Series FPGAs Memory Resources](https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf)
-  * [Ultrascale Memory Resources](https://www.xilinx.com/support/documentation/user_guides/ug573-ultrascale-memory-resources.pdf)
-
-### Intel
-  * [Intel Arria 10 Core Fabric and General Purpose I/Os Handbook](https://www.altera.com/en_US/pdfs/literature/hb/arria-10/a10_handbook.pdf)
-  * [Intel Arria 10 External Memory Interface IP User Guide](https://www.altera.com/en_US/pdfs/literature/ug/ug-20115.pdf)
-  * [Intel Arria 10 External Memory Interface IP Design Example](https://www.altera.com/en_US/pdfs/literature/ug/ug-20118.pdf)
-  * [Intel SCFIFO and DCFIFO](https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_fifo.pdf)
-  * [Intel Startix 10 High-Performance Design Handbook](https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/stratix-10/s10_hp_hb.pdf)
-  * [Intel Stratix 10 Embedded Memory User Guide](https://www.altera.com/en_US/pdfs/literature/hb/stratix-10/ug-s10-memory.pdf)
-
-### Supported FPGA boards
-  * [ZC706](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html)
-  * [ZCU102](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html)
-  * [A10SOC](https://www.altera.com/products/boards_and_kits/dev-kits/altera/arria-10-soc-development-kit.html)
diff --git a/adi_library/data_offload/component.xml b/adi_library/data_offload/component.xml
index f6483d19..f9111b22 100644
--- a/adi_library/data_offload/component.xml
+++ b/adi_library/data_offload/component.xml
@@ -659,7 +659,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>ceadfd38</spirit:value>
+            <spirit:value>d9849bc7</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -681,7 +681,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>ceadfd38</spirit:value>
+            <spirit:value>d9849bc7</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1771,7 +1771,7 @@
       <spirit:file>
         <spirit:name>data_offload.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_899431db</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_030b0371</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1948,11 +1948,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:50:18Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:07:11Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="f361c9fd"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="29e6b534"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="f72a0cff"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="c96ffe1f"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="3b0efb8f"/>
diff --git a/adi_library/data_offload/data_offload.v b/adi_library/data_offload/data_offload.v
index 1e1aed83..d4682f7e 100644
--- a/adi_library/data_offload/data_offload.v
+++ b/adi_library/data_offload/data_offload.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/data_offload/data_offload.xpr b/adi_library/data_offload/data_offload.xpr
index 4e12ca70..ec3ca421 100644
--- a/adi_library/data_offload/data_offload.xpr
+++ b/adi_library/data_offload/data_offload.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/data_offload/data_offload.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/data_offload/data_offload.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="1f7d1faac4524c79b3614f3e7268bcb1"/>
+    <Option Name="Id" Val="147fcfaa4b244bfd9e08b92bea8ca37f"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -192,21 +191,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -219,7 +218,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/data_offload/data_offload_fsm.v b/adi_library/data_offload/data_offload_fsm.v
index 3bccddc9..d32e1375 100644
--- a/adi_library/data_offload/data_offload_fsm.v
+++ b/adi_library/data_offload/data_offload_fsm.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/data_offload/data_offload_regmap.v b/adi_library/data_offload/data_offload_regmap.v
index dc3ea177..ff276e66 100644
--- a/adi_library/data_offload/data_offload_regmap.v
+++ b/adi_library/data_offload/data_offload_regmap.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/data_offload/docs/architecture_DDR.svg b/adi_library/data_offload/docs/architecture_DDR.svg
deleted file mode 100755
index 6bea3e11..00000000
--- a/adi_library/data_offload/docs/architecture_DDR.svg
+++ /dev/null
@@ -1,1260 +0,0 @@
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diff --git a/adi_library/i3c_controller/i3c_controller_core/Makefile b/adi_library/i3c_controller/i3c_controller_core/Makefile
new file mode 100644
index 00000000..a8916eb7
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_core/Makefile
@@ -0,0 +1,31 @@
+####################################################################################
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+LIBRARY_NAME := i3c_controller_core
+
+GENERIC_DEPS += i3c_controller_bit_mod.v
+GENERIC_DEPS += i3c_controller_bit_mod.vh
+GENERIC_DEPS += i3c_controller_core.v
+GENERIC_DEPS += i3c_controller_framing.v
+GENERIC_DEPS += i3c_controller_word.v
+GENERIC_DEPS += i3c_controller_word.vh
+
+XILINX_DEPS += i3c_controller_core_ip.tcl
+
+XILINX_DEPS += ../../i3c_controller/interfaces/i3c_controller.xml
+XILINX_DEPS += ../../i3c_controller/interfaces/i3c_controller_cmdp.xml
+XILINX_DEPS += ../../i3c_controller/interfaces/i3c_controller_cmdp_rtl.xml
+XILINX_DEPS += ../../i3c_controller/interfaces/i3c_controller_rmap.xml
+XILINX_DEPS += ../../i3c_controller/interfaces/i3c_controller_rmap_rtl.xml
+XILINX_DEPS += ../../i3c_controller/interfaces/i3c_controller_rtl.xml
+XILINX_DEPS += ../../i3c_controller/interfaces/i3c_controller_sdio.xml
+XILINX_DEPS += ../../i3c_controller/interfaces/i3c_controller_sdio_rtl.xml
+
+XILINX_INTERFACE_DEPS += i3c_controller/interfaces
+
+INTEL_DEPS += i3c_controller_core_hw.tcl
+
+include ../../scripts/library.mk
diff --git a/adi_library/i3c_controller/i3c_controller_core/component.xml b/adi_library/i3c_controller/i3c_controller_core/component.xml
new file mode 100644
index 00000000..ba3988bb
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_core/component.xml
@@ -0,0 +1,1016 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>i3c_controller_core</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>i3c</spirit:name>
+      <spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="i3c_controller" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="i3c_controller_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>scl</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i3c_scl</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sdo</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i3c_sdo</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sdi</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i3c_sdi</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>t</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>i3c_t</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>i3c_signal_clock</spirit:name>
+      <spirit:displayName>i3c_signal_clock</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.I3C_SIGNAL_CLOCK.ASSOCIATED_BUSIF">i3c</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.I3C_SIGNAL_CLOCK.ASSOCIATED_RESET">reset_n</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>i3c_signal_reset</spirit:name>
+      <spirit:displayName>i3c_signal_reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>reset_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.I3C_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>sdio</spirit:name>
+      <spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="i3c_controller_sdio" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="i3c_controller_sdio_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sdo_ready</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sdo_ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sdo_valid</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sdo_valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sdo</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sdo</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sdi_ready</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sdi_ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sdi_valid</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sdi_valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sdi_last</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sdi_last</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sdi</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sdi</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ibi_ready</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ibi_ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ibi_valid</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ibi_valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ibi</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ibi</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>sdio_signal_clock</spirit:name>
+      <spirit:displayName>sdio_signal_clock</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.SDIO_SIGNAL_CLOCK.ASSOCIATED_BUSIF">sdio</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.SDIO_SIGNAL_CLOCK.ASSOCIATED_RESET">reset_n</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>sdio_signal_reset</spirit:name>
+      <spirit:displayName>sdio_signal_reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>reset_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.SDIO_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>cmdp</spirit:name>
+      <spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="i3c_controller_cmdp" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="i3c_controller_cmdp_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cmdp_valid</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cmdp_valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cmdp_ready</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cmdp_ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cmdp</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cmdp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cmdp_error</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cmdp_error</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cmdp_nop</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cmdp_nop</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>cmdp_daa_trigger</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>cmdp_daa_trigger</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>cmdp_signal_clock</spirit:name>
+      <spirit:displayName>cmdp_signal_clock</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CMDP_SIGNAL_CLOCK.ASSOCIATED_BUSIF">cmdp</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.CMDP_SIGNAL_CLOCK.ASSOCIATED_RESET">reset_n</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>cmdp_signal_reset</spirit:name>
+      <spirit:displayName>cmdp_signal_reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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+          <spirit:physicalPort>
+            <spirit:name>reset_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
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diff --git a/adi_library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod.v b/adi_library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod.v
new file mode 100644
index 00000000..9b0ba9f3
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod.v
@@ -0,0 +1,247 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+/**
+ * Modulates the SDA and SCL lanes.
+ * SCL high time is fixed at 40ns in I3C mode:
+ * * 4 clock cycles at 100MHz clk.
+ * * 2 clock cycles at 50MHz clk.
+ * Parameter CLK_MOD tunes the number of clock cycles to module one lane bus bit,
+ * to achieve 12.5MHz at the maximum speed grade, set:
+ * * CLK_MOD = 0, clk = 100MHz
+ * * CLK_MOD = 1, clk = 50MHz
+ */
+
+`timescale 1ns/100ps
+
+`include "i3c_controller_bit_mod.vh"
+
+module i3c_controller_bit_mod #(
+  parameter CLK_MOD = 0
+) (
+  input reset_n,
+  input clk,
+
+  // Bit Modulation Command
+
+  input  [`MOD_BIT_CMD_WIDTH:0] cmdb,
+  input  cmdb_valid,
+  output cmdb_ready,
+
+  // Mux to alternative logic to support I²C devices.
+  input  i2c_mode,
+  // Indicates that the bus is not transferring,
+  // is *not* bus available condition because does not wait 1s after P.
+  output nop,
+  // 0:  1.56MHz
+  // 1:  3.12MHz
+  // 2:  6.25MHz
+  // 3: 12.50MHz
+  input [1:0] scl_pp_sg, // SCL push-pull speed grade.
+
+  output reg rx,
+  output     rx_valid,
+
+  // Bus drive signals
+
+  output     scl,
+  output reg sdo,
+  input      sdi,
+  output reg t
+);
+
+  localparam [1:0] SM_SETUP    = 0;
+  localparam [1:0] SM_STALL    = 1;
+  localparam [1:0] SM_SCL_LOW  = 2;
+  localparam [1:0] SM_SCL_HIGH = 3;
+
+  localparam COUNT_INCR = CLK_MOD ? 2 : 1;
+
+  reg [`MOD_BIT_CMD_WIDTH:0] cmdb_r;
+  reg [1:0] pp_sg;
+  reg [5:0] count; // Worst-case: 1.56MHz, 32-bits per half-bit.
+  reg       sr;
+  reg       i2c_mode_reg;
+  reg       i2c_scl_reg;
+  reg [3:0] count_delay;
+  reg [1:0] sm;
+
+  wire [`MOD_BIT_CMD_WIDTH:2] st;
+  wire [1:CLK_MOD] count_high;
+  wire [3:0] scl_posedge_multi;
+  wire       t_w;
+  wire       t_w2;
+  wire       sdo_w;
+  wire       scl_posedge;
+  wire       sr_sda;
+  wire       sr_scl;
+  wire       i3c_scl_posedge;
+  wire       i2c_scl;
+  wire       i2c_scl_posedge;
+  wire [1:0] ss;
+
+  always @(posedge clk) begin
+    count <= 4;
+    i2c_scl_reg <= i2c_scl;
+    count_delay <= {count_delay[2:0], count[5]};
+    if (!reset_n) begin
+      sm <= SM_SETUP;
+      cmdb_r <= {`MOD_BIT_CMD_NOP_, 2'b01};
+      pp_sg <= 2'b00;
+      sr <= 1'b0;
+      i2c_mode_reg <= 1'b0;
+    end else begin
+      if (sm == SM_SETUP & cmdb_valid) begin
+        i2c_mode_reg <= i2c_mode;
+      end
+
+      case (sm)
+        SM_SCL_LOW: begin
+          if (scl_posedge) begin
+            sm <= SM_SCL_HIGH;
+          end
+        end
+        SM_SCL_HIGH: begin
+          if (&count_high) begin
+            if (st == `MOD_BIT_CMD_STOP_) begin
+              sm <= SM_SETUP;
+            end else begin
+              sm <= SM_STALL;
+            end
+          end
+        end
+        SM_SETUP: begin
+          sr <= 1'b0;
+        end
+        SM_STALL: begin
+        end
+      endcase
+
+      if (cmdb_ready) begin
+        if (cmdb_valid) begin
+          cmdb_r <= cmdb[4:2] != `MOD_BIT_CMD_START_ ? cmdb : {cmdb[4:2], 1'b0, cmdb[0]};
+          // CMDW_MSG_RX is push-pull, but the Sr to stop from the controller side is open drain.
+          pp_sg <= cmdb[1] & cmdb[4:2] != `MOD_BIT_CMD_START_ ? scl_pp_sg : 2'b00;
+          sm <= SM_SCL_LOW;
+        end else begin
+          cmdb_r <= {`MOD_BIT_CMD_NOP_, 2'b01};
+        end
+      end
+
+      if (!cmdb_ready) begin
+        count <= count + COUNT_INCR;
+      end
+
+      if (sm == SM_SETUP) begin
+        sr <= 1'b0;
+      end else if (cmdb_ready) begin
+        sr <= 1'b1;
+      end
+    end
+  end
+
+  generate if (CLK_MOD) begin
+    // Is short on one clock cycle at clk 50MHz, scl 12.5MHz,
+    // but due to the lower clk frequency, timing slack to propagate is better.
+    always @(*) begin
+      rx = sdi === 1'b0 ? 1'b0 : 1'b1;
+    end
+  end else begin
+    always @(posedge clk) begin
+      rx <= sdi === 1'b0 ? 1'b0 : 1'b1;
+    end
+  end
+  endgenerate
+
+  always @(posedge clk) begin
+    // To guarantee thd_pp > 3ns.
+    sdo <= sdo_w;
+    t <= t_w2;
+  end
+
+  genvar i;
+  generate
+    for (i = 0; i < 4; i = i+1) begin: gen_scl
+      assign scl_posedge_multi[i] = &count[i+2:CLK_MOD];
+    end
+  endgenerate
+
+  assign scl_posedge = scl_posedge_multi[3-pp_sg];
+  assign count_high = count[1:CLK_MOD];
+  assign cmdb_ready = (sm == SM_SETUP) ||
+                      (sm == SM_STALL) ||
+                      (sm == SM_SCL_HIGH & &count_high);
+  assign ss = cmdb_r[1:0];
+  assign st = cmdb_r[`MOD_BIT_CMD_WIDTH:2];
+
+  // Used to generate Sr with generous timing (locked in open drain speed).
+  assign sr_sda = ((~count[4] & count[5]) | ~count[5]) & sm == SM_SCL_LOW;
+  assign sr_scl = count[5] | sm == SM_SCL_HIGH;
+  assign i2c_scl = count_delay[3];
+
+  assign i2c_scl_posedge = i2c_scl & ~i2c_scl_reg;
+  assign i3c_scl_posedge = (sm == SM_SCL_HIGH & &(~count_high));
+
+  // Multi-cycle-path worst-case:
+  // * 4 clks (12.5MHz, half-bit ack, 100MHz clk)
+  // * 2 clks (12.5MHz, half-bit ack, 50MHz clk)
+  assign rx_valid = i2c_mode_reg ? i2c_scl_posedge :
+                    CLK_MOD ? scl_posedge : i3c_scl_posedge;
+
+  assign sdo_w = st == `MOD_BIT_CMD_START_   ? sr_sda :
+                 st == `MOD_BIT_CMD_STOP_    ? 1'b0 :
+                 st == `MOD_BIT_CMD_WRITE_   ? ss[0] :
+                 st == `MOD_BIT_CMD_ACK_SDR_ ?
+                   (i2c_mode_reg ? 1'b1 : (sm == SM_SCL_HIGH ? rx : 1'b1)) :
+                 st == `MOD_BIT_CMD_ACK_IBI_ ?
+                   (sm == SM_SCL_HIGH ? 1'b1 : 1'b0) :
+                 1'b1;
+
+  // Expression ...
+  //assign t_w = st == `MOD_BIT_CMD_STOP_    ? 1'b0 :
+  //             st == `MOD_BIT_CMD_START_   ? 1'b0 :
+  //             st == `MOD_BIT_CMD_READ_    ? 1'b0 :
+  //             st == `MOD_BIT_CMD_ACK_SDR_ ? 1'b0 :
+  //             ss[1];
+  // ... gets optimized to
+  assign t_w  = st[4] ? 1'b0 : ss[1];
+  assign t_w2 = ~t_w & sdo_w ? 1'b1 : 1'b0;
+
+  assign scl = st == `MOD_BIT_CMD_START_ ? (sr ? sr_scl : 1'b1) :
+               i2c_mode_reg ? (i2c_scl || sm == SM_SETUP) :
+               (~(sm == SM_SCL_LOW || sm == SM_STALL));
+
+  assign nop = st == `MOD_BIT_CMD_NOP_ & sm == SM_SETUP;
+
+endmodule
diff --git a/adi_library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod.vh b/adi_library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod.vh
new file mode 100644
index 00000000..83916126
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod.vh
@@ -0,0 +1,74 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`ifndef BIT_MOD_CMD_V
+`define BIT_MOD_CMD_V
+
+`define MOD_BIT_CMD_WIDTH 4
+
+`define MOD_BIT_CMD_NOP_     3'b000
+`define MOD_BIT_CMD_WRITE_   3'b001
+`define MOD_BIT_CMD_ACK_IBI_ 3'b010
+
+`define MOD_BIT_CMD_START_   3'b100
+`define MOD_BIT_CMD_STOP_    3'b101
+`define MOD_BIT_CMD_ACK_SDR_ 3'b110
+`define MOD_BIT_CMD_READ_    3'b111
+
+// Stop, read, ack_sdr have PP variants to preserve the PP
+// speed-grade, but the they never active drive SDA High.
+// T-bit for read:
+//  To continue, yield ACK_SDR:
+//    Read RX to check if the peripheral wishes to continue.
+//  To stop, yield Start, creating a Sr.
+// ACK IBI bit:
+//  To ACK, yield ACK_IBI.
+//  to NACK, yield WRITE_OD_1
+
+`define MOD_BIT_CMD_NOP        {`MOD_BIT_CMD_NOP_,    2'b00}
+`define MOD_BIT_CMD_START_OD   {`MOD_BIT_CMD_START_,  2'b00}
+`define MOD_BIT_CMD_STOP_OD    {`MOD_BIT_CMD_STOP_,   2'b00}
+`define MOD_BIT_CMD_STOP_PP    {`MOD_BIT_CMD_STOP_,   2'b10}
+`define MOD_BIT_CMD_WRITE_OD_0 {`MOD_BIT_CMD_WRITE_,  2'b00}
+`define MOD_BIT_CMD_WRITE_OD_1 {`MOD_BIT_CMD_WRITE_,  2'b01}
+`define MOD_BIT_CMD_WRITE_PP_0 {`MOD_BIT_CMD_WRITE_,  2'b10}
+`define MOD_BIT_CMD_WRITE_PP_1 {`MOD_BIT_CMD_WRITE_,  2'b11}
+`define MOD_BIT_CMD_READ_OD    {`MOD_BIT_CMD_READ_,   2'b00}
+`define MOD_BIT_CMD_READ_PP    {`MOD_BIT_CMD_READ_,   2'b10}
+`define MOD_BIT_CMD_ACK_SDR_OD {`MOD_BIT_CMD_ACK_SDR_,2'b00}
+`define MOD_BIT_CMD_ACK_SDR_PP {`MOD_BIT_CMD_ACK_SDR_,2'b10}
+`define MOD_BIT_CMD_ACK_IBI    {`MOD_BIT_CMD_ACK_IBI_,2'b00}
+
+`endif
diff --git a/adi_library/i3c_controller/i3c_controller_core/i3c_controller_core.v b/adi_library/i3c_controller/i3c_controller_core/i3c_controller_core.v
new file mode 100644
index 00000000..b81f606b
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_core/i3c_controller_core.v
@@ -0,0 +1,194 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+`include "i3c_controller_bit_mod.vh"
+`include "i3c_controller_word.vh"
+
+module i3c_controller_core #(
+  parameter MAX_DEVS = 16,
+  parameter CLK_MOD = 0
+) (
+  input         clk,
+  input         reset_n,
+
+  // Command parsed
+
+  output        cmdp_ready,
+  input         cmdp_valid,
+  input  [30:0] cmdp,
+  output [2:0]  cmdp_error,
+  output        cmdp_nop,
+  output        cmdp_daa_trigger,
+
+  // Byte stream
+
+  output       sdo_ready,
+  input        sdo_valid,
+  input  [7:0] sdo,
+
+  input        sdi_ready,
+  output       sdi_valid,
+  output       sdi_last,
+  output [7:0] sdi,
+
+  input         ibi_ready,
+  output        ibi_valid,
+  output [14:0] ibi,
+
+  // uP accessible info
+
+  input  [1:0] rmap_ibi_config,
+  input  [1:0] rmap_pp_sg,
+  output [6:0] rmap_dev_char_addr,
+  input  [3:0] rmap_dev_char_data,
+
+  // I3C bus signals
+
+  output       i3c_scl,
+  output       i3c_sdo,
+  input        i3c_sdi,
+  output       i3c_t
+);
+
+  wire [`MOD_BIT_CMD_WIDTH:0] cmdb;
+  wire cmdb_valid;
+  wire cmdb_ready;
+
+  wire rx;
+  wire rx_valid;
+
+  wire cmdw_valid;
+  wire cmdw_ready;
+  wire [`CMDW_HEADER_WIDTH+8:0] cmdw;
+  wire cmdw_nack_bcast;
+  wire cmdw_nack_resp;
+
+  wire arbitration_valid;
+  wire ibi_bcr_2;
+  wire ibi_dev_is_attached;
+  wire ibi_requested;
+  wire ibi_requested_auto;
+  wire ibi_tick;
+  wire [6:0] ibi_da;
+  wire [7:0] ibi_mdb;
+
+  wire nop;
+  wire i2c_mode;
+
+  i3c_controller_framing #(
+    .MAX_DEVS(MAX_DEVS),
+    .CLK_MOD(CLK_MOD)
+  ) i_i3c_controller_framing (
+    .reset_n(reset_n),
+    .clk(clk),
+    .cmdp_valid(cmdp_valid),
+    .cmdp_ready(cmdp_ready),
+    .cmdp(cmdp),
+    .cmdp_error(cmdp_error),
+    .cmdp_daa_trigger(cmdp_daa_trigger),
+    .sdo_ready(sdo_ready),
+    .sdo_valid(sdo_valid),
+    .sdo(sdo),
+    .cmdw_valid(cmdw_valid),
+    .cmdw_ready(cmdw_ready),
+    .cmdw(cmdw),
+    .cmdw_nack_bcast(cmdw_nack_bcast),
+    .cmdw_nack_resp(cmdw_nack_resp),
+    .rx(rx),
+    .i2c_mode(i2c_mode),
+    .nop(nop),
+    .arbitration_valid(arbitration_valid),
+    .ibi_dev_is_attached(ibi_dev_is_attached),
+    .ibi_bcr_2(ibi_bcr_2),
+    .ibi_requested(ibi_requested),
+    .ibi_requested_auto(ibi_requested_auto),
+    .ibi_da(ibi_da),
+    .rmap_ibi_config(rmap_ibi_config),
+    .rmap_dev_char_addr(rmap_dev_char_addr),
+    .rmap_dev_char_data(rmap_dev_char_data));
+
+  i3c_controller_word
+  i_i3c_controller_word (
+    .reset_n(reset_n),
+    .clk(clk),
+    .cmdw_valid(cmdw_valid),
+    .cmdw_ready(cmdw_ready),
+    .cmdw(cmdw),
+    .cmdw_nack_bcast(cmdw_nack_bcast),
+    .cmdw_nack_resp(cmdw_nack_resp),
+    .sdi_ready(sdi_ready),
+    .sdi_valid(sdi_valid),
+    .sdi_last(sdi_last),
+    .sdi(sdi),
+    .cmdb(cmdb),
+    .cmdb_valid(cmdb_valid),
+    .cmdb_ready(cmdb_ready),
+    .rx(rx),
+    .rx_valid(rx_valid),
+    .arbitration_valid(arbitration_valid),
+    .ibi_dev_is_attached(ibi_dev_is_attached),
+    .ibi_bcr_2(ibi_bcr_2),
+    .ibi_requested(ibi_requested),
+    .ibi_requested_auto(ibi_requested_auto),
+    .ibi_tick(ibi_tick),
+    .ibi_da(ibi_da),
+    .ibi_mdb(ibi_mdb),
+    .rmap_ibi_config(rmap_ibi_config));
+
+  i3c_controller_bit_mod #(
+    .CLK_MOD(CLK_MOD)
+  ) i_i3c_controller_bit_mod (
+    .reset_n(reset_n),
+    .clk(clk),
+    .cmdb(cmdb),
+    .cmdb_valid(cmdb_valid),
+    .cmdb_ready(cmdb_ready),
+    .scl_pp_sg(rmap_pp_sg),
+    .rx(rx),
+    .rx_valid(rx_valid),
+    .i2c_mode(i2c_mode),
+    .nop(nop),
+    .scl(i3c_scl),
+    .sdo(i3c_sdo),
+    .sdi(i3c_sdi),
+    .t(i3c_t));
+
+  assign ibi = {ibi_da, ibi_mdb};
+  assign ibi_valid = ibi_tick;
+  assign cmdp_nop = nop;
+
+endmodule
diff --git a/adi_library/i3c_controller/i3c_controller_core/i3c_controller_core.xpr b/adi_library/i3c_controller/i3c_controller_core/i3c_controller_core.xpr
new file mode 100644
index 00000000..3c3e44de
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_core/i3c_controller_core.xpr
@@ -0,0 +1,433 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
+<!--                                                                         -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/i3c_controller/i3c_controller_core/i3c_controller_core.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
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+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
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+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
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+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
+    <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
+    <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
+    <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
+    <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
+    <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
+    <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+    <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+    <Option Name="BoardPart" Val=""/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
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+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
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+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="EnableResourceEstimation" Val="FALSE"/>
+    <Option Name="SimCompileState" Val="TRUE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
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+      <Config>
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+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="INFO"/>
+    <MsgAttr Name="Id" Val="Synth 8-3331"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="8"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="WARNING"/>
+    <MsgAttr Name="Id" Val="Synth 8-2490"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="9"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <Board/>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>
diff --git a/adi_library/i3c_controller/i3c_controller_core/i3c_controller_core_hw.tcl b/adi_library/i3c_controller/i3c_controller_core/i3c_controller_core_hw.tcl
new file mode 100644
index 00000000..82c59689
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_core/i3c_controller_core_hw.tcl
@@ -0,0 +1,93 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+package require qsys 14.0
+source ../../../scripts/adi_env.tcl
+source ../../scripts/adi_ip_intel.tcl
+
+ad_ip_create i3c_controller_core {I3C Controller Core} p_elaboration
+set_module_property ELABORATION_CALLBACK p_elaboration
+ad_ip_files i3c_controller_core [list \
+  i3c_controller_core.v \
+  i3c_controller_framing.v \
+  i3c_controller_word.v \
+  i3c_controller_word.vh \
+  i3c_controller_bit_mod.v \
+  i3c_controller_bit_mod.vh \
+]
+
+# parameters
+
+ad_ip_parameter MAX_DEVS STRING "MAX_DEVS"
+ad_ip_parameter CLK_MOD INTEGER 1
+
+proc p_elaboration {} {
+
+  # read parameters
+
+  set max_devs [get_parameter_value "MAX_DEVS"]
+  set clk_mod [get_parameter_value "CLK_MOD"]
+
+  # clock and reset interface
+
+  ad_interface clock  clk      input 1
+  ad_interface reset  reset_n  input 1 if_clk
+
+  add_interface sdo axi4stream end
+  add_interface_port sdo sdo_ready tready output 1
+  add_interface_port sdo sdo_valid tvalid input  1
+  add_interface_port sdo sdo       tdata  input  8
+
+  set_interface_property sdo associatedClock if_clk
+  set_interface_property sdo associatedReset if_reset_n
+
+  add_interface sdi axi4stream start
+  add_interface_port sdi sdi_ready tready input  1
+  add_interface_port sdi sdi_valid tvalid output 1
+  add_interface_port sdi sdi_last  tlast  output 1
+  add_interface_port sdi sdi       tdata  output 8
+
+  set_interface_property sdi associatedClock if_clk
+  set_interface_property sdi associatedReset if_reset_n
+
+  add_interface ibi axi4stream start
+  add_interface_port ibi ibi_ready tready input  1
+  add_interface_port ibi ibi_valid tvalid output 1
+  add_interface_port ibi ibi       tdata  output 15
+
+  set_interface_property ibi associatedClock if_clk
+  set_interface_property ibi associatedReset if_reset_n
+
+  add_interface cmdp conduit end
+  add_interface_port cmdp cmdp_ready       cready      output  1
+  add_interface_port cmdp cmdp_valid       cvalid      input   1
+  add_interface_port cmdp cmdp             cdata       input  31
+  add_interface_port cmdp cmdp_error       error       output  3
+  add_interface_port cmdp cmdp_nop         nop         output  1
+  add_interface_port cmdp cmdp_daa_trigger daa_trigger output  1
+
+  set_interface_property cmdp associatedClock if_clk
+  set_interface_property cmdp associatedReset if_reset_n
+
+  add_interface rmap conduit end
+  add_interface_port rmap rmap_ibi_config    ibi_config    input  2
+  add_interface_port rmap rmap_pp_sg         pp_sg         input  2
+  add_interface_port rmap rmap_dev_char_addr dev_char_addr output 7
+  add_interface_port rmap rmap_dev_char_data dev_char_data input  4
+
+  set_interface_property rmap associatedClock if_clk
+  set_interface_property rmap associatedReset if_reset_n
+
+  # physical I3C interface
+
+  add_interface i3c conduit end
+  add_interface_port i3c i3c_scl scl output 1
+  add_interface_port i3c i3c_sdo sdo output 1
+  add_interface_port i3c i3c_sdi sdi input  1
+  add_interface_port i3c i3c_t   t   output 1
+
+  set_interface_property i3c associatedClock if_clk
+  set_interface_property i3c associatedReset if_reset_n
+}
diff --git a/adi_library/i3c_controller/i3c_controller_core/i3c_controller_core_ip.tcl b/adi_library/i3c_controller/i3c_controller_core/i3c_controller_core_ip.tcl
new file mode 100644
index 00000000..4b7c428a
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_core/i3c_controller_core_ip.tcl
@@ -0,0 +1,126 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source ../../../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
+
+global VIVADO_IP_LIBRARY
+
+adi_ip_create i3c_controller_core
+adi_ip_files i3c_controller_core [list \
+  "i3c_controller_core.v" \
+  "i3c_controller_framing.v" \
+  "i3c_controller_word.v" \
+  "i3c_controller_word.vh" \
+  "i3c_controller_bit_mod.v" \
+  "i3c_controller_bit_mod.vh" \
+]
+
+adi_ip_properties_lite i3c_controller_core
+
+set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/i3c_controller/core} [ipx::current_core]
+
+# Remove all inferred interfaces
+ipx::remove_all_bus_interface [ipx::current_core]
+
+## Interface definitions
+
+adi_add_bus "i3c" "master" \
+  "analog.com:interface:i3c_controller_rtl:1.0" \
+  "analog.com:interface:i3c_controller:1.0" \
+  {
+    {"i3c_scl" "scl"} \
+    {"i3c_sdo" "sdo"} \
+    {"i3c_sdi" "sdi"} \
+    {"i3c_t"   "t"} \
+  }
+adi_add_bus_clock "clk" "i3c" "reset_n"
+
+adi_add_bus "sdio" "slave" \
+  "analog.com:interface:i3c_controller_sdio_rtl:1.0" \
+  "analog.com:interface:i3c_controller_sdio:1.0" \
+  {
+    {"sdo_ready" "sdo_ready"} \
+    {"sdo_valid" "sdo_valid"} \
+    {"sdo"       "sdo"} \
+    {"sdi_ready" "sdi_ready"} \
+    {"sdi_valid" "sdi_valid"} \
+    {"sdi_last"  "sdi_last"} \
+    {"sdi"       "sdi"} \
+    {"ibi_ready" "ibi_ready"} \
+    {"ibi_valid" "ibi_valid"} \
+    {"ibi"       "ibi"} \
+  }
+adi_add_bus_clock "clk" "sdio" "reset_n"
+
+adi_add_bus "cmdp" "slave" \
+  "analog.com:interface:i3c_controller_cmdp_rtl:1.0" \
+  "analog.com:interface:i3c_controller_cmdp:1.0" \
+  {
+    {"cmdp_valid"       "cmdp_valid"} \
+    {"cmdp_ready"       "cmdp_ready"} \
+    {"cmdp"             "cmdp"} \
+    {"cmdp_error"       "cmdp_error"} \
+    {"cmdp_nop"         "cmdp_nop"} \
+    {"cmdp_daa_trigger" "cmdp_daa_trigger"} \
+  }
+adi_add_bus_clock "clk" "cmdp" "reset_n"
+
+adi_add_bus "rmap" "slave" \
+  "analog.com:interface:i3c_controller_rmap_rtl:1.0" \
+  "analog.com:interface:i3c_controller_rmap:1.0" \
+  {
+    {"rmap_ibi_config"    "rmap_ibi_config"} \
+    {"rmap_pp_sg"         "rmap_pp_sg"} \
+    {"rmap_dev_char_addr" "rmap_dev_char_addr"} \
+    {"rmap_dev_char_data" "rmap_dev_char_data"} \
+  }
+adi_add_bus_clock "clk" "rmap" "reset_n" "master"
+
+set cc [ipx::current_core]
+
+## MAX_DEVS
+set_property -dict [list \
+  "value_validation_type" "range_long" \
+  "value_validation_range_minimum" "1" \
+  "value_validation_range_maximum" "16" \
+ ] \
+ [ipx::get_user_parameters MAX_DEVS -of_objects $cc]
+
+## CLK_MOD
+set_property -dict [list \
+	"value_validation_type" "pairs" \
+	"value_validation_pairs" {"8" 0 "4" 1} \
+] \
+[ipx::get_user_parameters CLK_MOD -of_objects $cc]
+
+## Customize IP Layout
+## Remove the automatically generated GUI page
+ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc]
+ipx::save_core [ipx::current_core]
+
+## Create general configuration page
+ipgui::add_page -name {I3C Controller Core} -component [ipx::current_core] -display_name {AXI I3C Controller Core}
+set page0 [ipgui::get_pagespec -name "I3C Controller Core" -component $cc]
+
+set general_group [ipgui::add_group -name "General Configuration" -component $cc \
+    -parent $page0 -display_name "General Configuration" ]
+
+ipgui::add_param -name "MAX_DEVS" -component $cc -parent $general_group
+set_property -dict [list \
+  "display_name" "Maximum number of peripherals" \
+  "tooltip" "\[MAX_DEVS\] Maximum number of peripherals in the bus, counting the controller" \
+] [ipgui::get_guiparamspec -name "MAX_DEVS" -component $cc]
+
+ipgui::add_param -name "CLK_MOD" -component $cc -parent $general_group
+set_property -dict [list \
+	"widget" "comboBox" \
+	"display_name" "Clock cycles per bit" \
+  "tooltip" "\[CLK_MOD\] Adjust clock cycles required to modulate the lane bus bits. Set 8 to achieve 12.5MHz at 100Mhz input clock, and 4 at 50MHz." \
+] [ipgui::get_guiparamspec -name "CLK_MOD" -component $cc]
+
+## Create and save the XGUI file
+ipx::create_xgui_files $cc
+ipx::save_core $cc
diff --git a/adi_library/i3c_controller/i3c_controller_core/i3c_controller_framing.v b/adi_library/i3c_controller/i3c_controller_core/i3c_controller_framing.v
new file mode 100644
index 00000000..a18629e0
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_core/i3c_controller_framing.v
@@ -0,0 +1,430 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+/**
+ * Frames commands to the word module.
+ * That means, joins cmdp and sdio bus into single interface cmdw.
+ * It is the main state-machine for the Command Descriptors received.
+ *
+ * The Dynamic Address Assigment (DAA) procedure is:
+ * Controller       | Peripheral  | Flow
+ * -----------------|-------------|---------
+ * S,0x7e,RnW=0     |             |    │
+ *                  | ACK         |    │
+ * ENTDAA,T         |             |    │
+ * Sr               |             | ┌─►│
+ * 0x7e,RnW=1       |             | │  ▼
+ *                  | ACK         | │  A──┐
+ *                  | PID+BCR+DCR | │  │  │
+ * DA, Par          |             | │  ▼  │
+ *                  | ACK         | └──B  │
+ * P                |             |    C◄─┘
+ *
+ * Notes
+ * From A with ACK, continue flow to B, or with NACK, goto C Stop,
+ * finishing the DAA. At B, goto on st state before A, Sr.
+ * The first and last ACK are mandatory in the flowchart, if a NACK is received,
+ * it is considered an error and the module resets.
+ * The whole DAA occurs in OD, hence the Start as Sr in the SM below.
+ */
+
+`timescale 1ns/100ps
+
+`include "i3c_controller_word.vh"
+
+module i3c_controller_framing #(
+  parameter MAX_DEVS = 16,
+  parameter CLK_MOD = 0
+) (
+  input         clk,
+  input         reset_n,
+
+  // Command parsed
+
+  output        cmdp_ready,
+  input         cmdp_valid,
+  input  [30:0] cmdp,
+  output [2:0]  cmdp_error,
+  output reg    cmdp_daa_trigger,
+
+  // Byte stream
+
+  output        sdo_ready,
+  input         sdo_valid,
+  input  [7:0]  sdo,
+
+  // Word command
+
+  output [`CMDW_HEADER_WIDTH+8:0] cmdw,
+  output        cmdw_valid,
+  input         cmdw_ready,
+  input         cmdw_nack_bcast,
+  input         cmdw_nack_resp,
+
+  // Raw SDO input
+
+  input         rx,
+
+  input         nop,
+  output reg    i2c_mode,
+
+  // IBI interface
+
+  input         arbitration_valid,
+  output        ibi_dev_is_attached,
+  output        ibi_bcr_2,
+  input         ibi_requested,
+  output reg    ibi_requested_auto,
+  input [6:0]   ibi_da,
+
+  // uP accessible info
+
+  input  [1:0]  rmap_ibi_config,
+  output [6:0]  rmap_dev_char_addr,
+  input  [3:0]  rmap_dev_char_data
+);
+
+  // Defines the bus available condition width (> 1us for target)
+  // Setting around 0.64us for the controller.
+  localparam BUS_AVAIL = CLK_MOD ? 4 : 5;
+
+  localparam [2:0] SM_SETUP       = 0;
+  localparam [2:0] SM_VALIDATE    = 1;
+  localparam [2:0] SM_TRANSFER    = 2;
+  localparam [2:0] SM_SETUP_SDO   = 3;
+  localparam [2:0] SM_CLEANUP     = 4;
+  localparam [2:0] SM_ARBITRATION = 5;
+
+  localparam [6:0] CCC_ENTDAA = 'h07;
+
+  reg [`CMDW_HEADER_WIDTH:0] st;
+  reg [BUS_AVAIL:0] bus_avail_reg;
+  reg        cmdp_ccc_reg;
+  reg        cmdp_ccc_bcast_reg;
+  reg [6:0]  cmdp_ccc_id_reg;
+  reg        cmdp_bcast_header_reg;
+  reg        cmdp_sr_reg;
+  reg [11:0] cmdp_buffer_len_reg;
+  reg [6:0]  cmdp_da_reg;
+  reg        cmdp_rnw_reg;
+  reg        cmdp_valid_reg;
+  reg [7:0]  cmdw_body;
+  reg        ctrl_daa;
+  reg        ctrl_validate;
+  reg [3:0]  j;
+  reg [2:0]  dev_char_len;
+  reg        daa_trigger;
+  reg        error_nack_bcast;
+  reg        error_unknown_da;
+  reg        error_nack_resp ;
+  reg [2:0]  sm;
+
+  wire        bus_avail;
+  wire        ibi_enable;
+  wire        ibi_listen;
+  wire        cmdp_rnw;
+  wire [6:0]  cmdp_da;
+  wire [11:0] cmdp_buffer_len;
+  wire        cmdp_sr;
+  wire        cmdp_bcast_header;
+  wire        cmdp_ccc;
+  wire [6:0]  cmdp_ccc_id;
+  wire        cmdp_ccc_bcast;
+  wire        dev_is_attached;
+  wire        dev_is_i2c;
+
+  always @(posedge clk) begin
+    error_unknown_da <= 1'b0;
+    if (!reset_n) begin
+      j <= 0;
+      st  <= `CMDW_NOP;
+      sm <= SM_SETUP;
+      ctrl_daa <= 1'b0;
+      ibi_requested_auto <= 1'b0;
+      cmdp_sr_reg <= 0;
+      daa_trigger <= 1'b0;
+      i2c_mode <= 1'b0;
+    end else if (cmdw_nack_bcast | cmdw_nack_resp) begin
+      j <= 0;
+      st  <= `CMDW_NOP;
+      sm <= cmdp_ccc_id_reg == CCC_ENTDAA ? SM_SETUP :
+             cmdp_rnw_reg ? SM_SETUP : SM_CLEANUP;
+      ctrl_daa <= 1'b0;
+    end else begin
+
+      // Delay DAA trigger one word to match last SDI byte.
+      cmdp_daa_trigger <= 1'b0;
+      if (cmdw_ready) begin
+        daa_trigger <= 1'b0;
+        cmdp_daa_trigger <= daa_trigger;
+      end
+
+      // SDI Ready is are not checked, data will be lost
+      // if it do not accept/provide data when needed.
+      case (sm)
+        SM_SETUP: begin
+          j <= 0;
+          i2c_mode <= 1'b0;
+          // Condition where a peripheral requested a IBI during quiet times.
+          if (cmdp_valid) begin
+            cmdp_sr_reg <= cmdp_sr;
+            // Look last SM_TRANSFER SR flag.
+            st <= cmdp_sr_reg ? `CMDW_MSG_SR : `CMDW_START;
+            // CCC Broadcast casts to all devices, validation not required.
+            // Direct is CCC_BCAST 1'b1
+            sm <= cmdp_ccc & ~cmdp_ccc_bcast ? SM_TRANSFER : SM_VALIDATE;
+            ctrl_validate <= 1'b0;
+          end else if (ibi_listen & rx === 1'b0 & bus_avail) begin
+            st <= `CMDW_BCAST_7E_W0;
+            sm <= SM_TRANSFER;
+            ibi_requested_auto <= 1'b1;
+          end
+          cmdp_valid_reg        <= cmdp_valid;
+          cmdp_ccc_reg          <= cmdp_ccc;
+          cmdp_ccc_bcast_reg    <= cmdp_ccc_bcast;
+          cmdp_ccc_id_reg       <= cmdp_ccc_id;
+          cmdp_bcast_header_reg <= cmdp_bcast_header;
+          cmdp_buffer_len_reg   <= cmdp_buffer_len;
+          cmdp_da_reg           <= cmdp_da;
+          cmdp_rnw_reg          <= cmdp_rnw;
+        end
+        SM_VALIDATE: begin
+          // Provide one clock cycle to read the BRAM and improve timing.
+          ctrl_validate <= 1'b1;
+          if (ctrl_validate) begin
+            if (dev_is_i2c) begin
+              i2c_mode <= 1'b1;
+            end else begin
+              i2c_mode <= 1'b0;
+            end
+            if (dev_is_attached) begin
+              sm <= SM_TRANSFER;
+            end else begin
+              error_unknown_da <= 1'b1;
+              sm <= cmdp_rnw_reg ? SM_SETUP : SM_CLEANUP;
+            end
+          end
+        end
+        SM_TRANSFER: begin
+          if (cmdw_ready) begin
+            ibi_requested_auto <= 1'b0;
+            case(st)
+              `CMDW_NOP: begin
+                sm <= SM_SETUP;
+                ctrl_daa <= 1'b0;
+              end
+              `CMDW_SR,
+              `CMDW_START: begin
+                cmdw_body <= {cmdp_da, cmdp_rnw}; // Attention to RnW here
+                st <= ctrl_daa ? `CMDW_BCAST_7E_W1 :
+                      (~cmdp_bcast_header_reg & ~cmdp_ccc_reg) | dev_is_i2c ? `CMDW_TARGET_ADDR_OD :
+                      `CMDW_BCAST_7E_W0;
+              end
+              `CMDW_BCAST_7E_W0: begin
+                sm <= SM_ARBITRATION;
+                cmdw_body <= {cmdp_ccc_bcast_reg, cmdp_ccc_id_reg}; // Attention to BCAST here
+              end
+              `CMDW_CCC_OD: begin
+                // Occurs only during the DAA
+                st <= `CMDW_START;
+                ctrl_daa <= 1'b1;
+              end
+              `CMDW_CCC_PP: begin
+                if (cmdp_ccc_bcast_reg) begin
+                  st <= `CMDW_MSG_SR;
+                end else if (~|cmdp_buffer_len_reg) begin
+                  st  <= `CMDW_STOP_PP;
+                  if (cmdp_sr_reg) begin
+                    sm <= SM_SETUP;
+                  end
+                end else begin
+                  st <= `CMDW_MSG_TX;
+                  sm <= SM_SETUP_SDO;
+                  cmdp_buffer_len_reg <= cmdp_buffer_len_reg - 1;
+                end
+              end
+              `CMDW_BCAST_7E_W1: begin
+                // Occurs only during the DAA
+                dev_char_len <= 7;
+                st <= `CMDW_DAA_DEV_CHAR;
+              end
+              `CMDW_DAA_DEV_CHAR: begin
+                dev_char_len <= dev_char_len - 1;
+                if (~|dev_char_len) begin
+                  st  <= `CMDW_DYN_ADDR;
+                  sm <= SM_SETUP_SDO;
+                  daa_trigger <= 1'b1;
+                end
+              end
+              `CMDW_DYN_ADDR: begin
+                st <= j == MAX_DEVS - 1 ? `CMDW_STOP_OD : `CMDW_START;
+              end
+              `CMDW_MSG_SR: begin
+                cmdw_body <= {cmdp_da, cmdp_rnw}; // Be aware of RnW here
+                st <= dev_is_i2c ? `CMDW_TARGET_ADDR_OD : `CMDW_TARGET_ADDR_PP;
+              end
+              `CMDW_TARGET_ADDR_OD,
+              `CMDW_TARGET_ADDR_PP: begin
+                if (cmdp_rnw_reg) begin
+                  st <= dev_is_i2c ? `CMDW_I2C_RX : `CMDW_MSG_RX;
+                end else begin
+                  st <= dev_is_i2c ? `CMDW_I2C_TX : `CMDW_MSG_TX;
+                  sm <= SM_SETUP_SDO;
+                end
+                cmdp_buffer_len_reg <= cmdp_buffer_len_reg - 1;
+              end
+              `CMDW_I2C_RX,
+              `CMDW_MSG_RX: begin
+                // I²C read transfers cannot be stopped by the peripheral.
+                cmdp_buffer_len_reg <= cmdp_buffer_len_reg - 1;
+                if (~|cmdp_buffer_len_reg) begin
+                  st  <= dev_is_i2c ? `CMDW_STOP_OD :`CMDW_STOP_PP;
+                  if (cmdp_sr_reg) begin
+                    sm <= SM_SETUP;
+                  end
+                end
+              end
+              `CMDW_I2C_TX,
+              `CMDW_MSG_TX: begin
+                cmdp_buffer_len_reg <= cmdp_buffer_len_reg - 1;
+                if (~|cmdp_buffer_len_reg) begin
+                  st  <= dev_is_i2c ? `CMDW_STOP_OD :`CMDW_STOP_PP;
+                  if (cmdp_sr_reg) begin
+                    sm <= SM_SETUP;
+                  end
+                end else begin
+                  sm <= SM_SETUP_SDO;
+                end
+              end
+              `CMDW_STOP_OD,
+              `CMDW_STOP_PP: begin
+                sm <= SM_SETUP;
+                st <= `CMDW_NOP;
+                cmdp_sr_reg <= 1'b0;
+              end
+              `CMDW_IBI_MDB: begin
+                st <= cmdp_valid_reg ? `CMDW_SR : `CMDW_STOP_PP;
+              end
+              default: begin
+                st <= `CMDW_NOP;
+              end
+            endcase
+          end
+        end
+        SM_SETUP_SDO: begin
+          if (sdo_valid) begin
+            sm <= SM_TRANSFER;
+          end
+          cmdw_body <= sdo;
+        end
+        SM_CLEANUP: begin
+          // The peripheral did not ACK the SM_TRANSFER, so it is cancelled.
+          // the SDO data is discarded
+          if (sdo_valid) begin
+            cmdp_buffer_len_reg <= cmdp_buffer_len_reg - 1;
+          end
+          if (cmdp_buffer_len_reg == 0) begin
+            sm <= SM_SETUP;
+          end
+        end
+        SM_ARBITRATION: begin
+          if (arbitration_valid) begin
+            sm <= SM_TRANSFER;
+            // IBI requested during CMDW_BCAST_7E_W0.
+            // At the word module, was ACKed if IBI is enabled and DA is known, if not, NACKed.
+            if (ibi_requested) begin
+              // Receive MSB if IBI is enabled, dev is known and BCR[2] is 1'b1.
+              if (ibi_enable & dev_is_attached & ibi_bcr_2) begin
+                st <= `CMDW_IBI_MDB;
+              end else begin
+                st <= cmdp_valid_reg ? `CMDW_START : `CMDW_STOP_OD;
+              end
+            // No IBI requested during CMDW_BCAST_7E_W0.
+            end else if (cmdp_valid_reg) begin
+              st <= cmdp_ccc_reg ?
+                    (cmdp_ccc_id_reg == CCC_ENTDAA ? `CMDW_CCC_OD : `CMDW_CCC_PP) : `CMDW_MSG_SR;
+            end else begin
+              st <= `CMDW_STOP_OD;
+            end
+          end
+        end
+        default: begin
+          sm <= SM_SETUP;
+        end
+      endcase
+    end
+    // Improve timing
+    error_nack_resp <= cmdw_nack_resp;
+    error_nack_bcast <= cmdw_nack_bcast;
+  end
+
+  // Bus available condition
+  always @(posedge clk) begin
+    if (!reset_n || !nop) begin
+      bus_avail_reg <= 0;
+    end else if (!bus_avail) begin
+      bus_avail_reg <= bus_avail_reg + 1;
+    end
+  end
+  assign bus_avail = &bus_avail_reg;
+
+  // Device characteristics look-up.
+
+  assign dev_is_i2c      = rmap_dev_char_data[0] === 1'b1;
+  assign dev_is_attached = rmap_dev_char_data[1] === 1'b1;
+  assign ibi_bcr_2       = rmap_dev_char_data[3] === 1'b1;
+
+  assign ibi_dev_is_attached = dev_is_attached;
+  assign rmap_dev_char_addr  = ibi_requested ? ibi_da : cmdp_da_reg;
+
+  assign cmdp_ready = sm == SM_SETUP & !cmdw_nack_bcast & !cmdw_nack_resp & reset_n;
+  assign sdo_ready = (sm == SM_SETUP_SDO | sm == SM_CLEANUP) & !cmdw_nack_bcast & !cmdw_nack_resp & reset_n;
+  assign cmdw = {st, cmdw_body};
+  assign cmdw_valid = sm == SM_TRANSFER;
+
+  assign ibi_enable = rmap_ibi_config[0];
+  assign ibi_listen = rmap_ibi_config[1];
+
+  assign cmdp_rnw          = cmdp[0];
+  assign cmdp_da           = cmdp[7:1];
+  assign cmdp_buffer_len   = cmdp[19:8];
+  assign cmdp_sr           = cmdp[20];
+  assign cmdp_bcast_header = cmdp[21];
+  assign cmdp_ccc          = cmdp[22];
+  assign cmdp_ccc_id       = cmdp[29:23];
+  assign cmdp_ccc_bcast    = cmdp[30];
+
+  assign cmdp_error = {error_nack_resp, error_unknown_da, error_nack_bcast};
+
+endmodule
diff --git a/adi_library/i3c_controller/i3c_controller_core/i3c_controller_word.v b/adi_library/i3c_controller/i3c_controller_core/i3c_controller_word.v
new file mode 100644
index 00000000..35858181
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_core/i3c_controller_word.v
@@ -0,0 +1,430 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+/**
+ * Executes Word Commands received by the framing module.
+ * Each state has linear sub-states counted in Bit Modulation Commands.
+ */
+
+`timescale 1ns/100ps
+
+`include "i3c_controller_word.vh"
+`include "i3c_controller_bit_mod.vh"
+
+module i3c_controller_word (
+  input      clk,
+  input      reset_n,
+
+  // Word command
+
+  output reg cmdw_nack_bcast,
+  output reg cmdw_nack_resp,
+  output     cmdw_ready,
+  input      cmdw_valid,
+  input  [`CMDW_HEADER_WIDTH+8:0] cmdw,
+
+  // Byte stream
+
+  input      sdi_ready,
+  output reg sdi_valid,
+  output     sdi_last,
+  output reg [7:0] sdi,
+
+  // Bit Modulation Command
+
+  output [`MOD_BIT_CMD_WIDTH:0] cmdb,
+  output       cmdb_valid,
+  input        cmdb_ready,
+
+  // RX and ACK
+
+  input        rx,
+  input        rx_valid,
+
+  // IBI interface
+
+  output reg   arbitration_valid,
+  input        ibi_dev_is_attached,
+  input        ibi_bcr_2,
+  output reg   ibi_requested,
+  input        ibi_requested_auto,
+  output reg   ibi_tick,
+  output [6:0] ibi_da,
+  output [7:0] ibi_mdb,
+
+  // uP accessible info
+
+  input [1:0]  rmap_ibi_config
+);
+
+  localparam [6:0] I3C_RESERVED = 7'h7e;
+
+  localparam [1:0] SM_GET      = 0;
+  localparam [1:0] SM_SETUP    = 1;
+  localparam [1:0] SM_TRANSFER = 2;
+  localparam [1:0] SM_RESOLVE  = 3;
+
+  reg [`CMDW_HEADER_WIDTH:0] st;
+  reg [`MOD_BIT_CMD_WIDTH:2] cmd_r;
+  reg [1:0] sm;
+  reg       sg;
+  reg [7:0] cmdw_body;
+  reg       cmdw_nacked;
+  reg [7:0] ibi_da_reg;
+  reg [7:0] ibi_mdb_reg;
+  reg       do_ack;  // Peripheral did NACK?
+  reg       do_rx_t; // Peripheral end Message at T in Read Data?
+  reg       cmd_wr;
+  reg       sdi_last_reg;
+  reg [5:0] i;
+  reg [5:0] i_;
+
+  wire ibi_enable;
+  wire cmdw_nack;
+  wire [`CMDW_HEADER_WIDTH:0] cmdw_header;
+
+  // # of Bit Modulation Commands - 1 per word
+  always @(st) begin
+    case (st)
+      `CMDW_NOP             : i_ =  0;
+      `CMDW_START           : i_ =  0;
+      `CMDW_BCAST_7E_W0     : i_ =  8; // 7'h7e+RnW=0+ACK / DA+RnW=1+ACK_IBI
+      `CMDW_CCC_OD          : i_ =  8; // Direct/Bcast+CCC+T
+      `CMDW_CCC_PP          : i_ =  8; // Direct/Bcast+CCC+T
+      `CMDW_TARGET_ADDR_OD  : i_ =  8; // DA+RNW+ACK
+      `CMDW_TARGET_ADDR_PP  : i_ =  8; // DA+RNW+ACK
+      `CMDW_MSG_SR          : i_ =  0;
+      `CMDW_MSG_RX          : i_ =  8; // SDI+T
+      `CMDW_MSG_TX          : i_ =  8; // SDO+T
+      `CMDW_STOP_OD         : i_ =  0;
+      `CMDW_STOP_PP         : i_ =  0;
+      `CMDW_BCAST_7E_W1     : i_ =  8; // 7'h7e+RnW=1+ACK
+      `CMDW_DAA_DEV_CHAR    : i_ =  7; // 8-bit section of the PID+BCR+DCR
+      `CMDW_DYN_ADDR        : i_ =  8; // DA+T+ACK
+      `CMDW_IBI_MDB         : i_ =  8; // MDB+T
+      `CMDW_SR              : i_ =  0;
+      `CMDW_I2C_TX          : i_ =  8; // SDO+ACK
+      `CMDW_I2C_RX          : i_ =  8; // SDI+ACK
+      default               : i_ =  0;
+    endcase
+
+    // Set speed grade (open drain or push-pull) for each word.
+    case (st)
+      `CMDW_NOP             : sg = 0;
+      `CMDW_START           : sg = 0;
+      `CMDW_BCAST_7E_W0     : sg = 0;
+      `CMDW_CCC_OD          : sg = 0;
+      `CMDW_CCC_PP          : sg = 1;
+      `CMDW_TARGET_ADDR_OD  : sg = 0;
+      `CMDW_TARGET_ADDR_PP  : sg = 1;
+      `CMDW_MSG_SR          : sg = 0;
+      `CMDW_MSG_RX          : sg = 1;
+      `CMDW_MSG_TX          : sg = 1;
+      `CMDW_STOP_OD         : sg = 0;
+      `CMDW_STOP_PP         : sg = 1;
+      `CMDW_BCAST_7E_W1     : sg = 0;
+      `CMDW_DAA_DEV_CHAR    : sg = 0;
+      `CMDW_DYN_ADDR        : sg = 0;
+      `CMDW_IBI_MDB         : sg = 1;
+      `CMDW_SR              : sg = 0;
+      `CMDW_I2C_TX          : sg = 0;
+      `CMDW_I2C_RX          : sg = 0;
+      default               : sg = 0;
+    endcase
+  end
+
+  always @(posedge clk) begin
+    ibi_tick <= 1'b0;
+    sdi_valid <= 1'b0;
+    sdi_last_reg <= 1'b0;
+    arbitration_valid <= 1'b0;
+    if (!reset_n) begin
+      i <= 0;
+      sm <= SM_GET;
+      cmd_wr <= 1'b0;
+      st <= `CMDW_NOP;
+      ibi_requested <= 1'b0;
+      cmd_r <= `MOD_BIT_CMD_NOP_;
+    end else begin
+      case (sm)
+        SM_GET: begin
+          if (cmdw_valid) begin
+            sm <= SM_SETUP;
+          end
+          st <= cmdw_header;
+          cmdw_body <= cmdw[7:0];
+          ibi_requested <= ibi_requested_auto;
+          i <= 0;
+          cmdw_nacked <= 1'b0;
+        end
+        SM_SETUP: begin
+          sm <= SM_TRANSFER;
+          do_ack  <= 1'b0;
+          do_rx_t <= 1'b0;
+
+          case (st)
+            `CMDW_NOP: begin
+              cmd_r <= `MOD_BIT_CMD_NOP_;
+            end
+            `CMDW_START: begin
+              cmd_r <= `MOD_BIT_CMD_START_;
+            end
+            `CMDW_BCAST_7E_W0: begin
+              // During the header broadcast, the peripheral shall issue an IBI, due
+              // to this the SDO is monitored and if the controller loses arbitration,
+              // shall ACK if IBI is enabled and the DA is attached.
+              // If the peripheral's BCR[2] == 1'b1, also receive the MDB.
+              // If the device is unknown, NACK the ibi request.
+              // resolved;
+              if (i[2:1] == 2'b11 & ~ibi_requested) begin
+                // 1'b0+RnW=0
+                cmd_r <= `MOD_BIT_CMD_WRITE_;
+                cmd_wr <= 1'b0;
+              end else if (i == 8) begin
+                if (ibi_requested) begin // also ibi_len ...
+                  // ACK if IBI is enabled and device is known if not, NACK.
+                  cmd_r <= ibi_enable & ibi_dev_is_attached ? `MOD_BIT_CMD_ACK_IBI_ : `MOD_BIT_CMD_READ_;
+                end else begin
+                  // ACK
+                  cmd_r <= `MOD_BIT_CMD_ACK_SDR_;
+                  do_ack <= 1'b1;
+                end
+              end else begin
+                // 6'b111111
+                cmd_r <= `MOD_BIT_CMD_READ_;
+              end
+            end
+            `CMDW_BCAST_7E_W1: begin
+              if (i == 7) begin
+                // RnW=1
+                cmd_r  <= `MOD_BIT_CMD_WRITE_;
+                cmd_wr <= 1'b1;
+              end else if (i == 8) begin
+                // ACK
+                cmd_r <= `MOD_BIT_CMD_ACK_SDR_;
+                do_ack <= 1'b1;
+              end else begin
+                // 7'h7e
+                cmd_r  <= `MOD_BIT_CMD_WRITE_;
+                cmd_wr <= I3C_RESERVED[6 - i[2:0]];
+              end
+            end
+            `CMDW_DYN_ADDR,
+            `CMDW_TARGET_ADDR_OD,
+            `CMDW_TARGET_ADDR_PP: begin
+              if (i == 8) begin
+                // ACK
+                cmd_r  <= `MOD_BIT_CMD_ACK_SDR_;
+                do_ack <= 1'b1;
+              end else begin
+                // DA+RnW/DA+T
+                cmd_r  <= `MOD_BIT_CMD_WRITE_;
+                cmd_wr <= cmdw_body[7 - i[2:0]];
+              end
+            end
+            `CMDW_SR,
+            `CMDW_MSG_SR: begin
+              cmd_r <= `MOD_BIT_CMD_START_;
+            end
+            `CMDW_I2C_RX: begin
+              if (i == 8) begin
+                // In I2C, the peripheral cannot stop the SM_TRANSFER.
+                cmd_r <= `MOD_BIT_CMD_WRITE_;
+                if (sdi_ready) begin
+                  cmd_wr <= 1'b0; // ACK
+                end else begin
+                  cmd_wr <= 1'b1; // NACK
+                end
+              end else begin
+                // SDI
+                cmd_r <= `MOD_BIT_CMD_READ_;
+              end
+            end
+            `CMDW_MSG_RX: begin
+              if (i == 8) begin
+                // T
+                if (sdi_ready) begin
+                  if (cmdw_header == `CMDW_STOP_PP) begin
+                    // Peek next command to see if the controller wishes to
+                    // end the SM_TRANSFER.
+                    cmd_r <= `MOD_BIT_CMD_START_;
+                  end else begin
+                    // continue, if peripheral wishes to do so
+                    cmd_r <= `MOD_BIT_CMD_ACK_SDR_;
+                    do_rx_t <= 1'b1;
+                  end
+                end else begin
+                  cmd_r <= `MOD_BIT_CMD_START_; // stop
+                end
+              end else begin
+                // SDI
+                cmd_r <= `MOD_BIT_CMD_READ_;
+              end
+            end
+            `CMDW_I2C_TX: begin
+              if (i == 8) begin
+                // ACK
+                do_ack <= 1'b1;
+                cmd_r <= `MOD_BIT_CMD_READ_;
+              end else begin
+                // SDO
+                cmd_r  <= `MOD_BIT_CMD_WRITE_;
+                cmd_wr <= cmdw_body[7 - i[2:0]];
+              end
+            end
+            `CMDW_CCC_OD,
+            `CMDW_CCC_PP,
+            `CMDW_MSG_TX: begin
+              if (i == 8) begin
+                // T
+                cmd_r  <= `MOD_BIT_CMD_WRITE_;
+                cmd_wr <= ~^cmdw_body;
+              end else begin
+                // SDO/BCAST+CCC
+                cmd_r  <= `MOD_BIT_CMD_WRITE_;
+                cmd_wr <= cmdw_body[7 - i[2:0]];
+              end
+            end
+            `CMDW_STOP_OD,
+            `CMDW_STOP_PP: begin
+              cmd_r <= `MOD_BIT_CMD_STOP_;
+            end
+            `CMDW_DAA_DEV_CHAR: begin
+              cmd_r <= `MOD_BIT_CMD_READ_;
+            end
+            `CMDW_IBI_MDB: begin
+              if (i == 8) begin
+                // T
+                cmd_r <= `MOD_BIT_CMD_READ_;
+              end else begin
+                // MDB
+                cmd_r <= `MOD_BIT_CMD_READ_;
+              end
+            end
+            default: begin
+              st <= `CMDW_NOP;
+            end
+          endcase
+        end
+        SM_TRANSFER: begin
+          if (cmdb_ready) begin
+            sm <= SM_RESOLVE;
+          end
+        end
+        SM_RESOLVE: begin
+          if (rx_valid) begin
+            i <= i + 1;
+            if (i == i_ | cmdw_nacked) begin
+              sm <= SM_GET;
+            end else begin
+              sm <= SM_SETUP;
+            end
+
+            // Condition to end rx stream:
+            // * Check if cmdw changed by peeking next cmd earlier
+            // * Peripheral NACKed
+            if ((i == i_ & st != cmdw_header) | cmdw_nack) begin
+              sdi_last_reg <= 1'b1;
+            end
+
+            if (cmdw_nack) begin
+              st <= sg ? `CMDW_STOP_PP : `CMDW_STOP_OD;
+              sm <= SM_SETUP;
+              cmdw_nacked <= 1'b1;
+            end
+
+            ibi_requested <= 1'b0;
+            case (st)
+              `CMDW_NOP,
+              `CMDW_START : begin
+                ibi_requested <= ibi_requested;
+               end
+              `CMDW_BCAST_7E_W0: begin
+                ibi_da_reg[7-i] <= rx;
+                // Arbitration for IBI request.
+                ibi_requested <= i < 6 & rx === 1'b0 ? 1'b1 : ibi_requested;
+                if (i[2:0] == 7) begin
+                  arbitration_valid <= 1'b1;
+                  if (ibi_enable & ibi_requested & ibi_dev_is_attached & ~ibi_bcr_2) begin
+                    ibi_tick <= 1'b1;
+                  end
+                end
+              end
+              `CMDW_DAA_DEV_CHAR,
+              `CMDW_I2C_RX,
+              `CMDW_MSG_RX: begin
+                if (i == i_) begin
+                  sdi_valid <= 1'b1;
+                end
+                /* T-bit is discarded */
+                sdi[7-i] <= rx;
+              end
+              `CMDW_IBI_MDB: begin
+                if (i[2:0] == 7) begin
+                  ibi_tick <= 1'b1;
+                end
+                ibi_mdb_reg[7-i] <= rx;
+              end
+              default: begin
+              end
+            endcase
+          end
+        end
+      endcase
+    end
+    cmdw_nack_bcast <= cmdw_nack && st == `CMDW_BCAST_7E_W0;
+    cmdw_nack_resp  <= cmdw_nack && st != `CMDW_BCAST_7E_W0;
+  end
+
+  assign cmdw_nack = sm == SM_RESOLVE & rx_valid ?
+                     (st == `CMDW_DYN_ADDR ||
+                      st == `CMDW_TARGET_ADDR_OD ||
+                      st == `CMDW_TARGET_ADDR_PP ||
+                      st == `CMDW_BCAST_7E_W1 ||
+                      st == `CMDW_BCAST_7E_W0 ||
+                      st == `CMDW_I2C_RX) ? (do_ack  & rx !== 1'b0) :
+                     (st == `CMDW_MSG_RX) ? (do_rx_t & rx === 1'b0) : 1'b0 : 1'b0;
+
+  assign cmdw_ready = sm == SM_GET;
+  assign cmdw_header = cmdw[`CMDW_HEADER_WIDTH+8 -: `CMDW_HEADER_WIDTH+1];
+
+  assign ibi_da  = ibi_da_reg [7:1];
+  assign ibi_mdb = ibi_mdb_reg;
+  assign ibi_enable = rmap_ibi_config[0];
+  assign cmdb_valid = sm == SM_TRANSFER;
+  assign cmdb = {cmd_r, sg, cmd_wr};
+
+  assign sdi_last = sdi_valid & sdi_last_reg;
+
+endmodule
diff --git a/adi_library/i3c_controller/i3c_controller_core/i3c_controller_word.vh b/adi_library/i3c_controller/i3c_controller_core/i3c_controller_word.vh
new file mode 100644
index 00000000..d5b99f58
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_core/i3c_controller_word.vh
@@ -0,0 +1,61 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`ifndef WORD_COMMAND_V
+`define WORD_COMMAND_V
+
+`define CMDW_HEADER_WIDTH 4
+
+`define CMDW_NOP                   5'd00
+`define CMDW_START                 5'd01
+`define CMDW_BCAST_7E_W0           5'd02
+`define CMDW_MSG_SR                5'd03
+`define CMDW_TARGET_ADDR_OD        5'd04
+`define CMDW_TARGET_ADDR_PP        5'd05
+`define CMDW_MSG_TX                5'd06
+`define CMDW_MSG_RX                5'd07
+`define CMDW_CCC_OD                5'd08
+`define CMDW_CCC_PP                5'd09
+`define CMDW_STOP_OD               5'd10
+`define CMDW_STOP_PP               5'd11
+`define CMDW_BCAST_7E_W1           5'd12
+`define CMDW_DAA_DEV_CHAR          5'd13
+`define CMDW_DYN_ADDR              5'd14
+`define CMDW_IBI_MDB               5'd15
+`define CMDW_SR                    5'd16
+`define CMDW_I2C_TX                5'd17
+`define CMDW_I2C_RX                5'd18
+
+`endif
diff --git a/adi_library/i3c_controller/i3c_controller_core/xgui/i3c_controller_core_v1_0.tcl b/adi_library/i3c_controller/i3c_controller_core/xgui/i3c_controller_core_v1_0.tcl
new file mode 100644
index 00000000..a3904b6d
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_core/xgui/i3c_controller_core_v1_0.tcl
@@ -0,0 +1,45 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set I3C_Controller_Core [ipgui::add_page $IPINST -name "I3C Controller Core" -display_name {AXI I3C Controller Core}]
+  #Adding Group
+  set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${I3C_Controller_Core}]
+  set MAX_DEVS [ipgui::add_param $IPINST -name "MAX_DEVS" -parent ${General_Configuration}]
+  set_property tooltip {[MAX_DEVS] Maximum number of peripherals in the bus, counting the controller} ${MAX_DEVS}
+  set CLK_MOD [ipgui::add_param $IPINST -name "CLK_MOD" -parent ${General_Configuration} -widget comboBox]
+  set_property tooltip {[CLK_MOD] Adjust clock cycles required to modulate the lane bus bits. Set 8 to achieve 12.5MHz at 100Mhz input clock, and 4 at 50MHz.} ${CLK_MOD}
+
+
+
+}
+
+proc update_PARAM_VALUE.CLK_MOD { PARAM_VALUE.CLK_MOD } {
+	# Procedure called to update CLK_MOD when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.CLK_MOD { PARAM_VALUE.CLK_MOD } {
+	# Procedure called to validate CLK_MOD
+	return true
+}
+
+proc update_PARAM_VALUE.MAX_DEVS { PARAM_VALUE.MAX_DEVS } {
+	# Procedure called to update MAX_DEVS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.MAX_DEVS { PARAM_VALUE.MAX_DEVS } {
+	# Procedure called to validate MAX_DEVS
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.MAX_DEVS { MODELPARAM_VALUE.MAX_DEVS PARAM_VALUE.MAX_DEVS } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.MAX_DEVS}] ${MODELPARAM_VALUE.MAX_DEVS}
+}
+
+proc update_MODELPARAM_VALUE.CLK_MOD { MODELPARAM_VALUE.CLK_MOD PARAM_VALUE.CLK_MOD } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.CLK_MOD}] ${MODELPARAM_VALUE.CLK_MOD}
+}
+
diff --git a/adi_library/i3c_controller/i3c_controller_host_interface/Makefile b/adi_library/i3c_controller/i3c_controller_host_interface/Makefile
new file mode 100644
index 00000000..ea4f41cd
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_host_interface/Makefile
@@ -0,0 +1,44 @@
+####################################################################################
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+LIBRARY_NAME := i3c_controller_host_interface
+
+GENERIC_DEPS += ../../common/ad_mem_dual.v
+GENERIC_DEPS += ../../common/ad_rst.v
+GENERIC_DEPS += ../../common/up_axi.v
+GENERIC_DEPS += i3c_controller_cmd_parser.v
+GENERIC_DEPS += i3c_controller_host_interface.v
+GENERIC_DEPS += i3c_controller_pack.v
+GENERIC_DEPS += i3c_controller_regmap.v
+GENERIC_DEPS += i3c_controller_regmap.vh
+GENERIC_DEPS += i3c_controller_unpack.v
+GENERIC_DEPS += i3c_controller_write_ibi.v
+
+XILINX_DEPS += ../../xilinx/common/ad_rst_constr.xdc
+XILINX_DEPS += i3c_controller_host_interface_constr.ttcl
+XILINX_DEPS += i3c_controller_host_interface_ip.tcl
+
+XILINX_DEPS += ../../i3c_controller/interfaces/i3c_controller_cmdp.xml
+XILINX_DEPS += ../../i3c_controller/interfaces/i3c_controller_cmdp_rtl.xml
+XILINX_DEPS += ../../i3c_controller/interfaces/i3c_controller_rmap.xml
+XILINX_DEPS += ../../i3c_controller/interfaces/i3c_controller_rmap_rtl.xml
+XILINX_DEPS += ../../i3c_controller/interfaces/i3c_controller_sdio.xml
+XILINX_DEPS += ../../i3c_controller/interfaces/i3c_controller_sdio_rtl.xml
+
+XILINX_LIB_DEPS += util_axis_fifo
+XILINX_LIB_DEPS += util_cdc
+
+XILINX_INTERFACE_DEPS += i3c_controller/interfaces
+
+INTEL_DEPS += ../../intel/common/up_rst_constr.sdc
+INTEL_DEPS += ../../util_axis_fifo/util_axis_fifo.v
+INTEL_DEPS += ../../util_axis_fifo/util_axis_fifo_address_generator.v
+INTEL_DEPS += ../../util_cdc/sync_bits.v
+INTEL_DEPS += ../../util_cdc/sync_gray.v
+INTEL_DEPS += i3c_controller_host_interface_constr.sdc
+INTEL_DEPS += i3c_controller_host_interface_hw.tcl
+
+include ../../scripts/library.mk
diff --git a/adi_library/i3c_controller/i3c_controller_host_interface/component.xml b/adi_library/i3c_controller/i3c_controller_host_interface/component.xml
new file mode 100644
index 00000000..8a598eaa
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_host_interface/component.xml
@@ -0,0 +1,1737 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>i3c_controller_host_interface</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>s_axi</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="s_axi"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_bready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_araddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ARREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_arready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rresp</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_rready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>s_axi_aclk</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aclk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_BUSIF">s_axi</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_RESET">s_axi_aresetn</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>s_axi_aresetn</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s_axi_aresetn</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ARESETN.POLARITY" spirit:choiceRef="choice_list_74b5137e">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>sdio</spirit:name>
+      <spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="i3c_controller_sdio" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="i3c_controller_sdio_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sdo_ready</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sdo_ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sdo_valid</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sdo_valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sdo</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sdo</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sdi_ready</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sdi_ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sdi_valid</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sdi_valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sdi_last</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sdi_last</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>sdi</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>sdi</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ibi_ready</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ibi_ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ibi_valid</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ibi_valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>ibi</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>ibi</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>sdio_signal_clock</spirit:name>
+      <spirit:displayName>sdio_signal_clock</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>CLK</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>clk</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.SDIO_SIGNAL_CLOCK.ASSOCIATED_BUSIF">sdio</spirit:value>
+        </spirit:parameter>
+        <spirit:parameter>
+          <spirit:name>ASSOCIATED_RESET</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.SDIO_SIGNAL_CLOCK.ASSOCIATED_RESET">reset_n</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>sdio_signal_reset</spirit:name>
+      <spirit:displayName>sdio_signal_reset</spirit:displayName>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+      <spirit:slave/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>RST</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>reset_n</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:parameters>
+        <spirit:parameter>
+          <spirit:name>POLARITY</spirit:name>
+          <spirit:value spirit:id="BUSIFPARAM_VALUE.SDIO_SIGNAL_RESET.POLARITY">ACTIVE_LOW</spirit:value>
+        </spirit:parameter>
+      </spirit:parameters>
+    </spirit:busInterface>
+    <spirit:busInterface>
+      <spirit:name>offload_sdi</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+      <spirit:master/>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>offload_sdi_ready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>offload_sdi_valid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>TDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>offload_sdi</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+      </spirit:portMaps>
+      <spirit:vendorExtensions>
+        <xilinx:busInterfaceInfo>
+          <xilinx:enablement>
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diff --git a/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_cmd_parser.v b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_cmd_parser.v
new file mode 100644
index 00000000..a9439db5
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_cmd_parser.v
@@ -0,0 +1,237 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+/**
+ * Parse commands.
+ * When the first command indicates a pair command (e.g. CCC), await next
+ * command to complete request (e.g. add CCC ID to parsed CCC command).
+ * If it is a simple command (e.g. private transfer), their is no pair command.
+ * Command receipts (cmdr) are transferred at the end of a transfer, with
+ * updated length field indicating the number of bytes actually transferred,
+ * since the peripheral shall cancel the transfer.
+ */
+
+`timescale 1ns/100ps
+
+module i3c_controller_cmd_parser (
+  input         clk,
+  input         reset_n,
+
+  // Command FIFO
+
+  output        cmd_ready,
+  input         cmd_valid,
+  input  [31:0] cmd,
+
+  input         cmdr_ready,
+  output        cmdr_valid,
+  output [31:0] cmdr,
+
+  // Command parsed
+
+  input         cmdp_ready,
+  output        cmdp_valid,
+  output [30:0] cmdp,
+  input  [2:0]  cmdp_error,
+
+  output        rd_bytes_stop,
+  input  [11:0] rd_bytes_lvl,
+  input         wr_bytes_stop,
+  input  [11:0] wr_bytes_lvl
+);
+
+  // Check bit 3 for any type of NACK (CE2_ERROR + NACK_RESP).
+  // Check bit 4 for unknown address.
+  // CE1_ERROR and CE3_ERROR are not implemented.
+  localparam [3:0] NO_ERROR  = 4'd0;
+  localparam [3:0] CE0_ERROR = 4'd1;
+  localparam [3:0] CE2_ERROR = 4'd4;
+  localparam [3:0] NACK_RESP = 4'd6;
+  localparam [3:0] UDA_ERROR = 4'd8;
+
+  localparam [6:0] CCC_ENTDAA = 'h07;
+
+  localparam [2:0] SM_RECEIVE         = 0;
+  localparam [2:0] SM_XFER_WAIT       = 1;
+  localparam [2:0] SM_XFER_WAIT_READY = 2;
+  localparam [2:0] SM_CCC_WAIT        = 3;
+  localparam [2:0] SM_PRE_RECEIPT     = 4;
+  localparam [2:0] SM_RECEIPT         = 5;
+
+  reg  [31:0] cmdr1;
+  reg  [7:0]  cmdr2;
+  reg  [3:0]  cmdr_error;
+  reg  [7:0]  cmdr_sync;
+
+  reg         error_nack_bcast_reg;
+  reg         error_nack_resp_reg;
+  reg         error_unknown_da_reg;
+
+  reg  [2:0]  sm;
+
+  reg         wr_bytes_stop_reg;
+  reg [11:0]  wr_bytes_lvl_reg;
+
+  wire        cmdp_rnw;
+  wire [11:0] cmdp_buffer_len;
+  wire        cmdp_ccc;
+  wire [6:0]  cmdp_ccc_id;
+  wire        error_nack_bcast;
+  wire        error_unknown_da;
+  wire        error_nack_resp;
+
+  wire [11:0] cmdr1_len;
+
+  always @(posedge clk) begin
+    if (!reset_n) begin
+      sm  <= SM_RECEIVE;
+      cmdr_error <= NO_ERROR;
+      cmdr_sync  <= 8'd0;
+    end else begin
+      case (sm)
+        SM_RECEIVE: begin
+          cmdr_error <= NO_ERROR;
+          cmdr2 <= 8'd0;
+          if (cmd_valid) begin
+            cmdr1 <= cmd;
+            /* cmd[22] is cmdp_ccc */
+            sm <= cmd[22] ? SM_CCC_WAIT : SM_XFER_WAIT;
+          end else begin
+            sm <= SM_RECEIVE;
+          end
+          error_nack_bcast_reg <= 1'b0;
+          error_unknown_da_reg <= 1'b0;
+          error_nack_resp_reg  <= 1'b0;
+        end
+        SM_XFER_WAIT: begin
+          sm <= cmdp_ready ? SM_XFER_WAIT_READY : sm;
+          end
+        SM_XFER_WAIT_READY: begin
+          if (cmdp_ready) begin
+            sm <= SM_PRE_RECEIPT;
+          end
+
+          if (error_nack_bcast) begin
+            error_nack_bcast_reg <= error_nack_bcast;
+          end
+          if (error_unknown_da) begin
+            error_unknown_da_reg <= error_unknown_da;
+          end
+          if (error_nack_resp) begin
+            error_nack_resp_reg <= error_nack_resp;
+          end
+        end
+        SM_CCC_WAIT: begin
+          cmdr2 <= cmd[7:0];
+          if (cmd_valid) begin
+            sm <= SM_XFER_WAIT;
+          end
+        end
+        SM_PRE_RECEIPT: begin
+          // CE1_ERROR and CE3_ERROR not implemented.
+          if (cmdp_ccc & |wr_bytes_lvl) begin
+            cmdr_error <= CE0_ERROR;
+          end else if (error_nack_bcast_reg) begin
+            cmdr_error <= CE2_ERROR;
+          end else if (error_unknown_da_reg) begin
+            cmdr_error <= UDA_ERROR;
+          end else if (error_nack_resp_reg) begin
+            cmdr_error <= NACK_RESP;
+          end
+          // Ensure all receipt content is ok
+          sm <= SM_RECEIPT;
+        end
+        SM_RECEIPT: begin
+          if (cmdr_ready) begin
+            sm <= SM_RECEIVE;
+            cmdr_sync <= cmdr_sync + 1;
+          end
+        end
+        default: begin
+          sm <= SM_RECEIVE;
+        end
+      endcase
+    end
+  end
+
+  // Lock on last sdi_bytes_lvl for the cmd
+  // Since level increment on get state and is cleared by last on put phase,
+  // delay i clock cycle.
+  // Clear when cmr is read, since some RX transfer might get NACKed at
+  // 0 bytes (no sdi_last).
+  always @(posedge clk) begin
+    wr_bytes_stop_reg <= wr_bytes_stop;
+    if (cmdr_valid & cmdr_ready) begin
+      wr_bytes_lvl_reg <= 0;
+    end else if (wr_bytes_stop_reg) begin
+      wr_bytes_lvl_reg <= wr_bytes_lvl;
+    end
+  end
+
+  assign cmd_ready  = (sm == SM_RECEIVE || sm == SM_CCC_WAIT) & reset_n;
+  assign cmdp_valid = (sm == SM_XFER_WAIT & reset_n);
+
+  assign cmdr = {8'd0, cmdr_error, cmdr1_len, cmdr_sync};
+  assign cmdr_valid = sm == SM_RECEIPT;
+
+  // For read bytes (write to peripheral), it is either all transferred or none,
+  // since the peripheral can only reject during the address ACK.
+  // For write bytes (read from peripheral), the peripheral shall cancel
+  // before finishing the transfer.
+  assign cmdr1_len = cmdp_rnw ?
+                       wr_bytes_lvl_reg :
+                       (error_nack_bcast_reg | error_nack_resp_reg ?
+                         12'd0 : cmdp_buffer_len
+                       );
+
+  assign rd_bytes_stop = (cmdp_buffer_len == rd_bytes_lvl) & |rd_bytes_lvl;
+
+  assign cmdp_rnw        = cmdr1[0];
+  assign cmdp_ccc        = cmdr1[22];
+  // The Linux implementation sets ENTDAA buffer length to 0,
+  // but we need with 1 to contiguously fetch the DAs.
+  assign cmdp_buffer_len = cmdp_ccc_id == CCC_ENTDAA ? 1 : cmdr1[19:08];
+  assign cmdp_ccc_id     = cmdr2[6:0];
+
+  assign error_nack_bcast = cmdp_error[0];
+  assign error_unknown_da = cmdp_error[1];
+  assign error_nack_resp  = cmdp_error[2];
+
+  // Remove reserved bits.
+  assign cmdp = {
+    cmdr2[7:0],
+    cmdr1[22:0]
+  };
+
+endmodule
diff --git a/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface.v b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface.v
new file mode 100644
index 00000000..4f76f902
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface.v
@@ -0,0 +1,253 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module i3c_controller_host_interface #(
+  parameter ID = 0,
+  parameter ASYNC_CLK = 0,
+  parameter OFFLOAD = 1
+) (
+  input  clk,
+  output reset_n,
+
+  // Slave AXI interface
+
+  input         s_axi_aclk,
+  input         s_axi_aresetn,
+  input         s_axi_awvalid,
+  input  [15:0] s_axi_awaddr,
+  output        s_axi_awready,
+  input   [2:0] s_axi_awprot,
+  input         s_axi_wvalid,
+  input  [31:0] s_axi_wdata,
+  input  [ 3:0] s_axi_wstrb,
+  output        s_axi_wready,
+  output        s_axi_bvalid,
+  output [ 1:0] s_axi_bresp,
+  input         s_axi_bready,
+  input         s_axi_arvalid,
+  input  [15:0] s_axi_araddr,
+  output        s_axi_arready,
+  input   [2:0] s_axi_arprot,
+  output        s_axi_rvalid,
+  input         s_axi_rready,
+  output [ 1:0] s_axi_rresp,
+  output [31:0] s_axi_rdata,
+
+  output irq,
+  input  offload_trigger,
+
+  // Command parsed
+
+  input         cmdp_ready,
+  output        cmdp_valid,
+  output [30:0] cmdp,
+  input  [2:0]  cmdp_error,
+  input         cmdp_nop,
+  input         cmdp_daa_trigger,
+
+  // Byte stream
+
+  input  sdo_ready,
+  output sdo_valid,
+  output [7:0] sdo,
+
+  output sdi_ready,
+  input  sdi_valid,
+  input  sdi_last,
+  input  [7:0] sdi,
+
+  output ibi_ready,
+  input  ibi_valid,
+  input  [14:0] ibi,
+
+  input  offload_sdi_ready,
+  output offload_sdi_valid,
+  output [31:0] offload_sdi,
+
+  // uP accessible info
+
+  output [1:0] rmap_ibi_config,
+  output [1:0] rmap_pp_sg,
+  input  [6:0] rmap_dev_char_addr,
+  output [3:0] rmap_dev_char_data
+);
+
+  wire rd_bytes_stop;
+  wire [11:0] rd_bytes_lvl;
+  wire [11:0] wr_bytes_lvl;
+
+  wire cmd_ready;
+  wire cmd_valid;
+  wire [31:0] cmd;
+
+  wire cmdr_ready;
+  wire cmdr_valid;
+  wire [31:0] cmdr;
+
+  wire sdo_ready_w;
+  wire sdo_valid_w;
+  wire [31:0] sdo_w;
+
+  wire sdi_ready_w;
+  wire sdi_valid_w;
+  wire [31:0] sdi_w;
+
+  wire ibi_ready_w;
+  wire ibi_valid_w;
+  wire [31:0] ibi_w;
+
+  wire clk_w;
+
+  generate if (ASYNC_CLK) begin
+    assign clk_w = clk;
+  end else begin
+    assign clk_w = s_axi_aclk;
+  end
+  endgenerate
+
+  i3c_controller_regmap #(
+    .ID(ID),
+    .OFFLOAD(OFFLOAD),
+    .ASYNC_CLK(ASYNC_CLK)
+  ) i_i3c_controller_regmap (
+    .s_axi_aclk(s_axi_aclk),
+    .s_axi_aresetn(s_axi_aresetn),
+    .s_axi_awvalid(s_axi_awvalid),
+    .s_axi_awaddr(s_axi_awaddr),
+    .s_axi_awready(s_axi_awready),
+    .s_axi_awprot(s_axi_awprot),
+    .s_axi_wvalid(s_axi_wvalid),
+    .s_axi_wdata(s_axi_wdata),
+    .s_axi_wstrb(s_axi_wstrb),
+    .s_axi_wready(s_axi_wready),
+    .s_axi_bvalid(s_axi_bvalid),
+    .s_axi_bresp(s_axi_bresp),
+    .s_axi_bready(s_axi_bready),
+    .s_axi_arvalid(s_axi_arvalid),
+    .s_axi_araddr(s_axi_araddr),
+    .s_axi_arready(s_axi_arready),
+    .s_axi_arprot(s_axi_arprot),
+    .s_axi_rvalid(s_axi_rvalid),
+    .s_axi_rready(s_axi_rready),
+    .s_axi_rresp(s_axi_rresp),
+    .s_axi_rdata(s_axi_rdata),
+    .irq(irq),
+    .clk(clk),
+    .a_reset_n(reset_n),
+    .cmd_nop(cmdp_nop),
+    .cmd_ready(cmd_ready),
+    .cmd_valid(cmd_valid),
+    .cmd(cmd),
+    .cmdr_ready(cmdr_ready),
+    .cmdr_valid(cmdr_valid),
+    .cmdr(cmdr),
+    .sdo_ready(sdo_ready_w),
+    .sdo_valid(sdo_valid_w),
+    .sdo(sdo_w),
+    .sdi_ready(sdi_ready_w),
+    .sdi_valid(sdi_valid_w),
+    .sdi(sdi_w),
+    .offload_sdi_ready(offload_sdi_ready),
+    .offload_sdi_valid(offload_sdi_valid),
+    .offload_sdi(offload_sdi),
+    .ibi_ready(ibi_ready_w),
+    .ibi_valid(ibi_valid_w),
+    .ibi(ibi_w),
+    .daa_trigger(cmdp_daa_trigger),
+    .offload_trigger(offload_trigger),
+    .rmap_ibi_config(rmap_ibi_config),
+    .rmap_pp_sg(rmap_pp_sg),
+    .rmap_dev_char_addr(rmap_dev_char_addr),
+    .rmap_dev_char_data(rmap_dev_char_data));
+
+  i3c_controller_unpack
+  i_i3c_controller_unpack (
+    .clk(clk_w),
+    .reset_n(reset_n),
+    .stop(rd_bytes_stop),
+    .u32_ready(sdo_ready_w),
+    .u32_valid(sdo_valid_w),
+    .u32(sdo_w),
+    .u8_lvl(rd_bytes_lvl),
+    .u8_ready(sdo_ready),
+    .u8_valid(sdo_valid),
+    .u8(sdo));
+
+  i3c_controller_pack
+  i_i3c_controller_pack (
+    .clk(clk_w),
+    .reset_n(reset_n),
+    .u32_ready(sdi_ready_w),
+    .u32_valid(sdi_valid_w),
+    .u32(sdi_w),
+    .u8_lvl(wr_bytes_lvl),
+    .u8_ready(sdi_ready),
+    .u8_valid(sdi_valid),
+    .u8_last(sdi_last),
+    .u8(sdi));
+
+  i3c_controller_write_ibi
+  i_i3c_controller_write_ibi (
+    .clk(clk_w),
+    .reset_n(reset_n),
+    .out_ready(ibi_ready_w),
+    .out_valid(ibi_valid_w),
+    .out(ibi_w),
+    .in_ready(ibi_ready),
+    .in_valid(ibi_valid),
+    .in(ibi));
+
+  i3c_controller_cmd_parser
+  i_i3c_controller_cmd_parser (
+    .clk(clk_w),
+    .reset_n(reset_n),
+    .cmd_ready(cmd_ready),
+    .cmd_valid(cmd_valid),
+    .cmd(cmd),
+    .cmdr_ready(cmdr_ready),
+    .cmdr_valid(cmdr_valid),
+    .cmdr(cmdr),
+    .cmdp_valid(cmdp_valid),
+    .cmdp_ready(cmdp_ready),
+    .cmdp(cmdp),
+    .cmdp_error(cmdp_error),
+    .rd_bytes_stop(rd_bytes_stop),
+    .rd_bytes_lvl(rd_bytes_lvl),
+    .wr_bytes_stop(sdi_last),
+    .wr_bytes_lvl(wr_bytes_lvl));
+
+endmodule
diff --git a/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface.xpr b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface.xpr
new file mode 100644
index 00000000..f1933f00
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface.xpr
@@ -0,0 +1,468 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
+<!--                                                                         -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
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+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
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+    <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
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+    <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
+    <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
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+    <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
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+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
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+    <MsgAttr Name="StringsToMatch" Val="HDPYFinalizeIO"/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="WARNING"/>
+    <MsgAttr Name="Id" Val="Place 30-73"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="11"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+    <MsgAttr Name="StringsToMatch" Val="axi_spi"/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="WARNING"/>
+    <MsgAttr Name="Id" Val=""/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="12"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+    <MsgAttr Name="StringsToMatch" Val="PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY"/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="WARNING"/>
+    <MsgAttr Name="Id" Val="BD 41-1343"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="2"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="WARNING"/>
+    <MsgAttr Name="Id" Val="BD 41-1306"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="3"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="ERROR"/>
+    <MsgAttr Name="Id" Val="BD 41-1276"/>
+    <MsgAttr Name="Severity" Val="CRITICAL WARNING"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="4"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="INFO"/>
+    <MsgAttr Name="Id" Val="IP_Flow 19-3656"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="5"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="INFO"/>
+    <MsgAttr Name="Id" Val="IP_Flow 19-4623"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="6"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="INFO"/>
+    <MsgAttr Name="Id" Val="IP_Flow 19-459"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="7"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="INFO"/>
+    <MsgAttr Name="Id" Val="Synth 8-3331"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="8"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <MsgRule>
+    <MsgAttr Name="RuleType" Val="1"/>
+    <MsgAttr Name="Limit" Val="-1"/>
+    <MsgAttr Name="NewSeverity" Val="WARNING"/>
+    <MsgAttr Name="Id" Val="Synth 8-2490"/>
+    <MsgAttr Name="Severity" Val="ANY"/>
+    <MsgAttr Name="ShowRule" Val="1"/>
+    <MsgAttr Name="RuleSource" Val="2"/>
+    <MsgAttr Name="StringIsRegExp" Val="0"/>
+    <MsgAttr Name="RuleId" Val="9"/>
+    <MsgAttr Name="Note" Val=""/>
+    <MsgAttr Name="Author" Val=""/>
+    <MsgAttr Name="CreatedTimestamp" Val=""/>
+  </MsgRule>
+  <Board/>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>
diff --git a/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface_constr.sdc b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface_constr.sdc
new file mode 100644
index 00000000..428cb5c7
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface_constr.sdc
@@ -0,0 +1,4 @@
+###############################################################################
+## Copyright (C) 2020-2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
diff --git a/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface_constr.ttcl b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface_constr.ttcl
new file mode 100644
index 00000000..059e963a
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface_constr.ttcl
@@ -0,0 +1,26 @@
+###############################################################################
+## Copyright (C) 2014 Analog Devices, Inc. All rights reserved.
+# SPDX short identifier: ADIBSD
+###############################################################################
+
+<: set ComponentName [getComponentNameString] :>
+<: setOutputDirectory "./" :>
+<: setFileName [ttcl_add $ComponentName "_constr"] :>
+<: setFileExtension ".xdc" :>
+<: setFileProcessingOrder late :>
+<: set async_clk [getBooleanValue "ASYNC_CLK"] :>
+
+<: if { $async_clk } { :>
+
+set_property ASYNC_REG TRUE \
+  [get_cells -quiet -hierarchical *cdc_sync_stage1_reg*] \
+  [get_cells -quiet -hierarchical *cdc_sync_stage2_reg*]
+
+set_false_path -quiet \
+ -from [get_cells -quiet -hierarchical -filter {NAME =~ *i_address_gray/*cdc_sync_stage0_reg* && IS_SEQUENTIAL}] \
+ -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_address_gray/*cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
+
+set_false_path -quiet \
+  -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_fifo_status/cdc_sync_stage1_reg* && IS_SEQUENTIAL}]
+
+<: } :>
diff --git a/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface_hw.tcl b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface_hw.tcl
new file mode 100644
index 00000000..0d5eddfa
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface_hw.tcl
@@ -0,0 +1,137 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+package require qsys 14.0
+source ../../../scripts/adi_env.tcl
+source ../../scripts/adi_ip_intel.tcl
+
+ad_ip_create i3c_controller_host_interface {I3C Controller Host Interface}
+set_module_property ELABORATION_CALLBACK p_elaboration
+ad_ip_files i3c_controller_host_interface [list \
+  $ad_hdl_dir/library/util_axis_fifo/util_axis_fifo.v \
+  $ad_hdl_dir/library/util_axis_fifo/util_axis_fifo_address_generator.v \
+  $ad_hdl_dir/library/util_cdc/sync_bits.v \
+  $ad_hdl_dir/library/util_cdc/sync_gray.v \
+  $ad_hdl_dir/library/common/ad_mem_dual.v \
+  $ad_hdl_dir/library/common/ad_rst.v \
+  $ad_hdl_dir/library/common/up_axi.v \
+  $ad_hdl_dir/library/intel/common/up_rst_constr.sdc \
+  i3c_controller_host_interface_constr.sdc \
+  i3c_controller_host_interface.v \
+  i3c_controller_regmap.v \
+  i3c_controller_regmap.vh \
+  i3c_controller_cmd_parser.v \
+  i3c_controller_pack.v \
+  i3c_controller_unpack.v \
+  i3c_controller_write_ibi.v \
+]
+
+# Parameters
+
+ad_ip_parameter ID INTEGER 0
+ad_ip_parameter ASYNC_CLK INTEGER 0
+ad_ip_parameter OFFLOAD INTEGER 0
+
+proc p_elaboration {} {
+
+  set disabled_intfs {}
+
+  # Read parameters
+
+  set id [get_parameter_value "ID"]
+  set async_clk [get_parameter_value "ASYNC_CLK"]
+  set offload [get_parameter_value "OFFLOAD"]
+
+  # Interrupt
+
+  add_interface interrupt_sender interrupt end
+  add_interface_port interrupt_sender irq irq Output 1
+
+  # AXI Memory Mapped interface
+
+  ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 16
+
+  set_interface_property interrupt_sender associatedAddressablePoint s_axi
+  set_interface_property interrupt_sender associatedClock s_axi_clock
+  set_interface_property interrupt_sender associatedReset s_axi_reset
+  set_interface_property interrupt_sender ENABLED true
+
+  ad_interface clock clk input 1
+
+  if {!($async_clk)} {
+    set if_clk s_axi_clock
+  } else {
+    set if_clk if_clk
+  }
+
+  ad_interface reset reset_n output 1 $if_clk
+
+  ad_interface signal offload_trigger input 1 if_pwm
+
+  add_interface sdo axi4stream start
+  add_interface_port sdo sdo_ready tready input  1
+  add_interface_port sdo sdo_valid tvalid output 1
+  add_interface_port sdo sdo       tdata  output 8
+
+  set_interface_property sdo associatedClock $if_clk
+  set_interface_property sdo associatedReset if_reset_n
+
+  add_interface sdi axi4stream end
+  add_interface_port sdi sdi_ready tready output 1
+  add_interface_port sdi sdi_valid tvalid input  1
+  add_interface_port sdi sdi_last  tlast  input  1
+  add_interface_port sdi sdi       tdata  input  8
+
+  set_interface_property sdi associatedClock $if_clk
+  set_interface_property sdi associatedReset if_reset_n
+
+  add_interface ibi axi4stream end
+  add_interface_port ibi ibi_ready tready output  1
+  add_interface_port ibi ibi_valid tvalid input   1
+  add_interface_port ibi ibi       tdata  input  15
+
+  set_interface_property ibi associatedClock $if_clk
+  set_interface_property ibi associatedReset if_reset_n
+
+  add_interface offload_sdi axi4stream start
+  add_interface_port offload_sdi offload_sdi_ready tready input   1
+  add_interface_port offload_sdi offload_sdi_valid tvalid output  1
+  add_interface_port offload_sdi offload_sdi       tdata  output 32
+
+  set_interface_property offload_sdi associatedClock $if_clk
+  set_interface_property offload_sdi associatedReset if_reset_n
+
+  add_interface cmdp conduit start
+  add_interface_port cmdp cmdp_ready       cready      input   1
+  add_interface_port cmdp cmdp_valid       cvalid      output  1
+  add_interface_port cmdp cmdp             cdata       output 31
+  add_interface_port cmdp cmdp_error       error       input   3
+  add_interface_port cmdp cmdp_nop         nop         input   1
+  add_interface_port cmdp cmdp_daa_trigger daa_trigger input   1
+
+  set_interface_property cmdp associatedClock $if_clk
+  set_interface_property cmdp associatedReset if_reset_n
+
+  add_interface rmap conduit start
+  add_interface_port rmap rmap_ibi_config    ibi_config    output 2
+  add_interface_port rmap rmap_pp_sg         pp_sg         output 2
+  add_interface_port rmap rmap_dev_char_addr dev_char_addr input  7
+  add_interface_port rmap rmap_dev_char_data dev_char_data output 4
+
+  set_interface_property rmap associatedClock $if_clk
+  set_interface_property rmap associatedReset if_reset_n
+
+  if {!($offload)} {
+    lappend disabled_intfs offload_sdi if_offload_trigger
+  }
+
+  if {!($async_clk)} {
+    lappend disabled_intfs if_clk
+  }
+
+  foreach interface $disabled_intfs {
+    set_interface_property $interface ENABLED false
+  }
+}
diff --git a/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface_ip.tcl b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface_ip.tcl
new file mode 100644
index 00000000..ee31f9f4
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_host_interface_ip.tcl
@@ -0,0 +1,156 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source ../../../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
+
+global VIVADO_IP_LIBRARY
+
+adi_ip_create i3c_controller_host_interface
+adi_ip_files i3c_controller_host_interface [list \
+  "$ad_hdl_dir/library/common/up_axi.v" \
+  "$ad_hdl_dir/library/common/ad_rst.v" \
+  "$ad_hdl_dir/library/common/ad_mem_dual.v" \
+  "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
+  "i3c_controller_host_interface_constr.ttcl" \
+  "i3c_controller_host_interface.v" \
+  "i3c_controller_regmap.v" \
+  "i3c_controller_regmap.vh" \
+  "i3c_controller_cmd_parser.v" \
+  "i3c_controller_pack.v" \
+  "i3c_controller_unpack.v" \
+  "i3c_controller_write_ibi.v" \
+]
+
+adi_ip_properties i3c_controller_host_interface
+adi_ip_ttcl i3c_controller_host_interface "i3c_controller_host_interface_constr.ttcl"
+
+adi_ip_add_core_dependencies [list \
+  analog.com:$VIVADO_IP_LIBRARY:util_axis_fifo:1.0 \
+  analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \
+]
+
+set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/i3c_controller/host_interface} [ipx::current_core]
+
+## Interface definitions
+
+adi_add_bus "sdio" "master" \
+  "analog.com:interface:i3c_controller_sdio_rtl:1.0" \
+  "analog.com:interface:i3c_controller_sdio:1.0" \
+  {
+    {"sdo_ready" "sdo_ready"} \
+    {"sdo_valid" "sdo_valid"} \
+    {"sdo"       "sdo"} \
+    {"sdi_ready" "sdi_ready"} \
+    {"sdi_valid" "sdi_valid"} \
+    {"sdi_last"  "sdi_last"} \
+    {"sdi"       "sdi"} \
+    {"ibi_ready" "ibi_ready"} \
+    {"ibi_valid" "ibi_valid"} \
+    {"ibi"       "ibi"} \
+  }
+adi_add_bus_clock "clk" "sdio" "reset_n"
+
+adi_add_bus "offload_sdi" "master" \
+  "xilinx.com:interface:axis_rtl:1.0" \
+  "xilinx.com:interface:axis:1.0" \
+  {
+    {"offload_sdi_ready"  "TREADY"} \
+    {"offload_sdi_valid"  "TVALID"} \
+    {"offload_sdi"        "TDATA"} \
+  }
+adi_add_bus_clock "clk" "offload_sdi" "reset_n" "master"
+
+adi_add_bus "cmdp" "master" \
+  "analog.com:interface:i3c_controller_cmdp_rtl:1.0" \
+  "analog.com:interface:i3c_controller_cmdp:1.0" \
+  {
+    {"cmdp_valid"       "cmdp_valid"} \
+    {"cmdp_ready"       "cmdp_ready"} \
+    {"cmdp"             "cmdp"} \
+    {"cmdp_error"       "cmdp_error"} \
+    {"cmdp_nop"         "cmdp_nop"} \
+    {"cmdp_daa_trigger" "cmdp_daa_trigger"} \
+  }
+adi_add_bus_clock "clk" "cmdp" "reset_n"
+
+adi_add_bus "rmap" "master" \
+  "analog.com:interface:i3c_controller_rmap_rtl:1.0" \
+  "analog.com:interface:i3c_controller_rmap:1.0" \
+  {
+    {"rmap_ibi_config"    "rmap_ibi_config"} \
+    {"rmap_pp_sg"         "rmap_pp_sg"} \
+    {"rmap_dev_char_addr" "rmap_dev_char_addr"} \
+    {"rmap_dev_char_data" "rmap_dev_char_data"} \
+  }
+adi_add_bus_clock "clk" "rmap" "reset_n" "master"
+
+adi_set_ports_dependency "clk" \
+      "(spirit:decode(id('MODELPARAM_VALUE.ASYNC_CLK')) = 1)"
+
+adi_set_bus_dependency "offload_sdi" "offload_sdi" \
+      "(spirit:decode(id('MODELPARAM_VALUE.OFFLOAD')) = 1)"
+adi_set_ports_dependency "offload_trigger" \
+      "(spirit:decode(id('MODELPARAM_VALUE.OFFLOAD')) = 1)" 0
+
+set cc [ipx::current_core]
+
+## ID
+set_property -dict [list \
+  "value_validation_type" "range_long" \
+  "value_validation_range_minimum" "0" \
+  "value_validation_range_maximum" "255" \
+ ] \
+ [ipx::get_user_parameters ID -of_objects $cc]
+
+foreach {k v} { \
+        "ASYNC_CLK" "false" \
+        "OFFLOAD" "false" \
+	} { \
+	set_property -dict [list \
+			"value_format" "bool" \
+			"value" $v \
+		] \
+		[ipx::get_user_parameters $k -of_objects $cc]
+	set_property -dict [list \
+			"value_format" "bool" \
+			"value" $v \
+		] \
+		[ipx::get_hdl_parameters $k -of_objects $cc]
+}
+
+## Customize IP Layout
+## Remove the automatically generated GUI page
+ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc]
+ipx::save_core [ipx::current_core]
+
+## Create general configuration page
+ipgui::add_page -name {I3C Controller Host Interface} -component [ipx::current_core] -display_name {AXI I3C Controller Host Interface}
+set page0 [ipgui::get_pagespec -name "I3C Controller Host Interface" -component $cc]
+
+set general_group [ipgui::add_group -name "General Configuration" -component $cc \
+    -parent $page0 -display_name "General Configuration" ]
+
+ipgui::add_param -name "ID" -component $cc -parent $general_group
+set_property -dict [list \
+  "display_name" "Core ID" \
+  "tooltip" "\[ID\] Core instance ID" \
+] [ipgui::get_guiparamspec -name "ID" -component $cc]
+
+ipgui::add_param -name "ASYNC_CLK" -component $cc -parent $general_group
+set_property -dict [list \
+  "display_name" "Asynchronous core clock" \
+  "tooltip" "\[ASYNC_CLK\] Define the relationship between the core clock and the memory mapped interface clock" \
+] [ipgui::get_guiparamspec -name "ASYNC_CLK" -component $cc]
+
+ipgui::add_param -name "OFFLOAD" -component $cc -parent $general_group
+set_property -dict [list \
+  "display_name" "Offload engine" \
+  "tooltip" "\[OFFLOAD\] Allows to offload output data to a external receiver, like a DMA" \
+] [ipgui::get_guiparamspec -name "OFFLOAD" -component $cc]
+
+## Create and save the XGUI file
+ipx::create_xgui_files $cc
+ipx::save_core $cc
diff --git a/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_pack.v b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_pack.v
new file mode 100644
index 00000000..63b9bddd
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_pack.v
@@ -0,0 +1,111 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+/**
+ * Packs u8 stream into u32.
+ * Restrictions:
+ * At partial payload, e.g. 3-bytes, the remaining byte value is unknown.
+ */
+
+`timescale 1ns/100ps
+
+module i3c_controller_pack (
+  input         clk,
+  input         reset_n,
+
+  input         u32_ready,
+  output        u32_valid,
+  output [31:0] u32,
+
+  output [11:0] u8_lvl,
+
+  output       u8_ready,
+  input        u8_valid,
+  input        u8_last,
+  input  [7:0] u8
+);
+
+  localparam [0:0] SM_GET = 0;
+  localparam [0:0] SM_PUT = 1;
+
+  reg [0:0]  sm;
+  reg [1:0]  c;
+  reg [7:0]  u32_reg [3:0];
+  reg [11:0] u8_lvl_reg;
+  reg        u8_last_reg;
+
+  always @(posedge clk) begin
+    if (!reset_n) begin
+      sm <= SM_GET;
+      c <= 2'b00;
+      u8_last_reg <= 1'b0;
+      u8_lvl_reg <= 0;
+    end else begin
+      case (sm)
+        SM_GET: begin
+          u8_last_reg <= u8_last;
+          if (u8_valid) begin // tick
+            u32_reg[3-c] <= u8;
+            u8_lvl_reg <= u8_lvl_reg + 1;
+            c <= c + 1;
+            if (c == 2'b11 | u8_last) begin
+              c <= 2'b00;
+              sm <= SM_PUT;
+            end
+          end
+        end
+        SM_PUT: begin
+          if (u32_ready) begin
+            sm <= SM_GET;
+            if (u8_last_reg) begin
+              u8_lvl_reg <= 0;
+            end
+          end
+        end
+      endcase
+    end
+  end
+
+  assign u8_ready = sm == SM_GET & reset_n;
+  assign u32_valid = sm == SM_PUT;
+  assign u8_lvl = u8_lvl_reg;
+
+  genvar i;
+  generate
+    for (i=0; i<4; i=i+1) begin: gen_u32
+      assign u32[8*i+7:8*i] = u32_reg[3-i];
+    end
+  endgenerate
+
+endmodule
diff --git a/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_regmap.v b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_regmap.v
new file mode 100644
index 00000000..c768290d
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_regmap.v
@@ -0,0 +1,747 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+`include "i3c_controller_regmap.vh"
+
+`define ADDRESS_WIDTH 8
+
+module i3c_controller_regmap #(
+  parameter ID = 0,
+  parameter ASYNC_CLK = 0,
+  parameter OFFLOAD = 1,
+  parameter DATA_WIDTH = 32
+) (
+
+  // Slave AXI interface
+
+  input         s_axi_aclk,
+  input         s_axi_aresetn,
+  input         s_axi_awvalid,
+  input  [15:0] s_axi_awaddr,
+  output        s_axi_awready,
+  input   [2:0] s_axi_awprot,
+  input         s_axi_wvalid,
+  input  [31:0] s_axi_wdata,
+  input  [ 3:0] s_axi_wstrb,
+  output        s_axi_wready,
+  output        s_axi_bvalid,
+  output [ 1:0] s_axi_bresp,
+  input         s_axi_bready,
+  input         s_axi_arvalid,
+  input  [15:0] s_axi_araddr,
+  output        s_axi_arready,
+  input   [2:0] s_axi_arprot,
+  output        s_axi_rvalid,
+  input         s_axi_rready,
+  output [ 1:0] s_axi_rresp,
+  output [31:0] s_axi_rdata,
+
+  output reg irq,
+
+  // Core basic signals
+
+  input  clk,
+  output a_reset_n,
+
+  // I3C control signals
+
+  input  cmd_ready,
+  input  cmd_nop,
+  output cmd_valid,
+  output [DATA_WIDTH-1:0] cmd,
+
+  output cmdr_ready,
+  input  cmdr_valid,
+  input  [DATA_WIDTH-1:0] cmdr,
+
+  input  sdo_ready,
+  output sdo_valid,
+  output [DATA_WIDTH-1:0] sdo,
+
+  output sdi_ready,
+  input  sdi_valid,
+  input  [DATA_WIDTH-1:0] sdi,
+
+  input  offload_sdi_ready,
+  output offload_sdi_valid,
+  output [DATA_WIDTH-1:0] offload_sdi,
+
+  output ibi_ready,
+  input  ibi_valid,
+  input  [DATA_WIDTH-1:0] ibi,
+
+  input  daa_trigger,
+  input  offload_trigger,
+
+  // uP accessible info
+
+  output reg [1:0] rmap_ibi_config,
+  output     [1:0] rmap_pp_sg,
+  input      [6:0] rmap_dev_char_addr,
+  output     [3:0] rmap_dev_char_data
+);
+
+  localparam PCORE_VERSION = 'h00000100;
+
+  reg [31:0] up_scratch  = 32'h00; // Scratch register
+  reg        up_sw_reset = 1'b1;
+  reg [31:0] up_rdata_ff = 32'd0;
+  reg        up_wack_ff  = 1'b0;
+  reg        up_rack_ff  = 1'b0;
+
+  // Holds DAA trigger High until sdo_fifo_empty goes Low,
+  // meaning DA got written.
+  reg        daa_trigger_lock;
+
+  reg        daa_pending;
+  reg        cmdr_pending;
+  reg        ibi_pending;
+
+  reg  [`I3C_REGMAP_IRQ_WIDTH:0] up_irq_mask = 8'h0;
+  reg  [6:0] ops;
+  reg  [6:0] ops_candidate;
+  reg  [6:0] dev_char_addr_reg;
+
+  // CMD FIFO
+
+  wire [`ADDRESS_WIDTH-1:0] cmd_fifo_room;
+  wire cmd_fifo_almost_empty;
+  wire up_cmd_fifo_almost_empty;
+
+  wire [DATA_WIDTH-1:0] cmd_fifo_data;
+  wire cmd_fifo_ready;
+  wire cmd_fifo_valid;
+
+  // CMDR FIFO
+
+  wire cmdr_fifo_data_msb_s;
+  wire [`ADDRESS_WIDTH-1:0] cmdr_fifo_level;
+  wire cmdr_fifo_almost_full;
+  wire up_cmdr_fifo_almost_full;
+
+  wire [DATA_WIDTH-1:0] cmdr_fifo_data;
+  wire cmdr_fifo_ready;
+  wire cmdr_fifo_valid;
+  wire cmdr_fifo_empty;
+
+  // SDO FIFO
+
+  wire [`ADDRESS_WIDTH-1:0] sdo_fifo_room;
+  wire sdo_fifo_almost_empty;
+  wire up_sdo_fifo_almost_empty;
+
+  wire [DATA_WIDTH-1:0] sdo_fifo_data;
+  wire sdo_fifo_ready;
+  wire sdo_fifo_valid;
+  wire sdo_fifo_empty;
+
+  // SDI FIFO
+
+  wire sdi_fifo_data_msb_s;
+  wire [`ADDRESS_WIDTH-1:0] sdi_fifo_level;
+  wire sdi_fifo_almost_full;
+  wire up_sdi_fifo_almost_full;
+
+  wire [DATA_WIDTH-1:0] sdi_fifo_data;
+  wire sdi_fifo_ready;
+  wire sdi_fifo_valid;
+  wire sdi_fifo_empty;
+
+  // IBI FIFO
+
+  wire ibi_fifo_data_msb_s;
+  wire [`ADDRESS_WIDTH-1:0] ibi_fifo_level;
+  wire ibi_fifo_almost_full;
+  wire up_ibi_fifo_almost_full;
+
+  wire [DATA_WIDTH-1:0] ibi_fifo_data;
+  wire ibi_fifo_ready;
+  wire ibi_fifo_valid;
+  wire ibi_fifo_empty;
+
+  wire up_sw_resetn = ~up_sw_reset;
+
+  wire [31:0] up_rdata_ff_w;
+  wire        up_wreq_s;
+  wire        up_rreq_s;
+  wire [31:0] up_wdata_s;
+  wire [13:0] up_waddr_s;
+  wire [13:0] up_raddr_s;
+  wire        up_cmd_nop;
+
+  // IRQ handling
+
+  wire [`I3C_REGMAP_IRQ_WIDTH:0] up_irq_source;
+  wire [`I3C_REGMAP_IRQ_WIDTH:0] up_irq_pending;
+
+  wire       ops_mode;
+  wire [3:0] ops_offload_len;
+  wire [1:0] ops_sg;
+  wire       offload_idle;
+
+  wire [31:0] cmd_w;
+  wire cmd_valid_w;
+  wire cmd_ready_w;
+
+  wire [6:0] dev_char_addr;
+  wire dev_char_w;
+  wire dev_char_wea;
+  wire dev_char_rea;
+  wire dev_char_ea;
+  wire [3:0] dev_char_wdata;
+  wire [3:0] dev_char_rdata;
+
+  // Offload mode
+
+  wire [31:0] offload_douta;
+  wire [31:0] offload_cmd;
+  wire [31:0] offload_sdo;
+  wire offload_cmd_valid;
+  wire offload_sdo_valid;
+
+  wire clk_1;
+
+  wire cmdr_valid_w;
+  wire cmdr_ready_w;
+
+  wire [31:0] sdo_w;
+  wire sdo_valid_w;
+  wire sdo_ready_w;
+
+  // Interface wrapper
+
+  up_axi #(
+    .AXI_ADDRESS_WIDTH (16)
+  ) i_up_axi (
+    .up_rstn(s_axi_aresetn),
+    .up_clk(s_axi_aclk),
+    .up_axi_awvalid(s_axi_awvalid),
+    .up_axi_awaddr(s_axi_awaddr),
+    .up_axi_awready(s_axi_awready),
+    .up_axi_wvalid(s_axi_wvalid),
+    .up_axi_wdata(s_axi_wdata),
+    .up_axi_wstrb(s_axi_wstrb),
+    .up_axi_wready(s_axi_wready),
+    .up_axi_bvalid(s_axi_bvalid),
+    .up_axi_bresp(s_axi_bresp),
+    .up_axi_bready(s_axi_bready),
+    .up_axi_arvalid(s_axi_arvalid),
+    .up_axi_araddr(s_axi_araddr),
+    .up_axi_arready(s_axi_arready),
+    .up_axi_rvalid(s_axi_rvalid),
+    .up_axi_rresp(s_axi_rresp),
+    .up_axi_rdata(s_axi_rdata),
+    .up_axi_rready(s_axi_rready),
+    .up_wreq(up_wreq_s),
+    .up_waddr(up_waddr_s),
+    .up_wdata(up_wdata_s),
+    .up_wack(up_wack_ff),
+    .up_rreq(up_rreq_s),
+    .up_raddr(up_raddr_s),
+    .up_rdata(up_rdata_ff_w),
+    .up_rack(up_rack_ff));
+
+  assign up_irq_source = {
+    daa_pending,
+    ibi_pending,
+    cmdr_pending,
+    up_ibi_fifo_almost_full,
+    up_sdi_fifo_almost_full,
+    up_sdo_fifo_almost_empty,
+    up_cmdr_fifo_almost_full,
+    up_cmd_fifo_almost_empty
+  };
+
+  assign up_irq_pending = up_irq_mask & up_irq_source;
+
+  always @(posedge s_axi_aclk) begin
+    if (s_axi_aresetn == 1'b0) begin
+      irq <= 1'b0;
+    end else begin
+      irq <= |up_irq_pending;
+    end
+  end
+
+  always @(posedge s_axi_aclk) begin
+    if (s_axi_aresetn == 1'b0) begin
+      up_wack_ff <= 1'b0;
+      up_scratch <= 32'h0;
+      up_sw_reset <= 1'b1;
+    end else begin
+      up_wack_ff <= up_wreq_s;
+      if (up_wreq_s) begin
+        case (up_waddr_s[7:0])
+          `I3C_REGMAP_ENABLE:  up_sw_reset <= up_wdata_s[0];
+          `I3C_REGMAP_SCRATCH: up_scratch <= up_wdata_s;
+        endcase
+      end
+    end
+  end
+
+  assign ops_mode = ops[0];
+  assign ops_offload_len = ops[4:1];
+  assign ops_sg = ops[6:5];
+  assign rmap_pp_sg = ops_sg;
+
+  always @(posedge s_axi_aclk) begin
+    if (!up_sw_resetn) begin
+      ops <= 7'b1100000;
+    end else if (up_cmd_nop) begin
+      if ((~ops_mode & ~cmd_valid_w) | (ops_mode & offload_idle)) begin
+        ops <= ops_candidate;
+      end
+    end
+  end
+
+  // the software reset should reset all the registers
+  integer i;
+  always @(posedge s_axi_aclk) begin
+    if (!up_sw_resetn) begin
+      up_irq_mask <= 8'h0;
+      rmap_ibi_config <= 2'h0;
+      ops_candidate <= 7'd0;
+    end else begin
+      if (up_wreq_s) begin
+        case (up_waddr_s[7:0])
+          `I3C_REGMAP_IRQ_MASK:   up_irq_mask <= up_wdata_s[`I3C_REGMAP_IRQ_WIDTH:0];
+          `I3C_REGMAP_IBI_CONFIG: rmap_ibi_config <= up_wdata_s[1:0];
+          `I3C_REGMAP_OPS:        ops_candidate <= up_wdata_s[6:0];
+          default: begin
+          end
+        endcase
+      end
+    end
+  end
+
+  always @(posedge s_axi_aclk) begin
+    if (s_axi_aresetn == 1'b0) begin
+      up_rack_ff <= 1'd0;
+    end else begin
+      up_rack_ff <= up_rreq_s;
+    end
+  end
+
+  always @(posedge s_axi_aclk) begin
+    case (up_raddr_s[7:0])
+      `I3C_REGMAP_VERSION:        up_rdata_ff <= PCORE_VERSION;
+      `I3C_REGMAP_DEVICE_ID:      up_rdata_ff <= ID;
+      `I3C_REGMAP_SCRATCH:        up_rdata_ff <= up_scratch;
+      `I3C_REGMAP_ENABLE:         up_rdata_ff <= up_sw_reset;
+      `I3C_REGMAP_IRQ_MASK:       up_rdata_ff <= up_irq_mask;
+      `I3C_REGMAP_IRQ_PENDING:    up_rdata_ff <= up_irq_pending;
+      `I3C_REGMAP_IRQ_SOURCE:     up_rdata_ff <= up_irq_source;
+      `I3C_REGMAP_CMD_FIFO_ROOM:  up_rdata_ff <= cmd_fifo_room;
+      `I3C_REGMAP_CMDR_FIFO_LEVEL:up_rdata_ff <= cmdr_fifo_level;
+      `I3C_REGMAP_SDO_FIFO_ROOM:  up_rdata_ff <= sdo_fifo_room;
+      `I3C_REGMAP_SDI_FIFO_LEVEL: up_rdata_ff <= sdi_fifo_level;
+      `I3C_REGMAP_IBI_FIFO_LEVEL: up_rdata_ff <= ibi_fifo_level;
+      `I3C_REGMAP_CMDR_FIFO:      up_rdata_ff <= cmdr_fifo_data;
+      `I3C_REGMAP_SDI_FIFO:       up_rdata_ff <= sdi_fifo_data;
+      `I3C_REGMAP_IBI_FIFO:       up_rdata_ff <= ibi_fifo_data;
+      `I3C_REGMAP_FIFO_STATUS:    up_rdata_ff <= {sdi_fifo_empty, ibi_fifo_empty, cmdr_fifo_empty};
+      `I3C_REGMAP_OPS:            up_rdata_ff <= {cmd_nop, ops};
+      default:                    up_rdata_ff <= 32'h0;
+    endcase
+  end
+
+  assign up_rdata_ff_w =  up_raddr_s[7:0] == `I3C_REGMAP_DEV_CHAR     ? {16'b0, dev_char_addr, 5'b0, dev_char_rdata} :
+                          up_raddr_s[7:4] == `I3C_REGMAP_OFFLOAD_CMD_ ? offload_douta :
+                          up_raddr_s[7:4] == `I3C_REGMAP_OFFLOAD_SDO_ ? offload_douta :
+                        ~|up_raddr_s[3:0] ? up_rdata_ff :
+                          up_rdata_ff;
+
+  ad_mem_dual #(
+    .INITIALIZE(1),
+    .DATA_WIDTH(4),
+    .ADDRESS_WIDTH(7)
+  ) i_mem_dev_char (
+    .clka(s_axi_aclk),
+    .wea(dev_char_wea),
+    .ea(1'b1),
+    .addra(dev_char_addr),
+    .dina(dev_char_wdata),
+    .douta(dev_char_rdata),
+    .clkb(s_axi_aclk),
+    .web(1'b0),
+    .eb(1'b1),
+    .addrb(rmap_dev_char_addr),
+    .dinb(),
+    .doutb(rmap_dev_char_data));
+
+  always @(posedge s_axi_aclk) begin
+    if (dev_char_w) begin
+      dev_char_addr_reg <= dev_char_addr;
+    end
+  end
+
+  assign dev_char_wdata = up_wdata_s[3:0];
+  assign dev_char_addr  = dev_char_w ? up_wdata_s[15:9] : dev_char_addr_reg;
+  assign dev_char_rea   = up_rreq_s == 1'b1 && (up_raddr_s[7:0] == `I3C_REGMAP_DEV_CHAR);
+  assign dev_char_w     = up_wreq_s == 1'b1 && (up_waddr_s[7:0] == `I3C_REGMAP_DEV_CHAR);
+  assign dev_char_wea   = dev_char_w && up_wdata_s[8];
+  assign dev_char_ea    = dev_char_rea | dev_char_wea;
+
+  generate if (OFFLOAD) begin
+    localparam [1:0] SM_CMD_GET = 0;
+    localparam [1:0] SM_CMD_PUT = 1;
+    localparam [1:0] SM_SDO_GET = 2;
+    localparam [1:0] SM_SDO_PUT = 3;
+
+    reg [1:0] sm;
+    reg [3:0] k;
+    reg [3:0] j;
+    reg [9:0] offload_sdo_buffer_len;
+
+    wire offload_ea;
+    wire offload_wea;
+    wire offload_rea;
+    wire [4:0] offload_addra;
+    wire offload_eb;
+    wire [4:0] offload_addrb;
+    wire [31:0] offload_doutb;
+
+    ad_mem_dual #(
+      .DATA_WIDTH(32),
+      .ADDRESS_WIDTH(5)
+    ) i_mem_offload (
+      .clka(s_axi_aclk),
+      .wea(offload_wea),
+      .ea(offload_ea),
+      .addra(offload_addra),
+      .dina(up_wdata_s),
+      .douta(offload_douta),
+      .clkb(s_axi_aclk),
+      .web(1'b0),
+      .eb(offload_eb),
+      .addrb(offload_addrb),
+      .dinb('d0),
+      .doutb(offload_doutb));
+
+    assign offload_addra = up_wreq_s ?
+                        {up_waddr_s[6], up_waddr_s[3:0]} :
+                        {up_raddr_s[6], up_raddr_s[3:0]};
+    assign offload_rea = up_rreq_s == 1'b1 &&
+                        (up_raddr_s[7:4] == `I3C_REGMAP_OFFLOAD_CMD_ |
+                         up_raddr_s[7:4] == `I3C_REGMAP_OFFLOAD_SDO_ );
+    assign offload_wea = up_wreq_s == 1'b1 &&
+                        (up_waddr_s[7:4] == `I3C_REGMAP_OFFLOAD_CMD_ |
+                         up_waddr_s[7:4] == `I3C_REGMAP_OFFLOAD_SDO_ );
+    assign offload_ea = offload_rea | offload_wea;
+
+    always @(posedge s_axi_aclk) begin
+      if (!a_reset_n | ~ops_mode | ops_offload_len == 0) begin
+         offload_sdo_buffer_len <= 0;
+         sm <= SM_CMD_GET;
+         k <= 'd0;
+      end else begin
+        // The same BRAM provides both cmd and sdo,
+        // therefore a request-like interface is used.
+        if (sm[1] == 1'b0) begin
+          j <= 0;
+        end
+        case (sm)
+          SM_CMD_GET: begin
+            if (offload_trigger | k != 0) begin
+              sm <= SM_CMD_PUT;
+              k <= k == ops_offload_len - 1 ? 0 : k + 1;
+            end
+          end
+          SM_CMD_PUT: begin
+            if (cmd_ready) begin
+              sm <= SM_SDO_GET;
+              if (~cmd[0]) begin
+                offload_sdo_buffer_len <= cmd[19:10] + {9'd0, |cmd[9:8]};
+              end
+            end
+          end
+          SM_SDO_GET: begin
+            sm <= SM_SDO_PUT;
+            j <= j + 1;
+          end
+          SM_SDO_PUT: begin
+            // New payload requested, check if is cmd or sdo.
+            if (cmd_ready) begin
+              sm <= SM_CMD_GET;
+            end else if (sdo_ready) begin
+              if (|offload_sdo_buffer_len) begin
+                offload_sdo_buffer_len <= offload_sdo_buffer_len - 1;
+              end
+              sm <= SM_SDO_GET;
+            end
+          end
+        endcase
+      end
+    end
+
+    assign offload_idle  = sm == SM_CMD_GET & k == 0;
+    assign offload_addrb = sm[1] == 1'b0 ? {1'b0,k} : {1'b1,j};
+    assign offload_eb    = sm[0] == 1'b0 & ops_mode;
+    assign offload_cmd_valid = sm == SM_CMD_PUT;
+    assign offload_sdo_valid = sm == SM_SDO_PUT & |offload_sdo_buffer_len;
+    assign offload_cmd = offload_doutb;
+    assign offload_sdo = offload_doutb;
+  end
+  endgenerate
+
+  always @(posedge s_axi_aclk) begin
+    if (up_sw_resetn == 1'b0) begin
+      daa_trigger_lock <= 1'b0;
+      daa_pending <= 1'b0;
+      cmdr_pending <= 1'b0;
+      ibi_pending <= 1'b0;
+    end else begin
+      if (cmdr_fifo_valid == 1'b1) begin
+        cmdr_pending <= 1'b1;
+      end else if (up_wreq_s == 1'b1 &&
+        up_waddr_s[7:0] == `I3C_REGMAP_IRQ_PENDING &&
+        up_wdata_s[`I3C_REGMAP_IRQ_CMDR_PENDING] == 1'b1) begin
+        cmdr_pending <= 1'b0;
+      end
+      if (ibi_fifo_valid == 1'b1) begin
+        ibi_pending <= 1'b1;
+      end else if (up_wreq_s == 1'b1 &&
+        up_waddr_s[7:0] == `I3C_REGMAP_IRQ_PENDING &&
+        up_wdata_s[`I3C_REGMAP_IRQ_IBI_PENDING] == 1'b1) begin
+        ibi_pending <= 1'b0;
+      end
+      if (daa_trigger_lock == 1'b1) begin
+        daa_pending <= 1'b1;
+      end else if (up_wreq_s == 1'b1 &&
+        up_waddr_s[7:0] == `I3C_REGMAP_IRQ_PENDING &&
+        up_wdata_s[`I3C_REGMAP_IRQ_DAA_PENDING] == 1'b1) begin
+        daa_pending <= 1'b0;
+      end
+      if (daa_trigger) begin
+        daa_trigger_lock <= 1'b1;
+      end else if (sdo_valid_w) begin
+        daa_trigger_lock <= 1'b0;
+      end
+    end
+  end
+
+  generate if (ASYNC_CLK) begin
+    wire a_reset;
+    ad_rst i_resetn (
+      .rst_async(up_sw_reset),
+      .clk(clk),
+      .rst(a_reset),
+      .rstn());
+    assign a_reset_n = ~a_reset;
+    assign clk_1 = clk;
+  end else begin /* ASYNC_CLK == 0 */
+    assign a_reset_n = ~up_sw_reset;
+    assign clk_1 = s_axi_aclk;
+  end
+  endgenerate
+
+  assign cmd = ~ops_mode ? cmd_w : offload_cmd;
+  assign cmd_valid   = ~ops_mode ? cmd_valid_w : offload_cmd_valid;
+  assign cmd_ready_w = ~ops_mode ? cmd_ready   : 1'b0;
+  assign cmd_fifo_valid = up_wreq_s == 1'b1 && up_waddr_s[7:0] == `I3C_REGMAP_CMD_FIFO;
+  assign cmd_fifo_data = up_wdata_s;
+
+  util_axis_fifo #(
+    .DATA_WIDTH(DATA_WIDTH),
+    .ADDRESS_WIDTH(`ADDRESS_WIDTH),
+    .ASYNC_CLK(ASYNC_CLK),
+    .M_AXIS_REGISTERED(0),
+    .ALMOST_EMPTY_THRESHOLD(1),
+    .ALMOST_FULL_THRESHOLD(1)
+  ) i_cmd_fifo (
+    .s_axis_aclk(s_axi_aclk),
+    .s_axis_aresetn(up_sw_resetn),
+    .s_axis_ready(cmd_fifo_ready),
+    .s_axis_valid(cmd_fifo_valid),
+    .s_axis_data(cmd_fifo_data),
+    .s_axis_room(cmd_fifo_room),
+    .s_axis_tlast(1'b0),
+    .s_axis_full(),
+    .s_axis_almost_full(),
+    .m_axis_aclk(clk_1),
+    .m_axis_aresetn(a_reset_n),
+    .m_axis_ready(cmd_ready_w),
+    .m_axis_valid(cmd_valid_w),
+    .m_axis_data(cmd_w),
+    .m_axis_tlast(),
+    .m_axis_empty(),
+    .m_axis_almost_empty(cmd_fifo_almost_empty),
+    .m_axis_level());
+
+  assign cmdr_ready   = ~ops_mode ? cmdr_ready_w : 1'b1; // In offload, discard cmdr
+  assign cmdr_valid_w = ~ops_mode ? cmdr_valid   : 1'b0;
+  assign cmdr_fifo_ready = up_rreq_s == 1'b1 && up_raddr_s[7:0] == `I3C_REGMAP_CMDR_FIFO;
+
+  util_axis_fifo #(
+    .DATA_WIDTH(DATA_WIDTH),
+    .ASYNC_CLK(ASYNC_CLK),
+    .ADDRESS_WIDTH(`ADDRESS_WIDTH),
+    .M_AXIS_REGISTERED(0),
+    .ALMOST_EMPTY_THRESHOLD(1),
+    .ALMOST_FULL_THRESHOLD(31)
+  ) i_cmdr_fifo (
+    .s_axis_aclk(clk_1),
+    .s_axis_aresetn(a_reset_n),
+    .s_axis_ready(cmdr_ready_w),
+    .s_axis_valid(cmdr_valid_w),
+    .s_axis_data(cmdr),
+    .s_axis_room(),
+    .s_axis_tlast(),
+    .s_axis_full(),
+    .s_axis_almost_full(cmdr_fifo_almost_full),
+    .m_axis_aclk(s_axi_aclk),
+    .m_axis_aresetn(up_sw_resetn),
+    .m_axis_ready(cmdr_fifo_ready),
+    .m_axis_valid(cmdr_fifo_valid),
+    .m_axis_data(cmdr_fifo_data),
+    .m_axis_tlast(),
+    .m_axis_level(cmdr_fifo_level),
+    .m_axis_empty(cmdr_fifo_empty),
+    .m_axis_almost_empty());
+
+  assign sdo = ~ops_mode ? sdo_w : offload_sdo;
+  assign sdo_valid   = ~ops_mode ? sdo_valid_w : offload_sdo_valid;
+  assign sdo_ready_w = ~ops_mode ? sdo_ready   : 1'b0;
+  assign sdo_fifo_valid = up_wreq_s == 1'b1 && up_waddr_s[7:0] == `I3C_REGMAP_SDO_FIFO;
+  assign sdo_fifo_data = up_wdata_s[31:0];
+
+  util_axis_fifo #(
+    .DATA_WIDTH(DATA_WIDTH),
+    .ASYNC_CLK(ASYNC_CLK),
+    .ADDRESS_WIDTH(`ADDRESS_WIDTH),
+    .M_AXIS_REGISTERED(0),
+    .ALMOST_EMPTY_THRESHOLD(1),
+    .ALMOST_FULL_THRESHOLD(1)
+  ) i_sdo_fifo (
+    .s_axis_aclk(s_axi_aclk),
+    .s_axis_aresetn(up_sw_resetn),
+    .s_axis_ready(sdo_fifo_ready),
+    .s_axis_valid(sdo_fifo_valid),
+    .s_axis_data(sdo_fifo_data),
+    .s_axis_room(sdo_fifo_room),
+    .s_axis_tlast(1'b0),
+    .s_axis_full(),
+    .s_axis_almost_full(),
+    .m_axis_aclk(clk_1),
+    .m_axis_aresetn(a_reset_n),
+    .m_axis_ready(sdo_ready_w),
+    .m_axis_valid(sdo_valid_w),
+    .m_axis_data(sdo_w),
+    .m_axis_tlast(),
+    .m_axis_level(),
+    .m_axis_empty(sdo_fifo_empty),
+    .m_axis_almost_empty(sdo_fifo_almost_empty));
+
+  wire sdi_valid_w;
+  wire sdi_ready_w;
+  assign offload_sdi = sdi;
+  assign offload_sdi_valid =  ops_mode ? sdi_valid : 1'b0;
+  assign sdi_valid_w       = ~ops_mode ? sdi_valid : 1'b0;
+  assign sdi_ready = ops_mode ? offload_sdi_ready : sdi_ready_w;
+  assign sdi_fifo_ready = up_rreq_s == 1'b1 && up_raddr_s[7:0] == `I3C_REGMAP_SDI_FIFO;
+
+  util_axis_fifo #(
+    .DATA_WIDTH(DATA_WIDTH),
+    .ASYNC_CLK(ASYNC_CLK),
+    .ADDRESS_WIDTH(`ADDRESS_WIDTH),
+    .M_AXIS_REGISTERED(0),
+    .ALMOST_EMPTY_THRESHOLD(1),
+    .ALMOST_FULL_THRESHOLD(31)
+  ) i_sdi_fifo (
+    .s_axis_aclk(clk_1),
+    .s_axis_aresetn(a_reset_n),
+    .s_axis_ready(sdi_ready_w),
+    .s_axis_valid(sdi_valid_w),
+    .s_axis_data(sdi),
+    .s_axis_room(),
+    .s_axis_tlast(),
+    .s_axis_full(),
+    .s_axis_almost_full(sdi_fifo_almost_full),
+    .m_axis_aclk(s_axi_aclk),
+    .m_axis_aresetn(up_sw_resetn),
+    .m_axis_ready(sdi_fifo_ready),
+    .m_axis_valid(sdi_fifo_valid),
+    .m_axis_data(sdi_fifo_data),
+    .m_axis_tlast(),
+    .m_axis_level(sdi_fifo_level),
+    .m_axis_empty(sdi_fifo_empty),
+    .m_axis_almost_empty());
+
+  assign ibi_fifo_ready = up_rreq_s == 1'b1 && up_raddr_s[7:0] == `I3C_REGMAP_IBI_FIFO;
+
+  util_axis_fifo #(
+    .DATA_WIDTH(DATA_WIDTH),
+    .ASYNC_CLK(ASYNC_CLK),
+    .ADDRESS_WIDTH(`ADDRESS_WIDTH),
+    .M_AXIS_REGISTERED(0),
+    .ALMOST_EMPTY_THRESHOLD(1),
+    .ALMOST_FULL_THRESHOLD(31)
+  ) i_ibi_fifo (
+    .s_axis_aclk(clk_1),
+    .s_axis_aresetn(a_reset_n),
+    .s_axis_ready(ibi_ready),
+    .s_axis_valid(ibi_valid),
+    .s_axis_data(ibi),
+    .s_axis_room(),
+    .s_axis_tlast(),
+    .s_axis_full(),
+    .s_axis_almost_full(ibi_fifo_almost_full),
+    .m_axis_aclk(s_axi_aclk),
+    .m_axis_aresetn(up_sw_resetn),
+    .m_axis_ready(ibi_fifo_ready),
+    .m_axis_valid(ibi_fifo_valid),
+    .m_axis_data(ibi_fifo_data),
+    .m_axis_tlast(),
+    .m_axis_level(ibi_fifo_level),
+    .m_axis_empty(ibi_fifo_empty),
+    .m_axis_almost_empty());
+
+  sync_bits #(
+    .NUM_OF_BITS (6),
+    .ASYNC_CLK (ASYNC_CLK)
+  ) i_fifo_status (
+    .in_bits ({
+      cmd_fifo_almost_empty, cmdr_fifo_almost_full, sdo_fifo_almost_empty,
+      sdi_fifo_almost_full, ibi_fifo_almost_full, cmd_nop
+    }),
+    .out_resetn (up_sw_resetn),
+    .out_clk (s_axi_aclk),
+    .out_bits ({up_cmd_fifo_almost_empty, up_cmdr_fifo_almost_full,
+      up_sdo_fifo_almost_empty, up_sdi_fifo_almost_full, up_ibi_fifo_almost_full,
+      up_cmd_nop
+    }));
+
+endmodule
diff --git a/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_regmap.vh b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_regmap.vh
new file mode 100644
index 00000000..e09ea184
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_regmap.vh
@@ -0,0 +1,68 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`ifndef I3C_CONTROLLER_REGMAP_V
+`define I3C_CONTROLLER_REGMAP_V
+
+`define I3C_REGMAP_VERSION          8'h00
+`define I3C_REGMAP_DEVICE_ID        8'h01
+`define I3C_REGMAP_SCRATCH          8'h02
+`define I3C_REGMAP_ENABLE           8'h10
+`define I3C_REGMAP_IRQ_MASK         8'h20
+`define I3C_REGMAP_IRQ_PENDING      8'h21
+`define I3C_REGMAP_IRQ_SOURCE       8'h22
+`define I3C_REGMAP_CMD_FIFO_ROOM    8'h30
+`define I3C_REGMAP_CMDR_FIFO_LEVEL  8'h31
+`define I3C_REGMAP_SDO_FIFO_ROOM    8'h32
+`define I3C_REGMAP_SDI_FIFO_LEVEL   8'h33
+`define I3C_REGMAP_IBI_FIFO_LEVEL   8'h34
+`define I3C_REGMAP_CMD_FIFO         8'h35
+`define I3C_REGMAP_CMDR_FIFO        8'h36
+`define I3C_REGMAP_SDO_FIFO         8'h37
+`define I3C_REGMAP_SDI_FIFO         8'h38
+`define I3C_REGMAP_IBI_FIFO         8'h39
+`define I3C_REGMAP_FIFO_STATUS      8'h3a
+`define I3C_REGMAP_OPS              8'h40
+`define I3C_REGMAP_IBI_CONFIG       8'h50
+`define I3C_REGMAP_DEV_CHAR         8'h60
+`define I3C_REGMAP_OFFLOAD_CMD_     4'hb
+`define I3C_REGMAP_OFFLOAD_SDO_     4'hc
+
+`define I3C_REGMAP_IRQ_WIDTH        7
+`define I3C_REGMAP_IRQ_CMDR_PENDING 5
+`define I3C_REGMAP_IRQ_IBI_PENDING  6
+`define I3C_REGMAP_IRQ_DAA_PENDING  7
+
+`endif
diff --git a/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_unpack.v b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_unpack.v
new file mode 100644
index 00000000..977869a3
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_unpack.v
@@ -0,0 +1,98 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+/**
+ * Unpacks u32 packages into u8 stream.
+ */
+
+`timescale 1ns/100ps
+
+module i3c_controller_unpack (
+  input         clk,
+  input         reset_n,
+  input         stop,
+
+  output        u32_ready,
+  input         u32_valid,
+  input  [31:0] u32,
+
+  output [11:0] u8_lvl,
+
+  input         u8_ready,
+  output        u8_valid,
+  output [7:0]  u8
+);
+
+  localparam [0:0] SM_GET = 0;
+  localparam [0:0] SM_PUT = 1;
+
+  reg [0:0]  sm;
+  reg [1:0]  c;
+  reg [11:0] u8_lvl_reg;
+  reg [31:0] u32_reg;
+
+  always @(posedge clk) begin
+    if (!reset_n | stop) begin
+      sm <= SM_GET;
+      c <= 2'b00;
+      u8_lvl_reg <= 0;
+    end else begin
+      case (sm)
+        SM_GET: begin
+          if (u32_valid) begin
+            sm <= SM_PUT;
+          end
+          u32_reg <= u32;
+          c <= 2'b00;
+        end
+        SM_PUT: begin
+          if (u8_ready) begin // tick
+            u8_lvl_reg <= u8_lvl_reg + 12'b1;
+            c <= c + 1;
+            if (c == 2'b11) begin
+              sm <= SM_GET;
+            end
+            u32_reg <= u32_reg >> 8;
+          end
+        end
+      endcase
+    end
+  end
+
+  assign u32_ready = sm == SM_GET & (reset_n | stop);
+  assign u8_valid = sm == SM_PUT;
+  assign u8_lvl = u8_lvl_reg;
+  assign u8 = u32_reg[7:0];
+
+endmodule
diff --git a/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_write_ibi.v b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_write_ibi.v
new file mode 100644
index 00000000..bf16d5b7
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_host_interface/i3c_controller_write_ibi.v
@@ -0,0 +1,82 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+//   1. The GNU General Public License version 2 as published by the
+//      Free Software Foundation, which can be found in the top level directory
+//      of this repository (LICENSE_GPL2), and also online at:
+//      <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
+//
+// OR
+//
+//   2. An ADI specific BSD license, which can be found in the top level directory
+//      of this repository (LICENSE_ADIBSD), and also on-line at:
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+//      This will allow to generate bit files and not release the source code,
+//      as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module i3c_controller_write_ibi (
+  input  clk,
+  input  reset_n,
+
+  input  out_ready,
+  output out_valid,
+  output [31:0] out,
+
+  output in_ready,
+  input  in_valid,
+  input  [14:0] in
+);
+
+  reg [0:0] sm;
+
+  reg [6:0] da;
+  reg [7:0] mdb;
+  reg [7:0] sync;
+
+  localparam [0:0] SM_GET = 0;
+  localparam [0:0] SM_PUT = 1;
+
+  always @(posedge clk) begin
+    if (!reset_n) begin
+      sm <= SM_GET;
+      sync <= 8'd0;
+    end else begin
+      case (sm)
+        SM_GET: begin
+          sm <= in_valid ? SM_PUT : sm;
+          da   <= in[14:8];
+          mdb  <= in[7:0];
+        end
+        SM_PUT: begin
+          sm <= out_ready ? SM_GET : sm;
+          sync <= out_ready ? sync+1 : sync;
+        end
+      endcase
+    end
+  end
+
+  assign out = {8'd0, da, 1'b0, mdb, sync};
+  assign in_ready = sm == SM_GET;
+  assign out_valid = sm == SM_PUT;
+endmodule
diff --git a/adi_library/i3c_controller/i3c_controller_host_interface/xgui/i3c_controller_host_interface_v1_0.tcl b/adi_library/i3c_controller/i3c_controller_host_interface/xgui/i3c_controller_host_interface_v1_0.tcl
new file mode 100644
index 00000000..1663106d
--- /dev/null
+++ b/adi_library/i3c_controller/i3c_controller_host_interface/xgui/i3c_controller_host_interface_v1_0.tcl
@@ -0,0 +1,61 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set I3C_Controller_Host_Interface [ipgui::add_page $IPINST -name "I3C Controller Host Interface" -display_name {AXI I3C Controller Host Interface}]
+  #Adding Group
+  set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${I3C_Controller_Host_Interface}]
+  set ID [ipgui::add_param $IPINST -name "ID" -parent ${General_Configuration}]
+  set_property tooltip {[ID] Core instance ID} ${ID}
+  set ASYNC_CLK [ipgui::add_param $IPINST -name "ASYNC_CLK" -parent ${General_Configuration}]
+  set_property tooltip {[ASYNC_CLK] Define the relationship between the core clock and the memory mapped interface clock} ${ASYNC_CLK}
+  set OFFLOAD [ipgui::add_param $IPINST -name "OFFLOAD" -parent ${General_Configuration}]
+  set_property tooltip {[OFFLOAD] Allows to offload output data to a external receiver, like a DMA} ${OFFLOAD}
+
+
+
+}
+
+proc update_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } {
+	# Procedure called to update ASYNC_CLK when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } {
+	# Procedure called to validate ASYNC_CLK
+	return true
+}
+
+proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
+	# Procedure called to update ID when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
+	# Procedure called to validate ID
+	return true
+}
+
+proc update_PARAM_VALUE.OFFLOAD { PARAM_VALUE.OFFLOAD } {
+	# Procedure called to update OFFLOAD when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.OFFLOAD { PARAM_VALUE.OFFLOAD } {
+	# Procedure called to validate OFFLOAD
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
+}
+
+proc update_MODELPARAM_VALUE.ASYNC_CLK { MODELPARAM_VALUE.ASYNC_CLK PARAM_VALUE.ASYNC_CLK } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK}] ${MODELPARAM_VALUE.ASYNC_CLK}
+}
+
+proc update_MODELPARAM_VALUE.OFFLOAD { MODELPARAM_VALUE.OFFLOAD PARAM_VALUE.OFFLOAD } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.OFFLOAD}] ${MODELPARAM_VALUE.OFFLOAD}
+}
+
diff --git a/adi_library/i3c_controller/interfaces/Makefile b/adi_library/i3c_controller/interfaces/Makefile
new file mode 100644
index 00000000..77d761b0
--- /dev/null
+++ b/adi_library/i3c_controller/interfaces/Makefile
@@ -0,0 +1,42 @@
+####################################################################################
+####################################################################################
+## Copyright (C) 2024 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS := interfaces_ip.tcl
+M_DEPS += ../../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_ip_xilinx.tcl
+
+M_VIVADO := vivado -mode batch -source
+
+XML_FLIST := i3c_controller.xml
+XML_FLIST += i3c_controller_rtl.xml
+XML_FLIST += i3c_controller_cmdp.xml
+XML_FLIST += i3c_controller_cmdp_rtl.xml
+XML_FLIST += i3c_controller_rmap.xml
+XML_FLIST += i3c_controller_rmap_rtl.xml
+XML_FLIST += i3c_controller_sdio.xml
+XML_FLIST += i3c_controller_sdio_rtl.xml
+
+M_FLIST := *.log
+M_FLIST += *.jou
+M_FLIST += $(XML_FLIST)
+
+.PHONY: all xilinx clean clean-all
+all: xilinx
+
+xilinx: $(XML_FLIST)
+
+clean:clean-all
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+%.xml: $(M_DEPS)
+	$(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/adi_library/i3c_controller/interfaces/i3c_controller.xml b/adi_library/i3c_controller/interfaces/i3c_controller.xml
new file mode 100644
index 00000000..0e90be56
--- /dev/null
+++ b/adi_library/i3c_controller/interfaces/i3c_controller.xml
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>interface</spirit:library>
+  <spirit:name>i3c_controller</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:directConnection>false</spirit:directConnection>
+  <spirit:isAddressable>false</spirit:isAddressable>
+  <spirit:maxMasters>1</spirit:maxMasters>
+  <spirit:maxSlaves>1</spirit:maxSlaves>
+</spirit:busDefinition>
diff --git a/adi_library/i3c_controller/interfaces/i3c_controller_cmdp.xml b/adi_library/i3c_controller/interfaces/i3c_controller_cmdp.xml
new file mode 100644
index 00000000..2608984b
--- /dev/null
+++ b/adi_library/i3c_controller/interfaces/i3c_controller_cmdp.xml
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>interface</spirit:library>
+  <spirit:name>i3c_controller_cmdp</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:directConnection>false</spirit:directConnection>
+  <spirit:isAddressable>false</spirit:isAddressable>
+  <spirit:maxMasters>1</spirit:maxMasters>
+  <spirit:maxSlaves>1</spirit:maxSlaves>
+</spirit:busDefinition>
diff --git a/adi_library/i3c_controller/interfaces/i3c_controller_cmdp_rtl.xml b/adi_library/i3c_controller/interfaces/i3c_controller_cmdp_rtl.xml
new file mode 100644
index 00000000..dfdc8a61
--- /dev/null
+++ b/adi_library/i3c_controller/interfaces/i3c_controller_cmdp_rtl.xml
@@ -0,0 +1,94 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>interface</spirit:library>
+  <spirit:name>i3c_controller_cmdp_rtl</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="i3c_controller_cmdp" spirit:version="1.0"/>
+  <spirit:ports>
+    <spirit:port>
+      <spirit:logicalName>cmdp_ready</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>cmdp_valid</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>cmdp</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>31</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>31</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>cmdp_error</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>3</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>3</spirit:width>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>cmdp_nop</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>cmdp_daa_trigger</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+  </spirit:ports>
+</spirit:abstractionDefinition>
diff --git a/adi_library/i3c_controller/interfaces/i3c_controller_cmdp_v1_0.sv b/adi_library/i3c_controller/interfaces/i3c_controller_cmdp_v1_0.sv
new file mode 100644
index 00000000..72356b05
--- /dev/null
+++ b/adi_library/i3c_controller/interfaces/i3c_controller_cmdp_v1_0.sv
@@ -0,0 +1,77 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+`ifndef i3c_controller_cmdp_v1_0
+`define i3c_controller_cmdp_v1_0
+
+interface i3c_controller_cmdp_v1_0();
+  logic cmdp_ready;                                      // 
+  logic cmdp_valid;                                      // 
+  logic [30:0] cmdp;                                      // 
+  logic [2:0] cmdp_error;                                // 
+  logic cmdp_nop;                                        // 
+  logic cmdp_daa_trigger;                                // 
+
+  modport MASTER (
+    input cmdp_ready, cmdp_error, cmdp_nop, cmdp_daa_trigger, 
+    output cmdp_valid, cmdp
+    );
+
+  modport SLAVE (
+    input cmdp_valid, cmdp, 
+    output cmdp_ready, cmdp_error, cmdp_nop, cmdp_daa_trigger
+    );
+
+  modport MONITOR (
+    input cmdp_ready, cmdp_valid, cmdp, cmdp_error, cmdp_nop, cmdp_daa_trigger
+    );
+
+endinterface // i3c_controller_cmdp_v1_0
+
+`endif
\ No newline at end of file
diff --git a/adi_library/i3c_controller/interfaces/i3c_controller_rmap.xml b/adi_library/i3c_controller/interfaces/i3c_controller_rmap.xml
new file mode 100644
index 00000000..14f5cf79
--- /dev/null
+++ b/adi_library/i3c_controller/interfaces/i3c_controller_rmap.xml
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>interface</spirit:library>
+  <spirit:name>i3c_controller_rmap</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:directConnection>false</spirit:directConnection>
+  <spirit:isAddressable>false</spirit:isAddressable>
+  <spirit:maxMasters>1</spirit:maxMasters>
+  <spirit:maxSlaves>1</spirit:maxSlaves>
+</spirit:busDefinition>
diff --git a/adi_library/i3c_controller/interfaces/i3c_controller_rmap_rtl.xml b/adi_library/i3c_controller/interfaces/i3c_controller_rmap_rtl.xml
new file mode 100644
index 00000000..ef8ea8b2
--- /dev/null
+++ b/adi_library/i3c_controller/interfaces/i3c_controller_rmap_rtl.xml
@@ -0,0 +1,66 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>interface</spirit:library>
+  <spirit:name>i3c_controller_rmap_rtl</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="i3c_controller_rmap" spirit:version="1.0"/>
+  <spirit:ports>
+    <spirit:port>
+      <spirit:logicalName>rmap_ibi_config</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>2</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>2</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rmap_pp_sg</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>2</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>2</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rmap_dev_char_addr</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>7</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>7</spirit:width>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>rmap_dev_char_data</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>4</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>4</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+  </spirit:ports>
+</spirit:abstractionDefinition>
diff --git a/adi_library/i3c_controller/interfaces/i3c_controller_rmap_v1_0.sv b/adi_library/i3c_controller/interfaces/i3c_controller_rmap_v1_0.sv
new file mode 100644
index 00000000..b4bc428a
--- /dev/null
+++ b/adi_library/i3c_controller/interfaces/i3c_controller_rmap_v1_0.sv
@@ -0,0 +1,75 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+`ifndef i3c_controller_rmap_v1_0
+`define i3c_controller_rmap_v1_0
+
+interface i3c_controller_rmap_v1_0();
+  logic [1:0] rmap_ibi_config;                           // 
+  logic [1:0] rmap_pp_sg;                                // 
+  logic [6:0] rmap_dev_char_addr;                        // 
+  logic [3:0] rmap_dev_char_data;                        // 
+
+  modport MASTER (
+    input rmap_dev_char_addr, 
+    output rmap_ibi_config, rmap_pp_sg, rmap_dev_char_data
+    );
+
+  modport SLAVE (
+    input rmap_ibi_config, rmap_pp_sg, rmap_dev_char_data, 
+    output rmap_dev_char_addr
+    );
+
+  modport MONITOR (
+    input rmap_ibi_config, rmap_pp_sg, rmap_dev_char_addr, rmap_dev_char_data
+    );
+
+endinterface // i3c_controller_rmap_v1_0
+
+`endif
\ No newline at end of file
diff --git a/adi_library/i3c_controller/interfaces/i3c_controller_rtl.xml b/adi_library/i3c_controller/interfaces/i3c_controller_rtl.xml
new file mode 100644
index 00000000..9a06ec57
--- /dev/null
+++ b/adi_library/i3c_controller/interfaces/i3c_controller_rtl.xml
@@ -0,0 +1,66 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>interface</spirit:library>
+  <spirit:name>i3c_controller_rtl</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="i3c_controller" spirit:version="1.0"/>
+  <spirit:ports>
+    <spirit:port>
+      <spirit:logicalName>scl</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sdo</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sdi</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>t</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+  </spirit:ports>
+</spirit:abstractionDefinition>
diff --git a/adi_library/i3c_controller/interfaces/i3c_controller_sdio.xml b/adi_library/i3c_controller/interfaces/i3c_controller_sdio.xml
new file mode 100644
index 00000000..33d57e4a
--- /dev/null
+++ b/adi_library/i3c_controller/interfaces/i3c_controller_sdio.xml
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>interface</spirit:library>
+  <spirit:name>i3c_controller_sdio</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:directConnection>false</spirit:directConnection>
+  <spirit:isAddressable>false</spirit:isAddressable>
+  <spirit:maxMasters>1</spirit:maxMasters>
+  <spirit:maxSlaves>1</spirit:maxSlaves>
+</spirit:busDefinition>
diff --git a/adi_library/i3c_controller/interfaces/i3c_controller_sdio_rtl.xml b/adi_library/i3c_controller/interfaces/i3c_controller_sdio_rtl.xml
new file mode 100644
index 00000000..77855980
--- /dev/null
+++ b/adi_library/i3c_controller/interfaces/i3c_controller_sdio_rtl.xml
@@ -0,0 +1,150 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>interface</spirit:library>
+  <spirit:name>i3c_controller_sdio_rtl</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="i3c_controller_sdio" spirit:version="1.0"/>
+  <spirit:ports>
+    <spirit:port>
+      <spirit:logicalName>sdo_ready</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sdo_valid</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sdo</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>8</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>8</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sdi_ready</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sdi_valid</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sdi_last</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sdi</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>8</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>8</spirit:width>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>ibi_ready</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>ibi_valid</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>ibi</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>15</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>15</spirit:width>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+  </spirit:ports>
+</spirit:abstractionDefinition>
diff --git a/adi_library/i3c_controller/interfaces/i3c_controller_sdio_v1_0.sv b/adi_library/i3c_controller/interfaces/i3c_controller_sdio_v1_0.sv
new file mode 100644
index 00000000..48f741c6
--- /dev/null
+++ b/adi_library/i3c_controller/interfaces/i3c_controller_sdio_v1_0.sv
@@ -0,0 +1,81 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+`ifndef i3c_controller_sdio_v1_0
+`define i3c_controller_sdio_v1_0
+
+interface i3c_controller_sdio_v1_0();
+  logic sdo_ready;                                       // 
+  logic sdo_valid;                                       // 
+  logic [7:0] sdo;                                       // 
+  logic sdi_ready;                                       // 
+  logic sdi_valid;                                       // 
+  logic sdi_last;                                        // 
+  logic [7:0] sdi;                                       // 
+  logic ibi_ready;                                       // 
+  logic ibi_valid;                                       // 
+  logic [14:0] ibi;                                       // 
+
+  modport MASTER (
+    input sdo_ready, sdi_valid, sdi_last, sdi, ibi_valid, ibi, 
+    output sdo_valid, sdo, sdi_ready, ibi_ready
+    );
+
+  modport SLAVE (
+    input sdo_valid, sdo, sdi_ready, ibi_ready, 
+    output sdo_ready, sdi_valid, sdi_last, sdi, ibi_valid, ibi
+    );
+
+  modport MONITOR (
+    input sdo_ready, sdo_valid, sdo, sdi_ready, sdi_valid, sdi_last, sdi, ibi_ready, ibi_valid, ibi
+    );
+
+endinterface // i3c_controller_sdio_v1_0
+
+`endif
\ No newline at end of file
diff --git a/adi_library/i3c_controller/interfaces/i3c_controller_v1_0.sv b/adi_library/i3c_controller/interfaces/i3c_controller_v1_0.sv
new file mode 100644
index 00000000..14dededf
--- /dev/null
+++ b/adi_library/i3c_controller/interfaces/i3c_controller_v1_0.sv
@@ -0,0 +1,75 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+`ifndef i3c_controller_v1_0
+`define i3c_controller_v1_0
+
+interface i3c_controller_v1_0();
+  logic scl;                                             // 
+  logic sdo;                                             // 
+  logic sdi;                                             // 
+  logic t;                                               // 
+
+  modport MASTER (
+    input sdi, 
+    output scl, sdo, t
+    );
+
+  modport SLAVE (
+    input scl, sdo, t, 
+    output sdi
+    );
+
+  modport MONITOR (
+    input scl, sdo, sdi, t
+    );
+
+endinterface // i3c_controller_v1_0
+
+`endif
\ No newline at end of file
diff --git a/adi_library/i3c_controller/interfaces/interfaces_ip.tcl b/adi_library/i3c_controller/interfaces/interfaces_ip.tcl
new file mode 100644
index 00000000..0550246e
--- /dev/null
+++ b/adi_library/i3c_controller/interfaces/interfaces_ip.tcl
@@ -0,0 +1,47 @@
+###############################################################################
+## Copyright (C) 2023 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source ../../../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
+
+# Bus interface
+
+adi_if_define "i3c_controller"
+adi_if_ports output 1 scl
+adi_if_ports output 1 sdo
+adi_if_ports input  1 sdi
+adi_if_ports output 1 t
+
+# Interface between Host Interface and Core for commands
+
+adi_if_define "i3c_controller_cmdp"
+adi_if_ports input   1 cmdp_ready
+adi_if_ports output  1 cmdp_valid
+adi_if_ports output 31 cmdp
+adi_if_ports input   3 cmdp_error
+adi_if_ports input   1 cmdp_nop
+adi_if_ports input   1 cmdp_daa_trigger
+
+# Interface between Host Interface and Core for register map access
+
+adi_if_define "i3c_controller_rmap"
+adi_if_ports output 2 rmap_ibi_config
+adi_if_ports output 2 rmap_pp_sg
+adi_if_ports input  7 rmap_dev_char_addr
+adi_if_ports output 4 rmap_dev_char_data
+
+# Interface between Host Interface and Core for data transfer
+
+adi_if_define "i3c_controller_sdio"
+adi_if_ports input  1  sdo_ready
+adi_if_ports output 1  sdo_valid
+adi_if_ports output 8  sdo
+adi_if_ports output 1  sdi_ready
+adi_if_ports input  1  sdi_valid
+adi_if_ports input  1  sdi_last
+adi_if_ports input  8  sdi
+adi_if_ports output 1  ibi_ready
+adi_if_ports input  1  ibi_valid
+adi_if_ports input  15 ibi
diff --git a/adi_library/i3c_controller/scripts/i3c_controller_bd.tcl b/adi_library/i3c_controller/scripts/i3c_controller_bd.tcl
new file mode 100644
index 00000000..49e488d9
--- /dev/null
+++ b/adi_library/i3c_controller/scripts/i3c_controller_bd.tcl
@@ -0,0 +1,53 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+proc i3c_controller_create {{name "i3c_controller"} {async_clk 0} {clk_mod 1} {offload 1} {max_devs 16}} {
+
+  create_bd_cell -type hier $name
+  current_bd_instance /$name
+
+  if {$async_clk == 1} {
+    create_bd_pin -dir I -type clk aclk
+  }
+  create_bd_pin -dir I -type clk clk
+  create_bd_pin -dir I -type rst reset_n
+  create_bd_pin -dir O irq
+  create_bd_intf_pin -mode Master -vlnv analog.com:interface:i3c_controller_rtl:1.0 m_i3c
+  if {$offload == 1} {
+    create_bd_pin -dir I trigger
+    create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 offload_sdi
+  }
+
+  ad_ip_instance i3c_controller_host_interface host_interface
+  ad_ip_parameter host_interface CONFIG.ASYNC_CLK $async_clk
+  ad_ip_parameter host_interface CONFIG.OFFLOAD $offload
+
+  ad_ip_instance i3c_controller_core core
+  ad_ip_parameter core CONFIG.MAX_DEVS $max_devs
+  ad_ip_parameter core CONFIG.CLK_MOD $clk_mod
+
+  ad_connect clk host_interface/s_axi_aclk
+  if {$async_clk == 1} {
+    ad_connect aclk host_interface/clk
+    ad_connect aclk core/clk
+  } else {
+    ad_connect clk core/clk
+  }
+  if {$offload == 1} {
+    ad_connect trigger host_interface/offload_trigger
+    ad_connect host_interface/offload_sdi offload_sdi
+  }
+
+  ad_connect core/i3c m_i3c
+  ad_connect host_interface/reset_n core/reset_n
+  ad_connect host_interface/rmap core/rmap
+  ad_connect host_interface/cmdp core/cmdp
+  ad_connect host_interface/sdio core/sdio
+
+  ad_connect reset_n host_interface/s_axi_aresetn
+  ad_connect irq     host_interface/irq
+
+  current_bd_instance /
+}
diff --git a/adi_library/i3c_controller/scripts/i3c_controller_qsys.tcl b/adi_library/i3c_controller/scripts/i3c_controller_qsys.tcl
new file mode 100644
index 00000000..f11d5e9e
--- /dev/null
+++ b/adi_library/i3c_controller/scripts/i3c_controller_qsys.tcl
@@ -0,0 +1,24 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+proc i3c_controller_create {{name "i3c_controller"} {async_clk 0} {clk_mod 1} {offload 1} {max_devs 16}} {
+  add_instance ${name}_host_interface i3c_controller_host_interface
+
+  set_instance_parameter_value ${name}_host_interface {ASYNC_CLK} $async_clk
+  set_instance_parameter_value ${name}_host_interface {OFFLOAD}   $offload
+
+  add_instance ${name}_core i3c_controller_core
+
+  set_instance_parameter_value ${name}_core {MAX_DEVS} $max_devs
+  set_instance_parameter_value ${name}_core {CLK_MOD} $clk_mod
+
+  add_connection ${name}_host_interface.sdo  ${name}_core.sdo
+  add_connection ${name}_host_interface.cmdp ${name}_core.cmdp
+  add_connection ${name}_host_interface.rmap ${name}_core.rmap
+  add_connection ${name}_core.sdi ${name}_host_interface.sdi
+  add_connection ${name}_core.ibi ${name}_host_interface.ibi
+
+  add_connection ${name}_host_interface.if_reset_n ${name}_core.if_reset_n
+}
diff --git a/adi_library/intel/adi_jesd204/adi_jesd204_glue.v b/adi_library/intel/adi_jesd204/adi_jesd204_glue.v
index 9ebf40ef..327ef259 100644
--- a/adi_library/intel/adi_jesd204/adi_jesd204_glue.v
+++ b/adi_library/intel/adi_jesd204/adi_jesd204_glue.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/intel/avl_adxcfg/avl_adxcfg.v b/adi_library/intel/avl_adxcfg/avl_adxcfg.v
index af903946..a93b2df2 100644
--- a/adi_library/intel/avl_adxcfg/avl_adxcfg.v
+++ b/adi_library/intel/avl_adxcfg/avl_adxcfg.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap.v b/adi_library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap.v
index 0b6030f4..f68946d1 100644
--- a/adi_library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap.v
+++ b/adi_library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/intel/avl_adxphy/avl_adxphy.v b/adi_library/intel/avl_adxphy/avl_adxphy.v
index dc371c98..4c43c77d 100644
--- a/adi_library/intel/avl_adxphy/avl_adxphy.v
+++ b/adi_library/intel/avl_adxphy/avl_adxphy.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/intel/avl_dacfifo/avl_dacfifo.v b/adi_library/intel/avl_dacfifo/avl_dacfifo.v
index 258ae14f..c7c412c9 100644
--- a/adi_library/intel/avl_dacfifo/avl_dacfifo.v
+++ b/adi_library/intel/avl_dacfifo/avl_dacfifo.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/intel/avl_dacfifo/avl_dacfifo_rd.v b/adi_library/intel/avl_dacfifo/avl_dacfifo_rd.v
index 722b98b3..ced1ca3c 100644
--- a/adi_library/intel/avl_dacfifo/avl_dacfifo_rd.v
+++ b/adi_library/intel/avl_dacfifo/avl_dacfifo_rd.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/intel/avl_dacfifo/avl_dacfifo_wr.v b/adi_library/intel/avl_dacfifo/avl_dacfifo_wr.v
index 21ec8c84..74ee1a24 100644
--- a/adi_library/intel/avl_dacfifo/avl_dacfifo_wr.v
+++ b/adi_library/intel/avl_dacfifo/avl_dacfifo_wr.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/intel/avl_dacfifo/util_dacfifo_bypass.v b/adi_library/intel/avl_dacfifo/util_dacfifo_bypass.v
index 9e01510d..9c32b838 100644
--- a/adi_library/intel/avl_dacfifo/util_dacfifo_bypass.v
+++ b/adi_library/intel/avl_dacfifo/util_dacfifo_bypass.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/intel/axi_adxcvr/axi_adxcvr.v b/adi_library/intel/axi_adxcvr/axi_adxcvr.v
index cb54ffa3..9a441163 100644
--- a/adi_library/intel/axi_adxcvr/axi_adxcvr.v
+++ b/adi_library/intel/axi_adxcvr/axi_adxcvr.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/intel/axi_adxcvr/axi_adxcvr_up.v b/adi_library/intel/axi_adxcvr/axi_adxcvr_up.v
index 366e7136..c213b270 100644
--- a/adi_library/intel/axi_adxcvr/axi_adxcvr_up.v
+++ b/adi_library/intel/axi_adxcvr/axi_adxcvr_up.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/intel/common/ad_dcfilter.v b/adi_library/intel/common/ad_dcfilter.v
index c135f35b..deb468c8 100644
--- a/adi_library/intel/common/ad_dcfilter.v
+++ b/adi_library/intel/common/ad_dcfilter.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/intel/common/ad_mul.v b/adi_library/intel/common/ad_mul.v
index 7359ec90..cf4aec56 100644
--- a/adi_library/intel/common/ad_mul.v
+++ b/adi_library/intel/common/ad_mul.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/intel/jesd204_phy/jesd204_phy_glue.v b/adi_library/intel/jesd204_phy/jesd204_phy_glue.v
index 28e2244b..36509a89 100644
--- a/adi_library/intel/jesd204_phy/jesd204_phy_glue.v
+++ b/adi_library/intel/jesd204_phy/jesd204_phy_glue.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/intel/util_clkdiv/util_clkdiv.v b/adi_library/intel/util_clkdiv/util_clkdiv.v
index 2c6836a9..df25fd62 100644
--- a/adi_library/intel/util_clkdiv/util_clkdiv.v
+++ b/adi_library/intel/util_clkdiv/util_clkdiv.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/interfaces/Makefile b/adi_library/interfaces/Makefile
index 7952cae9..b96091d7 100644
--- a/adi_library/interfaces/Makefile
+++ b/adi_library/interfaces/Makefile
@@ -16,6 +16,7 @@ M_VIVADO := vivado -mode batch -source
 
 M_FLIST := *.log
 M_FLIST += *.jou
+M_FLIST += *.sv
 M_FLIST += if_xcvr_cm.xml
 M_FLIST += if_xcvr_cm_rtl.xml
 M_FLIST += if_xcvr_ch.xml
diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v
index bd2bac0c..6240701b 100644
--- a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v
+++ b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.xpr b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.xpr
index d0f5430c..18cedfa2 100644
--- a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.xpr
+++ b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="d3e1001c6f6a4273955da0d13d53fb7b"/>
+    <Option Name="Id" Val="48dd613bd4ca48b89ed2c32714fcc0ba"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -311,21 +310,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -338,7 +337,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v
index 4a4b8a8a..27f153be 100644
--- a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v
+++ b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v
index c5e6aa2b..cc0004ac 100644
--- a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v
+++ b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v
index c477aa17..afdeccfe 100644
--- a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v
+++ b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v
index 88ae6b36..37568784 100644
--- a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v
+++ b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v
index 1b878c8e..cc3bd4d5 100644
--- a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v
+++ b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/component.xml b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/component.xml
index 67232740..345a8abb 100644
--- a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/component.xml
+++ b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/component.xml
@@ -296,7 +296,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>caecda58</spirit:value>
+            <spirit:value>670acfc5</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -312,7 +312,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>649450b5</spirit:value>
+            <spirit:value>f78cc535</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1055,30 +1055,6 @@
       <spirit:enumeration>12</spirit:enumeration>
       <spirit:enumeration>16</spirit:enumeration>
     </spirit:choice>
-    <spirit:choice>
-      <spirit:name>choice_pairs_00ecfe9a</spirit:name>
-      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
-      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
-      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
-      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
-      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
-      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
-      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
-      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
-      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
-      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
-      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
-      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
-      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
-      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
-      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
-      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
-      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
-      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
-      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
-      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
-      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
-    </spirit:choice>
     <spirit:choice>
       <spirit:name>choice_pairs_19f99f31</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
@@ -1104,7 +1080,32 @@
       <spirit:enumeration spirit:text="versal">4</spirit:enumeration>
     </spirit:choice>
     <spirit:choice>
-      <spirit:name>choice_pairs_fc01a186</spirit:name>
+      <spirit:name>choice_pairs_a6e6e044</spirit:name>
+      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
+      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
+      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
+      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
+      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
+      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
+      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
+      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
+      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
+      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
+      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
+      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
+      <spirit:enumeration spirit:text="ls">21</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a897e79d</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
       <spirit:enumeration spirit:text="artix">1</spirit:enumeration>
       <spirit:enumeration spirit:text="kintex">2</spirit:enumeration>
@@ -1112,6 +1113,7 @@
       <spirit:enumeration spirit:text="zynq">4</spirit:enumeration>
       <spirit:enumeration spirit:text="versalprime">5</spirit:enumeration>
       <spirit:enumeration spirit:text="versalaicore">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="versalpremium">7</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
   <spirit:fileSets>
@@ -1208,7 +1210,7 @@
       <spirit:file>
         <spirit:name>ad_ip_jesd204_tpl_adc.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_cd763ccf</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_2ae5caad</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1322,7 +1324,7 @@
     <spirit:parameter>
       <spirit:name>FPGA_FAMILY</spirit:name>
       <spirit:displayName>Fpga Family</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_fc01a186">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_a897e79d">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>SPEED_GRADE</spirit:name>
@@ -1332,7 +1334,7 @@
     <spirit:parameter>
       <spirit:name>DEV_PACKAGE</spirit:name>
       <spirit:displayName>Dev Package</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_00ecfe9a">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_a6e6e044">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>NUM_LANES</spirit:name>
@@ -1437,11 +1439,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/peripherals/jesd204/jesd204_tpl_adc</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:40:08Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T02:55:52Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="c47545eb"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="8d6bb3cd"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="7bb43336"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="19ccb69d"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="f184678c"/>
diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v b/adi_library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v
index f0d8de0d..8dc20219 100644
--- a/adi_library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v
+++ b/adi_library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v
index da0a973d..ba715944 100644
--- a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v
+++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.xpr b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.xpr
index b7be3517..a75cfff1 100644
--- a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.xpr
+++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="4e0e220c7a614532ba51097e300354d7"/>
+    <Option Name="Id" Val="06a9e6ac688f46b4af3225b2aac7ceed"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -360,21 +359,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -387,7 +386,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v
index 287a973e..643cdaa5 100644
--- a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v
+++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v
index f5e979f9..8fe0d702 100644
--- a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v
+++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v
index 242c1f4e..35bb3e09 100644
--- a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v
+++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_pn.v b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_pn.v
index 70c540f6..860ca01d 100644
--- a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_pn.v
+++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_pn.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v
index c89d5c20..7a80747c 100644
--- a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v
+++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/component.xml b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/component.xml
index 5bc7f3c4..7a7e2128 100644
--- a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/component.xml
+++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/component.xml
@@ -296,7 +296,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>7664e214</spirit:value>
+            <spirit:value>9efe5b40</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -312,7 +312,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>c6d3408b</spirit:value>
+            <spirit:value>cb21bb39</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1062,30 +1062,6 @@
       <spirit:enumeration>12</spirit:enumeration>
       <spirit:enumeration>16</spirit:enumeration>
     </spirit:choice>
-    <spirit:choice>
-      <spirit:name>choice_pairs_00ecfe9a</spirit:name>
-      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
-      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
-      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
-      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
-      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
-      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
-      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
-      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
-      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
-      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
-      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
-      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
-      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
-      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
-      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
-      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
-      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
-      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
-      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
-      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
-      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
-    </spirit:choice>
     <spirit:choice>
       <spirit:name>choice_pairs_19f99f31</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
@@ -1116,7 +1092,32 @@
       <spirit:enumeration spirit:text="CORDIC">1</spirit:enumeration>
     </spirit:choice>
     <spirit:choice>
-      <spirit:name>choice_pairs_fc01a186</spirit:name>
+      <spirit:name>choice_pairs_a6e6e044</spirit:name>
+      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
+      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
+      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
+      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
+      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
+      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
+      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
+      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
+      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
+      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
+      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
+      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
+      <spirit:enumeration spirit:text="ls">21</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a897e79d</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
       <spirit:enumeration spirit:text="artix">1</spirit:enumeration>
       <spirit:enumeration spirit:text="kintex">2</spirit:enumeration>
@@ -1124,6 +1125,7 @@
       <spirit:enumeration spirit:text="zynq">4</spirit:enumeration>
       <spirit:enumeration spirit:text="versalprime">5</spirit:enumeration>
       <spirit:enumeration spirit:text="versalaicore">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="versalpremium">7</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
   <spirit:fileSets>
@@ -1248,7 +1250,7 @@
       <spirit:file>
         <spirit:name>ad_ip_jesd204_tpl_dac.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_1106ebc2</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_96dd7c2c</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1397,7 +1399,7 @@
     <spirit:parameter>
       <spirit:name>FPGA_FAMILY</spirit:name>
       <spirit:displayName>Fpga Family</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_fc01a186">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_a897e79d">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>SPEED_GRADE</spirit:name>
@@ -1407,7 +1409,7 @@
     <spirit:parameter>
       <spirit:name>DEV_PACKAGE</spirit:name>
       <spirit:displayName>Dev Package</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_00ecfe9a">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_a6e6e044">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>NUM_LANES</spirit:name>
@@ -1553,11 +1555,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/peripherals/jesd204/jesd204_tpl_dac</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:50:42Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:08:10Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="7dc1a493"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="5a15e3b5"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="fcd834a6"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="290c1a7f"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="30a3933d"/>
diff --git a/adi_library/jesd204/axi_jesd204_common/axi_jesd204_common.xpr b/adi_library/jesd204/axi_jesd204_common/axi_jesd204_common.xpr
index 2479ca22..58b558aa 100644
--- a/adi_library/jesd204/axi_jesd204_common/axi_jesd204_common.xpr
+++ b/adi_library/jesd204/axi_jesd204_common/axi_jesd204_common.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/jesd204/axi_jesd204_common/axi_jesd204_common.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/jesd204/axi_jesd204_common/axi_jesd204_common.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="eaddf6ca246c4a3c8aced5d95e931dbe"/>
+    <Option Name="Id" Val="16751faac088488b95bf2a0a107878fe"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -60,7 +60,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -175,21 +174,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -202,7 +201,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/jesd204/axi_jesd204_common/component.xml b/adi_library/jesd204/axi_jesd204_common/component.xml
index cf06e5d7..1cb81807 100644
--- a/adi_library/jesd204/axi_jesd204_common/component.xml
+++ b/adi_library/jesd204/axi_jesd204_common/component.xml
@@ -21,7 +21,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>c4c41562</spirit:value>
+            <spirit:value>30b478ce</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -40,7 +40,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>dd8aa7f3</spirit:value>
+            <spirit:value>b6425778</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -376,11 +376,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:50:49Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:08:17Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="f09a8047"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="a9e3e021"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="7105858c"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="5ef422d3"/>
     </xilinx:packagingInfo>
diff --git a/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx.xpr b/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx.xpr
index e4f01124..8af86b12 100644
--- a/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx.xpr
+++ b/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/jesd204/axi_jesd204_rx/axi_jesd204_rx.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="65fc52178778410ba1471c34ea6a8f11"/>
+    <Option Name="Id" Val="a4b676d5960a420ebb6c481a26a6f59c"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -60,7 +60,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -190,21 +189,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -217,7 +216,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/jesd204/axi_jesd204_rx/component.xml b/adi_library/jesd204/axi_jesd204_rx/component.xml
index 23cd8670..4e024d6e 100644
--- a/adi_library/jesd204/axi_jesd204_rx/component.xml
+++ b/adi_library/jesd204/axi_jesd204_rx/component.xml
@@ -627,7 +627,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>ee177bde</spirit:value>
+            <spirit:value>34b2f2aa</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -646,7 +646,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>5ba02ad7</spirit:value>
+            <spirit:value>77c08331</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1835,11 +1835,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_rx</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:51:05Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:08:35Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="8b19c33c"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="df352823"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="72c0f30a"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="9a9f8847"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="71fa65e4"/>
diff --git a/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx.xpr b/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx.xpr
index 376f8fd7..010b1314 100644
--- a/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx.xpr
+++ b/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/jesd204/axi_jesd204_tx/axi_jesd204_tx.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="9162f4c9af3f47ffb44e034cdca2df90"/>
+    <Option Name="Id" Val="399ceeffdc5e4a859b9b5fcbd4843e7f"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -60,7 +60,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -176,21 +175,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -203,7 +202,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/jesd204/axi_jesd204_tx/component.xml b/adi_library/jesd204/axi_jesd204_tx/component.xml
index 95ea2b0d..7eced716 100644
--- a/adi_library/jesd204/axi_jesd204_tx/component.xml
+++ b/adi_library/jesd204/axi_jesd204_tx/component.xml
@@ -586,7 +586,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>dc0625d2</spirit:value>
+            <spirit:value>82a1546f</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -605,7 +605,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>eecd3758</spirit:value>
+            <spirit:value>90502e77</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1655,11 +1655,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_tx</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:51:15Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:08:45Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="7d6761b3"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="c87a572f"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="7bfda6e4"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="9a9f8847"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="e4c88b0c"/>
diff --git a/adi_library/jesd204/interfaces/Makefile b/adi_library/jesd204/interfaces/Makefile
index 30c763ec..a7492b31 100644
--- a/adi_library/jesd204/interfaces/Makefile
+++ b/adi_library/jesd204/interfaces/Makefile
@@ -33,6 +33,7 @@ XML_FLIST += jesd204_rx_event_rtl.xml
 
 M_FLIST := *.log
 M_FLIST += *.jou
+M_FLIST += *.sv
 M_FLIST += $(XML_FLIST)
 
 .PHONY: all xilinx clean clean-all
diff --git a/adi_library/jesd204/jesd204_common/component.xml b/adi_library/jesd204/jesd204_common/component.xml
index 75592bd1..0a1a90f7 100644
--- a/adi_library/jesd204/jesd204_common/component.xml
+++ b/adi_library/jesd204/jesd204_common/component.xml
@@ -190,7 +190,7 @@
     <spirit:fileSet>
       <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
       <spirit:file>
-        <spirit:name>xgui/pipeline_stage_v1_0.tcl</spirit:name>
+        <spirit:name>xgui/jesd204_common_v1_0.tcl</spirit:name>
         <spirit:fileType>tclSource</spirit:fileType>
         <spirit:userFileType>CHECKSUM_fa2aa10a</spirit:userFileType>
         <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
@@ -253,10 +253,10 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:51:22Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:08:53Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
       <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="022b1da1"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="98b19fb0"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="bf0ff3fe"/>
diff --git a/adi_library/jesd204/jesd204_common/jesd204_common.xpr b/adi_library/jesd204/jesd204_common/jesd204_common.xpr
index deb33a81..e053fcd3 100644
--- a/adi_library/jesd204/jesd204_common/jesd204_common.xpr
+++ b/adi_library/jesd204/jesd204_common/jesd204_common.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/jesd204/jesd204_common/jesd204_common.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/jesd204/jesd204_common/jesd204_common.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="c31c7c1bcbc14ce0b643d6cf5ca8398b"/>
+    <Option Name="Id" Val="7dba73c94f2b4584b00bd961dceecded"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -60,7 +60,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -204,21 +203,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -231,7 +230,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/jesd204/jesd204_common/jesd204_common_ip.tcl b/adi_library/jesd204/jesd204_common/jesd204_common_ip.tcl
index afd58a7d..19aa922b 100755
--- a/adi_library/jesd204/jesd204_common/jesd204_common_ip.tcl
+++ b/adi_library/jesd204/jesd204_common/jesd204_common_ip.tcl
@@ -27,4 +27,5 @@ set_property display_name "ADI JESD204C Common Library" [ipx::current_core]
 set_property description "ADI JESD204C Common Library" [ipx::current_core]
 set_property hide_in_gui {1} [ipx::current_core]
 
+ipx::create_xgui_files [ipx::current_core]
 ipx::save_core [ipx::current_core]
diff --git a/adi_library/jesd204/jesd204_common/xgui/jesd204_common_v1_0.tcl b/adi_library/jesd204/jesd204_common/xgui/jesd204_common_v1_0.tcl
new file mode 100644
index 00000000..a5103fce
--- /dev/null
+++ b/adi_library/jesd204/jesd204_common/xgui/jesd204_common_v1_0.tcl
@@ -0,0 +1,40 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "REGISTERED" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "WIDTH" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.REGISTERED { PARAM_VALUE.REGISTERED } {
+	# Procedure called to update REGISTERED when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.REGISTERED { PARAM_VALUE.REGISTERED } {
+	# Procedure called to validate REGISTERED
+	return true
+}
+
+proc update_PARAM_VALUE.WIDTH { PARAM_VALUE.WIDTH } {
+	# Procedure called to update WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.WIDTH { PARAM_VALUE.WIDTH } {
+	# Procedure called to validate WIDTH
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.REGISTERED { MODELPARAM_VALUE.REGISTERED PARAM_VALUE.REGISTERED } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.REGISTERED}] ${MODELPARAM_VALUE.REGISTERED}
+}
+
+proc update_MODELPARAM_VALUE.WIDTH { MODELPARAM_VALUE.WIDTH PARAM_VALUE.WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.WIDTH}] ${MODELPARAM_VALUE.WIDTH}
+}
+
diff --git a/adi_library/jesd204/jesd204_rx/component.xml b/adi_library/jesd204/jesd204_rx/component.xml
index 95c69426..6deb39cf 100644
--- a/adi_library/jesd204/jesd204_rx/component.xml
+++ b/adi_library/jesd204/jesd204_rx/component.xml
@@ -3221,7 +3221,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>bf400151</spirit:value>
+            <spirit:value>92d764be</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -3243,7 +3243,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>bf400151</spirit:value>
+            <spirit:value>92d764be</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -4322,7 +4322,7 @@
       <spirit:file>
         <spirit:name>../../common/ad_upack.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_b9097df1</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_1efbc24f</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -4576,11 +4576,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:51:40Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:09:13Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="c0fd4592"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="3c371bca"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="121fb194"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="89348620"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="c8d659ee"/>
diff --git a/adi_library/jesd204/jesd204_rx/jesd204_rx.xpr b/adi_library/jesd204/jesd204_rx/jesd204_rx.xpr
index 13c9a2ed..09e8e917 100644
--- a/adi_library/jesd204/jesd204_rx/jesd204_rx.xpr
+++ b/adi_library/jesd204/jesd204_rx/jesd204_rx.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/jesd204/jesd204_rx/jesd204_rx.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/jesd204/jesd204_rx/jesd204_rx.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="cfc9f32b8125432197831f319320dfe5"/>
+    <Option Name="Id" Val="4c46f66bfaf4474c8b78e1fca6b83af6"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -60,7 +60,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -262,21 +261,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -289,7 +288,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/jesd204/jesd204_rx_static_config/component.xml b/adi_library/jesd204/jesd204_rx_static_config/component.xml
index 1a145800..019b13c5 100644
--- a/adi_library/jesd204/jesd204_rx_static_config/component.xml
+++ b/adi_library/jesd204/jesd204_rx_static_config/component.xml
@@ -640,10 +640,10 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:51:47Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:09:21Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
       <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="b27f218c"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="245281c3"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="89c08d59"/>
diff --git a/adi_library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.xpr b/adi_library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.xpr
index 24742546..710636cb 100644
--- a/adi_library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.xpr
+++ b/adi_library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="5d3606a870bb4c23bb9d75709952ab5e"/>
+    <Option Name="Id" Val="5ccf326232b6499baaf58389e5f6f34e"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -154,21 +153,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -181,7 +180,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/jesd204/jesd204_tx/component.xml b/adi_library/jesd204/jesd204_tx/component.xml
index db54efb5..18734e5b 100644
--- a/adi_library/jesd204/jesd204_tx/component.xml
+++ b/adi_library/jesd204/jesd204_tx/component.xml
@@ -2060,7 +2060,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>df6c408b</spirit:value>
+            <spirit:value>a4213ab5</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -2082,7 +2082,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>df6c408b</spirit:value>
+            <spirit:value>a4213ab5</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -3139,11 +3139,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:52:01Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:09:36Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="bb00555f"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="a36665c5"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="8c4db624"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="d9bf1593"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="b0db50c8"/>
diff --git a/adi_library/jesd204/jesd204_tx/jesd204_tx.xpr b/adi_library/jesd204/jesd204_tx/jesd204_tx.xpr
index aae1ef5c..6719e47b 100644
--- a/adi_library/jesd204/jesd204_tx/jesd204_tx.xpr
+++ b/adi_library/jesd204/jesd204_tx/jesd204_tx.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/jesd204/jesd204_tx/jesd204_tx.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/jesd204/jesd204_tx/jesd204_tx.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="014cb9339f654cf5a96021a09e87f59b"/>
+    <Option Name="Id" Val="b75af0adacad4945953e6fde862370e0"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -60,7 +60,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -213,21 +212,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -240,7 +239,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/jesd204/jesd204_tx_static_config/component.xml b/adi_library/jesd204/jesd204_tx_static_config/component.xml
index 953c233a..4171c31b 100644
--- a/adi_library/jesd204/jesd204_tx_static_config/component.xml
+++ b/adi_library/jesd204/jesd204_tx_static_config/component.xml
@@ -774,10 +774,10 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:52:09Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:09:45Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
       <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="33dfcb96"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="788fa5d4"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="efdf1a77"/>
diff --git a/adi_library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.xpr b/adi_library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.xpr
index 3fa4c024..d477cd99 100644
--- a/adi_library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.xpr
+++ b/adi_library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="fe6e0fb21717486b96e464ee6d04c5ff"/>
+    <Option Name="Id" Val="43776910edb642308763322362c72306"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -161,21 +160,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -188,7 +187,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/jesd204/jesd204_versal_gt_adapter_rx/component.xml b/adi_library/jesd204/jesd204_versal_gt_adapter_rx/component.xml
index 3ffbd94b..87119f60 100644
--- a/adi_library/jesd204/jesd204_versal_gt_adapter_rx/component.xml
+++ b/adi_library/jesd204/jesd204_versal_gt_adapter_rx/component.xml
@@ -333,10 +333,10 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:52:17Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:09:53Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
       <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="59f935f5"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="dd3ed853"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="c254db4c"/>
diff --git a/adi_library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.xpr b/adi_library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.xpr
index 6b87fce0..b8fe7a97 100644
--- a/adi_library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.xpr
+++ b/adi_library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="4186a5db1f1f4cc498e2e361ba72e563"/>
+    <Option Name="Id" Val="54eb2fded4cc4ac19cf5013f2a985286"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -161,21 +160,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -188,7 +187,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/jesd204/jesd204_versal_gt_adapter_tx/component.xml b/adi_library/jesd204/jesd204_versal_gt_adapter_tx/component.xml
index 397df5bd..011ae106 100644
--- a/adi_library/jesd204/jesd204_versal_gt_adapter_tx/component.xml
+++ b/adi_library/jesd204/jesd204_versal_gt_adapter_tx/component.xml
@@ -261,10 +261,10 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:52:25Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:10:02Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
       <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="606d4414"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="f3584279"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="576635a4"/>
diff --git a/adi_library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.xpr b/adi_library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.xpr
index 9513ddde..83bcaa8a 100644
--- a/adi_library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.xpr
+++ b/adi_library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="1feb2f4aebfd4cd0a7c3e2b20367c907"/>
+    <Option Name="Id" Val="4f3e5e65ad3341eda162a5f5e5f4a621"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -154,21 +153,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -181,7 +180,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/scripts/adi_xilinx_device_info_enc.tcl b/adi_library/scripts/adi_xilinx_device_info_enc.tcl
index 85035a88..7632937c 100644
--- a/adi_library/scripts/adi_xilinx_device_info_enc.tcl
+++ b/adi_library/scripts/adi_xilinx_device_info_enc.tcl
@@ -35,14 +35,14 @@ set fpga_technology_list { \
         { versal      4 }}
 
 set fpga_family_list { \
-        { Unknown      0 } \
-        { artix        1 } \
-        { kintex       2 } \
-        { virtex       3 } \
-        { zynq         4 } \
-        { versalprime  5 } \
-        { versalaicore 6 } \
-      }
+        { Unknown       0 } \
+        { artix         1 } \
+        { kintex        2 } \
+        { virtex        3 } \
+        { zynq          4 } \
+        { versalprime   5 } \
+        { versalaicore  6 } \
+        { versalpremium 7 }}
 
 set speed_grade_list { \
         { Unknown 0  } \
@@ -80,7 +80,8 @@ set dev_package_list { \
         { fa      17 } \
         { fs      18 } \
         { fi      19 } \
-        { vs      20 }}
+        { vs      20 } \
+        { ls      21 }}
 
 
 set xcvr_type_list { \
diff --git a/adi_library/spi_engine/axi_spi_engine/Makefile b/adi_library/spi_engine/axi_spi_engine/Makefile
index 33588929..993f41e3 100644
--- a/adi_library/spi_engine/axi_spi_engine/Makefile
+++ b/adi_library/spi_engine/axi_spi_engine/Makefile
@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################
@@ -22,6 +22,8 @@ XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
 XILINX_LIB_DEPS += util_axis_fifo
 XILINX_LIB_DEPS += util_cdc
 
+XILINX_INTERFACE_DEPS += spi_engine/interfaces
+
 INTEL_DEPS += ../../common/ad_mem.v
 INTEL_DEPS += ../../intel/common/up_rst_constr.sdc
 INTEL_DEPS += ../../util_axis_fifo/util_axis_fifo.v
diff --git a/adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v b/adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v
index 77e3d9b4..cafe2e09 100644
--- a/adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v
+++ b/adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -133,7 +133,7 @@ module axi_spi_engine #(
   input [7:0] offload_sync_data
 );
 
-  localparam PCORE_VERSION = 'h010071;
+  localparam PCORE_VERSION = 'h010200;
   localparam S_AXI = 0;
   localparam UP_FIFO = 1;
 
@@ -334,12 +334,20 @@ module axi_spi_engine #(
   end
   endgenerate
 
+  reg [7:0] offload_sdo_mem_address_width = OFFLOAD0_SDO_MEM_ADDRESS_WIDTH;
+  reg [7:0] offload_cmd_mem_address_width = OFFLOAD0_CMD_MEM_ADDRESS_WIDTH;
+  reg [7:0] sdi_fifo_address_width = SDI_FIFO_ADDRESS_WIDTH;
+  reg [7:0] sdo_fifo_address_width = SDO_FIFO_ADDRESS_WIDTH;
+  reg [7:0] sync_fifo_address_width = SYNC_FIFO_ADDRESS_WIDTH;
+  reg [7:0] cmd_fifo_address_width = CMD_FIFO_ADDRESS_WIDTH;
   always @(posedge clk) begin
     case (up_raddr_s)
       8'h00: up_rdata_ff <= PCORE_VERSION;
       8'h01: up_rdata_ff <= ID;
       8'h02: up_rdata_ff <= up_scratch;
       8'h03: up_rdata_ff <= {8'b0, NUM_OF_SDI, DATA_WIDTH};
+      8'h04: up_rdata_ff <= {16'b0, offload_sdo_mem_address_width, offload_cmd_mem_address_width};
+      8'h05: up_rdata_ff <= {sdi_fifo_address_width, sdo_fifo_address_width, sync_fifo_address_width, cmd_fifo_address_width};
       8'h10: up_rdata_ff <= up_sw_reset;
       8'h20: up_rdata_ff <= up_irq_mask;
       8'h21: up_rdata_ff <= up_irq_pending;
diff --git a/adi_library/spi_engine/axi_spi_engine/axi_spi_engine.xpr b/adi_library/spi_engine/axi_spi_engine/axi_spi_engine.xpr
index 6a23ed21..39b5827c 100644
--- a/adi_library/spi_engine/axi_spi_engine/axi_spi_engine.xpr
+++ b/adi_library/spi_engine/axi_spi_engine/axi_spi_engine.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/spi_engine/axi_spi_engine/axi_spi_engine.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/spi_engine/axi_spi_engine/axi_spi_engine.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="7614137f133e45a3b5014a3375bb1862"/>
+    <Option Name="Id" Val="a6c121ede1ae47db9f9ddbaf67411ed8"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -175,21 +174,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -202,7 +201,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl b/adi_library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl
index 329cc3dc..8f9e2f5d 100644
--- a/adi_library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl
+++ b/adi_library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl
@@ -109,12 +109,6 @@ proc p_elaboration {} {
 
   }
 
-  ad_interface signal  pulse_gen_period  output  32
-  ad_interface signal  pulse_gen_width   output  32
-  ad_interface signal  pulse_gen_load    output   1
-
-  lappend disabled_intfs if_pulse_gen_period if_pulse_gen_width if_pulse_gen_load
-
   foreach interface $disabled_intfs {
     set_interface_property $interface ENABLED false
   }
diff --git a/adi_library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl b/adi_library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl
index 496a99fc..b775c377 100644
--- a/adi_library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl
+++ b/adi_library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -34,18 +34,18 @@ adi_add_bus "spi_engine_ctrl" "master" \
 	"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
 	"analog.com:interface:spi_engine_ctrl:1.0" \
 	{
-		{"cmd_ready" "CMD_READY"} \
-		{"cmd_valid" "CMD_VALID"} \
-		{"cmd_data" "CMD_DATA"} \
-		{"sdo_data_ready" "SDO_READY"} \
-		{"sdo_data_valid" "SDO_VALID"} \
-		{"sdo_data" "SDO_DATA"} \
-		{"sdi_data_ready" "SDI_READY"} \
-		{"sdi_data_valid" "SDI_VALID"} \
-		{"sdi_data" "SDI_DATA"} \
-		{"sync_ready" "SYNC_READY"} \
-		{"sync_valid" "SYNC_VALID"} \
-		{"sync_data" "SYNC_DATA"} \
+		{"cmd_ready" "cmd_ready"} \
+		{"cmd_valid" "cmd_valid"} \
+		{"cmd_data" "cmd_data"} \
+		{"sdo_data_ready" "sdo_ready"} \
+		{"sdo_data_valid" "sdo_valid"} \
+		{"sdo_data" "sdo_data"} \
+		{"sdi_data_ready" "sdi_ready"} \
+		{"sdi_data_valid" "sdi_valid"} \
+		{"sdi_data" "sdi_data"} \
+		{"sync_ready" "sync_ready"} \
+		{"sync_valid" "sync_valid"} \
+		{"sync_data" "sync_data"} \
 	}
 adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn" "master"
 
@@ -53,18 +53,17 @@ adi_add_bus "spi_engine_offload_ctrl0" "master" \
 	"analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \
 	"analog.com:interface:spi_engine_offload_ctrl:1.0" \
 	{ \
-		{ "offload0_cmd_wr_en" "CMD_WR_EN"} \
-		{ "offload0_cmd_wr_data" "CMD_WR_DATA"} \
-		{ "offload0_sdo_wr_en" "SDO_WR_EN"} \
-		{ "offload0_sdo_wr_data" "SDO_WR_DATA"} \
-		{ "offload0_enable" "ENABLE"} \
-		{ "offload0_enabled" "ENABLED"} \
-		{ "offload0_mem_reset" "MEM_RESET"} \
-		{ "offload_sync_ready" "SYNC_READY"} \
-		{ "offload_sync_valid" "SYNC_VALID"} \
-		{ "offload_sync_data" "SYNC_DATA"} \
+		{ "offload0_cmd_wr_en" "cmd_wr_en"} \
+		{ "offload0_cmd_wr_data" "cmd_wr_data"} \
+		{ "offload0_sdo_wr_en" "sdo_wr_en"} \
+		{ "offload0_sdo_wr_data" "sdo_wr_data"} \
+		{ "offload0_enable" "enable"} \
+		{ "offload0_enabled" "enabled"} \
+		{ "offload0_mem_reset" "mem_reset"} \
+		{ "offload_sync_ready" "sync_ready"} \
+		{ "offload_sync_valid" "sync_valid"} \
+		{ "offload_sync_data" "sync_data"} \
 	}
-
 adi_add_bus_clock "s_axi_aclk" "spi_engine_offload_ctrl0:s_axi" "s_axi_aresetn"
 
 foreach port {"up_clk" "up_rstn" "up_wreq" "up_waddr" "up_wdata" "up_rreq" "up_raddr"} {
diff --git a/adi_library/spi_engine/axi_spi_engine/component.xml b/adi_library/spi_engine/axi_spi_engine/component.xml
index e0fef590..d8efb4dc 100644
--- a/adi_library/spi_engine/axi_spi_engine/component.xml
+++ b/adi_library/spi_engine/axi_spi_engine/component.xml
@@ -230,7 +230,7 @@
       <spirit:portMaps>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>CMD_READY</spirit:name>
+            <spirit:name>cmd_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>cmd_ready</spirit:name>
@@ -238,7 +238,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>CMD_VALID</spirit:name>
+            <spirit:name>cmd_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>cmd_valid</spirit:name>
@@ -246,7 +246,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>CMD_DATA</spirit:name>
+            <spirit:name>cmd_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>cmd_data</spirit:name>
@@ -254,7 +254,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO_READY</spirit:name>
+            <spirit:name>sdo_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sdo_data_ready</spirit:name>
@@ -262,7 +262,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO_VALID</spirit:name>
+            <spirit:name>sdo_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sdo_data_valid</spirit:name>
@@ -270,7 +270,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO_DATA</spirit:name>
+            <spirit:name>sdo_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sdo_data</spirit:name>
@@ -278,7 +278,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDI_READY</spirit:name>
+            <spirit:name>sdi_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sdi_data_ready</spirit:name>
@@ -286,7 +286,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDI_VALID</spirit:name>
+            <spirit:name>sdi_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sdi_data_valid</spirit:name>
@@ -294,7 +294,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDI_DATA</spirit:name>
+            <spirit:name>sdi_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sdi_data</spirit:name>
@@ -302,7 +302,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_READY</spirit:name>
+            <spirit:name>sync_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sync_ready</spirit:name>
@@ -310,7 +310,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_VALID</spirit:name>
+            <spirit:name>sync_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sync_valid</spirit:name>
@@ -318,7 +318,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_DATA</spirit:name>
+            <spirit:name>sync_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sync_data</spirit:name>
@@ -384,7 +384,7 @@
       <spirit:portMaps>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>CMD_WR_EN</spirit:name>
+            <spirit:name>cmd_wr_en</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>offload0_cmd_wr_en</spirit:name>
@@ -392,7 +392,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>CMD_WR_DATA</spirit:name>
+            <spirit:name>cmd_wr_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>offload0_cmd_wr_data</spirit:name>
@@ -400,7 +400,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO_WR_EN</spirit:name>
+            <spirit:name>sdo_wr_en</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>offload0_sdo_wr_en</spirit:name>
@@ -408,7 +408,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO_WR_DATA</spirit:name>
+            <spirit:name>sdo_wr_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>offload0_sdo_wr_data</spirit:name>
@@ -416,7 +416,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>ENABLE</spirit:name>
+            <spirit:name>enable</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>offload0_enable</spirit:name>
@@ -424,7 +424,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>ENABLED</spirit:name>
+            <spirit:name>enabled</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>offload0_enabled</spirit:name>
@@ -432,7 +432,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>MEM_RESET</spirit:name>
+            <spirit:name>mem_reset</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>offload0_mem_reset</spirit:name>
@@ -440,7 +440,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_READY</spirit:name>
+            <spirit:name>sync_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>offload_sync_ready</spirit:name>
@@ -448,7 +448,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_VALID</spirit:name>
+            <spirit:name>sync_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>offload_sync_valid</spirit:name>
@@ -456,7 +456,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_DATA</spirit:name>
+            <spirit:name>sync_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>offload_sync_data</spirit:name>
@@ -553,7 +553,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>1fd5eec0</spirit:value>
+            <spirit:value>01e9a617</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -575,7 +575,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>089a1d05</spirit:value>
+            <spirit:value>2c2a08bc</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1868,7 +1868,7 @@
       <spirit:file>
         <spirit:name>axi_spi_engine.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_6b9f989c</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_a04cf31b</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -2074,11 +2074,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/peripherals/spi_engine/axi</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:52:34Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:10:12Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="071f18c1"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="35a91dd8"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="ca848ee8"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="e191cf5b"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="570013dc"/>
diff --git a/adi_library/spi_engine/interfaces/Makefile b/adi_library/spi_engine/interfaces/Makefile
new file mode 100644
index 00000000..b9b4d67f
--- /dev/null
+++ b/adi_library/spi_engine/interfaces/Makefile
@@ -0,0 +1,41 @@
+####################################################################################
+####################################################################################
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+####################################################################################
+
+M_DEPS := interfaces_ip.tcl
+M_DEPS += ../../../scripts/adi_env.tcl
+M_DEPS += ../../scripts/adi_ip_xilinx.tcl
+
+M_VIVADO := vivado -mode batch -source
+
+XML_FLIST := spi_engine.xml
+XML_FLIST += spi_engine_rtl.xml
+XML_FLIST += spi_engine_ctrl.xml
+XML_FLIST += spi_engine_ctrl_rtl.xml
+XML_FLIST += spi_engine_offload_ctrl.xml
+XML_FLIST += spi_engine_offload_ctrl_rtl.xml
+
+M_FLIST := *.log
+M_FLIST += *.jou
+M_FLIST += *.sv
+M_FLIST += $(XML_FLIST)
+
+.PHONY: all xilinx clean clean-all
+all: xilinx
+
+xilinx: $(XML_FLIST)
+
+clean:clean-all
+
+clean-all:
+	rm -rf $(M_FLIST)
+
+%.xml: $(M_DEPS)
+	$(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1
+
+####################################################################################
+####################################################################################
diff --git a/adi_library/spi_engine/interfaces/interfaces_ip.tcl b/adi_library/spi_engine/interfaces/interfaces_ip.tcl
new file mode 100644
index 00000000..fa1cc602
--- /dev/null
+++ b/adi_library/spi_engine/interfaces/interfaces_ip.tcl
@@ -0,0 +1,47 @@
+###############################################################################
+## Copyright (C) 2024 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source ../../../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
+
+# SPI interface
+
+adi_if_define "spi_engine"
+adi_if_ports output 1 sclk
+adi_if_ports output 1 sdo
+adi_if_ports output 1 sdo_t
+adi_if_ports input -1 sdi
+adi_if_ports output -1 cs
+adi_if_ports output 1 three_wire
+
+# Control interface
+
+adi_if_define "spi_engine_ctrl"
+adi_if_ports input 1 cmd_ready
+adi_if_ports output 1 cmd_valid
+adi_if_ports output 16 cmd_data
+adi_if_ports input 1 sdo_ready
+adi_if_ports output 1 sdo_valid
+adi_if_ports output -1 sdo_data
+adi_if_ports output 1 sdi_ready
+adi_if_ports input 1 sdi_valid
+adi_if_ports input -1 sdi_data
+adi_if_ports output 1 sync_ready
+adi_if_ports input 1 sync_valid
+adi_if_ports input 8 sync_data
+
+# Offload control interface
+
+adi_if_define "spi_engine_offload_ctrl"
+adi_if_ports output 1 cmd_wr_en
+adi_if_ports output 16 cmd_wr_data
+adi_if_ports output 1 sdo_wr_en
+adi_if_ports output -1 sdo_wr_data
+adi_if_ports output 1 mem_reset
+adi_if_ports output 1 enable
+adi_if_ports input 1 enabled
+adi_if_ports output 1 sync_ready
+adi_if_ports input 1 sync_valid
+adi_if_ports input 8 sync_data
diff --git a/adi_library/spi_engine/interfaces/spi_engine.xml b/adi_library/spi_engine/interfaces/spi_engine.xml
new file mode 100644
index 00000000..9e086f1a
--- /dev/null
+++ b/adi_library/spi_engine/interfaces/spi_engine.xml
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>interface</spirit:library>
+  <spirit:name>spi_engine</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:directConnection>false</spirit:directConnection>
+  <spirit:isAddressable>false</spirit:isAddressable>
+  <spirit:maxMasters>1</spirit:maxMasters>
+  <spirit:maxSlaves>1</spirit:maxSlaves>
+</spirit:busDefinition>
diff --git a/adi_library/spi_engine/interfaces/spi_engine_ctrl.xml b/adi_library/spi_engine/interfaces/spi_engine_ctrl.xml
index 0ccbf8de..9494af84 100644
--- a/adi_library/spi_engine/interfaces/spi_engine_ctrl.xml
+++ b/adi_library/spi_engine/interfaces/spi_engine_ctrl.xml
@@ -1,13 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com"
-		xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
-		xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
-	<spirit:vendor>analog.com</spirit:vendor>
-	<spirit:library>interface</spirit:library>
-	<spirit:name>spi_engine_ctrl</spirit:name>
-	<spirit:version>1.0</spirit:version>
-	<spirit:directConnection>false</spirit:directConnection>
-	<spirit:isAddressable>false</spirit:isAddressable>
-	<spirit:maxMasters>1</spirit:maxMasters>
-	<spirit:maxSlaves>1</spirit:maxSlaves>
+<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>interface</spirit:library>
+  <spirit:name>spi_engine_ctrl</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:directConnection>false</spirit:directConnection>
+  <spirit:isAddressable>false</spirit:isAddressable>
+  <spirit:maxMasters>1</spirit:maxMasters>
+  <spirit:maxSlaves>1</spirit:maxSlaves>
 </spirit:busDefinition>
diff --git a/adi_library/spi_engine/interfaces/spi_engine_ctrl_rtl.xml b/adi_library/spi_engine/interfaces/spi_engine_ctrl_rtl.xml
index 2ba4f27f..7b51d806 100644
--- a/adi_library/spi_engine/interfaces/spi_engine_ctrl_rtl.xml
+++ b/adi_library/spi_engine/interfaces/spi_engine_ctrl_rtl.xml
@@ -1,189 +1,174 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com"
-		xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
-		xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
-	<spirit:vendor>analog.com</spirit:vendor>
-	<spirit:library>interface</spirit:library>
-	<spirit:name>spi_engine_ctrl_rtl</spirit:name>
-	<spirit:version>1.0</spirit:version>
-	<spirit:busType spirit:vendor="analog.com"
-			spirit:library="interface"
-			spirit:name="spi_engine_ctrl"
-			spirit:version="1.0"/>
-	<spirit:ports>
-		<spirit:port>
-			<spirit:logicalName>CMD_READY</spirit:logicalName>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-				</spirit:onSlave>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>CMD_VALID</spirit:logicalName>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onSlave>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>CMD_DATA</spirit:logicalName>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>16</spirit:width>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>16</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onSlave>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>SDO_READY</spirit:logicalName>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-				</spirit:onSlave>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>SDO_VALID</spirit:logicalName>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onSlave>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>SDO_DATA</spirit:logicalName>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>8</spirit:width>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>8</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onSlave>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>SDI_READY</spirit:logicalName>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>out</spirit:direction>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onSlave>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>SDI_VALID</spirit:logicalName>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>out</spirit:direction>
-				</spirit:onSlave>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>SDI_DATA</spirit:logicalName>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>8</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>8</spirit:width>
-					<spirit:direction>out</spirit:direction>
-				</spirit:onSlave>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>SYNC_READY</spirit:logicalName>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>out</spirit:direction>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onSlave>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>SYNC_VALID</spirit:logicalName>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>out</spirit:direction>
-				</spirit:onSlave>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>SYNC_DATA</spirit:logicalName>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>8</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>8</spirit:width>
-					<spirit:direction>out</spirit:direction>
-				</spirit:onSlave>
-			</spirit:wire>
-		</spirit:port>
-	</spirit:ports>
+<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>interface</spirit:library>
+  <spirit:name>spi_engine_ctrl_rtl</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_ctrl" spirit:version="1.0"/>
+  <spirit:ports>
+    <spirit:port>
+      <spirit:logicalName>cmd_ready</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>cmd_valid</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>cmd_data</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>16</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>16</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sdo_ready</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sdo_valid</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sdo_data</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sdi_ready</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sdi_valid</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sdi_data</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sync_ready</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sync_valid</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sync_data</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>8</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>8</spirit:width>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+  </spirit:ports>
 </spirit:abstractionDefinition>
diff --git a/adi_library/spi_engine/interfaces/spi_engine_ctrl_v1_0.sv b/adi_library/spi_engine/interfaces/spi_engine_ctrl_v1_0.sv
new file mode 100644
index 00000000..8202f20b
--- /dev/null
+++ b/adi_library/spi_engine/interfaces/spi_engine_ctrl_v1_0.sv
@@ -0,0 +1,100 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+`ifndef spi_engine_ctrl_v1_0
+`define spi_engine_ctrl_v1_0
+
+package parameter_structs;
+
+  typedef struct packed {
+      bit    portEnabled;
+      integer    portWidth;
+  }portConfig;
+
+  typedef struct packed {
+    // <typeName> <LogicalName> = {<enablement>, <width>}
+    portConfig sdo_data;
+    portConfig sdi_data;
+  }spi_engine_ctrl_v1_0_port_configuration;
+
+  parameter spi_engine_ctrl_v1_0_port_configuration spi_engine_ctrl_v1_0_default_port_configuration = '{sdo_data:'{1, -1}, sdi_data:'{1, -1}};
+
+endpackage
+
+interface spi_engine_ctrl_v1_0 #(parameter_structs::spi_engine_ctrl_v1_0_port_configuration port_configuration)();
+  logic cmd_ready;                                                       // 
+  logic cmd_valid;                                                       // 
+  logic [15:0] cmd_data;                                                  // 
+  logic sdo_ready;                                                       // 
+  logic sdo_valid;                                                       // 
+  logic [port_configuration.sdo_data.portWidth-1:0] sdo_data;            // 
+  logic sdi_ready;                                                       // 
+  logic sdi_valid;                                                       // 
+  logic [port_configuration.sdi_data.portWidth-1:0] sdi_data;            // 
+  logic sync_ready;                                                      // 
+  logic sync_valid;                                                      // 
+  logic [7:0] sync_data;                                                 // 
+
+  modport MASTER (
+    input cmd_ready, sdo_ready, sdi_valid, sdi_data, sync_valid, sync_data, 
+    output cmd_valid, cmd_data, sdo_valid, sdo_data, sdi_ready, sync_ready
+    );
+
+  modport SLAVE (
+    input cmd_valid, cmd_data, sdo_valid, sdo_data, sdi_ready, sync_ready, 
+    output cmd_ready, sdo_ready, sdi_valid, sdi_data, sync_valid, sync_data
+    );
+
+  modport MONITOR (
+    input cmd_ready, cmd_valid, cmd_data, sdo_ready, sdo_valid, sdo_data, sdi_ready, sdi_valid, sdi_data, sync_ready, sync_valid, sync_data
+    );
+
+endinterface // spi_engine_ctrl_v1_0
+
+`endif
\ No newline at end of file
diff --git a/adi_library/spi_engine/interfaces/spi_engine_offload_ctrl.xml b/adi_library/spi_engine/interfaces/spi_engine_offload_ctrl.xml
index 5a8a05ea..6037dfed 100644
--- a/adi_library/spi_engine/interfaces/spi_engine_offload_ctrl.xml
+++ b/adi_library/spi_engine/interfaces/spi_engine_offload_ctrl.xml
@@ -1,13 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com"
-		xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
-		xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
-	<spirit:vendor>analog.com</spirit:vendor>
-	<spirit:library>interface</spirit:library>
-	<spirit:name>spi_engine_offload_ctrl</spirit:name>
-	<spirit:version>1.0</spirit:version>
-	<spirit:directConnection>false</spirit:directConnection>
-	<spirit:isAddressable>false</spirit:isAddressable>
-	<spirit:maxMasters>1</spirit:maxMasters>
-	<spirit:maxSlaves>1</spirit:maxSlaves>
+<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>interface</spirit:library>
+  <spirit:name>spi_engine_offload_ctrl</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:directConnection>false</spirit:directConnection>
+  <spirit:isAddressable>false</spirit:isAddressable>
+  <spirit:maxMasters>1</spirit:maxMasters>
+  <spirit:maxSlaves>1</spirit:maxSlaves>
 </spirit:busDefinition>
diff --git a/adi_library/spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml b/adi_library/spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
index 82013432..7f203683 100644
--- a/adi_library/spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
+++ b/adi_library/spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
@@ -1,158 +1,148 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com"
-		xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
-		xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
-	<spirit:vendor>analog.com</spirit:vendor>
-	<spirit:library>interface</spirit:library>
-	<spirit:name>spi_engine_offload_ctrl_rtl</spirit:name>
-	<spirit:version>1.0</spirit:version>
-	<spirit:busType spirit:vendor="analog.com"
-			spirit:library="interface"
-			spirit:name="spi_engine_offload_ctrl"
-			spirit:version="1.0"/>
-	<spirit:ports>
-		<spirit:port>
-			<spirit:logicalName>CMD_WR_EN</spirit:logicalName>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onSlave>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>CMD_WR_DATA</spirit:logicalName>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>16</spirit:width>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>16</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onSlave>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>SDO_WR_EN</spirit:logicalName>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>optional</spirit:presence>
-					<spirit:width>1</spirit:width>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>optional</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onSlave>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>SDO_WR_DATA</spirit:logicalName>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>optional</spirit:presence>
-					<spirit:width>8</spirit:width>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>optional</spirit:presence>
-					<spirit:width>8</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onSlave>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>ENABLE</spirit:logicalName>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onSlave>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>MEM_RESET</spirit:logicalName>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onSlave>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>ENABLED</spirit:logicalName>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-				</spirit:onSlave>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>SYNC_READY</spirit:logicalName>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>out</spirit:direction>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onSlave>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>SYNC_VALID</spirit:logicalName>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>out</spirit:direction>
-				</spirit:onSlave>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>SYNC_DATA</spirit:logicalName>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>8</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>8</spirit:width>
-					<spirit:direction>out</spirit:direction>
-				</spirit:onSlave>
-			</spirit:wire>
-		</spirit:port>
-	</spirit:ports>
+<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>interface</spirit:library>
+  <spirit:name>spi_engine_offload_ctrl_rtl</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_offload_ctrl" spirit:version="1.0"/>
+  <spirit:ports>
+    <spirit:port>
+      <spirit:logicalName>cmd_wr_en</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>cmd_wr_data</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>16</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>16</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sdo_wr_en</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sdo_wr_data</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>mem_reset</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>enable</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>enabled</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sync_ready</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sync_valid</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sync_data</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>8</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>8</spirit:width>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+  </spirit:ports>
 </spirit:abstractionDefinition>
diff --git a/adi_library/spi_engine/interfaces/spi_engine_offload_ctrl_v1_0.sv b/adi_library/spi_engine/interfaces/spi_engine_offload_ctrl_v1_0.sv
new file mode 100644
index 00000000..da40f317
--- /dev/null
+++ b/adi_library/spi_engine/interfaces/spi_engine_offload_ctrl_v1_0.sv
@@ -0,0 +1,97 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+`ifndef spi_engine_offload_ctrl_v1_0
+`define spi_engine_offload_ctrl_v1_0
+
+package parameter_structs;
+
+  typedef struct packed {
+      bit    portEnabled;
+      integer    portWidth;
+  }portConfig;
+
+  typedef struct packed {
+    // <typeName> <LogicalName> = {<enablement>, <width>}
+    portConfig sdo_wr_data;
+  }spi_engine_offload_ctrl_v1_0_port_configuration;
+
+  parameter spi_engine_offload_ctrl_v1_0_port_configuration spi_engine_offload_ctrl_v1_0_default_port_configuration = '{sdo_wr_data:'{1, -1}};
+
+endpackage
+
+interface spi_engine_offload_ctrl_v1_0 #(parameter_structs::spi_engine_offload_ctrl_v1_0_port_configuration port_configuration)();
+  logic cmd_wr_en;                                                             // 
+  logic [15:0] cmd_wr_data;                                                     // 
+  logic sdo_wr_en;                                                             // 
+  logic [port_configuration.sdo_wr_data.portWidth-1:0] sdo_wr_data;            // 
+  logic mem_reset;                                                             // 
+  logic enable;                                                                // 
+  logic enabled;                                                               // 
+  logic sync_ready;                                                            // 
+  logic sync_valid;                                                            // 
+  logic [7:0] sync_data;                                                       // 
+
+  modport MASTER (
+    input enabled, sync_valid, sync_data, 
+    output cmd_wr_en, cmd_wr_data, sdo_wr_en, sdo_wr_data, mem_reset, enable, sync_ready
+    );
+
+  modport SLAVE (
+    input cmd_wr_en, cmd_wr_data, sdo_wr_en, sdo_wr_data, mem_reset, enable, sync_ready, 
+    output enabled, sync_valid, sync_data
+    );
+
+  modport MONITOR (
+    input cmd_wr_en, cmd_wr_data, sdo_wr_en, sdo_wr_data, mem_reset, enable, enabled, sync_ready, sync_valid, sync_data
+    );
+
+endinterface // spi_engine_offload_ctrl_v1_0
+
+`endif
\ No newline at end of file
diff --git a/adi_library/spi_engine/interfaces/spi_engine_rtl.xml b/adi_library/spi_engine/interfaces/spi_engine_rtl.xml
new file mode 100644
index 00000000..0ebefde1
--- /dev/null
+++ b/adi_library/spi_engine/interfaces/spi_engine_rtl.xml
@@ -0,0 +1,90 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>analog.com</spirit:vendor>
+  <spirit:library>interface</spirit:library>
+  <spirit:name>spi_engine_rtl</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine" spirit:version="1.0"/>
+  <spirit:ports>
+    <spirit:port>
+      <spirit:logicalName>sclk</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sdo</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sdo_t</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>sdi</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>cs</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+    <spirit:port>
+      <spirit:logicalName>three_wire</spirit:logicalName>
+      <spirit:wire>
+        <spirit:onMaster>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+        </spirit:onMaster>
+        <spirit:onSlave>
+          <spirit:presence>required</spirit:presence>
+          <spirit:width>1</spirit:width>
+          <spirit:direction>in</spirit:direction>
+        </spirit:onSlave>
+      </spirit:wire>
+    </spirit:port>
+  </spirit:ports>
+</spirit:abstractionDefinition>
diff --git a/adi_library/spi_engine/interfaces/spi_engine_v1_0.sv b/adi_library/spi_engine/interfaces/spi_engine_v1_0.sv
new file mode 100644
index 00000000..57e8e046
--- /dev/null
+++ b/adi_library/spi_engine/interfaces/spi_engine_v1_0.sv
@@ -0,0 +1,94 @@
+// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of AMD and is protected under U.S. and international copyright
+// and other intellectual property laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// AMD, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) AMD shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or AMD had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// AMD products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of AMD products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+`ifndef spi_engine_v1_0
+`define spi_engine_v1_0
+
+package parameter_structs;
+
+  typedef struct packed {
+      bit    portEnabled;
+      integer    portWidth;
+  }portConfig;
+
+  typedef struct packed {
+    // <typeName> <LogicalName> = {<enablement>, <width>}
+    portConfig sdi;
+    portConfig cs;
+  }spi_engine_v1_0_port_configuration;
+
+  parameter spi_engine_v1_0_port_configuration spi_engine_v1_0_default_port_configuration = '{sdi:'{1, -1}, cs:'{1, -1}};
+
+endpackage
+
+interface spi_engine_v1_0 #(parameter_structs::spi_engine_v1_0_port_configuration port_configuration)();
+  logic sclk;                                                  // 
+  logic sdo;                                                   // 
+  logic sdo_t;                                                 // 
+  logic [port_configuration.sdi.portWidth-1:0] sdi;            // 
+  logic [port_configuration.cs.portWidth-1:0] cs;              // 
+  logic three_wire;                                            // 
+
+  modport MASTER (
+    input sdi, 
+    output sclk, sdo, sdo_t, cs, three_wire
+    );
+
+  modport SLAVE (
+    input sclk, sdo, sdo_t, cs, three_wire, 
+    output sdi
+    );
+
+  modport MONITOR (
+    input sclk, sdo, sdo_t, sdi, cs, three_wire
+    );
+
+endinterface // spi_engine_v1_0
+
+`endif
\ No newline at end of file
diff --git a/adi_library/spi_engine/interfaces/spi_master.xml b/adi_library/spi_engine/interfaces/spi_master.xml
deleted file mode 100644
index b03644e6..00000000
--- a/adi_library/spi_engine/interfaces/spi_master.xml
+++ /dev/null
@@ -1,14 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com"
-		xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
-		xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
-	<spirit:vendor>analog.com</spirit:vendor>
-	<spirit:library>interface</spirit:library>
-	<spirit:name>spi_master</spirit:name>
-	<spirit:version>1.0</spirit:version>
-	<spirit:directConnection>false</spirit:directConnection>
-	<spirit:isAddressable>false</spirit:isAddressable>
-	<spirit:maxMasters>1</spirit:maxMasters>
-	<spirit:maxSlaves>1</spirit:maxSlaves>
-	<spirit:description>SPI Engine physical interface</spirit:description>
-</spirit:busDefinition>
diff --git a/adi_library/spi_engine/interfaces/spi_master_rtl.xml b/adi_library/spi_engine/interfaces/spi_master_rtl.xml
deleted file mode 100644
index 3c406305..00000000
--- a/adi_library/spi_engine/interfaces/spi_master_rtl.xml
+++ /dev/null
@@ -1,112 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com"
-		xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009"
-		xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
-	<spirit:vendor>analog.com</spirit:vendor>
-	<spirit:library>interface</spirit:library>
-	<spirit:name>spi_master_rtl</spirit:name>
-	<spirit:version>1.0</spirit:version>
-	<spirit:busType spirit:vendor="analog.com" 
-			spirit:library="interface" 
-			spirit:name="spi_master" 
-			spirit:version="1.0"/>
-	<spirit:ports>
-		<spirit:port>
-			<spirit:logicalName>SCLK</spirit:logicalName>
-			<spirit:description>SPI clock</spirit:description>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>out</spirit:direction>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>required</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onSlave>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>SDI</spirit:logicalName>
-			<spirit:description>Serial data in</spirit:description>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>optional</spirit:presence>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>optional</spirit:presence>
-					<spirit:direction>out</spirit:direction>
-				</spirit:onSlave>
-			        <spirit:defaultValue>0</spirit:defaultValue>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>SDO</spirit:logicalName>
-			<spirit:description>Serial data out</spirit:description>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>optional</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>out</spirit:direction>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>optional</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onSlave>
-			        <spirit:defaultValue>0</spirit:defaultValue>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>SDO_T</spirit:logicalName>
-			<spirit:description>Serial data out three state controle line</spirit:description>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>optional</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>out</spirit:direction>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>optional</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onSlave>
-			        <spirit:defaultValue>0</spirit:defaultValue>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>THREE_WIRE</spirit:logicalName>
-			<spirit:description>Three wire mode</spirit:description>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>optional</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>out</spirit:direction>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>optional</spirit:presence>
-					<spirit:width>1</spirit:width>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onSlave>
-			        <spirit:defaultValue>0</spirit:defaultValue>
-			</spirit:wire>
-		</spirit:port>
-		<spirit:port>
-			<spirit:logicalName>CS</spirit:logicalName>
-			<spirit:description>Chip select</spirit:description>
-			<spirit:wire>
-				<spirit:onMaster>
-					<spirit:presence>required</spirit:presence>
-					<spirit:direction>out</spirit:direction>
-				</spirit:onMaster>
-				<spirit:onSlave>
-					<spirit:presence>required</spirit:presence>
-					<spirit:direction>in</spirit:direction>
-				</spirit:onSlave>
-			        <spirit:defaultValue>0</spirit:defaultValue>
-			</spirit:wire>
-		</spirit:port>
-	</spirit:ports>
-</spirit:abstractionDefinition>
diff --git a/adi_library/spi_engine/scripts/spi_engine.tcl b/adi_library/spi_engine/scripts/spi_engine.tcl
index f59a7db1..ec08f5be 100644
--- a/adi_library/spi_engine/scripts/spi_engine.tcl
+++ b/adi_library/spi_engine/scripts/spi_engine.tcl
@@ -1,9 +1,9 @@
 ###############################################################################
-## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2020-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {num_cs 1} {num_sdi 1} {num_sdo 1} {sdi_delay 0} {echo_sclk 0}} {
+proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {num_cs 1} {num_sdi 1} {num_sdo 1} {sdi_delay 0} {echo_sclk 0} {cmd_mem_addr_width 4} {data_mem_addr_width 4} {sdi_fifo_addr_width 5} {sdo_fifo_addr_width 5} {sync_fifo_addr_width 4} {cmd_fifo_addr_width 4}} {
   puts "echo_sclk: $echo_sclk"
 
   create_bd_cell -type hier $name
@@ -19,7 +19,7 @@ proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {n
   create_bd_pin -dir I -type rst resetn
   create_bd_pin -dir I trigger
   create_bd_pin -dir O irq
-  create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi
+  create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 m_spi
   create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_sample
 
   set execution "${name}_execution"
@@ -40,11 +40,19 @@ proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {n
   ad_ip_parameter $axi_regmap CONFIG.NUM_OFFLOAD 1
   ad_ip_parameter $axi_regmap CONFIG.NUM_OF_SDI $num_sdi
   ad_ip_parameter $axi_regmap CONFIG.ASYNC_SPI_CLK $async_spi_clk
+  ad_ip_parameter $axi_regmap CONFIG.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH $cmd_mem_addr_width
+  ad_ip_parameter $axi_regmap CONFIG.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH $data_mem_addr_width
+  ad_ip_parameter $axi_regmap CONFIG.SDI_FIFO_ADDRESS_WIDTH $sdi_fifo_addr_width
+  ad_ip_parameter $axi_regmap CONFIG.SDO_FIFO_ADDRESS_WIDTH $sdo_fifo_addr_width
+  ad_ip_parameter $axi_regmap CONFIG.SYNC_FIFO_ADDRESS_WIDTH $sync_fifo_addr_width
+  ad_ip_parameter $axi_regmap CONFIG.CMD_FIFO_ADDRESS_WIDTH $cmd_fifo_addr_width
 
   ad_ip_instance spi_engine_offload $offload
   ad_ip_parameter $offload CONFIG.DATA_WIDTH $data_width
   ad_ip_parameter $offload CONFIG.ASYNC_SPI_CLK $async_spi_clk
   ad_ip_parameter $offload CONFIG.NUM_OF_SDI $num_sdi
+  ad_ip_parameter $offload CONFIG.CMD_MEM_ADDRESS_WIDTH $cmd_mem_addr_width
+  ad_ip_parameter $offload CONFIG.SDO_MEM_ADDRESS_WIDTH $data_mem_addr_width
 
   ad_ip_instance spi_engine_interconnect $interconnect
   ad_ip_parameter $interconnect CONFIG.DATA_WIDTH $data_width
diff --git a/adi_library/spi_engine/spi_axis_reorder/Makefile b/adi_library/spi_engine/spi_axis_reorder/Makefile
index af8fe5be..2c87b01a 100644
--- a/adi_library/spi_engine/spi_axis_reorder/Makefile
+++ b/adi_library/spi_engine/spi_axis_reorder/Makefile
@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################
diff --git a/adi_library/spi_engine/spi_axis_reorder/component.xml b/adi_library/spi_engine/spi_axis_reorder/component.xml
index b928aa2b..76af2bf0 100644
--- a/adi_library/spi_engine/spi_axis_reorder/component.xml
+++ b/adi_library/spi_engine/spi_axis_reorder/component.xml
@@ -134,7 +134,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>6f89b3dc</spirit:value>
+            <spirit:value>d53c278f</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -150,7 +150,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>6f89b3dc</spirit:value>
+            <spirit:value>d53c278f</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -300,7 +300,7 @@
       <spirit:file>
         <spirit:name>spi_axis_reorder.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_6f89b3dc</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_d53c278f</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -370,11 +370,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:52:42Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:10:20Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="a930cd95"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="afbeddb7"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="db78853a"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="197f2558"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="f0fce92c"/>
diff --git a/adi_library/spi_engine/spi_axis_reorder/spi_axis_reorder.v b/adi_library/spi_engine/spi_axis_reorder/spi_axis_reorder.v
index 04a3356d..91df111f 100644
--- a/adi_library/spi_engine/spi_axis_reorder/spi_axis_reorder.v
+++ b/adi_library/spi_engine/spi_axis_reorder/spi_axis_reorder.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/spi_engine/spi_axis_reorder/spi_axis_reorder.xpr b/adi_library/spi_engine/spi_axis_reorder/spi_axis_reorder.xpr
index c951eaf2..41b4321a 100644
--- a/adi_library/spi_engine/spi_axis_reorder/spi_axis_reorder.xpr
+++ b/adi_library/spi_engine/spi_axis_reorder/spi_axis_reorder.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/spi_engine/spi_axis_reorder/spi_axis_reorder.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/spi_engine/spi_axis_reorder/spi_axis_reorder.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="e752d664dfd2410e84c9f4ba2321dd08"/>
+    <Option Name="Id" Val="3fc861695bd64c55a3491830fcd815ba"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -154,21 +153,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -181,7 +180,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/spi_engine/spi_engine_execution/Makefile b/adi_library/spi_engine/spi_engine_execution/Makefile
index 0bd32b44..30f20717 100644
--- a/adi_library/spi_engine/spi_engine_execution/Makefile
+++ b/adi_library/spi_engine/spi_engine_execution/Makefile
@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################
@@ -11,10 +11,12 @@ GENERIC_DEPS += spi_engine_execution.v
 XILINX_DEPS += spi_engine_execution_constr.ttcl
 XILINX_DEPS += spi_engine_execution_ip.tcl
 
+XILINX_DEPS += ../../spi_engine/interfaces/spi_engine.xml
 XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
 XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
-XILINX_DEPS += ../../spi_engine/interfaces/spi_master.xml
-XILINX_DEPS += ../../spi_engine/interfaces/spi_master_rtl.xml
+XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_rtl.xml
+
+XILINX_INTERFACE_DEPS += spi_engine/interfaces
 
 INTEL_DEPS += spi_engine_execution_hw.tcl
 
diff --git a/adi_library/spi_engine/spi_engine_execution/component.xml b/adi_library/spi_engine/spi_engine_execution/component.xml
index 311ff360..b08f86cc 100644
--- a/adi_library/spi_engine/spi_engine_execution/component.xml
+++ b/adi_library/spi_engine/spi_engine_execution/component.xml
@@ -13,7 +13,7 @@
       <spirit:portMaps>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>CMD_READY</spirit:name>
+            <spirit:name>cmd_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>cmd_ready</spirit:name>
@@ -21,7 +21,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>CMD_VALID</spirit:name>
+            <spirit:name>cmd_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>cmd_valid</spirit:name>
@@ -29,7 +29,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>CMD_DATA</spirit:name>
+            <spirit:name>cmd_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>cmd</spirit:name>
@@ -37,7 +37,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO_READY</spirit:name>
+            <spirit:name>sdo_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sdo_data_ready</spirit:name>
@@ -45,7 +45,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO_VALID</spirit:name>
+            <spirit:name>sdo_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sdo_data_valid</spirit:name>
@@ -53,7 +53,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO_DATA</spirit:name>
+            <spirit:name>sdo_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sdo_data</spirit:name>
@@ -61,7 +61,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDI_READY</spirit:name>
+            <spirit:name>sdi_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sdi_data_ready</spirit:name>
@@ -69,7 +69,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDI_VALID</spirit:name>
+            <spirit:name>sdi_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sdi_data_valid</spirit:name>
@@ -77,7 +77,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDI_DATA</spirit:name>
+            <spirit:name>sdi_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sdi_data</spirit:name>
@@ -85,7 +85,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_READY</spirit:name>
+            <spirit:name>sync_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sync_ready</spirit:name>
@@ -93,7 +93,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_VALID</spirit:name>
+            <spirit:name>sync_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sync_valid</spirit:name>
@@ -101,7 +101,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_DATA</spirit:name>
+            <spirit:name>sync_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sync</spirit:name>
@@ -161,13 +161,13 @@
     </spirit:busInterface>
     <spirit:busInterface>
       <spirit:name>spi</spirit:name>
-      <spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_master" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_master_rtl" spirit:version="1.0"/>
+      <spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_rtl" spirit:version="1.0"/>
       <spirit:master/>
       <spirit:portMaps>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SCLK</spirit:name>
+            <spirit:name>sclk</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sclk</spirit:name>
@@ -175,7 +175,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDI</spirit:name>
+            <spirit:name>sdi</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sdi</spirit:name>
@@ -183,7 +183,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO</spirit:name>
+            <spirit:name>sdo</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sdo</spirit:name>
@@ -191,7 +191,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO_T</spirit:name>
+            <spirit:name>sdo_t</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sdo_t</spirit:name>
@@ -199,7 +199,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>THREE_WIRE</spirit:name>
+            <spirit:name>three_wire</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>three_wire</spirit:name>
@@ -207,7 +207,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>CS</spirit:name>
+            <spirit:name>cs</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>cs</spirit:name>
@@ -280,7 +280,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>4f3438ce</spirit:value>
+            <spirit:value>8ce35280</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -296,7 +296,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>4f3438ce</spirit:value>
+            <spirit:value>8ce35280</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -442,9 +442,6 @@
               <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
-          <spirit:driver>
-            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
-          </spirit:driver>
         </spirit:wire>
       </spirit:port>
       <spirit:port>
@@ -613,9 +610,6 @@
               <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
-          <spirit:driver>
-            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
-          </spirit:driver>
         </spirit:wire>
       </spirit:port>
       <spirit:port>
@@ -716,7 +710,7 @@
       <spirit:file>
         <spirit:name>spi_engine_execution.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_4f3438ce</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_8ce35280</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -797,12 +791,12 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/peripherals/spi_engine/engine</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:52:49Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:10:29Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="b4974010"/>
-      <xilinx:checksum xilinx:scope="ports" xilinx:value="c2e40dde"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="7c5528bd"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="17dd883f"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="0dd4e337"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="0194bdcd"/>
     </xilinx:packagingInfo>
diff --git a/adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v b/adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v
index 418d2f01..d046d4df 100644
--- a/adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v
+++ b/adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -76,10 +76,11 @@ module spi_engine_execution #(
   output reg three_wire
 );
 
-  localparam CMD_TRANSFER = 2'b00;
-  localparam CMD_CHIPSELECT = 2'b01;
-  localparam CMD_WRITE = 2'b10;
-  localparam CMD_MISC = 2'b11;
+  localparam CMD_TRANSFER = 3'b000;
+  localparam CMD_CHIPSELECT = 3'b001;
+  localparam CMD_WRITE = 3'b010;
+  localparam CMD_MISC = 3'b011;
+  localparam CMD_CS_INV = 3'b100;
 
   localparam MISC_SYNC = 1'b0;
   localparam MISC_SLEEP = 1'b1;
@@ -134,6 +135,8 @@ module spi_engine_execution #(
   reg cpol = DEFAULT_SPI_CFG[1];
   reg [7:0] clk_div = DEFAULT_CLK_DIV;
 
+  reg [NUM_OF_CS-1:0] cs_inv_mask_reg = 'h0;
+
   reg sdo_enabled = 1'b0;
   reg sdi_enabled = 1'b0;
 
@@ -141,12 +144,12 @@ module spi_engine_execution #(
 
   reg [SDI_DELAY+1:0] trigger_rx_d = {(SDI_DELAY+2){1'b0}};
 
-  wire [1:0] inst = cmd[13:12];
-  wire [1:0] inst_d1 = cmd_d1[13:12];
+  wire [2:0] inst = cmd[14:12];
+  wire [2:0] inst_d1 = cmd_d1[14:12];
 
   wire exec_cmd = cmd_ready && cmd_valid;
   wire exec_transfer_cmd = exec_cmd && inst == CMD_TRANSFER;
-
+  wire exec_cs_inv_cmd = exec_cmd && inst == CMD_CS_INV;
   wire exec_write_cmd = exec_cmd && inst == CMD_WRITE;
   wire exec_chipselect_cmd = exec_cmd && inst == CMD_CHIPSELECT;
   wire exec_misc_cmd = exec_cmd && inst == CMD_MISC;
@@ -159,6 +162,7 @@ module spi_engine_execution #(
   wire cs_sleep_counter_compare;
   wire cs_sleep_early_exit;
   reg cs_sleep_repeat;
+  reg cs_active;
 
   wire io_ready1;
   wire io_ready2;
@@ -305,11 +309,21 @@ module spi_engine_execution #(
     end
   end
 
+  always @(posedge clk ) begin
+    if (resetn == 1'b0) begin
+      cs_inv_mask_reg <= 'h0;
+    end else begin
+      if (exec_cs_inv_cmd == 1'b1) begin
+        cs_inv_mask_reg <= cmd[NUM_OF_CS-1:0];
+      end
+    end
+  end
+
   always @(posedge clk) begin
     if (resetn == 1'b0) begin
       cs <= 'hff;
     end else if (cs_gen) begin
-      cs <= cmd_d1[NUM_OF_CS-1:0];
+      cs <= cmd_d1[NUM_OF_CS-1:0]^cs_inv_mask_reg[NUM_OF_CS-1:0];
     end
   end
 
@@ -420,7 +434,14 @@ module spi_engine_execution #(
   // used to latch the MISO lines, improving the overall timing margin of the
   // interface.
 
-  wire cs_active_s = (inst_d1 == CMD_CHIPSELECT) & ~(&cmd_d1[NUM_OF_CS-1:0]);
+  always @(posedge clk) begin
+    if (!resetn) begin // set cs_active during reset for a cycle to clear shift reg
+      cs_active <= 1;
+    end else begin
+      cs_active <= ~(&cmd_d1[NUM_OF_CS-1:0]) & cs_gen;
+    end
+  end
+
   genvar i;
 
   // NOTE: SPI configuration (CPOL/PHA) is only hardware configurable at this point
@@ -438,8 +459,8 @@ module spi_engine_execution #(
       for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
         reg [DATA_WIDTH-1:0] data_sdi_shift;
 
-        always @(negedge echo_sclk or posedge cs_active_s) begin
-          if (cs_active_s) begin
+        always @(negedge echo_sclk or posedge cs_active) begin
+          if (cs_active) begin
             data_sdi_shift <= 0;
           end else begin
             data_sdi_shift <= {data_sdi_shift, sdi[i]};
@@ -454,8 +475,8 @@ module spi_engine_execution #(
 
       end
 
-      always @(posedge echo_sclk or posedge cs_active_s) begin
-        if (cs_active_s == 1'b1) begin
+      always @(posedge echo_sclk or posedge cs_active) begin
+        if (cs_active) begin
           sdi_counter <= 8'b0;
           sdi_counter_d <= 8'b0;
         end else begin
@@ -469,8 +490,8 @@ module spi_engine_execution #(
       // MISO shift register runs on positive echo_sclk
       for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
         reg [DATA_WIDTH-1:0] data_sdi_shift;
-        always @(posedge echo_sclk or posedge cs_active_s) begin
-          if (cs_active_s) begin
+        always @(posedge echo_sclk or posedge cs_active) begin
+          if (cs_active) begin
             data_sdi_shift <= 0;
           end else begin
             data_sdi_shift <= {data_sdi_shift, sdi[i]};
@@ -483,8 +504,8 @@ module spi_engine_execution #(
         end
       end
 
-      always @(posedge echo_sclk or posedge cs_active_s) begin
-        if (cs_active_s == 1'b1) begin
+      always @(posedge echo_sclk or posedge cs_active) begin
+        if (cs_active) begin
           sdi_counter <= 8'b0;
           sdi_counter_d <= 8'b0;
         end else begin
@@ -503,7 +524,7 @@ module spi_engine_execution #(
 
     reg [3:0] last_sdi_bit_m = 4'b0;
     always @(posedge clk) begin
-      if (cs_active_s) begin
+      if (cs_active) begin
         last_sdi_bit_m <= 4'b0;
       end else begin
         last_sdi_bit_m <= {last_sdi_bit_m, last_sdi_bit};
@@ -511,7 +532,7 @@ module spi_engine_execution #(
     end
 
     always @(posedge clk) begin
-      if (cs_active_s) begin
+      if (cs_active) begin
         sdi_data_valid <= 1'b0;
       end else if (sdi_enabled == 1'b1 &&
                    last_sdi_bit_m[3] == 1'b0 &&
@@ -523,7 +544,7 @@ module spi_engine_execution #(
     end
 
     always @(posedge clk) begin
-      if (cs_active_s) begin
+      if (cs_active) begin
         num_of_transfers <= 8'b0;
       end else begin
         if (cmd_d1[15:12] == 4'b0) begin
@@ -533,7 +554,7 @@ module spi_engine_execution #(
     end
 
     always @(posedge clk) begin
-      if (cs_active_s) begin
+      if (cs_active) begin
         sdi_transfer_counter <= 0;
       end else if (last_sdi_bit_m[2] == 1'b0 &&
                    last_sdi_bit_m[1] == 1'b1) begin
@@ -554,7 +575,7 @@ module spi_engine_execution #(
       reg [DATA_WIDTH-1:0] data_sdi_shift;
 
       always @(posedge clk) begin
-        if (cs_active_s) begin
+        if (cs_active) begin
           data_sdi_shift <= 0;
         end else begin
           if (trigger_rx_s == 1'b1) begin
diff --git a/adi_library/spi_engine/spi_engine_execution/spi_engine_execution.xpr b/adi_library/spi_engine/spi_engine_execution/spi_engine_execution.xpr
index eaf39f03..30456c88 100644
--- a/adi_library/spi_engine/spi_engine_execution/spi_engine_execution.xpr
+++ b/adi_library/spi_engine/spi_engine_execution/spi_engine_execution.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/spi_engine/spi_engine_execution/spi_engine_execution.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/spi_engine/spi_engine_execution/spi_engine_execution.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="1f06667fc09742279c2aaecc7fa6d70e"/>
+    <Option Name="Id" Val="00911a71ecb04d8a81905b8675308ae8"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -155,21 +154,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -182,7 +181,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl b/adi_library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl
index 84c16d7c..7c5b4871 100644
--- a/adi_library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl
+++ b/adi_library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -26,31 +26,31 @@ adi_add_bus "ctrl" "slave" \
 	"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
 	"analog.com:interface:spi_engine_ctrl:1.0" \
 	{
-		{"cmd_ready" "CMD_READY"} \
-		{"cmd_valid" "CMD_VALID"} \
-		{"cmd" "CMD_DATA"} \
-		{"sdo_data_ready" "SDO_READY"} \
-		{"sdo_data_valid" "SDO_VALID"} \
-		{"sdo_data" "SDO_DATA"} \
-		{"sdi_data_ready" "SDI_READY"} \
-		{"sdi_data_valid" "SDI_VALID"} \
-		{"sdi_data" "SDI_DATA"} \
-		{"sync_ready" "SYNC_READY"} \
-		{"sync_valid" "SYNC_VALID"} \
-		{"sync" "SYNC_DATA"} \
+		{"cmd_ready" "cmd_ready"} \
+		{"cmd_valid" "cmd_valid"} \
+		{"cmd" "cmd_data"} \
+		{"sdo_data_ready" "sdo_ready"} \
+		{"sdo_data_valid" "sdo_valid"} \
+		{"sdo_data" "sdo_data"} \
+		{"sdi_data_ready" "sdi_ready"} \
+		{"sdi_data_valid" "sdi_valid"} \
+		{"sdi_data" "sdi_data"} \
+		{"sync_ready" "sync_ready"} \
+		{"sync_valid" "sync_valid"} \
+		{"sync" "sync_data"} \
 	}
 adi_add_bus_clock "clk" "ctrl" "resetn"
 
 adi_add_bus "spi" "master" \
-	"analog.com:interface:spi_master_rtl:1.0" \
-	"analog.com:interface:spi_master:1.0" \
+	"analog.com:interface:spi_engine_rtl:1.0" \
+	"analog.com:interface:spi_engine:1.0" \
 	{
-		{"sclk" "SCLK"} \
-		{"sdi" "SDI"} \
-		{"sdo" "SDO"} \
-		{"sdo_t" "SDO_T"} \
-		{"three_wire" "THREE_WIRE"} \
-		{"cs" "CS"} \
+		{"sclk" "sclk"} \
+		{"sdi" "sdi"} \
+		{"sdo" "sdo"} \
+		{"sdo_t" "sdo_t"} \
+		{"three_wire" "three_wire"} \
+		{"cs" "cs"} \
 	}
 adi_add_bus_clock "clk" "spi" "resetn"
 
diff --git a/adi_library/spi_engine/spi_engine_interconnect/Makefile b/adi_library/spi_engine/spi_engine_interconnect/Makefile
index 6624efa0..4b660e6d 100644
--- a/adi_library/spi_engine/spi_engine_interconnect/Makefile
+++ b/adi_library/spi_engine/spi_engine_interconnect/Makefile
@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################
@@ -13,6 +13,8 @@ XILINX_DEPS += spi_engine_interconnect_ip.tcl
 XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
 XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
 
+XILINX_INTERFACE_DEPS += spi_engine/interfaces
+
 INTEL_DEPS += spi_engine_interconnect_hw.tcl
 
 include ../../scripts/library.mk
diff --git a/adi_library/spi_engine/spi_engine_interconnect/component.xml b/adi_library/spi_engine/spi_engine_interconnect/component.xml
index 9c927203..4d5d0b57 100644
--- a/adi_library/spi_engine/spi_engine_interconnect/component.xml
+++ b/adi_library/spi_engine/spi_engine_interconnect/component.xml
@@ -13,7 +13,7 @@
       <spirit:portMaps>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>CMD_READY</spirit:name>
+            <spirit:name>cmd_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>m_cmd_ready</spirit:name>
@@ -21,7 +21,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>CMD_VALID</spirit:name>
+            <spirit:name>cmd_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>m_cmd_valid</spirit:name>
@@ -29,7 +29,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>CMD_DATA</spirit:name>
+            <spirit:name>cmd_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>m_cmd_data</spirit:name>
@@ -37,7 +37,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO_READY</spirit:name>
+            <spirit:name>sdo_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>m_sdo_ready</spirit:name>
@@ -45,7 +45,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO_VALID</spirit:name>
+            <spirit:name>sdo_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>m_sdo_valid</spirit:name>
@@ -53,7 +53,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO_DATA</spirit:name>
+            <spirit:name>sdo_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>m_sdo_data</spirit:name>
@@ -61,7 +61,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDI_READY</spirit:name>
+            <spirit:name>sdi_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>m_sdi_ready</spirit:name>
@@ -69,7 +69,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDI_VALID</spirit:name>
+            <spirit:name>sdi_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>m_sdi_valid</spirit:name>
@@ -77,7 +77,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDI_DATA</spirit:name>
+            <spirit:name>sdi_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>m_sdi_data</spirit:name>
@@ -85,7 +85,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_READY</spirit:name>
+            <spirit:name>sync_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>m_sync_ready</spirit:name>
@@ -93,7 +93,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_VALID</spirit:name>
+            <spirit:name>sync_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>m_sync_valid</spirit:name>
@@ -101,7 +101,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_DATA</spirit:name>
+            <spirit:name>sync_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>m_sync</spirit:name>
@@ -167,7 +167,7 @@
       <spirit:portMaps>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>CMD_READY</spirit:name>
+            <spirit:name>cmd_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s0_cmd_ready</spirit:name>
@@ -175,7 +175,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>CMD_VALID</spirit:name>
+            <spirit:name>cmd_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s0_cmd_valid</spirit:name>
@@ -183,7 +183,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>CMD_DATA</spirit:name>
+            <spirit:name>cmd_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s0_cmd_data</spirit:name>
@@ -191,7 +191,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO_READY</spirit:name>
+            <spirit:name>sdo_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s0_sdo_ready</spirit:name>
@@ -199,7 +199,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO_VALID</spirit:name>
+            <spirit:name>sdo_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s0_sdo_valid</spirit:name>
@@ -207,7 +207,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO_DATA</spirit:name>
+            <spirit:name>sdo_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s0_sdo_data</spirit:name>
@@ -215,7 +215,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDI_READY</spirit:name>
+            <spirit:name>sdi_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s0_sdi_ready</spirit:name>
@@ -223,7 +223,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDI_VALID</spirit:name>
+            <spirit:name>sdi_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s0_sdi_valid</spirit:name>
@@ -231,7 +231,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDI_DATA</spirit:name>
+            <spirit:name>sdi_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s0_sdi_data</spirit:name>
@@ -239,7 +239,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_READY</spirit:name>
+            <spirit:name>sync_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s0_sync_ready</spirit:name>
@@ -247,7 +247,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_VALID</spirit:name>
+            <spirit:name>sync_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s0_sync_valid</spirit:name>
@@ -255,7 +255,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_DATA</spirit:name>
+            <spirit:name>sync_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s0_sync</spirit:name>
@@ -321,7 +321,7 @@
       <spirit:portMaps>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>CMD_READY</spirit:name>
+            <spirit:name>cmd_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s1_cmd_ready</spirit:name>
@@ -329,7 +329,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>CMD_VALID</spirit:name>
+            <spirit:name>cmd_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s1_cmd_valid</spirit:name>
@@ -337,7 +337,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>CMD_DATA</spirit:name>
+            <spirit:name>cmd_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s1_cmd_data</spirit:name>
@@ -345,7 +345,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO_READY</spirit:name>
+            <spirit:name>sdo_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s1_sdo_ready</spirit:name>
@@ -353,7 +353,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO_VALID</spirit:name>
+            <spirit:name>sdo_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s1_sdo_valid</spirit:name>
@@ -361,7 +361,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO_DATA</spirit:name>
+            <spirit:name>sdo_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s1_sdo_data</spirit:name>
@@ -369,7 +369,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDI_READY</spirit:name>
+            <spirit:name>sdi_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s1_sdi_ready</spirit:name>
@@ -377,7 +377,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDI_VALID</spirit:name>
+            <spirit:name>sdi_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s1_sdi_valid</spirit:name>
@@ -385,7 +385,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDI_DATA</spirit:name>
+            <spirit:name>sdi_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s1_sdi_data</spirit:name>
@@ -393,7 +393,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_READY</spirit:name>
+            <spirit:name>sync_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s1_sync_ready</spirit:name>
@@ -401,7 +401,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_VALID</spirit:name>
+            <spirit:name>sync_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s1_sync_valid</spirit:name>
@@ -409,7 +409,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_DATA</spirit:name>
+            <spirit:name>sync_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>s1_sync</spirit:name>
@@ -482,7 +482,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>d4ae3839</spirit:value>
+            <spirit:value>e614a53f</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -498,7 +498,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>d4ae3839</spirit:value>
+            <spirit:value>e614a53f</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -687,9 +687,6 @@
               <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
-          <spirit:driver>
-            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
-          </spirit:driver>
         </spirit:wire>
       </spirit:port>
       <spirit:port>
@@ -884,9 +881,6 @@
               <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
-          <spirit:driver>
-            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
-          </spirit:driver>
         </spirit:wire>
       </spirit:port>
       <spirit:port>
@@ -1065,9 +1059,6 @@
               <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
-          <spirit:driver>
-            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
-          </spirit:driver>
         </spirit:wire>
       </spirit:port>
       <spirit:port>
@@ -1107,7 +1098,7 @@
       <spirit:file>
         <spirit:name>spi_engine_interconnect.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_d4ae3839</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_e614a53f</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1182,12 +1173,12 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/peripherals/spi_engine/interconnect</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:52:56Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:10:37Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="0b7a3255"/>
-      <xilinx:checksum xilinx:scope="ports" xilinx:value="c4f8ac06"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="decb81c1"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="6faa013d"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="9165e5ab"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="c4388edd"/>
     </xilinx:packagingInfo>
diff --git a/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v b/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v
index 85d1d1d4..9b2fa47f 100644
--- a/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v
+++ b/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr b/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr
index a29644b1..a29c1c55 100644
--- a/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr
+++ b/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="d07593d6329248f7b3897d72eb22855e"/>
+    <Option Name="Id" Val="6694bc3256f740b39a40b8b208e5d73a"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -154,21 +153,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -181,7 +180,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.tcl b/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.tcl
index 49e19b6e..650a72c0 100644
--- a/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.tcl
+++ b/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.tcl
@@ -24,18 +24,18 @@ adi_add_bus "m_ctrl" "master" \
 	"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
 	"analog.com:interface:spi_engine_ctrl:1.0" \
 	{ \
-		{"m_cmd_ready" "CMD_READY"} \
-		{"m_cmd_valid" "CMD_VALID"} \
-		{"m_cmd_data" "CMD_DATA"} \
-		{"m_sdo_ready" "SDO_READY"} \
-		{"m_sdo_valid" "SDO_VALID"} \
-		{"m_sdo_data" "SDO_DATA"} \
-		{"m_sdi_ready" "SDI_READY"} \
-		{"m_sdi_valid" "SDI_VALID"} \
-		{"m_sdi_data" "SDI_DATA"} \
-		{"m_sync_ready" "SYNC_READY"} \
-		{"m_sync_valid" "SYNC_VALID"} \
-		{"m_sync" "SYNC_DATA"} \
+		{"m_cmd_ready" "cmd_ready"} \
+		{"m_cmd_valid" "cmd_valid"} \
+		{"m_cmd_data" "cmd_data"} \
+		{"m_sdo_ready" "sdo_ready"} \
+		{"m_sdo_valid" "sdo_valid"} \
+		{"m_sdo_data" "sdo_data"} \
+		{"m_sdi_ready" "sdi_ready"} \
+		{"m_sdi_valid" "sdi_valid"} \
+		{"m_sdi_data" "sdi_data"} \
+		{"m_sync_ready" "sync_ready"} \
+		{"m_sync_valid" "sync_valid"} \
+		{"m_sync" "sync_data"} \
 	}
 adi_add_bus_clock "clk" "m_ctrl" "resetn"
 
@@ -44,18 +44,18 @@ foreach prefix [list "s0" "s1"] {
 		"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
 		"analog.com:interface:spi_engine_ctrl:1.0" \
 		[list \
-			[list [format "%s_cmd_ready" $prefix] "CMD_READY"] \
-			[list [format "%s_cmd_valid" $prefix] "CMD_VALID"] \
-			[list [format "%s_cmd_data" $prefix] "CMD_DATA"] \
-			[list [format "%s_sdo_ready" $prefix] "SDO_READY"] \
-			[list [format "%s_sdo_valid" $prefix] "SDO_VALID"] \
-			[list [format "%s_sdo_data" $prefix] "SDO_DATA"] \
-			[list [format "%s_sdi_ready" $prefix] "SDI_READY"] \
-			[list [format "%s_sdi_valid" $prefix] "SDI_VALID"] \
-			[list [format "%s_sdi_data" $prefix] "SDI_DATA"] \
-			[list [format "%s_sync_ready" $prefix] "SYNC_READY"] \
-			[list [format "%s_sync_valid" $prefix] "SYNC_VALID"] \
-			[list [format "%s_sync" $prefix] "SYNC_DATA"] \
+			[list [format "%s_cmd_ready" $prefix] "cmd_ready"] \
+			[list [format "%s_cmd_valid" $prefix] "cmd_valid"] \
+			[list [format "%s_cmd_data" $prefix] "cmd_data"] \
+			[list [format "%s_sdo_ready" $prefix] "sdo_ready"] \
+			[list [format "%s_sdo_valid" $prefix] "sdo_valid"] \
+			[list [format "%s_sdo_data" $prefix] "sdo_data"] \
+			[list [format "%s_sdi_ready" $prefix] "sdi_ready"] \
+			[list [format "%s_sdi_valid" $prefix] "sdi_valid"] \
+			[list [format "%s_sdi_data" $prefix] "sdi_data"] \
+			[list [format "%s_sync_ready" $prefix] "sync_ready"] \
+			[list [format "%s_sync_valid" $prefix] "sync_valid"] \
+			[list [format "%s_sync" $prefix] "sync_data"] \
 		]
 	adi_add_bus_clock "clk" [format "%s_ctrl" $prefix] "resetn"
 }
diff --git a/adi_library/spi_engine/spi_engine_offload/Makefile b/adi_library/spi_engine/spi_engine_offload/Makefile
index 0a7e97da..360c5802 100644
--- a/adi_library/spi_engine/spi_engine_offload/Makefile
+++ b/adi_library/spi_engine/spi_engine_offload/Makefile
@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################
@@ -18,7 +18,10 @@ XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml
 
 XILINX_LIB_DEPS += util_cdc
 
+XILINX_INTERFACE_DEPS += spi_engine/interfaces
+
 INTEL_DEPS += ../../util_cdc/sync_bits.v
+INTEL_DEPS += ../../util_cdc/sync_event.v
 INTEL_DEPS += spi_engine_offload_hw.tcl
 
 include ../../scripts/library.mk
diff --git a/adi_library/spi_engine/spi_engine_offload/component.xml b/adi_library/spi_engine/spi_engine_offload/component.xml
index 9266627e..239c76f1 100644
--- a/adi_library/spi_engine/spi_engine_offload/component.xml
+++ b/adi_library/spi_engine/spi_engine_offload/component.xml
@@ -13,7 +13,7 @@
       <spirit:portMaps>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>CMD_READY</spirit:name>
+            <spirit:name>cmd_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>cmd_ready</spirit:name>
@@ -21,7 +21,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>CMD_VALID</spirit:name>
+            <spirit:name>cmd_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>cmd_valid</spirit:name>
@@ -29,7 +29,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>CMD_DATA</spirit:name>
+            <spirit:name>cmd_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>cmd</spirit:name>
@@ -37,7 +37,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO_READY</spirit:name>
+            <spirit:name>sdo_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sdo_data_ready</spirit:name>
@@ -45,7 +45,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO_VALID</spirit:name>
+            <spirit:name>sdo_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sdo_data_valid</spirit:name>
@@ -53,7 +53,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO_DATA</spirit:name>
+            <spirit:name>sdo_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sdo_data</spirit:name>
@@ -61,7 +61,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDI_READY</spirit:name>
+            <spirit:name>sdi_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sdi_data_ready</spirit:name>
@@ -69,7 +69,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDI_VALID</spirit:name>
+            <spirit:name>sdi_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sdi_data_valid</spirit:name>
@@ -77,7 +77,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDI_DATA</spirit:name>
+            <spirit:name>sdi_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sdi_data</spirit:name>
@@ -85,7 +85,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_READY</spirit:name>
+            <spirit:name>sync_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sync_ready</spirit:name>
@@ -93,7 +93,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_VALID</spirit:name>
+            <spirit:name>sync_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sync_valid</spirit:name>
@@ -101,7 +101,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_DATA</spirit:name>
+            <spirit:name>sync_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>sync_data</spirit:name>
@@ -117,7 +117,7 @@
       <spirit:portMaps>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>CMD_WR_EN</spirit:name>
+            <spirit:name>cmd_wr_en</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>ctrl_cmd_wr_en</spirit:name>
@@ -125,7 +125,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>CMD_WR_DATA</spirit:name>
+            <spirit:name>cmd_wr_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>ctrl_cmd_wr_data</spirit:name>
@@ -133,7 +133,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO_WR_EN</spirit:name>
+            <spirit:name>sdo_wr_en</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>ctrl_sdo_wr_en</spirit:name>
@@ -141,7 +141,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SDO_WR_DATA</spirit:name>
+            <spirit:name>sdo_wr_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>ctrl_sdo_wr_data</spirit:name>
@@ -149,7 +149,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>ENABLE</spirit:name>
+            <spirit:name>enable</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>ctrl_enable</spirit:name>
@@ -157,7 +157,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>ENABLED</spirit:name>
+            <spirit:name>enabled</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>ctrl_enabled</spirit:name>
@@ -165,7 +165,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>MEM_RESET</spirit:name>
+            <spirit:name>mem_reset</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>ctrl_mem_reset</spirit:name>
@@ -173,7 +173,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_READY</spirit:name>
+            <spirit:name>sync_ready</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>status_sync_ready</spirit:name>
@@ -181,7 +181,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_VALID</spirit:name>
+            <spirit:name>sync_valid</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>status_sync_valid</spirit:name>
@@ -189,7 +189,7 @@
         </spirit:portMap>
         <spirit:portMap>
           <spirit:logicalPort>
-            <spirit:name>SYNC_DATA</spirit:name>
+            <spirit:name>sync_data</spirit:name>
           </spirit:logicalPort>
           <spirit:physicalPort>
             <spirit:name>status_sync_data</spirit:name>
@@ -320,7 +320,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>54da56d5</spirit:value>
+            <spirit:value>415947b9</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -339,7 +339,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>54da56d5</spirit:value>
+            <spirit:value>415947b9</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -842,7 +842,7 @@
       <spirit:file>
         <spirit:name>spi_engine_offload.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_54da56d5</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_415947b9</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -941,11 +941,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/peripherals/spi_engine/offload</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:53:04Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:10:45Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="8689cb20"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="582124d3"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="2756ddd5"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ae1a9eae"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="e2e1ec4a"/>
diff --git a/adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v b/adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v
index a15dfc18..b1ab7190 100644
--- a/adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v
+++ b/adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -96,9 +96,12 @@ module spi_engine_offload #(
   reg [15:0] cmd_mem[0:2**CMD_MEM_ADDRESS_WIDTH-1];
   reg [(DATA_WIDTH-1):0] sdo_mem[0:2**SDO_MEM_ADDRESS_WIDTH-1];
 
+  reg trigger_last_reg;
+
   wire [15:0] cmd_int_s;
   wire [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr_next;
   wire spi_enable;
+  wire trigger_posedge;
 
   assign cmd_valid = spi_active;
   assign sdo_data_valid = spi_active;
@@ -126,7 +129,7 @@ module spi_engine_offload #(
   wire [ 7:0] spi_sync_id_init_s;
 
   always @(posedge ctrl_clk) begin
-    if (ctrl_mem_reset == 1'b1) begin
+    if (ctrl_mem_reset) begin
       ctrl_sync_id_init <= 8'b0;
       ctrl_sync_id_load <= 1'b0;
     end else begin
@@ -160,7 +163,7 @@ module spi_engine_offload #(
     .out_bits(spi_sync_id_init_s));
 
   always @(posedge spi_clk) begin
-    if (spi_resetn == 1'b0) begin
+    if (!spi_resetn) begin
       spi_sync_id_counter <= 8'b0;
     end else begin
       if (spi_sync_id_load_s) begin
@@ -198,9 +201,9 @@ module spi_engine_offload #(
   reg spi_enabled = 1'b0;
 
   always @(posedge ctrl_clk) begin
-    if (ctrl_enable == 1'b1) begin
+    if (ctrl_enable) begin
       ctrl_do_enable <= 1'b1;
-    end else if (ctrl_is_enabled == 1'b1) begin
+    end else if (ctrl_is_enabled) begin
       ctrl_do_enable <= 1'b0;
     end
   end
@@ -247,57 +250,67 @@ module spi_engine_offload #(
     .out_bits(trigger_s));
 
   always @(posedge spi_clk) begin
-    if (spi_resetn == 1'b0) begin
+    if (!spi_resetn) begin
+      trigger_last_reg <= 1'b0;
+    end else begin
+      trigger_last_reg <= trigger_s;
+    end
+  end
+
+  assign trigger_posedge = trigger_s && !trigger_last_reg;
+
+  always @(posedge spi_clk) begin
+    if (!spi_resetn) begin
       spi_active <= 1'b0;
     end else begin
-      if (spi_active == 1'b0) begin
+      if (!spi_active) begin
         // start offload when we have a valid trigger, offload is enabled and
         // the DMA is enabled
-        if (trigger_s == 1'b1 && spi_enable == 1'b1 && offload_sdi_ready == 1'b1)
+        if (trigger_posedge && spi_enable && offload_sdi_ready)
           spi_active <= 1'b1;
-      end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin
+      end else if (cmd_ready && (spi_cmd_rd_addr_next == ctrl_cmd_wr_addr)) begin
         spi_active <= 1'b0;
       end
     end
   end
 
   always @(posedge spi_clk) begin
-    if (cmd_valid == 1'b0) begin
+    if (!cmd_valid) begin
       spi_cmd_rd_addr <= 'h00;
-    end else if (cmd_ready == 1'b1) begin
+    end else if (cmd_ready) begin
       spi_cmd_rd_addr <= spi_cmd_rd_addr_next;
     end
   end
 
   always @(posedge spi_clk) begin
-    if (spi_active == 1'b0) begin
+    if (!spi_active) begin
       spi_sdo_rd_addr <= 'h00;
-    end else if (sdo_data_ready == 1'b1) begin
+    end else if (sdo_data_ready) begin
       spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1;
     end
   end
 
   always @(posedge ctrl_clk) begin
-    if (ctrl_mem_reset == 1'b1)
+    if (ctrl_mem_reset)
       ctrl_cmd_wr_addr <= 'h00;
-    else if (ctrl_cmd_wr_en == 1'b1)
+    else if (ctrl_cmd_wr_en)
       ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1'b1;
   end
 
   always @(posedge ctrl_clk) begin
-    if (ctrl_cmd_wr_en == 1'b1)
+    if (ctrl_cmd_wr_en)
       cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data;
   end
 
   always @(posedge ctrl_clk) begin
-    if (ctrl_mem_reset == 1'b1)
+    if (ctrl_mem_reset)
       ctrl_sdo_wr_addr <= 'h00;
-    else if (ctrl_sdo_wr_en == 1'b1)
+    else if (ctrl_sdo_wr_en)
       ctrl_sdo_wr_addr <= ctrl_sdo_wr_addr + 1'b1;
   end
 
   always @(posedge ctrl_clk) begin
-    if (ctrl_sdo_wr_en == 1'b1)
+    if (ctrl_sdo_wr_en)
       sdo_mem[ctrl_sdo_wr_addr] <= ctrl_sdo_wr_data;
   end
 
diff --git a/adi_library/spi_engine/spi_engine_offload/spi_engine_offload.xpr b/adi_library/spi_engine/spi_engine_offload/spi_engine_offload.xpr
index 19013a72..89a761e0 100644
--- a/adi_library/spi_engine/spi_engine_offload/spi_engine_offload.xpr
+++ b/adi_library/spi_engine/spi_engine_offload/spi_engine_offload.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/spi_engine/spi_engine_offload/spi_engine_offload.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/spi_engine/spi_engine_offload/spi_engine_offload.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="30b4a7c406754ea493b787146654d616"/>
+    <Option Name="Id" Val="36637aefd0314394950d6379054a8d3c"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -155,21 +154,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -182,7 +181,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl b/adi_library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl
index 77887f61..fa3ed09f 100644
--- a/adi_library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl
+++ b/adi_library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl
@@ -10,6 +10,7 @@ source ../../scripts/adi_ip_intel.tcl
 ad_ip_create spi_engine_offload {SPI Engine Offload} p_elaboration
 ad_ip_files spi_engine_offload [list\
   $ad_hdl_dir/library/util_cdc/sync_bits.v \
+  $ad_hdl_dir/library/util_cdc/sync_event.v \
   spi_engine_offload.v]
 
 # parameters
diff --git a/adi_library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl b/adi_library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl
index 4f230890..c3e6510a 100644
--- a/adi_library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl
+++ b/adi_library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl
@@ -32,34 +32,34 @@ adi_add_bus "spi_engine_ctrl" "master" \
 	"analog.com:interface:spi_engine_ctrl_rtl:1.0" \
 	"analog.com:interface:spi_engine_ctrl:1.0" \
 	{
-		{"cmd_ready" "CMD_READY"} \
-		{"cmd_valid" "CMD_VALID"} \
-		{"cmd" "CMD_DATA"} \
-		{"sdo_data_ready" "SDO_READY"} \
-		{"sdo_data_valid" "SDO_VALID"} \
-		{"sdo_data" "SDO_DATA"} \
-		{"sdi_data_ready" "SDI_READY"} \
-		{"sdi_data_valid" "SDI_VALID"} \
-		{"sdi_data" "SDI_DATA"} \
-		{"sync_ready" "SYNC_READY"} \
-		{"sync_valid" "SYNC_VALID"} \
-		{"sync_data" "SYNC_DATA"} \
+		{"cmd_ready" "cmd_ready"} \
+		{"cmd_valid" "cmd_valid"} \
+		{"cmd" "cmd_data"} \
+		{"sdo_data_ready" "sdo_ready"} \
+		{"sdo_data_valid" "sdo_valid"} \
+		{"sdo_data" "sdo_data"} \
+		{"sdi_data_ready" "sdi_ready"} \
+		{"sdi_data_valid" "sdi_valid"} \
+		{"sdi_data" "sdi_data"} \
+		{"sync_ready" "sync_ready"} \
+		{"sync_valid" "sync_valid"} \
+		{"sync_data" "sync_data"} \
 	}
 
 adi_add_bus "spi_engine_offload_ctrl" "slave" \
 	"analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \
 	"analog.com:interface:spi_engine_offload_ctrl:1.0" \
 	{ \
-		{ "ctrl_cmd_wr_en" "CMD_WR_EN"} \
-		{ "ctrl_cmd_wr_data" "CMD_WR_DATA"} \
-		{ "ctrl_sdo_wr_en" "SDO_WR_EN"} \
-		{ "ctrl_sdo_wr_data" "SDO_WR_DATA"} \
-		{ "ctrl_enable" "ENABLE"} \
-		{ "ctrl_enabled" "ENABLED"} \
-		{ "ctrl_mem_reset" "MEM_RESET"} \
-		{ "status_sync_ready" "SYNC_READY"} \
-		{ "status_sync_valid" "SYNC_VALID"} \
-		{ "status_sync_data" "SYNC_DATA"} \
+		{ "ctrl_cmd_wr_en" "cmd_wr_en"} \
+		{ "ctrl_cmd_wr_data" "cmd_wr_data"} \
+		{ "ctrl_sdo_wr_en" "sdo_wr_en"} \
+		{ "ctrl_sdo_wr_data" "sdo_wr_data"} \
+		{ "ctrl_enable" "enable"} \
+		{ "ctrl_enabled" "enabled"} \
+		{ "ctrl_mem_reset" "mem_reset"} \
+		{ "status_sync_ready" "sync_ready"} \
+		{ "status_sync_valid" "sync_valid"} \
+		{ "status_sync_data" "sync_data"} \
 	}
 
 adi_add_bus "offload_sdi" "master" \
diff --git a/adi_library/sysid_rom/component.xml b/adi_library/sysid_rom/component.xml
index 85649ddf..ea1cb788 100644
--- a/adi_library/sysid_rom/component.xml
+++ b/adi_library/sysid_rom/component.xml
@@ -36,7 +36,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>c025daf5</spirit:value>
+            <spirit:value>176346af</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -52,7 +52,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>c025daf5</spirit:value>
+            <spirit:value>176346af</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -144,7 +144,7 @@
       <spirit:file>
         <spirit:name>sysid_rom.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_c025daf5</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_176346af</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -224,11 +224,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:53:11Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:10:53Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="bdd85203"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="eb28c658"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="95613975"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="95b7d3ef"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="72154e31"/>
diff --git a/adi_library/sysid_rom/sysid_rom.v b/adi_library/sysid_rom/sysid_rom.v
index fd15e993..31562c75 100755
--- a/adi_library/sysid_rom/sysid_rom.v
+++ b/adi_library/sysid_rom/sysid_rom.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/sysid_rom/sysid_rom.xpr b/adi_library/sysid_rom/sysid_rom.xpr
index 6a9800f5..fbf44d6a 100644
--- a/adi_library/sysid_rom/sysid_rom.xpr
+++ b/adi_library/sysid_rom/sysid_rom.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/sysid_rom/sysid_rom.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/sysid_rom/sysid_rom.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="0199d91bcefd41e3b699c96e2d8b3ddd"/>
+    <Option Name="Id" Val="eba16980a0de4f9a92b59e6248633f89"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -154,21 +153,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -181,7 +180,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_adcfifo/component.xml b/adi_library/util_adcfifo/component.xml
index 1ccd34a3..e20ff7d5 100644
--- a/adi_library/util_adcfifo/component.xml
+++ b/adi_library/util_adcfifo/component.xml
@@ -77,7 +77,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>2eb31c0a</spirit:value>
+            <spirit:value>40722f6c</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -96,7 +96,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>f2ab08a6</spirit:value>
+            <spirit:value>b633eec5</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -325,7 +325,7 @@
       <spirit:file>
         <spirit:name>util_adcfifo.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_4808813e</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_da662e4e</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -455,11 +455,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:53:21Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:11:03Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="64f564ba"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="f4830758"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="5dbe3b47"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="55f61cc5"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="d46500ed"/>
diff --git a/adi_library/util_adcfifo/util_adcfifo.v b/adi_library/util_adcfifo/util_adcfifo.v
index f0396d4b..78c184d1 100644
--- a/adi_library/util_adcfifo/util_adcfifo.v
+++ b/adi_library/util_adcfifo/util_adcfifo.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_adcfifo/util_adcfifo.xpr b/adi_library/util_adcfifo/util_adcfifo.xpr
index 1548eb2d..671c590b 100644
--- a/adi_library/util_adcfifo/util_adcfifo.xpr
+++ b/adi_library/util_adcfifo/util_adcfifo.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_adcfifo/util_adcfifo.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_adcfifo/util_adcfifo.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="325c2e37360849ab9fc74387219a4ef9"/>
+    <Option Name="Id" Val="bdb1e6ee11c24f8ebea5e86b6069fc81"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -181,21 +180,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -208,7 +207,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_axis_fifo/component.xml b/adi_library/util_axis_fifo/component.xml
index 1c56f68b..c4d46784 100644
--- a/adi_library/util_axis_fifo/component.xml
+++ b/adi_library/util_axis_fifo/component.xml
@@ -219,7 +219,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>4837ce55</spirit:value>
+            <spirit:value>2735fcaa</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -238,7 +238,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>4837ce55</spirit:value>
+            <spirit:value>2735fcaa</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -667,7 +667,7 @@
       <spirit:file>
         <spirit:name>util_axis_fifo.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_56c88183</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_f51e4483</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -827,11 +827,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/util_axis_fifo</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:45:42Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:01:48Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="59ef6667"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="34474606"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="de18f3ae"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="7abddce6"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="c7e77367"/>
diff --git a/adi_library/util_axis_fifo/util_axis_fifo.v b/adi_library/util_axis_fifo/util_axis_fifo.v
index 20cccf99..a1307791 100644
--- a/adi_library/util_axis_fifo/util_axis_fifo.v
+++ b/adi_library/util_axis_fifo/util_axis_fifo.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -148,8 +148,8 @@ module util_axis_fifo #(
               axis_tlast_d <= s_axis_tlast;
           end
           assign m_axis_tlast = axis_tlast_d;
-
-        end
+        end else
+          assign m_axis_tlast = 'b0;
 
         // TKEEP support
         if (TKEEP_EN) begin
@@ -161,8 +161,8 @@ module util_axis_fifo #(
               axis_tkeep_d <= s_axis_tkeep;
           end
           assign m_axis_tkeep = axis_tkeep_d;
-
-        end
+        end else
+          assign m_axis_tkeep = {DATA_WIDTH/8{1'b1}};
 
     end /* zerodeep */
     else
@@ -205,7 +205,8 @@ module util_axis_fifo #(
           end
         end
         assign m_axis_tlast = axis_tlast_d;
-      end
+      end else
+        assign m_axis_tlast = 'b0;
 
       // TKEEP support
       if (TKEEP_EN) begin
@@ -219,8 +220,8 @@ module util_axis_fifo #(
           end
         end
         assign m_axis_tkeep = axis_tkeep_d;
-
-      end
+      end else
+        assign m_axis_tkeep = {DATA_WIDTH/8{1'b1}};
 
      end /* !ASYNC_CLK */
 
@@ -288,13 +289,17 @@ module util_axis_fifo #(
     end else if (TKEEP_EN) begin
       assign s_axis_data_int_s = {s_axis_tkeep, s_axis_data};
       assign m_axis_tkeep = m_axis_data_int_s[MEM_WORD-1-:DATA_WIDTH/8];
+      assign m_axis_tlast = 'b0;
       assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0];
     end else if (TLAST_EN) begin
       assign s_axis_data_int_s = {s_axis_tlast, s_axis_data};
+      assign m_axis_tkeep = {DATA_WIDTH/8{1'b1}};
       assign m_axis_tlast = m_axis_data_int_s[DATA_WIDTH];
       assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0];
     end else begin
       assign s_axis_data_int_s = {s_axis_data};
+      assign m_axis_tkeep = {DATA_WIDTH/8{1'b1}};
+      assign m_axis_tlast = 'b0;
       assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0];
     end
 
diff --git a/adi_library/util_axis_fifo/util_axis_fifo.xpr b/adi_library/util_axis_fifo/util_axis_fifo.xpr
index ce9c3591..17174dda 100644
--- a/adi_library/util_axis_fifo/util_axis_fifo.xpr
+++ b/adi_library/util_axis_fifo/util_axis_fifo.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_axis_fifo/util_axis_fifo.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_axis_fifo/util_axis_fifo.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="93170d32d6b94034bdcbbb5a29c61566"/>
+    <Option Name="Id" Val="169c86b56d934501856fcb54a3d932bd"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -176,21 +175,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -203,7 +202,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_axis_fifo/util_axis_fifo_address_generator.v b/adi_library/util_axis_fifo/util_axis_fifo_address_generator.v
index 4e354617..885f8a62 100644
--- a/adi_library/util_axis_fifo/util_axis_fifo_address_generator.v
+++ b/adi_library/util_axis_fifo/util_axis_fifo_address_generator.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_axis_fifo_asym/component.xml b/adi_library/util_axis_fifo_asym/component.xml
index 5ba4b79b..648619a2 100644
--- a/adi_library/util_axis_fifo_asym/component.xml
+++ b/adi_library/util_axis_fifo_asym/component.xml
@@ -206,7 +206,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>94187aef</spirit:value>
+            <spirit:value>6da388ea</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -228,7 +228,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>94187aef</spirit:value>
+            <spirit:value>6da388ea</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -596,7 +596,7 @@
       <spirit:file>
         <spirit:name>util_axis_fifo_asym.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_94187aef</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_6da388ea</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -762,11 +762,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/util_axis_fifo_asym</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:50:07Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:06:59Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="e69cf0b7"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="1ba7ffa9"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="5e0743cc"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="4ac641e5"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="91f73006"/>
diff --git a/adi_library/util_axis_fifo_asym/util_axis_fifo_asym.v b/adi_library/util_axis_fifo_asym/util_axis_fifo_asym.v
index 888f87de..c297d64e 100644
--- a/adi_library/util_axis_fifo_asym/util_axis_fifo_asym.v
+++ b/adi_library/util_axis_fifo_asym/util_axis_fifo_asym.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_axis_fifo_asym/util_axis_fifo_asym.xpr b/adi_library/util_axis_fifo_asym/util_axis_fifo_asym.xpr
index f3bd772c..3d8ba133 100644
--- a/adi_library/util_axis_fifo_asym/util_axis_fifo_asym.xpr
+++ b/adi_library/util_axis_fifo_asym/util_axis_fifo_asym.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_axis_fifo_asym/util_axis_fifo_asym.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_axis_fifo_asym/util_axis_fifo_asym.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="982116b256fe4badaad1b4def00c83e1"/>
+    <Option Name="Id" Val="ce6ef921211d4599aec8918f1369b7ab"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -154,21 +153,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -181,7 +180,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_axis_resize/component.xml b/adi_library/util_axis_resize/component.xml
index 41b2d0f6..6376e08a 100644
--- a/adi_library/util_axis_resize/component.xml
+++ b/adi_library/util_axis_resize/component.xml
@@ -134,7 +134,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>a67c1595</spirit:value>
+            <spirit:value>6714e933</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -150,7 +150,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>a67c1595</spirit:value>
+            <spirit:value>6714e933</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -310,7 +310,7 @@
       <spirit:file>
         <spirit:name>util_axis_resize.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_a67c1595</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_6714e933</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -390,11 +390,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:53:28Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:11:11Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="2f9a7530"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="8f65f334"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="e3cb713c"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="7e409f46"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="27668bc8"/>
diff --git a/adi_library/util_axis_resize/util_axis_resize.v b/adi_library/util_axis_resize/util_axis_resize.v
index 0a5b1042..2a1b4042 100644
--- a/adi_library/util_axis_resize/util_axis_resize.v
+++ b/adi_library/util_axis_resize/util_axis_resize.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_axis_resize/util_axis_resize.xpr b/adi_library/util_axis_resize/util_axis_resize.xpr
index e678208a..6afec6a6 100644
--- a/adi_library/util_axis_resize/util_axis_resize.xpr
+++ b/adi_library/util_axis_resize/util_axis_resize.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_axis_resize/util_axis_resize.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_axis_resize/util_axis_resize.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="cfcd048827be4921bb8f08a933bd5b4e"/>
+    <Option Name="Id" Val="2a5bfe3fd1614e8382d71446a074e01a"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -154,21 +153,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -181,7 +180,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_axis_upscale/component.xml b/adi_library/util_axis_upscale/component.xml
index ab3b4647..a4d8883f 100644
--- a/adi_library/util_axis_upscale/component.xml
+++ b/adi_library/util_axis_upscale/component.xml
@@ -134,7 +134,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>81d2643b</spirit:value>
+            <spirit:value>dcedf3e5</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -150,7 +150,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>81d2643b</spirit:value>
+            <spirit:value>dcedf3e5</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -349,7 +349,7 @@
       <spirit:file>
         <spirit:name>../common/util_axis_upscale.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_81d2643b</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_dcedf3e5</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -429,11 +429,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:53:35Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:11:19Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="5e042eac"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="f6e727ac"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="603297fc"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="7d5d5bf1"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="ba4d064b"/>
diff --git a/adi_library/util_axis_upscale/util_axis_upscale.xpr b/adi_library/util_axis_upscale/util_axis_upscale.xpr
index ccc8b210..0e263d8f 100644
--- a/adi_library/util_axis_upscale/util_axis_upscale.xpr
+++ b/adi_library/util_axis_upscale/util_axis_upscale.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_axis_upscale/util_axis_upscale.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_axis_upscale/util_axis_upscale.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="f4ba2a1810c24c938c60e8f77f603eb0"/>
+    <Option Name="Id" Val="49c80461363947a1a3e716a6cb371ebe"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -154,21 +153,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -181,7 +180,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_bsplit/component.xml b/adi_library/util_bsplit/component.xml
index 25880222..401c148c 100644
--- a/adi_library/util_bsplit/component.xml
+++ b/adi_library/util_bsplit/component.xml
@@ -18,7 +18,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>ada098d6</spirit:value>
+            <spirit:value>7afe3378</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -34,7 +34,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>ada098d6</spirit:value>
+            <spirit:value>7afe3378</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -297,7 +297,7 @@
       <spirit:file>
         <spirit:name>util_bsplit.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_ada098d6</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_7afe3378</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -372,11 +372,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:53:43Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:11:27Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="90d6b8cc"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="70dc1f89"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="14e24645"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="4aeb2c19"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="c3c618f8"/>
diff --git a/adi_library/util_bsplit/util_bsplit.v b/adi_library/util_bsplit/util_bsplit.v
index 4371e2c1..5e924fa6 100644
--- a/adi_library/util_bsplit/util_bsplit.v
+++ b/adi_library/util_bsplit/util_bsplit.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_bsplit/util_bsplit.xpr b/adi_library/util_bsplit/util_bsplit.xpr
index 64c3d463..718e111c 100644
--- a/adi_library/util_bsplit/util_bsplit.xpr
+++ b/adi_library/util_bsplit/util_bsplit.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_bsplit/util_bsplit.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_bsplit/util_bsplit.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="f554c224e5ca486fac44f4b20b67e64b"/>
+    <Option Name="Id" Val="5d0a29e4b5204c0eac9ae316341abe8d"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -154,21 +153,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -181,7 +180,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_cdc/component.xml b/adi_library/util_cdc/component.xml
index 48a8d6b9..b528aace 100644
--- a/adi_library/util_cdc/component.xml
+++ b/adi_library/util_cdc/component.xml
@@ -18,7 +18,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>b5f3c2f0</spirit:value>
+            <spirit:value>c325f2fc</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -34,7 +34,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>b5f3c2f0</spirit:value>
+            <spirit:value>c325f2fc</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -146,7 +146,7 @@
       <spirit:file>
         <spirit:name>sync_event.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_afcd7b7e</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_fece0fbd</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -234,11 +234,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:38:18Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T02:53:53Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="ca7ebdc2"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="977245ef"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="c5b57d4d"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="1f4d93c9"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="c38123f1"/>
diff --git a/adi_library/util_cdc/sync_bits.v b/adi_library/util_cdc/sync_bits.v
index d6bd616c..991a6675 100644
--- a/adi_library/util_cdc/sync_bits.v
+++ b/adi_library/util_cdc/sync_bits.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_cdc/sync_data.v b/adi_library/util_cdc/sync_data.v
index a9f7c1db..6f37cb8b 100644
--- a/adi_library/util_cdc/sync_data.v
+++ b/adi_library/util_cdc/sync_data.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_cdc/sync_event.v b/adi_library/util_cdc/sync_event.v
index 8c93fe5a..33bee1ba 100644
--- a/adi_library/util_cdc/sync_event.v
+++ b/adi_library/util_cdc/sync_event.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_cdc/sync_gray.v b/adi_library/util_cdc/sync_gray.v
index a60e8559..f0cc8986 100644
--- a/adi_library/util_cdc/sync_gray.v
+++ b/adi_library/util_cdc/sync_gray.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_cdc/util_cdc.xpr b/adi_library/util_cdc/util_cdc.xpr
index e50672a4..3b1ccc6c 100644
--- a/adi_library/util_cdc/util_cdc.xpr
+++ b/adi_library/util_cdc/util_cdc.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_cdc/util_cdc.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_cdc/util_cdc.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="de705fbc02644034bb491142792663a8"/>
+    <Option Name="Id" Val="1e688099c41444db97dce5b9c73dc135"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -60,7 +60,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -176,21 +175,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -203,7 +202,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_cic/cic_comb.v b/adi_library/util_cic/cic_comb.v
index de176ceb..7383971f 100644
--- a/adi_library/util_cic/cic_comb.v
+++ b/adi_library/util_cic/cic_comb.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_cic/cic_int.v b/adi_library/util_cic/cic_int.v
index 06fbd8fd..ce49d56e 100644
--- a/adi_library/util_cic/cic_int.v
+++ b/adi_library/util_cic/cic_int.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_cic/component.xml b/adi_library/util_cic/component.xml
index 6a3bb58c..1eda3337 100644
--- a/adi_library/util_cic/component.xml
+++ b/adi_library/util_cic/component.xml
@@ -18,7 +18,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>55312928</spirit:value>
+            <spirit:value>89512e0f</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -34,7 +34,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>55312928</spirit:value>
+            <spirit:value>89512e0f</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -165,7 +165,7 @@
       <spirit:file>
         <spirit:name>cic_comb.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_17b13b1f</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_3aa554dc</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -255,11 +255,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:44:04Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:00:03Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4a862b9e"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="b9be146e"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="6b1ddd6f"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="e21ac4d3"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="1c2efb84"/>
diff --git a/adi_library/util_cic/util_cic.xpr b/adi_library/util_cic/util_cic.xpr
index 05d3d7bf..5bccc8b3 100644
--- a/adi_library/util_cic/util_cic.xpr
+++ b/adi_library/util_cic/util_cic.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_cic/util_cic.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_cic/util_cic.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="6e0efbd536554839aafe6816ea06000d"/>
+    <Option Name="Id" Val="b500cc75e2c24966937eb663f88e1864"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -60,7 +60,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -162,21 +161,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -189,7 +188,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_dacfifo/component.xml b/adi_library/util_dacfifo/component.xml
index d5e0791f..d667933e 100644
--- a/adi_library/util_dacfifo/component.xml
+++ b/adi_library/util_dacfifo/component.xml
@@ -96,7 +96,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>71800a14</spirit:value>
+            <spirit:value>17846ed1</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -112,7 +112,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>fb2fd7ae</spirit:value>
+            <spirit:value>e2931d44</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -373,7 +373,7 @@
       <spirit:file>
         <spirit:name>util_dacfifo.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_3ff18447</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_e8c0ed82</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -444,11 +444,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:53:57Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:11:39Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="1ddd9960"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="89dc634b"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="f31d9715"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="5f16fa27"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="d7f0d96a"/>
diff --git a/adi_library/util_dacfifo/util_dacfifo.v b/adi_library/util_dacfifo/util_dacfifo.v
index e17f9469..493da1c2 100644
--- a/adi_library/util_dacfifo/util_dacfifo.v
+++ b/adi_library/util_dacfifo/util_dacfifo.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_dacfifo/util_dacfifo.xpr b/adi_library/util_dacfifo/util_dacfifo.xpr
index ef9182b4..ab3df8df 100644
--- a/adi_library/util_dacfifo/util_dacfifo.xpr
+++ b/adi_library/util_dacfifo/util_dacfifo.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_dacfifo/util_dacfifo.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_dacfifo/util_dacfifo.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="133dd4c440e542f68a0d273a74be391e"/>
+    <Option Name="Id" Val="22f3e786fb984434a3c8418369e66ddd"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -196,21 +195,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -223,7 +222,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_dacfifo/util_dacfifo_bypass.v b/adi_library/util_dacfifo/util_dacfifo_bypass.v
index eb5e2459..afd6e991 100644
--- a/adi_library/util_dacfifo/util_dacfifo_bypass.v
+++ b/adi_library/util_dacfifo/util_dacfifo_bypass.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_dec256sinc24b/component.xml b/adi_library/util_dec256sinc24b/component.xml
index 327f845c..d57c777a 100644
--- a/adi_library/util_dec256sinc24b/component.xml
+++ b/adi_library/util_dec256sinc24b/component.xml
@@ -58,7 +58,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>82712b89</spirit:value>
+            <spirit:value>3f3eb049</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -74,7 +74,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>82712b89</spirit:value>
+            <spirit:value>3f3eb049</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -188,7 +188,7 @@
       <spirit:file>
         <spirit:name>../common/util_dec256sinc24b.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_82712b89</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_3f3eb049</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -253,11 +253,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:54:12Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:11:47Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="dedd6aeb"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="748c2c80"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="98eed4d1"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="cdc83e90"/>
     </xilinx:packagingInfo>
diff --git a/adi_library/util_dec256sinc24b/util_dec256sinc24b.xpr b/adi_library/util_dec256sinc24b/util_dec256sinc24b.xpr
index c1026e09..4b68cca9 100644
--- a/adi_library/util_dec256sinc24b/util_dec256sinc24b.xpr
+++ b/adi_library/util_dec256sinc24b/util_dec256sinc24b.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_dec256sinc24b/util_dec256sinc24b.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_dec256sinc24b/util_dec256sinc24b.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="06ca8f52e2284679bf0f8b659a553a7d"/>
+    <Option Name="Id" Val="4875a43ba36b49c488a93d69eb13e6a8"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -154,21 +153,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -181,7 +180,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_delay/component.xml b/adi_library/util_delay/component.xml
index cda22d21..d425fbfe 100644
--- a/adi_library/util_delay/component.xml
+++ b/adi_library/util_delay/component.xml
@@ -58,7 +58,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>18c36dfa</spirit:value>
+            <spirit:value>32ca0fba</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -74,7 +74,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>18c36dfa</spirit:value>
+            <spirit:value>32ca0fba</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -170,7 +170,7 @@
       <spirit:file>
         <spirit:name>../common/util_delay.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_18c36dfa</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_32ca0fba</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -245,11 +245,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:54:23Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:11:55Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="9912d2ec"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="778b6da1"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="6da0e9e5"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="3a8b9c4b"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="879c211d"/>
diff --git a/adi_library/util_delay/util_delay.xpr b/adi_library/util_delay/util_delay.xpr
index 6895d2ff..e211f4f8 100644
--- a/adi_library/util_delay/util_delay.xpr
+++ b/adi_library/util_delay/util_delay.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_delay/util_delay.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_delay/util_delay.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="e87bb30d91074553a367c7d8137b230c"/>
+    <Option Name="Id" Val="12cb7d981cc34d59b0fa0588cfcf53b6"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -154,21 +153,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -181,7 +180,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_do_ram/component.xml b/adi_library/util_do_ram/component.xml
index 4b7590b1..f843aed6 100644
--- a/adi_library/util_do_ram/component.xml
+++ b/adi_library/util_do_ram/component.xml
@@ -358,7 +358,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>f913396f</spirit:value>
+            <spirit:value>735a98aa</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -380,7 +380,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>f913396f</spirit:value>
+            <spirit:value>735a98aa</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -883,7 +883,7 @@
       <spirit:file>
         <spirit:name>util_do_ram.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_94f67d2d</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_06ac53d3</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -999,11 +999,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:54:37Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:12:05Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="a2d32e6c"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="2392c602"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="517750cb"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="e2af70cb"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="6db5087f"/>
diff --git a/adi_library/util_do_ram/util_do_ram.v b/adi_library/util_do_ram/util_do_ram.v
index 6e91233b..e1e30eeb 100644
--- a/adi_library/util_do_ram/util_do_ram.v
+++ b/adi_library/util_do_ram/util_do_ram.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -93,6 +93,7 @@ module util_do_ram #(
 
   wire  wr_enable;
   wire  [DST_DATA_WIDTH-1:0] rd_data;
+  wire  [DST_DATA_WIDTH/8-1:0] rd_keep;
   wire  [1:0] rd_fifo_room;
   wire        rd_enable;
   wire        rd_last_beat;
@@ -102,6 +103,7 @@ module util_do_ram #(
   reg [SRC_ADDRESS_WIDTH-1:0] wr_length = 'h0;
   reg [SRC_ADDRESS_WIDTH-1:0] wr_addr = 'h0;
   reg [DST_DATA_WIDTH-1:0]    rd_data_l2 = 'h0;
+  reg [DST_DATA_WIDTH/8-1:0]  rd_keep_l2 = 'h0;
   reg [DST_ADDRESS_WIDTH-1:0] rd_length = 'h0;
   reg [DST_ADDRESS_WIDTH-1:0] rd_addr = 'h0;
   reg rd_pending = 1'b0;
@@ -168,7 +170,7 @@ module util_do_ram #(
     .A_DATA_WIDTH (SRC_DATA_WIDTH),
     .B_ADDRESS_WIDTH (DST_ADDRESS_WIDTH),
     .B_DATA_WIDTH (DST_DATA_WIDTH)
-  ) i_mem (
+  ) i_mem_data (
     .clka (s_axis_aclk),
     .wea (wr_enable),
     .addra (wr_addr),
@@ -179,6 +181,22 @@ module util_do_ram #(
     .addrb (rd_addr),
     .doutb (rd_data));
 
+  ad_mem_asym #(
+    .A_ADDRESS_WIDTH (SRC_ADDRESS_WIDTH),
+    .A_DATA_WIDTH (SRC_DATA_WIDTH/8),
+    .B_ADDRESS_WIDTH (DST_ADDRESS_WIDTH),
+    .B_DATA_WIDTH (DST_DATA_WIDTH/8)
+  ) i_mem_keep (
+    .clka (s_axis_aclk),
+    .wea (wr_enable),
+    .addra (wr_addr),
+    .dina (s_axis_keep),
+
+    .clkb (m_axis_aclk),
+    .reb (1'b1),
+    .addrb (rd_addr),
+    .doutb (rd_keep));
+
   reg rd_active = 1'b0;
   reg [1:0] rd_req_cnt = 2'b0;
   always @(posedge m_axis_aclk) begin
@@ -238,9 +256,14 @@ module util_do_ram #(
   always @(posedge m_axis_aclk) begin
     if (rd_valid_l1)
       rd_data_l2 <= rd_data;
-   end
+  end
 
-   always @(posedge m_axis_aclk) begin
+  always @(posedge m_axis_aclk) begin
+    if (rd_valid_l1)
+      rd_keep_l2 <= rd_keep;
+  end
+
+  always @(posedge m_axis_aclk) begin
     if (rd_valid_l1)
       rd_valid_l2 <= 1'b1;
     else if (rd_fifo_s_ready)
@@ -254,31 +277,33 @@ module util_do_ram #(
 
   // Read datapath to AXIS logic
   util_axis_fifo #(
-    .DATA_WIDTH(DST_DATA_WIDTH+1),
+    .DATA_WIDTH(DST_DATA_WIDTH),
     .ADDRESS_WIDTH(2),
     .ASYNC_CLK(0),
-    .M_AXIS_REGISTERED(0)
+    .M_AXIS_REGISTERED(0),
+    .TLAST_EN(1),
+    .TKEEP_EN(1)
   ) i_rd_fifo (
     .s_axis_aclk(m_axis_aclk),
     .s_axis_aresetn(m_axis_aresetn & rd_request_enable),
     .s_axis_valid(rd_fifo_s_valid),
     .s_axis_ready(rd_fifo_s_ready),
     .s_axis_full(),
-    .s_axis_data({rd_last_l2,rd_data_l2}),
+    .s_axis_data(rd_data_l2),
     .s_axis_room(rd_fifo_room),
-    .s_axis_tkeep(),
-    .s_axis_tlast(),
+    .s_axis_tkeep(rd_keep_l2),
+    .s_axis_tlast(rd_last_l2),
     .s_axis_almost_full(),
 
     .m_axis_aclk(m_axis_aclk),
     .m_axis_aresetn(m_axis_aresetn & rd_request_enable),
     .m_axis_valid(m_axis_valid),
     .m_axis_ready(m_axis_ready),
-    .m_axis_data({m_axis_last,m_axis_data}),
+    .m_axis_data(m_axis_data),
     .m_axis_level(),
     .m_axis_empty(),
-    .m_axis_tkeep(),
-    .m_axis_tlast(),
+    .m_axis_tkeep(m_axis_keep),
+    .m_axis_tlast(m_axis_last),
     .m_axis_almost_empty());
 
 endmodule
diff --git a/adi_library/util_do_ram/util_do_ram.xpr b/adi_library/util_do_ram/util_do_ram.xpr
index 7fd3c91d..bd23bcae 100644
--- a/adi_library/util_do_ram/util_do_ram.xpr
+++ b/adi_library/util_do_ram/util_do_ram.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_do_ram/util_do_ram.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_do_ram/util_do_ram.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="0bf723676944490a9ab3c4490ea9a05f"/>
+    <Option Name="Id" Val="ab4b944285424e52805930350be11e16"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -168,21 +167,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -195,7 +194,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_extract/component.xml b/adi_library/util_extract/component.xml
index a8ba3899..bf54442d 100644
--- a/adi_library/util_extract/component.xml
+++ b/adi_library/util_extract/component.xml
@@ -36,7 +36,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>797a4514</spirit:value>
+            <spirit:value>efde078a</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -52,7 +52,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>797a4514</spirit:value>
+            <spirit:value>efde078a</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -195,7 +195,7 @@
       <spirit:file>
         <spirit:name>util_extract.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_797a4514</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_efde078a</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -270,11 +270,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/util_extract</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:54:45Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:12:13Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="93b4b22e"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="c4cfe2f4"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="ed9c6e09"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="98305203"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="f021692e"/>
diff --git a/adi_library/util_extract/util_extract.v b/adi_library/util_extract/util_extract.v
index 1058e62b..b8fbb24d 100644
--- a/adi_library/util_extract/util_extract.v
+++ b/adi_library/util_extract/util_extract.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_extract/util_extract.xpr b/adi_library/util_extract/util_extract.xpr
index bb6c6e8b..53ab0213 100644
--- a/adi_library/util_extract/util_extract.xpr
+++ b/adi_library/util_extract/util_extract.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_extract/util_extract.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_extract/util_extract.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="9e069dc633e046f1a36fdb08a7a77c30"/>
+    <Option Name="Id" Val="4eb449037e534e5b984b9b51114d0bf0"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -154,21 +153,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -181,7 +180,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_fir_dec/component.xml b/adi_library/util_fir_dec/component.xml
index 13371ecb..f6207485 100644
--- a/adi_library/util_fir_dec/component.xml
+++ b/adi_library/util_fir_dec/component.xml
@@ -21,7 +21,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>df87a941</spirit:value>
+            <spirit:value>0f8f8140</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -40,7 +40,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>df87a941</spirit:value>
+            <spirit:value>0f8f8140</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -196,7 +196,7 @@
       <spirit:file>
         <spirit:name>util_fir_dec.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_ae141850</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_45745699</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -266,11 +266,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:54:53Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:12:22Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="471be0bb"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="921b5421"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="8b602850"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="3d6f9dc5"/>
     </xilinx:packagingInfo>
diff --git a/adi_library/util_fir_dec/util_fir_dec.srcs/sources_1/ip/fir_decim/fir_decim.xci b/adi_library/util_fir_dec/util_fir_dec.srcs/sources_1/ip/fir_decim/fir_decim.xci
index ebdb193d..58b38a42 100644
--- a/adi_library/util_fir_dec/util_fir_dec.srcs/sources_1/ip/fir_decim/fir_decim.xci
+++ b/adi_library/util_fir_dec/util_fir_dec.srcs/sources_1/ip/fir_decim/fir_decim.xci
@@ -3,7 +3,7 @@
   "ip_inst": {
     "xci_name": "fir_decim",
     "component_reference": "xilinx.com:ip:fir_compiler:7.2",
-    "ip_revision": "20",
+    "ip_revision": "22",
     "gen_directory": "../../../../util_fir_dec.gen/sources_1/ip/fir_decim",
     "parameters": {
       "component_parameters": {
@@ -166,6 +166,7 @@
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
         "DEVICE": [ { "value": "xc7vx485t" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
         "PACKAGE": [ { "value": "ffg1157" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
@@ -176,12 +177,12 @@
       },
       "runtime_parameters": {
         "IPCONTEXT": [ { "value": "IP_Flow" } ],
-        "IPREVISION": [ { "value": "20" } ],
+        "IPREVISION": [ { "value": "22" } ],
         "MANAGED": [ { "value": "TRUE" } ],
         "OUTPUTDIR": [ { "value": "../../../../util_fir_dec.gen/sources_1/ip/fir_decim" } ],
         "SELECTEDSIMMODEL": [ { "value": "" } ],
         "SHAREDDIR": [ { "value": "." } ],
-        "SWVERSION": [ { "value": "2023.2.1" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
         "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
       }
     },
diff --git a/adi_library/util_fir_dec/util_fir_dec.v b/adi_library/util_fir_dec/util_fir_dec.v
index 04a68ce2..7d246b91 100644
--- a/adi_library/util_fir_dec/util_fir_dec.v
+++ b/adi_library/util_fir_dec/util_fir_dec.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_fir_dec/util_fir_dec.xpr b/adi_library/util_fir_dec/util_fir_dec.xpr
index 96ef415b..308f8c29 100644
--- a/adi_library/util_fir_dec/util_fir_dec.xpr
+++ b/adi_library/util_fir_dec/util_fir_dec.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_fir_dec/util_fir_dec.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_fir_dec/util_fir_dec.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="d2299c78a4e84b2d8bf8599835981767"/>
+    <Option Name="Id" Val="93c860c176634d42b6034ae3bca62228"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -167,21 +166,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -194,7 +193,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_fir_int/component.xml b/adi_library/util_fir_int/component.xml
index d7a6b09f..2f7c99f2 100644
--- a/adi_library/util_fir_int/component.xml
+++ b/adi_library/util_fir_int/component.xml
@@ -21,7 +21,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>20812f76</spirit:value>
+            <spirit:value>dc4c2051</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -40,7 +40,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>20812f76</spirit:value>
+            <spirit:value>dc4c2051</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -212,7 +212,7 @@
       <spirit:file>
         <spirit:name>util_fir_int.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_cfeb71c7</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_91185ea9</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -282,11 +282,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:55:02Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:12:31Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="cdcaca24"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="13e9b417"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="a2de3ee8"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="08306e01"/>
     </xilinx:packagingInfo>
diff --git a/adi_library/util_fir_int/util_fir_int.srcs/sources_1/ip/fir_interp/fir_interp.xci b/adi_library/util_fir_int/util_fir_int.srcs/sources_1/ip/fir_interp/fir_interp.xci
index 5d03e430..a33966b9 100644
--- a/adi_library/util_fir_int/util_fir_int.srcs/sources_1/ip/fir_interp/fir_interp.xci
+++ b/adi_library/util_fir_int/util_fir_int.srcs/sources_1/ip/fir_interp/fir_interp.xci
@@ -3,7 +3,7 @@
   "ip_inst": {
     "xci_name": "fir_interp",
     "component_reference": "xilinx.com:ip:fir_compiler:7.2",
-    "ip_revision": "20",
+    "ip_revision": "22",
     "gen_directory": "../../../../util_fir_int.gen/sources_1/ip/fir_interp",
     "parameters": {
       "component_parameters": {
@@ -166,6 +166,7 @@
         "BASE_BOARD_PART": [ { "value": "" } ],
         "BOARD_CONNECTIONS": [ { "value": "" } ],
         "DEVICE": [ { "value": "xc7vx485t" } ],
+        "NEXTGEN_VERSAL": [ { "value": "0" } ],
         "PACKAGE": [ { "value": "ffg1157" } ],
         "PREFHDL": [ { "value": "VERILOG" } ],
         "SILICON_REVISION": [ { "value": "" } ],
@@ -176,12 +177,12 @@
       },
       "runtime_parameters": {
         "IPCONTEXT": [ { "value": "IP_Flow" } ],
-        "IPREVISION": [ { "value": "20" } ],
+        "IPREVISION": [ { "value": "22" } ],
         "MANAGED": [ { "value": "TRUE" } ],
         "OUTPUTDIR": [ { "value": "../../../../util_fir_int.gen/sources_1/ip/fir_interp" } ],
         "SELECTEDSIMMODEL": [ { "value": "" } ],
         "SHAREDDIR": [ { "value": "." } ],
-        "SWVERSION": [ { "value": "2023.2.1" } ],
+        "SWVERSION": [ { "value": "2024.1" } ],
         "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
       }
     },
diff --git a/adi_library/util_fir_int/util_fir_int.v b/adi_library/util_fir_int/util_fir_int.v
index 9ad4ab20..34992472 100644
--- a/adi_library/util_fir_int/util_fir_int.v
+++ b/adi_library/util_fir_int/util_fir_int.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_fir_int/util_fir_int.xpr b/adi_library/util_fir_int/util_fir_int.xpr
index 24322152..11d1733a 100644
--- a/adi_library/util_fir_int/util_fir_int.xpr
+++ b/adi_library/util_fir_int/util_fir_int.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_fir_int/util_fir_int.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_fir_int/util_fir_int.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="03bfeccaf22b44a098fc90b465f892ad"/>
+    <Option Name="Id" Val="308d17c39c2345ce9a2f312279c7512b"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -167,21 +166,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -194,7 +193,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_gmii_to_rgmii/component.xml b/adi_library/util_gmii_to_rgmii/component.xml
index 31000c14..94107756 100644
--- a/adi_library/util_gmii_to_rgmii/component.xml
+++ b/adi_library/util_gmii_to_rgmii/component.xml
@@ -244,7 +244,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>4fe18eb9</spirit:value>
+            <spirit:value>cb848287</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -260,7 +260,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>a61fc92b</spirit:value>
+            <spirit:value>2d31abdf</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -676,7 +676,7 @@
       <spirit:file>
         <spirit:name>util_gmii_to_rgmii.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_1fb997f7</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_73d0c2ff</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -770,11 +770,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:55:11Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:12:40Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="09bf3647"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="236e78ff"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="34abb249"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="57c5cf1d"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="bb80d526"/>
diff --git a/adi_library/util_gmii_to_rgmii/mdc_mdio.v b/adi_library/util_gmii_to_rgmii/mdc_mdio.v
index 32099d96..b27f74fc 100644
--- a/adi_library/util_gmii_to_rgmii/mdc_mdio.v
+++ b/adi_library/util_gmii_to_rgmii/mdc_mdio.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v b/adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v
index 8c542b92..2389bc08 100644
--- a/adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v
+++ b/adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.xpr b/adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.xpr
index b4076c45..873a9557 100644
--- a/adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.xpr
+++ b/adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_gmii_to_rgmii/util_gmii_to_rgmii.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_gmii_to_rgmii/util_gmii_to_rgmii.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="5284976e41884aa7a69001d9ac3434cc"/>
+    <Option Name="Id" Val="d601592c6e234134911711fbfda30c3f"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -167,21 +166,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -194,7 +193,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_hbm/component.xml b/adi_library/util_hbm/component.xml
index fa05ed63..ba709d98 100644
--- a/adi_library/util_hbm/component.xml
+++ b/adi_library/util_hbm/component.xml
@@ -5674,7 +5674,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>e53075f6</spirit:value>
+            <spirit:value>adc69daf</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -5696,7 +5696,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>9b7d6e4d</spirit:value>
+            <spirit:value>7348ecf4</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -6696,7 +6696,7 @@
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>HBM_SEGMENTS_PER_MASTER</spirit:name>
         <spirit:displayName>Hbm Segments Per Master</spirit:displayName>
-        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HBM_SEGMENTS_PER_MASTER"/>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.HBM_SEGMENTS_PER_MASTER">8</spirit:value>
       </spirit:modelParameter>
       <spirit:modelParameter spirit:dataType="integer">
         <spirit:name>HBM_SEGMENT_INDEX</spirit:name>
@@ -6818,7 +6818,7 @@
       <spirit:file>
         <spirit:name>util_hbm.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_a4a1e134</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_fc2eb467</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -6948,7 +6948,7 @@
     <spirit:parameter>
       <spirit:name>LENGTH_WIDTH</spirit:name>
       <spirit:displayName>Storage size</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.LENGTH_WIDTH" spirit:choiceRef="choice_pairs_cebf9777">24</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.LENGTH_WIDTH" spirit:choiceRef="choice_pairs_cebf9777">28</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>AXI_PROTOCOL</spirit:name>
@@ -6973,7 +6973,7 @@
     <spirit:parameter>
       <spirit:name>HBM_SEGMENTS_PER_MASTER</spirit:name>
       <spirit:displayName>HBM sections per master</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.HBM_SEGMENTS_PER_MASTER"/>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.HBM_SEGMENTS_PER_MASTER">8</spirit:value>
       <spirit:vendorExtensions>
         <xilinx:parameterInfo>
           <xilinx:enablement>
@@ -7040,11 +7040,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:55:19Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:12:49Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="600a0db5"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="0cf35e7b"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="63780b38"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="10097211"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="cd4bda90"/>
diff --git a/adi_library/util_hbm/gui/util_hbm_v1_0.gtcl b/adi_library/util_hbm/gui/util_hbm_v1_0.gtcl
index 87f28807..a12abb84 100644
--- a/adi_library/util_hbm/gui/util_hbm_v1_0.gtcl
+++ b/adi_library/util_hbm/gui/util_hbm_v1_0.gtcl
@@ -1,4 +1,4 @@
 # This file is automatically written.  Do not modify.
-proc gen_USERPARAMETER_HBM_SEGMENTS_PER_MASTER_VALUE {LENGTH_WIDTH NUM_M } {expr  int(ceil(2**($LENGTH_WIDTH-28) / ${NUM_M}.0)) }
+proc gen_USERPARAMETER_HBM_SEGMENTS_PER_MASTER_VALUE {LENGTH_WIDTH NUM_M } {expr  ceil(2**($LENGTH_WIDTH-28) / ${NUM_M}) }
 proc gen_USERPARAMETER_HBM_SEGMENT_INDEX_ENABLEMENT {MEM_TYPE } {expr $MEM_TYPE == 2}
 proc gen_USERPARAMETER_DDR_BASE_ADDDRESS_ENABLEMENT {MEM_TYPE } {expr $MEM_TYPE == 1}
diff --git a/adi_library/util_hbm/scripts/adi_util_hbm.tcl b/adi_library/util_hbm/scripts/adi_util_hbm.tcl
index 45ddb3a0..1479bb0c 100644
--- a/adi_library/util_hbm/scripts/adi_util_hbm.tcl
+++ b/adi_library/util_hbm/scripts/adi_util_hbm.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -33,12 +33,12 @@ proc ad_create_hbm {ip_name {density "4GB"}} {
   }
 }
 
-proc ad_create_util_hbm {name rx_tx_n src_width dst_width mem_size {axi_data_width 256} {mem_type 2}} {
+proc ad_create_util_hbm {name tx_rx_n src_width dst_width mem_size {axi_data_width 256} {mem_type 2}} {
 
   if {$mem_type == 2} {
     # HBM
     # split converter side bus into multiple AXI masters
-    set number_of_masters [expr int(ceil((${rx_tx_n} == 1 ? ${dst_width}.0 : ${src_width}.0) / ${axi_data_width}.0))]
+    set number_of_masters [expr int(ceil((${tx_rx_n} == 1 ? ${dst_width}.0 : ${src_width}.0) / ${axi_data_width}.0))]
   } else {
     # DDR we have always one master
     set number_of_masters 1
@@ -49,7 +49,7 @@ proc ad_create_util_hbm {name rx_tx_n src_width dst_width mem_size {axi_data_wid
     SRC_DATA_WIDTH $src_width \
     DST_DATA_WIDTH $dst_width \
     AXI_DATA_WIDTH $axi_data_width \
-    TX_RX_N $rx_tx_n \
+    TX_RX_N $tx_rx_n \
     NUM_M $number_of_masters \
     MEM_TYPE $mem_type \
   ]
diff --git a/adi_library/util_hbm/util_hbm.v b/adi_library/util_hbm/util_hbm.v
index d5396d57..73e8c355 100644
--- a/adi_library/util_hbm/util_hbm.v
+++ b/adi_library/util_hbm/util_hbm.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_hbm/util_hbm.xpr b/adi_library/util_hbm/util_hbm.xpr
index 38d01326..5e7e828b 100644
--- a/adi_library/util_hbm/util_hbm.xpr
+++ b/adi_library/util_hbm/util_hbm.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_hbm/util_hbm.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_hbm/util_hbm.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="25ee62de6e2c4594bccbfad815be1926"/>
+    <Option Name="Id" Val="403e7461fe894850b63ec63e1744b067"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -168,21 +167,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -195,7 +194,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_hbm/util_hbm_ip.tcl b/adi_library/util_hbm/util_hbm_ip.tcl
index 00a70410..2637d459 100644
--- a/adi_library/util_hbm/util_hbm_ip.tcl
+++ b/adi_library/util_hbm/util_hbm_ip.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -153,7 +153,7 @@ foreach dir {"SRC" "DST"} {
 
 set_property -dict [list \
     "value_validation_type" "pairs" \
-    "value" "24" \
+    "value" "28" \
     "value_validation_pairs" {\
       "256MB" "28" \
       "512MB" "29" \
@@ -209,7 +209,7 @@ set_property -dict [list \
 # HBM_SEGMENTS_PER_MASTER = Storage size (MB) / 256 (MB) / number of masters
 set_property -dict [list \
     "enablement_value" "false" \
-    "value_tcl_expr" {expr  int(ceil(2**($LENGTH_WIDTH-28) / ${NUM_M}.0)) } \
+    "value_tcl_expr" { ceil(2**($LENGTH_WIDTH-28) / ${NUM_M}) } \
   ] \
   [ipx::get_user_parameters HBM_SEGMENTS_PER_MASTER -of_objects $cc]
 
diff --git a/adi_library/util_i2c_mixer/component.xml b/adi_library/util_i2c_mixer/component.xml
index 2e3f3fd1..f51b3529 100644
--- a/adi_library/util_i2c_mixer/component.xml
+++ b/adi_library/util_i2c_mixer/component.xml
@@ -76,7 +76,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>4ee188af</spirit:value>
+            <spirit:value>c5a06989</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -92,7 +92,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>4ee188af</spirit:value>
+            <spirit:value>c5a06989</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -299,7 +299,7 @@
       <spirit:file>
         <spirit:name>util_i2c_mixer.vhd</spirit:name>
         <spirit:fileType>vhdlSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_4ee188af</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_c5a06989</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -369,11 +369,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:55:27Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:12:57Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="76d104c0"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="55e7b4d1"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="f2bf6bb0"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="b1484132"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="9aed1625"/>
diff --git a/adi_library/util_i2c_mixer/util_i2c_mixer.vhd b/adi_library/util_i2c_mixer/util_i2c_mixer.vhd
index c24d96dd..8c165673 100644
--- a/adi_library/util_i2c_mixer/util_i2c_mixer.vhd
+++ b/adi_library/util_i2c_mixer/util_i2c_mixer.vhd
@@ -26,7 +26,7 @@
 --
 --   2. An ADI specific BSD license, which can be found in the top level directory
 --      of this repository (LICENSE_ADIBSD), and also on-line at:
---      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+--      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 --      This will allow to generate bit files and not release the source code,
 --      as long as it attaches to an ADI device.
 --
diff --git a/adi_library/util_i2c_mixer/util_i2c_mixer.xpr b/adi_library/util_i2c_mixer/util_i2c_mixer.xpr
index 0478c956..c8b1ed70 100644
--- a/adi_library/util_i2c_mixer/util_i2c_mixer.xpr
+++ b/adi_library/util_i2c_mixer/util_i2c_mixer.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_i2c_mixer/util_i2c_mixer.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_i2c_mixer/util_i2c_mixer.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="b8a6ab4cc3254dfb874b0c84486433ec"/>
+    <Option Name="Id" Val="32de3eabbe70471989293f2044ae14ee"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -153,21 +152,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -180,7 +179,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_mfifo/component.xml b/adi_library/util_mfifo/component.xml
index 31e1df83..fc51c4c3 100644
--- a/adi_library/util_mfifo/component.xml
+++ b/adi_library/util_mfifo/component.xml
@@ -96,7 +96,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>d636a054</spirit:value>
+            <spirit:value>a44eb22f</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -112,7 +112,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>d636a054</spirit:value>
+            <spirit:value>a44eb22f</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -636,7 +636,7 @@
       <spirit:file>
         <spirit:name>util_mfifo.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_86db3630</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_ebf844f5</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -720,11 +720,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:55:35Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:13:06Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="cb1bb0c0"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="36c8b66f"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="c4e32d84"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="24fe8ee1"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="e332cd35"/>
diff --git a/adi_library/util_mfifo/util_mfifo.v b/adi_library/util_mfifo/util_mfifo.v
index 0d9acffc..0ddc22bf 100644
--- a/adi_library/util_mfifo/util_mfifo.v
+++ b/adi_library/util_mfifo/util_mfifo.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_mfifo/util_mfifo.xpr b/adi_library/util_mfifo/util_mfifo.xpr
index 060665cb..8dd14dd6 100644
--- a/adi_library/util_mfifo/util_mfifo.xpr
+++ b/adi_library/util_mfifo/util_mfifo.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_mfifo/util_mfifo.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_mfifo/util_mfifo.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="bd9bb9320ab346d38e7448b1616daf56"/>
+    <Option Name="Id" Val="3e88fbdde3974c2eb276cd6f1b748d99"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -161,21 +160,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -188,7 +187,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_mii_to_rmii/component.xml b/adi_library/util_mii_to_rmii/component.xml
index f843ab28..b27bd88e 100644
--- a/adi_library/util_mii_to_rmii/component.xml
+++ b/adi_library/util_mii_to_rmii/component.xml
@@ -290,7 +290,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>7f96d891</spirit:value>
+            <spirit:value>276fcbf6</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -306,7 +306,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>7f96d891</spirit:value>
+            <spirit:value>276fcbf6</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -606,7 +606,7 @@
       <spirit:file>
         <spirit:name>util_mii_to_rmii.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_4eec8a2d</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_12f287d3</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -689,11 +689,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:55:44Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:13:15Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="67b1a9b4"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="7c3564c9"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="62d67d61"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="e10b60ca"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="c4cdb13a"/>
diff --git a/adi_library/util_mii_to_rmii/mac_phy_link.v b/adi_library/util_mii_to_rmii/mac_phy_link.v
index 5a9e5481..b26b486c 100644
--- a/adi_library/util_mii_to_rmii/mac_phy_link.v
+++ b/adi_library/util_mii_to_rmii/mac_phy_link.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_mii_to_rmii/phy_mac_link.v b/adi_library/util_mii_to_rmii/phy_mac_link.v
index 599302ae..60620630 100644
--- a/adi_library/util_mii_to_rmii/phy_mac_link.v
+++ b/adi_library/util_mii_to_rmii/phy_mac_link.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_mii_to_rmii/util_mii_to_rmii.v b/adi_library/util_mii_to_rmii/util_mii_to_rmii.v
index 59fca826..d062a7bf 100644
--- a/adi_library/util_mii_to_rmii/util_mii_to_rmii.v
+++ b/adi_library/util_mii_to_rmii/util_mii_to_rmii.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_mii_to_rmii/util_mii_to_rmii.xpr b/adi_library/util_mii_to_rmii/util_mii_to_rmii.xpr
index 486b6e98..f1e15fcb 100644
--- a/adi_library/util_mii_to_rmii/util_mii_to_rmii.xpr
+++ b/adi_library/util_mii_to_rmii/util_mii_to_rmii.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_mii_to_rmii/util_mii_to_rmii.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_mii_to_rmii/util_mii_to_rmii.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="d2ba56029db044b2b968806552cee863"/>
+    <Option Name="Id" Val="e3f47bcd9ac54dd0bf02f644556c59c6"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -168,21 +167,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -195,7 +194,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_pack/tb/cpack_tb.v b/adi_library/util_pack/tb/cpack_tb.v
index 3d7e0059..425231e3 100644
--- a/adi_library/util_pack/tb/cpack_tb.v
+++ b/adi_library/util_pack/tb/cpack_tb.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_pack/tb/tb_base.v b/adi_library/util_pack/tb/tb_base.v
index 169b98f8..9dbaed22 100644
--- a/adi_library/util_pack/tb/tb_base.v
+++ b/adi_library/util_pack/tb/tb_base.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_pack/tb/underflow_tb.v b/adi_library/util_pack/tb/underflow_tb.v
index c4b15aba..0d9482e2 100644
--- a/adi_library/util_pack/tb/underflow_tb.v
+++ b/adi_library/util_pack/tb/underflow_tb.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_pack/tb/upack_tb.v b/adi_library/util_pack/tb/upack_tb.v
index cc455c24..d8367c55 100644
--- a/adi_library/util_pack/tb/upack_tb.v
+++ b/adi_library/util_pack/tb/upack_tb.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_pack/util_cpack2/component.xml b/adi_library/util_pack/util_cpack2/component.xml
index e1f520cf..d517d2c4 100644
--- a/adi_library/util_pack/util_cpack2/component.xml
+++ b/adi_library/util_pack/util_cpack2/component.xml
@@ -110,7 +110,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>31917087</spirit:value>
+            <spirit:value>f7c1092b</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -126,7 +126,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>31917087</spirit:value>
+            <spirit:value>f7c1092b</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -3300,7 +3300,7 @@
       <spirit:file>
         <spirit:name>util_cpack2.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_c254821b</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_e28decc4</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -3404,11 +3404,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:55:56Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:13:28Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="43407f53"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="8bbdacbc"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="f62bda8c"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="aa511e64"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="65ba3f33"/>
diff --git a/adi_library/util_pack/util_cpack2/util_cpack2.v b/adi_library/util_pack/util_cpack2/util_cpack2.v
index 8006a249..422492a2 100644
--- a/adi_library/util_pack/util_cpack2/util_cpack2.v
+++ b/adi_library/util_pack/util_cpack2/util_cpack2.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_pack/util_cpack2/util_cpack2.xpr b/adi_library/util_pack/util_cpack2/util_cpack2.xpr
index 8080b6a0..d79281d7 100644
--- a/adi_library/util_pack/util_cpack2/util_cpack2.xpr
+++ b/adi_library/util_pack/util_cpack2/util_cpack2.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_pack/util_cpack2/util_cpack2.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_pack/util_cpack2/util_cpack2.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="c3ee003931df4a9fbea5772bd12ae512"/>
+    <Option Name="Id" Val="eb934cfafc36443d9b585de7aecfc71e"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -196,21 +195,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -223,7 +222,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_pack/util_cpack2/util_cpack2_impl.v b/adi_library/util_pack/util_cpack2/util_cpack2_impl.v
index 0b7b7530..13dabd5c 100644
--- a/adi_library/util_pack/util_cpack2/util_cpack2_impl.v
+++ b/adi_library/util_pack/util_cpack2/util_cpack2_impl.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_pack/util_pack_common/pack_ctrl.v b/adi_library/util_pack/util_pack_common/pack_ctrl.v
index d4df07d7..3e8e9294 100644
--- a/adi_library/util_pack/util_pack_common/pack_ctrl.v
+++ b/adi_library/util_pack/util_pack_common/pack_ctrl.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_pack/util_pack_common/pack_interconnect.v b/adi_library/util_pack/util_pack_common/pack_interconnect.v
index 273b76ce..e51378b4 100644
--- a/adi_library/util_pack/util_pack_common/pack_interconnect.v
+++ b/adi_library/util_pack/util_pack_common/pack_interconnect.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_pack/util_pack_common/pack_network.v b/adi_library/util_pack/util_pack_common/pack_network.v
index 6547a6c0..9b0c75ec 100644
--- a/adi_library/util_pack/util_pack_common/pack_network.v
+++ b/adi_library/util_pack/util_pack_common/pack_network.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_pack/util_pack_common/pack_shell.v b/adi_library/util_pack/util_pack_common/pack_shell.v
index 3a236dc9..b838daa9 100644
--- a/adi_library/util_pack/util_pack_common/pack_shell.v
+++ b/adi_library/util_pack/util_pack_common/pack_shell.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_pack/util_upack2/component.xml b/adi_library/util_pack/util_upack2/component.xml
index 4a36a6b7..bf98ceba 100644
--- a/adi_library/util_pack/util_upack2/component.xml
+++ b/adi_library/util_pack/util_upack2/component.xml
@@ -102,7 +102,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>7207a499</spirit:value>
+            <spirit:value>dbed0aa0</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -118,7 +118,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>7207a499</spirit:value>
+            <spirit:value>dbed0aa0</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -3103,7 +3103,7 @@
       <spirit:file>
         <spirit:name>util_upack2.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_afc8d127</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_6593dbb0</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -3207,11 +3207,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:56:07Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:13:41Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="c92da678"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="0e97e659"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="9e3be159"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="aa511e64"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="385785e0"/>
diff --git a/adi_library/util_pack/util_upack2/util_upack2.v b/adi_library/util_pack/util_upack2/util_upack2.v
index 3c53e745..cc9267ae 100644
--- a/adi_library/util_pack/util_upack2/util_upack2.v
+++ b/adi_library/util_pack/util_upack2/util_upack2.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_pack/util_upack2/util_upack2.xpr b/adi_library/util_pack/util_upack2/util_upack2.xpr
index 3c20d48a..065b3fbb 100644
--- a/adi_library/util_pack/util_upack2/util_upack2.xpr
+++ b/adi_library/util_pack/util_upack2/util_upack2.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_pack/util_upack2/util_upack2.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_pack/util_upack2/util_upack2.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="4b92ee49f54045c08bd08c23a7eb5aa4"/>
+    <Option Name="Id" Val="dd5b1cd645e94248aa7f8532292ce703"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -60,7 +60,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -197,21 +196,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -224,7 +223,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_pack/util_upack2/util_upack2_impl.v b/adi_library/util_pack/util_upack2/util_upack2_impl.v
index 395a76fa..9e9bc438 100644
--- a/adi_library/util_pack/util_upack2/util_upack2_impl.v
+++ b/adi_library/util_pack/util_upack2/util_upack2_impl.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_pad/component.xml b/adi_library/util_pad/component.xml
index 846b9087..4ff6698b 100644
--- a/adi_library/util_pad/component.xml
+++ b/adi_library/util_pad/component.xml
@@ -18,7 +18,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>b9c6e2ac</spirit:value>
+            <spirit:value>1b1c31dd</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -34,7 +34,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>b9c6e2ac</spirit:value>
+            <spirit:value>1b1c31dd</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -123,7 +123,7 @@
       <spirit:file>
         <spirit:name>util_pad.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_b9c6e2ac</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_1b1c31dd</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -213,11 +213,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:56:14Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:13:49Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="1b0a2ea7"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="3fce724a"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="7ab8b715"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ef966e44"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="40c99227"/>
diff --git a/adi_library/util_pad/util_pad.v b/adi_library/util_pad/util_pad.v
index c3bd5b84..acb22c0d 100644
--- a/adi_library/util_pad/util_pad.v
+++ b/adi_library/util_pad/util_pad.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_pad/util_pad.xpr b/adi_library/util_pad/util_pad.xpr
index 79ed0f0c..44413fbc 100644
--- a/adi_library/util_pad/util_pad.xpr
+++ b/adi_library/util_pad/util_pad.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_pad/util_pad.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_pad/util_pad.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="6dc78fd0a5604ccc9e16fa2e408879ae"/>
+    <Option Name="Id" Val="4c495c3d2f6f4d228b887dff25af39b4"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -154,21 +153,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -181,7 +180,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_pulse_gen/component.xml b/adi_library/util_pulse_gen/component.xml
index 439ed05d..6fa15311 100644
--- a/adi_library/util_pulse_gen/component.xml
+++ b/adi_library/util_pulse_gen/component.xml
@@ -64,7 +64,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>549b8bb7</spirit:value>
+            <spirit:value>41a81538</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -80,7 +80,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>549b8bb7</spirit:value>
+            <spirit:value>41a81538</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -230,7 +230,7 @@
       <spirit:file>
         <spirit:name>../common/util_pulse_gen.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_549b8bb7</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_41a81538</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -305,11 +305,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:56:22Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:13:57Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="75cd53d0"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="93a23dc2"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="db400b83"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ca109ff4"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="548495f7"/>
diff --git a/adi_library/util_pulse_gen/util_pulse_gen.xpr b/adi_library/util_pulse_gen/util_pulse_gen.xpr
index 37445c99..3b3e10cb 100644
--- a/adi_library/util_pulse_gen/util_pulse_gen.xpr
+++ b/adi_library/util_pulse_gen/util_pulse_gen.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_pulse_gen/util_pulse_gen.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_pulse_gen/util_pulse_gen.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="5975502d902440b5b8533dddf0bfb6b2"/>
+    <Option Name="Id" Val="f0a8da86a03b43178ec7232be2a00f08"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -154,21 +153,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -181,7 +180,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_rfifo/component.xml b/adi_library/util_rfifo/component.xml
index 02475a84..7e4fe7a9 100644
--- a/adi_library/util_rfifo/component.xml
+++ b/adi_library/util_rfifo/component.xml
@@ -102,7 +102,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>85e19357</spirit:value>
+            <spirit:value>dc4e373d</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -118,7 +118,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>f5768c51</spirit:value>
+            <spirit:value>34b4da5f</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1672,7 +1672,7 @@
       <spirit:file>
         <spirit:name>util_rfifo.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_1e6c5072</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_bcc95d9c</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1761,11 +1761,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/util_rfifo</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:56:30Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:14:06Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="db125f5f"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="54e2f3e7"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="34b57ad3"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="05df121e"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="7d8a3397"/>
diff --git a/adi_library/util_rfifo/util_rfifo.v b/adi_library/util_rfifo/util_rfifo.v
index 608f5e75..3c65faa2 100644
--- a/adi_library/util_rfifo/util_rfifo.v
+++ b/adi_library/util_rfifo/util_rfifo.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_rfifo/util_rfifo.xpr b/adi_library/util_rfifo/util_rfifo.xpr
index f5b6eaa7..3628c44c 100644
--- a/adi_library/util_rfifo/util_rfifo.xpr
+++ b/adi_library/util_rfifo/util_rfifo.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_rfifo/util_rfifo.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_rfifo/util_rfifo.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="73ab2dbb8bb446f48b8f278f829115e8"/>
+    <Option Name="Id" Val="eebad206ed894a73b9590204fb99ef1c"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -167,21 +166,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -194,7 +193,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_sigma_delta_spi/Makefile b/adi_library/util_sigma_delta_spi/Makefile
index 594d724e..80b90f64 100644
--- a/adi_library/util_sigma_delta_spi/Makefile
+++ b/adi_library/util_sigma_delta_spi/Makefile
@@ -1,5 +1,5 @@
 ####################################################################################
-## Copyright (c) 2018 - 2023 Analog Devices, Inc.
+## Copyright (c) 2018 - 2024 Analog Devices, Inc.
 ### SPDX short identifier: BSD-1-Clause
 ## Auto-generated, do not modify!
 ####################################################################################
@@ -10,7 +10,7 @@ GENERIC_DEPS += util_sigma_delta_spi.v
 
 XILINX_DEPS += util_sigma_delta_spi_ip.tcl
 
-XILINX_DEPS += ../spi_engine/interfaces/spi_master.xml
-XILINX_DEPS += ../spi_engine/interfaces/spi_master_rtl.xml
+XILINX_DEPS += ../spi_engine/interfaces/spi_engine.xml
+XILINX_DEPS += ../spi_engine/interfaces/spi_engine_rtl.xml
 
 include ../scripts/library.mk
diff --git a/adi_library/util_sigma_delta_spi/component.xml b/adi_library/util_sigma_delta_spi/component.xml
index c3e2e1a9..8a5f9ca1 100644
--- a/adi_library/util_sigma_delta_spi/component.xml
+++ b/adi_library/util_sigma_delta_spi/component.xml
@@ -7,8 +7,8 @@
   <spirit:busInterfaces>
     <spirit:busInterface>
       <spirit:name>m_spi</spirit:name>
-      <spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_master" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_master_rtl" spirit:version="1.0"/>
+      <spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_rtl" spirit:version="1.0"/>
       <spirit:master/>
       <spirit:portMaps>
         <spirit:portMap>
@@ -55,8 +55,8 @@
     </spirit:busInterface>
     <spirit:busInterface>
       <spirit:name>s_spi</spirit:name>
-      <spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_master" spirit:version="1.0"/>
-      <spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_master_rtl" spirit:version="1.0"/>
+      <spirit:busType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="analog.com" spirit:library="interface" spirit:name="spi_engine_rtl" spirit:version="1.0"/>
       <spirit:slave/>
       <spirit:portMaps>
         <spirit:portMap>
@@ -166,7 +166,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>1b2e346e</spirit:value>
+            <spirit:value>a6f05805</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -182,7 +182,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>1b2e346e</spirit:value>
+            <spirit:value>a6f05805</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -265,9 +265,6 @@
               <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
-          <spirit:driver>
-            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
-          </spirit:driver>
         </spirit:wire>
       </spirit:port>
       <spirit:port>
@@ -281,9 +278,6 @@
               <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
-          <spirit:driver>
-            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
-          </spirit:driver>
         </spirit:wire>
       </spirit:port>
       <spirit:port>
@@ -314,9 +308,6 @@
               <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
-          <spirit:driver>
-            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
-          </spirit:driver>
         </spirit:wire>
       </spirit:port>
       <spirit:port>
@@ -369,9 +360,6 @@
               <spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
             </spirit:wireTypeDef>
           </spirit:wireTypeDefs>
-          <spirit:driver>
-            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
-          </spirit:driver>
         </spirit:wire>
       </spirit:port>
       <spirit:port>
@@ -429,7 +417,7 @@
       <spirit:file>
         <spirit:name>util_sigma_delta_spi.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_1b2e346e</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_a6f05805</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -509,12 +497,12 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:56:37Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:14:14Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="496ed3fc"/>
-      <xilinx:checksum xilinx:scope="ports" xilinx:value="2f6b516b"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="45f729bf"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="30b6a2a0"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="a514d648"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="277bb2e3"/>
     </xilinx:packagingInfo>
diff --git a/adi_library/util_sigma_delta_spi/util_sigma_delta_spi.v b/adi_library/util_sigma_delta_spi/util_sigma_delta_spi.v
index e9ea123e..9a0b077a 100644
--- a/adi_library/util_sigma_delta_spi/util_sigma_delta_spi.v
+++ b/adi_library/util_sigma_delta_spi/util_sigma_delta_spi.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_sigma_delta_spi/util_sigma_delta_spi.xpr b/adi_library/util_sigma_delta_spi/util_sigma_delta_spi.xpr
index ff4a61f5..41e82980 100644
--- a/adi_library/util_sigma_delta_spi/util_sigma_delta_spi.xpr
+++ b/adi_library/util_sigma_delta_spi/util_sigma_delta_spi.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_sigma_delta_spi/util_sigma_delta_spi.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_sigma_delta_spi/util_sigma_delta_spi.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="4a3bd5e0f449466d976a36694b2bd079"/>
+    <Option Name="Id" Val="8eea3bdf432843579ded31d8a0cd21e4"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -154,21 +153,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -181,7 +180,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_sigma_delta_spi/util_sigma_delta_spi_ip.tcl b/adi_library/util_sigma_delta_spi/util_sigma_delta_spi_ip.tcl
index a90d8845..07a13422 100644
--- a/adi_library/util_sigma_delta_spi/util_sigma_delta_spi_ip.tcl
+++ b/adi_library/util_sigma_delta_spi/util_sigma_delta_spi_ip.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -14,8 +14,8 @@ adi_ip_files util_sigma_delta_spi [list \
 adi_ip_properties_lite util_sigma_delta_spi
 
 adi_add_bus "m_spi" "master" \
-	"analog.com:interface:spi_master_rtl:1.0" \
-	"analog.com:interface:spi_master:1.0" \
+	"analog.com:interface:spi_engine_rtl:1.0" \
+	"analog.com:interface:spi_engine:1.0" \
 	{
 		{"m_sclk" "SCLK"} \
 		{"m_sdi" "SDI"} \
@@ -25,8 +25,8 @@ adi_add_bus "m_spi" "master" \
 	}
 
 adi_add_bus "s_spi" "slave" \
-	"analog.com:interface:spi_master_rtl:1.0" \
-	"analog.com:interface:spi_master:1.0" \
+	"analog.com:interface:spi_engine_rtl:1.0" \
+	"analog.com:interface:spi_engine:1.0" \
 	{
 		{"s_sclk" "SCLK"} \
 		{"s_sdi" "SDI"} \
diff --git a/adi_library/util_tdd_sync/component.xml b/adi_library/util_tdd_sync/component.xml
index 7a91e465..04c01e2e 100644
--- a/adi_library/util_tdd_sync/component.xml
+++ b/adi_library/util_tdd_sync/component.xml
@@ -64,7 +64,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>bd31316a</spirit:value>
+            <spirit:value>b2de8cd8</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -80,7 +80,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>42356555</spirit:value>
+            <spirit:value>2b4034f5</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -195,7 +195,7 @@
       <spirit:file>
         <spirit:name>util_tdd_sync.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_ce98bc75</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_11c6ded8</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -269,11 +269,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:56:45Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:14:23Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="0b324105"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="87906293"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="66f8b5ce"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="30abfb13"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="7026aaad"/>
diff --git a/adi_library/util_tdd_sync/util_tdd_sync.v b/adi_library/util_tdd_sync/util_tdd_sync.v
index 9fd3aa57..7493cd0a 100644
--- a/adi_library/util_tdd_sync/util_tdd_sync.v
+++ b/adi_library/util_tdd_sync/util_tdd_sync.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_tdd_sync/util_tdd_sync.xpr b/adi_library/util_tdd_sync/util_tdd_sync.xpr
index 129199b4..62cc040c 100644
--- a/adi_library/util_tdd_sync/util_tdd_sync.xpr
+++ b/adi_library/util_tdd_sync/util_tdd_sync.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_tdd_sync/util_tdd_sync.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_tdd_sync/util_tdd_sync.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="ec48f973af5c428d88397d16fb0f393f"/>
+    <Option Name="Id" Val="ff157859b427434e9bbc9231342df14f"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -167,21 +166,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -194,7 +193,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_var_fifo/component.xml b/adi_library/util_var_fifo/component.xml
index 6f4105d3..d57c2856 100644
--- a/adi_library/util_var_fifo/component.xml
+++ b/adi_library/util_var_fifo/component.xml
@@ -58,7 +58,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>f71444ed</spirit:value>
+            <spirit:value>c02044a9</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -74,7 +74,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>f71444ed</spirit:value>
+            <spirit:value>c02044a9</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -324,7 +324,7 @@
       <spirit:file>
         <spirit:name>util_var_fifo.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_f71444ed</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_c02044a9</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -399,11 +399,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/util_var_fifo</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:56:53Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:14:31Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="c5f05d9d"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="6a90c0b4"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="29c7c5b5"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ad728d91"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="e5d1ba7d"/>
diff --git a/adi_library/util_var_fifo/util_var_fifo.v b/adi_library/util_var_fifo/util_var_fifo.v
index 19fd7cb8..a94fea65 100644
--- a/adi_library/util_var_fifo/util_var_fifo.v
+++ b/adi_library/util_var_fifo/util_var_fifo.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_var_fifo/util_var_fifo.xpr b/adi_library/util_var_fifo/util_var_fifo.xpr
index 49991aa7..a1cdcd8d 100644
--- a/adi_library/util_var_fifo/util_var_fifo.xpr
+++ b/adi_library/util_var_fifo/util_var_fifo.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_var_fifo/util_var_fifo.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_var_fifo/util_var_fifo.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="468dc91782184053b5df8b10122a5322"/>
+    <Option Name="Id" Val="34c009c705944137b4540d28550e6d75"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -154,21 +153,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -181,7 +180,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/util_wfifo/component.xml b/adi_library/util_wfifo/component.xml
index bda66577..7e12a5df 100644
--- a/adi_library/util_wfifo/component.xml
+++ b/adi_library/util_wfifo/component.xml
@@ -102,7 +102,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>ae0954fb</spirit:value>
+            <spirit:value>a2e0367c</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -118,7 +118,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>9484c44c</spirit:value>
+            <spirit:value>3ce14e9d</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1318,7 +1318,7 @@
       <spirit:file>
         <spirit:name>util_wfifo.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_74ba504e</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_5ef3b9cd</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1407,11 +1407,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/util_wfifo</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:57:01Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:14:40Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="1315f46d"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="7432b79f"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="3b5ef1e5"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="05df121e"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="680439ef"/>
diff --git a/adi_library/util_wfifo/util_wfifo.v b/adi_library/util_wfifo/util_wfifo.v
index a6dbb7c1..9248de77 100644
--- a/adi_library/util_wfifo/util_wfifo.v
+++ b/adi_library/util_wfifo/util_wfifo.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/util_wfifo/util_wfifo.xpr b/adi_library/util_wfifo/util_wfifo.xpr
index c09984b8..1224376a 100644
--- a/adi_library/util_wfifo/util_wfifo.xpr
+++ b/adi_library/util_wfifo/util_wfifo.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/util_wfifo/util_wfifo.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/util_wfifo/util_wfifo.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="d215e3084989476196202d1f761966ab"/>
+    <Option Name="Id" Val="69d77c7c4f2c4490ad84e3d98e530bf2"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -167,21 +166,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -194,7 +193,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/xilinx/axi_adcfifo/axi_adcfifo.v b/adi_library/xilinx/axi_adcfifo/axi_adcfifo.v
index 628b3e39..331d8af5 100644
--- a/adi_library/xilinx/axi_adcfifo/axi_adcfifo.v
+++ b/adi_library/xilinx/axi_adcfifo/axi_adcfifo.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/axi_adcfifo/axi_adcfifo.xpr b/adi_library/xilinx/axi_adcfifo/axi_adcfifo.xpr
index 40879b44..f832b91f 100644
--- a/adi_library/xilinx/axi_adcfifo/axi_adcfifo.xpr
+++ b/adi_library/xilinx/axi_adcfifo/axi_adcfifo.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/xilinx/axi_adcfifo/axi_adcfifo.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/xilinx/axi_adcfifo/axi_adcfifo.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="f5a19a8cb0864b3b80624e6b26f1e186"/>
+    <Option Name="Id" Val="39ef132a75b14b718f3e0b756a40d440"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -216,21 +215,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -243,7 +242,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v b/adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v
index 386b4849..271dbd82 100644
--- a/adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v
+++ b/adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v b/adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v
index 9b13e49b..9184d1e0 100644
--- a/adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v
+++ b/adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v b/adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v
index bb4881c6..a8dbdddf 100644
--- a/adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v
+++ b/adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v b/adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v
index cd1d2200..f0745c5b 100644
--- a/adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v
+++ b/adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/axi_adcfifo/component.xml b/adi_library/xilinx/axi_adcfifo/component.xml
index 0765e5e8..fb7f2d6c 100644
--- a/adi_library/xilinx/axi_adcfifo/component.xml
+++ b/adi_library/xilinx/axi_adcfifo/component.xml
@@ -475,7 +475,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>83221eac</spirit:value>
+            <spirit:value>9d3409ef</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -491,7 +491,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>ee0a0da4</spirit:value>
+            <spirit:value>26ee1cce</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1482,7 +1482,7 @@
       <spirit:file>
         <spirit:name>axi_adcfifo.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_e9086634</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_1b6ed270</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1619,11 +1619,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:57:14Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:14:53Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="fbb1487c"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="c22c759a"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="133b8887"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="7310d5b8"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="d9868e54"/>
diff --git a/adi_library/xilinx/axi_adxcvr/axi_adxcvr.v b/adi_library/xilinx/axi_adxcvr/axi_adxcvr.v
index 58ca8409..9f4e23dd 100644
--- a/adi_library/xilinx/axi_adxcvr/axi_adxcvr.v
+++ b/adi_library/xilinx/axi_adxcvr/axi_adxcvr.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/axi_adxcvr/axi_adxcvr.xpr b/adi_library/xilinx/axi_adxcvr/axi_adxcvr.xpr
index fa43b425..775f1806 100644
--- a/adi_library/xilinx/axi_adxcvr/axi_adxcvr.xpr
+++ b/adi_library/xilinx/axi_adxcvr/axi_adxcvr.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/xilinx/axi_adxcvr/axi_adxcvr.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/xilinx/axi_adxcvr/axi_adxcvr.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="d962d808e38e4e9ebfa5e5a8d48cec52"/>
+    <Option Name="Id" Val="59e01ca891c947bab49e5fab0e8feceb"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -203,21 +202,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -230,7 +229,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v b/adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v
index 1dd81b3d..a26a25c3 100644
--- a/adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v
+++ b/adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v b/adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v
index b705dfa6..94bfde12 100644
--- a/adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v
+++ b/adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v b/adi_library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v
index 325be6be..ce693b89 100644
--- a/adi_library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v
+++ b/adi_library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v b/adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v
index 3ac801e0..c4c76c18 100644
--- a/adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v
+++ b/adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/axi_adxcvr/component.xml b/adi_library/xilinx/axi_adxcvr/component.xml
index 0bbb674a..80d2abbe 100644
--- a/adi_library/xilinx/axi_adxcvr/component.xml
+++ b/adi_library/xilinx/axi_adxcvr/component.xml
@@ -9840,7 +9840,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>4afde498</spirit:value>
+            <spirit:value>d34781ea</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -9856,7 +9856,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>4afde498</spirit:value>
+            <spirit:value>d34781ea</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -26985,30 +26985,6 @@
       <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
       <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
     </spirit:choice>
-    <spirit:choice>
-      <spirit:name>choice_pairs_00ecfe9a</spirit:name>
-      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
-      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
-      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
-      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
-      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
-      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
-      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
-      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
-      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
-      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
-      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
-      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
-      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
-      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
-      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
-      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
-      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
-      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
-      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
-      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
-      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
-    </spirit:choice>
     <spirit:choice>
       <spirit:name>choice_pairs_07421b06</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
@@ -27053,7 +27029,32 @@
       <spirit:enumeration spirit:text="versal">4</spirit:enumeration>
     </spirit:choice>
     <spirit:choice>
-      <spirit:name>choice_pairs_fc01a186</spirit:name>
+      <spirit:name>choice_pairs_a6e6e044</spirit:name>
+      <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
+      <spirit:enumeration spirit:text="rf">1</spirit:enumeration>
+      <spirit:enumeration spirit:text="fl">2</spirit:enumeration>
+      <spirit:enumeration spirit:text="ff">3</spirit:enumeration>
+      <spirit:enumeration spirit:text="fb">4</spirit:enumeration>
+      <spirit:enumeration spirit:text="hc">5</spirit:enumeration>
+      <spirit:enumeration spirit:text="fh">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="cs">7</spirit:enumeration>
+      <spirit:enumeration spirit:text="cp">8</spirit:enumeration>
+      <spirit:enumeration spirit:text="ft">9</spirit:enumeration>
+      <spirit:enumeration spirit:text="fg">10</spirit:enumeration>
+      <spirit:enumeration spirit:text="sb">11</spirit:enumeration>
+      <spirit:enumeration spirit:text="rb">12</spirit:enumeration>
+      <spirit:enumeration spirit:text="rs">13</spirit:enumeration>
+      <spirit:enumeration spirit:text="cl">14</spirit:enumeration>
+      <spirit:enumeration spirit:text="sf">15</spirit:enumeration>
+      <spirit:enumeration spirit:text="ba">16</spirit:enumeration>
+      <spirit:enumeration spirit:text="fa">17</spirit:enumeration>
+      <spirit:enumeration spirit:text="fs">18</spirit:enumeration>
+      <spirit:enumeration spirit:text="fi">19</spirit:enumeration>
+      <spirit:enumeration spirit:text="vs">20</spirit:enumeration>
+      <spirit:enumeration spirit:text="ls">21</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_pairs_a897e79d</spirit:name>
       <spirit:enumeration spirit:text="Unknown">0</spirit:enumeration>
       <spirit:enumeration spirit:text="artix">1</spirit:enumeration>
       <spirit:enumeration spirit:text="kintex">2</spirit:enumeration>
@@ -27061,6 +27062,7 @@
       <spirit:enumeration spirit:text="zynq">4</spirit:enumeration>
       <spirit:enumeration spirit:text="versalprime">5</spirit:enumeration>
       <spirit:enumeration spirit:text="versalaicore">6</spirit:enumeration>
+      <spirit:enumeration spirit:text="versalpremium">7</spirit:enumeration>
     </spirit:choice>
   </spirit:choices>
   <spirit:fileSets>
@@ -27093,7 +27095,7 @@
       <spirit:file>
         <spirit:name>axi_adxcvr.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_7c4853b1</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_3280dc2a</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -27174,7 +27176,7 @@
     <spirit:parameter>
       <spirit:name>FPGA_FAMILY</spirit:name>
       <spirit:displayName>Fpga Family</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_fc01a186">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.FPGA_FAMILY" spirit:choiceRef="choice_pairs_a897e79d">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>SPEED_GRADE</spirit:name>
@@ -27184,7 +27186,7 @@
     <spirit:parameter>
       <spirit:name>DEV_PACKAGE</spirit:name>
       <spirit:displayName>Dev Package</spirit:displayName>
-      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_00ecfe9a">0</spirit:value>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.DEV_PACKAGE" spirit:choiceRef="choice_pairs_a6e6e044">0</spirit:value>
     </spirit:parameter>
     <spirit:parameter>
       <spirit:name>FPGA_VOLTAGE</spirit:name>
@@ -27255,12 +27257,12 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/axi_adxcvr</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:57:27Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:15:07Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
       <xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="68e94c68"/>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="671b7442"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="6c78aef8"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="4976afbc"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="fbcbf35e"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="b7dbfd72"/>
diff --git a/adi_library/xilinx/axi_dacfifo/axi_dacfifo.v b/adi_library/xilinx/axi_dacfifo/axi_dacfifo.v
index ad5f5665..67de5e3b 100644
--- a/adi_library/xilinx/axi_dacfifo/axi_dacfifo.v
+++ b/adi_library/xilinx/axi_dacfifo/axi_dacfifo.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/axi_dacfifo/axi_dacfifo.xpr b/adi_library/xilinx/axi_dacfifo/axi_dacfifo.xpr
index 5bd0e755..166a94f5 100644
--- a/adi_library/xilinx/axi_dacfifo/axi_dacfifo.xpr
+++ b/adi_library/xilinx/axi_dacfifo/axi_dacfifo.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/xilinx/axi_dacfifo/axi_dacfifo.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/xilinx/axi_dacfifo/axi_dacfifo.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="36f1e17cc07941c58cd2fa1d65f1e00e"/>
+    <Option Name="Id" Val="5b9b5849e1f64a6aa7d3c9909c25c9c6"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -223,21 +222,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -250,7 +249,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v b/adi_library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v
index aed1457c..9d6d324d 100644
--- a/adi_library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v
+++ b/adi_library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v b/adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v
index 549f1a04..ba7ff7ae 100644
--- a/adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v
+++ b/adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v b/adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
index 66bb6b4b..c80fdda4 100644
--- a/adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
+++ b/adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/axi_dacfifo/component.xml b/adi_library/xilinx/axi_dacfifo/component.xml
index 7cf4fc06..e809a84c 100644
--- a/adi_library/xilinx/axi_dacfifo/component.xml
+++ b/adi_library/xilinx/axi_dacfifo/component.xml
@@ -457,7 +457,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>36fedcbb</spirit:value>
+            <spirit:value>4534e2ce</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -473,7 +473,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>6f634deb</spirit:value>
+            <spirit:value>0e1eccf3</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -1410,7 +1410,7 @@
       <spirit:file>
         <spirit:name>axi_dacfifo.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_042d71fe</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_596be823</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -1546,11 +1546,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:57:40Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:15:22Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="49c36edd"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="6f05d9d2"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="b03ce28d"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="344035cc"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="cb4e6067"/>
diff --git a/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v b/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v
index befefe16..87ffe489 100644
--- a/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v
+++ b/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr b/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr
index 6756fd62..f60e7af7 100644
--- a/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr
+++ b/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="0820422988594cc5932574f6f5fce3c1"/>
+    <Option Name="Id" Val="4b37027d10c54b6b94ab33bd0eed0c3a"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -202,21 +201,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -229,7 +228,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v b/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v
index e23dd973..0e6880b8 100644
--- a/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v
+++ b/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/axi_xcvrlb/component.xml b/adi_library/xilinx/axi_xcvrlb/component.xml
index 7d8996a4..b1571063 100644
--- a/adi_library/xilinx/axi_xcvrlb/component.xml
+++ b/adi_library/xilinx/axi_xcvrlb/component.xml
@@ -244,7 +244,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>05fbea40</spirit:value>
+            <spirit:value>b7aa3ff4</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -263,7 +263,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>61f424a5</spirit:value>
+            <spirit:value>12c6a1c9</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -810,7 +810,7 @@
       <spirit:file>
         <spirit:name>axi_xcvrlb.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_4e7e40b2</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_97762049</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -958,11 +958,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:57:51Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:15:34Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="2fd94af6"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="87060927"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="b0d1cc30"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="8232f07a"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="48bfcb3f"/>
diff --git a/adi_library/xilinx/common/ad_data_clk.v b/adi_library/xilinx/common/ad_data_clk.v
index 08ac184d..6f28e8d4 100644
--- a/adi_library/xilinx/common/ad_data_clk.v
+++ b/adi_library/xilinx/common/ad_data_clk.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/common/ad_data_in.v b/adi_library/xilinx/common/ad_data_in.v
index c1dcd1b2..0105b21a 100755
--- a/adi_library/xilinx/common/ad_data_in.v
+++ b/adi_library/xilinx/common/ad_data_in.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/common/ad_data_out.v b/adi_library/xilinx/common/ad_data_out.v
index 68cd566d..b27453a9 100755
--- a/adi_library/xilinx/common/ad_data_out.v
+++ b/adi_library/xilinx/common/ad_data_out.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/common/ad_dcfilter.v b/adi_library/xilinx/common/ad_dcfilter.v
index c05b83aa..9fc704e4 100644
--- a/adi_library/xilinx/common/ad_dcfilter.v
+++ b/adi_library/xilinx/common/ad_dcfilter.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/common/ad_mmcm_drp.v b/adi_library/xilinx/common/ad_mmcm_drp.v
index bf19b4f2..4f054508 100644
--- a/adi_library/xilinx/common/ad_mmcm_drp.v
+++ b/adi_library/xilinx/common/ad_mmcm_drp.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/common/ad_mul.v b/adi_library/xilinx/common/ad_mul.v
index aeaac430..e95ed05a 100644
--- a/adi_library/xilinx/common/ad_mul.v
+++ b/adi_library/xilinx/common/ad_mul.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
@@ -52,7 +52,7 @@ module ad_mul #(
   // delay interface
 
   input       [(DELAY_DATA_WIDTH-1):0]  ddata_in,
-  output  reg [(DELAY_DATA_WIDTH-1):0]  ddata_out
+  output  reg [(DELAY_DATA_WIDTH-1):0]  ddata_out = 'd0
 );
 
   // internal registers
diff --git a/adi_library/xilinx/common/ad_serdes_clk.v b/adi_library/xilinx/common/ad_serdes_clk.v
index c438ac3b..24c4fc13 100644
--- a/adi_library/xilinx/common/ad_serdes_clk.v
+++ b/adi_library/xilinx/common/ad_serdes_clk.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/common/ad_serdes_in.v b/adi_library/xilinx/common/ad_serdes_in.v
index b9218b6d..4bfc12f7 100644
--- a/adi_library/xilinx/common/ad_serdes_in.v
+++ b/adi_library/xilinx/common/ad_serdes_in.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/common/ad_serdes_out.v b/adi_library/xilinx/common/ad_serdes_out.v
index a8d44716..747831b7 100644
--- a/adi_library/xilinx/common/ad_serdes_out.v
+++ b/adi_library/xilinx/common/ad_serdes_out.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/util_adxcvr/component.xml b/adi_library/xilinx/util_adxcvr/component.xml
index 68644ece..aa32526d 100644
--- a/adi_library/xilinx/util_adxcvr/component.xml
+++ b/adi_library/xilinx/util_adxcvr/component.xml
@@ -23899,7 +23899,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>1845bcbd</spirit:value>
+            <spirit:value>4dc43688</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -23918,7 +23918,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>7d9eb72f</spirit:value>
+            <spirit:value>01045f07</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -67075,7 +67075,7 @@
       <spirit:file>
         <spirit:name>util_adxcvr.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_ec24f6a3</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_ae47eb4b</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -67528,11 +67528,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>https://wiki.analog.com/resources/fpga/docs/util_xcvr</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:58:03Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:15:47Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="9b08bb86"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="b550c633"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="d70ad8a4"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="ef4432cb"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="46f75622"/>
diff --git a/adi_library/xilinx/util_adxcvr/util_adxcvr.v b/adi_library/xilinx/util_adxcvr/util_adxcvr.v
index ee127ba9..56990c13 100644
--- a/adi_library/xilinx/util_adxcvr/util_adxcvr.v
+++ b/adi_library/xilinx/util_adxcvr/util_adxcvr.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/util_adxcvr/util_adxcvr.xpr b/adi_library/xilinx/util_adxcvr/util_adxcvr.xpr
index 8bac4c81..97720422 100644
--- a/adi_library/xilinx/util_adxcvr/util_adxcvr.xpr
+++ b/adi_library/xilinx/util_adxcvr/util_adxcvr.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/xilinx/util_adxcvr/util_adxcvr.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/xilinx/util_adxcvr/util_adxcvr.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="f878f19e3bc741f591d4c52ce47e0e6e"/>
+    <Option Name="Id" Val="65384cf95b664434b53bcfe69d9aa0f8"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -195,21 +194,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -222,7 +221,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
diff --git a/adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v b/adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v
index 7f71c52e..5bd58266 100644
--- a/adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v
+++ b/adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v b/adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v
index 7b95fc54..61f7489a 100644
--- a/adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v
+++ b/adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/util_clkdiv/component.xml b/adi_library/xilinx/util_clkdiv/component.xml
index cf893dbc..c7dfae11 100644
--- a/adi_library/xilinx/util_clkdiv/component.xml
+++ b/adi_library/xilinx/util_clkdiv/component.xml
@@ -52,7 +52,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>e4784cb9</spirit:value>
+            <spirit:value>46f830fd</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -68,7 +68,7 @@
         <spirit:parameters>
           <spirit:parameter>
             <spirit:name>viewChecksum</spirit:name>
-            <spirit:value>a019022f</spirit:value>
+            <spirit:value>95c49aa5</spirit:value>
           </spirit:parameter>
         </spirit:parameters>
       </spirit:view>
@@ -185,7 +185,7 @@
       <spirit:file>
         <spirit:name>util_clkdiv.v</spirit:name>
         <spirit:fileType>verilogSource</spirit:fileType>
-        <spirit:userFileType>CHECKSUM_a019022f</spirit:userFileType>
+        <spirit:userFileType>CHECKSUM_95c49aa5</spirit:userFileType>
       </spirit:file>
     </spirit:fileSet>
     <spirit:fileSet>
@@ -241,11 +241,11 @@
       <xilinx:vendorDisplayName>Analog Devices</xilinx:vendorDisplayName>
       <xilinx:vendorURL>http://www.analog.com</xilinx:vendorURL>
       <xilinx:coreRevision>1</xilinx:coreRevision>
-      <xilinx:coreCreationDateTime>2024-01-14T03:58:15Z</xilinx:coreCreationDateTime>
+      <xilinx:coreCreationDateTime>2024-06-06T03:15:55Z</xilinx:coreCreationDateTime>
     </xilinx:coreExtensions>
     <xilinx:packagingInfo>
-      <xilinx:xilinxVersion>2023.2.1</xilinx:xilinxVersion>
-      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="3932f95c"/>
+      <xilinx:xilinxVersion>2024.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="eb30d391"/>
       <xilinx:checksum xilinx:scope="ports" xilinx:value="b5c8343e"/>
       <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="0c132cf6"/>
       <xilinx:checksum xilinx:scope="parameters" xilinx:value="253c2293"/>
diff --git a/adi_library/xilinx/util_clkdiv/util_clkdiv.v b/adi_library/xilinx/util_clkdiv/util_clkdiv.v
index e1930e02..c0fa3f57 100644
--- a/adi_library/xilinx/util_clkdiv/util_clkdiv.v
+++ b/adi_library/xilinx/util_clkdiv/util_clkdiv.v
@@ -26,7 +26,7 @@
 //
 //   2. An ADI specific BSD license, which can be found in the top level directory
 //      of this repository (LICENSE_ADIBSD), and also on-line at:
-//      https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
+//      https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
 //      This will allow to generate bit files and not release the source code,
 //      as long as it attaches to an ADI device.
 //
diff --git a/adi_library/xilinx/util_clkdiv/util_clkdiv.xpr b/adi_library/xilinx/util_clkdiv/util_clkdiv.xpr
index e4a59970..736e2f68 100644
--- a/adi_library/xilinx/util_clkdiv/util_clkdiv.xpr
+++ b/adi_library/xilinx/util_clkdiv/util_clkdiv.xpr
@@ -1,13 +1,13 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Product Version: Vivado v2023.2.1 (64-bit)                              -->
+<!-- Product Version: Vivado v2024.1 (64-bit)                              -->
 <!--                                                                         -->
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
-<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+<!-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="65" Path="/home/josh/tmp/hdl/library/xilinx/util_clkdiv/util_clkdiv.xpr">
+<Project Product="Vivado" Version="7" Minor="67" Path="/home/josh/Downloads/hdl/library/xilinx/util_clkdiv/util_clkdiv.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
-    <Option Name="Id" Val="38fa6399261742dabdbf07435be96e17"/>
+    <Option Name="Id" Val="7bb6456225b54353a38eceb257124c5d"/>
     <Option Name="Part" Val="xc7vx485tffg1157-1"/>
     <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
     <Option Name="CompiledLibDirXSim" Val=""/>
@@ -29,12 +29,12 @@
     <Option Name="SimulatorGccInstallDirVCS" Val=""/>
     <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
     <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
-    <Option Name="SimulatorVersionXsim" Val="2023.2"/>
+    <Option Name="SimulatorVersionXsim" Val="2024.1"/>
     <Option Name="SimulatorVersionModelSim" Val="2023.2"/>
     <Option Name="SimulatorVersionQuesta" Val="2023.2"/>
     <Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
     <Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
-    <Option Name="SimulatorVersionRiviera" Val="2022.10"/>
+    <Option Name="SimulatorVersionRiviera" Val="2023.04"/>
     <Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
     <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
@@ -59,7 +59,6 @@
     <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
-    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
     <Option Name="WTXSimLaunchSim" Val="0"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
@@ -161,21 +160,21 @@
       <Option Name="Description" Val="Riviera-PRO Simulator"/>
     </Simulator>
   </Simulators>
-  <Runs Version="1" Minor="21">
-    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+  <Runs Version="1" Minor="22">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
           <Desc>Vivado Synthesis Defaults</Desc>
         </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>
-    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7vx485tffg1157-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
           <Desc>Default settings for Implementation.</Desc>
         </StratHandle>
         <Step Id="init_design"/>
@@ -188,7 +187,7 @@
         <Step Id="post_route_phys_opt_design"/>
         <Step Id="write_bitstream"/>
       </Strategy>
-      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
       <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
       <RQSFiles/>
     </Run>