From 315a673005dab27cd9265cb90768bc56161a8f45 Mon Sep 17 00:00:00 2001 From: Josh Gao Date: Mon, 15 Jan 2024 09:36:08 +0800 Subject: [PATCH] initial commit, add dds_par module --- .gitignore | 104 + adi_library/Makefile | 31 + adi_library/ad463x_data_capture/Makefile | 13 + .../ad463x_data_capture/ad463x_data_capture.v | 131 + .../ad463x_data_capture.xpr | 399 + .../ad463x_data_capture_ip.tcl | 30 + adi_library/ad463x_data_capture/component.xml | 328 + .../xgui/ad463x_data_capture_v1_0.tcl | 55 + adi_library/axi_ad3552r/Makefile | 35 + adi_library/axi_ad3552r/axi_ad3552r.v | 233 + adi_library/axi_ad3552r/axi_ad3552r.xpr | 557 + adi_library/axi_ad3552r/axi_ad3552r_channel.v | 227 + adi_library/axi_ad3552r/axi_ad3552r_core.v | 261 + adi_library/axi_ad3552r/axi_ad3552r_if.v | 316 + adi_library/axi_ad3552r/axi_ad3552r_if_tb | 7 + adi_library/axi_ad3552r/axi_ad3552r_if_tb.v | 239 + adi_library/axi_ad3552r/axi_ad3552r_ip.tcl | 51 + adi_library/axi_ad3552r/bd/bd.tcl | 47 + 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create mode 100644 adi_library/xilinx/util_clkdiv/util_clkdiv.v create mode 100644 adi_library/xilinx/util_clkdiv/util_clkdiv.xpr create mode 100644 adi_library/xilinx/util_clkdiv/util_clkdiv_constr.xdc create mode 100644 adi_library/xilinx/util_clkdiv/util_clkdiv_ip.tcl create mode 100644 adi_library/xilinx/util_clkdiv/util_clkdiv_ooc.ttcl create mode 100644 adi_library/xilinx/util_clkdiv/xgui/util_clkdiv_v1_0.tcl create mode 100644 common/.gitkeep create mode 100644 common/ApproxAbs.v create mode 100644 common/ApproxModuli_26bit.v create mode 100644 common/adder_tree_ppl.v create mode 100644 common/trunc_32bit_to_12bit.v create mode 100644 common/truncate_manual.v create mode 100644 custom_ips/.gitkeep create mode 100644 modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.srcs/sim_1/new/tb_addr_to_wave.v create mode 100644 modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.srcs/sim_1/new/tb_dds_par.v create mode 100644 modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.srcs/sources_1/ip/coe/cos_16384_16b.coe create mode 100644 modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.srcs/sources_1/ip/cos_16384_16b/cos_16384_16b.xci create mode 100644 modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.srcs/sources_1/new/addr_to_wave.v create mode 100644 modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.srcs/sources_1/new/dds_par.v create mode 100644 modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.xpr diff --git a/.gitignore b/.gitignore new file mode 100644 index 00000000..360509cb --- /dev/null +++ b/.gitignore @@ -0,0 +1,104 @@ +################################################################################ +########################## Basic Directory Structure ########################### +################################################################################ + +# everything +* + +# exclude the directory structure +!/adi_library/ +!/adi_library/**/* +!/common/ +!/common/**/* +!/custom_ips/ +!/custom_ips/**/* +!/modules/ +!/modules/**/ +!/projects/ +!/projects/**/ +!/.gitattributes +!/.gitignore +!/README.md + +################################################################################ +############################# Vivado & SDK Common ############################## +################################################################################ + +# folders (and all of their contents) that should always be ignored, anywhere +# in the repo +.Xil/ + +# file patterns that should always be ignored (journal files, log files, dump +# files that are created upon Vivado/SDK errors) +*.jou +*.log +*.backup.jou +*.backup.log +*.upgrade_log +*.dmp +*.debug +vivado_pid* +*~ + +# vivado workspace files +xsim.dir/ +xvlog.pb + +################################################################################ +############################### Vivado Specific ################################ +################################################################################ + +# exclude +.metadata +*.cache/ +*.gen/ +*.hw/ +*.ip_user_files/ +*.runs/**/* +*.sim/ + +# include xpr +!*.xpr + +# include design source +!**/*.srcs/**/* + +# include design run results +!*.runs/impl_*/*.bit +!*.runs/impl_*/*.ltx + +################################################################################ +################################# SDK Specific ################################# +################################################################################ + +# include sdk directory and everything in it +!*.sdk/ +!*.sdk/** +*.sdk/**.log + +# exclude some obscure hidden SDK folders +*.sdk/.metadata/ +*.sdk/.sdk/ +*.sdk/RemoteSystemsTempFiles/ +*.sdk/webtalk/ + +# hw_platform: exclude the entire hw_platform folder, as everything can be +# generated from the .hdf file. Make sure to include the bitstream in the .hdf +# file when exporting from Vivado! +*.sdk/*_hw_platform_*/ + +# BSP: only keep `.cproject`, `.project`, `.sdkproject`, `.system.mss` and +# Makefile, ps lib files are regenerated automatically +*.sdk/*_bsp/* +!*.sdk/*_bsp/*.cproject +!*.sdk/*_bsp/*.project +!*.sdk/*_bsp/*.sdkproject +!*.sdk/*_bsp/system.mss +!*.sdk/*_bsp/Makefile + +# Application: ignored file patterns, exclude Debug & Release folders +*.sdk/**/*.o +*.sdk/**/*.d +*.sdk/**/*.a +*.sdk/*/Debug/ +*.sdk/*/Release/ diff --git a/adi_library/Makefile b/adi_library/Makefile new file mode 100644 index 00000000..02af0602 --- /dev/null +++ b/adi_library/Makefile @@ -0,0 +1,31 @@ +#################################################################################### +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +#################################################################################### +#################################################################################### + +include ../quiet.mk + +.PHONY: all lib clean clean-all +all: lib + +_LIBS := $(dir $(shell find . -mindepth 2 -name Makefile | sort)) + +# Create virtual targets "$library/all", "$library/clean" +_LIBS_ALL := $(addsuffix all, $(_LIBS)) +_LIBS_CLEAN := $(addsuffix clean, $(_LIBS)) + +$(_LIBS_ALL): + $(MAKE) -C $(@D) $(@F) + +$(_LIBS_CLEAN): + $(MAKE) -C $(@D) $(@F) + +clean: $(_LIBS_CLEAN) +clean-all: clean + +lib: $(_LIBS_ALL) + +#################################################################################### +#################################################################################### diff --git a/adi_library/ad463x_data_capture/Makefile b/adi_library/ad463x_data_capture/Makefile new file mode 100644 index 00000000..c2fbb9f6 --- /dev/null +++ b/adi_library/ad463x_data_capture/Makefile @@ -0,0 +1,13 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := ad463x_data_capture + +GENERIC_DEPS += ad463x_data_capture.v + +XILINX_DEPS += ad463x_data_capture_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/ad463x_data_capture/ad463x_data_capture.v b/adi_library/ad463x_data_capture/ad463x_data_capture.v new file mode 100644 index 00000000..066c3355 --- /dev/null +++ b/adi_library/ad463x_data_capture/ad463x_data_capture.v @@ -0,0 +1,131 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +// The AD4630-24 device requires this module to capture data in master and +// echo clock mode, because the data is clocked by the BUSY/SCLKOUT line, +// independent from the SPI interface + +module ad463x_data_capture #( + parameter DDR_EN = 0, + parameter NUM_OF_LANES = 2, + parameter DATA_WIDTH = 32 +) ( + input clk, // core clock of the SPIE + input csn, // CSN (chip select) + input echo_sclk, // BUSY/SCLKOUT + input [NUM_OF_LANES-1:0] data_in, // serial data lines + + output [(NUM_OF_LANES * DATA_WIDTH)-1:0] m_axis_data, // parallel data lines + output m_axis_valid, // data validation + input m_axis_ready // NOTE: back pressure is ignored +); + + reg csn_d; + + wire reset; + + always @(posedge clk) begin + csn_d <= csn; + end + + // negative edge resets the shift registers + assign reset = ~csn & csn_d; + + // CSN positive edge validates the output data + // WARNING: there isn't any buffering for data, if the sink module is not + // ready, the data will be discarded + assign m_axis_valid = csn & ~csn_d & m_axis_ready; + + genvar i, j; + generate + if (DDR_EN) // Double Data Rate mode + begin + + for (i=0; i + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/ad463x_data_capture/ad463x_data_capture_ip.tcl b/adi_library/ad463x_data_capture/ad463x_data_capture_ip.tcl new file mode 100644 index 00000000..bfb79e98 --- /dev/null +++ b/adi_library/ad463x_data_capture/ad463x_data_capture_ip.tcl @@ -0,0 +1,30 @@ +############################################################################### +## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create ad463x_data_capture +adi_ip_files ad463x_data_capture [list \ + "ad463x_data_capture.v" \ +] + +adi_ip_properties_lite ad463x_data_capture +# Remove all inferred interfaces +ipx::remove_all_bus_interface [ipx::current_core] + +# Interface definitions + +adi_add_bus "m_axis" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"m_axis_ready" "TREADY"} \ + {"m_axis_valid" "TVALID"} \ + {"m_axis_data" "TDATA"}] + +adi_add_bus_clock "clk" "m_axis" + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/ad463x_data_capture/component.xml b/adi_library/ad463x_data_capture/component.xml new file mode 100644 index 00000000..3a2dd033 --- /dev/null +++ b/adi_library/ad463x_data_capture/component.xml @@ -0,0 +1,328 @@ + + + analog.com + user + ad463x_data_capture + 1.0 + + + m_axis + + + + + + + TREADY + + + m_axis_ready + + + + + TVALID + + + m_axis_valid + + + + + TDATA + + + m_axis_data + + + + + + m_axis_signal_clock + m_axis_signal_clock + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_BUSIF + m_axis + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + ad463x_data_capture + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 8bb59c43 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + ad463x_data_capture + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 8bb59c43 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + b26bd2d7 + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + csn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + echo_sclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_in + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_data + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + DDR_EN + Ddr En + 0 + + + NUM_OF_LANES + Num Of Lanes + 2 + + + DATA_WIDTH + Data Width + 32 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + ad463x_data_capture.v + verilogSource + CHECKSUM_8bb59c43 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ad463x_data_capture.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/ad463x_data_capture_v1_0.tcl + tclSource + CHECKSUM_b26bd2d7 + XGUI_VERSION_2 + + + + ad463x_data_capture_v1_0 + + + DDR_EN + Ddr En + 0 + + + NUM_OF_LANES + Num Of Lanes + 2 + + + DATA_WIDTH + Data Width + 32 + + + Component_Name + ad463x_data_capture_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + ad463x_data_capture_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:37:32Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/ad463x_data_capture/xgui/ad463x_data_capture_v1_0.tcl b/adi_library/ad463x_data_capture/xgui/ad463x_data_capture_v1_0.tcl new file mode 100644 index 00000000..bed3365a --- /dev/null +++ b/adi_library/ad463x_data_capture/xgui/ad463x_data_capture_v1_0.tcl @@ -0,0 +1,55 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "DDR_EN" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_OF_LANES" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to validate DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.DDR_EN { PARAM_VALUE.DDR_EN } { + # Procedure called to update DDR_EN when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DDR_EN { PARAM_VALUE.DDR_EN } { + # Procedure called to validate DDR_EN + return true +} + +proc update_PARAM_VALUE.NUM_OF_LANES { PARAM_VALUE.NUM_OF_LANES } { + # Procedure called to update NUM_OF_LANES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_LANES { PARAM_VALUE.NUM_OF_LANES } { + # Procedure called to validate NUM_OF_LANES + return true +} + + +proc update_MODELPARAM_VALUE.DDR_EN { MODELPARAM_VALUE.DDR_EN PARAM_VALUE.DDR_EN } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DDR_EN}] ${MODELPARAM_VALUE.DDR_EN} +} + +proc update_MODELPARAM_VALUE.NUM_OF_LANES { MODELPARAM_VALUE.NUM_OF_LANES PARAM_VALUE.NUM_OF_LANES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_LANES}] ${MODELPARAM_VALUE.NUM_OF_LANES} +} + +proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} +} + diff --git a/adi_library/axi_ad3552r/Makefile b/adi_library/axi_ad3552r/Makefile new file mode 100755 index 00000000..3970c748 --- /dev/null +++ b/adi_library/axi_ad3552r/Makefile @@ -0,0 +1,35 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_ad3552r + +GENERIC_DEPS += ../common/ad_addsub.v +GENERIC_DEPS += ../common/ad_dds.v +GENERIC_DEPS += ../common/ad_dds_1.v +GENERIC_DEPS += ../common/ad_dds_2.v +GENERIC_DEPS += ../common/ad_dds_cordic_pipe.v +GENERIC_DEPS += ../common/ad_dds_sine.v +GENERIC_DEPS += ../common/ad_dds_sine_cordic.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_dac_channel.v +GENERIC_DEPS += ../common/up_dac_common.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_ad3552r.v +GENERIC_DEPS += axi_ad3552r_channel.v +GENERIC_DEPS += axi_ad3552r_core.v +GENERIC_DEPS += axi_ad3552r_if.v + +XILINX_DEPS += ../xilinx/common/ad_mul.v +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_ad3552r_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_ad3552r/axi_ad3552r.v b/adi_library/axi_ad3552r/axi_ad3552r.v new file mode 100755 index 00000000..2f4c4e20 --- /dev/null +++ b/adi_library/axi_ad3552r/axi_ad3552r.v @@ -0,0 +1,233 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad3552r #( + + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter DDS_DISABLE = 0, + parameter DDS_TYPE = 1, + parameter DDS_CORDIC_DW = 16, + parameter DDS_CORDIC_PHASE_DW = 16 +) ( + + // DAC INTERFACE + + input dac_clk, + + input [31:0] dma_data, + input valid_in_dma, + input valid_in_dma_sec, + output dac_data_ready, + + input [15:0] data_in_a, + input [15:0] data_in_b, + input valid_in_a, + input valid_in_b, + + output dac_sclk, + output dac_csn, + input [ 3:0] sdio_i, + output [ 3:0] sdio_o, + output sdio_t, + + // sync transfer between 2 DAC'S + + input external_sync, + output sync_ext_device, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready +); + + // internal clocks and resets + + wire dac_rst_s; + wire up_clk; + wire up_rstn; + + // internal signals + + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire up_wack_s; + wire up_rreq_s; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_s; + wire up_rack_s; + + wire [ 7:0] address; + wire [23:0] data_read; + wire [23:0] data_write; + wire ddr_sdr_n; + wire symb_8_16b; + wire transfer_data; + wire stream; + wire [31:0] dac_data; + wire dac_valid; + wire if_busy; + wire dac_ext_sync_arm; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // device interface + axi_ad3552r_if axi_ad3552r_interface ( + .clk_in(dac_clk), + .reset_in(dac_rst_s), + .dac_data(dac_data), + .dac_data_valid(dac_valid), + .dac_data_valid_ext(valid_in_dma_sec), + .dac_data_ready(dac_data_ready), + .address(address), + .data_read(data_read), + .data_write(data_write), + .sdr_ddr_n(sdr_ddr_n), + .symb_8_16b(symb_8_16b), + .transfer_data(transfer_data), + .stream(stream), + .if_busy(if_busy), + .external_sync(external_sync), + .external_sync_arm(dac_ext_sync_arm), + .sync_ext_device(sync_ext_device), + .sclk(dac_sclk), + .csn(dac_csn), + .sdio_i(sdio_i), + .sdio_o(sdio_o), + .sdio_t(sdio_t)); + + // core + axi_ad3552r_core #( + .ID(ID), + .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), + .FPGA_FAMILY(FPGA_FAMILY), + .SPEED_GRADE(SPEED_GRADE), + .DEV_PACKAGE(DEV_PACKAGE), + .DDS_DISABLE(DDS_DISABLE), + .DDS_TYPE(DDS_TYPE), + .DDS_CORDIC_DW(DDS_CORDIC_DW), + .DDS_CORDIC_PHASE_DW(DDS_CORDIC_PHASE_DW) + ) axi_ad3552r_up_core ( + .dac_clk(dac_clk), + .dac_rst(dac_rst_s), + .adc_data_in_a(data_in_a), + .adc_data_in_b(data_in_b), + .dma_data(dma_data), + .adc_valid_in_a(valid_in_a), + .adc_valid_in_b(valid_in_b), + .valid_in_dma(valid_in_dma), + .dac_data_ready(dac_data_ready), + .dac_data(dac_data), + .dac_valid(dac_valid), + .address(address), + .data_read(data_read), + .data_write(data_write), + .sdr_ddr_n(sdr_ddr_n), + .symb_8_16b(symb_8_16b), + .transfer_data(transfer_data), + .stream(stream), + .dac_ext_sync_arm(dac_ext_sync_arm), + .if_busy(if_busy), + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_wreq(up_wreq_s), + .up_waddr(up_waddr_s), + .up_wdata(up_wdata_s), + .up_wack(up_wack_s), + .up_rreq(up_rreq_s), + .up_raddr(up_raddr_s), + .up_rdata(up_rdata_s), + .up_rack(up_rack_s)); + + // up bus interface + + up_axi i_up_axi( + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_axi_awvalid(s_axi_awvalid), + .up_axi_awaddr(s_axi_awaddr), + .up_axi_awready(s_axi_awready), + .up_axi_wvalid(s_axi_wvalid), + .up_axi_wdata(s_axi_wdata), + .up_axi_wstrb(s_axi_wstrb), + .up_axi_wready(s_axi_wready), + .up_axi_bvalid(s_axi_bvalid), + .up_axi_bresp(s_axi_bresp), + .up_axi_bready(s_axi_bready), + .up_axi_arvalid(s_axi_arvalid), + .up_axi_araddr(s_axi_araddr), + .up_axi_arready(s_axi_arready), + .up_axi_rvalid(s_axi_rvalid), + .up_axi_rresp(s_axi_rresp), + .up_axi_rdata(s_axi_rdata), + .up_axi_rready(s_axi_rready), + .up_wreq(up_wreq_s), + .up_waddr(up_waddr_s), + .up_wdata(up_wdata_s), + .up_wack(up_wack_s), + .up_rreq(up_rreq_s), + .up_raddr(up_raddr_s), + .up_rdata(up_rdata_s), + .up_rack(up_rack_s)); +endmodule diff --git a/adi_library/axi_ad3552r/axi_ad3552r.xpr b/adi_library/axi_ad3552r/axi_ad3552r.xpr new file mode 100644 index 00000000..e0150b1c --- /dev/null +++ b/adi_library/axi_ad3552r/axi_ad3552r.xpr @@ -0,0 +1,557 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_ad3552r/axi_ad3552r_channel.v b/adi_library/axi_ad3552r/axi_ad3552r_channel.v new file mode 100755 index 00000000..0a73e9d0 --- /dev/null +++ b/adi_library/axi_ad3552r/axi_ad3552r_channel.v @@ -0,0 +1,227 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modificat +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad3552r_channel #( + + parameter CHANNEL_ID = 32'h0, + parameter DDS_DISABLE = 0, + parameter DDS_TYPE = 1, + parameter DDS_CORDIC_DW = 16, + parameter DDS_CORDIC_PHASE_DW = 16 +) ( + + // dac interface + + input dac_clk, + input dac_rst, + output dac_data_valid, + output [15:0] dac_data, + + // input sources + + input [15:0] dma_data, + input [15:0] adc_data, + input valid_in_adc, + input valid_in_dma, + input dac_data_ready, + + // processor interface + + input dac_data_sync, + input dac_dfmt_type, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // internal signals + + wire [15:0] formatted_dma_data; + wire [15:0] formatted_adc_data; + wire [ 3:0] dac_data_sel_s; + + wire [15:0] dac_dds_data_s; + wire [15:0] dac_dds_scale_1_s; + wire [15:0] dac_dds_init_1_s; + wire [15:0] dac_dds_incr_1_s; + wire [15:0] dac_dds_scale_2_s; + wire [15:0] dac_dds_init_2_s; + wire [15:0] dac_dds_incr_2_s; + wire [15:0] dac_pat_data_1_s; + wire [15:0] dac_pat_data_2_s; + + reg [15:0] ramp_pattern = 16'h0000; + reg ramp_valid = 1'b0; + reg [15:0] dac_data_int; + reg dac_data_valid_int; + + assign dac_data = dac_data_int; + assign dac_data_valid = dac_data_valid_int; + + assign formatted_dma_data [15] = dac_dfmt_type ^ dma_data[15]; + assign formatted_dma_data [14:0] = dma_data[14:0]; + assign formatted_adc_data [15] = dac_dfmt_type ^ adc_data[15]; + assign formatted_adc_data [14:0] = adc_data[14:0]; + + always @ (*) begin + case(dac_data_sel_s) + 4'h0 : + begin + dac_data_int = dac_dds_data_s; + dac_data_valid_int = 1'b1; + end + 4'h2 : + begin + dac_data_int = formatted_dma_data; + dac_data_valid_int = valid_in_dma; + end + 4'h3 : + begin + dac_data_int = 16'b0; + dac_data_valid_int = 1'b1; + end + 4'h8 : + begin + dac_data_int = formatted_adc_data; + dac_data_valid_int = valid_in_adc; + end + 4'hb : + begin + dac_data_int = ramp_pattern; + dac_data_valid_int = ramp_valid; + end + default : + begin + dac_data_int = 16'b0; + dac_data_valid_int = 1'b1; + end + endcase + end + + // ramp generator + + always @(posedge dac_clk) begin + ramp_valid <= 1'b1; + if(dac_data_ready == 1'b1) begin + ramp_pattern <= ramp_pattern + 1'b1; + end else begin + ramp_pattern <= ramp_pattern; + end + if(ramp_pattern == 16'hffff || dac_rst == 1'b1) begin + ramp_pattern <= 16'h0; + end + end + + ad_dds #( + .DISABLE (DDS_DISABLE), + .DDS_DW (16), + .PHASE_DW (16), + .DDS_TYPE (DDS_TYPE), + .CORDIC_DW (DDS_CORDIC_DW), + .CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW), + .CLK_RATIO (1) + ) i_dds ( + .clk (dac_clk), + .dac_dds_format (dac_dfmt_type), + .dac_data_sync (dac_data_sync), + .dac_valid (dac_data_ready), + .tone_1_scale (dac_dds_scale_1_s), + .tone_2_scale (dac_dds_scale_2_s), + .tone_1_init_offset (dac_dds_init_1_s), + .tone_2_init_offset (dac_dds_init_2_s), + .tone_1_freq_word (dac_dds_incr_1_s), + .tone_2_freq_word (dac_dds_incr_2_s), + .dac_dds_data (dac_dds_data_s)); + + // single channel processor + + up_dac_channel #( + .CHANNEL_ID(CHANNEL_ID), + .COMMON_ID(6'h01) + ) dac_channel ( + .dac_clk(dac_clk), + .dac_rst(dac_rst), + .dac_dds_scale_1(dac_dds_scale_1_s), + .dac_dds_init_1(dac_dds_init_1_s), + .dac_dds_incr_1(dac_dds_incr_1_s), + .dac_dds_scale_2(dac_dds_scale_2_s), + .dac_dds_init_2(dac_dds_init_2_s), + .dac_dds_incr_2(dac_dds_incr_2_s), + .dac_pat_data_1(dac_pat_data_1_s), + .dac_pat_data_2(dac_pat_data_2_s), + .dac_data_sel(dac_data_sel_s), + .dac_mask_enable(), + .dac_iq_mode(), + .dac_iqcor_enb(), + .dac_iqcor_coeff_1(), + .dac_iqcor_coeff_2(), + .dac_src_chan_sel(), + .up_usr_datatype_be(), + .up_usr_datatype_signed(), + .up_usr_datatype_shift(), + .up_usr_datatype_total_bits(), + .up_usr_datatype_bits(), + .up_usr_interpolation_m(), + .up_usr_interpolation_n(), + .dac_usr_datatype_be(1'd0), + .dac_usr_datatype_signed(1'd1), + .dac_usr_datatype_shift(8'd0), + .dac_usr_datatype_total_bits(8'd16), + .dac_usr_datatype_bits(8'd16), + .dac_usr_interpolation_m(16'd1), + .dac_usr_interpolation_n(16'd1), + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_wack(up_wack), + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata), + .up_rack(up_rack)); +endmodule diff --git a/adi_library/axi_ad3552r/axi_ad3552r_core.v b/adi_library/axi_ad3552r/axi_ad3552r_core.v new file mode 100755 index 00000000..a0fadfdd --- /dev/null +++ b/adi_library/axi_ad3552r/axi_ad3552r_core.v @@ -0,0 +1,261 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad3552r_core #( + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter DDS_DISABLE = 0, + parameter DDS_TYPE = 1, + parameter DDS_CORDIC_DW = 16, + parameter DDS_CORDIC_PHASE_DW = 16 +) ( + + // dac interface + + input dac_clk, + output dac_rst, + input [15:0] adc_data_in_a, + input [15:0] adc_data_in_b, + input [31:0] dma_data, + input adc_valid_in_a, + input adc_valid_in_b, + input valid_in_dma, + output [31:0] dac_data, + output dac_valid, + input dac_data_ready, + + // output + + output [ 7:0] address, + input if_busy, + input [23:0] data_read, + output [23:0] data_write, + output sdr_ddr_n, + output symb_8_16b, + output transfer_data, + output stream, + output dac_ext_sync_arm, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack +); + + wire [31:0] up_rdata_0_s; + wire up_rack_0_s; + wire up_wack_0_s; + wire [31:0] up_rdata_1_s; + wire up_rack_1_s; + wire up_wack_1_s; + wire [31:0] up_rdata_s; + wire up_rack_s; + wire up_wack_s; + + wire [15:0] dac_data_channel_0; + wire [15:0] dac_data_channel_1; + wire dac_valid_channel_0; + wire dac_valid_channel_1; + wire dac_rst_s; + + wire [31:0] dac_data_control; + wire [31:0] dac_control; + + wire dac_data_sync; + wire dac_dfmt_type; + + // defaults + + assign dac_rst = dac_rst_s; + assign dac_data = {dac_data_channel_1 ,dac_data_channel_0}; + assign dac_valid = dac_valid_channel_0 | dac_valid_channel_1; + + assign data_write = dac_data_control[23:0]; + assign transfer_data = dac_control[0]; + assign stream = dac_control[1]; + assign address = dac_control[31:24]; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if(up_rstn == 0) begin + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_rdata <= up_rdata_s | up_rdata_0_s | up_rdata_1_s; + up_rack <= up_rack_s | up_rack_0_s | up_rack_1_s; + up_wack <= up_wack_s | up_wack_0_s | up_wack_1_s; + end + end + + // DAC CHANNEL 0 + + axi_ad3552r_channel #( + .CHANNEL_ID(0), + .DDS_DISABLE(DDS_DISABLE), + .DDS_TYPE(DDS_TYPE), + .DDS_CORDIC_DW(DDS_CORDIC_DW), + .DDS_CORDIC_PHASE_DW(DDS_CORDIC_PHASE_DW) + ) axi_ad3552r_channel_0 ( + .dac_clk(dac_clk), + .dac_rst(dac_rst_s), + .dac_data_valid(dac_valid_channel_0), + .dac_data(dac_data_channel_0), + .dma_data(dma_data[15:0]), + .dac_data_ready(dac_data_ready), + .adc_data(adc_data_in_a), + .valid_in_adc(adc_valid_in_a), + .valid_in_dma(valid_in_dma), + .dac_data_sync(dac_data_sync), + .dac_dfmt_type(dac_dfmt_type), + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_wack(up_wack_0_s), + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata_0_s), + .up_rack(up_rack_0_s)); + + // DAC CHANNEL 1 + + axi_ad3552r_channel #( + .CHANNEL_ID(1), + .DDS_DISABLE(DDS_DISABLE), + .DDS_TYPE(DDS_TYPE), + .DDS_CORDIC_DW(DDS_CORDIC_DW), + .DDS_CORDIC_PHASE_DW(DDS_CORDIC_PHASE_DW) + ) axi_ad3552r_channel_1( + .dac_clk(dac_clk), + .dac_rst(dac_rst_s), + .dac_data_valid(dac_valid_channel_1), + .dac_data(dac_data_channel_1), + .dma_data(dma_data[31:16]), + .dac_data_ready(dac_data_ready), + .adc_data(adc_data_in_b), + .valid_in_adc(adc_valid_in_b), + .valid_in_dma(valid_in_dma), + .dac_data_sync(dac_data_sync), + .dac_dfmt_type(dac_dfmt_type), + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_wack(up_wack_1_s), + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata_1_s), + .up_rack(up_rack_1_s)); + + // dac common processor interface + + up_dac_common #( + .ID(ID), + .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), + .FPGA_FAMILY(FPGA_FAMILY), + .SPEED_GRADE(SPEED_GRADE), + .DEV_PACKAGE(DEV_PACKAGE), + .COMMON_ID(6'h00) + ) axi_ad3552r_common_core ( + .mmcm_rst(), + .dac_clk(dac_clk), + .dac_rst(dac_rst_s), + .dac_num_lanes(), + .dac_sdr_ddr_n(sdr_ddr_n), + .dac_symb_op(), + .dac_symb_8_16b(symb_8_16b), + .dac_sync(dac_data_sync), + .dac_ext_sync_arm(dac_ext_sync_arm), + .dac_ext_sync_disarm(), + .dac_ext_sync_manual_req(), + .dac_frame(), + .dac_clksel(), + .dac_custom_wr(dac_data_control), + .dac_custom_rd({8'b0, data_read}), + .dac_custom_control(dac_control), + .dac_status_if_busy(if_busy), + .dac_par_type(), + .dac_par_enb(), + .dac_r1_mode(), + .dac_datafmt(dac_dfmt_type), + .dac_datarate(), + .dac_status(), + .dac_sync_in_status(), + .dac_status_unf(), + .dac_clk_ratio(32'd1), + .up_dac_ce(), + .up_pps_rcounter(32'd0), + .up_pps_status(1'd0), + .up_pps_irq_mask(), + .up_dac_r1_mode(), + .up_drp_sel(), + .up_drp_wr(), + .up_drp_addr(), + .up_drp_wdata() , + .up_drp_rdata(32'd0), + .up_drp_ready(1'd1), + .up_drp_locked(1'd1), + .up_usr_chanmax(), + .dac_usr_chanmax(8'd1), + .up_dac_gpio_in(32'd0), + .up_dac_gpio_out(), + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_wack(up_wack_s), + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata_s), + .up_rack (up_rack_s)); +endmodule diff --git a/adi_library/axi_ad3552r/axi_ad3552r_if.v b/adi_library/axi_ad3552r/axi_ad3552r_if.v new file mode 100755 index 00000000..0b67b64c --- /dev/null +++ b/adi_library/axi_ad3552r/axi_ad3552r_if.v @@ -0,0 +1,316 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad3552r_if ( + + input clk_in, // 120MHz + input reset_in, + input [31:0] dac_data, + input dac_data_valid, + input dac_data_valid_ext, + output dac_data_ready, + + input [ 7:0] address, + input [23:0] data_write, + input sdr_ddr_n, + input symb_8_16b, + input transfer_data, + input stream, + input external_sync, + input external_sync_arm, + + output if_busy, + output sync_ext_device, + output reg [23:0] data_read, + + // DAC control signals + + output sclk, + output reg csn, + input [ 3:0] sdio_i, + output [ 3:0] sdio_o, + output sdio_t +); + + wire transfer_data_s; + wire start_synced; + wire [31:0] dac_data_int; + wire dac_data_valid_synced; + wire external_sync_s; + + reg [55:0] transfer_reg = 56'h0; + reg [15:0] counter = 16'h0; + reg [ 2:0] transfer_state = 0; + reg [ 2:0] transfer_state_next = 0; + reg cycle_done = 1'b0; + reg transfer_step = 1'b0; + reg sclk_ddr = 1'b0; + reg full_speed = 1'b0; + reg transfer_data_d = 1'b0; + reg transfer_data_dd = 1'b0; + reg [ 3:0] valid_captured_d = 4'b0; + reg data_r_wn = 1'b0; + reg valid_captured = 1'b0; + reg start_transfer = 1'b0; + reg if_busy_reg = 1'b0; + reg dac_data_ready_s = 1'b0; + reg external_sync_arm_reg = 1'b0; + reg external_sync_reg = 1'b0; + + localparam [ 2:0] IDLE = 3'h0, + CS_LOW = 3'h1, + WRITE_ADDRESS = 3'h2, + TRANSFER_REGISTER = 3'h3, + READ_REGISTER = 3'h4, + STREAM = 3'h5, + CS_HIGH = 3'h6; + + assign if_busy = if_busy_reg; + + // transform the transfer data rising edge into a pulse + + assign transfer_data_s = transfer_data_d & ~transfer_data_dd; + + // start the data stream transfer after valid has been captured + + assign start_synced = valid_captured_d[1] & start_transfer & stream; + assign sync_ext_device = start_synced ; + + // use dac_data valid from an external source only if external_sync_arm_reg is 1 + + assign dac_data_valid_synced = (external_sync_arm_reg == 1'b1) ? (dac_data_valid & dac_data_valid_ext) : dac_data_valid ; + assign dac_data_ready = dac_data_ready_s & dac_data_valid_synced; + assign dac_data_int = dac_data; + + // sync the data only if the synchronizations has been armed in software + + assign external_sync_s = ~external_sync_arm_reg | external_sync_reg; + + always @(posedge clk_in) begin + if(reset_in == 1'b1) begin + transfer_data_d <= 'd0; + transfer_data_dd <= 'd0; + valid_captured_d <= 4'b0; + valid_captured <= 1'b0; + end else begin + transfer_data_d <= transfer_data; + transfer_data_dd <= transfer_data_d; + valid_captured_d <= {valid_captured_d[2:0], valid_captured}; + end + if(transfer_state == CS_HIGH || stream == 1'b0) begin + start_transfer <= 1'b0; + valid_captured <= 1'b0; + valid_captured_d <= 4'b0; + end + + // pulse to level conversion + + if(external_sync_arm == 1'b1) begin + external_sync_arm_reg <= 1'b1; + end + if(external_sync == 1'b1) begin + external_sync_reg <= 1'b1; + end + + if(transfer_state == CS_HIGH) begin + external_sync_arm_reg <= 1'b0; + external_sync_reg <= 1'b0; + end + + if(dac_data_valid == 1'b1 && start_transfer == 1'b1) begin + valid_captured <= 1'b1; + end + if(transfer_data == 1'b1) begin + start_transfer <= 1'b1; + end + + end + + always @(posedge clk_in) begin + if (reset_in == 1'b1) begin + transfer_state <= IDLE; + end else begin + transfer_state <= transfer_state_next; + end + end + + // FSM next state logic + + always @(*) begin + case (transfer_state) + IDLE : begin + // goes in to the next state only if the control is to transfer register or synced transfer(if it's armed in software) + transfer_state_next = ((transfer_data_s == 1'b1 && stream == 1'b0) || (start_synced == 1'b1 && external_sync_s)) ? CS_LOW : IDLE; + csn = 1'b1; + transfer_step = 0; + cycle_done = 0; + end + CS_LOW : begin + // brings CS down + // loads all configuration + // puts data on the SDIO pins + // needs 5 ns before risedge of the clock + transfer_state_next = WRITE_ADDRESS; + csn = 1'b0; + transfer_step = 0; + cycle_done = 0; + end + WRITE_ADDRESS : begin + // writes the address + // it works either at full speed (60 MHz) when streaming or normal + // speed (15 MHz) + // full speed - 2 clock cycles + // half speed 8 clock cycles + cycle_done = full_speed ? (counter == 16'h3) : (counter == 16'hf); + transfer_state_next = cycle_done ? (stream ? STREAM : TRANSFER_REGISTER) : WRITE_ADDRESS ; + csn = 1'b0; + // in streaming, change data on falledge. On regular transfer, change data on negedge. + //A single step should be done for 8 bit addressing + transfer_step = full_speed ? (counter[0]== 1'h1) : ((counter[4:0] == 5'h5)); + end + TRANSFER_REGISTER : begin + // always works at 15 MHz + // can be DDR or SDR + cycle_done = sdr_ddr_n ? (symb_8_16b ? (counter == 16'h10) : (counter == 16'h20)) : + (symb_8_16b ? (counter == 16'h09) : (counter == 16'h11)); + transfer_state_next = cycle_done ? CS_HIGH : TRANSFER_REGISTER; + csn = 1'b0; + // in DDR mode, change data on falledge + transfer_step = sdr_ddr_n ? (counter[2:0] == 3'h0) : (counter[1:0] == 2'h0); + end + STREAM : begin + // can be DDR or SDR + // in DDR mode needs to be make sure the clock and data is shifted by 2 ns + cycle_done = stream ? (sdr_ddr_n ? (counter == 16'h0f) : (counter == 16'h7)): + (sdr_ddr_n ? (counter == 16'h10) : (counter == 16'h7)); + transfer_state_next = (stream && external_sync_s) ? STREAM: ((cycle_done || external_sync_s == 1'b0) ? CS_HIGH :STREAM); + csn = 1'b0; + transfer_step = sdr_ddr_n ? counter[0] : 1'b1; + end + CS_HIGH : begin + cycle_done = 1'b1; + transfer_state_next = cycle_done ? IDLE : CS_HIGH; + csn = 1'b1; + transfer_step = 0; + end + default : begin + cycle_done = 0; + transfer_state_next = IDLE; + csn = 1'b1; + transfer_step = 0; + end + endcase + end + + // counter is used to time all states + // depends on number of clock cycles per phase + + always @(posedge clk_in) begin + if (transfer_state == IDLE || reset_in == 1'b1) begin + counter <= 'b0; + end else if (transfer_state == WRITE_ADDRESS | transfer_state == TRANSFER_REGISTER | transfer_state == STREAM) begin + if (cycle_done) begin + counter <= 0; + end else begin + counter <= counter + 1; + end + end + end + + always @(negedge clk_in) begin + if (transfer_state == STREAM | transfer_state == WRITE_ADDRESS) begin + sclk_ddr <= !sclk_ddr; + end else begin + sclk_ddr <= 0; + end + end + + // selection between 60 MHz and 15 MHz + + assign sclk = full_speed ? (sdr_ddr_n ? counter[0] : sclk_ddr) : counter[2]; + + always @(posedge clk_in) begin + if (transfer_state == CS_LOW) begin + data_r_wn <= address[7]; + end else if (transfer_state == CS_HIGH) begin + data_r_wn <=1'b0; + end + if (transfer_state == STREAM) begin + if (cycle_done == 1'b1) begin + dac_data_ready_s <= stream; + end else begin + dac_data_ready_s <= 1'b0; + end + end else begin + dac_data_ready_s <= 1'b0; + end + if (transfer_state == CS_LOW) begin + full_speed = stream; + if(stream) begin + transfer_reg <= {address,dac_data_int, 16'h0}; + end else begin + transfer_reg <= {address,data_write, 24'h0}; + end + end else if ((transfer_state == STREAM & cycle_done) || (transfer_state != STREAM && transfer_state_next == STREAM)) begin + transfer_reg <= {dac_data_int, 24'h0}; + end else if (transfer_step && transfer_state != CS_HIGH) begin + transfer_reg <= {transfer_reg[51:0], sdio_i}; + end + + if (transfer_state == CS_HIGH) begin + if (symb_8_16b == 1'b0) begin + data_read <= {8'h0,transfer_reg[15:0]}; + end else begin + data_read <= {16'h0,transfer_reg[7:0]}; + end + end else begin + data_read <= data_read; + end + if (transfer_state == CS_HIGH || transfer_state == IDLE) begin + if_busy_reg <= 1'b0; + end else begin + if_busy_reg <= 1'b1; + end + end + + // address[7] is r_wn : depends also on the state machine, input only when + // in TRANSFER register mode + + assign sdio_t = (data_r_wn & transfer_state == TRANSFER_REGISTER); + assign sdio_o = transfer_reg[55:52]; + +endmodule diff --git a/adi_library/axi_ad3552r/axi_ad3552r_if_tb b/adi_library/axi_ad3552r/axi_ad3552r_if_tb new file mode 100755 index 00000000..485bf965 --- /dev/null +++ b/adi_library/axi_ad3552r/axi_ad3552r_if_tb @@ -0,0 +1,7 @@ +#!/bin/bash + +SOURCE="$0.v" +SOURCE+=" axi_ad3552r_if.v" + +cd `dirname $0` +source ../common/tb/run_tb.sh diff --git a/adi_library/axi_ad3552r/axi_ad3552r_if_tb.v b/adi_library/axi_ad3552r/axi_ad3552r_if_tb.v new file mode 100755 index 00000000..16521acc --- /dev/null +++ b/adi_library/axi_ad3552r/axi_ad3552r_if_tb.v @@ -0,0 +1,239 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad3552r_if_tb; + parameter VCD_FILE = "axi_ad3552r_if_tb.vcd"; + + `define TIMEOUT 9000 + `include "../common/tb/tb_base.v" + + wire [ 23:0] data_read; + wire dac_sclk; + wire dac_csn; + wire dac_data_ready; + wire [ 3:0] sdio_i; + wire [ 3:0] sdio_o; + wire sdio_t; + wire [31:0] dac_data_final; + wire [ 3:0] readback_data_shift; + wire [ 4:0] data_increment_valid; + wire if_busy; + + reg [ 7:0] address_write = 8'b0; + reg dac_clk = 1'b0; + reg reset_in = 1'b1; + reg transfer_data = 1'b0; + reg sdr_ddr_n = 1'b1; + reg reg_8b_16bn = 1'b0; + reg stream = 1'b0; + reg [23:0] data_write = 24'h0; + reg dac_data_valid = 1'b0; + reg [ 3:0] shift_count = 4'b0; + reg [31:0] transfer_reg = 32'h89abcdef; + reg [ 4:0] valid_counter = 5'b0; + reg [31:0] dac_data = 32'b0; + + always #4 dac_clk <= ~dac_clk; + + initial begin + + #100 reset_in = 1'b0; + + // Write 8 bit SDR + + address_write = 8'h2c; + data_write = 24'hab0000; + sdr_ddr_n = 1'b1; + reg_8b_16bn = 1'b1; + stream = 1'b0; + #500 transfer_data = 1'b1; + #100 transfer_data = 1'b0; + + // Read 8 bit SDR + + address_write = 8'hac; + data_write = 24'h000000; + sdr_ddr_n = 1'b1; + reg_8b_16bn = 1'b1; + stream = 1'b0; + #500 transfer_data = 1'b1; + #100 transfer_data = 1'b0; + + // Write 16 bit SDR + + address_write = 8'h2c; + data_write = 24'h123400; + sdr_ddr_n = 1'b1; + reg_8b_16bn = 1'b0; + stream = 1'b0; + #500 transfer_data = 1'b1; + #100 transfer_data = 1'b0; + + // Read 16 bit SDR + + address_write = 8'hac; + data_write = 24'h000000; + sdr_ddr_n = 1'b1; + reg_8b_16bn = 1'b0; + stream = 1'b0; + #500 transfer_data = 1'b1; + #100 transfer_data = 1'b0; + + #500; + + // Write 8 bit DDR + + address_write = 8'h2c; + data_write = 24'h120000; + sdr_ddr_n = 1'b0; + reg_8b_16bn = 1'b1; + stream = 1'b0; + #500 transfer_data = 1'b1; + #100 transfer_data = 1'b0; + + // Read 8 bit DDR + + address_write = 8'hac; + data_write = 24'h000000; + sdr_ddr_n = 1'b0; + reg_8b_16bn = 1'b1; + stream = 1'b0; + #500 transfer_data = 1'b1; + #100 transfer_data = 1'b0; + + // Write 16 bit DDR + + address_write = 8'h2c; + data_write = 24'h123400; + sdr_ddr_n = 1'b0; + reg_8b_16bn = 1'b0; + stream = 1'b0; + transfer_data = 1'b1; + #100 transfer_data = 1'b0; + + // Read 16 bit DDR + + address_write = 8'hac; + data_write = 24'h000000; + sdr_ddr_n = 1'b0; + reg_8b_16bn = 1'b0; + stream = 1'b0; + #500 transfer_data = 1'b1; + #100 transfer_data = 1'b0; + + #500; + + // Stream SDR + + address_write = 8'h2c; + sdr_ddr_n = 1'b1; + reg_8b_16bn = 1'b0; + stream = 1'b1; + transfer_data = 1'b1; + #100 transfer_data = 1'b0; + #1000 stream = 1'b0; + + #500; + + // Stream DDR + + address_write = 8'h2c; + reg_8b_16bn = 1'b1; + sdr_ddr_n = 1'b0; + stream = 1'b1; + transfer_data = 1'b1; + #100 transfer_data = 1'b0; + #1000 stream = 1'b0; + + end + + // data is incremented at each complete cycle + + assign dac_data_final = (stream == 1'b1) ? dac_data : data_write; + assign data_increment_valid = (sdr_ddr_n ) ? 5'd16: 5'h8; + + always @(posedge dac_clk) begin + if (valid_counter == data_increment_valid) begin + dac_data <= dac_data + 32'h00010002; + valid_counter <= 3'b0; + dac_data_valid <= 1'b1; + end else begin + dac_data <= dac_data; + valid_counter <= valid_counter + 3'b1; + dac_data_valid <= 1'b0; + end + end + + // data is circullary shifted at every sampling edge + + assign readback_data_shift = (sdr_ddr_n ) ? 4'h8 : 4'h4; + assign sdio_i = (sdio_t === 1'b1) ? transfer_reg[31:28] : 4'b0; + + always @(posedge dac_clk) begin + if (shift_count == readback_data_shift) begin + transfer_reg <= {transfer_reg[27:0],transfer_reg[31:28]}; + end else if (sdio_t === 1'b1) begin + transfer_reg <= transfer_reg; + end + if (shift_count == readback_data_shift || dac_csn == 1'b1) begin + shift_count <= 3'b0; + end else if (sdio_t === 1'b1) begin + shift_count <= shift_count + 3'b1; + end + end + + axi_ad3552r_if axi_ad3552r_interface ( + .clk_in(dac_clk), + .reset_in(reset_in), + .dac_data(dac_data_final), + .dac_data_valid(dac_data_valid), + .address(address_write), + .data_read(data_read), + .data_write(data_write), + .sdr_ddr_n(sdr_ddr_n), + .symb_8_16b(reg_8b_16bn), + .transfer_data(transfer_data), + .stream(stream), + .dac_data_ready(dac_data_ready), + .if_busy(if_busy), + .sclk(dac_sclk), + .csn(dac_csn), + .sdio_i(sdio_i), + .sdio_o(sdio_o), + .sdio_t(sdio_t)); + +endmodule diff --git a/adi_library/axi_ad3552r/axi_ad3552r_ip.tcl b/adi_library/axi_ad3552r/axi_ad3552r_ip.tcl new file mode 100755 index 00000000..561cca39 --- /dev/null +++ b/adi_library/axi_ad3552r/axi_ad3552r_ip.tcl @@ -0,0 +1,51 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_ad3552r +adi_ip_files axi_ad3552r [list \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_dac_common.v" \ + "$ad_hdl_dir/library/common/up_dac_channel.v" \ + "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine.v" \ + "$ad_hdl_dir/library/common/ad_dds_2.v" \ + "$ad_hdl_dir/library/common/ad_dds_1.v" \ + "$ad_hdl_dir/library/common/ad_dds.v" \ + "$ad_hdl_dir/library/common/ad_addsub.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "axi_ad3552r_channel.v" \ + "axi_ad3552r_core.v" \ + "axi_ad3552r_if.v" \ + "axi_ad3552r.v" ] + +adi_ip_properties axi_ad3552r +adi_init_bd_tcl +adi_ip_bd axi_ad3552r "bd/bd.tcl" + +set cc [ipx::current_core] + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad3552r} $cc + +set_property driver_value 0 [ipx::get_ports *dac* -of_objects $cc] +set_property driver_value 0 [ipx::get_ports *data* -of_objects $cc] +set_property driver_value 0 [ipx::get_ports *valid* -of_objects $cc] +ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 $cc + +adi_add_auto_fpga_spec_params + +ipx::create_xgui_files $cc +ipx::save_core $cc diff --git a/adi_library/axi_ad3552r/bd/bd.tcl b/adi_library/axi_ad3552r/bd/bd.tcl new file mode 100644 index 00000000..dceb9498 --- /dev/null +++ b/adi_library/axi_ad3552r/bd/bd.tcl @@ -0,0 +1,47 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + DEV_PACKAGE \ + SPEED_GRADE \ + FPGA_FAMILY \ + FPGA_TECHNOLOGY" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/axi_ad3552r/component.xml b/adi_library/axi_ad3552r/component.xml new file mode 100644 index 00000000..7e084116 --- /dev/null +++ b/adi_library/axi_ad3552r/component.xml @@ -0,0 +1,1318 @@ + + + analog.com + user + axi_ad3552r + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + dac_clk + + + + + + + CLK + + + dac_clk + + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_ad3552r + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 96287bb0 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_ad3552r + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + abc33695 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 681786b0 + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + + + dac_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + dma_data + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + valid_in_dma + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + valid_in_dma_sec + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + dac_data_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + data_in_a + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + data_in_b + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + valid_in_a + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + valid_in_b + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + dac_sclk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + dac_csn + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + sdio_i + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sdio_o + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sdio_t + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + external_sync + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + sync_ext_device + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + DDS_DISABLE + Dds Disable + 0 + + + DDS_TYPE + Dds Type + 1 + + + DDS_CORDIC_DW + Dds Cordic Dw + 16 + + + DDS_CORDIC_PHASE_DW + Dds Cordic Phase Dw + 16 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_00ecfe9a + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + + + choice_pairs_19f99f31 + 0 + 10 + 11 + 12 + 13 + 14 + 20 + 21 + 22 + 23 + 24 + 25 + 30 + + + choice_pairs_28f798a2 + 0 + 1 + 2 + 3 + 4 + + + choice_pairs_fc01a186 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../xilinx/common/up_clock_mon_constr.xdc + xdc + + + ../common/ad_dds.v + verilogSource + + + ../common/ad_dds_1.v + verilogSource + + + ../common/ad_dds_2.v + verilogSource + + + ../common/ad_dds_cordic_pipe.v + verilogSource + + + ../common/ad_dds_sine.v + verilogSource + + + ../common/ad_dds_sine_cordic.v + verilogSource + + + ../xilinx/common/ad_mul.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + axi_ad3552r_channel.v + verilogSource + + + axi_ad3552r_core.v + verilogSource + + + axi_ad3552r_if.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_dac_channel.v + verilogSource + + + ../common/up_dac_common.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad3552r.v + verilogSource + CHECKSUM_6bd0b0d1 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_dds.v + verilogSource + + + ../common/ad_dds_1.v + verilogSource + + + ../common/ad_dds_2.v + verilogSource + + + ../common/ad_dds_cordic_pipe.v + verilogSource + + + ../common/ad_dds_sine.v + verilogSource + + + ../common/ad_dds_sine_cordic.v + verilogSource + + + ../xilinx/common/ad_mul.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + axi_ad3552r_channel.v + verilogSource + + + axi_ad3552r_core.v + verilogSource + + + axi_ad3552r_if.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_dac_channel.v + verilogSource + + + ../common/up_dac_common.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad3552r.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_ad3552r_v1_0.tcl + tclSource + CHECKSUM_fd1c12bb + XGUI_VERSION_2 + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + axi_ad3552r_v1_0 + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + DDS_DISABLE + Dds Disable + 0 + + + DDS_TYPE + Dds Type + 1 + + + DDS_CORDIC_DW + Dds Cordic Dw + 16 + + + DDS_CORDIC_PHASE_DW + Dds Cordic Phase Dw + 16 + + + Component_Name + axi_ad3552r_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_ad3552r_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_ad3552r + 1 + 2024-01-14T03:37:52Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_ad3552r/temporary_case_dependencies.mk b/adi_library/axi_ad3552r/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/axi_ad3552r/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/axi_ad3552r/xgui/axi_ad3552r_v1_0.tcl b/adi_library/axi_ad3552r/xgui/axi_ad3552r_v1_0.tcl new file mode 100644 index 00000000..b7eda292 --- /dev/null +++ b/adi_library/axi_ad3552r/xgui/axi_ad3552r_v1_0.tcl @@ -0,0 +1,148 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DDS_CORDIC_DW" -parent ${Page_0} + ipgui::add_param $IPINST -name "DDS_CORDIC_PHASE_DW" -parent ${Page_0} + ipgui::add_param $IPINST -name "DDS_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "DDS_TYPE" -parent ${Page_0} + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.DDS_CORDIC_DW { PARAM_VALUE.DDS_CORDIC_DW } { + # Procedure called to update DDS_CORDIC_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DDS_CORDIC_DW { PARAM_VALUE.DDS_CORDIC_DW } { + # Procedure called to validate DDS_CORDIC_DW + return true +} + +proc update_PARAM_VALUE.DDS_CORDIC_PHASE_DW { PARAM_VALUE.DDS_CORDIC_PHASE_DW } { + # Procedure called to update DDS_CORDIC_PHASE_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DDS_CORDIC_PHASE_DW { PARAM_VALUE.DDS_CORDIC_PHASE_DW } { + # Procedure called to validate DDS_CORDIC_PHASE_DW + return true +} + +proc update_PARAM_VALUE.DDS_DISABLE { PARAM_VALUE.DDS_DISABLE } { + # Procedure called to update DDS_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DDS_DISABLE { PARAM_VALUE.DDS_DISABLE } { + # Procedure called to validate DDS_DISABLE + return true +} + +proc update_PARAM_VALUE.DDS_TYPE { PARAM_VALUE.DDS_TYPE } { + # Procedure called to update DDS_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DDS_TYPE { PARAM_VALUE.DDS_TYPE } { + # Procedure called to validate DDS_TYPE + return true +} + +proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to validate DEV_PACKAGE + return true +} + +proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to validate FPGA_FAMILY + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to validate SPEED_GRADE + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY} +} + +proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE} +} + +proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE} +} + +proc update_MODELPARAM_VALUE.DDS_DISABLE { MODELPARAM_VALUE.DDS_DISABLE PARAM_VALUE.DDS_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DDS_DISABLE}] ${MODELPARAM_VALUE.DDS_DISABLE} +} + +proc update_MODELPARAM_VALUE.DDS_TYPE { MODELPARAM_VALUE.DDS_TYPE PARAM_VALUE.DDS_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DDS_TYPE}] ${MODELPARAM_VALUE.DDS_TYPE} +} + +proc update_MODELPARAM_VALUE.DDS_CORDIC_DW { MODELPARAM_VALUE.DDS_CORDIC_DW PARAM_VALUE.DDS_CORDIC_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DDS_CORDIC_DW}] ${MODELPARAM_VALUE.DDS_CORDIC_DW} +} + +proc update_MODELPARAM_VALUE.DDS_CORDIC_PHASE_DW { MODELPARAM_VALUE.DDS_CORDIC_PHASE_DW PARAM_VALUE.DDS_CORDIC_PHASE_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DDS_CORDIC_PHASE_DW}] ${MODELPARAM_VALUE.DDS_CORDIC_PHASE_DW} +} + diff --git a/adi_library/axi_ad4858/Makefile b/adi_library/axi_ad4858/Makefile new file mode 100644 index 00000000..08691868 --- /dev/null +++ b/adi_library/axi_ad4858/Makefile @@ -0,0 +1,35 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_ad4858 + +GENERIC_DEPS += ../common/ad_datafmt.v +GENERIC_DEPS += ../common/ad_edge_detect.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_adc_channel.v +GENERIC_DEPS += ../common/up_adc_common.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_delay_cntrl.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_ad4858.v +GENERIC_DEPS += axi_ad4858_channel.v +GENERIC_DEPS += axi_ad4858_cmos.v +GENERIC_DEPS += axi_ad4858_crc.v +GENERIC_DEPS += axi_ad4858_lvds.v + +XILINX_DEPS += ../util_cdc/sync_bits.v +XILINX_DEPS += ../xilinx/common/ad_data_in.v +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/ad_serdes_out.v +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_ad4858_constr.ttcl +XILINX_DEPS += axi_ad4858_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_ad4858/axi_ad4858.v b/adi_library/axi_ad4858/axi_ad4858.v new file mode 100644 index 00000000..75e56834 --- /dev/null +++ b/adi_library/axi_ad4858/axi_ad4858.v @@ -0,0 +1,539 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad4858 #( + + parameter FPGA_TECHNOLOGY = 0, + parameter DELAY_REFCLK_FREQ = 200, + parameter IODELAY_ENABLE = 1, + parameter ID = 0, + parameter LVDS_CMOS_N = 1, + parameter LANE_0_ENABLE = "1", + parameter LANE_1_ENABLE = "1", + parameter LANE_2_ENABLE = "1", + parameter LANE_3_ENABLE = "1", + parameter LANE_4_ENABLE = "1", + parameter LANE_5_ENABLE = "1", + parameter LANE_6_ENABLE = "1", + parameter LANE_7_ENABLE = "1", + parameter ECHO_CLK_EN = 1, + parameter EXTERNAL_CLK = 1 +) ( + + // clocks + + input delay_clk, + input external_clk, + input external_fast_clk, + + // physical data interface + + input cnvs, + input busy, + output lvds_cmos_n, + + // cmos if signals + + output scki, + input scko, + input lane_0, + input lane_1, + input lane_2, + input lane_3, + input lane_4, + input lane_5, + input lane_6, + input lane_7, + + // lvds if signals + + output scki_p, + output scki_n, + input scko_p, + input scko_n, + input sdo_p, + input sdo_n, + + // AXI Slave Memory Map + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + + // Write FIFO interface + + input adc_dovf, + output adc_valid, + output adc_enable_0, + output adc_enable_1, + output adc_enable_2, + output adc_enable_3, + output adc_enable_4, + output adc_enable_5, + output adc_enable_6, + output adc_enable_7, + output [31:0] adc_data_0, + output [31:0] adc_data_1, + output [31:0] adc_data_2, + output [31:0] adc_data_3, + output [31:0] adc_data_4, + output [31:0] adc_data_5, + output [31:0] adc_data_6, + output [31:0] adc_data_7 +); + + // localparam + + localparam [ 0:0] READ_RAW = 1'b1; + localparam CONFIG = {18'd0, READ_RAW, 5'd0, ~LVDS_CMOS_N[0], 7'd0}; + localparam [ 7:0] ACTIVE_LANES = { + LANE_7_ENABLE == 1 ? 1'b1 : 1'b0, + LANE_6_ENABLE == 1 ? 1'b1 : 1'b0, + LANE_5_ENABLE == 1 ? 1'b1 : 1'b0, + LANE_4_ENABLE == 1 ? 1'b1 : 1'b0, + LANE_3_ENABLE == 1 ? 1'b1 : 1'b0, + LANE_2_ENABLE == 1 ? 1'b1 : 1'b0, + LANE_1_ENABLE == 1 ? 1'b1 : 1'b0, + LANE_0_ENABLE == 1 ? 1'b1 : 1'b0}; + + // internal registers + + reg up_wack = 1'b0; + reg up_rack = 1'b0; + reg [31:0] up_rdata = 32'b0; + reg up_status_or = 1'b0; + reg [ 7:0] adc_reset; + reg adc_if_reset; + + // internal signals + + wire adc_rst_s; + wire adc_clk_s; + + wire scko_s; + wire scko_s_p; + wire scko_s_n; + + wire up_clk; + wire up_rstn; + wire up_rreq_s; + wire [13:0] up_raddr_s; + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire [31:0] up_rdata_s[0:9]; + wire [ 9:0] up_rack_s; + wire [ 9:0] up_wack_s; + + wire [255:0] adc_data_if_s; + wire [ 7:0] adc_enable_s; + wire [31:0] adc_data_s[7:0]; + wire adc_valid_if; + wire [ 7:0] adc_valid_s; + wire crc_error; + wire [ 7:0] adc_or; + wire [ 7:0] up_adc_or_s; + + wire [ 7:0] up_adc_pn_err; + wire [ 7:0] up_adc_pn_oos; + + wire [ 7:0] adc_custom_control; + wire [ 1:0] packet_format; + wire oversampling_en; + wire adc_crc_enable_s; + + wire delay_rst; + wire delay_locked; + + // defaults + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + assign lvds_cmos_n = LVDS_CMOS_N[0]; + + assign adc_enable_0 = adc_enable_s[0]; + assign adc_enable_1 = adc_enable_s[1]; + assign adc_enable_2 = adc_enable_s[2]; + assign adc_enable_3 = adc_enable_s[3]; + assign adc_enable_4 = adc_enable_s[4]; + assign adc_enable_5 = adc_enable_s[5]; + assign adc_enable_6 = adc_enable_s[6]; + assign adc_enable_7 = adc_enable_s[7]; + + assign adc_valid = adc_valid_s[0]; + + assign adc_data_0 = adc_data_s[0]; + assign adc_data_1 = adc_data_s[1]; + assign adc_data_2 = adc_data_s[2]; + assign adc_data_3 = adc_data_s[3]; + assign adc_data_4 = adc_data_s[4]; + assign adc_data_5 = adc_data_s[5]; + assign adc_data_6 = adc_data_s[6]; + assign adc_data_7 = adc_data_s[7]; + + assign packet_format = adc_custom_control[1:0]; + assign oversampling_en = adc_custom_control[2]; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_status_or <= 'd0; + up_wack <= 'd0; + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_status_or <= | up_adc_or_s; + up_wack <= |up_wack_s; + up_rack <= |up_rack_s; + up_rdata <= up_rdata_s[0] | + up_rdata_s[1] | + up_rdata_s[2] | + up_rdata_s[3] | + up_rdata_s[4] | + up_rdata_s[5] | + up_rdata_s[6] | + up_rdata_s[7] | + up_rdata_s[8] | + up_rdata_s[9]; + end + end + + genvar i; + generate + if (EXTERNAL_CLK == 1'b1) begin + assign adc_clk_s = external_clk; + end else begin + assign adc_clk_s = up_clk; + end + + always @(posedge adc_clk_s) begin + adc_if_reset <= adc_rst_s; + end + + if (LVDS_CMOS_N == 1) begin // LVDS + + wire up_dld; + wire [ 4:0] up_dwdata; + wire [ 4:0] up_drdata; + + assign scki = 1'b0; + if (ECHO_CLK_EN == 1'b1) begin + assign scko_s_p = scko_p; + assign scko_s_n = scko_n; + end else begin + assign scko_s_p = scki_p; + assign scko_s_n = scki_n; + end + + axi_ad4858_lvds #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .DELAY_REFCLK_FREQ(DELAY_REFCLK_FREQ), + .IODELAY_ENABLE (IODELAY_ENABLE) + ) i_ad4858_lvds_interface ( + .rst (adc_if_reset), + .clk (adc_clk_s), + .fast_clk (external_fast_clk), + .adc_enable (adc_enable_s), + .adc_crc_enable (adc_crc_enable_s), + .packet_format_in (packet_format), + .oversampling_en (oversampling_en), + .scki_p (scki_p), + .scki_n (scki_n), + .scko_p (scko_s_p), + .scko_n (scko_s_n), + .sdo_p (sdo_p), + .sdo_n (sdo_n), + .busy (busy), + .cnvs (cnvs), + .adc_data (adc_data_if_s), + .adc_valid (adc_valid_if), + .crc_error (crc_error), + .dev_status (), + .up_clk (up_clk), + .up_adc_dld (up_dld), + .up_adc_dwdata (up_dwdata), + .up_adc_drdata (up_drdata), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked)); + + up_delay_cntrl #( + .DATA_WIDTH(1), + .BASE_ADDRESS(6'h02) + ) i_delay_cntrl ( + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked), + .up_dld (up_dld), + .up_dwdata (up_dwdata), + .up_drdata (up_drdata), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[9]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[9]), + .up_rack (up_rack_s[9])); + + end else begin // CMOS + + wire [ 7:0] up_dld; + wire [39:0] up_dwdata; + wire [39:0] up_drdata; + + assign scki_p = 1'b0; + assign scki_n = 1'b1; + if (ECHO_CLK_EN == 1'b1) begin + assign scko_s = scko; + end else begin + assign scko_s = scki; + end + axi_ad4858_cmos #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .DELAY_REFCLK_FREQ(DELAY_REFCLK_FREQ), + .IODELAY_ENABLE (IODELAY_ENABLE), + .ACTIVE_LANE (ACTIVE_LANES) + ) i_ad4858_cmos_interface ( + .rst (adc_if_reset), + .clk (adc_clk_s), + .adc_enable (adc_enable_s), + .adc_crc_enable (adc_crc_enable_s), + .packet_format (packet_format), + .oversampling_en (oversampling_en), + .scki (scki), + .scko (scko_s), + .db_i ({lane_7, + lane_6, + lane_5, + lane_4, + lane_3, + lane_2, + lane_1, + lane_0}), + .busy (busy), + .cnvs (cnvs), + .adc_data (adc_data_if_s), + .adc_valid (adc_valid_if), + .crc_error (crc_error), + .dev_status (), + .up_clk (up_clk), + .up_adc_dld (up_dld), + .up_adc_dwdata (up_dwdata), + .up_adc_drdata (up_drdata), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked)); + + up_delay_cntrl #( + .DATA_WIDTH(8), + .BASE_ADDRESS(6'h02) + ) i_delay_cntrl ( + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked), + .up_dld (up_dld), + .up_dwdata (up_dwdata), + .up_drdata (up_drdata), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[9]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[9]), + .up_rack (up_rack_s[9])); + end + + // adc channels + + for (i = 0; i < 8; i=i+1) begin : channel + always @(posedge adc_clk_s) begin + adc_reset[i] <= adc_rst_s; + end + axi_ad4858_channel #( + .CHANNEL_ID(i), + .ACTIVE_LANE (ACTIVE_LANES) + ) i_adc_channel ( + .adc_clk (adc_clk_s), + .adc_rst (adc_reset[i]), + .adc_ch_valid_in (adc_valid_if), + .adc_ch_data_in (adc_data_if_s[32*i+:32]), + .if_crc_err (crc_error), + .adc_enable (adc_enable_s[i]), + .adc_valid (adc_valid_s[i]), + .adc_data (adc_data_s[i]), + .adc_or (adc_or[i]), + .adc_status_header (), + .packet_format (packet_format), + .oversampling_en (oversampling_en), + .up_adc_or (up_adc_or_s[i]), + .up_adc_pn_err (up_adc_pn_err[i]), + .up_adc_pn_oos (up_adc_pn_oos[i]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[i]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[i]), + .up_rack (up_rack_s[i])); + end + endgenerate + + // adc up common + + up_adc_common #( + .ID(ID), + .CONFIG(CONFIG) + ) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk_s), + .adc_rst (adc_rst_s), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status ('h1), + .adc_sync_status (1'b1), + .adc_status_ovf (adc_dovf), + .adc_clk_ratio (32'd1), + .adc_start_code (), + .adc_sref_sync (), + .adc_sync (), + .adc_ext_sync_arm (), + .adc_ext_sync_disarm (), + .adc_ext_sync_manual_req (), + .adc_custom_control (adc_custom_control), + .adc_sdr_ddr_n (), + .adc_symb_op (), + .adc_symb_8_16b (), + .adc_num_lanes (), + .adc_crc_enable (adc_crc_enable_s), + .up_pps_rcounter (32'b0), + .up_pps_status (1'b0), + .up_pps_irq_mask (), + .up_adc_ce (), + .up_status_pn_err (|up_adc_pn_err), + .up_status_pn_oos (|up_adc_pn_oos), + .up_status_or (|up_status_or), + .up_adc_r1_mode(), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .adc_config_wr (), + .adc_config_ctrl (), + .adc_config_rd ('d0), + .adc_ctrl_status ('d0), + .up_usr_chanmax_out (), + .up_usr_chanmax_in (8'd8), + .up_adc_gpio_in (32'b0), + .up_adc_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[8]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[8]), + .up_rack (up_rack_s[8])); + + // up bus interface + + up_axi #( + .AXI_ADDRESS_WIDTH (16) + ) i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ad4858/axi_ad4858.xpr b/adi_library/axi_ad4858/axi_ad4858.xpr new file mode 100644 index 00000000..794e44c7 --- /dev/null +++ b/adi_library/axi_ad4858/axi_ad4858.xpr @@ -0,0 +1,552 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_ad4858/axi_ad4858_channel.v b/adi_library/axi_ad4858/axi_ad4858_channel.v new file mode 100644 index 00000000..9904f0cd --- /dev/null +++ b/adi_library/axi_ad4858/axi_ad4858_channel.v @@ -0,0 +1,275 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad4858_channel #( + + parameter CHANNEL_ID = 0, + parameter ACTIVE_LANE = 8'b11111111, // for cmos if + parameter USERPORTS_DISABLE = 0, + parameter DATAFORMAT_DISABLE = 0 +) ( + + // adc interface + + input adc_clk, + input adc_rst, + input adc_ch_valid_in, + input [31:0] adc_ch_data_in, + input if_crc_err, + + // dma interface + + output adc_enable, + output reg adc_valid, + output reg [31:0] adc_data, + + // error monitoring + + output reg adc_or, + output reg [ 6:0] adc_status_header, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, + + // format + + input [ 1:0] packet_format, + input oversampling_en, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // internal registers + + reg adc_pn_err; + reg adc_valid_f1; + reg [23:0] adc_data_f1; + reg [31:0] pattern; + reg [31:0] adc_raw_data; + reg [31:0] read_channel_data; + reg [31:0] expected_package_pattern; + + // internal signals + + wire to_be_checked; + + wire adc_dfmt_se_s; + wire adc_dfmt_type_s; + wire adc_dfmt_enable_s; + wire adc_pn_err_s; + + wire adc_valid_f2; + wire [31:0] adc_data_f2; + wire adc_valid_f2_ovs; + wire [31:0] adc_data_f2_ovs; + + wire [31:0] expected_pattern; + wire [31:0] expected_package_pattern_s; + + // expected pattern + + assign expected_pattern = {CHANNEL_ID[3:0], 28'hace3c2a}; + assign expected_package_pattern_s = packet_format == 2'd0 ? expected_pattern >> 12: + packet_format == 2'd1 ? expected_pattern >> 8: + packet_format == 2'd2 ? expected_pattern : expected_pattern; + + // the pattern check result is masked out for unused lanes(cmos) + assign to_be_checked = ACTIVE_LANE[CHANNEL_ID[3:0]] ? 1'b1 : 1'b0; + + always @(posedge adc_clk) begin + expected_package_pattern <= expected_package_pattern_s; + if (expected_package_pattern == pattern) begin + adc_pn_err <= 1'b0; + end else begin + adc_pn_err <= to_be_checked; + end + end + + // AD4858 is a 20 bit resolution ADC, when oversampling is enabled the data + // resolutions growes to 24 + always @(posedge adc_clk) begin + adc_valid_f1 <= adc_ch_valid_in; + case ({packet_format,oversampling_en}) + 3'h0,3'h1: begin // packet format 20 - oversampling on/off + adc_raw_data <= {12'd0,adc_ch_data_in[19:0]}; + adc_data_f1 <= {4'd0, adc_ch_data_in[19:0]}; + adc_or <= 1'b0; + adc_status_header <= 7'd0; + pattern <= {12'd0, adc_ch_data_in[19:0]}; + end + 3'h2: begin // packet format 24 - oversampling off + adc_raw_data <= {12'd0,adc_ch_data_in[23:4]}; + adc_data_f1 <= {4'd0, adc_ch_data_in[23:4]}; + adc_or <= adc_ch_data_in[3]; + adc_status_header <= {adc_ch_data_in[2:0], 4'd0}; + pattern <= {8'd0, adc_ch_data_in[23:0]}; + end + 3'h3: begin // packet format 24 - oversampling on + adc_raw_data <= {8'd0,adc_ch_data_in[23:0]}; + adc_data_f1 <= adc_ch_data_in[23:0]; + adc_or <= 3'd0; + adc_status_header <= 7'd0; + pattern <= {8'd0, adc_ch_data_in[23:0]}; + end + 3'h4,3'h6: begin // packet format 32 - oversampling off + adc_raw_data <= {12'd0, adc_ch_data_in[31:12]}; + adc_data_f1 <= {4'd0, adc_ch_data_in[31:12]}; + adc_or <= adc_ch_data_in[11]; + adc_status_header <= adc_ch_data_in[10:4]; + pattern <= adc_ch_data_in; + end + 3'h5,3'h7: begin // packet format 32 - oversampling on + adc_raw_data <= {8'd0, adc_ch_data_in[31:8]}; + adc_data_f1 <= adc_ch_data_in[31:8]; + adc_or <= adc_ch_data_in[7]; + adc_status_header <= adc_ch_data_in[6:0]; + pattern <= adc_ch_data_in; + end + endcase + end + + ad_datafmt #( + .DATA_WIDTH (20), + .BITS_PER_SAMPLE (32), + .DISABLE (DATAFORMAT_DISABLE) + ) i_ad_datafmt ( + .clk (adc_clk), + .valid (adc_valid_f1), + .data (adc_data_f1[19:0]), + .valid_out (adc_valid_f2), + .data_out (adc_data_f2), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + + ad_datafmt #( + .DATA_WIDTH (24), + .BITS_PER_SAMPLE (32), + .DISABLE (DATAFORMAT_DISABLE) + ) i_ad_datafmt_oversampling ( + .clk (adc_clk), + .valid (adc_valid_f1), + .data (adc_data_f1), + .valid_out (adc_valid_f2_ovs), + .data_out (adc_data_f2_ovs), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + + always @(posedge adc_clk) begin + adc_data <= (packet_format != 'd0 && oversampling_en) ? adc_data_f2_ovs : adc_data_f2; + adc_valid <= (packet_format != 'd0 && oversampling_en) ? adc_valid_f2_ovs : adc_valid_f2; + end + + always @(posedge adc_clk) begin + if (adc_valid_f1) begin + read_channel_data <= adc_raw_data; + end else begin + read_channel_data <= read_channel_data; + end + end + + // adc channel regmap + + up_adc_channel #( + .CHANNEL_ID (CHANNEL_ID), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), + .DCFILTER_DISABLE (1'b1), + .IQCORRECTION_DISABLE (1'b1) + ) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (), + .adc_dcfilt_enb (), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_dcfilt_offset (), + .adc_dcfilt_coeff (), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pnseq_sel (), + .adc_data_sel (), + .adc_pn_err (adc_pn_err), + .adc_pn_oos (1'b0), + .adc_or (1'b0), + .adc_read_data (read_channel_data), + .adc_status_header ({1'b1, adc_status_header}), + .adc_crc_err (if_crc_err), + .up_adc_crc_err (), + .up_adc_pn_err (up_adc_pn_err), + .up_adc_pn_oos (up_adc_pn_oos), + .up_adc_or (up_adc_or), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd32), + .adc_usr_datatype_bits (8'd20), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ad4858/axi_ad4858_cmos.v b/adi_library/axi_ad4858/axi_ad4858_cmos.v new file mode 100644 index 00000000..91d01bd6 --- /dev/null +++ b/adi_library/axi_ad4858/axi_ad4858_cmos.v @@ -0,0 +1,659 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad4858_cmos #( + + parameter FPGA_TECHNOLOGY = 0, + parameter DELAY_REFCLK_FREQ = 200, + parameter IODELAY_ENABLE = 1, + parameter IODELAY_GROUP = "dev_if_delay_group", + parameter ACTIVE_LANE = 8'b11111111 +) ( + + input rst, + input clk, + input [ 7:0] adc_enable, + input adc_crc_enable, + + // physical interface + + output scki, + input scko, + input [ 7:0] db_i, + input busy, + input cnvs, + + // format + + input [ 1:0] packet_format, + input oversampling_en, + + // channel interface + + output [255:0] adc_data, + output reg adc_valid, + output reg crc_error, + output [ 7:0] dev_status, + + // delay interface (for IDELAY macros) + + input up_clk, + input [ 7:0] up_adc_dld, + input [39:0] up_adc_dwdata, + output [39:0] up_adc_drdata, + input delay_clk, + input delay_rst, + output delay_locked +); + + localparam NEG_EDGE = 1; + localparam DW = 32; + localparam BW = DW - 1; + localparam PACKET_1_BITS = 20; + localparam PACKET_2_BITS = 24; + localparam PACKET_3_BITS = 32; + + // internal registers + + reg [BW:0] adc_lane_0; + reg [BW:0] adc_lane_1; + reg [BW:0] adc_lane_2; + reg [BW:0] adc_lane_3; + reg [BW:0] adc_lane_4; + reg [BW:0] adc_lane_5; + reg [BW:0] adc_lane_6; + reg [BW:0] adc_lane_7; + + reg [ 5:0] data_counter = 6'h0; + reg [ 5:0] scki_counter = 6'h0; + + reg scki_i; + reg scki_d; + + reg [BW:0] adc_data_store[8:0]; + reg [BW:0] adc_data_init[7:0]; + reg adc_valid_init; + reg adc_valid_init_d; + + reg [ 8:0] ch_capture; + reg [ 8:0] ch_captured; + + reg [ 4:0] adc_ch0_shift; + reg [ 4:0] adc_ch1_shift; + reg [ 4:0] adc_ch2_shift; + reg [ 4:0] adc_ch3_shift; + reg [ 4:0] adc_ch4_shift; + reg [ 4:0] adc_ch5_shift; + reg [ 4:0] adc_ch6_shift; + reg [ 4:0] adc_ch7_shift; + + reg [ 4:0] adc_ch0_shift_d; + reg [ 4:0] adc_ch1_shift_d; + reg [ 4:0] adc_ch2_shift_d; + reg [ 4:0] adc_ch3_shift_d; + reg [ 4:0] adc_ch4_shift_d; + reg [ 4:0] adc_ch5_shift_d; + reg [ 4:0] adc_ch6_shift_d; + reg [ 4:0] adc_ch7_shift_d; + + reg [ 3:0] lane_0_data = 'd0; + reg [ 3:0] lane_1_data = 'd0; + reg [ 3:0] lane_2_data = 'd0; + reg [ 3:0] lane_3_data = 'd0; + reg [ 3:0] lane_4_data = 'd0; + reg [ 3:0] lane_5_data = 'd0; + reg [ 3:0] lane_6_data = 'd0; + reg [ 3:0] lane_7_data = 'd0; + reg [ 8:0] ch_data_lock = 'h1ff; + + reg busy_m1; + reg busy_m2; + reg cnvs_d; + reg [31:0] period_cnt; + + reg conversion_quiet_time; + reg run_busy_period_cnt; + reg [31:0] busy_conversion_cnt; + reg [31:0] busy_measure_value; + reg start_transfer; + + reg crc_enable_window; + reg run_crc; + reg run_crc_d; + reg [288:0] crc_data_in; + reg [15:0] crc_cnt; + reg [ 7:0] data_in_byte; + + // internal wires + + wire [ 7:0] db_s; + + wire [31:0] status_and_crc_data; + + wire aquire_data; + wire scki_cnt_rst; + wire adc_cnvs_redge; + wire conversion_completed; + wire conversion_quiet_time_s; + + wire [ 5:0] packet_lenght; + + wire crc_reset; + wire crc_enable; + wire crc_valid; + wire [15:0] crc_res; + wire [15:0] crc_data_lenght; + + // packet format selection + + assign packet_lenght = packet_format == 2'd0 ? 6'd20 : + packet_format == 2'd1 ? 6'd24 : 6'd32; + + always @(posedge clk) begin + if (rst == 1'b1) begin + busy_m1 <= 1'b0; + busy_m2 <= 1'b0; + start_transfer <= 1'b0; + end else begin + busy_m1 <= busy; + busy_m2 <= busy_m1; + start_transfer <= busy_m2 & !busy_m1; + end + end + + always @(posedge clk) begin + if (start_transfer) begin + crc_enable_window <= adc_crc_enable; + end + end + + always @(posedge clk) begin + if (rst) begin + scki_counter <= 5'h0; + scki_i <= 1'b1; + scki_d <= 1'b0; + end else begin + scki_d <= scki_i; + if (aquire_data == 1'b0) begin + scki_counter <= 5'h0; + scki_i <= 1'b1; + end else if (scki_cnt_rst & (scki_d & ~scki_i)) begin // end of a capture + scki_counter <= 5'h1; + scki_i <= 1'b1; + end else if (scki_i == 1'b0) begin + scki_counter <= scki_counter + 1; + scki_i <= 1'b1; + end else if (conversion_quiet_time_s == 1'b1) begin + scki_counter <= scki_counter; + scki_i <= scki_i; + end else begin + scki_counter <= scki_counter; + scki_i <= ~scki_i; + end + end + end + + // busy period counter + always @(posedge clk) begin + if (rst == 1'b1) begin + run_busy_period_cnt <= 1'b0; + busy_conversion_cnt <= 'd0; + busy_measure_value <= 'd0; + end else begin + if (cnvs == 1'b1 && busy_m2 == 1'b1) begin + run_busy_period_cnt <= 1'b1; + end else if (start_transfer == 1'b1) begin + run_busy_period_cnt <= 1'b0; + end + + if (adc_cnvs_redge == 1'b1) begin + busy_conversion_cnt <= 'd0; + end else if (start_transfer == 1'b1) begin + busy_measure_value <= busy_conversion_cnt; + end else if (run_busy_period_cnt == 1'b1) begin + busy_conversion_cnt <= busy_conversion_cnt + 'd1; + end + end + end + + always @(posedge clk) begin + if (rst) begin + period_cnt <= 'd0; + cnvs_d <= 'd0; + conversion_quiet_time <= 1'b0; + end else begin + cnvs_d <= cnvs; + if (oversampling_en == 1 && adc_cnvs_redge == 1'b1) begin + conversion_quiet_time <= 1'b1; + end else begin + conversion_quiet_time <= conversion_quiet_time & ~conversion_completed; + end + if (adc_cnvs_redge == 1'b1) begin + period_cnt <= 'd0; + end else begin + period_cnt <= period_cnt + 1; + end + end + end + + assign conversion_quiet_time_s = (oversampling_en == 1) ? conversion_quiet_time | cnvs : 1'b0; + assign conversion_completed = (period_cnt == busy_measure_value) ? 1'b1 : 1'b0; + assign adc_cnvs_redge = ~cnvs_d & cnvs; + assign scki_cnt_rst = (scki_counter == packet_lenght) ? 1'b1 : 1'b0; + assign scki = scki_i | ~aquire_data; + + /* + The device sends each channel data on one of the 8 lines. + Data is stored in the device in a ring buffer. After the first packet is read + and no new conversion is activated if the reading process restarted, + the new data on the lines will be from the next index from the ring buffer. + e.g For second read process without a conversion start + line 0 = channel 1, line 1 = channel 2, line 2 = channel 3; so on and so forth. + */ + + always @(posedge clk) begin + if (start_transfer) begin + lane_0_data <= 4'd0; + lane_1_data <= 4'd1; + lane_2_data <= 4'd2; + lane_3_data <= 4'd3; + lane_4_data <= 4'd4; + lane_5_data <= 4'd5; + lane_6_data <= 4'd6; + lane_7_data <= 4'd7; + ch_data_lock <= 9'd0; + end else if (aquire_data == 1'b1 && (scki_cnt_rst & (~scki_d & scki_i))) begin + lane_0_data <= lane_0_data[3] == 1'b1 ? 4'd0 : lane_0_data + 1; + lane_1_data <= lane_1_data[3] == 1'b1 ? 4'd0 : lane_1_data + 1; + lane_2_data <= lane_2_data[3] == 1'b1 ? 4'd0 : lane_2_data + 1; + lane_3_data <= lane_3_data[3] == 1'b1 ? 4'd0 : lane_3_data + 1; + lane_4_data <= lane_4_data[3] == 1'b1 ? 4'd0 : lane_4_data + 1; + lane_5_data <= lane_5_data[3] == 1'b1 ? 4'd0 : lane_5_data + 1; + lane_6_data <= lane_6_data[3] == 1'b1 ? 4'd0 : lane_6_data + 1; + lane_7_data <= lane_7_data[3] == 1'b1 ? 4'd0 : lane_7_data + 1; + ch_data_lock[lane_0_data[3:0]] <= ACTIVE_LANE[0] ? 1'b1 : ch_data_lock[lane_0_data[2:0]]; + ch_data_lock[lane_1_data[3:0]] <= ACTIVE_LANE[1] ? 1'b1 : ch_data_lock[lane_1_data[2:0]]; + ch_data_lock[lane_2_data[3:0]] <= ACTIVE_LANE[2] ? 1'b1 : ch_data_lock[lane_2_data[2:0]]; + ch_data_lock[lane_3_data[3:0]] <= ACTIVE_LANE[3] ? 1'b1 : ch_data_lock[lane_3_data[2:0]]; + ch_data_lock[lane_4_data[3:0]] <= ACTIVE_LANE[4] ? 1'b1 : ch_data_lock[lane_4_data[2:0]]; + ch_data_lock[lane_5_data[3:0]] <= ACTIVE_LANE[5] ? 1'b1 : ch_data_lock[lane_5_data[2:0]]; + ch_data_lock[lane_6_data[3:0]] <= ACTIVE_LANE[6] ? 1'b1 : ch_data_lock[lane_6_data[2:0]]; + ch_data_lock[lane_7_data[3:0]] <= ACTIVE_LANE[7] ? 1'b1 : ch_data_lock[lane_7_data[2:0]]; + end else begin + lane_0_data <= lane_0_data; + lane_1_data <= lane_1_data; + lane_2_data <= lane_2_data; + lane_3_data <= lane_3_data; + lane_4_data <= lane_4_data; + lane_5_data <= lane_5_data; + lane_6_data <= lane_6_data; + lane_7_data <= lane_7_data; + ch_data_lock <= ch_data_lock; + end + end + + assign aquire_data = ~((ch_data_lock[0] | ~adc_enable[0]) & + (ch_data_lock[1] | ~adc_enable[1]) & + (ch_data_lock[2] | ~adc_enable[2]) & + (ch_data_lock[3] | ~adc_enable[3]) & + (ch_data_lock[4] | ~adc_enable[4]) & + (ch_data_lock[5] | ~adc_enable[5]) & + (ch_data_lock[6] | ~adc_enable[6]) & + (ch_data_lock[7] | ~adc_enable[7]) & + (ch_data_lock[8] | ~crc_enable_window)); + + // capture data + + genvar i; + generate + if (IODELAY_ENABLE == 1) begin + ad_data_in #( + .SINGLE_ENDED (1), + .DDR_SDR_N (0), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_CTRL (1), + .IODELAY_ENABLE (IODELAY_ENABLE), + .IODELAY_GROUP (IODELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQ) + ) i_rx_data ( + .rx_clk (scko), + .rx_data_in_p (db_i[0]), + .rx_data_in_n (1'd0), + .rx_data_p (db_s[0]), + .rx_data_n (), + .up_clk (up_clk), + .up_dld (up_adc_dld[0]), + .up_dwdata (up_adc_dwdata[4:0]), + .up_drdata (up_adc_drdata[4:0]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked)); + end + for (i = 1; i < 8; i = i + 1) begin: g_rx_lanes + ad_data_in #( + .SINGLE_ENDED (1), + .DDR_SDR_N (0), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_CTRL (0), + .IODELAY_ENABLE (IODELAY_ENABLE), + .IODELAY_GROUP (IODELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQ) + ) i_rx_data ( + .rx_clk (scko), + .rx_data_in_p (db_i[i]), + .rx_data_in_n (1'd0), + .rx_data_p (db_s[i]), + .rx_data_n (), + .up_clk (up_clk), + .up_dld (up_adc_dld[i]), + .up_dwdata (up_adc_dwdata[((i*5)+4):(i*5)]), + .up_drdata (up_adc_drdata[((i*5)+4):(i*5)]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + endgenerate + + // the most significant bits of the adc_lane_x will remaind from the + // previous sample for packet formats other than 32. + + always @(negedge scko) begin + adc_lane_0 <= {adc_lane_0[BW-1:0], db_s[0]}; + adc_lane_1 <= {adc_lane_1[BW-1:0], db_s[1]}; + adc_lane_2 <= {adc_lane_2[BW-1:0], db_s[2]}; + adc_lane_3 <= {adc_lane_3[BW-1:0], db_s[3]}; + adc_lane_4 <= {adc_lane_4[BW-1:0], db_s[4]}; + adc_lane_5 <= {adc_lane_5[BW-1:0], db_s[5]}; + adc_lane_6 <= {adc_lane_6[BW-1:0], db_s[6]}; + adc_lane_7 <= {adc_lane_7[BW-1:0], db_s[7]}; + end + + always @(posedge clk) begin + if (rst == 1'b1) begin + adc_valid_init <= 1'b0; + end else begin + if (data_counter == packet_lenght && adc_valid_init == 1'b0) begin + adc_valid_init <= 1'b1; + end else begin + adc_valid_init <= 1'b0; + end + end + end + + always @(posedge clk) begin + if (rst == 1'b1) begin + adc_data_init[0] <= 'h0; + adc_data_init[1] <= 'h0; + adc_data_init[2] <= 'h0; + adc_data_init[3] <= 'h0; + adc_data_init[4] <= 'h0; + adc_data_init[5] <= 'h0; + adc_data_init[6] <= 'h0; + adc_data_init[7] <= 'h0; + data_counter <= 'h0; + end else begin + data_counter <= scki_counter; + if (data_counter == packet_lenght) begin + adc_data_init[0] <= adc_lane_0; + adc_data_init[1] <= adc_lane_1; + adc_data_init[2] <= adc_lane_2; + adc_data_init[3] <= adc_lane_3; + adc_data_init[4] <= adc_lane_4; + adc_data_init[5] <= adc_lane_5; + adc_data_init[6] <= adc_lane_6; + adc_data_init[7] <= adc_lane_7; + end else begin + adc_data_init[0] <= adc_data_init[0]; + adc_data_init[1] <= adc_data_init[1]; + adc_data_init[2] <= adc_data_init[2]; + adc_data_init[3] <= adc_data_init[3]; + adc_data_init[4] <= adc_data_init[4]; + adc_data_init[5] <= adc_data_init[5]; + adc_data_init[6] <= adc_data_init[6]; + adc_data_init[7] <= adc_data_init[7]; + end + end + end + + always @(posedge clk) begin + if (rst == 1'b1 || adc_valid == 1'b1) begin + adc_valid <= 1'b0; + adc_valid_init_d <= 1'b0; + ch_capture <= 9'd0; + ch_captured <= 9'd0; + + adc_ch0_shift <= 4'd0; + adc_ch1_shift <= 4'd0; + adc_ch2_shift <= 4'd0; + adc_ch3_shift <= 4'd0; + adc_ch4_shift <= 4'd0; + adc_ch5_shift <= 4'd0; + adc_ch6_shift <= 4'd0; + adc_ch7_shift <= 4'd0; + adc_ch0_shift_d <= 4'd0; + adc_ch1_shift_d <= 4'd0; + adc_ch2_shift_d <= 4'd0; + adc_ch3_shift_d <= 4'd0; + adc_ch4_shift_d <= 4'd0; + adc_ch5_shift_d <= 4'd0; + adc_ch6_shift_d <= 4'd0; + adc_ch7_shift_d <= 4'd0; + end else begin + ch_capture <= ch_data_lock; + ch_captured <= ch_capture; + adc_valid_init_d <= adc_valid_init; + + adc_ch0_shift <= {ACTIVE_LANE[0],lane_0_data}; + adc_ch1_shift <= {ACTIVE_LANE[1],lane_1_data}; + adc_ch2_shift <= {ACTIVE_LANE[2],lane_2_data}; + adc_ch3_shift <= {ACTIVE_LANE[3],lane_3_data}; + adc_ch4_shift <= {ACTIVE_LANE[4],lane_4_data}; + adc_ch5_shift <= {ACTIVE_LANE[5],lane_5_data}; + adc_ch6_shift <= {ACTIVE_LANE[6],lane_6_data}; + adc_ch7_shift <= {ACTIVE_LANE[7],lane_7_data}; + adc_ch0_shift_d <= adc_ch0_shift; + adc_ch1_shift_d <= adc_ch1_shift; + adc_ch2_shift_d <= adc_ch2_shift; + adc_ch3_shift_d <= adc_ch3_shift; + adc_ch4_shift_d <= adc_ch4_shift; + adc_ch5_shift_d <= adc_ch5_shift; + adc_ch6_shift_d <= adc_ch6_shift; + adc_ch7_shift_d <= adc_ch7_shift; + adc_valid <= adc_valid_init_d & + (ch_captured[0] | ~adc_enable[0]) & + (ch_captured[1] | ~adc_enable[1]) & + (ch_captured[2] | ~adc_enable[2]) & + (ch_captured[3] | ~adc_enable[3]) & + (ch_captured[4] | ~adc_enable[4]) & + (ch_captured[5] | ~adc_enable[5]) & + (ch_captured[6] | ~adc_enable[6]) & + (ch_captured[7] | ~adc_enable[7]) & + (ch_captured[8] | ~crc_enable_window); + end + end + + always @(posedge clk) begin + if (rst == 1'b1) begin + adc_data_store[0] <= 'd0; + adc_data_store[1] <= 'd0; + adc_data_store[2] <= 'd0; + adc_data_store[3] <= 'd0; + adc_data_store[4] <= 'd0; + adc_data_store[5] <= 'd0; + adc_data_store[6] <= 'd0; + adc_data_store[7] <= 'd0; + adc_data_store[8] <= 'd0; + end else begin + if (!adc_valid_init_d & adc_valid_init) begin + if (adc_ch0_shift_d[4] == 1'b1) begin + adc_data_store[adc_ch0_shift_d[3:0]] <= adc_data_init[0]; + end + if (adc_ch1_shift_d[4] == 1'b1) begin + adc_data_store[adc_ch1_shift_d[3:0]] <= adc_data_init[1]; + end + if (adc_ch2_shift_d[4] == 1'b1) begin + adc_data_store[adc_ch2_shift_d[3:0]] <= adc_data_init[2]; + end + if (adc_ch3_shift_d[4] == 1'b1) begin + adc_data_store[adc_ch3_shift_d[3:0]] <= adc_data_init[3]; + end + if (adc_ch4_shift_d[4] == 1'b1) begin + adc_data_store[adc_ch4_shift_d[3:0]] <= adc_data_init[4]; + end + if (adc_ch5_shift_d[4] == 1'b1) begin + adc_data_store[adc_ch5_shift_d[3:0]] <= adc_data_init[5]; + end + if (adc_ch6_shift_d[4] == 1'b1) begin + adc_data_store[adc_ch6_shift_d[3:0]] <= adc_data_init[6]; + end + if (adc_ch7_shift_d[4] == 1'b1) begin + adc_data_store[adc_ch7_shift_d[3:0]] <= adc_data_init[7]; + end + end + end + end + + assign dev_status = packet_format == 0 ? adc_data_store[8][23:16] << 4 : + adc_data_store[8][23:16]; + assign crc_data = adc_data_store[8][15:0]; + assign adc_data = {adc_data_store[7], + adc_data_store[6], + adc_data_store[5], + adc_data_store[4], + adc_data_store[3], + adc_data_store[2], + adc_data_store[1], + adc_data_store[0]}; + + // CRC checker logic + + always @(posedge clk) begin + if (rst == 1) begin + crc_data_in <= 0; + end else begin + if (adc_valid == 1) begin + if (packet_format == 0) begin + crc_data_in <= {104'd0, + adc_data_store[0][19:0], + adc_data_store[1][19:0], + adc_data_store[2][19:0], + adc_data_store[3][19:0], + adc_data_store[4][19:0], + adc_data_store[5][19:0], + adc_data_store[6][19:0], + adc_data_store[7][19:0], + adc_data_store[8][19:0], + 4'd0}; + end else if (packet_format == 1) begin + crc_data_in <= {72'd0, + adc_data_store[0][23:0], + adc_data_store[1][23:0], + adc_data_store[2][23:0], + adc_data_store[3][23:0], + adc_data_store[4][23:0], + adc_data_store[5][23:0], + adc_data_store[6][23:0], + adc_data_store[7][23:0], + adc_data_store[8][23:0]}; + end else begin + crc_data_in <= {adc_data_store[0], + adc_data_store[1], + adc_data_store[2], + adc_data_store[3], + adc_data_store[4], + adc_data_store[5], + adc_data_store[6], + adc_data_store[7], + adc_data_store[8]}; + end + end + end + end + + // As an optimization, a crc checker with 8 parallel operations per clk cycle + // will be used for all packet formats. + // The channel plus status and crc data will be feed in byte packets to the + // crc checker. + // When packet_format is 20 bits, 20x8+20(st and crc) = 180 which is not a + // multiple of 8. So, we will feed 184 bits, which is a multiple of 8. + // First extra 4 bits entering the checker being 0, will not affect the result + // since the initial value of the LFSR is 0x0000. + assign crc_data_lenght = packet_format == 2'd0 ? 16'd176 : // 184-8 + packet_format == 2'd1 ? 16'd208 : 16'd280; + + always @(posedge clk) begin + if (crc_enable_window == 0 || adc_valid == 1) begin + crc_cnt <= crc_data_lenght; + data_in_byte <= 0; + run_crc <= adc_valid; + end else begin + if (run_crc == 1'b1) begin + if (crc_cnt == 0) begin + run_crc <= 1'b0; + end else begin + crc_cnt <= crc_cnt - 8; + end + data_in_byte <= crc_data_in[crc_cnt +: 8]; + end else begin + end + end + // the counter is initialized with n-1 to accommodate the byte shifter + run_crc_d <= run_crc; + end + + assign crc_reset = adc_valid; + assign crc_enable = run_crc | run_crc_d; + + always @(posedge clk) begin + if (crc_valid == 1) begin + if (crc_res == 16'd0) begin + crc_error <= 1'd0; + end else begin + crc_error <= 1'd1; + end + end + end + + axi_ad4858_crc i_ad4858_crc_8 ( + .rst (crc_reset), + .clk (clk), + .crc_en (crc_enable), + .d_in (data_in_byte), + .crc_valid (crc_valid), + .crc_res (crc_res)); + +endmodule diff --git a/adi_library/axi_ad4858/axi_ad4858_constr.ttcl b/adi_library/axi_ad4858/axi_ad4858_constr.ttcl new file mode 100644 index 00000000..5219dc7c --- /dev/null +++ b/adi_library/axi_ad4858/axi_ad4858_constr.ttcl @@ -0,0 +1,29 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName [ttcl_add $ComponentName "_constr"] :> +<: setFileExtension ".xdc" :> +<: setFileProcessingOrder late :> +<: set lvds_cmos_n [getBooleanValue "LVDS_CMOS_N"] :> + +set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]] + +<: if {$lvds_cmos_n} { :> + +set_false_path -quiet \ + -from $up_clk \ + -to [get_cells -quiet -hier -filter {name =~ *packet_format_reg* && IS_SEQUENTIAL}] + +set_false_path -quiet \ + -from $up_clk \ + -to [get_cells -quiet -hier -filter {name =~ *ch_*_base_reg* && IS_SEQUENTIAL}] + +set_false_path -quiet \ + -from [get_cells -hier -filter {name =~ *packet_format_reg* && IS_SEQUENTIAL}] \ + -to [get_cells -quiet -hieri -filter {name =~ *packet_cnt_length_reg* && IS_SEQUENTIAL}] + +<: } :> diff --git a/adi_library/axi_ad4858/axi_ad4858_crc.v b/adi_library/axi_ad4858/axi_ad4858_crc.v new file mode 100644 index 00000000..4628a776 --- /dev/null +++ b/adi_library/axi_ad4858/axi_ad4858_crc.v @@ -0,0 +1,83 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +// CRC polynomial 0x755B = x^16 + x^14 + x^13 + x^12 + x^10 + x^8 + x^6 + x^4 + x^3 + x + 1 +// CRC width: 16 bits +// Input word width: 8 bits +// Initial value: 0x0000 +// Direction: shift left + +module axi_ad4858_crc ( + input rst, + input clk, + input crc_en, + input [ 7:0] d_in, + output crc_valid, + output [15:0] crc_res +); + + reg [15:0] lfsr; + reg [15:0] crc_en_d; + + always @(posedge clk) begin + if (rst == 1'b1) begin + lfsr <= 16'd0; + crc_en_d <= 1'b0; + end else begin + crc_en_d <= crc_en; + if (crc_en == 1'b1) begin + lfsr[0] <= lfsr[8] ^ lfsr[10] ^ lfsr[11] ^ lfsr[14] ^ lfsr[15] ^ d_in[0] ^ d_in[2] ^ d_in[3] ^ d_in[6] ^ d_in[7]; + lfsr[1] <= lfsr[8] ^ lfsr[9] ^ lfsr[10] ^ lfsr[12] ^ lfsr[14] ^ d_in[0] ^ d_in[1] ^ d_in[2] ^ d_in[4] ^ d_in[6]; + lfsr[2] <= lfsr[9] ^ lfsr[10] ^ lfsr[11] ^ lfsr[13] ^ lfsr[15] ^ d_in[1] ^ d_in[2] ^ d_in[3] ^ d_in[5] ^ d_in[7]; + lfsr[3] <= lfsr[8] ^ lfsr[12] ^ lfsr[15] ^ d_in[0] ^ d_in[4] ^ d_in[7]; + lfsr[4] <= lfsr[8] ^ lfsr[9] ^ lfsr[10] ^ lfsr[11] ^ lfsr[13] ^ lfsr[14] ^ lfsr[15] ^ d_in[0] ^ d_in[1] ^ d_in[2] ^ d_in[3] ^ d_in[5] ^ d_in[6] ^ d_in[7]; + lfsr[5] <= lfsr[9] ^ lfsr[10] ^ lfsr[11] ^ lfsr[12] ^ lfsr[14] ^ lfsr[15] ^ d_in[1] ^ d_in[2] ^ d_in[3] ^ d_in[4] ^ d_in[6] ^ d_in[7]; + lfsr[6] <= lfsr[8] ^ lfsr[12] ^ lfsr[13] ^ lfsr[14] ^ d_in[0] ^ d_in[4] ^ d_in[5] ^ d_in[6]; + lfsr[7] <= lfsr[9] ^ lfsr[13] ^ lfsr[14] ^ lfsr[15] ^ d_in[1] ^ d_in[5] ^ d_in[6] ^ d_in[7]; + lfsr[8] <= lfsr[0] ^ lfsr[8] ^ lfsr[11] ^ d_in[0] ^ d_in[3]; + lfsr[9] <= lfsr[1] ^ lfsr[9] ^ lfsr[12] ^ d_in[1] ^ d_in[4]; + lfsr[10] <= lfsr[2] ^ lfsr[8] ^ lfsr[11] ^ lfsr[13] ^ lfsr[14] ^ lfsr[15] ^ d_in[0] ^ d_in[3] ^ d_in[5] ^ d_in[6] ^ d_in[7]; + lfsr[11] <= lfsr[3] ^ lfsr[9] ^ lfsr[12] ^ lfsr[14] ^ lfsr[15] ^ d_in[1] ^ d_in[4] ^ d_in[6] ^ d_in[7]; + lfsr[12] <= lfsr[4] ^ lfsr[8] ^ lfsr[11] ^ lfsr[13] ^ lfsr[14] ^ d_in[0] ^ d_in[3] ^ d_in[5] ^ d_in[6]; + lfsr[13] <= lfsr[5] ^ lfsr[8] ^ lfsr[9] ^ lfsr[10] ^ lfsr[11] ^ lfsr[12] ^ d_in[0] ^ d_in[1] ^ d_in[2] ^ d_in[3] ^ d_in[4]; + lfsr[14] <= lfsr[6] ^ lfsr[8] ^ lfsr[9] ^ lfsr[12] ^ lfsr[13] ^ lfsr[14] ^ lfsr[15] ^ d_in[0] ^ d_in[1] ^ d_in[4] ^ d_in[5] ^ d_in[6] ^ d_in[7]; + lfsr[15] <= lfsr[7] ^ lfsr[9] ^ lfsr[10] ^ lfsr[13] ^ lfsr[14] ^ lfsr[15] ^ d_in[1] ^ d_in[2] ^ d_in[5] ^ d_in[6] ^ d_in[7]; + end + end + end + + assign crc_res = lfsr; + assign crc_valid = !crc_en & crc_en_d; +endmodule diff --git a/adi_library/axi_ad4858/axi_ad4858_ip.tcl b/adi_library/axi_ad4858/axi_ad4858_ip.tcl new file mode 100644 index 00000000..e011067e --- /dev/null +++ b/adi_library/axi_ad4858/axi_ad4858_ip.tcl @@ -0,0 +1,139 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip + +source ../../scripts/adi_env.tcl + +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create axi_ad4858 +adi_ip_files axi_ad4858 [list \ + "$ad_hdl_dir/library/common/ad_edge_detect.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_serdes_out.v" \ + "$ad_hdl_dir/library/util_cdc/sync_bits.v" \ + "axi_ad4858_constr.ttcl" \ + "axi_ad4858_cmos.v" \ + "axi_ad4858_channel.v" \ + "axi_ad4858_crc.v" \ + "axi_ad4858_lvds.v" \ + "axi_ad4858.v" ] + +adi_ip_properties axi_ad4858 + +set cc [ipx::current_core] + +## Customize XGUI layout + +set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] + +adi_init_bd_tcl +adi_ip_bd axi_ad4858 "bd/bd.tcl" + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad4858} [ipx::current_core] + +ipgui::add_param -name "EXTERNAL_CLK" -component $cc -parent $page0 +set_property -dict [list \ + "display_name" "EXTERNAL_CLK_EN" \ + "tooltip" "External clock for interface logic, must be 2x faster than IF clk" \ + "widget" "checkBox" \ +] [ipgui::get_guiparamspec -name "EXTERNAL_CLK" -component $cc] + +ipgui::add_param -name "ECHO_CLK_EN" -component $cc -parent $page0 +set_property -dict [list \ + "display_name" "Echoed clock enabled" \ + "widget" "checkBox" \ +] [ipgui::get_guiparamspec -name "ECHO_CLK_EN" -component $cc] + +ipgui::add_param -name "LVDS_CMOS_N" -component $cc -parent $page0 +set_property -dict [list \ + "value_validation_type" "pairs" \ + "value_validation_pairs" { \ + "CMOS" "0" \ + "LVDS" "1" \ + } \ +] [ipx::get_user_parameters "LVDS_CMOS_N" -of_objects $cc] + +set_property -dict [list \ + "display_name" "Interface type" \ + "widget" "comboBox" \ +] [ipx::get_user_parameters "LVDS_CMOS_N" -of_objects $cc] + +for {set i 0} {$i < 8} {incr i} { + ipgui::add_param -name "LANE_${i}_ENABLE" -component $cc -parent $page0 + set_property -dict [list \ + "display_name" "LANE_${i}_ENABLE" \ + "tooltip" "Lane $i is used" \ + "widget" "checkBox" \ + ] [ipgui::get_guiparamspec -name "LANE_${i}_ENABLE" -component $cc] + + set_property value true [ipx::get_user_parameters LANE_${i}_ENABLE -of_objects [ipx::current_core]] + set_property value true [ipx::get_hdl_parameters LANE_${i}_ENABLE -of_objects [ipx::current_core]] + set_property enablement_tcl_expr {expr $LVDS_CMOS_N == 0} [ipx::get_user_parameters LANE_${i}_ENABLE -of_objects [ipx::current_core]] + set_property value_format bool [ipx::get_user_parameters LANE_${i}_ENABLE -of_objects [ipx::current_core]] + set_property value_format bool [ipx::get_hdl_parameters LANE_${i}_ENABLE -of_objects [ipx::current_core]] + + adi_set_ports_dependency "lane_$i" \ + "(spirit:decode(id('MODELPARAM_VALUE.LANE_${i}_ENABLE')) == 1)" + + adi_set_ports_dependency "lane_$i" \ + "(spirit:decode(id('MODELPARAM_VALUE.LVDS_CMOS_N')) == 0)" + + set_property DRIVER_VALUE "0" [ipx::get_ports lane_$i] +} + +# CMOS dependency +adi_set_ports_dependency "scki" \ + "(spirit:decode(id('MODELPARAM_VALUE.LVDS_CMOS_N')) == 0)" +adi_set_ports_dependency "scko" \ + "(spirit:decode(id('MODELPARAM_VALUE.LVDS_CMOS_N')) == 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.ECHO_CLK_EN')) = 1)" + +# LVDS dependency +adi_set_ports_dependency "scki_p" \ + "(spirit:decode(id('MODELPARAM_VALUE.LVDS_CMOS_N')) == 1)" +adi_set_ports_dependency "scki_n" \ + "(spirit:decode(id('MODELPARAM_VALUE.LVDS_CMOS_N')) == 1)" + +adi_set_ports_dependency "scko_p" \ + "(spirit:decode(id('MODELPARAM_VALUE.LVDS_CMOS_N')) == 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.ECHO_CLK_EN')) = 1)" +adi_set_ports_dependency "scko_n" \ + "(spirit:decode(id('MODELPARAM_VALUE.LVDS_CMOS_N')) == 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.ECHO_CLK_EN')) = 1)" + +adi_set_ports_dependency "sdo_p" \ + "(spirit:decode(id('MODELPARAM_VALUE.LVDS_CMOS_N')) == 1)" +adi_set_ports_dependency "sdo_n" \ + "(spirit:decode(id('MODELPARAM_VALUE.LVDS_CMOS_N')) == 1)" + +adi_set_ports_dependency "external_clk" \ + "(spirit:decode(id('MODELPARAM_VALUE.EXTERNAL_CLK')) = 1)" 0 + +set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects $cc] + +adi_add_auto_fpga_spec_params + +## Save the modifications + +ipx::create_xgui_files $cc + +ipx::save_core [ipx::current_core] diff --git a/adi_library/axi_ad4858/axi_ad4858_lvds.v b/adi_library/axi_ad4858/axi_ad4858_lvds.v new file mode 100644 index 00000000..de8668ac --- /dev/null +++ b/adi_library/axi_ad4858/axi_ad4858_lvds.v @@ -0,0 +1,540 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad4858_lvds #( + + parameter FPGA_TECHNOLOGY = 0, + parameter DELAY_REFCLK_FREQ = 200, + parameter IODELAY_ENABLE = 1, + parameter NEG_EDGE = 1 +) ( + + input rst, + input clk, + input fast_clk, + input [ 7:0] adc_enable, + input adc_crc_enable, + + // physical interface + + output scki_p, + output scki_n, + input scko_p, + input scko_n, + input sdo_p, + input sdo_n, + input busy, + input cnvs, + + // format + + input [ 1:0] packet_format_in, + input oversampling_en, + + // channel interface + + output reg [255:0] adc_data, + output reg adc_valid, + output reg crc_error, + output reg [ 7:0] dev_status, + + // delay interface (for IDELAY macros) + + input up_clk, + input up_adc_dld, + input [ 4:0] up_adc_dwdata, + output [ 4:0] up_adc_drdata, + input delay_clk, + input delay_rst, + output delay_locked +); + + localparam DW = 32; + localparam BW = DW - 1; + + // internal registers + + reg [ 1:0] packet_format; + reg [ 5:0] packet_cnt_length; + reg [ 15:0] crc_data_length; + + reg [143:0] rx_data_pos; + reg [143:0] rx_data_neg; + + reg [ 5:0] data_counter = 'h0; + reg [ 3:0] ch_counter = 'h0; + + reg busy_m1; + reg busy_m2; + reg cnvs_d; + reg [ 31:0] period_cnt; + + reg conversion_quiet_time; + reg run_busy_period_cnt; + reg [ 31:0] busy_conversion_cnt; + reg [ 31:0] busy_measure_value; + reg [ 31:0] busy_measure_value_plus; + + reg [287:0] adc_data_store; + reg [287:0] adc_data_init; + reg aquire_data; + reg capture_complete_init; + reg capture_complete_d; + reg start_transfer; + reg start_transfer_d; + + reg [ 15:0] dynamic_delay; + reg adc_valid_init; + reg adc_valid_init_d; + reg adc_valid_init_d2; + + reg [255:0] adc_data_0; + reg [255:0] adc_data_1; + reg [255:0] adc_data_2; + reg crc_enable_window; + reg run_crc; + reg run_crc_d; + reg [287:0] crc_data_in; + reg [287:0] crc_data_in_sh; + reg [ 15:0] crc_cnt; + reg [ 7:0] data_in_byte; + + reg [ 3:0] ch_7_index; + reg [ 3:0] ch_6_index; + reg [ 3:0] ch_5_index; + reg [ 3:0] ch_4_index; + reg [ 3:0] ch_3_index; + reg [ 3:0] ch_2_index; + reg [ 3:0] ch_1_index; + reg [ 3:0] ch_0_index; + reg [ 8:0] ch_7_base; + reg [ 8:0] ch_6_base; + reg [ 8:0] ch_5_base; + reg [ 8:0] ch_4_base; + reg [ 8:0] ch_3_base; + reg [ 8:0] ch_2_base; + reg [ 8:0] ch_1_base; + reg [ 8:0] ch_0_base; + reg [ 3:0] max_channel_transfer; + reg [ 31:0] device_status_store; + + // internal wires + + wire scko; + wire scko_s; + wire sdo; + wire conversion_completed; + wire conversion_quiet_time_s; + + wire capture_complete_s; + wire capture_complete; + + wire crc_reset; + wire crc_enable; + wire crc_valid; + wire [ 15:0] crc_res; + wire sdo_p_s; + wire sdo_n_s; + wire [ 8:0] ch_index_20_pack [8:0]; + wire [ 8:0] ch_index_24_pack [8:0]; + wire [ 8:0] ch_index_32_pack [8:0]; + + wire [143:0] rx_data_pos_s; + wire [143:0] rx_data_neg_s; + + // assgments + + genvar j; + generate + for (j = 0; j <= 8; j = j + 1) begin + assign ch_index_20_pack [j] = j * 20; + assign ch_index_24_pack [j] = j * 24; + assign ch_index_32_pack [j] = j * 32; + end + endgenerate + + always @(posedge clk) begin + busy_m1 <= busy; + busy_m2 <= busy_m1; + start_transfer <= busy_m2 & !busy_m1; + start_transfer_d <= start_transfer; + end + + always @(posedge clk) begin + packet_format <= packet_format_in; + if (start_transfer) begin + packet_cnt_length <= packet_format == 2'd0 ? 6'd20 - 6'd4 : + packet_format == 2'd1 ? 6'd24 - 6'd4 : 6'd32 - 6'd4; + max_channel_transfer <= adc_crc_enable ? 8 : 7; + crc_enable_window <= adc_crc_enable; + end + end + + // busy period counter + always @(posedge clk) begin + if (cnvs == 1'b1 && busy_m2 == 1'b1) begin + run_busy_period_cnt <= 1'b1; + end else if (start_transfer == 1'b1) begin + run_busy_period_cnt <= 1'b0; + end + end + + always @(posedge clk) begin + if (adc_cnvs_redge == 1'b1) begin + busy_conversion_cnt <= - 'd1; //adj for + 1 clk cycle measurement error + end else if (run_busy_period_cnt == 1'b1) begin + busy_conversion_cnt <= busy_conversion_cnt + 'd1; + end + end + + always @(posedge clk) begin + if (start_transfer == 1'b1) begin + busy_measure_value <= busy_conversion_cnt; + end + end + + always @(posedge clk) begin + cnvs_d <= cnvs; + if (oversampling_en == 1 && adc_cnvs_redge == 1'b1) begin + conversion_quiet_time <= 1'b1; + end else begin + conversion_quiet_time <= conversion_quiet_time & ~conversion_completed; + end + if (adc_cnvs_redge == 1'b1) begin + period_cnt <= 'd0; + end else begin + period_cnt <= period_cnt + 1; + end + end + + assign conversion_quiet_time_s = (oversampling_en == 1) ? conversion_quiet_time & !conversion_completed | cnvs : 1'b0; + assign conversion_completed = (period_cnt == busy_measure_value) ? 1'b1 : 1'b0; + assign adc_cnvs_redge = ~cnvs_d & cnvs; + + always @(posedge clk) begin + if (aquire_data == 1'b0 || data_counter == packet_cnt_length) begin + data_counter <= 2'h0; + end else begin + data_counter <= data_counter + 4; + end + + if (start_transfer == 1'b1) begin + ch_counter <= 4'h0; + end else begin + if (data_counter == packet_cnt_length) begin + if (ch_counter == max_channel_transfer) begin + ch_counter <= 4'h0; + end else begin + ch_counter <= ch_counter + 1; + end + end else begin + ch_counter <= ch_counter; + end + end + + if (data_counter == packet_cnt_length && ch_counter == max_channel_transfer) begin + aquire_data <= 1'b0; + capture_complete_init <= 1'b1; + end else if (aquire_data | start_transfer) begin + aquire_data <= ~conversion_quiet_time_s; + capture_complete_init <= 1'b0; + end + capture_complete_d <= capture_complete_init; + end + + assign capture_complete_s = ~capture_complete_d & capture_complete_init; + + // valid delay (0 to 15) + always @(posedge clk) begin + dynamic_delay <= {dynamic_delay[14:0], capture_complete_s}; + end + + assign capture_complete = dynamic_delay[4'd10]; + + IBUFDS i_scko_bufds ( + .O(scko_s), + .I(scko_p), + .IB(scko_n)); + + // It is added to constraint the tool to keep the logic in the same region + // as the input pins, otherwise the tool will automatically add a bufg and + // meeting the timing margins is harder. + BUFH BUFH_inst ( + .O(scko), + .I(scko_s) + ); + + // receive + + ad_data_in #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQ), + .IODELAY_CTRL (1), + .IODELAY_ENABLE (IODELAY_ENABLE), + .IDDR_CLK_EDGE ("OPPOSITE_EDGE") + ) i_rx ( + .rx_clk (scko), + .rx_data_in_p (sdo_p), + .rx_data_in_n (sdo_n), + .rx_data_p (sdo_p_s), + .rx_data_n (sdo_n_s), + .up_clk (up_clk), + .up_dld (up_adc_dld), + .up_dwdata (up_adc_dwdata[4:0]), + .up_drdata (up_adc_drdata[4:0]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked)); + + always @(posedge scko) begin + rx_data_pos <= {rx_data_pos[142:0], sdo_p_s}; + end + always @(negedge scko) begin + rx_data_neg <= {rx_data_neg[142:0], sdo_n_s}; + end + + assign rx_data_pos_s = {rx_data_pos[142:0], sdo_p_s}; + assign rx_data_neg_s = {rx_data_neg[142:0], sdo_n_s}; + + genvar i; + generate + for (i = 0; i <= 288 - 2; i = i + 2) begin + always @(posedge clk) begin + if (capture_complete) begin + adc_data_init[i+:2] <= {rx_data_pos_s[i>>1], rx_data_neg_s[i>>1]}; + end + end + end + endgenerate + + always @(posedge clk) begin + adc_valid_init <= capture_complete; + adc_valid_init_d <= adc_valid_init; + adc_valid_init_d2 <= adc_valid_init_d; + adc_valid <= adc_valid_init_d2; + adc_data_store <= adc_data_init; // relax timing + end + + always @(posedge clk) begin + if (start_transfer_d) begin + ch_7_index <= crc_enable_window ? 1 : 0; + ch_6_index <= crc_enable_window ? 2 : 1; + ch_5_index <= crc_enable_window ? 3 : 2; + ch_4_index <= crc_enable_window ? 4 : 3; + ch_3_index <= crc_enable_window ? 5 : 4; + ch_2_index <= crc_enable_window ? 6 : 5; + ch_1_index <= crc_enable_window ? 7 : 6; + ch_0_index <= crc_enable_window ? 8 : 7; + end + + ch_7_base <= packet_format == 0 ? ch_index_20_pack[ch_7_index] : + packet_format == 1 ? ch_index_24_pack[ch_7_index] : ch_index_32_pack[ch_7_index]; + ch_6_base <= packet_format == 0 ? ch_index_20_pack[ch_6_index] : + packet_format == 1 ? ch_index_24_pack[ch_6_index] : ch_index_32_pack[ch_6_index]; + ch_5_base <= packet_format == 0 ? ch_index_20_pack[ch_5_index] : + packet_format == 1 ? ch_index_24_pack[ch_5_index] : ch_index_32_pack[ch_5_index]; + ch_4_base <= packet_format == 0 ? ch_index_20_pack[ch_4_index] : + packet_format == 1 ? ch_index_24_pack[ch_4_index] : ch_index_32_pack[ch_4_index]; + ch_3_base <= packet_format == 0 ? ch_index_20_pack[ch_3_index] : + packet_format == 1 ? ch_index_24_pack[ch_3_index] : ch_index_32_pack[ch_3_index]; + ch_2_base <= packet_format == 0 ? ch_index_20_pack[ch_2_index] : + packet_format == 1 ? ch_index_24_pack[ch_2_index] : ch_index_32_pack[ch_2_index]; + ch_1_base <= packet_format == 0 ? ch_index_20_pack[ch_1_index] : + packet_format == 1 ? ch_index_24_pack[ch_1_index] : ch_index_32_pack[ch_1_index]; + ch_0_base <= packet_format == 0 ? ch_index_20_pack[ch_0_index] : + packet_format == 1 ? ch_index_24_pack[ch_0_index] : ch_index_32_pack[ch_0_index]; + end + + always @(posedge clk) begin + adc_data_0 <={12'b0,adc_data_store[ch_7_base+:20], + 12'b0,adc_data_store[ch_6_base+:20], + 12'b0,adc_data_store[ch_5_base+:20], + 12'b0,adc_data_store[ch_4_base+:20], + 12'b0,adc_data_store[ch_3_base+:20], + 12'b0,adc_data_store[ch_2_base+:20], + 12'b0,adc_data_store[ch_1_base+:20], + 12'b0,adc_data_store[ch_0_base+:20]}; + adc_data_1 <={8'b0,adc_data_store[ch_7_base+:24], + 8'b0,adc_data_store[ch_6_base+:24], + 8'b0,adc_data_store[ch_5_base+:24], + 8'b0,adc_data_store[ch_4_base+:24], + 8'b0,adc_data_store[ch_3_base+:24], + 8'b0,adc_data_store[ch_2_base+:24], + 8'b0,adc_data_store[ch_1_base+:24], + 8'b0,adc_data_store[ch_0_base+:24]}; + adc_data_2 <={adc_data_store[ch_7_base+:32], + adc_data_store[ch_6_base+:32], + adc_data_store[ch_5_base+:32], + adc_data_store[ch_4_base+:32], + adc_data_store[ch_3_base+:32], + adc_data_store[ch_2_base+:32], + adc_data_store[ch_1_base+:32], + adc_data_store[ch_0_base+:32]}; + end + + always @(posedge clk) begin + if (crc_enable_window == 1'b1) begin + device_status_store <= adc_data_store[31:0]; + end else begin + device_status_store <= 0; + end + end + + always @(posedge clk) begin + case (packet_format) + 2'h0: begin + adc_data <= adc_data_0; + dev_status <= device_status_store[19:0]; + end + 2'h1: begin + adc_data <= adc_data_1; + dev_status <= device_status_store[23:0]; + end + 2'h2: begin + adc_data <= adc_data_2; + dev_status <= device_status_store[31:0]; + end + 2'h3: begin + adc_data <= adc_data_2; + dev_status <= device_status_store[31:0]; + end + endcase + end + + // CRC checker logic + + always @(posedge clk) begin + if (adc_valid_init_d == 1) begin + if (packet_format == 0) begin + crc_data_in <= {adc_data_store[179:0], 108'd0}; + end else if (packet_format == 1) begin + crc_data_in <= {adc_data_store[215:0], 72'd0}; + end else begin + crc_data_in <= {adc_data_store}; + end + end + end + + // As an optimization, a crc checker with 8 parallel operations per clk cycle + // will be used for all packet formats. + // The channel plus status and crc data will be feed in byte packets to the + // crc checker. + // When packet_format is 20 bits, 20x8+20(st and crc) = 180 which is not a + // multiple of 8. So, we will feed 184 bits, which is a multiple of 8. + // Last extra 4 bits entering the checker being 0, will not affect the result + always @(posedge clk) begin + crc_data_length <= packet_format == 2'd0 ? 16'd176 : // 184-8 + packet_format == 2'd1 ? 16'd208 : 16'd280; + end + + always @(posedge clk) begin + if (adc_valid_init_d2 == 1'b1) begin + crc_cnt <= crc_data_length; + run_crc <= (crc_enable_window == 1) ? 1'b1 : 1'b0; + end else begin + if (run_crc == 1'b1) begin + if (crc_cnt == 0) begin + run_crc <= 1'b0; + end else begin + crc_cnt <= crc_cnt - 8; + end + end + end + // the counter is initialized with n-1 to accommodate the byte shifter + run_crc_d <= run_crc; + end + + always @(posedge clk) begin + if (adc_valid_init_d2 == 1'b1) begin + crc_data_in_sh <= crc_data_in; + end else if (run_crc == 1'b1) begin + crc_data_in_sh <= crc_data_in_sh << 8; + end + end + + always @(posedge clk) begin + if (run_crc == 1'b1) begin + data_in_byte <= crc_data_in_sh[287:280]; + end else begin + data_in_byte <= 8'd0; + end + end + + assign crc_reset = adc_valid_init_d2; + assign crc_enable = run_crc_d | run_crc; + + always @(posedge clk) begin + if (crc_valid == 1) begin + if (crc_res == 16'd0) begin + crc_error <= 1'd0; + end else begin + crc_error <= 1'd1; + end + end + end + + axi_ad4858_crc i_ad4858_crc_8 ( + .rst (crc_reset), + .clk (clk), + .crc_en (crc_enable), + .d_in (data_in_byte), + .crc_valid (crc_valid), + .crc_res (crc_res)); + + ad_serdes_out #( + .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), + .DDR_OR_SDR_N(1'b1), + .DATA_WIDTH(1), + .SERDES_FACTOR(4) + ) i_scki_out ( + .rst(rst), + .clk(fast_clk), + .div_clk(clk), + .data_oe(1'b1), + .data_s0(1'b0), + .data_s1(aquire_data), + .data_s2(1'b0), + .data_s3(aquire_data), + .data_s4(), + .data_s5(), + .data_s6(), + .data_s7(), + .data_out_se (), + .data_out_p(scki_p), + .data_out_n(scki_n)); + +endmodule diff --git a/adi_library/axi_ad4858/bd/bd.tcl b/adi_library/axi_ad4858/bd/bd.tcl new file mode 100644 index 00000000..ba898b2b --- /dev/null +++ b/adi_library/axi_ad4858/bd/bd.tcl @@ -0,0 +1,44 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/axi_ad4858/component.xml b/adi_library/axi_ad4858/component.xml new file mode 100644 index 00000000..d1dd0548 --- /dev/null +++ b/adi_library/axi_ad4858/component.xml @@ -0,0 +1,1865 @@ + + + analog.com + user + axi_ad4858 + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_ad4858 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + bc5d0f91 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_ad4858 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + bae8e501 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 16549e88 + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + + + delay_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + external_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + external_fast_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + cnvs + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + busy + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + lvds_cmos_n + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + scki + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + scko + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + lane_0 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + lane_1 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + lane_2 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + lane_3 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + lane_4 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + lane_5 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + lane_6 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + lane_7 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + scki_p + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + scki_n + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + scko_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + scko_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + sdo_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + sdo_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_dovf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_2 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_3 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_4 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_5 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_6 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_7 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_0 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_1 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_2 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_3 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_4 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_5 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_6 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_7 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + DELAY_REFCLK_FREQ + Delay Refclk Freq + 200 + + + IODELAY_ENABLE + Iodelay Enable + 1 + + + ID + Id + 0 + + + LVDS_CMOS_N + Lvds Cmos N + 1 + + + LANE_0_ENABLE + Lane 0 Enable + true + + + + false + + + + + + LANE_1_ENABLE + Lane 1 Enable + true + + + + false + + + + + + LANE_2_ENABLE + Lane 2 Enable + true + + + + false + + + + + + LANE_3_ENABLE + Lane 3 Enable + true + + + + false + + + + + + LANE_4_ENABLE + Lane 4 Enable + true + + + + false + + + + + + LANE_5_ENABLE + Lane 5 Enable + true + + + + false + + + + + + LANE_6_ENABLE + Lane 6 Enable + true + + + + false + + + + + + LANE_7_ENABLE + Lane 7 Enable + true + + + + false + + + + + + ECHO_CLK_EN + Echo Clk En + 1 + + + EXTERNAL_CLK + External Clk + 1 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_28f798a2 + 0 + 1 + 2 + 3 + 4 + + + choice_pairs_4191e6fe + 0 + 1 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../xilinx/common/up_clock_mon_constr.xdc + xdc + + + ../xilinx/common/ad_data_in.v + verilogSource + + + ../common/ad_datafmt.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../xilinx/common/ad_serdes_out.v + verilogSource + + + axi_ad4858_channel.v + verilogSource + + + axi_ad4858_cmos.v + verilogSource + + + axi_ad4858_crc.v + verilogSource + + + axi_ad4858_lvds.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_delay_cntrl.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad4858.v + verilogSource + CHECKSUM_ec735744 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../xilinx/common/ad_data_in.v + verilogSource + + + ../common/ad_datafmt.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../xilinx/common/ad_serdes_out.v + verilogSource + + + axi_ad4858_channel.v + verilogSource + + + axi_ad4858_cmos.v + verilogSource + + + axi_ad4858_crc.v + verilogSource + + + axi_ad4858_lvds.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_delay_cntrl.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad4858.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_ad4858_v1_0.tcl + tclSource + CHECKSUM_5a71ad18 + XGUI_VERSION_2 + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + xilinx_utilityxitfiles_view_fileset + + gui/axi_ad4858_v1_0.gtcl + GTCL + + + + axi_ad4858_v1_0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + DELAY_REFCLK_FREQ + Delay Refclk Freq + 200 + + + IODELAY_ENABLE + Iodelay Enable + 1 + + + ID + Id + 0 + + + LVDS_CMOS_N + Interface type + 1 + + + LANE_0_ENABLE + LANE_0_ENABLE + true + + + + false + + + + + + LANE_1_ENABLE + LANE_1_ENABLE + true + + + + false + + + + + + LANE_2_ENABLE + LANE_2_ENABLE + true + + + + false + + + + + + LANE_3_ENABLE + LANE_3_ENABLE + true + + + + false + + + + + + LANE_4_ENABLE + LANE_4_ENABLE + true + + + + false + + + + + + LANE_5_ENABLE + LANE_5_ENABLE + true + + + + false + + + + + + LANE_6_ENABLE + LANE_6_ENABLE + true + + + + false + + + + + + LANE_7_ENABLE + LANE_7_ENABLE + true + + + + false + + + + + + ECHO_CLK_EN + Echoed clock enabled + 1 + + + EXTERNAL_CLK + EXTERNAL_CLK_EN + 1 + + + Component_Name + axi_ad4858_v1_0 + + + + + + virtex7 + + + /Analog_Devices + + axi_ad4858_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_ad4858 + 1 + 2024-01-14T03:38:12Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_ad4858/gui/axi_ad4858_v1_0.gtcl b/adi_library/axi_ad4858/gui/axi_ad4858_v1_0.gtcl new file mode 100644 index 00000000..ec3f1722 --- /dev/null +++ b/adi_library/axi_ad4858/gui/axi_ad4858_v1_0.gtcl @@ -0,0 +1,9 @@ +# This file is automatically written. Do not modify. +proc gen_USERPARAMETER_LANE_0_ENABLE_ENABLEMENT {LVDS_CMOS_N } {expr $LVDS_CMOS_N == 0} +proc gen_USERPARAMETER_LANE_1_ENABLE_ENABLEMENT {LVDS_CMOS_N } {expr $LVDS_CMOS_N == 0} +proc gen_USERPARAMETER_LANE_2_ENABLE_ENABLEMENT {LVDS_CMOS_N } {expr $LVDS_CMOS_N == 0} +proc gen_USERPARAMETER_LANE_3_ENABLE_ENABLEMENT {LVDS_CMOS_N } {expr $LVDS_CMOS_N == 0} +proc gen_USERPARAMETER_LANE_4_ENABLE_ENABLEMENT {LVDS_CMOS_N } {expr $LVDS_CMOS_N == 0} +proc gen_USERPARAMETER_LANE_5_ENABLE_ENABLEMENT {LVDS_CMOS_N } {expr $LVDS_CMOS_N == 0} +proc gen_USERPARAMETER_LANE_6_ENABLE_ENABLEMENT {LVDS_CMOS_N } {expr $LVDS_CMOS_N == 0} +proc gen_USERPARAMETER_LANE_7_ENABLE_ENABLEMENT {LVDS_CMOS_N } {expr $LVDS_CMOS_N == 0} diff --git a/adi_library/axi_ad4858/temporary_case_dependencies.mk b/adi_library/axi_ad4858/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/axi_ad4858/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/axi_ad4858/xgui/axi_ad4858_v1_0.tcl b/adi_library/axi_ad4858/xgui/axi_ad4858_v1_0.tcl new file mode 100644 index 00000000..9986d0a2 --- /dev/null +++ b/adi_library/axi_ad4858/xgui/axi_ad4858_v1_0.tcl @@ -0,0 +1,323 @@ + +# Loading additional proc with user specified bodies to compute parameter values. +source [file join [file dirname [file dirname [info script]]] gui/axi_ad4858_v1_0.gtcl] + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DELAY_REFCLK_FREQ" -parent ${Page_0} + ipgui::add_param $IPINST -name "ECHO_CLK_EN" -parent ${Page_0} -widget checkBox + set EXTERNAL_CLK [ipgui::add_param $IPINST -name "EXTERNAL_CLK" -parent ${Page_0} -widget checkBox] + set_property tooltip {External clock for interface logic, must be 2x faster than IF clk} ${EXTERNAL_CLK} + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "IODELAY_ENABLE" -parent ${Page_0} + set LANE_0_ENABLE [ipgui::add_param $IPINST -name "LANE_0_ENABLE" -parent ${Page_0}] + set_property tooltip {Lane 0 is used} ${LANE_0_ENABLE} + set LANE_1_ENABLE [ipgui::add_param $IPINST -name "LANE_1_ENABLE" -parent ${Page_0}] + set_property tooltip {Lane 1 is used} ${LANE_1_ENABLE} + set LANE_2_ENABLE [ipgui::add_param $IPINST -name "LANE_2_ENABLE" -parent ${Page_0}] + set_property tooltip {Lane 2 is used} ${LANE_2_ENABLE} + set LANE_3_ENABLE [ipgui::add_param $IPINST -name "LANE_3_ENABLE" -parent ${Page_0}] + set_property tooltip {Lane 3 is used} ${LANE_3_ENABLE} + set LANE_4_ENABLE [ipgui::add_param $IPINST -name "LANE_4_ENABLE" -parent ${Page_0}] + set_property tooltip {Lane 4 is used} ${LANE_4_ENABLE} + set LANE_5_ENABLE [ipgui::add_param $IPINST -name "LANE_5_ENABLE" -parent ${Page_0}] + set_property tooltip {Lane 5 is used} ${LANE_5_ENABLE} + set LANE_6_ENABLE [ipgui::add_param $IPINST -name "LANE_6_ENABLE" -parent ${Page_0}] + set_property tooltip {Lane 6 is used} ${LANE_6_ENABLE} + set LANE_7_ENABLE [ipgui::add_param $IPINST -name "LANE_7_ENABLE" -parent ${Page_0}] + set_property tooltip {Lane 7 is used} ${LANE_7_ENABLE} + ipgui::add_param $IPINST -name "LVDS_CMOS_N" -parent ${Page_0} + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.LANE_0_ENABLE { PARAM_VALUE.LANE_0_ENABLE PARAM_VALUE.LVDS_CMOS_N } { + # Procedure called to update LANE_0_ENABLE when any of the dependent parameters in the arguments change + + set LANE_0_ENABLE ${PARAM_VALUE.LANE_0_ENABLE} + set LVDS_CMOS_N ${PARAM_VALUE.LVDS_CMOS_N} + set values(LVDS_CMOS_N) [get_property value $LVDS_CMOS_N] + if { [gen_USERPARAMETER_LANE_0_ENABLE_ENABLEMENT $values(LVDS_CMOS_N)] } { + set_property enabled true $LANE_0_ENABLE + } else { + set_property enabled false $LANE_0_ENABLE + } +} + +proc validate_PARAM_VALUE.LANE_0_ENABLE { PARAM_VALUE.LANE_0_ENABLE } { + # Procedure called to validate LANE_0_ENABLE + return true +} + +proc update_PARAM_VALUE.LANE_1_ENABLE { PARAM_VALUE.LANE_1_ENABLE PARAM_VALUE.LVDS_CMOS_N } { + # Procedure called to update LANE_1_ENABLE when any of the dependent parameters in the arguments change + + set LANE_1_ENABLE ${PARAM_VALUE.LANE_1_ENABLE} + set LVDS_CMOS_N ${PARAM_VALUE.LVDS_CMOS_N} + set values(LVDS_CMOS_N) [get_property value $LVDS_CMOS_N] + if { [gen_USERPARAMETER_LANE_1_ENABLE_ENABLEMENT $values(LVDS_CMOS_N)] } { + set_property enabled true $LANE_1_ENABLE + } else { + set_property enabled false $LANE_1_ENABLE + } +} + +proc validate_PARAM_VALUE.LANE_1_ENABLE { PARAM_VALUE.LANE_1_ENABLE } { + # Procedure called to validate LANE_1_ENABLE + return true +} + +proc update_PARAM_VALUE.LANE_2_ENABLE { PARAM_VALUE.LANE_2_ENABLE PARAM_VALUE.LVDS_CMOS_N } { + # Procedure called to update LANE_2_ENABLE when any of the dependent parameters in the arguments change + + set LANE_2_ENABLE ${PARAM_VALUE.LANE_2_ENABLE} + set LVDS_CMOS_N ${PARAM_VALUE.LVDS_CMOS_N} + set values(LVDS_CMOS_N) [get_property value $LVDS_CMOS_N] + if { [gen_USERPARAMETER_LANE_2_ENABLE_ENABLEMENT $values(LVDS_CMOS_N)] } { + set_property enabled true $LANE_2_ENABLE + } else { + set_property enabled false $LANE_2_ENABLE + } +} + +proc validate_PARAM_VALUE.LANE_2_ENABLE { PARAM_VALUE.LANE_2_ENABLE } { + # Procedure called to validate LANE_2_ENABLE + return true +} + +proc update_PARAM_VALUE.LANE_3_ENABLE { PARAM_VALUE.LANE_3_ENABLE PARAM_VALUE.LVDS_CMOS_N } { + # Procedure called to update LANE_3_ENABLE when any of the dependent parameters in the arguments change + + set LANE_3_ENABLE ${PARAM_VALUE.LANE_3_ENABLE} + set LVDS_CMOS_N ${PARAM_VALUE.LVDS_CMOS_N} + set values(LVDS_CMOS_N) [get_property value $LVDS_CMOS_N] + if { [gen_USERPARAMETER_LANE_3_ENABLE_ENABLEMENT $values(LVDS_CMOS_N)] } { + set_property enabled true $LANE_3_ENABLE + } else { + set_property enabled false $LANE_3_ENABLE + } +} + +proc validate_PARAM_VALUE.LANE_3_ENABLE { PARAM_VALUE.LANE_3_ENABLE } { + # Procedure called to validate LANE_3_ENABLE + return true +} + +proc update_PARAM_VALUE.LANE_4_ENABLE { PARAM_VALUE.LANE_4_ENABLE PARAM_VALUE.LVDS_CMOS_N } { + # Procedure called to update LANE_4_ENABLE when any of the dependent parameters in the arguments change + + set LANE_4_ENABLE ${PARAM_VALUE.LANE_4_ENABLE} + set LVDS_CMOS_N ${PARAM_VALUE.LVDS_CMOS_N} + set values(LVDS_CMOS_N) [get_property value $LVDS_CMOS_N] + if { [gen_USERPARAMETER_LANE_4_ENABLE_ENABLEMENT $values(LVDS_CMOS_N)] } { + set_property enabled true $LANE_4_ENABLE + } else { + set_property enabled false $LANE_4_ENABLE + } +} + +proc validate_PARAM_VALUE.LANE_4_ENABLE { PARAM_VALUE.LANE_4_ENABLE } { + # Procedure called to validate LANE_4_ENABLE + return true +} + +proc update_PARAM_VALUE.LANE_5_ENABLE { PARAM_VALUE.LANE_5_ENABLE PARAM_VALUE.LVDS_CMOS_N } { + # Procedure called to update LANE_5_ENABLE when any of the dependent parameters in the arguments change + + set LANE_5_ENABLE ${PARAM_VALUE.LANE_5_ENABLE} + set LVDS_CMOS_N ${PARAM_VALUE.LVDS_CMOS_N} + set values(LVDS_CMOS_N) [get_property value $LVDS_CMOS_N] + if { [gen_USERPARAMETER_LANE_5_ENABLE_ENABLEMENT $values(LVDS_CMOS_N)] } { + set_property enabled true $LANE_5_ENABLE + } else { + set_property enabled false $LANE_5_ENABLE + } +} + +proc validate_PARAM_VALUE.LANE_5_ENABLE { PARAM_VALUE.LANE_5_ENABLE } { + # Procedure called to validate LANE_5_ENABLE + return true +} + +proc update_PARAM_VALUE.LANE_6_ENABLE { PARAM_VALUE.LANE_6_ENABLE PARAM_VALUE.LVDS_CMOS_N } { + # Procedure called to update LANE_6_ENABLE when any of the dependent parameters in the arguments change + + set LANE_6_ENABLE ${PARAM_VALUE.LANE_6_ENABLE} + set LVDS_CMOS_N ${PARAM_VALUE.LVDS_CMOS_N} + set values(LVDS_CMOS_N) [get_property value $LVDS_CMOS_N] + if { [gen_USERPARAMETER_LANE_6_ENABLE_ENABLEMENT $values(LVDS_CMOS_N)] } { + set_property enabled true $LANE_6_ENABLE + } else { + set_property enabled false $LANE_6_ENABLE + } +} + +proc validate_PARAM_VALUE.LANE_6_ENABLE { PARAM_VALUE.LANE_6_ENABLE } { + # Procedure called to validate LANE_6_ENABLE + return true +} + +proc update_PARAM_VALUE.LANE_7_ENABLE { PARAM_VALUE.LANE_7_ENABLE PARAM_VALUE.LVDS_CMOS_N } { + # Procedure called to update LANE_7_ENABLE when any of the dependent parameters in the arguments change + + set LANE_7_ENABLE ${PARAM_VALUE.LANE_7_ENABLE} + set LVDS_CMOS_N ${PARAM_VALUE.LVDS_CMOS_N} + set values(LVDS_CMOS_N) [get_property value $LVDS_CMOS_N] + if { [gen_USERPARAMETER_LANE_7_ENABLE_ENABLEMENT $values(LVDS_CMOS_N)] } { + set_property enabled true $LANE_7_ENABLE + } else { + set_property enabled false $LANE_7_ENABLE + } +} + +proc validate_PARAM_VALUE.LANE_7_ENABLE { PARAM_VALUE.LANE_7_ENABLE } { + # Procedure called to validate LANE_7_ENABLE + return true +} + +proc update_PARAM_VALUE.DELAY_REFCLK_FREQ { PARAM_VALUE.DELAY_REFCLK_FREQ } { + # Procedure called to update DELAY_REFCLK_FREQ when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DELAY_REFCLK_FREQ { PARAM_VALUE.DELAY_REFCLK_FREQ } { + # Procedure called to validate DELAY_REFCLK_FREQ + return true +} + +proc update_PARAM_VALUE.ECHO_CLK_EN { PARAM_VALUE.ECHO_CLK_EN } { + # Procedure called to update ECHO_CLK_EN when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ECHO_CLK_EN { PARAM_VALUE.ECHO_CLK_EN } { + # Procedure called to validate ECHO_CLK_EN + return true +} + +proc update_PARAM_VALUE.EXTERNAL_CLK { PARAM_VALUE.EXTERNAL_CLK } { + # Procedure called to update EXTERNAL_CLK when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.EXTERNAL_CLK { PARAM_VALUE.EXTERNAL_CLK } { + # Procedure called to validate EXTERNAL_CLK + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.IODELAY_ENABLE { PARAM_VALUE.IODELAY_ENABLE } { + # Procedure called to update IODELAY_ENABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IODELAY_ENABLE { PARAM_VALUE.IODELAY_ENABLE } { + # Procedure called to validate IODELAY_ENABLE + return true +} + +proc update_PARAM_VALUE.LVDS_CMOS_N { PARAM_VALUE.LVDS_CMOS_N } { + # Procedure called to update LVDS_CMOS_N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.LVDS_CMOS_N { PARAM_VALUE.LVDS_CMOS_N } { + # Procedure called to validate LVDS_CMOS_N + return true +} + + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.DELAY_REFCLK_FREQ { MODELPARAM_VALUE.DELAY_REFCLK_FREQ PARAM_VALUE.DELAY_REFCLK_FREQ } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DELAY_REFCLK_FREQ}] ${MODELPARAM_VALUE.DELAY_REFCLK_FREQ} +} + +proc update_MODELPARAM_VALUE.IODELAY_ENABLE { MODELPARAM_VALUE.IODELAY_ENABLE PARAM_VALUE.IODELAY_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IODELAY_ENABLE}] ${MODELPARAM_VALUE.IODELAY_ENABLE} +} + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.LVDS_CMOS_N { MODELPARAM_VALUE.LVDS_CMOS_N PARAM_VALUE.LVDS_CMOS_N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LVDS_CMOS_N}] ${MODELPARAM_VALUE.LVDS_CMOS_N} +} + +proc update_MODELPARAM_VALUE.LANE_0_ENABLE { MODELPARAM_VALUE.LANE_0_ENABLE PARAM_VALUE.LANE_0_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LANE_0_ENABLE}] ${MODELPARAM_VALUE.LANE_0_ENABLE} +} + +proc update_MODELPARAM_VALUE.LANE_1_ENABLE { MODELPARAM_VALUE.LANE_1_ENABLE PARAM_VALUE.LANE_1_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LANE_1_ENABLE}] ${MODELPARAM_VALUE.LANE_1_ENABLE} +} + +proc update_MODELPARAM_VALUE.LANE_2_ENABLE { MODELPARAM_VALUE.LANE_2_ENABLE PARAM_VALUE.LANE_2_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LANE_2_ENABLE}] ${MODELPARAM_VALUE.LANE_2_ENABLE} +} + +proc update_MODELPARAM_VALUE.LANE_3_ENABLE { MODELPARAM_VALUE.LANE_3_ENABLE PARAM_VALUE.LANE_3_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LANE_3_ENABLE}] ${MODELPARAM_VALUE.LANE_3_ENABLE} +} + +proc update_MODELPARAM_VALUE.LANE_4_ENABLE { MODELPARAM_VALUE.LANE_4_ENABLE PARAM_VALUE.LANE_4_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LANE_4_ENABLE}] ${MODELPARAM_VALUE.LANE_4_ENABLE} +} + +proc update_MODELPARAM_VALUE.LANE_5_ENABLE { MODELPARAM_VALUE.LANE_5_ENABLE PARAM_VALUE.LANE_5_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LANE_5_ENABLE}] ${MODELPARAM_VALUE.LANE_5_ENABLE} +} + +proc update_MODELPARAM_VALUE.LANE_6_ENABLE { MODELPARAM_VALUE.LANE_6_ENABLE PARAM_VALUE.LANE_6_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LANE_6_ENABLE}] ${MODELPARAM_VALUE.LANE_6_ENABLE} +} + +proc update_MODELPARAM_VALUE.LANE_7_ENABLE { MODELPARAM_VALUE.LANE_7_ENABLE PARAM_VALUE.LANE_7_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LANE_7_ENABLE}] ${MODELPARAM_VALUE.LANE_7_ENABLE} +} + +proc update_MODELPARAM_VALUE.ECHO_CLK_EN { MODELPARAM_VALUE.ECHO_CLK_EN PARAM_VALUE.ECHO_CLK_EN } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ECHO_CLK_EN}] ${MODELPARAM_VALUE.ECHO_CLK_EN} +} + +proc update_MODELPARAM_VALUE.EXTERNAL_CLK { MODELPARAM_VALUE.EXTERNAL_CLK PARAM_VALUE.EXTERNAL_CLK } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.EXTERNAL_CLK}] ${MODELPARAM_VALUE.EXTERNAL_CLK} +} + diff --git a/adi_library/axi_ad5766/Makefile b/adi_library/axi_ad5766/Makefile new file mode 100644 index 00000000..e8003a62 --- /dev/null +++ b/adi_library/axi_ad5766/Makefile @@ -0,0 +1,28 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_ad5766 + +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_dac_common.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += ../common/util_pulse_gen.v +GENERIC_DEPS += axi_ad5766.v +GENERIC_DEPS += up_ad5766_sequencer.v + +XILINX_DEPS += axi_ad5766_ip.tcl + +XILINX_DEPS += ../spi_engine/interfaces/spi_engine_ctrl.xml +XILINX_DEPS += ../spi_engine/interfaces/spi_engine_ctrl_rtl.xml +XILINX_DEPS += ../spi_engine/interfaces/spi_engine_offload_ctrl.xml +XILINX_DEPS += ../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml + +XILINX_LIB_DEPS += util_cdc + +include ../scripts/library.mk diff --git a/adi_library/axi_ad5766/axi_ad5766.v b/adi_library/axi_ad5766/axi_ad5766.v new file mode 100644 index 00000000..172eabee --- /dev/null +++ b/adi_library/axi_ad5766/axi_ad5766.v @@ -0,0 +1,437 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad5766 #( + + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter ASYNC_SPI_CLK = 0, + parameter CMD_MEM_ADDRESS_WIDTH = 4, + parameter SDO_MEM_ADDRESS_WIDTH = 4 +) ( + + // Slave AXI interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + output s_axi_awready, + input [ 2:0] s_axi_awprot, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + output s_axi_arready, + input [ 2:0] s_axi_arprot, + output s_axi_rvalid, + input s_axi_rready, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + + // FIFO transmit + + output dma_clk, + output reg dma_valid, + input dma_enable, + input [15:0] dma_data, + input dma_xfer_req, + input dma_underflow, + + // SPI engine control interface (to the SPI engine interconnect) + + input spi_clk, // should be connected to up_clk + input spi_resetn, + + input cmd_ready, + output cmd_valid, + output [15:0] cmd_data, + + input sdo_data_ready, + output sdo_data_valid, + output [ 7:0] sdo_data, + + output sdi_data_ready, + input sdi_data_valid, + input [ 7:0] sdi_data, + + output sync_ready, + input sync_valid, + input [ 7:0] sync_data, + + // SPI engine offload interface (to the AXI SPI engine) + + input ctrl_clk, + input ctrl_cmd_wr_en, + input [15:0] ctrl_cmd_wr_data, + + input ctrl_enable, + output ctrl_enabled, + input ctrl_mem_reset +); + + // internal wires + + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire up_rreq_s; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_s[0:1]; + wire up_rack_s[0:1]; + wire up_wack_s[0:1]; + wire trigger_s; + wire [31:0] pulse_period_s; + wire [15:0] dac_datarate_s; + wire spi_reset; + wire spi_enable_s; + wire [ 3:0] sequencer[15:0]; + wire [ 3:0] cmd_bits; + wire [ 3:0] end_of_sequence; + wire spi_mem_reset_s; + wire sequence_valid_s; + wire [ 7:0] sequence_data_s; + wire dac_rst_s; + wire dac_rstn_s; + wire [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr_next; + + // registers + + reg [31:0] up_rdata = 32'b0; + reg up_rack = 0; + reg up_wack = 1'b0; + reg [15:0] cmd_mem[0:2**CMD_MEM_ADDRESS_WIDTH-1]; + reg [ 7:0] sdo_mem[0:2]; + reg [CMD_MEM_ADDRESS_WIDTH-1:0] ctrl_cmd_wr_addr = 'b0; + reg [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr = 'b0; + reg [SDO_MEM_ADDRESS_WIDTH-1:0] ctrl_sdo_wr_addr = 'b0; + reg [SDO_MEM_ADDRESS_WIDTH-1:0] spi_sdo_rd_addr = 'b0; + reg spi_active = 1'b0; + + assign up_rstn = s_axi_aresetn; + + // the dma interface runs on SPI_CLK + + assign dma_clk = spi_clk; + + // command and SDO data offload + + assign cmd_valid = spi_active; + assign cmd_data = cmd_mem[spi_cmd_rd_addr]; + assign sdo_data_valid = spi_active; + assign sdo_data = sdo_mem[spi_sdo_rd_addr]; + assign sync_ready = 1'b1; + + assign sdi_data_ready = 1'b0; + + generate if (ASYNC_SPI_CLK) begin + + /* + * The synchronization circuit takes care that there are no glitches on the + * ctrl_enabled signal. ctrl_do_enable is asserted whenever ctrl_enable is + * asserted, but only deasserted once the signal has been synchronized back from + * the SPI domain. This makes sure that we can't end up in a state where the + * enable signal in the SPI domain is asserted, but neither enable nor enabled + * is asserted in the control domain. + */ + + reg ctrl_do_enable = 1'b0; + wire ctrl_is_enabled; + reg spi_enabled = 1'b0; + + always @(posedge ctrl_clk) begin + if (ctrl_enable == 1'b1) begin + ctrl_do_enable <= 1'b1; + end else if (ctrl_is_enabled == 1'b1) begin + ctrl_do_enable <= 1'b0; + end + end + + assign ctrl_enabled = ctrl_is_enabled | ctrl_do_enable; + + always @(posedge spi_clk) begin + spi_enabled <= spi_enable_s | spi_active; + end + + sync_bits #( + .NUM_OF_BITS(1), + .ASYNC_CLK(1) + ) i_sync_enable ( + .in_bits(ctrl_do_enable), + .out_clk(spi_clk), + .out_resetn(1'b1), + .out_bits(spi_enable_s)); + + sync_bits #( + .NUM_OF_BITS(1), + .ASYNC_CLK(1) + ) i_sync_enabled ( + .in_bits(spi_enabled), + .out_clk(ctrl_clk), + .out_resetn(1'b1), + .out_bits(ctrl_is_enabled)); + + sync_bits #( + .NUM_OF_BITS(1), + .ASYNC_CLK(1) + ) i_sync_mem_reset ( + .in_bits(ctrl_mem_reset), + .out_clk(spi_clk), + .out_resetn(1'b1), + .out_bits(spi_mem_reset_s)); + + end else begin + assign spi_enable_s = ctrl_enable; + assign ctrl_enabled = spi_enable_s | spi_active; + assign spi_mem_reset_s = ctrl_mem_reset; + end endgenerate + + assign spi_cmd_rd_addr_next = spi_cmd_rd_addr + 1; + + always @(posedge spi_clk) begin + if (spi_resetn == 1'b0) begin + spi_active <= 1'b0; + end else begin + if (spi_active == 1'b0) begin + if ((trigger_s == 1'b1 && spi_enable_s == 1'b1)) begin + spi_active <= 1'b1; + end + end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin + spi_active <= 1'b0; + end + end + end + + always @(posedge spi_clk) begin + if (cmd_valid == 1'b0) begin + spi_cmd_rd_addr <= 'h00; + end else if (cmd_ready == 1'b1) begin + spi_cmd_rd_addr <= spi_cmd_rd_addr_next; + end + end + + always @(posedge spi_clk) begin + if (spi_active == 1'b0) begin + spi_sdo_rd_addr <= 'h00; + end else if (sdo_data_ready == 1'b1) begin + spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1; + end + end + + always @(posedge ctrl_clk) begin + if (ctrl_cmd_wr_en == 1'b1) begin + cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data; + end + end + + always @(posedge ctrl_clk) begin + if (ctrl_mem_reset == 1'b1) begin + ctrl_cmd_wr_addr <= 0; + end else if (ctrl_cmd_wr_en == 1'b1) begin + ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1; + end + end + + // request data from the DMA at the desired rate + + always @(posedge dma_clk) begin + if (dma_xfer_req == 1'b0) begin + dma_valid <= 1'b0; + end else begin + if ((trigger_s == 1'b1) && (dma_enable == 1'b1) && (spi_enable_s == 1'b1)) begin + dma_valid <= 1'b1; + end + if (dma_valid == 1'b1) begin + dma_valid <= 1'b0; + end + end + if (dma_valid == 1'b1) begin + sdo_mem[1] <= dma_data[15:8]; + sdo_mem[2] <= dma_data[ 7:0]; + end + if (sequence_valid_s == 1'b1) begin + sdo_mem[0] <= sequence_data_s; + end + end + + // rate controller + + assign dac_rstn_s = ~dac_rst_s; + util_pulse_gen #( + .PULSE_WIDTH(1) + ) i_trigger_gen ( + .clk (spi_clk), + .rstn (dac_rstn_s), + .pulse_width (1'b1), + .pulse_period (pulse_period_s), + .load_config (1'b1), + .pulse (trigger_s)); + + // offset of the sequencer registers are 8'h40 + + always @(negedge up_rstn or posedge spi_clk) begin + if (up_rstn == 1'b0) begin + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_rdata <= up_rdata_s[0] | up_rdata_s[1]; + up_rack <= up_rack_s[0] | up_rack_s[1]; + up_wack <= up_wack_s[0] | up_wack_s[1]; + end + end + + // DAC common registermap + + assign pulse_period_s = {16'h0, dac_datarate_s}; + + up_ad5766_sequencer #( + .SEQ_ID(4) + ) i_sequencer ( + .sequence_clk (spi_clk), + .sequence_rst (spi_mem_reset_s), + .sequence_req (dma_valid), + .sequence_valid (sequence_valid_s), + .sequence_data (sequence_data_s), + .up_rstn (up_rstn), + .up_clk (spi_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + up_dac_common #( + .COMMON_ID (0), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .CONFIG (0), + .CLK_EDGE_SEL (0), + .DRP_DISABLE (6'h00), + .USERPORTS_DISABLE (0), + .GPIO_DISABLE (0) + ) i_dac_common ( + .mmcm_rst (), + .dac_clk (spi_clk), + .dac_rst (dac_rst_s), + .dac_sync (), + .dac_frame (), + .dac_clksel (), + .dac_custom_wr(), + .dac_custom_rd(32'b0), + .dac_custom_control(), + .dac_status_if_busy(1'b0), + .dac_par_type (), + .dac_par_enb (), + .dac_r1_mode (), + .dac_datafmt (dac_datafmt), + .dac_datarate (dac_datarate_s), + .dac_status (1'b0), + .dac_status_unf (dma_underflow), + .dac_clk_ratio (32'b0), + .up_dac_ce (), + .up_pps_rcounter (32'b0), + .up_pps_status (1'b0), + .up_pps_irq_mask (), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (16'b0), + .up_drp_ready (1'b0), + .up_drp_locked (1'b0), + .up_usr_chanmax (), + .dac_usr_chanmax (8'b0), + .up_dac_gpio_in (32'b0), + .up_dac_gpio_out (), + .up_rstn (up_rstn), + .up_clk (spi_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // AXI wrapper + + up_axi #( + .AXI_ADDRESS_WIDTH (16) + ) i_up_axi ( + .up_rstn (up_rstn), + .up_clk (spi_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ad5766/axi_ad5766.xpr b/adi_library/axi_ad5766/axi_ad5766.xpr new file mode 100644 index 00000000..bac32314 --- /dev/null +++ b/adi_library/axi_ad5766/axi_ad5766.xpr @@ -0,0 +1,462 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_ad5766/axi_ad5766_ip.tcl b/adi_library/axi_ad5766/axi_ad5766_ip.tcl new file mode 100644 index 00000000..8bc108d1 --- /dev/null +++ b/adi_library/axi_ad5766/axi_ad5766_ip.tcl @@ -0,0 +1,69 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create axi_ad5766 +adi_ip_files axi_ad5766 [list \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_dac_common.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/util_pulse_gen.v" \ + "up_ad5766_sequencer.v" \ + "axi_ad5766.v" ] + +adi_ip_properties axi_ad5766 + +adi_init_bd_tcl +adi_ip_bd axi_ad5766 "bd/bd.tcl" + +adi_ip_add_core_dependencies [list \ + analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \ +] + +adi_add_bus "spi_engine_ctrl" "master" \ + "analog.com:interface:spi_engine_ctrl_rtl:1.0" \ + "analog.com:interface:spi_engine_ctrl:1.0" \ + { + {"cmd_ready" "CMD_READY"} \ + {"cmd_valid" "CMD_VALID"} \ + {"cmd_data" "CMD_DATA"} \ + {"sdo_data_ready" "SDO_READY"} \ + {"sdo_data_valid" "SDO_VALID"} \ + {"sdo_data" "SDO_DATA"} \ + {"sdi_data_ready" "SDI_READY"} \ + {"sdi_data_valid" "SDI_VALID"} \ + {"sdi_data" "SDI_DATA"} \ + {"sync_ready" "SYNC_READY"} \ + {"sync_valid" "SYNC_VALID"} \ + {"sync_data" "SYNC_DATA"} \ + } + +adi_add_bus "spi_engine_offload_ctrl" "slave" \ + "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \ + "analog.com:interface:spi_engine_offload_ctrl:1.0" \ + { \ + { "ctrl_cmd_wr_en" "CMD_WR_EN"} \ + { "ctrl_cmd_wr_data" "CMD_WR_DATA"} \ + { "ctrl_enable" "ENABLE"} \ + { "ctrl_enabled" "ENABLED"} \ + { "ctrl_mem_reset" "MEM_RESET"} \ + } + +adi_add_bus_clock "ctrl_clk" "spi_engine_offload_ctrl" +adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn" +adi_add_bus_clock "dma_clk" "dma_fifo_tx" + +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + +ipx::save_core [ipx::current_core] diff --git a/adi_library/axi_ad5766/bd/bd.tcl b/adi_library/axi_ad5766/bd/bd.tcl new file mode 100644 index 00000000..dceb9498 --- /dev/null +++ b/adi_library/axi_ad5766/bd/bd.tcl @@ -0,0 +1,47 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + DEV_PACKAGE \ + SPEED_GRADE \ + FPGA_FAMILY \ + FPGA_TECHNOLOGY" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/axi_ad5766/component.xml b/adi_library/axi_ad5766/component.xml new file mode 100644 index 00000000..e377d40d --- /dev/null +++ b/adi_library/axi_ad5766/component.xml @@ -0,0 +1,1600 @@ + + + analog.com + user + axi_ad5766 + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + spi_engine_ctrl + + + + + + + CMD_READY + + + cmd_ready + + + + + CMD_VALID + + + cmd_valid + + + + + CMD_DATA + + + cmd_data + + + + + SDO_READY + + + sdo_data_ready + + + + + SDO_VALID + + + sdo_data_valid + + + + + SDO_DATA + + + sdo_data + + + + + SDI_READY + + + sdi_data_ready + + + + + SDI_VALID + + + sdi_data_valid + + + + + SDI_DATA + + + sdi_data + + + + + SYNC_READY + + + sync_ready + + + + + SYNC_VALID + + + sync_valid + + + + + SYNC_DATA + + + sync_data + + + + + + spi_engine_offload_ctrl + + + + + + + CMD_WR_EN + + + ctrl_cmd_wr_en + + + + + CMD_WR_DATA + + + ctrl_cmd_wr_data + + + + + ENABLE + + + ctrl_enable + + + + + ENABLED + + + ctrl_enabled + + + + + MEM_RESET + + + ctrl_mem_reset + + + + + + spi_engine_offload_ctrl_signal_clock + spi_engine_offload_ctrl_signal_clock + + + + + + + CLK + + + ctrl_clk + + + + + + ASSOCIATED_BUSIF + spi_engine_offload_ctrl + + + + + spi_engine_ctrl_signal_clock + spi_engine_ctrl_signal_clock + + + + + + + CLK + + + spi_clk + + + + + + ASSOCIATED_BUSIF + spi_engine_ctrl + + + ASSOCIATED_RESET + spi_resetn + + + + + spi_engine_ctrl_signal_reset + spi_engine_ctrl_signal_reset + + + + + + + RST + + + spi_resetn + + + + + + POLARITY + ACTIVE_LOW + + + + + dma_fifo_tx_signal_clock + dma_fifo_tx_signal_clock + + + + + + + CLK + + + dma_clk + + + + + + ASSOCIATED_BUSIF + dma_fifo_tx + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_ad5766 + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + effc7a98 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_ad5766 + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + effc7a98 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_xpgui_view_fileset + + + + viewChecksum + cd4b316c + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_blockdiagram_view_fileset + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_valid + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_enable + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_data + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + dma_xfer_req + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_underflow + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + spi_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + spi_resetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cmd_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cmd_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cmd_data + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sdo_data_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + sdo_data_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sdo_data + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sdi_data_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sdi_data_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + sdi_data + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + sync_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sync_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sync_data + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + ctrl_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ctrl_cmd_wr_en + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + ctrl_cmd_wr_data + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + ctrl_enable + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ctrl_enabled + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ctrl_mem_reset + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + ASYNC_SPI_CLK + Async Spi Clk + 0 + + + CMD_MEM_ADDRESS_WIDTH + Cmd Mem Address Width + 4 + + + SDO_MEM_ADDRESS_WIDTH + Sdo Mem Address Width + 4 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_00ecfe9a + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + + + choice_pairs_19f99f31 + 0 + 10 + 11 + 12 + 13 + 14 + 20 + 21 + 22 + 23 + 24 + 25 + 30 + + + choice_pairs_28f798a2 + 0 + 1 + 2 + 3 + 4 + + + choice_pairs_fc01a186 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../common/ad_rst.v + verilogSource + + + up_ad5766_sequencer.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_dac_common.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + ../common/util_pulse_gen.v + verilogSource + + + axi_ad5766.v + verilogSource + CHECKSUM_285d8cd9 + + + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_rst.v + verilogSource + + + up_ad5766_sequencer.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_dac_common.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + ../common/util_pulse_gen.v + verilogSource + + + axi_ad5766.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axi_ad5766_v1_0.tcl + tclSource + CHECKSUM_092e488f + XGUI_VERSION_2 + + + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + axi_ad5766_v1_0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + ASYNC_SPI_CLK + Async Spi Clk + 0 + + + CMD_MEM_ADDRESS_WIDTH + Cmd Mem Address Width + 4 + + + SDO_MEM_ADDRESS_WIDTH + Sdo Mem Address Width + 4 + + + Component_Name + axi_ad5766_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_ad5766_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:38:31Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_ad5766/temporary_case_dependencies.mk b/adi_library/axi_ad5766/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/axi_ad5766/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/axi_ad5766/up_ad5766_sequencer.v b/adi_library/axi_ad5766/up_ad5766_sequencer.v new file mode 100644 index 00000000..a9ccb7e0 --- /dev/null +++ b/adi_library/axi_ad5766/up_ad5766_sequencer.v @@ -0,0 +1,260 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module up_ad5766_sequencer #( + + parameter SEQ_ID = 0 +) ( + input sequence_clk, + input sequence_rst, + input sequence_req, + output reg sequence_valid, + output reg [ 7:0] sequence_data, + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack +); + + // registers + + reg [ 7:0] up_sequencer[15:0]; + reg [ 3:0] up_endof_seq = 4'b0; + reg up_xfer_req = 1'b0; + reg [ 3:0] sequence_counter = 0; + + // internal signals + + wire up_wreq_s; + wire up_rreq_s; + wire [ 7:0] sequencer[15:0]; + wire [ 3:0] end_of_sequence; + + integer i; + + // sequence counter + + always @(posedge sequence_clk) begin + if (sequence_rst) begin + sequence_counter <= 4'b0; + end else if (sequence_req) begin + sequence_counter <= (sequence_counter == end_of_sequence) ? 0 : sequence_counter + 1; + end + end + + // sequence output mux + + always @(posedge sequence_clk) begin + if (sequence_rst) begin + sequence_data <= 16'b0; + end + else if (sequence_req) begin + sequence_data <= sequencer[sequence_counter]; + end + sequence_valid <= sequence_req; + end + + // decode block select + + assign up_wreq_s = (up_waddr[13:8] == SEQ_ID) ? up_wreq : 1'b0; + assign up_rreq_s = (up_raddr[13:8] == SEQ_ID) ? up_rreq : 1'b0; + + // processor write interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + for (i=0; i<16; i=i+1) begin + up_sequencer[i] <= 8'b0; + end + up_endof_seq <= 4'b0; + up_wack <= 1'b0; + end else begin + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h40)) begin + up_sequencer[0] <= up_wdata[7:0]; + up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h41)) begin + up_sequencer[1] <= up_wdata[7:0]; + up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h42)) begin + up_sequencer[2] <= up_wdata[7:0]; + up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h43)) begin + up_sequencer[3] <= up_wdata[7:0]; + up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h44)) begin + up_sequencer[4] <= up_wdata[7:0]; + up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h45)) begin + up_sequencer[5] <= up_wdata[7:0]; + up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h46)) begin + up_sequencer[6] <= up_wdata[7:0]; + up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h47)) begin + up_sequencer[7] <= up_wdata[7:0]; + up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h48)) begin + up_sequencer[8] <= up_wdata[7:0]; + up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h49)) begin + up_sequencer[9] <= up_wdata[7:0]; + up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4a)) begin + up_sequencer[10] <= up_wdata[7:0]; + up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4b)) begin + up_sequencer[11] <= up_wdata[7:0]; + up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4c)) begin + up_sequencer[12] <= up_wdata[7:0]; + up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4d)) begin + up_sequencer[13] <= up_wdata[7:0]; + up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4e)) begin + up_sequencer[14] <= up_wdata[7:0]; + up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h4f)) begin + up_sequencer[15] <= up_wdata[7:0]; + up_endof_seq <= (up_wdata[16]) ? up_waddr[3:0] : 4'b0; + end + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[7:0]) + 8'h40 : up_rdata <= {24'b0, up_sequencer[0]}; + 8'h41 : up_rdata <= {24'b0, up_sequencer[1]}; + 8'h42 : up_rdata <= {24'b0, up_sequencer[2]}; + 8'h43 : up_rdata <= {24'b0, up_sequencer[3]}; + 8'h44 : up_rdata <= {24'b0, up_sequencer[4]}; + 8'h45 : up_rdata <= {24'b0, up_sequencer[5]}; + 8'h46 : up_rdata <= {24'b0, up_sequencer[6]}; + 8'h47 : up_rdata <= {24'b0, up_sequencer[7]}; + 8'h48 : up_rdata <= {24'b0, up_sequencer[8]}; + 8'h49 : up_rdata <= {24'b0, up_sequencer[9]}; + 8'h4a : up_rdata <= {24'b0, up_sequencer[10]}; + 8'h4b : up_rdata <= {24'b0, up_sequencer[11]}; + 8'h4c : up_rdata <= {24'b0, up_sequencer[12]}; + 8'h4d : up_rdata <= {24'b0, up_sequencer[13]}; + 8'h4e : up_rdata <= {24'b0, up_sequencer[14]}; + 8'h4f : up_rdata <= {24'b0, up_sequencer[15]}; + 8'h60 : up_rdata <= {27'b0, up_xfer_req, up_endof_seq}; + endcase + end else begin + up_rdata <= 32'b0; + end + end + end + + // CDC + + up_xfer_cntrl #( + .DATA_WIDTH(132) + ) i_xfer_cntrl ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_cntrl ({up_endof_seq, + up_sequencer[0], + up_sequencer[1], + up_sequencer[2], + up_sequencer[3], + up_sequencer[4], + up_sequencer[5], + up_sequencer[6], + up_sequencer[7], + up_sequencer[8], + up_sequencer[9], + up_sequencer[10], + up_sequencer[11], + up_sequencer[12], + up_sequencer[13], + up_sequencer[14], + up_sequencer[15]}), + .up_xfer_done (up_cntrl_xfer_done), + .d_rst (sequence_rst), + .d_clk (sequence_clk), + .d_data_cntrl ({end_of_sequence, + sequencer[0], + sequencer[1], + sequencer[2], + sequencer[3], + sequencer[4], + sequencer[5], + sequencer[6], + sequencer[7], + sequencer[8], + sequencer[9], + sequencer[10], + sequencer[11], + sequencer[12], + sequencer[13], + sequencer[14], + sequencer[15]})); + +endmodule diff --git a/adi_library/axi_ad5766/xgui/axi_ad5766_v1_0.tcl b/adi_library/axi_ad5766/xgui/axi_ad5766_v1_0.tcl new file mode 100644 index 00000000..a5055400 --- /dev/null +++ b/adi_library/axi_ad5766/xgui/axi_ad5766_v1_0.tcl @@ -0,0 +1,118 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ASYNC_SPI_CLK" -parent ${Page_0} + ipgui::add_param $IPINST -name "CMD_MEM_ADDRESS_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "SDO_MEM_ADDRESS_WIDTH" -parent ${Page_0} + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } { + # Procedure called to update ASYNC_SPI_CLK when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } { + # Procedure called to validate ASYNC_SPI_CLK + return true +} + +proc update_PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } { + # Procedure called to update CMD_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } { + # Procedure called to validate CMD_MEM_ADDRESS_WIDTH + return true +} + +proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to validate DEV_PACKAGE + return true +} + +proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to validate FPGA_FAMILY + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } { + # Procedure called to update SDO_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } { + # Procedure called to validate SDO_MEM_ADDRESS_WIDTH + return true +} + +proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to validate SPEED_GRADE + return true +} + + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY} +} + +proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE} +} + +proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE} +} + +proc update_MODELPARAM_VALUE.ASYNC_SPI_CLK { MODELPARAM_VALUE.ASYNC_SPI_CLK PARAM_VALUE.ASYNC_SPI_CLK } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASYNC_SPI_CLK}] ${MODELPARAM_VALUE.ASYNC_SPI_CLK} +} + +proc update_MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH} +} + +proc update_MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH} +} + diff --git a/adi_library/axi_ad7606x/Makefile b/adi_library/axi_ad7606x/Makefile new file mode 100644 index 00000000..324a9b94 --- /dev/null +++ b/adi_library/axi_ad7606x/Makefile @@ -0,0 +1,30 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_ad7606x + +GENERIC_DEPS += ../common/ad_datafmt.v +GENERIC_DEPS += ../common/ad_edge_detect.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_adc_channel.v +GENERIC_DEPS += ../common/up_adc_common.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_delay_cntrl.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_ad7606x.v +GENERIC_DEPS += axi_ad7606x_16b_pif.v +GENERIC_DEPS += axi_ad7606x_18b_pif.v + +XILINX_DEPS += ../xilinx/common/ad_dcfilter.v +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_ad7606x_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_ad7606x/axi_ad7606x.v b/adi_library/axi_ad7606x/axi_ad7606x.v new file mode 100644 index 00000000..d458ce9a --- /dev/null +++ b/adi_library/axi_ad7606x/axi_ad7606x.v @@ -0,0 +1,488 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad7606x #( + + parameter ID = 0, + parameter DEV_CONFIG = 0, + parameter ADC_CH_DW = 16, + parameter ADC_N_BITS = 16, + parameter EXTERNAL_CLK = 0 +) ( + + // physical data interface + + output rx_cs_n, + output [15:0] rx_db_o, + input [15:0] rx_db_i, + output rx_db_t, + output rx_rd_n, + output rx_wr_n, + input external_clk, + + // physical control interface + + input rx_busy, + input first_data, + + // AXI Slave Memory Map + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + + input adc_dovf, + output adc_clk, + + output adc_valid, + output [ADC_CH_DW-1:0] adc_data_0, + output [ADC_CH_DW-1:0] adc_data_1, + output [ADC_CH_DW-1:0] adc_data_2, + output [ADC_CH_DW-1:0] adc_data_3, + output [ADC_CH_DW-1:0] adc_data_4, + output [ADC_CH_DW-1:0] adc_data_5, + output [ADC_CH_DW-1:0] adc_data_6, + output [ADC_CH_DW-1:0] adc_data_7, + output adc_enable_0, + output adc_enable_1, + output adc_enable_2, + output adc_enable_3, + output adc_enable_4, + output adc_enable_5, + output adc_enable_6, + output adc_enable_7, + output adc_reset +); + + localparam [31:0] RD_RAW_CAP = 32'h2000; + localparam AD7606B = 1'b0; + localparam AD7606C_16 = 1'b1; + + // internal registers + + reg up_wack = 1'b0; + reg up_rack = 1'b0; + reg [31:0] up_rdata = 32'b0; + reg [31:0] up_rdata_r; + reg up_rack_r; + reg up_wack_r; + + // internal signals + + wire [ADC_N_BITS-1:0] adc_data_0_s; + wire [ADC_N_BITS-1:0] adc_data_1_s; + wire [ADC_N_BITS-1:0] adc_data_2_s; + wire [ADC_N_BITS-1:0] adc_data_3_s; + wire [ADC_N_BITS-1:0] adc_data_4_s; + wire [ADC_N_BITS-1:0] adc_data_5_s; + wire [ADC_N_BITS-1:0] adc_data_6_s; + wire [ADC_N_BITS-1:0] adc_data_7_s; + wire [(8*ADC_N_BITS)-1:0] adc_data_s; + wire [ 7:0] adc_status_header[0:7]; + wire adc_status; + wire [15:0] adc_crc; + wire [15:0] adc_crc_res; + wire adc_crc_err; + wire adc_mode_en; + wire [ 7:0] adc_custom_control; + + wire adc_dfmt_enable_s[0:7]; + wire adc_dfmt_type_s[0:7]; + wire adc_dfmt_se_s[0:7]; + + wire adc_clk_s; + wire [ 7:0] adc_enable; + wire adc_reset_s; + + wire [(8*ADC_CH_DW)-1:0] dma_data; + wire dma_dvalid; + + wire up_clk; + wire up_rstn; + wire up_rreq_s; + wire [13:0] up_raddr_s; + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire [31:0] up_rdata_s[0:8]; + wire [8:0] up_rack_s; + wire [8:0] up_wack_s; + + wire up_wack_cntrl_s; + wire up_rack_cntrl_s; + wire [31:0] up_rdata_cntrl_s; + + wire [31:0] wr_data_s; + wire [15:0] rd_data_s; + wire rd_valid_s; + wire [31:0] adc_config_ctrl_s; + wire adc_ctrl_status_s; + wire m_axis_ready_s; + wire m_axis_valid_s; + wire [15:0] m_axis_data_s; + wire m_axis_xfer_req_s; + + // defaults + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + assign adc_reset = adc_reset_s; + + assign adc_enable_0 = adc_enable[0]; + assign adc_enable_1 = adc_enable[1]; + assign adc_enable_2 = adc_enable[2]; + assign adc_enable_3 = adc_enable[3]; + assign adc_enable_4 = adc_enable[4]; + assign adc_enable_5 = adc_enable[5]; + assign adc_enable_6 = adc_enable[6]; + assign adc_enable_7 = adc_enable[7]; + + // processor read interface + + integer j; + + always @(*) begin + up_rdata_r = 'h00; + up_rack_r = 'h00; + up_wack_r = 'h00; + for (j = 0; j <= 8; j=j+1) begin + up_rack_r = up_rack_r | up_rack_s[j]; + up_wack_r = up_wack_r | up_wack_s[j]; + up_rdata_r = up_rdata_r | up_rdata_s[j]; + end + end + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_rdata <= up_rdata_r; + up_rack <= up_rack_r; + up_wack <= up_wack_r; + end + end + + generate + if (EXTERNAL_CLK == 1'b1) begin + assign adc_clk_s = external_clk; + end else begin + assign adc_clk_s = up_clk; + end + endgenerate + + assign adc_clk = adc_clk_s; + + generate + genvar i; + for (i = 0; i < 8; i = i + 1) begin + up_adc_channel #( + .CHANNEL_ID(i) + ) i_up_adc_channel ( + .adc_clk (adc_clk_s), + .adc_rst (adc_reset_s), + .adc_enable (adc_enable[i]), + .adc_iqcor_enb (), + .adc_dcfilt_enb (), + .adc_dfmt_se (adc_dfmt_se_s[i]), + .adc_dfmt_type (adc_dfmt_type_s[i]), + .adc_dfmt_enable (adc_dfmt_enable_s[i]), + .adc_dcfilt_offset (), + .adc_dcfilt_coeff (), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pnseq_sel (), + .adc_data_sel (), + .adc_pn_err (1'b0), + .adc_pn_oos (1'b0), + .adc_or (1'b0), + .adc_read_data (rd_data_s), + .adc_status_header(adc_status_header[i]), + .adc_crc_err(adc_crc_err), + .up_adc_pn_err (), + .up_adc_pn_oos (), + .up_adc_or (), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[i]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[i]), + .up_rack (up_rack_s[i])); + end + endgenerate + + genvar k; + generate + for (k = 0;k < 8;k = k + 1) begin + ad_datafmt #( + .DATA_WIDTH (ADC_N_BITS), + .BITS_PER_SAMPLE (ADC_CH_DW) + ) i_datafmt ( + .clk (adc_clk), + .valid (1'b1), + .data (adc_data_s[k*ADC_N_BITS+(ADC_N_BITS-1):k*ADC_N_BITS]), + .valid_out (dma_dvalid), + .data_out (dma_data[k*ADC_CH_DW+(ADC_CH_DW-1):k*ADC_CH_DW]), + .dfmt_enable (adc_dfmt_enable_s[k]), + .dfmt_type (adc_dfmt_type_s[k]), + .dfmt_se (adc_dfmt_se_s[k])); + end + endgenerate + + generate + if (DEV_CONFIG == AD7606B || DEV_CONFIG == AD7606C_16) begin + axi_ad7606x_16b_pif i_ad7606_parallel_interface ( + .cs_n (rx_cs_n), + .db_o (rx_db_o), + .db_i (rx_db_i), + .db_t (rx_db_t), + .rd_n (rx_rd_n), + .wr_n (rx_wr_n), + .busy (rx_busy), + .first_data (first_data), + .adc_data_0 (adc_data_0_s), + .adc_status_0 (adc_status_header[0]), + .adc_data_1 (adc_data_1_s), + .adc_status_1 (adc_status_header[1]), + .adc_data_2 (adc_data_2_s), + .adc_status_2 (adc_status_header[2]), + .adc_data_3 (adc_data_3_s), + .adc_status_3 (adc_status_header[3]), + .adc_data_4 (adc_data_4_s), + .adc_status_4 (adc_status_header[4]), + .adc_data_5 (adc_data_5_s), + .adc_status_5 (adc_status_header[5]), + .adc_data_6 (adc_data_6_s), + .adc_status_6 (adc_status_header[6]), + .adc_data_7 (adc_data_7_s), + .adc_status_7 (adc_status_header[7]), + .adc_status (adc_status), + .adc_crc (adc_crc), + .adc_crc_res (adc_crc_res), + .adc_crc_err (adc_crc_err), + .adc_valid (adc_valid), + .clk (adc_clk_s), + .rstn (up_rstn), + .adc_config_ctrl (adc_config_ctrl_s), + .adc_ctrl_status (adc_ctrl_status_s), + .adc_mode_en (adc_mode_en), + .adc_custom_control (adc_custom_control), + .wr_data (wr_data_s[15:0]), + .rd_data (rd_data_s), + .rd_valid (rd_valid_s)); + end else begin + axi_ad7606x_18b_pif i_ad7606_parallel_interface ( + .cs_n (rx_cs_n), + .db_o (rx_db_o), + .db_i (rx_db_i), + .db_t (rx_db_t), + .rd_n (rx_rd_n), + .wr_n (rx_wr_n), + .busy (rx_busy), + .first_data (first_data), + .adc_data_0 (adc_data_0_s), + .adc_status_0 (adc_status_header[0]), + .adc_data_1 (adc_data_1_s), + .adc_status_1 (adc_status_header[1]), + .adc_data_2 (adc_data_2_s), + .adc_status_2 (adc_status_header[2]), + .adc_data_3 (adc_data_3_s), + .adc_status_3 (adc_status_header[3]), + .adc_data_4 (adc_data_4_s), + .adc_status_4 (adc_status_header[4]), + .adc_data_5 (adc_data_5_s), + .adc_status_5 (adc_status_header[5]), + .adc_data_6 (adc_data_6_s), + .adc_status_6 (adc_status_header[6]), + .adc_data_7 (adc_data_7_s), + .adc_status_7 (adc_status_header[7]), + .adc_status (adc_status), + .adc_crc (adc_crc), + .adc_crc_res (adc_crc_res), + .adc_crc_err (adc_crc_err), + .adc_valid (adc_valid), + .clk (adc_clk_s), + .rstn (up_rstn), + .adc_config_ctrl (adc_config_ctrl_s), + .adc_ctrl_status (adc_ctrl_status_s), + .adc_mode_en (adc_mode_en), + .adc_custom_control (adc_custom_control), + .wr_data (wr_data_s[15:0]), + .rd_data (rd_data_s), + .rd_valid (rd_valid_s)); + end + endgenerate + + assign adc_data_s = {adc_data_0_s,adc_data_1_s,adc_data_2_s,adc_data_3_s,adc_data_4_s,adc_data_5_s,adc_data_6_s,adc_data_7_s}; + assign adc_data_7 = dma_data[0*ADC_CH_DW+(ADC_CH_DW-1):0*ADC_CH_DW]; + assign adc_data_6 = dma_data[1*ADC_CH_DW+(ADC_CH_DW-1):1*ADC_CH_DW]; + assign adc_data_5 = dma_data[2*ADC_CH_DW+(ADC_CH_DW-1):2*ADC_CH_DW]; + assign adc_data_4 = dma_data[3*ADC_CH_DW+(ADC_CH_DW-1):3*ADC_CH_DW]; + assign adc_data_3 = dma_data[4*ADC_CH_DW+(ADC_CH_DW-1):4*ADC_CH_DW]; + assign adc_data_2 = dma_data[5*ADC_CH_DW+(ADC_CH_DW-1):5*ADC_CH_DW]; + assign adc_data_1 = dma_data[6*ADC_CH_DW+(ADC_CH_DW-1):6*ADC_CH_DW]; + assign adc_data_0 = dma_data[7*ADC_CH_DW+(ADC_CH_DW-1):7*ADC_CH_DW]; + + up_adc_common #( + .ID (ID), + .CONFIG (RD_RAW_CAP) + ) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk_s), + .adc_rst (adc_reset_s), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (adc_status), + .adc_sync_status (1'b1), + .adc_status_ovf (adc_dovf), + .adc_clk_ratio (), + .adc_start_code (), + .adc_sref_sync (), + .adc_sync (), + .adc_ext_sync_arm (), + .adc_ext_sync_disarm (), + .adc_ext_sync_manual_req (), + .adc_num_lanes (), + .adc_custom_control (adc_custom_control), + .adc_crc_enable (adc_mode_en), + .adc_sdr_ddr_n (), + .adc_symb_op (), + .adc_symb_8_16b (), + .up_pps_rcounter (), + .up_pps_status (), + .up_pps_irq_mask (), + .up_adc_r1_mode (), + .up_status_pn_err (), + .up_status_pn_oos (), + .up_status_or (), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (), + .up_drp_ready (), + .up_drp_locked (), + .adc_config_wr (wr_data_s), + .adc_config_ctrl (adc_config_ctrl_s), + .adc_config_rd ({16'd0, rd_data_s}), + .adc_ctrl_status (adc_ctrl_status_s), + .up_adc_gpio_in (), + .up_adc_gpio_out (), + .up_adc_ce (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[8]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[8]), + .up_rack (up_rack_s[8])); + + // up bus interface + + up_axi #( + .AXI_ADDRESS_WIDTH (16) + ) i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ad7606x/axi_ad7606x.xpr b/adi_library/axi_ad7606x/axi_ad7606x.xpr new file mode 100644 index 00000000..a8b5ba8c --- /dev/null +++ b/adi_library/axi_ad7606x/axi_ad7606x.xpr @@ -0,0 +1,516 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_ad7606x/axi_ad7606x_16b_pif.v b/adi_library/axi_ad7606x/axi_ad7606x_16b_pif.v new file mode 100644 index 00000000..a1fbf90a --- /dev/null +++ b/adi_library/axi_ad7606x/axi_ad7606x_16b_pif.v @@ -0,0 +1,475 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad7606x_16b_pif #( + parameter NEG_EDGE = 1, + parameter POS_EDGE = 0 +) ( + + // physical interface + + output cs_n, + output [15:0] db_o, + input [15:0] db_i, + output db_t, + output rd_n, + output wr_n, + input busy, + input first_data, + + // FIFO interface + + output reg [15:0] adc_data_0, + output reg [ 7:0] adc_status_0 = 'h0, + output reg [15:0] adc_data_1, + output reg [ 7:0] adc_status_1 = 'h0, + output reg [15:0] adc_data_2, + output reg [ 7:0] adc_status_2 = 'h0, + output reg [15:0] adc_data_3, + output reg [ 7:0] adc_status_3 = 'h0, + output reg [15:0] adc_data_4, + output reg [ 7:0] adc_status_4 = 'h0, + output reg [15:0] adc_data_5, + output reg [ 7:0] adc_status_5 = 'h0, + output reg [15:0] adc_data_6, + output reg [ 7:0] adc_status_6 = 'h0, + output reg [15:0] adc_data_7, + output reg [ 7:0] adc_status_7 = 'h0, + output adc_status, + output [15:0] adc_crc, + output [15:0] adc_crc_res, + output adc_crc_err, + output reg adc_valid, + + // register access + + input clk, + input rstn, + input [31:0] adc_config_ctrl, + output adc_ctrl_status, + input [15:0] wr_data, + input adc_mode_en, + input [7:0] adc_custom_control, + output reg [15:0] rd_data = 'hf, + output reg rd_valid +); + + // state registers + + localparam [ 2:0] IDLE = 3'h0; + localparam [ 2:0] CS_LOW = 3'h1; + localparam [ 2:0] CNTRL_LOW = 3'h2; + localparam [ 2:0] CNTRL_HIGH = 3'h3; + localparam [ 2:0] CS_HIGH = 3'h4; + localparam [ 1:0] SIMPLE = 0; + localparam [ 1:0] STATUS_HEADER = 2; + localparam [ 1:0] CRC_ENABLED = 1; + localparam [ 1:0] CRC_STATUS = 3; + + // internal registers + + reg [ 2:0] transfer_state = 3'h0; + reg [ 2:0] transfer_state_next = 3'h0; + reg [ 3:0] width_counter = 4'h0; + reg [ 4:0] channel_counter = 5'h0; + reg [ 4:0] nr_rd_burst = 5'h0; + + reg rd_conv_d = 1'h0; + reg adc_config_enable_d = 1'h0; + + reg rd_valid_d = 1'h0; + reg read_ch_data = 1'd0; + + reg [ 7:0] adc_status_er_ch_id = 8'h0; + reg [15:0] adc_crc_r = 16'h0; + reg [15:0] adc_crc_res_r = 16'h0; + + reg [ 1:0] adc_config_mode_r = 2'h0; + + // internal wires + + wire rd_req_s; + wire wr_req_s; + + wire end_of_conv; + wire start_transfer_s; + wire rd_valid_s; + wire rd_new_data_s; + wire adc_config_enable; + wire adc_config_en; + wire adc_config_rd_wr; + wire [ 1:0] adc_config_mode; + + wire [ 4:0] adc_status_er_5b; + wire adc_status_er; + + // adc_config_rd_wr - RD (1), WR (0) + + assign adc_config_enable = adc_config_ctrl[0]; + assign adc_config_rd_wr = adc_config_ctrl[1]; + + // instantiations + + ad_edge_detect #( + .EDGE(POS_EDGE) + ) i_ad_edge_detect_en ( + .clk (clk), + .rst (~rstn), + .signal_in (adc_config_enable), + .signal_out (adc_config_en)); + + ad_edge_detect #( + .EDGE(NEG_EDGE) + ) i_ad_edge_detect ( + .clk (clk), + .rst (~rstn), + .signal_in (busy), + .signal_out (end_of_conv)); + + // counters to control the RD_N and WR_N lines + + assign start_transfer_s = (end_of_conv | adc_config_en) ? 1'b1 : 1'b0; + + always @(posedge clk) begin + if (rstn == 1'b0) begin + adc_config_mode_r <= 2'h0; + end else begin + if (adc_mode_en) begin + if (adc_custom_control == 'h0) begin + adc_config_mode_r <= SIMPLE; + end else if (adc_custom_control == 'h1) begin + adc_config_mode_r <= CRC_ENABLED; + end else if (adc_custom_control == 'h2) begin + adc_config_mode_r <= STATUS_HEADER; + end else if (adc_custom_control == 'h3) begin + adc_config_mode_r <= CRC_STATUS; + end else begin + adc_config_mode_r <= adc_config_mode; + end + end else begin + adc_config_mode_r <= adc_config_mode; + end + end + end + + assign adc_config_mode = adc_config_mode_r; + + always @(negedge clk) begin + if (transfer_state == IDLE) begin + rd_conv_d <= end_of_conv; + adc_config_enable_d <= adc_config_en; + end + end + + always @(posedge clk) begin + if (rstn == 1'b0) begin + width_counter <= 4'h0; + end else begin + if(transfer_state == CNTRL_LOW || transfer_state == CNTRL_HIGH) begin + width_counter <= width_counter + 1; + end else begin + width_counter <= 4'h0; + end + end + end + + always @(posedge clk) begin + if (rstn == 1'b0) begin + channel_counter <= 5'h0; + end else begin + if (rd_new_data_s == 1'b1 && read_ch_data == 1'b1) begin + channel_counter <= channel_counter + 1; + end else if (transfer_state == IDLE) begin + channel_counter <= 5'h0; + end + end + end + + always @(posedge clk) begin + if (adc_config_mode == SIMPLE) begin + nr_rd_burst = 5'd8; + if ((first_data & ~cs_n) && ~adc_config_enable_d) begin + read_ch_data <= 1'b1; + end else if (channel_counter == 5'd8 && transfer_state == IDLE) begin + read_ch_data <= 1'b0; + end + end else if (adc_config_mode == CRC_ENABLED) begin + nr_rd_burst = 5'd9; + if ((first_data & ~cs_n) && ~adc_config_enable_d) begin + read_ch_data <= 1'b1; + end else if (channel_counter == 5'd9 && transfer_state == IDLE) begin + read_ch_data <= 1'b0; + end + end else if (adc_config_mode == STATUS_HEADER) begin + nr_rd_burst <= 5'd16; + if ((first_data & ~cs_n) && ~adc_config_enable_d) begin + read_ch_data <= 1'b1; + end else if (channel_counter == 5'd16 && transfer_state == IDLE) begin + read_ch_data <= 1'b0; + end + end else if (adc_config_mode == CRC_STATUS) begin + nr_rd_burst <= 5'd17; + if ((first_data & ~cs_n) && ~adc_config_enable_d) begin + read_ch_data <= 1'b0; + end else if (channel_counter == 5'd17 && transfer_state == IDLE) begin + read_ch_data <= 1'b0; + end + end else begin + read_ch_data <= 1'b1; + end + if (adc_config_mode == SIMPLE || adc_config_mode == CRC_ENABLED) begin + if (read_ch_data == 1'b1 && rd_new_data_s == 1'b1) begin + case (channel_counter) + 5'd0 : begin + adc_data_0 <= rd_data; + end + 5'd1 : begin + adc_data_1 <= rd_data; + end + 5'd2 : begin + adc_data_2 <= rd_data; + end + 5'd3 : begin + adc_data_3 <= rd_data; + end + 5'd4 : begin + adc_data_4 <= rd_data; + end + 5'd5 : begin + adc_data_5 <= rd_data; + end + 5'd6 : begin + adc_data_6 <= rd_data; + end + 5'd7 : begin + adc_data_7 <= rd_data; + end + 5'd8 : begin + adc_crc_r <= rd_data; + adc_crc_res_r <= crc_128({adc_data_0,adc_data_1,adc_data_2,adc_data_3, + adc_data_4,adc_data_5,adc_data_6,adc_data_7}); + end + endcase + end + case (adc_config_mode) + SIMPLE: begin + adc_valid <= (channel_counter == 5'd8) ? rd_valid_d : 1'b0; + end + CRC_ENABLED: begin + adc_valid <= (channel_counter == 5'd9) ? rd_valid_d : 1'b0; + end + endcase + end else if (adc_config_mode == STATUS_HEADER || adc_config_mode == CRC_STATUS) begin + if (read_ch_data == 1'b1 && rd_new_data_s == 1'b1) begin + case (channel_counter) + 5'd0: begin + adc_data_0 <= rd_data; + end + 5'd1: begin + adc_status_0 <= rd_data[15:8]; + end + 5'd2: begin + adc_data_1 <= rd_data; + end + 5'd3: begin + adc_status_1 <= rd_data[15:8]; + end + 5'd4: begin + adc_data_2 <= rd_data; + end + 5'd5: begin + adc_status_2 <= rd_data[15:8]; + end + 5'd6: begin + adc_data_3 <= rd_data; + end + 5'd7: begin + adc_status_3 <= rd_data[15:8]; + end + 5'd8: begin + adc_data_4 <= rd_data; + end + 5'd9: begin + adc_status_4 <= rd_data[15:8]; + end + 5'd10: begin + adc_data_5 <= rd_data; + end + 5'd11: begin + adc_status_5 <= rd_data[15:8]; + end + 5'd12: begin + adc_data_6 <= rd_data; + end + 5'd13: begin + adc_status_6 <= rd_data[15:8]; + end + 5'd14: begin + adc_data_7 <= rd_data; + end + 5'd15: begin + adc_status_7 <= rd_data[15:8]; + end + 5'd16: begin + adc_crc_r <= rd_data; + adc_crc_res_r <= crc_256({adc_data_0,8'b0,adc_status_0,adc_data_1,8'b0,adc_status_1,adc_data_2,8'b0,adc_status_2, + adc_data_3,8'b0,adc_status_3,adc_data_4,8'b0,adc_status_4,adc_data_5,8'b0,adc_status_5, + adc_data_6,8'b0,adc_status_6,adc_data_7,8'b0,adc_status_7}); + end + endcase + end + if (adc_config_mode == STATUS_HEADER) begin + adc_valid <= (channel_counter == 5'd16) ? rd_valid_d : 1'b0; + end else if (adc_config_mode == CRC_STATUS) begin + adc_valid <= (channel_counter == 5'd17) ? rd_valid_d : 1'b0; + end + end + end + + function [15:0] crc_128; + input [127:0] d; + begin + crc_128[0] = d[0] ^ d[2] ^ d[3] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[13] ^ d[18] ^ d[19] ^ d[23] ^ d[24] ^ d[25] ^ d[26] ^ d[28] ^ d[29] ^ d[32] ^ d[35] ^ d[36] ^ d[38] ^ d[42] ^ d[46] ^ d[51] ^ d[52] ^ d[54] ^ d[55] ^ d[56] ^ d[60] ^ d[61] ^ d[62] ^ d[64] ^ d[69] ^ d[70] ^ d[75] ^ d[77] ^ d[78] ^ d[82] ^ d[83] ^ d[84] ^ d[86] ^ d[88] ^ d[89] ^ d[90] ^ d[91] ^ d[92] ^ d[95] ^ d[97] ^ d[98] ^ d[99] ^ d[104] ^ d[111] ^ d[112] ^ d[113] ^ d[114] ^ d[119] ^ d[120] ^ d[121] ^ d[123] ^ d[124] ^ d[125]; + crc_128[1] = d[0] ^ d[1] ^ d[2] ^ d[4] ^ d[6] ^ d[11] ^ d[13] ^ d[14] ^ d[18] ^ d[20] ^ d[23] ^ d[27] ^ d[28] ^ d[30] ^ d[32] ^ d[33] ^ d[35] ^ d[37] ^ d[38] ^ d[39] ^ d[42] ^ d[43] ^ d[46] ^ d[47] ^ d[51] ^ d[53] ^ d[54] ^ d[57] ^ d[60] ^ d[63] ^ d[64] ^ d[65] ^ d[69] ^ d[71] ^ d[75] ^ d[76] ^ d[77] ^ d[79] ^ d[82] ^ d[85] ^ d[86] ^ d[87] ^ d[88] ^ d[93] ^ d[95] ^ d[96] ^ d[97] ^ d[100] ^ d[104] ^ d[105] ^ d[111] ^ d[115] ^ d[119] ^ d[122] ^ d[123] ^ d[126]; + crc_128[2] = d[1] ^ d[2] ^ d[3] ^ d[5] ^ d[7] ^ d[12] ^ d[14] ^ d[15] ^ d[19] ^ d[21] ^ d[24] ^ d[28] ^ d[29] ^ d[31] ^ d[33] ^ d[34] ^ d[36] ^ d[38] ^ d[39] ^ d[40] ^ d[43] ^ d[44] ^ d[47] ^ d[48] ^ d[52] ^ d[54] ^ d[55] ^ d[58] ^ d[61] ^ d[64] ^ d[65] ^ d[66] ^ d[70] ^ d[72] ^ d[76] ^ d[77] ^ d[78] ^ d[80] ^ d[83] ^ d[86] ^ d[87] ^ d[88] ^ d[89] ^ d[94] ^ d[96] ^ d[97] ^ d[98] ^ d[101] ^ d[105] ^ d[106] ^ d[112] ^ d[116] ^ d[120] ^ d[123] ^ d[124] ^ d[127]; + crc_128[3] = d[0] ^ d[4] ^ d[7] ^ d[9] ^ d[10] ^ d[15] ^ d[16] ^ d[18] ^ d[19] ^ d[20] ^ d[22] ^ d[23] ^ d[24] ^ d[26] ^ d[28] ^ d[30] ^ d[34] ^ d[36] ^ d[37] ^ d[38] ^ d[39] ^ d[40] ^ d[41] ^ d[42] ^ d[44] ^ d[45] ^ d[46] ^ d[48] ^ d[49] ^ d[51] ^ d[52] ^ d[53] ^ d[54] ^ d[59] ^ d[60] ^ d[61] ^ d[64] ^ d[65] ^ d[66] ^ d[67] ^ d[69] ^ d[70] ^ d[71] ^ d[73] ^ d[75] ^ d[79] ^ d[81] ^ d[82] ^ d[83] ^ d[86] ^ d[87] ^ d[91] ^ d[92] ^ d[102] ^ d[104] ^ d[106] ^ d[107] ^ d[111] ^ d[112] ^ d[114] ^ d[117] ^ d[119] ^ d[120] ^ d[123]; + crc_128[4] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[5] ^ d[6] ^ d[7] ^ d[9] ^ d[11] ^ d[13] ^ d[16] ^ d[17] ^ d[18] ^ d[20] ^ d[21] ^ d[26] ^ d[27] ^ d[28] ^ d[31] ^ d[32] ^ d[36] ^ d[37] ^ d[39] ^ d[40] ^ d[41] ^ d[43] ^ d[45] ^ d[47] ^ d[49] ^ d[50] ^ d[51] ^ d[53] ^ d[56] ^ d[64] ^ d[65] ^ d[66] ^ d[67] ^ d[68] ^ d[69] ^ d[71] ^ d[72] ^ d[74] ^ d[75] ^ d[76] ^ d[77] ^ d[78] ^ d[80] ^ d[86] ^ d[87] ^ d[89] ^ d[90] ^ d[91] ^ d[93] ^ d[95] ^ d[97] ^ d[98] ^ d[99] ^ d[103] ^ d[104] ^ d[105] ^ d[107] ^ d[108] ^ d[111] ^ d[114] ^ d[115] ^ d[118] ^ d[119] ^ d[123] ^ d[125]; + crc_128[5] = d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[6] ^ d[7] ^ d[8] ^ d[10] ^ d[12] ^ d[14] ^ d[17] ^ d[18] ^ d[19] ^ d[21] ^ d[22] ^ d[27] ^ d[28] ^ d[29] ^ d[32] ^ d[33] ^ d[37] ^ d[38] ^ d[40] ^ d[41] ^ d[42] ^ d[44] ^ d[46] ^ d[48] ^ d[50] ^ d[51] ^ d[52] ^ d[54] ^ d[57] ^ d[65] ^ d[66] ^ d[67] ^ d[68] ^ d[69] ^ d[70] ^ d[72] ^ d[73] ^ d[75] ^ d[76] ^ d[77] ^ d[78] ^ d[79] ^ d[81] ^ d[87] ^ d[88] ^ d[90] ^ d[91] ^ d[92] ^ d[94] ^ d[96] ^ d[98] ^ d[99] ^ d[100] ^ d[104] ^ d[105] ^ d[106] ^ d[108] ^ d[109] ^ d[112] ^ d[115] ^ d[116] ^ d[119] ^ d[120] ^ d[124] ^ d[126]; + crc_128[6] = d[0] ^ d[4] ^ d[5] ^ d[6] ^ d[10] ^ d[11] ^ d[15] ^ d[20] ^ d[22] ^ d[24] ^ d[25] ^ d[26] ^ d[30] ^ d[32] ^ d[33] ^ d[34] ^ d[35] ^ d[36] ^ d[39] ^ d[41] ^ d[43] ^ d[45] ^ d[46] ^ d[47] ^ d[49] ^ d[53] ^ d[54] ^ d[56] ^ d[58] ^ d[60] ^ d[61] ^ d[62] ^ d[64] ^ d[66] ^ d[67] ^ d[68] ^ d[71] ^ d[73] ^ d[74] ^ d[75] ^ d[76] ^ d[79] ^ d[80] ^ d[83] ^ d[84] ^ d[86] ^ d[90] ^ d[93] ^ d[98] ^ d[100] ^ d[101] ^ d[104] ^ d[105] ^ d[106] ^ d[107] ^ d[109] ^ d[110] ^ d[111] ^ d[112] ^ d[114] ^ d[116] ^ d[117] ^ d[119] ^ d[123] ^ d[124] ^ d[127]; + crc_128[7] = d[1] ^ d[5] ^ d[6] ^ d[7] ^ d[11] ^ d[12] ^ d[16] ^ d[21] ^ d[23] ^ d[25] ^ d[26] ^ d[27] ^ d[31] ^ d[33] ^ d[34] ^ d[35] ^ d[36] ^ d[37] ^ d[40] ^ d[42] ^ d[44] ^ d[46] ^ d[47] ^ d[48] ^ d[50] ^ d[54] ^ d[55] ^ d[57] ^ d[59] ^ d[61] ^ d[62] ^ d[63] ^ d[65] ^ d[67] ^ d[68] ^ d[69] ^ d[72] ^ d[74] ^ d[75] ^ d[76] ^ d[77] ^ d[80] ^ d[81] ^ d[84] ^ d[85] ^ d[87] ^ d[91] ^ d[94] ^ d[99] ^ d[101] ^ d[102] ^ d[105] ^ d[106] ^ d[107] ^ d[108] ^ d[110] ^ d[111] ^ d[112] ^ d[113] ^ d[115] ^ d[117] ^ d[118] ^ d[120] ^ d[124] ^ d[125]; + crc_128[8] = d[0] ^ d[3] ^ d[9] ^ d[10] ^ d[12] ^ d[17] ^ d[18] ^ d[19] ^ d[22] ^ d[23] ^ d[25] ^ d[27] ^ d[29] ^ d[34] ^ d[37] ^ d[41] ^ d[42] ^ d[43] ^ d[45] ^ d[46] ^ d[47] ^ d[48] ^ d[49] ^ d[52] ^ d[54] ^ d[58] ^ d[61] ^ d[63] ^ d[66] ^ d[68] ^ d[73] ^ d[76] ^ d[81] ^ d[83] ^ d[84] ^ d[85] ^ d[89] ^ d[90] ^ d[91] ^ d[97] ^ d[98] ^ d[99] ^ d[100] ^ d[102] ^ d[103] ^ d[104] ^ d[106] ^ d[107] ^ d[108] ^ d[109] ^ d[116] ^ d[118] ^ d[120] ^ d[123] ^ d[124] ^ d[126]; + crc_128[9] = d[1] ^ d[4] ^ d[10] ^ d[11] ^ d[13] ^ d[18] ^ d[19] ^ d[20] ^ d[23] ^ d[24] ^ d[26] ^ d[28] ^ d[30] ^ d[35] ^ d[38] ^ d[42] ^ d[43] ^ d[44] ^ d[46] ^ d[47] ^ d[48] ^ d[49] ^ d[50] ^ d[53] ^ d[55] ^ d[59] ^ d[62] ^ d[64] ^ d[67] ^ d[69] ^ d[74] ^ d[77] ^ d[82] ^ d[84] ^ d[85] ^ d[86] ^ d[90] ^ d[91] ^ d[92] ^ d[98] ^ d[99] ^ d[100] ^ d[101] ^ d[103] ^ d[104] ^ d[105] ^ d[107] ^ d[108] ^ d[109] ^ d[110] ^ d[117] ^ d[119] ^ d[121] ^ d[124] ^ d[125] ^ d[127]; + crc_128[10] = d[0] ^ d[3] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[18] ^ d[20] ^ d[21] ^ d[23] ^ d[26] ^ d[27] ^ d[28] ^ d[31] ^ d[32] ^ d[35] ^ d[38] ^ d[39] ^ d[42] ^ d[43] ^ d[44] ^ d[45] ^ d[46] ^ d[47] ^ d[48] ^ d[49] ^ d[50] ^ d[52] ^ d[55] ^ d[61] ^ d[62] ^ d[63] ^ d[64] ^ d[65] ^ d[68] ^ d[69] ^ d[77] ^ d[82] ^ d[84] ^ d[85] ^ d[87] ^ d[88] ^ d[89] ^ d[90] ^ d[93] ^ d[95] ^ d[97] ^ d[98] ^ d[100] ^ d[101] ^ d[102] ^ d[105] ^ d[106] ^ d[108] ^ d[109] ^ d[110] ^ d[112] ^ d[113] ^ d[114] ^ d[118] ^ d[119] ^ d[121] ^ d[122] ^ d[123] ^ d[124] ^ d[126]; + crc_128[11] = d[1] ^ d[4] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[19] ^ d[21] ^ d[22] ^ d[24] ^ d[27] ^ d[28] ^ d[29] ^ d[32] ^ d[33] ^ d[36] ^ d[39] ^ d[40] ^ d[43] ^ d[44] ^ d[45] ^ d[46] ^ d[47] ^ d[48] ^ d[49] ^ d[50] ^ d[51] ^ d[53] ^ d[56] ^ d[62] ^ d[63] ^ d[64] ^ d[65] ^ d[66] ^ d[69] ^ d[70] ^ d[78] ^ d[83] ^ d[85] ^ d[86] ^ d[88] ^ d[89] ^ d[90] ^ d[91] ^ d[94] ^ d[96] ^ d[98] ^ d[99] ^ d[101] ^ d[102] ^ d[103] ^ d[106] ^ d[107] ^ d[109] ^ d[110] ^ d[111] ^ d[113] ^ d[114] ^ d[115] ^ d[119] ^ d[120] ^ d[122] ^ d[123] ^ d[124] ^ d[125] ^ d[127]; + crc_128[12] = d[0] ^ d[3] ^ d[5] ^ d[6] ^ d[11] ^ d[12] ^ d[14] ^ d[15] ^ d[16] ^ d[18] ^ d[19] ^ d[20] ^ d[22] ^ d[24] ^ d[26] ^ d[30] ^ d[32] ^ d[33] ^ d[34] ^ d[35] ^ d[36] ^ d[37] ^ d[38] ^ d[40] ^ d[41] ^ d[42] ^ d[44] ^ d[45] ^ d[47] ^ d[48] ^ d[49] ^ d[50] ^ d[55] ^ d[56] ^ d[57] ^ d[60] ^ d[61] ^ d[62] ^ d[63] ^ d[65] ^ d[66] ^ d[67] ^ d[69] ^ d[71] ^ d[75] ^ d[77] ^ d[78] ^ d[79] ^ d[82] ^ d[83] ^ d[87] ^ d[88] ^ d[98] ^ d[100] ^ d[102] ^ d[103] ^ d[107] ^ d[108] ^ d[110] ^ d[113] ^ d[115] ^ d[116] ^ d[119] ^ d[126]; + crc_128[13] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[8] ^ d[9] ^ d[10] ^ d[12] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^ d[20] ^ d[21] ^ d[24] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[31] ^ d[32] ^ d[33] ^ d[34] ^ d[37] ^ d[39] ^ d[41] ^ d[43] ^ d[45] ^ d[48] ^ d[49] ^ d[50] ^ d[52] ^ d[54] ^ d[55] ^ d[57] ^ d[58] ^ d[60] ^ d[63] ^ d[66] ^ d[67] ^ d[68] ^ d[69] ^ d[72] ^ d[75] ^ d[76] ^ d[77] ^ d[79] ^ d[80] ^ d[82] ^ d[86] ^ d[90] ^ d[91] ^ d[92] ^ d[95] ^ d[97] ^ d[98] ^ d[101] ^ d[103] ^ d[108] ^ d[109] ^ d[112] ^ d[113] ^ d[116] ^ d[117] ^ d[119] ^ d[121] ^ d[123] ^ d[124] ^ d[125] ^ d[127]; + crc_128[14] = d[0] ^ d[1] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[11] ^ d[16] ^ d[17] ^ d[21] ^ d[22] ^ d[23] ^ d[24] ^ d[26] ^ d[27] ^ d[30] ^ d[33] ^ d[34] ^ d[36] ^ d[40] ^ d[44] ^ d[49] ^ d[50] ^ d[52] ^ d[53] ^ d[54] ^ d[58] ^ d[59] ^ d[60] ^ d[62] ^ d[67] ^ d[68] ^ d[73] ^ d[75] ^ d[76] ^ d[80] ^ d[81] ^ d[82] ^ d[84] ^ d[86] ^ d[87] ^ d[88] ^ d[89] ^ d[90] ^ d[93] ^ d[95] ^ d[96] ^ d[97] ^ d[102] ^ d[109] ^ d[110] ^ d[111] ^ d[112] ^ d[117] ^ d[118] ^ d[119] ^ d[121] ^ d[122] ^ d[123] ^ d[126]; + crc_128[15] = d[1] ^ d[2] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[12] ^ d[17] ^ d[18] ^ d[22] ^ d[23] ^ d[24] ^ d[25] ^ d[27] ^ d[28] ^ d[31] ^ d[34] ^ d[35] ^ d[37] ^ d[41] ^ d[45] ^ d[50] ^ d[51] ^ d[53] ^ d[54] ^ d[55] ^ d[59] ^ d[60] ^ d[61] ^ d[63] ^ d[68] ^ d[69] ^ d[74] ^ d[76] ^ d[77] ^ d[81] ^ d[82] ^ d[83] ^ d[85] ^ d[87] ^ d[88] ^ d[89] ^ d[90] ^ d[91] ^ d[94] ^ d[96] ^ d[97] ^ d[98] ^ d[103] ^ d[110] ^ d[111] ^ d[112] ^ d[113] ^ d[118] ^ d[119] ^ d[120] ^ d[122] ^ d[123] ^ d[124] ^ d[127]; + end + endfunction + + function [15:0] crc_256; + input [255:0] d; + begin + crc_256[0] = d[0] ^ d[2] ^ d[3] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[13] ^ d[18] ^ d[19] ^ d[23] ^ d[24] ^ d[25] ^ d[26] ^ d[28] ^ d[29] ^ d[32] ^ d[35] ^ d[36] ^ d[38] ^ d[42] ^ d[46] ^ d[51] ^ d[52] ^ d[54] ^ d[55] ^ d[56] ^ d[60] ^ d[61] ^ d[62] ^ d[64] ^ d[69] ^ d[70] ^ d[75] ^ d[77] ^ d[78] ^ d[82] ^ d[83] ^ d[84] ^ d[86] ^ d[88] ^ d[89] ^ d[90] ^ d[91] ^ d[92] ^ d[95] ^ d[97] ^ d[98] ^ d[99] ^ d[104] ^ d[111] ^ d[112] ^ d[113] ^ d[114] ^ d[119] ^ d[120] ^ d[121] ^ d[123] ^ d[124] ^ d[125] ^ d[128] ^ d[131] ^ d[133] ^ d[134] ^ d[136] ^ d[138] ^ d[139] ^ d[144] ^ d[150] ^ d[151] ^ d[153] ^ d[154] ^ d[155] ^ d[157] ^ d[158] ^ d[159] ^ d[160] ^ d[162] ^ d[163] ^ d[164] ^ d[165] ^ d[166] ^ d[169] ^ d[172] ^ d[175] ^ d[176] ^ d[177] ^ d[178] ^ d[179] ^ d[181] ^ d[184] ^ d[186] ^ d[189] ^ d[190] ^ d[192] ^ d[193] ^ d[194] ^ d[196] ^ d[197] ^ d[198] ^ d[200] ^ d[201] ^ d[203] ^ d[204] ^ d[205] ^ d[207] ^ d[208] ^ d[210] ^ d[211] ^ d[213] ^ d[216] ^ d[218] ^ d[220] ^ d[221] ^ d[222] ^ d[223] ^ d[224] ^ d[225] ^ d[226] ^ d[227] ^ d[229] ^ d[231] ^ d[235] ^ d[236] ^ d[241] ^ d[245] ^ d[248] ^ d[249] ^ d[252] ^ d[253] ^ d[254]; + crc_256[1] = d[0] ^ d[1] ^ d[2] ^ d[4] ^ d[6] ^ d[11] ^ d[13] ^ d[14] ^ d[18] ^ d[20] ^ d[23] ^ d[27] ^ d[28] ^ d[30] ^ d[32] ^ d[33] ^ d[35] ^ d[37] ^ d[38] ^ d[39] ^ d[42] ^ d[43] ^ d[46] ^ d[47] ^ d[51] ^ d[53] ^ d[54] ^ d[57] ^ d[60] ^ d[63] ^ d[64] ^ d[65] ^ d[69] ^ d[71] ^ d[75] ^ d[76] ^ d[77] ^ d[79] ^ d[82] ^ d[85] ^ d[86] ^ d[87] ^ d[88] ^ d[93] ^ d[95] ^ d[96] ^ d[97] ^ d[100] ^ d[104] ^ d[105] ^ d[111] ^ d[115] ^ d[119] ^ d[122] ^ d[123] ^ d[126] ^ d[128] ^ d[129] ^ d[131] ^ d[132] ^ d[133] ^ d[135] ^ d[136] ^ d[137] ^ d[138] ^ d[140] ^ d[144] ^ d[145] ^ d[150] ^ d[152] ^ d[153] ^ d[156] ^ d[157] ^ d[161] ^ d[162] ^ d[167] ^ d[169] ^ d[170] ^ d[172] ^ d[173] ^ d[175] ^ d[180] ^ d[181] ^ d[182] ^ d[184] ^ d[185] ^ d[186] ^ d[187] ^ d[189] ^ d[191] ^ d[192] ^ d[195] ^ d[196] ^ d[199] ^ d[200] ^ d[202] ^ d[203] ^ d[206] ^ d[207] ^ d[209] ^ d[210] ^ d[212] ^ d[213] ^ d[214] ^ d[216] ^ d[217] ^ d[218] ^ d[219] ^ d[220] ^ d[228] ^ d[229] ^ d[230] ^ d[231] ^ d[232] ^ d[235] ^ d[237] ^ d[241] ^ d[242] ^ d[245] ^ d[246] ^ d[248] ^ d[250] ^ d[252] ^ d[255]; + crc_256[2] = d[1] ^ d[2] ^ d[3] ^ d[5] ^ d[7] ^ d[12] ^ d[14] ^ d[15] ^ d[19] ^ d[21] ^ d[24] ^ d[28] ^ d[29] ^ d[31] ^ d[33] ^ d[34] ^ d[36] ^ d[38] ^ d[39] ^ d[40] ^ d[43] ^ d[44] ^ d[47] ^ d[48] ^ d[52] ^ d[54] ^ d[55] ^ d[58] ^ d[61] ^ d[64] ^ d[65] ^ d[66] ^ d[70] ^ d[72] ^ d[76] ^ d[77] ^ d[78] ^ d[80] ^ d[83] ^ d[86] ^ d[87] ^ d[88] ^ d[89] ^ d[94] ^ d[96] ^ d[97] ^ d[98] ^ d[101] ^ d[105] ^ d[106] ^ d[112] ^ d[116] ^ d[120] ^ d[123] ^ d[124] ^ d[127] ^ d[129] ^ d[130] ^ d[132] ^ d[133] ^ d[134] ^ d[136] ^ d[137] ^ d[138] ^ d[139] ^ d[141] ^ d[145] ^ d[146] ^ d[151] ^ d[153] ^ d[154] ^ d[157] ^ d[158] ^ d[162] ^ d[163] ^ d[168] ^ d[170] ^ d[171] ^ d[173] ^ d[174] ^ d[176] ^ d[181] ^ d[182] ^ d[183] ^ d[185] ^ d[186] ^ d[187] ^ d[188] ^ d[190] ^ d[192] ^ d[193] ^ d[196] ^ d[197] ^ d[200] ^ d[201] ^ d[203] ^ d[204] ^ d[207] ^ d[208] ^ d[210] ^ d[211] ^ d[213] ^ d[214] ^ d[215] ^ d[217] ^ d[218] ^ d[219] ^ d[220] ^ d[221] ^ d[229] ^ d[230] ^ d[231] ^ d[232] ^ d[233] ^ d[236] ^ d[238] ^ d[242] ^ d[243] ^ d[246] ^ d[247] ^ d[249] ^ d[251] ^ d[253]; + crc_256[3] = d[0] ^ d[4] ^ d[7] ^ d[9] ^ d[10] ^ d[15] ^ d[16] ^ d[18] ^ d[19] ^ d[20] ^ d[22] ^ d[23] ^ d[24] ^ d[26] ^ d[28] ^ d[30] ^ d[34] ^ d[36] ^ d[37] ^ d[38] ^ d[39] ^ d[40] ^ d[41] ^ d[42] ^ d[44] ^ d[45] ^ d[46] ^ d[48] ^ d[49] ^ d[51] ^ d[52] ^ d[53] ^ d[54] ^ d[59] ^ d[60] ^ d[61] ^ d[64] ^ d[65] ^ d[66] ^ d[67] ^ d[69] ^ d[70] ^ d[71] ^ d[73] ^ d[75] ^ d[79] ^ d[81] ^ d[82] ^ d[83] ^ d[86] ^ d[87] ^ d[91] ^ d[92] ^ d[102] ^ d[104] ^ d[106] ^ d[107] ^ d[111] ^ d[112] ^ d[114] ^ d[117] ^ d[119] ^ d[120] ^ d[123] ^ d[130] ^ d[135] ^ d[136] ^ d[137] ^ d[140] ^ d[142] ^ d[144] ^ d[146] ^ d[147] ^ d[150] ^ d[151] ^ d[152] ^ d[153] ^ d[157] ^ d[160] ^ d[162] ^ d[165] ^ d[166] ^ d[171] ^ d[174] ^ d[176] ^ d[178] ^ d[179] ^ d[181] ^ d[182] ^ d[183] ^ d[187] ^ d[188] ^ d[190] ^ d[191] ^ d[192] ^ d[196] ^ d[200] ^ d[202] ^ d[203] ^ d[207] ^ d[209] ^ d[210] ^ d[212] ^ d[213] ^ d[214] ^ d[215] ^ d[219] ^ d[223] ^ d[224] ^ d[225] ^ d[226] ^ d[227] ^ d[229] ^ d[230] ^ d[232] ^ d[233] ^ d[234] ^ d[235] ^ d[236] ^ d[237] ^ d[239] ^ d[241] ^ d[243] ^ d[244] ^ d[245] ^ d[247] ^ d[249] ^ d[250] ^ d[253]; + crc_256[4] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[5] ^ d[6] ^ d[7] ^ d[9] ^ d[11] ^ d[13] ^ d[16] ^ d[17] ^ d[18] ^ d[20] ^ d[21] ^ d[26] ^ d[27] ^ d[28] ^ d[31] ^ d[32] ^ d[36] ^ d[37] ^ d[39] ^ d[40] ^ d[41] ^ d[43] ^ d[45] ^ d[47] ^ d[49] ^ d[50] ^ d[51] ^ d[53] ^ d[56] ^ d[64] ^ d[65] ^ d[66] ^ d[67] ^ d[68] ^ d[69] ^ d[71] ^ d[72] ^ d[74] ^ d[75] ^ d[76] ^ d[77] ^ d[78] ^ d[80] ^ d[86] ^ d[87] ^ d[89] ^ d[90] ^ d[91] ^ d[93] ^ d[95] ^ d[97] ^ d[98] ^ d[99] ^ d[103] ^ d[104] ^ d[105] ^ d[107] ^ d[108] ^ d[111] ^ d[114] ^ d[115] ^ d[118] ^ d[119] ^ d[123] ^ d[125] ^ d[128] ^ d[133] ^ d[134] ^ d[137] ^ d[139] ^ d[141] ^ d[143] ^ d[144] ^ d[145] ^ d[147] ^ d[148] ^ d[150] ^ d[152] ^ d[155] ^ d[157] ^ d[159] ^ d[160] ^ d[161] ^ d[162] ^ d[164] ^ d[165] ^ d[167] ^ d[169] ^ d[176] ^ d[178] ^ d[180] ^ d[181] ^ d[182] ^ d[183] ^ d[186] ^ d[188] ^ d[190] ^ d[191] ^ d[194] ^ d[196] ^ d[198] ^ d[200] ^ d[205] ^ d[207] ^ d[214] ^ d[215] ^ d[218] ^ d[221] ^ d[222] ^ d[223] ^ d[228] ^ d[229] ^ d[230] ^ d[233] ^ d[234] ^ d[237] ^ d[238] ^ d[240] ^ d[241] ^ d[242] ^ d[244] ^ d[246] ^ d[249] ^ d[250] ^ d[251] ^ d[252] ^ d[253]; + crc_256[5] = d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[6] ^ d[7] ^ d[8] ^ d[10] ^ d[12] ^ d[14] ^ d[17] ^ d[18] ^ d[19] ^ d[21] ^ d[22] ^ d[27] ^ d[28] ^ d[29] ^ d[32] ^ d[33] ^ d[37] ^ d[38] ^ d[40] ^ d[41] ^ d[42] ^ d[44] ^ d[46] ^ d[48] ^ d[50] ^ d[51] ^ d[52] ^ d[54] ^ d[57] ^ d[65] ^ d[66] ^ d[67] ^ d[68] ^ d[69] ^ d[70] ^ d[72] ^ d[73] ^ d[75] ^ d[76] ^ d[77] ^ d[78] ^ d[79] ^ d[81] ^ d[87] ^ d[88] ^ d[90] ^ d[91] ^ d[92] ^ d[94] ^ d[96] ^ d[98] ^ d[99] ^ d[100] ^ d[104] ^ d[105] ^ d[106] ^ d[108] ^ d[109] ^ d[112] ^ d[115] ^ d[116] ^ d[119] ^ d[120] ^ d[124] ^ d[126] ^ d[129] ^ d[134] ^ d[135] ^ d[138] ^ d[140] ^ d[142] ^ d[144] ^ d[145] ^ d[146] ^ d[148] ^ d[149] ^ d[151] ^ d[153] ^ d[156] ^ d[158] ^ d[160] ^ d[161] ^ d[162] ^ d[163] ^ d[165] ^ d[166] ^ d[168] ^ d[170] ^ d[177] ^ d[179] ^ d[181] ^ d[182] ^ d[183] ^ d[184] ^ d[187] ^ d[189] ^ d[191] ^ d[192] ^ d[195] ^ d[197] ^ d[199] ^ d[201] ^ d[206] ^ d[208] ^ d[215] ^ d[216] ^ d[219] ^ d[222] ^ d[223] ^ d[224] ^ d[229] ^ d[230] ^ d[231] ^ d[234] ^ d[235] ^ d[238] ^ d[239] ^ d[241] ^ d[242] ^ d[243] ^ d[245] ^ d[247] ^ d[250] ^ d[251] ^ d[252] ^ d[253] ^ d[254]; + crc_256[6] = d[0] ^ d[4] ^ d[5] ^ d[6] ^ d[10] ^ d[11] ^ d[15] ^ d[20] ^ d[22] ^ d[24] ^ d[25] ^ d[26] ^ d[30] ^ d[32] ^ d[33] ^ d[34] ^ d[35] ^ d[36] ^ d[39] ^ d[41] ^ d[43] ^ d[45] ^ d[46] ^ d[47] ^ d[49] ^ d[53] ^ d[54] ^ d[56] ^ d[58] ^ d[60] ^ d[61] ^ d[62] ^ d[64] ^ d[66] ^ d[67] ^ d[68] ^ d[71] ^ d[73] ^ d[74] ^ d[75] ^ d[76] ^ d[79] ^ d[80] ^ d[83] ^ d[84] ^ d[86] ^ d[90] ^ d[93] ^ d[98] ^ d[100] ^ d[101] ^ d[104] ^ d[105] ^ d[106] ^ d[107] ^ d[109] ^ d[110] ^ d[111] ^ d[112] ^ d[114] ^ d[116] ^ d[117] ^ d[119] ^ d[123] ^ d[124] ^ d[127] ^ d[128] ^ d[130] ^ d[131] ^ d[133] ^ d[134] ^ d[135] ^ d[138] ^ d[141] ^ d[143] ^ d[144] ^ d[145] ^ d[146] ^ d[147] ^ d[149] ^ d[151] ^ d[152] ^ d[153] ^ d[155] ^ d[158] ^ d[160] ^ d[161] ^ d[165] ^ d[167] ^ d[171] ^ d[172] ^ d[175] ^ d[176] ^ d[177] ^ d[179] ^ d[180] ^ d[181] ^ d[182] ^ d[183] ^ d[185] ^ d[186] ^ d[188] ^ d[189] ^ d[194] ^ d[197] ^ d[201] ^ d[202] ^ d[203] ^ d[204] ^ d[205] ^ d[208] ^ d[209] ^ d[210] ^ d[211] ^ d[213] ^ d[217] ^ d[218] ^ d[221] ^ d[222] ^ d[226] ^ d[227] ^ d[229] ^ d[230] ^ d[232] ^ d[239] ^ d[240] ^ d[241] ^ d[242] ^ d[243] ^ d[244] ^ d[245] ^ d[246] ^ d[249] ^ d[251] ^ d[255]; + crc_256[7] = d[1] ^ d[5] ^ d[6] ^ d[7] ^ d[11] ^ d[12] ^ d[16] ^ d[21] ^ d[23] ^ d[25] ^ d[26] ^ d[27] ^ d[31] ^ d[33] ^ d[34] ^ d[35] ^ d[36] ^ d[37] ^ d[40] ^ d[42] ^ d[44] ^ d[46] ^ d[47] ^ d[48] ^ d[50] ^ d[54] ^ d[55] ^ d[57] ^ d[59] ^ d[61] ^ d[62] ^ d[63] ^ d[65] ^ d[67] ^ d[68] ^ d[69] ^ d[72] ^ d[74] ^ d[75] ^ d[76] ^ d[77] ^ d[80] ^ d[81] ^ d[84] ^ d[85] ^ d[87] ^ d[91] ^ d[94] ^ d[99] ^ d[101] ^ d[102] ^ d[105] ^ d[106] ^ d[107] ^ d[108] ^ d[110] ^ d[111] ^ d[112] ^ d[113] ^ d[115] ^ d[117] ^ d[118] ^ d[120] ^ d[124] ^ d[125] ^ d[128] ^ d[129] ^ d[131] ^ d[132] ^ d[134] ^ d[135] ^ d[136] ^ d[139] ^ d[142] ^ d[144] ^ d[145] ^ d[146] ^ d[147] ^ d[148] ^ d[150] ^ d[152] ^ d[153] ^ d[154] ^ d[156] ^ d[159] ^ d[161] ^ d[162] ^ d[166] ^ d[168] ^ d[172] ^ d[173] ^ d[176] ^ d[177] ^ d[178] ^ d[180] ^ d[181] ^ d[182] ^ d[183] ^ d[184] ^ d[186] ^ d[187] ^ d[189] ^ d[190] ^ d[195] ^ d[198] ^ d[202] ^ d[203] ^ d[204] ^ d[205] ^ d[206] ^ d[209] ^ d[210] ^ d[211] ^ d[212] ^ d[214] ^ d[218] ^ d[219] ^ d[222] ^ d[223] ^ d[227] ^ d[228] ^ d[230] ^ d[231] ^ d[233] ^ d[240] ^ d[241] ^ d[242] ^ d[243] ^ d[244] ^ d[245] ^ d[246] ^ d[247] ^ d[250] ^ d[252]; + crc_256[8] = d[0] ^ d[3] ^ d[9] ^ d[10] ^ d[12] ^ d[17] ^ d[18] ^ d[19] ^ d[22] ^ d[23] ^ d[25] ^ d[27] ^ d[29] ^ d[34] ^ d[37] ^ d[41] ^ d[42] ^ d[43] ^ d[45] ^ d[46] ^ d[47] ^ d[48] ^ d[49] ^ d[52] ^ d[54] ^ d[58] ^ d[61] ^ d[63] ^ d[66] ^ d[68] ^ d[73] ^ d[76] ^ d[81] ^ d[83] ^ d[84] ^ d[85] ^ d[89] ^ d[90] ^ d[91] ^ d[97] ^ d[98] ^ d[99] ^ d[100] ^ d[102] ^ d[103] ^ d[104] ^ d[106] ^ d[107] ^ d[108] ^ d[109] ^ d[116] ^ d[118] ^ d[120] ^ d[123] ^ d[124] ^ d[126] ^ d[128] ^ d[129] ^ d[130] ^ d[131] ^ d[132] ^ d[134] ^ d[135] ^ d[137] ^ d[138] ^ d[139] ^ d[140] ^ d[143] ^ d[144] ^ d[145] ^ d[146] ^ d[147] ^ d[148] ^ d[149] ^ d[150] ^ d[158] ^ d[159] ^ d[164] ^ d[165] ^ d[166] ^ d[167] ^ d[172] ^ d[173] ^ d[174] ^ d[175] ^ d[176] ^ d[182] ^ d[183] ^ d[185] ^ d[186] ^ d[187] ^ d[188] ^ d[189] ^ d[191] ^ d[192] ^ d[193] ^ d[194] ^ d[197] ^ d[198] ^ d[199] ^ d[200] ^ d[201] ^ d[206] ^ d[208] ^ d[212] ^ d[215] ^ d[216] ^ d[218] ^ d[219] ^ d[221] ^ d[222] ^ d[225] ^ d[226] ^ d[227] ^ d[228] ^ d[232] ^ d[234] ^ d[235] ^ d[236] ^ d[242] ^ d[243] ^ d[244] ^ d[246] ^ d[247] ^ d[249] ^ d[251] ^ d[252] ^ d[254]; + crc_256[9] = d[1] ^ d[4] ^ d[10] ^ d[11] ^ d[13] ^ d[18] ^ d[19] ^ d[20] ^ d[23] ^ d[24] ^ d[26] ^ d[28] ^ d[30] ^ d[35] ^ d[38] ^ d[42] ^ d[43] ^ d[44] ^ d[46] ^ d[47] ^ d[48] ^ d[49] ^ d[50] ^ d[53] ^ d[55] ^ d[59] ^ d[62] ^ d[64] ^ d[67] ^ d[69] ^ d[74] ^ d[77] ^ d[82] ^ d[84] ^ d[85] ^ d[86] ^ d[90] ^ d[91] ^ d[92] ^ d[98] ^ d[99] ^ d[100] ^ d[101] ^ d[103] ^ d[104] ^ d[105] ^ d[107] ^ d[108] ^ d[109] ^ d[110] ^ d[117] ^ d[119] ^ d[121] ^ d[124] ^ d[125] ^ d[127] ^ d[129] ^ d[130] ^ d[131] ^ d[132] ^ d[133] ^ d[135] ^ d[136] ^ d[138] ^ d[139] ^ d[140] ^ d[141] ^ d[144] ^ d[145] ^ d[146] ^ d[147] ^ d[148] ^ d[149] ^ d[150] ^ d[151] ^ d[159] ^ d[160] ^ d[165] ^ d[166] ^ d[167] ^ d[168] ^ d[173] ^ d[174] ^ d[175] ^ d[176] ^ d[177] ^ d[183] ^ d[184] ^ d[186] ^ d[187] ^ d[188] ^ d[189] ^ d[190] ^ d[192] ^ d[193] ^ d[194] ^ d[195] ^ d[198] ^ d[199] ^ d[200] ^ d[201] ^ d[202] ^ d[207] ^ d[209] ^ d[213] ^ d[216] ^ d[217] ^ d[219] ^ d[220] ^ d[222] ^ d[223] ^ d[226] ^ d[227] ^ d[228] ^ d[229] ^ d[233] ^ d[235] ^ d[236] ^ d[237] ^ d[243] ^ d[244] ^ d[245] ^ d[247] ^ d[248] ^ d[250] ^ d[252] ^ d[253] ^ d[255]; + crc_256[10] = d[0] ^ d[3] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[18] ^ d[20] ^ d[21] ^ d[23] ^ d[26] ^ d[27] ^ d[28] ^ d[31] ^ d[32] ^ d[35] ^ d[38] ^ d[39] ^ d[42] ^ d[43] ^ d[44] ^ d[45] ^ d[46] ^ d[47] ^ d[48] ^ d[49] ^ d[50] ^ d[52] ^ d[55] ^ d[61] ^ d[62] ^ d[63] ^ d[64] ^ d[65] ^ d[68] ^ d[69] ^ d[77] ^ d[82] ^ d[84] ^ d[85] ^ d[87] ^ d[88] ^ d[89] ^ d[90] ^ d[93] ^ d[95] ^ d[97] ^ d[98] ^ d[100] ^ d[101] ^ d[102] ^ d[105] ^ d[106] ^ d[108] ^ d[109] ^ d[110] ^ d[112] ^ d[113] ^ d[114] ^ d[118] ^ d[119] ^ d[121] ^ d[122] ^ d[123] ^ d[124] ^ d[126] ^ d[130] ^ d[132] ^ d[137] ^ d[138] ^ d[140] ^ d[141] ^ d[142] ^ d[144] ^ d[145] ^ d[146] ^ d[147] ^ d[148] ^ d[149] ^ d[152] ^ d[153] ^ d[154] ^ d[155] ^ d[157] ^ d[158] ^ d[159] ^ d[161] ^ d[162] ^ d[163] ^ d[164] ^ d[165] ^ d[167] ^ d[168] ^ d[172] ^ d[174] ^ d[179] ^ d[181] ^ d[185] ^ d[186] ^ d[187] ^ d[188] ^ d[191] ^ d[192] ^ d[195] ^ d[197] ^ d[198] ^ d[199] ^ d[202] ^ d[204] ^ d[205] ^ d[207] ^ d[211] ^ d[213] ^ d[214] ^ d[216] ^ d[217] ^ d[222] ^ d[225] ^ d[226] ^ d[228] ^ d[230] ^ d[231] ^ d[234] ^ d[235] ^ d[237] ^ d[238] ^ d[241] ^ d[244] ^ d[246] ^ d[251] ^ d[252]; + crc_256[11] = d[1] ^ d[4] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[19] ^ d[21] ^ d[22] ^ d[24] ^ d[27] ^ d[28] ^ d[29] ^ d[32] ^ d[33] ^ d[36] ^ d[39] ^ d[40] ^ d[43] ^ d[44] ^ d[45] ^ d[46] ^ d[47] ^ d[48] ^ d[49] ^ d[50] ^ d[51] ^ d[53] ^ d[56] ^ d[62] ^ d[63] ^ d[64] ^ d[65] ^ d[66] ^ d[69] ^ d[70] ^ d[78] ^ d[83] ^ d[85] ^ d[86] ^ d[88] ^ d[89] ^ d[90] ^ d[91] ^ d[94] ^ d[96] ^ d[98] ^ d[99] ^ d[101] ^ d[102] ^ d[103] ^ d[106] ^ d[107] ^ d[109] ^ d[110] ^ d[111] ^ d[113] ^ d[114] ^ d[115] ^ d[119] ^ d[120] ^ d[122] ^ d[123] ^ d[124] ^ d[125] ^ d[127] ^ d[131] ^ d[133] ^ d[138] ^ d[139] ^ d[141] ^ d[142] ^ d[143] ^ d[145] ^ d[146] ^ d[147] ^ d[148] ^ d[149] ^ d[150] ^ d[153] ^ d[154] ^ d[155] ^ d[156] ^ d[158] ^ d[159] ^ d[160] ^ d[162] ^ d[163] ^ d[164] ^ d[165] ^ d[166] ^ d[168] ^ d[169] ^ d[173] ^ d[175] ^ d[180] ^ d[182] ^ d[186] ^ d[187] ^ d[188] ^ d[189] ^ d[192] ^ d[193] ^ d[196] ^ d[198] ^ d[199] ^ d[200] ^ d[203] ^ d[205] ^ d[206] ^ d[208] ^ d[212] ^ d[214] ^ d[215] ^ d[217] ^ d[218] ^ d[223] ^ d[226] ^ d[227] ^ d[229] ^ d[231] ^ d[232] ^ d[235] ^ d[236] ^ d[238] ^ d[239] ^ d[242] ^ d[245] ^ d[247] ^ d[252] ^ d[253]; + crc_256[12] = d[0] ^ d[3] ^ d[5] ^ d[6] ^ d[11] ^ d[12] ^ d[14] ^ d[15] ^ d[16] ^ d[18] ^ d[19] ^ d[20] ^ d[22] ^ d[24] ^ d[26] ^ d[30] ^ d[32] ^ d[33] ^ d[34] ^ d[35] ^ d[36] ^ d[37] ^ d[38] ^ d[40] ^ d[41] ^ d[42] ^ d[44] ^ d[45] ^ d[47] ^ d[48] ^ d[49] ^ d[50] ^ d[55] ^ d[56] ^ d[57] ^ d[60] ^ d[61] ^ d[62] ^ d[63] ^ d[65] ^ d[66] ^ d[67] ^ d[69] ^ d[71] ^ d[75] ^ d[77] ^ d[78] ^ d[79] ^ d[82] ^ d[83] ^ d[87] ^ d[88] ^ d[98] ^ d[100] ^ d[102] ^ d[103] ^ d[107] ^ d[108] ^ d[110] ^ d[113] ^ d[115] ^ d[116] ^ d[119] ^ d[126] ^ d[131] ^ d[132] ^ d[133] ^ d[136] ^ d[138] ^ d[140] ^ d[142] ^ d[143] ^ d[146] ^ d[147] ^ d[148] ^ d[149] ^ d[153] ^ d[156] ^ d[158] ^ d[161] ^ d[162] ^ d[167] ^ d[170] ^ d[172] ^ d[174] ^ d[175] ^ d[177] ^ d[178] ^ d[179] ^ d[183] ^ d[184] ^ d[186] ^ d[187] ^ d[188] ^ d[192] ^ d[196] ^ d[198] ^ d[199] ^ d[203] ^ d[205] ^ d[206] ^ d[208] ^ d[209] ^ d[210] ^ d[211] ^ d[215] ^ d[219] ^ d[220] ^ d[221] ^ d[222] ^ d[223] ^ d[225] ^ d[226] ^ d[228] ^ d[229] ^ d[230] ^ d[231] ^ d[232] ^ d[233] ^ d[235] ^ d[237] ^ d[239] ^ d[240] ^ d[241] ^ d[243] ^ d[245] ^ d[246] ^ d[249] ^ d[252]; + crc_256[13] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[8] ^ d[9] ^ d[10] ^ d[12] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^ d[20] ^ d[21] ^ d[24] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[31] ^ d[32] ^ d[33] ^ d[34] ^ d[37] ^ d[39] ^ d[41] ^ d[43] ^ d[45] ^ d[48] ^ d[49] ^ d[50] ^ d[52] ^ d[54] ^ d[55] ^ d[57] ^ d[58] ^ d[60] ^ d[63] ^ d[66] ^ d[67] ^ d[68] ^ d[69] ^ d[72] ^ d[75] ^ d[76] ^ d[77] ^ d[79] ^ d[80] ^ d[82] ^ d[86] ^ d[90] ^ d[91] ^ d[92] ^ d[95] ^ d[97] ^ d[98] ^ d[101] ^ d[103] ^ d[108] ^ d[109] ^ d[112] ^ d[113] ^ d[116] ^ d[117] ^ d[119] ^ d[121] ^ d[123] ^ d[124] ^ d[125] ^ d[127] ^ d[128] ^ d[131] ^ d[132] ^ d[136] ^ d[137] ^ d[138] ^ d[141] ^ d[143] ^ d[147] ^ d[148] ^ d[149] ^ d[151] ^ d[153] ^ d[155] ^ d[158] ^ d[160] ^ d[164] ^ d[165] ^ d[166] ^ d[168] ^ d[169] ^ d[171] ^ d[172] ^ d[173] ^ d[177] ^ d[180] ^ d[181] ^ d[185] ^ d[186] ^ d[187] ^ d[188] ^ d[190] ^ d[192] ^ d[194] ^ d[196] ^ d[198] ^ d[199] ^ d[201] ^ d[203] ^ d[205] ^ d[206] ^ d[208] ^ d[209] ^ d[212] ^ d[213] ^ d[218] ^ d[225] ^ d[230] ^ d[232] ^ d[233] ^ d[234] ^ d[235] ^ d[238] ^ d[240] ^ d[242] ^ d[244] ^ d[245] ^ d[246] ^ d[247] ^ d[248] ^ d[249] ^ d[250] ^ d[252] ^ d[254]; + crc_256[14] = d[0] ^ d[1] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[11] ^ d[16] ^ d[17] ^ d[21] ^ d[22] ^ d[23] ^ d[24] ^ d[26] ^ d[27] ^ d[30] ^ d[33] ^ d[34] ^ d[36] ^ d[40] ^ d[44] ^ d[49] ^ d[50] ^ d[52] ^ d[53] ^ d[54] ^ d[58] ^ d[59] ^ d[60] ^ d[62] ^ d[67] ^ d[68] ^ d[73] ^ d[75] ^ d[76] ^ d[80] ^ d[81] ^ d[82] ^ d[84] ^ d[86] ^ d[87] ^ d[88] ^ d[89] ^ d[90] ^ d[93] ^ d[95] ^ d[96] ^ d[97] ^ d[102] ^ d[109] ^ d[110] ^ d[111] ^ d[112] ^ d[117] ^ d[118] ^ d[119] ^ d[121] ^ d[122] ^ d[123] ^ d[126] ^ d[129] ^ d[131] ^ d[132] ^ d[134] ^ d[136] ^ d[137] ^ d[142] ^ d[148] ^ d[149] ^ d[151] ^ d[152] ^ d[153] ^ d[155] ^ d[156] ^ d[157] ^ d[158] ^ d[160] ^ d[161] ^ d[162] ^ d[163] ^ d[164] ^ d[167] ^ d[170] ^ d[173] ^ d[174] ^ d[175] ^ d[176] ^ d[177] ^ d[179] ^ d[182] ^ d[184] ^ d[187] ^ d[188] ^ d[190] ^ d[191] ^ d[192] ^ d[194] ^ d[195] ^ d[196] ^ d[198] ^ d[199] ^ d[201] ^ d[202] ^ d[203] ^ d[205] ^ d[206] ^ d[208] ^ d[209] ^ d[211] ^ d[214] ^ d[216] ^ d[218] ^ d[219] ^ d[220] ^ d[221] ^ d[222] ^ d[223] ^ d[224] ^ d[225] ^ d[227] ^ d[229] ^ d[233] ^ d[234] ^ d[239] ^ d[243] ^ d[246] ^ d[247] ^ d[250] ^ d[251] ^ d[252] ^ d[254] ^ d[255]; + crc_256[15] = d[1] ^ d[2] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[12] ^ d[17] ^ d[18] ^ d[22] ^ d[23] ^ d[24] ^ d[25] ^ d[27] ^ d[28] ^ d[31] ^ d[34] ^ d[35] ^ d[37] ^ d[41] ^ d[45] ^ d[50] ^ d[51] ^ d[53] ^ d[54] ^ d[55] ^ d[59] ^ d[60] ^ d[61] ^ d[63] ^ d[68] ^ d[69] ^ d[74] ^ d[76] ^ d[77] ^ d[81] ^ d[82] ^ d[83] ^ d[85] ^ d[87] ^ d[88] ^ d[89] ^ d[90] ^ d[91] ^ d[94] ^ d[96] ^ d[97] ^ d[98] ^ d[103] ^ d[110] ^ d[111] ^ d[112] ^ d[113] ^ d[118] ^ d[119] ^ d[120] ^ d[122] ^ d[123] ^ d[124] ^ d[127] ^ d[130] ^ d[132] ^ d[133] ^ d[135] ^ d[137] ^ d[138] ^ d[143] ^ d[149] ^ d[150] ^ d[152] ^ d[153] ^ d[154] ^ d[156] ^ d[157] ^ d[158] ^ d[159] ^ d[161] ^ d[162] ^ d[163] ^ d[164] ^ d[165] ^ d[168] ^ d[171] ^ d[174] ^ d[175] ^ d[176] ^ d[177] ^ d[178] ^ d[180] ^ d[183] ^ d[185] ^ d[188] ^ d[189] ^ d[191] ^ d[192] ^ d[193] ^ d[195] ^ d[196] ^ d[197] ^ d[199] ^ d[200] ^ d[202] ^ d[203] ^ d[204] ^ d[206] ^ d[207] ^ d[209] ^ d[210] ^ d[212] ^ d[215] ^ d[217] ^ d[219] ^ d[220] ^ d[221] ^ d[222] ^ d[223] ^ d[224] ^ d[225] ^ d[226] ^ d[228] ^ d[230] ^ d[234] ^ d[235] ^ d[240] ^ d[244] ^ d[247] ^ d[248] ^ d[251] ^ d[252] ^ d[253] ^ d[255]; + end + endfunction + + assign adc_crc_err = (adc_crc == adc_crc_res) ? 1'b0 : 1'b1; + + // FSM state register + + always @(posedge clk) begin + if (rstn == 1'b0) begin + transfer_state <= 3'h0; + end else begin + transfer_state <= transfer_state_next; + end + end + + // FSM next state logic + + always @(*) begin + case (transfer_state) + IDLE : begin + transfer_state_next <= (start_transfer_s == 1'b1) ? CS_LOW : IDLE; + end + CS_LOW : begin + transfer_state_next <= CNTRL_LOW; + end + CNTRL_LOW : begin + transfer_state_next <= (width_counter == 4'd8) ? CNTRL_HIGH : CNTRL_LOW; + end + CNTRL_HIGH : begin + transfer_state_next <= (adc_config_enable_d | rd_conv_d) ? CS_HIGH : CNTRL_HIGH; + end + CS_HIGH : begin + transfer_state_next <= (channel_counter == nr_rd_burst || adc_config_enable_d) ? IDLE : CNTRL_LOW; + end + default : begin + transfer_state_next <= IDLE; + end + endcase + end + + // data valid for the register access + + assign rd_valid_s = (transfer_state == CNTRL_HIGH && rd_conv_d == 1'b1) ? 1'b1 : 1'b0; + assign adc_ctrl_status = (transfer_state == CNTRL_HIGH && (adc_config_enable_d == 1'b1 && adc_config_rd_wr == 1'b1)) ? 1'b1 : 1'b0; + + // FSM output logic + + assign db_o = wr_data; + + assign rd_new_data_s = rd_valid_s & ~rd_valid_d; + + always @(posedge clk) begin + rd_data <= ~rd_n ? db_i : rd_data; + rd_valid <= rd_new_data_s; + rd_valid_d <= rd_valid_s; + end + + assign adc_status_er_5b = adc_status_0[7:3] | adc_status_1[7:3] | adc_status_2[7:3] | adc_status_3[7:3] | adc_status_4[7:3] | adc_status_5[7:3] | adc_status_6[7:3] | adc_status_7[7:3]; + assign adc_status_er = adc_status_er_5b[0] | adc_status_er_5b[1] | adc_status_er_5b[2] | adc_status_er_5b[3] | adc_status_er_5b[4]; + assign adc_status = (adc_config_mode == STATUS_HEADER || adc_config_mode == CRC_STATUS) ? (adc_status_er ? 1'b0 : 1'b1) : 1'b1; + + // clear adc_crc* signals if the adc_config_mode is STATUS_HEADER or SIMPLE + + assign adc_crc = (adc_config_mode == STATUS_HEADER || adc_config_mode == SIMPLE) ? 16'h0 : adc_crc_r; + assign adc_crc_res = (adc_config_mode == STATUS_HEADER || adc_config_mode == SIMPLE) ? 16'h0 : adc_crc_res_r; + + assign cs_n = (transfer_state == IDLE) ? 1'b1 : 1'b0; + assign db_t = (adc_config_enable_d == 1'b1 && adc_config_rd_wr == 1'b0) ? 1'b0 : 1'b1; + assign rd_n = (transfer_state == CNTRL_LOW) && (rd_conv_d == 1'b1 || (adc_config_enable_d == 1'b1 && adc_config_rd_wr == 1'b1)) ? 1'b0 : 1'b1; + assign wr_n = (transfer_state == CNTRL_LOW) && (adc_config_enable_d == 1'b1 && adc_config_rd_wr == 1'b0) ? 1'b0 : 1'b1; + +endmodule diff --git a/adi_library/axi_ad7606x/axi_ad7606x_18b_pif.v b/adi_library/axi_ad7606x/axi_ad7606x_18b_pif.v new file mode 100644 index 00000000..76cdf702 --- /dev/null +++ b/adi_library/axi_ad7606x/axi_ad7606x_18b_pif.v @@ -0,0 +1,432 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad7606x_18b_pif #( + parameter NEG_EDGE = 1, + parameter POS_EDGE = 0 +) ( + + // physical interface + + output cs_n, + output [15:0] db_o, + input [15:0] db_i, + output db_t, + output rd_n, + output wr_n, + input busy, + input first_data, + + // FIFO interface + + output reg [17:0] adc_data_0, + output reg [ 7:0] adc_status_0 = 'h0, + output reg [17:0] adc_data_1, + output reg [ 7:0] adc_status_1 = 'h0, + output reg [17:0] adc_data_2, + output reg [ 7:0] adc_status_2 = 'h0, + output reg [17:0] adc_data_3, + output reg [ 7:0] adc_status_3 = 'h0, + output reg [17:0] adc_data_4, + output reg [ 7:0] adc_status_4 = 'h0, + output reg [17:0] adc_data_5, + output reg [ 7:0] adc_status_5 = 'h0, + output reg [17:0] adc_data_6, + output reg [ 7:0] adc_status_6 = 'h0, + output reg [17:0] adc_data_7, + output reg [ 7:0] adc_status_7 = 'h0, + output adc_status, + output [15:0] adc_crc, + output [15:0] adc_crc_res, + output adc_crc_err, + output reg adc_valid, + + // register access + + input clk, + input rstn, + input [31:0] adc_config_ctrl, + output adc_ctrl_status, + input [15:0] wr_data, + input adc_mode_en, + input [7:0] adc_custom_control, + output reg [15:0] rd_data = 'hf, + output reg rd_valid +); + + // state registers + + localparam [ 2:0] IDLE = 3'h0; + localparam [ 2:0] CS_LOW = 3'h1; + localparam [ 2:0] CNTRL_LOW = 3'h2; + localparam [ 2:0] CNTRL_HIGH = 3'h3; + localparam [ 2:0] CS_HIGH = 3'h4; + localparam [ 1:0] SIMPLE = 0; + localparam [ 1:0] STATUS_HEADER = 2; + localparam [ 1:0] CRC_ENABLED = 1; + localparam [ 1:0] CRC_STATUS = 3; + + // internal registers + + reg [ 2:0] transfer_state = 3'h0; + reg [ 2:0] transfer_state_next = 3'h0; + reg [ 3:0] width_counter = 4'h0; + reg [ 4:0] channel_counter = 5'h0; + reg [ 4:0] nr_rd_burst = 5'h0; + + reg rd_conv_d = 1'h0; + reg adc_config_enable_d = 1'h0; + + reg rd_valid_d = 1'h0; + reg read_ch_data = 1'd0; + + reg [ 7:0] adc_status_er_ch_id = 8'h0; + reg [15:0] adc_crc_r = 16'h0; + reg [15:0] adc_crc_res_r = 16'h0; + + reg [ 1:0] adc_config_mode_r = 2'h0; + + // internal wires + + wire rd_req_s; + wire wr_req_s; + + wire end_of_conv; + wire start_transfer_s; + wire rd_valid_s; + wire rd_new_data_s; + wire adc_config_enable; + wire adc_config_en; + wire adc_config_rd_wr; + wire [ 1:0] adc_config_mode; + + wire [ 4:0] adc_status_er_5b; + wire adc_status_er; + + // adc_config_rd_wr - RD (1), WR (0) + + assign adc_config_enable = adc_config_ctrl[0]; + assign adc_config_rd_wr = adc_config_ctrl[1]; + + // instantiations + + ad_edge_detect #( + .EDGE(POS_EDGE) + ) i_ad_edge_detect_en ( + .clk (clk), + .rst (~rstn), + .signal_in (adc_config_enable), + .signal_out (adc_config_en)); + + ad_edge_detect #( + .EDGE(NEG_EDGE) + ) i_ad_edge_detect ( + .clk (clk), + .rst (~rstn), + .signal_in (busy), + .signal_out (end_of_conv)); + + // counters to control the RD_N and WR_N lines + + assign start_transfer_s = (end_of_conv | adc_config_en) ? 1'b1 : 1'b0; + + always @(posedge clk) begin + if (rstn == 1'b0) begin + adc_config_mode_r <= 2'h0; + end else begin + if (adc_mode_en) begin + if (adc_custom_control == 'h0) begin + adc_config_mode_r <= SIMPLE; + end else if (adc_custom_control == 'h1) begin + adc_config_mode_r <= CRC_ENABLED; + end else if (adc_custom_control == 'h2) begin + adc_config_mode_r <= STATUS_HEADER; + end else if (adc_custom_control == 'h3) begin + adc_config_mode_r <= CRC_STATUS; + end else begin + adc_config_mode_r <= adc_config_mode; + end + end else begin + adc_config_mode_r <= adc_config_mode; + end + end + end + + assign adc_config_mode = adc_config_mode_r; + + always @(negedge clk) begin + if (transfer_state == IDLE) begin + rd_conv_d <= end_of_conv; + adc_config_enable_d <= adc_config_en; + end + end + + always @(posedge clk) begin + if (rstn == 1'b0) begin + width_counter <= 4'h0; + end else begin + if(transfer_state == CNTRL_LOW || transfer_state == CNTRL_HIGH) begin + width_counter <= width_counter + 1; + end else begin + width_counter <= 4'h0; + end + end + end + + always @(posedge clk) begin + if (rstn == 1'b0) begin + channel_counter <= 5'h0; + end else begin + if (rd_new_data_s == 1'b1 && read_ch_data == 1'b1) begin + channel_counter <= channel_counter + 1; + end else if (transfer_state == IDLE) begin + channel_counter <= 5'h0; + end + end + end + + always @(posedge clk) begin + if (adc_config_mode == SIMPLE || adc_config_mode == STATUS_HEADER) begin + nr_rd_burst = 5'd16; + if ((first_data & ~cs_n) && ~adc_config_enable_d) begin + read_ch_data <= 1'b1; + end else if (channel_counter == 5'd16 && transfer_state == IDLE) begin + read_ch_data <= 1'b0; + end + end else if (adc_config_mode == CRC_ENABLED || adc_config_mode == CRC_STATUS) begin + nr_rd_burst = 5'd17; + if ((first_data & ~cs_n) && ~adc_config_enable_d) begin + read_ch_data <= 1'b1; + end else if (channel_counter == 5'd17 && transfer_state == IDLE) begin + read_ch_data <= 1'b0; + end + end else begin + read_ch_data <= 1'b1; + end + if (read_ch_data == 1'b1 && rd_new_data_s == 1'b1) begin + case (channel_counter) + 5'd0 : begin + adc_data_0[17:2] <= rd_data; + end + 5'd1 : begin + adc_data_0[1:0] <= rd_data[15:14]; + if (adc_config_mode == STATUS_HEADER || adc_config_mode == CRC_STATUS) begin + adc_status_0 <= rd_data[7:0]; + end + end + 5'd2 : begin + adc_data_1[17:2] <= rd_data; + end + 5'd3 : begin + adc_data_1[1:0] <= rd_data[15:14]; + if (adc_config_mode == STATUS_HEADER || adc_config_mode == CRC_STATUS) begin + adc_status_1 <= rd_data[7:0]; + end + end + 5'd4 : begin + adc_data_2[17:2] <= rd_data; + end + 5'd5 : begin + adc_data_2[1:0] <= rd_data[15:14]; + if (adc_config_mode == STATUS_HEADER || adc_config_mode == CRC_STATUS) begin + adc_status_2 <= rd_data[7:0]; + end + end + 5'd6 : begin + adc_data_3[17:2] <= rd_data; + end + 5'd7 : begin + adc_data_3[1:0] <= rd_data[15:14]; + if (adc_config_mode == STATUS_HEADER || adc_config_mode == CRC_STATUS) begin + adc_status_3 <= rd_data[7:0]; + end + end + 5'd8 : begin + adc_data_4[17:2] <= rd_data; + end + 5'd9 : begin + adc_data_4[1:0] <= rd_data[15:14]; + if (adc_config_mode == STATUS_HEADER || adc_config_mode == CRC_STATUS) begin + adc_status_4 <= rd_data[7:0]; + end + end + 5'd10 : begin + adc_data_5[17:2] <= rd_data; + end + 5'd11 : begin + adc_data_5[1:0] <= rd_data[15:14]; + if (adc_config_mode == STATUS_HEADER || adc_config_mode == CRC_STATUS) begin + adc_status_5 <= rd_data[7:0]; + end + end + 5'd12 : begin + adc_data_6[17:2] <= rd_data; + end + 5'd13 : begin + adc_data_6[1:0] <= rd_data[15:14]; + if (adc_config_mode == STATUS_HEADER || adc_config_mode == CRC_STATUS) begin + adc_status_6 <= rd_data[7:0]; + end + end + 5'd14 : begin + adc_data_7[17:2] <= rd_data; + end + 5'd15 : begin + adc_data_7[1:0] <= rd_data[15:14]; + if (adc_config_mode == STATUS_HEADER || adc_config_mode == CRC_STATUS) begin + adc_status_7 <= rd_data[7:0]; + end + end + 5'd16 : begin + adc_crc_r <= rd_data; + if (adc_config_mode == CRC_ENABLED) begin + adc_crc_res_r <= crc_256({adc_data_0,14'b0,adc_data_1,14'b0,adc_data_2,14'b0,adc_data_3,14'b0, + adc_data_4,14'b0,adc_data_5,14'b0,adc_data_6,14'b0,adc_data_7,14'b0}); + end else if (adc_config_mode == CRC_STATUS) begin + adc_crc_res_r <= crc_256({adc_data_0,6'b0,adc_status_0,adc_data_1,6'b0,adc_status_1,adc_data_2,6'b0,adc_status_2, + adc_data_3,6'b0,adc_status_3,adc_data_4,6'b0,adc_status_4,adc_data_5,6'b0,adc_status_5, + adc_data_6,6'b0,adc_status_6,adc_data_7,6'b0,adc_status_7}); + end + end + endcase + end + case (adc_config_mode) + SIMPLE: begin + adc_valid <= (channel_counter == 5'd16) ? rd_valid_d : 1'b0; + end + STATUS_HEADER: begin + adc_valid <= (channel_counter == 5'd16) ? rd_valid_d : 1'b0; + end + CRC_ENABLED: begin + adc_valid <= (channel_counter == 5'd17) ? rd_valid_d : 1'b0; + end + CRC_STATUS: begin + adc_valid <= (channel_counter == 5'd17) ? rd_valid_d : 1'b0; + end + endcase + end + + function [15:0] crc_256; + input [255:0] d; + begin + crc_256[0] = d[0] ^ d[2] ^ d[3] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[13] ^ d[18] ^ d[19] ^ d[23] ^ d[24] ^ d[25] ^ d[26] ^ d[28] ^ d[29] ^ d[32] ^ d[35] ^ d[36] ^ d[38] ^ d[42] ^ d[46] ^ d[51] ^ d[52] ^ d[54] ^ d[55] ^ d[56] ^ d[60] ^ d[61] ^ d[62] ^ d[64] ^ d[69] ^ d[70] ^ d[75] ^ d[77] ^ d[78] ^ d[82] ^ d[83] ^ d[84] ^ d[86] ^ d[88] ^ d[89] ^ d[90] ^ d[91] ^ d[92] ^ d[95] ^ d[97] ^ d[98] ^ d[99] ^ d[104] ^ d[111] ^ d[112] ^ d[113] ^ d[114] ^ d[119] ^ d[120] ^ d[121] ^ d[123] ^ d[124] ^ d[125] ^ d[128] ^ d[131] ^ d[133] ^ d[134] ^ d[136] ^ d[138] ^ d[139] ^ d[144] ^ d[150] ^ d[151] ^ d[153] ^ d[154] ^ d[155] ^ d[157] ^ d[158] ^ d[159] ^ d[160] ^ d[162] ^ d[163] ^ d[164] ^ d[165] ^ d[166] ^ d[169] ^ d[172] ^ d[175] ^ d[176] ^ d[177] ^ d[178] ^ d[179] ^ d[181] ^ d[184] ^ d[186] ^ d[189] ^ d[190] ^ d[192] ^ d[193] ^ d[194] ^ d[196] ^ d[197] ^ d[198] ^ d[200] ^ d[201] ^ d[203] ^ d[204] ^ d[205] ^ d[207] ^ d[208] ^ d[210] ^ d[211] ^ d[213] ^ d[216] ^ d[218] ^ d[220] ^ d[221] ^ d[222] ^ d[223] ^ d[224] ^ d[225] ^ d[226] ^ d[227] ^ d[229] ^ d[231] ^ d[235] ^ d[236] ^ d[241] ^ d[245] ^ d[248] ^ d[249] ^ d[252] ^ d[253] ^ d[254]; + crc_256[1] = d[0] ^ d[1] ^ d[2] ^ d[4] ^ d[6] ^ d[11] ^ d[13] ^ d[14] ^ d[18] ^ d[20] ^ d[23] ^ d[27] ^ d[28] ^ d[30] ^ d[32] ^ d[33] ^ d[35] ^ d[37] ^ d[38] ^ d[39] ^ d[42] ^ d[43] ^ d[46] ^ d[47] ^ d[51] ^ d[53] ^ d[54] ^ d[57] ^ d[60] ^ d[63] ^ d[64] ^ d[65] ^ d[69] ^ d[71] ^ d[75] ^ d[76] ^ d[77] ^ d[79] ^ d[82] ^ d[85] ^ d[86] ^ d[87] ^ d[88] ^ d[93] ^ d[95] ^ d[96] ^ d[97] ^ d[100] ^ d[104] ^ d[105] ^ d[111] ^ d[115] ^ d[119] ^ d[122] ^ d[123] ^ d[126] ^ d[128] ^ d[129] ^ d[131] ^ d[132] ^ d[133] ^ d[135] ^ d[136] ^ d[137] ^ d[138] ^ d[140] ^ d[144] ^ d[145] ^ d[150] ^ d[152] ^ d[153] ^ d[156] ^ d[157] ^ d[161] ^ d[162] ^ d[167] ^ d[169] ^ d[170] ^ d[172] ^ d[173] ^ d[175] ^ d[180] ^ d[181] ^ d[182] ^ d[184] ^ d[185] ^ d[186] ^ d[187] ^ d[189] ^ d[191] ^ d[192] ^ d[195] ^ d[196] ^ d[199] ^ d[200] ^ d[202] ^ d[203] ^ d[206] ^ d[207] ^ d[209] ^ d[210] ^ d[212] ^ d[213] ^ d[214] ^ d[216] ^ d[217] ^ d[218] ^ d[219] ^ d[220] ^ d[228] ^ d[229] ^ d[230] ^ d[231] ^ d[232] ^ d[235] ^ d[237] ^ d[241] ^ d[242] ^ d[245] ^ d[246] ^ d[248] ^ d[250] ^ d[252] ^ d[255]; + crc_256[2] = d[1] ^ d[2] ^ d[3] ^ d[5] ^ d[7] ^ d[12] ^ d[14] ^ d[15] ^ d[19] ^ d[21] ^ d[24] ^ d[28] ^ d[29] ^ d[31] ^ d[33] ^ d[34] ^ d[36] ^ d[38] ^ d[39] ^ d[40] ^ d[43] ^ d[44] ^ d[47] ^ d[48] ^ d[52] ^ d[54] ^ d[55] ^ d[58] ^ d[61] ^ d[64] ^ d[65] ^ d[66] ^ d[70] ^ d[72] ^ d[76] ^ d[77] ^ d[78] ^ d[80] ^ d[83] ^ d[86] ^ d[87] ^ d[88] ^ d[89] ^ d[94] ^ d[96] ^ d[97] ^ d[98] ^ d[101] ^ d[105] ^ d[106] ^ d[112] ^ d[116] ^ d[120] ^ d[123] ^ d[124] ^ d[127] ^ d[129] ^ d[130] ^ d[132] ^ d[133] ^ d[134] ^ d[136] ^ d[137] ^ d[138] ^ d[139] ^ d[141] ^ d[145] ^ d[146] ^ d[151] ^ d[153] ^ d[154] ^ d[157] ^ d[158] ^ d[162] ^ d[163] ^ d[168] ^ d[170] ^ d[171] ^ d[173] ^ d[174] ^ d[176] ^ d[181] ^ d[182] ^ d[183] ^ d[185] ^ d[186] ^ d[187] ^ d[188] ^ d[190] ^ d[192] ^ d[193] ^ d[196] ^ d[197] ^ d[200] ^ d[201] ^ d[203] ^ d[204] ^ d[207] ^ d[208] ^ d[210] ^ d[211] ^ d[213] ^ d[214] ^ d[215] ^ d[217] ^ d[218] ^ d[219] ^ d[220] ^ d[221] ^ d[229] ^ d[230] ^ d[231] ^ d[232] ^ d[233] ^ d[236] ^ d[238] ^ d[242] ^ d[243] ^ d[246] ^ d[247] ^ d[249] ^ d[251] ^ d[253]; + crc_256[3] = d[0] ^ d[4] ^ d[7] ^ d[9] ^ d[10] ^ d[15] ^ d[16] ^ d[18] ^ d[19] ^ d[20] ^ d[22] ^ d[23] ^ d[24] ^ d[26] ^ d[28] ^ d[30] ^ d[34] ^ d[36] ^ d[37] ^ d[38] ^ d[39] ^ d[40] ^ d[41] ^ d[42] ^ d[44] ^ d[45] ^ d[46] ^ d[48] ^ d[49] ^ d[51] ^ d[52] ^ d[53] ^ d[54] ^ d[59] ^ d[60] ^ d[61] ^ d[64] ^ d[65] ^ d[66] ^ d[67] ^ d[69] ^ d[70] ^ d[71] ^ d[73] ^ d[75] ^ d[79] ^ d[81] ^ d[82] ^ d[83] ^ d[86] ^ d[87] ^ d[91] ^ d[92] ^ d[102] ^ d[104] ^ d[106] ^ d[107] ^ d[111] ^ d[112] ^ d[114] ^ d[117] ^ d[119] ^ d[120] ^ d[123] ^ d[130] ^ d[135] ^ d[136] ^ d[137] ^ d[140] ^ d[142] ^ d[144] ^ d[146] ^ d[147] ^ d[150] ^ d[151] ^ d[152] ^ d[153] ^ d[157] ^ d[160] ^ d[162] ^ d[165] ^ d[166] ^ d[171] ^ d[174] ^ d[176] ^ d[178] ^ d[179] ^ d[181] ^ d[182] ^ d[183] ^ d[187] ^ d[188] ^ d[190] ^ d[191] ^ d[192] ^ d[196] ^ d[200] ^ d[202] ^ d[203] ^ d[207] ^ d[209] ^ d[210] ^ d[212] ^ d[213] ^ d[214] ^ d[215] ^ d[219] ^ d[223] ^ d[224] ^ d[225] ^ d[226] ^ d[227] ^ d[229] ^ d[230] ^ d[232] ^ d[233] ^ d[234] ^ d[235] ^ d[236] ^ d[237] ^ d[239] ^ d[241] ^ d[243] ^ d[244] ^ d[245] ^ d[247] ^ d[249] ^ d[250] ^ d[253]; + crc_256[4] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[5] ^ d[6] ^ d[7] ^ d[9] ^ d[11] ^ d[13] ^ d[16] ^ d[17] ^ d[18] ^ d[20] ^ d[21] ^ d[26] ^ d[27] ^ d[28] ^ d[31] ^ d[32] ^ d[36] ^ d[37] ^ d[39] ^ d[40] ^ d[41] ^ d[43] ^ d[45] ^ d[47] ^ d[49] ^ d[50] ^ d[51] ^ d[53] ^ d[56] ^ d[64] ^ d[65] ^ d[66] ^ d[67] ^ d[68] ^ d[69] ^ d[71] ^ d[72] ^ d[74] ^ d[75] ^ d[76] ^ d[77] ^ d[78] ^ d[80] ^ d[86] ^ d[87] ^ d[89] ^ d[90] ^ d[91] ^ d[93] ^ d[95] ^ d[97] ^ d[98] ^ d[99] ^ d[103] ^ d[104] ^ d[105] ^ d[107] ^ d[108] ^ d[111] ^ d[114] ^ d[115] ^ d[118] ^ d[119] ^ d[123] ^ d[125] ^ d[128] ^ d[133] ^ d[134] ^ d[137] ^ d[139] ^ d[141] ^ d[143] ^ d[144] ^ d[145] ^ d[147] ^ d[148] ^ d[150] ^ d[152] ^ d[155] ^ d[157] ^ d[159] ^ d[160] ^ d[161] ^ d[162] ^ d[164] ^ d[165] ^ d[167] ^ d[169] ^ d[176] ^ d[178] ^ d[180] ^ d[181] ^ d[182] ^ d[183] ^ d[186] ^ d[188] ^ d[190] ^ d[191] ^ d[194] ^ d[196] ^ d[198] ^ d[200] ^ d[205] ^ d[207] ^ d[214] ^ d[215] ^ d[218] ^ d[221] ^ d[222] ^ d[223] ^ d[228] ^ d[229] ^ d[230] ^ d[233] ^ d[234] ^ d[237] ^ d[238] ^ d[240] ^ d[241] ^ d[242] ^ d[244] ^ d[246] ^ d[249] ^ d[250] ^ d[251] ^ d[252] ^ d[253]; + crc_256[5] = d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[6] ^ d[7] ^ d[8] ^ d[10] ^ d[12] ^ d[14] ^ d[17] ^ d[18] ^ d[19] ^ d[21] ^ d[22] ^ d[27] ^ d[28] ^ d[29] ^ d[32] ^ d[33] ^ d[37] ^ d[38] ^ d[40] ^ d[41] ^ d[42] ^ d[44] ^ d[46] ^ d[48] ^ d[50] ^ d[51] ^ d[52] ^ d[54] ^ d[57] ^ d[65] ^ d[66] ^ d[67] ^ d[68] ^ d[69] ^ d[70] ^ d[72] ^ d[73] ^ d[75] ^ d[76] ^ d[77] ^ d[78] ^ d[79] ^ d[81] ^ d[87] ^ d[88] ^ d[90] ^ d[91] ^ d[92] ^ d[94] ^ d[96] ^ d[98] ^ d[99] ^ d[100] ^ d[104] ^ d[105] ^ d[106] ^ d[108] ^ d[109] ^ d[112] ^ d[115] ^ d[116] ^ d[119] ^ d[120] ^ d[124] ^ d[126] ^ d[129] ^ d[134] ^ d[135] ^ d[138] ^ d[140] ^ d[142] ^ d[144] ^ d[145] ^ d[146] ^ d[148] ^ d[149] ^ d[151] ^ d[153] ^ d[156] ^ d[158] ^ d[160] ^ d[161] ^ d[162] ^ d[163] ^ d[165] ^ d[166] ^ d[168] ^ d[170] ^ d[177] ^ d[179] ^ d[181] ^ d[182] ^ d[183] ^ d[184] ^ d[187] ^ d[189] ^ d[191] ^ d[192] ^ d[195] ^ d[197] ^ d[199] ^ d[201] ^ d[206] ^ d[208] ^ d[215] ^ d[216] ^ d[219] ^ d[222] ^ d[223] ^ d[224] ^ d[229] ^ d[230] ^ d[231] ^ d[234] ^ d[235] ^ d[238] ^ d[239] ^ d[241] ^ d[242] ^ d[243] ^ d[245] ^ d[247] ^ d[250] ^ d[251] ^ d[252] ^ d[253] ^ d[254]; + crc_256[6] = d[0] ^ d[4] ^ d[5] ^ d[6] ^ d[10] ^ d[11] ^ d[15] ^ d[20] ^ d[22] ^ d[24] ^ d[25] ^ d[26] ^ d[30] ^ d[32] ^ d[33] ^ d[34] ^ d[35] ^ d[36] ^ d[39] ^ d[41] ^ d[43] ^ d[45] ^ d[46] ^ d[47] ^ d[49] ^ d[53] ^ d[54] ^ d[56] ^ d[58] ^ d[60] ^ d[61] ^ d[62] ^ d[64] ^ d[66] ^ d[67] ^ d[68] ^ d[71] ^ d[73] ^ d[74] ^ d[75] ^ d[76] ^ d[79] ^ d[80] ^ d[83] ^ d[84] ^ d[86] ^ d[90] ^ d[93] ^ d[98] ^ d[100] ^ d[101] ^ d[104] ^ d[105] ^ d[106] ^ d[107] ^ d[109] ^ d[110] ^ d[111] ^ d[112] ^ d[114] ^ d[116] ^ d[117] ^ d[119] ^ d[123] ^ d[124] ^ d[127] ^ d[128] ^ d[130] ^ d[131] ^ d[133] ^ d[134] ^ d[135] ^ d[138] ^ d[141] ^ d[143] ^ d[144] ^ d[145] ^ d[146] ^ d[147] ^ d[149] ^ d[151] ^ d[152] ^ d[153] ^ d[155] ^ d[158] ^ d[160] ^ d[161] ^ d[165] ^ d[167] ^ d[171] ^ d[172] ^ d[175] ^ d[176] ^ d[177] ^ d[179] ^ d[180] ^ d[181] ^ d[182] ^ d[183] ^ d[185] ^ d[186] ^ d[188] ^ d[189] ^ d[194] ^ d[197] ^ d[201] ^ d[202] ^ d[203] ^ d[204] ^ d[205] ^ d[208] ^ d[209] ^ d[210] ^ d[211] ^ d[213] ^ d[217] ^ d[218] ^ d[221] ^ d[222] ^ d[226] ^ d[227] ^ d[229] ^ d[230] ^ d[232] ^ d[239] ^ d[240] ^ d[241] ^ d[242] ^ d[243] ^ d[244] ^ d[245] ^ d[246] ^ d[249] ^ d[251] ^ d[255]; + crc_256[7] = d[1] ^ d[5] ^ d[6] ^ d[7] ^ d[11] ^ d[12] ^ d[16] ^ d[21] ^ d[23] ^ d[25] ^ d[26] ^ d[27] ^ d[31] ^ d[33] ^ d[34] ^ d[35] ^ d[36] ^ d[37] ^ d[40] ^ d[42] ^ d[44] ^ d[46] ^ d[47] ^ d[48] ^ d[50] ^ d[54] ^ d[55] ^ d[57] ^ d[59] ^ d[61] ^ d[62] ^ d[63] ^ d[65] ^ d[67] ^ d[68] ^ d[69] ^ d[72] ^ d[74] ^ d[75] ^ d[76] ^ d[77] ^ d[80] ^ d[81] ^ d[84] ^ d[85] ^ d[87] ^ d[91] ^ d[94] ^ d[99] ^ d[101] ^ d[102] ^ d[105] ^ d[106] ^ d[107] ^ d[108] ^ d[110] ^ d[111] ^ d[112] ^ d[113] ^ d[115] ^ d[117] ^ d[118] ^ d[120] ^ d[124] ^ d[125] ^ d[128] ^ d[129] ^ d[131] ^ d[132] ^ d[134] ^ d[135] ^ d[136] ^ d[139] ^ d[142] ^ d[144] ^ d[145] ^ d[146] ^ d[147] ^ d[148] ^ d[150] ^ d[152] ^ d[153] ^ d[154] ^ d[156] ^ d[159] ^ d[161] ^ d[162] ^ d[166] ^ d[168] ^ d[172] ^ d[173] ^ d[176] ^ d[177] ^ d[178] ^ d[180] ^ d[181] ^ d[182] ^ d[183] ^ d[184] ^ d[186] ^ d[187] ^ d[189] ^ d[190] ^ d[195] ^ d[198] ^ d[202] ^ d[203] ^ d[204] ^ d[205] ^ d[206] ^ d[209] ^ d[210] ^ d[211] ^ d[212] ^ d[214] ^ d[218] ^ d[219] ^ d[222] ^ d[223] ^ d[227] ^ d[228] ^ d[230] ^ d[231] ^ d[233] ^ d[240] ^ d[241] ^ d[242] ^ d[243] ^ d[244] ^ d[245] ^ d[246] ^ d[247] ^ d[250] ^ d[252]; + crc_256[8] = d[0] ^ d[3] ^ d[9] ^ d[10] ^ d[12] ^ d[17] ^ d[18] ^ d[19] ^ d[22] ^ d[23] ^ d[25] ^ d[27] ^ d[29] ^ d[34] ^ d[37] ^ d[41] ^ d[42] ^ d[43] ^ d[45] ^ d[46] ^ d[47] ^ d[48] ^ d[49] ^ d[52] ^ d[54] ^ d[58] ^ d[61] ^ d[63] ^ d[66] ^ d[68] ^ d[73] ^ d[76] ^ d[81] ^ d[83] ^ d[84] ^ d[85] ^ d[89] ^ d[90] ^ d[91] ^ d[97] ^ d[98] ^ d[99] ^ d[100] ^ d[102] ^ d[103] ^ d[104] ^ d[106] ^ d[107] ^ d[108] ^ d[109] ^ d[116] ^ d[118] ^ d[120] ^ d[123] ^ d[124] ^ d[126] ^ d[128] ^ d[129] ^ d[130] ^ d[131] ^ d[132] ^ d[134] ^ d[135] ^ d[137] ^ d[138] ^ d[139] ^ d[140] ^ d[143] ^ d[144] ^ d[145] ^ d[146] ^ d[147] ^ d[148] ^ d[149] ^ d[150] ^ d[158] ^ d[159] ^ d[164] ^ d[165] ^ d[166] ^ d[167] ^ d[172] ^ d[173] ^ d[174] ^ d[175] ^ d[176] ^ d[182] ^ d[183] ^ d[185] ^ d[186] ^ d[187] ^ d[188] ^ d[189] ^ d[191] ^ d[192] ^ d[193] ^ d[194] ^ d[197] ^ d[198] ^ d[199] ^ d[200] ^ d[201] ^ d[206] ^ d[208] ^ d[212] ^ d[215] ^ d[216] ^ d[218] ^ d[219] ^ d[221] ^ d[222] ^ d[225] ^ d[226] ^ d[227] ^ d[228] ^ d[232] ^ d[234] ^ d[235] ^ d[236] ^ d[242] ^ d[243] ^ d[244] ^ d[246] ^ d[247] ^ d[249] ^ d[251] ^ d[252] ^ d[254]; + crc_256[9] = d[1] ^ d[4] ^ d[10] ^ d[11] ^ d[13] ^ d[18] ^ d[19] ^ d[20] ^ d[23] ^ d[24] ^ d[26] ^ d[28] ^ d[30] ^ d[35] ^ d[38] ^ d[42] ^ d[43] ^ d[44] ^ d[46] ^ d[47] ^ d[48] ^ d[49] ^ d[50] ^ d[53] ^ d[55] ^ d[59] ^ d[62] ^ d[64] ^ d[67] ^ d[69] ^ d[74] ^ d[77] ^ d[82] ^ d[84] ^ d[85] ^ d[86] ^ d[90] ^ d[91] ^ d[92] ^ d[98] ^ d[99] ^ d[100] ^ d[101] ^ d[103] ^ d[104] ^ d[105] ^ d[107] ^ d[108] ^ d[109] ^ d[110] ^ d[117] ^ d[119] ^ d[121] ^ d[124] ^ d[125] ^ d[127] ^ d[129] ^ d[130] ^ d[131] ^ d[132] ^ d[133] ^ d[135] ^ d[136] ^ d[138] ^ d[139] ^ d[140] ^ d[141] ^ d[144] ^ d[145] ^ d[146] ^ d[147] ^ d[148] ^ d[149] ^ d[150] ^ d[151] ^ d[159] ^ d[160] ^ d[165] ^ d[166] ^ d[167] ^ d[168] ^ d[173] ^ d[174] ^ d[175] ^ d[176] ^ d[177] ^ d[183] ^ d[184] ^ d[186] ^ d[187] ^ d[188] ^ d[189] ^ d[190] ^ d[192] ^ d[193] ^ d[194] ^ d[195] ^ d[198] ^ d[199] ^ d[200] ^ d[201] ^ d[202] ^ d[207] ^ d[209] ^ d[213] ^ d[216] ^ d[217] ^ d[219] ^ d[220] ^ d[222] ^ d[223] ^ d[226] ^ d[227] ^ d[228] ^ d[229] ^ d[233] ^ d[235] ^ d[236] ^ d[237] ^ d[243] ^ d[244] ^ d[245] ^ d[247] ^ d[248] ^ d[250] ^ d[252] ^ d[253] ^ d[255]; + crc_256[10] = d[0] ^ d[3] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[18] ^ d[20] ^ d[21] ^ d[23] ^ d[26] ^ d[27] ^ d[28] ^ d[31] ^ d[32] ^ d[35] ^ d[38] ^ d[39] ^ d[42] ^ d[43] ^ d[44] ^ d[45] ^ d[46] ^ d[47] ^ d[48] ^ d[49] ^ d[50] ^ d[52] ^ d[55] ^ d[61] ^ d[62] ^ d[63] ^ d[64] ^ d[65] ^ d[68] ^ d[69] ^ d[77] ^ d[82] ^ d[84] ^ d[85] ^ d[87] ^ d[88] ^ d[89] ^ d[90] ^ d[93] ^ d[95] ^ d[97] ^ d[98] ^ d[100] ^ d[101] ^ d[102] ^ d[105] ^ d[106] ^ d[108] ^ d[109] ^ d[110] ^ d[112] ^ d[113] ^ d[114] ^ d[118] ^ d[119] ^ d[121] ^ d[122] ^ d[123] ^ d[124] ^ d[126] ^ d[130] ^ d[132] ^ d[137] ^ d[138] ^ d[140] ^ d[141] ^ d[142] ^ d[144] ^ d[145] ^ d[146] ^ d[147] ^ d[148] ^ d[149] ^ d[152] ^ d[153] ^ d[154] ^ d[155] ^ d[157] ^ d[158] ^ d[159] ^ d[161] ^ d[162] ^ d[163] ^ d[164] ^ d[165] ^ d[167] ^ d[168] ^ d[172] ^ d[174] ^ d[179] ^ d[181] ^ d[185] ^ d[186] ^ d[187] ^ d[188] ^ d[191] ^ d[192] ^ d[195] ^ d[197] ^ d[198] ^ d[199] ^ d[202] ^ d[204] ^ d[205] ^ d[207] ^ d[211] ^ d[213] ^ d[214] ^ d[216] ^ d[217] ^ d[222] ^ d[225] ^ d[226] ^ d[228] ^ d[230] ^ d[231] ^ d[234] ^ d[235] ^ d[237] ^ d[238] ^ d[241] ^ d[244] ^ d[246] ^ d[251] ^ d[252]; + crc_256[11] = d[1] ^ d[4] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[10] ^ d[11] ^ d[12] ^ d[13] ^ d[14] ^ d[15] ^ d[19] ^ d[21] ^ d[22] ^ d[24] ^ d[27] ^ d[28] ^ d[29] ^ d[32] ^ d[33] ^ d[36] ^ d[39] ^ d[40] ^ d[43] ^ d[44] ^ d[45] ^ d[46] ^ d[47] ^ d[48] ^ d[49] ^ d[50] ^ d[51] ^ d[53] ^ d[56] ^ d[62] ^ d[63] ^ d[64] ^ d[65] ^ d[66] ^ d[69] ^ d[70] ^ d[78] ^ d[83] ^ d[85] ^ d[86] ^ d[88] ^ d[89] ^ d[90] ^ d[91] ^ d[94] ^ d[96] ^ d[98] ^ d[99] ^ d[101] ^ d[102] ^ d[103] ^ d[106] ^ d[107] ^ d[109] ^ d[110] ^ d[111] ^ d[113] ^ d[114] ^ d[115] ^ d[119] ^ d[120] ^ d[122] ^ d[123] ^ d[124] ^ d[125] ^ d[127] ^ d[131] ^ d[133] ^ d[138] ^ d[139] ^ d[141] ^ d[142] ^ d[143] ^ d[145] ^ d[146] ^ d[147] ^ d[148] ^ d[149] ^ d[150] ^ d[153] ^ d[154] ^ d[155] ^ d[156] ^ d[158] ^ d[159] ^ d[160] ^ d[162] ^ d[163] ^ d[164] ^ d[165] ^ d[166] ^ d[168] ^ d[169] ^ d[173] ^ d[175] ^ d[180] ^ d[182] ^ d[186] ^ d[187] ^ d[188] ^ d[189] ^ d[192] ^ d[193] ^ d[196] ^ d[198] ^ d[199] ^ d[200] ^ d[203] ^ d[205] ^ d[206] ^ d[208] ^ d[212] ^ d[214] ^ d[215] ^ d[217] ^ d[218] ^ d[223] ^ d[226] ^ d[227] ^ d[229] ^ d[231] ^ d[232] ^ d[235] ^ d[236] ^ d[238] ^ d[239] ^ d[242] ^ d[245] ^ d[247] ^ d[252] ^ d[253]; + crc_256[12] = d[0] ^ d[3] ^ d[5] ^ d[6] ^ d[11] ^ d[12] ^ d[14] ^ d[15] ^ d[16] ^ d[18] ^ d[19] ^ d[20] ^ d[22] ^ d[24] ^ d[26] ^ d[30] ^ d[32] ^ d[33] ^ d[34] ^ d[35] ^ d[36] ^ d[37] ^ d[38] ^ d[40] ^ d[41] ^ d[42] ^ d[44] ^ d[45] ^ d[47] ^ d[48] ^ d[49] ^ d[50] ^ d[55] ^ d[56] ^ d[57] ^ d[60] ^ d[61] ^ d[62] ^ d[63] ^ d[65] ^ d[66] ^ d[67] ^ d[69] ^ d[71] ^ d[75] ^ d[77] ^ d[78] ^ d[79] ^ d[82] ^ d[83] ^ d[87] ^ d[88] ^ d[98] ^ d[100] ^ d[102] ^ d[103] ^ d[107] ^ d[108] ^ d[110] ^ d[113] ^ d[115] ^ d[116] ^ d[119] ^ d[126] ^ d[131] ^ d[132] ^ d[133] ^ d[136] ^ d[138] ^ d[140] ^ d[142] ^ d[143] ^ d[146] ^ d[147] ^ d[148] ^ d[149] ^ d[153] ^ d[156] ^ d[158] ^ d[161] ^ d[162] ^ d[167] ^ d[170] ^ d[172] ^ d[174] ^ d[175] ^ d[177] ^ d[178] ^ d[179] ^ d[183] ^ d[184] ^ d[186] ^ d[187] ^ d[188] ^ d[192] ^ d[196] ^ d[198] ^ d[199] ^ d[203] ^ d[205] ^ d[206] ^ d[208] ^ d[209] ^ d[210] ^ d[211] ^ d[215] ^ d[219] ^ d[220] ^ d[221] ^ d[222] ^ d[223] ^ d[225] ^ d[226] ^ d[228] ^ d[229] ^ d[230] ^ d[231] ^ d[232] ^ d[233] ^ d[235] ^ d[237] ^ d[239] ^ d[240] ^ d[241] ^ d[243] ^ d[245] ^ d[246] ^ d[249] ^ d[252]; + crc_256[13] = d[0] ^ d[1] ^ d[2] ^ d[3] ^ d[4] ^ d[8] ^ d[9] ^ d[10] ^ d[12] ^ d[15] ^ d[16] ^ d[17] ^ d[18] ^ d[20] ^ d[21] ^ d[24] ^ d[26] ^ d[27] ^ d[28] ^ d[29] ^ d[31] ^ d[32] ^ d[33] ^ d[34] ^ d[37] ^ d[39] ^ d[41] ^ d[43] ^ d[45] ^ d[48] ^ d[49] ^ d[50] ^ d[52] ^ d[54] ^ d[55] ^ d[57] ^ d[58] ^ d[60] ^ d[63] ^ d[66] ^ d[67] ^ d[68] ^ d[69] ^ d[72] ^ d[75] ^ d[76] ^ d[77] ^ d[79] ^ d[80] ^ d[82] ^ d[86] ^ d[90] ^ d[91] ^ d[92] ^ d[95] ^ d[97] ^ d[98] ^ d[101] ^ d[103] ^ d[108] ^ d[109] ^ d[112] ^ d[113] ^ d[116] ^ d[117] ^ d[119] ^ d[121] ^ d[123] ^ d[124] ^ d[125] ^ d[127] ^ d[128] ^ d[131] ^ d[132] ^ d[136] ^ d[137] ^ d[138] ^ d[141] ^ d[143] ^ d[147] ^ d[148] ^ d[149] ^ d[151] ^ d[153] ^ d[155] ^ d[158] ^ d[160] ^ d[164] ^ d[165] ^ d[166] ^ d[168] ^ d[169] ^ d[171] ^ d[172] ^ d[173] ^ d[177] ^ d[180] ^ d[181] ^ d[185] ^ d[186] ^ d[187] ^ d[188] ^ d[190] ^ d[192] ^ d[194] ^ d[196] ^ d[198] ^ d[199] ^ d[201] ^ d[203] ^ d[205] ^ d[206] ^ d[208] ^ d[209] ^ d[212] ^ d[213] ^ d[218] ^ d[225] ^ d[230] ^ d[232] ^ d[233] ^ d[234] ^ d[235] ^ d[238] ^ d[240] ^ d[242] ^ d[244] ^ d[245] ^ d[246] ^ d[247] ^ d[248] ^ d[249] ^ d[250] ^ d[252] ^ d[254]; + crc_256[14] = d[0] ^ d[1] ^ d[4] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[11] ^ d[16] ^ d[17] ^ d[21] ^ d[22] ^ d[23] ^ d[24] ^ d[26] ^ d[27] ^ d[30] ^ d[33] ^ d[34] ^ d[36] ^ d[40] ^ d[44] ^ d[49] ^ d[50] ^ d[52] ^ d[53] ^ d[54] ^ d[58] ^ d[59] ^ d[60] ^ d[62] ^ d[67] ^ d[68] ^ d[73] ^ d[75] ^ d[76] ^ d[80] ^ d[81] ^ d[82] ^ d[84] ^ d[86] ^ d[87] ^ d[88] ^ d[89] ^ d[90] ^ d[93] ^ d[95] ^ d[96] ^ d[97] ^ d[102] ^ d[109] ^ d[110] ^ d[111] ^ d[112] ^ d[117] ^ d[118] ^ d[119] ^ d[121] ^ d[122] ^ d[123] ^ d[126] ^ d[129] ^ d[131] ^ d[132] ^ d[134] ^ d[136] ^ d[137] ^ d[142] ^ d[148] ^ d[149] ^ d[151] ^ d[152] ^ d[153] ^ d[155] ^ d[156] ^ d[157] ^ d[158] ^ d[160] ^ d[161] ^ d[162] ^ d[163] ^ d[164] ^ d[167] ^ d[170] ^ d[173] ^ d[174] ^ d[175] ^ d[176] ^ d[177] ^ d[179] ^ d[182] ^ d[184] ^ d[187] ^ d[188] ^ d[190] ^ d[191] ^ d[192] ^ d[194] ^ d[195] ^ d[196] ^ d[198] ^ d[199] ^ d[201] ^ d[202] ^ d[203] ^ d[205] ^ d[206] ^ d[208] ^ d[209] ^ d[211] ^ d[214] ^ d[216] ^ d[218] ^ d[219] ^ d[220] ^ d[221] ^ d[222] ^ d[223] ^ d[224] ^ d[225] ^ d[227] ^ d[229] ^ d[233] ^ d[234] ^ d[239] ^ d[243] ^ d[246] ^ d[247] ^ d[250] ^ d[251] ^ d[252] ^ d[254] ^ d[255]; + crc_256[15] = d[1] ^ d[2] ^ d[5] ^ d[6] ^ d[7] ^ d[8] ^ d[9] ^ d[12] ^ d[17] ^ d[18] ^ d[22] ^ d[23] ^ d[24] ^ d[25] ^ d[27] ^ d[28] ^ d[31] ^ d[34] ^ d[35] ^ d[37] ^ d[41] ^ d[45] ^ d[50] ^ d[51] ^ d[53] ^ d[54] ^ d[55] ^ d[59] ^ d[60] ^ d[61] ^ d[63] ^ d[68] ^ d[69] ^ d[74] ^ d[76] ^ d[77] ^ d[81] ^ d[82] ^ d[83] ^ d[85] ^ d[87] ^ d[88] ^ d[89] ^ d[90] ^ d[91] ^ d[94] ^ d[96] ^ d[97] ^ d[98] ^ d[103] ^ d[110] ^ d[111] ^ d[112] ^ d[113] ^ d[118] ^ d[119] ^ d[120] ^ d[122] ^ d[123] ^ d[124] ^ d[127] ^ d[130] ^ d[132] ^ d[133] ^ d[135] ^ d[137] ^ d[138] ^ d[143] ^ d[149] ^ d[150] ^ d[152] ^ d[153] ^ d[154] ^ d[156] ^ d[157] ^ d[158] ^ d[159] ^ d[161] ^ d[162] ^ d[163] ^ d[164] ^ d[165] ^ d[168] ^ d[171] ^ d[174] ^ d[175] ^ d[176] ^ d[177] ^ d[178] ^ d[180] ^ d[183] ^ d[185] ^ d[188] ^ d[189] ^ d[191] ^ d[192] ^ d[193] ^ d[195] ^ d[196] ^ d[197] ^ d[199] ^ d[200] ^ d[202] ^ d[203] ^ d[204] ^ d[206] ^ d[207] ^ d[209] ^ d[210] ^ d[212] ^ d[215] ^ d[217] ^ d[219] ^ d[220] ^ d[221] ^ d[222] ^ d[223] ^ d[224] ^ d[225] ^ d[226] ^ d[228] ^ d[230] ^ d[234] ^ d[235] ^ d[240] ^ d[244] ^ d[247] ^ d[248] ^ d[251] ^ d[252] ^ d[253] ^ d[255]; + end + endfunction + + assign adc_crc_err = (adc_crc == adc_crc_res) ? 1'b0 : 1'b1; + + // FSM state register + + always @(posedge clk) begin + if (rstn == 1'b0) begin + transfer_state <= 3'h0; + end else begin + transfer_state <= transfer_state_next; + end + end + + // FSM next state logic + + always @(*) begin + case (transfer_state) + IDLE : begin + transfer_state_next <= (start_transfer_s == 1'b1) ? CS_LOW : IDLE; + end + CS_LOW : begin + transfer_state_next <= CNTRL_LOW; + end + CNTRL_LOW : begin + transfer_state_next <= (width_counter == 4'd3) ? CNTRL_HIGH : CNTRL_LOW; + end + CNTRL_HIGH : begin + transfer_state_next <= (adc_config_enable_d | rd_conv_d) ? CS_HIGH : CNTRL_HIGH; + end + CS_HIGH : begin + transfer_state_next <= (channel_counter == nr_rd_burst || adc_config_enable_d) ? IDLE : CNTRL_LOW; + end + default : begin + transfer_state_next <= IDLE; + end + endcase + end + + // data valid for the register access + + assign rd_valid_s = (transfer_state == CNTRL_HIGH && rd_conv_d == 1'b1) ? 1'b1 : 1'b0; + assign adc_ctrl_status = (transfer_state == CNTRL_HIGH && (adc_config_enable_d == 1'b1 && adc_config_rd_wr == 1'b1)) ? 1'b1 : 1'b0; + // FSM output logic + + assign db_o = wr_data; + + assign rd_new_data_s = rd_valid_s & ~rd_valid_d; + + always @(posedge clk) begin + rd_data <= ~rd_n ? db_i : rd_data; + rd_valid <= rd_new_data_s; + rd_valid_d <= rd_valid_s; + end + + assign adc_status_er_5b = adc_status_0[7:3] | adc_status_1[7:3] | adc_status_2[7:3] | adc_status_3[7:3] | adc_status_4[7:3] | adc_status_5[7:3] | adc_status_6[7:3] | adc_status_7[7:3]; + assign adc_status_er = adc_status_er_5b[0] | adc_status_er_5b[1] | adc_status_er_5b[2] | adc_status_er_5b[3] | adc_status_er_5b[4]; + assign adc_status = (adc_config_mode == STATUS_HEADER || adc_config_mode == CRC_STATUS) ? (adc_status_er ? 1'b0 : 1'b1) : 1'b1; + + // clear adc_crc* signals if the adc_config_mode is STATUS_HEADER or SIMPLE + + assign adc_crc = (adc_config_mode == STATUS_HEADER || adc_config_mode == SIMPLE) ? 16'h0 : adc_crc_r; + assign adc_crc_res = (adc_config_mode == STATUS_HEADER || adc_config_mode == SIMPLE) ? 16'h0 : adc_crc_res_r; + + assign cs_n = (transfer_state == IDLE) ? 1'b1 : 1'b0; + assign db_t = (adc_config_enable_d == 1'b1 && adc_config_rd_wr == 1'b0) ? 1'b0 : 1'b1; + assign rd_n = (transfer_state == CNTRL_LOW) && (rd_conv_d == 1'b1 || (adc_config_enable_d == 1'b1 && adc_config_rd_wr == 1'b1)) ? 1'b0 : 1'b1; + assign wr_n = (transfer_state == CNTRL_LOW) && (adc_config_enable_d == 1'b1 && adc_config_rd_wr == 1'b0) ? 1'b0 : 1'b1; + +endmodule diff --git a/adi_library/axi_ad7606x/axi_ad7606x_ip.tcl b/adi_library/axi_ad7606x/axi_ad7606x_ip.tcl new file mode 100644 index 00000000..cd52d7e4 --- /dev/null +++ b/adi_library/axi_ad7606x/axi_ad7606x_ip.tcl @@ -0,0 +1,105 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create axi_ad7606x + +adi_ip_files axi_ad7606x [list \ + "$ad_hdl_dir/library/common/ad_edge_detect.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "axi_ad7606x_16b_pif.v" \ + "axi_ad7606x_18b_pif.v" \ + "axi_ad7606x.v" ] + +adi_ip_properties axi_ad7606x + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad7606x} [ipx::current_core] + +ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +set reset_intf [ipx::infer_bus_interface adc_reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]] +set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_intf] +set_property value "ACTIVE_HIGH" $reset_polarity + +set cc [ipx::current_core] + +set_property display_name "AXI AD7606X" $cc +set_property description "AXI AD7606X HDL interface" $cc + +## define external_clk port as clock interface +adi_add_bus external_clk slave \ + "xilinx.com:signal:clock_rtl:1.0" \ + "xilinx.com:signal:clock:1.0" \ + [list {"external_clk" "CLK"} ] + +adi_set_ports_dependency "external_clk" \ + "(spirit:decode(id('MODELPARAM_VALUE.EXTERNAL_CLK')) = 1)" 0 + +## parameter validation + +set_property -dict [list \ + "value_format" "bool" \ + "value" "true" \ + ] \ +[ipx::get_hdl_parameters EXTERNAL_CLK -of_objects $cc] + +## customize XGUI layout + +## remove the automatically generated GUI page + +ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] +ipx::save_core $cc + +## create a new GUI page + +ipgui::add_page -name {AXI AD7606X} -component $cc -display_name {AXI AD7606X} +set page0 [ipgui::get_pagespec -name "AXI AD7606X" -component $cc] + +ipgui::add_param -name "EXTERNAL_CLK" -component $cc -parent $page0 +set_property -dict [list \ + "display_name" "EXTERNAL_CLK" \ + "tooltip" "External clock for the ADC" \ + "widget" "checkBox" \ +] [ipgui::get_guiparamspec -name "EXTERNAL_CLK" -component $cc] + +ipgui::add_param -name "DEV_CONFIG" -component $cc -parent $page0 +set_property -dict [list \ + "widget" "comboBox" \ + "display_name" "Device Type Selection" \ +] [ipgui::get_guiparamspec -name "DEV_CONFIG" -component $cc] + +set_property -dict [list \ + "value_validation_type" "pairs" \ + "value_validation_pairs" { \ + "AD7606B" "0" \ + "AD7606C-16" "1" \ + "AD7606C-18" "2" \ + } \ +] [ipx::get_user_parameters DEV_CONFIG -of_objects $cc] + +adi_add_auto_fpga_spec_params + +## save the modifications + +ipx::create_xgui_files $cc +ipx::save_core $cc diff --git a/adi_library/axi_ad7606x/component.xml b/adi_library/axi_ad7606x/component.xml new file mode 100644 index 00000000..2616960a --- /dev/null +++ b/adi_library/axi_ad7606x/component.xml @@ -0,0 +1,1364 @@ + + + analog.com + user + axi_ad7606x + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + adc_clk + + + + + + + CLK + + + adc_clk + + + + + + ASSOCIATED_RESET + adc_reset + + + + + adc_reset + + + + + + + RST + + + adc_reset + + + + + + POLARITY + ACTIVE_HIGH + + + + + external_clk + + + + + + + CLK + + + external_clk + + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_ad7606x + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 499fbfb9 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_ad7606x + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + b5e2e2ed + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + c7c7b169 + + + + + + + rx_cs_n + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_db_o + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_db_i + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_db_t + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_rd_n + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_wr_n + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + external_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + rx_busy + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + first_data + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_dovf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_0 + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_1 + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_2 + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_3 + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_4 + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_5 + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_6 + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_7 + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_2 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_3 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_4 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_5 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_6 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_7 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_reset + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + ID + Id + 0 + + + DEV_CONFIG + Dev Config + 0 + + + ADC_CH_DW + Adc Ch Dw + 16 + + + ADC_N_BITS + Adc N Bits + 16 + + + EXTERNAL_CLK + External Clk + true + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_5f95957e + 0 + 1 + 2 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../xilinx/common/up_clock_mon_constr.xdc + xdc + + + ../common/ad_datafmt.v + verilogSource + + + ../common/ad_edge_detect.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + axi_ad7606x_16b_pif.v + verilogSource + + + axi_ad7606x_18b_pif.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad7606x.v + verilogSource + CHECKSUM_461f9622 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_datafmt.v + verilogSource + + + ../common/ad_edge_detect.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + axi_ad7606x_16b_pif.v + verilogSource + + + axi_ad7606x_18b_pif.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad7606x.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_ad7606x_v1_0.tcl + tclSource + CHECKSUM_3f71ec0b + XGUI_VERSION_2 + + + + AXI AD7606X HDL interface + + + ID + Id + 0 + + + DEV_CONFIG + Device Type Selection + 0 + + + ADC_CH_DW + Adc Ch Dw + 16 + + + ADC_N_BITS + Adc N Bits + 16 + + + EXTERNAL_CLK + EXTERNAL_CLK + 0 + + + Component_Name + axi_ad7606x_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + AXI AD7606X + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_ad7606x + 1 + 2024-01-14T03:38:47Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_ad7606x/xgui/axi_ad7606x_v1_0.tcl b/adi_library/axi_ad7606x/xgui/axi_ad7606x_v1_0.tcl new file mode 100644 index 00000000..1e935d3d --- /dev/null +++ b/adi_library/axi_ad7606x/xgui/axi_ad7606x_v1_0.tcl @@ -0,0 +1,83 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set AXI_AD7606X [ipgui::add_page $IPINST -name "AXI AD7606X"] + set EXTERNAL_CLK [ipgui::add_param $IPINST -name "EXTERNAL_CLK" -parent ${AXI_AD7606X} -widget checkBox] + set_property tooltip {External clock for the ADC} ${EXTERNAL_CLK} + ipgui::add_param $IPINST -name "DEV_CONFIG" -parent ${AXI_AD7606X} -widget comboBox + + +} + +proc update_PARAM_VALUE.ADC_CH_DW { PARAM_VALUE.ADC_CH_DW } { + # Procedure called to update ADC_CH_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADC_CH_DW { PARAM_VALUE.ADC_CH_DW } { + # Procedure called to validate ADC_CH_DW + return true +} + +proc update_PARAM_VALUE.ADC_N_BITS { PARAM_VALUE.ADC_N_BITS } { + # Procedure called to update ADC_N_BITS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADC_N_BITS { PARAM_VALUE.ADC_N_BITS } { + # Procedure called to validate ADC_N_BITS + return true +} + +proc update_PARAM_VALUE.DEV_CONFIG { PARAM_VALUE.DEV_CONFIG } { + # Procedure called to update DEV_CONFIG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEV_CONFIG { PARAM_VALUE.DEV_CONFIG } { + # Procedure called to validate DEV_CONFIG + return true +} + +proc update_PARAM_VALUE.EXTERNAL_CLK { PARAM_VALUE.EXTERNAL_CLK } { + # Procedure called to update EXTERNAL_CLK when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.EXTERNAL_CLK { PARAM_VALUE.EXTERNAL_CLK } { + # Procedure called to validate EXTERNAL_CLK + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.DEV_CONFIG { MODELPARAM_VALUE.DEV_CONFIG PARAM_VALUE.DEV_CONFIG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEV_CONFIG}] ${MODELPARAM_VALUE.DEV_CONFIG} +} + +proc update_MODELPARAM_VALUE.ADC_CH_DW { MODELPARAM_VALUE.ADC_CH_DW PARAM_VALUE.ADC_CH_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADC_CH_DW}] ${MODELPARAM_VALUE.ADC_CH_DW} +} + +proc update_MODELPARAM_VALUE.ADC_N_BITS { MODELPARAM_VALUE.ADC_N_BITS PARAM_VALUE.ADC_N_BITS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADC_N_BITS}] ${MODELPARAM_VALUE.ADC_N_BITS} +} + +proc update_MODELPARAM_VALUE.EXTERNAL_CLK { MODELPARAM_VALUE.EXTERNAL_CLK PARAM_VALUE.EXTERNAL_CLK } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.EXTERNAL_CLK}] ${MODELPARAM_VALUE.EXTERNAL_CLK} +} + diff --git a/adi_library/axi_ad7616/Makefile b/adi_library/axi_ad7616/Makefile new file mode 100644 index 00000000..d49c6265 --- /dev/null +++ b/adi_library/axi_ad7616/Makefile @@ -0,0 +1,16 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_ad7616 + +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += axi_ad7616.v +GENERIC_DEPS += axi_ad7616_control.v +GENERIC_DEPS += axi_ad7616_pif.v + +XILINX_DEPS += axi_ad7616_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_ad7616/axi_ad7616.v b/adi_library/axi_ad7616/axi_ad7616.v new file mode 100644 index 00000000..6b69f1c7 --- /dev/null +++ b/adi_library/axi_ad7616/axi_ad7616.v @@ -0,0 +1,210 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad7616 #( + + parameter ID = 0 +) ( + + // physical data interface + + output rx_cs_n, + output [15:0] rx_db_o, + input [15:0] rx_db_i, + output rx_db_t, + output rx_rd_n, + output rx_wr_n, + + // physical control interface + + input rx_trigger, + + // AXI Slave Memory Map + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + + // Write FIFO interface + + output adc_valid, + output [15:0] adc_data, + output adc_sync +); + + // internal registers + + reg up_wack = 1'b0; + reg up_rack = 1'b0; + reg [31:0] up_rdata = 32'b0; + + // internal signals + + wire up_clk; + wire up_rstn; + wire up_rst; + wire up_rreq_s; + wire [13:0] up_raddr_s; + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + + wire up_wack_cntrl_s; + wire up_rack_cntrl_s; + wire [31:0] up_rdata_cntrl_s; + + wire trigger_s; + + wire rd_req_s; + wire wr_req_s; + wire [15:0] wr_data_s; + wire [15:0] rd_data_s; + wire rd_valid_s; + wire [ 4:0] burst_length_s; + + // defaults + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + assign up_rst = ~s_axi_aresetn; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_wack <= up_wack_cntrl_s; + up_rack <= up_rack_cntrl_s; + up_rdata <= up_rdata_cntrl_s; + end + end + + axi_ad7616_pif i_ad7616_parallel_interface ( + .cs_n (rx_cs_n), + .db_o (rx_db_o), + .db_i (rx_db_i), + .db_t (rx_db_t), + .rd_n (rx_rd_n), + .wr_n (rx_wr_n), + .adc_data (adc_data), + .adc_valid (adc_valid), + .adc_sync (adc_sync), + .end_of_conv (rx_trigger), + .burst_length(burst_length_s), + .clk (up_clk), + .rstn (up_rstn), + .rd_req (rd_req_s), + .wr_req (wr_req_s), + .wr_data (wr_data_s), + .rd_data (rd_data_s), + .rd_valid (rd_valid_s)); + + axi_ad7616_control #( + .ID(ID) + ) i_ad7616_control ( + .up_burst_length (burst_length_s), + .up_read_data (rd_data_s), + .up_read_valid (rd_valid_s), + .up_write_data (wr_data_s), + .up_read_req (rd_req_s), + .up_write_req (wr_req_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_cntrl_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_cntrl_s), + .up_rack (up_rack_cntrl_s)); + + // up bus interface + + up_axi #( + .AXI_ADDRESS_WIDTH (16) + ) i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ad7616/axi_ad7616.xpr b/adi_library/axi_ad7616/axi_ad7616.xpr new file mode 100644 index 00000000..aae0d225 --- /dev/null +++ b/adi_library/axi_ad7616/axi_ad7616.xpr @@ -0,0 +1,420 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_ad7616/axi_ad7616_control.v b/adi_library/axi_ad7616/axi_ad7616_control.v new file mode 100644 index 00000000..6c842ce4 --- /dev/null +++ b/adi_library/axi_ad7616/axi_ad7616_control.v @@ -0,0 +1,159 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad7616_control #( + + parameter ID = 0 +) ( + + // control signals + + input [15:0] up_read_data, + input up_read_valid, + output reg [15:0] up_write_data, + output up_read_req, + output up_write_req, + + output reg [ 4:0] up_burst_length, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack +); + + localparam PCORE_VERSION = 'h00001002; + localparam POS_EDGE = 0; + localparam NEG_EDGE = 1; + + // internal signals + + reg [31:0] up_scratch = 32'b0; + reg up_resetn = 1'b0; + reg up_cnvst_en = 1'b0; + reg [31:0] up_conv_rate = 32'b0; + + reg [31:0] cnvst_counter = 32'b0; + reg [ 3:0] pulse_counter = 8'b0; + reg cnvst_buf = 1'b0; + reg cnvst_pulse = 1'b0; + reg [ 2:0] chsel_ff = 3'b0; + + wire up_rst; + wire up_rack_s; + + wire [31:0] up_read_data_s; + wire up_read_valid_s; + + // the up_[read/write]_data interfaces are valid just in parallel mode + + assign up_read_valid_s = up_read_valid; + assign up_read_data_s = {16'h0, up_read_data}; + + // processor write interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 1'h0; + up_scratch <= 32'b0; + up_resetn <= 1'b0; + up_cnvst_en <= 1'b0; + up_conv_rate <= 32'b0; + up_burst_length <= 5'h0; + up_write_data <= 16'h0; + end else begin + up_wack <= up_wreq; + if ((up_wreq == 1'b1) && (up_waddr[8:0] == 9'h102)) begin + up_scratch <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr[8:0] == 9'h110)) begin + up_resetn <= up_wdata[0]; + up_cnvst_en <= up_wdata[1]; + end + if ((up_wreq == 1'b1) && (up_waddr[8:0] == 9'h111)) begin + up_conv_rate <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr[8:0] == 9'h112)) begin + up_burst_length <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr[8:0] == 9'h114)) begin + up_write_data <= up_wdata; + end + end + end + + assign up_write_req = (up_waddr[8:0] == 9'h114) ? up_wreq : 1'h0; + + // processor read interface + + assign up_rack_s = (up_raddr[8:0] == 9'h113) ? up_read_valid_s : up_rreq; + assign up_read_req = (up_raddr[8:0] == 9'h113) ? up_rreq : 1'b0; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 1'b0; + up_rdata <= 32'b0; + end else begin + up_rack <= up_rack_s; + if (up_rack_s == 1'b1) begin + case (up_raddr[8:0]) + 9'h100 : up_rdata <= PCORE_VERSION; + 9'h101 : up_rdata <= ID; + 9'h102 : up_rdata <= up_scratch; + 9'h110 : up_rdata <= {29'b0, up_cnvst_en, up_resetn}; + 9'h111 : up_rdata <= up_conv_rate; + 9'h112 : up_rdata <= {27'b0, up_burst_length}; + 9'h113 : up_rdata <= up_read_data_s; + default : up_rdata <= 'h0; + endcase + end + end + end + + // instantiations + + assign up_rst = ~up_rstn; + +endmodule diff --git a/adi_library/axi_ad7616/axi_ad7616_ip.tcl b/adi_library/axi_ad7616/axi_ad7616_ip.tcl new file mode 100644 index 00000000..ca1c98e2 --- /dev/null +++ b/adi_library/axi_ad7616/axi_ad7616_ip.tcl @@ -0,0 +1,25 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create axi_ad7616 +adi_ip_files axi_ad7616 [list \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "axi_ad7616_control.v" \ + "axi_ad7616_pif.v" \ + "axi_ad7616.v" ] + +adi_ip_properties axi_ad7616 + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad7616} [ipx::current_core] + +set_property DRIVER_VALUE "0" [ipx::get_ports rx_db_i] + +ipx::save_core [ipx::current_core] diff --git a/adi_library/axi_ad7616/axi_ad7616_pif.v b/adi_library/axi_ad7616/axi_ad7616_pif.v new file mode 100644 index 00000000..7e131db0 --- /dev/null +++ b/adi_library/axi_ad7616/axi_ad7616_pif.v @@ -0,0 +1,215 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad7616_pif #( + + parameter UP_ADDRESS_WIDTH = 14 +) ( + + // physical interface + + output cs_n, + output [15:0] db_o, + input [15:0] db_i, + output db_t, + output rd_n, + output wr_n, + + // FIFO interface + + output [15:0] adc_data, + output adc_valid, + output reg adc_sync, + + // end of convertion + + input end_of_conv, + input [ 4:0] burst_length, + + // register access + + input clk, + input rstn, + input rd_req, + input wr_req, + input [15:0] wr_data, + output reg [15:0] rd_data, + output reg rd_valid +); + + // state registers + + localparam [ 2:0] IDLE = 3'h0, + CS_LOW = 3'h1, + CNTRL0_LOW = 3'h2, + CNTRL0_HIGH = 3'h3, + CNTRL1_LOW = 3'h4, + CNTRL1_HIGH = 3'h5, + CS_HIGH = 3'h6; + + // internal registers + + reg [ 2:0] transfer_state = 3'h0; + reg [ 2:0] transfer_state_next = 3'h0; + reg [ 1:0] width_counter = 2'h0; + reg [ 4:0] burst_counter = 5'h0; + + reg wr_req_d = 1'h0; + reg rd_req_d = 1'h0; + reg rd_conv_d = 1'h0; + + reg xfer_req_d = 1'h0; + + reg rd_valid_d = 1'h0; + + // internal wires + + wire start_transfer_s; + wire rd_valid_s; + + // FSM state register + + always @(posedge clk) begin + if (rstn == 1'b0) begin + transfer_state <= 3'h0; + end else begin + transfer_state <= transfer_state_next; + end + end + + // counters to control the RD_N and WR_N lines + + assign start_transfer_s = end_of_conv | rd_req | wr_req; + + always @(posedge clk) begin + if (rstn == 1'b0) begin + width_counter <= 2'h0; + end else begin + if((transfer_state == CNTRL0_LOW) || (transfer_state == CNTRL0_HIGH) || + (transfer_state == CNTRL1_LOW) || (transfer_state == CNTRL1_HIGH)) + width_counter <= width_counter + 1; + else + width_counter <= 2'h0; + end + end + + always @(posedge clk) begin + if (rstn == 1'b0) begin + burst_counter <= 2'h0; + end else begin + if (transfer_state == CS_HIGH) + burst_counter <= burst_counter + 1; + else if (transfer_state == IDLE) + burst_counter <= 5'h0; + end + end + + always @(negedge clk) begin + if (transfer_state == IDLE) begin + wr_req_d <= wr_req; + rd_req_d <= rd_req; + rd_conv_d <= end_of_conv; + end + end + + // FSM next state logic + + always @(*) begin + case (transfer_state) + IDLE : begin + transfer_state_next <= (start_transfer_s == 1'b1) ? CS_LOW : IDLE; + end + CS_LOW : begin + transfer_state_next <= CNTRL0_LOW; + end + CNTRL0_LOW : begin + transfer_state_next <= (width_counter != 2'b11) ? CNTRL0_LOW : CNTRL0_HIGH; + end + CNTRL0_HIGH : begin + transfer_state_next <= (width_counter != 2'b11) ? CNTRL0_HIGH : + ((wr_req_d == 1'b1) || (rd_req_d == 1'b1)) ? CS_HIGH : CNTRL1_LOW; + end + CNTRL1_LOW : begin + transfer_state_next <= (width_counter != 2'b11) ? CNTRL1_LOW : CNTRL1_HIGH; + end + CNTRL1_HIGH : begin + transfer_state_next <= (width_counter != 2'b11) ? CNTRL1_HIGH : CS_HIGH; + end + CS_HIGH : begin + transfer_state_next <= (burst_length == burst_counter) ? IDLE : CNTRL0_LOW; + end + default : begin + transfer_state_next <= IDLE; + end + endcase + end + + // data valid for the register access and m_axis interface + + assign rd_valid_s = (((transfer_state == CNTRL0_HIGH) || (transfer_state == CNTRL1_HIGH)) && + ((rd_req_d == 1'b1) || (rd_conv_d == 1'b1))) ? 1'b1 : 1'b0; + + // FSM output logic + + assign db_o = wr_data; + + always @(posedge clk) begin + rd_data <= (rd_valid_s & ~rd_valid_d) ? db_i : rd_data; + rd_valid_d <= rd_valid_s; + rd_valid <= rd_valid_s & ~rd_valid_d; + end + + assign adc_valid = rd_valid; + assign adc_data = rd_data; + + assign cs_n = (transfer_state == IDLE) ? 1'b1 : 1'b0; + assign db_t = ~wr_req_d; + assign rd_n = (((transfer_state == CNTRL0_LOW) && ((rd_conv_d == 1'b1) || rd_req_d == 1'b1)) || + (transfer_state == CNTRL1_LOW)) ? 1'b0 : 1'b1; + assign wr_n = ((transfer_state == CNTRL0_LOW) && (wr_req_d == 1'b1)) ? 1'b0 : 1'b1; + + // sync will be asserted at the first valid data right after the convertion start + + always @(posedge clk) begin + if (end_of_conv == 1'b1) begin + adc_sync <= 1'b1; + end else if (rd_valid == 1'b1) begin + adc_sync <= 1'b0; + end + end + +endmodule diff --git a/adi_library/axi_ad7616/component.xml b/adi_library/axi_ad7616/component.xml new file mode 100644 index 00000000..24548d5f --- /dev/null +++ b/adi_library/axi_ad7616/component.xml @@ -0,0 +1,893 @@ + + + analog.com + user + axi_ad7616 + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_ad7616 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + c191877d + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_ad7616 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + c191877d + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 6a7455d5 + + + + + + + rx_cs_n + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_db_o + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_db_i + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + rx_db_t + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_rd_n + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_wr_n + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_trigger + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_sync + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + ID + Id + 0 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + axi_ad7616_control.v + verilogSource + + + axi_ad7616_pif.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + axi_ad7616.v + verilogSource + CHECKSUM_2739560c + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + axi_ad7616_control.v + verilogSource + + + axi_ad7616_pif.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + axi_ad7616.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_ad7616_v1_0.tcl + tclSource + CHECKSUM_6a7455d5 + XGUI_VERSION_2 + + + + axi_ad7616_v1_0 + + + ID + Id + 0 + + + Component_Name + axi_ad7616_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_ad7616_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_ad7616 + 1 + 2024-01-14T03:38:56Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_ad7616/xgui/axi_ad7616_v1_0.tcl b/adi_library/axi_ad7616/xgui/axi_ad7616_v1_0.tcl new file mode 100644 index 00000000..2b091276 --- /dev/null +++ b/adi_library/axi_ad7616/xgui/axi_ad7616_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + diff --git a/adi_library/axi_ad7768/Makefile b/adi_library/axi_ad7768/Makefile new file mode 100644 index 00000000..4a708f1b --- /dev/null +++ b/adi_library/axi_ad7768/Makefile @@ -0,0 +1,32 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_ad7768 + +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_adc_channel.v +GENERIC_DEPS += ../common/up_adc_common.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_ad7768.v +GENERIC_DEPS += axi_ad7768_if.v + +XILINX_DEPS += ../common/ad_datafmt.v +XILINX_DEPS += ../common/up_delay_cntrl.v +XILINX_DEPS += ../xilinx/common/ad_data_clk.v +XILINX_DEPS += ../xilinx/common/ad_data_in.v +XILINX_DEPS += ../xilinx/common/ad_dcfilter.v +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_ad7768_ip.tcl + +INTEL_DEPS += axi_ad7768_hw.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_ad7768/axi_ad7768.v b/adi_library/axi_ad7768/axi_ad7768.v new file mode 100644 index 00000000..0e27f0d5 --- /dev/null +++ b/adi_library/axi_ad7768/axi_ad7768.v @@ -0,0 +1,364 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns / 1ps + +module axi_ad7768 #( + parameter ID = 0, + parameter NUM_CHANNELS = 8 +) ( + + input adc_dovf, + input clk_in, + input ready_in, + input [ 7:0] data_in, + input adc_sshot, + output adc_enable_0, + output adc_enable_1, + output adc_enable_2, + output adc_enable_3, + output adc_enable_4, + output adc_enable_5, + output adc_enable_6, + output adc_enable_7, + output adc_valid_0, + output adc_valid_1, + output adc_valid_2, + output adc_valid_3, + output adc_valid_4, + output adc_valid_5, + output adc_valid_6, + output adc_valid_7, + output [31:0] adc_data_0, + output [31:0] adc_data_1, + output [31:0] adc_data_2, + output [31:0] adc_data_3, + output [31:0] adc_data_4, + output [31:0] adc_data_5, + output [31:0] adc_data_6, + output [31:0] adc_data_7, + output [31:0] adc_data, + + output adc_clk, + output adc_sync, + output adc_reset, + output adc_valid, + output [ 7:0] adc_crc_ch_mismatch, + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready +); + + // internal registers + + reg [31:0] up_rdata = 'd0; + reg up_rack = 'd0; + reg up_wack = 'd0; + reg [31:0] up_rdata_r; + reg up_rack_r; + reg up_wack_r; + + // internal signals + + wire adc_rst_s; + wire up_rstn; + wire up_clk; + wire [13:0] up_waddr_s; + wire [13:0] up_raddr_s; + wire adc_clk_s; + wire up_wreq_s; + wire up_rreq_s; + wire [13:0] up_addr_s; + wire [31:0] up_wdata_s; + wire [31:0] up_rdata_s[0:8]; + wire [8:0] up_rack_s; + wire [8:0] up_wack_s; + wire [7:0] adc_enable; + wire [4:0] adc_num_lanes; + wire adc_crc_enable; + wire [7:0] adc_status_header[0:7]; + wire [7:0] adc_crc_err; + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + assign adc_clk = adc_clk_s; + assign adc_reset = adc_rst_s; + + assign adc_enable_0 = adc_enable[0]; + assign adc_enable_1 = adc_enable[1]; + assign adc_enable_2 = adc_enable[2]; + assign adc_enable_3 = adc_enable[3]; + assign adc_enable_4 = adc_enable[4]; + assign adc_enable_5 = adc_enable[5]; + assign adc_enable_6 = adc_enable[6]; + assign adc_enable_7 = adc_enable[7]; + assign adc_valid_0 = adc_valid; + assign adc_valid_1 = adc_valid; + assign adc_valid_2 = adc_valid; + assign adc_valid_3 = adc_valid; + assign adc_valid_4 = adc_valid; + assign adc_valid_5 = adc_valid; + assign adc_valid_6 = adc_valid; + assign adc_valid_7 = adc_valid; + assign adc_crc_ch_mismatch = adc_crc_err; + + integer j; + + always @(*) begin + up_rdata_r = 'h00; + up_rack_r = 'h00; + up_wack_r = 'h00; + for (j = 0; j <= 8; j=j+1) begin + up_rack_r = up_rack_r | up_rack_s[j]; + up_wack_r = up_wack_r | up_wack_s[j]; + up_rdata_r = up_rdata_r | up_rdata_s[j]; + end + end + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_rdata <= up_rdata_r; + up_rack <= up_rack_r; + up_wack <= up_wack_r; + end + end + + // adc channels + + generate + genvar i; + for (i = 0; i < NUM_CHANNELS; i=i+1) begin : ad7768_channels + up_adc_channel #( + .CHANNEL_ID(i) + ) i_up_adc_channel ( + .adc_clk (adc_clk_s), + .adc_rst (adc_rst_s), + .adc_enable (adc_enable[i]), + .adc_iqcor_enb (), + .adc_dcfilt_enb (), + .adc_dfmt_se (), + .adc_dfmt_type (), + .adc_dfmt_enable (), + .adc_dcfilt_offset (), + .adc_dcfilt_coeff (), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pnseq_sel (), + .adc_data_sel (), + .adc_pn_err (1'b0), + .adc_pn_oos (1'b0), + .adc_or (1'b0), + .adc_read_data ('d0), + .adc_status_header(adc_status_header[i]), + .adc_crc_err(adc_crc_err[i]), + .up_adc_pn_err (), + .up_adc_pn_oos (), + .up_adc_or (), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd32), + .adc_usr_datatype_bits (8'd32), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[i]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[i]), + .up_rack (up_rack_s[i])); + end + endgenerate + + // adc interface + + axi_ad7768_if #( + .NUM_CHANNELS(NUM_CHANNELS) + ) i_ad7768_if ( + .clk_in (clk_in), + .ready_in (ready_in), + .data_in (data_in), + .adc_clk (adc_clk_s), + .adc_valid (adc_valid), + .adc_data (adc_data), + .adc_sshot(adc_sshot), + .adc_format(adc_num_lanes), + .adc_crc_enable(adc_crc_enable), + .adc_sync(adc_sync), + .adc_data_0 (adc_data_0), + .adc_data_1 (adc_data_1), + .adc_data_2 (adc_data_2), + .adc_data_3 (adc_data_3), + .adc_data_4 (adc_data_4), + .adc_data_5 (adc_data_5), + .adc_data_6 (adc_data_6), + .adc_data_7 (adc_data_7), + .adc_crc_ch_mismatch(adc_crc_err), + .adc_status_0(adc_status_header[0]), + .adc_status_1(adc_status_header[1]), + .adc_status_2(adc_status_header[2]), + .adc_status_3(adc_status_header[3]), + .adc_status_4(adc_status_header[4]), + .adc_status_5(adc_status_header[5]), + .adc_status_6(adc_status_header[6]), + .adc_status_7(adc_status_header[7])); + + // adc up common + + up_adc_common #( + .ID(ID) + ) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk_s), + .adc_rst (adc_rst_s), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status ('h00), + .adc_sync_status (1'b1), + .adc_status_ovf (adc_dovf), + .adc_clk_ratio (32'd1), + .adc_start_code (), + .adc_sref_sync (), + .adc_sync (), + .adc_ext_sync_arm(), + .adc_ext_sync_disarm(), + .adc_ext_sync_manual_req(), + .adc_custom_control(), + .adc_sdr_ddr_n(), + .adc_symb_op(), + .adc_symb_8_16b(), + .adc_num_lanes(adc_num_lanes), + .adc_crc_enable(adc_crc_enable), + .up_pps_rcounter (32'b0), + .up_pps_status (1'b0), + .up_pps_irq_mask (), + .up_adc_ce (), + .up_status_pn_err (1'b0), + .up_status_pn_oos (1'b0), + .up_status_or (1'b0), + .up_adc_r1_mode(), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .adc_config_wr (), + .adc_config_ctrl (), + .adc_config_rd ('d0), + .adc_ctrl_status ('d0), + .up_usr_chanmax_out (), + .up_usr_chanmax_in (NUM_CHANNELS), + .up_adc_gpio_in (32'b0), + .up_adc_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[NUM_CHANNELS]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[NUM_CHANNELS]), + .up_rack (up_rack_s[NUM_CHANNELS])); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ad7768/axi_ad7768.xpr b/adi_library/axi_ad7768/axi_ad7768.xpr new file mode 100644 index 00000000..99fea34f --- /dev/null +++ b/adi_library/axi_ad7768/axi_ad7768.xpr @@ -0,0 +1,526 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_ad7768/axi_ad7768_hw.tcl b/adi_library/axi_ad7768/axi_ad7768_hw.tcl new file mode 100644 index 00000000..c59b405c --- /dev/null +++ b/adi_library/axi_ad7768/axi_ad7768_hw.tcl @@ -0,0 +1,82 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys +source ../../scripts/adi_env.tcl +source ../scripts/adi_ip_intel.tcl + +set_module_property NAME axi_ad7768 +set_module_property DESCRIPTION "AXI AD7768 IP core" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME axi_ad7768 +set_module_property ELABORATION_CALLBACK create_ports +# source files + +ad_ip_files axi_ad7768 [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "axi_ad7768_if.v" \ + "axi_ad7768.v"] + +# IP parameters + +add_parameter ID INTEGER 0 +set_parameter_property ID DEFAULT_VALUE 0 +set_parameter_property ID DISPLAY_NAME "ID" +set_parameter_property ID UNITS None +set_parameter_property ID HDL_PARAMETER true + + +set group "General Configuration" + +ad_ip_parameter NUM_CHANNELS INTEGER 8 true [list \ + DISPLAY_NAME "Number of channels" \ + DISPLAY_UNITS "channels" \ + ALLOWED_RANGES {4 8} \ + GROUP $group \ +] + +# AXI4 Memory Mapped Interface + +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 15 + +# ad7768_if and axi_gpreg ports + +ad_interface signal adc_dovf input 1 ovf +ad_interface signal clk_in input 1 +ad_interface signal ready_in input 1 +ad_interface signal data_in input 8 + +ad_interface reset adc_reset output 1 +ad_interface clock adc_clk output 1 +ad_interface signal adc_sync output 1 sync +ad_interface signal adc_valid output 1 valid +ad_interface signal adc_data output 32 data + +set_interface_property if_adc_reset associatedClock if_adc_clk + +proc create_ports {} { +set num_channels [get_parameter_value "NUM_CHANNELS"] +set samples_per_channel 1 +set sample_data_width 32 +set channel_data_width [expr $sample_data_width * $samples_per_channel] + +for {set n 0} {$n < $num_channels} {incr n} { +add_interface adc_ch_$n conduit end +add_interface_port adc_ch_$n adc_enable_$n enable Output 1 +add_interface_port adc_ch_$n adc_data_$n data Output $sample_data_width +add_interface_port adc_ch_$n adc_valid_$n valid Output 1 +set_interface_property adc_ch_$n associatedClock if_adc_clk +set_interface_property adc_ch_$n associatedReset none +} + +} + diff --git a/adi_library/axi_ad7768/axi_ad7768_if.v b/adi_library/axi_ad7768/axi_ad7768_if.v new file mode 100644 index 00000000..a59c898c --- /dev/null +++ b/adi_library/axi_ad7768/axi_ad7768_if.v @@ -0,0 +1,490 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad7768_if #( + parameter NUM_CHANNELS = 8 +) ( + + // device-interface + + input clk_in, + input ready_in, + input [ 7:0] data_in, + + // data path interface + + output adc_clk, + output adc_valid, + output [31:0] adc_data, + output adc_sync, + output [31:0] adc_data_0, + output [31:0] adc_data_1, + output [31:0] adc_data_2, + output [31:0] adc_data_3, + output [31:0] adc_data_4, + output [31:0] adc_data_5, + output [31:0] adc_data_6, + output [31:0] adc_data_7, + output [ 7:0] adc_status_0, + output [ 7:0] adc_status_1, + output [ 7:0] adc_status_2, + output [ 7:0] adc_status_3, + output [ 7:0] adc_status_4, + output [ 7:0] adc_status_5, + output [ 7:0] adc_status_6, + output [ 7:0] adc_status_7, + output [ 7:0] adc_crc_ch_mismatch, + + // control interface + + input adc_sshot, + input [ 4:0] adc_format, + input adc_crc_enable +); + + // internal registers + + reg [ 95:0] adc_crc_data_s [0:7]; + reg [ 7:0] adc_crc_read_data [0:7]; + reg [ 7:0] adc_crc_reg [0:7]; + reg [ 31:0] adc_data_s_d [0:7]; + reg [ 31:0] adc_data_s [0:7]; + reg [ 31:0] adc_data_int = 'd0; + reg [ 3:0] adc_crc_cnt = 'd0; + reg [ 8:0] adc_cnt_p = 'd0; + reg [255:0] adc_data_p = 'd0; + reg [255:0] adc_ch_data_d0 = 'd0; + reg [255:0] adc_ch_data_d1 = 'd0; + reg [255:0] adc_ch_data_d2 = 'd0; + reg [255:0] adc_ch_data_d3 = 'd0; + reg [255:0] adc_ch_data_d4 = 'd0; + reg [255:0] adc_ch_data_d5 = 'd0; + reg [255:0] adc_ch_data_d6 = 'd0; + reg [255:0] adc_ch_data_d7 = 'd0; + reg [ 7:0] adc_status_0_s = 'd0; + reg [ 7:0] adc_status_1_s = 'd0; + reg [ 7:0] adc_status_2_s = 'd0; + reg [ 7:0] adc_status_3_s = 'd0; + reg [ 7:0] adc_status_4_s = 'd0; + reg [ 7:0] adc_status_5_s = 'd0; + reg [ 7:0] adc_status_6_s = 'd0; + reg [ 7:0] adc_status_7_s = 'd0; + reg [ 7:0] adc_crc_ch_mismatch_s = 'd0; + reg adc_valid_s = 'b0; + reg adc_valid_s_d = 'b0; + reg adc_crc_valid_p = 'b0; + reg sync_ss = 'd0; + reg adc_valid_p = 'd0; + reg adc_ready = 'd0; + reg adc_cnt_enable_s_d = 'b0; + // internal signals + + wire [ 7:0] adc_crc_in_s [0:7]; + wire [ 7:0] adc_crc_s [0:7]; + wire [ 3:0] adc_crc_cnt_value; + wire [ 8:0] adc_cnt_value; + wire [ 7:0] adc_crc_mismatch_s; + wire adc_crc_cnt_enable_s; + wire adc_cnt_enable_s; + wire adc_ready_in_s; + wire crc_in_sync_n; + + // function (crc8) + + function [ 7:0] crc8; + input [95:0] din; + input [ 7:0] cin; + reg [ 7:0] cout; + begin + + cout[0] = cin[0] ^ cin[2] ^ cin[4] ^ cin[5] ^ cin[6] ^ din[0] ^ din[6] ^ din[7] ^ din[8] ^ din[12] ^ din[14] ^ din[16] ^ + din[18] ^ din[19] ^ din[21] ^ din[23] ^ din[28] ^ din[30] ^ din[31] ^ din[34] ^ din[35] ^ din[39] ^ din[40] ^ din[43] ^ + din[45] ^ din[48] ^ din[49] ^ din[50] ^ din[52] ^ din[53] ^ din[54] ^ din[56] ^ din[60] ^ din[63] ^ din[64] ^ din[66] ^ + din[67] ^ din[68] ^ din[69] ^ din[74] ^ din[75] ^ din[77] ^ din[80] ^ din[84] ^ din[85] ^ din[86] ^ din[87] ^ din[88] ^ + din[90] ^ din[92] ^ din[93] ^ din[94]; + cout[1] = cin[1] ^ cin[2] ^ cin[3] ^ cin[4] ^ cin[7] ^ din[0] ^ din[1] ^ din[6] ^ din[9] ^ din[12] ^ din[13] ^ din[14] ^ + din[15] ^ din[16] ^ din[17] ^ din[18] ^ din[20] ^ din[21] ^ din[22] ^ din[23] ^ din[24] ^ din[28] ^ din[29] ^ din[30] ^ + din[32] ^ din[34] ^ din[36] ^ din[39] ^ din[41] ^ din[43] ^ din[44] ^ din[45] ^ din[46] ^ din[48] ^ din[51] ^ din[52] ^ + din[55] ^ din[56] ^ din[57] ^ din[60] ^ din[61] ^ din[63] ^ din[65] ^ din[66] ^ din[70] ^ din[74] ^ din[76] ^ din[77] ^ + din[78] ^ din[80] ^ din[81] ^ din[84] ^ din[89] ^ din[90] ^ din[91] ^ din[92] ^ din[95]; + cout[2] = cin[0] ^ cin[3] ^ cin[6] ^ din[0] ^ din[1] ^ din[2] ^ din[6] ^ din[8] ^ din[10] ^ din[12] ^ din[13] ^ din[15] ^ + din[17] ^ din[22] ^ din[24] ^ din[25] ^ din[28] ^ din[29] ^ din[33] ^ din[34] ^ din[37] ^ din[39] ^ din[42] ^ din[43] ^ + din[44] ^ din[46] ^ din[47] ^ din[48] ^ din[50] ^ din[54] ^ din[57] ^ din[58] ^ din[60] ^ din[61] ^ din[62] ^ din[63] ^ + din[68] ^ din[69] ^ din[71] ^ din[74] ^ din[78] ^ din[79] ^ din[80] ^ din[81] ^ din[82] ^ din[84] ^ din[86] ^ din[87] ^ + din[88] ^ din[91] ^ din[94]; + cout[3] = cin[0] ^ cin[1] ^ cin[4] ^ cin[7] ^ din[1] ^ din[2] ^ din[3] ^ din[7] ^ din[9] ^ din[11] ^ din[13] ^ din[14] ^ + din[16] ^ din[18] ^ din[23] ^ din[25] ^ din[26] ^ din[29] ^ din[30] ^ din[34] ^ din[35] ^ din[38] ^ din[40] ^ din[43] ^ + din[44] ^ din[45] ^ din[47] ^ din[48] ^ din[49] ^ din[51] ^ din[55] ^ din[58] ^ din[59] ^ din[61] ^ din[62] ^ din[63] ^ + din[64] ^ din[69] ^ din[70] ^ din[72] ^ din[75] ^ din[79] ^ din[80] ^ din[81] ^ din[82] ^ din[83] ^ din[85] ^ din[87] ^ + din[88] ^ din[89] ^ din[92] ^ din[95]; + cout[4] = cin[0] ^ cin[1] ^ cin[2] ^ cin[5] ^ din[2] ^ din[3] ^ din[4] ^ din[8] ^ din[10] ^ din[12] ^ din[14] ^ din[15] ^ + din[17] ^ din[19] ^ din[24] ^ din[26] ^ din[27] ^ din[30] ^ din[31] ^ din[35] ^ din[36] ^ din[39] ^ din[41] ^ din[44] ^ + din[45] ^ din[46] ^ din[48] ^ din[49] ^ din[50] ^ din[52] ^ din[56] ^ din[59] ^ din[60] ^ din[62] ^ din[63] ^ din[64] ^ + din[65] ^ din[70] ^ din[71] ^ din[73] ^ din[76] ^ din[80] ^ din[81] ^ din[82] ^ din[83] ^ din[84] ^ din[86] ^ din[88] ^ + din[89] ^ din[90] ^ din[93]; + cout[5] = cin[1] ^ cin[2] ^ cin[3] ^ cin[6] ^ din[3] ^ din[4] ^ din[5] ^ din[9] ^ din[11] ^ din[13] ^ din[15] ^ din[16] ^ + din[18] ^ din[20] ^ din[25] ^ din[27] ^ din[28] ^ din[31] ^ din[32] ^ din[36] ^ din[37] ^ din[40] ^ din[42] ^ din[45] ^ + din[46] ^ din[47] ^ din[49] ^ din[50] ^ din[51] ^ din[53] ^ din[57] ^ din[60] ^ din[61] ^ din[63] ^ din[64] ^ din[65] ^ + din[66] ^ din[71] ^ din[72] ^ din[74] ^ din[77] ^ din[81] ^ din[82] ^ din[83] ^ din[84] ^ din[85] ^ din[87] ^ din[89] ^ + din[90] ^ din[91] ^ din[94]; + cout[6] = cin[0] ^ cin[2] ^ cin[3] ^ cin[4] ^ cin[7] ^ din[4] ^ din[5] ^ din[6] ^ din[10] ^ din[12] ^ din[14] ^ din[16] ^ + din[17] ^ din[19] ^ din[21] ^ din[26] ^ din[28] ^ din[29] ^ din[32] ^ din[33] ^ din[37] ^ din[38] ^ din[41] ^ din[43] ^ + din[46] ^ din[47] ^ din[48] ^ din[50] ^ din[51] ^ din[52] ^ din[54] ^ din[58] ^ din[61] ^ din[62] ^ din[64] ^ din[65] ^ + din[66] ^ din[67] ^ din[72] ^ din[73] ^ din[75] ^ din[78] ^ din[82] ^ din[83] ^ din[84] ^ din[85] ^ din[86] ^ din[88] ^ + din[90] ^ din[91] ^ din[92] ^ din[95]; + cout[7] = cin[1] ^ cin[3] ^ cin[4] ^ cin[5] ^ din[5] ^ din[6] ^ din[7] ^ din[11] ^ din[13] ^ din[15] ^ din[17] ^ din[18] ^ + din[20] ^ din[22] ^ din[27] ^ din[29] ^ din[30] ^ din[33] ^ din[34] ^ din[38] ^ din[39] ^ din[42] ^ din[44] ^ din[47] ^ + din[48] ^ din[49] ^ din[51] ^ din[52] ^ din[53] ^ din[55] ^ din[59] ^ din[62] ^ din[63] ^ din[65] ^ din[66] ^ din[67] ^ + din[68] ^ din[73] ^ din[74] ^ din[76] ^ din[79] ^ din[83] ^ din[84] ^ din[85] ^ din[86] ^ din[87] ^ din[89] ^ din[91] ^ + din[92] ^ din[93]; + crc8 = cout; + end + endfunction + + assign adc_ready_in_s = ready_in; + assign adc_clk = clk_in; + assign adc_valid = adc_valid_s_d; + assign adc_data= adc_data_int; + assign adc_data_0 = adc_data_s_d[0]; + assign adc_data_1 = adc_data_s_d[1]; + assign adc_data_2 = adc_data_s_d[2]; + assign adc_data_3 = adc_data_s_d[3]; + assign adc_data_4 = adc_data_s_d[4]; + assign adc_data_5 = adc_data_s_d[5]; + assign adc_data_6 = adc_data_s_d[6]; + assign adc_data_7 = adc_data_s_d[7]; + assign adc_status_0 = adc_status_0_s; + assign adc_status_1 = adc_status_1_s; + assign adc_status_2 = adc_status_2_s; + assign adc_status_3 = adc_status_3_s; + assign adc_status_4 = adc_status_4_s; + assign adc_status_5 = adc_status_5_s; + assign adc_status_6 = adc_status_6_s; + assign adc_status_7 = adc_status_7_s; + assign adc_crc_ch_mismatch = adc_crc_ch_mismatch_s; + assign crc_in_sync_n = |adc_crc_mismatch_s; + + // CRC check + + assign adc_crc_mismatch_s[0] = (adc_crc_read_data[0] == adc_crc_s[0]) ? 1'b0 : adc_crc_enable; + assign adc_crc_mismatch_s[1] = (adc_crc_read_data[1] == adc_crc_s[1]) ? 1'b0 : adc_crc_enable; + assign adc_crc_mismatch_s[2] = (adc_crc_read_data[2] == adc_crc_s[2]) ? 1'b0 : adc_crc_enable; + assign adc_crc_mismatch_s[3] = (adc_crc_read_data[3] == adc_crc_s[3]) ? 1'b0 : adc_crc_enable; + assign adc_crc_mismatch_s[4] = (adc_crc_read_data[4] == adc_crc_s[4] || NUM_CHANNELS == 4) ? 1'b0 : adc_crc_enable; + assign adc_crc_mismatch_s[5] = (adc_crc_read_data[5] == adc_crc_s[5] || NUM_CHANNELS == 4) ? 1'b0 : adc_crc_enable; + assign adc_crc_mismatch_s[6] = (adc_crc_read_data[6] == adc_crc_s[6] || NUM_CHANNELS == 4) ? 1'b0 : adc_crc_enable; + assign adc_crc_mismatch_s[7] = (adc_crc_read_data[7] == adc_crc_s[7] || NUM_CHANNELS == 4) ? 1'b0 : adc_crc_enable; + + assign adc_crc_s[0] = crc8(adc_crc_data_s[0], adc_crc_in_s[0]); + assign adc_crc_s[1] = crc8(adc_crc_data_s[1], adc_crc_in_s[1]); + assign adc_crc_s[2] = crc8(adc_crc_data_s[2], adc_crc_in_s[2]); + assign adc_crc_s[3] = crc8(adc_crc_data_s[3], adc_crc_in_s[3]); + assign adc_crc_s[4] = crc8(adc_crc_data_s[4], adc_crc_in_s[4]); + assign adc_crc_s[5] = crc8(adc_crc_data_s[5], adc_crc_in_s[5]); + assign adc_crc_s[6] = crc8(adc_crc_data_s[6], adc_crc_in_s[6]); + assign adc_crc_s[7] = crc8(adc_crc_data_s[7], adc_crc_in_s[7]); + + assign adc_crc_in_s[0] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[0]; + assign adc_crc_in_s[1] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[1]; + assign adc_crc_in_s[2] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[2]; + assign adc_crc_in_s[3] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[3]; + assign adc_crc_in_s[4] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[4]; + assign adc_crc_in_s[5] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[5]; + assign adc_crc_in_s[6] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[6]; + assign adc_crc_in_s[7] = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg[7]; + + assign adc_sync = adc_valid_s & ~adc_valid_s_d & sync_ss; + + // serial output data + + always @(posedge adc_clk) begin + if (adc_valid_s) begin + sync_ss <= 1'h1; + end else if (adc_sync) begin + sync_ss <= 1'h0; + end + + adc_data_int <= adc_ch_data_d0[((32*0)+31):(32*0)] | adc_ch_data_d1[((32*1)+31):(32*1)] | adc_ch_data_d2[((32*2)+31):(32*2)] | + adc_ch_data_d3[((32*3)+31):(32*3)] | adc_ch_data_d4[((32*4)+31):(32*4)] | adc_ch_data_d5[((32*5)+31):(32*5)] | + adc_ch_data_d6[((32*6)+31):(32*6)] | adc_ch_data_d7[((32*7)+31):(32*7)]; + + adc_ch_data_d0 <= {adc_ch_data_d0[((32*6)+31):(32*0)],adc_data_s[0]}; + adc_ch_data_d1 <= {adc_ch_data_d1[((32*6)+31):(32*0)],adc_data_s[1]}; + adc_ch_data_d2 <= {adc_ch_data_d2[((32*6)+31):(32*0)],adc_data_s[2]}; + adc_ch_data_d3 <= {adc_ch_data_d3[((32*6)+31):(32*0)],adc_data_s[3]}; + adc_ch_data_d4 <= {adc_ch_data_d4[((32*6)+31):(32*0)],adc_data_s[4]}; + adc_ch_data_d5 <= {adc_ch_data_d5[((32*6)+31):(32*0)],adc_data_s[5]}; + adc_ch_data_d6 <= {adc_ch_data_d6[((32*6)+31):(32*0)],adc_data_s[6]}; + adc_ch_data_d7 <= {adc_ch_data_d7[((32*6)+31):(32*0)],adc_data_s[7]}; + + end + + always @(posedge adc_clk) begin + + adc_status_0_s <= (adc_valid_s == 1'b1) ? adc_data_s[0][31:24]: adc_status_0_s; + adc_status_1_s <= (adc_valid_s == 1'b1) ? adc_data_s[1][31:24]: adc_status_1_s; + adc_status_2_s <= (adc_valid_s == 1'b1) ? adc_data_s[2][31:24]: adc_status_2_s; + adc_status_3_s <= (adc_valid_s == 1'b1) ? adc_data_s[3][31:24]: adc_status_3_s; + adc_status_4_s <= (adc_valid_s == 1'b1) ? adc_data_s[4][31:24]: adc_status_4_s; + adc_status_5_s <= (adc_valid_s == 1'b1) ? adc_data_s[5][31:24]: adc_status_5_s; + adc_status_6_s <= (adc_valid_s == 1'b1) ? adc_data_s[6][31:24]: adc_status_6_s; + adc_status_7_s <= (adc_valid_s == 1'b1) ? adc_data_s[7][31:24]: adc_status_7_s; + adc_crc_ch_mismatch_s[0] <= (adc_crc_valid_p == 1'b1) ? adc_crc_mismatch_s[0] : adc_crc_ch_mismatch_s[0]; + adc_crc_ch_mismatch_s[1] <= (adc_crc_valid_p == 1'b1) ? adc_crc_mismatch_s[1] : adc_crc_ch_mismatch_s[1]; + adc_crc_ch_mismatch_s[2] <= (adc_crc_valid_p == 1'b1) ? adc_crc_mismatch_s[2] : adc_crc_ch_mismatch_s[2]; + adc_crc_ch_mismatch_s[3] <= (adc_crc_valid_p == 1'b1) ? adc_crc_mismatch_s[3] : adc_crc_ch_mismatch_s[3]; + adc_crc_ch_mismatch_s[4] <= (adc_crc_valid_p == 1'b1) ? adc_crc_mismatch_s[4] : adc_crc_ch_mismatch_s[4]; + adc_crc_ch_mismatch_s[5] <= (adc_crc_valid_p == 1'b1) ? adc_crc_mismatch_s[5] : adc_crc_ch_mismatch_s[5]; + adc_crc_ch_mismatch_s[6] <= (adc_crc_valid_p == 1'b1) ? adc_crc_mismatch_s[6] : adc_crc_ch_mismatch_s[6]; + adc_crc_ch_mismatch_s[7] <= (adc_crc_valid_p == 1'b1) ? adc_crc_mismatch_s[7] : adc_crc_ch_mismatch_s[7]; + + end + + // 4 samples counter for crc + + assign adc_crc_cnt_value = 4'h4; + + assign adc_crc_cnt_enable_s = (adc_crc_cnt < adc_crc_cnt_value) ? 1'b1 : 1'b0; + + always @(posedge adc_clk) begin + if ((crc_in_sync_n == 1'b0) || (adc_crc_enable == 1'b0) || (adc_crc_cnt_enable_s ==1'b0)) begin + adc_crc_cnt <= 4'd0; + end else if ((adc_valid_p == 1'b1) && (adc_crc_enable == 1'b1)) begin + adc_crc_cnt <= adc_crc_cnt + 1'b1; + end + + if (adc_crc_cnt == adc_crc_cnt_value) begin + adc_crc_valid_p <= 1'b1; + end else begin + adc_crc_valid_p <= 1'b0; + end + end + + // capturing crc data + + always @(posedge adc_clk) begin + if(adc_valid_s == 1'b1) begin + adc_crc_data_s[0] <= {adc_crc_data_s[0][71:0],adc_data_s[0][23:0]}; + adc_crc_data_s[1] <= {adc_crc_data_s[1][71:0],adc_data_s[1][23:0]}; + adc_crc_data_s[2] <= {adc_crc_data_s[2][71:0],adc_data_s[2][23:0]}; + adc_crc_data_s[3] <= {adc_crc_data_s[3][71:0],adc_data_s[3][23:0]}; + adc_crc_data_s[4] <= {adc_crc_data_s[4][71:0],adc_data_s[4][23:0]}; + adc_crc_data_s[5] <= {adc_crc_data_s[5][71:0],adc_data_s[5][23:0]}; + adc_crc_data_s[6] <= {adc_crc_data_s[6][71:0],adc_data_s[6][23:0]}; + adc_crc_data_s[7] <= {adc_crc_data_s[7][71:0],adc_data_s[7][23:0]}; + adc_crc_read_data[0] <=adc_data_s[0][31:24]; + adc_crc_read_data[1] <=adc_data_s[1][31:24]; + adc_crc_read_data[2] <=adc_data_s[2][31:24]; + adc_crc_read_data[3] <=adc_data_s[3][31:24]; + adc_crc_read_data[4] <=adc_data_s[4][31:24]; + adc_crc_read_data[5] <=adc_data_s[5][31:24]; + adc_crc_read_data[6] <=adc_data_s[6][31:24]; + adc_crc_read_data[7] <=adc_data_s[7][31:24]; + adc_crc_reg[0] <= adc_crc_s[0]; + adc_crc_reg[1] <= adc_crc_s[1]; + adc_crc_reg[2] <= adc_crc_s[2]; + adc_crc_reg[3] <= adc_crc_s[3]; + adc_crc_reg[4] <= adc_crc_s[4]; + adc_crc_reg[5] <= adc_crc_s[5]; + adc_crc_reg[6] <= adc_crc_s[6]; + adc_crc_reg[7] <= adc_crc_s[7]; + end else begin + adc_crc_data_s[0] <= adc_crc_data_s[0]; + adc_crc_data_s[1] <= adc_crc_data_s[1]; + adc_crc_data_s[2] <= adc_crc_data_s[2]; + adc_crc_data_s[3] <= adc_crc_data_s[3]; + adc_crc_data_s[4] <= adc_crc_data_s[4]; + adc_crc_data_s[5] <= adc_crc_data_s[5]; + adc_crc_data_s[6] <= adc_crc_data_s[6]; + adc_crc_data_s[7] <= adc_crc_data_s[7]; + adc_crc_read_data[0] <= 8'b0; + adc_crc_read_data[1] <= 8'b0; + adc_crc_read_data[2] <= 8'b0; + adc_crc_read_data[3] <= 8'b0; + adc_crc_read_data[4] <= 8'b0; + adc_crc_read_data[5] <= 8'b0; + adc_crc_read_data[6] <= 8'b0; + adc_crc_read_data[7] <= 8'b0; + adc_crc_reg[0] <= 'b0; + adc_crc_reg[1] <= 'b0; + adc_crc_reg[2] <= 'b0; + adc_crc_reg[3] <= 'b0; + adc_crc_reg[4] <= 'b0; + adc_crc_reg[5] <= 'b0; + adc_crc_reg[6] <= 'b0; + adc_crc_reg[7] <= 'b0; + end + end + + // data capturing counter + + assign adc_cnt_value = (adc_format == 'h1 && NUM_CHANNELS == 8) ? 'hff : + (((adc_format == 'h2 && NUM_CHANNELS == 8) || (adc_format == 'h1 && NUM_CHANNELS == 4)) ? 'h7f : 'h1f); + + assign adc_cnt_enable_s = (adc_cnt_p < adc_cnt_value) ? 1'b1 : 1'b0; + + always @(negedge adc_clk) begin + adc_cnt_enable_s_d <= adc_cnt_enable_s; + if (adc_ready == 1'b0) begin + adc_cnt_p <= 'h000; + end else if (adc_cnt_enable_s == 1'b1) begin + adc_cnt_p <= adc_cnt_p + 1'b1; + end + if (adc_cnt_p == adc_cnt_value && adc_cnt_enable_s_d == 1'b1) begin + adc_valid_p <= 1'b1; + end else begin + adc_valid_p <= 1'b0; + end + end + + //delay data 1 clk for data, data_valid and crc mismatch for alignment + + always @(posedge adc_clk) begin + if (adc_valid_s == 1'b1) begin + adc_data_s_d[0] <= adc_data_s[0]; + adc_data_s_d[1] <= adc_data_s[1]; + adc_data_s_d[2] <= adc_data_s[2]; + adc_data_s_d[3] <= adc_data_s[3]; + adc_data_s_d[4] <= adc_data_s[4]; + adc_data_s_d[5] <= adc_data_s[5]; + adc_data_s_d[6] <= adc_data_s[6]; + adc_data_s_d[7] <= adc_data_s[7]; + adc_valid_s_d <= adc_valid_s; + end else begin + adc_data_s_d[0] <= 32'b0; + adc_data_s_d[1] <= 32'b0; + adc_data_s_d[2] <= 32'b0; + adc_data_s_d[3] <= 32'b0; + adc_data_s_d[4] <= 32'b0; + adc_data_s_d[5] <= 32'b0; + adc_data_s_d[6] <= 32'b0; + adc_data_s_d[7] <= 32'b0; + adc_valid_s_d <= 1'b0; + end + end + + always @(posedge adc_clk) begin + if (adc_valid_p == 1'b1) begin + if(adc_format == 'h1 && NUM_CHANNELS == 8) begin // 1 active line + adc_data_s[0] <= adc_data_p[((32*7)+31):(32*7)]; + adc_data_s[1] <= adc_data_p[((32*6)+31):(32*6)]; + adc_data_s[2] <= adc_data_p[((32*5)+31):(32*5)]; + adc_data_s[3] <= adc_data_p[((32*4)+31):(32*4)]; + adc_data_s[4] <= adc_data_p[((32*3)+31):(32*3)]; + adc_data_s[5] <= adc_data_p[((32*2)+31):(32*2)]; + adc_data_s[6] <= adc_data_p[((32*1)+31):(32*1)]; + adc_data_s[7] <= adc_data_p[((32*0)+31):(32*0)]; + end else if((adc_format == 'h2 && NUM_CHANNELS == 8) || (adc_format == 'h1 && NUM_CHANNELS == 4)) begin // 2 active lines or 1 for ad7768-4 + adc_data_s[0] <= adc_data_p[((32*3)+31):(32*3)]; + adc_data_s[1] <= adc_data_p[((32*2)+31):(32*2)]; + adc_data_s[2] <= adc_data_p[((32*1)+31):(32*1)]; + adc_data_s[3] <= adc_data_p[((32*0)+31):(32*0)]; + adc_data_s[4] <= adc_data_p[((32*7)+31):(32*7)]; + adc_data_s[5] <= adc_data_p[((32*6)+31):(32*6)]; + adc_data_s[6] <= adc_data_p[((32*5)+31):(32*5)]; + adc_data_s[7] <= adc_data_p[((32*4)+31):(32*4)]; + end else begin // 8 active lines + adc_data_s[0] <= adc_data_p[((32*0)+31):(32*0)]; + adc_data_s[1] <= adc_data_p[((32*1)+31):(32*1)]; + adc_data_s[2] <= adc_data_p[((32*2)+31):(32*2)]; + adc_data_s[3] <= adc_data_p[((32*3)+31):(32*3)]; + adc_data_s[4] <= adc_data_p[((32*4)+31):(32*4)]; + adc_data_s[5] <= adc_data_p[((32*5)+31):(32*5)]; + adc_data_s[6] <= adc_data_p[((32*6)+31):(32*6)]; + adc_data_s[7] <= adc_data_p[((32*7)+31):(32*7)]; + end + adc_valid_s <= adc_valid_p; + end else begin + adc_data_s[0] <= 32'b0; + adc_data_s[1] <= 32'b0; + adc_data_s[2] <= 32'b0; + adc_data_s[3] <= 32'b0; + adc_data_s[4] <= 32'b0; + adc_data_s[5] <= 32'b0; + adc_data_s[6] <= 32'b0; + adc_data_s[7] <= 32'b0; + adc_valid_s <= 1'b0; + end + end + + // data (individual lanes) + + always @(negedge adc_clk) begin + if(adc_format == 'h1 && NUM_CHANNELS == 8) begin // 1 active line for ad7768 + if (adc_cnt_p == 'h0) begin + adc_data_p[((256*0)+255):(256*0)] <= {255'd0, data_in[0]}; + end else begin + adc_data_p[((256*0)+255):(255*0)] <= {adc_data_p[((256*0)+254):(256*0)], data_in[0]}; + end + end else if((adc_format == 'h2 && NUM_CHANNELS == 8) || (adc_format == 'h1 && NUM_CHANNELS == 4)) begin // 2 active lines or 1 active lane for ad7768-4 + if (adc_cnt_p == 'h0) begin + adc_data_p[((128*0)+127):(128*0)] <= {127'd0, data_in[0]}; + adc_data_p[((128*1)+127):(128*1)] <= {127'd0, data_in[1]}; + end else begin + adc_data_p[((128*0)+127):(128*0)] <= {adc_data_p[((128*0)+126):(128*0)], data_in[0]}; + adc_data_p[((128*1)+127):(128*1)] <= {adc_data_p[((128*1)+126):(128*1)], data_in[1]}; + end + end else begin // 8 active lines or 4 active lane for ad7768-4 + if (adc_cnt_p == 'h0) begin + adc_data_p[((32*0)+31):(32*0)] <= {31'd0, data_in[0]}; + adc_data_p[((32*1)+31):(32*1)] <= {31'd0, data_in[1]}; + adc_data_p[((32*2)+31):(32*2)] <= {31'd0, data_in[2]}; + adc_data_p[((32*3)+31):(32*3)] <= {31'd0, data_in[3]}; + adc_data_p[((32*4)+31):(32*4)] <= {31'd0, data_in[4]}; + adc_data_p[((32*5)+31):(32*5)] <= {31'd0, data_in[5]}; + adc_data_p[((32*6)+31):(32*6)] <= {31'd0, data_in[6]}; + adc_data_p[((32*7)+31):(32*7)] <= {31'd0, data_in[7]}; + end else begin + adc_data_p[((32*0)+31):(32*0)] <= {adc_data_p[((32*0)+30):(32*0)], data_in[0]}; + adc_data_p[((32*1)+31):(32*1)] <= {adc_data_p[((32*1)+30):(32*1)], data_in[1]}; + adc_data_p[((32*2)+31):(32*2)] <= {adc_data_p[((32*2)+30):(32*2)], data_in[2]}; + adc_data_p[((32*3)+31):(32*3)] <= {adc_data_p[((32*3)+30):(32*3)], data_in[3]}; + adc_data_p[((32*4)+31):(32*4)] <= {adc_data_p[((32*4)+30):(32*4)], data_in[4]}; + adc_data_p[((32*5)+31):(32*5)] <= {adc_data_p[((32*5)+30):(32*5)], data_in[5]}; + adc_data_p[((32*6)+31):(32*6)] <= {adc_data_p[((32*6)+30):(32*6)], data_in[6]}; + adc_data_p[((32*7)+31):(32*7)] <= {adc_data_p[((32*7)+30):(32*7)], data_in[7]}; + end + end + end + + // ready (single shot or continous) + + always @(posedge adc_clk) begin + adc_ready <= adc_sshot ~^ adc_ready_in_s; + end + +endmodule diff --git a/adi_library/axi_ad7768/axi_ad7768_ip.tcl b/adi_library/axi_ad7768/axi_ad7768_ip.tcl new file mode 100644 index 00000000..ddc8525c --- /dev/null +++ b/adi_library/axi_ad7768/axi_ad7768_ip.tcl @@ -0,0 +1,66 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_ad7768 + +adi_ip_files axi_ad7768 [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "axi_ad7768_if.v" \ + "axi_ad7768.v" ] + +adi_ip_properties axi_ad7768 + +adi_init_bd_tcl +adi_ip_bd axi_ad7768 "bd/bd.tcl" + +set cc [ipx::current_core] + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/ad7768} $cc + + +set_property driver_value 0 [ipx::get_ports *dovf* -of_objects $cc] +set_property driver_value 0 [ipx::get_ports *adc* -of_objects $cc] + +set_property -dict [list \ + value_validation_type list \ + value_validation_list {4 8} \ + ] [ipx::get_user_parameters NUM_CHANNELS -of_objects $cc] + +set_property enablement_dependency { $NUM_CHANNELS == 8 } \ + [ipx::get_ports *_4 -of_objects $cc] \ + [ipx::get_ports *_5 -of_objects $cc] \ + [ipx::get_ports *_6 -of_objects $cc] \ + [ipx::get_ports *_7 -of_objects $cc] + + +ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 $cc +ipx::infer_bus_interface clk_in xilinx.com:signal:clock_rtl:1.0 $cc +set reset_intf [ipx::infer_bus_interface adc_reset xilinx.com:signal:reset_rtl:1.0 $cc ] +set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_intf] +set_property value "ACTIVE_HIGH" $reset_polarity + +adi_add_auto_fpga_spec_params +ipx::create_xgui_files $cc + +ipx::save_core $cc diff --git a/adi_library/axi_ad7768/bd/bd.tcl b/adi_library/axi_ad7768/bd/bd.tcl new file mode 100644 index 00000000..f0062cf8 --- /dev/null +++ b/adi_library/axi_ad7768/bd/bd.tcl @@ -0,0 +1,41 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/axi_ad7768/component.xml b/adi_library/axi_ad7768/component.xml new file mode 100644 index 00000000..f4c287a7 --- /dev/null +++ b/adi_library/axi_ad7768/component.xml @@ -0,0 +1,1573 @@ + + + analog.com + user + axi_ad7768 + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + adc_clk + + + + + + + CLK + + + adc_clk + + + + + + ASSOCIATED_RESET + adc_reset + + + + + clk_in + + + + + + + CLK + + + clk_in + + + + + + adc_reset + + + + + + + RST + + + adc_reset + + + + + + POLARITY + ACTIVE_HIGH + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_ad7768 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 0214c281 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_ad7768 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + baa268ac + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 0e280ada + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + + + adc_dovf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + clk_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ready_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_in + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_sshot + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_enable_0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_enable_1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_enable_2 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_enable_3 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_enable_4 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + adc_enable_5 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + adc_enable_6 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + adc_enable_7 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + adc_valid_0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_valid_1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_valid_2 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_valid_3 + + out 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xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_sync + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_reset + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_crc_ch_mismatch + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + NUM_CHANNELS + Num Channels + 8 + + + + + + choice_list_6e06e1af + 4 + 8 + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../xilinx/common/up_clock_mon_constr.xdc + xdc + + + ../common/ad_rst.v + verilogSource + + + axi_ad7768_if.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad7768.v + verilogSource + CHECKSUM_54865af8 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_rst.v + verilogSource + + + axi_ad7768_if.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad7768.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_ad7768_v1_0.tcl + tclSource + CHECKSUM_0e280ada + XGUI_VERSION_2 + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + axi_ad7768_v1_0 + + + ID + Id + 0 + + + NUM_CHANNELS + Num Channels + 8 + + + Component_Name + axi_ad7768_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_ad7768_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/ad7768 + 1 + 2024-01-14T03:39:13Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_ad7768/temporary_case_dependencies.mk b/adi_library/axi_ad7768/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/axi_ad7768/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/axi_ad7768/xgui/axi_ad7768_v1_0.tcl b/adi_library/axi_ad7768/xgui/axi_ad7768_v1_0.tcl new file mode 100644 index 00000000..9d7502d4 --- /dev/null +++ b/adi_library/axi_ad7768/xgui/axi_ad7768_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_CHANNELS" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.NUM_CHANNELS { PARAM_VALUE.NUM_CHANNELS } { + # Procedure called to update NUM_CHANNELS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_CHANNELS { PARAM_VALUE.NUM_CHANNELS } { + # Procedure called to validate NUM_CHANNELS + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.NUM_CHANNELS { MODELPARAM_VALUE.NUM_CHANNELS PARAM_VALUE.NUM_CHANNELS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_CHANNELS}] ${MODELPARAM_VALUE.NUM_CHANNELS} +} + diff --git a/adi_library/axi_ad777x/Makefile b/adi_library/axi_ad777x/Makefile new file mode 100644 index 00000000..fc0887ce --- /dev/null +++ b/adi_library/axi_ad777x/Makefile @@ -0,0 +1,35 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_ad777x + +GENERIC_DEPS += ../common/ad_datafmt.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_adc_channel.v +GENERIC_DEPS += ../common/up_adc_common.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_delay_cntrl.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_ad777x.v +GENERIC_DEPS += axi_ad777x_if.v + +XILINX_DEPS += ../xilinx/common/ad_dcfilter.v +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_ad777x_ip.tcl + +INTEL_DEPS += ../intel/common/ad_dcfilter.v +INTEL_DEPS += ../intel/common/up_clock_mon_constr.sdc +INTEL_DEPS += ../intel/common/up_rst_constr.sdc +INTEL_DEPS += ../intel/common/up_xfer_cntrl_constr.sdc +INTEL_DEPS += ../intel/common/up_xfer_status_constr.sdc +INTEL_DEPS += axi_ad777x_hw.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_ad777x/axi_ad777x.v b/adi_library/axi_ad777x/axi_ad777x.v new file mode 100644 index 00000000..d8f1d46e --- /dev/null +++ b/adi_library/axi_ad777x/axi_ad777x.v @@ -0,0 +1,360 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns / 1ps + +module axi_ad777x #( + parameter ID = 0 +) ( + + input adc_dovf, + input clk_in, + input ready_in, + output sync_adc_mosi, + input sync_adc_miso, + input [ 3:0] data_in, + + output adc_enable_0, + output adc_enable_1, + output adc_enable_2, + output adc_enable_3, + output adc_enable_4, + output adc_enable_5, + output adc_enable_6, + output adc_enable_7, + output adc_valid_0, + output adc_valid_1, + output adc_valid_2, + output adc_valid_3, + output adc_valid_4, + output adc_valid_5, + output adc_valid_6, + output adc_valid_7, + output [31:0] adc_data_0, + output [31:0] adc_data_1, + output [31:0] adc_data_2, + output [31:0] adc_data_3, + output [31:0] adc_data_4, + output [31:0] adc_data_5, + output [31:0] adc_data_6, + output [31:0] adc_data_7, + + output adc_clk, + output adc_reset, + output adc_valid, + output [ 7:0] adc_crc_ch_mismatch, + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready +); + + // internal registers + + reg [31:0] up_rdata = 'd0; + reg up_rack = 'd0; + reg up_wack = 'd0; + reg [31:0] up_rdata_r; + reg up_rack_r; + reg up_wack_r; + + // internal signals + + wire adc_rst_s; + wire up_rstn; + wire up_clk; + wire [13:0] up_waddr_s; + wire [13:0] up_raddr_s; + wire adc_clk_s; + wire up_wreq_s; + wire up_rreq_s; + wire [13:0] up_addr_s; + wire [31:0] up_wdata_s; + wire [31:0] up_rdata_s[0:8]; + wire [8:0] up_rack_s; + wire [8:0] up_wack_s; + wire [7:0] adc_enable; + wire [4:0] adc_num_lanes; + wire adc_crc_enable; + wire [7:0] adc_status_header[0:7]; + wire [7:0] adc_crc_err; + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + assign adc_clk = adc_clk_s; + assign adc_reset = adc_rst_s; + + assign adc_enable_0 = adc_enable[0]; + assign adc_enable_1 = adc_enable[1]; + assign adc_enable_2 = adc_enable[2]; + assign adc_enable_3 = adc_enable[3]; + assign adc_enable_4 = adc_enable[4]; + assign adc_enable_5 = adc_enable[5]; + assign adc_enable_6 = adc_enable[6]; + assign adc_enable_7 = adc_enable[7]; + assign adc_valid_0 = adc_valid; + assign adc_valid_1 = adc_valid; + assign adc_valid_2 = adc_valid; + assign adc_valid_3 = adc_valid; + assign adc_valid_4 = adc_valid; + assign adc_valid_5 = adc_valid; + assign adc_valid_6 = adc_valid; + assign adc_valid_7 = adc_valid; + assign adc_crc_ch_mismatch = adc_crc_err; + + integer j; + + always @(*) begin + up_rdata_r = 'h00; + up_rack_r = 'h00; + up_wack_r = 'h00; + for (j = 0; j <= 8; j=j+1) begin + up_rack_r = up_rack_r | up_rack_s[j]; + up_wack_r = up_wack_r | up_wack_s[j]; + up_rdata_r = up_rdata_r | up_rdata_s[j]; + end + end + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_rdata <= up_rdata_r; + up_rack <= up_rack_r; + up_wack <= up_wack_r; + end + end + + // adc channels + + generate + genvar i; + for (i = 0; i < 8; i=i+1) begin : ad777x_channels + up_adc_channel #( + .CHANNEL_ID(i) + ) i_up_adc_channel ( + .adc_clk (adc_clk_s), + .adc_rst (adc_rst_s), + .adc_enable (adc_enable[i]), + .adc_iqcor_enb (), + .adc_dcfilt_enb (), + .adc_dfmt_se (), + .adc_dfmt_type (), + .adc_dfmt_enable (), + .adc_dcfilt_offset (), + .adc_dcfilt_coeff (), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pnseq_sel (), + .adc_data_sel (), + .adc_pn_err (1'b0), + .adc_pn_oos (1'b0), + .adc_or (1'b0), + .adc_read_data ('d0), + .adc_status_header(adc_status_header[i]), + .adc_crc_err(adc_crc_err[i]), + .up_adc_pn_err (), + .up_adc_pn_oos (), + .up_adc_or (), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd32), + .adc_usr_datatype_bits (8'd32), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[i]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[i]), + .up_rack (up_rack_s[i])); + end + endgenerate + + // adc interface + + axi_ad777x_if i_ad777x_if ( + .clk_in (clk_in), + .ready_in (ready_in), + .data_in (data_in), + .adc_clk (adc_clk_s), + .adc_valid (adc_valid), + .sync_adc_mosi(sync_adc_mosi), + .sync_adc_miso(sync_adc_miso), + .adc_crc_ch_mismatch(adc_crc_err), + .adc_num_lanes(adc_num_lanes), + .adc_crc_enable(adc_crc_enable), + .adc_data_0 (adc_data_0), + .adc_data_1 (adc_data_1), + .adc_data_2 (adc_data_2), + .adc_data_3 (adc_data_3), + .adc_data_4 (adc_data_4), + .adc_data_5 (adc_data_5), + .adc_data_6 (adc_data_6), + .adc_data_7 (adc_data_7), + .adc_status_0(adc_status_header[0]), + .adc_status_1(adc_status_header[1]), + .adc_status_2(adc_status_header[2]), + .adc_status_3(adc_status_header[3]), + .adc_status_4(adc_status_header[4]), + .adc_status_5(adc_status_header[5]), + .adc_status_6(adc_status_header[6]), + .adc_status_7(adc_status_header[7])); + + // adc up common + + up_adc_common #( + .ID(ID) + ) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk_s), + .adc_rst (adc_rst_s), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status ('h00), + .adc_sync_status (1'b1), + .adc_status_ovf (adc_dovf), + .adc_clk_ratio (32'd1), + .adc_start_code (), + .adc_sref_sync (), + .adc_sync (), + .adc_ext_sync_arm(), + .adc_ext_sync_disarm(), + .adc_ext_sync_manual_req(), + .adc_custom_control(), + .adc_sdr_ddr_n(), + .adc_symb_op(), + .adc_symb_8_16b(), + .adc_num_lanes(adc_num_lanes), + .adc_crc_enable(adc_crc_enable), + .up_pps_rcounter (32'b0), + .up_pps_status (1'b0), + .up_pps_irq_mask (), + .up_adc_ce (), + .up_status_pn_err (1'b0), + .up_status_pn_oos (1'b0), + .up_status_or (1'b0), + .up_adc_r1_mode(), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .adc_config_wr (), + .adc_config_ctrl (), + .adc_config_rd ('d0), + .adc_ctrl_status ('d0), + .up_usr_chanmax_out (), + .up_usr_chanmax_in (8), + .up_adc_gpio_in (32'b0), + .up_adc_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[8]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[8]), + .up_rack (up_rack_s[8])); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + + endmodule diff --git a/adi_library/axi_ad777x/axi_ad777x.xpr b/adi_library/axi_ad777x/axi_ad777x.xpr new file mode 100644 index 00000000..76797772 --- /dev/null +++ b/adi_library/axi_ad777x/axi_ad777x.xpr @@ -0,0 +1,510 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_ad777x/axi_ad777x_hw.tcl b/adi_library/axi_ad777x/axi_ad777x_hw.tcl new file mode 100644 index 00000000..2328f141 --- /dev/null +++ b/adi_library/axi_ad777x/axi_ad777x_hw.tcl @@ -0,0 +1,116 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys +source ../../scripts/adi_env.tcl +source ../scripts/adi_ip_intel.tcl + +set_module_property NAME axi_ad777x +set_module_property DESCRIPTION "AXI AD777x IP" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME axi_ad777x + +# source files + +ad_ip_files axi_ad777x [list\ + $ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_rst_constr.sdc \ + $ad_hdl_dir/library/intel/common/ad_dcfilter.v \ + $ad_hdl_dir/library/common/ad_rst.v \ + $ad_hdl_dir/library/common/up_axi.v \ + $ad_hdl_dir/library/common/ad_datafmt.v \ + $ad_hdl_dir/library/common/up_xfer_cntrl.v \ + $ad_hdl_dir/library/common/up_xfer_status.v \ + $ad_hdl_dir/library/common/up_clock_mon.v \ + $ad_hdl_dir/library/common/up_delay_cntrl.v \ + $ad_hdl_dir/library/common/up_adc_channel.v \ + $ad_hdl_dir/library/common/up_adc_common.v \ + axi_ad777x_if.v \ + axi_ad777x.v ] + +# IP parameters + +add_parameter ID INTEGER 0 +set_parameter_property ID DEFAULT_VALUE 0 +set_parameter_property ID DISPLAY_NAME "ID" +set_parameter_property ID UNITS None +set_parameter_property ID HDL_PARAMETER true + +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 16 + + # adc clock interface + +add_interface adc_if conduit end +set_interface_property adc_if associatedClock clk_in +add_interface_port adc_if ready_in adc_ready Input 1 +add_interface_port adc_if data_in adc_data_in Input 4 +add_interface_port adc_if sync_adc_miso sync_adc_miso Input 1 +add_interface_port adc_if sync_adc_mosi sync_adc_mosi Output 1 + +ad_interface signal clk_in input 1 +ad_interface clock adc_clk output 1 +ad_interface reset adc_reset output 1 +set_interface_property if_adc_reset associatedClock if_adc_clk +ad_interface signal adc_crc_ch_mismatch output 8 +ad_interface signal adc_dovf input 1 ovf + +add_interface adc_ch_0 conduit end +add_interface_port adc_ch_0 adc_enable_0 enable Output 1 +add_interface_port adc_ch_0 adc_data_0 data Output 32 +add_interface_port adc_ch_0 adc_valid_0 valid Output 1 +set_interface_property adc_ch_0 associatedClock if_adc_clk +set_interface_property adc_ch_0 associatedReset none + +add_interface adc_ch_1 conduit end +add_interface_port adc_ch_1 adc_enable_1 enable Output 1 +add_interface_port adc_ch_1 adc_data_1 data Output 32 +add_interface_port adc_ch_1 adc_valid_1 valid Output 1 +set_interface_property adc_ch_1 associatedClock if_adc_clk +set_interface_property adc_ch_1 associatedReset none + +add_interface adc_ch_2 conduit end +add_interface_port adc_ch_2 adc_enable_2 enable Output 1 +add_interface_port adc_ch_2 adc_data_2 data Output 32 +add_interface_port adc_ch_2 adc_valid_2 valid Output 1 +set_interface_property adc_ch_2 associatedClock if_adc_clk +set_interface_property adc_ch_2 associatedReset none + +add_interface adc_ch_3 conduit end +add_interface_port adc_ch_3 adc_enable_3 enable Output 1 +add_interface_port adc_ch_3 adc_data_3 data Output 32 +add_interface_port adc_ch_3 adc_valid_3 valid Output 1 +set_interface_property adc_ch_3 associatedClock if_adc_clk +set_interface_property adc_ch_3 associatedReset none + +add_interface adc_ch_4 conduit end +add_interface_port adc_ch_4 adc_enable_4 enable Output 1 +add_interface_port adc_ch_4 adc_data_4 data Output 32 +add_interface_port adc_ch_4 adc_valid_4 valid Output 1 +set_interface_property adc_ch_4 associatedClock if_adc_clk +set_interface_property adc_ch_4 associatedReset none + +add_interface adc_ch_5 conduit end +add_interface_port adc_ch_5 adc_enable_5 enable Output 1 +add_interface_port adc_ch_5 adc_data_5 data Output 32 +add_interface_port adc_ch_5 adc_valid_5 valid Output 1 +set_interface_property adc_ch_5 associatedClock if_adc_clk +set_interface_property adc_ch_5 associatedReset none + +add_interface adc_ch_6 conduit end +add_interface_port adc_ch_6 adc_enable_6 enable Output 1 +add_interface_port adc_ch_6 adc_data_6 data Output 32 +add_interface_port adc_ch_6 adc_valid_6 valid Output 1 +set_interface_property adc_ch_6 associatedClock if_adc_clk +set_interface_property adc_ch_6 associatedReset none + +add_interface adc_ch_7 conduit end +add_interface_port adc_ch_7 adc_enable_7 enable Output 1 +add_interface_port adc_ch_7 adc_data_7 data Output 32 +add_interface_port adc_ch_7 adc_valid_7 valid Output 1 +set_interface_property adc_ch_7 associatedClock if_adc_clk +set_interface_property adc_ch_7 associatedReset none diff --git a/adi_library/axi_ad777x/axi_ad777x_if.v b/adi_library/axi_ad777x/axi_ad777x_if.v new file mode 100644 index 00000000..c260b82e --- /dev/null +++ b/adi_library/axi_ad777x/axi_ad777x_if.v @@ -0,0 +1,378 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad777x_if ( + + // device-interface + + input clk_in, + input ready_in, + output sync_adc_mosi, + input sync_adc_miso, + input [ 3:0] data_in, + input [ 4:0] adc_num_lanes, + input adc_crc_enable, + + // data path interface + + output adc_clk, + output adc_valid, + output [ 7:0] adc_crc_ch_mismatch, + output [31:0] adc_data_0, + output [31:0] adc_data_1, + output [31:0] adc_data_2, + output [31:0] adc_data_3, + output [31:0] adc_data_4, + output [31:0] adc_data_5, + output [31:0] adc_data_6, + output [31:0] adc_data_7, + output [ 7:0] adc_status_0, + output [ 7:0] adc_status_1, + output [ 7:0] adc_status_2, + output [ 7:0] adc_status_3, + output [ 7:0] adc_status_4, + output [ 7:0] adc_status_5, + output [ 7:0] adc_status_6, + output [ 7:0] adc_status_7 +); + + // internal registers + + reg [ 8:0] adc_cnt_p = 'd0; + reg adc_valid_p = 'd0; + reg [255:0] adc_data_p = 'd0; + reg [31:0] adc_data_0_s = 'd0; + reg [31:0] adc_data_1_s = 'd0; + reg [31:0] adc_data_2_s = 'd0; + reg [31:0] adc_data_3_s = 'd0; + reg [31:0] adc_data_4_s = 'd0; + reg [31:0] adc_data_5_s = 'd0; + reg [31:0] adc_data_6_s = 'd0; + reg [31:0] adc_data_7_s = 'd0; + reg [31:0] adc_data_0_s_d = 'd0; + reg [31:0] adc_data_1_s_d = 'd0; + reg [31:0] adc_data_2_s_d = 'd0; + reg [31:0] adc_data_3_s_d = 'd0; + reg [31:0] adc_data_4_s_d = 'd0; + reg [31:0] adc_data_5_s_d = 'd0; + reg [31:0] adc_data_6_s_d = 'd0; + reg [31:0] adc_data_7_s_d = 'd0; + reg adc_valid_s = 'b0; + reg adc_valid_s_d = 'b0; + reg [ 7:0] adc_crc_read_data_0_1 = 'd0; + reg [ 7:0] adc_crc_read_data_2_3 = 'd0; + reg [ 7:0] adc_crc_read_data_4_5 = 'd0; + reg [ 7:0] adc_crc_read_data_6_7 = 'd0; + reg [55:0] adc_crc_data_0_1 = 'd0; + reg [55:0] adc_crc_data_2_3 = 'd0; + reg [55:0] adc_crc_data_4_5 = 'd0; + reg [55:0] adc_crc_data_6_7 = 'd0; + reg [ 7:0] adc_crc_reg_0_1 = 'd0; + reg [ 7:0] adc_crc_reg_2_3 = 'd0; + reg [ 7:0] adc_crc_reg_4_5 = 'd0; + reg [ 7:0] adc_crc_reg_6_7 = 'd0; + reg [ 7:0] adc_status_0_s = 'd0; + reg [ 7:0] adc_status_1_s = 'd0; + reg [ 7:0] adc_status_2_s = 'd0; + reg [ 7:0] adc_status_3_s = 'd0; + reg [ 7:0] adc_status_4_s = 'd0; + reg [ 7:0] adc_status_5_s = 'd0; + reg [ 7:0] adc_status_6_s = 'd0; + reg [ 7:0] adc_status_7_s = 'd0; + reg [ 7:0] adc_crc_ch_mismatch_s = 'd0; + + // internal signals + + wire adc_cnt_enable_s; + wire adc_ready_in_s; + wire [ 8:0] adc_cnt_value; + wire [ 7:0] adc_crc_in_s_0_1; + wire [ 7:0] adc_crc_in_s_2_3; + wire [ 7:0] adc_crc_in_s_4_5; + wire [ 7:0] adc_crc_in_s_6_7; + wire [ 7:0] adc_crc_s_0_1; + wire [ 7:0] adc_crc_s_2_3; + wire [ 7:0] adc_crc_s_4_5; + wire [ 7:0] adc_crc_s_6_7; + wire adc_crc_mismatch_s_0_1; + wire adc_crc_mismatch_s_2_3; + wire adc_crc_mismatch_s_4_5; + wire adc_crc_mismatch_s_6_7; + + assign adc_valid = adc_valid_s_d; + assign adc_ready_in_s = ready_in; + assign adc_data_0 = adc_data_0_s_d; + assign adc_data_1 = adc_data_1_s_d; + assign adc_data_2 = adc_data_2_s_d; + assign adc_data_3 = adc_data_3_s_d; + assign adc_data_4 = adc_data_4_s_d; + assign adc_data_5 = adc_data_5_s_d; + assign adc_data_6 = adc_data_6_s_d; + assign adc_data_7 = adc_data_7_s_d; + assign sync_adc_mosi = sync_adc_miso; + assign adc_clk = clk_in; + + assign adc_status_0 = adc_status_0_s; + assign adc_status_1 = adc_status_1_s; + assign adc_status_2 = adc_status_2_s; + assign adc_status_3 = adc_status_3_s; + assign adc_status_4 = adc_status_4_s; + assign adc_status_5 = adc_status_5_s; + assign adc_status_6 = adc_status_6_s; + assign adc_status_7 = adc_status_7_s; + assign adc_crc_ch_mismatch = adc_crc_ch_mismatch_s; + + // function (crc) + + function [ 7:0] crc8; + input [55:0] din; + input [ 7:0] cin; + reg [ 7:0] cout; + begin + cout[0] = cin[ 0] ^ cin[ 1] ^ cin[ 2] ^ cin[ 4] ^ cin[ 5] ^ cin[ 6] ^ din[ 0] ^ din[ 6] ^ din[ 7] ^ din[ 8] ^ din[12] ^ din[14] ^ din[16] ^ + din[18] ^ din[19] ^ din[21] ^ din[23] ^ din[28] ^ din[30] ^ din[31] ^ din[34] ^ din[35] ^ din[39] ^ din[40] ^ din[43] ^ din[45] ^ + din[48] ^ din[49] ^ din[50] ^ din[52] ^ din[53] ^ din[54]; + cout[1] = cin[ 0] ^ cin[ 3] ^ cin[ 4] ^ cin[ 7] ^ din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[13] ^ din[14] ^ din[15] ^ din[16] ^ + din[17] ^ din[18] ^ din[20] ^ din[21] ^ din[22] ^ din[23] ^ din[24] ^ din[28] ^ din[29] ^ din[30] ^ din[32] ^ din[34] ^ din[36] ^ + din[39] ^ din[41] ^ din[43] ^ din[44] ^ din[45] ^ din[46] ^ din[48] ^ din[51] ^ din[52] ^ din[55]; + cout[2] = cin[ 0] ^ cin[ 2] ^ cin[ 6] ^ din[ 0] ^ din[ 1] ^ din[ 2] ^ din[ 6] ^ din[ 8] ^ din[10] ^ din[12] ^ din[13] ^ din[15] ^ din[17] ^ + din[22] ^ din[24] ^ din[25] ^ din[28] ^ din[29] ^ din[33] ^ din[34] ^ din[37] ^ din[39] ^ din[42] ^ din[43] ^ din[44] ^ din[46] ^ + din[47] ^ din[48] ^ din[50] ^ din[54]; + cout[3] = cin[ 0] ^ cin[ 1] ^ cin[ 3] ^ cin[ 7] ^ din[ 1] ^ din[ 2] ^ din[ 3] ^ din[ 7] ^ din[ 9] ^ din[11] ^ din[13] ^ din[14] ^ din[16] ^ + din[18] ^ din[23] ^ din[25] ^ din[26] ^ din[29] ^ din[30] ^ din[34] ^ din[35] ^ din[38] ^ din[40] ^ din[43] ^ din[44] ^ din[45] ^ + din[47] ^ din[48] ^ din[49] ^ din[51] ^ din[55]; + cout[4] = cin[ 0] ^ cin[ 1] ^ cin[ 2] ^ cin[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 4] ^ din[ 8] ^ din[10] ^ din[12] ^ din[14] ^ din[15] ^ din[17] ^ + din[19] ^ din[24] ^ din[26] ^ din[27] ^ din[30] ^ din[31] ^ din[35] ^ din[36] ^ din[39] ^ din[41] ^ din[44] ^ din[45] ^ din[46] ^ + din[48] ^ din[49] ^ din[50] ^ din[52]; + cout[5] = cin[ 1] ^ cin[ 2] ^ cin[ 3] ^ cin[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 5] ^ din[ 9] ^ din[11] ^ din[13] ^ din[15] ^ din[16] ^ din[18] ^ + din[20] ^ din[25] ^ din[27] ^ din[28] ^ din[31] ^ din[32] ^ din[36] ^ din[37] ^ din[40] ^ din[42] ^ din[45] ^ din[46] ^ din[47] ^ + din[49] ^ din[50] ^ din[51] ^ din[53]; + cout[6] = cin[ 0] ^ cin[ 2] ^ cin[ 3] ^ cin[ 4] ^ cin[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 6] ^ din[10] ^ din[12] ^ din[14] ^ din[16] ^ din[17] ^ + din[19] ^ din[21] ^ din[26] ^ din[28] ^ din[29] ^ din[32] ^ din[33] ^ din[37] ^ din[38] ^ din[41] ^ din[43] ^ din[46] ^ din[47] ^ + din[48] ^ din[50] ^ din[51] ^ din[52] ^ din[54]; + cout[7] = cin[ 0] ^ cin[ 1] ^ cin[ 3] ^ cin[ 4] ^ cin[ 5] ^ cin[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 7] ^ din[11] ^ din[13] ^ din[15] ^ din[17] ^ + din[18] ^ din[20] ^ din[22] ^ din[27] ^ din[29] ^ din[30] ^ din[33] ^ din[34] ^ din[38] ^ din[39] ^ din[42] ^ din[44] ^ din[47] ^ + din[48] ^ din[49] ^ din[51] ^ din[52] ^ din[53] ^ din[55]; + crc8 = cout; + end + endfunction + + //crc computing + + assign adc_crc_s_0_1 = crc8(adc_crc_data_0_1, adc_crc_in_s_0_1); + assign adc_crc_s_2_3 = crc8(adc_crc_data_2_3, adc_crc_in_s_2_3); + assign adc_crc_s_4_5 = crc8(adc_crc_data_4_5, adc_crc_in_s_4_5); + assign adc_crc_s_6_7 = crc8(adc_crc_data_6_7, adc_crc_in_s_6_7); + + assign adc_crc_in_s_0_1 = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg_0_1; + assign adc_crc_in_s_2_3 = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg_2_3; + assign adc_crc_in_s_4_5 = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg_4_5; + assign adc_crc_in_s_6_7 = (adc_crc_enable == 'd1) ? 8'hff : adc_crc_reg_6_7; + + assign adc_crc_mismatch_s_0_1 = (adc_crc_read_data_0_1 == adc_crc_s_0_1) ? 1'b0 : adc_crc_enable; + assign adc_crc_mismatch_s_2_3 = (adc_crc_read_data_2_3 == adc_crc_s_2_3) ? 1'b0 : adc_crc_enable; + assign adc_crc_mismatch_s_4_5 = (adc_crc_read_data_4_5 == adc_crc_s_4_5) ? 1'b0 : adc_crc_enable; + assign adc_crc_mismatch_s_6_7 = (adc_crc_read_data_6_7 == adc_crc_s_6_7) ? 1'b0 : adc_crc_enable; + + always @(posedge adc_clk) begin + adc_status_0_s <= (adc_valid_s == 1'b1 ) ? adc_data_0_s[31:24]: adc_status_0_s; + adc_status_1_s <= (adc_valid_s == 1'b1 ) ? adc_data_1_s[31:24]: adc_status_1_s; + adc_status_2_s <= (adc_valid_s == 1'b1 ) ? adc_data_2_s[31:24]: adc_status_2_s; + adc_status_3_s <= (adc_valid_s == 1'b1 ) ? adc_data_3_s[31:24]: adc_status_3_s; + adc_status_4_s <= (adc_valid_s == 1'b1 ) ? adc_data_4_s[31:24]: adc_status_4_s; + adc_status_5_s <= (adc_valid_s == 1'b1 ) ? adc_data_5_s[31:24]: adc_status_5_s; + adc_status_6_s <= (adc_valid_s == 1'b1 ) ? adc_data_6_s[31:24]: adc_status_6_s; + adc_status_7_s <= (adc_valid_s == 1'b1 ) ? adc_data_7_s[31:24]: adc_status_7_s; + + adc_crc_ch_mismatch_s[1:0] <= (adc_valid_s_d == 1'b1 ) ? {2{adc_crc_mismatch_s_0_1}} : adc_crc_ch_mismatch_s[1:0]; + adc_crc_ch_mismatch_s[3:2] <= (adc_valid_s_d == 1'b1 ) ? {2{adc_crc_mismatch_s_2_3}} : adc_crc_ch_mismatch_s[3:2]; + adc_crc_ch_mismatch_s[5:4] <= (adc_valid_s_d == 1'b1 ) ? {2{adc_crc_mismatch_s_4_5}} : adc_crc_ch_mismatch_s[5:4]; + adc_crc_ch_mismatch_s[7:6] <= (adc_valid_s_d == 1'b1 ) ? {2{adc_crc_mismatch_s_6_7}} : adc_crc_ch_mismatch_s[7:6]; + end + + // crc generation/validation data + + always @(posedge adc_clk) begin + if (adc_valid_s == 1'b1) begin + adc_crc_reg_0_1 <= adc_crc_s_0_1; + adc_crc_reg_2_3 <= adc_crc_s_2_3; + adc_crc_reg_4_5 <= adc_crc_s_4_5; + adc_crc_reg_6_7 <= adc_crc_s_6_7; + adc_crc_read_data_0_1 <= {adc_data_0_s[27:24],adc_data_1_s[27:24]}; + adc_crc_read_data_2_3 <= {adc_data_2_s[27:24],adc_data_3_s[27:24]}; + adc_crc_read_data_4_5 <= {adc_data_4_s[27:24],adc_data_5_s[27:24]}; + adc_crc_read_data_6_7 <= {adc_data_6_s[27:24],adc_data_7_s[27:24]}; + adc_crc_data_0_1 <= {adc_data_0_s[31:28],adc_data_0_s[23:0],adc_data_1_s[31:28],adc_data_1_s[23:0]}; + adc_crc_data_2_3 <= {adc_data_2_s[31:28],adc_data_2_s[23:0],adc_data_3_s[31:28],adc_data_3_s[23:0]}; + adc_crc_data_4_5 <= {adc_data_4_s[31:28],adc_data_4_s[23:0],adc_data_5_s[31:28],adc_data_5_s[23:0]}; + adc_crc_data_6_7 <= {adc_data_6_s[31:28],adc_data_6_s[23:0],adc_data_7_s[31:28],adc_data_7_s[23:0]}; + end else begin + adc_crc_reg_0_1 <= 'd0; + adc_crc_reg_2_3 <= 'd0; + adc_crc_reg_4_5 <= 'd0; + adc_crc_reg_6_7 <= 'd0; + adc_crc_read_data_0_1 <= 'd0; + adc_crc_read_data_2_3 <= 'd0; + adc_crc_read_data_4_5 <= 'd0; + adc_crc_read_data_6_7 <= 'd0; + adc_crc_data_0_1 <= 'd0; + adc_crc_data_2_3 <= 'd0; + adc_crc_data_4_5 <= 'd0; + adc_crc_data_6_7 <= 'd0; + end + end + + //delay data 1 clk for data, data_valid and crc mismatch for alignment + + always @(posedge adc_clk) begin + if (adc_valid_s == 1'b1) begin + adc_data_0_s_d <= adc_data_0_s; + adc_data_1_s_d <= adc_data_1_s; + adc_data_2_s_d <= adc_data_2_s; + adc_data_3_s_d <= adc_data_3_s; + adc_data_4_s_d <= adc_data_4_s; + adc_data_5_s_d <= adc_data_5_s; + adc_data_6_s_d <= adc_data_6_s; + adc_data_7_s_d <= adc_data_7_s; + adc_valid_s_d <= adc_valid_s; + end else begin + adc_data_0_s_d <= 32'b0; + adc_data_1_s_d <= 32'b0; + adc_data_2_s_d <= 32'b0; + adc_data_3_s_d <= 32'b0; + adc_data_4_s_d <= 32'b0; + adc_data_5_s_d <= 32'b0; + adc_data_6_s_d <= 32'b0; + adc_data_7_s_d <= 32'b0; + adc_valid_s_d <= 1'b0; + end + end + + always @(posedge adc_clk) begin + if (adc_valid_p == 1'b1) begin + if( adc_num_lanes == 'h1) begin + adc_data_0_s <= adc_data_p[((32*7)+31):(32*7)]; + adc_data_1_s <= adc_data_p[((32*6)+31):(32*6)]; + adc_data_2_s <= adc_data_p[((32*5)+31):(32*5)]; + adc_data_3_s <= adc_data_p[((32*4)+31):(32*4)]; + adc_data_4_s <= adc_data_p[((32*3)+31):(32*3)]; + adc_data_5_s <= adc_data_p[((32*2)+31):(32*2)]; + adc_data_6_s <= adc_data_p[((32*1)+31):(32*1)]; + adc_data_7_s <= adc_data_p[((32*0)+31):(32*0)]; + end else if( adc_num_lanes == 'h2) begin + adc_data_0_s <= adc_data_p[((32*3)+31):(32*3)]; + adc_data_1_s <= adc_data_p[((32*2)+31):(32*2)]; + adc_data_2_s <= adc_data_p[((32*1)+31):(32*1)]; + adc_data_3_s <= adc_data_p[((32*0)+31):(32*0)]; + adc_data_4_s <= adc_data_p[((32*7)+31):(32*7)]; + adc_data_5_s <= adc_data_p[((32*6)+31):(32*6)]; + adc_data_6_s <= adc_data_p[((32*5)+31):(32*5)]; + adc_data_7_s <= adc_data_p[((32*4)+31):(32*4)]; + end else begin + adc_data_0_s <= adc_data_p[((32*1)+31):(32*1)]; + adc_data_1_s <= adc_data_p[((32*0)+31):(32*0)]; + adc_data_2_s <= adc_data_p[((32*3)+31):(32*3)]; + adc_data_3_s <= adc_data_p[((32*2)+31):(32*2)]; + adc_data_4_s <= adc_data_p[((32*5)+31):(32*5)]; + adc_data_5_s <= adc_data_p[((32*4)+31):(32*4)]; + adc_data_6_s <= adc_data_p[((32*7)+31):(32*7)]; + adc_data_7_s <= adc_data_p[((32*6)+31):(32*6)]; + end + adc_valid_s <= adc_valid_p; + end else begin + adc_data_0_s <= 32'b0; + adc_data_1_s <= 32'b0; + adc_data_2_s <= 32'b0; + adc_data_3_s <= 32'b0; + adc_data_4_s <= 32'b0; + adc_data_5_s <= 32'b0; + adc_data_6_s <= 32'b0; + adc_data_7_s <= 32'b0; + adc_valid_s <= 1'b0; + end + end + + assign adc_cnt_value = (adc_num_lanes == 'h1) ? 'hff : + ((adc_num_lanes == 'h2)? 'h7f : 'h3f); + + assign adc_cnt_enable_s = (adc_cnt_p < adc_cnt_value) ? 1'b1 : 1'b0; + + always @(negedge adc_clk) begin + if (adc_ready_in_s == 1'b1) begin + adc_cnt_p <= 'h000; + end else if (adc_cnt_enable_s == 1'b1) begin + adc_cnt_p <= adc_cnt_p + 1'b1; + end + if (adc_cnt_p == adc_cnt_value) begin + adc_valid_p <= 1'b1; + end else begin + adc_valid_p <= 1'b0; + end + end + + // data (individual lanes) + + always @(negedge adc_clk) begin + if( adc_num_lanes == 'h1) begin + if (adc_cnt_p == 'h000 ) begin + adc_data_p[((256*0)+255):(256*0)] <= {255'd0, data_in[0]}; + end else begin + adc_data_p[((256*0)+255):(255*0)] <= {adc_data_p[((256*0)+254):(256*0)], data_in[0]}; + end + end else if( adc_num_lanes == 'h2) begin + if (adc_cnt_p == 'h000 ) begin + adc_data_p[((128*0)+127):(128*0)] <= {127'd0, data_in[0]}; + adc_data_p[((128*1)+127):(128*1)] <= {127'd0, data_in[1]}; + end else begin + adc_data_p[((128*0)+127):(128*0)] <= {adc_data_p[((128*0)+126):(128*0)], data_in[0]}; + adc_data_p[((128*1)+127):(128*1)] <= {adc_data_p[((128*1)+126):(128*1)], data_in[1]}; + end + end else begin + if (adc_cnt_p == 'h000 ) begin + adc_data_p[((64*0)+63):(64*0)] <= {63'd0, data_in[0]}; + adc_data_p[((64*1)+63):(64*1)] <= {63'd0, data_in[1]}; + adc_data_p[((64*2)+63):(64*2)] <= {63'd0, data_in[2]}; + adc_data_p[((64*3)+63):(64*3)] <= {63'd0, data_in[3]}; + end else begin + adc_data_p[((64*0)+63):(64*0)] <= {adc_data_p[((64*0)+62):(64*0)], data_in[0]}; + adc_data_p[((64*1)+63):(64*1)] <= {adc_data_p[((64*1)+62):(64*1)], data_in[1]}; + adc_data_p[((64*2)+63):(64*2)] <= {adc_data_p[((64*2)+62):(64*2)], data_in[2]}; + adc_data_p[((64*3)+63):(64*3)] <= {adc_data_p[((64*3)+62):(64*3)], data_in[3]}; + end + end + end +endmodule diff --git a/adi_library/axi_ad777x/axi_ad777x_ip.tcl b/adi_library/axi_ad777x/axi_ad777x_ip.tcl new file mode 100644 index 00000000..0cbb79a6 --- /dev/null +++ b/adi_library/axi_ad777x/axi_ad777x_ip.tcl @@ -0,0 +1,49 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_ad777x + +adi_ip_files axi_ad777x [list \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "axi_ad777x_if.v" \ + "axi_ad777x.v" ] + +adi_ip_properties axi_ad777x + +adi_init_bd_tcl +adi_ip_bd axi_ad777x "bd/bd.tcl" + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/ad777x} [ipx::current_core] + +set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] + +ipx::infer_bus_interface clk_in xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +set reset_intf [ipx::infer_bus_interface adc_reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]] +set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_intf] +set_property value "ACTIVE_HIGH" $reset_polarity + +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + +ipx::save_core [ipx::current_core] diff --git a/adi_library/axi_ad777x/bd/bd.tcl b/adi_library/axi_ad777x/bd/bd.tcl new file mode 100644 index 00000000..f0062cf8 --- /dev/null +++ b/adi_library/axi_ad777x/bd/bd.tcl @@ -0,0 +1,41 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/axi_ad777x/component.xml b/adi_library/axi_ad777x/component.xml new file mode 100644 index 00000000..f1120c2e --- /dev/null +++ b/adi_library/axi_ad777x/component.xml @@ -0,0 +1,1364 @@ + + + analog.com + user + axi_ad777x + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + clk_in + + + + + + + CLK + + + clk_in + + + + + + adc_clk + + + + + + + CLK + + + adc_clk + + + + + + ASSOCIATED_RESET + adc_reset + + + + + adc_reset + + + + + + + RST + + + adc_reset + + + + + + POLARITY + ACTIVE_HIGH + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_ad777x + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 7b5d4a4d + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_ad777x + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + c5473c1f + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 6a7455d5 + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + + + adc_dovf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + clk_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ready_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sync_adc_mosi + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sync_adc_miso + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_in + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_2 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_3 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_4 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_5 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_6 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_7 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid_0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid_1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid_2 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid_3 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid_4 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid_5 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid_6 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid_7 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_0 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_1 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_2 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_3 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_4 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_5 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_6 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_7 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_reset + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_crc_ch_mismatch + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../xilinx/common/up_clock_mon_constr.xdc + xdc + + + ../common/ad_rst.v + verilogSource + + + axi_ad777x_if.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad777x.v + verilogSource + CHECKSUM_c058d44e + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_rst.v + verilogSource + + + axi_ad777x_if.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad777x.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_ad777x_v1_0.tcl + tclSource + CHECKSUM_6a7455d5 + XGUI_VERSION_2 + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + axi_ad777x_v1_0 + + + ID + Id + 0 + + + Component_Name + axi_ad777x_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_ad777x_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/ad777x + 1 + 2024-01-14T03:39:29Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_ad777x/temporary_case_dependencies.mk b/adi_library/axi_ad777x/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/axi_ad777x/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/axi_ad777x/xgui/axi_ad777x_v1_0.tcl b/adi_library/axi_ad777x/xgui/axi_ad777x_v1_0.tcl new file mode 100644 index 00000000..2b091276 --- /dev/null +++ b/adi_library/axi_ad777x/xgui/axi_ad777x_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + diff --git a/adi_library/axi_ad9122/Makefile b/adi_library/axi_ad9122/Makefile new file mode 100644 index 00000000..005cdb9c --- /dev/null +++ b/adi_library/axi_ad9122/Makefile @@ -0,0 +1,46 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_ad9122 + +GENERIC_DEPS += ../common/ad_dds.v +GENERIC_DEPS += ../common/ad_dds_1.v +GENERIC_DEPS += ../common/ad_dds_2.v +GENERIC_DEPS += ../common/ad_dds_cordic_pipe.v +GENERIC_DEPS += ../common/ad_dds_sine.v +GENERIC_DEPS += ../common/ad_dds_sine_cordic.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_dac_channel.v +GENERIC_DEPS += ../common/up_dac_common.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_ad9122.v +GENERIC_DEPS += axi_ad9122_channel.v +GENERIC_DEPS += axi_ad9122_core.v +GENERIC_DEPS += axi_ad9122_if.v + +XILINX_DEPS += ../xilinx/common/ad_mmcm_drp.v +XILINX_DEPS += ../xilinx/common/ad_mul.v +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/ad_serdes_clk.v +XILINX_DEPS += ../xilinx/common/ad_serdes_out.v +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_ad9122_constr.xdc +XILINX_DEPS += axi_ad9122_ip.tcl + +INTEL_DEPS += ../intel/common/ad_mul.v +INTEL_DEPS += ../intel/common/up_clock_mon_constr.sdc +INTEL_DEPS += ../intel/common/up_rst_constr.sdc +INTEL_DEPS += ../intel/common/up_xfer_cntrl_constr.sdc +INTEL_DEPS += ../intel/common/up_xfer_status_constr.sdc +INTEL_DEPS += axi_ad9122_constr.sdc +INTEL_DEPS += axi_ad9122_hw.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_ad9122/axi_ad9122.v b/adi_library/axi_ad9122/axi_ad9122.v new file mode 100644 index 00000000..14952afe --- /dev/null +++ b/adi_library/axi_ad9122/axi_ad9122.v @@ -0,0 +1,300 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9122 #( + + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter SERDES_OR_DDR_N = 1, + parameter MMCM_OR_BUFIO_N = 1, + parameter MMCM_CLKIN_PERIOD = 1.667, + parameter MMCM_VCO_DIV = 2, + parameter MMCM_VCO_MUL = 4, + parameter MMCM_CLK0_DIV = 2, + parameter MMCM_CLK1_DIV = 8, + parameter DAC_DATAPATH_DISABLE = 0, + parameter DAC_DDS_TYPE = 1, + parameter DAC_DDS_CORDIC_DW = 20, + parameter DAC_DDS_CORDIC_PHASE_DW = 18, + parameter IO_DELAY_GROUP = "dev_if_delay_group" +) ( + + // dac interface + + input dac_clk_in_p, + input dac_clk_in_n, + output dac_clk_out_p, + output dac_clk_out_n, + output dac_frame_out_p, + output dac_frame_out_n, + output [15:0] dac_data_out_p, + output [15:0] dac_data_out_n, + + // master/slave + + output dac_sync_out, + input dac_sync_in, + + // dma interface + + output dac_div_clk, + output dac_valid_0, + output dac_enable_0, + input [63:0] dac_ddata_0, + output dac_valid_1, + output dac_enable_1, + input [63:0] dac_ddata_1, + input dac_dunf, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot +); + + // internal clocks and resets + + wire dac_rst; + wire mmcm_rst; + wire up_clk; + wire up_rstn; + + // internal signals + + wire dac_frame_i0_s; + wire [15:0] dac_data_i0_s; + wire dac_frame_i1_s; + wire [15:0] dac_data_i1_s; + wire dac_frame_i2_s; + wire [15:0] dac_data_i2_s; + wire dac_frame_i3_s; + wire [15:0] dac_data_i3_s; + wire dac_frame_q0_s; + wire [15:0] dac_data_q0_s; + wire dac_frame_q1_s; + wire [15:0] dac_data_q1_s; + wire dac_frame_q2_s; + wire [15:0] dac_data_q2_s; + wire dac_frame_q3_s; + wire [15:0] dac_data_q3_s; + wire dac_status_s; + wire up_drp_sel_s; + wire up_drp_wr_s; + wire [11:0] up_drp_addr_s; + wire [31:0] up_drp_wdata_s; + wire [31:0] up_drp_rdata_s; + wire up_drp_ready_s; + wire up_drp_locked_s; + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire up_wack_s; + wire up_rreq_s; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_s; + wire up_rack_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // device interface + + axi_ad9122_if #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .SERDES_OR_DDR_N (SERDES_OR_DDR_N), + .MMCM_OR_BUFIO_N (MMCM_OR_BUFIO_N), + .MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD), + .MMCM_VCO_DIV (MMCM_VCO_DIV), + .MMCM_VCO_MUL (MMCM_VCO_MUL), + .MMCM_CLK0_DIV (MMCM_CLK0_DIV), + .MMCM_CLK1_DIV (MMCM_CLK1_DIV) + ) i_if ( + .dac_clk_in_p (dac_clk_in_p), + .dac_clk_in_n (dac_clk_in_n), + .dac_clk_out_p (dac_clk_out_p), + .dac_clk_out_n (dac_clk_out_n), + .dac_frame_out_p (dac_frame_out_p), + .dac_frame_out_n (dac_frame_out_n), + .dac_data_out_p (dac_data_out_p), + .dac_data_out_n (dac_data_out_n), + .dac_rst (dac_rst), + .dac_clk (), + .dac_div_clk (dac_div_clk), + .dac_status (dac_status_s), + .dac_frame_i0 (dac_frame_i0_s), + .dac_data_i0 (dac_data_i0_s), + .dac_frame_i1 (dac_frame_i1_s), + .dac_data_i1 (dac_data_i1_s), + .dac_frame_i2 (dac_frame_i2_s), + .dac_data_i2 (dac_data_i2_s), + .dac_frame_i3 (dac_frame_i3_s), + .dac_data_i3 (dac_data_i3_s), + .dac_frame_q0 (dac_frame_q0_s), + .dac_data_q0 (dac_data_q0_s), + .dac_frame_q1 (dac_frame_q1_s), + .dac_data_q1 (dac_data_q1_s), + .dac_frame_q2 (dac_frame_q2_s), + .dac_data_q2 (dac_data_q2_s), + .dac_frame_q3 (dac_frame_q3_s), + .dac_data_q3 (dac_data_q3_s), + .mmcm_rst (mmcm_rst), + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_drp_sel (up_drp_sel_s), + .up_drp_wr (up_drp_wr_s), + .up_drp_addr (up_drp_addr_s), + .up_drp_wdata (up_drp_wdata_s), + .up_drp_rdata (up_drp_rdata_s), + .up_drp_ready (up_drp_ready_s), + .up_drp_locked (up_drp_locked_s)); + + // core + + axi_ad9122_core #( + .ID(ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE) + ) i_core ( + .dac_div_clk (dac_div_clk), + .dac_rst (dac_rst), + .dac_frame_i0 (dac_frame_i0_s), + .dac_data_i0 (dac_data_i0_s), + .dac_frame_i1 (dac_frame_i1_s), + .dac_data_i1 (dac_data_i1_s), + .dac_frame_i2 (dac_frame_i2_s), + .dac_data_i2 (dac_data_i2_s), + .dac_frame_i3 (dac_frame_i3_s), + .dac_data_i3 (dac_data_i3_s), + .dac_frame_q0 (dac_frame_q0_s), + .dac_data_q0 (dac_data_q0_s), + .dac_frame_q1 (dac_frame_q1_s), + .dac_data_q1 (dac_data_q1_s), + .dac_frame_q2 (dac_frame_q2_s), + .dac_data_q2 (dac_data_q2_s), + .dac_frame_q3 (dac_frame_q3_s), + .dac_data_q3 (dac_data_q3_s), + .dac_status (dac_status_s), + .dac_sync_out (dac_sync_out), + .dac_sync_in (dac_sync_in), + .dac_valid_0 (dac_valid_0), + .dac_enable_0 (dac_enable_0), + .dac_ddata_0 (dac_ddata_0), + .dac_valid_1 (dac_valid_1), + .dac_enable_1 (dac_enable_1), + .dac_ddata_1 (dac_ddata_1), + .dac_dunf (dac_dunf), + .mmcm_rst (mmcm_rst), + .up_drp_sel (up_drp_sel_s), + .up_drp_wr (up_drp_wr_s), + .up_drp_addr (up_drp_addr_s), + .up_drp_wdata (up_drp_wdata_s), + .up_drp_rdata (up_drp_rdata_s), + .up_drp_ready (up_drp_ready_s), + .up_drp_locked (up_drp_locked_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + +endmodule diff --git a/adi_library/axi_ad9122/axi_ad9122.xpr b/adi_library/axi_ad9122/axi_ad9122.xpr new file mode 100644 index 00000000..1f428c6f --- /dev/null +++ b/adi_library/axi_ad9122/axi_ad9122.xpr @@ -0,0 +1,576 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_ad9122/axi_ad9122_channel.v b/adi_library/axi_ad9122/axi_ad9122_channel.v new file mode 100644 index 00000000..7fecc676 --- /dev/null +++ b/adi_library/axi_ad9122/axi_ad9122_channel.v @@ -0,0 +1,178 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9122_channel #( + + parameter CHANNEL_ID = 32'h0, + parameter DAC_DDS_TYPE = 1, + parameter DAC_DDS_CORDIC_DW = 16, + parameter DAC_DDS_CORDIC_PHASE_DW = 16, + parameter DATAPATH_DISABLE = 0 +) ( + + // dac interface + + input dac_div_clk, + input dac_rst, + output reg dac_enable, + output reg [63:0] dac_data, + output reg [ 3:0] dac_frame, + input [63:0] dma_data, + + // processor interface + + input dac_data_frame, + input dac_data_sync, + input dac_dds_format, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // internal signals + + wire [15:0] dac_dds_data_s; + wire [15:0] dac_dds_scale_1_s; + wire [15:0] dac_dds_init_1_s; + wire [15:0] dac_dds_incr_1_s; + wire [15:0] dac_dds_scale_2_s; + wire [15:0] dac_dds_init_2_s; + wire [15:0] dac_dds_incr_2_s; + wire [15:0] dac_pat_data_1_s; + wire [15:0] dac_pat_data_2_s; + wire [ 3:0] dac_data_sel_s; + + // dac data select + + always @(posedge dac_div_clk) begin + dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; + case (dac_data_sel_s) + 4'h2: dac_data <= dma_data; + 4'ha, 4'h1: dac_data <= {dac_pat_data_2_s, dac_pat_data_1_s, + dac_pat_data_2_s, dac_pat_data_1_s}; + default: dac_data <= dac_dds_data_s; + endcase + if (dac_data_sel_s == 4'h1) begin + dac_frame <= 4'b0101; + end else begin + dac_frame <= {3'd0, dac_data_frame}; + end + end + + // dds + + ad_dds #( + .DISABLE (DATAPATH_DISABLE), + .DDS_DW (16), + .PHASE_DW (16), + .DDS_TYPE (DAC_DDS_TYPE), + .CORDIC_DW (DAC_DDS_CORDIC_DW), + .CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .CLK_RATIO (4) + ) i_dds ( + .clk (dac_clk), + .dac_dds_format (dac_dds_format), + .dac_data_sync (dac_data_sync), + .dac_valid (1'b1), + .tone_1_scale (dac_dds_scale_1_s), + .tone_2_scale (dac_dds_scale_2_s), + .tone_1_init_offset (dac_dds_init_1_s), + .tone_2_init_offset (dac_dds_init_2_s), + .tone_1_freq_word (dac_dds_init_2_s), + .tone_2_freq_word (dac_dds_incr_2_s), + .dac_dds_data (dac_dds_data_s)); + + // single channel processor + + up_dac_channel #( + .COMMON_ID (6'h11), + .CHANNEL_ID(CHANNEL_ID), + .DDS_DISABLE (0), + .USERPORTS_DISABLE (0), + .IQCORRECTION_DISABLE (0) + ) i_up_dac_channel ( + .dac_clk (dac_div_clk), + .dac_rst (dac_rst), + .dac_dds_scale_1 (dac_dds_scale_1_s), + .dac_dds_init_1 (dac_dds_init_1_s), + .dac_dds_incr_1 (dac_dds_incr_1_s), + .dac_dds_scale_2 (dac_dds_scale_2_s), + .dac_dds_init_2 (dac_dds_init_2_s), + .dac_dds_incr_2 (dac_dds_incr_2_s), + .dac_pat_data_1 (dac_pat_data_1_s), + .dac_pat_data_2 (dac_pat_data_2_s), + .dac_data_sel (dac_data_sel_s), + .dac_iq_mode (), + .dac_iqcor_enb (), + .dac_iqcor_coeff_1 (), + .dac_iqcor_coeff_2 (), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_interpolation_m (), + .up_usr_interpolation_n (), + .dac_usr_datatype_be (1'b0), + .dac_usr_datatype_signed (1'b1), + .dac_usr_datatype_shift (8'd0), + .dac_usr_datatype_total_bits (8'd16), + .dac_usr_datatype_bits (8'd16), + .dac_usr_interpolation_m (16'd1), + .dac_usr_interpolation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ad9122/axi_ad9122_constr.sdc b/adi_library/axi_ad9122/axi_ad9122_constr.sdc new file mode 100644 index 00000000..bd13d026 --- /dev/null +++ b/adi_library/axi_ad9122/axi_ad9122_constr.sdc @@ -0,0 +1,7 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_false_path -from [get_registers *up_drp_locked*] -to [get_registers *dac_status_m1*] + diff --git a/adi_library/axi_ad9122/axi_ad9122_constr.xdc b/adi_library/axi_ad9122/axi_ad9122_constr.xdc new file mode 100644 index 00000000..12ff9639 --- /dev/null +++ b/adi_library/axi_ad9122/axi_ad9122_constr.xdc @@ -0,0 +1,7 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_false_path -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *dac_status_m1_reg && IS_SEQUENTIAL}] diff --git a/adi_library/axi_ad9122/axi_ad9122_core.v b/adi_library/axi_ad9122/axi_ad9122_core.v new file mode 100644 index 00000000..4b701488 --- /dev/null +++ b/adi_library/axi_ad9122/axi_ad9122_core.v @@ -0,0 +1,273 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9122_core #( + + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter DAC_DDS_TYPE = 1, + parameter DAC_DDS_CORDIC_DW = 16, + parameter DAC_DDS_CORDIC_PHASE_DW = 16, + parameter DATAPATH_DISABLE = 0 +) ( + + // dac interface + + input dac_div_clk, + output dac_rst, + output dac_frame_i0, + output [15:0] dac_data_i0, + output dac_frame_i1, + output [15:0] dac_data_i1, + output dac_frame_i2, + output [15:0] dac_data_i2, + output dac_frame_i3, + output [15:0] dac_data_i3, + output dac_frame_q0, + output [15:0] dac_data_q0, + output dac_frame_q1, + output [15:0] dac_data_q1, + output dac_frame_q2, + output [15:0] dac_data_q2, + output dac_frame_q3, + output [15:0] dac_data_q3, + input dac_status, + + // master/slave + + output dac_sync_out, + input dac_sync_in, + + // dma interface + + output dac_valid_0, + output dac_enable_0, + input [63:0] dac_ddata_0, + output dac_valid_1, + output dac_enable_1, + input [63:0] dac_ddata_1, + input dac_dunf, + + // mmcm reset + + output mmcm_rst, + + // drp interface + + output up_drp_sel, + output up_drp_wr, + output [11:0] up_drp_addr, + output [31:0] up_drp_wdata, + input [31:0] up_drp_rdata, + input up_drp_ready, + input up_drp_locked, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack +); + + // internal registers + + // internal signals + + wire dac_sync_s; + wire dac_frame_s; + wire dac_datafmt_s; + wire [31:0] up_rdata_0_s; + wire up_rack_0_s; + wire up_wack_0_s; + wire [31:0] up_rdata_1_s; + wire up_rack_1_s; + wire up_wack_1_s; + wire [31:0] up_rdata_s; + wire up_rack_s; + wire up_wack_s; + + // defaults + + assign dac_valid_0 = 1'b1; + assign dac_valid_1 = 1'b1; + + // master/slave (clocks must be synchronous) + + assign dac_sync_s = (ID == 0) ? dac_sync_out : dac_sync_in; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_rdata <= up_rdata_s | up_rdata_0_s | up_rdata_1_s; + up_rack <= up_rack_s | up_rack_0_s | up_rack_1_s; + up_wack <= up_wack_s | up_wack_0_s | up_wack_1_s; + end + end + + // dac channel + + axi_ad9122_channel #( + .CHANNEL_ID(0), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .DATAPATH_DISABLE(DATAPATH_DISABLE) + ) i_channel_0 ( + .dac_div_clk (dac_div_clk), + .dac_rst (dac_rst), + .dac_enable (dac_enable_0), + .dac_data ({dac_data_i3, dac_data_i2, dac_data_i1, dac_data_i0}), + .dac_frame ({dac_frame_i3, dac_frame_i2, dac_frame_i1, dac_frame_i0}), + .dma_data (dac_ddata_0), + .dac_data_frame (dac_frame_s), + .dac_data_sync (dac_sync_s), + .dac_dds_format (dac_datafmt_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_0_s), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_0_s), + .up_rack (up_rack_0_s)); + + // dac channel + + axi_ad9122_channel #( + .CHANNEL_ID(1), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .DATAPATH_DISABLE(DATAPATH_DISABLE) + ) i_channel_1 ( + .dac_div_clk (dac_div_clk), + .dac_rst (dac_rst), + .dac_enable (dac_enable_1), + .dac_data ({dac_data_q3, dac_data_q2, dac_data_q1, dac_data_q0}), + .dac_frame ({dac_frame_q3, dac_frame_q2, dac_frame_q1, dac_frame_q0}), + .dma_data (dac_ddata_1), + .dac_data_frame (dac_frame_s), + .dac_data_sync (dac_sync_s), + .dac_dds_format (dac_datafmt_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_1_s), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_1_s), + .up_rack (up_rack_1_s)); + + // dac common processor interface + + up_dac_common #( + .ID(ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .CONFIG (0), + .CLK_EDGE_SEL (0), + .COMMON_ID (6'h10), + .DRP_DISABLE (6'h00), + .USERPORTS_DISABLE (0), + .GPIO_DISABLE (0) + ) i_up_dac_common ( + .mmcm_rst (mmcm_rst), + .dac_clk (dac_div_clk), + .dac_rst (dac_rst), + .dac_sync (dac_sync_out), + .dac_frame (dac_frame_s), + .dac_clksel (), + .dac_custom_wr(), + .dac_custom_rd(32'b0), + .dac_custom_control(), + .dac_status_if_busy(1'b0), + .dac_par_type (), + .dac_par_enb (), + .dac_r1_mode (), + .dac_datafmt (dac_datafmt_s), + .dac_datarate (), + .dac_status (dac_status), + .dac_status_unf (dac_dunf), + .dac_clk_ratio (32'd4), + .up_dac_ce (), + .up_pps_rcounter(32'd0), + .up_pps_status(1'd0), + .up_pps_irq_mask(), + .up_drp_sel (up_drp_sel), + .up_drp_wr (up_drp_wr), + .up_drp_addr (up_drp_addr), + .up_drp_wdata (up_drp_wdata), + .up_drp_rdata (up_drp_rdata), + .up_drp_ready (up_drp_ready), + .up_drp_locked (up_drp_locked), + .up_usr_chanmax (), + .dac_usr_chanmax (8'd3), + .up_dac_gpio_in (32'd0), + .up_dac_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + +endmodule diff --git a/adi_library/axi_ad9122/axi_ad9122_hw.tcl b/adi_library/axi_ad9122/axi_ad9122_hw.tcl new file mode 100644 index 00000000..d222feaa --- /dev/null +++ b/adi_library/axi_ad9122/axi_ad9122_hw.tcl @@ -0,0 +1,120 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +package require quartus::device + +source ../../scripts/adi_env.tcl +source ../scripts/adi_ip_intel.tcl + +ad_ip_create axi_ad9122 {AXI AD9122 Interface} +set_module_property VALIDATION_CALLBACK info_param_validate + +ad_ip_files axi_ad9122 [list \ + $ad_hdl_dir/library/common/ad_dds_cordic_pipe.v \ + $ad_hdl_dir/library/common/ad_dds_sine_cordic.v \ + $ad_hdl_dir/library/common/ad_dds_sine.v \ + $ad_hdl_dir/library/common/ad_dds_2.v \ + $ad_hdl_dir/library/common/ad_dds_1.v \ + $ad_hdl_dir/library/common/ad_dds.v \ + $ad_hdl_dir/library/intel/common/ad_mul.v \ + $ad_hdl_dir/library/common/ad_rst.v \ + $ad_hdl_dir/library/common/up_axi.v \ + $ad_hdl_dir/library/common/up_xfer_cntrl.v \ + $ad_hdl_dir/library/common/up_xfer_status.v \ + $ad_hdl_dir/library/common/up_clock_mon.v \ + $ad_hdl_dir/library/common/up_dac_common.v \ + $ad_hdl_dir/library/common/up_dac_channel.v \ + axi_ad9122_channel.v \ + axi_ad9122_core.v \ + axi_ad9122_if.v \ + axi_ad9122.v \ + $ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_rst_constr.sdc \ + axi_ad9122_constr.sdc] \ + axi_ad9122_fileset + +# parameters + +add_parameter ID INTEGER 0 +set_parameter_property ID DEFAULT_VALUE 0 +set_parameter_property ID DISPLAY_NAME ID +set_parameter_property ID UNITS None +set_parameter_property ID HDL_PARAMETER true + +add_parameter FPGA_TECHNOLOGY INTEGER 0 +set_parameter_property FPGA_TECHNOLOGY DEFAULT_VALUE 0 +set_parameter_property FPGA_TECHNOLOGY DISPLAY_NAME FPGA_TECHNOLOGY +set_parameter_property FPGA_TECHNOLOGY TYPE INTEGER +set_parameter_property FPGA_TECHNOLOGY UNITS None +set_parameter_property FPGA_TECHNOLOGY HDL_PARAMETER true + +adi_add_auto_fpga_spec_params + +# axi4 slave + +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn + +# dac device interface + +add_interface device_if conduit end +set_interface_property device_if associatedClock none +set_interface_property device_if associatedReset none + +add_interface_port device_if dac_clk_in_p dac_clk_in_p Input 1 +add_interface_port device_if dac_clk_in_n dac_clk_in_n Input 1 +add_interface_port device_if dac_clk_out_p dac_clk_out_p Output 1 +add_interface_port device_if dac_clk_out_n dac_clk_out_n Output 1 +add_interface_port device_if dac_frame_out_p dac_frame_out_p Output 1 +add_interface_port device_if dac_frame_out_n dac_frame_out_n Output 1 +add_interface_port device_if dac_data_out_p dac_data_out_p Output 16 +add_interface_port device_if dac_data_out_n dac_data_out_n Output 16 + +add_interface_port device_if dac_sync_out dac_sync_out Output 1 +add_interface_port device_if dac_sync_in dac_sync_in Input 1 + +# dma interface + +ad_interface clock dac_div_clk Output 1 + +add_interface dac_ch_0 conduit end +add_interface_port dac_ch_0 dac_valid_0 valid Output 1 +add_interface_port dac_ch_0 dac_enable_0 enable Output 1 +add_interface_port dac_ch_0 dac_ddata_0 data Input 64 +set_interface_property dac_ch_0 associatedClock if_dac_div_clk +set_interface_property dac_ch_0 associatedReset none + +add_interface dac_ch_1 conduit end +add_interface_port dac_ch_1 dac_valid_1 valid Output 1 +add_interface_port dac_ch_1 dac_enable_1 enable Output 1 +add_interface_port dac_ch_1 dac_ddata_1 data Input 64 +set_interface_property dac_ch_1 associatedClock if_dac_div_clk +set_interface_property dac_ch_1 associatedReset none + +ad_interface signal dac_dunf input 1 unf + +# SERDES instances and configurations + +add_hdl_instance ad_serdes_clk_core_tx intel_serdes +set_instance_parameter_value ad_serdes_clk_core_tx {MODE} {CLK} +set_instance_parameter_value ad_serdes_clk_core_tx {DDR_OR_SDR_N} {1} +set_instance_parameter_value ad_serdes_clk_core_tx {SERDES_FACTOR} {8} +set_instance_parameter_value ad_serdes_clk_core_tx {CLKIN_FREQUENCY} {500.0} + +add_hdl_instance ad_serdes_out_core intel_serdes +set_instance_parameter_value ad_serdes_out_core {MODE} {OUT} +set_instance_parameter_value ad_serdes_out_core {DDR_OR_SDR_N} {1} +set_instance_parameter_value ad_serdes_out_core {SERDES_FACTOR} {8} +set_instance_parameter_value ad_serdes_out_core {CLKIN_FREQUENCY} {500.0} + +proc axi_ad9122_fileset { entityName } { + + ad_ip_modfile ad_serdes_out.v ad_serdes_out.v ad_serdes_out_core + ad_ip_modfile ad_serdes_clk.v ad_serdes_clk.v ad_serdes_clk_core_tx + +} + diff --git a/adi_library/axi_ad9122/axi_ad9122_if.v b/adi_library/axi_ad9122/axi_ad9122_if.v new file mode 100644 index 00000000..4f9ba61d --- /dev/null +++ b/adi_library/axi_ad9122/axi_ad9122_if.v @@ -0,0 +1,225 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// This is the dac physical interface (drives samples from the low speed clock to the +// dac clock domain. + +`timescale 1ns/100ps + +module axi_ad9122_if #( + + parameter FPGA_TECHNOLOGY = 0, + parameter SERDES_OR_DDR_N = 1, + parameter MMCM_OR_BUFIO_N = 1, + parameter MMCM_CLKIN_PERIOD = 1.667, + parameter MMCM_VCO_DIV = 6, + parameter MMCM_VCO_MUL = 12, + parameter MMCM_CLK0_DIV = 2, + parameter MMCM_CLK1_DIV = 8, + parameter IO_DELAY_GROUP = "dac_if_delay_group" +) ( + + // dac interface + + input dac_clk_in_p, + input dac_clk_in_n, + output dac_clk_out_p, + output dac_clk_out_n, + output dac_frame_out_p, + output dac_frame_out_n, + output [15:0] dac_data_out_p, + output [15:0] dac_data_out_n, + + // internal resets and clocks + + input dac_rst, + output dac_clk, + output dac_div_clk, + output reg dac_status, + + // data interface + + input dac_frame_i0, + input [15:0] dac_data_i0, + input dac_frame_i1, + input [15:0] dac_data_i1, + input dac_frame_i2, + input [15:0] dac_data_i2, + input dac_frame_i3, + input [15:0] dac_data_i3, + + input dac_frame_q0, + input [15:0] dac_data_q0, + input dac_frame_q1, + input [15:0] dac_data_q1, + input dac_frame_q2, + input [15:0] dac_data_q2, + input dac_frame_q3, + input [15:0] dac_data_q3, + + // mmcm reset + + input mmcm_rst, + + // drp interface + + input up_clk, + input up_rstn, + input up_drp_sel, + input up_drp_wr, + input [11:0] up_drp_addr, + input [31:0] up_drp_wdata, + output [31:0] up_drp_rdata, + output up_drp_ready, + output up_drp_locked +); + + // internal registers + + reg dac_status_m1 = 'd0; + + // internal signals + + wire dac_out_clk; + + // dac status + + always @(posedge dac_div_clk) begin + if (dac_rst == 1'b1) begin + dac_status_m1 <= 1'd0; + dac_status <= 1'd0; + end else begin + dac_status_m1 <= up_drp_locked; + dac_status <= dac_status_m1; + end + end + + // dac data output serdes(s) & buffers + + ad_serdes_out #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .DDR_OR_SDR_N (SERDES_OR_DDR_N), + .DATA_WIDTH (16) + ) i_serdes_out_data ( + .rst (dac_rst), + .clk (dac_clk), + .div_clk (dac_div_clk), + .data_oe (1'b1), + .data_s0 (dac_data_i0), + .data_s1 (dac_data_q0), + .data_s2 (dac_data_i1), + .data_s3 (dac_data_q1), + .data_s4 (dac_data_i2), + .data_s5 (dac_data_q2), + .data_s6 (dac_data_i3), + .data_s7 (dac_data_q3), + .data_out_se (), + .data_out_p (dac_data_out_p), + .data_out_n (dac_data_out_n)); + + // dac frame output serdes & buffer + + ad_serdes_out #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .DDR_OR_SDR_N (SERDES_OR_DDR_N), + .DATA_WIDTH (1) + ) i_serdes_out_frame ( + .rst (dac_rst), + .clk (dac_clk), + .div_clk (dac_div_clk), + .data_oe (1'b1), + .data_s0 (dac_frame_i0), + .data_s1 (dac_frame_q0), + .data_s2 (dac_frame_i1), + .data_s3 (dac_frame_q1), + .data_s4 (dac_frame_i2), + .data_s5 (dac_frame_q2), + .data_s6 (dac_frame_i3), + .data_s7 (dac_frame_q3), + .data_out_se (), + .data_out_p (dac_frame_out_p), + .data_out_n (dac_frame_out_n)); + + // dac clock output serdes & buffer + + ad_serdes_out #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .DDR_OR_SDR_N (SERDES_OR_DDR_N), + .DATA_WIDTH (1) + ) i_serdes_out_clk ( + .rst (dac_rst), + .clk (dac_clk), + .div_clk (dac_div_clk), + .data_oe (1'b1), + .data_s0 (1'b1), + .data_s1 (1'b0), + .data_s2 (1'b1), + .data_s3 (1'b0), + .data_s4 (1'b1), + .data_s5 (1'b0), + .data_s6 (1'b1), + .data_s7 (1'b0), + .data_out_se (), + .data_out_p (dac_clk_out_p), + .data_out_n (dac_clk_out_n)); + + // dac clock input buffers + + ad_serdes_clk #( + .DDR_OR_SDR_N (SERDES_OR_DDR_N), + .MMCM_OR_BUFR_N (MMCM_OR_BUFIO_N), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD), + .MMCM_VCO_DIV (MMCM_VCO_DIV), + .MMCM_VCO_MUL (MMCM_VCO_MUL), + .MMCM_CLK0_DIV (MMCM_CLK0_DIV), + .MMCM_CLK1_DIV (MMCM_CLK1_DIV) + ) i_serdes_clk ( + .rst (mmcm_rst), + .clk_in_p (dac_clk_in_p), + .clk_in_n (dac_clk_in_n), + .clk (dac_clk), + .div_clk (dac_div_clk), + .out_clk (dac_out_clk), + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_drp_sel (up_drp_sel), + .up_drp_wr (up_drp_wr), + .up_drp_addr (up_drp_addr), + .up_drp_wdata (up_drp_wdata), + .up_drp_rdata (up_drp_rdata), + .up_drp_ready (up_drp_ready), + .up_drp_locked (up_drp_locked)); + +endmodule diff --git a/adi_library/axi_ad9122/axi_ad9122_ip.tcl b/adi_library/axi_ad9122/axi_ad9122_ip.tcl new file mode 100644 index 00000000..66441036 --- /dev/null +++ b/adi_library/axi_ad9122/axi_ad9122_ip.tcl @@ -0,0 +1,58 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_ad9122 +adi_ip_files axi_ad9122 [list \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ + "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine.v" \ + "$ad_hdl_dir/library/common/ad_dds_2.v" \ + "$ad_hdl_dir/library/common/ad_dds_1.v" \ + "$ad_hdl_dir/library/common/ad_dds.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_serdes_out.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_dac_common.v" \ + "$ad_hdl_dir/library/common/up_dac_channel.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "axi_ad9122_channel.v" \ + "axi_ad9122_core.v" \ + "axi_ad9122_if.v" \ + "axi_ad9122_constr.xdc" \ + "axi_ad9122.v" ] + +adi_ip_properties axi_ad9122 + +adi_init_bd_tcl +adi_ip_bd axi_ad9122 "bd/bd.tcl" + +set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] + +ipx::infer_bus_interface dac_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface dac_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface dac_clk_out_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface dac_clk_out_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface dac_div_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + +adi_add_auto_fpga_spec_params + +ipx::create_xgui_files [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/axi_ad9122/bd/bd.tcl b/adi_library/axi_ad9122/bd/bd.tcl new file mode 100644 index 00000000..dceb9498 --- /dev/null +++ b/adi_library/axi_ad9122/bd/bd.tcl @@ -0,0 +1,47 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + DEV_PACKAGE \ + SPEED_GRADE \ + FPGA_FAMILY \ + FPGA_TECHNOLOGY" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/axi_ad9122/component.xml b/adi_library/axi_ad9122/component.xml new file mode 100644 index 00000000..dc3776d4 --- /dev/null +++ b/adi_library/axi_ad9122/component.xml @@ -0,0 +1,1473 @@ + + + analog.com + user + axi_ad9122 + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + dac_clk_in_p + + + + + + + CLK + + + dac_clk_in_p + + + + + + dac_clk_in_n + + + + + + + CLK + + + dac_clk_in_n + + + + + + dac_clk_out_p + + + + + + + CLK + + + dac_clk_out_p + + + + + + dac_clk_out_n + + + + + + + CLK + + + dac_clk_out_n + + + + + + dac_div_clk + + + + + + + CLK + + + dac_div_clk + + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_ad9122 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 95d72be9 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_ad9122 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + c583edc2 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 47aa4ecf + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + + + dac_clk_in_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_clk_in_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_clk_out_p + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_clk_out_n + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_frame_out_p + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_frame_out_n + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_data_out_p + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_data_out_n + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_sync_out + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_sync_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + dac_div_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_valid_0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_enable_0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_ddata_0 + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_valid_1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_enable_1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_ddata_1 + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_dunf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + SERDES_OR_DDR_N + Serdes Or Ddr N + 1 + + + MMCM_OR_BUFIO_N + Mmcm Or Bufio N + 1 + + + MMCM_CLKIN_PERIOD + Mmcm Clkin Period + 1.667 + + + MMCM_VCO_DIV + Mmcm Vco Div + 2 + + + MMCM_VCO_MUL + Mmcm Vco Mul + 4 + + + MMCM_CLK0_DIV + Mmcm Clk0 Div + 2 + + + MMCM_CLK1_DIV + Mmcm Clk1 Div + 8 + + + DAC_DATAPATH_DISABLE + Dac Datapath Disable + 0 + + + DAC_DDS_TYPE + Dac Dds Type + 1 + + + DAC_DDS_CORDIC_DW + Dac Dds Cordic Dw + 20 + + + DAC_DDS_CORDIC_PHASE_DW + Dac Dds Cordic Phase Dw + 18 + + + IO_DELAY_GROUP + Io Delay Group + dev_if_delay_group + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_00ecfe9a + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + + + choice_pairs_19f99f31 + 0 + 10 + 11 + 12 + 13 + 14 + 20 + 21 + 22 + 23 + 24 + 25 + 30 + + + choice_pairs_28f798a2 + 0 + 1 + 2 + 3 + 4 + + + choice_pairs_fc01a186 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../xilinx/common/up_clock_mon_constr.xdc + xdc + + + axi_ad9122_constr.xdc + xdc + + + ../common/ad_dds.v + verilogSource + + + ../common/ad_dds_1.v + verilogSource + + + ../common/ad_dds_2.v + verilogSource + + + ../common/ad_dds_cordic_pipe.v + verilogSource + + + ../common/ad_dds_sine.v + verilogSource + + + ../common/ad_dds_sine_cordic.v + verilogSource + + + ../xilinx/common/ad_mmcm_drp.v + verilogSource + + + ../xilinx/common/ad_mul.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../xilinx/common/ad_serdes_clk.v + verilogSource + + + ../xilinx/common/ad_serdes_out.v + verilogSource + + + axi_ad9122_channel.v + verilogSource + + + axi_ad9122_core.v + verilogSource + + + axi_ad9122_if.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_dac_channel.v + verilogSource + + + ../common/up_dac_common.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad9122.v + verilogSource + CHECKSUM_27052783 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_dds.v + verilogSource + + + ../common/ad_dds_1.v + verilogSource + + + ../common/ad_dds_2.v + verilogSource + + + ../common/ad_dds_cordic_pipe.v + verilogSource + + + ../common/ad_dds_sine.v + verilogSource + + + ../common/ad_dds_sine_cordic.v + verilogSource + + + ../xilinx/common/ad_mmcm_drp.v + verilogSource + + + ../xilinx/common/ad_mul.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../xilinx/common/ad_serdes_clk.v + verilogSource + + + ../xilinx/common/ad_serdes_out.v + verilogSource + + + axi_ad9122_channel.v + verilogSource + + + axi_ad9122_core.v + verilogSource + + + axi_ad9122_if.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_dac_channel.v + verilogSource + + + ../common/up_dac_common.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad9122.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_ad9122_v1_0.tcl + tclSource + CHECKSUM_15446c99 + XGUI_VERSION_2 + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + axi_ad9122_v1_0 + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + SERDES_OR_DDR_N + Serdes Or Ddr N + 1 + + + MMCM_OR_BUFIO_N + Mmcm Or Bufio N + 1 + + + MMCM_CLKIN_PERIOD + Mmcm Clkin Period + 1.667 + + + MMCM_VCO_DIV + Mmcm Vco Div + 2 + + + MMCM_VCO_MUL + Mmcm Vco Mul + 4 + + + MMCM_CLK0_DIV + Mmcm Clk0 Div + 2 + + + MMCM_CLK1_DIV + Mmcm Clk1 Div + 8 + + + DAC_DATAPATH_DISABLE + Dac Datapath Disable + 0 + + + DAC_DDS_TYPE + Dac Dds Type + 1 + + + DAC_DDS_CORDIC_DW + Dac Dds Cordic Dw + 20 + + + DAC_DDS_CORDIC_PHASE_DW + Dac Dds Cordic Phase Dw + 18 + + + IO_DELAY_GROUP + Io Delay Group + dev_if_delay_group + + + Component_Name + axi_ad9122_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_ad9122_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:39:49Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_ad9122/temporary_case_dependencies.mk b/adi_library/axi_ad9122/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/axi_ad9122/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/axi_ad9122/xgui/axi_ad9122_v1_0.tcl b/adi_library/axi_ad9122/xgui/axi_ad9122_v1_0.tcl new file mode 100644 index 00000000..a707638c --- /dev/null +++ b/adi_library/axi_ad9122/xgui/axi_ad9122_v1_0.tcl @@ -0,0 +1,268 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DAC_DATAPATH_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_DW" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_PHASE_DW" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_DDS_TYPE" -parent ${Page_0} + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "IO_DELAY_GROUP" -parent ${Page_0} + ipgui::add_param $IPINST -name "MMCM_CLK0_DIV" -parent ${Page_0} + ipgui::add_param $IPINST -name "MMCM_CLK1_DIV" -parent ${Page_0} + ipgui::add_param $IPINST -name "MMCM_CLKIN_PERIOD" -parent ${Page_0} + ipgui::add_param $IPINST -name "MMCM_OR_BUFIO_N" -parent ${Page_0} + ipgui::add_param $IPINST -name "MMCM_VCO_DIV" -parent ${Page_0} + ipgui::add_param $IPINST -name "MMCM_VCO_MUL" -parent ${Page_0} + ipgui::add_param $IPINST -name "SERDES_OR_DDR_N" -parent ${Page_0} + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } { + # Procedure called to update DAC_DATAPATH_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } { + # Procedure called to validate DAC_DATAPATH_DISABLE + return true +} + +proc update_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } { + # Procedure called to update DAC_DDS_CORDIC_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } { + # Procedure called to validate DAC_DDS_CORDIC_DW + return true +} + +proc update_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } { + # Procedure called to update DAC_DDS_CORDIC_PHASE_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } { + # Procedure called to validate DAC_DDS_CORDIC_PHASE_DW + return true +} + +proc update_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } { + # Procedure called to update DAC_DDS_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } { + # Procedure called to validate DAC_DDS_TYPE + return true +} + +proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to validate DEV_PACKAGE + return true +} + +proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to validate FPGA_FAMILY + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to update IO_DELAY_GROUP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to validate IO_DELAY_GROUP + return true +} + +proc update_PARAM_VALUE.MMCM_CLK0_DIV { PARAM_VALUE.MMCM_CLK0_DIV } { + # Procedure called to update MMCM_CLK0_DIV when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.MMCM_CLK0_DIV { PARAM_VALUE.MMCM_CLK0_DIV } { + # Procedure called to validate MMCM_CLK0_DIV + return true +} + +proc update_PARAM_VALUE.MMCM_CLK1_DIV { PARAM_VALUE.MMCM_CLK1_DIV } { + # Procedure called to update MMCM_CLK1_DIV when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.MMCM_CLK1_DIV { PARAM_VALUE.MMCM_CLK1_DIV } { + # Procedure called to validate MMCM_CLK1_DIV + return true +} + +proc update_PARAM_VALUE.MMCM_CLKIN_PERIOD { PARAM_VALUE.MMCM_CLKIN_PERIOD } { + # Procedure called to update MMCM_CLKIN_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.MMCM_CLKIN_PERIOD { PARAM_VALUE.MMCM_CLKIN_PERIOD } { + # Procedure called to validate MMCM_CLKIN_PERIOD + return true +} + +proc update_PARAM_VALUE.MMCM_OR_BUFIO_N { PARAM_VALUE.MMCM_OR_BUFIO_N } { + # Procedure called to update MMCM_OR_BUFIO_N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.MMCM_OR_BUFIO_N { PARAM_VALUE.MMCM_OR_BUFIO_N } { + # Procedure called to validate MMCM_OR_BUFIO_N + return true +} + +proc update_PARAM_VALUE.MMCM_VCO_DIV { PARAM_VALUE.MMCM_VCO_DIV } { + # Procedure called to update MMCM_VCO_DIV when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.MMCM_VCO_DIV { PARAM_VALUE.MMCM_VCO_DIV } { + # Procedure called to validate MMCM_VCO_DIV + return true +} + +proc update_PARAM_VALUE.MMCM_VCO_MUL { PARAM_VALUE.MMCM_VCO_MUL } { + # Procedure called to update MMCM_VCO_MUL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.MMCM_VCO_MUL { PARAM_VALUE.MMCM_VCO_MUL } { + # Procedure called to validate MMCM_VCO_MUL + return true +} + +proc update_PARAM_VALUE.SERDES_OR_DDR_N { PARAM_VALUE.SERDES_OR_DDR_N } { + # Procedure called to update SERDES_OR_DDR_N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SERDES_OR_DDR_N { PARAM_VALUE.SERDES_OR_DDR_N } { + # Procedure called to validate SERDES_OR_DDR_N + return true +} + +proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to validate SPEED_GRADE + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY} +} + +proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE} +} + +proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE} +} + +proc update_MODELPARAM_VALUE.SERDES_OR_DDR_N { MODELPARAM_VALUE.SERDES_OR_DDR_N PARAM_VALUE.SERDES_OR_DDR_N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SERDES_OR_DDR_N}] ${MODELPARAM_VALUE.SERDES_OR_DDR_N} +} + +proc update_MODELPARAM_VALUE.MMCM_OR_BUFIO_N { MODELPARAM_VALUE.MMCM_OR_BUFIO_N PARAM_VALUE.MMCM_OR_BUFIO_N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.MMCM_OR_BUFIO_N}] ${MODELPARAM_VALUE.MMCM_OR_BUFIO_N} +} + +proc update_MODELPARAM_VALUE.MMCM_CLKIN_PERIOD { MODELPARAM_VALUE.MMCM_CLKIN_PERIOD PARAM_VALUE.MMCM_CLKIN_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.MMCM_CLKIN_PERIOD}] ${MODELPARAM_VALUE.MMCM_CLKIN_PERIOD} +} + +proc update_MODELPARAM_VALUE.MMCM_VCO_DIV { MODELPARAM_VALUE.MMCM_VCO_DIV PARAM_VALUE.MMCM_VCO_DIV } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.MMCM_VCO_DIV}] ${MODELPARAM_VALUE.MMCM_VCO_DIV} +} + +proc update_MODELPARAM_VALUE.MMCM_VCO_MUL { MODELPARAM_VALUE.MMCM_VCO_MUL PARAM_VALUE.MMCM_VCO_MUL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.MMCM_VCO_MUL}] ${MODELPARAM_VALUE.MMCM_VCO_MUL} +} + +proc update_MODELPARAM_VALUE.MMCM_CLK0_DIV { MODELPARAM_VALUE.MMCM_CLK0_DIV PARAM_VALUE.MMCM_CLK0_DIV } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.MMCM_CLK0_DIV}] ${MODELPARAM_VALUE.MMCM_CLK0_DIV} +} + +proc update_MODELPARAM_VALUE.MMCM_CLK1_DIV { MODELPARAM_VALUE.MMCM_CLK1_DIV PARAM_VALUE.MMCM_CLK1_DIV } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.MMCM_CLK1_DIV}] ${MODELPARAM_VALUE.MMCM_CLK1_DIV} +} + +proc update_MODELPARAM_VALUE.DAC_DATAPATH_DISABLE { MODELPARAM_VALUE.DAC_DATAPATH_DISABLE PARAM_VALUE.DAC_DATAPATH_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_DATAPATH_DISABLE}] ${MODELPARAM_VALUE.DAC_DATAPATH_DISABLE} +} + +proc update_MODELPARAM_VALUE.DAC_DDS_TYPE { MODELPARAM_VALUE.DAC_DDS_TYPE PARAM_VALUE.DAC_DDS_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_DDS_TYPE}] ${MODELPARAM_VALUE.DAC_DDS_TYPE} +} + +proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_DW PARAM_VALUE.DAC_DDS_CORDIC_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_DW} +} + +proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW} +} + +proc update_MODELPARAM_VALUE.IO_DELAY_GROUP { MODELPARAM_VALUE.IO_DELAY_GROUP PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IO_DELAY_GROUP}] ${MODELPARAM_VALUE.IO_DELAY_GROUP} +} + diff --git a/adi_library/axi_ad9250/Makefile b/adi_library/axi_ad9250/Makefile new file mode 100644 index 00000000..91a00047 --- /dev/null +++ b/adi_library/axi_ad9250/Makefile @@ -0,0 +1,38 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_ad9250 + +GENERIC_DEPS += axi_ad9250.v + +XILINX_DEPS += axi_ad9250_ip.tcl + +XILINX_LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc + +INTEL_DEPS += ../common/ad_datafmt.v +INTEL_DEPS += ../common/ad_perfect_shuffle.v +INTEL_DEPS += ../common/ad_pnmon.v +INTEL_DEPS += ../common/ad_rst.v +INTEL_DEPS += ../common/ad_xcvr_rx_if.v +INTEL_DEPS += ../common/up_adc_channel.v +INTEL_DEPS += ../common/up_adc_common.v +INTEL_DEPS += ../common/up_axi.v +INTEL_DEPS += ../common/up_clock_mon.v +INTEL_DEPS += ../common/up_xfer_cntrl.v +INTEL_DEPS += ../common/up_xfer_status.v +INTEL_DEPS += ../intel/common/up_clock_mon_constr.sdc +INTEL_DEPS += ../intel/common/up_rst_constr.sdc +INTEL_DEPS += ../intel/common/up_xfer_cntrl_constr.sdc +INTEL_DEPS += ../intel/common/up_xfer_status_constr.sdc +INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v +INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v +INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v +INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v +INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v +INTEL_DEPS += ../jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v +INTEL_DEPS += axi_ad9250_hw.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_ad9250/axi_ad9250.v b/adi_library/axi_ad9250/axi_ad9250.v new file mode 100644 index 00000000..7c8f1e0e --- /dev/null +++ b/adi_library/axi_ad9250/axi_ad9250.v @@ -0,0 +1,141 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9250 #( + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0 +) ( + + // jesd interface + // rx_clk is (line-rate/40) + + input rx_clk, + input [ 3:0] rx_sof, + input rx_valid, + input [63:0] rx_data, + output rx_ready, + + // dma interface + + output adc_clk, + output adc_valid_a, + output adc_enable_a, + output [31:0] adc_data_a, + output adc_valid_b, + output adc_enable_b, + output [31:0] adc_data_b, + input adc_dovf, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [11:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [11:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready +); + + assign adc_clk = rx_clk; + + ad_ip_jesd204_tpl_adc #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .NUM_LANES (2), + .NUM_CHANNELS (2), + .SAMPLES_PER_FRAME (1), + .CONVERTER_RESOLUTION (14), + .BITS_PER_SAMPLE (16), + .OCTETS_PER_BEAT (4), + .TWOS_COMPLEMENT (1) + ) i_adc_jesd204 ( + .link_clk (rx_clk), + + .link_sof (rx_sof), + .link_valid (rx_valid), + .link_data (rx_data), + .link_ready (rx_ready), + + .enable ({adc_enable_b,adc_enable_a}), + .adc_valid ({adc_valid_b,adc_valid_a}), + .adc_data ({adc_data_b,adc_data_a}), + .adc_dovf (adc_dovf), + + .s_axi_aclk (s_axi_aclk), + .s_axi_aresetn (s_axi_aresetn), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awprot (s_axi_awprot), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready(s_axi_wready), + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bready (s_axi_bready), + .s_axi_bresp (s_axi_bresp), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), + .s_axi_araddr (s_axi_araddr), + .s_axi_arprot (s_axi_arprot), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rready (s_axi_rready), + .s_axi_rresp (s_axi_rresp), + .s_axi_rdata (s_axi_rdata)); + +endmodule diff --git a/adi_library/axi_ad9250/axi_ad9250.xpr b/adi_library/axi_ad9250/axi_ad9250.xpr new file mode 100644 index 00000000..37fa40c1 --- /dev/null +++ b/adi_library/axi_ad9250/axi_ad9250.xpr @@ -0,0 +1,406 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_ad9250/axi_ad9250_hw.tcl b/adi_library/axi_ad9250/axi_ad9250_hw.tcl new file mode 100644 index 00000000..de87265a --- /dev/null +++ b/adi_library/axi_ad9250/axi_ad9250_hw.tcl @@ -0,0 +1,95 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +package require quartus::device + +source ../../scripts/adi_env.tcl +source ../scripts/adi_ip_intel.tcl + +set_module_property NAME axi_ad9250 +set_module_property DESCRIPTION "AXI AD9250 Interface" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME axi_ad9250 +set_module_property VALIDATION_CALLBACK info_param_validate + +# files + +add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" +set_fileset_property quartus_synth TOP_LEVEL axi_ad9250 +add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v +add_fileset_file ad_perfect_shuffle.v VERILOG PATH $ad_hdl_dir/library/common/ad_perfect_shuffle.v +add_fileset_file ad_pnmon.v VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v +add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v +add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v +add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v +add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v +add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v +add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v +add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v +add_fileset_file ad_xcvr_rx_if.v VERILOG PATH $ad_hdl_dir/library/common/ad_xcvr_rx_if.v + +add_fileset_file ad_ip_jesd204_adc_pnmon.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v +add_fileset_file ad_ip_jesd204_adc_channel.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v +add_fileset_file ad_ip_jesd204_adc_core.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v +add_fileset_file ad_ip_jesd204_adc_deframer.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v +add_fileset_file ad_ip_jesd204_adc_regmap.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v +add_fileset_file ad_ip_jesd204_adc.v VERILOG PATH $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v + +add_fileset_file axi_ad9250.v VERILOG PATH axi_ad9250.v TOP_LEVEL_FILE +add_fileset_file up_xfer_cntrl_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc +add_fileset_file up_xfer_status_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc +add_fileset_file up_clock_mon_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc +add_fileset_file up_rst_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_rst_constr.sdc + +# parameters + +add_parameter ID INTEGER 0 +set_parameter_property ID DEFAULT_VALUE 0 +set_parameter_property ID DISPLAY_NAME ID +set_parameter_property ID UNITS None +set_parameter_property ID HDL_PARAMETER true + +adi_add_auto_fpga_spec_params + +# axi4 slave + +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn + +# transceiver interface + +ad_interface clock rx_clk input 1 +ad_interface signal rx_sof input 4 export + +add_interface if_rx_data avalon_streaming sink +add_interface_port if_rx_data rx_data data input 64 +add_interface_port if_rx_data rx_valid valid input 1 +add_interface_port if_rx_data rx_ready ready output 1 +set_interface_property if_rx_data associatedClock if_rx_clk +set_interface_property if_rx_data dataBitsPerSymbol 64 + +# dma interface + +ad_interface clock adc_clk output 1 + +add_interface adc_ch_0 conduit end +add_interface_port adc_ch_0 adc_enable_a enable Output 1 +add_interface_port adc_ch_0 adc_valid_a valid Output 1 +add_interface_port adc_ch_0 adc_data_a data Output 32 + +set_interface_property adc_ch_0 associatedClock if_rx_clk +set_interface_property adc_ch_0 associatedReset none + +add_interface adc_ch_1 conduit end +add_interface_port adc_ch_1 adc_enable_b enable Output 1 +add_interface_port adc_ch_1 adc_valid_b valid Output 1 +add_interface_port adc_ch_1 adc_data_b data Output 32 + +set_interface_property adc_ch_1 associatedClock if_rx_clk +set_interface_property adc_ch_1 associatedReset none + +ad_interface signal adc_dovf input 1 ovf + diff --git a/adi_library/axi_ad9250/axi_ad9250_ip.tcl b/adi_library/axi_ad9250/axi_ad9250_ip.tcl new file mode 100644 index 00000000..b525b658 --- /dev/null +++ b/adi_library/axi_ad9250/axi_ad9250_ip.tcl @@ -0,0 +1,34 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create axi_ad9250 +adi_ip_files axi_ad9250 [list \ + "axi_ad9250.v" ] + +adi_ip_properties axi_ad9250 + +adi_init_bd_tcl +adi_ip_bd axi_ad9250 "bd/bd.tcl" + +adi_ip_add_core_dependencies [list \ + analog.com:$VIVADO_IP_LIBRARY:ad_ip_jesd204_tpl_adc:1.0 \ +] + +set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] + +ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + +ipx::save_core [ipx::current_core] diff --git a/adi_library/axi_ad9250/bd/bd.tcl b/adi_library/axi_ad9250/bd/bd.tcl new file mode 100644 index 00000000..dceb9498 --- /dev/null +++ b/adi_library/axi_ad9250/bd/bd.tcl @@ -0,0 +1,47 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + DEV_PACKAGE \ + SPEED_GRADE \ + FPGA_FAMILY \ + FPGA_TECHNOLOGY" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/axi_ad9250/component.xml b/adi_library/axi_ad9250/component.xml new file mode 100644 index 00000000..73eb7a71 --- /dev/null +++ b/adi_library/axi_ad9250/component.xml @@ -0,0 +1,1111 @@ + + + analog.com + user + axi_ad9250 + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + rx_clk + + + + + + + CLK + + + rx_clk + + + + + + adc_clk + + + + + + + CLK + + + adc_clk + + + + + + + + s_axi + + axi_lite + 0 + 4096 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_ad9250 + + xilinx_anylanguagesynthesis_analog_com_user_ad_ip_jesd204_tpl_adc_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 8673dcf2 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_ad9250 + + xilinx_anylanguagebehavioralsimulation_analog_com_user_ad_ip_jesd204_tpl_adc_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 8673dcf2 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_analog_com_user_ad_ip_jesd204_tpl_adc_1_0__ref_view_fileset + + + xilinx_xpgui_view_fileset + + + + viewChecksum + 783e7a8b + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_analog_com_user_ad_ip_jesd204_tpl_adc_1_0__ref_view_fileset + + + xilinx_blockdiagram_view_fileset + + + + + + rx_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_sof + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + rx_data + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + rx_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid_a + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_a + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_a + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid_b + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_b + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_b + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_dovf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 11 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 11 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_00ecfe9a + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + + + choice_pairs_19f99f31 + 0 + 10 + 11 + 12 + 13 + 14 + 20 + 21 + 22 + 23 + 24 + 25 + 30 + + + choice_pairs_28f798a2 + 0 + 1 + 2 + 3 + 4 + + + choice_pairs_fc01a186 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + + + xilinx_anylanguagesynthesis_view_fileset + + axi_ad9250.v + verilogSource + CHECKSUM_8673dcf2 + + + + xilinx_anylanguagesynthesis_analog_com_user_ad_ip_jesd204_tpl_adc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + axi_ad9250.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_ad_ip_jesd204_tpl_adc_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axi_ad9250_v1_0.tcl + tclSource + CHECKSUM_14b777a3 + XGUI_VERSION_2 + + + + xilinx_xpgui_analog_com_user_ad_ip_jesd204_tpl_adc_1_0__ref_view_fileset + + + + + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + xilinx_blockdiagram_analog_com_user_ad_ip_jesd204_tpl_adc_1_0__ref_view_fileset + + + + + + + + axi_ad9250_v1_0 + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + Component_Name + axi_ad9250_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_ad9250_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:40:16Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_ad9250/temporary_case_dependencies.mk b/adi_library/axi_ad9250/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/axi_ad9250/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/axi_ad9250/xgui/axi_ad9250_v1_0.tcl b/adi_library/axi_ad9250/xgui/axi_ad9250_v1_0.tcl new file mode 100644 index 00000000..815d3254 --- /dev/null +++ b/adi_library/axi_ad9250/xgui/axi_ad9250_v1_0.tcl @@ -0,0 +1,88 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to validate DEV_PACKAGE + return true +} + +proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to validate FPGA_FAMILY + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to validate SPEED_GRADE + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY} +} + +proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE} +} + +proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE} +} + diff --git a/adi_library/axi_ad9265/Makefile b/adi_library/axi_ad9265/Makefile new file mode 100644 index 00000000..5a88597e --- /dev/null +++ b/adi_library/axi_ad9265/Makefile @@ -0,0 +1,33 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_ad9265 + +GENERIC_DEPS += ../common/ad_datafmt.v +GENERIC_DEPS += ../common/ad_pnmon.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_adc_channel.v +GENERIC_DEPS += ../common/up_adc_common.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_delay_cntrl.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_ad9265.v +GENERIC_DEPS += axi_ad9265_channel.v +GENERIC_DEPS += axi_ad9265_if.v +GENERIC_DEPS += axi_ad9265_pnmon.v + +XILINX_DEPS += ../xilinx/common/ad_data_clk.v +XILINX_DEPS += ../xilinx/common/ad_data_in.v +XILINX_DEPS += ../xilinx/common/ad_dcfilter.v +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_ad9265_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_ad9265/axi_ad9265.v b/adi_library/axi_ad9265/axi_ad9265.v new file mode 100644 index 00000000..92b5b164 --- /dev/null +++ b/adi_library/axi_ad9265/axi_ad9265.v @@ -0,0 +1,333 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9265 #( + + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter ADC_DATAPATH_DISABLE = 0, + parameter IO_DELAY_GROUP = "adc_if_delay_group" +) ( + + // adc interface (clk, data, over-range) + + input adc_clk_in_p, + input adc_clk_in_n, + input [ 7:0] adc_data_in_p, + input [ 7:0] adc_data_in_n, + input adc_or_in_p, + input adc_or_in_n, + + // delay interface + + input delay_clk, + + // dma interface + + output adc_clk, + output adc_rst, + output adc_valid, + output adc_enable, + output [15:0] adc_data, + input adc_dovf, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot +); + + // internal registers + + reg up_status_pn_err = 'd0; + reg up_status_pn_oos = 'd0; + reg up_status_or = 'd0; + reg [31:0] up_rdata = 'd0; + reg up_wack = 'd0; + reg up_rack = 'd0; + + // internal clocks & resets + + wire up_rstn; + wire up_clk; + wire delay_rst; + + // internal signals + + wire [15:0] adc_data_s; + wire adc_or_s; + wire up_status_pn_err_s; + wire up_status_pn_oos_s; + wire up_status_or_s; + wire adc_status_s; + wire [ 8:0] up_dld_s; + wire [44:0] up_dwdata_s; + wire [44:0] up_drdata_s; + wire delay_locked_s; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_s[0:2]; + wire up_rack_s[0:2]; + wire up_wack_s[0:2]; + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire up_rreq_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_status_pn_err <= 'd0; + up_status_pn_oos <= 'd0; + up_status_or <= 'd0; + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_status_pn_err <= up_status_pn_err_s; + up_status_pn_oos <= up_status_pn_oos_s; + up_status_or <= up_status_or_s; + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2]; + up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2]; + up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2]; + end + end + + // channel + + axi_ad9265_channel #( + .CHANNEL_ID(0), + .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE) + ) i_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_data_s), + .adc_or (adc_or_s), + .adc_dcfilter_data_out (adc_data), + .adc_enable (adc_enable), + .adc_valid (adc_valid), + .up_adc_pn_err (up_status_pn_err_s), + .up_adc_pn_oos (up_status_pn_oos_s), + .up_adc_or (up_status_or_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // main (device interface) + + axi_ad9265_if #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IO_DELAY_GROUP (IO_DELAY_GROUP) + ) i_if ( + .adc_clk_in_p (adc_clk_in_p), + .adc_clk_in_n (adc_clk_in_n), + .adc_data_in_p (adc_data_in_p), + .adc_data_in_n (adc_data_in_n), + .adc_or_in_p (adc_or_in_p), + .adc_or_in_n (adc_or_in_n), + .adc_clk (adc_clk), + .adc_data (adc_data_s), + .adc_or (adc_or_s), + .adc_status (adc_status_s), + .up_clk (up_clk), + .up_dld (up_dld_s), + .up_dwdata (up_dwdata_s), + .up_drdata (up_drdata_s), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s)); + + // adc delay control + + up_delay_cntrl #( + .DATA_WIDTH(9), + .BASE_ADDRESS(6'h02) + ) i_delay_cntrl ( + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s), + .up_dld (up_dld_s), + .up_dwdata (up_dwdata_s), + .up_drdata (up_drdata_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + // common processor control + + up_adc_common #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .CONFIG (0), + .COMMON_ID (6'h00), + .DRP_DISABLE (6'h00), + .USERPORTS_DISABLE (0), + .GPIO_DISABLE (0), + .START_CODE_DISABLE(0) + ) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (adc_status_s), + .adc_sync_status (1'd0), + .adc_status_ovf (adc_dovf), + .adc_clk_ratio (32'd1), + .adc_start_code (), + .adc_sref_sync (), + .adc_sync (), + .adc_ext_sync_arm (), + .adc_ext_sync_disarm (), + .adc_ext_sync_manual_req (), + .adc_num_lanes (), + .adc_custom_control (), + .adc_crc_enable (), + .adc_sdr_ddr_n (), + .adc_symb_op (), + .adc_symb_8_16b (), + .up_pps_rcounter(32'd0), + .up_pps_status(1'd0), + .up_pps_irq_mask(), + .up_adc_r1_mode (), + .up_adc_ce (), + .up_status_pn_err (up_status_pn_err), + .up_status_pn_oos (up_status_pn_oos), + .up_status_or (up_status_or), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .adc_config_wr (), + .adc_config_ctrl (), + .adc_config_rd ('d0), + .adc_ctrl_status ('d0), + .up_usr_chanmax_out (), + .up_usr_chanmax_in (8'd0), + .up_adc_gpio_in (32'd0), + .up_adc_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ad9265/axi_ad9265.xpr b/adi_library/axi_ad9265/axi_ad9265.xpr new file mode 100644 index 00000000..2592d63b --- /dev/null +++ b/adi_library/axi_ad9265/axi_ad9265.xpr @@ -0,0 +1,542 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_ad9265/axi_ad9265_channel.v b/adi_library/axi_ad9265/axi_ad9265_channel.v new file mode 100644 index 00000000..9eb736fe --- /dev/null +++ b/adi_library/axi_ad9265/axi_ad9265_channel.v @@ -0,0 +1,187 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// ADC channel- + +`timescale 1ns/100ps + +module axi_ad9265_channel #( + + parameter CHANNEL_ID = 0, + parameter DATAPATH_DISABLE = 0 +) ( + + // adc interface + + input adc_clk, + input adc_rst, + input [15:0] adc_data, + input adc_or, + + // channel interface + + output [15:0] adc_dcfilter_data_out, + output adc_valid, + output adc_enable, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // internal signals + + wire [15:0] adc_dfmt_data_s; + wire adc_dcfilt_enb_s; + wire adc_dfmt_se_s; + wire adc_dfmt_type_s; + wire adc_dfmt_enable_s; + wire [15:0] adc_dcfilt_offset_s; + wire [15:0] adc_dcfilt_coeff_s; + wire [ 3:0] adc_pnseq_sel_s; + wire adc_pn_err_s; + wire adc_pn_oos_s; + + // iq correction inputs + + axi_ad9265_pnmon i_pnmon ( + .adc_clk (adc_clk), + .adc_data (adc_data), + .adc_pn_oos (adc_pn_oos_s), + .adc_pn_err (adc_pn_err_s), + .adc_pnseq_sel (adc_pnseq_sel_s)); + + generate + if (DATAPATH_DISABLE == 1) begin + assign adc_dfmt_data_s = adc_data; + end else begin + ad_datafmt #( + .DATA_WIDTH(16) + ) i_ad_datafmt ( + .clk (adc_clk), + .valid (1'b1), + .data (adc_data), + .valid_out (), + .data_out (adc_dfmt_data_s), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + end + endgenerate + + generate + if (DATAPATH_DISABLE == 1) begin + assign adc_dcfilter_data_out = adc_dfmt_data_s; + end else begin + ad_dcfilter i_ad_dcfilter ( + .clk (adc_clk), + .valid (1'b1), + .data (adc_dfmt_data_s), + .valid_out (adc_valid), + .data_out (adc_dcfilter_data_out), + .dcfilt_enb (adc_dcfilt_enb_s), + .dcfilt_coeff (adc_dcfilt_coeff_s), + .dcfilt_offset (adc_dcfilt_offset_s)); + end + endgenerate + + up_adc_channel #( + .COMMON_ID (6'h01), + .CHANNEL_ID(CHANNEL_ID), + .USERPORTS_DISABLE (0), + .DATAFORMAT_DISABLE (0), + .DCFILTER_DISABLE (0), + .IQCORRECTION_DISABLE (0) + ) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (), + .adc_dcfilt_enb (adc_dcfilt_enb_s), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_dcfilt_offset (adc_dcfilt_offset_s), + .adc_dcfilt_coeff (adc_dcfilt_coeff_s), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_data_sel (), + .adc_pn_err (adc_pn_err_s), + .adc_pn_oos (adc_pn_oos_s), + .adc_or (adc_or), + .adc_read_data ('d0), + .adc_status_header ('d0), + .adc_crc_err ('d0), + .up_adc_pn_err (up_adc_pn_err), + .up_adc_pn_oos (up_adc_pn_oos), + .up_adc_or (up_adc_or), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ad9265/axi_ad9265_if.v b/adi_library/axi_ad9265/axi_ad9265_if.v new file mode 100644 index 00000000..abeb2c74 --- /dev/null +++ b/adi_library/axi_ad9265/axi_ad9265_if.v @@ -0,0 +1,153 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// This is the LVDS/DDR interface, note that overrange is independent of data path, +// software will not be able to relate overrange to a specific sample! + +`timescale 1ns/100ps + +module axi_ad9265_if #( + + parameter FPGA_TECHNOLOGY = 0, + parameter IO_DELAY_GROUP = "adc_if_delay_group", + parameter DELAY_REFCLK_FREQUENCY = 200 +) ( + + // adc interface (clk, data, over-range) + // nominal clock 125 MHz, up to 300 MHz + + input adc_clk_in_p, + input adc_clk_in_n, + input [ 7:0] adc_data_in_p, + input [ 7:0] adc_data_in_n, + input adc_or_in_p, + input adc_or_in_n, + + // interface outputs + + output adc_clk, + output reg [15:0] adc_data, + output reg adc_or, + output reg adc_status, + + // delay control signals + + input up_clk, + input [ 8:0] up_dld, + input [44:0] up_dwdata, + output [44:0] up_drdata, + input delay_clk, + input delay_rst, + output delay_locked +); + + // internal registers + + reg [ 7:0] adc_data_p = 'd0; + reg [ 7:0] adc_data_n = 'd0; + reg adc_or_p = 'd0; + reg adc_or_n = 'd0; + + // internal signals + + wire [ 7:0] adc_data_p_s; + wire [ 7:0] adc_data_n_s; + wire adc_or_p_s; + wire adc_or_n_s; + + genvar l_inst; + + always @(posedge adc_clk) + begin + adc_status <= 1'b1; + adc_or <= adc_or_p_s | adc_or_n_s; + adc_data <= { adc_data_p_s[7], adc_data_n_s[7], adc_data_p_s[6], adc_data_n_s[6], adc_data_p_s[5], adc_data_n_s[5], adc_data_p_s[4], adc_data_n_s[4], adc_data_p_s[3], adc_data_n_s[3], adc_data_p_s[2], adc_data_n_s[2], adc_data_p_s[1], adc_data_n_s[1], adc_data_p_s[0], adc_data_n_s[0]}; + end + + // data interface + + generate + for (l_inst = 0; l_inst <= 7; l_inst = l_inst + 1) begin : g_adc_if + ad_data_in #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_adc_data ( + .rx_clk (adc_clk), + .rx_data_in_p (adc_data_in_p[l_inst]), + .rx_data_in_n (adc_data_in_n[l_inst]), + .rx_data_p (adc_data_p_s[l_inst]), + .rx_data_n (adc_data_n_s[l_inst]), + .up_clk (up_clk), + .up_dld (up_dld[l_inst]), + .up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]), + .up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + endgenerate + + // over-range interface + + ad_data_in #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_CTRL (1), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_adc_or ( + .rx_clk (adc_clk), + .rx_data_in_p (adc_or_in_p), + .rx_data_in_n (adc_or_in_n), + .rx_data_p (adc_or_p_s), + .rx_data_n (adc_or_n_s), + .up_clk (up_clk), + .up_dld (up_dld[8]), + .up_dwdata (up_dwdata[44:40]), + .up_drdata (up_drdata[44:40]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked)); + + // clock + + ad_data_clk i_adc_clk ( + .rst (1'b0), + .locked (), + .clk_in_p (adc_clk_in_p), + .clk_in_n (adc_clk_in_n), + .clk (adc_clk)); + +endmodule diff --git a/adi_library/axi_ad9265/axi_ad9265_ip.tcl b/adi_library/axi_ad9265/axi_ad9265_ip.tcl new file mode 100644 index 00000000..a8f05be8 --- /dev/null +++ b/adi_library/axi_ad9265/axi_ad9265_ip.tcl @@ -0,0 +1,52 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_ad9265 +adi_ip_files axi_ad9265 [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "axi_ad9265_pnmon.v" \ + "axi_ad9265_if.v" \ + "axi_ad9265_channel.v" \ + "axi_ad9265.v" ] + +adi_ip_properties axi_ad9265 + +adi_init_bd_tcl +adi_ip_bd axi_ad9265 "bd/bd.tcl" + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad9265} [ipx::current_core] + +set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] + +ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface adc_clk_in_P xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface adc_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + +ipx::save_core [ipx::current_core] diff --git a/adi_library/axi_ad9265/axi_ad9265_pnmon.v b/adi_library/axi_ad9265/axi_ad9265_pnmon.v new file mode 100644 index 00000000..3b51442c --- /dev/null +++ b/adi_library/axi_ad9265/axi_ad9265_pnmon.v @@ -0,0 +1,175 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// PN monitors + +`timescale 1ns/100ps + +module axi_ad9265_pnmon ( + + // adc interface + + input adc_clk, + input [15:0] adc_data, + + // pn out of sync and error + + output adc_pn_oos, + output adc_pn_err, + input [ 3:0] adc_pnseq_sel +); + + // internal registers + + reg adc_valid_in = 'd0; + reg [31:0] adc_pn_data_in = 'd0; + reg [31:0] adc_pn_data_pn = 'd0; + + // internal signals + + wire [31:0] adc_pn_data_pn_s; + + // PN23 function + + function [31:0] pn23; + input [31:0] din; + reg [31:0] dout; + begin + dout[31] = din[22] ^ din[17]; + dout[30] = din[21] ^ din[16]; + dout[29] = din[20] ^ din[15]; + dout[28] = din[19] ^ din[14]; + dout[27] = din[18] ^ din[13]; + dout[26] = din[17] ^ din[12]; + dout[25] = din[16] ^ din[11]; + dout[24] = din[15] ^ din[10]; + dout[23] = din[14] ^ din[ 9]; + dout[22] = din[13] ^ din[ 8]; + dout[21] = din[12] ^ din[ 7]; + dout[20] = din[11] ^ din[ 6]; + dout[19] = din[10] ^ din[ 5]; + dout[18] = din[ 9] ^ din[ 4]; + dout[17] = din[ 8] ^ din[ 3]; + dout[16] = din[ 7] ^ din[ 2]; + dout[15] = din[ 6] ^ din[ 1]; + dout[14] = din[ 5] ^ din[ 0]; + dout[13] = din[ 4] ^ din[22] ^ din[17]; + dout[12] = din[ 3] ^ din[21] ^ din[16]; + dout[11] = din[ 2] ^ din[20] ^ din[15]; + dout[10] = din[ 1] ^ din[19] ^ din[14]; + dout[ 9] = din[ 0] ^ din[18] ^ din[13]; + dout[ 8] = din[22] ^ din[12]; + dout[ 7] = din[21] ^ din[11]; + dout[ 6] = din[20] ^ din[10]; + dout[ 5] = din[19] ^ din[ 9]; + dout[ 4] = din[18] ^ din[ 8]; + dout[ 3] = din[17] ^ din[ 7]; + dout[ 2] = din[16] ^ din[ 6]; + dout[ 1] = din[15] ^ din[ 5]; + dout[ 0] = din[14] ^ din[ 4]; + pn23 = dout; + end + endfunction + + // PN9 function + + function [31:0] pn9; + input [31:0] din; + reg [31:0] dout; + begin + dout[31] = din[ 8] ^ din[ 4]; + dout[30] = din[ 7] ^ din[ 3]; + dout[29] = din[ 6] ^ din[ 2]; + dout[28] = din[ 5] ^ din[ 1]; + dout[27] = din[ 4] ^ din[ 0]; + dout[26] = din[ 3] ^ din[ 8] ^ din[ 4]; + dout[25] = din[ 2] ^ din[ 7] ^ din[ 3]; + dout[24] = din[ 1] ^ din[ 6] ^ din[ 2]; + dout[23] = din[ 0] ^ din[ 5] ^ din[ 1]; + dout[22] = din[ 8] ^ din[ 0]; + dout[21] = din[ 7] ^ din[ 8] ^ din[ 4]; + dout[20] = din[ 6] ^ din[ 7] ^ din[ 3]; + dout[19] = din[ 5] ^ din[ 6] ^ din[ 2]; + dout[18] = din[ 4] ^ din[ 5] ^ din[ 1]; + dout[17] = din[ 3] ^ din[ 4] ^ din[ 0]; + dout[16] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[15] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; + dout[14] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[13] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[12] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; + dout[11] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; + dout[10] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[ 9] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[ 8] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; + dout[ 7] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0]; + dout[ 6] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4]; + dout[ 5] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3]; + dout[ 4] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[ 3] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1]; + dout[ 2] = din[ 6] ^ din[ 8] ^ din[ 0]; + dout[ 1] = din[5] ^ din[7] ^ din[8] ^ din[4]; + dout[ 0] = din[4] ^ din[6] ^ din[7] ^ din[3]; + pn9 = dout; + end + endfunction + + // pn sequence select + + assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn; + + always @(posedge adc_clk) begin + adc_valid_in <= ~adc_valid_in; + adc_pn_data_in <= {adc_pn_data_in[15:0], adc_data[15:0]}; + if(adc_valid_in == 1'b1) begin + if (adc_pnseq_sel == 4'd0) begin + adc_pn_data_pn <= pn9(adc_pn_data_pn_s); + end else begin + adc_pn_data_pn <= pn23(adc_pn_data_pn_s); + end + end + end + + // pn oos & pn err + + ad_pnmon #( + .DATA_WIDTH(32) + ) i_pnmon ( + .adc_clk (adc_clk), + .adc_valid_in (adc_valid_in), + .adc_data_in (adc_pn_data_in), + .adc_data_pn (adc_pn_data_pn), + .adc_pn_oos (adc_pn_oos), + .adc_pn_err (adc_pn_err)); + +endmodule diff --git a/adi_library/axi_ad9265/bd/bd.tcl b/adi_library/axi_ad9265/bd/bd.tcl new file mode 100644 index 00000000..dceb9498 --- /dev/null +++ b/adi_library/axi_ad9265/bd/bd.tcl @@ -0,0 +1,47 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + DEV_PACKAGE \ + SPEED_GRADE \ + FPGA_FAMILY \ + FPGA_TECHNOLOGY" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/axi_ad9265/component.xml b/adi_library/axi_ad9265/component.xml new file mode 100644 index 00000000..777a7d69 --- /dev/null +++ b/adi_library/axi_ad9265/component.xml @@ -0,0 +1,1277 @@ + + + analog.com + user + axi_ad9265 + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + adc_clk + + + + + + + CLK + + + adc_clk + + + + + + ASSOCIATED_RESET + adc_rst + + + + + delay_clk + + + + + + + CLK + + + delay_clk + + + + + + adc_clk_in_P + + + + + + + CLK + + + adc_clk_in_P + + + + + + adc_clk_in_n + + + + + + + CLK + + + adc_clk_in_n + + + + + + adc_rst + + + + + + + RST + + + adc_rst + + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_ad9265 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 3e8bc828 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_ad9265 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + d0cfa85e + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 3a2ede8f + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + + + adc_clk_in_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_clk_in_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_in_p + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_data_in_n + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_or_in_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_or_in_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + delay_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_rst + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_dovf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + ADC_DATAPATH_DISABLE + Adc Datapath Disable + 0 + + + IO_DELAY_GROUP + Io Delay Group + adc_if_delay_group + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_00ecfe9a + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + + + choice_pairs_19f99f31 + 0 + 10 + 11 + 12 + 13 + 14 + 20 + 21 + 22 + 23 + 24 + 25 + 30 + + + choice_pairs_28f798a2 + 0 + 1 + 2 + 3 + 4 + + + choice_pairs_fc01a186 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../xilinx/common/up_clock_mon_constr.xdc + xdc + + + ../xilinx/common/ad_data_clk.v + verilogSource + + + ../xilinx/common/ad_data_in.v + verilogSource + + + ../common/ad_datafmt.v + verilogSource + + + ../xilinx/common/ad_dcfilter.v + verilogSource + + + ../common/ad_pnmon.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + axi_ad9265_channel.v + verilogSource + + + axi_ad9265_if.v + verilogSource + + + axi_ad9265_pnmon.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_delay_cntrl.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad9265.v + verilogSource + CHECKSUM_e418fdd8 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../xilinx/common/ad_data_clk.v + verilogSource + + + ../xilinx/common/ad_data_in.v + verilogSource + + + ../common/ad_datafmt.v + verilogSource + + + ../xilinx/common/ad_dcfilter.v + verilogSource + + + ../common/ad_pnmon.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + axi_ad9265_channel.v + verilogSource + + + axi_ad9265_if.v + verilogSource + + + axi_ad9265_pnmon.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_delay_cntrl.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad9265.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_ad9265_v1_0.tcl + tclSource + CHECKSUM_881bcfa5 + XGUI_VERSION_2 + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + axi_ad9265_v1_0 + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + ADC_DATAPATH_DISABLE + Adc Datapath Disable + 0 + + + IO_DELAY_GROUP + Io Delay Group + adc_if_delay_group + + + Component_Name + axi_ad9265_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_ad9265_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_ad9265 + 1 + 2024-01-14T03:40:37Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_ad9265/temporary_case_dependencies.mk b/adi_library/axi_ad9265/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/axi_ad9265/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/axi_ad9265/xgui/axi_ad9265_v1_0.tcl b/adi_library/axi_ad9265/xgui/axi_ad9265_v1_0.tcl new file mode 100644 index 00000000..00b022f4 --- /dev/null +++ b/adi_library/axi_ad9265/xgui/axi_ad9265_v1_0.tcl @@ -0,0 +1,118 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ADC_DATAPATH_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "IO_DELAY_GROUP" -parent ${Page_0} + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.ADC_DATAPATH_DISABLE { PARAM_VALUE.ADC_DATAPATH_DISABLE } { + # Procedure called to update ADC_DATAPATH_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADC_DATAPATH_DISABLE { PARAM_VALUE.ADC_DATAPATH_DISABLE } { + # Procedure called to validate ADC_DATAPATH_DISABLE + return true +} + +proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to validate DEV_PACKAGE + return true +} + +proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to validate FPGA_FAMILY + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to update IO_DELAY_GROUP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to validate IO_DELAY_GROUP + return true +} + +proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to validate SPEED_GRADE + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY} +} + +proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE} +} + +proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE} +} + +proc update_MODELPARAM_VALUE.ADC_DATAPATH_DISABLE { MODELPARAM_VALUE.ADC_DATAPATH_DISABLE PARAM_VALUE.ADC_DATAPATH_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADC_DATAPATH_DISABLE}] ${MODELPARAM_VALUE.ADC_DATAPATH_DISABLE} +} + +proc update_MODELPARAM_VALUE.IO_DELAY_GROUP { MODELPARAM_VALUE.IO_DELAY_GROUP PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IO_DELAY_GROUP}] ${MODELPARAM_VALUE.IO_DELAY_GROUP} +} + diff --git a/adi_library/axi_ad9361/Makefile b/adi_library/axi_ad9361/Makefile new file mode 100644 index 00000000..8dc4a9c9 --- /dev/null +++ b/adi_library/axi_ad9361/Makefile @@ -0,0 +1,69 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_ad9361 + +GENERIC_DEPS += ../common/ad_addsub.v +GENERIC_DEPS += ../common/ad_datafmt.v +GENERIC_DEPS += ../common/ad_dds.v +GENERIC_DEPS += ../common/ad_dds_1.v +GENERIC_DEPS += ../common/ad_dds_2.v +GENERIC_DEPS += ../common/ad_dds_cordic_pipe.v +GENERIC_DEPS += ../common/ad_dds_sine.v +GENERIC_DEPS += ../common/ad_dds_sine_cordic.v +GENERIC_DEPS += ../common/ad_iqcor.v +GENERIC_DEPS += ../common/ad_pnmon.v +GENERIC_DEPS += ../common/ad_pps_receiver.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/ad_tdd_control.v +GENERIC_DEPS += ../common/up_adc_channel.v +GENERIC_DEPS += ../common/up_adc_common.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_dac_channel.v +GENERIC_DEPS += ../common/up_dac_common.v +GENERIC_DEPS += ../common/up_delay_cntrl.v +GENERIC_DEPS += ../common/up_tdd_cntrl.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_ad9361.v +GENERIC_DEPS += axi_ad9361_rx.v +GENERIC_DEPS += axi_ad9361_rx_channel.v +GENERIC_DEPS += axi_ad9361_rx_pnmon.v +GENERIC_DEPS += axi_ad9361_tdd.v +GENERIC_DEPS += axi_ad9361_tdd_if.v +GENERIC_DEPS += axi_ad9361_tx.v +GENERIC_DEPS += axi_ad9361_tx_channel.v + +XILINX_DEPS += ../common/ad_pps_receiver_constr.ttcl +XILINX_DEPS += ../xilinx/common/ad_data_clk.v +XILINX_DEPS += ../xilinx/common/ad_data_in.v +XILINX_DEPS += ../xilinx/common/ad_data_out.v +XILINX_DEPS += ../xilinx/common/ad_dcfilter.v +XILINX_DEPS += ../xilinx/common/ad_mul.v +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_ad9361_constr.xdc +XILINX_DEPS += axi_ad9361_ip.tcl +XILINX_DEPS += xilinx/axi_ad9361_cmos_if.v +XILINX_DEPS += xilinx/axi_ad9361_lvds_if.v + +INTEL_DEPS += ../intel/common/ad_dcfilter.v +INTEL_DEPS += ../intel/common/ad_mul.v +INTEL_DEPS += ../intel/common/up_clock_mon_constr.sdc +INTEL_DEPS += ../intel/common/up_rst_constr.sdc +INTEL_DEPS += ../intel/common/up_xfer_cntrl_constr.sdc +INTEL_DEPS += ../intel/common/up_xfer_status_constr.sdc +INTEL_DEPS += axi_ad9361_constr.sdc +INTEL_DEPS += axi_ad9361_hw.tcl +INTEL_DEPS += intel/axi_ad9361_cmos_if.v +INTEL_DEPS += intel/axi_ad9361_lvds_if.v +INTEL_DEPS += intel/axi_ad9361_lvds_if_10.v +INTEL_DEPS += intel/axi_ad9361_lvds_if_c5.v + +include ../scripts/library.mk diff --git a/adi_library/axi_ad9361/axi_ad9361.v b/adi_library/axi_ad9361/axi_ad9361.v new file mode 100644 index 00000000..01c7ef76 --- /dev/null +++ b/adi_library/axi_ad9361/axi_ad9361.v @@ -0,0 +1,758 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9361 #( + + // parameters + + parameter ID = 0, + parameter MODE_1R1T = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter TDD_DISABLE = 0, + parameter PPS_RECEIVER_ENABLE = 0, + parameter CMOS_OR_LVDS_N = 0, + parameter ADC_INIT_DELAY = 0, + parameter ADC_DATAPATH_DISABLE = 0, + parameter ADC_USERPORTS_DISABLE = 0, + parameter ADC_DATAFORMAT_DISABLE = 0, + parameter ADC_DCFILTER_DISABLE = 0, + parameter ADC_IQCORRECTION_DISABLE = 0, + parameter DAC_INIT_DELAY = 0, + parameter DAC_CLK_EDGE_SEL = 0, + parameter DAC_IODELAY_ENABLE = 0, + parameter DAC_DATAPATH_DISABLE = 0, + parameter DAC_DDS_DISABLE = 0, + parameter DAC_DDS_TYPE = 1, + parameter DAC_DDS_PHASE_DW = 16, + parameter DAC_DDS_CORDIC_DW = 14, + parameter DAC_DDS_CORDIC_PHASE_DW = 13, + parameter DAC_USERPORTS_DISABLE = 0, + parameter DAC_IQCORRECTION_DISABLE = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group", + parameter IODELAY_CTRL = 1, + parameter MIMO_ENABLE = 0, + parameter USE_SSI_CLK = 1, + parameter DELAY_REFCLK_FREQUENCY = 200, + parameter RX_NODPA = 0 +) ( + + // physical interface (receive-lvds) + + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + + // physical interface (receive-cmos) + + input rx_clk_in, + input rx_frame_in, + input [11:0] rx_data_in, + + // physical interface (transmit-lvds) + + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, + + // physical interface (transmit-cmos) + + output tx_clk_out, + output tx_frame_out, + output [11:0] tx_data_out, + + // ensm control + + output enable, + output txnrx, + + // transmit master/slave + + input dac_sync_in, + output dac_sync_out, + + // tdd sync + + input tdd_sync, + output tdd_sync_cntr, + + input gps_pps, + output gps_pps_irq, + + // delay clock + + input delay_clk, + + // master interface + + output l_clk, + input clk, + output rst, + + // dma interface + + output adc_enable_i0, + output adc_valid_i0, + output [15:0] adc_data_i0, + output adc_enable_q0, + output adc_valid_q0, + output [15:0] adc_data_q0, + output adc_enable_i1, + output adc_valid_i1, + output [15:0] adc_data_i1, + output adc_enable_q1, + output adc_valid_q1, + output [15:0] adc_data_q1, + input adc_dovf, + output adc_r1_mode, + + output dac_enable_i0, + output dac_valid_i0, + input [15:0] dac_data_i0, + output dac_enable_q0, + output dac_valid_q0, + input [15:0] dac_data_q0, + output dac_enable_i1, + output dac_valid_i1, + input [15:0] dac_data_i1, + output dac_enable_q1, + output dac_valid_q1, + input [15:0] dac_data_q1, + input dac_dunf, + output dac_r1_mode, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready, + + // gpio + + input up_enable, + input up_txnrx, + input [31:0] up_dac_gpio_in, + output [31:0] up_dac_gpio_out, + input [31:0] up_adc_gpio_in, + output [31:0] up_adc_gpio_out +); + + // derived parameters + + localparam ADC_USERPORTS_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_USERPORTS_DISABLE; + localparam ADC_DATAFORMAT_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_DATAFORMAT_DISABLE; + localparam ADC_DCFILTER_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_DCFILTER_DISABLE; + localparam ADC_IQCORRECTION_DISABLE_INT = (ADC_DATAPATH_DISABLE == 1) ? 1 : ADC_IQCORRECTION_DISABLE; + localparam DAC_DDS_DISABLE_INT = (DAC_DATAPATH_DISABLE == 1) ? 1 : DAC_DDS_DISABLE; + localparam DAC_USERPORTS_DISABLE_INT = (DAC_DATAPATH_DISABLE == 1) ? 1 : DAC_USERPORTS_DISABLE; + localparam DAC_DELAYCNTRL_DISABLE_INT = (DAC_IODELAY_ENABLE == 1) ? 0 : 1; + localparam DAC_IQCORRECTION_DISABLE_INT = (DAC_DATAPATH_DISABLE == 1) ? 1 : DAC_IQCORRECTION_DISABLE; + + // internal registers + + reg adc_valid_i0_int = 'd0; + reg adc_valid_q0_int = 'd0; + reg adc_valid_i1_int = 'd0; + reg adc_valid_q1_int = 'd0; + reg [15:0] adc_data_i0_int = 'd0; + reg [15:0] adc_data_q0_int = 'd0; + reg [15:0] adc_data_i1_int = 'd0; + reg [15:0] adc_data_q1_int = 'd0; + reg dac_valid_i0_int = 'd0; + reg dac_valid_q0_int = 'd0; + reg dac_valid_i1_int = 'd0; + reg dac_valid_q1_int = 'd0; + reg up_wack = 'd0; + reg up_rack = 'd0; + reg [31:0] up_rdata = 'd0; + + // internal clocks and resets + + wire up_clk; + wire up_rstn; + wire mmcm_rst; + wire delay_rst; + + // internal signals + + wire adc_ddr_edgesel_s; + wire adc_valid_s; + wire adc_valid_i0_s; + wire adc_valid_q0_s; + wire adc_valid_i1_s; + wire adc_valid_q1_s; + wire [15:0] adc_data_i0_s; + wire [15:0] adc_data_q0_s; + wire [15:0] adc_data_i1_s; + wire [15:0] adc_data_q1_s; + wire [47:0] adc_data_s; + wire adc_status_s; + wire dac_clksel_s; + wire dac_valid_s; + wire [47:0] dac_data_s; + wire dac_valid_i0_s; + wire dac_valid_q0_s; + wire dac_valid_i1_s; + wire dac_valid_q1_s; + wire dac_data_i0_s; + wire dac_data_q0_s; + wire dac_data_i1_s; + wire dac_data_q1_s; + wire dac_sync_enable; + wire [12:0] up_adc_dld_s; + wire [64:0] up_adc_dwdata_s; + wire [64:0] up_adc_drdata_s; + wire [15:0] up_dac_dld_s; + wire [79:0] up_dac_dwdata_s; + wire [79:0] up_dac_drdata_s; + wire delay_locked_s; + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire up_wack_rx_s; + wire up_wack_tx_s; + wire up_rreq_s; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_rx_s; + wire up_rack_rx_s; + wire [31:0] up_rdata_tx_s; + wire up_rack_tx_s; + wire up_wack_tdd_s; + wire up_rack_tdd_s; + wire [31:0] up_rdata_tdd_s; + wire tdd_enable_s; + wire tdd_txnrx_s; + wire tdd_mode_s; + wire tdd_tx_valid_s; + wire tdd_rx_valid_s; + wire tdd_rx_vco_en_s; + wire tdd_tx_vco_en_s; + wire tdd_rx_rf_en_s; + wire tdd_tx_rf_en_s; + wire [ 7:0] tdd_status_s; + wire up_drp_sel; + wire up_drp_wr; + wire [11:0] up_drp_addr; + wire [31:0] up_drp_wdata; + wire [31:0] up_drp_rdata; + wire up_drp_ready; + wire up_drp_locked; + + wire [31:0] up_pps_rcounter_s; + wire up_pps_status_s; + wire up_irq_mask_s; + wire adc_up_pps_irq_mask_s; + wire dac_up_pps_irq_mask_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_wack <= up_wack_rx_s | up_wack_tx_s | up_wack_tdd_s; + up_rack <= up_rack_rx_s | up_rack_tx_s | up_rack_tdd_s; + up_rdata <= up_rdata_rx_s | up_rdata_tx_s | up_rdata_tdd_s; + end + end + + // device interface + + generate + if (CMOS_OR_LVDS_N == 1) begin + + assign tx_clk_out_p = 1'd0; + assign tx_clk_out_n = 1'd1; + assign tx_frame_out_p = 1'd0; + assign tx_frame_out_n = 1'd0; + assign tx_data_out_p = 6'h00; + assign tx_data_out_n = 6'h3f; + + axi_ad9361_cmos_if #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IO_DELAY_GROUP (IO_DELAY_GROUP), + .IODELAY_CTRL (IODELAY_CTRL), + .CLK_DESKEW (MIMO_ENABLE), + .USE_SSI_CLK (USE_SSI_CLK), + .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_dev_if ( + .rx_clk_in (rx_clk_in), + .rx_frame_in (rx_frame_in), + .rx_data_in (rx_data_in), + .tx_clk_out (tx_clk_out), + .tx_frame_out (tx_frame_out), + .tx_data_out (tx_data_out), + .enable (enable), + .txnrx (txnrx), + .rst (rst), + .clk (clk), + .l_clk (l_clk), + .adc_valid (adc_valid_s), + .adc_data (adc_data_s), + .adc_status (adc_status_s), + .adc_r1_mode (adc_r1_mode), + .adc_ddr_edgesel (adc_ddr_edgesel_s), + .dac_valid (dac_valid_s), + .dac_data (dac_data_s), + .dac_clksel (dac_clksel_s), + .dac_r1_mode (dac_r1_mode), + .tdd_enable (tdd_enable_s), + .tdd_txnrx (tdd_txnrx_s), + .tdd_mode (tdd_mode_s), + .mmcm_rst (mmcm_rst), + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_enable (up_enable), + .up_txnrx (up_txnrx), + .up_adc_dld (up_adc_dld_s), + .up_adc_dwdata (up_adc_dwdata_s), + .up_adc_drdata (up_adc_drdata_s), + .up_dac_dld (up_dac_dld_s), + .up_dac_dwdata (up_dac_dwdata_s), + .up_dac_drdata (up_dac_drdata_s), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s), + .up_drp_sel (up_drp_sel), + .up_drp_wr (up_drp_wr), + .up_drp_addr (up_drp_addr), + .up_drp_wdata (up_drp_wdata), + .up_drp_rdata (up_drp_rdata), + .up_drp_ready (up_drp_ready), + .up_drp_locked(up_drp_locked)); + end + endgenerate + + generate + if (CMOS_OR_LVDS_N == 0) begin + + assign tx_clk_out = 1'd0; + assign tx_frame_out = 1'd0; + assign tx_data_out = 12'd0; + assign up_adc_drdata_s[64:35] = 30'd0; + assign up_dac_drdata_s[79:50] = 30'd0; + + axi_ad9361_lvds_if #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .DAC_IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IO_DELAY_GROUP (IO_DELAY_GROUP), + .IODELAY_CTRL (IODELAY_CTRL), + .CLK_DESKEW (MIMO_ENABLE), + .USE_SSI_CLK (USE_SSI_CLK), + .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY), + .RX_NODPA (RX_NODPA) + ) i_dev_if ( + .rx_clk_in_p (rx_clk_in_p), + .rx_clk_in_n (rx_clk_in_n), + .rx_frame_in_p (rx_frame_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_data_in_n (rx_data_in_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_clk_out_n (tx_clk_out_n), + .tx_frame_out_p (tx_frame_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_data_out_n (tx_data_out_n), + .enable (enable), + .txnrx (txnrx), + .rst (rst), + .clk (clk), + .l_clk (l_clk), + .adc_valid (adc_valid_s), + .adc_data (adc_data_s), + .adc_status (adc_status_s), + .adc_r1_mode (adc_r1_mode), + .adc_ddr_edgesel (adc_ddr_edgesel_s), + .dac_valid (dac_valid_s), + .dac_data (dac_data_s), + .dac_clksel (dac_clksel_s), + .dac_r1_mode (dac_r1_mode), + .tdd_enable (tdd_enable_s), + .tdd_txnrx (tdd_txnrx_s), + .tdd_mode (tdd_mode_s), + .mmcm_rst (mmcm_rst), + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_enable (up_enable), + .up_txnrx (up_txnrx), + .up_adc_dld (up_adc_dld_s[6:0]), + .up_adc_dwdata (up_adc_dwdata_s[34:0]), + .up_adc_drdata (up_adc_drdata_s[34:0]), + .up_dac_dld (up_dac_dld_s[9:0]), + .up_dac_dwdata (up_dac_dwdata_s[49:0]), + .up_dac_drdata (up_dac_drdata_s[49:0]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s), + .up_drp_sel (up_drp_sel), + .up_drp_wr (up_drp_wr), + .up_drp_addr (up_drp_addr), + .up_drp_wdata (up_drp_wdata), + .up_drp_rdata (up_drp_rdata), + .up_drp_ready (up_drp_ready), + .up_drp_locked(up_drp_locked)); + end + endgenerate + + assign adc_valid_i0 = adc_valid_i0_int; + assign adc_valid_q0 = adc_valid_q0_int; + assign adc_valid_i1 = adc_valid_i1_int; + assign adc_valid_q1 = adc_valid_q1_int; + + always @(posedge clk) begin + adc_valid_i0_int <= tdd_rx_valid_s & adc_valid_i0_s; + adc_valid_q0_int <= tdd_rx_valid_s & adc_valid_q0_s; + adc_valid_i1_int <= tdd_rx_valid_s & adc_valid_i1_s; + adc_valid_q1_int <= tdd_rx_valid_s & adc_valid_q1_s; + end + + assign adc_data_i0 = adc_data_i0_int; + assign adc_data_q0 = adc_data_q0_int; + assign adc_data_i1 = adc_data_i1_int; + assign adc_data_q1 = adc_data_q1_int; + + always @(posedge clk) begin + adc_data_i0_int <= adc_data_i0_s; + adc_data_q0_int <= adc_data_q0_s; + adc_data_i1_int <= adc_data_i1_s; + adc_data_q1_int <= adc_data_q1_s; + end + + assign dac_valid_i0 = dac_valid_i0_int; + assign dac_valid_q0 = dac_valid_q0_int; + assign dac_valid_i1 = dac_valid_i1_int; + assign dac_valid_q1 = dac_valid_q1_int; + + always @(posedge clk) begin + dac_valid_i0_int <= tdd_tx_valid_s & dac_valid_i0_s; + dac_valid_q0_int <= tdd_tx_valid_s & dac_valid_q0_s; + dac_valid_i1_int <= tdd_tx_valid_s & dac_valid_i1_s; + dac_valid_q1_int <= tdd_tx_valid_s & dac_valid_q1_s; + end + + // tdd + + generate + if (TDD_DISABLE == 1) begin + assign tdd_enable_s = 1'b0; + assign tdd_txnrx_s = 1'b0; + assign tdd_txnrx_s = 1'b0; + assign tdd_mode_s = 1'b0; + assign tdd_rx_vco_en_s = 1'b0; + assign tdd_tx_vco_en_s = 1'b0; + assign tdd_rx_rf_en_s = 1'b0; + assign tdd_tx_rf_en_s = 1'b0; + assign tdd_status_s = 8'd0; + assign tdd_sync_cntr = 1'b0; + assign tdd_tx_valid_s = 1'b1; + assign tdd_rx_valid_s = 1'b1; + assign up_wack_tdd_s = 1'b0; + assign up_rack_tdd_s = 1'b0; + assign up_rdata_tdd_s = 32'b0; + assign dac_sync_enable = adc_valid_s; + end + endgenerate + + generate + if (TDD_DISABLE == 0) begin + axi_ad9361_tdd_if #( + .LEVEL_OR_PULSE_N(1) + ) i_tdd_if ( + .clk (clk), + .rst (rst), + .tdd_rx_vco_en (tdd_rx_vco_en_s), + .tdd_tx_vco_en (tdd_tx_vco_en_s), + .tdd_rx_rf_en (tdd_rx_rf_en_s), + .tdd_tx_rf_en (tdd_tx_rf_en_s), + .ad9361_txnrx (tdd_txnrx_s), + .ad9361_enable (tdd_enable_s), + .ad9361_tdd_status (tdd_status_s)); + + axi_ad9361_tdd i_tdd ( + .clk (clk), + .rst (rst), + .tdd_rx_vco_en (tdd_rx_vco_en_s), + .tdd_tx_vco_en (tdd_tx_vco_en_s), + .tdd_rx_rf_en (tdd_rx_rf_en_s), + .tdd_tx_rf_en (tdd_tx_rf_en_s), + .tdd_enabled (tdd_mode_s), + .tdd_status (tdd_status_s), + .tdd_sync (tdd_sync), + .tdd_sync_cntr (tdd_sync_cntr), + .tdd_tx_valid (tdd_tx_valid_s), + .tdd_rx_valid (tdd_rx_valid_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_tdd_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_tdd_s), + .up_rack (up_rack_tdd_s)); + + assign dac_sync_enable = adc_valid_s || tdd_mode_s; + + end + endgenerate + + generate if (PPS_RECEIVER_ENABLE == 1) begin + // GPS's PPS receiver + ad_pps_receiver i_pps_receiver ( + .clk (clk), + .rst (rst), + .gps_pps (gps_pps), + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_pps_rcounter (up_pps_rcounter_s), + .up_pps_status (up_pps_status_s), + .up_irq_mask (up_irq_mask_s), + .up_irq (gps_pps_irq)); + assign up_irq_mask_s = adc_up_pps_irq_mask_s | dac_up_pps_irq_mask_s; + end + endgenerate + + generate if (PPS_RECEIVER_ENABLE == 0) begin + assign up_pps_rcounter_s = 32'b0; + assign up_pps_status_s = 1'b1; + assign gps_pps_irq = 1'b0; + end + endgenerate + + // receive + + axi_ad9361_rx #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .MODE_1R1T (MODE_1R1T), + .CMOS_OR_LVDS_N (CMOS_OR_LVDS_N), + .PPS_RECEIVER_ENABLE (PPS_RECEIVER_ENABLE), + .INIT_DELAY (ADC_INIT_DELAY), + .USERPORTS_DISABLE (ADC_USERPORTS_DISABLE_INT), + .DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE_INT), + .DCFILTER_DISABLE (ADC_DCFILTER_DISABLE_INT), + .IQCORRECTION_DISABLE (ADC_IQCORRECTION_DISABLE_INT) + ) i_rx ( + .mmcm_rst (mmcm_rst), + .adc_rst (rst), + .adc_clk (clk), + + .adc_valid (adc_valid_s), + .adc_data (adc_data_s), + .adc_status (adc_status_s), + .adc_r1_mode (adc_r1_mode), + .adc_ddr_edgesel (adc_ddr_edgesel_s), + .dac_data (dac_data_s), + .up_dld (up_adc_dld_s), + .up_dwdata (up_adc_dwdata_s), + .up_drdata (up_adc_drdata_s), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s), + .adc_enable_i0 (adc_enable_i0), + .adc_valid_i0 (adc_valid_i0_s), + .adc_data_i0 (adc_data_i0_s), + .adc_enable_q0 (adc_enable_q0), + .adc_valid_q0 (adc_valid_q0_s), + .adc_data_q0 (adc_data_q0_s), + .adc_enable_i1 (adc_enable_i1), + .adc_valid_i1 (adc_valid_i1_s), + .adc_data_i1 (adc_data_i1_s), + .adc_enable_q1 (adc_enable_q1), + .adc_valid_q1 (adc_valid_q1_s), + .adc_data_q1 (adc_data_q1_s), + .adc_dovf (adc_dovf), + .up_adc_gpio_in (up_adc_gpio_in), + .up_adc_gpio_out (up_adc_gpio_out), + .up_pps_rcounter (up_pps_rcounter_s), + .up_pps_status (up_pps_status_s), + .up_pps_irq_mask (adc_up_pps_irq_mask_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_rx_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_rx_s), + .up_rack (up_rack_rx_s), + .up_drp_sel (up_drp_sel), + .up_drp_wr (up_drp_wr), + .up_drp_addr (up_drp_addr), + .up_drp_wdata (up_drp_wdata), + .up_drp_rdata (up_drp_rdata), + .up_drp_ready (up_drp_ready), + .up_drp_locked(up_drp_locked)); + + // transmit + + axi_ad9361_tx #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .MODE_1R1T (MODE_1R1T), + .CLK_EDGE_SEL (DAC_CLK_EDGE_SEL), + .CMOS_OR_LVDS_N (CMOS_OR_LVDS_N), + .PPS_RECEIVER_ENABLE (PPS_RECEIVER_ENABLE), + .INIT_DELAY (DAC_INIT_DELAY), + .DAC_DDS_DISABLE (DAC_DDS_DISABLE_INT), + .DAC_DDS_PHASE_DW (DAC_DDS_PHASE_DW), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .USERPORTS_DISABLE (DAC_USERPORTS_DISABLE_INT), + .DELAYCNTRL_DISABLE (DAC_DELAYCNTRL_DISABLE_INT), + .IQCORRECTION_DISABLE (DAC_IQCORRECTION_DISABLE_INT) + ) i_tx ( + .dac_clk (clk), + .dac_valid (dac_valid_s), + .dac_data (dac_data_s), + .dac_clksel (dac_clksel_s), + .dac_r1_mode (dac_r1_mode), + .adc_data (adc_data_s), + .up_dld (up_dac_dld_s), + .up_dwdata (up_dac_dwdata_s), + .up_drdata (up_dac_drdata_s), + .delay_clk (delay_clk), + .delay_rst (), + .delay_locked (delay_locked_s), + .dac_sync_enable (dac_sync_enable), + .dac_sync_in (dac_sync_in), + .dac_sync_out (dac_sync_out), + .dac_enable_i0 (dac_enable_i0), + .dac_valid_i0 (dac_valid_i0_s), + .dac_data_i0 (dac_data_i0), + .dac_enable_q0 (dac_enable_q0), + .dac_valid_q0 (dac_valid_q0_s), + .dac_data_q0 (dac_data_q0), + .dac_enable_i1 (dac_enable_i1), + .dac_valid_i1 (dac_valid_i1_s), + .dac_data_i1 (dac_data_i1), + .dac_enable_q1 (dac_enable_q1), + .dac_valid_q1 (dac_valid_q1_s), + .dac_data_q1 (dac_data_q1), + .dac_dunf(dac_dunf), + .up_pps_rcounter (up_pps_rcounter_s), + .up_pps_status (up_pps_status_s), + .up_pps_irq_mask (dac_up_pps_irq_mask_s), + .up_dac_gpio_in (up_dac_gpio_in), + .up_dac_gpio_out (up_dac_gpio_out), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_tx_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_tx_s), + .up_rack (up_rack_tx_s)); + + // axi interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ad9361/axi_ad9361.xpr b/adi_library/axi_ad9361/axi_ad9361.xpr new file mode 100644 index 00000000..c400e6aa --- /dev/null +++ b/adi_library/axi_ad9361/axi_ad9361.xpr @@ -0,0 +1,696 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_ad9361/axi_ad9361_constr.sdc b/adi_library/axi_ad9361/axi_ad9361_constr.sdc new file mode 100644 index 00000000..ab4a1b5d --- /dev/null +++ b/adi_library/axi_ad9361/axi_ad9361_constr.sdc @@ -0,0 +1,11 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_false_path -from [get_registers *i_dev_if|up_enable_int*] -to [get_registers *i_dev_if|enable_up_m1*] +set_false_path -from [get_registers *i_dev_if|up_txnrx_int*] -to [get_registers *i_dev_if|txnrx_up_m1*] +set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_xfer_toggle*] -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_state_m1*] +set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_toggle*] -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_xfer_toggle_m1*] +set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_data*] -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_data_cntrl*] + diff --git a/adi_library/axi_ad9361/axi_ad9361_constr.xdc b/adi_library/axi_ad9361/axi_ad9361_constr.xdc new file mode 100644 index 00000000..86a7a75a --- /dev/null +++ b/adi_library/axi_ad9361/axi_ad9361_constr.xdc @@ -0,0 +1,14 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property ASYNC_REG TRUE \ + [get_cells -hier *enable_up_*] \ + [get_cells -hier *txnrx_up_*] \ + [get_cells -hier *tdd_sync_d*] + +set_false_path -from [get_cells -hier -filter {name =~ *up_enable_int_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *enable_up_m1_reg && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *up_txnrx_int_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *txnrx_up_m1_reg && IS_SEQUENTIAL}] +set_false_path -quiet -to [get_cells -quiet -hier -filter {name =~ *tdd_sync_d1_reg && IS_SEQUENTIAL}] + diff --git a/adi_library/axi_ad9361/axi_ad9361_delay.tcl b/adi_library/axi_ad9361/axi_ad9361_delay.tcl new file mode 100644 index 00000000..764c2f49 --- /dev/null +++ b/adi_library/axi_ad9361/axi_ad9361_delay.tcl @@ -0,0 +1,47 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# report delays +set m_file [open "axi_ad9361_delay.log" w] +set m_ios [get_ports -filter {NAME =~ rx_*_in*}] +set m_ddr_ios [get_pins -hierarchical -filter {NAME =~ *i_rx_data_iddr/C || NAME =~ *i_rx_data_iddr/D}] +set m_info [report_timing -no_header -return_string -from $m_ios -to $m_ddr_ios -max_paths 100] + +set m_sources {} +set m_string $m_info +while {[regexp {\s+Source:\s+(.*?)\s+(.*)} $m_string m1 m_value m_string] == 1} { + lappend m_sources $m_value +} +set m_destinations {} +set m_string $m_info +while {[regexp {\s+Destination:\s+(.*?)\s+(.*)} $m_string m1 m_value m_string] == 1} { + lappend m_destinations $m_value +} +set m_delays {} +set m_string $m_info +while {[regexp {\s+Data\s+Path\s+Delay:\s+(.*?)\s+(.*)} $m_string m1 m_value m_string] == 1} { + lappend m_delays $m_value +} + +set m_size [llength $m_sources] +if {[llength $m_destinations] != $m_size} { + puts "CRITICAL WARNING: axi_ad9361_delay.tcl, source-destination size mismatch" +} +if {[llength $m_delays] != $m_size} { + puts "CRITICAL WARNING: axi_ad9361_delay.tcl, source-delay size mismatch" +} + +for {set m_index 0} {$m_index < $m_size} {incr m_index} { + set m_delay [lindex $m_delays $m_index] + set m_source [lindex $m_sources $m_index] + set m_destination [lindex $m_destinations $m_index] + puts "$m_source $m_destination $m_delay" + puts $m_file "$m_source $m_destination $m_delay" +} + +puts $m_file "\nDetails:\n" +puts $m_file $m_info +close $m_file + diff --git a/adi_library/axi_ad9361/axi_ad9361_hw.tcl b/adi_library/axi_ad9361/axi_ad9361_hw.tcl new file mode 100644 index 00000000..aa0af56c --- /dev/null +++ b/adi_library/axi_ad9361/axi_ad9361_hw.tcl @@ -0,0 +1,253 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +package require quartus::device + +source ../../scripts/adi_env.tcl +source ../scripts/adi_ip_intel.tcl + +ad_ip_create axi_ad9361 {AXI AD9361 Interface} axi_ad9361_elab +set_module_property VALIDATION_CALLBACK info_param_validate + +ad_ip_files axi_ad9361 [list\ + $ad_hdl_dir/library/intel/common/ad_mul.v \ + $ad_hdl_dir/library/intel/common/ad_dcfilter.v \ + $ad_hdl_dir/library/common/ad_rst.v \ + $ad_hdl_dir/library/common/ad_pnmon.v \ + $ad_hdl_dir/library/common/ad_dds_cordic_pipe.v \ + $ad_hdl_dir/library/common/ad_dds_sine_cordic.v \ + $ad_hdl_dir/library/common/ad_dds_sine.v \ + $ad_hdl_dir/library/common/ad_dds_2.v \ + $ad_hdl_dir/library/common/ad_dds_1.v \ + $ad_hdl_dir/library/common/ad_dds.v \ + $ad_hdl_dir/library/common/ad_datafmt.v \ + $ad_hdl_dir/library/common/ad_iqcor.v \ + $ad_hdl_dir/library/common/ad_addsub.v \ + $ad_hdl_dir/library/common/ad_tdd_control.v \ + $ad_hdl_dir/library/common/ad_pps_receiver.v \ + $ad_hdl_dir/library/common/up_axi.v \ + $ad_hdl_dir/library/common/up_xfer_cntrl.v \ + $ad_hdl_dir/library/common/up_xfer_status.v \ + $ad_hdl_dir/library/common/up_clock_mon.v \ + $ad_hdl_dir/library/common/up_delay_cntrl.v \ + $ad_hdl_dir/library/common/up_adc_common.v \ + $ad_hdl_dir/library/common/up_adc_channel.v \ + $ad_hdl_dir/library/common/up_dac_common.v \ + $ad_hdl_dir/library/common/up_dac_channel.v \ + $ad_hdl_dir/library/common/up_tdd_cntrl.v \ + intel/axi_ad9361_lvds_if_10.v \ + intel/axi_ad9361_lvds_if_c5.v \ + intel/axi_ad9361_lvds_if.v \ + intel/axi_ad9361_cmos_if.v \ + axi_ad9361_rx_pnmon.v \ + axi_ad9361_rx_channel.v \ + axi_ad9361_rx.v \ + axi_ad9361_tx_channel.v \ + axi_ad9361_tx.v \ + axi_ad9361_tdd.v \ + axi_ad9361_tdd_if.v \ + axi_ad9361.v \ + $ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_rst_constr.sdc \ + axi_ad9361_constr.sdc] + +# parameters + +ad_ip_parameter ID INTEGER 0 +ad_ip_parameter MODE_1R1T INTEGER 0 +ad_ip_parameter TDD_DISABLE INTEGER 0 +ad_ip_parameter CMOS_OR_LVDS_N INTEGER 0 +ad_ip_parameter ADC_DATAPATH_DISABLE INTEGER 0 +ad_ip_parameter ADC_USERPORTS_DISABLE INTEGER 0 +ad_ip_parameter ADC_DATAFORMAT_DISABLE INTEGER 0 +ad_ip_parameter ADC_DCFILTER_DISABLE INTEGER 0 +ad_ip_parameter ADC_IQCORRECTION_DISABLE INTEGER 0 +ad_ip_parameter DAC_IODELAY_ENABLE INTEGER 0 +ad_ip_parameter DAC_DATAPATH_DISABLE INTEGER 0 +ad_ip_parameter DAC_DDS_DISABLE INTEGER 0 +ad_ip_parameter DAC_USERPORTS_DISABLE INTEGER 0 +ad_ip_parameter DAC_IQCORRECTION_DISABLE INTEGER 0 +ad_ip_parameter IO_DELAY_GROUP STRING {dev_if_delay_group} +ad_ip_parameter MIMO_ENABLE INTEGER 0 +ad_ip_parameter RX_NODPA INTEGER 0 + +adi_add_auto_fpga_spec_params + +# interfaces + +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn + +ad_interface signal dac_sync_in input 1 +ad_interface signal dac_sync_out output 1 +ad_interface signal tdd_sync input 1 +ad_interface signal tdd_sync_cntr output 1 + +ad_interface clock delay_clk input 1 +ad_interface clock l_clk output 1 +ad_interface clock clk input 1 + +ad_interface reset rst output 1 if_clk +set_interface_property if_rst associatedResetSinks s_axi_reset + +add_interface adc_ch_0 conduit end +add_interface_port adc_ch_0 adc_enable_i0 enable Output 1 +add_interface_port adc_ch_0 adc_valid_i0 valid Output 1 +add_interface_port adc_ch_0 adc_data_i0 data Output 16 + +set_interface_property adc_ch_0 associatedClock if_clk +set_interface_property adc_ch_0 associatedReset none + +add_interface adc_ch_1 conduit end +add_interface_port adc_ch_1 adc_enable_q0 enable Output 1 +add_interface_port adc_ch_1 adc_valid_q0 valid Output 1 +add_interface_port adc_ch_1 adc_data_q0 data Output 16 + +set_interface_property adc_ch_1 associatedClock if_clk +set_interface_property adc_ch_1 associatedReset none + +add_interface adc_ch_2 conduit end +add_interface_port adc_ch_2 adc_enable_i1 enable Output 1 +add_interface_port adc_ch_2 adc_valid_i1 valid Output 1 +add_interface_port adc_ch_2 adc_data_i1 data Output 16 + +set_interface_property adc_ch_2 associatedClock if_clk +set_interface_property adc_ch_2 associatedReset none + +add_interface adc_ch_3 conduit end +add_interface_port adc_ch_3 adc_enable_q1 enable Output 1 +add_interface_port adc_ch_3 adc_valid_q1 valid Output 1 +add_interface_port adc_ch_3 adc_data_q1 data Output 16 + +set_interface_property adc_ch_3 associatedClock if_clk +set_interface_property adc_ch_3 associatedReset none + +ad_interface signal adc_dovf input 1 ovf +ad_interface signal adc_r1_mode output 1 r1_mode + +add_interface dac_ch_0 conduit end +add_interface_port dac_ch_0 dac_enable_i0 enable Output 1 +add_interface_port dac_ch_0 dac_valid_i0 valid Output 1 +add_interface_port dac_ch_0 dac_data_i0 data Input 16 + +set_interface_property dac_ch_0 associatedClock if_clk +set_interface_property dac_ch_0 associatedReset none + +add_interface dac_ch_1 conduit end +add_interface_port dac_ch_1 dac_enable_q0 enable Output 1 +add_interface_port dac_ch_1 dac_valid_q0 valid Output 1 +add_interface_port dac_ch_1 dac_data_q0 data Input 16 + +set_interface_property dac_ch_1 associatedClock if_clk +set_interface_property dac_ch_1 associatedReset none + +add_interface dac_ch_2 conduit end +add_interface_port dac_ch_2 dac_enable_i1 enable Output 1 +add_interface_port dac_ch_2 dac_valid_i1 valid Output 1 +add_interface_port dac_ch_2 dac_data_i1 data Input 16 + +set_interface_property dac_ch_2 associatedClock if_clk +set_interface_property dac_ch_2 associatedReset none + +add_interface dac_ch_3 conduit end +add_interface_port dac_ch_3 dac_enable_q1 enable Output 1 +add_interface_port dac_ch_3 dac_valid_q1 valid Output 1 +add_interface_port dac_ch_3 dac_data_q1 data Input 16 + +set_interface_property dac_ch_3 associatedClock if_clk +set_interface_property dac_ch_3 associatedReset none + +ad_interface signal dac_dunf input 1 unf +ad_interface signal dac_r1_mode output 1 r1_mode + +ad_interface signal up_enable input 1 +ad_interface signal up_txnrx input 1 +ad_interface signal up_dac_gpio_in input 32 +ad_interface signal up_dac_gpio_out output 32 +ad_interface signal up_adc_gpio_in input 32 +ad_interface signal up_adc_gpio_out output 32 + +# updates + +proc axi_ad9361_elab {} { + + set m_fpga_technology [get_parameter_value "FPGA_TECHNOLOGY"] + set m_cmos_or_lvds_n [get_parameter_value "CMOS_OR_LVDS_N"] + set rx_nodpa [get_parameter_value "RX_NODPA"] + + # 103 - stands for "Arria 10" see adi_intel_device_info_enc.tcl + if {$m_fpga_technology == 103} { + + add_hdl_instance axi_ad9361_serdes_clk intel_serdes 1.0 + set_instance_parameter_value axi_ad9361_serdes_clk {DEVICE_FAMILY} {Arria 10} + set_instance_parameter_value axi_ad9361_serdes_clk {MODE} {CLK} + set_instance_parameter_value axi_ad9361_serdes_clk {DDR_OR_SDR_N} {1} + set_instance_parameter_value axi_ad9361_serdes_clk {SERDES_FACTOR} {4} + set_instance_parameter_value axi_ad9361_serdes_clk {CLKIN_FREQUENCY} {250.0} + + set rx_serdes_mode IN + if {$rx_nodpa == 1} {set rx_serdes_mode IN_NODPA} + + add_hdl_instance axi_ad9361_serdes_in intel_serdes 1.0 + set_instance_parameter_value axi_ad9361_serdes_in {DEVICE_FAMILY} {Arria 10} + set_instance_parameter_value axi_ad9361_serdes_in {MODE} $rx_serdes_mode + set_instance_parameter_value axi_ad9361_serdes_in {DDR_OR_SDR_N} {1} + set_instance_parameter_value axi_ad9361_serdes_in {SERDES_FACTOR} {4} + set_instance_parameter_value axi_ad9361_serdes_in {CLKIN_FREQUENCY} {250.0} + + add_hdl_instance axi_ad9361_serdes_out intel_serdes 1.0 + set_instance_parameter_value axi_ad9361_serdes_out {DEVICE_FAMILY} {Arria 10} + set_instance_parameter_value axi_ad9361_serdes_out {MODE} {OUT} + set_instance_parameter_value axi_ad9361_serdes_out {DDR_OR_SDR_N} {1} + set_instance_parameter_value axi_ad9361_serdes_out {SERDES_FACTOR} {4} + set_instance_parameter_value axi_ad9361_serdes_out {CLKIN_FREQUENCY} {250.0} + + add_hdl_instance axi_ad9361_data_out altera_gpio 19.1 + set_instance_parameter_value axi_ad9361_data_out {DEVICE_FAMILY} {Arria 10} + set_instance_parameter_value axi_ad9361_data_out {PIN_TYPE_GUI} {Output} + set_instance_parameter_value axi_ad9361_data_out {SIZE} {1} + set_instance_parameter_value axi_ad9361_data_out {gui_io_reg_mode} {DDIO} + + add_hdl_instance clk_buffer altclkctrl 19.1 + set_instance_parameter_value clk_buffer {DEVICE_FAMILY} {Arria 10} + + } + + add_interface device_if conduit end + set_interface_property device_if associatedClock none + set_interface_property device_if associatedReset none + + if {$m_cmos_or_lvds_n == 1} { + + add_interface_port device_if rx_clk_in rx_clk_in Input 1 + add_interface_port device_if rx_frame_in rx_frame_in Input 1 + add_interface_port device_if rx_data_in rx_data_in Input 12 + add_interface_port device_if tx_clk_out tx_clk_out Output 1 + add_interface_port device_if tx_frame_out tx_frame_out Output 1 + add_interface_port device_if tx_data_out tx_data_out Output 12 + } + + if {$m_cmos_or_lvds_n == 0} { + + add_interface_port device_if rx_clk_in_p rx_clk_in_p Input 1 + add_interface_port device_if rx_clk_in_n rx_clk_in_n Input 1 + add_interface_port device_if rx_frame_in_p rx_frame_in_p Input 1 + add_interface_port device_if rx_frame_in_n rx_frame_in_n Input 1 + add_interface_port device_if rx_data_in_p rx_data_in_p Input 6 + add_interface_port device_if rx_data_in_n rx_data_in_n Input 6 + add_interface_port device_if tx_clk_out_p tx_clk_out_p Output 1 + add_interface_port device_if tx_clk_out_n tx_clk_out_n Output 1 + add_interface_port device_if tx_frame_out_p tx_frame_out_p Output 1 + add_interface_port device_if tx_frame_out_n tx_frame_out_n Output 1 + add_interface_port device_if tx_data_out_p tx_data_out_p Output 6 + add_interface_port device_if tx_data_out_n tx_data_out_n Output 6 + } + + add_interface_port device_if enable enable Output 1 + add_interface_port device_if txnrx txnrx Output 1 +} + diff --git a/adi_library/axi_ad9361/axi_ad9361_ip.tcl b/adi_library/axi_ad9361/axi_ad9361_ip.tcl new file mode 100644 index 00000000..1278cf01 --- /dev/null +++ b/adi_library/axi_ad9361/axi_ad9361_ip.tcl @@ -0,0 +1,117 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_ad9361 +adi_ip_files axi_ad9361 [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_out.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ + "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine.v" \ + "$ad_hdl_dir/library/common/ad_dds_2.v" \ + "$ad_hdl_dir/library/common/ad_dds_1.v" \ + "$ad_hdl_dir/library/common/ad_dds.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/ad_iqcor.v" \ + "$ad_hdl_dir/library/common/ad_addsub.v" \ + "$ad_hdl_dir/library/common/ad_tdd_control.v" \ + "$ad_hdl_dir/library/common/ad_pps_receiver.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/up_dac_common.v" \ + "$ad_hdl_dir/library/common/up_dac_channel.v" \ + "$ad_hdl_dir/library/common/up_tdd_cntrl.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_pps_receiver_constr.ttcl" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "axi_ad9361_constr.xdc" \ + "xilinx/axi_ad9361_lvds_if.v" \ + "xilinx/axi_ad9361_cmos_if.v" \ + "axi_ad9361_rx_pnmon.v" \ + "axi_ad9361_rx_channel.v" \ + "axi_ad9361_rx.v" \ + "axi_ad9361_tx_channel.v" \ + "axi_ad9361_tx.v" \ + "axi_ad9361_tdd.v" \ + "axi_ad9361_tdd_if.v" \ + "axi_ad9361.v" ] + +adi_ip_properties axi_ad9361 +adi_ip_ttcl axi_ad9361 "../common/ad_pps_receiver_constr.ttcl" + +adi_init_bd_tcl +adi_ip_bd axi_ad9361 "bd/bd.tcl" + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad9361} [ipx::current_core] + +set_property driver_value 0 [ipx::get_ports *rx_clk_in* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *rx_frame_in* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *rx_data_in* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *gpio_in* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *gps_pps* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CMOS_OR_LVDS_N')) == 0} \ + [ipx::get_ports rx_clk_in_p -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_in_n -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_frame_in_p -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_frame_in_n -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_data_in_p -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_data_in_n -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_out_p -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_out_n -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_frame_out_p -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_frame_out_n -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_data_out_p -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_data_out_n -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.CMOS_OR_LVDS_N')) == 1} \ + [ipx::get_ports rx_clk_in -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_frame_in -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_data_in -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_out -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_frame_out -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_data_out -of_objects [ipx::current_core]] + +ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \ + -of_objects [ipx::current_core]] +set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ + -of_objects [ipx::get_bus_interfaces s_axi_aclk \ + -of_objects [ipx::current_core]]] + +ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface l_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +set reset_intf [ipx::infer_bus_interface rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]] +set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_intf] +set_property value "ACTIVE_HIGH" $reset_polarity + +ipx::infer_bus_interface gps_pps_irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core] + +ipgui::remove_param -component [ipx::current_core] [ipgui::get_guiparamspec -name "RX_NODPA" -component [ipx::current_core]] + +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/axi_ad9361/axi_ad9361_rx.v b/adi_library/axi_ad9361/axi_ad9361_rx.v new file mode 100644 index 00000000..0e94f63c --- /dev/null +++ b/adi_library/axi_ad9361/axi_ad9361_rx.v @@ -0,0 +1,431 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9361_rx #( + + // parameters + + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter MODE_1R1T = 0, + parameter CMOS_OR_LVDS_N = 0, + parameter PPS_RECEIVER_ENABLE = 0, + parameter INIT_DELAY = 0, + parameter USERPORTS_DISABLE = 0, + parameter DATAFORMAT_DISABLE = 0, + parameter DCFILTER_DISABLE = 0, + parameter IQCORRECTION_DISABLE = 0 +) ( + + // common + + output mmcm_rst, + + // adc interface + + output adc_rst, + input adc_clk, + input adc_valid, + input [47:0] adc_data, + input adc_status, + output adc_r1_mode, + output adc_ddr_edgesel, + input [47:0] dac_data, + + // delay interface + + output [12:0] up_dld, + output [64:0] up_dwdata, + input [64:0] up_drdata, + input delay_clk, + output delay_rst, + input delay_locked, + + // dma interface + + output adc_enable_i0, + output adc_valid_i0, + output [15:0] adc_data_i0, + output adc_enable_q0, + output adc_valid_q0, + output [15:0] adc_data_q0, + output adc_enable_i1, + output adc_valid_i1, + output [15:0] adc_data_i1, + output adc_enable_q1, + output adc_valid_q1, + output [15:0] adc_data_q1, + input adc_dovf, + + // gpio + + input [31:0] up_adc_gpio_in, + output [31:0] up_adc_gpio_out, + + // 1PPS reporting counter and interrupt + + input [31:0] up_pps_rcounter, + input up_pps_status, + output up_pps_irq_mask, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack, + + // drp interface + + output up_drp_sel, + output up_drp_wr, + output [11:0] up_drp_addr, + output [31:0] up_drp_wdata, + input [31:0] up_drp_rdata, + input up_drp_ready, + input up_drp_locked +); + + // configuration settings + + localparam CONFIG = (PPS_RECEIVER_ENABLE * 256) + + (CMOS_OR_LVDS_N * 128) + + (MODE_1R1T * 16) + + (USERPORTS_DISABLE * 8) + + (DATAFORMAT_DISABLE * 4) + + (DCFILTER_DISABLE * 2) + + (IQCORRECTION_DISABLE * 1); + + // internal registers + + reg up_status_pn_err = 'd0; + reg up_status_pn_oos = 'd0; + reg up_status_or = 'd0; + reg [31:0] up_rdata_int = 'd0; + reg up_rack_int = 'd0; + reg up_wack_int = 'd0; + + // internal signals + + wire [15:0] adc_dcfilter_data_out_0_s; + wire [15:0] adc_dcfilter_data_out_1_s; + wire [15:0] adc_dcfilter_data_out_2_s; + wire [15:0] adc_dcfilter_data_out_3_s; + wire [ 3:0] up_adc_pn_err_s; + wire [ 3:0] up_adc_pn_oos_s; + wire [ 3:0] up_adc_or_s; + wire [31:0] up_rdata_s[0:5]; + wire [ 5:0] up_rack_s; + wire [ 5:0] up_wack_s; + + // processor read interface + + assign up_wack = up_wack_int; + assign up_rack = up_rack_int; + assign up_rdata = up_rdata_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_status_pn_err <= 'd0; + up_status_pn_oos <= 'd0; + up_status_or <= 'd0; + up_rdata_int <= 'd0; + up_rack_int <= 'd0; + up_wack_int <= 'd0; + end else begin + up_status_pn_err <= | up_adc_pn_err_s; + up_status_pn_oos <= | up_adc_pn_oos_s; + up_status_or <= | up_adc_or_s; + up_rdata_int <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | + up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5]; + up_rack_int <= | up_rack_s; + up_wack_int <= | up_wack_s; + end + end + + // channel 0 (i) + + axi_ad9361_rx_channel #( + .Q_OR_I_N (0), + .CHANNEL_ID (0), + .DISABLE (0), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), + .DCFILTER_DISABLE (DCFILTER_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE) + ) i_rx_channel_0 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_valid (adc_valid), + .adc_data (adc_data[11:0]), + .adc_data_q (adc_data[23:12]), + .adc_or (1'b0), + .dac_data (dac_data[11:0]), + .adc_dcfilter_data_out (adc_dcfilter_data_out_0_s), + .adc_dcfilter_data_in (adc_dcfilter_data_out_1_s), + .adc_iqcor_valid (adc_valid_i0), + .adc_iqcor_data (adc_data_i0), + .adc_enable (adc_enable_i0), + .up_adc_pn_err (up_adc_pn_err_s[0]), + .up_adc_pn_oos (up_adc_pn_oos_s[0]), + .up_adc_or (up_adc_or_s[0]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // channel 1 (q) + + axi_ad9361_rx_channel #( + .Q_OR_I_N (1), + .CHANNEL_ID (1), + .DISABLE (0), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), + .DCFILTER_DISABLE (DCFILTER_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE) + ) i_rx_channel_1 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_valid (adc_valid), + .adc_data (adc_data[23:12]), + .adc_data_q (adc_data[11:0]), + .adc_or (1'b0), + .dac_data (dac_data[23:12]), + .adc_dcfilter_data_out (adc_dcfilter_data_out_1_s), + .adc_dcfilter_data_in (adc_dcfilter_data_out_0_s), + .adc_iqcor_valid (adc_valid_q0), + .adc_iqcor_data (adc_data_q0), + .adc_enable (adc_enable_q0), + .up_adc_pn_err (up_adc_pn_err_s[1]), + .up_adc_pn_oos (up_adc_pn_oos_s[1]), + .up_adc_or (up_adc_or_s[1]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // channel 2 (i) + + axi_ad9361_rx_channel #( + .Q_OR_I_N (0), + .CHANNEL_ID (2), + .DISABLE (MODE_1R1T), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), + .DCFILTER_DISABLE (DCFILTER_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE) + ) i_rx_channel_2 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_valid (adc_valid), + .adc_data (adc_data[35:24]), + .adc_data_q (adc_data[47:36]), + .adc_or (1'b0), + .dac_data (dac_data[35:24]), + .adc_dcfilter_data_out (adc_dcfilter_data_out_2_s), + .adc_dcfilter_data_in (adc_dcfilter_data_out_3_s), + .adc_iqcor_valid (adc_valid_i1), + .adc_iqcor_data (adc_data_i1), + .adc_enable (adc_enable_i1), + .up_adc_pn_err (up_adc_pn_err_s[2]), + .up_adc_pn_oos (up_adc_pn_oos_s[2]), + .up_adc_or (up_adc_or_s[2]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + // channel 3 (q) + + axi_ad9361_rx_channel #( + .Q_OR_I_N (1), + .CHANNEL_ID (3), + .DISABLE (MODE_1R1T), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), + .DCFILTER_DISABLE (DCFILTER_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE) + ) i_rx_channel_3 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_valid (adc_valid), + .adc_data (adc_data[47:36]), + .adc_data_q (adc_data[35:24]), + .adc_or (1'b0), + .dac_data (dac_data[47:36]), + .adc_dcfilter_data_out (adc_dcfilter_data_out_3_s), + .adc_dcfilter_data_in (adc_dcfilter_data_out_2_s), + .adc_iqcor_valid (adc_valid_q1), + .adc_iqcor_data (adc_data_q1), + .adc_enable (adc_enable_q1), + .up_adc_pn_err (up_adc_pn_err_s[3]), + .up_adc_pn_oos (up_adc_pn_oos_s[3]), + .up_adc_or (up_adc_or_s[3]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[3]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[3]), + .up_rack (up_rack_s[3])); + + // common processor control + + up_adc_common #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .CONFIG (CONFIG), + .DRP_DISABLE (1), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .GPIO_DISABLE (0), + .START_CODE_DISABLE (0) + ) i_up_adc_common ( + .mmcm_rst (mmcm_rst), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (adc_r1_mode), + .adc_ddr_edgesel (adc_ddr_edgesel), + .adc_pin_mode (), + .adc_status (adc_status), + .adc_sync_status (1'd0), + .adc_status_ovf (adc_dovf), + .adc_clk_ratio (32'd1), + .adc_start_code (), + .adc_sref_sync (), + .adc_sync (), + .adc_ext_sync_arm (), + .adc_ext_sync_disarm (), + .adc_ext_sync_manual_req (), + .adc_num_lanes (), + .adc_custom_control (), + .adc_crc_enable (), + .adc_sdr_ddr_n (), + .adc_symb_op (), + .adc_symb_8_16b (), + .up_adc_ce (), + .up_pps_rcounter (up_pps_rcounter), + .up_pps_status (up_pps_status), + .up_pps_irq_mask (up_pps_irq_mask), + .up_adc_r1_mode (), + .up_status_pn_err (up_status_pn_err), + .up_status_pn_oos (up_status_pn_oos), + .up_status_or (up_status_or), + .up_drp_sel (up_drp_sel), + .up_drp_wr (up_drp_wr), + .up_drp_addr (up_drp_addr), + .up_drp_wdata (up_drp_wdata), + .up_drp_rdata (up_drp_rdata), + .up_drp_ready (up_drp_ready), + .up_drp_locked (up_drp_locked), + .adc_config_wr (), + .adc_config_ctrl (), + .adc_config_rd ('d0), + .adc_ctrl_status ('d0), + .up_usr_chanmax_out (), + .up_usr_chanmax_in (8'd3), + .up_adc_gpio_in (up_adc_gpio_in), + .up_adc_gpio_out (up_adc_gpio_out), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[4]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[4]), + .up_rack (up_rack_s[4])); + + // adc delay control + + up_delay_cntrl #( + .INIT_DELAY (INIT_DELAY), + .DATA_WIDTH (13), + .BASE_ADDRESS (6'h02) + ) i_delay_cntrl ( + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked), + .up_dld (up_dld), + .up_dwdata (up_dwdata), + .up_drdata (up_drdata), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[5]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[5]), + .up_rack (up_rack_s[5])); + +endmodule diff --git a/adi_library/axi_ad9361/axi_ad9361_rx_channel.v b/adi_library/axi_ad9361/axi_ad9361_rx_channel.v new file mode 100644 index 00000000..4ed32492 --- /dev/null +++ b/adi_library/axi_ad9361/axi_ad9361_rx_channel.v @@ -0,0 +1,240 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9361_rx_channel #( + + // parameters + + parameter Q_OR_I_N = 0, + parameter CHANNEL_ID = 0, + parameter DISABLE = 0, + parameter USERPORTS_DISABLE = 0, + parameter DATAFORMAT_DISABLE = 0, + parameter DCFILTER_DISABLE = 0, + parameter IQCORRECTION_DISABLE = 0 +) ( + + // adc interface + + input adc_clk, + input adc_rst, + input adc_valid, + input [11:0] adc_data, + input [11:0] adc_data_q, + input adc_or, + input [11:0] dac_data, + + // channel interface + + output [15:0] adc_dcfilter_data_out, + input [15:0] adc_dcfilter_data_in, + output adc_iqcor_valid, + output [15:0] adc_iqcor_data, + output adc_enable, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // internal signals + + wire [11:0] adc_data_s; + wire adc_dfmt_valid_s; + wire [15:0] adc_dfmt_data_s; + wire adc_dcfilter_valid_s; + wire [15:0] adc_dcfilter_data_s; + wire adc_iqcor_enb_s; + wire adc_dcfilt_enb_s; + wire adc_dfmt_se_s; + wire adc_dfmt_type_s; + wire adc_dfmt_enable_s; + wire [15:0] adc_dcfilt_offset_s; + wire [15:0] adc_dcfilt_coeff_s; + wire [15:0] adc_iqcor_coeff_1_s; + wire [15:0] adc_iqcor_coeff_2_s; + wire [ 3:0] adc_pnseq_sel_s; + wire [ 3:0] adc_data_sel_s; + wire adc_pn_err_s; + wire adc_pn_oos_s; + + // data-path disable + + generate + if (DISABLE == 1) begin + assign adc_dcfilter_data_out = 16'd0; + assign adc_iqcor_valid = 1'd0; + assign adc_iqcor_data = 16'd0; + assign adc_enable = 1'd0; + assign up_adc_pn_err = 1'd0; + assign up_adc_pn_oos = 1'd0; + assign up_adc_or = 1'd0; + assign up_wack = 1'd0; + assign up_rdata = 32'd0; + assign up_rack = 1'd0; + end + endgenerate + + generate + if (DISABLE == 0) begin + + // iq correction inputs + + assign adc_data_s = (adc_data_sel_s == 4'h0) ? adc_data : dac_data; + assign adc_dcfilter_data_out = adc_dcfilter_data_s; + + axi_ad9361_rx_pnmon #( + .Q_OR_I_N (Q_OR_I_N), + .PRBS_SEL (CHANNEL_ID) + ) i_rx_pnmon ( + .adc_clk (adc_clk), + .adc_valid (adc_valid), + .adc_data_i (adc_data), + .adc_data_q (adc_data_q), + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_pn_oos (adc_pn_oos_s), + .adc_pn_err (adc_pn_err_s)); + + ad_datafmt #( + .DATA_WIDTH (12), + .DISABLE (DATAFORMAT_DISABLE) + ) i_ad_datafmt ( + .clk (adc_clk), + .valid (adc_valid), + .data (adc_data_s), + .valid_out (adc_dfmt_valid_s), + .data_out (adc_dfmt_data_s), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + + ad_dcfilter #( + .DISABLE (DCFILTER_DISABLE) + ) i_ad_dcfilter ( + .clk (adc_clk), + .valid (adc_dfmt_valid_s), + .data (adc_dfmt_data_s), + .valid_out (adc_dcfilter_valid_s), + .data_out (adc_dcfilter_data_s), + .dcfilt_enb (adc_dcfilt_enb_s), + .dcfilt_coeff (adc_dcfilt_coeff_s), + .dcfilt_offset (adc_dcfilt_offset_s)); + + ad_iqcor #( + .Q_OR_I_N (Q_OR_I_N), + .DISABLE (IQCORRECTION_DISABLE) + ) i_ad_iqcor ( + .clk (adc_clk), + .valid (adc_dcfilter_valid_s), + .data_in (adc_dcfilter_data_s), + .data_iq (adc_dcfilter_data_in), + .valid_out (adc_iqcor_valid), + .data_out (adc_iqcor_data), + .iqcor_enable (adc_iqcor_enb_s), + .iqcor_coeff_1 (adc_iqcor_coeff_1_s), + .iqcor_coeff_2 (adc_iqcor_coeff_2_s)); + + up_adc_channel #( + .CHANNEL_ID (CHANNEL_ID), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), + .DCFILTER_DISABLE (DCFILTER_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE) + ) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (adc_iqcor_enb_s), + .adc_dcfilt_enb (adc_dcfilt_enb_s), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_dcfilt_offset (adc_dcfilt_offset_s), + .adc_dcfilt_coeff (adc_dcfilt_coeff_s), + .adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s), + .adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s), + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_data_sel (adc_data_sel_s), + .adc_pn_err (adc_pn_err_s), + .adc_pn_oos (adc_pn_oos_s), + .adc_or (adc_or), + .adc_read_data ('d0), + .adc_status_header ('d0), + .adc_crc_err ('d0), + .up_adc_pn_err (up_adc_pn_err), + .up_adc_pn_oos (up_adc_pn_oos), + .up_adc_or (up_adc_or), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + + end + endgenerate +endmodule diff --git a/adi_library/axi_ad9361/axi_ad9361_rx_pnmon.v b/adi_library/axi_ad9361/axi_ad9361_rx_pnmon.v new file mode 100644 index 00000000..fb90cd85 --- /dev/null +++ b/adi_library/axi_ad9361/axi_ad9361_rx_pnmon.v @@ -0,0 +1,303 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// PN monitors + +`timescale 1ns/100ps + +module axi_ad9361_rx_pnmon #( + + parameter Q_OR_I_N = 0, + parameter PRBS_SEL = 0 +) ( + + // adc interface + + input adc_clk, + input adc_valid, + input [11:0] adc_data_i, + input [11:0] adc_data_q, + + // pn out of sync and error + + input [ 3:0] adc_pnseq_sel, + output adc_pn_oos, + output adc_pn_err +); + + localparam PRBS_P09 = 0; + localparam PRBS_P11 = 1; + localparam PRBS_P15 = 2; + localparam PRBS_P20 = 3; + + // internal registers + + reg adc_pn0_valid = 'd0; + reg [15:0] adc_pn0_data = 'd0; + reg adc_pn0_valid_in = 'd0; + reg [15:0] adc_pn0_data_in = 'd0; + reg [15:0] adc_pn0_data_pn = 'd0; + reg adc_pn1_valid_t = 'd0; + reg [11:0] adc_pn1_data_d = 'd0; + reg adc_pn1_valid_in = 'd0; + reg [23:0] adc_pn1_data_in = 'd0; + reg [23:0] adc_pn1_data_pn = 'd0; + reg adc_pn_valid_in = 'd0; + reg [23:0] adc_pn_data_in = 'd0; + reg [23:0] adc_pn_data_pn = 'd0; + + // internal signals + + wire [11:0] adc_pn0_data_i_s; + wire [11:0] adc_pn0_data_q_s; + wire [11:0] adc_pn0_data_q_rev_s; + wire [15:0] adc_pn0_data_s; + wire adc_pn0_iq_match_s; + wire [15:0] adc_pn0_data_pn_s; + wire adc_pn1_valid_s; + wire [23:0] adc_pn1_data_pn_s; + + // bit reversal function + + function [11:0] brfn; + input [11:0] din; + reg [11:0] dout; + begin + dout[11] = din[ 0]; + dout[10] = din[ 1]; + dout[ 9] = din[ 2]; + dout[ 8] = din[ 3]; + dout[ 7] = din[ 4]; + dout[ 6] = din[ 5]; + dout[ 5] = din[ 6]; + dout[ 4] = din[ 7]; + dout[ 3] = din[ 8]; + dout[ 2] = din[ 9]; + dout[ 1] = din[10]; + dout[ 0] = din[11]; + brfn = dout; + end + endfunction + + // device-specific prbs function + + function [15:0] pn0fn; + input [15:0] din; + reg [15:0] dout; + begin + dout = {din[14:0], ((^din[15:4]) ^ (^din[2:1]))}; + pn0fn = dout; + end + endfunction + + // standard prbs functions + + function [23:0] pn1fn; + input [23:0] din; + reg [23:0] dout; + begin + case (PRBS_SEL) + PRBS_P09: begin + dout[23] = din[ 8] ^ din[ 4]; + dout[22] = din[ 7] ^ din[ 3]; + dout[21] = din[ 6] ^ din[ 2]; + dout[20] = din[ 5] ^ din[ 1]; + dout[19] = din[ 4] ^ din[ 0]; + dout[18] = din[ 3] ^ din[ 8] ^ din[ 4]; + dout[17] = din[ 2] ^ din[ 7] ^ din[ 3]; + dout[16] = din[ 1] ^ din[ 6] ^ din[ 2]; + dout[15] = din[ 0] ^ din[ 5] ^ din[ 1]; + dout[14] = din[ 8] ^ din[ 0]; + dout[13] = din[ 7] ^ din[ 8] ^ din[ 4]; + dout[12] = din[ 6] ^ din[ 7] ^ din[ 3]; + dout[11] = din[ 5] ^ din[ 6] ^ din[ 2]; + dout[10] = din[ 4] ^ din[ 5] ^ din[ 1]; + dout[ 9] = din[ 3] ^ din[ 4] ^ din[ 0]; + dout[ 8] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[ 7] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; + dout[ 6] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[ 5] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[ 4] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; + dout[ 3] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; + dout[ 2] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[ 1] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[ 0] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; + end + PRBS_P11: begin + dout[23] = din[10] ^ din[ 8]; + dout[22] = din[ 9] ^ din[ 7]; + dout[21] = din[ 8] ^ din[ 6]; + dout[20] = din[ 7] ^ din[ 5]; + dout[19] = din[ 6] ^ din[ 4]; + dout[18] = din[ 5] ^ din[ 3]; + dout[17] = din[ 4] ^ din[ 2]; + dout[16] = din[ 3] ^ din[ 1]; + dout[15] = din[ 2] ^ din[ 0]; + dout[14] = din[ 1] ^ din[10] ^ din[ 8]; + dout[13] = din[ 0] ^ din[ 9] ^ din[ 7]; + dout[12] = din[10] ^ din[ 6]; + dout[11] = din[ 9] ^ din[ 5]; + dout[10] = din[ 8] ^ din[ 4]; + dout[ 9] = din[ 7] ^ din[ 3]; + dout[ 8] = din[ 6] ^ din[ 2]; + dout[ 7] = din[ 5] ^ din[ 1]; + dout[ 6] = din[ 4] ^ din[ 0]; + dout[ 5] = din[ 3] ^ din[10] ^ din[ 8]; + dout[ 4] = din[ 2] ^ din[ 9] ^ din[ 7]; + dout[ 3] = din[ 1] ^ din[ 8] ^ din[ 6]; + dout[ 2] = din[ 0] ^ din[ 7] ^ din[ 5]; + dout[ 1] = din[10] ^ din[ 6] ^ din[ 8] ^ din[ 4]; + dout[ 0] = din[ 9] ^ din[ 5] ^ din[ 7] ^ din[ 3]; + end + PRBS_P15: begin + dout[23] = din[14] ^ din[13]; + dout[22] = din[13] ^ din[12]; + dout[21] = din[12] ^ din[11]; + dout[20] = din[11] ^ din[10]; + dout[19] = din[10] ^ din[ 9]; + dout[18] = din[ 9] ^ din[ 8]; + dout[17] = din[ 8] ^ din[ 7]; + dout[16] = din[ 7] ^ din[ 6]; + dout[15] = din[ 6] ^ din[ 5]; + dout[14] = din[ 5] ^ din[ 4]; + dout[13] = din[ 4] ^ din[ 3]; + dout[12] = din[ 3] ^ din[ 2]; + dout[11] = din[ 2] ^ din[ 1]; + dout[10] = din[ 1] ^ din[ 0]; + dout[ 9] = din[ 0] ^ din[14] ^ din[13]; + dout[ 8] = din[14] ^ din[12]; + dout[ 7] = din[13] ^ din[11]; + dout[ 6] = din[12] ^ din[10]; + dout[ 5] = din[11] ^ din[ 9]; + dout[ 4] = din[10] ^ din[ 8]; + dout[ 3] = din[ 9] ^ din[ 7]; + dout[ 2] = din[ 8] ^ din[ 6]; + dout[ 1] = din[ 7] ^ din[ 5]; + dout[ 0] = din[ 6] ^ din[ 4]; + end + PRBS_P20: begin + dout[23] = din[19] ^ din[ 2]; + dout[22] = din[18] ^ din[ 1]; + dout[21] = din[17] ^ din[ 0]; + dout[20] = din[16] ^ din[19] ^ din[ 2]; + dout[19] = din[15] ^ din[18] ^ din[ 1]; + dout[18] = din[14] ^ din[17] ^ din[ 0]; + dout[17] = din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[16] = din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[15] = din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[14] = din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[13] = din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[12] = din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[11] = din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[10] = din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 9] = din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[ 8] = din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[ 7] = din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 6] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[ 5] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[ 4] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 3] = din[19] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[ 2] = din[18] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[ 1] = din[17] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 0] = din[16] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + end + endcase + pn1fn = dout; + end + endfunction + + // device specific, assuming lower nibble is lost- + + assign adc_pn0_data_i_s = (Q_OR_I_N == 1) ? adc_data_q : adc_data_i; + assign adc_pn0_data_q_s = (Q_OR_I_N == 1) ? adc_data_i : adc_data_q; + assign adc_pn0_data_q_rev_s = brfn(adc_pn0_data_q_s); + assign adc_pn0_data_s = {adc_pn0_data_i_s, adc_pn0_data_q_rev_s[3:0]}; + assign adc_pn0_iq_match_s = (adc_pn0_data_i_s[7:0] == adc_pn0_data_q_rev_s[11:4]) ? 1'b1 : 1'b0; + assign adc_pn0_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn0_data_in : adc_pn0_data_pn; + + always @(posedge adc_clk) begin + adc_pn0_valid <= adc_valid; + adc_pn0_data <= (adc_pn0_iq_match_s == 1'b0) ? 16'hdead : adc_pn0_data_s; + adc_pn0_valid_in <= adc_pn0_valid; + if (adc_pn0_valid == 1'b1) begin + adc_pn0_data_in <= adc_pn0_data; + adc_pn0_data_pn <= pn0fn(adc_pn0_data_pn_s); + end + end + + // standard, runs on 24bit + + assign adc_pn1_valid_s = adc_pn1_valid_t & adc_valid; + assign adc_pn1_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn1_data_in : adc_pn1_data_pn; + + always @(posedge adc_clk) begin + if (adc_valid == 1'b1) begin + adc_pn1_valid_t <= ~adc_pn1_valid_t; + adc_pn1_data_d <= adc_data_i; + end + adc_pn1_valid_in <= adc_pn1_valid_s; + if (adc_pn1_valid_s == 1'b1) begin + adc_pn1_data_in <= {adc_pn1_data_d, adc_data_i}; + adc_pn1_data_pn <= pn1fn(adc_pn1_data_pn_s); + end + end + + // pn mux + + always @(posedge adc_clk) begin + if (adc_pnseq_sel == 4'h9) begin + adc_pn_valid_in <= adc_pn1_valid_in; + adc_pn_data_in <= adc_pn1_data_in; + adc_pn_data_pn <= adc_pn1_data_pn; + end else begin + adc_pn_valid_in <= adc_pn0_valid_in; + adc_pn_data_in <= {adc_pn0_data_in[7:0], adc_pn0_data_in}; + adc_pn_data_pn <= {adc_pn0_data_pn[7:0], adc_pn0_data_pn}; + end + end + + // pn oos & pn err + + ad_pnmon #( + .DATA_WIDTH(24) + ) i_pnmon ( + .adc_clk (adc_clk), + .adc_valid_in (adc_pn_valid_in), + .adc_data_in (adc_pn_data_in), + .adc_data_pn (adc_pn_data_pn), + .adc_pattern_has_zero (1'b0), + .adc_pn_oos (adc_pn_oos), + .adc_pn_err (adc_pn_err)); + +endmodule diff --git a/adi_library/axi_ad9361/axi_ad9361_tdd.v b/adi_library/axi_ad9361/axi_ad9361_tdd.v new file mode 100644 index 00000000..6392bdf2 --- /dev/null +++ b/adi_library/axi_ad9361/axi_ad9361_tdd.v @@ -0,0 +1,254 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module axi_ad9361_tdd ( + + // clock + + input clk, + input rst, + + // control signals from the tdd control + + output tdd_rx_vco_en, + output tdd_tx_vco_en, + output tdd_rx_rf_en, + output tdd_tx_rf_en, + + // status signal + + output tdd_enabled, + input [ 7:0] tdd_status, + + // sync signal + + input tdd_sync, + output reg tdd_sync_cntr, + + // tx/rx data flow control + + output reg tdd_tx_valid, + output reg tdd_rx_valid, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // internal signals + + wire tdd_enable_s; + wire tdd_secondary_s; + wire [ 7:0] tdd_burst_count_s; + wire tdd_rx_only_s; + wire tdd_tx_only_s; + wire tdd_gated_rx_dmapath_s; + wire tdd_gated_tx_dmapath_s; + wire [23:0] tdd_counter_init_s; + wire [23:0] tdd_frame_length_s; + wire tdd_terminal_type_s; + wire tdd_sync_enable_s; + wire [23:0] tdd_vco_rx_on_1_s; + wire [23:0] tdd_vco_rx_off_1_s; + wire [23:0] tdd_vco_tx_on_1_s; + wire [23:0] tdd_vco_tx_off_1_s; + wire [23:0] tdd_rx_on_1_s; + wire [23:0] tdd_rx_off_1_s; + wire [23:0] tdd_rx_dp_on_1_s; + wire [23:0] tdd_rx_dp_off_1_s; + wire [23:0] tdd_tx_on_1_s; + wire [23:0] tdd_tx_off_1_s; + wire [23:0] tdd_tx_dp_on_1_s; + wire [23:0] tdd_tx_dp_off_1_s; + wire [23:0] tdd_vco_rx_on_2_s; + wire [23:0] tdd_vco_rx_off_2_s; + wire [23:0] tdd_vco_tx_on_2_s; + wire [23:0] tdd_vco_tx_off_2_s; + wire [23:0] tdd_rx_on_2_s; + wire [23:0] tdd_rx_off_2_s; + wire [23:0] tdd_rx_dp_on_2_s; + wire [23:0] tdd_rx_dp_off_2_s; + wire [23:0] tdd_tx_on_2_s; + wire [23:0] tdd_tx_off_2_s; + wire [23:0] tdd_tx_dp_on_2_s; + wire [23:0] tdd_tx_dp_off_2_s; + + wire [23:0] tdd_counter_status; + + wire tdd_rx_dp_en_s; + wire tdd_tx_dp_en_s; + + assign tdd_enabled = tdd_enable_s; + + // syncronization control signal + + always @(posedge clk) begin + if (tdd_enable_s == 1'b1) begin + tdd_sync_cntr <= ~tdd_terminal_type_s; + end else begin + tdd_sync_cntr <= 1'b0; + end + end + + // tx/rx data flow control + + always @(posedge clk) begin + if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin + tdd_tx_valid <= tdd_tx_dp_en_s; + end else begin + tdd_tx_valid <= 1'b1; + end + end + + always @(posedge clk) begin + if((tdd_enable_s == 1) && (tdd_gated_rx_dmapath_s == 1)) begin + tdd_rx_valid <= tdd_rx_dp_en_s; + end else begin + tdd_rx_valid <= 1'b1; + end + end + + // instantiations + + up_tdd_cntrl i_up_tdd_cntrl ( + .clk(clk), + .rst(rst), + .tdd_enable(tdd_enable_s), + .tdd_secondary(tdd_secondary_s), + .tdd_burst_count(tdd_burst_count_s), + .tdd_tx_only(tdd_tx_only_s), + .tdd_rx_only(tdd_rx_only_s), + .tdd_gated_rx_dmapath(tdd_gated_rx_dmapath_s), + .tdd_gated_tx_dmapath(tdd_gated_tx_dmapath_s), + .tdd_counter_init(tdd_counter_init_s), + .tdd_frame_length(tdd_frame_length_s), + .tdd_terminal_type(tdd_terminal_type_s), + .tdd_vco_rx_on_1(tdd_vco_rx_on_1_s), + .tdd_vco_rx_off_1(tdd_vco_rx_off_1_s), + .tdd_vco_tx_on_1(tdd_vco_tx_on_1_s), + .tdd_vco_tx_off_1(tdd_vco_tx_off_1_s), + .tdd_rx_on_1(tdd_rx_on_1_s), + .tdd_rx_off_1(tdd_rx_off_1_s), + .tdd_rx_dp_on_1(tdd_rx_dp_on_1_s), + .tdd_rx_dp_off_1(tdd_rx_dp_off_1_s), + .tdd_tx_on_1(tdd_tx_on_1_s), + .tdd_tx_off_1(tdd_tx_off_1_s), + .tdd_tx_dp_on_1(tdd_tx_dp_on_1_s), + .tdd_tx_dp_off_1(tdd_tx_dp_off_1_s), + .tdd_vco_rx_on_2(tdd_vco_rx_on_2_s), + .tdd_vco_rx_off_2(tdd_vco_rx_off_2_s), + .tdd_vco_tx_on_2(tdd_vco_tx_on_2_s), + .tdd_vco_tx_off_2(tdd_vco_tx_off_2_s), + .tdd_rx_on_2(tdd_rx_on_2_s), + .tdd_rx_off_2(tdd_rx_off_2_s), + .tdd_rx_dp_on_2(tdd_rx_dp_on_2_s), + .tdd_rx_dp_off_2(tdd_rx_dp_off_2_s), + .tdd_tx_on_2(tdd_tx_on_2_s), + .tdd_tx_off_2(tdd_tx_off_2_s), + .tdd_tx_dp_on_2(tdd_tx_dp_on_2_s), + .tdd_tx_dp_off_2(tdd_tx_dp_off_2_s), + .tdd_status(tdd_status), + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_wack(up_wack), + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata), + .up_rack(up_rack)); + + // the TX_DATA_PATH_DELAY and CONTROL_PATH_DELAY are specificly defined + // for the axi_ad9361 core + + ad_tdd_control #( + .TX_DATA_PATH_DELAY(), + .CONTROL_PATH_DELAY() + ) i_tdd_control( + .clk(clk), + .rst(rst), + .tdd_enable(tdd_enable_s), + .tdd_secondary(tdd_secondary_s), + .tdd_counter_init(tdd_counter_init_s), + .tdd_frame_length(tdd_frame_length_s), + .tdd_burst_count(tdd_burst_count_s), + .tdd_rx_only(tdd_rx_only_s), + .tdd_tx_only(tdd_tx_only_s), + .tdd_sync (tdd_sync), + .tdd_vco_rx_on_1(tdd_vco_rx_on_1_s), + .tdd_vco_rx_off_1(tdd_vco_rx_off_1_s), + .tdd_vco_tx_on_1(tdd_vco_tx_on_1_s), + .tdd_vco_tx_off_1(tdd_vco_tx_off_1_s), + .tdd_rx_on_1(tdd_rx_on_1_s), + .tdd_rx_off_1(tdd_rx_off_1_s), + .tdd_rx_dp_on_1(tdd_rx_dp_on_1_s), + .tdd_rx_dp_off_1(tdd_rx_dp_off_1_s), + .tdd_tx_on_1(tdd_tx_on_1_s), + .tdd_tx_off_1(tdd_tx_off_1_s), + .tdd_tx_dp_on_1(tdd_tx_dp_on_1_s), + .tdd_tx_dp_off_1(tdd_tx_dp_off_1_s), + .tdd_vco_rx_on_2(tdd_vco_rx_on_2_s), + .tdd_vco_rx_off_2(tdd_vco_rx_off_2_s), + .tdd_vco_tx_on_2(tdd_vco_tx_on_2_s), + .tdd_vco_tx_off_2(tdd_vco_tx_off_2_s), + .tdd_rx_on_2(tdd_rx_on_2_s), + .tdd_rx_off_2(tdd_rx_off_2_s), + .tdd_rx_dp_on_2(tdd_rx_dp_on_2_s), + .tdd_rx_dp_off_2(tdd_rx_dp_off_2_s), + .tdd_tx_on_2(tdd_tx_on_2_s), + .tdd_tx_off_2(tdd_tx_off_2_s), + .tdd_tx_dp_on_2(tdd_tx_dp_on_2_s), + .tdd_tx_dp_off_2(tdd_tx_dp_off_2_s), + .tdd_rx_dp_en(tdd_rx_dp_en_s), + .tdd_tx_dp_en(tdd_tx_dp_en_s), + .tdd_rx_vco_en(tdd_rx_vco_en), + .tdd_tx_vco_en(tdd_tx_vco_en), + .tdd_rx_rf_en(tdd_rx_rf_en), + .tdd_tx_rf_en(tdd_tx_rf_en), + .tdd_counter_status(tdd_counter_status)); + +endmodule diff --git a/adi_library/axi_ad9361/axi_ad9361_tdd_if.v b/adi_library/axi_ad9361/axi_ad9361_tdd_if.v new file mode 100644 index 00000000..3583ceb1 --- /dev/null +++ b/adi_library/axi_ad9361/axi_ad9361_tdd_if.v @@ -0,0 +1,104 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module axi_ad9361_tdd_if #( + parameter LEVEL_OR_PULSE_N = 0 +) ( + input clk, + input rst, + + // control signals from the tdd control + + input tdd_rx_vco_en, + input tdd_tx_vco_en, + input tdd_rx_rf_en, + input tdd_tx_rf_en, + + // device interface + + output ad9361_txnrx, + output ad9361_enable, + + // interface status + + output [ 7:0] ad9361_tdd_status +); + + localparam PULSE_MODE = 0; + localparam LEVEL_MODE = 1; + + // internal registers + + reg tdd_vco_overlap = 1'b0; + reg tdd_rf_overlap = 1'b0; + + wire ad9361_txnrx_s; + wire ad9361_enable_s; + + // just one VCO can be enabled at a time + assign ad9361_txnrx_s = tdd_tx_vco_en & ~tdd_rx_vco_en; + + generate + if (LEVEL_OR_PULSE_N == PULSE_MODE) begin + reg tdd_rx_rf_en_d = 1'b0; + reg tdd_tx_rf_en_d = 1'b0; + always @(posedge clk) begin + tdd_rx_rf_en_d <= tdd_rx_rf_en; + tdd_tx_rf_en_d <= tdd_tx_rf_en; + end + assign ad9361_enable_s = (tdd_rx_rf_en_d ^ tdd_rx_rf_en) || + (tdd_tx_rf_en_d ^ tdd_tx_rf_en); + end else + assign ad9361_enable_s = (tdd_rx_rf_en | tdd_tx_rf_en); + endgenerate + + always @(posedge clk) begin + if (rst == 1'b1) begin + tdd_vco_overlap <= 1'b0; + tdd_rf_overlap <= 1'b0; + end else begin + tdd_vco_overlap <= tdd_rx_vco_en & tdd_tx_vco_en; + tdd_rf_overlap <= tdd_rx_rf_en & tdd_tx_rf_en; + end + end + + assign ad9361_tdd_status = {6'b0, tdd_rf_overlap, tdd_vco_overlap}; + + assign ad9361_txnrx = ad9361_txnrx_s; + assign ad9361_enable = ad9361_enable_s; + +endmodule diff --git a/adi_library/axi_ad9361/axi_ad9361_tx.v b/adi_library/axi_ad9361/axi_ad9361_tx.v new file mode 100644 index 00000000..07c3008d --- /dev/null +++ b/adi_library/axi_ad9361/axi_ad9361_tx.v @@ -0,0 +1,452 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9361_tx #( + + // parameters + + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter MODE_1R1T = 0, + parameter CLK_EDGE_SEL = 0, + parameter CMOS_OR_LVDS_N = 0, + parameter PPS_RECEIVER_ENABLE = 0, + parameter INIT_DELAY = 0, + parameter DAC_DDS_DISABLE = 0, + parameter DAC_DDS_TYPE = 1, + parameter DAC_DDS_PHASE_DW = 16, + parameter DAC_DDS_CORDIC_DW = 14, + parameter DAC_DDS_CORDIC_PHASE_DW = 13, + parameter USERPORTS_DISABLE = 0, + parameter DELAYCNTRL_DISABLE = 0, + parameter IQCORRECTION_DISABLE = 0 +) ( + + // dac interface + + input dac_clk, + output dac_valid, + output [47:0] dac_data, + output dac_clksel, + output dac_r1_mode, + input [47:0] adc_data, + + // delay interface + + output [15:0] up_dld, + output [79:0] up_dwdata, + input [79:0] up_drdata, + input delay_clk, + output delay_rst, + input delay_locked, + + // master/slave + + input dac_sync_enable, + input dac_sync_in, + output dac_sync_out, + + // dma interface + + output dac_enable_i0, + output dac_valid_i0, + input [15:0] dac_data_i0, + output dac_enable_q0, + output dac_valid_q0, + input [15:0] dac_data_q0, + output dac_enable_i1, + output dac_valid_i1, + input [15:0] dac_data_i1, + output dac_enable_q1, + output dac_valid_q1, + input [15:0] dac_data_q1, + input dac_dunf, + + // gpio + + input [31:0] up_dac_gpio_in, + output [31:0] up_dac_gpio_out, + + // 1PPS reporting counter and interrupt + + input [31:0] up_pps_rcounter, + input up_pps_status, + output up_pps_irq_mask, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // configuration settings + + localparam CONFIG = (PPS_RECEIVER_ENABLE * 256) + + (CMOS_OR_LVDS_N * 128) + + (DAC_DDS_DISABLE * 64) + + (DELAYCNTRL_DISABLE * 32) + + (MODE_1R1T * 16) + + (USERPORTS_DISABLE * 8) + + (IQCORRECTION_DISABLE * 1); + + // internal registers + + reg dac_data_sync = 'd0; + reg [15:0] dac_rate_cnt = 'd0; + reg dac_valid_int = 'd0; + reg dac_valid_i0_int = 'd0; + reg dac_valid_q0_int = 'd0; + reg dac_valid_i1_int = 'd0; + reg dac_valid_q1_int = 'd0; + reg up_wack_int = 'd0; + reg up_rack_int = 'd0; + reg [31:0] up_rdata_int = 'd0; + + // internal clock and resets + + wire dac_rst; + + // internal signals + + wire dac_data_sync_s; + wire dac_dds_format_s; + wire [15:0] dac_datarate_s; + wire [47:0] dac_data_int_s; + wire [ 5:0] up_wack_s; + wire [ 5:0] up_rack_s; + wire [31:0] up_rdata_s[0:5]; + + // master/slave + + assign dac_data_sync_s = (ID == 0) ? dac_sync_out : dac_sync_in; + assign dac_sync_out = dac_sync & dac_sync_enable; + + always @(posedge dac_clk) begin + dac_data_sync <= dac_data_sync_s; + end + + // rate counters and data sync signals + + always @(posedge dac_clk) begin + if (dac_rst == 1'b1) begin + dac_rate_cnt <= 16'b0; + end else begin + if ((dac_data_sync == 1'b1) || (dac_rate_cnt == 16'd0)) begin + dac_rate_cnt <= dac_datarate_s; + end else begin + dac_rate_cnt <= dac_rate_cnt - 1'b1; + end + end + end + + // dma interface + + assign dac_valid = dac_valid_int; + assign dac_valid_i0 = dac_valid_i0_int; + assign dac_valid_q0 = dac_valid_q0_int; + assign dac_valid_i1 = dac_valid_i1_int; + assign dac_valid_q1 = dac_valid_q1_int; + + always @(posedge dac_clk) begin + dac_valid_int <= (dac_rate_cnt == 16'd0) ? 1'b1 : 1'b0; + dac_valid_i0_int <= dac_valid_int; + dac_valid_q0_int <= dac_valid_int; + dac_valid_i1_int <= dac_valid_int & ~dac_r1_mode; + dac_valid_q1_int <= dac_valid_int & ~dac_r1_mode; + end + + // processor read interface + + assign up_wack = up_wack_int; + assign up_rack = up_rack_int; + assign up_rdata = up_rdata_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack_int <= 'd0; + up_rack_int <= 'd0; + up_rdata_int <= 'd0; + end else begin + up_wack_int <= | up_wack_s; + up_rack_int <= | up_rack_s; + up_rdata_int <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | + up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5]; + end + end + + // dac channel + + axi_ad9361_tx_channel #( + .CHANNEL_ID (0), + .Q_OR_I_N (0), + .DISABLE (0), + .DAC_DDS_DISABLE (DAC_DDS_DISABLE), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_PHASE_DW (DAC_DDS_PHASE_DW), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE) + ) i_tx_channel_0 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_valid (dac_valid_int), + .dma_data (dac_data_i0), + .adc_data (adc_data[11:0]), + .dac_data (dac_data[11:0]), + .dac_data_out (dac_data_int_s[11:0]), + .dac_data_in (dac_data_int_s[23:12]), + .dac_enable (dac_enable_i0), + .dac_data_sync (dac_data_sync), + .dac_dds_format (dac_dds_format_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // dac channel + + axi_ad9361_tx_channel #( + .CHANNEL_ID (1), + .Q_OR_I_N (1), + .DISABLE (0), + .DAC_DDS_DISABLE (DAC_DDS_DISABLE), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_PHASE_DW (DAC_DDS_PHASE_DW), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE) + ) i_tx_channel_1 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_valid (dac_valid_int), + .dma_data (dac_data_q0), + .adc_data (adc_data[23:12]), + .dac_data (dac_data[23:12]), + .dac_data_out (dac_data_int_s[23:12]), + .dac_data_in (dac_data_int_s[11:0]), + .dac_enable (dac_enable_q0), + .dac_data_sync (dac_data_sync), + .dac_dds_format (dac_dds_format_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // dac channel + + axi_ad9361_tx_channel #( + .CHANNEL_ID (2), + .Q_OR_I_N (0), + .DISABLE (MODE_1R1T), + .DAC_DDS_DISABLE (DAC_DDS_DISABLE), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_PHASE_DW (DAC_DDS_PHASE_DW), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE) + ) i_tx_channel_2 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_valid (dac_valid_int), + .dma_data (dac_data_i1), + .adc_data (adc_data[35:24]), + .dac_data (dac_data[35:24]), + .dac_data_out (dac_data_int_s[35:24]), + .dac_data_in (dac_data_int_s[47:36]), + .dac_enable (dac_enable_i1), + .dac_data_sync (dac_data_sync), + .dac_dds_format (dac_dds_format_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + // dac channel + + axi_ad9361_tx_channel #( + .CHANNEL_ID (3), + .Q_OR_I_N (1), + .DISABLE (MODE_1R1T), + .DAC_DDS_DISABLE (DAC_DDS_DISABLE), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_PHASE_DW (DAC_DDS_PHASE_DW), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE) + ) i_tx_channel_3 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_valid (dac_valid_int), + .dma_data (dac_data_q1), + .adc_data (adc_data[47:36]), + .dac_data (dac_data[47:36]), + .dac_data_out (dac_data_int_s[47:36]), + .dac_data_in (dac_data_int_s[35:24]), + .dac_enable (dac_enable_q1), + .dac_data_sync (dac_data_sync), + .dac_dds_format (dac_dds_format_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[3]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[3]), + .up_rack (up_rack_s[3])); + + // dac common processor interface + + up_dac_common #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .CONFIG (CONFIG), + .CLK_EDGE_SEL (CLK_EDGE_SEL), + .DRP_DISABLE (1), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .GPIO_DISABLE (0) + ) i_up_dac_common ( + .mmcm_rst (), + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_num_lanes (), + .dac_sdr_ddr_n (), + .dac_sync (dac_sync), + .dac_frame (), + .dac_clksel (dac_clksel), + .dac_custom_wr(), + .dac_custom_rd(32'b0), + .dac_custom_control(), + .dac_status_if_busy(1'b0), + .dac_par_type (), + .dac_par_enb (), + .dac_r1_mode (dac_r1_mode), + .dac_datafmt (dac_dds_format_s), + .dac_datarate (dac_datarate_s), + .dac_status (1'b1), + .dac_sync_in_status (1'b1), + .dac_status_unf (dac_dunf), + .dac_clk_ratio (32'd1), + .up_dac_ce (), + .up_pps_rcounter (up_pps_rcounter), + .up_pps_status (up_pps_status), + .up_pps_irq_mask (up_pps_irq_mask), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .up_usr_chanmax (), + .dac_usr_chanmax (8'd3), + .up_dac_gpio_in (up_dac_gpio_in), + .up_dac_gpio_out (up_dac_gpio_out), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[4]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[4]), + .up_rack (up_rack_s[4])); + + // dac delay control + + up_delay_cntrl #( + .DISABLE (DELAYCNTRL_DISABLE), + .INIT_DELAY (INIT_DELAY), + .DATA_WIDTH(16), + .BASE_ADDRESS(6'h12) + ) i_delay_cntrl ( + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked), + .up_dld (up_dld), + .up_dwdata (up_dwdata), + .up_drdata (up_drdata), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[5]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[5]), + .up_rack (up_rack_s[5])); + +endmodule diff --git a/adi_library/axi_ad9361/axi_ad9361_tx_channel.v b/adi_library/axi_ad9361/axi_ad9361_tx_channel.v new file mode 100644 index 00000000..82ea69d7 --- /dev/null +++ b/adi_library/axi_ad9361/axi_ad9361_tx_channel.v @@ -0,0 +1,397 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9361_tx_channel #( + + // parameters + + parameter Q_OR_I_N = 0, + parameter CHANNEL_ID = 32'h0, + parameter DISABLE = 0, + parameter DAC_DDS_DISABLE = 0, + parameter DAC_DDS_TYPE = 1, + parameter DAC_DDS_PHASE_DW = 16, + parameter DAC_DDS_CORDIC_DW = 14, + parameter DAC_DDS_CORDIC_PHASE_DW = 13, + parameter USERPORTS_DISABLE = 0, + parameter IQCORRECTION_DISABLE = 0 +) ( + + // dac interface + + input dac_clk, + input dac_rst, + input dac_valid, + input [15:0] dma_data, + input [11:0] adc_data, + output [11:0] dac_data, + output [11:0] dac_data_out, + input [11:0] dac_data_in, + + // processor interface + + output dac_enable, + input dac_data_sync, + input dac_dds_format, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // parameters + + localparam PRBS_SEL = CHANNEL_ID; + localparam PRBS_P09 = 0; + localparam PRBS_P11 = 1; + localparam PRBS_P15 = 2; + localparam PRBS_P20 = 3; + + // internal registers + + reg dac_valid_sel = 'd0; + reg dac_enable_int = 'd0; + reg [11:0] dac_data_int = 'd0; + reg [11:0] dac_data_out_int = 'd0; + reg [23:0] dac_pn_seq = 'd0; + reg [11:0] dac_pn_data = 'd0; + reg [15:0] dac_pat_data = 'd0; + + // internal signals + + wire dac_iqcor_valid_s; + wire [15:0] dac_iqcor_data_s; + wire [11:0] dac_dds_data_s; + wire [15:0] dac_dds_scale_1_s; + wire [DAC_DDS_PHASE_DW-1:0] dac_dds_init_1_s; + wire [DAC_DDS_PHASE_DW-1:0] dac_dds_incr_1_s; + wire [15:0] dac_dds_scale_2_s; + wire [DAC_DDS_PHASE_DW-1:0] dac_dds_init_2_s; + wire [DAC_DDS_PHASE_DW-1:0] dac_dds_incr_2_s; + wire [15:0] dac_pat_data_1_s; + wire [15:0] dac_pat_data_2_s; + wire [ 3:0] dac_data_sel_s; + wire dac_iqcor_enb_s; + wire [15:0] dac_iqcor_coeff_1_s; + wire [15:0] dac_iqcor_coeff_2_s; + wire up_wack_s; + wire up_rack_s; + wire [31:0] up_rdata_s; + + // standard prbs functions + + function [23:0] pn1fn; + input [23:0] din; + reg [23:0] dout; + begin + case (PRBS_SEL) + PRBS_P09: begin + dout[23] = din[ 8] ^ din[ 4]; + dout[22] = din[ 7] ^ din[ 3]; + dout[21] = din[ 6] ^ din[ 2]; + dout[20] = din[ 5] ^ din[ 1]; + dout[19] = din[ 4] ^ din[ 0]; + dout[18] = din[ 3] ^ din[ 8] ^ din[ 4]; + dout[17] = din[ 2] ^ din[ 7] ^ din[ 3]; + dout[16] = din[ 1] ^ din[ 6] ^ din[ 2]; + dout[15] = din[ 0] ^ din[ 5] ^ din[ 1]; + dout[14] = din[ 8] ^ din[ 0]; + dout[13] = din[ 7] ^ din[ 8] ^ din[ 4]; + dout[12] = din[ 6] ^ din[ 7] ^ din[ 3]; + dout[11] = din[ 5] ^ din[ 6] ^ din[ 2]; + dout[10] = din[ 4] ^ din[ 5] ^ din[ 1]; + dout[ 9] = din[ 3] ^ din[ 4] ^ din[ 0]; + dout[ 8] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[ 7] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; + dout[ 6] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[ 5] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[ 4] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; + dout[ 3] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; + dout[ 2] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[ 1] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[ 0] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; + end + PRBS_P11: begin + dout[23] = din[10] ^ din[ 8]; + dout[22] = din[ 9] ^ din[ 7]; + dout[21] = din[ 8] ^ din[ 6]; + dout[20] = din[ 7] ^ din[ 5]; + dout[19] = din[ 6] ^ din[ 4]; + dout[18] = din[ 5] ^ din[ 3]; + dout[17] = din[ 4] ^ din[ 2]; + dout[16] = din[ 3] ^ din[ 1]; + dout[15] = din[ 2] ^ din[ 0]; + dout[14] = din[ 1] ^ din[10] ^ din[ 8]; + dout[13] = din[ 0] ^ din[ 9] ^ din[ 7]; + dout[12] = din[10] ^ din[ 6]; + dout[11] = din[ 9] ^ din[ 5]; + dout[10] = din[ 8] ^ din[ 4]; + dout[ 9] = din[ 7] ^ din[ 3]; + dout[ 8] = din[ 6] ^ din[ 2]; + dout[ 7] = din[ 5] ^ din[ 1]; + dout[ 6] = din[ 4] ^ din[ 0]; + dout[ 5] = din[ 3] ^ din[10] ^ din[ 8]; + dout[ 4] = din[ 2] ^ din[ 9] ^ din[ 7]; + dout[ 3] = din[ 1] ^ din[ 8] ^ din[ 6]; + dout[ 2] = din[ 0] ^ din[ 7] ^ din[ 5]; + dout[ 1] = din[10] ^ din[ 6] ^ din[ 8] ^ din[ 4]; + dout[ 0] = din[ 9] ^ din[ 5] ^ din[ 7] ^ din[ 3]; + end + PRBS_P15: begin + dout[23] = din[14] ^ din[13]; + dout[22] = din[13] ^ din[12]; + dout[21] = din[12] ^ din[11]; + dout[20] = din[11] ^ din[10]; + dout[19] = din[10] ^ din[ 9]; + dout[18] = din[ 9] ^ din[ 8]; + dout[17] = din[ 8] ^ din[ 7]; + dout[16] = din[ 7] ^ din[ 6]; + dout[15] = din[ 6] ^ din[ 5]; + dout[14] = din[ 5] ^ din[ 4]; + dout[13] = din[ 4] ^ din[ 3]; + dout[12] = din[ 3] ^ din[ 2]; + dout[11] = din[ 2] ^ din[ 1]; + dout[10] = din[ 1] ^ din[ 0]; + dout[ 9] = din[ 0] ^ din[14] ^ din[13]; + dout[ 8] = din[14] ^ din[12]; + dout[ 7] = din[13] ^ din[11]; + dout[ 6] = din[12] ^ din[10]; + dout[ 5] = din[11] ^ din[ 9]; + dout[ 4] = din[10] ^ din[ 8]; + dout[ 3] = din[ 9] ^ din[ 7]; + dout[ 2] = din[ 8] ^ din[ 6]; + dout[ 1] = din[ 7] ^ din[ 5]; + dout[ 0] = din[ 6] ^ din[ 4]; + end + PRBS_P20: begin + dout[23] = din[19] ^ din[ 2]; + dout[22] = din[18] ^ din[ 1]; + dout[21] = din[17] ^ din[ 0]; + dout[20] = din[16] ^ din[19] ^ din[ 2]; + dout[19] = din[15] ^ din[18] ^ din[ 1]; + dout[18] = din[14] ^ din[17] ^ din[ 0]; + dout[17] = din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[16] = din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[15] = din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[14] = din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[13] = din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[12] = din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[11] = din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[10] = din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 9] = din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[ 8] = din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[ 7] = din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 6] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[ 5] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[ 4] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 3] = din[19] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + dout[ 2] = din[18] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2]; + dout[ 1] = din[17] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1]; + dout[ 0] = din[16] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0]; + end + endcase + pn1fn = dout; + end + endfunction + + // global toggle + + always @(posedge dac_clk) begin + if (dac_data_sync == 1'b1) begin + dac_valid_sel <= 1'b0; + end else if (dac_valid == 1'b1) begin + dac_valid_sel <= ~dac_valid_sel; + end + end + + // dac iq correction + + assign dac_enable = (DISABLE == 1) ? 1'd0 : dac_enable_int; + assign dac_data = (DISABLE == 1) ? 12'd0 : dac_data_int; + + always @(posedge dac_clk) begin + dac_enable_int <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; + if (dac_iqcor_valid_s == 1'b1) begin + dac_data_int <= dac_iqcor_data_s[15:4]; + end + end + + ad_iqcor #( + .Q_OR_I_N (Q_OR_I_N), + .DISABLE (IQCORRECTION_DISABLE) + ) i_ad_iqcor ( + .clk (dac_clk), + .valid (dac_valid), + .data_in ({dac_data_out_int, 4'd0}), + .data_iq ({dac_data_in, 4'd0}), + .valid_out (dac_iqcor_valid_s), + .data_out (dac_iqcor_data_s), + .iqcor_enable (dac_iqcor_enb_s), + .iqcor_coeff_1 (dac_iqcor_coeff_1_s), + .iqcor_coeff_2 (dac_iqcor_coeff_2_s)); + + // dac mux + + assign dac_data_out = (DISABLE == 1) ? 12'd0 : dac_data_out_int; + + always @(posedge dac_clk) begin + case (dac_data_sel_s) + 4'h9: dac_data_out_int <= dac_pn_data; + 4'h8: dac_data_out_int <= adc_data; + 4'h3: dac_data_out_int <= 12'd0; + 4'h2: dac_data_out_int <= dma_data[15:4]; + 4'h1: dac_data_out_int <= dac_pat_data[15:4]; + default: dac_data_out_int <= dac_dds_data_s; + endcase + end + + // prbs sequences + + always @(posedge dac_clk) begin + if (dac_data_sync == 1'b1) begin + dac_pn_seq <= 24'hffffff; + dac_pn_data <= 12'd0; + end else if (dac_valid == 1'b1) begin + if (dac_valid_sel == 1'b1) begin + dac_pn_seq <= pn1fn(dac_pn_seq); + dac_pn_data <= dac_pn_seq[11: 0]; + end else begin + dac_pn_seq <= dac_pn_seq; + dac_pn_data <= dac_pn_seq[23:12]; + end + end + end + + // pattern + + always @(posedge dac_clk) begin + if (dac_valid == 1'b1) begin + if (dac_valid_sel == 1'b0) begin + dac_pat_data <= dac_pat_data_1_s; + end else begin + dac_pat_data <= dac_pat_data_2_s; + end + end + end + + // dds + + ad_dds #( + .DISABLE (DAC_DDS_DISABLE), + .DDS_DW (12), + .PHASE_DW (DAC_DDS_PHASE_DW), + .DDS_TYPE (DAC_DDS_TYPE), + .CORDIC_DW (DAC_DDS_CORDIC_DW), + .CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .CLK_RATIO (1) + ) i_dds ( + .clk (dac_clk), + .dac_dds_format (dac_dds_format), + .dac_data_sync (dac_data_sync), + .dac_valid (dac_valid), + .tone_1_scale (dac_dds_scale_1_s), + .tone_2_scale (dac_dds_scale_2_s), + .tone_1_init_offset (dac_dds_init_1_s), + .tone_2_init_offset (dac_dds_init_2_s), + .tone_1_freq_word (dac_dds_incr_1_s), + .tone_2_freq_word (dac_dds_incr_2_s), + .dac_dds_data (dac_dds_data_s)); + + // single channel processor + + assign up_wack = (DISABLE == 1) ? 1'd0 : up_wack_s; + assign up_rack = (DISABLE == 1) ? 1'd0 : up_rack_s; + assign up_rdata = (DISABLE == 1) ? 32'd0 : up_rdata_s; + + up_dac_channel #( + .COMMON_ID (6'h11), + .CHANNEL_ID (CHANNEL_ID), + .DDS_DISABLE (DAC_DDS_DISABLE), + .DDS_PHASE_DW (DAC_DDS_PHASE_DW), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE) + ) i_up_dac_channel ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_dds_scale_1 (dac_dds_scale_1_s), + .dac_dds_init_1 (dac_dds_init_1_s), + .dac_dds_incr_1 (dac_dds_incr_1_s), + .dac_dds_scale_2 (dac_dds_scale_2_s), + .dac_dds_init_2 (dac_dds_init_2_s), + .dac_dds_incr_2 (dac_dds_incr_2_s), + .dac_pat_data_1 (dac_pat_data_1_s), + .dac_pat_data_2 (dac_pat_data_2_s), + .dac_data_sel (dac_data_sel_s), + .dac_iq_mode (), + .dac_iqcor_enb (dac_iqcor_enb_s), + .dac_iqcor_coeff_1 (dac_iqcor_coeff_1_s), + .dac_iqcor_coeff_2 (dac_iqcor_coeff_2_s), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_interpolation_m (), + .up_usr_interpolation_n (), + .dac_usr_datatype_be (1'b0), + .dac_usr_datatype_signed (1'b1), + .dac_usr_datatype_shift (8'd0), + .dac_usr_datatype_total_bits (8'd16), + .dac_usr_datatype_bits (8'd16), + .dac_usr_interpolation_m (16'd1), + .dac_usr_interpolation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + +endmodule diff --git a/adi_library/axi_ad9361/bd/bd.tcl b/adi_library/axi_ad9361/bd/bd.tcl new file mode 100644 index 00000000..dceb9498 --- /dev/null +++ b/adi_library/axi_ad9361/bd/bd.tcl @@ -0,0 +1,47 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + DEV_PACKAGE \ + SPEED_GRADE \ + FPGA_FAMILY \ + FPGA_TECHNOLOGY" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/axi_ad9361/component.xml b/adi_library/axi_ad9361/component.xml new file mode 100644 index 00000000..08644253 --- /dev/null +++ b/adi_library/axi_ad9361/component.xml @@ -0,0 +1,2601 @@ + + + analog.com + user + axi_ad9361 + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + clk + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_RESET + rst + + + + + l_clk + + + + + + + CLK + + + l_clk + + + + + + delay_clk + + + + + + + CLK + + + delay_clk + + + + + + rst + + + + + + + RST + + + rst + + + + + + POLARITY + ACTIVE_HIGH + + + + + gps_pps_irq + + + + + + + INTERRUPT + + + gps_pps_irq + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_ad9361 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 2de5525c + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_ad9361 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 93e7a57e + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + aba2bc91 + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + + + rx_clk_in_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + rx_clk_in_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + rx_frame_in_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + rx_frame_in_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + rx_data_in_p + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + rx_data_in_n + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + rx_clk_in + + in + + + std_logic + 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+ + DAC_INIT_DELAY + Dac Init Delay + 0 + + + DAC_CLK_EDGE_SEL + Dac Clk Edge Sel + 0 + + + DAC_IODELAY_ENABLE + Dac Iodelay Enable + 0 + + + DAC_DATAPATH_DISABLE + Dac Datapath Disable + 0 + + + DAC_DDS_DISABLE + Dac Dds Disable + 0 + + + DAC_DDS_TYPE + Dac Dds Type + 1 + + + DAC_DDS_PHASE_DW + Dac Dds Phase Dw + 16 + + + DAC_DDS_CORDIC_DW + Dac Dds Cordic Dw + 14 + + + DAC_DDS_CORDIC_PHASE_DW + Dac Dds Cordic Phase Dw + 13 + + + DAC_USERPORTS_DISABLE + Dac Userports Disable + 0 + + + DAC_IQCORRECTION_DISABLE + Dac Iqcorrection Disable + 0 + + + IO_DELAY_GROUP + Io Delay Group + dev_if_delay_group + + + IODELAY_CTRL + Iodelay Ctrl + 1 + + + MIMO_ENABLE + Mimo Enable + 0 + + + USE_SSI_CLK + Use Ssi Clk + 1 + + + DELAY_REFCLK_FREQUENCY + Delay Refclk Frequency + 200 + + + RX_NODPA + Rx Nodpa + 0 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_list_9ca20931 + LEVEL_HIGH + LEVEL_LOW + EDGE_RISING + EDGE_FALLING + + + choice_pairs_00ecfe9a + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + + + choice_pairs_19f99f31 + 0 + 10 + 11 + 12 + 13 + 14 + 20 + 21 + 22 + 23 + 24 + 25 + 30 + + + choice_pairs_28f798a2 + 0 + 1 + 2 + 3 + 4 + + + choice_pairs_fc01a186 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../common/ad_pps_receiver_constr.ttcl + ttcl + + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../xilinx/common/up_clock_mon_constr.xdc + xdc + + + axi_ad9361_constr.xdc + xdc + + + ../common/ad_addsub.v + verilogSource + + + ../xilinx/common/ad_data_clk.v + verilogSource + + + ../xilinx/common/ad_data_in.v + verilogSource + + + ../xilinx/common/ad_data_out.v + verilogSource + + + ../common/ad_datafmt.v + verilogSource + + + ../xilinx/common/ad_dcfilter.v + verilogSource + + + ../common/ad_dds.v + verilogSource + + + ../common/ad_dds_1.v + verilogSource + + + ../common/ad_dds_2.v + verilogSource + + + ../common/ad_dds_cordic_pipe.v + verilogSource + + + ../common/ad_dds_sine.v + verilogSource + + + ../common/ad_dds_sine_cordic.v + verilogSource + + + ../common/ad_iqcor.v + verilogSource + + + ../xilinx/common/ad_mul.v + verilogSource + + + ../common/ad_pnmon.v + verilogSource + + + ../common/ad_pps_receiver.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../common/ad_tdd_control.v + verilogSource + + + xilinx/axi_ad9361_cmos_if.v + verilogSource + + + xilinx/axi_ad9361_lvds_if.v + verilogSource + + + axi_ad9361_rx.v + verilogSource + + + axi_ad9361_rx_channel.v + verilogSource + + + axi_ad9361_rx_pnmon.v + verilogSource + + + axi_ad9361_tdd.v + verilogSource + + + axi_ad9361_tdd_if.v + verilogSource + + + axi_ad9361_tx.v + verilogSource + + + axi_ad9361_tx_channel.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_dac_channel.v + verilogSource + + + ../common/up_dac_common.v + verilogSource + + + ../common/up_delay_cntrl.v + verilogSource + + + ../common/up_tdd_cntrl.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad9361.v + verilogSource + CHECKSUM_c067097f + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_addsub.v + verilogSource + + + ../xilinx/common/ad_data_clk.v + verilogSource + + + ../xilinx/common/ad_data_in.v + verilogSource + + + ../xilinx/common/ad_data_out.v + verilogSource + + + ../common/ad_datafmt.v + verilogSource + + + ../xilinx/common/ad_dcfilter.v + verilogSource + + + ../common/ad_dds.v + verilogSource + + + ../common/ad_dds_1.v + verilogSource + + + ../common/ad_dds_2.v + verilogSource + + + ../common/ad_dds_cordic_pipe.v + verilogSource + + + ../common/ad_dds_sine.v + verilogSource + + + ../common/ad_dds_sine_cordic.v + verilogSource + + + ../common/ad_iqcor.v + verilogSource + + + ../xilinx/common/ad_mul.v + verilogSource + + + ../common/ad_pnmon.v + verilogSource + + + ../common/ad_pps_receiver.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../common/ad_tdd_control.v + verilogSource + + + xilinx/axi_ad9361_cmos_if.v + verilogSource + + + xilinx/axi_ad9361_lvds_if.v + verilogSource + + + axi_ad9361_rx.v + verilogSource + + + axi_ad9361_rx_channel.v + verilogSource + + + axi_ad9361_rx_pnmon.v + verilogSource + + + axi_ad9361_tdd.v + verilogSource + + + axi_ad9361_tdd_if.v + verilogSource + + + axi_ad9361_tx.v + verilogSource + + + axi_ad9361_tx_channel.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_dac_channel.v + verilogSource + + + ../common/up_dac_common.v + verilogSource + + + ../common/up_delay_cntrl.v + verilogSource + + + ../common/up_tdd_cntrl.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad9361.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_ad9361_v1_0.tcl + tclSource + CHECKSUM_4ea9eb31 + XGUI_VERSION_2 + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + axi_ad9361_v1_0 + + + ID + Id + 0 + + + MODE_1R1T + Mode 1r1t + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + TDD_DISABLE + Tdd Disable + 0 + + + PPS_RECEIVER_ENABLE + Pps Receiver Enable + 0 + + + CMOS_OR_LVDS_N + Cmos Or Lvds N + 0 + + + ADC_INIT_DELAY + Adc Init Delay + 0 + + + ADC_DATAPATH_DISABLE + Adc Datapath Disable + 0 + + + ADC_USERPORTS_DISABLE + Adc Userports Disable + 0 + + + ADC_DATAFORMAT_DISABLE + Adc Dataformat Disable + 0 + + + ADC_DCFILTER_DISABLE + Adc Dcfilter Disable + 0 + + + ADC_IQCORRECTION_DISABLE + Adc Iqcorrection Disable + 0 + + + DAC_INIT_DELAY + Dac Init Delay + 0 + + + DAC_CLK_EDGE_SEL + Dac Clk Edge Sel + 0 + + + DAC_IODELAY_ENABLE + Dac Iodelay Enable + 0 + + + DAC_DATAPATH_DISABLE + Dac Datapath Disable + 0 + + + DAC_DDS_DISABLE + Dac Dds Disable + 0 + + + DAC_DDS_TYPE + Dac Dds Type + 1 + + + DAC_DDS_PHASE_DW + Dac Dds Phase Dw + 16 + + + DAC_DDS_CORDIC_DW + Dac Dds Cordic Dw + 14 + + + DAC_DDS_CORDIC_PHASE_DW + Dac Dds Cordic Phase Dw + 13 + + + DAC_USERPORTS_DISABLE + Dac Userports Disable + 0 + + + DAC_IQCORRECTION_DISABLE + Dac Iqcorrection Disable + 0 + + + IO_DELAY_GROUP + Io Delay Group + dev_if_delay_group + + + IODELAY_CTRL + Iodelay Ctrl + 1 + + + MIMO_ENABLE + Mimo Enable + 0 + + + USE_SSI_CLK + Use Ssi Clk + 1 + + + DELAY_REFCLK_FREQUENCY + Delay Refclk Frequency + 200 + + + RX_NODPA + Rx Nodpa + 0 + + + Component_Name + axi_ad9361_v1_0 + + + + + + virtex7 + + + /Analog_Devices + + axi_ad9361_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_ad9361 + 1 + 2024-01-14T03:41:10Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_ad9361/intel/axi_ad9361_alt_lvds_rx.v b/adi_library/axi_ad9361/intel/axi_ad9361_alt_lvds_rx.v new file mode 100644 index 00000000..a73f6a74 --- /dev/null +++ b/adi_library/axi_ad9361/intel/axi_ad9361_alt_lvds_rx.v @@ -0,0 +1,179 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9361_alt_lvds_rx ( + + // physical interface (receive) + + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + + // data interface + + output clk, + output [ 3:0] rx_frame, + output [ 5:0] rx_data_0, + output [ 5:0] rx_data_1, + output [ 5:0] rx_data_2, + output [ 5:0] rx_data_3, + output rx_locked +); + + // internal signals + + wire [27:0] rx_data_s; + + // instantiations + + assign rx_frame[3] = rx_data_s[24]; + assign rx_frame[2] = rx_data_s[25]; + assign rx_frame[1] = rx_data_s[26]; + assign rx_frame[0] = rx_data_s[27]; + assign rx_data_3[5] = rx_data_s[20]; + assign rx_data_3[4] = rx_data_s[16]; + assign rx_data_3[3] = rx_data_s[12]; + assign rx_data_3[2] = rx_data_s[ 8]; + assign rx_data_3[1] = rx_data_s[ 4]; + assign rx_data_3[0] = rx_data_s[ 0]; + assign rx_data_2[5] = rx_data_s[21]; + assign rx_data_2[4] = rx_data_s[17]; + assign rx_data_2[3] = rx_data_s[13]; + assign rx_data_2[2] = rx_data_s[ 9]; + assign rx_data_2[1] = rx_data_s[ 5]; + assign rx_data_2[0] = rx_data_s[ 1]; + assign rx_data_1[5] = rx_data_s[22]; + assign rx_data_1[4] = rx_data_s[18]; + assign rx_data_1[3] = rx_data_s[14]; + assign rx_data_1[2] = rx_data_s[10]; + assign rx_data_1[1] = rx_data_s[ 6]; + assign rx_data_1[0] = rx_data_s[ 2]; + assign rx_data_0[5] = rx_data_s[23]; + assign rx_data_0[4] = rx_data_s[19]; + assign rx_data_0[3] = rx_data_s[15]; + assign rx_data_0[2] = rx_data_s[11]; + assign rx_data_0[1] = rx_data_s[ 7]; + assign rx_data_0[0] = rx_data_s[ 3]; + + altlvds_rx #( + .buffer_implementation ("RAM"), + .cds_mode ("UNUSED"), + .common_rx_tx_pll ("ON"), + .data_align_rollover (4), + .data_rate ("500.0 Mbps"), + .deserialization_factor (4), + .dpa_initial_phase_value (0), + .dpll_lock_count (0), + .dpll_lock_window (0), + .enable_clock_pin_mode ("UNUSED"), + .enable_dpa_align_to_rising_edge_only ("OFF"), + .enable_dpa_calibration ("ON"), + .enable_dpa_fifo ("UNUSED"), + .enable_dpa_initial_phase_selection ("OFF"), + .enable_dpa_mode ("OFF"), + .enable_dpa_pll_calibration ("OFF"), + .enable_soft_cdr_mode ("OFF"), + .implement_in_les ("OFF"), + .inclock_boost (0), + .inclock_data_alignment ("EDGE_ALIGNED"), + .inclock_period (4000), + .inclock_phase_shift (0), + .input_data_rate (500), + .intended_device_family ("Cyclone V"), + .lose_lock_on_one_change ("UNUSED"), + .lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_alt_lvds_rx"), + .lpm_type ("altlvds_rx"), + .number_of_channels (7), + .outclock_resource ("Regional clock"), + .pll_operation_mode ("NORMAL"), + .pll_self_reset_on_loss_lock ("UNUSED"), + .port_rx_channel_data_align ("PORT_UNUSED"), + .port_rx_data_align ("PORT_UNUSED"), + .refclk_frequency ("250.000000 MHz"), + .registered_data_align_input ("UNUSED"), + .registered_output ("ON"), + .reset_fifo_at_first_lock ("UNUSED"), + .rx_align_data_reg ("RISING_EDGE"), + .sim_dpa_is_negative_ppm_drift ("OFF"), + .sim_dpa_net_ppm_variation (0), + .sim_dpa_output_clock_phase_shift (0), + .use_coreclock_input ("OFF"), + .use_dpll_rawperror ("OFF"), + .use_external_pll ("OFF"), + .use_no_phase_shift ("ON"), + .x_on_bitslip ("ON"), + .clk_src_is_pll ("off") + ) i_altlvds_rx ( + .rx_inclock (rx_clk_in_p), + .rx_in ({rx_frame_in_p, rx_data_in_p}), + .rx_outclock (clk), + .rx_out (rx_data_s), + .rx_locked (rx_locked), + .dpa_pll_cal_busy (), + .dpa_pll_recal (1'b0), + .pll_areset (1'b0), + .pll_phasecounterselect (), + .pll_phasedone (1'b1), + .pll_phasestep (), + .pll_phaseupdown (), + .pll_scanclk (), + .rx_cda_max (), + .rx_cda_reset ({7{1'b0}}), + .rx_channel_data_align ({7{1'b0}}), + .rx_coreclk ({7{1'b1}}), + .rx_data_align (1'b0), + .rx_data_align_reset (1'b0), + .rx_data_reset (1'b0), + .rx_deskew (1'b0), + .rx_divfwdclk (), + .rx_dpa_lock_reset ({7{1'b0}}), + .rx_dpa_locked (), + .rx_dpaclock (1'b0), + .rx_dpll_enable ({7{1'b1}}), + .rx_dpll_hold ({7{1'b0}}), + .rx_dpll_reset ({7{1'b0}}), + .rx_enable (1'b1), + .rx_fifo_reset ({7{1'b0}}), + .rx_pll_enable (1'b1), + .rx_readclock (1'b0), + .rx_reset ({7{1'b0}}), + .rx_syncclock (1'b0)); + +endmodule diff --git a/adi_library/axi_ad9361/intel/axi_ad9361_alt_lvds_tx.v b/adi_library/axi_ad9361/intel/axi_ad9361_alt_lvds_tx.v new file mode 100644 index 00000000..eebb11fb --- /dev/null +++ b/adi_library/axi_ad9361/intel/axi_ad9361_alt_lvds_tx.v @@ -0,0 +1,162 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9361_alt_lvds_tx ( + + // physical interface (transmit) + + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, + + // data interface + + input tx_clk, + input clk, + input [ 3:0] tx_frame, + input [ 5:0] tx_data_0, + input [ 5:0] tx_data_1, + input [ 5:0] tx_data_2, + input [ 5:0] tx_data_3, + output tx_locked +); + + // internal registers + + reg [27:0] tx_data_n = 'd0; + reg [27:0] tx_data_p = 'd0; + + // internal signals + + wire core_clk; + wire [27:0] tx_data_s; + + // instantiations + + assign tx_clk_out_n = 1'd0; + assign tx_frame_out_n = 1'd0; + assign tx_data_out_n = 6'd0; + + assign tx_data_s[24] = tx_frame[3]; + assign tx_data_s[25] = tx_frame[2]; + assign tx_data_s[26] = tx_frame[1]; + assign tx_data_s[27] = tx_frame[0]; + assign tx_data_s[20] = tx_data_3[5]; + assign tx_data_s[16] = tx_data_3[4]; + assign tx_data_s[12] = tx_data_3[3]; + assign tx_data_s[ 8] = tx_data_3[2]; + assign tx_data_s[ 4] = tx_data_3[1]; + assign tx_data_s[ 0] = tx_data_3[0]; + assign tx_data_s[21] = tx_data_2[5]; + assign tx_data_s[17] = tx_data_2[4]; + assign tx_data_s[13] = tx_data_2[3]; + assign tx_data_s[ 9] = tx_data_2[2]; + assign tx_data_s[ 5] = tx_data_2[1]; + assign tx_data_s[ 1] = tx_data_2[0]; + assign tx_data_s[22] = tx_data_1[5]; + assign tx_data_s[18] = tx_data_1[4]; + assign tx_data_s[14] = tx_data_1[3]; + assign tx_data_s[10] = tx_data_1[2]; + assign tx_data_s[ 6] = tx_data_1[1]; + assign tx_data_s[ 2] = tx_data_1[0]; + assign tx_data_s[23] = tx_data_0[5]; + assign tx_data_s[19] = tx_data_0[4]; + assign tx_data_s[15] = tx_data_0[3]; + assign tx_data_s[11] = tx_data_0[2]; + assign tx_data_s[ 7] = tx_data_0[1]; + assign tx_data_s[ 3] = tx_data_0[0]; + + always @(negedge clk) begin + tx_data_n <= tx_data_s; + end + + always @(posedge core_clk) begin + tx_data_p <= tx_data_n; + end + + altlvds_tx #( + .center_align_msb ("UNUSED"), + .common_rx_tx_pll ("ON"), + .coreclock_divide_by (1), + .data_rate ("500.0 Mbps"), + .deserialization_factor (4), + .differential_drive (0), + .enable_clock_pin_mode ("UNUSED"), + .implement_in_les ("OFF"), + .inclock_boost (0), + .inclock_data_alignment ("EDGE_ALIGNED"), + .inclock_period (4000), + .inclock_phase_shift (0), + .intended_device_family ("Cyclone V"), + .lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_alt_lvds_tx"), + .lpm_type ("altlvds_tx"), + .multi_clock ("OFF"), + .number_of_channels (7), + .outclock_alignment ("EDGE_ALIGNED"), + .outclock_divide_by (2), + .outclock_duty_cycle (50), + .outclock_multiply_by (1), + .outclock_phase_shift (0), + .outclock_resource ("Regional clock"), + .output_data_rate (500), + .pll_compensation_mode ("AUTO"), + .pll_self_reset_on_loss_lock ("OFF"), + .preemphasis_setting (0), + .refclk_frequency ("250.000000 MHz"), + .registered_input ("TX_CORECLK"), + .use_external_pll ("OFF"), + .use_no_phase_shift ("ON"), + .vod_setting (0), + .clk_src_is_pll ("off") + ) i_altlvds_tx ( + .tx_inclock (tx_clk), + .tx_coreclock (core_clk), + .tx_in (tx_data_p), + .tx_outclock (tx_clk_out_p), + .tx_out ({tx_frame_out_p, tx_data_out_p}), + .tx_locked (tx_locked), + .pll_areset (1'b0), + .sync_inclock (1'b0), + .tx_data_reset (1'b0), + .tx_enable (1'b1), + .tx_pll_enable (1'b1), + .tx_syncclock (1'b0)); + +endmodule diff --git a/adi_library/axi_ad9361/intel/axi_ad9361_cmos_if.v b/adi_library/axi_ad9361/intel/axi_ad9361_cmos_if.v new file mode 100644 index 00000000..a3b02fa1 --- /dev/null +++ b/adi_library/axi_ad9361/intel/axi_ad9361_cmos_if.v @@ -0,0 +1,141 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9361_cmos_if #( + + parameter FPGA_TECHNOLOGY = 0, + parameter DAC_IODELAY_ENABLE = 0, + parameter CLK_DESKEW = 0, + parameter USE_SSI_CLK = 1, + + // Dummy parameters, required keep the code consistency(used on Xilinx) + parameter IO_DELAY_GROUP = "dev_if_delay_group", + parameter IODELAY_CTRL = 1, + parameter DELAY_REFCLK_FREQUENCY = 0 +) ( + + // physical interface (receive) + + input rx_clk_in, + input rx_frame_in, + input [11:0] rx_data_in, + + // physical interface (transmit) + + output tx_clk_out, + output tx_frame_out, + output [11:0] tx_data_out, + + // ensm control + + output enable, + output txnrx, + + // clock (common to both receive and transmit) + + input rst, + input clk, + output l_clk, + + // receive data path interface + + output adc_valid, + output [47:0] adc_data, + output adc_status, + input adc_r1_mode, + input adc_ddr_edgesel, + + // transmit data path interface + + input dac_valid, + input [47:0] dac_data, + input dac_clksel, + input dac_r1_mode, + + // tdd interface + + input tdd_enable, + input tdd_txnrx, + input tdd_mode, + + // delay interface + + input mmcm_rst, + input up_clk, + input up_rstn, + input up_enable, + input up_txnrx, + input [12:0] up_adc_dld, + input [64:0] up_adc_dwdata, + output [64:0] up_adc_drdata, + input [15:0] up_dac_dld, + input [79:0] up_dac_dwdata, + output [79:0] up_dac_drdata, + input delay_clk, + input delay_rst, + output delay_locked, + + // drp interface + + input up_drp_sel, + input up_drp_wr, + input [11:0] up_drp_addr, + input [31:0] up_drp_wdata, + output [31:0] up_drp_rdata, + output up_drp_ready, + output up_drp_locked +); + + // cmos is not supported on intel platforms yet. + + assign tx_clk_out = 1'd0; + assign tx_frame_out = 1'd0; + assign tx_data_out = 12'd0; + assign enable = 1'd0; + assign txnrx = 1'd0; + assign l_clk = 1'd0; + assign adc_valid = 1'd0; + assign adc_data = 48'd0; + assign adc_status = 1'd0; + assign up_adc_drdata = 65'd0; + assign up_dac_drdata = 80'd0; + assign delay_locked = 1'd0; + assign up_drp_rdata = 32'd0; + assign up_drp_ready = 1'd0; + assign up_drp_locked = 1'd0; + +endmodule diff --git a/adi_library/axi_ad9361/intel/axi_ad9361_lvds_if.v b/adi_library/axi_ad9361/intel/axi_ad9361_lvds_if.v new file mode 100644 index 00000000..78eb16fd --- /dev/null +++ b/adi_library/axi_ad9361/intel/axi_ad9361_lvds_if.v @@ -0,0 +1,571 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9361_lvds_if #( + + parameter FPGA_TECHNOLOGY = 0, + parameter DAC_IODELAY_ENABLE = 0, + parameter CLK_DESKEW = 0, + + // Dummy parameters, required keep the code consistency(used on Xilinx) + parameter USE_SSI_CLK = 1, + parameter IO_DELAY_GROUP = "dev_if_delay_group", + parameter IODELAY_CTRL = 1, + parameter DELAY_REFCLK_FREQUENCY = 0, + parameter RX_NODPA = 0 +) ( + + // physical interface (receive) + + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + + // physical interface (transmit) + + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, + + // ensm control + + output enable, + output txnrx, + + // clock (common to both receive and transmit) + + input rst, + input clk, + output l_clk, + + // receive data path interface + + output adc_valid, + output [47:0] adc_data, + output adc_status, + input adc_r1_mode, + input adc_ddr_edgesel, + + // transmit data path interface + + input dac_valid, + input [47:0] dac_data, + input dac_clksel, + input dac_r1_mode, + + // tdd interface + + input tdd_enable, + input tdd_txnrx, + input tdd_mode, + + // delay interface + + input mmcm_rst, + input up_clk, + input up_rstn, + input up_enable, + input up_txnrx, + input [ 6:0] up_adc_dld, + input [34:0] up_adc_dwdata, + output [34:0] up_adc_drdata, + input [ 9:0] up_dac_dld, + input [49:0] up_dac_dwdata, + output [49:0] up_dac_drdata, + input delay_clk, + input delay_rst, + output delay_locked, + + // drp interface + + input up_drp_sel, + input up_drp_wr, + input [11:0] up_drp_addr, + input [31:0] up_drp_wdata, + output [31:0] up_drp_rdata, + output up_drp_ready, + output up_drp_locked +); + + // internal registers + + reg up_drp_locked_m1 = 1'd0; + reg up_drp_locked_int = 1'd0; + reg rx_r1_mode = 'd0; + reg [ 3:0] rx_frame_d = 'd0; + reg [ 5:0] rx_data_3 = 'd0; + reg [ 5:0] rx_data_2 = 'd0; + reg [ 5:0] rx_data_1 = 'd0; + reg adc_valid_p = 'd0; + reg [47:0] adc_data_p = 'd0; + reg adc_status_p = 'd0; + reg adc_valid_int = 'd0; + reg [47:0] adc_data_int = 'd0; + reg adc_status_int = 'd0; + reg tx_valid = 'd0; + reg [47:0] tx_data = 'd0; + reg [ 3:0] tx_frame_p = 'd0; + reg [ 5:0] tx_data_0_p = 'd0; + reg [ 5:0] tx_data_1_p = 'd0; + reg [ 5:0] tx_data_2_p = 'd0; + reg [ 5:0] tx_data_3_p = 'd0; + reg [ 3:0] tx_frame = 'd0; + reg [ 5:0] tx_data_0 = 'd0; + reg [ 5:0] tx_data_1 = 'd0; + reg [ 5:0] tx_data_2 = 'd0; + reg [ 5:0] tx_data_3 = 'd0; + reg up_enable_int = 'd0; + reg up_txnrx_int = 'd0; + reg enable_up_m1 = 'd0; + reg txnrx_up_m1 = 'd0; + reg enable_up = 'd0; + reg txnrx_up = 'd0; + reg enable_int = 'd0; + reg txnrx_int = 'd0; + reg enable_int_p = 'd0; + reg txnrx_int_p = 'd0; + + // internal signals + + wire locked_s; + wire [ 3:0] rx_frame_s; + wire [ 5:0] rx_data_3_s; + wire [ 5:0] rx_data_2_s; + wire [ 5:0] rx_data_1_s; + wire [ 5:0] rx_data_0_s; + + // local parameters + + localparam CYCLONE5 = 101; + localparam ARRIA10 = 103; + + // unused interface signals + + assign up_adc_drdata = 35'b0; + assign up_dac_drdata = 50'b0; + assign delay_locked = 1'b1; + + // drp locked must be on up-clock + + assign up_drp_locked = up_drp_locked_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_drp_locked_m1 <= 1'd0; + up_drp_locked_int <= 1'd0; + end else begin + up_drp_locked_m1 <= locked_s; + up_drp_locked_int <= up_drp_locked_m1; + end + end + + // r1mode + + generate if (CLK_DESKEW) begin + + reg adc_r1_mode_n = 'd0; + + always @(negedge clk) begin + adc_r1_mode_n <= adc_r1_mode; + end + + always @(posedge l_clk) begin + rx_r1_mode <= adc_r1_mode_n; + end + + end else begin /* CLK_DESKEW == 0 */ + + always @(posedge l_clk) begin + rx_r1_mode <= adc_r1_mode; + end + + end + endgenerate + + // frame check + + always @(posedge l_clk) begin + if (rx_r1_mode == 1'd1) begin + rx_frame_d <= rx_frame_s; + end else begin + rx_frame_d <= ~rx_frame_s; + end + end + + // data hold + + always @(posedge l_clk) begin + rx_data_3 <= rx_data_3_s; + rx_data_2 <= rx_data_2_s; + rx_data_1 <= rx_data_1_s; + end + + // delineation + + always @(posedge l_clk) begin + case ({rx_r1_mode, rx_frame_s}) + 5'b01111: begin + adc_valid_p <= 1'b0; + adc_data_p[47:24] <= 24'd0; + adc_data_p[23:12] <= {rx_data_1_s, rx_data_3_s}; + adc_data_p[11: 0] <= {rx_data_0_s, rx_data_2_s}; + end + 5'b00000: begin + adc_valid_p <= 1'b1; + adc_data_p[47:36] <= {rx_data_1_s, rx_data_3_s}; + adc_data_p[35:24] <= {rx_data_0_s, rx_data_2_s}; + adc_data_p[23: 0] <= adc_data_p[23:0]; + end + 5'b00111: begin + adc_valid_p <= 1'b0; + adc_data_p[47:24] <= 24'd0; + adc_data_p[23:12] <= {rx_data_0_s, rx_data_2_s}; + adc_data_p[11: 0] <= {rx_data_3, rx_data_1_s}; + end + 5'b01000: begin + adc_valid_p <= 1'b1; + adc_data_p[47:36] <= {rx_data_0_s, rx_data_2_s}; + adc_data_p[35:24] <= {rx_data_3, rx_data_1_s}; + adc_data_p[23: 0] <= adc_data_p[23:0]; + end + 5'b00011: begin + adc_valid_p <= 1'b0; + adc_data_p[47:24] <= 24'd0; + adc_data_p[23:12] <= {rx_data_3, rx_data_1_s}; + adc_data_p[11: 0] <= {rx_data_2, rx_data_0_s}; + end + 5'b01100: begin + adc_valid_p <= 1'b1; + adc_data_p[47:36] <= {rx_data_3, rx_data_1_s}; + adc_data_p[35:24] <= {rx_data_2, rx_data_0_s}; + adc_data_p[23: 0] <= adc_data_p[23:0]; + end + 5'b00001: begin + adc_valid_p <= 1'b0; + adc_data_p[47:24] <= 24'd0; + adc_data_p[23:12] <= {rx_data_2, rx_data_0_s}; + adc_data_p[11: 0] <= {rx_data_1, rx_data_3}; + end + 5'b01110: begin + adc_valid_p <= 1'b1; + adc_data_p[47:36] <= {rx_data_2, rx_data_0_s}; + adc_data_p[35:24] <= {rx_data_1, rx_data_3}; + adc_data_p[23: 0] <= adc_data_p[23:0]; + end + 5'b10011: begin + adc_valid_p <= 1'b1; + adc_data_p[47:24] <= 24'd0; + adc_data_p[23:12] <= {rx_data_1_s, rx_data_3_s}; + adc_data_p[11: 0] <= {rx_data_0_s, rx_data_2_s}; + end + 5'b11001: begin + adc_valid_p <= 1'b1; + adc_data_p[47:24] <= 24'd0; + adc_data_p[23:12] <= {rx_data_0_s, rx_data_2_s}; + adc_data_p[11: 0] <= {rx_data_3, rx_data_1_s}; + end + 5'b11100: begin + adc_valid_p <= 1'b1; + adc_data_p[47:24] <= 24'd0; + adc_data_p[23:12] <= {rx_data_3, rx_data_1_s}; + adc_data_p[11: 0] <= {rx_data_2, rx_data_0_s}; + end + 5'b10110: begin + adc_valid_p <= 1'b1; + adc_data_p[47:24] <= 24'd0; + adc_data_p[23:12] <= {rx_data_2, rx_data_0_s}; + adc_data_p[11: 0] <= {rx_data_1, rx_data_3}; + end + default: begin + adc_valid_p <= 1'b0; + adc_data_p <= 48'd0; + end + endcase + end + + // adc-status + + always @(posedge l_clk) begin + if (rx_frame_d == rx_frame_s) begin + adc_status_p <= locked_s; + end else begin + adc_status_p <= 1'b0; + end + end + + // transfer to common clock + + generate if (CLK_DESKEW) begin + + reg adc_valid_n = 'd0; + reg [47:0] adc_data_n = 'd0; + reg adc_status_n = 'd0; + + always @(negedge l_clk) begin + adc_valid_n <= adc_valid_p; + adc_data_n <= adc_data_p; + adc_status_n <= adc_status_p; + end + + always @(posedge clk) begin + adc_valid_int <= adc_valid_n; + adc_data_int <= adc_data_n; + adc_status_int <= adc_status_n; + end + + end else begin /* CLK_DESKEW == 0 */ + + always @(posedge l_clk) begin + adc_valid_int <= adc_valid_p; + adc_data_int <= adc_data_p; + adc_status_int <= adc_status_p; + end + + end + endgenerate + + assign adc_valid = adc_valid_int; + assign adc_data = adc_data_int; + assign adc_status = adc_status_int; + + // dac-tx interface + + always @(posedge clk) begin + tx_valid <= dac_valid; + if (dac_valid == 1'b1) begin + tx_data <= dac_data; + end + end + + always @(posedge clk) begin + if (dac_r1_mode == 1'b1) begin + tx_frame_p <= 4'b0011; + tx_data_0_p <= tx_data[11: 6]; + tx_data_1_p <= tx_data[23:18]; + tx_data_2_p <= tx_data[ 5: 0]; + tx_data_3_p <= tx_data[17:12]; + end else if (tx_valid == 1'b1) begin + tx_frame_p <= 4'b1111; + tx_data_0_p <= tx_data[11: 6]; + tx_data_1_p <= tx_data[23:18]; + tx_data_2_p <= tx_data[ 5: 0]; + tx_data_3_p <= tx_data[17:12]; + end else begin + tx_frame_p <= 4'b0000; + tx_data_0_p <= tx_data[35:30]; + tx_data_1_p <= tx_data[47:42]; + tx_data_2_p <= tx_data[29:24]; + tx_data_3_p <= tx_data[41:36]; + end + end + + // transfer to local clock + + generate if (CLK_DESKEW) begin + + reg tx_frame_n = 'd0; + reg [ 5:0] tx_data_0_n = 'd0; + reg [ 5:0] tx_data_1_n = 'd0; + reg [ 5:0] tx_data_2_n = 'd0; + reg [ 5:0] tx_data_3_n = 'd0; + + always @(negedge clk) begin + tx_frame_n <= tx_frame_p; + tx_data_0_n <= tx_data_0_p; + tx_data_1_n <= tx_data_1_p; + tx_data_2_n <= tx_data_2_p; + tx_data_3_n <= tx_data_3_p; + end + + always @(posedge l_clk) begin + tx_frame <= tx_frame_n; + tx_data_0 <= tx_data_0_n; + tx_data_1 <= tx_data_1_n; + tx_data_2 <= tx_data_2_n; + tx_data_3 <= tx_data_3_n; + end + + end else begin /* CLK_DESKEW == 0 */ + + always @(posedge l_clk) begin + tx_frame <= tx_frame_p; + tx_data_0 <= tx_data_0_p; + tx_data_1 <= tx_data_1_p; + tx_data_2 <= tx_data_2_p; + tx_data_3 <= tx_data_3_p; + end + + end + endgenerate + + // tdd/ensm control + + always @(posedge up_clk) begin + up_enable_int <= up_enable; + up_txnrx_int <= up_txnrx; + end + + always @(posedge clk or posedge rst) begin + if (rst == 1'b1) begin + enable_up_m1 <= 1'b0; + txnrx_up_m1 <= 1'b0; + enable_up <= 1'b0; + txnrx_up <= 1'b0; + end else begin + enable_up_m1 <= up_enable_int; + txnrx_up_m1 <= up_txnrx_int; + enable_up <= enable_up_m1; + txnrx_up <= txnrx_up_m1; + end + end + + always @(posedge clk) begin + if (tdd_mode == 1'b1) begin + enable_int <= tdd_enable; + txnrx_int <= tdd_txnrx; + end else begin + enable_int <= enable_up; + txnrx_int <= txnrx_up; + end + end + + generate if (CLK_DESKEW) begin + + reg enable_int_n = 'd0; + reg txnrx_int_n = 'd0; + + always @(negedge clk) begin + enable_int_n <= enable_int; + txnrx_int_n <= txnrx_int; + end + + always @(posedge l_clk) begin + enable_int_p <= enable_int_n; + txnrx_int_p <= txnrx_int_n; + end + + end else begin /* CLK_DESKEW == 0 */ + + always @(posedge l_clk) begin + enable_int_p <= enable_int; + txnrx_int_p <= txnrx_int; + end + + end + endgenerate + + generate + if (FPGA_TECHNOLOGY == CYCLONE5) begin + axi_ad9361_lvds_if_c5 i_axi_ad9361_lvds_if_c5 ( + .rx_clk_in_p (rx_clk_in_p), + .rx_clk_in_n (rx_clk_in_n), + .rx_frame_in_p (rx_frame_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_data_in_n (rx_data_in_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_clk_out_n (tx_clk_out_n), + .tx_frame_out_p (tx_frame_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_data_out_n (tx_data_out_n), + .enable (enable), + .txnrx (txnrx), + .clk (l_clk), + .rx_frame (rx_frame_s), + .rx_data_0 (rx_data_0_s), + .rx_data_1 (rx_data_1_s), + .rx_data_2 (rx_data_2_s), + .rx_data_3 (rx_data_3_s), + .tx_frame (tx_frame), + .tx_data_0 (tx_data_0), + .tx_data_1 (tx_data_1), + .tx_data_2 (tx_data_2), + .tx_data_3 (tx_data_3), + .tx_enable (enable_int_p), + .tx_txnrx (txnrx_int_p), + .locked (locked_s), + .up_clk (up_clk), + .up_rstn (up_rstn)); + end + endgenerate + + generate + if (FPGA_TECHNOLOGY == ARRIA10) begin + axi_ad9361_lvds_if_10 #( + .RX_NODPA (RX_NODPA) + ) i_axi_ad9361_lvds_if_10 ( + .rx_clk_in_p (rx_clk_in_p), + .rx_clk_in_n (rx_clk_in_n), + .rx_frame_in_p (rx_frame_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_data_in_n (rx_data_in_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_clk_out_n (tx_clk_out_n), + .tx_frame_out_p (tx_frame_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_data_out_n (tx_data_out_n), + .enable (enable), + .txnrx (txnrx), + .clk (l_clk), + .rx_frame (rx_frame_s), + .rx_data_0 (rx_data_0_s), + .rx_data_1 (rx_data_1_s), + .rx_data_2 (rx_data_2_s), + .rx_data_3 (rx_data_3_s), + .tx_frame (tx_frame), + .tx_data_0 (tx_data_0), + .tx_data_1 (tx_data_1), + .tx_data_2 (tx_data_2), + .tx_data_3 (tx_data_3), + .tx_enable (enable_int_p), + .tx_txnrx (txnrx_int_p), + .locked (locked_s), + .up_clk (up_clk), + .up_rstn (up_rstn)); + end + endgenerate + +endmodule diff --git a/adi_library/axi_ad9361/intel/axi_ad9361_lvds_if_10.v b/adi_library/axi_ad9361/intel/axi_ad9361_lvds_if_10.v new file mode 100644 index 00000000..1e35d129 --- /dev/null +++ b/adi_library/axi_ad9361/intel/axi_ad9361_lvds_if_10.v @@ -0,0 +1,306 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9361_lvds_if_10 #( + + parameter RX_NODPA = 0 +) ( + + // physical interface (receive) + + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + + // physical interface (transmit) + + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, + + // ensm control + + output enable, + output txnrx, + + // clock (common to both receive and transmit) + + output clk, + + // receive data path interface + + output [ 3:0] rx_frame, + output [ 5:0] rx_data_0, + output [ 5:0] rx_data_1, + output [ 5:0] rx_data_2, + output [ 5:0] rx_data_3, + + // transmit data path interface + + input [ 3:0] tx_frame, + input [ 5:0] tx_data_0, + input [ 5:0] tx_data_1, + input [ 5:0] tx_data_2, + input [ 5:0] tx_data_3, + input tx_enable, + input tx_txnrx, + + // locked (status) + + output locked, + + // delay interface + + input up_clk, + input up_rstn +); + + // internal registers + + reg pll_rst = 1'd1; + reg locked_int = 'd0; + + // internal signals + + wire [27:0] rx_data_s; + wire [ 6:0] rx_data_locked_s; + wire [ 6:0] rx_delay_locked_s; + wire [27:0] tx_data_s; + wire locked_s; + wire lvds_clk; + wire lvds_loaden; + wire [ 7:0] lvds_phase; + wire rx_clk; + + // pll reset + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + pll_rst <= 1'b1; + end else begin + pll_rst <= 1'b0; + end + end + + assign locked = locked_int; + + always @(posedge clk) begin + locked_int <= locked_s & (& rx_data_locked_s) & + (& rx_delay_locked_s); + end + + // receive + + assign rx_frame[3] = rx_data_s[24]; + assign rx_frame[2] = rx_data_s[25]; + assign rx_frame[1] = rx_data_s[26]; + assign rx_frame[0] = rx_data_s[27]; + + assign rx_data_3[5] = rx_data_s[20]; + assign rx_data_3[4] = rx_data_s[16]; + assign rx_data_3[3] = rx_data_s[12]; + assign rx_data_3[2] = rx_data_s[ 8]; + assign rx_data_3[1] = rx_data_s[ 4]; + assign rx_data_3[0] = rx_data_s[ 0]; + assign rx_data_2[5] = rx_data_s[21]; + assign rx_data_2[4] = rx_data_s[17]; + assign rx_data_2[3] = rx_data_s[13]; + assign rx_data_2[2] = rx_data_s[ 9]; + assign rx_data_2[1] = rx_data_s[ 5]; + assign rx_data_2[0] = rx_data_s[ 1]; + assign rx_data_1[5] = rx_data_s[22]; + assign rx_data_1[4] = rx_data_s[18]; + assign rx_data_1[3] = rx_data_s[14]; + assign rx_data_1[2] = rx_data_s[10]; + assign rx_data_1[1] = rx_data_s[ 6]; + assign rx_data_1[0] = rx_data_s[ 2]; + assign rx_data_0[5] = rx_data_s[23]; + assign rx_data_0[4] = rx_data_s[19]; + assign rx_data_0[3] = rx_data_s[15]; + assign rx_data_0[2] = rx_data_s[11]; + assign rx_data_0[1] = rx_data_s[ 7]; + assign rx_data_0[0] = rx_data_s[ 3]; + + // transmit + + assign tx_clk_out_n = 1'd0; + assign tx_frame_out_n = 1'd0; + assign tx_data_out_n = 6'd0; + + assign tx_data_s[24] = tx_frame[3]; + assign tx_data_s[25] = tx_frame[2]; + assign tx_data_s[26] = tx_frame[1]; + assign tx_data_s[27] = tx_frame[0]; + + assign tx_data_s[20] = tx_data_3[5]; + assign tx_data_s[16] = tx_data_3[4]; + assign tx_data_s[12] = tx_data_3[3]; + assign tx_data_s[ 8] = tx_data_3[2]; + assign tx_data_s[ 4] = tx_data_3[1]; + assign tx_data_s[ 0] = tx_data_3[0]; + assign tx_data_s[21] = tx_data_2[5]; + assign tx_data_s[17] = tx_data_2[4]; + assign tx_data_s[13] = tx_data_2[3]; + assign tx_data_s[ 9] = tx_data_2[2]; + assign tx_data_s[ 5] = tx_data_2[1]; + assign tx_data_s[ 1] = tx_data_2[0]; + assign tx_data_s[22] = tx_data_1[5]; + assign tx_data_s[18] = tx_data_1[4]; + assign tx_data_s[14] = tx_data_1[3]; + assign tx_data_s[10] = tx_data_1[2]; + assign tx_data_s[ 6] = tx_data_1[1]; + assign tx_data_s[ 2] = tx_data_1[0]; + assign tx_data_s[23] = tx_data_0[5]; + assign tx_data_s[19] = tx_data_0[4]; + assign tx_data_s[15] = tx_data_0[3]; + assign tx_data_s[11] = tx_data_0[2]; + assign tx_data_s[ 7] = tx_data_0[1]; + assign tx_data_s[ 3] = tx_data_0[0]; + + // instantiations + + genvar i; + generate + for (i = 0; i < 6; i = i + 1) begin: g_rx_data + if (RX_NODPA == 0) begin + axi_ad9361_serdes_in i_rx_data ( + .data_in_export (rx_data_in_p[i]), + .clk_export (lvds_clk), + .loaden_export (lvds_loaden), + .div_clk_export (clk), + .hs_phase_export (lvds_phase), + .locked_export (rx_data_locked_s[i]), + .data_s_export (rx_data_s[((i*4)+3):(i*4)]), + .delay_locked_export (rx_delay_locked_s[i])); + end else begin + axi_ad9361_serdes_in i_rx_data ( + .data_in_export (rx_data_in_p[i]), + .clk_export (lvds_clk), + .loaden_export (lvds_loaden), + .div_clk_export (clk), + .data_s_export (rx_data_s[((i*4)+3):(i*4)])); + + assign rx_data_locked_s[i] = 1'b1; + assign rx_delay_locked_s[i] = 1'b1; + + end + end + + if (RX_NODPA == 0) begin + + axi_ad9361_serdes_in i_rx_frame ( + .data_in_export (rx_frame_in_p), + .clk_export (lvds_clk), + .loaden_export (lvds_loaden), + .div_clk_export (clk), + .hs_phase_export (lvds_phase), + .locked_export (rx_data_locked_s[6]), + .data_s_export (rx_data_s[27:24]), + .delay_locked_export (rx_delay_locked_s[6])); + + assign rx_clk = rx_clk_in_p; + + end else begin + + axi_ad9361_serdes_in i_rx_frame ( + .data_in_export (rx_frame_in_p), + .clk_export (lvds_clk), + .loaden_export (lvds_loaden), + .div_clk_export (clk), + .data_s_export (rx_data_s[27:24]) ); + + assign rx_data_locked_s[6] = 1'b1; + assign rx_delay_locked_s[6] = 1'b1; + + clk_buffer clk_buf ( + .inclk (rx_clk_in_p), + .outclk (rx_clk)); + + end + endgenerate + + generate + for (i = 0; i < 6; i = i + 1) begin: g_tx_data + axi_ad9361_serdes_out i_tx_data ( + .data_out_export (tx_data_out_p[i]), + .clk_export (lvds_clk), + .loaden_export (lvds_loaden), + .div_clk_export (clk), + .data_s_export (tx_data_s[((i*4)+3):(i*4)])); + end + endgenerate + + axi_ad9361_serdes_out i_tx_frame ( + .data_out_export (tx_frame_out_p), + .clk_export (lvds_clk), + .loaden_export (lvds_loaden), + .div_clk_export (clk), + .data_s_export (tx_data_s[27:24])); + + axi_ad9361_serdes_out i_tx_clk ( + .data_out_export (tx_clk_out_p), + .clk_export (lvds_clk), + .loaden_export (lvds_loaden), + .div_clk_export (clk), + .data_s_export (4'b1010)); + + axi_ad9361_data_out i_enable ( + .ck (clk), + .din ({tx_enable, tx_enable}), + .pad_out (enable)); + + axi_ad9361_data_out i_txnrx ( + .ck (clk), + .din ({tx_txnrx, tx_txnrx}), + .pad_out (txnrx)); + + axi_ad9361_serdes_clk i_clk ( + .rst_reset (pll_rst), + .ref_clk_clk (rx_clk), + .locked_export (locked_s), + .hs_phase_phout (lvds_phase), + .hs_clk_lvds_clk (lvds_clk), + .loaden_loaden (lvds_loaden), + .ls_clk_clk (clk)); + +endmodule diff --git a/adi_library/axi_ad9361/intel/axi_ad9361_lvds_if_c5.v b/adi_library/axi_ad9361/intel/axi_ad9361_lvds_if_c5.v new file mode 100644 index 00000000..a01980ad --- /dev/null +++ b/adi_library/axi_ad9361/intel/axi_ad9361_lvds_if_c5.v @@ -0,0 +1,395 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9361_lvds_if_c5 ( + + // physical interface (receive) + + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + + // physical interface (transmit) + + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, + + // ensm control + + output enable, + output txnrx, + + // clock (common to both receive and transmit) + + output clk, + + // receive data path interface + + output [ 3:0] rx_frame, + output [ 5:0] rx_data_0, + output [ 5:0] rx_data_1, + output [ 5:0] rx_data_2, + output [ 5:0] rx_data_3, + + // transmit data path interface + + input [ 3:0] tx_frame, + input [ 5:0] tx_data_0, + input [ 5:0] tx_data_1, + input [ 5:0] tx_data_2, + input [ 5:0] tx_data_3, + input tx_enable, + input tx_txnrx, + + // locked (status) + + output locked, + + // delay interface + + input up_clk, + input up_rstn +); + + // internal registers + + reg pll_rst = 1'd1; + reg locked_int = 'd0; + reg tx_core_enable_int = 'd0; + reg tx_core_txnrx_int = 'd0; + reg [27:0] tx_core_data_int = 'd0; + reg tx_core_enable = 'd0; + reg tx_core_txnrx = 'd0; + reg [27:0] tx_core_data = 'd0; + reg tx_locked_int = 'd0; + reg tx_locked = 'd0; + + // internal signals + + wire [27:0] rx_core_data_s; + wire rx_locked_s; + wire tx_core_clk; + wire tx_locked_s; + + // pll reset + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + pll_rst <= 1'b1; + end else begin + pll_rst <= 1'b0; + end + end + + assign locked = locked_int; + + always @(posedge clk) begin + locked_int <= rx_locked_s & tx_locked; + end + + // receive + + assign rx_frame[3] = rx_core_data_s[24]; + assign rx_frame[2] = rx_core_data_s[25]; + assign rx_frame[1] = rx_core_data_s[26]; + assign rx_frame[0] = rx_core_data_s[27]; + + assign rx_data_3[5] = rx_core_data_s[20]; + assign rx_data_3[4] = rx_core_data_s[16]; + assign rx_data_3[3] = rx_core_data_s[12]; + assign rx_data_3[2] = rx_core_data_s[ 8]; + assign rx_data_3[1] = rx_core_data_s[ 4]; + assign rx_data_3[0] = rx_core_data_s[ 0]; + assign rx_data_2[5] = rx_core_data_s[21]; + assign rx_data_2[4] = rx_core_data_s[17]; + assign rx_data_2[3] = rx_core_data_s[13]; + assign rx_data_2[2] = rx_core_data_s[ 9]; + assign rx_data_2[1] = rx_core_data_s[ 5]; + assign rx_data_2[0] = rx_core_data_s[ 1]; + assign rx_data_1[5] = rx_core_data_s[22]; + assign rx_data_1[4] = rx_core_data_s[18]; + assign rx_data_1[3] = rx_core_data_s[14]; + assign rx_data_1[2] = rx_core_data_s[10]; + assign rx_data_1[1] = rx_core_data_s[ 6]; + assign rx_data_1[0] = rx_core_data_s[ 2]; + assign rx_data_0[5] = rx_core_data_s[23]; + assign rx_data_0[4] = rx_core_data_s[19]; + assign rx_data_0[3] = rx_core_data_s[15]; + assign rx_data_0[2] = rx_core_data_s[11]; + assign rx_data_0[1] = rx_core_data_s[ 7]; + assign rx_data_0[0] = rx_core_data_s[ 3]; + + // transmit (by definition, tx_core_clk and clk are the same (shared pll)) + // however, we safe guard transition - incase you keep them separate + + assign tx_clk_out_n = 1'd0; + assign tx_frame_out_n = 1'd0; + assign tx_data_out_n = 6'd0; + + always @(negedge clk) begin + tx_core_enable_int <= tx_enable; + tx_core_txnrx_int <= tx_txnrx; + tx_core_data_int[24] <= tx_frame[3]; + tx_core_data_int[25] <= tx_frame[2]; + tx_core_data_int[26] <= tx_frame[1]; + tx_core_data_int[27] <= tx_frame[0]; + tx_core_data_int[20] <= tx_data_3[5]; + tx_core_data_int[16] <= tx_data_3[4]; + tx_core_data_int[12] <= tx_data_3[3]; + tx_core_data_int[ 8] <= tx_data_3[2]; + tx_core_data_int[ 4] <= tx_data_3[1]; + tx_core_data_int[ 0] <= tx_data_3[0]; + tx_core_data_int[21] <= tx_data_2[5]; + tx_core_data_int[17] <= tx_data_2[4]; + tx_core_data_int[13] <= tx_data_2[3]; + tx_core_data_int[ 9] <= tx_data_2[2]; + tx_core_data_int[ 5] <= tx_data_2[1]; + tx_core_data_int[ 1] <= tx_data_2[0]; + tx_core_data_int[22] <= tx_data_1[5]; + tx_core_data_int[18] <= tx_data_1[4]; + tx_core_data_int[14] <= tx_data_1[3]; + tx_core_data_int[10] <= tx_data_1[2]; + tx_core_data_int[ 6] <= tx_data_1[1]; + tx_core_data_int[ 2] <= tx_data_1[0]; + tx_core_data_int[23] <= tx_data_0[5]; + tx_core_data_int[19] <= tx_data_0[4]; + tx_core_data_int[15] <= tx_data_0[3]; + tx_core_data_int[11] <= tx_data_0[2]; + tx_core_data_int[ 7] <= tx_data_0[1]; + tx_core_data_int[ 3] <= tx_data_0[0]; + end + + always @(posedge tx_core_clk) begin + tx_core_enable <= tx_core_enable_int; + tx_core_txnrx <= tx_core_txnrx_int; + tx_core_data <= tx_core_data_int; + end + + always @(negedge tx_core_clk) begin + tx_locked_int <= tx_locked_s; + end + + always @(posedge clk) begin + tx_locked <= tx_locked_int; + end + + // instantiations + + altlvds_rx #( + .buffer_implementation ("RAM"), + .cds_mode ("UNUSED"), + .common_rx_tx_pll ("ON"), + .data_align_rollover (4), + .data_rate ("500.0 Mbps"), + .deserialization_factor (4), + .dpa_initial_phase_value (0), + .dpll_lock_count (0), + .dpll_lock_window (0), + .enable_clock_pin_mode ("UNUSED"), + .enable_dpa_align_to_rising_edge_only ("OFF"), + .enable_dpa_calibration ("ON"), + .enable_dpa_fifo ("UNUSED"), + .enable_dpa_initial_phase_selection ("OFF"), + .enable_dpa_mode ("OFF"), + .enable_dpa_pll_calibration ("OFF"), + .enable_soft_cdr_mode ("OFF"), + .implement_in_les ("OFF"), + .inclock_boost (0), + .inclock_data_alignment ("EDGE_ALIGNED"), + .inclock_period (4000), + .inclock_phase_shift (0), + .input_data_rate (500), + .intended_device_family ("Cyclone V"), + .lose_lock_on_one_change ("UNUSED"), + .lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_lvds_if_c5_rx"), + .lpm_type ("altlvds_rx"), + .number_of_channels (7), + .outclock_resource ("Global clock"), + .pll_operation_mode ("NORMAL"), + .pll_self_reset_on_loss_lock ("UNUSED"), + .port_rx_channel_data_align ("PORT_UNUSED"), + .port_rx_data_align ("PORT_UNUSED"), + .refclk_frequency ("250.000000 MHz"), + .registered_data_align_input ("UNUSED"), + .registered_output ("ON"), + .reset_fifo_at_first_lock ("UNUSED"), + .rx_align_data_reg ("RISING_EDGE"), + .sim_dpa_is_negative_ppm_drift ("OFF"), + .sim_dpa_net_ppm_variation (0), + .sim_dpa_output_clock_phase_shift (0), + .use_coreclock_input ("OFF"), + .use_dpll_rawperror ("OFF"), + .use_external_pll ("OFF"), + .use_no_phase_shift ("ON"), + .x_on_bitslip ("ON"), + .clk_src_is_pll ("off")) + i_altlvds_rx ( + .pll_areset (pll_rst), + .rx_in ({rx_frame_in_p, rx_data_in_p}), + .rx_inclock (rx_clk_in_p), + .rx_locked (rx_locked_s), + .rx_out (rx_core_data_s), + .rx_outclock (clk), + .dpa_pll_cal_busy (), + .dpa_pll_recal (1'b0), + .pll_phasecounterselect (), + .pll_phasedone (1'b1), + .pll_phasestep (), + .pll_phaseupdown (), + .pll_scanclk (), + .rx_cda_max (), + .rx_cda_reset ({7{1'b0}}), + .rx_channel_data_align ({7{1'b0}}), + .rx_coreclk ({7{1'b1}}), + .rx_data_align (1'b0), + .rx_data_align_reset (1'b0), + .rx_data_reset (1'b0), + .rx_deskew (1'b0), + .rx_divfwdclk (), + .rx_dpa_lock_reset ({7{1'b0}}), + .rx_dpa_locked (), + .rx_dpaclock (1'b0), + .rx_dpll_enable ({7{1'b1}}), + .rx_dpll_hold ({7{1'b0}}), + .rx_dpll_reset ({7{1'b0}}), + .rx_enable (1'b1), + .rx_fifo_reset ({7{1'b0}}), + .rx_pll_enable (1'b1), + .rx_readclock (1'b0), + .rx_reset ({7{1'b0}}), + .rx_syncclock (1'b0)); + + altlvds_tx #( + .center_align_msb ("UNUSED"), + .common_rx_tx_pll ("ON"), + .coreclock_divide_by (1), + .data_rate ("500.0 Mbps"), + .deserialization_factor (4), + .differential_drive (0), + .enable_clock_pin_mode ("UNUSED"), + .implement_in_les ("OFF"), + .inclock_boost (0), + .inclock_data_alignment ("EDGE_ALIGNED"), + .inclock_period (4000), + .inclock_phase_shift (0), + .intended_device_family ("Cyclone V"), + .lpm_hint ("CBX_MODULE_PREFIX=axi_ad9361_lvds_if_c5_tx"), + .lpm_type ("altlvds_tx"), + .multi_clock ("OFF"), + .number_of_channels (7), + .outclock_alignment ("EDGE_ALIGNED"), + .outclock_divide_by (2), + .outclock_duty_cycle (50), + .outclock_multiply_by (1), + .outclock_phase_shift (0), + .outclock_resource ("Global clock"), + .output_data_rate (500), + .pll_compensation_mode ("AUTO"), + .pll_self_reset_on_loss_lock ("OFF"), + .preemphasis_setting (0), + .refclk_frequency ("250.000000 MHz"), + .registered_input ("TX_CORECLK"), + .use_external_pll ("OFF"), + .use_no_phase_shift ("ON"), + .vod_setting (0), + .clk_src_is_pll ("off")) + i_altlvds_tx ( + .pll_areset (pll_rst), + .tx_in (tx_core_data), + .tx_inclock (rx_clk_in_p), + .tx_coreclock (tx_core_clk), + .tx_locked (tx_locked_s), + .tx_out ({tx_frame_out_p, tx_data_out_p}), + .tx_outclock (tx_clk_out_p), + .sync_inclock (1'b0), + .tx_data_reset (1'b0), + .tx_enable (1'b1), + .tx_pll_enable (1'b1), + .tx_syncclock (1'b0)); + + altddio_out #( + .extend_oe_disable ("OFF"), + .intended_device_family ("Cyclone V"), + .invert_output ("OFF"), + .lpm_hint ("UNUSED"), + .lpm_type ("altddio_out"), + .oe_reg ("UNREGISTERED"), + .power_up_high ("OFF"), + .width (1)) + i_altddio_enable ( + .datain_h (tx_core_enable), + .datain_l (tx_core_enable), + .outclock (tx_core_clk), + .dataout (enable), + .aclr (1'b0), + .aset (1'b0), + .oe (1'b1), + .oe_out (), + .outclocken (1'b1), + .sclr (1'b0), + .sset (1'b0)); + + altddio_out #( + .extend_oe_disable ("OFF"), + .intended_device_family ("Cyclone V"), + .invert_output ("OFF"), + .lpm_hint ("UNUSED"), + .lpm_type ("altddio_out"), + .oe_reg ("UNREGISTERED"), + .power_up_high ("OFF"), + .width (1)) + i_altddio_txnrx ( + .datain_h (tx_core_txnrx), + .datain_l (tx_core_txnrx), + .outclock (tx_core_clk), + .dataout (txnrx), + .aclr (1'b0), + .aset (1'b0), + .oe (1'b1), + .oe_out (), + .outclocken (1'b1), + .sclr (1'b0), + .sset (1'b0)); + +endmodule diff --git a/adi_library/axi_ad9361/temporary_case_dependencies.mk b/adi_library/axi_ad9361/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/axi_ad9361/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/axi_ad9361/xgui/axi_ad9361_v1_0.tcl b/adi_library/axi_ad9361/xgui/axi_ad9361_v1_0.tcl new file mode 100644 index 00000000..4c57af9e --- /dev/null +++ b/adi_library/axi_ad9361/xgui/axi_ad9361_v1_0.tcl @@ -0,0 +1,492 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ADC_DATAFORMAT_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "ADC_DATAPATH_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "ADC_DCFILTER_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "ADC_INIT_DELAY" -parent ${Page_0} + ipgui::add_param $IPINST -name "ADC_IQCORRECTION_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "ADC_USERPORTS_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "CMOS_OR_LVDS_N" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_CLK_EDGE_SEL" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_DATAPATH_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_DW" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_PHASE_DW" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_DDS_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_DDS_PHASE_DW" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_DDS_TYPE" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_INIT_DELAY" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_IODELAY_ENABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_IQCORRECTION_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_USERPORTS_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "DELAY_REFCLK_FREQUENCY" -parent ${Page_0} + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "IODELAY_CTRL" -parent ${Page_0} + ipgui::add_param $IPINST -name "IO_DELAY_GROUP" -parent ${Page_0} + ipgui::add_param $IPINST -name "MIMO_ENABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "MODE_1R1T" -parent ${Page_0} + ipgui::add_param $IPINST -name "PPS_RECEIVER_ENABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "TDD_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "USE_SSI_CLK" -parent ${Page_0} + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.ADC_DATAFORMAT_DISABLE { PARAM_VALUE.ADC_DATAFORMAT_DISABLE } { + # Procedure called to update ADC_DATAFORMAT_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADC_DATAFORMAT_DISABLE { PARAM_VALUE.ADC_DATAFORMAT_DISABLE } { + # Procedure called to validate ADC_DATAFORMAT_DISABLE + return true +} + +proc update_PARAM_VALUE.ADC_DATAPATH_DISABLE { PARAM_VALUE.ADC_DATAPATH_DISABLE } { + # Procedure called to update ADC_DATAPATH_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADC_DATAPATH_DISABLE { PARAM_VALUE.ADC_DATAPATH_DISABLE } { + # Procedure called to validate ADC_DATAPATH_DISABLE + return true +} + +proc update_PARAM_VALUE.ADC_DCFILTER_DISABLE { PARAM_VALUE.ADC_DCFILTER_DISABLE } { + # Procedure called to update ADC_DCFILTER_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADC_DCFILTER_DISABLE { PARAM_VALUE.ADC_DCFILTER_DISABLE } { + # Procedure called to validate ADC_DCFILTER_DISABLE + return true +} + +proc update_PARAM_VALUE.ADC_INIT_DELAY { PARAM_VALUE.ADC_INIT_DELAY } { + # Procedure called to update ADC_INIT_DELAY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADC_INIT_DELAY { PARAM_VALUE.ADC_INIT_DELAY } { + # Procedure called to validate ADC_INIT_DELAY + return true +} + +proc update_PARAM_VALUE.ADC_IQCORRECTION_DISABLE { PARAM_VALUE.ADC_IQCORRECTION_DISABLE } { + # Procedure called to update ADC_IQCORRECTION_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADC_IQCORRECTION_DISABLE { PARAM_VALUE.ADC_IQCORRECTION_DISABLE } { + # Procedure called to validate ADC_IQCORRECTION_DISABLE + return true +} + +proc update_PARAM_VALUE.ADC_USERPORTS_DISABLE { PARAM_VALUE.ADC_USERPORTS_DISABLE } { + # Procedure called to update ADC_USERPORTS_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADC_USERPORTS_DISABLE { PARAM_VALUE.ADC_USERPORTS_DISABLE } { + # Procedure called to validate ADC_USERPORTS_DISABLE + return true +} + +proc update_PARAM_VALUE.CMOS_OR_LVDS_N { PARAM_VALUE.CMOS_OR_LVDS_N } { + # Procedure called to update CMOS_OR_LVDS_N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CMOS_OR_LVDS_N { PARAM_VALUE.CMOS_OR_LVDS_N } { + # Procedure called to validate CMOS_OR_LVDS_N + return true +} + +proc update_PARAM_VALUE.DAC_CLK_EDGE_SEL { PARAM_VALUE.DAC_CLK_EDGE_SEL } { + # Procedure called to update DAC_CLK_EDGE_SEL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_CLK_EDGE_SEL { PARAM_VALUE.DAC_CLK_EDGE_SEL } { + # Procedure called to validate DAC_CLK_EDGE_SEL + return true +} + +proc update_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } { + # Procedure called to update DAC_DATAPATH_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } { + # Procedure called to validate DAC_DATAPATH_DISABLE + return true +} + +proc update_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } { + # Procedure called to update DAC_DDS_CORDIC_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } { + # Procedure called to validate DAC_DDS_CORDIC_DW + return true +} + +proc update_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } { + # Procedure called to update DAC_DDS_CORDIC_PHASE_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } { + # Procedure called to validate DAC_DDS_CORDIC_PHASE_DW + return true +} + +proc update_PARAM_VALUE.DAC_DDS_DISABLE { PARAM_VALUE.DAC_DDS_DISABLE } { + # Procedure called to update DAC_DDS_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_DDS_DISABLE { PARAM_VALUE.DAC_DDS_DISABLE } { + # Procedure called to validate DAC_DDS_DISABLE + return true +} + +proc update_PARAM_VALUE.DAC_DDS_PHASE_DW { PARAM_VALUE.DAC_DDS_PHASE_DW } { + # Procedure called to update DAC_DDS_PHASE_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_DDS_PHASE_DW { PARAM_VALUE.DAC_DDS_PHASE_DW } { + # Procedure called to validate DAC_DDS_PHASE_DW + return true +} + +proc update_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } { + # Procedure called to update DAC_DDS_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } { + # Procedure called to validate DAC_DDS_TYPE + return true +} + +proc update_PARAM_VALUE.DAC_INIT_DELAY { PARAM_VALUE.DAC_INIT_DELAY } { + # Procedure called to update DAC_INIT_DELAY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_INIT_DELAY { PARAM_VALUE.DAC_INIT_DELAY } { + # Procedure called to validate DAC_INIT_DELAY + return true +} + +proc update_PARAM_VALUE.DAC_IODELAY_ENABLE { PARAM_VALUE.DAC_IODELAY_ENABLE } { + # Procedure called to update DAC_IODELAY_ENABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_IODELAY_ENABLE { PARAM_VALUE.DAC_IODELAY_ENABLE } { + # Procedure called to validate DAC_IODELAY_ENABLE + return true +} + +proc update_PARAM_VALUE.DAC_IQCORRECTION_DISABLE { PARAM_VALUE.DAC_IQCORRECTION_DISABLE } { + # Procedure called to update DAC_IQCORRECTION_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_IQCORRECTION_DISABLE { PARAM_VALUE.DAC_IQCORRECTION_DISABLE } { + # Procedure called to validate DAC_IQCORRECTION_DISABLE + return true +} + +proc update_PARAM_VALUE.DAC_USERPORTS_DISABLE { PARAM_VALUE.DAC_USERPORTS_DISABLE } { + # Procedure called to update DAC_USERPORTS_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_USERPORTS_DISABLE { PARAM_VALUE.DAC_USERPORTS_DISABLE } { + # Procedure called to validate DAC_USERPORTS_DISABLE + return true +} + +proc update_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } { + # Procedure called to update DELAY_REFCLK_FREQUENCY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } { + # Procedure called to validate DELAY_REFCLK_FREQUENCY + return true +} + +proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to validate DEV_PACKAGE + return true +} + +proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to validate FPGA_FAMILY + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.IODELAY_CTRL { PARAM_VALUE.IODELAY_CTRL } { + # Procedure called to update IODELAY_CTRL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IODELAY_CTRL { PARAM_VALUE.IODELAY_CTRL } { + # Procedure called to validate IODELAY_CTRL + return true +} + +proc update_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to update IO_DELAY_GROUP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to validate IO_DELAY_GROUP + return true +} + +proc update_PARAM_VALUE.MIMO_ENABLE { PARAM_VALUE.MIMO_ENABLE } { + # Procedure called to update MIMO_ENABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.MIMO_ENABLE { PARAM_VALUE.MIMO_ENABLE } { + # Procedure called to validate MIMO_ENABLE + return true +} + +proc update_PARAM_VALUE.MODE_1R1T { PARAM_VALUE.MODE_1R1T } { + # Procedure called to update MODE_1R1T when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.MODE_1R1T { PARAM_VALUE.MODE_1R1T } { + # Procedure called to validate MODE_1R1T + return true +} + +proc update_PARAM_VALUE.PPS_RECEIVER_ENABLE { PARAM_VALUE.PPS_RECEIVER_ENABLE } { + # Procedure called to update PPS_RECEIVER_ENABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PPS_RECEIVER_ENABLE { PARAM_VALUE.PPS_RECEIVER_ENABLE } { + # Procedure called to validate PPS_RECEIVER_ENABLE + return true +} + +proc update_PARAM_VALUE.RX_NODPA { PARAM_VALUE.RX_NODPA } { + # Procedure called to update RX_NODPA when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RX_NODPA { PARAM_VALUE.RX_NODPA } { + # Procedure called to validate RX_NODPA + return true +} + +proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to validate SPEED_GRADE + return true +} + +proc update_PARAM_VALUE.TDD_DISABLE { PARAM_VALUE.TDD_DISABLE } { + # Procedure called to update TDD_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TDD_DISABLE { PARAM_VALUE.TDD_DISABLE } { + # Procedure called to validate TDD_DISABLE + return true +} + +proc update_PARAM_VALUE.USE_SSI_CLK { PARAM_VALUE.USE_SSI_CLK } { + # Procedure called to update USE_SSI_CLK when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.USE_SSI_CLK { PARAM_VALUE.USE_SSI_CLK } { + # Procedure called to validate USE_SSI_CLK + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.MODE_1R1T { MODELPARAM_VALUE.MODE_1R1T PARAM_VALUE.MODE_1R1T } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.MODE_1R1T}] ${MODELPARAM_VALUE.MODE_1R1T} +} + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY} +} + +proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE} +} + +proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE} +} + +proc update_MODELPARAM_VALUE.TDD_DISABLE { MODELPARAM_VALUE.TDD_DISABLE PARAM_VALUE.TDD_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TDD_DISABLE}] ${MODELPARAM_VALUE.TDD_DISABLE} +} + +proc update_MODELPARAM_VALUE.PPS_RECEIVER_ENABLE { MODELPARAM_VALUE.PPS_RECEIVER_ENABLE PARAM_VALUE.PPS_RECEIVER_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PPS_RECEIVER_ENABLE}] ${MODELPARAM_VALUE.PPS_RECEIVER_ENABLE} +} + +proc update_MODELPARAM_VALUE.CMOS_OR_LVDS_N { MODELPARAM_VALUE.CMOS_OR_LVDS_N PARAM_VALUE.CMOS_OR_LVDS_N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CMOS_OR_LVDS_N}] ${MODELPARAM_VALUE.CMOS_OR_LVDS_N} +} + +proc update_MODELPARAM_VALUE.ADC_INIT_DELAY { MODELPARAM_VALUE.ADC_INIT_DELAY PARAM_VALUE.ADC_INIT_DELAY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADC_INIT_DELAY}] ${MODELPARAM_VALUE.ADC_INIT_DELAY} +} + +proc update_MODELPARAM_VALUE.ADC_DATAPATH_DISABLE { MODELPARAM_VALUE.ADC_DATAPATH_DISABLE PARAM_VALUE.ADC_DATAPATH_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADC_DATAPATH_DISABLE}] ${MODELPARAM_VALUE.ADC_DATAPATH_DISABLE} +} + +proc update_MODELPARAM_VALUE.ADC_USERPORTS_DISABLE { MODELPARAM_VALUE.ADC_USERPORTS_DISABLE PARAM_VALUE.ADC_USERPORTS_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADC_USERPORTS_DISABLE}] ${MODELPARAM_VALUE.ADC_USERPORTS_DISABLE} +} + +proc update_MODELPARAM_VALUE.ADC_DATAFORMAT_DISABLE { MODELPARAM_VALUE.ADC_DATAFORMAT_DISABLE PARAM_VALUE.ADC_DATAFORMAT_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADC_DATAFORMAT_DISABLE}] ${MODELPARAM_VALUE.ADC_DATAFORMAT_DISABLE} +} + +proc update_MODELPARAM_VALUE.ADC_DCFILTER_DISABLE { MODELPARAM_VALUE.ADC_DCFILTER_DISABLE PARAM_VALUE.ADC_DCFILTER_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADC_DCFILTER_DISABLE}] ${MODELPARAM_VALUE.ADC_DCFILTER_DISABLE} +} + +proc update_MODELPARAM_VALUE.ADC_IQCORRECTION_DISABLE { MODELPARAM_VALUE.ADC_IQCORRECTION_DISABLE PARAM_VALUE.ADC_IQCORRECTION_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADC_IQCORRECTION_DISABLE}] ${MODELPARAM_VALUE.ADC_IQCORRECTION_DISABLE} +} + +proc update_MODELPARAM_VALUE.DAC_INIT_DELAY { MODELPARAM_VALUE.DAC_INIT_DELAY PARAM_VALUE.DAC_INIT_DELAY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_INIT_DELAY}] ${MODELPARAM_VALUE.DAC_INIT_DELAY} +} + +proc update_MODELPARAM_VALUE.DAC_CLK_EDGE_SEL { MODELPARAM_VALUE.DAC_CLK_EDGE_SEL PARAM_VALUE.DAC_CLK_EDGE_SEL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_CLK_EDGE_SEL}] ${MODELPARAM_VALUE.DAC_CLK_EDGE_SEL} +} + +proc update_MODELPARAM_VALUE.DAC_IODELAY_ENABLE { MODELPARAM_VALUE.DAC_IODELAY_ENABLE PARAM_VALUE.DAC_IODELAY_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_IODELAY_ENABLE}] ${MODELPARAM_VALUE.DAC_IODELAY_ENABLE} +} + +proc update_MODELPARAM_VALUE.DAC_DATAPATH_DISABLE { MODELPARAM_VALUE.DAC_DATAPATH_DISABLE PARAM_VALUE.DAC_DATAPATH_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_DATAPATH_DISABLE}] ${MODELPARAM_VALUE.DAC_DATAPATH_DISABLE} +} + +proc update_MODELPARAM_VALUE.DAC_DDS_DISABLE { MODELPARAM_VALUE.DAC_DDS_DISABLE PARAM_VALUE.DAC_DDS_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_DDS_DISABLE}] ${MODELPARAM_VALUE.DAC_DDS_DISABLE} +} + +proc update_MODELPARAM_VALUE.DAC_DDS_TYPE { MODELPARAM_VALUE.DAC_DDS_TYPE PARAM_VALUE.DAC_DDS_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_DDS_TYPE}] ${MODELPARAM_VALUE.DAC_DDS_TYPE} +} + +proc update_MODELPARAM_VALUE.DAC_DDS_PHASE_DW { MODELPARAM_VALUE.DAC_DDS_PHASE_DW PARAM_VALUE.DAC_DDS_PHASE_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_DDS_PHASE_DW}] ${MODELPARAM_VALUE.DAC_DDS_PHASE_DW} +} + +proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_DW PARAM_VALUE.DAC_DDS_CORDIC_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_DW} +} + +proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW} +} + +proc update_MODELPARAM_VALUE.DAC_USERPORTS_DISABLE { MODELPARAM_VALUE.DAC_USERPORTS_DISABLE PARAM_VALUE.DAC_USERPORTS_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_USERPORTS_DISABLE}] ${MODELPARAM_VALUE.DAC_USERPORTS_DISABLE} +} + +proc update_MODELPARAM_VALUE.DAC_IQCORRECTION_DISABLE { MODELPARAM_VALUE.DAC_IQCORRECTION_DISABLE PARAM_VALUE.DAC_IQCORRECTION_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_IQCORRECTION_DISABLE}] ${MODELPARAM_VALUE.DAC_IQCORRECTION_DISABLE} +} + +proc update_MODELPARAM_VALUE.IO_DELAY_GROUP { MODELPARAM_VALUE.IO_DELAY_GROUP PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IO_DELAY_GROUP}] ${MODELPARAM_VALUE.IO_DELAY_GROUP} +} + +proc update_MODELPARAM_VALUE.IODELAY_CTRL { MODELPARAM_VALUE.IODELAY_CTRL PARAM_VALUE.IODELAY_CTRL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IODELAY_CTRL}] ${MODELPARAM_VALUE.IODELAY_CTRL} +} + +proc update_MODELPARAM_VALUE.MIMO_ENABLE { MODELPARAM_VALUE.MIMO_ENABLE PARAM_VALUE.MIMO_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.MIMO_ENABLE}] ${MODELPARAM_VALUE.MIMO_ENABLE} +} + +proc update_MODELPARAM_VALUE.USE_SSI_CLK { MODELPARAM_VALUE.USE_SSI_CLK PARAM_VALUE.USE_SSI_CLK } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.USE_SSI_CLK}] ${MODELPARAM_VALUE.USE_SSI_CLK} +} + +proc update_MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY { MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY PARAM_VALUE.DELAY_REFCLK_FREQUENCY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DELAY_REFCLK_FREQUENCY}] ${MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY} +} + +proc update_MODELPARAM_VALUE.RX_NODPA { MODELPARAM_VALUE.RX_NODPA PARAM_VALUE.RX_NODPA } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RX_NODPA}] ${MODELPARAM_VALUE.RX_NODPA} +} + diff --git a/adi_library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v b/adi_library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v new file mode 100644 index 00000000..9e9f47b9 --- /dev/null +++ b/adi_library/axi_ad9361/xilinx/axi_ad9361_cmos_if.v @@ -0,0 +1,618 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9361_cmos_if #( + + parameter FPGA_TECHNOLOGY = 0, + parameter DAC_IODELAY_ENABLE = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group", + parameter IODELAY_CTRL = 1, + parameter CLK_DESKEW = 0, + parameter USE_SSI_CLK = 1, + parameter DELAY_REFCLK_FREQUENCY = 200 +) ( + + // physical interface (receive) + + input rx_clk_in, + input rx_frame_in, + input [11:0] rx_data_in, + + // physical interface (transmit) + + output tx_clk_out, + output tx_frame_out, + output [11:0] tx_data_out, + + // ensm control + + output enable, + output txnrx, + + // clock (common to both receive and transmit) + + input rst, + input clk, + output l_clk, + + // receive data path interface + + output adc_valid, + output [47:0] adc_data, + output adc_status, + input adc_r1_mode, + input adc_ddr_edgesel, + + // transmit data path interface + + input dac_valid, + input [47:0] dac_data, + input dac_clksel, + input dac_r1_mode, + + // tdd interface + + input tdd_enable, + input tdd_txnrx, + input tdd_mode, + + // delay interface + + input mmcm_rst, + input up_clk, + input up_rstn, + input up_enable, + input up_txnrx, + input [12:0] up_adc_dld, + input [64:0] up_adc_dwdata, + output [64:0] up_adc_drdata, + input [15:0] up_dac_dld, + input [79:0] up_dac_dwdata, + output [79:0] up_dac_drdata, + input delay_clk, + input delay_rst, + output delay_locked, + + // drp interface + + input up_drp_sel, + input up_drp_wr, + input [11:0] up_drp_addr, + input [31:0] up_drp_wdata, + output [31:0] up_drp_rdata, + output up_drp_ready, + output up_drp_locked +); + + // internal registers + + reg adc_r1_mode_n = 'd0; + reg rx_r1_mode = 'd0; + reg rx_locked_m1 = 'd0; + reg rx_locked = 'd0; + reg [ 1:0] rx_frame = 'd0; + reg [11:0] rx_data_1 = 'd0; + reg adc_valid_p = 'd0; + reg [47:0] adc_data_p = 'd0; + reg adc_status_p = 'd0; + reg adc_valid_n = 'd0; + reg [47:0] adc_data_n = 'd0; + reg adc_status_n = 'd0; + reg adc_valid_int = 'd0; + reg [47:0] adc_data_int = 'd0; + reg adc_status_int = 'd0; + reg [ 1:0] tx_clk_p = 'd0; + reg [ 1:0] tx_frame_p = 'd0; + reg [11:0] tx_data_0_p = 'd0; + reg [11:0] tx_data_1_p = 'd0; + reg [ 1:0] tx_clk_n = 'd0; + reg [ 1:0] tx_frame_n = 'd0; + reg [11:0] tx_data_0_n = 'd0; + reg [11:0] tx_data_1_n = 'd0; + reg [ 1:0] tx_clk = 'd0; + reg [ 1:0] tx_frame = 'd0; + reg [11:0] tx_data_0 = 'd0; + reg [11:0] tx_data_1 = 'd0; + reg up_enable_int = 'd0; + reg up_txnrx_int = 'd0; + reg enable_up_m1 = 'd0; + reg txnrx_up_m1 = 'd0; + reg enable_up = 'd0; + reg txnrx_up = 'd0; + reg enable_int = 'd0; + reg txnrx_int = 'd0; + reg enable_int_p = 'd0; + reg txnrx_int_p = 'd0; + + // internal signals + + wire [11:0] rx_data_1_s; + wire [11:0] rx_data_0_s; + wire [ 1:0] rx_frame_s; + wire locked_s; + + // drp interface signals + + assign up_drp_rdata = 32'd0; + assign up_drp_ready = 1'd0; + assign up_drp_locked = 1'd1; + + // r1mode + + generate if (CLK_DESKEW) begin + + reg adc_r1_mode_n = 'd0; + + always @(negedge clk) begin + adc_r1_mode_n <= adc_r1_mode; + end + + always @(posedge l_clk) begin + rx_r1_mode <= adc_r1_mode_n; + end + + end else begin /* CLK_DESKEW == 0 */ + + always @(posedge l_clk) begin + rx_r1_mode <= adc_r1_mode; + end + + end + endgenerate + + // adc-status + + assign delay_locked = locked_s; + + always @(posedge l_clk) begin + rx_locked_m1 <= locked_s; + rx_locked <= rx_locked_m1; + end + + // frame check + + always @(posedge l_clk) begin + if (rx_r1_mode == 1'd1) begin + rx_frame <= rx_frame_s; + end else begin + rx_frame <= ~rx_frame_s; + end + end + + // data hold + + always @(posedge l_clk) begin + rx_data_1 <= rx_data_1_s; + end + + // delineation + + always @(posedge l_clk) begin + case ({rx_r1_mode, rx_frame_s}) + 3'b011: begin + adc_valid_p <= 1'b0; + adc_data_p[47:24] <= 24'd0; + adc_data_p[23: 0] <= {rx_data_1_s, rx_data_0_s}; + end + 3'b000: begin + adc_valid_p <= 1'b1; + adc_data_p[47:24] <= {rx_data_1_s, rx_data_0_s}; + adc_data_p[23: 0] <= adc_data_p[23:0]; + end + 3'b001: begin + adc_valid_p <= 1'b0; + adc_data_p[47:24] <= 24'd0; + adc_data_p[23: 0] <= {rx_data_0_s, rx_data_1}; + end + 3'b010: begin + adc_valid_p <= 1'b1; + adc_data_p[47:24] <= {rx_data_0_s, rx_data_1}; + adc_data_p[23: 0] <= adc_data_p[23:0]; + end + 3'b110: begin + adc_valid_p <= 1'b1; + adc_data_p[47:24] <= 24'd0; + adc_data_p[23: 0] <= {rx_data_0_s, rx_data_1}; + end + 3'b101: begin + adc_valid_p <= 1'b1; + adc_data_p[47:24] <= 24'd0; + adc_data_p[23: 0] <= {rx_data_1_s, rx_data_0_s}; + end + default: begin + adc_valid_p <= 1'b0; + adc_data_p <= 48'd0; + end + endcase + end + + // adc-status + + always @(posedge l_clk) begin + if (rx_frame == rx_frame_s) begin + adc_status_p <= rx_locked; + end else begin + adc_status_p <= 1'b0; + end + end + + // transfer to common clock + + generate if (CLK_DESKEW) begin + + reg adc_valid_n = 'd0; + reg [47:0] adc_data_n = 'd0; + reg adc_status_n = 'd0; + + always @(negedge l_clk) begin + adc_valid_n <= adc_valid_p; + adc_data_n <= adc_data_p; + adc_status_n <= adc_status_p; + end + + always @(posedge clk) begin + adc_valid_int <= adc_valid_n; + adc_data_int <= adc_data_n; + adc_status_int <= adc_status_n; + end + + assign adc_valid = adc_valid_int; + assign adc_data = adc_data_int; + assign adc_status = adc_status_int; + + end else begin /* CLK_DESKEW == 0 */ + + always @(posedge clk) begin + adc_valid_int <= adc_valid_p; + adc_data_int <= adc_data_p; + adc_status_int <= adc_status_p; + end + + assign adc_valid = adc_valid_int; + assign adc_data = adc_data_int; + assign adc_status = adc_status_int; + + end + endgenerate + + // dac-tx interface + + always @(posedge clk) begin + tx_clk_p <= {~dac_clksel, dac_clksel}; + end + + always @(posedge clk) begin + case ({dac_r1_mode, dac_valid}) + 3'b00: begin + tx_frame_p <= 2'b00; + tx_data_0_p <= dac_data[35:24]; + tx_data_1_p <= dac_data[47:36]; + end + 2'b01: begin + tx_frame_p <= 2'b11; + tx_data_0_p <= dac_data[11:0]; + tx_data_1_p <= dac_data[23:12]; + end + 2'b11: begin + tx_frame_p <= 2'b01; + tx_data_0_p <= dac_data[11:0]; + tx_data_1_p <= dac_data[23:12]; + end + default: begin + tx_frame_p <= 2'd0; + tx_data_0_p <= 12'd0; + tx_data_1_p <= 12'd0; + end + endcase + end + + // transfer to local clock + + generate if (CLK_DESKEW) begin + + reg [ 1:0] tx_clk_n = 'd0; + reg tx_frame_n = 'd0; + reg [ 5:0] tx_data_0_n = 'd0; + reg [ 5:0] tx_data_1_n = 'd0; + + always @(negedge clk) begin + tx_clk_n <= tx_clk_p; + tx_frame_n <= tx_frame_p; + tx_data_0_n <= tx_data_0_p; + tx_data_1_n <= tx_data_1_p; + end + + always @(posedge l_clk) begin + tx_clk <= tx_clk_n; + tx_frame <= tx_frame_n; + tx_data_0 <= tx_data_0_n; + tx_data_1 <= tx_data_1_n; + end + + end else begin /* CLK_DESKEW == 0 */ + + always @(posedge l_clk) begin + tx_clk <= tx_clk_p; + tx_frame <= tx_frame_p; + tx_data_0 <= tx_data_0_p; + tx_data_1 <= tx_data_1_p; + end + + end + endgenerate + + // tdd/ensm control + + always @(posedge up_clk) begin + up_enable_int <= up_enable; + up_txnrx_int <= up_txnrx; + end + + always @(posedge clk or posedge rst) begin + if (rst == 1'b1) begin + enable_up_m1 <= 1'b0; + txnrx_up_m1 <= 1'b0; + enable_up <= 1'b0; + txnrx_up <= 1'b0; + end else begin + enable_up_m1 <= up_enable_int; + txnrx_up_m1 <= up_txnrx_int; + enable_up <= enable_up_m1; + txnrx_up <= txnrx_up_m1; + end + end + + always @(posedge clk) begin + if (tdd_mode == 1'b1) begin + enable_int <= tdd_enable; + txnrx_int <= tdd_txnrx; + end else begin + enable_int <= enable_up; + txnrx_int <= txnrx_up; + end + end + + generate if (CLK_DESKEW) begin + + reg enable_int_n = 'd0; + reg txnrx_int_n = 'd0; + + always @(negedge clk) begin + enable_int_n <= enable_int; + txnrx_int_n <= txnrx_int; + end + + always @(posedge l_clk) begin + enable_int_p <= enable_int_n; + txnrx_int_p <= txnrx_int_n; + end + + end else begin /* CLK_DESKEW == 0 */ + + always @(posedge l_clk) begin + enable_int_p <= enable_int; + txnrx_int_p <= txnrx_int; + end + + end + endgenerate + + // receive data interface, ibuf -> idelay -> iddr + + genvar i; + generate + for (i = 0; i < 12; i = i + 1) begin: g_rx_data + ad_data_in #( + .SINGLE_ENDED (1), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_rx_data ( + .rx_clk (l_clk), + .rx_data_in_p (rx_data_in[i]), + .rx_data_in_n (1'd0), + .rx_data_p (rx_data_1_s[i]), + .rx_data_n (rx_data_0_s[i]), + .up_clk (up_clk), + .up_dld (up_adc_dld[i]), + .up_dwdata (up_adc_dwdata[((i*5)+4):(i*5)]), + .up_drdata (up_adc_drdata[((i*5)+4):(i*5)]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + endgenerate + + // receive frame interface, ibuf -> idelay -> iddr + + ad_data_in #( + .SINGLE_ENDED (1), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_CTRL (IODELAY_CTRL), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_rx_frame ( + .rx_clk (l_clk), + .rx_data_in_p (rx_frame_in), + .rx_data_in_n (1'd0), + .rx_data_p (rx_frame_s[1]), + .rx_data_n (rx_frame_s[0]), + .up_clk (up_clk), + .up_dld (up_adc_dld[12]), + .up_dwdata (up_adc_dwdata[64:60]), + .up_drdata (up_adc_drdata[64:60]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (locked_s)); + + // transmit data interface, oddr -> obuf + + generate + for (i = 0; i < 12; i = i + 1) begin: g_tx_data + ad_data_out #( + .SINGLE_ENDED (1), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_tx_data ( + .tx_clk (l_clk), + .tx_data_p (tx_data_1[i]), + .tx_data_n (tx_data_0[i]), + .tx_data_out_p (tx_data_out[i]), + .tx_data_out_n (), + .up_clk (up_clk), + .up_dld (up_dac_dld[i]), + .up_dwdata (up_dac_dwdata[((i*5)+4):(i*5)]), + .up_drdata (up_dac_drdata[((i*5)+4):(i*5)]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + endgenerate + + // transmit frame interface, oddr -> obuf + + ad_data_out #( + .SINGLE_ENDED (1), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_tx_frame ( + .tx_clk (l_clk), + .tx_data_p (tx_frame[1]), + .tx_data_n (tx_frame[0]), + .tx_data_out_p (tx_frame_out), + .tx_data_out_n (), + .up_clk (up_clk), + .up_dld (up_dac_dld[12]), + .up_dwdata (up_dac_dwdata[64:60]), + .up_drdata (up_dac_drdata[64:60]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + // transmit clock interface, oddr -> obuf + + ad_data_out #( + .SINGLE_ENDED (1), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_tx_clk ( + .tx_clk (l_clk), + .tx_data_p (tx_clk[1]), + .tx_data_n (tx_clk[0]), + .tx_data_out_p (tx_clk_out), + .tx_data_out_n (), + .up_clk (up_clk), + .up_dld (up_dac_dld[13]), + .up_dwdata (up_dac_dwdata[69:65]), + .up_drdata (up_dac_drdata[69:65]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + // enable, oddr -> obuf + + ad_data_out #( + .SINGLE_ENDED (1), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_enable ( + .tx_clk (l_clk), + .tx_data_p (enable_int_p), + .tx_data_n (enable_int_p), + .tx_data_out_p (enable), + .tx_data_out_n (), + .up_clk (up_clk), + .up_dld (up_dac_dld[14]), + .up_dwdata (up_dac_dwdata[74:70]), + .up_drdata (up_dac_drdata[74:70]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + // txnrx, oddr -> obuf + + ad_data_out #( + .SINGLE_ENDED (1), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_txnrx ( + .tx_clk (l_clk), + .tx_data_p (txnrx_int_p), + .tx_data_n (txnrx_int_p), + .tx_data_out_p (txnrx), + .tx_data_out_n (), + .up_clk (up_clk), + .up_dld (up_dac_dld[15]), + .up_dwdata (up_dac_dwdata[79:75]), + .up_drdata (up_dac_drdata[79:75]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + // device clock interface (receive clock) + + generate if (USE_SSI_CLK == 1) begin + ad_data_clk #( + .SINGLE_ENDED (1) + ) i_clk ( + .rst (1'd0), + .locked (), + .clk_in_p (rx_clk_in), + .clk_in_n (1'd0), + .clk (l_clk)); + end else begin + assign l_clk = clk; + end + endgenerate + +endmodule diff --git a/adi_library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v b/adi_library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v new file mode 100644 index 00000000..ee5ca7ce --- /dev/null +++ b/adi_library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v @@ -0,0 +1,625 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9361_lvds_if #( + + parameter FPGA_TECHNOLOGY = 0, + parameter DAC_IODELAY_ENABLE = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group", + parameter IODELAY_CTRL = 1, + parameter CLK_DESKEW = 0, + parameter USE_SSI_CLK = 1, + parameter DELAY_REFCLK_FREQUENCY = 200, + parameter RX_NODPA = 0 +) ( + + // physical interface (receive) + + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + + // physical interface (transmit) + + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, + + // ensm control + + output enable, + output txnrx, + + // clock (common to both receive and transmit) + + input rst, + input clk, + output l_clk, + + // receive data path interface + + output adc_valid, + output [47:0] adc_data, + output adc_status, + input adc_r1_mode, + input adc_ddr_edgesel, + + // transmit data path interface + + input dac_valid, + input [47:0] dac_data, + input dac_clksel, + input dac_r1_mode, + + // tdd interface + + input tdd_enable, + input tdd_txnrx, + input tdd_mode, + + // delay interface + + input mmcm_rst, + input up_clk, + input up_rstn, + input up_enable, + input up_txnrx, + input [ 6:0] up_adc_dld, + input [34:0] up_adc_dwdata, + output [34:0] up_adc_drdata, + input [ 9:0] up_dac_dld, + input [49:0] up_dac_dwdata, + output [49:0] up_dac_drdata, + input delay_clk, + input delay_rst, + output delay_locked, + + // drp interface + + input up_drp_sel, + input up_drp_wr, + input [11:0] up_drp_addr, + input [31:0] up_drp_wdata, + output [31:0] up_drp_rdata, + output up_drp_ready, + output up_drp_locked +); + + // internal registers + + reg rx_r1_mode = 'd0; + reg rx_locked_m1 = 'd0; + reg rx_locked = 'd0; + reg [ 1:0] rx_frame = 'd0; + reg [ 5:0] rx_data_1 = 'd0; + reg [ 5:0] rx_data_0 = 'd0; + reg adc_valid_p = 'd0; + reg [47:0] adc_data_p = 'd0; + reg adc_status_p = 'd0; + reg adc_valid_int = 'd0; + reg [47:0] adc_data_int = 'd0; + reg adc_status_int = 'd0; + reg [ 1:0] tx_data_sel = 'd0; + reg [47:0] tx_data = 'd0; + reg [ 1:0] tx_clk_p = 'd0; + reg tx_frame_p = 'd0; + reg [ 5:0] tx_data_0_p = 'd0; + reg [ 5:0] tx_data_1_p = 'd0; + reg [ 1:0] tx_clk = 'd0; + reg tx_frame = 'd0; + reg [ 5:0] tx_data_0 = 'd0; + reg [ 5:0] tx_data_1 = 'd0; + reg up_enable_int = 'd0; + reg up_txnrx_int = 'd0; + reg enable_up_m1 = 'd0; + reg txnrx_up_m1 = 'd0; + reg enable_up = 'd0; + reg txnrx_up = 'd0; + reg enable_int = 'd0; + reg txnrx_int = 'd0; + reg enable_int_p = 'd0; + reg txnrx_int_p = 'd0; + + // internal signals + + wire [ 5:0] rx_data_1_s; + wire [ 5:0] rx_data_0_s; + wire [ 1:0] rx_frame_s; + wire locked_s; + + // drp interface signals + + assign up_drp_rdata = 32'd0; + assign up_drp_ready = 1'd0; + assign up_drp_locked = 1'd1; + + // r1mode + + generate if (CLK_DESKEW) begin + + reg adc_r1_mode_n = 'd0; + + always @(negedge clk) begin + adc_r1_mode_n <= adc_r1_mode; + end + + always @(posedge l_clk) begin + rx_r1_mode <= adc_r1_mode_n; + end + + end else begin /* CLK_DESKEW == 0 */ + + always @(posedge l_clk) begin + rx_r1_mode <= adc_r1_mode; + end + + end + endgenerate + + // adc-status + + assign delay_locked = locked_s; + + always @(posedge l_clk) begin + rx_locked_m1 <= locked_s; + rx_locked <= rx_locked_m1; + end + + // intel-equivalence + + always @(posedge l_clk) begin + rx_frame <= rx_frame_s; + rx_data_1 <= rx_data_1_s; + rx_data_0 <= rx_data_0_s; + end + + // frame check + + // delineation + reg rx_error_r1 = 'd0; + reg rx_error_r2 = 'd0; + + always @(posedge l_clk) begin + rx_error_r1 <= ~((rx_frame_s == 4'b1100) || (rx_frame_s == 4'b0011)); + rx_error_r2 <= ~((rx_frame_s == 4'b1111) || (rx_frame_s == 4'b1100) || + (rx_frame_s == 4'b0000) || (rx_frame_s == 4'b0011)); + end + + always @(posedge l_clk) begin + case ({rx_r1_mode, rx_frame_s, rx_frame}) + 5'b01111: begin + adc_valid_p <= 1'b0; + adc_data_p[23:12] <= {rx_data_1, rx_data_1_s}; + adc_data_p[11: 0] <= {rx_data_0, rx_data_0_s}; + end + 5'b00000: begin + adc_valid_p <= 1'b1; + adc_data_p[47:36] <= {rx_data_1, rx_data_1_s}; + adc_data_p[35:24] <= {rx_data_0, rx_data_0_s}; + end + 5'b10011: begin + adc_valid_p <= 1'b1; + adc_data_p[47:24] <= 24'd0; + adc_data_p[23:12] <= {rx_data_1, rx_data_1_s}; + adc_data_p[11: 0] <= {rx_data_0, rx_data_0_s}; + end + default: begin + adc_valid_p <= 1'b0; + end + endcase + end + + // adc-status + + always @(posedge l_clk) begin + if (adc_r1_mode == 1'b1) begin + adc_status_p <= ~rx_error_r1 & rx_locked; + end else begin + adc_status_p <= ~rx_error_r2 & rx_locked; + end + end + + // transfer to common clock + + generate if (CLK_DESKEW) begin + + reg adc_valid_n = 'd0; + reg [47:0] adc_data_n = 'd0; + reg adc_status_n = 'd0; + + always @(negedge l_clk) begin + adc_valid_n <= adc_valid_p; + adc_data_n <= adc_data_p; + adc_status_n <= adc_status_p; + end + + always @(posedge clk) begin + adc_valid_int <= adc_valid_n; + adc_data_int <= adc_data_n; + adc_status_int <= adc_status_n; + end + + assign adc_valid = adc_valid_int; + assign adc_data = adc_data_int; + assign adc_status = adc_status_int; + + end else begin /* CLK_DESKEW == 0 */ + + always @(posedge clk) begin + adc_valid_int <= adc_valid_p; + adc_data_int <= adc_data_p; + adc_status_int <= adc_status_p; + end + + assign adc_valid = adc_valid_int; + assign adc_data = adc_data_int; + assign adc_status = adc_status_int; + + end + endgenerate + + // dac-tx interface + + always @(posedge clk) begin + if (dac_valid == 1'b1) begin + tx_data_sel <= 2'b00; + end else begin + tx_data_sel <= tx_data_sel + 1'b1; + end + if (dac_valid == 1'b1) begin + tx_data <= dac_data; + end + end + + always @(posedge clk) begin + tx_clk_p <= {~dac_clksel, dac_clksel}; + end + + always @(posedge clk) begin + case ({dac_r1_mode, tx_data_sel}) + 3'b000: begin + tx_frame_p <= 1'b1; + tx_data_0_p <= tx_data[11:6]; + tx_data_1_p <= tx_data[23:18]; + end + 3'b001: begin + tx_frame_p <= 1'b1; + tx_data_0_p <= tx_data[5:0]; + tx_data_1_p <= tx_data[17:12]; + end + 3'b010: begin + tx_frame_p <= 1'b0; + tx_data_0_p <= tx_data[35:30]; + tx_data_1_p <= tx_data[47:42]; + end + 3'b011: begin + tx_frame_p <= 1'b0; + tx_data_0_p <= tx_data[29:24]; + tx_data_1_p <= tx_data[41:36]; + end + 3'b100: begin + tx_frame_p <= 1'b1; + tx_data_0_p <= tx_data[11:6]; + tx_data_1_p <= tx_data[23:18]; + end + 3'b101: begin + tx_frame_p <= 1'b0; + tx_data_0_p <= tx_data[5:0]; + tx_data_1_p <= tx_data[17:12]; + end + default: begin + tx_frame_p <= 1'b0; + tx_data_0_p <= 6'd0; + tx_data_1_p <= 6'd0; + end + endcase + end + + // transfer to local clock + + generate if (CLK_DESKEW) begin + + reg [ 1:0] tx_clk_n = 'd0; + reg tx_frame_n = 'd0; + reg [ 5:0] tx_data_0_n = 'd0; + reg [ 5:0] tx_data_1_n = 'd0; + + always @(negedge clk) begin + tx_clk_n <= tx_clk_p; + tx_frame_n <= tx_frame_p; + tx_data_0_n <= tx_data_0_p; + tx_data_1_n <= tx_data_1_p; + end + + always @(posedge l_clk) begin + tx_clk <= tx_clk_n; + tx_frame <= tx_frame_n; + tx_data_0 <= tx_data_0_n; + tx_data_1 <= tx_data_1_n; + end + + end else begin /* CLK_DESKEW == 0 */ + + always @(posedge l_clk) begin + tx_clk <= tx_clk_p; + tx_frame <= tx_frame_p; + tx_data_0 <= tx_data_0_p; + tx_data_1 <= tx_data_1_p; + end + + end + endgenerate + + // tdd/ensm control + + always @(posedge up_clk) begin + up_enable_int <= up_enable; + up_txnrx_int <= up_txnrx; + end + + always @(posedge clk or posedge rst) begin + if (rst == 1'b1) begin + enable_up_m1 <= 1'b0; + txnrx_up_m1 <= 1'b0; + enable_up <= 1'b0; + txnrx_up <= 1'b0; + end else begin + enable_up_m1 <= up_enable_int; + txnrx_up_m1 <= up_txnrx_int; + enable_up <= enable_up_m1; + txnrx_up <= txnrx_up_m1; + end + end + + always @(posedge clk) begin + if (tdd_mode == 1'b1) begin + enable_int <= tdd_enable; + txnrx_int <= tdd_txnrx; + end else begin + enable_int <= enable_up; + txnrx_int <= txnrx_up; + end + end + + generate if (CLK_DESKEW) begin + + reg enable_int_n = 'd0; + reg txnrx_int_n = 'd0; + + always @(negedge clk) begin + enable_int_n <= enable_int; + txnrx_int_n <= txnrx_int; + end + + always @(posedge l_clk) begin + enable_int_p <= enable_int_n; + txnrx_int_p <= txnrx_int_n; + end + + end else begin /* CLK_DESKEW == 0 */ + + always @(posedge l_clk) begin + enable_int_p <= enable_int; + txnrx_int_p <= txnrx_int; + end + + end + endgenerate + + // receive data interface, ibuf -> idelay -> iddr + + genvar i; + generate + for (i = 0; i < 6; i = i + 1) begin: g_rx_data + ad_data_in #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_rx_data ( + .rx_clk (l_clk), + .rx_data_in_p (rx_data_in_p[i]), + .rx_data_in_n (rx_data_in_n[i]), + .rx_data_p (rx_data_1_s[i]), + .rx_data_n (rx_data_0_s[i]), + .up_clk (up_clk), + .up_dld (up_adc_dld[i]), + .up_dwdata (up_adc_dwdata[((i*5)+4):(i*5)]), + .up_drdata (up_adc_drdata[((i*5)+4):(i*5)]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + endgenerate + + // receive frame interface, ibuf -> idelay -> iddr + + ad_data_in #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_CTRL (IODELAY_CTRL), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_rx_frame ( + .rx_clk (l_clk), + .rx_data_in_p (rx_frame_in_p), + .rx_data_in_n (rx_frame_in_n), + .rx_data_p (rx_frame_s[1]), + .rx_data_n (rx_frame_s[0]), + .up_clk (up_clk), + .up_dld (up_adc_dld[6]), + .up_dwdata (up_adc_dwdata[34:30]), + .up_drdata (up_adc_drdata[34:30]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (locked_s)); + + // transmit data interface, oddr -> obuf + + generate + for (i = 0; i < 6; i = i + 1) begin: g_tx_data + ad_data_out #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_tx_data ( + .tx_clk (l_clk), + .tx_data_p (tx_data_1[i]), + .tx_data_n (tx_data_0[i]), + .tx_data_out_p (tx_data_out_p[i]), + .tx_data_out_n (tx_data_out_n[i]), + .up_clk (up_clk), + .up_dld (up_dac_dld[i]), + .up_dwdata (up_dac_dwdata[((i*5)+4):(i*5)]), + .up_drdata (up_dac_drdata[((i*5)+4):(i*5)]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + endgenerate + + // transmit frame interface, oddr -> obuf + + ad_data_out #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_tx_frame ( + .tx_clk (l_clk), + .tx_data_p (tx_frame), + .tx_data_n (tx_frame), + .tx_data_out_p (tx_frame_out_p), + .tx_data_out_n (tx_frame_out_n), + .up_clk (up_clk), + .up_dld (up_dac_dld[6]), + .up_dwdata (up_dac_dwdata[34:30]), + .up_drdata (up_dac_drdata[34:30]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + // transmit clock interface, oddr -> obuf + + ad_data_out #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_tx_clk ( + .tx_clk (l_clk), + .tx_data_p (tx_clk[1]), + .tx_data_n (tx_clk[0]), + .tx_data_out_p (tx_clk_out_p), + .tx_data_out_n (tx_clk_out_n), + .up_clk (up_clk), + .up_dld (up_dac_dld[7]), + .up_dwdata (up_dac_dwdata[39:35]), + .up_drdata (up_dac_drdata[39:35]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + // enable, oddr -> obuf + + ad_data_out #( + .SINGLE_ENDED (1), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_enable ( + .tx_clk (l_clk), + .tx_data_p (enable_int_p), + .tx_data_n (enable_int_p), + .tx_data_out_p (enable), + .tx_data_out_n (), + .up_clk (up_clk), + .up_dld (up_dac_dld[8]), + .up_dwdata (up_dac_dwdata[44:40]), + .up_drdata (up_dac_drdata[44:40]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + // txnrx, oddr -> obuf + + ad_data_out #( + .SINGLE_ENDED (1), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_ENABLE (DAC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_txnrx ( + .tx_clk (l_clk), + .tx_data_p (txnrx_int_p), + .tx_data_n (txnrx_int_p), + .tx_data_out_p (txnrx), + .tx_data_out_n (), + .up_clk (up_clk), + .up_dld (up_dac_dld[9]), + .up_dwdata (up_dac_dwdata[49:45]), + .up_drdata (up_dac_drdata[49:45]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + // device clock interface (receive clock) + generate if (USE_SSI_CLK == 1) begin + ad_data_clk i_clk ( + .rst (1'd0), + .locked (), + .clk_in_p (rx_clk_in_p), + .clk_in_n (rx_clk_in_n), + .clk (l_clk)); + end else begin + assign l_clk = clk; + end + endgenerate + +endmodule diff --git a/adi_library/axi_ad9434/Makefile b/adi_library/axi_ad9434/Makefile new file mode 100644 index 00000000..d147e9a3 --- /dev/null +++ b/adi_library/axi_ad9434/Makefile @@ -0,0 +1,34 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_ad9434 + +GENERIC_DEPS += ../common/ad_datafmt.v +GENERIC_DEPS += ../common/ad_pnmon.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_adc_channel.v +GENERIC_DEPS += ../common/up_adc_common.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_delay_cntrl.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_ad9434.v +GENERIC_DEPS += axi_ad9434_core.v +GENERIC_DEPS += axi_ad9434_if.v +GENERIC_DEPS += axi_ad9434_pnmon.v + +XILINX_DEPS += ../xilinx/common/ad_mmcm_drp.v +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/ad_serdes_clk.v +XILINX_DEPS += ../xilinx/common/ad_serdes_in.v +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_ad9434_constr.xdc +XILINX_DEPS += axi_ad9434_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_ad9434/axi_ad9434.v b/adi_library/axi_ad9434/axi_ad9434.v new file mode 100644 index 00000000..cb3da79a --- /dev/null +++ b/adi_library/axi_ad9434/axi_ad9434.v @@ -0,0 +1,239 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9434 #( + + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter IODELAY_ENABLE = 1, + parameter IO_DELAY_GROUP = "dev_if_delay_group" +) ( + + // physical interface + input adc_clk_in_p, + input adc_clk_in_n, + input [11:0] adc_data_in_p, + input [11:0] adc_data_in_n, + input adc_or_in_p, + input adc_or_in_n, + + // delay interface + input delay_clk, + + // dma interface + output adc_clk, + output adc_enable, + output adc_valid, + output [63:0] adc_data, + input adc_dovf, + + // axi interface + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot +); + + // internal clocks & resets + wire adc_rst; + wire up_rstn; + wire mmcm_rst; + wire up_clk; + + // internal signals + wire up_wreq_s; + wire up_rreq_s; + wire [13:0] up_waddr_s; + wire [13:0] up_raddr_s; + wire [31:0] up_wdata_s; + wire [31:0] up_rdata_s; + wire up_wack_s; + wire up_rack_s; + + wire [ 1:0] up_status_pn_err_s; + wire [ 1:0] up_status_pn_oos_s; + wire [ 1:0] up_status_or_s; + wire adc_status_s; + + wire [12:0] up_dld_s; + wire [64:0] up_dwdata_s; + wire [64:0] up_drdata_s; + wire delay_clk_s; + wire delay_rst; + wire delay_locked_s; + + wire up_drp_sel_s; + wire up_drp_wr_s; + wire [11:0] up_drp_addr_s; + wire [31:0] up_drp_wdata_s; + wire [31:0] up_drp_rdata_s; + wire up_drp_ready_s; + wire up_drp_locked_s; + + wire [47:0] adc_data_if_s; + wire adc_or_if_s; + + // clock/reset assignments + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + axi_ad9434_if #( + .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), + .IODELAY_ENABLE (IODELAY_ENABLE), + .IO_DELAY_GROUP(IO_DELAY_GROUP) + ) i_if ( + .adc_clk_in_p(adc_clk_in_p), + .adc_clk_in_n(adc_clk_in_n), + .adc_data_in_p(adc_data_in_p), + .adc_data_in_n(adc_data_in_n), + .adc_or_in_p(adc_or_in_p), + .adc_or_in_n(adc_or_in_n), + .adc_data(adc_data_if_s), + .adc_or(adc_or_if_s), + .adc_clk(adc_clk), + .adc_rst(adc_rst), + .adc_status(adc_status_s), + .up_clk (up_clk), + .up_adc_dld (up_dld_s), + .up_adc_dwdata (up_dwdata_s), + .up_adc_drdata (up_drdata_s), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s), + .mmcm_rst(mmcm_rst), + .up_rstn(up_rstn), + .up_drp_sel(up_drp_sel_s), + .up_drp_wr(up_drp_wr_s), + .up_drp_addr(up_drp_addr_s), + .up_drp_wdata(up_drp_wdata_s), + .up_drp_rdata(up_drp_rdata_s), + .up_drp_ready(up_drp_ready_s), + .up_drp_locked(up_drp_locked_s)); + + // common processor control + axi_ad9434_core #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE) + ) i_core ( + .adc_clk(adc_clk), + .adc_data(adc_data_if_s), + .adc_or(adc_or_if_s), + .mmcm_rst (mmcm_rst), + .adc_rst (adc_rst), + .adc_enable(adc_enable), + .adc_status (adc_status_s), + .dma_dvalid (adc_valid), + .dma_data (adc_data), + .dma_dovf (adc_dovf), + .up_dld (up_dld_s), + .up_dwdata (up_dwdata_s), + .up_drdata (up_drdata_s), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s), + .up_drp_sel (up_drp_sel_s), + .up_drp_wr (up_drp_wr_s), + .up_drp_addr (up_drp_addr_s), + .up_drp_wdata (up_drp_wdata_s), + .up_drp_rdata (up_drp_rdata_s), + .up_drp_ready (up_drp_ready_s), + .up_drp_locked (up_drp_locked_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + + // up bus interface + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata_s), + .up_wack (up_wack_s), + .up_raddr (up_raddr_s), + .up_rreq (up_rreq_s), + .up_rack (up_rack_s)); + +endmodule diff --git a/adi_library/axi_ad9434/axi_ad9434.xpr b/adi_library/axi_ad9434/axi_ad9434.xpr new file mode 100644 index 00000000..d6209d34 --- /dev/null +++ b/adi_library/axi_ad9434/axi_ad9434.xpr @@ -0,0 +1,548 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_ad9434/axi_ad9434_constr.xdc b/adi_library/axi_ad9434/axi_ad9434_constr.xdc new file mode 100644 index 00000000..e1ba0686 --- /dev/null +++ b/adi_library/axi_ad9434/axi_ad9434_constr.xdc @@ -0,0 +1,7 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_false_path -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}] -to \ +[get_cells -hier -filter {name =~ *adc_status_m1_reg && IS_SEQUENTIAL}] diff --git a/adi_library/axi_ad9434/axi_ad9434_core.v b/adi_library/axi_ad9434/axi_ad9434_core.v new file mode 100644 index 00000000..7132f74e --- /dev/null +++ b/adi_library/axi_ad9434/axi_ad9434_core.v @@ -0,0 +1,308 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9434_core #( + + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0 +) ( + + // device interface + + input adc_clk, + input [47:0] adc_data, + input adc_or, + + // dma interface + + output dma_dvalid, + output [63:0] dma_data, + input dma_dovf, + + // drp interface + + output up_drp_sel, + output up_drp_wr, + output [11:0] up_drp_addr, + output [31:0] up_drp_wdata, + input [31:0] up_drp_rdata, + input up_drp_ready, + input up_drp_locked, + + // delay interface + + output [12:0] up_dld, + output [64:0] up_dwdata, + input [64:0] up_drdata, + input delay_clk, + output delay_rst, + input delay_locked, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack, + + // status and control signals + + output mmcm_rst, + output adc_rst, + output adc_enable, + input adc_status +); + + // internal signals + wire up_status_pn_err_s; + wire up_status_pn_oos_s; + wire up_status_or_s; + + wire adc_dfmt_se_s; + wire adc_dfmt_type_s; + wire adc_dfmt_enable_s; + + wire [ 3:0] adc_pnseq_sel_s; + wire adc_pn_err_s; + wire adc_pn_oos_s; + + wire up_wack_s[0:2]; + wire [31:0] up_rdata_s[0:2]; + wire up_rack_s[0:2]; + + // instantiations + axi_ad9434_pnmon i_pnmon ( + .adc_clk (adc_clk), + .adc_data (adc_data), + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_pn_err (adc_pn_err_s), + .adc_pn_oos (adc_pn_oos_s)); + + genvar n; + generate + for (n = 0; n < 4; n = n + 1) begin: g_ad_dfmt + ad_datafmt #( + .DATA_WIDTH(12) + ) i_datafmt ( + .clk (adc_clk), + .valid (1'b1), + .data (adc_data[n*12+11:n*12]), + .valid_out (dma_dvalid), + .data_out (dma_data[n*16+15:n*16]), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + end + endgenerate + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2]; + up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2]; + up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2]; + end + end + + up_adc_common #( + .ID(ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .CONFIG(0), + .COMMON_ID(0), + .DRP_DISABLE(0), + .USERPORTS_DISABLE(1), + .GPIO_DISABLE(1), + .START_CODE_DISABLE(1) + ) i_adc_common( + .mmcm_rst (mmcm_rst), + + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (adc_status), + .adc_sync_status (1'd0), + .adc_status_ovf (dma_dovf), + .adc_clk_ratio (32'd4), + .adc_start_code (), + .adc_sref_sync (), + .adc_ext_sync_arm (), + .adc_ext_sync_disarm (), + .adc_ext_sync_manual_req (), + .adc_num_lanes (), + .adc_custom_control (), + .adc_crc_enable (), + .adc_sdr_ddr_n (), + .adc_symb_op (), + .adc_symb_8_16b (), + .adc_sync (), + + .up_pps_rcounter(32'h0), + .up_adc_r1_mode (), + .up_pps_status(1'b0), + .up_pps_irq_mask(), + + .up_adc_ce (), + .up_status_pn_err (up_status_pn_err_s), + .up_status_pn_oos (up_status_pn_oos_s), + .up_status_or (up_status_or_s), + + .up_drp_sel (up_drp_sel), + .up_drp_wr (up_drp_wr), + .up_drp_addr (up_drp_addr), + .adc_config_wr (), + .adc_config_ctrl (), + .adc_config_rd ('d0), + .adc_ctrl_status ('d0), + .up_drp_wdata (up_drp_wdata), + .up_drp_rdata (up_drp_rdata), + .up_drp_ready (up_drp_ready), + .up_drp_locked (up_drp_locked), + + .up_usr_chanmax_out (), + .up_usr_chanmax_in (8'd0), + .up_adc_gpio_in (32'd0), + .up_adc_gpio_out (), + + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + up_adc_channel #( + .CHANNEL_ID(0), + .USERPORTS_DISABLE(1), + .DATAFORMAT_DISABLE(0), + .DCFILTER_DISABLE(1), + .IQCORRECTION_DISABLE(1) + ) i_adc_channel( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (), + .adc_dcfilt_enb (), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_dcfilt_offset (), + .adc_dcfilt_coeff (), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_data_sel (), + .adc_pn_err (adc_pn_err_s), + .adc_pn_oos (adc_pn_oos_s), + .adc_or (adc_or), + .adc_read_data ('d0), + .adc_status_header ('d0), + .adc_crc_err ('d0), + .up_adc_pn_err (up_status_pn_err_s), + .up_adc_pn_oos (up_status_pn_oos_s), + .up_adc_or (up_status_or_s), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // adc delay control + + up_delay_cntrl #( + .DATA_WIDTH(13), + .BASE_ADDRESS(6'h02) + ) i_delay_cntrl ( + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked), + .up_dld (up_dld), + .up_dwdata (up_dwdata), + .up_drdata (up_drdata), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + +endmodule diff --git a/adi_library/axi_ad9434/axi_ad9434_if.v b/adi_library/axi_ad9434/axi_ad9434_if.v new file mode 100644 index 00000000..b27e5990 --- /dev/null +++ b/adi_library/axi_ad9434/axi_ad9434_if.v @@ -0,0 +1,207 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9434_if #( + + parameter FPGA_TECHNOLOGY = 0, + parameter IODELAY_ENABLE = 1, + parameter IO_DELAY_GROUP = "dev_if_delay_group" +) ( + + // device interface + input adc_clk_in_p, + input adc_clk_in_n, + input [11:0] adc_data_in_p, + input [11:0] adc_data_in_n, + input adc_or_in_p, + input adc_or_in_n, + + // interface outputs + output [47:0] adc_data, + output adc_or, + + // internl reset and clocks + output adc_clk, + input adc_rst, + output reg adc_status, + + // delay interface (for IDELAY macros) + input up_clk, + input [12:0] up_adc_dld, + input [64:0] up_adc_dwdata, + output [64:0] up_adc_drdata, + input delay_clk, + input delay_rst, + output delay_locked, + + // mmcm reset + input mmcm_rst, + + // drp interface for MMCM_OR_BUFR_N + input up_rstn, + input up_drp_sel, + input up_drp_wr, + input [11:0] up_drp_addr, + input [31:0] up_drp_wdata, + output [31:0] up_drp_rdata, + output up_drp_ready, + output up_drp_locked +); + + localparam SDR = 0; + + // internal registers + + reg adc_status_m1 = 'd0; + + // internal signals + + wire [3:0] adc_or_s; + + wire adc_clk_in; + wire adc_div_clk; + + genvar l_inst; + + // output assignment for adc clock (1:4 of the sampling clock) + assign adc_clk = adc_div_clk; + + // data interface + ad_serdes_in #( + .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), + .IODELAY_ENABLE (IODELAY_ENABLE), + .IODELAY_CTRL(0), + .IODELAY_GROUP(IO_DELAY_GROUP), + .DDR_OR_SDR_N(SDR), + .DATA_WIDTH(12), + .SERDES_FACTOR(4) + ) i_adc_data ( + .rst(adc_rst), + .clk(adc_clk_in), + .div_clk(adc_div_clk), + .data_s0(adc_data[47:36]), + .data_s1(adc_data[35:24]), + .data_s2(adc_data[23:12]), + .data_s3(adc_data[11: 0]), + .data_s4(), + .data_s5(), + .data_s6(), + .data_s7(), + .data_in_p(adc_data_in_p), + .data_in_n(adc_data_in_n), + .up_clk (up_clk), + .up_dld (up_adc_dld[11:0]), + .up_dwdata (up_adc_dwdata[59:0]), + .up_drdata (up_adc_drdata[59:0]), + .delay_clk(delay_clk), + .delay_rst(delay_rst), + .delay_locked()); + + // over-range interface + ad_serdes_in #( + .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), + .IODELAY_ENABLE (IODELAY_ENABLE), + .IODELAY_CTRL(1), + .IODELAY_GROUP(IO_DELAY_GROUP), + .DDR_OR_SDR_N(SDR), + .DATA_WIDTH(1), + .SERDES_FACTOR(4) + ) i_adc_or ( + .rst(adc_rst), + .clk(adc_clk_in), + .div_clk(adc_div_clk), + .data_s0(adc_or_s[3]), + .data_s1(adc_or_s[2]), + .data_s2(adc_or_s[1]), + .data_s3(adc_or_s[0]), + .data_s4(), + .data_s5(), + .data_s6(), + .data_s7(), + .data_in_p(adc_or_in_p), + .data_in_n(adc_or_in_n), + .up_clk (up_clk), + .up_dld (up_adc_dld[12]), + .up_dwdata (up_adc_dwdata[64:60]), + .up_drdata (up_adc_drdata[64:60]), + .delay_clk(delay_clk), + .delay_rst(delay_rst), + .delay_locked(delay_locked)); + + // clock input buffers and MMCM_OR_BUFR_N + ad_serdes_clk #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .CLKIN_DS_OR_SE_N (1), + .MMCM_OR_BUFR_N (1), + .MMCM_CLKIN_PERIOD (2), + .MMCM_VCO_DIV (6), + .MMCM_VCO_MUL (12), + .MMCM_CLK0_DIV (2), + .MMCM_CLK1_DIV (8), + .SERDES_FACTOR(4) + ) i_serdes_clk ( + .rst (mmcm_rst), + .clk_in_p (adc_clk_in_p), + .clk_in_n (adc_clk_in_n), + .clk (adc_clk_in), + .div_clk (adc_div_clk), + .out_clk (), + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_drp_sel (up_drp_sel), + .up_drp_wr (up_drp_wr), + .up_drp_addr (up_drp_addr), + .up_drp_wdata (up_drp_wdata), + .up_drp_rdata (up_drp_rdata), + .up_drp_ready (up_drp_ready), + .up_drp_locked (up_drp_locked)); + + // adc over range + assign adc_or = adc_or_s[0] | adc_or_s[1] | adc_or_s[2] | adc_or_s[3]; + + // adc status: adc is up, if both the MMCM_OR_BUFR_N and DELAY blocks are up + always @(posedge adc_div_clk) begin + if (adc_rst == 1'b1) begin + adc_status_m1 <= 1'b0; + adc_status <= 1'b0; + end else begin + adc_status_m1 <= up_drp_locked & delay_locked; + adc_status <= adc_status_m1; + end + end + +endmodule diff --git a/adi_library/axi_ad9434/axi_ad9434_ip.tcl b/adi_library/axi_ad9434/axi_ad9434_ip.tcl new file mode 100644 index 00000000..1fa37ee2 --- /dev/null +++ b/adi_library/axi_ad9434/axi_ad9434_ip.tcl @@ -0,0 +1,49 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_ad9434 +adi_ip_files axi_ad9434 [list \ + "$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_serdes_in.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "axi_ad9434_if.v" \ + "axi_ad9434_pnmon.v" \ + "axi_ad9434_core.v" \ + "axi_ad9434_constr.xdc" \ + "axi_ad9434.v" ] + +adi_ip_properties axi_ad9434 + +adi_init_bd_tcl +adi_ip_bd axi_ad9434 "bd/bd.tcl" + +set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] + +ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/axi_ad9434/axi_ad9434_pnmon.v b/adi_library/axi_ad9434/axi_ad9434_pnmon.v new file mode 100644 index 00000000..a7c645d0 --- /dev/null +++ b/adi_library/axi_ad9434/axi_ad9434_pnmon.v @@ -0,0 +1,195 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module axi_ad9434_pnmon ( + + // adc interface + input adc_clk, + input [47:0] adc_data, + + // pn interface + input [ 3:0] adc_pnseq_sel, + output adc_pn_err, + output adc_pn_oos +); + + // internal registers + reg [47:0] adc_pn_data_pn = 'd0; + + // internal signals + wire [47:0] adc_pn_data_pn_s; + + wire [47:0] adc_data_inv_s; + + // prbs pn9 function + function [47:0] pn9; + input [47:0] din; + reg [47:0] dout; + begin + dout[47] = din[8] ^ din[4]; + dout[46] = din[7] ^ din[3]; + dout[45] = din[6] ^ din[2]; + dout[44] = din[5] ^ din[1]; + dout[43] = din[4] ^ din[0]; + dout[42] = din[3] ^ din[8] ^ din[4]; + dout[41] = din[2] ^ din[7] ^ din[3]; + dout[40] = din[1] ^ din[6] ^ din[2]; + dout[39] = din[0] ^ din[5] ^ din[1]; + dout[38] = din[8] ^ din[0]; + dout[37] = din[7] ^ din[8] ^ din[4]; + dout[36] = din[6] ^ din[7] ^ din[3]; + dout[35] = din[5] ^ din[6] ^ din[2]; + dout[34] = din[4] ^ din[5] ^ din[1]; + dout[33] = din[3] ^ din[4] ^ din[0]; + dout[32] = din[2] ^ din[3] ^ din[8] ^ din[4]; + dout[31] = din[1] ^ din[2] ^ din[7] ^ din[3]; + dout[30] = din[0] ^ din[1] ^ din[6] ^ din[2]; + dout[29] = din[8] ^ din[0] ^ din[4] ^ din[5] ^ din[1]; + dout[28] = din[7] ^ din[8] ^ din[3] ^ din[0]; + dout[27] = din[6] ^ din[7] ^ din[2] ^ din[8] ^ din[4]; + dout[26] = din[5] ^ din[6] ^ din[1] ^ din[7] ^ din[3]; + dout[25] = din[4] ^ din[5] ^ din[0] ^ din[6] ^ din[2]; + dout[24] = din[3] ^ din[8] ^ din[5] ^ din[1]; + dout[23] = din[2] ^ din[4] ^ din[7] ^ din[0]; + dout[22] = din[1] ^ din[3] ^ din[6] ^ din[8] ^ din[4]; + dout[21] = din[0] ^ din[2] ^ din[5] ^ din[7] ^ din[3]; + dout[20] = din[8] ^ din[1] ^ din[6] ^ din[2]; + dout[19] = din[7] ^ din[0] ^ din[5] ^ din[1]; + dout[18] = din[6] ^ din[8] ^ din[0]; + dout[17] = din[5] ^ din[7] ^ din[8] ^ din[4]; + dout[16] = din[4] ^ din[6] ^ din[7] ^ din[3]; + dout[15] = din[3] ^ din[5] ^ din[6] ^ din[2]; + dout[14] = din[2] ^ din[4] ^ din[5] ^ din[1]; + dout[13] = din[1] ^ din[3] ^ din[4] ^ din[0]; + dout[12] = din[0] ^ din[2] ^ din[3] ^ din[8] ^ din[4]; + dout[11] = din[8] ^ din[1] ^ din[2] ^ din[4] ^ din[7] ^ din[3]; + dout[10] = din[7] ^ din[0] ^ din[1] ^ din[3] ^ din[6] ^ din[2]; + dout[9] = din[6] ^ din[8] ^ din[0] ^ din[2] ^ din[4] ^ din[5] ^ din[1]; + dout[8] = din[5] ^ din[7] ^ din[8] ^ din[1] ^ din[3] ^ din[0]; + dout[7] = din[6] ^ din[7] ^ din[0] ^ din[2] ^ din[8]; + dout[6] = din[5] ^ din[6] ^ din[8] ^ din[1] ^ din[4] ^ din[7]; + dout[5] = din[4] ^ din[5] ^ din[7] ^ din[0] ^ din[3] ^ din[6]; + dout[4] = din[3] ^ din[6] ^ din[8] ^ din[2] ^ din[5]; + dout[3] = din[2] ^ din[4] ^ din[5] ^ din[7] ^ din[1]; + dout[2] = din[1] ^ din[4] ^ din[3] ^ din[6] ^ din[0]; + dout[1] = din[0] ^ din[3] ^ din[2] ^ din[5] ^ din[8] ^ din[4]; + dout[0] = din[8] ^ din[2] ^ din[1] ^ din[7] ^ din[3]; + pn9 = dout; + end + endfunction + + // prbs pn23 function + function [47:0] pn23; + input [47:0] din; + reg [47:0] dout; + begin + dout[47] = din[22] ^ din[17]; + dout[46] = din[21] ^ din[16]; + dout[45] = din[20] ^ din[15]; + dout[44] = din[19] ^ din[14]; + dout[43] = din[18] ^ din[13]; + dout[42] = din[17] ^ din[12]; + dout[41] = din[16] ^ din[11]; + dout[40] = din[15] ^ din[10]; + dout[39] = din[14] ^ din[9]; + dout[38] = din[13] ^ din[8]; + dout[37] = din[12] ^ din[7]; + dout[36] = din[11] ^ din[6]; + dout[35] = din[10] ^ din[5]; + dout[34] = din[9] ^ din[4]; + dout[33] = din[8] ^ din[3]; + dout[32] = din[7] ^ din[2]; + dout[31] = din[6] ^ din[1]; + dout[30] = din[5] ^ din[0]; + dout[29] = din[4] ^ din[22] ^ din[17]; + dout[28] = din[3] ^ din[21] ^ din[16]; + dout[27] = din[2] ^ din[20] ^ din[15]; + dout[26] = din[1] ^ din[19] ^ din[14]; + dout[25] = din[0] ^ din[18] ^ din[13]; + dout[24] = din[22] ^ din[12]; + dout[23] = din[21] ^ din[11]; + dout[22] = din[20] ^ din[10]; + dout[21] = din[19] ^ din[9]; + dout[20] = din[18] ^ din[8]; + dout[19] = din[17] ^ din[7]; + dout[18] = din[16] ^ din[6]; + dout[17] = din[15] ^ din[5]; + dout[16] = din[14] ^ din[4]; + dout[15] = din[13] ^ din[3]; + dout[14] = din[12] ^ din[2]; + dout[13] = din[11] ^ din[1]; + dout[12] = din[10] ^ din[0]; + dout[11] = din[9] ^ din[22] ^ din[17]; + dout[10] = din[8] ^ din[21] ^ din[16]; + dout[9] = din[7] ^ din[20] ^ din[15]; + dout[8] = din[6] ^ din[19] ^ din[14]; + dout[7] = din[5] ^ din[18] ^ din[13]; + dout[6] = din[4] ^ din[17] ^ din[12]; + dout[5] = din[3] ^ din[16] ^ din[11]; + dout[4] = din[2] ^ din[15] ^ din[10]; + dout[3] = din[1] ^ din[14] ^ din[9]; + dout[2] = din[0] ^ din[13] ^ din[8]; + dout[1] = din[22] ^ din[12] ^ din[17] ^ din[7]; + dout[0] = din[21] ^ din[11] ^ din[16] ^ din[6]; + pn23 = dout; + end + endfunction + + // pn sequence selection + assign adc_data_inv_s = {adc_data[11:0], adc_data[23:12], adc_data[35:24], adc_data[47:36]}; + assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_data_inv_s : adc_pn_data_pn; + + always @(posedge adc_clk) begin + if(adc_pnseq_sel == 4'b0) begin + adc_pn_data_pn <= pn9(adc_pn_data_pn_s); + end else begin + adc_pn_data_pn <= pn23(adc_pn_data_pn_s); + end + end + + // pn oos & pn err + ad_pnmon #( + .DATA_WIDTH(48) + ) i_pnmon ( + .adc_clk (adc_clk), + .adc_valid_in (1'b1), + .adc_data_in (adc_data_inv_s), + .adc_data_pn (adc_pn_data_pn), + .adc_pn_oos (adc_pn_oos), + .adc_pn_err (adc_pn_err)); + +endmodule diff --git a/adi_library/axi_ad9434/bd/bd.tcl b/adi_library/axi_ad9434/bd/bd.tcl new file mode 100644 index 00000000..dceb9498 --- /dev/null +++ b/adi_library/axi_ad9434/bd/bd.tcl @@ -0,0 +1,47 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + DEV_PACKAGE \ + SPEED_GRADE \ + FPGA_FAMILY \ + FPGA_TECHNOLOGY" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/axi_ad9434/component.xml b/adi_library/axi_ad9434/component.xml new file mode 100644 index 00000000..77341550 --- /dev/null +++ b/adi_library/axi_ad9434/component.xml @@ -0,0 +1,1214 @@ + + + analog.com + user + axi_ad9434 + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + delay_clk + + + + + + + CLK + + + delay_clk + + + + + + adc_clk + + + + + + + CLK + + + adc_clk + + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_ad9434 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + fe8e998e + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_ad9434 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 56668191 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + ba43b184 + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + + + adc_clk_in_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_clk_in_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_in_p + + in + + 11 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_data_in_n + + in + + 11 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_or_in_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_or_in_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + delay_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_dovf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + IODELAY_ENABLE + Iodelay Enable + 1 + + + IO_DELAY_GROUP + Io Delay Group + dev_if_delay_group + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_00ecfe9a + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + + + choice_pairs_19f99f31 + 0 + 10 + 11 + 12 + 13 + 14 + 20 + 21 + 22 + 23 + 24 + 25 + 30 + + + choice_pairs_28f798a2 + 0 + 1 + 2 + 3 + 4 + + + choice_pairs_fc01a186 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../xilinx/common/up_clock_mon_constr.xdc + xdc + + + axi_ad9434_constr.xdc + xdc + + + ../common/ad_datafmt.v + verilogSource + + + ../xilinx/common/ad_mmcm_drp.v + verilogSource + + + ../common/ad_pnmon.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../xilinx/common/ad_serdes_clk.v + verilogSource + + + ../xilinx/common/ad_serdes_in.v + verilogSource + + + axi_ad9434_core.v + verilogSource + + + axi_ad9434_if.v + verilogSource + + + axi_ad9434_pnmon.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_delay_cntrl.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad9434.v + verilogSource + CHECKSUM_abffd711 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_datafmt.v + verilogSource + + + ../xilinx/common/ad_mmcm_drp.v + verilogSource + + + ../common/ad_pnmon.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../xilinx/common/ad_serdes_clk.v + verilogSource + + + ../xilinx/common/ad_serdes_in.v + verilogSource + + + axi_ad9434_core.v + verilogSource + + + axi_ad9434_if.v + verilogSource + + + axi_ad9434_pnmon.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_delay_cntrl.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad9434.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_ad9434_v1_0.tcl + tclSource + CHECKSUM_28471896 + XGUI_VERSION_2 + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + axi_ad9434_v1_0 + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + IODELAY_ENABLE + Iodelay Enable + 1 + + + IO_DELAY_GROUP + Io Delay Group + dev_if_delay_group + + + Component_Name + axi_ad9434_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_ad9434_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:41:27Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_ad9434/temporary_case_dependencies.mk b/adi_library/axi_ad9434/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/axi_ad9434/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/axi_ad9434/xgui/axi_ad9434_v1_0.tcl b/adi_library/axi_ad9434/xgui/axi_ad9434_v1_0.tcl new file mode 100644 index 00000000..bc88d409 --- /dev/null +++ b/adi_library/axi_ad9434/xgui/axi_ad9434_v1_0.tcl @@ -0,0 +1,118 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "IODELAY_ENABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "IO_DELAY_GROUP" -parent ${Page_0} + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to validate DEV_PACKAGE + return true +} + +proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to validate FPGA_FAMILY + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.IODELAY_ENABLE { PARAM_VALUE.IODELAY_ENABLE } { + # Procedure called to update IODELAY_ENABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IODELAY_ENABLE { PARAM_VALUE.IODELAY_ENABLE } { + # Procedure called to validate IODELAY_ENABLE + return true +} + +proc update_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to update IO_DELAY_GROUP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to validate IO_DELAY_GROUP + return true +} + +proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to validate SPEED_GRADE + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY} +} + +proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE} +} + +proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE} +} + +proc update_MODELPARAM_VALUE.IODELAY_ENABLE { MODELPARAM_VALUE.IODELAY_ENABLE PARAM_VALUE.IODELAY_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IODELAY_ENABLE}] ${MODELPARAM_VALUE.IODELAY_ENABLE} +} + +proc update_MODELPARAM_VALUE.IO_DELAY_GROUP { MODELPARAM_VALUE.IO_DELAY_GROUP PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IO_DELAY_GROUP}] ${MODELPARAM_VALUE.IO_DELAY_GROUP} +} + diff --git a/adi_library/axi_ad9467/Makefile b/adi_library/axi_ad9467/Makefile new file mode 100644 index 00000000..4d148cfb --- /dev/null +++ b/adi_library/axi_ad9467/Makefile @@ -0,0 +1,32 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_ad9467 + +GENERIC_DEPS += ../common/ad_datafmt.v +GENERIC_DEPS += ../common/ad_pnmon.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_adc_channel.v +GENERIC_DEPS += ../common/up_adc_common.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_delay_cntrl.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_ad9467.v +GENERIC_DEPS += axi_ad9467_channel.v +GENERIC_DEPS += axi_ad9467_if.v +GENERIC_DEPS += axi_ad9467_pnmon.v + +XILINX_DEPS += ../xilinx/common/ad_data_clk.v +XILINX_DEPS += ../xilinx/common/ad_data_in.v +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_ad9467_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_ad9467/axi_ad9467.v b/adi_library/axi_ad9467/axi_ad9467.v new file mode 100644 index 00000000..b6dc9bfd --- /dev/null +++ b/adi_library/axi_ad9467/axi_ad9467.v @@ -0,0 +1,324 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9467#( + + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group", + parameter DELAY_REFCLK_FREQUENCY = 200 +) ( + + // physical interface + + input adc_clk_in_p, + input adc_clk_in_n, + input [ 7:0] adc_data_in_p, + input [ 7:0] adc_data_in_n, + input adc_or_in_p, + input adc_or_in_n, + + // delay_clock + + input delay_clk, + + // dma interface + + output adc_clk, + output adc_valid, + output adc_enable, + output [15:0] adc_data, + input adc_dovf, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready +); + + // internal registers + + reg up_wack = 'd0; + reg [31:0] up_rdata = 'd0; + reg up_rack = 'd0; + + // internal clocks & resets + + wire adc_rst; + wire up_clk; + wire up_rstn; + wire delay_rst; + + // internal signals + + wire [15:0] adc_data_s; + wire adc_or_s; + wire adc_ddr_edgesel_s; + wire [ 8:0] up_dld_s; + wire [44:0] up_dwdata_s; + wire [44:0] up_drdata_s; + wire delay_locked_s; + wire up_status_pn_err_s; + wire up_status_pn_oos_s; + wire up_status_or_s; + wire up_rreq_s; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_s[0:2]; + wire up_rack_s[0:2]; + wire up_wack_s[0:2]; + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + + //defaults + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + assign adc_valid = 1'b1; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 32'd0; + up_rack <= 1'd0; + up_wack <= 1'd0; + end else begin + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2]; + up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2]; + up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2]; + end + end + + // main (device interface) + + axi_ad9467_if #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IO_DELAY_GROUP (IO_DELAY_GROUP), + .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_if ( + .adc_clk_in_p (adc_clk_in_p), + .adc_clk_in_n (adc_clk_in_n), + .adc_data_in_p (adc_data_in_p), + .adc_data_in_n (adc_data_in_n), + .adc_or_in_p (adc_or_in_p), + .adc_or_in_n (adc_or_in_n), + .adc_clk (adc_clk), + .adc_data (adc_data_s), + .adc_or (adc_or_s), + .adc_ddr_edgesel (adc_ddr_edgesel_s), + .up_clk (up_clk), + .up_dld (up_dld_s), + .up_dwdata (up_dwdata_s), + .up_drdata (up_drdata_s), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s)); + + // channel + + axi_ad9467_channel #( + .CHANNEL_ID(0) + ) i_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_data_s), + .adc_or (adc_or_s), + .adc_dfmt_data (adc_data), + .adc_enable (adc_enable), + .up_adc_pn_err (up_status_pn_err_s), + .up_adc_pn_oos (up_status_pn_oos_s), + .up_adc_or (up_status_or_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // adc delay control + + up_delay_cntrl #( + .DATA_WIDTH(9), + .BASE_ADDRESS(6'h02) + ) i_delay_cntrl ( + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s), + .up_dld (up_dld_s), + .up_dwdata (up_dwdata_s), + .up_drdata (up_drdata_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + // common processor control + + up_adc_common #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .CONFIG (0), + .COMMON_ID (6'h00), + .DRP_DISABLE (6'h00), + .USERPORTS_DISABLE (0), + .GPIO_DISABLE (0), + .START_CODE_DISABLE(0) + ) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (adc_ddr_edgesel_s), + .adc_pin_mode (), + .adc_status (1'b1), + .adc_sync_status (1'd0), + .adc_status_ovf (adc_dovf), + .adc_clk_ratio (32'b1), + .adc_start_code (), + .adc_sref_sync (), + .adc_sync (), + .adc_ext_sync_arm (), + .adc_ext_sync_disarm (), + .adc_ext_sync_manual_req (), + .adc_num_lanes (), + .adc_custom_control (), + .adc_crc_enable (), + .adc_sdr_ddr_n (), + .adc_symb_op (), + .adc_symb_8_16b (), + .up_pps_rcounter (32'd0), + .up_pps_status (1'd0), + .up_pps_irq_mask (), + .up_adc_r1_mode (), + .up_adc_ce (), + .up_status_pn_err (up_status_pn_err_s), + .up_status_pn_oos (up_status_pn_oos_s), + .up_status_or (up_status_or_s), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (16'b0), + .up_drp_ready (1'b0), + .up_drp_locked (1'b1), + .adc_config_wr (), + .adc_config_ctrl (), + .adc_config_rd ('d0), + .adc_ctrl_status ('d0), + .up_usr_chanmax_out (), + .up_usr_chanmax_in (8'd1), + .up_adc_gpio_in (32'd0), + .up_adc_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ad9467/axi_ad9467.xpr b/adi_library/axi_ad9467/axi_ad9467.xpr new file mode 100644 index 00000000..8e6add71 --- /dev/null +++ b/adi_library/axi_ad9467/axi_ad9467.xpr @@ -0,0 +1,535 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_ad9467/axi_ad9467_channel.v b/adi_library/axi_ad9467/axi_ad9467_channel.v new file mode 100644 index 00000000..a64d8f66 --- /dev/null +++ b/adi_library/axi_ad9467/axi_ad9467_channel.v @@ -0,0 +1,158 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9467_channel#( + + parameter CHANNEL_ID = 0 +) ( + + // adc interface + + input adc_clk, + input adc_rst, + input [15:0] adc_data, + input adc_or, + + // channel interface + + output [15:0] adc_dfmt_data, + output adc_enable, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // internal signals + + wire adc_pn_oos_s; + wire adc_pn_err_s; + wire [ 3:0] adc_pnseq_sel_s; + wire adc_dfmt_enable_s; + wire adc_dfmt_type_s; + wire adc_dfmt_se_s; + + // instantiations + + axi_ad9467_pnmon i_axi_ad9467_pnmon ( + .adc_clk (adc_clk), + .adc_data (adc_data), + .adc_pn_oos (adc_pn_oos_s), + .adc_pn_err (adc_pn_err_s), + .adc_pnseq_sel (adc_pnseq_sel_s)); + + ad_datafmt #( + .DATA_WIDTH(16) + ) i_datafmt ( + .clk(adc_clk), + .valid(1'b1), + .data(adc_data), + .valid_out(), + .data_out(adc_dfmt_data), + .dfmt_enable(adc_dfmt_enable_s), + .dfmt_type(adc_dfmt_type_s), + .dfmt_se(adc_dfmt_se_s)); + + up_adc_channel #( + .COMMON_ID (6'h01), + .CHANNEL_ID(CHANNEL_ID), + .USERPORTS_DISABLE (0), + .DATAFORMAT_DISABLE (0), + .DCFILTER_DISABLE (0), + .IQCORRECTION_DISABLE (0) + ) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (), + .adc_dcfilt_enb (), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_dcfilt_offset (), + .adc_dcfilt_coeff (), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_data_sel (), + .adc_pn_err (adc_pn_err_s), + .adc_pn_oos (adc_pn_oos_s), + .adc_or (adc_or), + .adc_read_data ('d0), + .adc_status_header ('d0), + .adc_crc_err ('d0), + .up_adc_pn_err (up_adc_pn_err), + .up_adc_pn_oos (up_adc_pn_oos), + .up_adc_or (up_adc_or), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ad9467/axi_ad9467_if.v b/adi_library/axi_ad9467/axi_ad9467_if.v new file mode 100644 index 00000000..b804b464 --- /dev/null +++ b/adi_library/axi_ad9467/axi_ad9467_if.v @@ -0,0 +1,183 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// This is the LVDS/DDR interface + +`timescale 1ns/100ps + +module axi_ad9467_if #( + + parameter FPGA_TECHNOLOGY = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group", + parameter DELAY_REFCLK_FREQUENCY = 200 +) ( + + // adc interface (clk, data, over-range) + + input adc_clk_in_p, + input adc_clk_in_n, + input [ 7:0] adc_data_in_p, + input [ 7:0] adc_data_in_n, + input adc_or_in_p, + input adc_or_in_n, + + // interface outputs + + output adc_clk, + output reg [15:0] adc_data, + output reg adc_or, + + // processor interface + + input adc_ddr_edgesel, + + // delay control signals + + input up_clk, + input [ 8:0] up_dld, + input [44:0] up_dwdata, + output [44:0] up_drdata, + input delay_clk, + input delay_rst, + output delay_locked +); + + // internal registers + + reg [ 7:0] adc_data_p = 'd0; + reg [ 7:0] adc_data_n = 'd0; + reg [ 7:0] adc_data_p_d = 'd0; + reg [ 7:0] adc_dmux_a = 'd0; + reg [ 7:0] adc_dmux_b = 'd0; + reg adc_or_p = 'd0; + reg adc_or_n = 'd0; + + // internal signals + + wire [ 7:0] adc_data_p_s; + wire [ 7:0] adc_data_n_s; + wire adc_or_p_s; + wire adc_or_n_s; + + genvar l_inst; + + // sample select (p/n) swap + + always @(posedge adc_clk) begin + adc_data_p <= adc_data_p_s; + adc_data_n <= adc_data_n_s; + adc_data_p_d <= adc_data_p; + adc_dmux_a <= (adc_ddr_edgesel == 1'b1) ? adc_data_n : adc_data_p; + adc_dmux_b <= (adc_ddr_edgesel == 1'b1) ? adc_data_p_d : adc_data_n; + adc_data[15] <= adc_dmux_b[7]; + adc_data[14] <= adc_dmux_a[7]; + adc_data[13] <= adc_dmux_b[6]; + adc_data[12] <= adc_dmux_a[6]; + adc_data[11] <= adc_dmux_b[5]; + adc_data[10] <= adc_dmux_a[5]; + adc_data[ 9] <= adc_dmux_b[4]; + adc_data[ 8] <= adc_dmux_a[4]; + adc_data[ 7] <= adc_dmux_b[3]; + adc_data[ 6] <= adc_dmux_a[3]; + adc_data[ 5] <= adc_dmux_b[2]; + adc_data[ 4] <= adc_dmux_a[2]; + adc_data[ 3] <= adc_dmux_b[1]; + adc_data[ 2] <= adc_dmux_a[1]; + adc_data[ 1] <= adc_dmux_b[0]; + adc_data[ 0] <= adc_dmux_a[0]; + adc_or_p <= adc_or_p_s; + adc_or_n <= adc_or_n_s; + if ((adc_or_p == 1'b1) || (adc_or_n == 1'b1)) begin + adc_or <= 1'b1; + end else begin + adc_or <= 1'b0; + end + end + + // data interface + + generate + for (l_inst = 0; l_inst <= 7; l_inst = l_inst + 1) begin : g_adc_if + ad_data_in #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_adc_data ( + .rx_clk (adc_clk), + .rx_data_in_p (adc_data_in_p[l_inst]), + .rx_data_in_n (adc_data_in_n[l_inst]), + .rx_data_p (adc_data_p_s[l_inst]), + .rx_data_n (adc_data_n_s[l_inst]), + .up_clk (up_clk), + .up_dld (up_dld[l_inst]), + .up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]), + .up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + endgenerate + + // over-range interface + + ad_data_in #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_CTRL (1), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_adc_or ( + .rx_clk (adc_clk), + .rx_data_in_p (adc_or_in_p), + .rx_data_in_n (adc_or_in_n), + .rx_data_p (adc_or_p_s), + .rx_data_n (adc_or_n_s), + .up_clk (up_clk), + .up_dld (up_dld[8]), + .up_dwdata (up_dwdata[44:40]), + .up_drdata (up_drdata[44:40]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked)); + + // clock + + ad_data_clk i_adc_clk ( + .rst (1'b0), + .locked (), + .clk_in_p (adc_clk_in_p), + .clk_in_n (adc_clk_in_n), + .clk (adc_clk)); + +endmodule diff --git a/adi_library/axi_ad9467/axi_ad9467_ip.tcl b/adi_library/axi_ad9467/axi_ad9467_ip.tcl new file mode 100644 index 00000000..4e87a9eb --- /dev/null +++ b/adi_library/axi_ad9467/axi_ad9467_ip.tcl @@ -0,0 +1,50 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_ad9467 +adi_ip_files axi_ad9467 [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "axi_ad9467_pnmon.v" \ + "axi_ad9467_if.v" \ + "axi_ad9467_channel.v" \ + "axi_ad9467.v" ] + +adi_ip_properties axi_ad9467 + +adi_init_bd_tcl +adi_ip_bd axi_ad9467 "bd/bd.tcl" + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad9467} [ipx::current_core] + +set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] + +ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface adc_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface adc_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + +ipx::save_core [ipx::current_core] diff --git a/adi_library/axi_ad9467/axi_ad9467_pnmon.v b/adi_library/axi_ad9467/axi_ad9467_pnmon.v new file mode 100644 index 00000000..8f0ec793 --- /dev/null +++ b/adi_library/axi_ad9467/axi_ad9467_pnmon.v @@ -0,0 +1,176 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// PN monitors + +`timescale 1ns/100ps + +module axi_ad9467_pnmon ( + + // adc interface + + input adc_clk, + input [15:0] adc_data, + + // pn out of sync and error + + output adc_pn_oos, + output adc_pn_err, + input [ 3:0] adc_pnseq_sel +); + + // internal registers + + reg adc_valid_in = 'd0; + reg [31:0] adc_pn_data_in = 'd0; + reg [31:0] adc_pn_data_pn = 'd0; + + // internal signals + + wire [31:0] adc_pn_data_pn_s; + + // PN23 function + + function [31:0] pn23; + input [31:0] din; + reg [31:0] dout; + begin + dout[31] = din[22] ^ din[17]; + dout[30] = din[21] ^ din[16]; + dout[29] = din[20] ^ din[15]; + dout[28] = din[19] ^ din[14]; + dout[27] = din[18] ^ din[13]; + dout[26] = din[17] ^ din[12]; + dout[25] = din[16] ^ din[11]; + dout[24] = din[15] ^ din[10]; + dout[23] = din[14] ^ din[ 9]; + dout[22] = din[13] ^ din[ 8]; + dout[21] = din[12] ^ din[ 7]; + dout[20] = din[11] ^ din[ 6]; + dout[19] = din[10] ^ din[ 5]; + dout[18] = din[ 9] ^ din[ 4]; + dout[17] = din[ 8] ^ din[ 3]; + dout[16] = din[ 7] ^ din[ 2]; + dout[15] = din[ 6] ^ din[ 1]; + dout[14] = din[ 5] ^ din[ 0]; + dout[13] = din[ 4] ^ din[22] ^ din[17]; + dout[12] = din[ 3] ^ din[21] ^ din[16]; + dout[11] = din[ 2] ^ din[20] ^ din[15]; + dout[10] = din[ 1] ^ din[19] ^ din[14]; + dout[ 9] = din[ 0] ^ din[18] ^ din[13]; + dout[ 8] = din[22] ^ din[12]; + dout[ 7] = din[21] ^ din[11]; + dout[ 6] = din[20] ^ din[10]; + dout[ 5] = din[19] ^ din[ 9]; + dout[ 4] = din[18] ^ din[ 8]; + dout[ 3] = din[17] ^ din[ 7]; + dout[ 2] = din[16] ^ din[ 6]; + dout[ 1] = din[15] ^ din[ 5]; + dout[ 0] = din[14] ^ din[ 4]; + pn23 = dout; + end + endfunction + + // PN9 function + + function [31:0] pn9; + input [31:0] din; + reg [31:0] dout; + begin + dout[31] = din[ 8] ^ din[ 4]; + dout[30] = din[ 7] ^ din[ 3]; + dout[29] = din[ 6] ^ din[ 2]; + dout[28] = din[ 5] ^ din[ 1]; + dout[27] = din[ 4] ^ din[ 0]; + dout[26] = din[ 3] ^ din[ 8] ^ din[ 4]; + dout[25] = din[ 2] ^ din[ 7] ^ din[ 3]; + dout[24] = din[ 1] ^ din[ 6] ^ din[ 2]; + dout[23] = din[ 0] ^ din[ 5] ^ din[ 1]; + dout[22] = din[ 8] ^ din[ 0]; + dout[21] = din[ 7] ^ din[ 8] ^ din[ 4]; + dout[20] = din[ 6] ^ din[ 7] ^ din[ 3]; + dout[19] = din[ 5] ^ din[ 6] ^ din[ 2]; + dout[18] = din[ 4] ^ din[ 5] ^ din[ 1]; + dout[17] = din[ 3] ^ din[ 4] ^ din[ 0]; + dout[16] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[15] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; + dout[14] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[13] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[12] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; + dout[11] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; + dout[10] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[ 9] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[ 8] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; + dout[ 7] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0]; + dout[ 6] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4]; + dout[ 5] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3]; + dout[ 4] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[ 3] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1]; + dout[ 2] = din[ 6] ^ din[ 8] ^ din[ 0]; + dout[ 1] = din[5] ^ din[7] ^ din[8] ^ din[4]; + dout[ 0] = din[4] ^ din[6] ^ din[7] ^ din[3]; + pn9 = dout; + end + endfunction + + // pn sequence select + + assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn; + + always @(posedge adc_clk) begin + adc_valid_in <= ~adc_valid_in; + adc_pn_data_in <= {adc_pn_data_in[15:0], ~adc_data[15], adc_data[14:0]}; + if (adc_valid_in == 1'b1) begin + if (adc_pnseq_sel == 4'd0) begin + adc_pn_data_pn <= pn9(adc_pn_data_pn_s); + end else begin + adc_pn_data_pn <= pn23(adc_pn_data_pn_s); + end + end + end + + // pn oos & pn err + + ad_pnmon #( + .DATA_WIDTH(32) + ) i_pnmon ( + .adc_clk (adc_clk), + .adc_valid_in (adc_valid_in), + .adc_data_in (adc_pn_data_in), + .adc_data_pn (adc_pn_data_pn), + .adc_pattern_has_zero (1'b0), + .adc_pn_oos (adc_pn_oos), + .adc_pn_err (adc_pn_err)); + +endmodule diff --git a/adi_library/axi_ad9467/bd/bd.tcl b/adi_library/axi_ad9467/bd/bd.tcl new file mode 100644 index 00000000..dceb9498 --- /dev/null +++ b/adi_library/axi_ad9467/bd/bd.tcl @@ -0,0 +1,47 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + DEV_PACKAGE \ + SPEED_GRADE \ + FPGA_FAMILY \ + FPGA_TECHNOLOGY" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/axi_ad9467/component.xml b/adi_library/axi_ad9467/component.xml new file mode 100644 index 00000000..a4e1f690 --- /dev/null +++ b/adi_library/axi_ad9467/component.xml @@ -0,0 +1,1234 @@ + + + analog.com + user + axi_ad9467 + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + adc_clk + + + + + + + CLK + + + adc_clk + + + + + + delay_clk + + + + + + + CLK + + + delay_clk + + + + + + adc_clk_in_p + + + + + + + CLK + + + adc_clk_in_p + + + + + + adc_clk_in_n + + + + + + + CLK + + + adc_clk_in_n + + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_ad9467 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 565f585b + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_ad9467 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 4cefe2bf + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + e2b240ad + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + + + adc_clk_in_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_clk_in_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_in_p + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_data_in_n + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_or_in_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_or_in_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + delay_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_dovf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + IO_DELAY_GROUP + Io Delay Group + dev_if_delay_group + + + DELAY_REFCLK_FREQUENCY + Delay Refclk Frequency + 200 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_00ecfe9a + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + + + choice_pairs_19f99f31 + 0 + 10 + 11 + 12 + 13 + 14 + 20 + 21 + 22 + 23 + 24 + 25 + 30 + + + choice_pairs_28f798a2 + 0 + 1 + 2 + 3 + 4 + + + choice_pairs_fc01a186 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../xilinx/common/up_clock_mon_constr.xdc + xdc + + + ../xilinx/common/ad_data_clk.v + verilogSource + + + ../xilinx/common/ad_data_in.v + verilogSource + + + ../common/ad_datafmt.v + verilogSource + + + ../common/ad_pnmon.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + axi_ad9467_channel.v + verilogSource + + + axi_ad9467_if.v + verilogSource + + + axi_ad9467_pnmon.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_delay_cntrl.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad9467.v + verilogSource + CHECKSUM_f69b9b05 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../xilinx/common/ad_data_clk.v + verilogSource + + + ../xilinx/common/ad_data_in.v + verilogSource + + + ../common/ad_datafmt.v + verilogSource + + + ../common/ad_pnmon.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + axi_ad9467_channel.v + verilogSource + + + axi_ad9467_if.v + verilogSource + + + axi_ad9467_pnmon.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_delay_cntrl.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad9467.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_ad9467_v1_0.tcl + tclSource + CHECKSUM_55ba7c0c + XGUI_VERSION_2 + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + axi_ad9467_v1_0 + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + IO_DELAY_GROUP + Io Delay Group + dev_if_delay_group + + + DELAY_REFCLK_FREQUENCY + Delay Refclk Frequency + 200 + + + Component_Name + axi_ad9467_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_ad9467_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_ad9467 + 1 + 2024-01-14T03:41:45Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_ad9467/temporary_case_dependencies.mk b/adi_library/axi_ad9467/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/axi_ad9467/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/axi_ad9467/xgui/axi_ad9467_v1_0.tcl b/adi_library/axi_ad9467/xgui/axi_ad9467_v1_0.tcl new file mode 100644 index 00000000..b0030012 --- /dev/null +++ b/adi_library/axi_ad9467/xgui/axi_ad9467_v1_0.tcl @@ -0,0 +1,118 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DELAY_REFCLK_FREQUENCY" -parent ${Page_0} + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "IO_DELAY_GROUP" -parent ${Page_0} + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } { + # Procedure called to update DELAY_REFCLK_FREQUENCY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } { + # Procedure called to validate DELAY_REFCLK_FREQUENCY + return true +} + +proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to validate DEV_PACKAGE + return true +} + +proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to validate FPGA_FAMILY + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to update IO_DELAY_GROUP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to validate IO_DELAY_GROUP + return true +} + +proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to validate SPEED_GRADE + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY} +} + +proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE} +} + +proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE} +} + +proc update_MODELPARAM_VALUE.IO_DELAY_GROUP { MODELPARAM_VALUE.IO_DELAY_GROUP PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IO_DELAY_GROUP}] ${MODELPARAM_VALUE.IO_DELAY_GROUP} +} + +proc update_MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY { MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY PARAM_VALUE.DELAY_REFCLK_FREQUENCY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DELAY_REFCLK_FREQUENCY}] ${MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY} +} + diff --git a/adi_library/axi_ad9625/Makefile b/adi_library/axi_ad9625/Makefile new file mode 100644 index 00000000..3067f37e --- /dev/null +++ b/adi_library/axi_ad9625/Makefile @@ -0,0 +1,31 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_ad9625 + +GENERIC_DEPS += ../common/ad_datafmt.v +GENERIC_DEPS += ../common/ad_mem.v +GENERIC_DEPS += ../common/ad_pnmon.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/ad_xcvr_rx_if.v +GENERIC_DEPS += ../common/up_adc_channel.v +GENERIC_DEPS += ../common/up_adc_common.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_ad9625.v +GENERIC_DEPS += axi_ad9625_channel.v +GENERIC_DEPS += axi_ad9625_if.v +GENERIC_DEPS += axi_ad9625_pnmon.v + +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_ad9625_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_ad9625/axi_ad9625.v b/adi_library/axi_ad9625/axi_ad9625.v new file mode 100644 index 00000000..7aee8070 --- /dev/null +++ b/adi_library/axi_ad9625/axi_ad9625.v @@ -0,0 +1,288 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9625 #( + + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter DELAY_REFCLK_FREQUENCY = 200 +) ( + + // jesd interface + // rx_clk is (line-rate/40) + + input rx_clk, + input [ 3:0] rx_sof, + input rx_valid, + input [255:0] rx_data, + output rx_ready, + + // dma interface + + output adc_clk, + output adc_rst, + output adc_valid, + output adc_enable, + output [255:0] adc_data, + input adc_dovf, + output [ 15:0] adc_sref, + input [ 3:0] adc_raddr_in, + output [ 3:0] adc_raddr_out, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [ 15:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [ 31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [ 15:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [ 31:0] s_axi_rdata, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot +); + + // internal registers + + reg [ 31:0] up_rdata = 'd0; + reg up_rack = 'd0; + reg up_wack = 'd0; + + // internal signals + + wire up_rstn; + wire up_clk; + wire [191:0] adc_data_s; + wire adc_or_s; + wire adc_status_s; + wire adc_sref_sync_s; + wire up_adc_pn_err_s; + wire up_adc_pn_oos_s; + wire up_adc_or_s; + wire [ 31:0] up_rdata_s[0:1]; + wire up_rack_s[0:1]; + wire up_wack_s[0:1]; + wire up_wreq_s; + wire [ 13:0] up_waddr_s; + wire [ 31:0] up_wdata_s; + wire up_rreq_s; + wire [ 13:0] up_raddr_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // defaults + + assign rx_ready = 1'b1; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_rdata <= up_rdata_s[0] | up_rdata_s[1]; + up_rack <= up_rack_s[0] | up_rack_s[1] ; + up_wack <= up_wack_s[0] | up_wack_s[1] ; + end + end + + // main (device interface) + + assign adc_valid = 1'b1; + + axi_ad9625_if #( + .ID (ID) + ) i_if ( + .rx_clk (rx_clk), + .rx_sof (rx_sof), + .rx_data (rx_data), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_data_s), + .adc_or (adc_or_s), + .adc_status (adc_status_s), + .adc_sref (adc_sref), + .adc_sref_sync (adc_sref_sync_s), + .adc_raddr_in (adc_raddr_in), + .adc_raddr_out (adc_raddr_out)); + + // channel + + axi_ad9625_channel i_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_data_s), + .adc_or (adc_or_s), + .adc_dfmt_data (adc_data), + .adc_enable (adc_enable), + .up_adc_pn_err (up_adc_pn_err_s), + .up_adc_pn_oos (up_adc_pn_oos_s), + .up_adc_or (up_adc_or_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // common processor control + + up_adc_common #( + .ID(ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .CONFIG(0), + .COMMON_ID(6'h0), + .DRP_DISABLE(1), + .USERPORTS_DISABLE(1), + .GPIO_DISABLE(1), + .START_CODE_DISABLE(1) + ) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (adc_status_s), + .adc_sync_status (1'd0), + .adc_status_ovf (adc_dovf), + .adc_clk_ratio (32'd16), + .adc_start_code (), + .adc_sync (), + .adc_sref_sync (adc_sref_sync_s), + .adc_ext_sync_arm (), + .adc_ext_sync_disarm (), + .adc_ext_sync_manual_req (), + .adc_num_lanes (), + .adc_custom_control (), + .adc_crc_enable (), + .adc_sdr_ddr_n (), + .adc_symb_op (), + .adc_symb_8_16b (), + .up_pps_rcounter(32'h0), + .up_pps_status(1'b0), + .up_pps_irq_mask(), + .up_adc_r1_mode (), + .up_adc_ce (), + .up_status_pn_err (up_adc_pn_err_s), + .up_status_pn_oos (up_adc_pn_oos_s), + .up_status_or (up_adc_or_s), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .adc_config_wr (), + .adc_config_ctrl (), + .adc_config_rd ('d0), + .adc_ctrl_status ('d0), + .up_usr_chanmax_out (), + .up_usr_chanmax_in (8'd1), + .up_adc_gpio_in (32'd0), + .up_adc_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ad9625/axi_ad9625.xpr b/adi_library/axi_ad9625/axi_ad9625.xpr new file mode 100644 index 00000000..12ce751d --- /dev/null +++ b/adi_library/axi_ad9625/axi_ad9625.xpr @@ -0,0 +1,528 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_ad9625/axi_ad9625_channel.v b/adi_library/axi_ad9625/axi_ad9625_channel.v new file mode 100644 index 00000000..cd6921b5 --- /dev/null +++ b/adi_library/axi_ad9625/axi_ad9625_channel.v @@ -0,0 +1,160 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9625_channel ( + + // adc interface + + input adc_clk, + input adc_rst, + input [191:0] adc_data, + input adc_or, + + // channel interface + + output [255:0] adc_dfmt_data, + output adc_enable, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [ 13:0] up_waddr, + input [ 31:0] up_wdata, + output up_wack, + input up_rreq, + input [ 13:0] up_raddr, + output [ 31:0] up_rdata, + output up_rack +); + + // internal signals + + wire adc_pn_oos_s; + wire adc_pn_err_s; + wire adc_dfmt_enable_s; + wire adc_dfmt_type_s; + wire adc_dfmt_se_s; + wire [ 3:0] adc_pnseq_sel_s; + + // instantiations + + axi_ad9625_pnmon i_pnmon ( + .adc_clk (adc_clk), + .adc_data (adc_data), + .adc_pn_oos (adc_pn_oos_s), + .adc_pn_err (adc_pn_err_s), + .adc_pnseq_sel (adc_pnseq_sel_s)); + + genvar n; + generate + for (n = 0; n < 16; n = n + 1) begin: g_ad_datafmt_1 + ad_datafmt #( + .DATA_WIDTH(12) + ) i_ad_datafmt ( + .clk (adc_clk), + .valid (1'b1), + .data (adc_data[n*12+11:n*12]), + .valid_out (), + .data_out (adc_dfmt_data[n*16+15:n*16]), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + end + endgenerate + + up_adc_channel #( + .COMMON_ID(6'h1), + .CHANNEL_ID(0), + .USERPORTS_DISABLE(1), + .DATAFORMAT_DISABLE(0), + .DCFILTER_DISABLE(1), + .IQCORRECTION_DISABLE(1) + ) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (), + .adc_dcfilt_enb (), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_dcfilt_offset (), + .adc_dcfilt_coeff (), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_data_sel (), + .adc_pn_err (adc_pn_err_s), + .adc_pn_oos (adc_pn_oos_s), + .adc_or (adc_or), + .adc_read_data ('d0), + .adc_status_header ('d0), + .adc_crc_err ('d0), + .up_adc_pn_err (up_adc_pn_err), + .up_adc_pn_oos (up_adc_pn_oos), + .up_adc_or (up_adc_or), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ad9625/axi_ad9625_if.v b/adi_library/axi_ad9625/axi_ad9625_if.v new file mode 100644 index 00000000..0ccf1e39 --- /dev/null +++ b/adi_library/axi_ad9625/axi_ad9625_if.v @@ -0,0 +1,240 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9625_if #( + + parameter ID = 0 +) ( + + // jesd interface + // rx_clk is (line-rate/40) + + input rx_clk, + input [ 3:0] rx_sof, + input [255:0] rx_data, + + // adc data output + + output adc_clk, + input adc_rst, + output [191:0] adc_data, + output adc_or, + output adc_status, + output [ 15:0] adc_sref, + input adc_sref_sync, + input [ 3:0] adc_raddr_in, + output [ 3:0] adc_raddr_out +); + + // internal registers + + reg [191:0] adc_data_int = 'd0; + reg adc_status_int = 'd0; + reg [ 15:0] adc_sref_int = 'd0; + reg [191:0] adc_data_cur = 'd0; + reg [191:0] adc_data_prv = 'd0; + reg [ 3:0] adc_waddr = 'd0; + reg [191:0] adc_wdata = 'd0; + reg [ 3:0] adc_raddr = 'd0; + + // internal signals + + wire [191:0] adc_rdata_s; + wire [ 3:0] adc_raddr_s; + wire [ 15:0] adc_sref_s; + wire [191:0] adc_data_s; + wire [ 15:0] adc_data_s15_s; + wire [ 15:0] adc_data_s14_s; + wire [ 15:0] adc_data_s13_s; + wire [ 15:0] adc_data_s12_s; + wire [ 15:0] adc_data_s11_s; + wire [ 15:0] adc_data_s10_s; + wire [ 15:0] adc_data_s09_s; + wire [ 15:0] adc_data_s08_s; + wire [ 15:0] adc_data_s07_s; + wire [ 15:0] adc_data_s06_s; + wire [ 15:0] adc_data_s05_s; + wire [ 15:0] adc_data_s04_s; + wire [ 15:0] adc_data_s03_s; + wire [ 15:0] adc_data_s02_s; + wire [ 15:0] adc_data_s01_s; + wire [ 15:0] adc_data_s00_s; + wire [ 31:0] rx_data0_s; + wire [ 31:0] rx_data1_s; + wire [ 31:0] rx_data2_s; + wire [ 31:0] rx_data3_s; + wire [ 31:0] rx_data4_s; + wire [ 31:0] rx_data5_s; + wire [ 31:0] rx_data6_s; + wire [ 31:0] rx_data7_s; + wire [255:0] rx_data_s; + + // nothing much to do on clock & over-range + + assign adc_clk = rx_clk; + assign adc_or = 1'b0; + + // synchronization mode, multiple instances + + assign adc_data = adc_data_int; + assign adc_status = adc_status_int; + assign adc_sref = adc_sref_int; + assign adc_raddr_out = adc_raddr; + assign adc_raddr_s = (ID == 0) ? adc_raddr : adc_raddr_in; + + always @(posedge rx_clk) begin + if (adc_sref_sync == 1'b1) begin + adc_data_int <= adc_rdata_s; + end else begin + adc_data_int <= adc_data_s; + end + if (adc_sref_s != 16'd0) begin + adc_sref_int <= adc_sref_s; + end + adc_data_cur <= adc_data_s; + adc_data_prv <= adc_data_cur; + if (adc_sref_s == 16'd0) begin + adc_waddr <= adc_waddr + 1'b1; + adc_raddr <= adc_raddr + 1'b1; + end else begin + adc_waddr <= 4'h0; + adc_raddr <= 4'h8; + end + case (adc_sref_int) + 16'h8000: adc_wdata <= {adc_data_cur[179:0], adc_data_prv[191:180]}; + 16'h4000: adc_wdata <= {adc_data_cur[167:0], adc_data_prv[191:168]}; + 16'h2000: adc_wdata <= {adc_data_cur[155:0], adc_data_prv[191:156]}; + 16'h1000: adc_wdata <= {adc_data_cur[143:0], adc_data_prv[191:144]}; + 16'h0800: adc_wdata <= {adc_data_cur[131:0], adc_data_prv[191:132]}; + 16'h0400: adc_wdata <= {adc_data_cur[119:0], adc_data_prv[191:120]}; + 16'h0200: adc_wdata <= {adc_data_cur[107:0], adc_data_prv[191:108]}; + 16'h0100: adc_wdata <= {adc_data_cur[ 95:0], adc_data_prv[191: 96]}; + 16'h0080: adc_wdata <= {adc_data_cur[ 83:0], adc_data_prv[191: 84]}; + 16'h0040: adc_wdata <= {adc_data_cur[ 71:0], adc_data_prv[191: 72]}; + 16'h0020: adc_wdata <= {adc_data_cur[ 59:0], adc_data_prv[191: 60]}; + 16'h0010: adc_wdata <= {adc_data_cur[ 47:0], adc_data_prv[191: 48]}; + 16'h0008: adc_wdata <= {adc_data_cur[ 35:0], adc_data_prv[191: 36]}; + 16'h0004: adc_wdata <= {adc_data_cur[ 23:0], adc_data_prv[191: 24]}; + 16'h0002: adc_wdata <= {adc_data_cur[ 11:0], adc_data_prv[191: 12]}; + default: adc_wdata <= adc_data_prv; + endcase + end + + // samples only + + assign adc_sref_s = {adc_data_s15_s[14], adc_data_s14_s[14], + adc_data_s13_s[14], adc_data_s12_s[14], adc_data_s11_s[14], + adc_data_s10_s[14], adc_data_s09_s[14], adc_data_s08_s[14], + adc_data_s07_s[14], adc_data_s06_s[14], adc_data_s05_s[14], + adc_data_s04_s[14], adc_data_s03_s[14], adc_data_s02_s[14], + adc_data_s01_s[14], adc_data_s00_s[14]}; + + assign adc_data_s = {adc_data_s15_s[11:0], adc_data_s14_s[11:0], + adc_data_s13_s[11:0], adc_data_s12_s[11:0], adc_data_s11_s[11:0], + adc_data_s10_s[11:0], adc_data_s09_s[11:0], adc_data_s08_s[11:0], + adc_data_s07_s[11:0], adc_data_s06_s[11:0], adc_data_s05_s[11:0], + adc_data_s04_s[11:0], adc_data_s03_s[11:0], adc_data_s02_s[11:0], + adc_data_s01_s[11:0], adc_data_s00_s[11:0]}; + + // data is received across multiple lanes (reconstruct samples) + + assign adc_data_s15_s = {rx_data7_s[27:24], rx_data6_s[31:24], rx_data7_s[31:28]}; + assign adc_data_s14_s = {rx_data5_s[27:24], rx_data4_s[31:24], rx_data5_s[31:28]}; + assign adc_data_s13_s = {rx_data3_s[27:24], rx_data2_s[31:24], rx_data3_s[31:28]}; + assign adc_data_s12_s = {rx_data1_s[27:24], rx_data0_s[31:24], rx_data1_s[31:28]}; + assign adc_data_s11_s = {rx_data7_s[19:16], rx_data6_s[23:16], rx_data7_s[23:20]}; + assign adc_data_s10_s = {rx_data5_s[19:16], rx_data4_s[23:16], rx_data5_s[23:20]}; + assign adc_data_s09_s = {rx_data3_s[19:16], rx_data2_s[23:16], rx_data3_s[23:20]}; + assign adc_data_s08_s = {rx_data1_s[19:16], rx_data0_s[23:16], rx_data1_s[23:20]}; + assign adc_data_s07_s = {rx_data7_s[11: 8], rx_data6_s[15: 8], rx_data7_s[15:12]}; + assign adc_data_s06_s = {rx_data5_s[11: 8], rx_data4_s[15: 8], rx_data5_s[15:12]}; + assign adc_data_s05_s = {rx_data3_s[11: 8], rx_data2_s[15: 8], rx_data3_s[15:12]}; + assign adc_data_s04_s = {rx_data1_s[11: 8], rx_data0_s[15: 8], rx_data1_s[15:12]}; + assign adc_data_s03_s = {rx_data7_s[ 3: 0], rx_data6_s[ 7: 0], rx_data7_s[ 7: 4]}; + assign adc_data_s02_s = {rx_data5_s[ 3: 0], rx_data4_s[ 7: 0], rx_data5_s[ 7: 4]}; + assign adc_data_s01_s = {rx_data3_s[ 3: 0], rx_data2_s[ 7: 0], rx_data3_s[ 7: 4]}; + assign adc_data_s00_s = {rx_data1_s[ 3: 0], rx_data0_s[ 7: 0], rx_data1_s[ 7: 4]}; + + assign rx_data0_s = rx_data_s[ 31: 0]; + assign rx_data1_s = rx_data_s[ 63: 32]; + assign rx_data2_s = rx_data_s[ 95: 64]; + assign rx_data3_s = rx_data_s[127: 96]; + assign rx_data4_s = rx_data_s[159:128]; + assign rx_data5_s = rx_data_s[191:160]; + assign rx_data6_s = rx_data_s[223:192]; + assign rx_data7_s = rx_data_s[255:224]; + + // status + + always @(posedge rx_clk) begin + if (adc_rst == 1'b1) begin + adc_status_int <= 1'b0; + end else begin + adc_status_int <= 1'b1; + end + end + + // alignment fifo + + ad_mem #( + .ADDRESS_WIDTH(4), + .DATA_WIDTH(192) + ) i_mem ( + .clka (rx_clk), + .wea (1'b1), + .addra (adc_waddr), + .dina (adc_wdata), + .clkb (rx_clk), + .reb (1'b1), + .addrb (adc_raddr_s), + .doutb (adc_rdata_s)); + + // frame-alignment + + genvar n; + generate + for (n = 0; n < 8; n = n + 1) begin: g_xcvr_if + ad_xcvr_rx_if i_xcvr_if ( + .rx_clk (rx_clk), + .rx_ip_sof (rx_sof), + .rx_ip_data (rx_data[((n*32)+31):(n*32)]), + .rx_sof (), + .rx_data (rx_data_s[((n*32)+31):(n*32)])); + end + endgenerate + +endmodule diff --git a/adi_library/axi_ad9625/axi_ad9625_ip.tcl b/adi_library/axi_ad9625/axi_ad9625_ip.tcl new file mode 100644 index 00000000..f8489ece --- /dev/null +++ b/adi_library/axi_ad9625/axi_ad9625_ip.tcl @@ -0,0 +1,50 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_ad9625 +adi_ip_files axi_ad9625 [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/ad_mem.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "axi_ad9625_pnmon.v" \ + "axi_ad9625_channel.v" \ + "axi_ad9625_if.v" \ + "axi_ad9625.v" ] + +adi_ip_properties axi_ad9625 + +adi_init_bd_tcl +adi_ip_bd axi_ad9625 "bd/bd.tcl" + +set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *raddr_in* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] + +ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + +ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/axi_ad9625/axi_ad9625_pnmon.v b/adi_library/axi_ad9625/axi_ad9625_pnmon.v new file mode 100644 index 00000000..3ffeb058 --- /dev/null +++ b/adi_library/axi_ad9625/axi_ad9625_pnmon.v @@ -0,0 +1,508 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9625_pnmon ( + + // adc interface + + input adc_clk, + input [191:0] adc_data, + + // pn out of sync and error + + output adc_pn_oos, + output adc_pn_err, + + // processor interface PN9 (0x0), PN23 (0x1) + + input [ 3:0] adc_pnseq_sel +); + + // internal registers + + reg [191:0] adc_pn_data_in = 'd0; + reg [191:0] adc_pn_data_pn = 'd0; + + // internal signals + + wire [191:0] adc_pn_data_pn_s; + + // PN23 function + + function [191:0] pn23; + input [191:0] din; + reg [191:0] dout; + begin + dout[191] = din[22] ^ din[17]; + dout[190] = din[21] ^ din[16]; + dout[189] = din[20] ^ din[15]; + dout[188] = din[19] ^ din[14]; + dout[187] = din[18] ^ din[13]; + dout[186] = din[17] ^ din[12]; + dout[185] = din[16] ^ din[11]; + dout[184] = din[15] ^ din[10]; + dout[183] = din[14] ^ din[ 9]; + dout[182] = din[13] ^ din[ 8]; + dout[181] = din[12] ^ din[ 7]; + dout[180] = din[11] ^ din[ 6]; + dout[179] = din[10] ^ din[ 5]; + dout[178] = din[ 9] ^ din[ 4]; + dout[177] = din[ 8] ^ din[ 3]; + dout[176] = din[ 7] ^ din[ 2]; + dout[175] = din[ 6] ^ din[ 1]; + dout[174] = din[ 5] ^ din[ 0]; + dout[173] = din[ 4] ^ din[22] ^ din[17]; + dout[172] = din[ 3] ^ din[21] ^ din[16]; + dout[171] = din[ 2] ^ din[20] ^ din[15]; + dout[170] = din[ 1] ^ din[19] ^ din[14]; + dout[169] = din[ 0] ^ din[18] ^ din[13]; + dout[168] = din[22] ^ din[12]; + dout[167] = din[21] ^ din[11]; + dout[166] = din[20] ^ din[10]; + dout[165] = din[19] ^ din[ 9]; + dout[164] = din[18] ^ din[ 8]; + dout[163] = din[17] ^ din[ 7]; + dout[162] = din[16] ^ din[ 6]; + dout[161] = din[15] ^ din[ 5]; + dout[160] = din[14] ^ din[ 4]; + dout[159] = din[13] ^ din[ 3]; + dout[158] = din[12] ^ din[ 2]; + dout[157] = din[11] ^ din[ 1]; + dout[156] = din[10] ^ din[ 0]; + dout[155] = din[ 9] ^ din[22] ^ din[17]; + dout[154] = din[ 8] ^ din[21] ^ din[16]; + dout[153] = din[ 7] ^ din[20] ^ din[15]; + dout[152] = din[ 6] ^ din[19] ^ din[14]; + dout[151] = din[ 5] ^ din[18] ^ din[13]; + dout[150] = din[ 4] ^ din[17] ^ din[12]; + dout[149] = din[ 3] ^ din[16] ^ din[11]; + dout[148] = din[ 2] ^ din[15] ^ din[10]; + dout[147] = din[ 1] ^ din[14] ^ din[ 9]; + dout[146] = din[ 0] ^ din[13] ^ din[ 8]; + dout[145] = din[22] ^ din[12] ^ din[17] ^ din[ 7]; + dout[144] = din[21] ^ din[11] ^ din[16] ^ din[ 6]; + dout[143] = din[20] ^ din[10] ^ din[15] ^ din[ 5]; + dout[142] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4]; + dout[141] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3]; + dout[140] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2]; + dout[139] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1]; + dout[138] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0]; + dout[137] = din[14] ^ din[ 4] ^ din[ 9] ^ din[22] ^ din[17]; + dout[136] = din[13] ^ din[ 3] ^ din[ 8] ^ din[21] ^ din[16]; + dout[135] = din[12] ^ din[ 2] ^ din[ 7] ^ din[20] ^ din[15]; + dout[134] = din[11] ^ din[ 1] ^ din[ 6] ^ din[19] ^ din[14]; + dout[133] = din[10] ^ din[ 0] ^ din[ 5] ^ din[18] ^ din[13]; + dout[132] = din[ 9] ^ din[22] ^ din[ 4] ^ din[12]; + dout[131] = din[ 8] ^ din[21] ^ din[ 3] ^ din[11]; + dout[130] = din[ 7] ^ din[20] ^ din[ 2] ^ din[10]; + dout[129] = din[ 6] ^ din[19] ^ din[ 1] ^ din[ 9]; + dout[128] = din[ 5] ^ din[18] ^ din[ 0] ^ din[ 8]; + dout[127] = din[ 4] ^ din[22] ^ din[ 7]; + dout[126] = din[ 3] ^ din[21] ^ din[ 6]; + dout[125] = din[ 2] ^ din[20] ^ din[ 5]; + dout[124] = din[ 1] ^ din[19] ^ din[ 4]; + dout[123] = din[ 0] ^ din[18] ^ din[ 3]; + dout[122] = din[22] ^ din[ 2]; + dout[121] = din[21] ^ din[ 1]; + dout[120] = din[20] ^ din[ 0]; + dout[119] = din[19] ^ din[22] ^ din[17]; + dout[118] = din[18] ^ din[21] ^ din[16]; + dout[117] = din[17] ^ din[20] ^ din[15]; + dout[116] = din[16] ^ din[19] ^ din[14]; + dout[115] = din[15] ^ din[18] ^ din[13]; + dout[114] = din[14] ^ din[17] ^ din[12]; + dout[113] = din[13] ^ din[16] ^ din[11]; + dout[112] = din[12] ^ din[15] ^ din[10]; + dout[111] = din[11] ^ din[14] ^ din[ 9]; + dout[110] = din[10] ^ din[13] ^ din[ 8]; + dout[109] = din[ 9] ^ din[12] ^ din[ 7]; + dout[108] = din[ 8] ^ din[11] ^ din[ 6]; + dout[107] = din[ 7] ^ din[10] ^ din[ 5]; + dout[106] = din[ 6] ^ din[ 9] ^ din[ 4]; + dout[105] = din[ 5] ^ din[ 8] ^ din[ 3]; + dout[104] = din[ 4] ^ din[ 7] ^ din[ 2]; + dout[103] = din[ 3] ^ din[ 6] ^ din[ 1]; + dout[102] = din[ 2] ^ din[ 5] ^ din[ 0]; + dout[101] = din[ 1] ^ din[ 4] ^ din[22] ^ din[17]; + dout[100] = din[ 0] ^ din[ 3] ^ din[21] ^ din[16]; + dout[ 99] = din[22] ^ din[ 2] ^ din[17] ^ din[20] ^ din[15]; + dout[ 98] = din[21] ^ din[ 1] ^ din[16] ^ din[19] ^ din[14]; + dout[ 97] = din[20] ^ din[ 0] ^ din[15] ^ din[18] ^ din[13]; + dout[ 96] = din[19] ^ din[22] ^ din[14] ^ din[12]; + dout[ 95] = din[18] ^ din[21] ^ din[13] ^ din[11]; + dout[ 94] = din[17] ^ din[20] ^ din[12] ^ din[10]; + dout[ 93] = din[16] ^ din[19] ^ din[11] ^ din[ 9]; + dout[ 92] = din[15] ^ din[18] ^ din[10] ^ din[ 8]; + dout[ 91] = din[14] ^ din[17] ^ din[ 9] ^ din[ 7]; + dout[ 90] = din[13] ^ din[16] ^ din[ 8] ^ din[ 6]; + dout[ 89] = din[12] ^ din[15] ^ din[ 7] ^ din[ 5]; + dout[ 88] = din[11] ^ din[14] ^ din[ 6] ^ din[ 4]; + dout[ 87] = din[10] ^ din[13] ^ din[ 5] ^ din[ 3]; + dout[ 86] = din[ 9] ^ din[12] ^ din[ 4] ^ din[ 2]; + dout[ 85] = din[ 8] ^ din[11] ^ din[ 3] ^ din[ 1]; + dout[ 84] = din[ 7] ^ din[10] ^ din[ 2] ^ din[ 0]; + dout[ 83] = din[ 6] ^ din[ 9] ^ din[ 1] ^ din[22] ^ din[17]; + dout[ 82] = din[ 5] ^ din[ 8] ^ din[ 0] ^ din[21] ^ din[16]; + dout[ 81] = din[ 4] ^ din[ 7] ^ din[22] ^ din[17] ^ din[20] ^ din[15]; + dout[ 80] = din[ 3] ^ din[ 6] ^ din[21] ^ din[16] ^ din[19] ^ din[14]; + dout[ 79] = din[ 2] ^ din[ 5] ^ din[20] ^ din[15] ^ din[18] ^ din[13]; + dout[ 78] = din[ 1] ^ din[ 4] ^ din[17] ^ din[19] ^ din[14] ^ din[12]; + dout[ 77] = din[ 0] ^ din[ 3] ^ din[16] ^ din[18] ^ din[13] ^ din[11]; + dout[ 76] = din[22] ^ din[ 2] ^ din[15] ^ din[12] ^ din[10]; + dout[ 75] = din[21] ^ din[ 1] ^ din[14] ^ din[11] ^ din[ 9]; + dout[ 74] = din[20] ^ din[ 0] ^ din[13] ^ din[10] ^ din[ 8]; + dout[ 73] = din[19] ^ din[22] ^ din[12] ^ din[17] ^ din[ 9] ^ din[ 7]; + dout[ 72] = din[18] ^ din[21] ^ din[11] ^ din[16] ^ din[ 8] ^ din[ 6]; + dout[ 71] = din[17] ^ din[20] ^ din[10] ^ din[15] ^ din[ 7] ^ din[ 5]; + dout[ 70] = din[16] ^ din[19] ^ din[ 9] ^ din[14] ^ din[ 6] ^ din[ 4]; + dout[ 69] = din[15] ^ din[18] ^ din[ 8] ^ din[13] ^ din[ 5] ^ din[ 3]; + dout[ 68] = din[14] ^ din[17] ^ din[ 7] ^ din[12] ^ din[ 4] ^ din[ 2]; + dout[ 67] = din[13] ^ din[16] ^ din[ 6] ^ din[11] ^ din[ 3] ^ din[ 1]; + dout[ 66] = din[12] ^ din[15] ^ din[ 5] ^ din[10] ^ din[ 2] ^ din[ 0]; + dout[ 65] = din[11] ^ din[14] ^ din[ 4] ^ din[ 9] ^ din[ 1] ^ din[22] ^ din[17]; + dout[ 64] = din[10] ^ din[13] ^ din[ 3] ^ din[ 8] ^ din[ 0] ^ din[21] ^ din[16]; + dout[ 63] = din[ 9] ^ din[12] ^ din[ 2] ^ din[ 7] ^ din[22] ^ din[17] ^ din[20] ^ din[15]; + dout[ 62] = din[ 8] ^ din[11] ^ din[ 1] ^ din[ 6] ^ din[21] ^ din[16] ^ din[19] ^ din[14]; + dout[ 61] = din[ 7] ^ din[10] ^ din[ 0] ^ din[ 5] ^ din[20] ^ din[15] ^ din[18] ^ din[13]; + dout[ 60] = din[ 6] ^ din[ 9] ^ din[22] ^ din[ 4] ^ din[19] ^ din[14] ^ din[12]; + dout[ 59] = din[ 5] ^ din[ 8] ^ din[21] ^ din[ 3] ^ din[18] ^ din[13] ^ din[11]; + dout[ 58] = din[ 4] ^ din[ 7] ^ din[17] ^ din[20] ^ din[ 2] ^ din[12] ^ din[10]; + dout[ 57] = din[ 3] ^ din[ 6] ^ din[16] ^ din[19] ^ din[ 1] ^ din[11] ^ din[ 9]; + dout[ 56] = din[ 2] ^ din[ 5] ^ din[15] ^ din[18] ^ din[ 0] ^ din[10] ^ din[ 8]; + dout[ 55] = din[ 1] ^ din[ 4] ^ din[14] ^ din[22] ^ din[ 9] ^ din[ 7]; + dout[ 54] = din[ 0] ^ din[ 3] ^ din[13] ^ din[21] ^ din[ 8] ^ din[ 6]; + dout[ 53] = din[22] ^ din[ 2] ^ din[12] ^ din[17] ^ din[20] ^ din[ 7] ^ din[ 5]; + dout[ 52] = din[21] ^ din[ 1] ^ din[11] ^ din[16] ^ din[19] ^ din[ 6] ^ din[ 4]; + dout[ 51] = din[20] ^ din[ 0] ^ din[10] ^ din[15] ^ din[18] ^ din[ 5] ^ din[ 3]; + dout[ 50] = din[19] ^ din[22] ^ din[ 9] ^ din[14] ^ din[ 4] ^ din[ 2]; + dout[ 49] = din[18] ^ din[21] ^ din[ 8] ^ din[13] ^ din[ 3] ^ din[ 1]; + dout[ 48] = din[17] ^ din[20] ^ din[ 7] ^ din[12] ^ din[ 2] ^ din[ 0]; + dout[ 47] = din[16] ^ din[19] ^ din[ 6] ^ din[11] ^ din[ 1] ^ din[22] ^ din[17]; + dout[ 46] = din[15] ^ din[18] ^ din[ 5] ^ din[10] ^ din[ 0] ^ din[21] ^ din[16]; + dout[ 45] = din[14] ^ din[ 4] ^ din[ 9] ^ din[22] ^ din[20] ^ din[15]; + dout[ 44] = din[13] ^ din[ 3] ^ din[ 8] ^ din[21] ^ din[19] ^ din[14]; + dout[ 43] = din[12] ^ din[ 2] ^ din[ 7] ^ din[20] ^ din[18] ^ din[13]; + dout[ 42] = din[11] ^ din[ 1] ^ din[17] ^ din[ 6] ^ din[19] ^ din[12]; + dout[ 41] = din[10] ^ din[ 0] ^ din[16] ^ din[ 5] ^ din[18] ^ din[11]; + dout[ 40] = din[ 9] ^ din[22] ^ din[15] ^ din[ 4] ^ din[10]; + dout[ 39] = din[ 8] ^ din[21] ^ din[14] ^ din[ 3] ^ din[ 9]; + dout[ 38] = din[ 7] ^ din[20] ^ din[13] ^ din[ 2] ^ din[ 8]; + dout[ 37] = din[ 6] ^ din[19] ^ din[12] ^ din[ 1] ^ din[ 7]; + dout[ 36] = din[ 5] ^ din[18] ^ din[11] ^ din[ 0] ^ din[ 6]; + dout[ 35] = din[ 4] ^ din[10] ^ din[22] ^ din[ 5]; + dout[ 34] = din[ 3] ^ din[ 9] ^ din[21] ^ din[ 4]; + dout[ 33] = din[ 2] ^ din[ 8] ^ din[20] ^ din[ 3]; + dout[ 32] = din[ 1] ^ din[ 7] ^ din[19] ^ din[ 2]; + dout[ 31] = din[ 0] ^ din[ 6] ^ din[18] ^ din[ 1]; + dout[ 30] = din[22] ^ din[ 5] ^ din[ 0]; + dout[ 29] = din[21] ^ din[ 4] ^ din[22] ^ din[17]; + dout[ 28] = din[20] ^ din[ 3] ^ din[21] ^ din[16]; + dout[ 27] = din[19] ^ din[ 2] ^ din[20] ^ din[15]; + dout[ 26] = din[18] ^ din[ 1] ^ din[19] ^ din[14]; + dout[ 25] = din[17] ^ din[ 0] ^ din[18] ^ din[13]; + dout[ 24] = din[16] ^ din[22] ^ din[12]; + dout[ 23] = din[15] ^ din[21] ^ din[11]; + dout[ 22] = din[14] ^ din[20] ^ din[10]; + dout[ 21] = din[13] ^ din[19] ^ din[ 9]; + dout[ 20] = din[12] ^ din[18] ^ din[ 8]; + dout[ 19] = din[11] ^ din[17] ^ din[ 7]; + dout[ 18] = din[10] ^ din[16] ^ din[ 6]; + dout[ 17] = din[ 9] ^ din[15] ^ din[ 5]; + dout[ 16] = din[ 8] ^ din[14] ^ din[ 4]; + dout[ 15] = din[ 7] ^ din[13] ^ din[ 3]; + dout[ 14] = din[ 6] ^ din[12] ^ din[ 2]; + dout[ 13] = din[ 5] ^ din[11] ^ din[ 1]; + dout[ 12] = din[ 4] ^ din[10] ^ din[ 0]; + dout[ 11] = din[ 3] ^ din[ 9] ^ din[22] ^ din[17]; + dout[ 10] = din[ 2] ^ din[ 8] ^ din[21] ^ din[16]; + dout[ 9] = din[ 1] ^ din[ 7] ^ din[20] ^ din[15]; + dout[ 8] = din[ 0] ^ din[ 6] ^ din[19] ^ din[14]; + dout[ 7] = din[22] ^ din[ 5] ^ din[17] ^ din[18] ^ din[13]; + dout[ 6] = din[21] ^ din[ 4] ^ din[17] ^ din[16] ^ din[12]; + dout[ 5] = din[20] ^ din[ 3] ^ din[16] ^ din[15] ^ din[11]; + dout[ 4] = din[19] ^ din[ 2] ^ din[15] ^ din[14] ^ din[10]; + dout[ 3] = din[18] ^ din[ 1] ^ din[14] ^ din[13] ^ din[ 9]; + dout[ 2] = din[17] ^ din[ 0] ^ din[13] ^ din[12] ^ din[ 8]; + dout[ 1] = din[16] ^ din[22] ^ din[12] ^ din[11] ^ din[17] ^ din[ 7]; + dout[ 0] = din[15] ^ din[21] ^ din[11] ^ din[10] ^ din[16] ^ din[ 6]; + pn23 = dout; + end + endfunction + + // PN9 function + + function [191:0] pn9; + input [191:0] din; + reg [191:0] dout; + begin + dout[191] = din[ 8] ^ din[ 4]; + dout[190] = din[ 7] ^ din[ 3]; + dout[189] = din[ 6] ^ din[ 2]; + dout[188] = din[ 5] ^ din[ 1]; + dout[187] = din[ 4] ^ din[ 0]; + dout[186] = din[ 3] ^ din[ 8] ^ din[ 4]; + dout[185] = din[ 2] ^ din[ 7] ^ din[ 3]; + dout[184] = din[ 1] ^ din[ 6] ^ din[ 2]; + dout[183] = din[ 0] ^ din[ 5] ^ din[ 1]; + dout[182] = din[ 8] ^ din[ 0]; + dout[181] = din[ 7] ^ din[ 8] ^ din[ 4]; + dout[180] = din[ 6] ^ din[ 7] ^ din[ 3]; + dout[179] = din[ 5] ^ din[ 6] ^ din[ 2]; + dout[178] = din[ 4] ^ din[ 5] ^ din[ 1]; + dout[177] = din[ 3] ^ din[ 4] ^ din[ 0]; + dout[176] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[175] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; + dout[174] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[173] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[172] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; + dout[171] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; + dout[170] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[169] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[168] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; + dout[167] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0]; + dout[166] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4]; + dout[165] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3]; + dout[164] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[163] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1]; + dout[162] = din[ 6] ^ din[ 8] ^ din[ 0]; + dout[161] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4]; + dout[160] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3]; + dout[159] = din[ 3] ^ din[ 5] ^ din[ 6] ^ din[ 2]; + dout[158] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[157] = din[ 1] ^ din[ 3] ^ din[ 4] ^ din[ 0]; + dout[156] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[155] = din[ 8] ^ din[ 1] ^ din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 3]; + dout[154] = din[ 7] ^ din[ 0] ^ din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 2]; + dout[153] = din[ 6] ^ din[ 8] ^ din[ 0] ^ din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[152] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 1] ^ din[ 3] ^ din[ 0]; + dout[151] = din[ 6] ^ din[ 7] ^ din[ 0] ^ din[ 2] ^ din[ 8]; + dout[150] = din[ 5] ^ din[ 6] ^ din[ 8] ^ din[ 1] ^ din[ 4] ^ din[ 7]; + dout[149] = din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 0] ^ din[ 3] ^ din[ 6]; + dout[148] = din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 2] ^ din[ 5]; + dout[147] = din[ 2] ^ din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 1]; + dout[146] = din[ 1] ^ din[ 4] ^ din[ 3] ^ din[ 6] ^ din[ 0]; + dout[145] = din[ 0] ^ din[ 3] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[ 4]; + dout[144] = din[ 8] ^ din[ 2] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[143] = din[ 7] ^ din[ 1] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[142] = din[ 6] ^ din[ 0] ^ din[ 8] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[141] = din[ 5] ^ din[ 8] ^ din[ 7] ^ din[ 3] ^ din[ 0]; + dout[140] = din[ 7] ^ din[ 6] ^ din[ 2] ^ din[ 8]; + dout[139] = din[ 6] ^ din[ 5] ^ din[ 1] ^ din[ 7]; + dout[138] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6]; + dout[137] = din[ 3] ^ din[ 8] ^ din[ 5]; + dout[136] = din[ 2] ^ din[ 4] ^ din[ 7]; + dout[135] = din[ 1] ^ din[ 3] ^ din[ 6]; + dout[134] = din[ 0] ^ din[ 2] ^ din[ 5]; + dout[133] = din[ 8] ^ din[ 1]; + dout[132] = din[ 7] ^ din[ 0]; + dout[131] = din[ 6] ^ din[ 8] ^ din[ 4]; + dout[130] = din[ 5] ^ din[ 7] ^ din[ 3]; + dout[129] = din[ 4] ^ din[ 6] ^ din[ 2]; + dout[128] = din[ 3] ^ din[ 5] ^ din[ 1]; + dout[127] = din[ 2] ^ din[ 4] ^ din[ 0]; + dout[126] = din[ 1] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[125] = din[ 0] ^ din[ 2] ^ din[ 7] ^ din[ 3]; + dout[124] = din[ 8] ^ din[ 1] ^ din[ 4] ^ din[ 6] ^ din[ 2]; + dout[123] = din[ 7] ^ din[ 0] ^ din[ 3] ^ din[ 5] ^ din[ 1]; + dout[122] = din[ 6] ^ din[ 8] ^ din[ 2] ^ din[ 0]; + dout[121] = din[ 5] ^ din[ 7] ^ din[ 1] ^ din[ 8] ^ din[ 4]; + dout[120] = din[ 4] ^ din[ 6] ^ din[ 0] ^ din[ 7] ^ din[ 3]; + dout[119] = din[ 3] ^ din[ 5] ^ din[ 8] ^ din[ 4] ^ din[ 6] ^ din[ 2]; + dout[118] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1]; + dout[117] = din[ 1] ^ din[ 3] ^ din[ 4] ^ din[ 6] ^ din[ 2] ^ din[ 0]; + dout[116] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 8] ^ din[ 4]; + dout[115] = din[ 8] ^ din[ 1] ^ din[ 2] ^ din[ 0] ^ din[ 7] ^ din[ 3]; + dout[114] = din[ 7] ^ din[ 0] ^ din[ 1] ^ din[ 8] ^ din[ 4] ^ din[ 6] ^ din[ 2]; + dout[113] = din[ 6] ^ din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1]; + dout[112] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 6] ^ din[ 2] ^ din[ 0]; + dout[111] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 5] ^ din[ 1] ^ din[ 8]; + dout[110] = din[ 5] ^ din[ 4] ^ din[ 6] ^ din[ 1] ^ din[ 0] ^ din[ 7]; + dout[109] = din[ 3] ^ din[ 5] ^ din[ 0] ^ din[ 8] ^ din[ 6]; + dout[108] = din[ 2] ^ din[ 8] ^ din[ 7] ^ din[ 5]; + dout[107] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[ 6]; + dout[106] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 5]; + dout[105] = din[ 8] ^ din[ 2] ^ din[ 5]; + dout[104] = din[ 4] ^ din[ 7] ^ din[ 1]; + dout[103] = din[ 3] ^ din[ 6] ^ din[ 0]; + dout[102] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[ 4]; + dout[101] = din[ 4] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[100] = din[ 3] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[ 99] = din[ 2] ^ din[ 8] ^ din[ 5] ^ din[ 4] ^ din[ 1]; + dout[ 98] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[ 3] ^ din[ 0]; + dout[ 97] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 2] ^ din[ 8] ^ din[ 4]; + dout[ 96] = din[ 8] ^ din[ 2] ^ din[ 5] ^ din[ 4] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[ 95] = din[ 4] ^ din[ 7] ^ din[ 1] ^ din[ 3] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[ 94] = din[ 3] ^ din[ 6] ^ din[ 0] ^ din[ 2] ^ din[ 8] ^ din[ 5] ^ din[ 4] ^ din[ 1]; + dout[ 93] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[ 1] ^ din[ 7] ^ din[ 3] ^ din[ 0]; + dout[ 92] = din[ 1] ^ din[ 7] ^ din[ 0] ^ din[ 6] ^ din[ 2] ^ din[ 8]; + dout[ 91] = din[ 0] ^ din[ 6] ^ din[ 8] ^ din[ 5] ^ din[ 4] ^ din[ 1] ^ din[ 7]; + dout[ 90] = din[ 8] ^ din[ 5] ^ din[ 7] ^ din[ 3] ^ din[ 0] ^ din[ 6]; + dout[ 89] = din[ 7] ^ din[ 6] ^ din[ 2] ^ din[ 8] ^ din[ 5]; + dout[ 88] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 1] ^ din[ 7]; + dout[ 87] = din[ 5] ^ din[ 4] ^ din[ 3] ^ din[ 0] ^ din[ 6]; + dout[ 86] = din[ 3] ^ din[ 2] ^ din[ 8] ^ din[ 5]; + dout[ 85] = din[ 2] ^ din[ 4] ^ din[ 1] ^ din[ 7]; + dout[ 84] = din[ 1] ^ din[ 3] ^ din[ 0] ^ din[ 6]; + dout[ 83] = din[ 0] ^ din[ 2] ^ din[ 8] ^ din[ 4] ^ din[ 5]; + dout[ 82] = din[ 8] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[ 81] = din[ 7] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[ 80] = din[ 6] ^ din[ 8] ^ din[ 5] ^ din[ 4] ^ din[ 1]; + dout[ 79] = din[ 4] ^ din[ 5] ^ din[ 7] ^ din[ 3] ^ din[ 0]; + dout[ 78] = din[ 3] ^ din[ 6] ^ din[ 2] ^ din[ 8]; + dout[ 77] = din[ 2] ^ din[ 5] ^ din[ 1] ^ din[ 7]; + dout[ 76] = din[ 4] ^ din[ 1] ^ din[ 0] ^ din[ 6]; + dout[ 75] = din[ 3] ^ din[ 0] ^ din[ 8] ^ din[ 5] ^ din[ 4]; + dout[ 74] = din[ 2] ^ din[ 8] ^ din[ 7] ^ din[ 3]; + dout[ 73] = din[ 1] ^ din[ 7] ^ din[ 6] ^ din[ 2]; + dout[ 72] = din[ 0] ^ din[ 6] ^ din[ 5] ^ din[ 1]; + dout[ 71] = din[ 8] ^ din[ 5] ^ din[ 0]; + dout[ 70] = din[ 7] ^ din[ 8]; + dout[ 69] = din[ 6] ^ din[ 7]; + dout[ 68] = din[ 5] ^ din[ 6]; + dout[ 67] = din[ 4] ^ din[ 5]; + dout[ 66] = din[ 3] ^ din[ 4]; + dout[ 65] = din[ 2] ^ din[ 3]; + dout[ 64] = din[ 1] ^ din[ 2]; + dout[ 63] = din[ 0] ^ din[ 1]; + dout[ 62] = din[ 8] ^ din[ 0] ^ din[ 4]; + dout[ 61] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 4]; + dout[ 60] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 3]; + dout[ 59] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 2]; + dout[ 58] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 1]; + dout[ 57] = din[ 3] ^ din[ 8] ^ din[ 0]; + dout[ 56] = din[ 2] ^ din[ 7] ^ din[ 8] ^ din[ 4]; + dout[ 55] = din[ 1] ^ din[ 6] ^ din[ 7] ^ din[ 3]; + dout[ 54] = din[ 0] ^ din[ 5] ^ din[ 6] ^ din[ 2]; + dout[ 53] = din[ 8] ^ din[ 5] ^ din[ 1]; + dout[ 52] = din[ 7] ^ din[ 4] ^ din[ 0]; + dout[ 51] = din[ 6] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[ 50] = din[ 5] ^ din[ 2] ^ din[ 7] ^ din[ 3]; + dout[ 49] = din[ 4] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[ 48] = din[ 3] ^ din[ 0] ^ din[ 5] ^ din[ 1]; + dout[ 47] = din[ 2] ^ din[ 8] ^ din[ 0]; + dout[ 46] = din[ 1] ^ din[ 7] ^ din[ 8] ^ din[ 4]; + dout[ 45] = din[ 0] ^ din[ 6] ^ din[ 7] ^ din[ 3]; + dout[ 44] = din[ 8] ^ din[ 5] ^ din[ 4] ^ din[ 6] ^ din[ 2]; + dout[ 43] = din[ 7] ^ din[ 4] ^ din[ 3] ^ din[ 5] ^ din[ 1]; + dout[ 42] = din[ 6] ^ din[ 3] ^ din[ 4] ^ din[ 2] ^ din[ 0]; + dout[ 41] = din[ 5] ^ din[ 2] ^ din[ 3] ^ din[ 1] ^ din[ 8] ^ din[ 4]; + dout[ 40] = din[ 4] ^ din[ 1] ^ din[ 2] ^ din[ 0] ^ din[ 7] ^ din[ 3]; + dout[ 39] = din[ 3] ^ din[ 0] ^ din[ 1] ^ din[ 8] ^ din[ 4] ^ din[ 6] ^ din[ 2]; + dout[ 38] = din[ 2] ^ din[ 8] ^ din[ 0] ^ din[ 7] ^ din[ 4] ^ din[ 3] ^ din[ 5] ^ din[ 1]; + dout[ 37] = din[ 1] ^ din[ 7] ^ din[ 8] ^ din[ 6] ^ din[ 3] ^ din[ 2] ^ din[ 0]; + dout[ 36] = din[ 0] ^ din[ 6] ^ din[ 7] ^ din[ 5] ^ din[ 2] ^ din[ 1] ^ din[ 8] ^ din[ 4]; + dout[ 35] = din[ 8] ^ din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 0] ^ din[ 7] ^ din[ 3]; + dout[ 34] = din[ 7] ^ din[ 5] ^ din[ 0] ^ din[ 8] ^ din[ 6] ^ din[ 2]; + dout[ 33] = din[ 6] ^ din[ 8] ^ din[ 7] ^ din[ 5] ^ din[ 1]; + dout[ 32] = din[ 5] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 0]; + dout[ 31] = din[ 3] ^ din[ 6] ^ din[ 5] ^ din[ 8]; + dout[ 30] = din[ 4] ^ din[ 2] ^ din[ 5] ^ din[ 7]; + dout[ 29] = din[ 4] ^ din[ 3] ^ din[ 1] ^ din[ 6]; + dout[ 28] = din[ 3] ^ din[ 2] ^ din[ 0] ^ din[ 5]; + dout[ 27] = din[ 2] ^ din[ 1] ^ din[ 8]; + dout[ 26] = din[ 1] ^ din[ 0] ^ din[ 7]; + dout[ 25] = din[ 0] ^ din[ 8] ^ din[ 6] ^ din[ 4]; + dout[ 24] = din[ 8] ^ din[ 7] ^ din[ 5] ^ din[ 4] ^ din[ 3]; + dout[ 23] = din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 3] ^ din[ 2]; + dout[ 22] = din[ 3] ^ din[ 6] ^ din[ 5] ^ din[ 2] ^ din[ 1]; + dout[ 21] = din[ 4] ^ din[ 2] ^ din[ 5] ^ din[ 1] ^ din[ 0]; + dout[ 20] = din[ 3] ^ din[ 1] ^ din[ 0] ^ din[ 8]; + dout[ 19] = din[ 2] ^ din[ 0] ^ din[ 8] ^ din[ 7] ^ din[ 4]; + dout[ 18] = din[ 1] ^ din[ 8] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 3]; + dout[ 17] = din[ 0] ^ din[ 7] ^ din[ 3] ^ din[ 6] ^ din[ 5] ^ din[ 2]; + dout[ 16] = din[ 8] ^ din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1]; + dout[ 15] = din[ 7] ^ din[ 5] ^ din[ 4] ^ din[ 1] ^ din[ 0]; + dout[ 14] = din[ 6] ^ din[ 3] ^ din[ 0] ^ din[ 8]; + dout[ 13] = din[ 5] ^ din[ 2] ^ din[ 8] ^ din[ 4] ^ din[ 7]; + dout[ 12] = din[ 4] ^ din[ 1] ^ din[ 7] ^ din[ 3] ^ din[ 6]; + dout[ 11] = din[ 3] ^ din[ 0] ^ din[ 6] ^ din[ 2] ^ din[ 5]; + dout[ 10] = din[ 2] ^ din[ 8] ^ din[ 5] ^ din[ 1]; + dout[ 9] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[ 0]; + dout[ 8] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4]; + dout[ 7] = din[ 8] ^ din[ 2] ^ din[ 5] ^ din[ 4] ^ din[ 7] ^ din[ 3]; + dout[ 6] = din[ 7] ^ din[ 4] ^ din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 2]; + dout[ 5] = din[ 6] ^ din[ 3] ^ din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 1]; + dout[ 4] = din[ 5] ^ din[ 2] ^ din[ 8] ^ din[ 1] ^ din[ 0]; + dout[ 3] = din[ 1] ^ din[ 7] ^ din[ 0] ^ din[ 8]; + dout[ 2] = din[ 0] ^ din[ 6] ^ din[ 8] ^ din[ 4] ^ din[ 7]; + dout[ 1] = din[ 8] ^ din[ 5] ^ din[ 7] ^ din[ 4] ^ din[ 3] ^ din[ 6]; + dout[ 0] = din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 3] ^ din[ 2] ^ din[ 5]; + pn9 = dout; + end + endfunction + + // pn sequence select + + assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn; + + always @(posedge adc_clk) begin + adc_pn_data_in <= { ~adc_data[ 11], adc_data[ 10: 0], + ~adc_data[ 23], adc_data[ 22: 12], + ~adc_data[ 35], adc_data[ 34: 24], + ~adc_data[ 47], adc_data[ 46: 36], + ~adc_data[ 59], adc_data[ 58: 48], + ~adc_data[ 71], adc_data[ 70: 60], + ~adc_data[ 83], adc_data[ 82: 72], + ~adc_data[ 95], adc_data[ 94: 84], + ~adc_data[107], adc_data[106: 96], + ~adc_data[119], adc_data[118:108], + ~adc_data[131], adc_data[130:120], + ~adc_data[143], adc_data[142:132], + ~adc_data[155], adc_data[154:144], + ~adc_data[167], adc_data[166:156], + ~adc_data[179], adc_data[178:168], + ~adc_data[191], adc_data[190:180]}; + if (adc_pnseq_sel == 4'd0) begin + adc_pn_data_pn <= pn9(adc_pn_data_pn_s); + end else begin + adc_pn_data_pn <= pn23(adc_pn_data_pn_s); + end + end + + // pn oos & pn error + + ad_pnmon #( + .DATA_WIDTH(192) + ) i_pnmon ( + .adc_clk (adc_clk), + .adc_valid_in (1'b1), + .adc_data_in (adc_pn_data_in), + .adc_data_pn (adc_pn_data_pn), + .adc_pn_oos (adc_pn_oos), + .adc_pn_err (adc_pn_err)); + +endmodule diff --git a/adi_library/axi_ad9625/bd/bd.tcl b/adi_library/axi_ad9625/bd/bd.tcl new file mode 100644 index 00000000..dceb9498 --- /dev/null +++ b/adi_library/axi_ad9625/bd/bd.tcl @@ -0,0 +1,47 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + DEV_PACKAGE \ + SPEED_GRADE \ + FPGA_FAMILY \ + FPGA_TECHNOLOGY" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/axi_ad9625/component.xml b/adi_library/axi_ad9625/component.xml new file mode 100644 index 00000000..515f9866 --- /dev/null +++ b/adi_library/axi_ad9625/component.xml @@ -0,0 +1,1247 @@ + + + analog.com + user + axi_ad9625 + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + rx_clk + + + + + + + CLK + + + rx_clk + + + + + + adc_clk + + + + + + + CLK + + + adc_clk + + + + + + ASSOCIATED_RESET + adc_rst + + + + + adc_rst + + + + + + + RST + + + adc_rst + + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_ad9625 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 195caded + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_ad9625 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 881c06b9 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 804b322e + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + + + rx_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_sof + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + rx_data + + in + + 255 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + rx_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_rst + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data + + out + + 255 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_dovf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_sref + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_raddr_in + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_raddr_out + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + DELAY_REFCLK_FREQUENCY + Delay Refclk Frequency + 200 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_00ecfe9a + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + + + choice_pairs_19f99f31 + 0 + 10 + 11 + 12 + 13 + 14 + 20 + 21 + 22 + 23 + 24 + 25 + 30 + + + choice_pairs_28f798a2 + 0 + 1 + 2 + 3 + 4 + + + choice_pairs_fc01a186 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../xilinx/common/up_clock_mon_constr.xdc + xdc + + + ../common/ad_datafmt.v + verilogSource + + + ../common/ad_mem.v + verilogSource + + + ../common/ad_pnmon.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../common/ad_xcvr_rx_if.v + verilogSource + + + axi_ad9625_channel.v + verilogSource + + + axi_ad9625_if.v + verilogSource + + + axi_ad9625_pnmon.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad9625.v + verilogSource + CHECKSUM_2272f51d + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_datafmt.v + verilogSource + + + ../common/ad_mem.v + verilogSource + + + ../common/ad_pnmon.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../common/ad_xcvr_rx_if.v + verilogSource + + + axi_ad9625_channel.v + verilogSource + + + axi_ad9625_if.v + verilogSource + + + axi_ad9625_pnmon.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad9625.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_ad9625_v1_0.tcl + tclSource + CHECKSUM_243d7c29 + XGUI_VERSION_2 + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + axi_ad9625_v1_0 + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + DELAY_REFCLK_FREQUENCY + Delay Refclk Frequency + 200 + + + Component_Name + axi_ad9625_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_ad9625_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:42:01Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_ad9625/temporary_case_dependencies.mk b/adi_library/axi_ad9625/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/axi_ad9625/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/axi_ad9625/xgui/axi_ad9625_v1_0.tcl b/adi_library/axi_ad9625/xgui/axi_ad9625_v1_0.tcl new file mode 100644 index 00000000..ca987acc --- /dev/null +++ b/adi_library/axi_ad9625/xgui/axi_ad9625_v1_0.tcl @@ -0,0 +1,103 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DELAY_REFCLK_FREQUENCY" -parent ${Page_0} + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } { + # Procedure called to update DELAY_REFCLK_FREQUENCY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } { + # Procedure called to validate DELAY_REFCLK_FREQUENCY + return true +} + +proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to validate DEV_PACKAGE + return true +} + +proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to validate FPGA_FAMILY + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to validate SPEED_GRADE + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY} +} + +proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE} +} + +proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE} +} + +proc update_MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY { MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY PARAM_VALUE.DELAY_REFCLK_FREQUENCY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DELAY_REFCLK_FREQUENCY}] ${MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY} +} + diff --git a/adi_library/axi_ad9671/Makefile b/adi_library/axi_ad9671/Makefile new file mode 100644 index 00000000..eb2ca3dd --- /dev/null +++ b/adi_library/axi_ad9671/Makefile @@ -0,0 +1,37 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_ad9671 + +GENERIC_DEPS += ../common/ad_datafmt.v +GENERIC_DEPS += ../common/ad_mem.v +GENERIC_DEPS += ../common/ad_pnmon.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/ad_xcvr_rx_if.v +GENERIC_DEPS += ../common/up_adc_channel.v +GENERIC_DEPS += ../common/up_adc_common.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_ad9671.v +GENERIC_DEPS += axi_ad9671_channel.v +GENERIC_DEPS += axi_ad9671_if.v +GENERIC_DEPS += axi_ad9671_pnmon.v + +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_ad9671_ip.tcl + +INTEL_DEPS += ../intel/common/up_clock_mon_constr.sdc +INTEL_DEPS += ../intel/common/up_rst_constr.sdc +INTEL_DEPS += ../intel/common/up_xfer_cntrl_constr.sdc +INTEL_DEPS += ../intel/common/up_xfer_status_constr.sdc +INTEL_DEPS += axi_ad9671_hw.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_ad9671/axi_ad9671.v b/adi_library/axi_ad9671/axi_ad9671.v new file mode 100644 index 00000000..1872d7a3 --- /dev/null +++ b/adi_library/axi_ad9671/axi_ad9671.v @@ -0,0 +1,324 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9671 #( + + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter QUAD_OR_DUAL_N = 1 +) ( + + // jesd interface + // rx_clk is (line-rate/40) + + input rx_clk, + input [ 3:0] rx_sof, + input rx_valid, + input [(64*QUAD_OR_DUAL_N)+63:0] rx_data, + output rx_ready, + + // dma interface + + output adc_clk, + output [ 7:0] adc_valid, + output [ 7:0] adc_enable, + output [127:0] adc_data, + input adc_dovf, + input adc_sync_in, + output adc_sync_out, + input [ 3:0] adc_raddr_in, + output [ 3:0] adc_raddr_out, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [ 15:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [ 31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [ 15:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [ 31:0] s_axi_rdata, + input s_axi_rready +); + + // internal registers + + reg up_status_pn_err = 'd0; + reg up_status_pn_oos = 'd0; + reg up_status_or = 'd0; + reg [ 31:0] up_rdata = 'd0; + reg up_rack = 'd0; + reg up_wack = 'd0; + + // internal clocks & resets + + wire adc_rst; + wire up_rstn; + wire up_clk; + + // internal signals + + wire adc_status_s; + wire adc_sync_status_s; + wire adc_valid_s; + wire [ 15:0] adc_data_s[7:0]; + wire [ 7:0] adc_or_s; + wire [ 7:0] up_adc_pn_err_s; + wire [ 7:0] up_adc_pn_oos_s; + wire [ 7:0] up_adc_or_s; + wire up_wreq_s; + wire [ 13:0] up_waddr_s; + wire [ 31:0] up_wdata_s; + wire up_rreq_s; + wire [ 13:0] up_raddr_s; + wire [ 31:0] up_rdata_s[8:0]; + wire up_rack_s[8:0]; + wire up_wack_s[8:0]; + wire [ 31:0] adc_start_code; + wire adc_sync; + + // signal name changes + + assign rx_ready = 1'b1; + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_status_pn_err <= 'd0; + up_status_pn_oos <= 'd0; + up_status_or <= 'd0; + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_status_pn_err <= | up_adc_pn_err_s; + up_status_pn_oos <= | up_adc_pn_oos_s; + up_status_or <= | up_adc_or_s; + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] | + up_rdata_s[4] | up_rdata_s[5] | up_rdata_s[6] | up_rdata_s[7] | up_rdata_s[8]; + up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3] | + up_rack_s[4] | up_rack_s[5] | up_rack_s[6] | up_rack_s[7] | up_rack_s[8]; + up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3] | + up_wack_s[4] | up_wack_s[5] | up_wack_s[6] | up_wack_s[7] | up_wack_s[8]; + end + end + + // main (device interface) + + axi_ad9671_if #( + .QUAD_OR_DUAL_N (QUAD_OR_DUAL_N), + .ID (ID) + ) i_if ( + .rx_clk (rx_clk), + .rx_data (rx_data), + .rx_sof (rx_sof), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_valid (adc_valid_s), + .adc_data_a (adc_data_s[0]), + .adc_or_a (adc_or_s[0]), + .adc_data_b (adc_data_s[1]), + .adc_or_b (adc_or_s[1]), + .adc_data_c (adc_data_s[2]), + .adc_or_c (adc_or_s[2]), + .adc_data_d (adc_data_s[3]), + .adc_or_d (adc_or_s[3]), + .adc_data_e (adc_data_s[4]), + .adc_or_e (adc_or_s[4]), + .adc_data_f (adc_data_s[5]), + .adc_or_f (adc_or_s[5]), + .adc_data_g (adc_data_s[6]), + .adc_or_g (adc_or_s[6]), + .adc_data_h (adc_data_s[7]), + .adc_or_h (adc_or_s[7]), + .adc_start_code (adc_start_code), + .adc_sync (adc_sync), + .adc_sync_in (adc_sync_in), + .adc_sync_out (adc_sync_out), + .adc_sync_status (adc_sync_status_s), + .adc_status (adc_status_s), + .adc_raddr_in (adc_raddr_in), + .adc_raddr_out (adc_raddr_out)); + + // channels + + genvar n; + generate + for (n = 0; n < 8; n = n + 1) begin: g_channel + axi_ad9671_channel #( + .CHANNEL_ID(n) + ) i_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_valid (adc_valid_s), + .adc_data (adc_data_s[n]), + .adc_or (adc_or_s[n]), + .adc_dfmt_valid (adc_valid[n]), + .adc_dfmt_data (adc_data[(n*16)+15:(n*16)]), + .adc_enable (adc_enable[n]), + .up_adc_pn_err (up_adc_pn_err_s[n]), + .up_adc_pn_oos (up_adc_pn_oos_s[n]), + .up_adc_or (up_adc_or_s[n]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[n]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[n]), + .up_rack (up_rack_s[n])); + end + endgenerate + + // common processor control + + up_adc_common #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE) + ) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (adc_status_s), + .adc_sync_status (adc_sync_status_s), + .adc_status_ovf (adc_dovf), + .adc_clk_ratio (32'd1), + .adc_start_code (adc_start_code), + .adc_sref_sync (), + .adc_sync (adc_sync), + .adc_ext_sync_arm (), + .adc_ext_sync_disarm (), + .adc_ext_sync_manual_req (), + .adc_num_lanes (), + .adc_custom_control (), + .adc_crc_enable (), + .adc_sdr_ddr_n (), + .adc_symb_op (), + .adc_symb_8_16b (), + .up_pps_rcounter ('d0), + .up_pps_status ('d0), + .up_pps_irq_mask (), + .up_adc_r1_mode (), + .up_adc_ce (), + .up_status_pn_err (up_status_pn_err), + .up_status_pn_oos (up_status_pn_oos), + .up_status_or (up_status_or), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .adc_config_wr (), + .adc_config_ctrl (), + .adc_config_rd ('d0), + .adc_ctrl_status ('d0), + .up_usr_chanmax_out (), + .up_usr_chanmax_in (8'd7), + .up_adc_gpio_in (32'd0), + .up_adc_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[8]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[8]), + .up_rack (up_rack_s[8])); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ad9671/axi_ad9671.xpr b/adi_library/axi_ad9671/axi_ad9671.xpr new file mode 100644 index 00000000..94f3234a --- /dev/null +++ b/adi_library/axi_ad9671/axi_ad9671.xpr @@ -0,0 +1,528 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_ad9671/axi_ad9671_channel.v b/adi_library/axi_ad9671/axi_ad9671_channel.v new file mode 100644 index 00000000..5ecb0c0d --- /dev/null +++ b/adi_library/axi_ad9671/axi_ad9671_channel.v @@ -0,0 +1,157 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// ADC channel- + +`timescale 1ns/100ps + +module axi_ad9671_channel #( + + parameter CHANNEL_ID = 0 +) ( + + // adc interface + + input adc_clk, + input adc_rst, + input adc_valid, + input [15:0] adc_data, + input adc_or, + + // channel interface + + output adc_dfmt_valid, + output [15:0] adc_dfmt_data, + output adc_enable, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // internal signals + + wire adc_dfmt_se_s; + wire adc_dfmt_type_s; + wire adc_dfmt_enable_s; + wire [ 3:0] adc_pnseq_sel_s; + wire adc_pn_err_s; + wire adc_pn_oos_s; + + // instantiations + + axi_ad9671_pnmon i_pnmon ( + .adc_clk (adc_clk), + .adc_valid (adc_valid), + .adc_data (adc_data), + .adc_pn_oos (adc_pn_oos_s), + .adc_pn_err (adc_pn_err_s), + .adc_pnseq_sel (adc_pnseq_sel_s)); + + ad_datafmt #( + .DATA_WIDTH(16) + ) i_ad_datafmt ( + .clk (adc_clk), + .valid (adc_valid), + .data (adc_data), + .valid_out (adc_dfmt_valid), + .data_out (adc_dfmt_data), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + + up_adc_channel #( + .CHANNEL_ID(CHANNEL_ID) + ) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (), + .adc_dcfilt_enb (), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_dcfilt_offset (), + .adc_dcfilt_coeff (), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_data_sel (), + .adc_pn_err (adc_pn_err_s), + .adc_pn_oos (adc_pn_oos_s), + .adc_or (adc_or), + .adc_read_data ('d0), + .adc_status_header ('d0), + .adc_crc_err ('d0), + .up_adc_pn_err (up_adc_pn_err), + .up_adc_pn_oos (up_adc_pn_oos), + .up_adc_or (up_adc_or), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ad9671/axi_ad9671_hw.tcl b/adi_library/axi_ad9671/axi_ad9671_hw.tcl new file mode 100644 index 00000000..ce00aed9 --- /dev/null +++ b/adi_library/axi_ad9671/axi_ad9671_hw.tcl @@ -0,0 +1,96 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +package require quartus::device + +source ../../scripts/adi_env.tcl +source ../scripts/adi_ip_intel.tcl + +set_module_property NAME axi_ad9671 +set_module_property DESCRIPTION "AXI AD9671 Interface" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME axi_ad9671 +set_module_property VALIDATION_CALLBACK info_param_validate + +# files + +add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" +set_fileset_property quartus_synth TOP_LEVEL axi_ad9671 +add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/ad_rst.v +add_fileset_file ad_pnmon.v VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v +add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v +add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v +add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v +add_fileset_file up_xfer_status.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_status.v +add_fileset_file up_clock_mon.v VERILOG PATH $ad_hdl_dir/library/common/up_clock_mon.v +add_fileset_file up_adc_common.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_common.v +add_fileset_file up_adc_channel.v VERILOG PATH $ad_hdl_dir/library/common/up_adc_channel.v +add_fileset_file ad_xcvr_rx_if.v VERILOG PATH $ad_hdl_dir/library/common/ad_xcvr_rx_if.v +add_fileset_file ad_mem.v VERILOG PATH $ad_hdl_dir/library/common/ad_mem.v +add_fileset_file axi_ad9671_pnmon.v VERILOG PATH axi_ad9671_pnmon.v +add_fileset_file axi_ad9671_if.v VERILOG PATH axi_ad9671_if.v +add_fileset_file axi_ad9671_channel.v VERILOG PATH axi_ad9671_channel.v +add_fileset_file axi_ad9671.v VERILOG PATH axi_ad9671.v TOP_LEVEL_FILE +add_fileset_file up_xfer_cntrl_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc +add_fileset_file up_xfer_status_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc +add_fileset_file up_clock_mon_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc +add_fileset_file up_rst_constr.sdc SDC PATH $ad_hdl_dir/library/intel/common/up_rst_constr.sdc + +# parameters + +add_parameter ID INTEGER 0 +set_parameter_property ID DEFAULT_VALUE 0 +set_parameter_property ID DISPLAY_NAME ID +set_parameter_property ID UNITS None +set_parameter_property ID HDL_PARAMETER true + +add_parameter QUAD_OR_DUAL_N INTEGER 0 +set_parameter_property QUAD_OR_DUAL_N DEFAULT_VALUE 1 +set_parameter_property QUAD_OR_DUAL_N DISPLAY_NAME QUAD_OR_DUAL_N +set_parameter_property QUAD_OR_DUAL_N UNITS None +set_parameter_property QUAD_OR_DUAL_N HDL_PARAMETER true + +adi_add_auto_fpga_spec_params + +# axi4 slave + +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn + +# transceiver interface + +ad_interface clock rx_clk input 1 +ad_interface signal rx_sof input 4 export + +add_interface if_rx_data avalon_streaming sink +add_interface_port if_rx_data rx_data data input 64*QUAD_OR_DUAL_N+64 +add_interface_port if_rx_data rx_valid valid input 1 +add_interface_port if_rx_data rx_ready ready output 1 +set_interface_property if_rx_data associatedClock if_rx_clk +set_interface_property if_rx_data dataBitsPerSymbol 64 + +add_interface if_sync conduit end +set_interface_property if_sync associatedClock if_clk +add_interface_port if_sync adc_sync_in sync_in Input 1 +add_interface_port if_sync adc_sync_out sync_out Output 1 +add_interface_port if_sync adc_raddr_in raddr_in Input 4 +add_interface_port if_sync adc_raddr_out raddr_out Output 4 + +# dma interface + +ad_interface clock adc_clk output 1 +ad_interface reset adc_rst output 1 if_adc_clk + +add_interface adc_ch conduit end +add_interface_port adc_ch adc_enable enable Output 8 +add_interface_port adc_ch adc_valid valid Output 8 +add_interface_port adc_ch adc_data data Output 128 + +set_interface_property adc_ch associatedClock if_rx_clk +set_interface_property adc_ch associatedReset none + +ad_interface signal adc_dovf input 1 ovf + diff --git a/adi_library/axi_ad9671/axi_ad9671_if.v b/adi_library/axi_ad9671/axi_ad9671_if.v new file mode 100644 index 00000000..7644f339 --- /dev/null +++ b/adi_library/axi_ad9671/axi_ad9671_if.v @@ -0,0 +1,216 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9671_if #( + + parameter QUAD_OR_DUAL_N = 1, + parameter ID = 0 +) ( + + // jesd interface + // rx_clk is (line-rate/40) + + input rx_clk, + input [ 3:0] rx_sof, + input [(64*QUAD_OR_DUAL_N)+63:0] rx_data, + + // adc data output + + output adc_clk, + input adc_rst, + output adc_valid, + output reg [ 15:0] adc_data_a, + output adc_or_a, + output reg [ 15:0] adc_data_b, + output adc_or_b, + output reg [ 15:0] adc_data_c, + output adc_or_c, + output reg [ 15:0] adc_data_d, + output adc_or_d, + output reg [ 15:0] adc_data_e, + output adc_or_e, + output reg [ 15:0] adc_data_f, + output adc_or_f, + output reg [ 15:0] adc_data_g, + output adc_or_g, + output reg [ 15:0] adc_data_h, + output adc_or_h, + input [ 31:0] adc_start_code, + input adc_sync_in, + output adc_sync_out, + input adc_sync, + output reg adc_sync_status, + output reg adc_status, + input [ 3:0] adc_raddr_in, + output reg [ 3:0] adc_raddr_out +); + + // internal wires + + wire [(2*QUAD_OR_DUAL_N)+1:0] rx_sof_s; + wire [(64*QUAD_OR_DUAL_N)+63:0] rx_data_s; + wire [127:0] adc_wdata; + wire [127:0] adc_rdata; + wire [ 15:0] adc_data_a_s; + wire [ 15:0] adc_data_b_s; + wire [ 15:0] adc_data_c_s; + wire [ 15:0] adc_data_d_s; + wire [ 15:0] adc_data_e_s; + wire [ 15:0] adc_data_f_s; + wire [ 15:0] adc_data_g_s; + wire [ 15:0] adc_data_h_s; + wire [ 3:0] adc_raddr_s; + wire adc_sync_s; + + // internal registers + + reg int_valid = 'd0; + reg [127:0] int_data = 'd0; + reg rx_sof_d = 'd0; + reg [ 3:0] adc_waddr = 'd0; + + // adc clock & valid + + assign adc_clk = rx_clk; + assign adc_valid = int_valid; + assign adc_sync_out = adc_sync; + + assign adc_or_a = 'd0; + assign adc_or_b = 'd0; + assign adc_or_c = 'd0; + assign adc_or_d = 'd0; + assign adc_or_e = 'd0; + assign adc_or_f = 'd0; + assign adc_or_g = 'd0; + assign adc_or_h = 'd0; + + assign adc_data_a_s = {int_data[ 7: 0], int_data[ 15: 8]}; + assign adc_data_b_s = {int_data[ 23: 16], int_data[ 31: 24]}; + assign adc_data_c_s = {int_data[ 39: 32], int_data[ 47: 40]}; + assign adc_data_d_s = {int_data[ 55: 48], int_data[ 63: 56]}; + assign adc_data_e_s = {int_data[ 71: 64], int_data[ 79: 72]}; + assign adc_data_f_s = {int_data[ 87: 80], int_data[ 95: 88]}; + assign adc_data_g_s = {int_data[103: 96], int_data[111:104]}; + assign adc_data_h_s = {int_data[119:112], int_data[127:120]}; + + assign adc_wdata = {adc_data_h_s, adc_data_g_s, adc_data_f_s, adc_data_e_s, + adc_data_d_s, adc_data_c_s, adc_data_b_s, adc_data_a_s}; + + assign adc_raddr_s = (ID == 0) ? adc_raddr_out : adc_raddr_in; + assign adc_sync_s = (ID == 0) ? adc_sync_out : adc_sync_in; + + always @(posedge rx_clk) begin + adc_data_a <= adc_rdata[ 15: 0]; + adc_data_b <= adc_rdata[ 31: 16]; + adc_data_c <= adc_rdata[ 47: 32]; + adc_data_d <= adc_rdata[ 63: 48]; + adc_data_e <= adc_rdata[ 79: 64]; + adc_data_f <= adc_rdata[ 95: 80]; + adc_data_g <= adc_rdata[111: 96]; + adc_data_h <= adc_rdata[127:112]; + end + + always @(posedge rx_clk) begin + if (adc_rst == 1'b1) begin + adc_waddr <= 4'h0; + adc_raddr_out <= 4'h8; + adc_sync_status <= 1'b0; + end else begin + if (adc_data_d_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin + adc_sync_status <= 1'b0; + end else if(adc_sync_s == 1'b1) begin + adc_sync_status <= 1'b1; + end + if (adc_data_d_s == adc_start_code[15:0] && adc_sync_status == 1'b1) begin + adc_waddr <= 4'h0; + adc_raddr_out <= 4'h8; + end else if (int_valid == 1'b1) begin + adc_waddr <= adc_waddr + 1; + adc_raddr_out <= adc_raddr_out + 1; + end + end + end + + always @(posedge rx_clk) begin + if (QUAD_OR_DUAL_N == 1'b1) begin + int_valid <= 1'b1; + int_data <= rx_data_s; + end else begin + rx_sof_d <= &rx_sof_s; + int_valid <= rx_sof_d; + int_data[63:0] <= {rx_data_s[31: 0], int_data[ 63:32]}; + int_data[127:64] <= {rx_data_s[63:32], int_data[127:96]}; + end + end + + always @(posedge rx_clk) begin + if (adc_rst == 1'b1) begin + adc_status <= 1'b0; + end else begin + adc_status <= 1'b1; + end + end + + ad_mem #( + .ADDRESS_WIDTH(4), + .DATA_WIDTH(128) + ) i_mem ( + .clka(rx_clk), + .wea(int_valid), + .addra(adc_waddr), + .dina(adc_wdata), + .clkb(rx_clk), + .reb (1'b1), + .addrb(adc_raddr_s), + .doutb(adc_rdata)); + + // frame-alignment + + genvar n; + + generate + for (n = 0; n < ((2*QUAD_OR_DUAL_N)+2); n = n + 1) begin: g_xcvr_if + ad_xcvr_rx_if i_xcvr_if ( + .rx_clk (rx_clk), + .rx_ip_sof (rx_sof), + .rx_ip_data (rx_data[((n*32)+31):(n*32)]), + .rx_sof (rx_sof_s[n]), + .rx_data (rx_data_s[((n*32)+31):(n*32)])); + end + endgenerate + +endmodule diff --git a/adi_library/axi_ad9671/axi_ad9671_ip.tcl b/adi_library/axi_ad9671/axi_ad9671_ip.tcl new file mode 100644 index 00000000..470f3035 --- /dev/null +++ b/adi_library/axi_ad9671/axi_ad9671_ip.tcl @@ -0,0 +1,48 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_ad9671 +adi_ip_files axi_ad9671 [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/ad_mem.v" \ + "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "axi_ad9671_pnmon.v" \ + "axi_ad9671_channel.v" \ + "axi_ad9671_if.v" \ + "axi_ad9671.v" ] + +adi_ip_properties axi_ad9671 + +adi_init_bd_tcl +adi_ip_bd axi_ad9371 "bd/bd.tcl" + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad9671} [ipx::current_core] + +set_property driver_value 0 [ipx::get_ports *rx_valid* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *sync_in* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *raddr_in* -of_objects [ipx::current_core]] + +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/axi_ad9671/axi_ad9671_pnmon.v b/adi_library/axi_ad9671/axi_ad9671_pnmon.v new file mode 100644 index 00000000..6132b787 --- /dev/null +++ b/adi_library/axi_ad9671/axi_ad9671_pnmon.v @@ -0,0 +1,180 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// PN monitors + +`timescale 1ns/100ps + +module axi_ad9671_pnmon ( + + // adc interface + + input adc_clk, + input adc_valid, + input [15:0] adc_data, + + // pn out of sync and error + + output adc_pn_oos, + output adc_pn_err, + input [ 3:0] adc_pnseq_sel +); + + // internal registers + + reg adc_pn_valid = 'd0; + reg [31:0] adc_pn_data_in = 'd0; + reg [31:0] adc_pn_data_pn = 'd0; + + // internal signals + + wire adc_pn_valid_s; + wire [31:0] adc_pn_data_pn_s; + + // PN23 function + + function [31:0] pn23; + input [31:0] din; + reg [31:0] dout; + begin + dout[31] = din[22] ^ din[17]; + dout[30] = din[21] ^ din[16]; + dout[29] = din[20] ^ din[15]; + dout[28] = din[19] ^ din[14]; + dout[27] = din[18] ^ din[13]; + dout[26] = din[17] ^ din[12]; + dout[25] = din[16] ^ din[11]; + dout[24] = din[15] ^ din[10]; + dout[23] = din[14] ^ din[ 9]; + dout[22] = din[13] ^ din[ 8]; + dout[21] = din[12] ^ din[ 7]; + dout[20] = din[11] ^ din[ 6]; + dout[19] = din[10] ^ din[ 5]; + dout[18] = din[ 9] ^ din[ 4]; + dout[17] = din[ 8] ^ din[ 3]; + dout[16] = din[ 7] ^ din[ 2]; + dout[15] = din[ 6] ^ din[ 1]; + dout[14] = din[ 5] ^ din[ 0]; + dout[13] = din[ 4] ^ din[22] ^ din[17]; + dout[12] = din[ 3] ^ din[21] ^ din[16]; + dout[11] = din[ 2] ^ din[20] ^ din[15]; + dout[10] = din[ 1] ^ din[19] ^ din[14]; + dout[ 9] = din[ 0] ^ din[18] ^ din[13]; + dout[ 8] = din[22] ^ din[12]; + dout[ 7] = din[21] ^ din[11]; + dout[ 6] = din[20] ^ din[10]; + dout[ 5] = din[19] ^ din[ 9]; + dout[ 4] = din[18] ^ din[ 8]; + dout[ 3] = din[17] ^ din[ 7]; + dout[ 2] = din[16] ^ din[ 6]; + dout[ 1] = din[15] ^ din[ 5]; + dout[ 0] = din[14] ^ din[ 4]; + pn23 = dout; + end + endfunction + + // PN9 function + + function [31:0] pn9; + input [31:0] din; + reg [31:0] dout; + begin + dout[31] = din[ 8] ^ din[ 4]; + dout[30] = din[ 7] ^ din[ 3]; + dout[29] = din[ 6] ^ din[ 2]; + dout[28] = din[ 5] ^ din[ 1]; + dout[27] = din[ 4] ^ din[ 0]; + dout[26] = din[ 3] ^ din[ 8] ^ din[ 4]; + dout[25] = din[ 2] ^ din[ 7] ^ din[ 3]; + dout[24] = din[ 1] ^ din[ 6] ^ din[ 2]; + dout[23] = din[ 0] ^ din[ 5] ^ din[ 1]; + dout[22] = din[ 8] ^ din[ 0]; + dout[21] = din[ 7] ^ din[ 8] ^ din[ 4]; + dout[20] = din[ 6] ^ din[ 7] ^ din[ 3]; + dout[19] = din[ 5] ^ din[ 6] ^ din[ 2]; + dout[18] = din[ 4] ^ din[ 5] ^ din[ 1]; + dout[17] = din[ 3] ^ din[ 4] ^ din[ 0]; + dout[16] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[15] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; + dout[14] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[13] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1]; + dout[12] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; + dout[11] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; + dout[10] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[ 9] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[ 8] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; + dout[ 7] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0]; + dout[ 6] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4]; + dout[ 5] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3]; + dout[ 4] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[ 3] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1]; + dout[ 2] = din[ 6] ^ din[ 8] ^ din[ 0]; + dout[ 1] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4]; + dout[ 0] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3]; + pn9 = dout; + end + endfunction + + // pn sequence select + + assign adc_pn_valid_s = adc_valid & adc_pn_valid; + assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn; + + always @(posedge adc_clk) begin + if (adc_valid == 1'b1) begin + adc_pn_valid <= ~adc_pn_valid; + adc_pn_data_in <= {adc_pn_data_in[15:0], ~adc_data[15], adc_data[14:0]}; + end + if (adc_pn_valid_s == 1'b1) begin + if (adc_pnseq_sel == 4'd0) begin + adc_pn_data_pn <= pn9(adc_pn_data_pn_s); + end else begin + adc_pn_data_pn <= pn23(adc_pn_data_pn_s); + end + end + end + + // pn oos & pn err + + ad_pnmon #( + .DATA_WIDTH(32) + ) i_pnmon ( + .adc_clk (adc_clk), + .adc_valid_in (adc_pn_valid_s), + .adc_data_in (adc_pn_data_in), + .adc_data_pn (adc_pn_data_pn), + .adc_pn_oos (adc_pn_oos), + .adc_pn_err (adc_pn_err)); + +endmodule diff --git a/adi_library/axi_ad9671/bd/bd.tcl b/adi_library/axi_ad9671/bd/bd.tcl new file mode 100644 index 00000000..dceb9498 --- /dev/null +++ b/adi_library/axi_ad9671/bd/bd.tcl @@ -0,0 +1,47 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + DEV_PACKAGE \ + SPEED_GRADE \ + FPGA_FAMILY \ + FPGA_TECHNOLOGY" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/axi_ad9671/component.xml b/adi_library/axi_ad9671/component.xml new file mode 100644 index 00000000..d904c52d --- /dev/null +++ b/adi_library/axi_ad9671/component.xml @@ -0,0 +1,1200 @@ + + + analog.com + user + axi_ad9671 + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_ad9671 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 9d552b9e + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_ad9671 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + d3400fb9 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 3945c296 + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + + + rx_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_sof + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + rx_data + + in + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + rx_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data + + out + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_dovf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_sync_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_sync_out + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_raddr_in + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_raddr_out + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + QUAD_OR_DUAL_N + Quad Or Dual N + 1 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_00ecfe9a + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + + + choice_pairs_19f99f31 + 0 + 10 + 11 + 12 + 13 + 14 + 20 + 21 + 22 + 23 + 24 + 25 + 30 + + + choice_pairs_28f798a2 + 0 + 1 + 2 + 3 + 4 + + + choice_pairs_fc01a186 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../xilinx/common/up_clock_mon_constr.xdc + xdc + + + ../common/ad_datafmt.v + verilogSource + + + ../common/ad_mem.v + verilogSource + + + ../common/ad_pnmon.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../common/ad_xcvr_rx_if.v + verilogSource + + + axi_ad9671_channel.v + verilogSource + + + axi_ad9671_if.v + verilogSource + + + axi_ad9671_pnmon.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad9671.v + verilogSource + CHECKSUM_8448a1fc + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_datafmt.v + verilogSource + + + ../common/ad_mem.v + verilogSource + + + ../common/ad_pnmon.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../common/ad_xcvr_rx_if.v + verilogSource + + + axi_ad9671_channel.v + verilogSource + + + axi_ad9671_if.v + verilogSource + + + axi_ad9671_pnmon.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad9671.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_ad9671_v1_0.tcl + tclSource + CHECKSUM_7979ea6f + XGUI_VERSION_2 + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + axi_ad9671_v1_0 + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + QUAD_OR_DUAL_N + Quad Or Dual N + 1 + + + Component_Name + axi_ad9671_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_ad9671_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_ad9671 + 1 + 2024-01-14T03:42:18Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_ad9671/temporary_case_dependencies.mk b/adi_library/axi_ad9671/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/axi_ad9671/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/axi_ad9671/xgui/axi_ad9671_v1_0.tcl b/adi_library/axi_ad9671/xgui/axi_ad9671_v1_0.tcl new file mode 100644 index 00000000..d9abf522 --- /dev/null +++ b/adi_library/axi_ad9671/xgui/axi_ad9671_v1_0.tcl @@ -0,0 +1,103 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "QUAD_OR_DUAL_N" -parent ${Page_0} + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to validate DEV_PACKAGE + return true +} + +proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to validate FPGA_FAMILY + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.QUAD_OR_DUAL_N { PARAM_VALUE.QUAD_OR_DUAL_N } { + # Procedure called to update QUAD_OR_DUAL_N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.QUAD_OR_DUAL_N { PARAM_VALUE.QUAD_OR_DUAL_N } { + # Procedure called to validate QUAD_OR_DUAL_N + return true +} + +proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to validate SPEED_GRADE + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY} +} + +proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE} +} + +proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE} +} + +proc update_MODELPARAM_VALUE.QUAD_OR_DUAL_N { MODELPARAM_VALUE.QUAD_OR_DUAL_N PARAM_VALUE.QUAD_OR_DUAL_N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.QUAD_OR_DUAL_N}] ${MODELPARAM_VALUE.QUAD_OR_DUAL_N} +} + diff --git a/adi_library/axi_ad9684/Makefile b/adi_library/axi_ad9684/Makefile new file mode 100644 index 00000000..3799628d --- /dev/null +++ b/adi_library/axi_ad9684/Makefile @@ -0,0 +1,41 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_ad9684 + +GENERIC_DEPS += ../common/ad_datafmt.v +GENERIC_DEPS += ../common/ad_pnmon.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_adc_channel.v +GENERIC_DEPS += ../common/up_adc_common.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_delay_cntrl.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_ad9684.v +GENERIC_DEPS += axi_ad9684_channel.v +GENERIC_DEPS += axi_ad9684_if.v +GENERIC_DEPS += axi_ad9684_pnmon.v + +XILINX_DEPS += ../xilinx/common/ad_mmcm_drp.v +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/ad_serdes_clk.v +XILINX_DEPS += ../xilinx/common/ad_serdes_in.v +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_ad9684_constr.xdc +XILINX_DEPS += axi_ad9684_ip.tcl + +INTEL_DEPS += ../intel/common/up_clock_mon_constr.sdc +INTEL_DEPS += ../intel/common/up_rst_constr.sdc +INTEL_DEPS += ../intel/common/up_xfer_cntrl_constr.sdc +INTEL_DEPS += ../intel/common/up_xfer_status_constr.sdc +INTEL_DEPS += axi_ad9684_constr.sdc +INTEL_DEPS += axi_ad9684_hw.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_ad9684/axi_ad9684.v b/adi_library/axi_ad9684/axi_ad9684.v new file mode 100644 index 00000000..ce9ac84a --- /dev/null +++ b/adi_library/axi_ad9684/axi_ad9684.v @@ -0,0 +1,390 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9684 #( + + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter IODELAY_ENABLE = 1, + parameter IO_DELAY_GROUP = "dev_if_delay_group", + parameter OR_STATUS = 1 +) ( + + // device interface ports + + input adc_clk_in_p, + input adc_clk_in_n, + input [13:0] adc_data_in_p, + input [13:0] adc_data_in_n, + input adc_data_or_p, + input adc_data_or_n, + + // dma interface ports + + output adc_clk, + output adc_rst, + output adc_valid_0, + output adc_enable_0, + output [31:0] adc_data_0, + output adc_valid_1, + output adc_enable_1, + output [31:0] adc_data_1, + input adc_dovf, + + // delay clock ports + + input delay_clk, + + // axi slave interface ports + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready +); + + // internal registers + + reg up_wack = 1'b0; + reg [31:0] up_rdata = 32'b0; + reg up_rack = 1'b0; + + // internal clocks & resets + + wire up_clk; + wire up_rstn; + wire delay_rst; + + // internal signals + + wire [55:0] adc_rawdata_s; + wire [27:0] adc_rawdata_0_s; + wire [27:0] adc_rawdata_1_s; + wire adc_or_0_s; + wire adc_or_1_s; + wire adc_status_s; + wire adc_or_s; + wire [14:0] up_dld_s; + wire [74:0] up_dwdata_s; + wire [74:0] up_drdata_s; + wire delay_locked_s; + wire up_status_pn_err_s; + wire up_status_pn_oos_s; + wire up_status_or_s; + wire [ 1:0] up_adc_pn_err_s; + wire [ 1:0] up_adc_pn_oos_s; + wire [ 1:0] up_adc_or_s; + wire up_rreq_s; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_s[0:3]; + wire up_rack_s[0:3]; + wire up_wack_s[0:3]; + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire up_drp_sel_s; + wire up_drp_wr_s; + wire [11:0] up_drp_addr_s; + wire [31:0] up_drp_wdata_s; + wire [31:0] up_drp_rdata_s; + wire up_drp_ready_s; + wire up_drp_locked_s; + wire rst_s; + + //defaults + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + assign adc_valid = 1'b1; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 32'd0; + up_rack <= 1'd0; + up_wack <= 1'd0; + end else begin + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3]; + up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3]; + up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3]; + end + end + + // device interface instance + + axi_ad9684_if #( + .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), + .IODELAY_ENABLE (IODELAY_ENABLE), + .IO_DELAY_GROUP(IO_DELAY_GROUP), + .OR_STATUS (OR_STATUS) + ) i_ad9684_if ( + .adc_clk_in_p (adc_clk_in_p), + .adc_clk_in_n (adc_clk_in_n), + .adc_data_in_p (adc_data_in_p), + .adc_data_in_n (adc_data_in_n), + .adc_data_or_p (adc_data_or_p), + .adc_data_or_n (adc_data_or_n), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data_a (adc_rawdata_0_s), + .adc_or_a (adc_or_0_s), + .adc_data_b (adc_rawdata_1_s), + .adc_or_b (adc_or_1_s), + .adc_status (adc_status_s), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_dload (up_dld_s), + .delay_wdata (up_dwdata_s), + .delay_rdata (up_drdata_s), + .delay_locked (delay_locked_s), + .rst (rst_s), + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_drp_sel (up_drp_sel_s), + .up_drp_wr (up_drp_wr_s), + .up_drp_addr (up_drp_addr_s), + .up_drp_wdata (up_drp_wdata_s), + .up_drp_rdata (up_drp_rdata_s), + .up_drp_ready (up_drp_ready_s), + .up_drp_locked (up_drp_locked_s)); + + // common processor control instance + + assign up_status_pn_err_s = up_adc_pn_err_s[0] | up_adc_pn_err_s[1]; + assign up_status_pn_oos_s = up_adc_pn_oos_s[0] | up_adc_pn_oos_s[1]; + assign up_status_or_s = up_adc_or_s[0] | up_adc_or_s[1]; + + up_adc_common #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .CONFIG (0), + .COMMON_ID (6'h00), + .DRP_DISABLE (6'h00), + .USERPORTS_DISABLE (0), + .GPIO_DISABLE (0), + .START_CODE_DISABLE(0) + ) i_up_adc_common ( + .mmcm_rst (rst_s), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (adc_status_s), + .adc_sync_status (1'd0), + .adc_status_ovf (adc_dovf), + .adc_clk_ratio (32'b1), + .adc_start_code (), + .adc_sref_sync(), + .adc_sync (), + .adc_ext_sync_arm (), + .adc_ext_sync_disarm (), + .adc_ext_sync_manual_req (), + .adc_num_lanes (), + .adc_custom_control (), + .adc_crc_enable (), + .adc_sdr_ddr_n (), + .adc_symb_op (), + .adc_symb_8_16b (), + .up_pps_rcounter(32'd0), + .up_pps_status(1'd0), + .up_pps_irq_mask(), + .up_adc_r1_mode (), + .up_adc_ce(), + .up_status_pn_err (up_status_pn_err_s), + .up_status_pn_oos (up_status_pn_oos_s), + .up_status_or (up_status_or_s), + .up_drp_sel (up_drp_sel_s), + .up_drp_wr (up_drp_wr_s), + .up_drp_addr (up_drp_addr_s), + .up_drp_wdata (up_drp_wdata_s), + .up_drp_rdata (up_drp_rdata_s), + .up_drp_ready (up_drp_ready_s), + .up_drp_locked (up_drp_locked_s), + .adc_config_wr (), + .adc_config_ctrl (), + .adc_config_rd ('d0), + .adc_ctrl_status ('d0), + .up_usr_chanmax_out (), + .up_usr_chanmax_in (8'd1), + .up_adc_gpio_in (32'd0), + .up_adc_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // adc channel 0 instance + + axi_ad9684_channel #( + .CHANNEL_ID (0), + .Q_OR_I_N (0) + ) i_channel_0 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_rawdata_0_s), + .adc_data_q (adc_rawdata_1_s), + .adc_or (adc_or_0_s), + .adc_dfmt_data (adc_data_0), + .adc_valid (adc_valid_0), + .adc_enable (adc_enable_0), + .up_adc_pn_err (up_adc_pn_err_s[0]), + .up_adc_pn_oos (up_adc_pn_oos_s[0]), + .up_adc_or (up_adc_or_s[0]), + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // adc channel 1 instance + + axi_ad9684_channel #( + .CHANNEL_ID (1), + .Q_OR_I_N (1) + ) i_channel_1 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_rawdata_1_s), + .adc_data_q (adc_rawdata_0_s), + .adc_or (adc_or_1_s), + .adc_dfmt_data (adc_data_1), + .adc_valid (adc_valid_1), + .adc_enable (adc_enable_1), + .up_adc_pn_err (up_adc_pn_err_s[1]), + .up_adc_pn_oos (up_adc_pn_oos_s[1]), + .up_adc_or (up_adc_or_s[1] ), + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + // adc delay control instance + + up_delay_cntrl #( + .DATA_WIDTH(15) + ) i_delay_cntrl ( + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s), + .up_dld (up_dld_s), + .up_dwdata (up_dwdata_s), + .up_drdata (up_drdata_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[3]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[3]), + .up_rack (up_rack_s[3])); + + // uP bus interface instance + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ad9684/axi_ad9684.xpr b/adi_library/axi_ad9684/axi_ad9684.xpr new file mode 100644 index 00000000..d885a276 --- /dev/null +++ b/adi_library/axi_ad9684/axi_ad9684.xpr @@ -0,0 +1,548 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_ad9684/axi_ad9684_channel.v b/adi_library/axi_ad9684/axi_ad9684_channel.v new file mode 100644 index 00000000..c6d87688 --- /dev/null +++ b/adi_library/axi_ad9684/axi_ad9684_channel.v @@ -0,0 +1,170 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9684_channel #( + + parameter Q_OR_I_N = 0, + parameter CHANNEL_ID = 0, + parameter DATAPATH_DISABLE = 0 +) ( + + // adc data interface + + input adc_clk, + input adc_rst, + input [27:0] adc_data, + input [27:0] adc_data_q, + input adc_or, + + // channel interface + + output [31:0] adc_dfmt_data, + output adc_valid, + output adc_enable, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, + + // up interface + + input up_clk, + input up_rstn, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // internal signals + + wire adc_pn_oos_s; + wire adc_pn_err_s; + wire adc_dfmt_enable_s; + wire adc_dfmt_type_s; + wire adc_dfmt_se_s; + wire [ 1:0] adc_dfmt_valid_s; + wire [ 3:0] adc_pnseq_sel_s; + + // instantiations + + axi_ad9684_pnmon i_pnmon ( + .adc_clk (adc_clk), + .adc_data (adc_data), + .adc_pn_oos (adc_pn_oos_s), + .adc_pn_err (adc_pn_err_s), + .adc_pnseq_sel (adc_pnseq_sel_s)); + + genvar n; + generate + for (n = 0; n < 2; n = n + 1) begin: g_ad_datafmt_1 + ad_datafmt #( + .DATA_WIDTH(14) + ) i_ad_datafmt ( + .clk (adc_clk), + .valid (1'b1), + .data (adc_data[n*14+13:n*14]), + .valid_out (adc_dfmt_valid_s[n]), + .data_out (adc_dfmt_data[n*16+15:n*16]), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + end + endgenerate + + assign adc_valid = adc_dfmt_valid_s[0] | adc_dfmt_valid_s[1]; + + up_adc_channel #( + .COMMON_ID (6'h01), + .CHANNEL_ID(CHANNEL_ID), + .USERPORTS_DISABLE (0), + .DATAFORMAT_DISABLE (0), + .DCFILTER_DISABLE (0), + .IQCORRECTION_DISABLE (0) + ) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (), + .adc_dcfilt_enb (), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_dcfilt_offset (), + .adc_dcfilt_coeff (), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_data_sel (), + .adc_pn_err (adc_pn_err_s), + .adc_pn_oos (adc_pn_oos_s), + .adc_or (adc_or), + .adc_read_data ('d0), + .adc_status_header ('d0), + .adc_crc_err ('d0), + .up_adc_pn_err (up_adc_pn_err), + .up_adc_pn_oos (up_adc_pn_oos), + .up_adc_or (up_adc_or), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ad9684/axi_ad9684_constr.sdc b/adi_library/axi_ad9684/axi_ad9684_constr.sdc new file mode 100644 index 00000000..9c237190 --- /dev/null +++ b/adi_library/axi_ad9684/axi_ad9684_constr.sdc @@ -0,0 +1,8 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_false_path -to [get_registers *axi_ad9684_if:i_ad9684_if|adc_status_m1*] +set_false_path -to [get_registers *up_delay_cntrl:i_delay_cntrl|up_dlocked_m1*] + diff --git a/adi_library/axi_ad9684/axi_ad9684_constr.xdc b/adi_library/axi_ad9684/axi_ad9684_constr.xdc new file mode 100644 index 00000000..97b0a99b --- /dev/null +++ b/adi_library/axi_ad9684/axi_ad9684_constr.xdc @@ -0,0 +1,6 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_false_path -from [get_cells -hier -filter {name =~ *up_drp_locked_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *adc_status_m1_reg && IS_SEQUENTIAL}] diff --git a/adi_library/axi_ad9684/axi_ad9684_hw.tcl b/adi_library/axi_ad9684/axi_ad9684_hw.tcl new file mode 100644 index 00000000..2717c2f3 --- /dev/null +++ b/adi_library/axi_ad9684/axi_ad9684_hw.tcl @@ -0,0 +1,129 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +package require quartus::device + +source ../../scripts/adi_env.tcl +source ../scripts/adi_ip_intel.tcl + +ad_ip_create axi_ad9684 {AXI AD9684 Interface} axi_ad9684_elab +set_module_property VALIDATION_CALLBACK info_param_validate + +ad_ip_files axi_ad9684 [list \ + $ad_hdl_dir/library/common/ad_rst.v \ + $ad_hdl_dir/library/common/ad_datafmt.v \ + $ad_hdl_dir/library/common/ad_pnmon.v \ + $ad_hdl_dir/library/common/up_xfer_status.v \ + $ad_hdl_dir/library/common/up_xfer_cntrl.v \ + $ad_hdl_dir/library/common/up_clock_mon.v \ + $ad_hdl_dir/library/common/up_delay_cntrl.v \ + $ad_hdl_dir/library/common/up_adc_common.v \ + $ad_hdl_dir/library/common/up_adc_channel.v \ + $ad_hdl_dir/library/common/up_axi.v \ + axi_ad9684_pnmon.v \ + axi_ad9684_if.v \ + axi_ad9684_channel.v \ + axi_ad9684.v \ + $ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_rst_constr.sdc \ + axi_ad9684_constr.sdc] \ + axi_ad9684_fileset + +# parameters + +add_parameter ID INTEGER 0 +set_parameter_property ID DEFAULT_VALUE 0 +set_parameter_property ID DISPLAY_NAME ID +set_parameter_property ID DESCRIPTION "Instance ID" +set_parameter_property ID UNITS None +set_parameter_property ID HDL_PARAMETER true + +add_parameter FPGA_TECHNOLOGY INTEGER 0 +set_parameter_property FPGA_TECHNOLOGY DEFAULT_VALUE 0 +set_parameter_property FPGA_TECHNOLOGY DISPLAY_NAME FPGA_TECHNOLOGY +set_parameter_property FPGA_TECHNOLOGY TYPE INTEGER +set_parameter_property FPGA_TECHNOLOGY DESCRIPTION "Specify the FPGA device type" +set_parameter_property FPGA_TECHNOLOGY UNITS None +set_parameter_property FPGA_TECHNOLOGY HDL_PARAMETER true + +add_parameter OR_STATUS INTEGER 1 +set_parameter_property OR_STATUS DEFAULT_VALUE 1 +set_parameter_property OR_STATUS DISPLAY_NAME OR_STATUS +set_parameter_property OR_STATUS DESCRIPTION "This parameter enables the OVER RANGE line at the physical interface" +set_parameter_property OR_STATUS UNITS None +set_parameter_property OR_STATUS HDL_PARAMETER true + +adi_add_auto_fpga_spec_params + +# axi4 slave + +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn + +# adc device interface + +add_interface device_if conduit end +set_interface_property device_if associatedClock none +set_interface_property device_if associatedReset none + +add_interface_port device_if adc_clk_in_p adc_clk_in_p Input 1 +add_interface_port device_if adc_clk_in_n adc_clk_in_n Input 1 +add_interface_port device_if adc_data_in_p adc_data_in_p Input 14 +add_interface_port device_if adc_data_in_n adc_data_in_n Input 14 + +# dma interface + +ad_interface clock adc_clk output 1 +ad_interface reset adc_rst output 1 if_adc_clk + +add_interface adc_ch_0 conduit end +add_interface_port adc_ch_0 adc_valid_0 valid Output 1 +add_interface_port adc_ch_0 adc_enable_0 enable Output 1 +add_interface_port adc_ch_0 adc_data_0 data Output 32 +set_interface_property adc_ch_0 associatedClock if_adc_clk +set_interface_property adc_ch_0 associatedReset none + +add_interface adc_ch_1 conduit end +add_interface_port adc_ch_1 adc_valid_1 valid Output 1 +add_interface_port adc_ch_1 adc_enable_1 enable Output 1 +add_interface_port adc_ch_1 adc_data_1 data Output 32 +set_interface_property adc_ch_1 associatedClock if_adc_clk +set_interface_property adc_ch_1 associatedReset none + +ad_interface signal adc_dovf input 1 ovf + +# SERDES instances and configurations + +add_hdl_instance ad_serdes_clk_core_rx intel_serdes +set_instance_parameter_value ad_serdes_clk_core_rx {MODE} {CLK} +set_instance_parameter_value ad_serdes_clk_core_rx {DDR_OR_SDR_N} {1} +set_instance_parameter_value ad_serdes_clk_core_rx {SERDES_FACTOR} {4} +set_instance_parameter_value ad_serdes_clk_core_rx {CLKIN_FREQUENCY} {500.0} + +add_hdl_instance ad_serdes_in_core intel_serdes +set_instance_parameter_value ad_serdes_in_core {MODE} {IN} +set_instance_parameter_value ad_serdes_in_core {DDR_OR_SDR_N} {1} +set_instance_parameter_value ad_serdes_in_core {SERDES_FACTOR} {4} +set_instance_parameter_value ad_serdes_in_core {CLKIN_FREQUENCY} {500.0} + +proc axi_ad9684_elab {} { + + set or_status [get_parameter_value OR_STATUS] + + if {$or_status == 1} { + add_interface_port device_if adc_data_or_p adc_data_or_p Input 1 + add_interface_port device_if adc_data_or_n adc_data_or_n Input 1 + } +} + +proc axi_ad9684_fileset { entityName } { + + ad_ip_modfile ad_serdes_in.v ad_serdes_in.v ad_serdes_in_core + ad_ip_modfile ad_serdes_clk.v ad_serdes_clk.v ad_serdes_clk_core_rx + +} + diff --git a/adi_library/axi_ad9684/axi_ad9684_if.v b/adi_library/axi_ad9684/axi_ad9684_if.v new file mode 100644 index 00000000..41196807 --- /dev/null +++ b/adi_library/axi_ad9684/axi_ad9684_if.v @@ -0,0 +1,217 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9684_if #( + + parameter FPGA_TECHNOLOGY = 0, + parameter IODELAY_ENABLE = 1, + parameter IO_DELAY_GROUP = "dev_if_delay_group", + parameter OR_STATUS = 0 +) ( + + // device interface + input adc_clk_in_p, + input adc_clk_in_n, + input [13:0] adc_data_in_p, + input [13:0] adc_data_in_n, + input adc_data_or_p, + input adc_data_or_n, + + // data interface + output adc_clk, + input adc_rst, + output [27:0] adc_data_a, + output adc_or_a, + output [27:0] adc_data_b, + output adc_or_b, + output reg adc_status, + + // delay interface + input delay_clk, + input delay_rst, + input [14:0] delay_dload, + input [74:0] delay_wdata, + output [74:0] delay_rdata, + output delay_locked, + + // reset + input rst, + + // drp interface + input up_clk, + input up_rstn, + input up_drp_sel, + input up_drp_wr, + input [11:0] up_drp_addr, + input [31:0] up_drp_wdata, + output [31:0] up_drp_rdata, + output up_drp_ready, + output up_drp_locked +); + + localparam DDR_OR_SDR_N = 1; + + // internal registers + + reg adc_status_m1 = 'd0; + + // internal signals + + wire adc_clk_in; + wire adc_div_clk; + wire [ 1:0] adc_data_or_a_s; + wire [ 1:0] adc_data_or_b_s; + wire [ 7:0] phase_s; + + genvar l_inst; + + // adc_clk is 1:2 of the sampling clock + // f_max = 250 MHz + + assign adc_clk = adc_div_clk; + + // data interface + + ad_serdes_in #( + .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), + .IODELAY_ENABLE (IODELAY_ENABLE), + .IODELAY_CTRL(1), + .IODELAY_GROUP(IO_DELAY_GROUP), + .DDR_OR_SDR_N(DDR_OR_SDR_N), + .DATA_WIDTH(14) + ) i_adc_data ( + .rst(adc_rst), + .clk(adc_clk_in), + .div_clk(adc_div_clk), + .data_s0(adc_data_b[27:14]), + .data_s1(adc_data_a[27:14]), + .data_s2(adc_data_b[13: 0]), + .data_s3(adc_data_a[13: 0]), + .data_s4(), + .data_s5(), + .data_s6(), + .data_s7(), + .data_in_p(adc_data_in_p[13:0]), + .data_in_n(adc_data_in_n[13:0]), + .up_clk (up_clk), + .up_dld (delay_dload[13:0]), + .up_dwdata (delay_wdata[69:0]), + .up_drdata (delay_rdata[69:0]), + .delay_clk(delay_clk), + .delay_rst(delay_rst), + .delay_locked(delay_locked)); + + generate if (OR_STATUS == 1) begin + + ad_serdes_in #( + .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), + .IODELAY_ENABLE (IODELAY_ENABLE), + .IODELAY_CTRL(0), + .IODELAY_GROUP(IO_DELAY_GROUP), + .DDR_OR_SDR_N(DDR_OR_SDR_N), + .DATA_WIDTH(1) + ) i_adc_or ( + .rst(adc_rst), + .clk(adc_clk_in), + .div_clk(adc_div_clk), + .data_s0(adc_data_or_b_s[1]), + .data_s1(adc_data_or_a_s[1]), + .data_s2(adc_data_or_b_s[0]), + .data_s3(adc_data_or_a_s[0]), + .data_s4(), + .data_s5(), + .data_s6(), + .data_s7(), + .data_in_p(adc_data_or_p), + .data_in_n(adc_data_or_n), + .up_clk (up_clk), + .up_dld (delay_dload[14]), + .up_dwdata (delay_wdata[74:70]), + .up_drdata (delay_rdata[74:70]), + .delay_clk(delay_clk), + .delay_rst(delay_rst), + .delay_locked()); + + assign adc_or_a = adc_data_or_a_s[0] | adc_data_or_a_s[1]; + assign adc_or_b = adc_data_or_b_s[0] | adc_data_or_b_s[1]; + + end else begin + + assign adc_or_a = 1'b0; + assign adc_or_b = 1'b0; + + end + endgenerate + + // clock input buffers and MMCM_OR_BUFR_N + + ad_serdes_clk #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .MMCM_CLKIN_PERIOD (2), + .MMCM_VCO_DIV (6), + .MMCM_VCO_MUL (12), + .MMCM_CLK0_DIV (2), + .MMCM_CLK1_DIV (4) + ) i_serdes_clk ( + .rst (rst), + .clk_in_p (adc_clk_in_p), + .clk_in_n (adc_clk_in_n), + .clk (adc_clk_in), + .div_clk (adc_div_clk), + .out_clk (), + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_drp_sel (up_drp_sel), + .up_drp_wr (up_drp_wr), + .up_drp_addr (up_drp_addr), + .up_drp_wdata (up_drp_wdata), + .up_drp_rdata (up_drp_rdata), + .up_drp_ready (up_drp_ready), + .up_drp_locked (up_drp_locked)); + + // adc status: adc is up, if both the MMCM_OR_BUFR_N and DELAY blocks are up + always @(posedge adc_div_clk) begin + if(adc_rst == 1'b1) begin + adc_status_m1 <= 1'b0; + adc_status <= 1'b0; + end else begin + adc_status_m1 <= up_drp_locked; + adc_status <= adc_status_m1; + end + end + +endmodule diff --git a/adi_library/axi_ad9684/axi_ad9684_ip.tcl b/adi_library/axi_ad9684/axi_ad9684_ip.tcl new file mode 100644 index 00000000..4389c4bf --- /dev/null +++ b/adi_library/axi_ad9684/axi_ad9684_ip.tcl @@ -0,0 +1,52 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_ad9684 +adi_ip_files axi_ad9684 [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_serdes_in.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "axi_ad9684_pnmon.v" \ + "axi_ad9684_if.v" \ + "axi_ad9684_channel.v" \ + "axi_ad9684_constr.xdc" \ + "axi_ad9684.v" ] + +adi_ip_properties axi_ad9684 + +adi_init_bd_tcl +adi_ip_bd axi_ad9684 "bd/bd.tcl" + +set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] + +ipx::infer_bus_interface adc_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface adc_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + +ipx::save_core [ipx::current_core] diff --git a/adi_library/axi_ad9684/axi_ad9684_pnmon.v b/adi_library/axi_ad9684/axi_ad9684_pnmon.v new file mode 100644 index 00000000..ba0c5400 --- /dev/null +++ b/adi_library/axi_ad9684/axi_ad9684_pnmon.v @@ -0,0 +1,173 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// PN monitors + +`timescale 1ns/100ps + +module axi_ad9684_pnmon ( + + // adc interface + + input adc_clk, + input [27:0] adc_data, + + // pn out of sync and error + + output adc_pn_oos, + output adc_pn_err, + + // processor interface PN9 (0x0), PN23 (0x1) + + input [ 3:0] adc_pnseq_sel +); + + // internal registers + + reg [27:0] adc_pn_data_in = 'd0; + reg [27:0] adc_pn_data_pn = 'd0; + + // internal signals + + wire [27:0] adc_pn_data_pn_s; + wire [31:0] adc_pn_data_pn9_s; + + // PN23 function + + function [27:0] pn23; + input [27:0] din; + reg [27:0] dout; + begin + dout[27] = din[22] ^ din[17]; + dout[26] = din[21] ^ din[16]; + dout[25] = din[20] ^ din[15]; + dout[24] = din[19] ^ din[14]; + dout[23] = din[18] ^ din[13]; + dout[22] = din[17] ^ din[12]; + dout[21] = din[16] ^ din[11]; + dout[20] = din[15] ^ din[10]; + dout[19] = din[14] ^ din[ 9]; + dout[18] = din[13] ^ din[ 8]; + dout[17] = din[12] ^ din[ 7]; + dout[16] = din[11] ^ din[ 6]; + dout[15] = din[10] ^ din[ 5]; + dout[14] = din[ 9] ^ din[ 4]; + dout[13] = din[ 8] ^ din[ 3]; + dout[12] = din[ 7] ^ din[ 2]; + dout[11] = din[ 6] ^ din[ 1]; + dout[10] = din[ 5] ^ din[ 0]; + dout[ 9] = din[ 4] ^ din[22] ^ din[17]; + dout[ 8] = din[ 3] ^ din[21] ^ din[16]; + dout[ 7] = din[ 2] ^ din[20] ^ din[15]; + dout[ 6] = din[ 1] ^ din[19] ^ din[14]; + dout[ 5] = din[ 0] ^ din[18] ^ din[13]; + dout[ 4] = din[22] ^ din[12]; + dout[ 3] = din[21] ^ din[11]; + dout[ 2] = din[20] ^ din[10]; + dout[ 1] = din[19] ^ din[ 9]; + dout[ 0] = din[18] ^ din[ 8]; + pn23 = dout; + end + endfunction + + // PN9 function + + function [31:0] pn9; + input [27:0] din; + reg [31:0] dout; + begin + dout[31] = din[ 8] ^ din[ 4]; + dout[30] = din[ 7] ^ din[ 3]; + dout[29] = din[ 6] ^ din[ 2]; + dout[28] = din[ 5] ^ din[ 1]; + dout[27] = din[ 4] ^ din[ 0]; + dout[26] = din[ 3] ^ din[ 8] ^ din[ 4]; + dout[25] = din[ 2] ^ din[ 7] ^ din[ 3]; + dout[24] = din[ 1] ^ din[ 6] ^ din[ 2]; + dout[23] = din[ 0] ^ din[ 5] ^ din[ 1]; + dout[22] = din[ 8] ^ din[ 0]; + dout[21] = din[ 7] ^ din[ 8] ^ din[ 4]; + dout[20] = din[ 6] ^ din[ 7] ^ din[ 3]; + dout[19] = din[ 5] ^ din[ 6] ^ din[ 2]; + dout[18] = din[ 4] ^ din[ 5] ^ din[ 1]; + dout[17] = din[ 3] ^ din[ 4] ^ din[ 0]; + dout[16] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4]; + dout[15] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3]; + dout[14] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[13] = din[ 8] ^ din[ 0] ^ din[ 5] ^ din[ 1] ^ din[ 4]; + dout[12] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0]; + dout[11] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4]; + dout[10] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3]; + dout[ 9] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2]; + dout[ 8] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1]; + dout[ 7] = din[ 2] ^ din[ 4] ^ din[ 7] ^ din[ 0]; + dout[ 6] = din[ 1] ^ din[ 3] ^ din[ 6] ^ din[ 8] ^ din[ 4]; + dout[ 5] = din[ 0] ^ din[ 2] ^ din[ 5] ^ din[ 7] ^ din[ 3]; + dout[ 4] = din[ 8] ^ din[ 1] ^ din[ 6] ^ din[ 2]; + dout[ 3] = din[ 7] ^ din[ 0] ^ din[ 5] ^ din[ 1]; + dout[ 2] = din[ 6] ^ din[ 8] ^ din[ 0]; + dout[ 1] = din[ 5] ^ din[ 7] ^ din[ 8] ^ din[ 4]; + dout[ 0] = din[ 4] ^ din[ 6] ^ din[ 7] ^ din[ 3]; + pn9 = dout; + end + endfunction + + // pn sequence select + + assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn; + assign adc_pn_data_pn9_s = pn9(adc_pn_data_pn_s); + + always @(posedge adc_clk) begin + adc_pn_data_in <= { ~adc_data[13], adc_data[12: 0], + ~adc_data[27], adc_data[26:14]}; + if (adc_pnseq_sel == 4'd0) begin + adc_pn_data_pn <= {adc_pn_data_pn9_s[29:16], adc_pn_data_pn9_s[13:0]}; + end else begin + adc_pn_data_pn <= pn23(adc_pn_data_pn_s); + end + end + + // pn oos & pn err + + ad_pnmon #( + .DATA_WIDTH(28) + ) i_pnmon ( + .adc_clk (adc_clk), + .adc_valid_in (1'b1), + .adc_data_in (adc_pn_data_in), + .adc_data_pn (adc_pn_data_pn), + .adc_pn_oos (adc_pn_oos), + .adc_pn_err (adc_pn_err)); + +endmodule diff --git a/adi_library/axi_ad9684/bd/bd.tcl b/adi_library/axi_ad9684/bd/bd.tcl new file mode 100644 index 00000000..dceb9498 --- /dev/null +++ b/adi_library/axi_ad9684/bd/bd.tcl @@ -0,0 +1,47 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + DEV_PACKAGE \ + SPEED_GRADE \ + FPGA_FAMILY \ + FPGA_TECHNOLOGY" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/axi_ad9684/component.xml b/adi_library/axi_ad9684/component.xml new file mode 100644 index 00000000..24c9c06a --- /dev/null +++ b/adi_library/axi_ad9684/component.xml @@ -0,0 +1,1340 @@ + + + analog.com + user + axi_ad9684 + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + adc_clk_in_p + + + + + + + CLK + + + adc_clk_in_p + + + + + + ASSOCIATED_RESET + adc_rst + + + + + adc_clk_in_n + + + + + + + CLK + + + adc_clk_in_n + + + + + + delay_clk + + + + + + + CLK + + + delay_clk + + + + + + adc_clk + + + + + + + CLK + + + adc_clk + + + + + + adc_rst + + + + + + + RST + + + adc_rst + + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_ad9684 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 67f60fe5 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_ad9684 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 738d2417 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + e6bab7be + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + + + adc_clk_in_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_clk_in_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_in_p + + in + + 13 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_data_in_n + + in + + 13 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_data_or_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_data_or_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_rst + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid_0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_0 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid_1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_1 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_dovf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + delay_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + IODELAY_ENABLE + Iodelay Enable + 1 + + + IO_DELAY_GROUP + Io Delay Group + dev_if_delay_group + + + OR_STATUS + Or Status + 1 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_00ecfe9a + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + + + choice_pairs_19f99f31 + 0 + 10 + 11 + 12 + 13 + 14 + 20 + 21 + 22 + 23 + 24 + 25 + 30 + + + choice_pairs_28f798a2 + 0 + 1 + 2 + 3 + 4 + + + choice_pairs_fc01a186 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../xilinx/common/up_clock_mon_constr.xdc + xdc + + + axi_ad9684_constr.xdc + xdc + + + ../common/ad_datafmt.v + verilogSource + + + ../xilinx/common/ad_mmcm_drp.v + verilogSource + + + ../common/ad_pnmon.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../xilinx/common/ad_serdes_clk.v + verilogSource + + + ../xilinx/common/ad_serdes_in.v + verilogSource + + + axi_ad9684_channel.v + verilogSource + + + axi_ad9684_if.v + verilogSource + + + axi_ad9684_pnmon.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_delay_cntrl.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad9684.v + verilogSource + CHECKSUM_ee771002 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_datafmt.v + verilogSource + + + ../xilinx/common/ad_mmcm_drp.v + verilogSource + + + ../common/ad_pnmon.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../xilinx/common/ad_serdes_clk.v + verilogSource + + + ../xilinx/common/ad_serdes_in.v + verilogSource + + + axi_ad9684_channel.v + verilogSource + + + axi_ad9684_if.v + verilogSource + + + axi_ad9684_pnmon.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_delay_cntrl.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad9684.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_ad9684_v1_0.tcl + tclSource + CHECKSUM_96f0cbca + XGUI_VERSION_2 + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + axi_ad9684_v1_0 + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + IODELAY_ENABLE + Iodelay Enable + 1 + + + IO_DELAY_GROUP + Io Delay Group + dev_if_delay_group + + + OR_STATUS + Or Status + 1 + + + Component_Name + axi_ad9684_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_ad9684_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:42:36Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_ad9684/temporary_case_dependencies.mk b/adi_library/axi_ad9684/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/axi_ad9684/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/axi_ad9684/xgui/axi_ad9684_v1_0.tcl b/adi_library/axi_ad9684/xgui/axi_ad9684_v1_0.tcl new file mode 100644 index 00000000..b936f881 --- /dev/null +++ b/adi_library/axi_ad9684/xgui/axi_ad9684_v1_0.tcl @@ -0,0 +1,133 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "IODELAY_ENABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "IO_DELAY_GROUP" -parent ${Page_0} + ipgui::add_param $IPINST -name "OR_STATUS" -parent ${Page_0} + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to validate DEV_PACKAGE + return true +} + +proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to validate FPGA_FAMILY + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.IODELAY_ENABLE { PARAM_VALUE.IODELAY_ENABLE } { + # Procedure called to update IODELAY_ENABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IODELAY_ENABLE { PARAM_VALUE.IODELAY_ENABLE } { + # Procedure called to validate IODELAY_ENABLE + return true +} + +proc update_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to update IO_DELAY_GROUP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to validate IO_DELAY_GROUP + return true +} + +proc update_PARAM_VALUE.OR_STATUS { PARAM_VALUE.OR_STATUS } { + # Procedure called to update OR_STATUS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OR_STATUS { PARAM_VALUE.OR_STATUS } { + # Procedure called to validate OR_STATUS + return true +} + +proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to validate SPEED_GRADE + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY} +} + +proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE} +} + +proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE} +} + +proc update_MODELPARAM_VALUE.IODELAY_ENABLE { MODELPARAM_VALUE.IODELAY_ENABLE PARAM_VALUE.IODELAY_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IODELAY_ENABLE}] ${MODELPARAM_VALUE.IODELAY_ENABLE} +} + +proc update_MODELPARAM_VALUE.IO_DELAY_GROUP { MODELPARAM_VALUE.IO_DELAY_GROUP PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IO_DELAY_GROUP}] ${MODELPARAM_VALUE.IO_DELAY_GROUP} +} + +proc update_MODELPARAM_VALUE.OR_STATUS { MODELPARAM_VALUE.OR_STATUS PARAM_VALUE.OR_STATUS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OR_STATUS}] ${MODELPARAM_VALUE.OR_STATUS} +} + diff --git a/adi_library/axi_ad9739a/Makefile b/adi_library/axi_ad9739a/Makefile new file mode 100644 index 00000000..6ed9b8e2 --- /dev/null +++ b/adi_library/axi_ad9739a/Makefile @@ -0,0 +1,35 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_ad9739a + +GENERIC_DEPS += ../common/ad_dds.v +GENERIC_DEPS += ../common/ad_dds_1.v +GENERIC_DEPS += ../common/ad_dds_2.v +GENERIC_DEPS += ../common/ad_dds_cordic_pipe.v +GENERIC_DEPS += ../common/ad_dds_sine.v +GENERIC_DEPS += ../common/ad_dds_sine_cordic.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_dac_channel.v +GENERIC_DEPS += ../common/up_dac_common.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_ad9739a.v +GENERIC_DEPS += axi_ad9739a_channel.v +GENERIC_DEPS += axi_ad9739a_core.v +GENERIC_DEPS += axi_ad9739a_if.v + +XILINX_DEPS += ../xilinx/common/ad_mul.v +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/ad_serdes_out.v +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_ad9739a_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_ad9739a/axi_ad9739a.v b/adi_library/axi_ad9739a/axi_ad9739a.v new file mode 100644 index 00000000..0036a9d2 --- /dev/null +++ b/adi_library/axi_ad9739a/axi_ad9739a.v @@ -0,0 +1,249 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9739a #( + + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter SERDES_OR_DDR_N = 1, + parameter MMCM_OR_BUFIO_N = 1, + parameter DAC_DDS_TYPE = 2, + parameter DAC_DDS_CORDIC_DW = 16, + parameter DAC_DDS_CORDIC_PHASE_DW = 16, + parameter DAC_DATAPATH_DISABLE = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group" +) ( + + // dac interface + + input dac_clk_in_p, + input dac_clk_in_n, + output dac_clk_out_p, + output dac_clk_out_n, + output [ 13:0] dac_data_out_a_p, + output [ 13:0] dac_data_out_a_n, + output [ 13:0] dac_data_out_b_p, + output [ 13:0] dac_data_out_b_n, + + // dma interface + + output dac_div_clk, + output dac_valid, + output dac_enable, + input [255:0] dac_ddata, + input dac_dunf, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [ 15:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [ 31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [ 15:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot +); + + // internal clocks and resets + + wire dac_rst; + wire up_clk; + wire up_rstn; + + // internal signals + + wire [ 15:0] dac_data_00_s; + wire [ 15:0] dac_data_01_s; + wire [ 15:0] dac_data_02_s; + wire [ 15:0] dac_data_03_s; + wire [ 15:0] dac_data_04_s; + wire [ 15:0] dac_data_05_s; + wire [ 15:0] dac_data_06_s; + wire [ 15:0] dac_data_07_s; + wire [ 15:0] dac_data_08_s; + wire [ 15:0] dac_data_09_s; + wire [ 15:0] dac_data_10_s; + wire [ 15:0] dac_data_11_s; + wire [ 15:0] dac_data_12_s; + wire [ 15:0] dac_data_13_s; + wire [ 15:0] dac_data_14_s; + wire [ 15:0] dac_data_15_s; + wire dac_status_s; + wire up_wreq_s; + wire [ 13:0] up_waddr_s; + wire [ 31:0] up_wdata_s; + wire up_wack_s; + wire up_rreq_s; + wire [ 13:0] up_raddr_s; + wire [ 31:0] up_rdata_s; + wire up_rack_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // device interface + + axi_ad9739a_if #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY) + ) i_if ( + .dac_clk_in_p (dac_clk_in_p), + .dac_clk_in_n (dac_clk_in_n), + .dac_clk_out_p (dac_clk_out_p), + .dac_clk_out_n (dac_clk_out_n), + .dac_data_out_a_p (dac_data_out_a_p), + .dac_data_out_a_n (dac_data_out_a_n), + .dac_data_out_b_p (dac_data_out_b_p), + .dac_data_out_b_n (dac_data_out_b_n), + .dac_rst (dac_rst), + .dac_clk (), + .dac_div_clk (dac_div_clk), + .dac_status (dac_status_s), + .dac_data_00 (dac_data_00_s), + .dac_data_01 (dac_data_01_s), + .dac_data_02 (dac_data_02_s), + .dac_data_03 (dac_data_03_s), + .dac_data_04 (dac_data_04_s), + .dac_data_05 (dac_data_05_s), + .dac_data_06 (dac_data_06_s), + .dac_data_07 (dac_data_07_s), + .dac_data_08 (dac_data_08_s), + .dac_data_09 (dac_data_09_s), + .dac_data_10 (dac_data_10_s), + .dac_data_11 (dac_data_11_s), + .dac_data_12 (dac_data_12_s), + .dac_data_13 (dac_data_13_s), + .dac_data_14 (dac_data_14_s), + .dac_data_15 (dac_data_15_s)); + + // core + + axi_ad9739a_core #( + .ID(ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE) + ) i_core ( + .dac_div_clk (dac_div_clk), + .dac_rst (dac_rst), + .dac_data_00 (dac_data_00_s), + .dac_data_01 (dac_data_01_s), + .dac_data_02 (dac_data_02_s), + .dac_data_03 (dac_data_03_s), + .dac_data_04 (dac_data_04_s), + .dac_data_05 (dac_data_05_s), + .dac_data_06 (dac_data_06_s), + .dac_data_07 (dac_data_07_s), + .dac_data_08 (dac_data_08_s), + .dac_data_09 (dac_data_09_s), + .dac_data_10 (dac_data_10_s), + .dac_data_11 (dac_data_11_s), + .dac_data_12 (dac_data_12_s), + .dac_data_13 (dac_data_13_s), + .dac_data_14 (dac_data_14_s), + .dac_data_15 (dac_data_15_s), + .dac_status (dac_status_s), + .dac_valid (dac_valid), + .dac_enable (dac_enable), + .dac_ddata (dac_ddata), + .dac_dunf (dac_dunf), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + +endmodule diff --git a/adi_library/axi_ad9739a/axi_ad9739a.xpr b/adi_library/axi_ad9739a/axi_ad9739a.xpr new file mode 100644 index 00000000..57567ed8 --- /dev/null +++ b/adi_library/axi_ad9739a/axi_ad9739a.xpr @@ -0,0 +1,556 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_ad9739a/axi_ad9739a_channel.v b/adi_library/axi_ad9739a/axi_ad9739a_channel.v new file mode 100644 index 00000000..925b942f --- /dev/null +++ b/adi_library/axi_ad9739a/axi_ad9739a_channel.v @@ -0,0 +1,232 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9739a_channel #( + + parameter CHANNEL_ID = 32'h0, + parameter DAC_DDS_TYPE = 1, + parameter DAC_DDS_CORDIC_DW = 16, + parameter DAC_DDS_CORDIC_PHASE_DW = 16, + parameter DATAPATH_DISABLE = 0 +) ( + + // dac interface + + input dac_div_clk, + input dac_rst, + output reg dac_enable, + output reg [ 15:0] dac_data_00, + output reg [ 15:0] dac_data_01, + output reg [ 15:0] dac_data_02, + output reg [ 15:0] dac_data_03, + output reg [ 15:0] dac_data_04, + output reg [ 15:0] dac_data_05, + output reg [ 15:0] dac_data_06, + output reg [ 15:0] dac_data_07, + output reg [ 15:0] dac_data_08, + output reg [ 15:0] dac_data_09, + output reg [ 15:0] dac_data_10, + output reg [ 15:0] dac_data_11, + output reg [ 15:0] dac_data_12, + output reg [ 15:0] dac_data_13, + output reg [ 15:0] dac_data_14, + output reg [ 15:0] dac_data_15, + input [255:0] dma_data, + + // processor interface + + input dac_data_sync, + input dac_dds_format, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [ 13:0] up_waddr, + input [ 31:0] up_wdata, + output up_wack, + input up_rreq, + input [ 13:0] up_raddr, + output [ 31:0] up_rdata, + output up_rack +); + + // internal signals + + wire [255:0] dac_dds_data_s; + wire [ 15:0] dac_dds_scale_1_s; + wire [ 15:0] dac_dds_init_1_s; + wire [ 15:0] dac_dds_incr_1_s; + wire [ 15:0] dac_dds_scale_2_s; + wire [ 15:0] dac_dds_init_2_s; + wire [ 15:0] dac_dds_incr_2_s; + wire [ 15:0] dac_pat_data_1_s; + wire [ 15:0] dac_pat_data_2_s; + wire [ 3:0] dac_data_sel_s; + + // dac data select + + always @(posedge dac_div_clk) begin + dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; + case (dac_data_sel_s) + 4'h2: begin + dac_data_00 <= dma_data[ 15: 0]; + dac_data_01 <= dma_data[ 31: 16]; + dac_data_02 <= dma_data[ 47: 32]; + dac_data_03 <= dma_data[ 63: 48]; + dac_data_04 <= dma_data[ 79: 64]; + dac_data_05 <= dma_data[ 95: 80]; + dac_data_06 <= dma_data[111: 96]; + dac_data_07 <= dma_data[127:112]; + dac_data_08 <= dma_data[143:128]; + dac_data_09 <= dma_data[159:144]; + dac_data_10 <= dma_data[175:160]; + dac_data_11 <= dma_data[191:176]; + dac_data_12 <= dma_data[207:192]; + dac_data_13 <= dma_data[223:208]; + dac_data_14 <= dma_data[239:224]; + dac_data_15 <= dma_data[255:240]; + end + 4'h1: begin + dac_data_00 <= dac_pat_data_1_s; + dac_data_01 <= dac_pat_data_2_s; + dac_data_02 <= dac_pat_data_1_s; + dac_data_03 <= dac_pat_data_2_s; + dac_data_04 <= dac_pat_data_1_s; + dac_data_05 <= dac_pat_data_2_s; + dac_data_06 <= dac_pat_data_1_s; + dac_data_07 <= dac_pat_data_2_s; + dac_data_08 <= dac_pat_data_1_s; + dac_data_09 <= dac_pat_data_2_s; + dac_data_10 <= dac_pat_data_1_s; + dac_data_11 <= dac_pat_data_2_s; + dac_data_12 <= dac_pat_data_1_s; + dac_data_13 <= dac_pat_data_2_s; + dac_data_14 <= dac_pat_data_1_s; + dac_data_15 <= dac_pat_data_2_s; + end + default: begin + dac_data_00 <= dac_dds_data_s[ 15: 0]; + dac_data_01 <= dac_dds_data_s[ 31: 16]; + dac_data_02 <= dac_dds_data_s[ 47: 32]; + dac_data_03 <= dac_dds_data_s[ 63: 48]; + dac_data_04 <= dac_dds_data_s[ 79: 64]; + dac_data_05 <= dac_dds_data_s[ 95: 80]; + dac_data_06 <= dac_dds_data_s[111: 96]; + dac_data_07 <= dac_dds_data_s[127:112]; + dac_data_08 <= dac_dds_data_s[143:128]; + dac_data_09 <= dac_dds_data_s[159:144]; + dac_data_10 <= dac_dds_data_s[175:160]; + dac_data_11 <= dac_dds_data_s[191:176]; + dac_data_12 <= dac_dds_data_s[207:192]; + dac_data_13 <= dac_dds_data_s[223:208]; + dac_data_14 <= dac_dds_data_s[239:224]; + dac_data_15 <= dac_dds_data_s[255:240]; + end + endcase + end + + // dds + + ad_dds #( + .DISABLE (DATAPATH_DISABLE), + .DDS_DW (16), + .PHASE_DW (16), + .DDS_TYPE (DAC_DDS_TYPE), + .CORDIC_DW (DAC_DDS_CORDIC_DW), + .CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .CLK_RATIO (16) + ) i_dds ( + .clk (dac_div_clk), + .dac_dds_format (dac_dds_format), + .dac_data_sync (dac_data_sync), + .dac_valid (1'b1), + .tone_1_scale (dac_dds_scale_1_s), + .tone_2_scale (dac_dds_scale_2_s), + .tone_1_init_offset (dac_dds_init_1_s), + .tone_2_init_offset (dac_dds_init_2_s), + .tone_1_freq_word (dac_dds_incr_1_s), + .tone_2_freq_word (dac_dds_incr_2_s), + .dac_dds_data (dac_dds_data_s)); + + // single channel processor + + up_dac_channel #( + .CHANNEL_ID(CHANNEL_ID) + ) i_up_dac_channel ( + .dac_clk (dac_div_clk), + .dac_rst (dac_rst), + .dac_dds_scale_1 (dac_dds_scale_1_s), + .dac_dds_init_1 (dac_dds_init_1_s), + .dac_dds_incr_1 (dac_dds_incr_1_s), + .dac_dds_scale_2 (dac_dds_scale_2_s), + .dac_dds_init_2 (dac_dds_init_2_s), + .dac_dds_incr_2 (dac_dds_incr_2_s), + .dac_pat_data_1 (dac_pat_data_1_s), + .dac_pat_data_2 (dac_pat_data_2_s), + .dac_data_sel (dac_data_sel_s), + .dac_iq_mode (), + .dac_iqcor_enb (), + .dac_iqcor_coeff_1 (), + .dac_iqcor_coeff_2 (), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_interpolation_m (), + .up_usr_interpolation_n (), + .dac_usr_datatype_be (1'b0), + .dac_usr_datatype_signed (1'b1), + .dac_usr_datatype_shift (8'd0), + .dac_usr_datatype_total_bits (8'd16), + .dac_usr_datatype_bits (8'd16), + .dac_usr_interpolation_m (16'd1), + .dac_usr_interpolation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ad9739a/axi_ad9739a_core.v b/adi_library/axi_ad9739a/axi_ad9739a_core.v new file mode 100644 index 00000000..3a31641f --- /dev/null +++ b/adi_library/axi_ad9739a/axi_ad9739a_core.v @@ -0,0 +1,220 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9739a_core #( + + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter DAC_DDS_TYPE = 1, + parameter DAC_DDS_CORDIC_DW = 16, + parameter DAC_DDS_CORDIC_PHASE_DW = 16, + parameter DATAPATH_DISABLE = 0 +) ( + + // dac interface + + input dac_div_clk, + output dac_rst, + output [ 15:0] dac_data_00, + output [ 15:0] dac_data_01, + output [ 15:0] dac_data_02, + output [ 15:0] dac_data_03, + output [ 15:0] dac_data_04, + output [ 15:0] dac_data_05, + output [ 15:0] dac_data_06, + output [ 15:0] dac_data_07, + output [ 15:0] dac_data_08, + output [ 15:0] dac_data_09, + output [ 15:0] dac_data_10, + output [ 15:0] dac_data_11, + output [ 15:0] dac_data_12, + output [ 15:0] dac_data_13, + output [ 15:0] dac_data_14, + output [ 15:0] dac_data_15, + input dac_status, + + // dma interface + + output dac_valid, + output dac_enable, + input [255:0] dac_ddata, + input dac_dunf, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [ 13:0] up_waddr, + input [ 31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [ 13:0] up_raddr, + output reg [ 31:0] up_rdata, + output reg up_rack +); + + // internal registers + + // internal signals + + wire dac_sync_s; + wire dac_datafmt_s; + wire [ 31:0] up_rdata_0_s; + wire up_rack_0_s; + wire up_wack_0_s; + wire [ 31:0] up_rdata_s; + wire up_rack_s; + wire up_wack_s; + + // defaults + + assign dac_valid = 1'b1; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_rdata <= up_rdata_s | up_rdata_0_s; + up_rack <= up_rack_s | up_rack_0_s; + up_wack <= up_wack_s | up_wack_0_s; + end + end + + // dac channel + + axi_ad9739a_channel #( + .CHANNEL_ID(0), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .DATAPATH_DISABLE(DATAPATH_DISABLE) + ) i_channel_0 ( + .dac_div_clk (dac_div_clk), + .dac_rst (dac_rst), + .dac_enable (dac_enable), + .dac_data_00 (dac_data_00), + .dac_data_01 (dac_data_01), + .dac_data_02 (dac_data_02), + .dac_data_03 (dac_data_03), + .dac_data_04 (dac_data_04), + .dac_data_05 (dac_data_05), + .dac_data_06 (dac_data_06), + .dac_data_07 (dac_data_07), + .dac_data_08 (dac_data_08), + .dac_data_09 (dac_data_09), + .dac_data_10 (dac_data_10), + .dac_data_11 (dac_data_11), + .dac_data_12 (dac_data_12), + .dac_data_13 (dac_data_13), + .dac_data_14 (dac_data_14), + .dac_data_15 (dac_data_15), + .dma_data (dac_ddata), + .dac_data_sync (dac_sync_s), + .dac_dds_format (dac_datafmt_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_0_s), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_0_s), + .up_rack (up_rack_0_s)); + + // dac common processor interface + + up_dac_common #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE) + ) i_up_dac_common ( + .mmcm_rst (), + .dac_clk (dac_div_clk), + .dac_rst (dac_rst), + .dac_sync (dac_sync_s), + .dac_frame (), + .dac_clksel (), + .dac_custom_wr(), + .dac_custom_rd(32'b0), + .dac_custom_control(), + .dac_status_if_busy(1'b0), + .dac_par_type (), + .dac_par_enb (), + .dac_r1_mode (), + .dac_datafmt (dac_datafmt_s), + .dac_datarate (), + .dac_status (dac_status), + .dac_status_unf (dac_dunf), + .dac_clk_ratio (32'd16), + .up_dac_ce (), + .up_pps_rcounter (31'd0), + .up_pps_status (1'd0), + .up_pps_irq_mask (), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd1), + .up_drp_locked (1'd1), + .up_usr_chanmax (), + .dac_usr_chanmax (8'd1), + .up_dac_gpio_in (32'd0), + .up_dac_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + +endmodule diff --git a/adi_library/axi_ad9739a/axi_ad9739a_if.v b/adi_library/axi_ad9739a/axi_ad9739a_if.v new file mode 100644 index 00000000..c05c5132 --- /dev/null +++ b/adi_library/axi_ad9739a/axi_ad9739a_if.v @@ -0,0 +1,195 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// This is the dac physical interface (drives samples from the low speed clock to the +// dac clock domain. + +`timescale 1ns/100ps + +module axi_ad9739a_if #( + + parameter FPGA_TECHNOLOGY = 0 +) ( + + // dac interface + + input dac_clk_in_p, + input dac_clk_in_n, + output dac_clk_out_p, + output dac_clk_out_n, + output [13:0] dac_data_out_a_p, + output [13:0] dac_data_out_a_n, + output [13:0] dac_data_out_b_p, + output [13:0] dac_data_out_b_n, + + // internal resets and clocks + + input dac_rst, + output dac_clk, + output dac_div_clk, + output reg dac_status, + + // data interface + + input [15:0] dac_data_00, + input [15:0] dac_data_01, + input [15:0] dac_data_02, + input [15:0] dac_data_03, + input [15:0] dac_data_04, + input [15:0] dac_data_05, + input [15:0] dac_data_06, + input [15:0] dac_data_07, + input [15:0] dac_data_08, + input [15:0] dac_data_09, + input [15:0] dac_data_10, + input [15:0] dac_data_11, + input [15:0] dac_data_12, + input [15:0] dac_data_13, + input [15:0] dac_data_14, + input [15:0] dac_data_15 +); + + // internal registers + + // internal signals + + wire dac_clk_in_s; + wire dac_div_clk_s; + + // dac status + + always @(posedge dac_div_clk) begin + if (dac_rst == 1'b1) begin + dac_status <= 1'd0; + end else begin + dac_status <= 1'd1; + end + end + + // dac data output serdes(s) & buffers + + ad_serdes_out #( + .DDR_OR_SDR_N(1), + .DATA_WIDTH(14), + .SERDES_FACTOR(8), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY) + ) i_serdes_out_data_a ( + .rst (dac_rst), + .clk (dac_clk), + .div_clk (dac_div_clk), + .data_oe (1'b1), + .data_s0 (dac_data_00[15:2]), + .data_s1 (dac_data_02[15:2]), + .data_s2 (dac_data_04[15:2]), + .data_s3 (dac_data_06[15:2]), + .data_s4 (dac_data_08[15:2]), + .data_s5 (dac_data_10[15:2]), + .data_s6 (dac_data_12[15:2]), + .data_s7 (dac_data_14[15:2]), + .data_out_se (), + .data_out_p (dac_data_out_a_p), + .data_out_n (dac_data_out_a_n)); + + // dac data output serdes(s) & buffers + + ad_serdes_out #( + .DDR_OR_SDR_N(1), + .DATA_WIDTH(14), + .SERDES_FACTOR(8), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY) + ) i_serdes_out_data_b ( + .rst (dac_rst), + .clk (dac_clk), + .div_clk (dac_div_clk), + .data_oe (1'b1), + .data_s0 (dac_data_01[15:2]), + .data_s1 (dac_data_03[15:2]), + .data_s2 (dac_data_05[15:2]), + .data_s3 (dac_data_07[15:2]), + .data_s4 (dac_data_09[15:2]), + .data_s5 (dac_data_11[15:2]), + .data_s6 (dac_data_13[15:2]), + .data_s7 (dac_data_15[15:2]), + .data_out_se (), + .data_out_p (dac_data_out_b_p), + .data_out_n (dac_data_out_b_n)); + + // dac clock output serdes & buffer + + ad_serdes_out #( + .DDR_OR_SDR_N(1), + .DATA_WIDTH(1), + .SERDES_FACTOR(8), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY) + ) i_serdes_out_clk ( + .rst (dac_rst), + .clk (dac_clk), + .div_clk (dac_div_clk), + .data_oe (1'b1), + .data_s0 (1'b1), + .data_s1 (1'b0), + .data_s2 (1'b1), + .data_s3 (1'b0), + .data_s4 (1'b1), + .data_s5 (1'b0), + .data_s6 (1'b1), + .data_s7 (1'b0), + .data_out_se (), + .data_out_p (dac_clk_out_p), + .data_out_n (dac_clk_out_n)); + + // dac clock input buffers + + IBUFGDS i_dac_clk_in_ibuf ( + .I (dac_clk_in_p), + .IB (dac_clk_in_n), + .O (dac_clk_in_s)); + + BUFG i_dac_clk_in_gbuf ( + .I (dac_clk_in_s), + .O (dac_clk)); + + BUFR #( + .BUFR_DIVIDE("4") + ) i_dac_div_clk_rbuf ( + .CLR (1'b0), + .CE (1'b1), + .I (dac_clk_in_s), + .O (dac_div_clk_s)); + + BUFG i_dac_div_clk_gbuf ( + .I (dac_div_clk_s), + .O (dac_div_clk)); + +endmodule diff --git a/adi_library/axi_ad9739a/axi_ad9739a_ip.tcl b/adi_library/axi_ad9739a/axi_ad9739a_ip.tcl new file mode 100644 index 00000000..61fb51fd --- /dev/null +++ b/adi_library/axi_ad9739a/axi_ad9739a_ip.tcl @@ -0,0 +1,47 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_ad9739a +adi_ip_files axi_ad9739a [list \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ + "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine.v" \ + "$ad_hdl_dir/library/common/ad_dds_2.v" \ + "$ad_hdl_dir/library/common/ad_dds_1.v" \ + "$ad_hdl_dir/library/common/ad_dds.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_serdes_out.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_dac_common.v" \ + "$ad_hdl_dir/library/common/up_dac_channel.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "axi_ad9739a_channel.v" \ + "axi_ad9739a_core.v" \ + "axi_ad9739a_if.v" \ + "axi_ad9739a.v" ] + +adi_ip_properties axi_ad9739a + +adi_init_bd_tcl +adi_ip_bd axi_ad9739a "bd/bd.tcl" + +set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] + +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/axi_ad9739a/bd/bd.tcl b/adi_library/axi_ad9739a/bd/bd.tcl new file mode 100644 index 00000000..dceb9498 --- /dev/null +++ b/adi_library/axi_ad9739a/bd/bd.tcl @@ -0,0 +1,47 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + DEV_PACKAGE \ + SPEED_GRADE \ + FPGA_FAMILY \ + FPGA_TECHNOLOGY" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/axi_ad9739a/component.xml b/adi_library/axi_ad9739a/component.xml new file mode 100644 index 00000000..4e21fe12 --- /dev/null +++ b/adi_library/axi_ad9739a/component.xml @@ -0,0 +1,1259 @@ + + + analog.com + user + axi_ad9739a + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_ad9739a + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 3ef462ac + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_ad9739a + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + b3068069 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f9fe85b1 + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + + + dac_clk_in_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_clk_in_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_clk_out_p + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_clk_out_n + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_data_out_a_p + + out + + 13 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_data_out_a_n + + out + + 13 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_data_out_b_p + + out + + 13 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_data_out_b_n + + out + + 13 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_div_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_enable + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_ddata + + in + + 255 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_dunf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + SERDES_OR_DDR_N + Serdes Or Ddr N + 1 + + + MMCM_OR_BUFIO_N + Mmcm Or Bufio N + 1 + + + DAC_DDS_TYPE + Dac Dds Type + 2 + + + DAC_DDS_CORDIC_DW + Dac Dds Cordic Dw + 16 + + + DAC_DDS_CORDIC_PHASE_DW + Dac Dds Cordic Phase Dw + 16 + + + DAC_DATAPATH_DISABLE + Dac Datapath Disable + 0 + + + IO_DELAY_GROUP + Io Delay Group + dev_if_delay_group + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_00ecfe9a + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + + + choice_pairs_19f99f31 + 0 + 10 + 11 + 12 + 13 + 14 + 20 + 21 + 22 + 23 + 24 + 25 + 30 + + + choice_pairs_28f798a2 + 0 + 1 + 2 + 3 + 4 + + + choice_pairs_fc01a186 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../xilinx/common/up_clock_mon_constr.xdc + xdc + + + ../common/ad_dds.v + verilogSource + + + ../common/ad_dds_1.v + verilogSource + + + ../common/ad_dds_2.v + verilogSource + + + ../common/ad_dds_cordic_pipe.v + verilogSource + + + ../common/ad_dds_sine.v + verilogSource + + + ../common/ad_dds_sine_cordic.v + verilogSource + + + ../xilinx/common/ad_mul.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../xilinx/common/ad_serdes_out.v + verilogSource + + + axi_ad9739a_channel.v + verilogSource + + + axi_ad9739a_core.v + verilogSource + + + axi_ad9739a_if.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_dac_channel.v + verilogSource + + + ../common/up_dac_common.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad9739a.v + verilogSource + CHECKSUM_0cc357b1 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_dds.v + verilogSource + + + ../common/ad_dds_1.v + verilogSource + + + ../common/ad_dds_2.v + verilogSource + + + ../common/ad_dds_cordic_pipe.v + verilogSource + + + ../common/ad_dds_sine.v + verilogSource + + + ../common/ad_dds_sine_cordic.v + verilogSource + + + ../xilinx/common/ad_mul.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../xilinx/common/ad_serdes_out.v + verilogSource + + + axi_ad9739a_channel.v + verilogSource + + + axi_ad9739a_core.v + verilogSource + + + axi_ad9739a_if.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_dac_channel.v + verilogSource + + + ../common/up_dac_common.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad9739a.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_ad9739a_v1_0.tcl + tclSource + CHECKSUM_402bd57a + XGUI_VERSION_2 + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + axi_ad9739a_v1_0 + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + SERDES_OR_DDR_N + Serdes Or Ddr N + 1 + + + MMCM_OR_BUFIO_N + Mmcm Or Bufio N + 1 + + + DAC_DDS_TYPE + Dac Dds Type + 2 + + + DAC_DDS_CORDIC_DW + Dac Dds Cordic Dw + 16 + + + DAC_DDS_CORDIC_PHASE_DW + Dac Dds Cordic Phase Dw + 16 + + + DAC_DATAPATH_DISABLE + Dac Datapath Disable + 0 + + + IO_DELAY_GROUP + Io Delay Group + dev_if_delay_group + + + Component_Name + axi_ad9739a_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_ad9739a_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:42:55Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_ad9739a/temporary_case_dependencies.mk b/adi_library/axi_ad9739a/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/axi_ad9739a/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/axi_ad9739a/xgui/axi_ad9739a_v1_0.tcl b/adi_library/axi_ad9739a/xgui/axi_ad9739a_v1_0.tcl new file mode 100644 index 00000000..fb032941 --- /dev/null +++ b/adi_library/axi_ad9739a/xgui/axi_ad9739a_v1_0.tcl @@ -0,0 +1,193 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DAC_DATAPATH_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_DW" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_PHASE_DW" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_DDS_TYPE" -parent ${Page_0} + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "IO_DELAY_GROUP" -parent ${Page_0} + ipgui::add_param $IPINST -name "MMCM_OR_BUFIO_N" -parent ${Page_0} + ipgui::add_param $IPINST -name "SERDES_OR_DDR_N" -parent ${Page_0} + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } { + # Procedure called to update DAC_DATAPATH_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } { + # Procedure called to validate DAC_DATAPATH_DISABLE + return true +} + +proc update_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } { + # Procedure called to update DAC_DDS_CORDIC_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } { + # Procedure called to validate DAC_DDS_CORDIC_DW + return true +} + +proc update_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } { + # Procedure called to update DAC_DDS_CORDIC_PHASE_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } { + # Procedure called to validate DAC_DDS_CORDIC_PHASE_DW + return true +} + +proc update_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } { + # Procedure called to update DAC_DDS_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } { + # Procedure called to validate DAC_DDS_TYPE + return true +} + +proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to validate DEV_PACKAGE + return true +} + +proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to validate FPGA_FAMILY + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to update IO_DELAY_GROUP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to validate IO_DELAY_GROUP + return true +} + +proc update_PARAM_VALUE.MMCM_OR_BUFIO_N { PARAM_VALUE.MMCM_OR_BUFIO_N } { + # Procedure called to update MMCM_OR_BUFIO_N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.MMCM_OR_BUFIO_N { PARAM_VALUE.MMCM_OR_BUFIO_N } { + # Procedure called to validate MMCM_OR_BUFIO_N + return true +} + +proc update_PARAM_VALUE.SERDES_OR_DDR_N { PARAM_VALUE.SERDES_OR_DDR_N } { + # Procedure called to update SERDES_OR_DDR_N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SERDES_OR_DDR_N { PARAM_VALUE.SERDES_OR_DDR_N } { + # Procedure called to validate SERDES_OR_DDR_N + return true +} + +proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to validate SPEED_GRADE + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY} +} + +proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE} +} + +proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE} +} + +proc update_MODELPARAM_VALUE.SERDES_OR_DDR_N { MODELPARAM_VALUE.SERDES_OR_DDR_N PARAM_VALUE.SERDES_OR_DDR_N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SERDES_OR_DDR_N}] ${MODELPARAM_VALUE.SERDES_OR_DDR_N} +} + +proc update_MODELPARAM_VALUE.MMCM_OR_BUFIO_N { MODELPARAM_VALUE.MMCM_OR_BUFIO_N PARAM_VALUE.MMCM_OR_BUFIO_N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.MMCM_OR_BUFIO_N}] ${MODELPARAM_VALUE.MMCM_OR_BUFIO_N} +} + +proc update_MODELPARAM_VALUE.DAC_DDS_TYPE { MODELPARAM_VALUE.DAC_DDS_TYPE PARAM_VALUE.DAC_DDS_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_DDS_TYPE}] ${MODELPARAM_VALUE.DAC_DDS_TYPE} +} + +proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_DW PARAM_VALUE.DAC_DDS_CORDIC_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_DW} +} + +proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW} +} + +proc update_MODELPARAM_VALUE.DAC_DATAPATH_DISABLE { MODELPARAM_VALUE.DAC_DATAPATH_DISABLE PARAM_VALUE.DAC_DATAPATH_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_DATAPATH_DISABLE}] ${MODELPARAM_VALUE.DAC_DATAPATH_DISABLE} +} + +proc update_MODELPARAM_VALUE.IO_DELAY_GROUP { MODELPARAM_VALUE.IO_DELAY_GROUP PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IO_DELAY_GROUP}] ${MODELPARAM_VALUE.IO_DELAY_GROUP} +} + diff --git a/adi_library/axi_ad9783/Makefile b/adi_library/axi_ad9783/Makefile new file mode 100755 index 00000000..a6b81de3 --- /dev/null +++ b/adi_library/axi_ad9783/Makefile @@ -0,0 +1,35 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_ad9783 + +GENERIC_DEPS += ../common/ad_dds.v +GENERIC_DEPS += ../common/ad_dds_1.v +GENERIC_DEPS += ../common/ad_dds_2.v +GENERIC_DEPS += ../common/ad_dds_cordic_pipe.v +GENERIC_DEPS += ../common/ad_dds_sine.v +GENERIC_DEPS += ../common/ad_dds_sine_cordic.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_dac_channel.v +GENERIC_DEPS += ../common/up_dac_common.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_ad9783.v +GENERIC_DEPS += axi_ad9783_channel.v +GENERIC_DEPS += axi_ad9783_core.v +GENERIC_DEPS += axi_ad9783_if.v + +XILINX_DEPS += ../xilinx/common/ad_mul.v +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/ad_serdes_out.v +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_ad9783_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_ad9783/axi_ad9783.v b/adi_library/axi_ad9783/axi_ad9783.v new file mode 100755 index 00000000..b11d66dc --- /dev/null +++ b/adi_library/axi_ad9783/axi_ad9783.v @@ -0,0 +1,226 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9783 #( + + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter DAC_DDS_TYPE = 2, + parameter DAC_DDS_CORDIC_DW = 16, + parameter DAC_DDS_CORDIC_PHASE_DW = 16, + parameter DAC_DATAPATH_DISABLE = 0 +) ( + + // dac interface + // from dco1_p + input dac_clk_in_p, + // from dco1_n + input dac_clk_in_n, + // to dci_p + output dac_clk_out_p, + // to dci_n + output dac_clk_out_n, + output [ 15:0] dac_data_out_p, + output [ 15:0] dac_data_out_n, + + // dma interface + + output dac_div_clk, + output dac_rst, + output dac_valid, + output dac_enable_0, + output dac_enable_1, + input [ 63:0] dac_ddata_0, + input [ 63:0] dac_ddata_1, + input dac_dunf, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [ 15:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [ 31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [ 15:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot +); + + // internal clocks and resets + + wire dac_rst_s; + wire up_clk; + wire up_rstn; + + // internal signals + + wire [ 15:0] dac_data_a0_s; + wire [ 15:0] dac_data_a1_s; + wire [ 15:0] dac_data_a2_s; + wire [ 15:0] dac_data_a3_s; + wire [ 15:0] dac_data_b0_s; + wire [ 15:0] dac_data_b1_s; + wire [ 15:0] dac_data_b2_s; + wire [ 15:0] dac_data_b3_s; + wire dac_status_s; + wire up_wreq_s; + wire [ 13:0] up_waddr_s; + wire [ 31:0] up_wdata_s; + wire up_wack_s; + wire up_rreq_s; + wire [ 13:0] up_raddr_s; + wire [ 31:0] up_rdata_s; + wire up_rack_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + assign dac_rst = dac_rst_s; + + // device interface + + axi_ad9783_if #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY) + ) i_if ( + .dac_clk_in_p (dac_clk_in_p), + .dac_clk_in_n (dac_clk_in_n), + .dac_clk_out_p (dac_clk_out_p), + .dac_clk_out_n (dac_clk_out_n), + .dac_data_out_p (dac_data_out_p), + .dac_data_out_n (dac_data_out_n), + .dac_rst (dac_rst_s), + .dac_div_clk (dac_div_clk), + .dac_status (dac_status_s), + .dac_data_a0 (dac_data_a0_s), + .dac_data_a1 (dac_data_a1_s), + .dac_data_a2 (dac_data_a2_s), + .dac_data_a3 (dac_data_a3_s), + .dac_data_b0 (dac_data_b0_s), + .dac_data_b1 (dac_data_b1_s), + .dac_data_b2 (dac_data_b2_s), + .dac_data_b3 (dac_data_b3_s)); + + // core + + axi_ad9783_core #( + .ID(ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .DATAPATH_DISABLE(DAC_DATAPATH_DISABLE) + ) i_core ( + .dac_div_clk (dac_div_clk), + .dac_rst (dac_rst_s), + .dac_data_a0 (dac_data_a0_s), + .dac_data_a1 (dac_data_a1_s), + .dac_data_a2 (dac_data_a2_s), + .dac_data_a3 (dac_data_a3_s), + .dac_data_b0 (dac_data_b0_s), + .dac_data_b1 (dac_data_b1_s), + .dac_data_b2 (dac_data_b2_s), + .dac_data_b3 (dac_data_b3_s), + .dac_status (dac_status_s), + .dac_valid (dac_valid), + .dac_enable_0 (dac_enable_0), + .dac_enable_1 (dac_enable_1), + .dac_ddata_0 (dac_ddata_0), + .dac_ddata_1 (dac_ddata_1), + .dac_dunf (dac_dunf), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + +endmodule diff --git a/adi_library/axi_ad9783/axi_ad9783.xpr b/adi_library/axi_ad9783/axi_ad9783.xpr new file mode 100644 index 00000000..ae20dfc4 --- /dev/null +++ b/adi_library/axi_ad9783/axi_ad9783.xpr @@ -0,0 +1,556 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_ad9783/axi_ad9783_channel.v b/adi_library/axi_ad9783/axi_ad9783_channel.v new file mode 100755 index 00000000..f96a11d2 --- /dev/null +++ b/adi_library/axi_ad9783/axi_ad9783_channel.v @@ -0,0 +1,217 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9783_channel #( + + parameter CHANNEL_ID = 32'h0, + parameter DAC_DDS_TYPE = 1, + parameter DAC_DDS_CORDIC_DW = 16, + parameter DAC_DDS_CORDIC_PHASE_DW = 16, + parameter DATAPATH_DISABLE = 0 +) ( + + // dac interface + + input dac_div_clk, + input dac_rst, + output reg dac_enable, + output reg [15:0] dac_data0, + output reg [15:0] dac_data1, + output reg [15:0] dac_data2, + output reg [15:0] dac_data3, + input [63:0] dma_data, + + // processor interface + + input dac_data_sync, + input dac_dds_format, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // internal signals + + wire [63:0] dac_dds_data_s; + wire [15:0] dac_dds_scale_1_s; + wire [15:0] dac_dds_init_1_s; + wire [15:0] dac_dds_incr_1_s; + wire [15:0] dac_dds_scale_2_s; + wire [15:0] dac_dds_init_2_s; + wire [15:0] dac_dds_incr_2_s; + wire [15:0] dac_pat_data_1_s; + wire [15:0] dac_pat_data_2_s; + wire [ 3:0] dac_data_sel_s; + + reg [23:0] dac_prbs_data = 'd0; + reg [15:0] dac_prbs_counter = 'd0; + + // pn23 function + function [23:0] pn23; + input [23:0] din; + reg [23:0] dout; + begin + dout = {din[22:0], din[22] ^ din[17]}; + pn23 = dout; + end + endfunction + + // dac data select + + always @(posedge dac_div_clk) begin + dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; + case (dac_data_sel_s) + 4'h2: begin + dac_data0 <= dma_data[15: 0]; + dac_data1 <= dma_data[31:16]; + dac_data2 <= dma_data[47:32]; + dac_data3 <= dma_data[63:48]; + end + 4'h3: begin + dac_data0 <= 16'h0; + dac_data1 <= 16'h0; + dac_data2 <= 16'h0; + dac_data3 <= 16'h0; + end + 4'h9: begin + dac_data0 <= dac_prbs_data[15:0]; + dac_data1 <= dac_prbs_data[23:8]; + dac_data2 <= dac_prbs_data[15:0]; + dac_data3 <= dac_prbs_data[23:8]; + end + default: begin + dac_data0 <= dac_dds_data_s[15: 0]; + dac_data1 <= dac_dds_data_s[31:16]; + dac_data2 <= dac_dds_data_s[47:32]; + dac_data3 <= dac_dds_data_s[63:48]; + end + endcase + end + + always @(posedge dac_div_clk) begin + if(dac_data_sel_s != 9) begin + dac_prbs_data <= 24'hffffff; + dac_prbs_counter <= 16'h0; + end else begin + if (dac_prbs_counter == 4096) begin + dac_prbs_data <= 24'h0; + end else begin + dac_prbs_data <= pn23(dac_prbs_data); + dac_prbs_counter <= dac_prbs_counter + 1; + end + end + end + + // dds + + ad_dds #( + .DISABLE (DATAPATH_DISABLE), + .DDS_DW (16), + .PHASE_DW (16), + .DDS_TYPE (DAC_DDS_TYPE), + .CORDIC_DW (DAC_DDS_CORDIC_DW), + .CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .CLK_RATIO (4) + ) i_dds ( + .clk (dac_div_clk), + .dac_dds_format (dac_dds_format), + .dac_data_sync (dac_data_sync), + .dac_valid (1'b1), + .tone_1_scale (dac_dds_scale_1_s), + .tone_2_scale (dac_dds_scale_2_s), + .tone_1_init_offset (dac_dds_init_1_s), + .tone_2_init_offset (dac_dds_init_2_s), + .tone_1_freq_word (dac_dds_incr_1_s), + .tone_2_freq_word (dac_dds_incr_2_s), + .dac_dds_data (dac_dds_data_s)); + + // single channel processor + + up_dac_channel #( + .CHANNEL_ID(CHANNEL_ID) + ) i_up_dac_channel ( + .dac_clk (dac_div_clk), + .dac_rst (dac_rst), + .dac_dds_scale_1 (dac_dds_scale_1_s), + .dac_dds_init_1 (dac_dds_init_1_s), + .dac_dds_incr_1 (dac_dds_incr_1_s), + .dac_dds_scale_2 (dac_dds_scale_2_s), + .dac_dds_init_2 (dac_dds_init_2_s), + .dac_dds_incr_2 (dac_dds_incr_2_s), + .dac_pat_data_1 (dac_pat_data_1_s), + .dac_pat_data_2 (dac_pat_data_2_s), + .dac_data_sel (dac_data_sel_s), + .dac_iq_mode (), + .dac_iqcor_enb (), + .dac_iqcor_coeff_1 (), + .dac_iqcor_coeff_2 (), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_interpolation_m (), + .up_usr_interpolation_n (), + .dac_usr_datatype_be (1'b0), + .dac_usr_datatype_signed (1'b1), + .dac_usr_datatype_shift (8'd0), + .dac_usr_datatype_total_bits (8'd16), + .dac_usr_datatype_bits (8'd16), + .dac_usr_interpolation_m (16'd1), + .dac_usr_interpolation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ad9783/axi_ad9783_core.v b/adi_library/axi_ad9783/axi_ad9783_core.v new file mode 100755 index 00000000..749c7cb1 --- /dev/null +++ b/adi_library/axi_ad9783/axi_ad9783_core.v @@ -0,0 +1,237 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9783_core #( + + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter DAC_DDS_TYPE = 1, + parameter DAC_DDS_CORDIC_DW = 16, + parameter DAC_DDS_CORDIC_PHASE_DW = 16, + parameter DATAPATH_DISABLE = 0 +) ( + + // dac interface + + input dac_div_clk, + output dac_rst, + output [ 15:0] dac_data_a0, + output [ 15:0] dac_data_a1, + output [ 15:0] dac_data_a2, + output [ 15:0] dac_data_a3, + output [ 15:0] dac_data_b0, + output [ 15:0] dac_data_b1, + output [ 15:0] dac_data_b2, + output [ 15:0] dac_data_b3, + input dac_status, + + // dma interface + + output dac_valid, + output dac_enable_0, + output dac_enable_1, + input [ 63:0] dac_ddata_0, + input [ 63:0] dac_ddata_1, + input dac_dunf, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [ 13:0] up_waddr, + input [ 31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [ 13:0] up_raddr, + output reg [ 31:0] up_rdata, + output reg up_rack +); + + // internal registers + + // internal signals + + wire dac_sync_s; + wire dac_datafmt_s; + wire [ 31:0] up_rdata_0_s; + wire up_rack_0_s; + wire up_wack_0_s; + wire [ 31:0] up_rdata_1_s; + wire up_rack_1_s; + wire up_wack_1_s; + wire [ 31:0] up_rdata_s; + wire up_rack_s; + wire up_wack_s; + wire dac_enable_0_reg; + wire dac_enable_1_reg; + + // defaults + + assign dac_valid = 1'b1; + assign dac_enable_0 = dac_enable_0_reg; + assign dac_enable_1 = dac_enable_1_reg; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_rdata <= up_rdata_s | up_rdata_0_s | up_rdata_1_s; + up_rack <= up_rack_s | up_rack_0_s | up_rack_1_s; + up_wack <= up_wack_s | up_wack_0_s | up_wack_1_s; + end + end + + // dac channel + + axi_ad9783_channel #( + .CHANNEL_ID(0), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .DATAPATH_DISABLE(DATAPATH_DISABLE) + ) i_channel_0 ( + .dac_div_clk (dac_div_clk), + .dac_rst (dac_rst), + .dac_enable (dac_enable_0_reg), + .dac_data0 (dac_data_a0), + .dac_data1 (dac_data_a1), + .dac_data2 (dac_data_a2), + .dac_data3 (dac_data_a3), + .dma_data (dac_ddata_0), + .dac_data_sync (dac_sync_s), + .dac_dds_format (dac_datafmt_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_0_s), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_0_s), + .up_rack (up_rack_0_s)); + + axi_ad9783_channel #( + .CHANNEL_ID(1), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .DATAPATH_DISABLE(DATAPATH_DISABLE) + ) i_channel_1 ( + .dac_div_clk (dac_div_clk), + .dac_rst (dac_rst), + .dac_enable (dac_enable_1_reg), + .dac_data0 (dac_data_b0), + .dac_data1 (dac_data_b1), + .dac_data2 (dac_data_b2), + .dac_data3 (dac_data_b3), + .dma_data (dac_ddata_1), + .dac_data_sync (dac_sync_s), + .dac_dds_format (dac_datafmt_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_1_s), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_1_s), + .up_rack (up_rack_1_s)); + + // dac common processor interface + + up_dac_common #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE) + ) i_up_dac_common ( + .mmcm_rst (), + .dac_clk (dac_div_clk), + .dac_rst (dac_rst), + .dac_sync (dac_sync_s), + .dac_frame (), + .dac_clksel (), + .dac_custom_wr(), + .dac_custom_rd(32'b0), + .dac_custom_control(), + .dac_status_if_busy(1'b0), + .dac_par_type (), + .dac_par_enb (), + .dac_r1_mode (), + .dac_datafmt (dac_datafmt_s), + .dac_datarate (), + .dac_status (dac_status), + .dac_status_unf (dac_dunf), + .dac_clk_ratio (32'd16), + .up_dac_ce (), + .up_pps_rcounter (31'd0), + .up_pps_status (1'd0), + .up_pps_irq_mask (), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd1), + .up_drp_locked (1'd1), + .up_usr_chanmax (), + .dac_usr_chanmax (8'd1), + .up_dac_gpio_in (32'd0), + .up_dac_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + +endmodule diff --git a/adi_library/axi_ad9783/axi_ad9783_if.v b/adi_library/axi_ad9783/axi_ad9783_if.v new file mode 100755 index 00000000..b6385444 --- /dev/null +++ b/adi_library/axi_ad9783/axi_ad9783_if.v @@ -0,0 +1,160 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// This is the dac physical interface (drives samples from the low speed clock to the +// dac clock domain. + +`timescale 1ns/100ps + +module axi_ad9783_if #( + + parameter FPGA_TECHNOLOGY = 0 +) ( + + // dac interface + + input dac_clk_in_p, + input dac_clk_in_n, + output dac_clk_out_p, + output dac_clk_out_n, + output [15:0] dac_data_out_p, + output [15:0] dac_data_out_n, + + // internal resets and clocks + + input dac_rst, + output dac_div_clk, + output reg dac_status, + + // data interface + + input [15:0] dac_data_a0, + input [15:0] dac_data_a1, + input [15:0] dac_data_a2, + input [15:0] dac_data_a3, + input [15:0] dac_data_b0, + input [15:0] dac_data_b1, + input [15:0] dac_data_b2, + input [15:0] dac_data_b3 +); + + // internal registers + + // internal signals + + wire dac_clk_in_s; + wire dac_div_clk_s; + wire dac_clk_s; + + // dac status + + always @(posedge dac_div_clk) begin + if (dac_rst == 1'b1) begin + dac_status <= 1'd0; + end else begin + dac_status <= 1'd1; + end + end + + // dac data output serdes(s) & buffers + + ad_serdes_out #( + .DDR_OR_SDR_N(1), + .DATA_WIDTH(16), + .SERDES_FACTOR(8), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY) + ) i_serdes_out_data ( + .rst (dac_rst), + .clk (dac_clk_s), + .div_clk (dac_div_clk), + .data_oe (1'b1), + .data_s0 (dac_data_a0), + .data_s1 (dac_data_b0), + .data_s2 (dac_data_a1), + .data_s3 (dac_data_b1), + .data_s4 (dac_data_a2), + .data_s5 (dac_data_b2), + .data_s6 (dac_data_a3), + .data_s7 (dac_data_b3), + .data_out_se (), + .data_out_p (dac_data_out_p), + .data_out_n (dac_data_out_n)); + + // dac clock output serdes & buffer + + ad_serdes_out #( + .DDR_OR_SDR_N(1), + .DATA_WIDTH(1), + .SERDES_FACTOR(8), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY) + ) i_serdes_out_clk ( + .rst (dac_rst), + .clk (dac_clk_s), + .div_clk (dac_div_clk), + .data_oe (1'b1), + .data_s0 (1'b1), + .data_s1 (1'b0), + .data_s2 (1'b1), + .data_s3 (1'b0), + .data_s4 (1'b1), + .data_s5 (1'b0), + .data_s6 (1'b1), + .data_s7 (1'b0), + .data_out_se (), + .data_out_p (dac_clk_out_p), + .data_out_n (dac_clk_out_n)); + + // dac clock input buffers + + IBUFGDS i_dac_clk_in_ibuf ( + .I (dac_clk_in_p), + .IB (dac_clk_in_n), + .O (dac_clk_s)); + + BUFGCE_DIV #( + .BUFGCE_DIVIDE (4), + .IS_CE_INVERTED (1'b0), + .IS_CLR_INVERTED (1'b0), + .IS_I_INVERTED (1'b0) + ) i_dac_div_clk_rbuf ( + .O (dac_div_clk_s), + .CE (1'b1), + .CLR (1'b0), + .I (dac_clk_s)); + + BUFG i_dac_div_clk_gbuf ( + .I (dac_div_clk_s), + .O (dac_div_clk)); + +endmodule diff --git a/adi_library/axi_ad9783/axi_ad9783_ip.tcl b/adi_library/axi_ad9783/axi_ad9783_ip.tcl new file mode 100755 index 00000000..27739ff8 --- /dev/null +++ b/adi_library/axi_ad9783/axi_ad9783_ip.tcl @@ -0,0 +1,48 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_ad9783 +adi_ip_files axi_ad9783 [list \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ + "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine.v" \ + "$ad_hdl_dir/library/common/ad_dds_2.v" \ + "$ad_hdl_dir/library/common/ad_dds_1.v" \ + "$ad_hdl_dir/library/common/ad_dds.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_serdes_out.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_dac_common.v" \ + "$ad_hdl_dir/library/common/up_dac_channel.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "axi_ad9783_channel.v" \ + "axi_ad9783_core.v" \ + "axi_ad9783_if.v" \ + "axi_ad9783.v" ] + +adi_ip_properties axi_ad9783 + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad9783} [ipx::current_core] + +adi_init_bd_tcl +adi_ip_bd axi_ad9783 "bd/bd.tcl" + +set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] + +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + +ipx::save_core [ipx::current_core] diff --git a/adi_library/axi_ad9783/bd/bd.tcl b/adi_library/axi_ad9783/bd/bd.tcl new file mode 100644 index 00000000..dceb9498 --- /dev/null +++ b/adi_library/axi_ad9783/bd/bd.tcl @@ -0,0 +1,47 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + DEV_PACKAGE \ + SPEED_GRADE \ + FPGA_FAMILY \ + FPGA_TECHNOLOGY" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/axi_ad9783/component.xml b/adi_library/axi_ad9783/component.xml new file mode 100644 index 00000000..0be16842 --- /dev/null +++ b/adi_library/axi_ad9783/component.xml @@ -0,0 +1,1238 @@ + + + analog.com + user + axi_ad9783 + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_ad9783 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 9bcf1355 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_ad9783 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 363a7ee4 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + acfb27cb + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + + + dac_clk_in_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_clk_in_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_clk_out_p + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_clk_out_n + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_data_out_p + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_data_out_n + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_div_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_rst + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_enable_0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_enable_1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_ddata_0 + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_ddata_1 + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_dunf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + DAC_DDS_TYPE + Dac Dds Type + 2 + + + DAC_DDS_CORDIC_DW + Dac Dds Cordic Dw + 16 + + + DAC_DDS_CORDIC_PHASE_DW + Dac Dds Cordic Phase Dw + 16 + + + DAC_DATAPATH_DISABLE + Dac Datapath Disable + 0 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_00ecfe9a + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + + + choice_pairs_19f99f31 + 0 + 10 + 11 + 12 + 13 + 14 + 20 + 21 + 22 + 23 + 24 + 25 + 30 + + + choice_pairs_28f798a2 + 0 + 1 + 2 + 3 + 4 + + + choice_pairs_fc01a186 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../xilinx/common/up_clock_mon_constr.xdc + xdc + + + ../common/ad_dds.v + verilogSource + + + ../common/ad_dds_1.v + verilogSource + + + ../common/ad_dds_2.v + verilogSource + + + ../common/ad_dds_cordic_pipe.v + verilogSource + + + ../common/ad_dds_sine.v + verilogSource + + + ../common/ad_dds_sine_cordic.v + verilogSource + + + ../xilinx/common/ad_mul.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../xilinx/common/ad_serdes_out.v + verilogSource + + + axi_ad9783_channel.v + verilogSource + + + axi_ad9783_core.v + verilogSource + + + axi_ad9783_if.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_dac_channel.v + verilogSource + + + ../common/up_dac_common.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad9783.v + verilogSource + CHECKSUM_43e249c6 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_dds.v + verilogSource + + + ../common/ad_dds_1.v + verilogSource + + + ../common/ad_dds_2.v + verilogSource + + + ../common/ad_dds_cordic_pipe.v + verilogSource + + + ../common/ad_dds_sine.v + verilogSource + + + ../common/ad_dds_sine_cordic.v + verilogSource + + + ../xilinx/common/ad_mul.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../xilinx/common/ad_serdes_out.v + verilogSource + + + axi_ad9783_channel.v + verilogSource + + + axi_ad9783_core.v + verilogSource + + + axi_ad9783_if.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_dac_channel.v + verilogSource + + + ../common/up_dac_common.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad9783.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_ad9783_v1_0.tcl + tclSource + CHECKSUM_668e552f + XGUI_VERSION_2 + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + axi_ad9783_v1_0 + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + DAC_DDS_TYPE + Dac Dds Type + 2 + + + DAC_DDS_CORDIC_DW + Dac Dds Cordic Dw + 16 + + + DAC_DDS_CORDIC_PHASE_DW + Dac Dds Cordic Phase Dw + 16 + + + DAC_DATAPATH_DISABLE + Dac Datapath Disable + 0 + + + Component_Name + axi_ad9783_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_ad9783_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_ad9783 + 1 + 2024-01-14T03:43:14Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_ad9783/temporary_case_dependencies.mk b/adi_library/axi_ad9783/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/axi_ad9783/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/axi_ad9783/xgui/axi_ad9783_v1_0.tcl b/adi_library/axi_ad9783/xgui/axi_ad9783_v1_0.tcl new file mode 100644 index 00000000..bbabe95a --- /dev/null +++ b/adi_library/axi_ad9783/xgui/axi_ad9783_v1_0.tcl @@ -0,0 +1,148 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DAC_DATAPATH_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_DW" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_PHASE_DW" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_DDS_TYPE" -parent ${Page_0} + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } { + # Procedure called to update DAC_DATAPATH_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } { + # Procedure called to validate DAC_DATAPATH_DISABLE + return true +} + +proc update_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } { + # Procedure called to update DAC_DDS_CORDIC_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } { + # Procedure called to validate DAC_DDS_CORDIC_DW + return true +} + +proc update_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } { + # Procedure called to update DAC_DDS_CORDIC_PHASE_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } { + # Procedure called to validate DAC_DDS_CORDIC_PHASE_DW + return true +} + +proc update_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } { + # Procedure called to update DAC_DDS_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } { + # Procedure called to validate DAC_DDS_TYPE + return true +} + +proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to validate DEV_PACKAGE + return true +} + +proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to validate FPGA_FAMILY + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to validate SPEED_GRADE + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY} +} + +proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE} +} + +proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE} +} + +proc update_MODELPARAM_VALUE.DAC_DDS_TYPE { MODELPARAM_VALUE.DAC_DDS_TYPE PARAM_VALUE.DAC_DDS_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_DDS_TYPE}] ${MODELPARAM_VALUE.DAC_DDS_TYPE} +} + +proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_DW PARAM_VALUE.DAC_DDS_CORDIC_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_DW} +} + +proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW} +} + +proc update_MODELPARAM_VALUE.DAC_DATAPATH_DISABLE { MODELPARAM_VALUE.DAC_DATAPATH_DISABLE PARAM_VALUE.DAC_DATAPATH_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_DATAPATH_DISABLE}] ${MODELPARAM_VALUE.DAC_DATAPATH_DISABLE} +} + diff --git a/adi_library/axi_ad9963/Makefile b/adi_library/axi_ad9963/Makefile new file mode 100644 index 00000000..906729ec --- /dev/null +++ b/adi_library/axi_ad9963/Makefile @@ -0,0 +1,46 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_ad9963 + +GENERIC_DEPS += ../common/ad_datafmt.v +GENERIC_DEPS += ../common/ad_dds.v +GENERIC_DEPS += ../common/ad_dds_1.v +GENERIC_DEPS += ../common/ad_dds_2.v +GENERIC_DEPS += ../common/ad_dds_cordic_pipe.v +GENERIC_DEPS += ../common/ad_dds_sine.v +GENERIC_DEPS += ../common/ad_dds_sine_cordic.v +GENERIC_DEPS += ../common/ad_iqcor.v +GENERIC_DEPS += ../common/ad_pnmon.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_adc_channel.v +GENERIC_DEPS += ../common/up_adc_common.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_dac_channel.v +GENERIC_DEPS += ../common/up_dac_common.v +GENERIC_DEPS += ../common/up_delay_cntrl.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_ad9963.v +GENERIC_DEPS += axi_ad9963_if.v +GENERIC_DEPS += axi_ad9963_rx.v +GENERIC_DEPS += axi_ad9963_rx_channel.v +GENERIC_DEPS += axi_ad9963_rx_pnmon.v +GENERIC_DEPS += axi_ad9963_tx.v +GENERIC_DEPS += axi_ad9963_tx_channel.v + +XILINX_DEPS += ../xilinx/common/ad_data_in.v +XILINX_DEPS += ../xilinx/common/ad_dcfilter.v +XILINX_DEPS += ../xilinx/common/ad_mul.v +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_ad9963_constr.xdc +XILINX_DEPS += axi_ad9963_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_ad9963/axi_ad9963.v b/adi_library/axi_ad9963/axi_ad9963.v new file mode 100644 index 00000000..c1b84551 --- /dev/null +++ b/adi_library/axi_ad9963/axi_ad9963.v @@ -0,0 +1,332 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9963 #( + + // parameters + + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter ADC_IODELAY_ENABLE = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group", + parameter IODELAY_ENABLE = 0, + parameter DAC_DDS_TYPE = 1, + parameter DAC_DDS_CORDIC_DW = 14, + parameter DAC_DDS_CORDIC_PHASE_DW = 13, + parameter DAC_DATAPATH_DISABLE = 0, + parameter ADC_USERPORTS_DISABLE = 0, + parameter ADC_DATAFORMAT_DISABLE = 0, + parameter ADC_DCFILTER_DISABLE = 0, + parameter ADC_IQCORRECTION_DISABLE = 0, + parameter ADC_SCALECORRECTION_ONLY = 1, + parameter DELAY_REFCLK_FREQUENCY = 200 +) ( + + // physical interface (receive) + + input trx_clk, + input trx_iq, + input [11:0] trx_data, + + // physical interface (transmit) + + input tx_clk, + output tx_iq, + output [11:0] tx_data, + + // transmit master/slave + + input dac_sync_in, + output dac_sync_out, + + // delay clock + + input delay_clk, + + // master interface + + output adc_clk, + output dac_clk, + output adc_rst, + output dac_rst, + + // dma interface + + output adc_enable_i, + output adc_valid_i, + output [15:0] adc_data_i, + output adc_enable_q, + output adc_valid_q, + output [15:0] adc_data_q, + input adc_dovf, + + output dac_enable_i, + output dac_valid_i, + input [15:0] dac_data_i, + input dma_valid_i, + output dac_enable_q, + output dac_valid_q, + input [15:0] dac_data_q, + input dma_valid_q, + input dac_dunf, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready +); + + // internal registers + + reg up_wack = 'd0; + reg up_rack = 'd0; + reg [31:0] up_rdata = 'd0; + + // internal clocks and resets + + wire up_clk; + wire up_rstn; + wire delay_rst; + + // internal signals + + wire adc_valid_s; + wire [23:0] adc_data_s; + wire adc_status_s; + wire [23:0] dac_data_s; + wire [12:0] up_adc_dld_s; + wire [64:0] up_adc_dwdata_s; + wire [64:0] up_adc_drdata_s; + wire delay_locked_s; + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire up_wack_rx_s; + wire up_wack_tx_s; + wire up_rreq_s; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_rx_s; + wire up_rack_rx_s; + wire [31:0] up_rdata_tx_s; + wire up_rack_tx_s; + wire up_adc_ce; + wire up_dac_ce; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // processor read interface + + always @(*) begin + up_wack = up_wack_rx_s | up_wack_tx_s; + up_rack = up_rack_rx_s | up_rack_tx_s; + up_rdata = up_rdata_rx_s | up_rdata_tx_s; + end + + // device interface + + axi_ad9963_if #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .ADC_IODELAY_ENABLE (ADC_IODELAY_ENABLE), + .IO_DELAY_GROUP (IO_DELAY_GROUP), + .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_dev_if ( + .trx_clk (trx_clk), + .trx_iq (trx_iq), + .trx_data (trx_data), + .tx_clk (tx_clk), + .tx_iq (tx_iq), + .tx_data (tx_data), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .adc_valid (adc_valid_s), + .adc_data (adc_data_s), + .adc_status (adc_status_s), + .up_adc_ce(up_adc_ce), + .dac_data (dac_data_s), + .up_dac_ce(up_dac_ce), + .up_clk (up_clk), + .up_adc_dld (up_adc_dld_s), + .up_adc_dwdata (up_adc_dwdata_s), + .up_adc_drdata (up_adc_drdata_s), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s)); + + // receive + + axi_ad9963_rx #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .USERPORTS_DISABLE (ADC_USERPORTS_DISABLE), + .DATAFORMAT_DISABLE (ADC_DATAFORMAT_DISABLE), + .DCFILTER_DISABLE (ADC_DCFILTER_DISABLE), + .IQCORRECTION_DISABLE (ADC_IQCORRECTION_DISABLE), + .SCALECORRECTION_ONLY (ADC_SCALECORRECTION_ONLY), + .IODELAY_ENABLE (ADC_IODELAY_ENABLE) + ) i_rx ( + .adc_rst (adc_rst), + .adc_clk (adc_clk), + .adc_valid (adc_valid_s), + .adc_data (adc_data_s), + .adc_status (adc_status_s), + .up_adc_ce(up_adc_ce), + .up_dld (up_adc_dld_s), + .up_dwdata (up_adc_dwdata_s), + .up_drdata (up_adc_drdata_s), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s), + .adc_enable_i (adc_enable_i), + .adc_valid_i (adc_valid_i), + .adc_data_i (adc_data_i), + .adc_enable_q (adc_enable_q), + .adc_valid_q (adc_valid_q), + .adc_data_q (adc_data_q), + .adc_dovf (adc_dovf), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_rx_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_rx_s), + .up_rack (up_rack_rx_s)); + + // transmit + + axi_ad9963_tx #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .DATAPATH_DISABLE (DAC_DATAPATH_DISABLE) + ) i_tx ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_data (dac_data_s), + .adc_data (adc_data_s), + .dac_sync_in (dac_sync_in), + .dac_sync_out (dac_sync_out), + .dac_enable_i (dac_enable_i), + .dac_valid_i (dac_valid_i), + .dac_data_i (dac_data_i), + .dma_valid_i (dma_valid_i), + .dac_enable_q (dac_enable_q), + .dac_valid_q (dac_valid_q), + .dac_data_q (dac_data_q), + .dma_valid_q (dma_valid_q), + .dac_dunf(dac_dunf), + .up_dac_ce(up_dac_ce), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_tx_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_tx_s), + .up_rack (up_rack_tx_s)); + + // axi interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ad9963/axi_ad9963.xpr b/adi_library/axi_ad9963/axi_ad9963.xpr new file mode 100644 index 00000000..1f101fd1 --- /dev/null +++ b/adi_library/axi_ad9963/axi_ad9963.xpr @@ -0,0 +1,632 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_ad9963/axi_ad9963_constr.xdc b/adi_library/axi_ad9963/axi_ad9963_constr.xdc new file mode 100644 index 00000000..fffa0bf6 --- /dev/null +++ b/adi_library/axi_ad9963/axi_ad9963_constr.xdc @@ -0,0 +1,6 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_false_path -from [get_cells -hier -filter {name =~ *up_*clk_enb* && IS_SEQUENTIAL}] -to [get_pins -hier -filter {name =~ *bufgctrl*/S0}] diff --git a/adi_library/axi_ad9963/axi_ad9963_if.v b/adi_library/axi_ad9963/axi_ad9963_if.v new file mode 100644 index 00000000..de4e4f13 --- /dev/null +++ b/adi_library/axi_ad9963/axi_ad9963_if.v @@ -0,0 +1,250 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9963_if #( + + // this parameter controls the buffer type based on the target device. + + parameter FPGA_TECHNOLOGY = 0, + parameter ADC_IODELAY_ENABLE = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group", + parameter DELAY_REFCLK_FREQUENCY = 200 +) ( + + // physical interface (receive) + + input trx_clk, + input trx_iq, + input [11:0] trx_data, + + // physical interface (transmit) + + input tx_clk, + output tx_iq, + output [11:0] tx_data, + + // clock (common to both receive and transmit) + + input adc_rst, + input dac_rst, + output adc_clk, + output dac_clk, + + // receive data path interface + + output reg adc_valid, + output reg [23:0] adc_data, + output reg adc_status, + input up_adc_ce, + + // transmit data path interface + + input [23:0] dac_data, + input up_dac_ce, + + // delay interface + + input up_clk, + input [12:0] up_adc_dld, + input [64:0] up_adc_dwdata, + output [64:0] up_adc_drdata, + input delay_clk, + input delay_rst, + output delay_locked +); + + // internal registers + + reg [11:0] rx_data_p = 0; + + // internal signals + + wire [11:0] rx_data_p_s; + wire [11:0] rx_data_n_s; + wire rx_iq_p_s; + wire rx_iq_n_s; + wire [11:0] tx_data_p; + wire [11:0] tx_data_n; + + wire div_clk; + + genvar l_inst; + + always @(posedge adc_clk) begin + if( rx_iq_p_s == 1'b1) begin + adc_data <= {rx_data_n_s, rx_data_p_s} ; // data[11:00] I + adc_valid <= 1'b1; // data[23:12] Q + end else begin + rx_data_p <= rx_data_p_s; // if this happens it means that risedge data is sampled on falledge + adc_data <= {rx_data_p, rx_data_n_s}; // so we take current N data with previous P data + adc_valid <= 1'b1; // in order to have data sampled at the same instance sent to the DMA + end + end + + assign tx_data_p = dac_data[11: 0]; + assign tx_data_n = dac_data[23:12]; + + always @(posedge adc_clk) begin + if (adc_rst == 1'b1) begin + adc_status <= 1'b0; + end else begin + adc_status <= 1'b1; + end + end + + // device clock interface (receive clock) + + BUFGCTRL #( + .INIT_OUT(0), + .PRESELECT_I0("FALSE"), + .PRESELECT_I1("FALSE") + ) bufgctrl_adc ( + .O(adc_clk), + .CE0(1'b1), + .CE1(1'b0), + .I0(trx_clk), + .I1(1'b0), + .IGNORE0(1'b0), + .IGNORE1(1'b0), + .S0(up_adc_ce), + .S1(1'b0)); + + // receive data interface, ibuf -> idelay -> iddr + + generate + for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_rx_data + ad_data_in #( + .SINGLE_ENDED (1), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_ENABLE (ADC_IODELAY_ENABLE), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_rx_data ( + .rx_clk (adc_clk), + .rx_data_in_p (trx_data[l_inst]), + .rx_data_in_n (1'b0), + .rx_data_p (rx_data_p_s[l_inst]), + .rx_data_n (rx_data_n_s[l_inst]), + .up_clk (up_clk), + .up_dld (up_adc_dld[l_inst]), + .up_dwdata (up_adc_dwdata[((l_inst*5)+4):(l_inst*5)]), + .up_drdata (up_adc_drdata[((l_inst*5)+4):(l_inst*5)]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + endgenerate + + // receive iq interface, ibuf -> idelay -> iddr + + ad_data_in #( + .SINGLE_ENDED (1), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_ENABLE (ADC_IODELAY_ENABLE), + .IODELAY_CTRL (1), + .IODELAY_GROUP (IO_DELAY_GROUP) + ) i_rx_iq ( + .rx_clk (adc_clk), + .rx_data_in_p (trx_iq), + .rx_data_in_n (1'b0), + .rx_data_p (rx_iq_p_s), + .rx_data_n (rx_iq_n_s), + .up_clk (up_clk), + .up_dld (up_adc_dld[12]), + .up_dwdata (up_adc_dwdata[64:60]), + .up_drdata (up_adc_drdata[64:60]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked)); + + // transmit data interface + + BUFR #( + .BUFR_DIVIDE(2) + ) i_div_clk_buf ( + .CLR (1'b0), + .CE (1'b1), + .I (tx_clk), + .O (div_clk)); + + BUFGCTRL #( + .INIT_OUT(0), + .PRESELECT_I0("FALSE"), + .PRESELECT_I1("FALSE") + ) bufgctrl_dac ( + .O(dac_clk), + .CE0(1'b1), + .CE1(1'b0), + .I0(div_clk), + .I1(1'b0), + .IGNORE0(1'b0), + .IGNORE1(1'b0), + .S0(up_dac_ce), + .S1(1'b0)); + + generate + for (l_inst = 0; l_inst <= 11; l_inst = l_inst + 1) begin: g_tx_data + ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE"), + .INIT (1'b0), + .SRTYPE ("SYNC") + ) i_tx_data_oddr ( + .CE (1'b1), + .R (dac_rst), + .S (1'b0), + .C (dac_clk), + .D1 (tx_data_p[l_inst]), + .D2 (tx_data_n[l_inst]), + .Q (tx_data[l_inst])); + end + endgenerate + + ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE"), + .INIT (1'b0), + .SRTYPE ("SYNC") + ) i_tx_data_oddr ( + .CE (1'b1), + .R (dac_rst), + .S (1'b0), + .C (dac_clk), + .D1 (1'b1), + .D2 (1'b0), + .Q (tx_iq)); + +endmodule diff --git a/adi_library/axi_ad9963/axi_ad9963_ip.tcl b/adi_library/axi_ad9963/axi_ad9963_ip.tcl new file mode 100644 index 00000000..b4ee1692 --- /dev/null +++ b/adi_library/axi_ad9963/axi_ad9963_ip.tcl @@ -0,0 +1,75 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_ad9963 +adi_ip_files axi_ad9963 [list \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ + "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine.v" \ + "$ad_hdl_dir/library/common/ad_dds_2.v" \ + "$ad_hdl_dir/library/common/ad_dds_1.v" \ + "$ad_hdl_dir/library/common/ad_dds.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/ad_iqcor.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/up_dac_common.v" \ + "$ad_hdl_dir/library/common/up_dac_channel.v" \ + "axi_ad9963_constr.xdc" \ + "axi_ad9963_if.v" \ + "axi_ad9963_rx_pnmon.v" \ + "axi_ad9963_rx_channel.v" \ + "axi_ad9963_rx.v" \ + "axi_ad9963_tx_channel.v" \ + "axi_ad9963_tx.v" \ + "axi_ad9963.v" ] + +adi_ip_properties axi_ad9963 + +adi_init_bd_tcl +adi_ip_bd axi_ad9963 "bd/bd.tcl" + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_ad9963} [ipx::current_core] + +set_property driver_value 0 [ipx::get_ports *dac_sync_in* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] + +adi_set_ports_dependency "delay_clk" \ + "(spirit:decode(id('MODELPARAM_VALUE.ADC_IODELAY_ENABLE')) = 1)" 0 + +ipx::infer_bus_interface trx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + +ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/axi_ad9963/axi_ad9963_rx.v b/adi_library/axi_ad9963/axi_ad9963_rx.v new file mode 100644 index 00000000..3fe3ecb5 --- /dev/null +++ b/adi_library/axi_ad9963/axi_ad9963_rx.v @@ -0,0 +1,320 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9963_rx #( + + // parameters + + parameter USERPORTS_DISABLE = 0, + parameter DATAFORMAT_DISABLE = 0, + parameter DCFILTER_DISABLE = 0, + parameter IQCORRECTION_DISABLE = 0, + parameter SCALECORRECTION_ONLY = 1, + parameter IODELAY_ENABLE = 0, + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0 +) ( + + // adc interface + + output adc_rst, + input adc_clk, + input adc_valid, + input [23:0] adc_data, + input adc_status, + + // delay interface + + output [12:0] up_dld, + output [64:0] up_dwdata, + input [64:0] up_drdata, + input delay_clk, + output delay_rst, + input delay_locked, + + // dma interface + + output adc_enable_i, + output adc_valid_i, + output [15:0] adc_data_i, + output adc_enable_q, + output adc_valid_q, + output [15:0] adc_data_q, + input adc_dovf, + + output up_adc_ce, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack +); + + // configuration settings + + localparam CONFIG = (SCALECORRECTION_ONLY * 512) + + (0 * 16) + + (USERPORTS_DISABLE * 8) + + (DATAFORMAT_DISABLE * 4) + + (DCFILTER_DISABLE * 2) + + (IQCORRECTION_DISABLE * 1); + + // internal registers + + reg up_status_pn_err = 'd0; + reg up_status_pn_oos = 'd0; + reg up_status_or = 'd0; + + // internal signals + + wire [15:0] adc_dcfilter_data_out_0_s; + wire [15:0] adc_dcfilter_data_out_1_s; + wire [ 1:0] up_adc_pn_err_s; + wire [ 1:0] up_adc_pn_oos_s; + wire [ 1:0] up_adc_or_s; + wire [31:0] up_rdata_s[0:3]; + wire up_rack_s[0:3]; + wire up_wack_s[0:3]; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_status_pn_err <= 'd0; + up_status_pn_oos <= 'd0; + up_status_or <= 'd0; + end else begin + up_status_pn_err <= | up_adc_pn_err_s; + up_status_pn_oos <= | up_adc_pn_oos_s; + up_status_or <= | up_adc_or_s; + end + end + + always @(*) begin + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3]; + up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3]; + up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3]; + end + + // channel 0 (i) + + axi_ad9963_rx_channel #( + .Q_OR_I_N(0), + .CHANNEL_ID(0), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), + .DCFILTER_DISABLE (DCFILTER_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE), + .SCALECORRECTION_ONLY (SCALECORRECTION_ONLY) + ) i_rx_channel_0 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_valid (adc_valid), + .adc_data (adc_data[11:0]), + .adc_or (1'b0), + .adc_dcfilter_data_out (adc_dcfilter_data_out_0_s), + .adc_dcfilter_data_in (adc_dcfilter_data_out_1_s), + .adc_iqcor_valid (adc_valid_i), + .adc_iqcor_data (adc_data_i), + .adc_enable (adc_enable_i), + .up_adc_pn_err (up_adc_pn_err_s[0]), + .up_adc_pn_oos (up_adc_pn_oos_s[0]), + .up_adc_or (up_adc_or_s[0]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // channel 1 (q) + + axi_ad9963_rx_channel #( + .Q_OR_I_N(1), + .CHANNEL_ID(1), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), + .DCFILTER_DISABLE (DCFILTER_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE), + .SCALECORRECTION_ONLY (SCALECORRECTION_ONLY) + ) i_rx_channel_1 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_valid (adc_valid), + .adc_data (adc_data[23:12]), + .adc_or (1'b0), + .adc_dcfilter_data_out (adc_dcfilter_data_out_1_s), + .adc_dcfilter_data_in (adc_dcfilter_data_out_0_s), + .adc_iqcor_valid (adc_valid_q), + .adc_iqcor_data (adc_data_q), + .adc_enable (adc_enable_q), + .up_adc_pn_err (up_adc_pn_err_s[1]), + .up_adc_pn_oos (up_adc_pn_oos_s[1]), + .up_adc_or (up_adc_or_s[1]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // common processor control + + up_adc_common #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .CONFIG (CONFIG), + .COMMON_ID(6'h00), + .DRP_DISABLE (1), + .USERPORTS_DISABLE (1), + .GPIO_DISABLE (1), + .START_CODE_DISABLE (1) + ) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (adc_status), + .adc_sync_status (1'd0), + .adc_status_ovf (adc_dovf), + .adc_clk_ratio (32'd1), + .adc_start_code (), + .adc_sref_sync (), + .adc_sync (), + .adc_ext_sync_arm (), + .adc_ext_sync_disarm (), + .adc_ext_sync_manual_req (), + .adc_num_lanes (), + .adc_custom_control (), + .adc_crc_enable (), + .adc_sdr_ddr_n (), + .adc_symb_op (), + .adc_symb_8_16b (), + .up_pps_rcounter(32'h0), + .up_pps_status(1'b0), + .up_pps_irq_mask(), + .up_adc_r1_mode (), + .up_status_pn_err (up_status_pn_err), + .up_status_pn_oos (up_status_pn_oos), + .up_status_or (up_status_or), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (16'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .up_usr_chanmax_out (), + .adc_config_wr (), + .adc_config_ctrl (), + .adc_config_rd ('d0), + .adc_ctrl_status ('d0), + .up_usr_chanmax_in (8'd1), + .up_adc_gpio_in (32'h0), + .up_adc_gpio_out (), + .up_adc_ce(up_adc_ce), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + // adc delay control + + generate if (IODELAY_ENABLE == 1) begin + + up_delay_cntrl #( + .DATA_WIDTH(13), + .BASE_ADDRESS(6'h02) + ) i_delay_cntrl ( + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked), + .up_dld (up_dld), + .up_dwdata (up_dwdata), + .up_drdata (up_drdata), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[3]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[3]), + .up_rack (up_rack_s[3])); + + end else begin + assign up_dld = 'h00; + assign up_dwdata = 'h00; + assign delay_rst = 1'b1; + assign up_wack_s[3] = 0; + assign up_rack_s[3] = 0; + assign up_rdata_s[3] = 'h00; + end + endgenerate + +endmodule diff --git a/adi_library/axi_ad9963/axi_ad9963_rx_channel.v b/adi_library/axi_ad9963/axi_ad9963_rx_channel.v new file mode 100644 index 00000000..571056a6 --- /dev/null +++ b/adi_library/axi_ad9963/axi_ad9963_rx_channel.v @@ -0,0 +1,223 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9963_rx_channel #( + + // parameters + + parameter Q_OR_I_N = 0, + parameter CHANNEL_ID = 0, + parameter USERPORTS_DISABLE = 0, + parameter DATAFORMAT_DISABLE = 0, + parameter DCFILTER_DISABLE = 0, + parameter IQCORRECTION_DISABLE = 0, + parameter SCALECORRECTION_ONLY = 1 +) ( + + // adc interface + + input adc_clk, + input adc_rst, + input adc_valid, + input [11:0] adc_data, + input adc_or, + + // channel interface + + output [15:0] adc_dcfilter_data_out, + input [15:0] adc_dcfilter_data_in, + output adc_iqcor_valid, + output [15:0] adc_iqcor_data, + output adc_enable, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // internal signals + + wire adc_dfmt_valid_s; + wire [15:0] adc_dfmt_data_s; + wire adc_dcfilter_valid_s; + wire [15:0] adc_dcfilter_data_s; + wire adc_iqcor_enb_s; + wire adc_dcfilt_enb_s; + wire adc_dfmt_se_s; + wire adc_dfmt_type_s; + wire adc_dfmt_enable_s; + wire [15:0] adc_dcfilt_offset_s; + wire [15:0] adc_dcfilt_coeff_s; + wire [15:0] adc_iqcor_coeff_1_s; + wire [15:0] adc_iqcor_coeff_2_s; + wire [ 3:0] adc_pnseq_sel_s; + wire [ 3:0] adc_data_sel_s; + wire adc_pn_err_s; + wire adc_pn_oos_s; + + // iq correction inputs + + assign adc_dcfilter_data_out = adc_dcfilter_data_s; + + axi_ad9963_rx_pnmon i_rx_pnmon ( + .adc_clk (adc_clk), + .adc_valid (adc_valid), + .adc_data (adc_data), + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_pn_oos (adc_pn_oos_s), + .adc_pn_err (adc_pn_err_s)); + + generate + if (DATAFORMAT_DISABLE == 1) begin + assign adc_dfmt_valid_s = adc_valid; + assign adc_dfmt_data_s = {{4{adc_data[11]}}, adc_data}; + end else begin + ad_datafmt #( + .DATA_WIDTH (12) + ) i_ad_datafmt ( + .clk (adc_clk), + .valid (adc_valid), + .data (adc_data), + .valid_out (adc_dfmt_valid_s), + .data_out (adc_dfmt_data_s), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + end + endgenerate + + generate + if (DCFILTER_DISABLE == 1) begin + assign adc_dcfilter_valid_s = adc_dfmt_valid_s; + assign adc_dcfilter_data_s = adc_dfmt_data_s; + end else begin + ad_dcfilter i_ad_dcfilter ( + .clk (adc_clk), + .valid (adc_dfmt_valid_s), + .data (adc_dfmt_data_s), + .valid_out (adc_dcfilter_valid_s), + .data_out (adc_dcfilter_data_s), + .dcfilt_enb (adc_dcfilt_enb_s), + .dcfilt_coeff (adc_dcfilt_coeff_s), + .dcfilt_offset (adc_dcfilt_offset_s)); + end + endgenerate + + ad_iqcor #( + .Q_OR_I_N (Q_OR_I_N), + .DISABLE(IQCORRECTION_DISABLE == 1), + .SCALE_ONLY(SCALECORRECTION_ONLY) + ) i_ad_iqcor ( + .clk (adc_clk), + .valid (adc_dcfilter_valid_s), + .data_in (adc_dcfilter_data_s), + .data_iq (adc_dcfilter_data_in), + .valid_out (adc_iqcor_valid), + .data_out (adc_iqcor_data), + .iqcor_enable (adc_iqcor_enb_s), + .iqcor_coeff_1 (adc_iqcor_coeff_1_s), + .iqcor_coeff_2 (adc_iqcor_coeff_2_s)); + + up_adc_channel #( + .COMMON_ID (6'h01), + .CHANNEL_ID (CHANNEL_ID), + .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), + .DCFILTER_DISABLE (DCFILTER_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE == 1), + .USERPORTS_DISABLE (USERPORTS_DISABLE) + ) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (adc_iqcor_enb_s), + .adc_dcfilt_enb (adc_dcfilt_enb_s), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_dcfilt_offset (adc_dcfilt_offset_s), + .adc_dcfilt_coeff (adc_dcfilt_coeff_s), + .adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s), + .adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s), + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_data_sel (adc_data_sel_s), + .adc_pn_err (adc_pn_err_s), + .adc_pn_oos (adc_pn_oos_s), + .adc_or (adc_or), + .adc_read_data ('d0), + .adc_status_header ('d0), + .adc_crc_err ('d0), + .up_adc_pn_err (up_adc_pn_err), + .up_adc_pn_oos (up_adc_pn_oos), + .up_adc_or (up_adc_or), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ad9963/axi_ad9963_rx_pnmon.v b/adi_library/axi_ad9963/axi_ad9963_rx_pnmon.v new file mode 100644 index 00000000..ec2f4063 --- /dev/null +++ b/adi_library/axi_ad9963/axi_ad9963_rx_pnmon.v @@ -0,0 +1,120 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// PN monitors + +`timescale 1ns/100ps + +module axi_ad9963_rx_pnmon ( + + // adc interface + + input adc_clk, + input adc_valid, + input [11:0] adc_data, + + // pn out of sync and error + + input [ 3:0] adc_pnseq_sel, + output adc_pn_oos, + output adc_pn_err +); + + // internal registers + + reg [23:0] adc_pn_data_in = 'd0; + reg [23:0] adc_pn_data_pn = 'd0; + + // internal signals + + wire [31:0] adc_pn_data_pn_s; + + // bit reversal function + + function [11:0] brfn; + input [11:0] din; + reg [11:0] dout; + begin + dout[11] = din[ 0]; + dout[10] = din[ 1]; + dout[ 9] = din[ 2]; + dout[ 8] = din[ 3]; + dout[ 7] = din[ 4]; + dout[ 6] = din[ 5]; + dout[ 5] = din[ 6]; + dout[ 4] = din[ 7]; + dout[ 3] = din[ 8]; + dout[ 2] = din[ 9]; + dout[ 1] = din[10]; + dout[ 0] = din[11]; + brfn = dout; + end + endfunction + + // standard prbs functions + + function [23:0] pn23; + input [23:0] din; + reg [23:0] dout; + begin + dout = {din[22:0], din[22] ^ din[17]}; + pn23 = dout; + end + endfunction + + // standard, runs on 24bit + + assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn; + + always @(posedge adc_clk) begin + if(adc_valid == 1'b1) begin + adc_pn_data_in <= {adc_pn_data_in[22:11], adc_data}; + adc_pn_data_pn <= pn23(adc_pn_data_pn_s); + end + end + + // pn oos & pn err + + ad_pnmon #( + .DATA_WIDTH(24) + ) i_pnmon ( + .adc_clk (adc_clk), + .adc_valid_in (adc_valid), + .adc_data_in (adc_pn_data_in), + .adc_data_pn (adc_pn_data_pn), + .adc_pattern_has_zero (1'b0), + .adc_pn_oos (adc_pn_oos), + .adc_pn_err (adc_pn_err)); + +endmodule diff --git a/adi_library/axi_ad9963/axi_ad9963_tx.v b/adi_library/axi_ad9963/axi_ad9963_tx.v new file mode 100644 index 00000000..0fe50071 --- /dev/null +++ b/adi_library/axi_ad9963/axi_ad9963_tx.v @@ -0,0 +1,254 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9963_tx #( + + // parameters + + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter DAC_DDS_TYPE = 1, + parameter DAC_DDS_CORDIC_DW = 14, + parameter DAC_DDS_CORDIC_PHASE_DW = 13, + parameter DATAPATH_DISABLE = 0 +) ( + + // dac interface + + input dac_clk, + output dac_rst, + output [23:0] dac_data, + input [23:0] adc_data, + + // master/slave + + input dac_sync_in, + output dac_sync_out, + + // dma interface + + output dac_enable_i, + output reg dac_valid_i, + input [15:0] dac_data_i, + input dma_valid_i, + output dac_enable_q, + output reg dac_valid_q, + input [15:0] dac_data_q, + input dma_valid_q, + input dac_dunf, + + output up_dac_ce, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack +); + + // internal signals + + wire dac_data_sync_s; + wire dac_dds_format_s; + wire [23:0] dac_data_int_s; + wire [31:0] up_rdata_s[0:2]; + wire up_rack_s[0:2]; + wire up_wack_s[0:2]; + + // master/slave + + assign dac_data_sync_s = (ID == 0) ? dac_sync_out : dac_sync_in; + + // dma interface + + always @(posedge dac_clk) begin + if (dac_rst == 1'b1) begin + dac_valid_i <= 1'b0; + dac_valid_q <= 1'b0; + end else begin + dac_valid_i <= 1'b1; + dac_valid_q <= 1'b1; + end + end + + // processor read interface + + always @(*) begin + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2]; + up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2]; + up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2]; + end + + // dac channel + + axi_ad9963_tx_channel #( + .CHANNEL_ID (0), + .Q_OR_I_N (0), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .DATAPATH_DISABLE (DATAPATH_DISABLE) + ) i_tx_channel_0 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_valid (dac_valid_i), + .dma_data (dac_data_i), + .adc_data (adc_data[11:0]), + .dac_data (dac_data[11:0]), + .dac_data_out (dac_data_int_s[11:0]), + .dac_data_in (dac_data_int_s[23:12]), + .dac_enable (dac_enable_i), + .dac_data_sync (dac_data_sync_s), + .dac_dds_format (dac_dds_format_s), + .dma_valid (dma_valid_i), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // dac channel + + axi_ad9963_tx_channel #( + .CHANNEL_ID (1), + .Q_OR_I_N (1), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .DATAPATH_DISABLE (DATAPATH_DISABLE) + ) i_tx_channel_1 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_valid (dac_valid_q), + .dma_data (dac_data_q), + .adc_data (adc_data[23:12]), + .dac_data (dac_data[23:12]), + .dac_data_out (dac_data_int_s[23:12]), + .dac_data_in (dac_data_int_s[11:0]), + .dac_enable (dac_enable_q), + .dac_data_sync (dac_data_sync_s), + .dac_dds_format (dac_dds_format_s), + .dma_valid (dma_valid_q), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // dac common processor interface + + up_dac_common #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .CONFIG(0), + .CLK_EDGE_SEL(0), + .COMMON_ID(6'h10), + .DRP_DISABLE (1), + .USERPORTS_DISABLE (1), + .GPIO_DISABLE(1) + ) i_up_dac_common ( + .mmcm_rst (), + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_num_lanes (), + .dac_sdr_ddr_n (), + .dac_sync (dac_sync_out), + .dac_frame (), + .dac_clksel(), + .dac_custom_wr(), + .dac_custom_rd(32'b0), + .dac_custom_control(), + .dac_status_if_busy(1'b0), + .dac_par_type (), + .dac_par_enb (), + .dac_r1_mode (), + .dac_datafmt (dac_dds_format_s), + .dac_datarate (), + .dac_status (1'b1), + .dac_sync_in_status (1'b1), + .dac_status_unf (dac_dunf), + .dac_clk_ratio (32'd1), + .up_dac_ce(up_dac_ce), + .up_pps_rcounter(32'h0), + .up_pps_status(1'b0), + .up_pps_irq_mask(), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (16'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .up_usr_chanmax (), + .dac_usr_chanmax (8'd2), + .up_dac_gpio_in (32'h0), + .up_dac_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + +endmodule diff --git a/adi_library/axi_ad9963/axi_ad9963_tx_channel.v b/adi_library/axi_ad9963/axi_ad9963_tx_channel.v new file mode 100644 index 00000000..4eb549d8 --- /dev/null +++ b/adi_library/axi_ad9963/axi_ad9963_tx_channel.v @@ -0,0 +1,272 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ad9963_tx_channel #( + + // parameters + + parameter CHANNEL_ID = 32'h0, + parameter Q_OR_I_N = 0, + parameter DAC_DDS_TYPE = 1, + parameter DAC_DDS_CORDIC_DW = 14, + parameter DAC_DDS_CORDIC_PHASE_DW = 13, + parameter DATAPATH_DISABLE = 0 +) ( + + // dac interface + + input dac_clk, + input dac_rst, + input dac_valid, + input [15:0] dma_data, + input [11:0] adc_data, + output reg [11:0] dac_data, + output reg [11:0] dac_data_out, + input [11:0] dac_data_in, + input dma_valid, + + // processor interface + + output reg dac_enable, + input dac_data_sync, + input dac_dds_format, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + localparam PRBS_SEL = CHANNEL_ID; + localparam PRBS_P09 = 0; + localparam PRBS_P11 = 1; + localparam PRBS_P15 = 2; + localparam PRBS_P20 = 3; + + // internal registers + + reg dac_valid_sel = 'd0; + reg data_source_valid = 'd0; + reg [23:0] dac_test_data = 'd0; + reg [15:0] dac_test_counter = 'd0; + reg [15:0] dac_pat_data = 'd0; + reg dma_valid_m = 1'd0; + + // internal signals + + wire dac_iqcor_valid_s; + wire [15:0] dac_iqcor_data_s; + wire [11:0] dac_dds_data_s; + wire [15:0] dac_dds_scale_1_s; + wire [15:0] dac_dds_init_1_s; + wire [15:0] dac_dds_incr_1_s; + wire [15:0] dac_dds_scale_2_s; + wire [15:0] dac_dds_init_2_s; + wire [15:0] dac_dds_incr_2_s; + wire [15:0] dac_pat_data_1_s; + wire [15:0] dac_pat_data_2_s; + wire [ 3:0] dac_data_sel_s; + wire dac_iqcor_enb_s; + wire [15:0] dac_iqcor_coeff_1_s; + wire [15:0] dac_iqcor_coeff_2_s; + + // dac iq correction + + always @(posedge dac_clk) begin + data_source_valid <= dac_data_sel_s == 4'h2 ? dma_valid_m : dac_valid; + dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; + if (dac_iqcor_valid_s == 1'b1) begin + dac_data <= dac_iqcor_data_s[15:4]; + end + end + + generate + if (DATAPATH_DISABLE == 1) begin + assign dac_iqcor_valid_s = data_source_valid; + assign dac_iqcor_data_s = {dac_data_out, 4'd0}; + end else begin + ad_iqcor #( + .Q_OR_I_N (Q_OR_I_N) + ) i_ad_iqcor ( + .clk (dac_clk), + .valid (data_source_valid), + .data_in ({dac_data_out, 4'd0}), + .data_iq ({dac_data_in, 4'd0}), + .valid_out (dac_iqcor_valid_s), + .data_out (dac_iqcor_data_s), + .iqcor_enable (dac_iqcor_enb_s), + .iqcor_coeff_1 (dac_iqcor_coeff_1_s), + .iqcor_coeff_2 (dac_iqcor_coeff_2_s)); + end + endgenerate + + // dac mux + + always @(posedge dac_clk) begin + case (dac_data_sel_s) + 4'h6: dac_data_out <= dac_test_data[11:0]; + 4'h5: dac_data_out <= dac_data_out-1; + 4'h4: dac_data_out <= dac_data_out+1; + 4'h3: dac_data_out <= 12'd0; + 4'h2: dac_data_out <= dma_data[15:4]; + 4'h1: dac_data_out <= dac_pat_data[15:4]; + default: dac_data_out <= dac_dds_data_s; + endcase + dma_valid_m <= dma_valid; + end + + function [23:0] pn23; + input [23:0] din; + reg [23:0] dout; + begin + dout = {din[22:0], din[22] ^ din[17]}; + pn23 = dout; + end + endfunction + + always @(posedge dac_clk) begin + if(dac_data_sel_s != 6) begin + dac_test_data <= 24'hffffff; + dac_test_counter <= 16'h0; + end else if (dac_test_counter == 1024) begin + dac_test_data <= 24'h0; + end else begin + dac_test_data <= pn23(dac_test_data); + dac_test_counter <= dac_test_counter + 1; + end + end + + // pattern + always @(posedge dac_clk) begin + if (dac_data_sync == 1'b1) begin + dac_valid_sel <= 1'b0; + end else if (dac_valid == 1'b1) begin + dac_valid_sel <= ~dac_valid_sel; + end + end + + always @(posedge dac_clk) begin + if (dac_valid == 1'b1) begin + if (dac_valid_sel == 1'b0) begin + dac_pat_data <= dac_pat_data_1_s; + end else begin + dac_pat_data <= dac_pat_data_2_s; + end + end + end + + // dds + + ad_dds #( + .DISABLE (DATAPATH_DISABLE), + .DDS_DW (12), + .PHASE_DW (16), + .DDS_TYPE (DAC_DDS_TYPE), + .CORDIC_DW (DAC_DDS_CORDIC_DW), + .CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .CLK_RATIO (1) + ) i_dds ( + .clk (dac_clk), + .dac_dds_format (dac_dds_format), + .dac_data_sync (dac_data_sync), + .dac_valid (dac_valid), + .tone_1_scale (dac_dds_scale_1_s), + .tone_2_scale (dac_dds_scale_2_s), + .tone_1_init_offset (dac_dds_init_1_s), + .tone_2_init_offset (dac_dds_init_2_s), + .tone_1_freq_word (dac_dds_init_2_s), + .tone_2_freq_word (dac_dds_incr_2_s), + .dac_dds_data (dac_dds_data_s)); + + // single channel processor + + up_dac_channel #( + .COMMON_ID (6'h11), + .CHANNEL_ID(CHANNEL_ID), + .DDS_DISABLE(DATAPATH_DISABLE), + .IQCORRECTION_DISABLE(DATAPATH_DISABLE), + .USERPORTS_DISABLE(1) + ) i_up_dac_channel ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_dds_scale_1 (dac_dds_scale_1_s), + .dac_dds_init_1 (dac_dds_init_1_s), + .dac_dds_incr_1 (dac_dds_incr_1_s), + .dac_dds_scale_2 (dac_dds_scale_2_s), + .dac_dds_init_2 (dac_dds_init_2_s), + .dac_dds_incr_2 (dac_dds_incr_2_s), + .dac_pat_data_1 (dac_pat_data_1_s), + .dac_pat_data_2 (dac_pat_data_2_s), + .dac_iq_mode(), + .dac_data_sel (dac_data_sel_s), + .dac_iqcor_enb (dac_iqcor_enb_s), + .dac_iqcor_coeff_1 (dac_iqcor_coeff_1_s), + .dac_iqcor_coeff_2 (dac_iqcor_coeff_2_s), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_interpolation_m (), + .up_usr_interpolation_n (), + .dac_usr_datatype_be (1'b0), + .dac_usr_datatype_signed (1'b1), + .dac_usr_datatype_shift (8'd0), + .dac_usr_datatype_total_bits (8'd16), + .dac_usr_datatype_bits (8'd16), + .dac_usr_interpolation_m (16'd1), + .dac_usr_interpolation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ad9963/bd/bd.tcl b/adi_library/axi_ad9963/bd/bd.tcl new file mode 100644 index 00000000..dceb9498 --- /dev/null +++ b/adi_library/axi_ad9963/bd/bd.tcl @@ -0,0 +1,47 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + DEV_PACKAGE \ + SPEED_GRADE \ + FPGA_FAMILY \ + FPGA_TECHNOLOGY" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/axi_ad9963/component.xml b/adi_library/axi_ad9963/component.xml new file mode 100644 index 00000000..e8102160 --- /dev/null +++ b/adi_library/axi_ad9963/component.xml @@ -0,0 +1,1764 @@ + + + analog.com + user + axi_ad9963 + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + trx_clk + + + + + + + CLK + + + trx_clk + + + + + + tx_clk + + + + + + + CLK + + + tx_clk + + + + + + delay_clk + + + + + + + CLK + + + delay_clk + + + + + + adc_clk + + + + + + + CLK + + + adc_clk + + + + + + ASSOCIATED_RESET + adc_rst + + + + + adc_rst + + + + + + + RST + + + adc_rst + + + + + + dac_clk + + + + + + + CLK + + + dac_clk + + + + + + ASSOCIATED_RESET + dac_rst + + + + + dac_rst + + + + + + + RST + + + dac_rst + + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_ad9963 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 706a8f32 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_ad9963 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + a287393e + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + cdeb984c + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + + + trx_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + trx_iq + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + trx_data + + in + + 11 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + tx_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + tx_iq + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + tx_data + + out + + 11 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_sync_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + dac_sync_out + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + delay_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + adc_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_rst + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_rst + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_i + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid_i + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_i + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable_q + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid_q + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_q + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_dovf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + dac_enable_i + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_valid_i + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_data_i + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + dma_valid_i + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_enable_q + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_valid_q + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_data_q + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + dma_valid_q + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_dunf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + ADC_IODELAY_ENABLE + Adc Iodelay Enable + 0 + + + IO_DELAY_GROUP + Io Delay Group + dev_if_delay_group + + + IODELAY_ENABLE + Iodelay Enable + 0 + + + DAC_DDS_TYPE + Dac Dds Type + 1 + + + DAC_DDS_CORDIC_DW + Dac Dds Cordic Dw + 14 + + + DAC_DDS_CORDIC_PHASE_DW + Dac Dds Cordic Phase Dw + 13 + + + DAC_DATAPATH_DISABLE + Dac Datapath Disable + 0 + + + ADC_USERPORTS_DISABLE + Adc Userports Disable + 0 + + + ADC_DATAFORMAT_DISABLE + Adc Dataformat Disable + 0 + + + ADC_DCFILTER_DISABLE + Adc Dcfilter Disable + 0 + + + ADC_IQCORRECTION_DISABLE + Adc Iqcorrection Disable + 0 + + + ADC_SCALECORRECTION_ONLY + Adc Scalecorrection Only + 1 + + + DELAY_REFCLK_FREQUENCY + Delay Refclk Frequency + 200 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_00ecfe9a + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + + + choice_pairs_19f99f31 + 0 + 10 + 11 + 12 + 13 + 14 + 20 + 21 + 22 + 23 + 24 + 25 + 30 + + + choice_pairs_28f798a2 + 0 + 1 + 2 + 3 + 4 + + + choice_pairs_fc01a186 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../xilinx/common/up_clock_mon_constr.xdc + xdc + + + axi_ad9963_constr.xdc + xdc + + + ../xilinx/common/ad_data_in.v + verilogSource + + + ../common/ad_datafmt.v + verilogSource + + + ../xilinx/common/ad_dcfilter.v + verilogSource + + + ../common/ad_dds.v + verilogSource + + + ../common/ad_dds_1.v + verilogSource + + + ../common/ad_dds_2.v + verilogSource + + + ../common/ad_dds_cordic_pipe.v + verilogSource + + + ../common/ad_dds_sine.v + verilogSource + + + ../common/ad_dds_sine_cordic.v + verilogSource + + + ../common/ad_iqcor.v + verilogSource + + + ../xilinx/common/ad_mul.v + verilogSource + + + ../common/ad_pnmon.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + axi_ad9963_if.v + verilogSource + + + axi_ad9963_rx.v + verilogSource + + + axi_ad9963_rx_channel.v + verilogSource + + + axi_ad9963_rx_pnmon.v + verilogSource + + + axi_ad9963_tx.v + verilogSource + + + axi_ad9963_tx_channel.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_dac_channel.v + verilogSource + + + ../common/up_dac_common.v + verilogSource + + + ../common/up_delay_cntrl.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad9963.v + verilogSource + CHECKSUM_a1f81693 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../xilinx/common/ad_data_in.v + verilogSource + + + ../common/ad_datafmt.v + verilogSource + + + ../xilinx/common/ad_dcfilter.v + verilogSource + + + ../common/ad_dds.v + verilogSource + + + ../common/ad_dds_1.v + verilogSource + + + ../common/ad_dds_2.v + verilogSource + + + ../common/ad_dds_cordic_pipe.v + verilogSource + + + ../common/ad_dds_sine.v + verilogSource + + + ../common/ad_dds_sine_cordic.v + verilogSource + + + ../common/ad_iqcor.v + verilogSource + + + ../xilinx/common/ad_mul.v + verilogSource + + + ../common/ad_pnmon.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + axi_ad9963_if.v + verilogSource + + + axi_ad9963_rx.v + verilogSource + + + axi_ad9963_rx_channel.v + verilogSource + + + axi_ad9963_rx_pnmon.v + verilogSource + + + axi_ad9963_tx.v + verilogSource + + + axi_ad9963_tx_channel.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_dac_channel.v + verilogSource + + + ../common/up_dac_common.v + verilogSource + + + ../common/up_delay_cntrl.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ad9963.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_ad9963_v1_0.tcl + tclSource + CHECKSUM_dc697a44 + XGUI_VERSION_2 + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + axi_ad9963_v1_0 + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + ADC_IODELAY_ENABLE + Adc Iodelay Enable + 0 + + + IO_DELAY_GROUP + Io Delay Group + dev_if_delay_group + + + IODELAY_ENABLE + Iodelay Enable + 0 + + + DAC_DDS_TYPE + Dac Dds Type + 1 + + + DAC_DDS_CORDIC_DW + Dac Dds Cordic Dw + 14 + + + DAC_DDS_CORDIC_PHASE_DW + Dac Dds Cordic Phase Dw + 13 + + + DAC_DATAPATH_DISABLE + Dac Datapath Disable + 0 + + + ADC_USERPORTS_DISABLE + Adc Userports Disable + 0 + + + ADC_DATAFORMAT_DISABLE + Adc Dataformat Disable + 0 + + + ADC_DCFILTER_DISABLE + Adc Dcfilter Disable + 0 + + + ADC_IQCORRECTION_DISABLE + Adc Iqcorrection Disable + 0 + + + ADC_SCALECORRECTION_ONLY + Adc Scalecorrection Only + 1 + + + DELAY_REFCLK_FREQUENCY + Delay Refclk Frequency + 200 + + + Component_Name + axi_ad9963_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_ad9963_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_ad9963 + 1 + 2024-01-14T03:43:40Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_ad9963/temporary_case_dependencies.mk b/adi_library/axi_ad9963/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/axi_ad9963/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/axi_ad9963/xgui/axi_ad9963_v1_0.tcl b/adi_library/axi_ad9963/xgui/axi_ad9963_v1_0.tcl new file mode 100644 index 00000000..3cd03904 --- /dev/null +++ b/adi_library/axi_ad9963/xgui/axi_ad9963_v1_0.tcl @@ -0,0 +1,283 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ADC_DATAFORMAT_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "ADC_DCFILTER_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "ADC_IODELAY_ENABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "ADC_IQCORRECTION_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "ADC_SCALECORRECTION_ONLY" -parent ${Page_0} + ipgui::add_param $IPINST -name "ADC_USERPORTS_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_DATAPATH_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_DW" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_DDS_CORDIC_PHASE_DW" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_DDS_TYPE" -parent ${Page_0} + ipgui::add_param $IPINST -name "DELAY_REFCLK_FREQUENCY" -parent ${Page_0} + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "IODELAY_ENABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "IO_DELAY_GROUP" -parent ${Page_0} + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.ADC_DATAFORMAT_DISABLE { PARAM_VALUE.ADC_DATAFORMAT_DISABLE } { + # Procedure called to update ADC_DATAFORMAT_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADC_DATAFORMAT_DISABLE { PARAM_VALUE.ADC_DATAFORMAT_DISABLE } { + # Procedure called to validate ADC_DATAFORMAT_DISABLE + return true +} + +proc update_PARAM_VALUE.ADC_DCFILTER_DISABLE { PARAM_VALUE.ADC_DCFILTER_DISABLE } { + # Procedure called to update ADC_DCFILTER_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADC_DCFILTER_DISABLE { PARAM_VALUE.ADC_DCFILTER_DISABLE } { + # Procedure called to validate ADC_DCFILTER_DISABLE + return true +} + +proc update_PARAM_VALUE.ADC_IODELAY_ENABLE { PARAM_VALUE.ADC_IODELAY_ENABLE } { + # Procedure called to update ADC_IODELAY_ENABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADC_IODELAY_ENABLE { PARAM_VALUE.ADC_IODELAY_ENABLE } { + # Procedure called to validate ADC_IODELAY_ENABLE + return true +} + +proc update_PARAM_VALUE.ADC_IQCORRECTION_DISABLE { PARAM_VALUE.ADC_IQCORRECTION_DISABLE } { + # Procedure called to update ADC_IQCORRECTION_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADC_IQCORRECTION_DISABLE { PARAM_VALUE.ADC_IQCORRECTION_DISABLE } { + # Procedure called to validate ADC_IQCORRECTION_DISABLE + return true +} + +proc update_PARAM_VALUE.ADC_SCALECORRECTION_ONLY { PARAM_VALUE.ADC_SCALECORRECTION_ONLY } { + # Procedure called to update ADC_SCALECORRECTION_ONLY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADC_SCALECORRECTION_ONLY { PARAM_VALUE.ADC_SCALECORRECTION_ONLY } { + # Procedure called to validate ADC_SCALECORRECTION_ONLY + return true +} + +proc update_PARAM_VALUE.ADC_USERPORTS_DISABLE { PARAM_VALUE.ADC_USERPORTS_DISABLE } { + # Procedure called to update ADC_USERPORTS_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADC_USERPORTS_DISABLE { PARAM_VALUE.ADC_USERPORTS_DISABLE } { + # Procedure called to validate ADC_USERPORTS_DISABLE + return true +} + +proc update_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } { + # Procedure called to update DAC_DATAPATH_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_DATAPATH_DISABLE { PARAM_VALUE.DAC_DATAPATH_DISABLE } { + # Procedure called to validate DAC_DATAPATH_DISABLE + return true +} + +proc update_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } { + # Procedure called to update DAC_DDS_CORDIC_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_DDS_CORDIC_DW { PARAM_VALUE.DAC_DDS_CORDIC_DW } { + # Procedure called to validate DAC_DDS_CORDIC_DW + return true +} + +proc update_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } { + # Procedure called to update DAC_DDS_CORDIC_PHASE_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } { + # Procedure called to validate DAC_DDS_CORDIC_PHASE_DW + return true +} + +proc update_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } { + # Procedure called to update DAC_DDS_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_DDS_TYPE { PARAM_VALUE.DAC_DDS_TYPE } { + # Procedure called to validate DAC_DDS_TYPE + return true +} + +proc update_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } { + # Procedure called to update DELAY_REFCLK_FREQUENCY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } { + # Procedure called to validate DELAY_REFCLK_FREQUENCY + return true +} + +proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to validate DEV_PACKAGE + return true +} + +proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to validate FPGA_FAMILY + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.IODELAY_ENABLE { PARAM_VALUE.IODELAY_ENABLE } { + # Procedure called to update IODELAY_ENABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IODELAY_ENABLE { PARAM_VALUE.IODELAY_ENABLE } { + # Procedure called to validate IODELAY_ENABLE + return true +} + +proc update_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to update IO_DELAY_GROUP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to validate IO_DELAY_GROUP + return true +} + +proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to validate SPEED_GRADE + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY} +} + +proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE} +} + +proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE} +} + +proc update_MODELPARAM_VALUE.ADC_IODELAY_ENABLE { MODELPARAM_VALUE.ADC_IODELAY_ENABLE PARAM_VALUE.ADC_IODELAY_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADC_IODELAY_ENABLE}] ${MODELPARAM_VALUE.ADC_IODELAY_ENABLE} +} + +proc update_MODELPARAM_VALUE.IO_DELAY_GROUP { MODELPARAM_VALUE.IO_DELAY_GROUP PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IO_DELAY_GROUP}] ${MODELPARAM_VALUE.IO_DELAY_GROUP} +} + +proc update_MODELPARAM_VALUE.IODELAY_ENABLE { MODELPARAM_VALUE.IODELAY_ENABLE PARAM_VALUE.IODELAY_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IODELAY_ENABLE}] ${MODELPARAM_VALUE.IODELAY_ENABLE} +} + +proc update_MODELPARAM_VALUE.DAC_DDS_TYPE { MODELPARAM_VALUE.DAC_DDS_TYPE PARAM_VALUE.DAC_DDS_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_DDS_TYPE}] ${MODELPARAM_VALUE.DAC_DDS_TYPE} +} + +proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_DW PARAM_VALUE.DAC_DDS_CORDIC_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_DW} +} + +proc update_MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW { MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW}] ${MODELPARAM_VALUE.DAC_DDS_CORDIC_PHASE_DW} +} + +proc update_MODELPARAM_VALUE.DAC_DATAPATH_DISABLE { MODELPARAM_VALUE.DAC_DATAPATH_DISABLE PARAM_VALUE.DAC_DATAPATH_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_DATAPATH_DISABLE}] ${MODELPARAM_VALUE.DAC_DATAPATH_DISABLE} +} + +proc update_MODELPARAM_VALUE.ADC_USERPORTS_DISABLE { MODELPARAM_VALUE.ADC_USERPORTS_DISABLE PARAM_VALUE.ADC_USERPORTS_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADC_USERPORTS_DISABLE}] ${MODELPARAM_VALUE.ADC_USERPORTS_DISABLE} +} + +proc update_MODELPARAM_VALUE.ADC_DATAFORMAT_DISABLE { MODELPARAM_VALUE.ADC_DATAFORMAT_DISABLE PARAM_VALUE.ADC_DATAFORMAT_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADC_DATAFORMAT_DISABLE}] ${MODELPARAM_VALUE.ADC_DATAFORMAT_DISABLE} +} + +proc update_MODELPARAM_VALUE.ADC_DCFILTER_DISABLE { MODELPARAM_VALUE.ADC_DCFILTER_DISABLE PARAM_VALUE.ADC_DCFILTER_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADC_DCFILTER_DISABLE}] ${MODELPARAM_VALUE.ADC_DCFILTER_DISABLE} +} + +proc update_MODELPARAM_VALUE.ADC_IQCORRECTION_DISABLE { MODELPARAM_VALUE.ADC_IQCORRECTION_DISABLE PARAM_VALUE.ADC_IQCORRECTION_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADC_IQCORRECTION_DISABLE}] ${MODELPARAM_VALUE.ADC_IQCORRECTION_DISABLE} +} + +proc update_MODELPARAM_VALUE.ADC_SCALECORRECTION_ONLY { MODELPARAM_VALUE.ADC_SCALECORRECTION_ONLY PARAM_VALUE.ADC_SCALECORRECTION_ONLY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADC_SCALECORRECTION_ONLY}] ${MODELPARAM_VALUE.ADC_SCALECORRECTION_ONLY} +} + +proc update_MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY { MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY PARAM_VALUE.DELAY_REFCLK_FREQUENCY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DELAY_REFCLK_FREQUENCY}] ${MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY} +} + diff --git a/adi_library/axi_adaq8092/Makefile b/adi_library/axi_adaq8092/Makefile new file mode 100644 index 00000000..ad8b8de9 --- /dev/null +++ b/adi_library/axi_adaq8092/Makefile @@ -0,0 +1,33 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_adaq8092 + +GENERIC_DEPS += ../common/ad_datafmt.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_adc_channel.v +GENERIC_DEPS += ../common/up_adc_common.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_delay_cntrl.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_adaq8092.v +GENERIC_DEPS += axi_adaq8092_apb_decode.v +GENERIC_DEPS += axi_adaq8092_channel.v +GENERIC_DEPS += axi_adaq8092_if.v +GENERIC_DEPS += axi_adaq8092_rand_decode.v + +XILINX_DEPS += ../xilinx/common/ad_data_clk.v +XILINX_DEPS += ../xilinx/common/ad_data_in.v +XILINX_DEPS += ../xilinx/common/ad_dcfilter.v +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_adaq8092_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_adaq8092/axi_adaq8092.v b/adi_library/axi_adaq8092/axi_adaq8092.v new file mode 100644 index 00000000..0ee7188f --- /dev/null +++ b/adi_library/axi_adaq8092/axi_adaq8092.v @@ -0,0 +1,387 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adaq8092 #( + + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter ADC_DATAPATH_DISABLE = 0, + parameter IO_DELAY_GROUP = "adc_if_delay_group", + parameter OUTPUT_MODE = 0, + parameter [27:0] POLARITY_MASK ='hfffffff +) ( + + // adc interface (clk, data, over-range) + + input adc_clk_in_p, + input adc_clk_in_n, + input [ 6:0] lvds_adc_data_in1_p, + input [ 6:0] lvds_adc_data_in1_n, + input [ 6:0] lvds_adc_data_in2_p, + input [ 6:0] lvds_adc_data_in2_n, + input lvds_adc_or_in_p, + input lvds_adc_or_in_n, + input [13:0] cmos_adc_data_in1, + input [13:0] cmos_adc_data_in2, + input cmos_adc_or_in_1, + input cmos_adc_or_in_2, + + // delay interface + + input delay_clk, + + // dma interface + + output adc_clk, + output adc_rst, + output adc_valid, + output adc_enable_1, + output adc_enable_2, + output [15:0] adc_data_channel1, + output [15:0] adc_data_channel2, + input adc_dovf, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot +); + + // configuration settings + + localparam CONFIG = (OUTPUT_MODE * 128); + + // internal registers + + reg up_status_or = 'd0; + reg [31:0] up_rdata = 'd0; + reg up_wack = 'd0; + reg up_rack = 'd0; + + // internal clocks & resets + + wire up_rstn; + wire up_clk; + wire delay_rst; + + // internal signals + + wire adc_or_s; + wire [27:0] adc_data_s; + wire [1:0] up_status_or_s; + wire adc_status_s; + wire [29:0] up_dld_s; + wire [149:0] up_dwdata_s; + wire [149:0] up_drdata_s; + wire delay_locked_s; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_s[0:3]; + wire [3:0] up_rack_s; + wire [3:0] up_wack_s; + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire up_rreq_s; + wire [13:0] adc_decoded_data_s_1; + wire [13:0] adc_decoded_data_s_2; + wire [27:0] adc_part_decoded_data_s; + wire [7:0] adc_custom_control_s; + wire sdr_or_ddr_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + assign adc_valid = 1'b1; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_status_or <= 'd0; + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_status_or <= up_status_or_s[0] | up_status_or_s[1]; + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3]; + up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3]; + up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3]; + end + end + + // ADC channel 1 + + axi_adaq8092_channel #( + .CHANNEL_ID(0), + .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE) + ) i_channel_1 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_decoded_data_s_1), + .adc_or (adc_or_s), + .adc_dcfilter_data_out (adc_data_channel1), + .adc_enable (adc_enable_1), + .adc_valid (), + .up_adc_or (up_status_or_s[0]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // ADC channel 2 + + axi_adaq8092_channel #( + .CHANNEL_ID(1), + .DATAPATH_DISABLE (ADC_DATAPATH_DISABLE) + ) i_channel_2 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data (adc_decoded_data_s_2), + .adc_or (adc_or_s), + .adc_dcfilter_data_out (adc_data_channel2), + .adc_enable (adc_enable_2), + .adc_valid (), + .up_adc_or (up_status_or_s[1]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // ADC interface + + axi_adaq8092_rand_decode i_rand ( + .adc_data(adc_data_s), + .adc_clk(adc_clk), + .adc_rand_enb(adc_custom_control_s[0]), + .adc_data_decoded(adc_part_decoded_data_s)); + + axi_adaq8092_apb_decode i_apb ( + .adc_data(adc_part_decoded_data_s), + .adc_clk(adc_clk), + .adc_abp_enb(adc_custom_control_s[1]), + .adc_data_decoded({adc_decoded_data_s_2,adc_decoded_data_s_1})); + + axi_adaq8092_if #( + .OUTPUT_MODE(OUTPUT_MODE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IO_DELAY_GROUP (IO_DELAY_GROUP), + .POLARITY_MASK(POLARITY_MASK) + ) i_if ( + .adc_clk_in_p (adc_clk_in_p), + .adc_clk_in_n (adc_clk_in_n), + .lvds_adc_data_p({lvds_adc_data_in2_p,lvds_adc_data_in1_p}), + .lvds_adc_data_n({lvds_adc_data_in2_n,lvds_adc_data_in1_n}), + .lvds_adc_or_p(lvds_adc_or_in_p), + .lvds_adc_or_n(lvds_adc_or_in_n), + .cmos_adc_data({cmos_adc_data_in2,cmos_adc_data_in1}), + .cmos_adc_data_or_1(cmos_adc_or_in_1), + .cmos_adc_data_or_2(cmos_adc_or_in_2), + .sdr_or_ddr(sdr_or_ddr_s), + .adc_clk (adc_clk), + .adc_data(adc_data_s), + .adc_or(adc_or_s), + .adc_status (adc_status_s), + .up_clk (up_clk), + .up_dld (up_dld_s), + .up_dwdata (up_dwdata_s), + .up_drdata (up_drdata_s), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s)); + + // adc delay control + + up_delay_cntrl #( + .DATA_WIDTH(30), + .BASE_ADDRESS(6'h02) + ) i_delay_cntrl ( + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s), + .up_dld (up_dld_s), + .up_dwdata (up_dwdata_s), + .up_drdata (up_drdata_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + // common processor control + + up_adc_common #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .CONFIG (CONFIG), + .COMMON_ID (6'h00), + .DRP_DISABLE (6'h00), + .USERPORTS_DISABLE (0), + .GPIO_DISABLE (0), + .START_CODE_DISABLE(0) + ) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_custom_control(adc_custom_control_s), + .adc_sdr_ddr_n(sdr_or_ddr_s), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (adc_status_s), + .adc_sync_status (1'd0), + .adc_status_ovf (adc_dovf), + .adc_clk_ratio (32'd1), + .adc_start_code (), + .adc_sref_sync (), + .adc_sync (), + .adc_ext_sync_arm(), + .adc_ext_sync_disarm(), + .adc_ext_sync_manual_req(), + .adc_crc_enable (), + .adc_num_lanes(), + .adc_symb_op(), + .adc_symb_8_16b(), + + .up_pps_rcounter(32'd0), + .up_pps_status(1'd0), + .up_pps_irq_mask(), + .up_adc_ce (), + .up_status_pn_err (), + .up_status_pn_oos (), + .up_status_or (), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .adc_config_wr (), + .adc_config_ctrl (), + .adc_config_rd ('d0), + .adc_ctrl_status ('d0), + .up_usr_chanmax_out (), + .up_usr_chanmax_in (8'd0), + .up_adc_gpio_in (32'd0), + .up_adc_gpio_out (), + .up_adc_r1_mode(), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[3]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[3]), + .up_rack (up_rack_s[3])); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_adaq8092/axi_adaq8092.xpr b/adi_library/axi_adaq8092/axi_adaq8092.xpr new file mode 100644 index 00000000..1a54758d --- /dev/null +++ b/adi_library/axi_adaq8092/axi_adaq8092.xpr @@ -0,0 +1,542 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_adaq8092/axi_adaq8092_apb_decode.v b/adi_library/axi_adaq8092/axi_adaq8092_apb_decode.v new file mode 100644 index 00000000..cc763c0d --- /dev/null +++ b/adi_library/axi_adaq8092/axi_adaq8092_apb_decode.v @@ -0,0 +1,64 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// ADC ALTERNATE BIT POLARITY DECODE + +`timescale 1ns/100ps + +module axi_adaq8092_apb_decode ( + + input [27:0] adc_data, + input adc_clk, + input adc_abp_enb, + output [27:0] adc_data_decoded +); + + // internal registers + + reg [27:0] adc_data_decoded_s; + + // internal variable + + integer i; + + assign adc_data_decoded = adc_abp_enb ? adc_data_decoded_s : adc_data ; + + always @(posedge adc_clk) begin + for (i = 0; i <= 13; i = i + 1) begin + adc_data_decoded_s[2*i+1] = ~adc_data[2*i+1]; + adc_data_decoded_s[2*i] = adc_data[2*i]; + end + end + +endmodule diff --git a/adi_library/axi_adaq8092/axi_adaq8092_channel.v b/adi_library/axi_adaq8092/axi_adaq8092_channel.v new file mode 100644 index 00000000..ff3d4940 --- /dev/null +++ b/adi_library/axi_adaq8092/axi_adaq8092_channel.v @@ -0,0 +1,173 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// ADC channel- + +`timescale 1ns/100ps + +module axi_adaq8092_channel #( + + parameter CHANNEL_ID = 0, + parameter DATAPATH_DISABLE = 0 +) ( + + // adc interface + + input adc_clk, + input adc_rst, + input [13:0] adc_data, + input adc_or, + + // channel interface + + output [15:0] adc_dcfilter_data_out, + output adc_valid, + output adc_enable, + output up_adc_or, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // internal signals + + wire [15:0] adc_dfmt_data_s; + wire adc_dcfilt_enb_s; + wire adc_dfmt_se_s; + wire adc_dfmt_type_s; + wire adc_dfmt_enable_s; + wire [15:0] adc_dcfilt_offset_s; + wire [15:0] adc_dcfilt_coeff_s; + + generate + if (DATAPATH_DISABLE == 1) begin + assign adc_dfmt_data_s = {2'b0 , adc_data}; + end else begin + ad_datafmt #( + .DATA_WIDTH(14) + ) i_ad_datafmt ( + .clk (adc_clk), + .valid (1'b1), + .data (adc_data), + .valid_out (), + .data_out (adc_dfmt_data_s), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + end + endgenerate + + generate + if (DATAPATH_DISABLE == 1) begin + assign adc_dcfilter_data_out = adc_dfmt_data_s; + end else begin + ad_dcfilter i_ad_dcfilter ( + .clk (adc_clk), + .valid (1'b1), + .data (adc_dfmt_data_s), + .valid_out (adc_valid), + .data_out (adc_dcfilter_data_out), + .dcfilt_enb (adc_dcfilt_enb_s), + .dcfilt_coeff (adc_dcfilt_coeff_s), + .dcfilt_offset (adc_dcfilt_offset_s)); + end + endgenerate + + up_adc_channel #( + .COMMON_ID (6'h01), + .CHANNEL_ID(CHANNEL_ID), + .USERPORTS_DISABLE (0), + .DATAFORMAT_DISABLE (0), + .DCFILTER_DISABLE (0), + .IQCORRECTION_DISABLE (0) + ) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (), + .adc_dcfilt_enb (adc_dcfilt_enb_s), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_dcfilt_offset (adc_dcfilt_offset_s), + .adc_dcfilt_coeff (adc_dcfilt_coeff_s), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pnseq_sel (), + .adc_data_sel (), + .adc_pn_err (), + .adc_pn_oos (), + .adc_or (adc_or), + .adc_read_data ('d0), + .adc_status_header ('d0), + .adc_crc_err ('d0), + .up_adc_pn_err (), + .up_adc_pn_oos (), + .up_adc_or (up_adc_or), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd14), + .adc_usr_datatype_bits (8'd14), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_adaq8092/axi_adaq8092_if.v b/adi_library/axi_adaq8092/axi_adaq8092_if.v new file mode 100644 index 00000000..17433b50 --- /dev/null +++ b/adi_library/axi_adaq8092/axi_adaq8092_if.v @@ -0,0 +1,299 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// This is the LVDS/DDR interface, note that overrange is independent of data path, +// software will not be able to relate overrange to a specific sample! + +`timescale 1ns/100ps + +module axi_adaq8092_if #( + + parameter FPGA_TECHNOLOGY = 0, + parameter IO_DELAY_GROUP = "adc_if_delay_group", + parameter DELAY_REFCLK_FREQUENCY = 200, + parameter [27:0] POLARITY_MASK ='hfffffff, + parameter OUTPUT_MODE = 0 +) ( + + // adc interface (clk, data, over-range) + // nominal clock 80 MHz, up to 105 MHz + + input adc_clk_in_p, + input adc_clk_in_n, + + input [13:0] lvds_adc_data_p, + input [13:0] lvds_adc_data_n, + input lvds_adc_or_p, + input lvds_adc_or_n, + + input [27:0] cmos_adc_data, + input cmos_adc_data_or_1, + input cmos_adc_data_or_2, + + // up control SDR or DDR + + input sdr_or_ddr, + + // interface outputs + + output adc_clk, + output reg [27:0] adc_data, + output reg adc_or, + output reg adc_status, + + // delay control signals + + input up_clk, + input [29:0] up_dld, + input [149:0] up_dwdata, + output [149:0] up_drdata, + input delay_clk, + input delay_rst, + output delay_locked +); + + // internal registers + + reg [27:0] adc_data_s='b0; + + // internal signals + + wire [13:0] lvds_adc_data_p_s; + wire [13:0] lvds_adc_data_n_s; + wire [27:0] cmos_adc_data_p_s; + wire [27:0] cmos_adc_data_n_s; + wire adc_or_s_1; + wire adc_or_s_2; + wire adc_or_s_1_p; + wire adc_or_s_1_n; + wire adc_or_s_2_p; + wire adc_or_s_2_n; + wire [27:0] adc_data_if_out; + + genvar l_inst; + + // LOCAL parameters + + localparam LVDS = 0; + localparam CMOS = 1; + + always @(posedge adc_clk) begin + + adc_status <= 1'b1; + + if (OUTPUT_MODE == LVDS) begin + + adc_or <= adc_or_s_1 | adc_or_s_2; + adc_data <= POLARITY_MASK ^ adc_data_s; + adc_data_s <= { lvds_adc_data_n_s[13], lvds_adc_data_p_s[13], + lvds_adc_data_n_s[12], lvds_adc_data_p_s[12], + lvds_adc_data_n_s[11], lvds_adc_data_p_s[11], + lvds_adc_data_n_s[10], lvds_adc_data_p_s[10], + lvds_adc_data_n_s[9], lvds_adc_data_p_s[9], + lvds_adc_data_n_s[8], lvds_adc_data_p_s[8], + lvds_adc_data_n_s[7], lvds_adc_data_p_s[7], + lvds_adc_data_n_s[6], lvds_adc_data_p_s[6], + lvds_adc_data_n_s[5], lvds_adc_data_p_s[5], + lvds_adc_data_n_s[4], lvds_adc_data_p_s[4], + lvds_adc_data_n_s[3], lvds_adc_data_p_s[3], + lvds_adc_data_n_s[2], lvds_adc_data_p_s[2], + lvds_adc_data_n_s[1], lvds_adc_data_p_s[1], + lvds_adc_data_n_s[0], lvds_adc_data_p_s[0]}; + + end else if (OUTPUT_MODE == CMOS) begin + adc_data <= adc_data_s; + if (sdr_or_ddr == 0) begin //DDR_CMOS + adc_or <= adc_or_s_1_p | adc_or_s_1_n; + adc_data_s <= { cmos_adc_data_n_s[27], cmos_adc_data_p_s[27], + cmos_adc_data_n_s[25], cmos_adc_data_p_s[25], + cmos_adc_data_n_s[23], cmos_adc_data_p_s[23], + cmos_adc_data_n_s[21], cmos_adc_data_p_s[21], + cmos_adc_data_n_s[19], cmos_adc_data_p_s[19], + cmos_adc_data_n_s[17], cmos_adc_data_p_s[17], + cmos_adc_data_n_s[15], cmos_adc_data_p_s[15], + cmos_adc_data_n_s[13], cmos_adc_data_p_s[13], + cmos_adc_data_n_s[11], cmos_adc_data_p_s[11], + cmos_adc_data_n_s[9], cmos_adc_data_p_s[9], + cmos_adc_data_n_s[7], cmos_adc_data_p_s[7], + cmos_adc_data_n_s[5], cmos_adc_data_p_s[5], + cmos_adc_data_n_s[3], cmos_adc_data_p_s[3], + cmos_adc_data_n_s[1], cmos_adc_data_p_s[1]}; + end else if (sdr_or_ddr == 1) begin //SDR_CMOS + adc_or <= adc_or_s_1_p | adc_or_s_2_p; + adc_data_s <= { cmos_adc_data_p_s[27], cmos_adc_data_p_s[26], + cmos_adc_data_p_s[25], cmos_adc_data_p_s[24], + cmos_adc_data_p_s[23], cmos_adc_data_p_s[22], + cmos_adc_data_p_s[21], cmos_adc_data_p_s[20], + cmos_adc_data_p_s[19], cmos_adc_data_p_s[18], + cmos_adc_data_p_s[17], cmos_adc_data_p_s[16], + cmos_adc_data_p_s[15], cmos_adc_data_p_s[14], + cmos_adc_data_p_s[13], cmos_adc_data_p_s[12], + cmos_adc_data_p_s[11], cmos_adc_data_p_s[10], + cmos_adc_data_p_s[9], cmos_adc_data_p_s[8], + cmos_adc_data_p_s[7], cmos_adc_data_p_s[6], + cmos_adc_data_p_s[5], cmos_adc_data_p_s[4], + cmos_adc_data_p_s[3], cmos_adc_data_p_s[2], + cmos_adc_data_p_s[1], cmos_adc_data_p_s[0]}; + end + end + end + + // data interface + + generate + if (OUTPUT_MODE == LVDS) begin + for (l_inst = 0; l_inst <= 13; l_inst = l_inst + 1) begin : lvds_adc_if // DDR LVDS INTERFACE + ad_data_in #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY), + .IDDR_CLK_EDGE("OPPOSITE_EDGE") + ) i_adc_data ( + .rx_clk (adc_clk), + .rx_data_in_p (lvds_adc_data_p[l_inst]), + .rx_data_in_n (lvds_adc_data_n[l_inst]), + .rx_data_p (lvds_adc_data_p_s[l_inst]), + .rx_data_n (lvds_adc_data_n_s[l_inst]), + .up_clk (up_clk), + .up_dld (up_dld[l_inst]), + .up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]), + .up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + end else if (OUTPUT_MODE == CMOS) begin + + for (l_inst = 0; l_inst <= 27; l_inst = l_inst + 1) begin : cmos_adc_if // CMOS INTERFACE + ad_data_in #( + .SINGLE_ENDED(1), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY), + .IDDR_CLK_EDGE("OPPOSITE_EDGE") + ) i_adc_data ( + .rx_clk (adc_clk), + .rx_data_in_p (cmos_adc_data[l_inst]), + .rx_data_in_n (), + .rx_data_p (cmos_adc_data_p_s[l_inst]), + .rx_data_n (cmos_adc_data_n_s[l_inst]), + .up_clk (up_clk), + .up_dld (up_dld[l_inst]), + .up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]), + .up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + end + endgenerate + + // over-range interface + + if (OUTPUT_MODE == LVDS) begin + ad_data_in #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_CTRL (1), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY), + .IDDR_CLK_EDGE("OPPOSITE_EDGE") + ) i_adc_or_lvds ( + .rx_clk (adc_clk), + .rx_data_in_p (lvds_adc_or_p), + .rx_data_in_n (lvds_adc_or_n), + .rx_data_p (adc_or_s_1), + .rx_data_n (adc_or_s_2), + .up_clk (up_clk), + .up_dld (up_dld[14]), + .up_dwdata (up_dwdata[74:70]), + .up_drdata (up_drdata[74:70]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked)); + end else if (OUTPUT_MODE == CMOS) begin + ad_data_in #( + .SINGLE_ENDED(1), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_CTRL (1), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY), + .IDDR_CLK_EDGE("OPPOSITE_EDGE") + ) i_adc_or_cmos_1 ( + .rx_clk (adc_clk), + .rx_data_in_p (cmos_adc_data_or_1), + .rx_data_in_n (), + .rx_data_p (adc_or_s_1_p), + .rx_data_n (adc_or_s_1_n), + .up_clk (up_clk), + .up_dld (up_dld[28]), + .up_dwdata (up_dwdata[144:140]), + .up_drdata (up_drdata[144:140]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + ad_data_in #( + .SINGLE_ENDED(1), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_CTRL (1), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY), + .IDDR_CLK_EDGE("OPPOSITE_EDGE") + ) i_adc_or_cmos_2 ( + .rx_clk (adc_clk), + .rx_data_in_p (cmos_adc_data_or_2), + .rx_data_in_n (), + .rx_data_p (adc_or_s_2_p), + .rx_data_n (adc_or_s_2_n), + .up_clk (up_clk), + .up_dld (up_dld[29]), + .up_dwdata (up_dwdata[149:145]), + .up_drdata (up_drdata[149:145]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + end + + // clock + + ad_data_clk i_adc_clk ( + .rst (1'b0), + .locked (), + .clk_in_p (adc_clk_in_p), + .clk_in_n (adc_clk_in_n), + .clk (adc_clk)); + +endmodule diff --git a/adi_library/axi_adaq8092/axi_adaq8092_ip.tcl b/adi_library/axi_adaq8092/axi_adaq8092_ip.tcl new file mode 100644 index 00000000..bb807f60 --- /dev/null +++ b/adi_library/axi_adaq8092/axi_adaq8092_ip.tcl @@ -0,0 +1,69 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_adaq8092 + +adi_ip_files axi_adaq8092 [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_dcfilter.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "axi_adaq8092_if.v" \ + "axi_adaq8092_channel.v" \ + "axi_adaq8092_apb_decode.v"\ + "axi_adaq8092_rand_decode.v"\ + "axi_adaq8092.v" ] + +adi_ip_properties axi_adaq8092 + +adi_init_bd_tcl +adi_ip_bd axi_adaq8092 "bd/bd.tcl" + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/adaq8092} [ipx::current_core] + +set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *adc* -of_objects [ipx::current_core]] + +set_property -dict [list \ + value_validation_type pairs \ + value_validation_pairs {LVDS 0 CMOS 1 } \ +] [ipx::get_user_parameters OUTPUT_MODE -of_objects [ipx::current_core]] + +set_property enablement_dependency { $OUTPUT_MODE == 0 } \ + [ipx::get_ports *lvds* -of_objects [ipx::current_core]] +set_property enablement_dependency { $OUTPUT_MODE == 1 } \ + [ipx::get_ports *cmos* -of_objects [ipx::current_core]] + +set_property enablement_tcl_expr {$OUTPUT_MODE == 0} \ + [ipx::get_user_parameters POLARITY_MASK -of_objects [ipx::current_core]] + +ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface adc_clk_in_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface adc_clk_in_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +set reset_intf [ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]] +set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_intf] +set_property value "ACTIVE_HIGH" $reset_polarity + +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + +ipx::save_core [ipx::current_core] diff --git a/adi_library/axi_adaq8092/axi_adaq8092_rand_decode.v b/adi_library/axi_adaq8092/axi_adaq8092_rand_decode.v new file mode 100644 index 00000000..e4e11220 --- /dev/null +++ b/adi_library/axi_adaq8092/axi_adaq8092_rand_decode.v @@ -0,0 +1,71 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// ADC DIGITAL OUTPUT RANDOMIZE DECODE + +`timescale 1ns/100ps + +module axi_adaq8092_rand_decode ( + + // data interface + + input [27:0] adc_data, + input adc_clk, + input adc_rand_enb, + output [27:0] adc_data_decoded +); + + // internal register + + reg [27:0] adc_data_decoded_s; + + integer i; + + assign adc_data_decoded = adc_rand_enb ? adc_data_decoded_s : adc_data ; + + // DATA DECODING + + always @(posedge adc_clk) begin + for (i = 1; i <= 13; i = i + 1) begin + adc_data_decoded_s[i] = adc_data[i] ^ adc_data[0]; + end + for (i = 15; i <= 27; i = i + 1) begin + adc_data_decoded_s[i] = adc_data[i] ^ adc_data[14]; + end + + adc_data_decoded_s[0] = adc_data[0]; + adc_data_decoded_s[14] = adc_data[14]; + end + +endmodule diff --git a/adi_library/axi_adaq8092/bd/bd.tcl b/adi_library/axi_adaq8092/bd/bd.tcl new file mode 100644 index 00000000..dceb9498 --- /dev/null +++ b/adi_library/axi_adaq8092/bd/bd.tcl @@ -0,0 +1,47 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + DEV_PACKAGE \ + SPEED_GRADE \ + FPGA_FAMILY \ + FPGA_TECHNOLOGY" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/axi_adaq8092/component.xml b/adi_library/axi_adaq8092/component.xml new file mode 100644 index 00000000..b64f4f10 --- /dev/null +++ b/adi_library/axi_adaq8092/component.xml @@ -0,0 +1,1575 @@ + + + analog.com + user + axi_adaq8092 + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + adc_clk + + + + + + + CLK + + + adc_clk + + + + + + ASSOCIATED_RESET + adc_rst + + + + + delay_clk + + + + + + + CLK + + + delay_clk + + + + + + adc_clk_in_p + + + + + + + CLK + + + adc_clk_in_p + + + + + + adc_clk_in_n + + + + + + + CLK + + + adc_clk_in_n + + + + + + adc_rst + + + + + + + RST + + + adc_rst + + + + + + POLARITY + ACTIVE_HIGH + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_adaq8092 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + bb1a1301 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_adaq8092 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + e3df1f91 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 373784f1 + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + + + adc_clk_in_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_clk_in_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + lvds_adc_data_in1_p + + in + + 6 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + lvds_adc_data_in1_n + + in + + 6 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + lvds_adc_data_in2_p + + in + + 6 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + lvds_adc_data_in2_n + + in + + 6 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + lvds_adc_or_in_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + lvds_adc_or_in_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + cmos_adc_data_in1 + + in + + 13 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + cmos_adc_data_in2 + + in + + 13 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + cmos_adc_or_in_1 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + cmos_adc_or_in_2 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + delay_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_rst + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_enable_1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_enable_2 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_data_channel1 + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_data_channel2 + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_dovf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + ADC_DATAPATH_DISABLE + Adc Datapath Disable + 0 + + + IO_DELAY_GROUP + Io Delay Group + adc_if_delay_group + + + OUTPUT_MODE + Output Mode + 0 + + + POLARITY_MASK + Polarity Mask + 0x0FFFFFFF + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_00ecfe9a + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + + + choice_pairs_092d6e3a + 0 + 1 + + + choice_pairs_19f99f31 + 0 + 10 + 11 + 12 + 13 + 14 + 20 + 21 + 22 + 23 + 24 + 25 + 30 + + + choice_pairs_28f798a2 + 0 + 1 + 2 + 3 + 4 + + + choice_pairs_fc01a186 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../xilinx/common/up_clock_mon_constr.xdc + xdc + + + ../xilinx/common/ad_data_clk.v + verilogSource + + + ../xilinx/common/ad_data_in.v + verilogSource + + + ../common/ad_datafmt.v + verilogSource + + + ../xilinx/common/ad_dcfilter.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + axi_adaq8092_apb_decode.v + verilogSource + + + axi_adaq8092_channel.v + verilogSource + + + axi_adaq8092_if.v + verilogSource + + + axi_adaq8092_rand_decode.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_delay_cntrl.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_adaq8092.v + verilogSource + CHECKSUM_4e016119 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../xilinx/common/ad_data_clk.v + verilogSource + + + ../xilinx/common/ad_data_in.v + verilogSource + + + ../common/ad_datafmt.v + verilogSource + + + ../xilinx/common/ad_dcfilter.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + axi_adaq8092_apb_decode.v + verilogSource + + + axi_adaq8092_channel.v + verilogSource + + + axi_adaq8092_if.v + verilogSource + + + axi_adaq8092_rand_decode.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_delay_cntrl.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_adaq8092.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_adaq8092_v1_0.tcl + tclSource + CHECKSUM_7027a60d + XGUI_VERSION_2 + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + xilinx_utilityxitfiles_view_fileset + + gui/axi_adaq8092_v1_0.gtcl + GTCL + + + + axi_adaq8092_v1_0 + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + ADC_DATAPATH_DISABLE + Adc Datapath Disable + 0 + + + IO_DELAY_GROUP + Io Delay Group + adc_if_delay_group + + + OUTPUT_MODE + Output Mode + 0 + + + POLARITY_MASK + Polarity Mask + 0x0FFFFFFF + + + + true + + + + + + Component_Name + axi_adaq8092_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_adaq8092_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/adaq8092 + 1 + 2024-01-14T03:43:58Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_adaq8092/gui/axi_adaq8092_v1_0.gtcl b/adi_library/axi_adaq8092/gui/axi_adaq8092_v1_0.gtcl new file mode 100644 index 00000000..9339abd7 --- /dev/null +++ b/adi_library/axi_adaq8092/gui/axi_adaq8092_v1_0.gtcl @@ -0,0 +1,2 @@ +# This file is automatically written. Do not modify. +proc gen_USERPARAMETER_POLARITY_MASK_ENABLEMENT {OUTPUT_MODE } {expr $OUTPUT_MODE == 0} diff --git a/adi_library/axi_adaq8092/temporary_case_dependencies.mk b/adi_library/axi_adaq8092/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/axi_adaq8092/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/axi_adaq8092/xgui/axi_adaq8092_v1_0.tcl b/adi_library/axi_adaq8092/xgui/axi_adaq8092_v1_0.tcl new file mode 100644 index 00000000..877a7edf --- /dev/null +++ b/adi_library/axi_adaq8092/xgui/axi_adaq8092_v1_0.tcl @@ -0,0 +1,161 @@ + +# Loading additional proc with user specified bodies to compute parameter values. +source [file join [file dirname [file dirname [info script]]] gui/axi_adaq8092_v1_0.gtcl] + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ADC_DATAPATH_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "IO_DELAY_GROUP" -parent ${Page_0} + ipgui::add_param $IPINST -name "OUTPUT_MODE" -parent ${Page_0} + ipgui::add_param $IPINST -name "POLARITY_MASK" -parent ${Page_0} + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.POLARITY_MASK { PARAM_VALUE.POLARITY_MASK PARAM_VALUE.OUTPUT_MODE } { + # Procedure called to update POLARITY_MASK when any of the dependent parameters in the arguments change + + set POLARITY_MASK ${PARAM_VALUE.POLARITY_MASK} + set OUTPUT_MODE ${PARAM_VALUE.OUTPUT_MODE} + set values(OUTPUT_MODE) [get_property value $OUTPUT_MODE] + if { [gen_USERPARAMETER_POLARITY_MASK_ENABLEMENT $values(OUTPUT_MODE)] } { + set_property enabled true $POLARITY_MASK + } else { + set_property enabled false $POLARITY_MASK + } +} + +proc validate_PARAM_VALUE.POLARITY_MASK { PARAM_VALUE.POLARITY_MASK } { + # Procedure called to validate POLARITY_MASK + return true +} + +proc update_PARAM_VALUE.ADC_DATAPATH_DISABLE { PARAM_VALUE.ADC_DATAPATH_DISABLE } { + # Procedure called to update ADC_DATAPATH_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADC_DATAPATH_DISABLE { PARAM_VALUE.ADC_DATAPATH_DISABLE } { + # Procedure called to validate ADC_DATAPATH_DISABLE + return true +} + +proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to validate DEV_PACKAGE + return true +} + +proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to validate FPGA_FAMILY + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to update IO_DELAY_GROUP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to validate IO_DELAY_GROUP + return true +} + +proc update_PARAM_VALUE.OUTPUT_MODE { PARAM_VALUE.OUTPUT_MODE } { + # Procedure called to update OUTPUT_MODE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUTPUT_MODE { PARAM_VALUE.OUTPUT_MODE } { + # Procedure called to validate OUTPUT_MODE + return true +} + +proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to validate SPEED_GRADE + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY} +} + +proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE} +} + +proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE} +} + +proc update_MODELPARAM_VALUE.ADC_DATAPATH_DISABLE { MODELPARAM_VALUE.ADC_DATAPATH_DISABLE PARAM_VALUE.ADC_DATAPATH_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADC_DATAPATH_DISABLE}] ${MODELPARAM_VALUE.ADC_DATAPATH_DISABLE} +} + +proc update_MODELPARAM_VALUE.IO_DELAY_GROUP { MODELPARAM_VALUE.IO_DELAY_GROUP PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IO_DELAY_GROUP}] ${MODELPARAM_VALUE.IO_DELAY_GROUP} +} + +proc update_MODELPARAM_VALUE.OUTPUT_MODE { MODELPARAM_VALUE.OUTPUT_MODE PARAM_VALUE.OUTPUT_MODE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUTPUT_MODE}] ${MODELPARAM_VALUE.OUTPUT_MODE} +} + +proc update_MODELPARAM_VALUE.POLARITY_MASK { MODELPARAM_VALUE.POLARITY_MASK PARAM_VALUE.POLARITY_MASK } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.POLARITY_MASK}] ${MODELPARAM_VALUE.POLARITY_MASK} +} + diff --git a/adi_library/axi_adc_decimate/Makefile b/adi_library/axi_adc_decimate/Makefile new file mode 100644 index 00000000..c5cbe7e5 --- /dev/null +++ b/adi_library/axi_adc_decimate/Makefile @@ -0,0 +1,24 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_adc_decimate + +GENERIC_DEPS += ../common/ad_iqcor.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += axi_adc_decimate.v +GENERIC_DEPS += axi_adc_decimate_filter.v +GENERIC_DEPS += axi_adc_decimate_reg.v +GENERIC_DEPS += cic_decim.v +GENERIC_DEPS += fir_decim.v + +XILINX_DEPS += ../xilinx/common/ad_mul.v +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += axi_adc_decimate_ip.tcl + +XILINX_LIB_DEPS += util_cic + +include ../scripts/library.mk diff --git a/adi_library/axi_adc_decimate/axi_adc_decimate.v b/adi_library/axi_adc_decimate/axi_adc_decimate.v new file mode 100644 index 00000000..9c216cb4 --- /dev/null +++ b/adi_library/axi_adc_decimate/axi_adc_decimate.v @@ -0,0 +1,186 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adc_decimate #( + + parameter CORRECTION_DISABLE = 1 +) ( + input adc_clk, + input adc_rst, + + input [15:0] adc_data_a, + input [15:0] adc_data_b, + input adc_valid_a, + input adc_valid_b, + + output [15:0] adc_dec_data_a, + output [15:0] adc_dec_data_b, + output adc_dec_valid_a, + output adc_dec_valid_b, + output [ 2:0] adc_data_rate, + output adc_oversampling_en, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [ 6:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [ 6:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready +); + + // internal signals + + wire up_clk; + wire up_rstn; + wire [ 4:0] up_waddr; + wire [31:0] up_wdata; + wire up_wack; + wire up_wreq; + wire up_rack; + wire [31:0] up_rdata; + wire up_rreq; + wire [ 4:0] up_raddr; + + wire [31:0] decimation_ratio; + wire [ 2:0] filter_mask; + wire adc_correction_enable_a; + wire adc_correction_enable_b; + wire [15:0] adc_correction_coefficient_a; + wire [15:0] adc_correction_coefficient_b; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + assign adc_data_rate = filter_mask; + assign adc_oversampling_en = |decimation_ratio; + + axi_adc_decimate_filter #( + .CORRECTION_DISABLE(CORRECTION_DISABLE) + ) axi_adc_decimate_filter ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + + .decimation_ratio (decimation_ratio), + .filter_mask (filter_mask), + .adc_correction_enable_a(adc_correction_enable_a), + .adc_correction_enable_b(adc_correction_enable_b), + .adc_correction_coefficient_a(adc_correction_coefficient_a), + .adc_correction_coefficient_b(adc_correction_coefficient_b), + + .adc_valid_a(adc_valid_a), + .adc_valid_b(adc_valid_b), + .adc_data_a(adc_data_a[11:0]), + .adc_data_b(adc_data_b[11:0]), + + .adc_dec_data_a(adc_dec_data_a), + .adc_dec_data_b(adc_dec_data_b), + .adc_dec_valid_a(adc_dec_valid_a), + .adc_dec_valid_b(adc_dec_valid_b)); + + axi_adc_decimate_reg axi_adc_decimate_reg ( + .clk (adc_clk), + + .adc_decimation_ratio (decimation_ratio), + .adc_filter_mask (filter_mask), + + .adc_correction_enable_a(adc_correction_enable_a), + .adc_correction_enable_b(adc_correction_enable_b), + .adc_correction_coefficient_a(adc_correction_coefficient_a), + .adc_correction_coefficient_b(adc_correction_coefficient_b), + + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + + up_axi #( + .AXI_ADDRESS_WIDTH(7) + ) i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_adc_decimate/axi_adc_decimate.xpr b/adi_library/axi_adc_decimate/axi_adc_decimate.xpr new file mode 100644 index 00000000..efd6d632 --- /dev/null +++ b/adi_library/axi_adc_decimate/axi_adc_decimate.xpr @@ -0,0 +1,461 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_adc_decimate/axi_adc_decimate_filter.v b/adi_library/axi_adc_decimate/axi_adc_decimate_filter.v new file mode 100644 index 00000000..4f21caa0 --- /dev/null +++ b/adi_library/axi_adc_decimate/axi_adc_decimate_filter.v @@ -0,0 +1,210 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adc_decimate_filter #( + + parameter CORRECTION_DISABLE = 1 +) ( + input adc_clk, + input adc_rst, + + input [31:0] decimation_ratio, + input [ 2:0] filter_mask, + + input adc_correction_enable_a, + input adc_correction_enable_b, + input [15:0] adc_correction_coefficient_a, + input [15:0] adc_correction_coefficient_b, + + input adc_valid_a, + input adc_valid_b, + input [11:0] adc_data_a, + input [11:0] adc_data_b, + + output [15:0] adc_dec_data_a, + output [15:0] adc_dec_data_b, + output adc_dec_valid_a, + output adc_dec_valid_b +); + + // internal signals + + reg [31:0] decimation_counter; + + reg adc_dec_valid_a_filter; + reg adc_dec_valid_b_filter; + + reg [4:0] filter_enable = 5'h00; + + reg [15:0] adc_dec_data_a_r; + reg [15:0] adc_dec_data_b_r; + reg adc_dec_valid_a_r; + reg adc_dec_valid_b_r; + + wire [25:0] adc_fir_data_a; + wire adc_fir_valid_a; + wire [25:0] adc_fir_data_b; + wire adc_fir_valid_b; + + wire [11:0] adc_cic_data_a; + wire adc_cic_valid_a; + wire [11:0] adc_cic_data_b; + wire adc_cic_valid_b; + + cic_decim cic_decimation_a ( + .clk(adc_clk), + .clk_enable(adc_valid_a), + .filter_enable(filter_enable), + .reset(adc_rst), + .filter_in(adc_data_a[11:0]), + .rate_sel(filter_mask), + .filter_out(adc_cic_data_a), + .ce_out(adc_cic_valid_a)); + + cic_decim cic_decimation_b ( + .clk(adc_clk), + .clk_enable(adc_valid_b), + .filter_enable(filter_enable), + .reset(adc_rst), + .filter_in(adc_data_b[11:0]), + .rate_sel(filter_mask), + .filter_out(adc_cic_data_b), + .ce_out(adc_cic_valid_b)); + + fir_decim fir_decimation_a ( + .clk(adc_clk), + .clk_enable(adc_cic_valid_a), + .reset(adc_rst), + .filter_in(adc_cic_data_a), + .filter_out(adc_fir_data_a), + .ce_out(adc_fir_valid_a)); + + fir_decim fir_decimation_b ( + .clk(adc_clk), + .clk_enable(adc_cic_valid_b), + .reset(adc_rst), + .filter_in(adc_cic_data_b), + .filter_out(adc_fir_data_b), + .ce_out(adc_fir_valid_b)); + + ad_iqcor #( + .Q_OR_I_N (0), + .DISABLE(CORRECTION_DISABLE), + .SCALE_ONLY(1) + ) i_scale_correction_a ( + .clk (adc_clk), + .valid (adc_dec_valid_a_r), + .data_in (adc_dec_data_a_r), + .data_iq (16'h0), + .valid_out (adc_dec_valid_a), + .data_out (adc_dec_data_a), + .iqcor_enable (adc_correction_enable_a), + .iqcor_coeff_1 (adc_correction_coefficient_a), + .iqcor_coeff_2 (16'h0)); + + ad_iqcor #( + .Q_OR_I_N (0), + .DISABLE(CORRECTION_DISABLE), + .SCALE_ONLY(1) + ) i_scale_correction_b ( + .clk (adc_clk), + .valid (adc_dec_valid_b_r), + .data_in (adc_dec_data_b_r), + .data_iq (16'h0), + .valid_out (adc_dec_valid_b), + .data_out (adc_dec_data_b), + .iqcor_enable (adc_correction_enable_b), + .iqcor_coeff_1 (adc_correction_coefficient_b), + .iqcor_coeff_2 (16'h0)); + + always @(posedge adc_clk) begin + case (filter_mask) + 3'h1: filter_enable <= 5'b00001; + 3'h2: filter_enable <= 5'b00011; + 3'h3: filter_enable <= 5'b00111; + 3'h6: filter_enable <= 5'b01111; + 3'h7: filter_enable <= 5'b11111; + default: filter_enable <= 5'b00000; + endcase + end + + always @(*) begin + case (filter_enable[0]) + 1'b0: adc_dec_data_a_r = {{4{adc_data_a[11]}},adc_data_a}; + default: adc_dec_data_a_r = {adc_fir_data_a[25], adc_fir_data_a[25:11]}; + endcase + + case (filter_enable[0]) + 1'b0: adc_dec_valid_a_filter = adc_valid_a; + default: adc_dec_valid_a_filter = adc_fir_valid_a; + endcase + + case (filter_enable[0]) + 1'b0: adc_dec_data_b_r = {{4{adc_data_b[11]}},adc_data_b}; + default adc_dec_data_b_r = {adc_fir_data_b[25], adc_fir_data_b[25:11]}; + endcase + + case (filter_enable[0]) + 1'b0: adc_dec_valid_b_filter = adc_valid_b; + default: adc_dec_valid_b_filter = adc_fir_valid_b; + endcase + end + + always @(posedge adc_clk) begin + if (adc_rst == 1'b1) begin + decimation_counter <= 32'b0; + adc_dec_valid_a_r <= 1'b0; + adc_dec_valid_b_r <= 1'b0; + end else begin + if (adc_dec_valid_a_filter == 1'b1) begin + if (decimation_counter < decimation_ratio) begin + decimation_counter <= decimation_counter + 1; + adc_dec_valid_a_r <= 1'b0; + adc_dec_valid_b_r <= 1'b0; + end else begin + decimation_counter <= 0; + adc_dec_valid_a_r <= 1'b1; + adc_dec_valid_b_r <= 1'b1; + end + end else begin + adc_dec_valid_a_r <= 1'b0; + adc_dec_valid_b_r <= 1'b0; + end + end + end + +endmodule diff --git a/adi_library/axi_adc_decimate/axi_adc_decimate_ip.tcl b/adi_library/axi_adc_decimate/axi_adc_decimate_ip.tcl new file mode 100644 index 00000000..59062a14 --- /dev/null +++ b/adi_library/axi_adc_decimate/axi_adc_decimate_ip.tcl @@ -0,0 +1,36 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create axi_adc_decimate +adi_ip_files axi_adc_decimate [list \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/ad_iqcor.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "fir_decim.v" \ + "cic_decim.v" \ + "axi_adc_decimate_filter.v" \ + "axi_adc_decimate_reg.v" \ + "axi_adc_decimate.v" ] + +adi_ip_properties axi_adc_decimate + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_adc_decimate} [ipx::current_core] + +adi_ip_add_core_dependencies [list \ + analog.com:$VIVADO_IP_LIBRARY:util_cic:1.0 \ +] + +ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] diff --git a/adi_library/axi_adc_decimate/axi_adc_decimate_reg.v b/adi_library/axi_adc_decimate/axi_adc_decimate_reg.v new file mode 100644 index 00000000..c57cfb55 --- /dev/null +++ b/adi_library/axi_adc_decimate/axi_adc_decimate_reg.v @@ -0,0 +1,155 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adc_decimate_reg( + + input clk, + + output [31:0] adc_decimation_ratio, + output [ 2:0] adc_filter_mask, + + output adc_correction_enable_a, + output adc_correction_enable_b, + output [15:0] adc_correction_coefficient_a, + output [15:0] adc_correction_coefficient_b, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [ 4:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [ 4:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack +); + + // internal registers + + reg [31:0] up_version = 32'h00010000; + reg [31:0] up_scratch = 32'h0; + + reg [31:0] up_decimation_ratio = 32'h0; + reg [ 2:0] up_filter_mask = 32'h0; + + reg [ 1:0] up_config = 1'h0; + reg [15:0] up_correction_coefficient_a = 16'h0; + reg [15:0] up_correction_coefficient_b = 16'h0; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_scratch <= 'd0; + up_decimation_ratio <= 'd0; + up_filter_mask <= 'd0; + up_config <= 'd0; + up_correction_coefficient_a <= 'd0; + up_correction_coefficient_b <= 'd0; + end else begin + up_wack <= up_wreq; + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin + up_scratch <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h10)) begin + up_decimation_ratio <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h11)) begin + up_filter_mask <= up_wdata[2:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h12)) begin + up_config <= up_wdata[1:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h13)) begin + up_correction_coefficient_a <= up_wdata[15:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h14)) begin + up_correction_coefficient_b <= up_wdata[15:0]; + end + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq; + if (up_rreq == 1'b1) begin + case (up_raddr[4:0]) + 5'h0: up_rdata <= up_version; + 5'h1: up_rdata <= up_scratch; + 5'h10: up_rdata <= up_decimation_ratio; + 5'h11: up_rdata <= { 29'h0, up_filter_mask }; + 5'h12: up_rdata <= { 30'h0, up_config }; + 5'h13: up_rdata <= { 16'h0, up_correction_coefficient_a }; + 5'h14: up_rdata <= { 16'h0, up_correction_coefficient_b }; + default: up_rdata <= 0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + up_xfer_cntrl #( + .DATA_WIDTH (69) + ) i_xfer_cntrl ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_cntrl ({ up_config[1], // 1 + up_config[0], // 1 + up_correction_coefficient_b, // 16 + up_correction_coefficient_a, // 16 + up_decimation_ratio, // 32 + up_filter_mask}), // 3 + + .up_xfer_done (), + .d_rst (1'b0), + .d_clk (clk), + .d_data_cntrl ({ adc_correction_enable_b, // 1 + adc_correction_enable_a, // 1 + adc_correction_coefficient_b, // 16 + adc_correction_coefficient_a, // 16 + adc_decimation_ratio, // 32 + adc_filter_mask})); // 3 + +endmodule diff --git a/adi_library/axi_adc_decimate/cic_decim.v b/adi_library/axi_adc_decimate/cic_decim.v new file mode 100644 index 00000000..13866099 --- /dev/null +++ b/adi_library/axi_adc_decimate/cic_decim.v @@ -0,0 +1,159 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1 ns / 1 ns + +module cic_decim ( + input clk, + input clk_enable, + input [4:0] filter_enable, + input reset, + input [11:0] filter_in, + input [2:0] rate_sel, + output [11:0] filter_out, + output ce_out +); + + localparam NUM_STAGES = 6; + localparam DATA_WIDTH = 106; + + reg [11:0] filter_input_stage = 'h00; + wire signed [DATA_WIDTH-1:0] data_stage[0:NUM_STAGES*2]; + wire signed [DATA_WIDTH-1:0] data_final_stage; + + reg [16:0] counter = 'h00; + reg ce_comb = 1'b0; + + reg ce_out_reg = 1'b0; + reg [11:0] data_out = 'h00; + + reg [15:0] rate; + + wire [4:0] enable = (clk_enable == 1'b1) ? filter_enable : 5'b0; + + always @(*) begin + case (rate_sel) + 3'h1: rate <= 16'd5 - 1; + 3'h2: rate <= 16'd50 - 1; + 3'h3: rate <= 16'd500 - 1; + 3'h6: rate <= 16'd5000 - 1; + default: rate <= 16'd50000 - 1; + endcase + end + + wire [15:0] counter_in = counter[16] == 1'b1 ? rate : counter[15:0]; + + always @(posedge clk) begin + if (reset == 1'b1) begin + counter <= {1'b1,16'h00}; + end else if (clk_enable == 1'b1 && enable[0] == 1'b1) begin + counter <= counter_in - 1'b1; + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + ce_comb <= 1'b0; + end else begin + ce_comb <= enable[0] & counter[16]; + end + end + + always @(posedge clk) begin + if (enable[0] == 1'b1) begin + filter_input_stage <= filter_in; + end + end + + assign data_stage[0] = $signed(filter_input_stage); + + generate + genvar i; + for (i = 0; i < NUM_STAGES; i = i + 1) begin + cic_int #( + .DATA_WIDTH(DATA_WIDTH), + .NUM_STAGES(5), + .STAGE_WIDTH(20) + ) i_int ( + .clk(clk), + .ce(enable), + .data_in(data_stage[i]), + .data_out(data_stage[i+1])); + end + endgenerate + + cic_comb #( + .DATA_WIDTH(DATA_WIDTH), + .SEQ(5), + .NUM_STAGES(5), + .STAGE_WIDTH(20) + ) i_comb0 ( + .clk(clk), + .ce(ce_comb), + .enable(filter_enable), + .data_in(data_stage[6]), + .data_out(data_stage[11])); + + cic_comb #( + .DATA_WIDTH(DATA_WIDTH), + .SEQ(1), + .NUM_STAGES(5), + .STAGE_WIDTH(20) + ) i_comb1 ( + .clk(clk), + .ce(ce_comb), + .enable(filter_enable), + .data_in(data_stage[11]), + .data_out(data_stage[12])); + + assign data_final_stage = data_stage[2*NUM_STAGES]; + + always @(posedge clk) begin + if (ce_comb == 1'b1) begin + case (rate_sel) + 'h1: data_out <= data_final_stage[25:14]; + 'h2: data_out <= data_final_stage[45:34]; + 'h3: data_out <= data_final_stage[65:54]; + 'h6: data_out <= data_final_stage[85:74]; + default: data_out <= data_final_stage[105:94]; + endcase + end + ce_out_reg <= ce_comb; + end + + assign ce_out = ce_out_reg; + assign filter_out = data_out; + +endmodule // cic_decim diff --git a/adi_library/axi_adc_decimate/component.xml b/adi_library/axi_adc_decimate/component.xml new file mode 100644 index 00000000..81b172f6 --- /dev/null +++ b/adi_library/axi_adc_decimate/component.xml @@ -0,0 +1,1049 @@ + + + analog.com + user + axi_adc_decimate + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + adc_clk + + + + + + + CLK + + + adc_clk + + + + + + ASSOCIATED_RESET + adc_rst + + + + + adc_rst + + + + + + + RST + + + adc_rst + + + + + + + + s_axi + + axi_lite + 0 + 128 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_adc_decimate + + xilinx_anylanguagesynthesis_analog_com_user_util_cic_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 8aeba977 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_adc_decimate + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cic_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 5bbf0b8c + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_analog_com_user_util_cic_1_0__ref_view_fileset + + + xilinx_xpgui_view_fileset + + + + viewChecksum + 18feff19 + + + + + + + adc_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_rst + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_a + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_data_b + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + adc_valid_a + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid_b + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_dec_data_a + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_dec_data_b + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_dec_valid_a + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_dec_valid_b + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data_rate + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_oversampling_en + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 6 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 6 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + CORRECTION_DISABLE + Correction Disable + 1 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../common/ad_iqcor.v + verilogSource + + + ../xilinx/common/ad_mul.v + verilogSource + + + axi_adc_decimate_filter.v + verilogSource + + + axi_adc_decimate_reg.v + verilogSource + + + cic_decim.v + verilogSource + + + fir_decim.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + axi_adc_decimate.v + verilogSource + CHECKSUM_7d514d91 + + + + xilinx_anylanguagesynthesis_analog_com_user_util_cic_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_iqcor.v + verilogSource + + + ../xilinx/common/ad_mul.v + verilogSource + + + axi_adc_decimate_filter.v + verilogSource + + + axi_adc_decimate_reg.v + verilogSource + + + cic_decim.v + verilogSource + + + fir_decim.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + axi_adc_decimate.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cic_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axi_adc_decimate_v1_0.tcl + tclSource + CHECKSUM_18feff19 + XGUI_VERSION_2 + + + + xilinx_xpgui_analog_com_user_util_cic_1_0__ref_view_fileset + + + + + + + + axi_adc_decimate_v1_0 + + + CORRECTION_DISABLE + Correction Disable + 1 + + + Component_Name + axi_adc_decimate_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_adc_decimate_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_adc_decimate + 1 + 2024-01-14T03:44:17Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_adc_decimate/fir_decim.v b/adi_library/axi_adc_decimate/fir_decim.v new file mode 100644 index 00000000..7da46732 --- /dev/null +++ b/adi_library/axi_adc_decimate/fir_decim.v @@ -0,0 +1,279 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1 ns / 1 ns + +module fir_decim #( + parameter USE_DSP48E = 1 +) ( + input clk, + input clk_enable, + input reset, + input signed [11:0] filter_in, + output reg signed [25:0] filter_out, + output reg ce_out +); + + localparam signed [11:0] coeffphase1_1 = 12'b000011010101; //sfix12_En11 + localparam signed [11:0] coeffphase1_2 = 12'b011011110010; //sfix12_En11 + localparam signed [11:0] coeffphase1_3 = 12'b110000111110; //sfix12_En11 + + // We know that clk_enable is asserted at most every 5th clock cycle and the + // output is decimated by two. So we have 10 clock cycles to compute the + // result. That's plenty of time considering that there are only 6 + // coefficients. + + reg active = 1'b0; + reg active_d1 = 1'b0; + reg active_d2 = 1'b0; + + reg [1:0] count = 2'b00; + reg phase = 1'b1; + reg ready = 1'b0; + + reg [3:0] storage0[0:11]; + reg [3:0] storage1[0:11]; + + reg signed [11:0] data0; + reg signed [11:0] data1; + + reg signed [11:0] coeff; + + wire signed [25:0] sum; + + integer j; + + initial begin + for (j = 0; j < 12; j = j + 1) begin + storage0[j] <= 'h00; + storage1[j] <= 'h00; + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + phase <= 1'b1; + end else begin + if (clk_enable == 1'b1) begin + phase <= phase + 1'b1; + end + end + end + + always @(posedge clk) begin + if (clk_enable == 1'b1 && phase == 1'b1) begin + active <= 1'b1; + end else if (count == 'h2) begin + active <= 1'b0; + end + active_d1 <= active; + active_d2 <= active_d1; + end + + always @(posedge clk) begin + if (active == 1'b1) begin + case (count) + 'h2: count <= 'h0; + default: count <= count + 1'b1; + endcase + end + end + + always @(posedge clk) begin + if (active_d1 == 1'b0 && active_d2 == 1'b1) begin + ready <= 1'b1; + end else begin + ready <= 1'b0; + end + end + + generate + genvar i; + for (i = 0; i < 12; i = i + 1) begin + always @(posedge clk) begin + if (clk_enable == 1'b1) begin + if (phase == 1'b0) begin + storage0[i] <= {storage0[i][2:0],filter_in[i]}; + end + if (phase == 1'b1) begin + storage1[i] <= {storage1[i][2:0],filter_in[i]}; + end + end + end + + always @(*) begin + data0[i] <= storage0[i][2-count]; + data1[i] <= storage1[i][count]; + end + end + endgenerate + + always @(*) begin + case (count) + 'h0: coeff <= coeffphase1_1; + 'h1: coeff <= coeffphase1_2; + 'h2: coeff <= coeffphase1_3; + default: coeff <= 'h00; + endcase + end + + generate if (USE_DSP48E) begin + wire [47:0] _sum; + wire [6:0] opmode = {1'b0,active_d2,5'b00101}; + + // Can't exceed 26 bit. + assign sum = _sum[43:18]; + + // MAC with pre-adder + DSP48E1 #( + .ACASCREG (0), + .ADREG (1), + .ALUMODEREG (0), + .AREG (0), + .AUTORESET_PATDET ("NO_RESET"), + .A_INPUT ("DIRECT"), + .BCASCREG (1), + .BREG (1), + .B_INPUT ("DIRECT"), + .CARRYINREG (0), + .CARRYINSELREG (0), + .CREG (0), + .DREG (0), + .INMODEREG (0), + .MASK (48'h3fffffffffff), + .MREG (1), + .OPMODEREG (1), + .PATTERN (48'h000000000000), + .PREG (1), + .SEL_MASK ("MASK"), + .SEL_PATTERN ("PATTERN"), + .USE_DPORT ("TRUE"), + .USE_MULT ("MULTIPLY"), + .USE_PATTERN_DETECT ("NO_PATDET"), + .USE_SIMD ("ONE48")) + i_dsp_mac ( + .CLK (clk), + .A ({5'h0,data0[11],data0,12'h0}), // MSB aligned to 24-bit, 25th bit signed extended + .B ({coeff,6'b0}), + .C (48'h00), + .D ({data1[11],data1,12'h0}), + .MULTSIGNIN (1'b0), + .CARRYIN (1'b0), + .CARRYCASCIN (1'b0), + .ACIN (30'h0), + .BCIN (18'h0), + .PCIN (48'h0), + .P (_sum), + .MULTSIGNOUT (), + .CARRYOUT (), + .CARRYCASCOUT (), + .ACOUT (), + .BCOUT (), + .PCOUT (), + .ALUMODE (4'b0000), + .CARRYINSEL (3'h0), + .INMODE (5'b00100), + .OPMODE (opmode), + .PATTERNBDETECT (), + .PATTERNDETECT (), + .OVERFLOW (), + .UNDERFLOW (), + .CEA1 (1'b0), + .CEA2 (1'b0), + .CEAD (active), + .CEALUMODE (1'b0), + .CEB1 (1'b0), + .CEB2 (active), + .CEC (1'b0), + .CECARRYIN (1'b0), + .CECTRL (active), + .CED (1'b0), + .CEINMODE (1'b0), + .CEM (active_d1), + .CEP (active_d2), + .RSTA (1'b0), + .RSTALLCARRYIN (1'b0), + .RSTALUMODE (1'b0), + .RSTB (1'b0), + .RSTC (1'b0), + .RSTCTRL (1'b0), + .RSTD (1'b0), + .RSTINMODE (1'b0), + .RSTM (1'b0), + .RSTP (1'b0) + ); + + end else begin + reg signed [25:0] _sum = 'h00; + reg signed [12:0] pre_adder; + reg signed [11:0] coeff_d1; + reg signed [23:0] product = 'h00; + + assign sum = _sum; + + always @(posedge clk) begin + if (active == 1'b1) begin + pre_adder <= data0 + data1; + coeff_d1 <= coeff; + end + + if (active_d1 == 1'b1) begin + product <= coeff_d1 * pre_adder; + end + + if (reset == 1'b1 || ready == 1'b1) begin + _sum <= 'h00; + end else if (active_d2 == 1'b1) begin + _sum <= _sum + product; + end + end + end + endgenerate + + always @(posedge clk) begin + if (reset == 1'b1) begin + ce_out <= 1'b0; + end else begin + ce_out <= ready; + end + end + + always @(posedge clk) begin + if (ready == 1'b1) begin + filter_out <= sum; + end + end + +endmodule diff --git a/adi_library/axi_adc_decimate/m2k_decim.m b/adi_library/axi_adc_decimate/m2k_decim.m new file mode 100644 index 00000000..7ff2e46c --- /dev/null +++ b/adi_library/axi_adc_decimate/m2k_decim.m @@ -0,0 +1,46 @@ +clear all; +close all; + +decim_rate = 50000; + +h_cic = dsp.CICDecimator(decim_rate,1,6); +gainCIC = (h_cic.DecimationFactor*h_cic.DifferentialDelay)^h_cic.NumSections +[h1, w1] = h_cic.freqz(); + +fs = 1; +fPass = 0.20; +fStop = 0.50; +ast = 70; + +CICCompDecim = dsp.CICCompensationDecimator(h_cic, ... + 'DecimationFactor',2,'PassbandFrequency',fPass, ... + 'StopbandFrequency',fStop,'SampleRate',fs, ... + 'StopbandAttenuation',ast); +[h2, w2] = CICCompDecim.freqz(); +CICCompDecim.coeffs() + +FC = dsp.FilterCascade(h_cic,CICCompDecim); +[h3, w3] = FC.freqz(); + +subplot(311); hold on; +plot(w1/pi, 20*log10(abs(h1)/gainCIC)); +plot(w2/pi, 20*log10(abs(h2))); +hold off; grid + +subplot(312); plot(w3/pi, 20*log10(abs(h3)/gainCIC)); grid + +% M = 8; % Decimation factor +% Fp = 40; % Passband-edge frequency +% Fst = 60; % Stopband-edge frequency +% Ap = 0.1; % Passband peak-to-peak ripple +% Ast = 80; % Minimum stopband attenuation +% Fs = 800; % Sampling frequency +% HfdDecim = fdesign.decimator(M,'lowpass',Fp,Fst,Ap,Ast,Fs); +% HNyqDecim = design(HfdDecim,'kaiserwin','SystemObject', true); +% +% [h4, w4] = freqz(HNyqDecim); +% subplot(313); plot(w4/pi, 20*log10(abs(h4))); grid + +nt = numerictype(1,12,11); +fdhdltool(h_cic, nt); +fdhdltool(CICCompDecim, nt) \ No newline at end of file diff --git a/adi_library/axi_adc_decimate/xgui/axi_adc_decimate_v1_0.tcl b/adi_library/axi_adc_decimate/xgui/axi_adc_decimate_v1_0.tcl new file mode 100644 index 00000000..dd6d1dbb --- /dev/null +++ b/adi_library/axi_adc_decimate/xgui/axi_adc_decimate_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "CORRECTION_DISABLE" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.CORRECTION_DISABLE { PARAM_VALUE.CORRECTION_DISABLE } { + # Procedure called to update CORRECTION_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CORRECTION_DISABLE { PARAM_VALUE.CORRECTION_DISABLE } { + # Procedure called to validate CORRECTION_DISABLE + return true +} + + +proc update_MODELPARAM_VALUE.CORRECTION_DISABLE { MODELPARAM_VALUE.CORRECTION_DISABLE PARAM_VALUE.CORRECTION_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CORRECTION_DISABLE}] ${MODELPARAM_VALUE.CORRECTION_DISABLE} +} + diff --git a/adi_library/axi_adc_trigger/Makefile b/adi_library/axi_adc_trigger/Makefile new file mode 100644 index 00000000..905e9b88 --- /dev/null +++ b/adi_library/axi_adc_trigger/Makefile @@ -0,0 +1,18 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_adc_trigger + +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += axi_adc_trigger.v +GENERIC_DEPS += axi_adc_trigger_reg.v + +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += axi_adc_trigger_constr.xdc +XILINX_DEPS += axi_adc_trigger_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_adc_trigger/axi_adc_trigger.v b/adi_library/axi_adc_trigger/axi_adc_trigger.v new file mode 100644 index 00000000..6d7274a0 --- /dev/null +++ b/adi_library/axi_adc_trigger/axi_adc_trigger.v @@ -0,0 +1,645 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adc_trigger #( + + // parameters + + parameter SIGN_BITS = 2, + parameter OUT_PIN_HOLD_N = 100000 +) ( + + // interface + + input clk, + input reset, + + input trigger_in, + + input [ 1:0] trigger_i, + output reg [ 1:0] trigger_o, + output [ 1:0] trigger_t, + + input [15:0] data_a, + input [15:0] data_b, + input data_valid_a, + input data_valid_b, + + output reg [15:0] data_a_trig, + output reg [15:0] data_b_trig, + output reg data_valid_a_trig, + output reg data_valid_b_trig, + output trigger_out, + output trigger_out_la, + + output [31:0] fifo_depth, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [ 6:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [ 6:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready +); + + localparam DW = 15 - SIGN_BITS; + + // internal signals + + wire up_clk; + wire up_rstn; + wire [ 4:0] up_waddr; + wire [31:0] up_wdata; + wire up_wack; + wire up_wreq; + wire up_rack; + wire [31:0] up_rdata; + wire up_rreq; + wire [ 4:0] up_raddr; + + wire [ 7:0] io_selection; + + wire [ 1:0] low_level; + wire [ 1:0] high_level; + wire [ 1:0] any_edge; + wire [ 1:0] rise_edge; + wire [ 1:0] fall_edge; + + wire [15:0] limit_a; + wire [ 1:0] function_a; + wire [31:0] hysteresis_a; + wire [ 3:0] trigger_l_mix_a; + + wire [15:0] limit_b; + wire [ 1:0] function_b; + wire [31:0] hysteresis_b; + wire [ 3:0] trigger_l_mix_b; + + wire [16:0] trigger_out_control; + wire [31:0] trigger_delay; + + wire [31:0] trigger_holdoff; + wire [19:0] trigger_out_hold_pins; + + wire signed [DW:0] data_a_cmp; + wire signed [DW:0] data_b_cmp; + wire signed [DW:0] limit_a_cmp; + wire signed [DW:0] limit_b_cmp; + + wire comp_low_a_s; // signal is over the limit + wire comp_low_b_s; // signal is over the limit + wire trigger_a_fall_edge; + wire trigger_a_rise_edge; + wire trigger_b_fall_edge; + wire trigger_b_rise_edge; + wire trigger_a_any_edge; + wire trigger_b_any_edge; + wire trigger_out_delayed; + wire [ 1:0] trigger_up_o_s; + wire trigger_out_holdoff; + wire holdoff_cnt_en; + wire streaming; + wire trigger_out_s; + wire embedded_trigger; + wire external_trigger; + + reg trigger_a_d1; // synchronization flip flop + reg trigger_a_d2; // synchronization flip flop + reg trigger_a_d3; + reg trigger_b_d1; // synchronization flip flop + reg trigger_b_d2; // synchronization flip flop + reg trigger_b_d3; + reg comp_high_a; // signal is over the limit + reg old_comp_high_a; // t + 1 version of comp_high_a + reg hyst_high_limit_pass_a; // valid hysteresis range on passthrough high trigger limit + reg hyst_low_limit_pass_a; // valid hysteresis range on passthrough low trigger limit + reg signed [DW:0] hyst_a_high_limit; + reg signed [DW:0] hyst_a_low_limit; + reg comp_high_b; // signal is over the limit + reg old_comp_high_b; // t + 1 version of comp_high_b + reg hyst_high_limit_pass_b; // valid hysteresis range on passthrough high trigger limit + reg hyst_low_limit_pass_b; // valid hysteresis range on passthrough low trigger limit + reg signed [DW:0] hyst_b_high_limit; + reg signed [DW:0] hyst_b_low_limit; + reg passthrough_high_a; // trigger when rising through the limit + reg passthrough_low_a; // trigger when fallingh thorugh the limit + reg passthrough_high_b; // trigger when rising through the limit + reg passthrough_low_b; // trigger when fallingh thorugh the limit + + reg trigger_pin_a; + reg trigger_pin_b; + reg [ 1:0] trigger_o_m = 1'd0; + + reg trig_o_hold_0 = 1'b0; + reg trig_o_hold_1 = 1'b0; + reg [19:0] trig_o_hold_cnt_0 = 20'd0; + reg [19:0] trig_o_hold_cnt_1 = 20'd0; + + reg trigger_adc_a; + reg trigger_adc_b; + + reg trigger_a; + reg trigger_b; + + reg trigger_out_mixed; + reg up_triggered; + reg up_triggered_d1; + reg up_triggered_d2; + + reg up_triggered_set; + reg up_triggered_reset; + reg up_triggered_reset_d1; + reg up_triggered_reset_d2; + + reg [31:0] trigger_delay_counter = 32'h0; + reg [31:0] trigger_holdoff_counter = 32'h0; + reg triggered; + reg trigger_out_m1; + reg trigger_out_m2; + + reg streaming_on; + reg trigger_out_hold; + reg trigger_out_ack; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + assign trigger_t = io_selection[1:0]; + + assign trigger_a_fall_edge = (trigger_a_d2 == 1'b0 && trigger_a_d3 == 1'b1) ? 1'b1: 1'b0; + assign trigger_a_rise_edge = (trigger_a_d2 == 1'b1 && trigger_a_d3 == 1'b0) ? 1'b1: 1'b0; + assign trigger_a_any_edge = trigger_a_rise_edge | trigger_a_fall_edge; + assign trigger_b_fall_edge = (trigger_b_d2 == 1'b0 && trigger_b_d3 == 1'b1) ? 1'b1: 1'b0; + assign trigger_b_rise_edge = (trigger_b_d2 == 1'b1 && trigger_b_d3 == 1'b0) ? 1'b1: 1'b0; + assign trigger_b_any_edge = trigger_b_rise_edge | trigger_b_fall_edge; + + assign data_a_cmp = data_a[DW:0]; + assign data_b_cmp = data_b[DW:0]; + assign limit_a_cmp = limit_a[DW:0]; + assign limit_b_cmp = limit_b[DW:0]; + + always @(*) begin + case(io_selection[4:2]) + 3'h0: trigger_o_m[0] = trigger_up_o_s[0]; + 3'h1: trigger_o_m[0] = trigger_i[0]; + 3'h2: trigger_o_m[0] = trigger_i[1]; + 3'h3: trigger_o_m[0] = trigger_out_mixed; + 3'h4: trigger_o_m[0] = trigger_in; + default: trigger_o_m[0] = trigger_up_o_s[0]; + endcase + case(io_selection[7:5]) + 3'h0: trigger_o_m[1] = trigger_up_o_s[1]; + 3'h1: trigger_o_m[1] = trigger_i[1]; + 3'h2: trigger_o_m[1] = trigger_i[0]; + 3'h3: trigger_o_m[1] = trigger_out_mixed; + 3'h4: trigger_o_m[1] = trigger_in; + default: trigger_o_m[1] = trigger_up_o_s[1]; + endcase + end + + // External trigger output hold 100000 clock cycles(1ms) on polarity change. + // All trigger signals that are to be outputted on the external trigger after a + // trigger out is acknowledged by the hold counter will be disregarded for 1ms. + // This was done to avoid noise created by high frequency switches on long + // wires. + + always @(posedge clk) begin + // trigger_o[0] hold start + if (trig_o_hold_cnt_0 != 20'd0) begin + trig_o_hold_cnt_0 <= trig_o_hold_cnt_0 - 20'd1; + end else if (trig_o_hold_0 != trigger_o_m[0]) begin + trig_o_hold_cnt_0 <= trigger_out_hold_pins; + trig_o_hold_0 <= trigger_o_m[0]; + end + + // trigger_o[1] hold start + if (trig_o_hold_cnt_1 != 20'd0) begin + trig_o_hold_cnt_1 <= trig_o_hold_cnt_1 - 20'd1; + end else if (trig_o_hold_1 != trigger_o_m[1]) begin + trig_o_hold_cnt_1 <= trigger_out_hold_pins; + trig_o_hold_1 <= trigger_o_m[1]; + end + + // hold + trigger_o[0] <= (trig_o_hold_cnt_0 == 'd0) ? trigger_o_m[0] : trig_o_hold_0; + trigger_o[1] <= (trig_o_hold_cnt_1 == 'd0) ? trigger_o_m[1] : trig_o_hold_1; + end + + // 1. keep data in sync with the trigger. The trigger bypasses the variable + // fifo. The data goes through and it is delayed with 4 clock cycles) + // 2. For non max sample rate of the ADC, the trigger signal that originates + // from an external source is stored until the valid acknowledges the trigger. + always @(posedge clk) begin + if (reset == 1'b1) begin + trigger_out_m1 <= 1'b0; + trigger_out_m2 <= 1'b0; + trigger_out_ack <= 1'b0; + trigger_out_hold <= 1'b0; + end else begin + if (data_out_valid == 1'b1) begin + trigger_out_m1 <= trigger_out_s | trigger_out_hold; + trigger_out_m2 <= trigger_out_m1; + trigger_out_ack <= trigger_out_hold; + end + if (~trigger_out_m1 & trigger_out_s & ~data_out_valid) begin + trigger_out_hold <= 1'b1; + end + if (trigger_out_ack) begin + trigger_out_hold <= 1'b0; + end + end + end + + assign data_out_valid = data_valid_a | data_valid_b; + + assign trigger_out_la = trigger_out_mixed; + assign trigger_out = trigger_out_m2; + + always @(posedge clk) begin + if (data_out_valid) begin + data_a_trig <= (embedded_trigger == 1'h0) ? {data_a[14],data_a[14:0]} : {trigger_out_s,data_a[14:0]}; + data_b_trig <= (embedded_trigger == 1'h0) ? {data_b[14],data_b[14:0]} : {trigger_out_s,data_b[14:0]}; + end + + data_valid_a_trig <= data_valid_a; + data_valid_b_trig <= data_valid_b; + end + + assign embedded_trigger = trigger_out_control[16]; + assign trigger_out_s = (trigger_delay == 32'h0) ? (trigger_out_holdoff | streaming_on) : + (trigger_out_delayed | streaming_on); + + assign trigger_out_delayed = (trigger_delay_counter == 32'h0) ? 1 : 0; + + // delay out trigger + always @(posedge clk) begin + if (trigger_delay == 0) begin + trigger_delay_counter <= 32'h0; + end else begin + if (data_valid_a == 1'b1) begin + triggered <= trigger_out_holdoff | triggered; + if (trigger_delay_counter == 0) begin + trigger_delay_counter <= trigger_delay; + triggered <= 1'b0; + end else begin + if(triggered == 1'b1 || trigger_out_holdoff == 1'b1) begin + trigger_delay_counter <= trigger_delay_counter - 1; + end + end + end + end + end + + always @(posedge clk) begin + if (trigger_delay == 0) begin + if (streaming == 1'b1 && data_valid_a == 1'b1 && trigger_out_holdoff == 1'b1) begin + streaming_on <= 1'b1; + end else if (streaming == 1'b0) begin + streaming_on <= 1'b0; + end + end else begin + if (streaming == 1'b1 && data_valid_a == 1'b1 && trigger_out_delayed == 1'b1) begin + streaming_on <= 1'b1; + end else if (streaming == 1'b0) begin + streaming_on <= 1'b0; + end + end + end + + // hold off trigger + assign trigger_out_holdoff = (trigger_holdoff_counter != 0) ? 0 : trigger_out_mixed; + + always @(posedge clk) begin + if (reset == 1'b1) begin + trigger_holdoff_counter <= 0; + end else begin + if (trigger_holdoff_counter != 0) begin + trigger_holdoff_counter <= trigger_holdoff_counter - 1'b1; + end else if (trigger_out_holdoff == 1'b1) begin + trigger_holdoff_counter <= trigger_holdoff; + end else begin + trigger_holdoff_counter <= trigger_holdoff_counter; + end + end + end + + always @(posedge clk) begin + if (data_valid_a == 1'b1 && trigger_out_holdoff == 1'b1) begin + up_triggered_set <= 1'b1; + end else if (up_triggered_reset == 1'b1) begin + up_triggered_set <= 1'b0; + end + up_triggered_reset_d1 <= up_triggered; + up_triggered_reset_d2 <= up_triggered_reset_d1; + up_triggered_reset <= up_triggered_reset_d2; + end + + always @(posedge up_clk) begin + up_triggered_d1 <= up_triggered_set; + up_triggered_d2 <= up_triggered_d1; + up_triggered <= up_triggered_d2; + end + + always @(*) begin + case(trigger_l_mix_a) + 4'h0: trigger_a = 1'b1; + 4'h1: trigger_a = trigger_pin_a; + 4'h2: trigger_a = trigger_adc_a; + 4'h4: trigger_a = trigger_pin_a | trigger_adc_a ; + 4'h5: trigger_a = trigger_pin_a & trigger_adc_a ; + 4'h6: trigger_a = trigger_pin_a ^ trigger_adc_a ; + 4'h7: trigger_a = !(trigger_pin_a | trigger_adc_a) ; + 4'h8: trigger_a = !(trigger_pin_a & trigger_adc_a) ; + 4'h9: trigger_a = !(trigger_pin_a ^ trigger_adc_a) ; + default: trigger_a = 1'b1; + endcase + end + + always @(*) begin + case(trigger_l_mix_b) + 4'h0: trigger_b = 1'b1; + 4'h1: trigger_b = trigger_pin_b; + 4'h2: trigger_b = trigger_adc_b; + 4'h4: trigger_b = trigger_pin_b | trigger_adc_b ; + 4'h5: trigger_b = trigger_pin_b & trigger_adc_b ; + 4'h6: trigger_b = trigger_pin_b ^ trigger_adc_b ; + 4'h7: trigger_b = !(trigger_pin_b | trigger_adc_b) ; + 4'h8: trigger_b = !(trigger_pin_b & trigger_adc_b) ; + 4'h9: trigger_b = !(trigger_pin_b ^ trigger_adc_b) ; + default: trigger_b = 1'b1; + endcase + end + + always @(*) begin + case(function_a) + 2'h0: trigger_adc_a = comp_low_a_s; + 2'h1: trigger_adc_a = comp_high_a; + 2'h2: trigger_adc_a = passthrough_high_a; + 2'h3: trigger_adc_a = passthrough_low_a; + default: trigger_adc_a = comp_low_a_s; + endcase + end + + always @(*) begin + case(function_b) + 2'h0: trigger_adc_b = comp_low_b_s; + 2'h1: trigger_adc_b = comp_high_b; + 2'h2: trigger_adc_b = passthrough_high_b; + 2'h3: trigger_adc_b = passthrough_low_b; + default: trigger_adc_b = comp_low_b_s; + endcase + end + + always @(posedge clk) begin + trigger_a_d1 <= trigger_i[0]; + trigger_a_d2 <= trigger_a_d1; + trigger_a_d3 <= trigger_a_d2; + trigger_b_d1 <= trigger_i[1]; + trigger_b_d2 <= trigger_b_d1; + trigger_b_d3 <= trigger_b_d2; + end + + always @(*) begin + trigger_pin_a = ((!trigger_a_d3 & low_level[0]) | + (trigger_a_d3 & high_level[0]) | + (trigger_a_fall_edge & fall_edge[0]) | + (trigger_a_rise_edge & rise_edge[0]) | + (trigger_a_any_edge & any_edge[0])); + end + + always @(*) begin + trigger_pin_b = ((!trigger_b_d3 & low_level[1]) | + (trigger_b_d3 & high_level[1]) | + (trigger_b_fall_edge & fall_edge[1]) | + (trigger_b_rise_edge & rise_edge[1]) | + (trigger_b_any_edge & any_edge[1])); + end + + always @(*) begin + case(trigger_out_control[3:0]) + 4'h0: trigger_out_mixed = trigger_a; + 4'h1: trigger_out_mixed = trigger_b; + 4'h2: trigger_out_mixed = trigger_a | trigger_b; + 4'h3: trigger_out_mixed = trigger_a & trigger_b; + 4'h4: trigger_out_mixed = trigger_a ^ trigger_b; + 4'h5: trigger_out_mixed = trigger_in; + 4'h6: trigger_out_mixed = trigger_a | trigger_in; + 4'h7: trigger_out_mixed = trigger_b | trigger_in; + 4'h8: trigger_out_mixed = trigger_a | trigger_b | trigger_in; + 4'hf: trigger_out_mixed = 1'b0; // trigger disable + default: trigger_out_mixed = 1'b0; + endcase + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + comp_high_a <= 1'b0; + old_comp_high_a <= 1'b0; + passthrough_high_a <= 1'b0; + passthrough_low_a <= 1'b0; + hyst_a_high_limit <= {DW{1'b0}}; + hyst_a_low_limit <= {DW{1'b0}}; + hyst_high_limit_pass_a <= 1'b0; + hyst_low_limit_pass_a <= 1'b0; + end else begin + if (data_valid_a == 1'b1) begin + hyst_a_high_limit <= limit_a_cmp + hysteresis_a[DW:0]; + hyst_a_low_limit <= limit_a_cmp - hysteresis_a[DW:0]; + + if (data_a_cmp >= limit_a_cmp) begin + comp_high_a <= 1'b1; + end else begin + comp_high_a <= 1'b0; + end + + if (data_a_cmp > hyst_a_high_limit) begin + hyst_low_limit_pass_a <= 1'b1; + end else begin + hyst_low_limit_pass_a <= (passthrough_low_a) ? 1'b0 : hyst_low_limit_pass_a; + end + if (data_a_cmp < hyst_a_low_limit) begin + hyst_high_limit_pass_a <= 1'b1; + end else begin + hyst_high_limit_pass_a <= passthrough_high_a ? 1'b0 : hyst_high_limit_pass_a; + end + + old_comp_high_a <= comp_high_a; + passthrough_high_a <= !old_comp_high_a & comp_high_a & hyst_high_limit_pass_a; + passthrough_low_a <= old_comp_high_a & !comp_high_a & hyst_low_limit_pass_a; + end + end + end + + assign comp_low_a_s = !comp_high_a; + + always @(posedge clk) begin + if (reset == 1'b1) begin + comp_high_b <= 1'b0; + old_comp_high_b <= 1'b0; + passthrough_high_b <= 1'b0; + passthrough_low_b <= 1'b0; + hyst_b_high_limit <= {DW{1'b0}}; + hyst_b_low_limit <= {DW{1'b0}}; + hyst_high_limit_pass_b <= 1'b0; + hyst_low_limit_pass_b <= 1'b0; + end else begin + if (data_valid_b == 1'b1) begin + hyst_b_high_limit <= limit_b_cmp + hysteresis_b[DW:0]; + hyst_b_low_limit <= limit_b_cmp - hysteresis_b[DW:0]; + + if (data_b_cmp >= limit_b_cmp) begin + comp_high_b <= 1'b1; + end else begin + comp_high_b <= 1'b0; + end + + if (data_b_cmp > hyst_b_high_limit) begin + hyst_low_limit_pass_b <= 1'b1; + end else begin + hyst_low_limit_pass_b <= (passthrough_low_b) ? 1'b0 : hyst_low_limit_pass_b; + end + if (data_b_cmp < hyst_b_low_limit) begin + hyst_high_limit_pass_b <= 1'b1; + end else begin + hyst_high_limit_pass_b <= passthrough_high_b ? 1'b0 : hyst_high_limit_pass_b; + end + + old_comp_high_b <= comp_high_b; + passthrough_high_b <= !old_comp_high_b & comp_high_b & hyst_high_limit_pass_b; + passthrough_low_b <= old_comp_high_b & !comp_high_b & hyst_low_limit_pass_b; + end + end + end + + assign comp_low_b_s = !comp_high_b; + + axi_adc_trigger_reg adc_trigger_registers ( + .clk(clk), + + .io_selection(io_selection), + .trigger_o(trigger_up_o_s), + .triggered(up_triggered), + + .low_level(low_level), + .high_level(high_level), + .any_edge(any_edge), + .rise_edge(rise_edge), + .fall_edge(fall_edge), + + .limit_a(limit_a), + .function_a(function_a), + .hysteresis_a(hysteresis_a), + .trigger_l_mix_a(trigger_l_mix_a), + + .limit_b(limit_b), + .function_b(function_b), + .hysteresis_b(hysteresis_b), + .trigger_l_mix_b(trigger_l_mix_b), + + .trigger_out_control(trigger_out_control), + .trigger_delay(trigger_delay), + .trigger_holdoff (trigger_holdoff), + .trigger_out_hold_pins (trigger_out_hold_pins), + + .fifo_depth(fifo_depth), + + .streaming(streaming), + + // bus interface + + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_wack(up_wack), + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata), + .up_rack(up_rack)); + + up_axi #( + .AXI_ADDRESS_WIDTH(7) + ) i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_adc_trigger/axi_adc_trigger.xpr b/adi_library/axi_adc_trigger/axi_adc_trigger.xpr new file mode 100644 index 00000000..dafb3285 --- /dev/null +++ b/adi_library/axi_adc_trigger/axi_adc_trigger.xpr @@ -0,0 +1,432 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_adc_trigger/axi_adc_trigger_constr.xdc b/adi_library/axi_adc_trigger/axi_adc_trigger_constr.xdc new file mode 100644 index 00000000..678a4ac5 --- /dev/null +++ b/adi_library/axi_adc_trigger/axi_adc_trigger_constr.xdc @@ -0,0 +1,16 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_a_d*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_b_d*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_d*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_reset_d*}] + +set_false_path -to [get_cells -hier -filter {name =~ *trigger_a_d1_reg* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *trigger_b_d1_reg* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_d1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_reset_d1* && IS_SEQUENTIAL}] + diff --git a/adi_library/axi_adc_trigger/axi_adc_trigger_ip.tcl b/adi_library/axi_adc_trigger/axi_adc_trigger_ip.tcl new file mode 100644 index 00000000..b8404c2f --- /dev/null +++ b/adi_library/axi_adc_trigger/axi_adc_trigger_ip.tcl @@ -0,0 +1,27 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_adc_trigger +adi_ip_files axi_adc_trigger [list \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "axi_adc_trigger_constr.xdc" \ + "axi_adc_trigger_reg.v" \ + "axi_adc_trigger.v" ] + +adi_ip_properties axi_adc_trigger + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_adc_trigger} [ipx::current_core] + +ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/axi_adc_trigger/axi_adc_trigger_reg.v b/adi_library/axi_adc_trigger/axi_adc_trigger_reg.v new file mode 100644 index 00000000..a6fae39b --- /dev/null +++ b/adi_library/axi_adc_trigger/axi_adc_trigger_reg.v @@ -0,0 +1,286 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adc_trigger_reg ( + + input clk, + + output [ 7:0] io_selection, + output [ 1:0] trigger_o, + input triggered, + + output [ 1:0] low_level, + output [ 1:0] high_level, + output [ 1:0] any_edge, + output [ 1:0] rise_edge, + output [ 1:0] fall_edge, + + output [15:0] limit_a, + output [ 1:0] function_a, + output [31:0] hysteresis_a, + output [ 3:0] trigger_l_mix_a, + + output [15:0] limit_b, + output [ 1:0] function_b, + output [31:0] hysteresis_b, + output [ 3:0] trigger_l_mix_b, + + output [16:0] trigger_out_control, + output [31:0] fifo_depth, + output [31:0] trigger_delay, + output [31:0] trigger_holdoff, + output [19:0] trigger_out_hold_pins, + + output streaming, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [ 4:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [ 4:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack +); + + localparam DEFAULT_OUT_HOLD = 100000; // 1ms + + // internal signals + + wire [ 9:0] config_trigger_i; + + // internal registers + + reg [31:0] up_version = 32'h00030000; + reg [31:0] up_scratch = 32'h0; + reg [ 7:0] up_io_selection = 8'h0; + reg [ 1:0] up_trigger_o = 2'h0; + reg [ 9:0] up_config_trigger_i = 10'h0; + reg [15:0] up_limit_a = 16'h0; + reg [ 1:0] up_function_a = 2'h0; + reg [31:0] up_hysteresis_a = 32'h0; + reg [ 3:0] up_trigger_l_mix_a = 4'h0; + reg [15:0] up_limit_b = 16'h0; + reg [ 1:0] up_function_b = 2'h0; + reg [31:0] up_hysteresis_b = 32'h0; + reg [ 3:0] up_trigger_l_mix_b = 4'h0; + reg [16:0] up_trigger_out_control = 17'h0; + reg [31:0] up_fifo_depth = 32'h0; + reg [31:0] up_trigger_delay = 32'h0; + reg [31:0] up_trigger_holdoff = 32'h0; + reg [19:0] up_trigger_out_hold_pins = DEFAULT_OUT_HOLD; + reg up_triggered = 1'h0; + reg up_streaming = 1'h0; + + assign low_level = config_trigger_i[1:0]; + assign high_level = config_trigger_i[3:2]; + assign any_edge = config_trigger_i[5:4]; + assign rise_edge = config_trigger_i[7:6]; + assign fall_edge = config_trigger_i[9:8]; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_scratch <= 'd0; + up_trigger_o <= 'd0; + up_io_selection <= 'd1; + up_config_trigger_i <= 'd0; + up_limit_a <= 'd0; + up_function_a <= 'd0; + up_hysteresis_a <= 'd0; + up_limit_b <= 'd0; + up_function_b <= 'd0; + up_hysteresis_b <= 'd0; + up_fifo_depth <= 'd0; + up_trigger_delay <= 'd0; + up_trigger_l_mix_a <= 'd0; + up_trigger_l_mix_b <= 'd0; + up_trigger_out_control <= 'd0; + up_triggered <= 1'd0; + up_streaming <= 1'd0; + up_trigger_holdoff <= 32'h0; + up_trigger_out_hold_pins <= DEFAULT_OUT_HOLD; + end else begin + up_wack <= up_wreq; + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin + up_scratch <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h2)) begin + up_trigger_o <= up_wdata[1:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h3)) begin + up_io_selection <= up_wdata[7:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h4)) begin + up_config_trigger_i <= up_wdata[9:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h5)) begin + up_limit_a <= up_wdata[15:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h6)) begin + up_function_a <= up_wdata[1:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h7)) begin + up_hysteresis_a <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h8)) begin + up_trigger_l_mix_a <= up_wdata[3:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h9)) begin + up_limit_b <= up_wdata[15:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'ha)) begin + up_function_b <= up_wdata[1:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hb)) begin + up_hysteresis_b <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hc)) begin + up_trigger_l_mix_b <= up_wdata[3:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hd)) begin + up_trigger_out_control <= up_wdata[16:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'he)) begin + up_fifo_depth <= up_wdata; + end + if (triggered == 1'b1) begin + up_triggered <= 1'b1; + end else if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hf)) begin + up_triggered <= up_triggered & ~up_wdata[0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h10)) begin + up_trigger_delay <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h11)) begin + up_streaming <= up_wdata[0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h12)) begin + up_trigger_holdoff <= up_wdata[31:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h13)) begin + up_trigger_out_hold_pins <= up_wdata[19:0]; + end + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq; + if (up_rreq == 1'b1) begin + case (up_raddr[4:0]) + 5'h0: up_rdata <= up_version; + 5'h1: up_rdata <= up_scratch; + 5'h2: up_rdata <= {30'h0,up_trigger_o}; + 5'h3: up_rdata <= {24'h0,up_io_selection}; + 5'h4: up_rdata <= {22'h0,up_config_trigger_i}; + 5'h5: up_rdata <= {16'h0,up_limit_a}; + 5'h6: up_rdata <= {30'h0,up_function_a}; + 5'h7: up_rdata <= up_hysteresis_a; + 5'h8: up_rdata <= {28'h0,up_trigger_l_mix_a}; + 5'h9: up_rdata <= {16'h0,up_limit_b}; + 5'ha: up_rdata <= {30'h0,up_function_b}; + 5'hb: up_rdata <= up_hysteresis_b; + 5'hc: up_rdata <= {28'h0,up_trigger_l_mix_b}; + 5'hd: up_rdata <= {15'h0,up_trigger_out_control}; + 5'he: up_rdata <= up_fifo_depth; + 5'hf: up_rdata <= {31'h0,up_triggered}; + 5'h10: up_rdata <= up_trigger_delay; + 5'h11: up_rdata <= {31'h0,up_streaming}; + 5'h12: up_rdata <= up_trigger_holdoff; + 5'h13: up_rdata <= {12'h0,up_trigger_out_hold_pins}; + default: up_rdata <= 0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + up_xfer_cntrl #( + .DATA_WIDTH(262) + ) i_xfer_cntrl ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_cntrl ({ up_streaming, // 1 + up_trigger_o, // 2 + up_io_selection, // 8 + up_config_trigger_i, // 10 + up_limit_a, // 16 + up_function_a, // 2 + up_hysteresis_a, // 32 + up_trigger_l_mix_a, // 4 + up_limit_b, // 16 + up_function_b, // 2 + up_hysteresis_b, // 32 + up_trigger_l_mix_b, // 4 + up_trigger_out_control, // 17 + up_fifo_depth, // 32 + up_trigger_holdoff, // 32 + up_trigger_out_hold_pins, // 20 + up_trigger_delay}), // 32 + .up_xfer_done (), + .d_rst (1'b0), + .d_clk (clk), + .d_data_cntrl ({ streaming, // 1 + trigger_o, // 2 + io_selection, // 8 + config_trigger_i, // 10 + limit_a, // 16 + function_a, // 2 + hysteresis_a, // 32 + trigger_l_mix_a, // 4 + limit_b, // 16 + function_b, // 2 + hysteresis_b, // 32 + trigger_l_mix_b, // 4 + trigger_out_control, // 17 + fifo_depth, // 32 + trigger_holdoff, // 32 + trigger_out_hold_pins, // 20 + trigger_delay})); // 32 + +endmodule diff --git a/adi_library/axi_adc_trigger/component.xml b/adi_library/axi_adc_trigger/component.xml new file mode 100644 index 00000000..fcdb4ad8 --- /dev/null +++ b/adi_library/axi_adc_trigger/component.xml @@ -0,0 +1,1057 @@ + + + analog.com + user + axi_adc_trigger + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + clk + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_RESET + reset + + + + + reset + + + + + + + RST + + + reset + + + + + + + + s_axi + + axi_lite + 0 + 128 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_adc_trigger + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + d3f469cd + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_adc_trigger + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 1b9bccd7 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 8991825b + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + reset + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + trigger_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + trigger_i + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + trigger_o + + out + + 1 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + trigger_t + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_a + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_b + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_valid_a + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_valid_b + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_a_trig + + out + + 15 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_b_trig + + out + + 15 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_valid_a_trig + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_valid_b_trig + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + trigger_out + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + trigger_out_la + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + fifo_depth + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 6 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 6 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + SIGN_BITS + Sign Bits + 2 + + + OUT_PIN_HOLD_N + Out Pin Hold N + 100000 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + axi_adc_trigger_constr.xdc + xdc + + + axi_adc_trigger_reg.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + axi_adc_trigger.v + verilogSource + CHECKSUM_89ec07dc + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + axi_adc_trigger_reg.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + axi_adc_trigger.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_adc_trigger_v1_0.tcl + tclSource + CHECKSUM_8991825b + XGUI_VERSION_2 + + + + axi_adc_trigger_v1_0 + + + SIGN_BITS + Sign Bits + 2 + + + OUT_PIN_HOLD_N + Out Pin Hold N + 100000 + + + Component_Name + axi_adc_trigger_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_adc_trigger_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_adc_trigger + 1 + 2024-01-14T03:44:26Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_adc_trigger/xgui/axi_adc_trigger_v1_0.tcl b/adi_library/axi_adc_trigger/xgui/axi_adc_trigger_v1_0.tcl new file mode 100644 index 00000000..19e959f5 --- /dev/null +++ b/adi_library/axi_adc_trigger/xgui/axi_adc_trigger_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "OUT_PIN_HOLD_N" -parent ${Page_0} + ipgui::add_param $IPINST -name "SIGN_BITS" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.OUT_PIN_HOLD_N { PARAM_VALUE.OUT_PIN_HOLD_N } { + # Procedure called to update OUT_PIN_HOLD_N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_PIN_HOLD_N { PARAM_VALUE.OUT_PIN_HOLD_N } { + # Procedure called to validate OUT_PIN_HOLD_N + return true +} + +proc update_PARAM_VALUE.SIGN_BITS { PARAM_VALUE.SIGN_BITS } { + # Procedure called to update SIGN_BITS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SIGN_BITS { PARAM_VALUE.SIGN_BITS } { + # Procedure called to validate SIGN_BITS + return true +} + + +proc update_MODELPARAM_VALUE.SIGN_BITS { MODELPARAM_VALUE.SIGN_BITS PARAM_VALUE.SIGN_BITS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SIGN_BITS}] ${MODELPARAM_VALUE.SIGN_BITS} +} + +proc update_MODELPARAM_VALUE.OUT_PIN_HOLD_N { MODELPARAM_VALUE.OUT_PIN_HOLD_N PARAM_VALUE.OUT_PIN_HOLD_N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_PIN_HOLD_N}] ${MODELPARAM_VALUE.OUT_PIN_HOLD_N} +} + diff --git a/adi_library/axi_adrv9001/Makefile b/adi_library/axi_adrv9001/Makefile new file mode 100644 index 00000000..3ec90399 --- /dev/null +++ b/adi_library/axi_adrv9001/Makefile @@ -0,0 +1,72 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_adrv9001 + +GENERIC_DEPS += ../common/ad_addsub.v +GENERIC_DEPS += ../common/ad_datafmt.v +GENERIC_DEPS += ../common/ad_dds.v +GENERIC_DEPS += ../common/ad_dds_1.v +GENERIC_DEPS += ../common/ad_dds_2.v +GENERIC_DEPS += ../common/ad_dds_cordic_pipe.v +GENERIC_DEPS += ../common/ad_dds_sine.v +GENERIC_DEPS += ../common/ad_dds_sine_cordic.v +GENERIC_DEPS += ../common/ad_pngen.v +GENERIC_DEPS += ../common/ad_pnmon.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/ad_tdd_control.v +GENERIC_DEPS += ../common/up_adc_channel.v +GENERIC_DEPS += ../common/up_adc_common.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_dac_channel.v +GENERIC_DEPS += ../common/up_dac_common.v +GENERIC_DEPS += ../common/up_delay_cntrl.v +GENERIC_DEPS += ../common/up_tdd_cntrl.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += adrv9001_aligner4.v +GENERIC_DEPS += adrv9001_aligner8.v +GENERIC_DEPS += adrv9001_pack.v +GENERIC_DEPS += adrv9001_rx_link.v +GENERIC_DEPS += adrv9001_tx_link.v +GENERIC_DEPS += axi_adrv9001.v +GENERIC_DEPS += axi_adrv9001_core.v +GENERIC_DEPS += axi_adrv9001_if.v +GENERIC_DEPS += axi_adrv9001_rx.v +GENERIC_DEPS += axi_adrv9001_rx_channel.v +GENERIC_DEPS += axi_adrv9001_tdd.v +GENERIC_DEPS += axi_adrv9001_tx.v +GENERIC_DEPS += axi_adrv9001_tx_channel.v + +XILINX_DEPS += ../xilinx/common/ad_mmcm_drp.v +XILINX_DEPS += ../xilinx/common/ad_mul.v +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/ad_serdes_clk.v +XILINX_DEPS += ../xilinx/common/ad_serdes_in.v +XILINX_DEPS += ../xilinx/common/ad_serdes_out.v +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += adrv9001_rx.v +XILINX_DEPS += adrv9001_tx.v +XILINX_DEPS += axi_adrv9001_constr.xdc +XILINX_DEPS += axi_adrv9001_ip.tcl + +XILINX_LIB_DEPS += util_cdc + +INTEL_DEPS += ../intel/common/ad_mul.v +INTEL_DEPS += ../intel/common/up_clock_mon_constr.sdc +INTEL_DEPS += ../intel/common/up_rst_constr.sdc +INTEL_DEPS += ../intel/common/up_xfer_cntrl_constr.sdc +INTEL_DEPS += ../intel/common/up_xfer_status_constr.sdc +INTEL_DEPS += ../util_cdc/sync_bits.v +INTEL_DEPS += axi_adrv9001_constr.sdc +INTEL_DEPS += axi_adrv9001_hw.tcl +INTEL_DEPS += intel/adrv9001_rx.v +INTEL_DEPS += intel/adrv9001_tx.v + +include ../scripts/library.mk diff --git a/adi_library/axi_adrv9001/adrv9001_aligner4.v b/adi_library/axi_adrv9001/adrv9001_aligner4.v new file mode 100644 index 00000000..3d43f57a --- /dev/null +++ b/adi_library/axi_adrv9001/adrv9001_aligner4.v @@ -0,0 +1,87 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module adrv9001_aligner4 ( + input clk, + input rst, + input [3:0] idata, + input ivalid, + input [3:0] strobe, + output reg [3:0] odata, + output ovalid +); + + reg [3:0] idata_d = 'b0; + reg ivalid_d = 'b0; + + always @(posedge clk) begin + if (rst) begin + idata_d <= 'h0; + end else if (ivalid) begin + idata_d <= idata; + end + ivalid_d <= ivalid; + end + + reg [1:0] phase = 'h0; + always @(posedge clk) begin + if (rst) begin + phase <= 0; + end else if (ivalid) begin + if ((strobe != 'b1111) && (strobe != 'b0000)) begin + casex (strobe) + 'b1xxx : phase <= 0; + 'b01xx : phase <= 1; + 'b001x : phase <= 2; + 'b0001 : phase <= 3; + default : phase <= phase; + endcase + end + end + end + + always @(posedge clk) begin + case (phase) + 0 : odata <= idata_d; + 1 : odata <= {idata_d[2:0],idata[3:3]}; + 2 : odata <= {idata_d[1:0],idata[3:2]}; + 3 : odata <= {idata_d[0:0],idata[3:1]}; + endcase + end + assign ovalid = ivalid_d; + +endmodule diff --git a/adi_library/axi_adrv9001/adrv9001_aligner8.v b/adi_library/axi_adrv9001/adrv9001_aligner8.v new file mode 100644 index 00000000..e4f41524 --- /dev/null +++ b/adi_library/axi_adrv9001/adrv9001_aligner8.v @@ -0,0 +1,95 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module adrv9001_aligner8 ( + input clk, + input rst, + input [7:0] idata, + input ivalid, + input [7:0] strobe, + output reg [7:0] odata, + output ovalid +); + + reg [7:0] idata_d = 'b0; + reg ivalid_d = 'b0; + + always @(posedge clk) begin + if (rst) begin + idata_d <= 'h0; + end else if (ivalid) begin + idata_d <= idata; + end + ivalid_d <= ivalid; + end + + reg [2:0] phase = 'h0; + always @(posedge clk) begin + if (rst) begin + phase <= 0; + end if (ivalid) begin + if ((strobe != 'b1111_1111) && (strobe != 'b0000_0000)) begin + casex (strobe) + 'b1xxx_xxxx : phase <= 0; + 'b01xx_xxxx : phase <= 1; + 'b001x_xxxx : phase <= 2; + 'b0001_xxxx : phase <= 3; + 'b0000_1xxx : phase <= 4; + 'b0000_01xx : phase <= 5; + 'b0000_001x : phase <= 6; + 'b0000_0001 : phase <= 7; + default : phase <= phase; + endcase + end + end + end + + always @(posedge clk) begin + case (phase) + 0 : odata <= idata_d; + 1 : odata <= {idata_d[6:0],idata[7:7]}; + 2 : odata <= {idata_d[5:0],idata[7:6]}; + 3 : odata <= {idata_d[4:0],idata[7:5]}; + 4 : odata <= {idata_d[3:0],idata[7:4]}; + 5 : odata <= {idata_d[2:0],idata[7:3]}; + 6 : odata <= {idata_d[1:0],idata[7:2]}; + 7 : odata <= {idata_d[0:0],idata[7:1]}; + endcase + end + assign ovalid = ivalid_d; + +endmodule diff --git a/adi_library/axi_adrv9001/adrv9001_pack.v b/adi_library/axi_adrv9001/adrv9001_pack.v new file mode 100644 index 00000000..659c5e8e --- /dev/null +++ b/adi_library/axi_adrv9001/adrv9001_pack.v @@ -0,0 +1,89 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +// +// Pack two input beats into one and align it based on start of frame +// +// Frame size 2 beats: +// Temporal ordering of input: +// idata : MS Beat, LS Beat, MS Beat, LS Beat, ... +// sof : 1, 0, 1, 0, ... +// Format of output beats: {MS Beat, LS Beat} +// +// Frame size 4 beats: +// Temporal ordering of input: +// idata : MS Beat, LS Beat, MS Beat, LS Beat, MS Beat, LS Beat, ... +// sof : 1, 0, 0, 0, 1, 0, ... + +module adrv9001_pack #( + parameter WIDTH = 8 +) ( + input clk, // Input clock + input rst, + input sof, // Start of frame indicator marking the MS Beat + input [WIDTH-1:0] idata, // Input data beat + input ivalid, // Input data qualifier + output reg [WIDTH*2-1:0] odata, // Output data beat + output reg ovalid, // Output data qualifier + output reg osof // Output Start of frame indicator +); + + reg [WIDTH-1:0] idata_d = {WIDTH{1'b0}}; + always @(posedge clk) begin + if (ivalid) begin + idata_d <= idata; + end + end + + // Single clock mode: + reg [6:0] sof_d = 7'b000; + // Use sof_d[2] for frame size of 4 beats + // Use sof_d[4,6] for frame size of 8 beats + always @(posedge clk) begin + if (rst) begin + sof_d <= 7'b0; + end else if (ivalid) begin + sof_d <= {sof_d[5:0],sof}; + end + if (ivalid &(sof_d[0] | sof_d[2] | sof_d[4] | sof_d[6])) begin + odata <= {idata_d,idata}; + end + ovalid <= ivalid & (sof_d[0] | sof_d[2] | sof_d[4] | sof_d[6]); + osof <= ivalid & sof_d[0]; + end + +endmodule diff --git a/adi_library/axi_adrv9001/adrv9001_rx.v b/adi_library/axi_adrv9001/adrv9001_rx.v new file mode 100644 index 00000000..7f9dc3f1 --- /dev/null +++ b/adi_library/axi_adrv9001/adrv9001_rx.v @@ -0,0 +1,277 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module adrv9001_rx #( + parameter CMOS_LVDS_N = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter NUM_LANES = 3, + parameter DRP_WIDTH = 5, + parameter IODELAY_ENABLE = 1, + parameter IODELAY_CTRL = 0, + parameter USE_BUFG = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group" +) ( + + // device interface + input rx_dclk_in_n_NC, + input rx_dclk_in_p_dclk_in, + input rx_idata_in_n_idata0, + input rx_idata_in_p_idata1, + input rx_qdata_in_n_qdata2, + input rx_qdata_in_p_qdata3, + input rx_strobe_in_n_NC, + input rx_strobe_in_p_strobe_in, + + // internal reset and clocks + input adc_rst, + output adc_clk, + output adc_clk_div, + output [7:0] adc_data_0, + output [7:0] adc_data_1, + output [7:0] adc_data_2, + output [7:0] adc_data_3, + output [7:0] adc_data_strobe, + output adc_valid, + + output [31:0] adc_clk_ratio, + + // delay interface (for IDELAY macros) + input up_clk, + input [NUM_LANES-1:0] up_adc_dld, + input [DRP_WIDTH*NUM_LANES-1:0] up_adc_dwdata, + output [DRP_WIDTH*NUM_LANES-1:0] up_adc_drdata, + input delay_clk, + input delay_rst, + output delay_locked, + + input mssi_sync, + output ssi_sync_out, + input ssi_sync_in, + output ssi_rst +); + + // Use always DDR mode + localparam DDR_OR_SDR_N = 1; + + localparam SEVEN_SERIES = 1; + localparam ULTRASCALE = 2; + localparam ULTRASCALE_PLUS = 3; + + // internal wire + wire clk_in_s; + wire [NUM_LANES-1:0] serdes_in_p; + wire [NUM_LANES-1:0] serdes_in_n; + wire [NUM_LANES-1:0] data_s0; + wire [NUM_LANES-1:0] data_s1; + wire [NUM_LANES-1:0] data_s2; + wire [NUM_LANES-1:0] data_s3; + wire [NUM_LANES-1:0] data_s4; + wire [NUM_LANES-1:0] data_s5; + wire [NUM_LANES-1:0] data_s6; + wire [NUM_LANES-1:0] data_s7; + wire adc_clk_in_fast; + + // internal registers + + // data interface + ad_serdes_in #( + .CMOS_LVDS_N (CMOS_LVDS_N), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IODELAY_CTRL (IODELAY_CTRL), + .IODELAY_ENABLE (IODELAY_ENABLE), + .IODELAY_GROUP (IO_DELAY_GROUP), + .DDR_OR_SDR_N (DDR_OR_SDR_N), + .DATA_WIDTH (NUM_LANES), + .DRP_WIDTH (DRP_WIDTH), + .SERDES_FACTOR (8) + ) i_serdes ( + .rst (adc_rst|ssi_rst), + .clk (adc_clk_in_fast), + .div_clk (adc_clk_div), + .data_s0 (data_s0), + .data_s1 (data_s1), + .data_s2 (data_s2), + .data_s3 (data_s3), + .data_s4 (data_s4), + .data_s5 (data_s5), + .data_s6 (data_s6), + .data_s7 (data_s7), + .data_in_p (serdes_in_p), + .data_in_n (serdes_in_n), + .up_clk (up_clk), + .up_dld (up_adc_dld), + .up_dwdata (up_adc_dwdata), + .up_drdata (up_adc_drdata), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked)); + + generate + if (CMOS_LVDS_N == 0) begin + + IBUFGDS i_clk_in_ibuf ( + .I (rx_dclk_in_p_dclk_in), + .IB (rx_dclk_in_n_NC), + .O (clk_in_s)); + + assign {adc_data_strobe[0],adc_data_1[0],adc_data_0[0]} = data_s0; + assign {adc_data_strobe[1],adc_data_1[1],adc_data_0[1]} = data_s1; + assign {adc_data_strobe[2],adc_data_1[2],adc_data_0[2]} = data_s2; + assign {adc_data_strobe[3],adc_data_1[3],adc_data_0[3]} = data_s3; + assign {adc_data_strobe[4],adc_data_1[4],adc_data_0[4]} = data_s4; + assign {adc_data_strobe[5],adc_data_1[5],adc_data_0[5]} = data_s5; + assign {adc_data_strobe[6],adc_data_1[6],adc_data_0[6]} = data_s6; + assign {adc_data_strobe[7],adc_data_1[7],adc_data_0[7]} = data_s7; + + assign serdes_in_p = {rx_strobe_in_p_strobe_in, + rx_qdata_in_p_qdata3, + rx_idata_in_p_idata1}; + assign serdes_in_n = {rx_strobe_in_n_NC, + rx_qdata_in_n_qdata2, + rx_idata_in_n_idata0}; + + end else begin + + IBUF i_clk_in_ibuf ( + .I (rx_dclk_in_p_dclk_in), + .O (clk_in_s)); + + assign {adc_data_strobe[0],adc_data_3[0],adc_data_2[0],adc_data_1[0],adc_data_0[0]} = data_s0; + assign {adc_data_strobe[1],adc_data_3[1],adc_data_2[1],adc_data_1[1],adc_data_0[1]} = data_s1; + assign {adc_data_strobe[2],adc_data_3[2],adc_data_2[2],adc_data_1[2],adc_data_0[2]} = data_s2; + assign {adc_data_strobe[3],adc_data_3[3],adc_data_2[3],adc_data_1[3],adc_data_0[3]} = data_s3; + assign {adc_data_strobe[4],adc_data_3[4],adc_data_2[4],adc_data_1[4],adc_data_0[4]} = data_s4; + assign {adc_data_strobe[5],adc_data_3[5],adc_data_2[5],adc_data_1[5],adc_data_0[5]} = data_s5; + assign {adc_data_strobe[6],adc_data_3[6],adc_data_2[6],adc_data_1[6],adc_data_0[6]} = data_s6; + assign {adc_data_strobe[7],adc_data_3[7],adc_data_2[7],adc_data_1[7],adc_data_0[7]} = data_s7; + + assign serdes_in_p = {rx_strobe_in_p_strobe_in, + rx_qdata_in_p_qdata3, + rx_qdata_in_n_qdata2, + rx_idata_in_p_idata1, + rx_idata_in_n_idata0}; + assign serdes_in_n = 5'b0; + + end + endgenerate + + generate + if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin + + BUFIO i_clk_buf ( + .I (clk_in_s), + .O (adc_clk_in_fast)); + + BUFR #( + .BUFR_DIVIDE("4") + ) i_div_clk_buf ( + .CLR (mssi_sync), + .CE (1'b1), + .I (clk_in_s), + .O (adc_clk_div_s)); + + if (USE_BUFG == 1) begin + BUFG I_bufg ( + .I (adc_clk_div_s), + .O (adc_clk_div)); + end else begin + assign adc_clk_div = adc_clk_div_s; + end + + xpm_cdc_async_rst #( + .DEST_SYNC_FF (10), // DECIMAL; range: 2-10 + .INIT_SYNC_FF ( 0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values + .RST_ACTIVE_HIGH ( 1) // DECIMAL; 0=active low reset, 1=active high reset + ) rst_syncro ( + .src_arst (mssi_sync), + .dest_clk (adc_clk_div), + .dest_arst(ssi_rst)); + + end else begin + wire adc_clk_in; + + reg mssi_sync_d = 1'b0; + reg mssi_sync_2d = 1'b0; + reg mssi_sync_3d = 1'b0; + reg mssi_sync_edge = 1'b0; + always @(posedge adc_clk_in) begin + mssi_sync_d <= mssi_sync; + mssi_sync_2d <= mssi_sync_d; + mssi_sync_3d <= mssi_sync_2d; + mssi_sync_edge <= mssi_sync_2d & ~mssi_sync_3d; + end + + assign ssi_sync_out = mssi_sync_edge; + + reg ssi_rst_pos; + always @(posedge adc_clk_in) begin + ssi_rst_pos <= ssi_sync_in; + end + + assign adc_clk_in = clk_in_s; + + BUFGCE #( + .CE_TYPE ("SYNC"), + .IS_CE_INVERTED (1'b0), + .IS_I_INVERTED (1'b0) + ) i_clk_buf_fast ( + .O (adc_clk_in_fast), + .CE (1'b1), + .I (adc_clk_in)); + + BUFGCE_DIV #( + .BUFGCE_DIVIDE (4), + .IS_CE_INVERTED (1'b0), + .IS_CLR_INVERTED (1'b0), + .IS_I_INVERTED (1'b0) + ) i_div_clk_buf ( + .O (adc_clk_div), + .CE (1'b1), + .CLR (ssi_rst), + .I (adc_clk_in)); + + assign ssi_rst = ssi_rst_pos; + + end + + endgenerate + + assign adc_clk = adc_clk_in_fast; + assign adc_valid = ~adc_rst; + assign adc_clk_ratio = 4; + +endmodule diff --git a/adi_library/axi_adrv9001/adrv9001_rx_link.v b/adi_library/axi_adrv9001/adrv9001_rx_link.v new file mode 100644 index 00000000..467d5631 --- /dev/null +++ b/adi_library/axi_adrv9001/adrv9001_rx_link.v @@ -0,0 +1,332 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module adrv9001_rx_link #( + parameter CMOS_LVDS_N = 0 +) ( + input adc_rst, + input adc_clk_div, + input [7:0] adc_data_0, + input [7:0] adc_data_1, + input [7:0] adc_data_2, + input [7:0] adc_data_3, + input [7:0] adc_data_strobe, + input adc_valid, + + // upper layer data interface + output rx_clk, + output rx_data_valid, + output [15:0] rx_data_i, + output [15:0] rx_data_q, + + // Config interface + input rx_sdr_ddr_n, + input rx_single_lane, + input rx_symb_op, + input rx_symb_8_16b +); + + wire [7:0] data_0; + wire [7:0] data_1; + wire [7:0] data_2; + wire [7:0] data_3; + wire [7:0] data_strobe; + wire data_valid; + + assign rx_clk = adc_clk_div; + + // CMOS can operate in SDR or DDR mode + generate if (CMOS_LVDS_N) begin : cmos_4_to_8 + wire [3:0] sdr_data_0; + wire [3:0] sdr_data_1; + wire [3:0] sdr_data_2; + wire [3:0] sdr_data_3; + wire [3:0] sdr_data_strobe; + wire sdr_data_valid; + + wire [3:0] sdr_data_0_aligned; + wire [3:0] sdr_data_1_aligned; + wire [3:0] sdr_data_2_aligned; + wire [3:0] sdr_data_3_aligned; + wire [3:0] sdr_data_strobe_aligned; + + wire [7:0] sdr_data_0_packed; + wire [7:0] sdr_data_1_packed; + wire [7:0] sdr_data_2_packed; + wire [7:0] sdr_data_3_packed; + wire [7:0] sdr_data_strobe_packed; + + wire aligner4_ovalid; + + // For SDR drop every second DDR bit + + assign sdr_data_0 = {adc_data_0[7],adc_data_0[5],adc_data_0[3],adc_data_0[1]}; + assign sdr_data_1 = {adc_data_1[7],adc_data_1[5],adc_data_1[3],adc_data_1[1]}; + assign sdr_data_2 = {adc_data_2[7],adc_data_2[5],adc_data_2[3],adc_data_2[1]}; + assign sdr_data_3 = {adc_data_3[7],adc_data_3[5],adc_data_3[3],adc_data_3[1]}; + assign sdr_data_strobe = {adc_data_strobe[7],adc_data_strobe[5],adc_data_strobe[3],adc_data_strobe[1]}; + + adrv9001_aligner4 i_rx_aligner4_0 ( + .clk (adc_clk_div), + .rst (adc_rst), + .idata (sdr_data_0), + .ivalid (adc_valid), + .strobe (sdr_data_strobe), + .odata (sdr_data_0_aligned)); + + adrv9001_aligner4 i_rx_aligner4_1 ( + .clk (adc_clk_div), + .rst (adc_rst), + .idata (sdr_data_1), + .ivalid (adc_valid), + .strobe (sdr_data_strobe), + .odata (sdr_data_1_aligned)); + + adrv9001_aligner4 i_rx_aligner4_2 ( + .clk (adc_clk_div), + .rst (adc_rst), + .idata (sdr_data_2), + .ivalid (adc_valid), + .strobe (sdr_data_strobe), + .odata (sdr_data_2_aligned)); + + adrv9001_aligner4 i_rx_aligner4_3 ( + .clk (adc_clk_div), + .rst (adc_rst), + .idata (sdr_data_3), + .ivalid (adc_valid), + .strobe (sdr_data_strobe), + .odata (sdr_data_3_aligned)); + + adrv9001_aligner4 i_rx_aligner4_strobe ( + .clk (adc_clk_div), + .rst (adc_rst), + .idata (sdr_data_strobe), + .ivalid (adc_valid), + .strobe (sdr_data_strobe), + .ovalid (aligner4_ovalid), + .odata (sdr_data_strobe_aligned)); + + adrv9001_pack #( + .WIDTH(4) + ) i_rx_pack_4_to_8_0 ( + .clk (adc_clk_div), + .rst (adc_rst), + .idata (sdr_data_0_aligned), + .ivalid (aligner4_ovalid), + .sof (sdr_data_strobe_aligned[3]), + .odata (sdr_data_0_packed), + .ovalid (sdr_data_valid)); + + adrv9001_pack #( + .WIDTH(4) + ) i_rx_pack_4_to_8_1 ( + .clk (adc_clk_div), + .rst (adc_rst), + .idata (sdr_data_1_aligned), + .ivalid (aligner4_ovalid), + .sof (sdr_data_strobe_aligned[3]), + .odata (sdr_data_1_packed), + .ovalid ()); + + adrv9001_pack #( + .WIDTH(4) + ) i_rx_pack_4_to_8_2 ( + .clk (adc_clk_div), + .idata (sdr_data_2_aligned), + .ivalid (aligner4_ovalid), + .sof (sdr_data_strobe_aligned[3]), + .odata (sdr_data_2_packed), + .ovalid ()); + + adrv9001_pack #( + .WIDTH(4) + ) i_rx_pack_4_to_8_3 ( + .clk (adc_clk_div), + .rst (adc_rst), + .idata (sdr_data_3_aligned), + .ivalid (aligner4_ovalid), + .sof (sdr_data_strobe_aligned[3]), + .odata (sdr_data_3_packed), + .ovalid ()); + + adrv9001_pack #( + .WIDTH(4) + ) i_rx_pack_4_to_8_strobe ( + .clk (adc_clk_div), + .rst (adc_rst), + .idata (sdr_data_strobe_aligned), + .ivalid (aligner4_ovalid), + .sof (sdr_data_strobe_aligned[3]), + .odata (sdr_data_strobe_packed), + .ovalid ()); + + assign data_0 = rx_sdr_ddr_n ? sdr_data_0_packed : adc_data_0; + assign data_1 = rx_sdr_ddr_n ? sdr_data_1_packed : adc_data_1; + assign data_2 = rx_sdr_ddr_n ? sdr_data_2_packed : adc_data_2; + assign data_3 = rx_sdr_ddr_n ? sdr_data_3_packed : adc_data_3; + assign data_strobe = rx_sdr_ddr_n ? sdr_data_strobe_packed : adc_data_strobe; + assign data_valid = rx_sdr_ddr_n ? sdr_data_valid : adc_valid; + end else begin + assign data_0 = adc_data_0; + assign data_1 = adc_data_1; + assign data_2 = adc_data_2; + assign data_3 = adc_data_3; + assign data_strobe = adc_data_strobe; + assign data_valid = adc_valid; + end + endgenerate + + // ADC + + wire [7:0] rx_data8_0_aligned; + wire [7:0] rx_data8_1_aligned; + wire [7:0] rx_data8_2_aligned; + wire [7:0] rx_data8_3_aligned; + wire [7:0] rx_data8_strobe_aligned; + wire rx_data8_0_aligned_valid; + wire rx_data8_1_aligned_valid; + + wire [15:0] rx_data16_0_packed; + wire [15:0] rx_data16_1_packed; + wire rx_data16_0_packed_valid; + wire rx_data16_1_packed_valid; + wire rx_data16_0_packed_osof; + wire rx_data16_1_packed_osof; + + wire [31:0] rx_data32_0_packed; + wire rx_data32_0_packed_valid; + + adrv9001_aligner8 i_rx_aligner8_0 ( + .clk (adc_clk_div), + .rst (adc_rst), + .idata (data_0), + .ivalid (data_valid), + .strobe (data_strobe), + .odata (rx_data8_0_aligned), + .ovalid (rx_data8_0_aligned_valid)); + + adrv9001_aligner8 i_rx_aligner8_1 ( + .clk (adc_clk_div), + .rst (adc_rst), + .ivalid (data_valid), + .idata (data_1), + .strobe (data_strobe), + .odata (rx_data8_1_aligned), + .ovalid (rx_data8_1_aligned_valid)); + + generate if (CMOS_LVDS_N) begin : cmos_aligner8 + adrv9001_aligner8 i_rx_aligner8_2 ( + .clk (adc_clk_div), + .rst (adc_rst), + .idata (data_2), + .ivalid (data_valid), + .strobe (data_strobe), + .odata (rx_data8_2_aligned)); + + adrv9001_aligner8 i_rx_aligner8_3( + .clk (adc_clk_div), + .rst (adc_rst), + .idata (data_3), + .ivalid (data_valid), + .strobe (data_strobe), + .odata (rx_data8_3_aligned)); + end + endgenerate + + adrv9001_aligner8 i_rx_strobe_aligner ( + .clk (adc_clk_div), + .rst (adc_rst), + .idata (data_strobe), + .ivalid (data_valid), + .strobe (data_strobe), + .odata (rx_data8_strobe_aligned)); + + adrv9001_pack #( + .WIDTH (8) + ) i_rx_pack_8_to_16_0 ( + .clk (adc_clk_div), + .rst (adc_rst), + .ivalid (rx_data8_0_aligned_valid), + .idata (rx_data8_0_aligned), + .sof (rx_data8_strobe_aligned[7]), + .odata (rx_data16_0_packed), + .ovalid (rx_data16_0_packed_valid), + .osof (rx_data16_0_packed_osof)); + + adrv9001_pack #( + .WIDTH (8) + ) i_rx_pack_8_to_16_1 ( + .clk (adc_clk_div), + .rst (adc_rst), + .ivalid (rx_data8_1_aligned_valid), + .idata (rx_data8_1_aligned), + .sof (rx_data8_strobe_aligned[7]), + .odata (rx_data16_1_packed), + .ovalid (rx_data16_1_paked_valid), + .osof (rx_data16_1_packed_osof)); + + adrv9001_pack #( + .WIDTH (16) + ) i_rx_pack_16_to_32_0 ( + .clk (adc_clk_div), + .rst (adc_rst), + .ivalid (rx_data16_0_packed_valid), + .idata (rx_data16_0_packed), + .sof (rx_data16_0_packed_osof), + .odata (rx_data32_0_packed), + .ovalid (rx_data32_0_packed_valid), + .osof (rx_data32_0_packed_osof)); + + generate if (CMOS_LVDS_N) begin + assign rx_data_i = ~rx_single_lane ? {rx_data8_1_aligned,rx_data8_0_aligned} : + (rx_symb_op ? rx_data16_0_packed : rx_data32_0_packed[31:16]); + assign rx_data_q = ~rx_single_lane ? {rx_data8_3_aligned,rx_data8_2_aligned} : + (rx_symb_op ? 'b0 : rx_data32_0_packed[15:0]); + assign rx_data_valid = ~rx_single_lane ? rx_data8_0_aligned_valid : + (rx_symb_op ? (rx_symb_8_16b ? rx_data8_0_aligned_valid : rx_data16_0_packed_valid) : rx_data32_0_packed_valid); + end else begin + assign rx_data_i = ~rx_single_lane ? rx_data16_0_packed : + rx_data32_0_packed[31:16]; + assign rx_data_q = ~rx_single_lane ? rx_data16_1_packed : + rx_data32_0_packed[15:0]; + assign rx_data_valid = ~rx_single_lane ? rx_data16_0_packed_valid : + rx_data32_0_packed_valid; + end + endgenerate + +endmodule diff --git a/adi_library/axi_adrv9001/adrv9001_tx.v b/adi_library/axi_adrv9001/adrv9001_tx.v new file mode 100644 index 00000000..602fc1ea --- /dev/null +++ b/adi_library/axi_adrv9001/adrv9001_tx.v @@ -0,0 +1,256 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module adrv9001_tx #( + parameter CMOS_LVDS_N = 0, + parameter NUM_LANES = 4, + parameter FPGA_TECHNOLOGY = 0, + parameter USE_BUFG = 0, + parameter USE_RX_CLK_FOR_TX = 0 +) ( + input ref_clk, + input up_clk, + + input mssi_sync, + input tx_output_enable, + + // physical interface (transmit) + output tx_dclk_out_n_NC, + output tx_dclk_out_p_dclk_out, + input tx_dclk_in_n_NC, + input tx_dclk_in_p_dclk_in, + output tx_idata_out_n_idata0, + output tx_idata_out_p_idata1, + output tx_qdata_out_n_qdata2, + output tx_qdata_out_p_qdata3, + output tx_strobe_out_n_NC, + output tx_strobe_out_p_strobe_out, + + input rx_clk_div, + input rx_clk, + input rx_ssi_rst, + + // internal resets and clocks + output [31:0] dac_clk_ratio, + + input dac_rst, + output dac_clk_div, + + input [7:0] dac_data_0, + input [7:0] dac_data_1, + input [7:0] dac_data_2, + input [7:0] dac_data_3, + input [7:0] dac_data_strb, + input [7:0] dac_data_clk, + input dac_data_valid +); + + localparam SEVEN_SERIES = 1; + localparam ULTRASCALE = 2; + localparam ULTRASCALE_PLUS = 3; + + // internal wire + wire tx_dclk_in_s; + wire dac_fast_clk; + wire [NUM_LANES-1:0] serdes_out_p; + wire [NUM_LANES-1:0] serdes_out_n; + wire [NUM_LANES-1:0] data_s0; + wire [NUM_LANES-1:0] data_s1; + wire [NUM_LANES-1:0] data_s2; + wire [NUM_LANES-1:0] data_s3; + wire [NUM_LANES-1:0] data_s4; + wire [NUM_LANES-1:0] data_s5; + wire [NUM_LANES-1:0] data_s6; + wire [NUM_LANES-1:0] data_s7; + wire ssi_rst; + + ad_serdes_out #( + .CMOS_LVDS_N (CMOS_LVDS_N), + .DDR_OR_SDR_N(1), + .DATA_WIDTH(NUM_LANES), + .SERDES_FACTOR(8), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY) + ) i_serdes ( + .rst (dac_rst|ssi_rst), + .clk (dac_fast_clk), + .div_clk (dac_clk_div), + .data_oe (tx_output_enable), + .data_s0 (data_s0), + .data_s1 (data_s1), + .data_s2 (data_s2), + .data_s3 (data_s3), + .data_s4 (data_s4), + .data_s5 (data_s5), + .data_s6 (data_s6), + .data_s7 (data_s7), + .data_out_se (), + .data_out_p (serdes_out_p), + .data_out_n (serdes_out_n)); + + generate + if (CMOS_LVDS_N == 0) begin + + IBUFGDS i_dac_clk_in_ibuf ( + .I (tx_dclk_in_p_dclk_in), + .IB (tx_dclk_in_n_NC), + .O (tx_dclk_in_s)); + + assign data_s0 = {dac_data_clk[7],dac_data_strb[7],dac_data_1[7],dac_data_0[7]}; + assign data_s1 = {dac_data_clk[6],dac_data_strb[6],dac_data_1[6],dac_data_0[6]}; + assign data_s2 = {dac_data_clk[5],dac_data_strb[5],dac_data_1[5],dac_data_0[5]}; + assign data_s3 = {dac_data_clk[4],dac_data_strb[4],dac_data_1[4],dac_data_0[4]}; + assign data_s4 = {dac_data_clk[3],dac_data_strb[3],dac_data_1[3],dac_data_0[3]}; + assign data_s5 = {dac_data_clk[2],dac_data_strb[2],dac_data_1[2],dac_data_0[2]}; + assign data_s6 = {dac_data_clk[1],dac_data_strb[1],dac_data_1[1],dac_data_0[1]}; + assign data_s7 = {dac_data_clk[0],dac_data_strb[0],dac_data_1[0],dac_data_0[0]}; + + assign {tx_dclk_out_p_dclk_out, + tx_strobe_out_p_strobe_out, + tx_qdata_out_p_qdata3, + tx_idata_out_p_idata1} = serdes_out_p; + + assign {tx_dclk_out_n_NC, + tx_strobe_out_n_NC, + tx_qdata_out_n_qdata2, + tx_idata_out_n_idata0} = serdes_out_n; + end else begin + + IBUF i_dac_clk_in_ibuf ( + .I (tx_dclk_in_p_dclk_in), + .O (tx_dclk_in_s)); + + assign data_s0 = {dac_data_clk[7],dac_data_strb[7],dac_data_3[7],dac_data_2[7],dac_data_1[7],dac_data_0[7]}; + assign data_s1 = {dac_data_clk[6],dac_data_strb[6],dac_data_3[6],dac_data_2[6],dac_data_1[6],dac_data_0[6]}; + assign data_s2 = {dac_data_clk[5],dac_data_strb[5],dac_data_3[5],dac_data_2[5],dac_data_1[5],dac_data_0[5]}; + assign data_s3 = {dac_data_clk[4],dac_data_strb[4],dac_data_3[4],dac_data_2[4],dac_data_1[4],dac_data_0[4]}; + assign data_s4 = {dac_data_clk[3],dac_data_strb[3],dac_data_3[3],dac_data_2[3],dac_data_1[3],dac_data_0[3]}; + assign data_s5 = {dac_data_clk[2],dac_data_strb[2],dac_data_3[2],dac_data_2[2],dac_data_1[2],dac_data_0[2]}; + assign data_s6 = {dac_data_clk[1],dac_data_strb[1],dac_data_3[1],dac_data_2[1],dac_data_1[1],dac_data_0[1]}; + assign data_s7 = {dac_data_clk[0],dac_data_strb[0],dac_data_3[0],dac_data_2[0],dac_data_1[0],dac_data_0[0]}; + + assign {tx_dclk_out_p_dclk_out, + tx_strobe_out_p_strobe_out, + tx_qdata_out_p_qdata3, + tx_qdata_out_n_qdata2, + tx_idata_out_p_idata1, + tx_idata_out_n_idata0} = serdes_out_p; + + assign {tx_dclk_out_n_NC, + tx_strobe_out_n_NC} = 2'b0; + end + + if (USE_RX_CLK_FOR_TX == 0) begin + + if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin + + // SERDES fast clock + BUFIO i_dac_clk_in_gbuf ( + .I (tx_dclk_in_s), + .O (dac_fast_clk)); + + // SERDES slow clock + BUFR #( + .BUFR_DIVIDE("4") + ) i_dac_div_clk_rbuf ( + .CLR (mssi_sync), + .CE (1'b1), + .I (tx_dclk_in_s), + .O (dac_clk_div_s)); + + if (USE_BUFG == 1) begin + BUFG I_bufg ( + .I (dac_clk_div_s), + .O (dac_clk_div)); + end else begin + assign dac_clk_div = dac_clk_div_s; + end + + xpm_cdc_async_rst #( + .DEST_SYNC_FF (10), // DECIMAL; range: 2-10 + .INIT_SYNC_FF ( 0), // DECIMAL; 0=disable simulation init values, 1=enable simulation init values + .RST_ACTIVE_HIGH ( 1) // DECIMAL; 0=active low reset, 1=active high reset + ) rst_syncro ( + .src_arst (mssi_sync), + .dest_clk (dac_clk_div), + .dest_arst(ssi_rst)); + + end else begin + + reg mssi_sync_d = 1'b0; + reg mssi_sync_2d = 1'b0; + always @(posedge dac_fast_clk) begin + mssi_sync_d <= mssi_sync; + mssi_sync_2d <= mssi_sync_d; + end + + BUFGCE #( + .CE_TYPE ("SYNC"), + .IS_CE_INVERTED (1'b0), + .IS_I_INVERTED (1'b0) + ) i_dac_clk_in_gbuf ( + .O (dac_fast_clk), + .CE (1'b1), + .I (tx_dclk_in_s)); + + BUFGCE_DIV #( + .BUFGCE_DIVIDE (4), + .IS_CE_INVERTED (1'b0), + .IS_CLR_INVERTED (1'b0), + .IS_I_INVERTED (1'b0) + ) i_dac_div_clk_rbuf ( + .O (dac_clk_div), + .CE (1'b1), + .CLR (mssi_sync_2d), + .I (tx_dclk_in_s)); + + assign ssi_rst = mssi_sync_2d; + + end + + end else begin + + assign dac_fast_clk = rx_clk; + assign dac_clk_div = rx_clk_div; + assign ssi_rst = rx_ssi_rst; + + end + + endgenerate + + assign dac_clk_ratio = 4; + +endmodule diff --git a/adi_library/axi_adrv9001/adrv9001_tx_link.v b/adi_library/axi_adrv9001/adrv9001_tx_link.v new file mode 100644 index 00000000..d8882c12 --- /dev/null +++ b/adi_library/axi_adrv9001/adrv9001_tx_link.v @@ -0,0 +1,220 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module adrv9001_tx_link #( + parameter CMOS_LVDS_N = 0, + parameter CLK_DIV_IS_FAST_CLK = 0 +) ( + input dac_clk_div, + output [7:0] dac_data_0, + output [7:0] dac_data_1, + output [7:0] dac_data_2, + output [7:0] dac_data_3, + output [7:0] dac_data_strobe, + output [7:0] dac_data_clk, + output dac_data_valid, + + // upper layer data interface + output tx_clk, + input tx_rst, + input tx_data_valid, + input [15:0] tx_data_i, + input [15:0] tx_data_q, + + // Config interface + input tx_sdr_ddr_n, + input tx_single_lane, + input tx_symb_op, + input tx_symb_8_16b +); + + assign tx_clk = dac_clk_div; + + wire [7:0] data32sdr; + wire [7:0] strobe32sdr; + wire [7:0] data16sdr_0; + wire [7:0] strobe16sdr; + + wire [7:0] data8sdr_0; + wire [7:0] data8sdr_1; + wire [7:0] data8sdr_2; + wire [7:0] data8sdr_3; + wire [7:0] strobe8sdr; + + wire ld_next; + + reg [31:0] data32 = 32'b0; + reg [31:0] strobe32 = 32'b0; + reg [15:0] data16_0 = 16'b0; + reg [15:0] data16_1 = 16'b0; + reg [15:0] strobe16 = 16'b0; + reg [7:0] data8_0 = 8'b0; + reg [7:0] data8_1 = 8'b0; + reg [7:0] data8_2 = 8'b0; + reg [7:0] data8_3 = 8'b0; + reg [7:0] strobe8 = 8'b0; + reg [3:0] valid_gen = 4'b0; + + // Serialization factor Per data lane 32 + always @(posedge tx_clk) begin + if (tx_data_valid) begin + data32 <= {tx_data_i,tx_data_q}; + strobe32 <= {1'b1,31'b0}; + end else if (ld_next) begin + if (tx_sdr_ddr_n) begin + data32 <= {data32,4'b0}; + strobe32 <= {strobe32,4'b0}; + end else begin + data32 <= {data32,8'b0}; + strobe32 <= {strobe32,8'b0}; + end + end + end + + // Double each bit due the DDR PHY + assign data32sdr = {data32[31],data32[31], + data32[30],data32[30], + data32[29],data32[29], + data32[28],data32[28]}; + assign strobe32sdr = {strobe32[31],strobe32[31], + strobe32[30],strobe32[30], + strobe32[29],strobe32[29], + strobe32[28],strobe32[28]}; + + // Serialization factor Per data lane 16 + always @(posedge tx_clk) begin + if (tx_data_valid) begin + data16_0 <= tx_data_i; + data16_1 <= tx_data_q; + strobe16 <= {1'b1,15'b0}; + end else if (ld_next) begin + if(tx_sdr_ddr_n) begin + data16_0 <= {data16_0,4'b0}; + data16_1 <= {data16_1,4'b0}; + strobe16 <= {strobe16,4'b0}; + end else begin + data16_0 <= {data16_0,8'b0}; + data16_1 <= {data16_1,8'b0}; + strobe16 <= {strobe16,8'b0}; + end + end + end + + // Double each bit due to the DDR PHY + assign data16sdr_0 = {data16_0[15],data16_0[15], + data16_0[14],data16_0[14], + data16_0[13],data16_0[13], + data16_0[12],data16_0[12]}; + assign strobe16sdr = {strobe16[15],strobe16[15], + strobe16[14],strobe16[14], + strobe16[13],strobe16[13], + strobe16[12],strobe16[12]}; + + // Serialization factor Per data lane 8 + always @(posedge tx_clk) begin + if (tx_data_valid) begin + data8_0 <= tx_data_i[7:0]; + data8_1 <= tx_data_i[15:8]; + data8_2 <= tx_data_q[7:0]; + data8_3 <= tx_data_q[15:8]; + strobe8 <= {1'b1,7'b0}; + end else if (ld_next) begin + data8_0 <= {data8_0,4'b0}; + data8_1 <= {data8_1,4'b0}; + data8_2 <= {data8_2,4'b0}; + data8_3 <= {data8_3,4'b0}; + strobe8 <= {strobe16,4'b0}; + end + end + + // Double each bit due the DDR PHY + assign data8sdr_0 = {data8_0[7],data8_0[7], + data8_0[6],data8_0[6], + data8_0[5],data8_0[5], + data8_0[4],data8_0[4]}; + assign data8sdr_1 = {data8_1[7],data8_1[7], + data8_1[6],data8_1[6], + data8_1[5],data8_1[5], + data8_1[4],data8_1[4]}; + assign data8sdr_2 = {data8_2[7],data8_2[7], + data8_2[6],data8_2[6], + data8_2[5],data8_2[5], + data8_2[4],data8_2[4]}; + assign data8sdr_3 = {data8_3[7],data8_3[7], + data8_3[6],data8_3[6], + data8_3[5],data8_3[5], + data8_3[4],data8_3[4]}; + assign strobe8sdr = {strobe8[7],strobe8[7], + strobe8[6],strobe8[6], + strobe8[5],strobe8[5], + strobe8[4],strobe8[4]}; + + assign dac_data_0 = tx_single_lane ? (tx_symb_op ? (tx_sdr_ddr_n ? data16sdr_0 : data16_0[15-:8]) : + (tx_sdr_ddr_n ? data32sdr : data32[31-:8])) : + (CMOS_LVDS_N ? (tx_sdr_ddr_n ? data8sdr_0 : data8_0) : data16_0[15-:8]); + + assign dac_data_1 = tx_single_lane ? 'b0 : + (CMOS_LVDS_N ? (tx_sdr_ddr_n ? data8sdr_1 : data8_1) : + data16_1[15-:8]); + + assign dac_data_2 = tx_single_lane ? 'b0 : + (CMOS_LVDS_N ? (tx_sdr_ddr_n ? data8sdr_2 : data8_2) : + 1'b0); + + assign dac_data_3 = tx_single_lane ? 'b0 : + (CMOS_LVDS_N ? (tx_sdr_ddr_n ? data8sdr_3 : data8_3) : + 1'b0); + + assign dac_data_strobe = tx_single_lane ? (tx_symb_op ? (tx_symb_8_16b ? (tx_sdr_ddr_n ? strobe8sdr : strobe8) : + (tx_sdr_ddr_n ? strobe16sdr : strobe16[15-:8])): + (tx_sdr_ddr_n ? strobe32sdr : strobe32[31-:8])) : + (CMOS_LVDS_N ? (tx_sdr_ddr_n ? strobe8sdr : strobe8) : strobe16[15-:8]); + + assign dac_data_clk = {4{1'b1,1'b0}}; + + assign dac_data_valid = (CLK_DIV_IS_FAST_CLK == 0) ? 1'b1 : valid_gen[3]; + + always @(posedge tx_clk) begin + if (tx_data_valid) begin + valid_gen <= 4'b1000; + end else begin + valid_gen <= {valid_gen[2:0],valid_gen[3]}; + end + end + assign ld_next = (CLK_DIV_IS_FAST_CLK == 0) ? 1'b1 : valid_gen[2]; + +endmodule diff --git a/adi_library/axi_adrv9001/axi_adrv9001.v b/adi_library/axi_adrv9001/axi_adrv9001.v new file mode 100644 index 00000000..cdacf6c6 --- /dev/null +++ b/adi_library/axi_adrv9001/axi_adrv9001.v @@ -0,0 +1,612 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adrv9001 #( + parameter ID = 0, + parameter CMOS_LVDS_N = 0, + parameter TDD_DISABLE = 0, + parameter DDS_DISABLE = 0, + parameter INDEPENDENT_1R1T_SUPPORT = 1, + parameter COMMON_2R2T_SUPPORT = 1, + parameter DISABLE_RX2_SSI = 0, + parameter DISABLE_TX2_SSI = 0, + parameter RX_USE_BUFG = 0, + parameter TX_USE_BUFG = 0, + parameter IODELAY_CTRL = 1, + parameter IODELAY_ENABLE = 1, + parameter IO_DELAY_GROUP = "dev_if_delay_group", + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter EXT_SYNC = 0, + parameter USE_RX_CLK_FOR_TX = 0 +) ( + input ref_clk, + input mssi_sync, + input tx_output_enable, + + // external synchronization signals + input adc_sync_in, + input dac_sync_in, + + // physical interface + input rx1_dclk_in_n_NC, + input rx1_dclk_in_p_dclk_in, + input rx1_idata_in_n_idata0, + input rx1_idata_in_p_idata1, + input rx1_qdata_in_n_qdata2, + input rx1_qdata_in_p_qdata3, + input rx1_strobe_in_n_NC, + input rx1_strobe_in_p_strobe_in, + + input rx2_dclk_in_n_NC, + input rx2_dclk_in_p_dclk_in, + input rx2_idata_in_n_idata0, + input rx2_idata_in_p_idata1, + input rx2_qdata_in_n_qdata2, + input rx2_qdata_in_p_qdata3, + input rx2_strobe_in_n_NC, + input rx2_strobe_in_p_strobe_in, + + output tx1_dclk_out_n_NC, + output tx1_dclk_out_p_dclk_out, + input tx1_dclk_in_n_NC, + input tx1_dclk_in_p_dclk_in, + output tx1_idata_out_n_idata0, + output tx1_idata_out_p_idata1, + output tx1_qdata_out_n_qdata2, + output tx1_qdata_out_p_qdata3, + output tx1_strobe_out_n_NC, + output tx1_strobe_out_p_strobe_out, + + output tx2_dclk_out_n_NC, + output tx2_dclk_out_p_dclk_out, + input tx2_dclk_in_n_NC, + input tx2_dclk_in_p_dclk_in, + output tx2_idata_out_n_idata0, + output tx2_idata_out_p_idata1, + output tx2_qdata_out_n_qdata2, + output tx2_qdata_out_p_qdata3, + output tx2_strobe_out_n_NC, + output tx2_strobe_out_p_strobe_out, + + output rx1_enable, + output rx2_enable, + output tx1_enable, + output tx2_enable, + + input delay_clk, + + // user interface + + output adc_1_clk, + output adc_1_rst, + + output adc_1_valid_i0, + output adc_1_enable_i0, + output [15:0] adc_1_data_i0, + output adc_1_valid_q0, + output adc_1_enable_q0, + output [15:0] adc_1_data_q0, + output adc_1_valid_i1, + output adc_1_enable_i1, + output [15:0] adc_1_data_i1, + output adc_1_valid_q1, + output adc_1_enable_q1, + output [15:0] adc_1_data_q1, + input adc_1_dovf, + + output adc_2_clk, + output adc_2_rst, + output adc_2_valid_i0, + output adc_2_enable_i0, + output [15:0] adc_2_data_i0, + output adc_2_valid_q0, + output adc_2_enable_q0, + output [15:0] adc_2_data_q0, + input adc_2_dovf, + + output dac_1_clk, + output dac_1_rst, + output dac_1_valid_i0, + output dac_1_enable_i0, + input [15:0] dac_1_data_i0, + output dac_1_valid_q0, + output dac_1_enable_q0, + input [15:0] dac_1_data_q0, + output dac_1_valid_i1, + output dac_1_enable_i1, + input [15:0] dac_1_data_i1, + output dac_1_valid_q1, + output dac_1_enable_q1, + input [15:0] dac_1_data_q1, + input dac_1_dunf, + + output dac_2_clk, + output dac_2_rst, + output dac_2_valid_i0, + output dac_2_enable_i0, + input [15:0] dac_2_data_i0, + output dac_2_valid_q0, + output dac_2_enable_q0, + input [15:0] dac_2_data_q0, + input dac_2_dunf, + + // TDD interface + input tdd_sync, + output tdd_sync_cntr, + + input gpio_rx1_enable_in, + input gpio_rx2_enable_in, + input gpio_tx1_enable_in, + input gpio_tx2_enable_in, + + // axi interface + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot +); + + localparam SEVEN_SERIES = 1; + localparam ULTRASCALE = 2; + localparam ULTRASCALE_PLUS = 3; + + localparam DRP_WIDTH = FPGA_TECHNOLOGY == ULTRASCALE ? 9 : + FPGA_TECHNOLOGY == ULTRASCALE_PLUS ? 9 : 5; + + localparam NUM_LANES = CMOS_LVDS_N ? 5 : 3; + + // internal signals + wire up_wreq_s; + wire up_rreq_s; + wire [13:0] up_waddr_s; + wire [13:0] up_raddr_s; + wire [31:0] up_wdata_s; + wire [31:0] up_rdata_s; + wire up_wack_s; + wire up_rack_s; + + wire [15:0] rx1_data_i; + wire [15:0] rx1_data_q; + wire rx1_data_valid; + wire rx1_single_lane; + wire rx1_sdr_ddr_n; + wire rx1_symb_op; + wire rx1_symb_8_16b; + wire [15:0] rx2_data_i; + wire [15:0] rx2_data_q; + wire rx2_data_valid; + wire rx2_single_lane; + wire rx2_sdr_ddr_n; + wire rx2_symb_op; + wire rx2_symb_8_16b; + + wire [15:0] tx1_data_i; + wire [15:0] tx1_data_q; + wire tx1_data_valid; + wire tx1_single_lane; + wire tx1_sdr_ddr_n; + wire tx1_symb_op; + wire tx1_symb_8_16b; + wire [15:0] tx2_data_i; + wire [15:0] tx2_data_q; + wire tx2_data_valid; + wire tx2_single_lane; + wire tx2_sdr_ddr_n; + wire tx2_symb_op; + wire tx2_symb_8_16b; + + wire adc_1_valid; + wire adc_2_valid; + wire dac_1_valid; + wire dac_2_valid; + + // internal clocks & resets + wire up_rstn; + wire up_clk; + + // clock/reset assignments + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + wire [NUM_LANES-1:0] up_rx1_dld; + wire [DRP_WIDTH*NUM_LANES-1:0] up_rx1_dwdata; + wire [DRP_WIDTH*NUM_LANES-1:0] up_rx1_drdata; + wire [NUM_LANES-1:0] up_rx2_dld; + wire [DRP_WIDTH*NUM_LANES-1:0] up_rx2_dwdata; + wire [DRP_WIDTH*NUM_LANES-1:0] up_rx2_drdata; + wire delay_rx1_rst; + wire delay_rx2_rst; + wire delay_rx1_locked; + wire delay_rx2_locked; + wire [31:0] adc_clk_ratio; + wire [31:0] dac_clk_ratio; + + axi_adrv9001_if #( + .CMOS_LVDS_N (CMOS_LVDS_N), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .NUM_LANES (NUM_LANES), + .DRP_WIDTH (DRP_WIDTH), + .RX_USE_BUFG (RX_USE_BUFG), + .TX_USE_BUFG (TX_USE_BUFG), + .IODELAY_CTRL (IODELAY_CTRL), + .IODELAY_ENABLE (IODELAY_ENABLE), + .IO_DELAY_GROUP (IO_DELAY_GROUP), + .DISABLE_RX2_SSI (DISABLE_RX2_SSI), + .DISABLE_TX2_SSI (DISABLE_TX2_SSI), + .USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX) + ) i_if ( + + // + // Physical interface + // + .ref_clk (ref_clk), + .mssi_sync (mssi_sync), + .tx_output_enable (tx_output_enable), + + .rx1_dclk_in_n_NC (rx1_dclk_in_n_NC), + .rx1_dclk_in_p_dclk_in (rx1_dclk_in_p_dclk_in), + .rx1_idata_in_n_idata0 (rx1_idata_in_n_idata0), + .rx1_idata_in_p_idata1 (rx1_idata_in_p_idata1), + .rx1_qdata_in_n_qdata2 (rx1_qdata_in_n_qdata2), + .rx1_qdata_in_p_qdata3 (rx1_qdata_in_p_qdata3), + .rx1_strobe_in_n_NC (rx1_strobe_in_n_NC), + .rx1_strobe_in_p_strobe_in (rx1_strobe_in_p_strobe_in), + + .rx2_dclk_in_n_NC (rx2_dclk_in_n_NC), + .rx2_dclk_in_p_dclk_in (rx2_dclk_in_p_dclk_in), + .rx2_idata_in_n_idata0 (rx2_idata_in_n_idata0), + .rx2_idata_in_p_idata1 (rx2_idata_in_p_idata1), + .rx2_qdata_in_n_qdata2 (rx2_qdata_in_n_qdata2), + .rx2_qdata_in_p_qdata3 (rx2_qdata_in_p_qdata3), + .rx2_strobe_in_n_NC (rx2_strobe_in_n_NC), + .rx2_strobe_in_p_strobe_in (rx2_strobe_in_p_strobe_in), + + .tx1_dclk_out_n_NC (tx1_dclk_out_n_NC), + .tx1_dclk_out_p_dclk_out (tx1_dclk_out_p_dclk_out), + .tx1_dclk_in_n_NC (tx1_dclk_in_n_NC), + .tx1_dclk_in_p_dclk_in (tx1_dclk_in_p_dclk_in), + .tx1_idata_out_n_idata0 (tx1_idata_out_n_idata0), + .tx1_idata_out_p_idata1 (tx1_idata_out_p_idata1), + .tx1_qdata_out_n_qdata2 (tx1_qdata_out_n_qdata2), + .tx1_qdata_out_p_qdata3 (tx1_qdata_out_p_qdata3), + .tx1_strobe_out_n_NC (tx1_strobe_out_n_NC), + .tx1_strobe_out_p_strobe_out (tx1_strobe_out_p_strobe_out), + + .tx2_dclk_out_n_NC (tx2_dclk_out_n_NC), + .tx2_dclk_out_p_dclk_out (tx2_dclk_out_p_dclk_out), + .tx2_dclk_in_n_NC (tx2_dclk_in_n_NC), + .tx2_dclk_in_p_dclk_in (tx2_dclk_in_p_dclk_in), + .tx2_idata_out_n_idata0 (tx2_idata_out_n_idata0), + .tx2_idata_out_p_idata1 (tx2_idata_out_p_idata1), + .tx2_qdata_out_n_qdata2 (tx2_qdata_out_n_qdata2), + .tx2_qdata_out_p_qdata3 (tx2_qdata_out_p_qdata3), + .tx2_strobe_out_n_NC (tx2_strobe_out_n_NC), + .tx2_strobe_out_p_strobe_out (tx2_strobe_out_p_strobe_out), + + // + // Control interface + // + + // delay interface (for IDELAY macros) + .delay_clk (delay_clk), + .delay_rx1_rst (delay_rx1_rst), + .delay_rx2_rst (delay_rx2_rst), + .delay_rx1_locked (delay_rx1_locked), + .delay_rx2_locked (delay_rx2_locked), + .up_clk (up_clk), + .up_rx1_dld (up_rx1_dld), + .up_rx1_dwdata (up_rx1_dwdata), + .up_rx1_drdata (up_rx1_drdata), + + .up_rx2_dld (up_rx2_dld), + .up_rx2_dwdata (up_rx2_dwdata), + .up_rx2_drdata (up_rx2_drdata), + + // + // Transport layer interface + // + + // ADC interface + .adc_clk_ratio (adc_clk_ratio), + .rx1_clk (adc_1_clk), + .rx1_rst (adc_1_rst), + .rx1_data_valid (rx1_data_valid), + .rx1_data_i (rx1_data_i), + .rx1_data_q (rx1_data_q), + + .rx1_single_lane (rx1_single_lane), + .rx1_sdr_ddr_n (rx1_sdr_ddr_n), + .rx1_symb_op (rx1_symb_op), + .rx1_symb_8_16b (rx1_symb_8_16b), + + .rx2_clk (adc_2_clk), + .rx2_rst (adc_2_rst), + .rx2_data_valid (rx2_data_valid), + .rx2_data_i (rx2_data_i), + .rx2_data_q (rx2_data_q), + + .rx2_single_lane (rx2_single_lane), + .rx2_sdr_ddr_n (rx2_sdr_ddr_n), + .rx2_symb_op (rx2_symb_op), + .rx2_symb_8_16b (rx2_symb_8_16b), + + // DAC interface + .dac_clk_ratio (dac_clk_ratio), + .tx1_clk (dac_1_clk), + .tx1_rst (dac_1_rst), + .tx1_data_valid (tx1_data_valid), + .tx1_data_i (tx1_data_i), + .tx1_data_q (tx1_data_q), + + .tx1_single_lane (tx1_single_lane), + .tx1_sdr_ddr_n (tx1_sdr_ddr_n), + .tx1_symb_op (tx1_symb_op), + .tx1_symb_8_16b (tx1_symb_8_16b), + + .tx2_clk (dac_2_clk), + .tx2_rst (dac_2_rst), + .tx2_data_valid (tx2_data_valid), + .tx2_data_i (tx2_data_i), + .tx2_data_q (tx2_data_q), + + .tx2_single_lane (tx2_single_lane), + .tx2_sdr_ddr_n (tx2_sdr_ddr_n), + .tx2_symb_op (tx2_symb_op), + .tx2_symb_8_16b (tx2_symb_8_16b)); + + // common processor control + axi_adrv9001_core #( + .ID (ID), + .NUM_LANES (NUM_LANES), + .CMOS_LVDS_N (CMOS_LVDS_N), + .USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX), + .DRP_WIDTH (DRP_WIDTH), + .TDD_DISABLE (TDD_DISABLE), + .DDS_DISABLE (DDS_DISABLE), + .INDEPENDENT_1R1T_SUPPORT (INDEPENDENT_1R1T_SUPPORT), + .COMMON_2R2T_SUPPORT (COMMON_2R2T_SUPPORT), + .DISABLE_RX2_SSI (DISABLE_RX2_SSI), + .DISABLE_TX2_SSI (DISABLE_TX2_SSI), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .EXT_SYNC (EXT_SYNC) + ) i_core ( + // ADC interface + .rx1_clk (adc_1_clk), + .rx1_rst (adc_1_rst), + .rx1_data_valid (rx1_data_valid), + .rx1_data_i (rx1_data_i), + .rx1_data_q (rx1_data_q), + + .rx1_single_lane (rx1_single_lane), + .rx1_sdr_ddr_n (rx1_sdr_ddr_n), + .rx1_symb_op (rx1_symb_op), + .rx1_symb_8_16b (rx1_symb_8_16b), + + .rx2_clk (adc_2_clk), + .rx2_rst (adc_2_rst), + .rx2_data_valid (rx2_data_valid), + .rx2_data_i (rx2_data_i), + .rx2_data_q (rx2_data_q), + + .rx2_single_lane (rx2_single_lane), + .rx2_sdr_ddr_n (rx2_sdr_ddr_n), + .rx2_symb_op (rx2_symb_op), + .rx2_symb_8_16b (rx2_symb_8_16b), + + .adc_clk_ratio (adc_clk_ratio), + + //DAC interface + .tx1_clk (dac_1_clk), + .tx1_rst (dac_1_rst), + .tx1_data_valid (tx1_data_valid), + .tx1_data_i (tx1_data_i), + .tx1_data_q (tx1_data_q), + + .tx1_single_lane (tx1_single_lane), + .tx1_sdr_ddr_n (tx1_sdr_ddr_n), + .tx1_symb_op (tx1_symb_op), + .tx1_symb_8_16b (tx1_symb_8_16b), + + .tx2_clk (dac_2_clk), + .tx2_rst (dac_2_rst), + .tx2_data_valid (tx2_data_valid), + .tx2_data_i (tx2_data_i), + .tx2_data_q (tx2_data_q), + + .tx2_single_lane (tx2_single_lane), + .tx2_sdr_ddr_n (tx2_sdr_ddr_n), + .tx2_symb_op (tx2_symb_op), + .tx2_symb_8_16b (tx2_symb_8_16b), + + .dac_clk_ratio (dac_clk_ratio), + // + // User layer interface + // + .adc_1_valid (adc_1_valid), + .adc_1_enable_i0 (adc_1_enable_i0), + .adc_1_data_i0 (adc_1_data_i0), + .adc_1_enable_q0 (adc_1_enable_q0), + .adc_1_data_q0 (adc_1_data_q0), + .adc_1_enable_i1 (adc_1_enable_i1), + .adc_1_data_i1 (adc_1_data_i1), + .adc_1_enable_q1 (adc_1_enable_q1), + .adc_1_data_q1 (adc_1_data_q1), + .adc_1_dovf (adc_1_dovf), + + .adc_2_valid (adc_2_valid), + .adc_2_enable_i (adc_2_enable_i0), + .adc_2_data_i (adc_2_data_i0), + .adc_2_enable_q (adc_2_enable_q0), + .adc_2_data_q (adc_2_data_q0), + .adc_2_dovf (adc_2_dovf), + + .dac_1_valid (dac_1_valid), + .dac_1_enable_i0 (dac_1_enable_i0), + .dac_1_data_i0 (dac_1_data_i0), + .dac_1_enable_q0 (dac_1_enable_q0), + .dac_1_data_q0 (dac_1_data_q0), + .dac_1_enable_i1 (dac_1_enable_i1), + .dac_1_data_i1 (dac_1_data_i1), + .dac_1_enable_q1 (dac_1_enable_q1), + .dac_1_data_q1 (dac_1_data_q1), + .dac_1_dunf (dac_1_dunf), + + .dac_2_valid (dac_2_valid), + .dac_2_enable_i0 (dac_2_enable_i0), + .dac_2_data_i0 (dac_2_data_i0), + .dac_2_enable_q0 (dac_2_enable_q0), + .dac_2_data_q0 (dac_2_data_q0), + .dac_2_dunf (dac_2_dunf), + + .delay_clk (delay_clk), + + .up_rx1_dld (up_rx1_dld), + .up_rx1_dwdata (up_rx1_dwdata), + .up_rx1_drdata (up_rx1_drdata), + .delay_rx1_rst (delay_rx1_rst), + .delay_rx1_locked (delay_rx1_locked), + + .up_rx2_dld (up_rx2_dld), + .up_rx2_dwdata (up_rx2_dwdata), + .up_rx2_drdata (up_rx2_drdata), + .delay_rx2_rst (delay_rx2_rst), + .delay_rx2_locked (delay_rx2_locked), + + // TDD interface + .tdd_sync (tdd_sync), + .tdd_sync_cntr (tdd_sync_cntr), + .tdd_rx1_rf_en (tdd_rx1_rf_en), + .tdd_tx1_rf_en (tdd_tx1_rf_en), + .tdd_if1_mode (tdd_if1_mode), + .tdd_rx2_rf_en (tdd_rx2_rf_en), + .tdd_tx2_rf_en (tdd_tx2_rf_en), + .tdd_if2_mode (tdd_if2_mode), + + .ref_clk (ref_clk), + .adc_sync_in (adc_sync_in), + .dac_sync_in (dac_sync_in), + + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + + assign adc_1_valid_i0 = adc_1_valid; + assign adc_1_valid_q0 = adc_1_valid; + assign adc_1_valid_i1 = adc_1_valid; + assign adc_1_valid_q1 = adc_1_valid; + assign adc_2_valid_i0 = adc_2_valid; + assign adc_2_valid_q0 = adc_2_valid; + + assign dac_1_valid_i0 = dac_1_valid; + assign dac_1_valid_q0 = dac_1_valid; + assign dac_1_valid_i1 = dac_1_valid; + assign dac_1_valid_q1 = dac_1_valid; + assign dac_2_valid_i0 = dac_2_valid; + assign dac_2_valid_q0 = dac_2_valid; + + assign rx1_enable = tdd_if1_mode ? tdd_rx1_rf_en : gpio_rx1_enable_in; + assign rx2_enable = tdd_if2_mode ? tdd_rx2_rf_en : gpio_rx2_enable_in; + assign tx1_enable = tdd_if1_mode ? tdd_tx1_rf_en : gpio_tx1_enable_in; + assign tx2_enable = tdd_if2_mode ? tdd_tx2_rf_en : gpio_tx2_enable_in; + + // up bus interface + up_axi #( + .AXI_ADDRESS_WIDTH(15) + ) i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr[14:0]), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr[14:0]), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s[12:0]), + .up_wdata (up_wdata_s), + .up_rdata (up_rdata_s), + .up_wack (up_wack_s), + .up_raddr (up_raddr_s[12:0]), + .up_rreq (up_rreq_s), + .up_rack (up_rack_s)); + + // Alias Rx/Tx peripherals @ 0x8000 + assign up_raddr_s[13] = 1'b0; + assign up_waddr_s[13] = 1'b0; + +endmodule diff --git a/adi_library/axi_adrv9001/axi_adrv9001.xpr b/adi_library/axi_adrv9001/axi_adrv9001.xpr new file mode 100644 index 00000000..9b597988 --- /dev/null +++ b/adi_library/axi_adrv9001/axi_adrv9001.xpr @@ -0,0 +1,725 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_adrv9001/axi_adrv9001_constr.sdc b/adi_library/axi_adrv9001/axi_adrv9001_constr.sdc new file mode 100644 index 00000000..aad83464 --- /dev/null +++ b/adi_library/axi_adrv9001/axi_adrv9001_constr.sdc @@ -0,0 +1,18 @@ +############################################################################### +## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set script_dir [file dirname [info script]] + +source "$script_dir/util_cdc_constr.tcl" + +set_false_path -from [get_registers *i_dev_if|up_enable_int*] -to [get_registers *i_dev_if|enable_up_m1*] +set_false_path -from [get_registers *i_dev_if|up_txnrx_int*] -to [get_registers *i_dev_if|txnrx_up_m1*] +set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_xfer_toggle*] -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_state_m1*] +set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_toggle*] -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_xfer_toggle_m1*] +set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_tdd_control|up_xfer_data*] -to [get_registers *up_xfer_cntrl:i_xfer_tdd_control|d_data_cntrl*] + +util_cdc_sync_bits_constr {*|sync_bits:i_rx1_ctrl_sync} +util_cdc_sync_bits_constr {*|sync_bits:i_tx1_ctrl_sync} + diff --git a/adi_library/axi_adrv9001/axi_adrv9001_constr.xdc b/adi_library/axi_adrv9001/axi_adrv9001_constr.xdc new file mode 100644 index 00000000..c3f6f3d9 --- /dev/null +++ b/adi_library/axi_adrv9001/axi_adrv9001_constr.xdc @@ -0,0 +1,41 @@ +############################################################################### +## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_false_path -quiet -from [get_cells -quiet -hier *in_toggle_d1_reg* -filter {NAME =~ *i_serdes* && IS_SEQUENTIAL}] +set_false_path -quiet -from [get_cells -quiet -hier *out_toggle_d1_reg* -filter {NAME =~ *i_serdes* && IS_SEQUENTIAL}] + +set_false_path -through [get_pins -hier *i_idelay/CNTVALUEOUT] +set_false_path -through [get_pins -hier *i_idelay/CNTVALUEIN] + +# sync bits i_rx1_ctrl_sync +set_false_path \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_rx1_ctrl_sync* && IS_SEQUENTIAL}] + +# sync bits i_tx1_ctrl_sync +set_false_path \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_tx1_ctrl_sync* && IS_SEQUENTIAL}] + +# sync event i_rx_external_sync +set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*i_rx_external_sync/out_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*i_rx_external_sync/i_sync_in/cdc_sync_stage1_reg[0]/D}] +set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*i_rx_external_sync/in_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*i_rx_external_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}] + +# sync event i_tx_external_sync +set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*i_tx_external_sync/out_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*i_tx_external_sync/i_sync_in/cdc_sync_stage1_reg[0]/D}] +set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*i_tx_external_sync/in_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*i_tx_external_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}] + +# mssi_sync +set_false_path \ + -to [get_cells -quiet -hier *mssi_sync_d_reg* \ + -filter {NAME =~ *i_*_phy* && IS_SEQUENTIAL}] diff --git a/adi_library/axi_adrv9001/axi_adrv9001_core.v b/adi_library/axi_adrv9001/axi_adrv9001_core.v new file mode 100644 index 00000000..279aac59 --- /dev/null +++ b/adi_library/axi_adrv9001/axi_adrv9001_core.v @@ -0,0 +1,727 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adrv9001_core #( + parameter ID = 0, + parameter CMOS_LVDS_N = 0, + parameter USE_RX_CLK_FOR_TX = 0, + parameter NUM_LANES = 3, + parameter DRP_WIDTH = 5, + parameter TDD_DISABLE = 0, + parameter DDS_DISABLE = 0, + parameter INDEPENDENT_1R1T_SUPPORT = 1, + parameter COMMON_2R2T_SUPPORT = 1, + parameter DISABLE_RX2_SSI = 0, + parameter DISABLE_TX2_SSI = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter EXT_SYNC = 0, + + parameter DAC_DDS_TYPE = 1, + parameter DAC_DDS_CORDIC_DW = 20, + parameter DAC_DDS_CORDIC_PHASE_DW = 18 +) ( + + // ADC interface + input rx1_clk, + output rx1_rst, + input rx1_data_valid, + input [15:0] rx1_data_i, + input [15:0] rx1_data_q, + + output rx1_single_lane, + output rx1_sdr_ddr_n, + output rx1_symb_op, + output rx1_symb_8_16b, + + input rx2_clk, + output rx2_rst, + input rx2_data_valid, + input [15:0] rx2_data_i, + input [15:0] rx2_data_q, + + output rx2_single_lane, + output rx2_sdr_ddr_n, + output rx2_symb_op, + output rx2_symb_8_16b, + + // DAC interface + input tx1_clk, + output tx1_rst, + output tx1_data_valid, + output [15:0] tx1_data_i, + output [15:0] tx1_data_q, + + output tx1_single_lane, + output tx1_sdr_ddr_n, + output tx1_symb_op, + output tx1_symb_8_16b, + + input tx2_clk, + output tx2_rst, + output tx2_data_valid, + output [15:0] tx2_data_i, + output [15:0] tx2_data_q, + + output tx2_single_lane, + output tx2_sdr_ddr_n, + output tx2_symb_op, + output tx2_symb_8_16b, + + input [ 31:0] adc_clk_ratio, + input [ 31:0] dac_clk_ratio, + + // DMA interface + output adc_1_valid, + output adc_1_enable_i0, + output [15:0] adc_1_data_i0, + output adc_1_enable_q0, + output [15:0] adc_1_data_q0, + output adc_1_enable_i1, + output [15:0] adc_1_data_i1, + output adc_1_enable_q1, + output [15:0] adc_1_data_q1, + input adc_1_dovf, + + output adc_2_valid, + output adc_2_enable_i, + output [15:0] adc_2_data_i, + output adc_2_enable_q, + output [15:0] adc_2_data_q, + input adc_2_dovf, + + output dac_1_valid, + output dac_1_enable_i0, + input [15:0] dac_1_data_i0, + output dac_1_enable_q0, + input [15:0] dac_1_data_q0, + output dac_1_enable_i1, + input [15:0] dac_1_data_i1, + output dac_1_enable_q1, + input [15:0] dac_1_data_q1, + input dac_1_dunf, + + output dac_2_valid, + output dac_2_enable_i0, + input [15:0] dac_2_data_i0, + output dac_2_enable_q0, + input [15:0] dac_2_data_q0, + input dac_2_dunf, + + // delay interface + + input delay_clk, + output delay_rx1_rst, + input delay_rx1_locked, + output delay_rx2_rst, + input delay_rx2_locked, + + output [NUM_LANES-1:0] up_rx1_dld, + output [DRP_WIDTH*NUM_LANES-1:0] up_rx1_dwdata, + input [DRP_WIDTH*NUM_LANES-1:0] up_rx1_drdata, + + output [NUM_LANES-1:0] up_rx2_dld, + output [DRP_WIDTH*NUM_LANES-1:0] up_rx2_dwdata, + input [DRP_WIDTH*NUM_LANES-1:0] up_rx2_drdata, + + // TDD interface + input tdd_sync, + output tdd_sync_cntr, + + output tdd_rx1_rf_en, + output tdd_tx1_rf_en, + output tdd_if1_mode, + output tdd_rx2_rf_en, + output tdd_tx2_rf_en, + output tdd_if2_mode, + + // external syncronization signals + input adc_sync_in, + input dac_sync_in, + input ref_clk, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack +); + + wire [7:0] up_wack_s; + wire [31:0] up_rdata_s[0:7]; + wire [7:0] up_rack_s; + + wire tx1_data_valid_A; + wire [15:0] tx1_data_i_A; + wire [15:0] tx1_data_q_A; + wire tx1_data_valid_B; + wire [15:0] tx1_data_i_B; + wire [15:0] tx1_data_q_B; + wire tx2_data_valid_A; + wire [15:0] tx2_data_i_A; + wire [15:0] tx2_data_q_A; + wire up_rx1_r1_mode; + wire rx1_r1_mode; + wire rx2_rst_loc; + wire rx2_single_lane_loc; + wire rx2_sdr_ddr_n_loc; + wire rx2_symb_op_loc; + wire rx2_symb_8_16b_loc; + wire up_tx1_r1_mode; + wire tx1_r1_mode; + wire tx2_rst_loc; + wire tx2_single_lane_loc; + wire tx2_sdr_ddr_n_loc; + wire tx2_symb_op_loc; + wire tx2_symb_8_16b_loc; + wire adc_sync; + wire adc_sync_m; + wire dac_sync_m; + wire dac_sync_out_1; + wire dac_sync_out_2; + + reg tx1_data_valid_A_d; + reg [15:0] tx1_data_i_A_d; + reg [15:0] tx1_data_q_A_d; + reg tx1_data_valid_B_d; + reg [15:0] tx1_data_i_B_d; + reg [15:0] tx1_data_q_B_d; + reg tx2_data_valid_A_d; + reg [15:0] tx2_data_i_A_d; + reg [15:0] tx2_data_q_A_d; + reg sync_adc_valid = 1'b1; + reg adc_sync_armed = 1'b0; + reg adc_sync_in_d1 = 1'b0; + reg adc_sync_d1 = 1'b0; + reg dac_sync_arm = 1'b0; + reg dac_ext_sync_arm_d = 1'b0; + reg dac_sync_in_d1 = 1'b0; + reg external_dac_sync = 1'b0; + + // rx1_r1_mode and tx1_r1_mode considered static during operation + // rx1_r1_mode should be 0 only when rx1_clk and rx2_clk have the same frequency + // tx1_r1_mode should be 0 only when tx1_clk and tx2_clk have the same frequency + + sync_bits #( + .NUM_OF_BITS (6), + .ASYNC_CLK (1) + ) i_rx1_ctrl_sync ( + .in_bits ({up_rx1_r1_mode,rx1_symb_op,rx1_symb_8_16b,rx1_sdr_ddr_n,rx1_single_lane,rx1_rst}), + .out_clk (rx2_clk), + .out_resetn (1'b1), + .out_bits ({rx1_r1_mode,rx1_symb_op_s,rx1_symb_8_16b_s,rx1_sdr_ddr_n_s,rx1_single_lane_s,rx1_rst_s})); + + sync_bits #( + .NUM_OF_BITS (6), + .ASYNC_CLK (1) + ) i_tx1_ctrl_sync ( + .in_bits ({up_tx1_r1_mode,tx1_symb_op,tx1_symb_8_16b,tx1_sdr_ddr_n,tx1_single_lane,tx1_rst}), + .out_clk (tx2_clk), + .out_resetn (1'b1), + .out_bits ({tx1_r1_mode,tx1_symb_op_s,tx1_symb_8_16b_s,tx1_sdr_ddr_n_s,tx1_single_lane_s,tx1_rst_s})); + + assign rx2_rst = rx1_r1_mode ? rx2_rst_loc : rx1_rst_s; + assign rx2_single_lane = rx1_r1_mode ? rx2_single_lane_loc : rx1_single_lane_s; + assign rx2_sdr_ddr_n = rx1_r1_mode ? rx2_sdr_ddr_n_loc : rx1_sdr_ddr_n_s; + assign rx2_symb_op = rx1_r1_mode ? rx2_symb_op_loc : rx1_symb_op_s; + assign rx2_symb_8_16b = rx1_r1_mode ? rx2_symb_8_16b_loc : rx1_symb_8_16b_s; + + assign tx2_rst = tx1_r1_mode ? tx2_rst_loc : tx1_rst_s; + assign tx2_single_lane = tx1_r1_mode ? tx2_single_lane_loc : tx1_single_lane_s; + assign tx2_sdr_ddr_n = tx1_r1_mode ? tx2_sdr_ddr_n_loc : tx1_sdr_ddr_n_s; + assign tx2_symb_op = tx1_r1_mode ? tx2_symb_op_loc : tx1_symb_op_s; + assign tx2_symb_8_16b = tx1_r1_mode ? tx2_symb_8_16b_loc : tx1_symb_8_16b_s; + assign tx1_data_valid = tx1_data_valid_A_d; + assign tx1_data_i = tx1_data_i_A_d; + assign tx1_data_q = tx1_data_q_A_d; + + assign tx2_data_valid = tx1_r1_mode ? tx2_data_valid_A_d : tx1_data_valid_B_d; + assign tx2_data_i = tx1_r1_mode ? tx2_data_i_A_d : tx1_data_i_B_d; + assign tx2_data_q = tx1_r1_mode ? tx2_data_q_A_d : tx1_data_q_B_d; + + always @(posedge tx1_clk) begin + tx1_data_valid_A_d <= tx1_data_valid_A; + tx1_data_i_A_d <= tx1_data_i_A; + tx1_data_q_A_d <= tx1_data_q_A; + end + + always @(posedge tx2_clk) begin + tx2_data_valid_A_d <= tx2_data_valid_A; + tx2_data_i_A_d <= tx2_data_i_A; + tx2_data_q_A_d <= tx2_data_q_A; + end + + // Use tx1_r1_mode as clock enable when the two clocks have different frequency + always @(posedge tx2_clk) begin + if (tx1_r1_mode==0) begin + tx1_data_valid_B_d <= tx1_data_valid_B; + tx1_data_i_B_d <= tx1_data_i_B; + tx1_data_q_B_d <= tx1_data_q_B; + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_rdata <= up_rdata_s[0] | + up_rdata_s[1] | + up_rdata_s[2] | + up_rdata_s[3] | + up_rdata_s[4] | + up_rdata_s[5] | + up_rdata_s[6] | + up_rdata_s[7]; + up_rack <= |up_rack_s; + up_wack <= |up_wack_s; + end + end + + sync_event #( + .NUM_OF_EVENTS (1), + .ASYNC_CLK (1) + ) i_rx_external_sync ( + .in_clk (ref_clk), + .in_event (adc_sync_in), + .out_clk (rx1_clk), + .out_event (adc_sync_m)); + + always @(posedge rx1_clk) begin + if (rx1_rst == 1'b1) begin + adc_sync_armed <= 1'b0; + adc_sync_in_d1 <= 1'b0; + adc_sync_d1 <= 1'b0; + sync_adc_valid <= 1'b1; + end else begin + adc_sync_in_d1 <= adc_sync_m; + adc_sync_d1 <= adc_sync; + if (~adc_sync_d1 & adc_sync) begin + sync_adc_valid <= 1'b0; + adc_sync_armed <= 1'b1; + end else if (~adc_sync_in_d1 & adc_sync_m & adc_sync_armed) begin + sync_adc_valid <= 1'b1; + adc_sync_armed <= 1'b0; + end + end + end + + sync_event #( + .NUM_OF_EVENTS (1), + .ASYNC_CLK (1) + ) i_tx_external_sync ( + .in_clk (ref_clk), + .in_event (dac_sync_in), + .out_clk (tx1_clk), + .out_event (dac_sync_m)); + + always @(posedge tx1_clk) begin + if (tx1_rst == 1'b1) begin + dac_ext_sync_arm_d <= 1'b0; + dac_sync_in_d1 <= 1'b0; + external_dac_sync <= 1'b0; + end else begin + dac_sync_in_d1 <= dac_sync_m; + dac_ext_sync_arm_d <= dac_ext_sync_arm; + if (~dac_ext_sync_arm_d & dac_ext_sync_arm) begin + external_dac_sync <= ~external_dac_sync; + end else if (~dac_sync_in_d1 & dac_sync_m) begin + external_dac_sync <= 1'b0; + end + end + end + + axi_adrv9001_rx #( + .ID (ID), + .ENABLED (1), + .CMOS_LVDS_N (CMOS_LVDS_N), + .COMMON_BASE_ADDR(6'h00), + .CHANNEL_BASE_ADDR(6'h01), + .MODE_R1 (COMMON_2R2T_SUPPORT == 0 || DISABLE_RX2_SSI == 1), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .DATAFORMAT_DISABLE (0), + .DCFILTER_DISABLE (1), + .IQCORRECTION_DISABLE (1) + ) i_rx1 ( + .adc_rst (rx1_rst), + .adc_clk (rx1_clk), + .adc_valid_A (rx1_data_valid & tdd_rx1_valid & sync_adc_valid), + .adc_data_i_A (rx1_data_i), + .adc_data_q_A (rx1_data_q), + + .adc_valid_B (rx2_data_valid & tdd_rx1_valid & sync_adc_valid), + .adc_data_i_B (rx2_data_i), + .adc_data_q_B (rx2_data_q), + + .adc_single_lane (rx1_single_lane), + .adc_sdr_ddr_n (rx1_sdr_ddr_n), + .adc_symb_op (rx1_symb_op), + .adc_symb_8_16b (rx1_symb_8_16b), + .up_adc_r1_mode (up_rx1_r1_mode), + + .adc_clk_ratio (adc_clk_ratio), + + .dac_data_valid_A (tx1_data_valid_A), + .dac_data_i_A (tx1_data_i_A), + .dac_data_q_A (tx1_data_q_A), + .dac_data_valid_B (tx1_data_valid_B), + .dac_data_i_B (tx1_data_i_B), + .dac_data_q_B (tx1_data_q_B), + + .adc_valid (adc_1_valid), + + .adc_enable_i0 (adc_1_enable_i0), + .adc_data_i0 (adc_1_data_i0[15:0]), + .adc_enable_q0 (adc_1_enable_q0), + .adc_data_q0 (adc_1_data_q0[15:0]), + + .adc_enable_i1 (adc_1_enable_i1), + .adc_data_i1 (adc_1_data_i1[15:0]), + .adc_enable_q1 (adc_1_enable_q1), + .adc_data_q1 (adc_1_data_q1[15:0]), + + .adc_dovf (adc_1_dovf), + .adc_sync (adc_sync), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + axi_adrv9001_rx #( + .ID (ID), + .ENABLED (INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_RX2_SSI != 1), + .CMOS_LVDS_N (CMOS_LVDS_N), + .COMMON_BASE_ADDR(6'h04), + .CHANNEL_BASE_ADDR(6'h05), + .MODE_R1 (1), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .DATAFORMAT_DISABLE (0), + .DCFILTER_DISABLE (1), + .IQCORRECTION_DISABLE (1) + ) i_rx2 ( + .adc_rst (rx2_rst_loc), + .adc_clk (rx2_clk), + .adc_valid_A (rx2_data_valid & tdd_rx2_valid & sync_adc_valid), + .adc_data_i_A (rx2_data_i), + .adc_data_q_A (rx2_data_q), + + .adc_valid_B (1'b0), + .adc_data_i_B (16'b0), + .adc_data_q_B (16'b0), + + .adc_single_lane (rx2_single_lane_loc), + .adc_sdr_ddr_n (rx2_sdr_ddr_n_loc), + .adc_symb_op (rx2_symb_op_loc), + .adc_symb_8_16b (rx2_symb_8_16b_loc), + + .adc_clk_ratio (adc_clk_ratio), + + .dac_data_valid_A (tx2_data_valid_A), + .dac_data_i_A (tx2_data_i_A), + .dac_data_q_A (tx2_data_q_A), + .dac_data_valid_B (1'b0), + .dac_data_i_B (16'b0), + .dac_data_q_B (16'b0), + + .adc_valid (adc_2_valid), + + .adc_enable_i0 (adc_2_enable_i), + .adc_data_i0 (adc_2_data_i[15:0]), + .adc_enable_q0 (adc_2_enable_q), + .adc_data_q0 (adc_2_data_q[15:0]), + + .adc_dovf (adc_2_dovf), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + axi_adrv9001_tx #( + .ID (ID), + .ENABLED (1), + .CMOS_LVDS_N (CMOS_LVDS_N), + .USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX), + .COMMON_BASE_ADDR ('h08), + .CHANNEL_BASE_ADDR ('h09), + .MODE_R1 (COMMON_2R2T_SUPPORT == 0 || DISABLE_RX2_SSI == 1), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .EXT_SYNC (EXT_SYNC), + .DDS_DISABLE (DDS_DISABLE), + .IQCORRECTION_DISABLE (1), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW) + ) i_tx1 ( + .dac_rst (tx1_rst), + .dac_clk (tx1_clk), + .dac_data_valid_A (tx1_data_valid_A), + .dac_data_i_A (tx1_data_i_A), + .dac_data_q_A (tx1_data_q_A), + .dac_data_valid_B (tx1_data_valid_B), + .dac_data_i_B (tx1_data_i_B), + .dac_data_q_B (tx1_data_q_B), + .dac_single_lane (tx1_single_lane), + .dac_sdr_ddr_n (tx1_sdr_ddr_n), + .dac_symb_op (tx1_symb_op), + .dac_symb_8_16b (tx1_symb_8_16b), + .up_dac_r1_mode (up_tx1_r1_mode), + .tdd_tx_valid (tdd_tx1_valid), + .dac_clk_ratio (dac_clk_ratio), + .dac_sync_in (external_dac_sync | dac_sync_out_1 | dac_sync_out_2), + .dac_sync_out (dac_sync_out_1), + .dac_ext_sync_arm (dac_ext_sync_arm), + .dac_enable_i0 (dac_1_enable_i0), + .dac_valid (dac_1_valid), + .dac_data_i0 (dac_1_data_i0[15:0]), + .dac_enable_q0 (dac_1_enable_q0), + .dac_data_q0 (dac_1_data_q0[15:0]), + .dac_enable_i1 (dac_1_enable_i1), + .dac_data_i1 (dac_1_data_i1[15:0]), + .dac_enable_q1 (dac_1_enable_q1), + .dac_data_q1 (dac_1_data_q1[15:0]), + .dac_dunf (dac_1_dunf), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + axi_adrv9001_tx #( + .ID (ID), + .ENABLED (INDEPENDENT_1R1T_SUPPORT == 1 && DISABLE_TX2_SSI != 1), + .CMOS_LVDS_N (CMOS_LVDS_N), + .USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX), + .COMMON_BASE_ADDR ('h10), + .CHANNEL_BASE_ADDR ('h11), + .MODE_R1 (1), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .EXT_SYNC (EXT_SYNC), + .DDS_DISABLE (DDS_DISABLE), + .IQCORRECTION_DISABLE (1), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW) + ) i_tx2 ( + .dac_rst (tx2_rst_loc), + .dac_clk (tx2_clk), + .dac_data_valid_A (tx2_data_valid_A), + .dac_data_i_A (tx2_data_i_A), + .dac_data_q_A (tx2_data_q_A), + .dac_data_valid_B (), + .dac_data_i_B (), + .dac_data_q_B (), + .dac_single_lane (tx2_single_lane_loc), + .dac_sdr_ddr_n (tx2_sdr_ddr_n_loc), + .dac_symb_op (tx2_symb_op_loc), + .dac_symb_8_16b (tx2_symb_8_16b_loc), + .dac_sync_in (external_dac_sync | dac_sync_out_1 | dac_sync_out_2), + .dac_sync_out (dac_sync_out_2), + .dac_valid (dac_2_valid), + .dac_enable_i0 (dac_2_enable_i0), + .dac_data_i0 (dac_2_data_i0[15:0]), + .dac_enable_q0 (dac_2_enable_q0), + .dac_data_q0 (dac_2_data_q0[15:0]), + .dac_enable_i1 (), + .dac_data_i1 (16'b0), + .dac_enable_q1 (), + .dac_data_q1 (16'b0), + .dac_dunf (dac_2_dunf), + .tdd_tx_valid (tdd_tx2_valid), + .dac_clk_ratio (dac_clk_ratio), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[3]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[3]), + .up_rack (up_rack_s[3])); + + // adc delay control + up_delay_cntrl #( + .DATA_WIDTH(NUM_LANES), + .DRP_WIDTH(DRP_WIDTH), + .BASE_ADDRESS(6'h02) + ) i_delay_cntrl_rx1 ( + .delay_clk (delay_clk), + .delay_rst (delay_rx1_rst), + .delay_locked (delay_rx1_locked), + .up_dld (up_rx1_dld), + .up_dwdata (up_rx1_dwdata), + .up_drdata (up_rx1_drdata), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[4]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[4]), + .up_rack (up_rack_s[4])); + + up_delay_cntrl #( + .DATA_WIDTH(NUM_LANES), + .DRP_WIDTH(DRP_WIDTH), + .DISABLE(DISABLE_RX2_SSI), + .BASE_ADDRESS(6'h06) + ) i_delay_cntrl_rx2 ( + .delay_clk (delay_clk), + .delay_rst (delay_rx2_rst), + .delay_locked (delay_rx2_locked), + .up_dld (up_rx2_dld), + .up_dwdata (up_rx2_dwdata), + .up_drdata (up_rx2_drdata), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[5]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[5]), + .up_rack (up_rack_s[5])); + + wire tdd_rx2_rf_en_loc; + wire tdd_tx2_rf_en_loc; + wire tdd_if2_mode_loc; + + axi_adrv9001_tdd #( + .BASE_ADDRESS (6'h12), + .ENABLED (TDD_DISABLE==0) + ) i_tdd_1 ( + .clk (rx1_clk), + .rst (rx1_rst), + .tdd_rx_vco_en (), + .tdd_tx_vco_en (), + .tdd_rx_rf_en (tdd_rx1_rf_en), + .tdd_tx_rf_en (tdd_tx1_rf_en), + .tdd_enabled (tdd_if1_mode), + .tdd_status (8'h0), + .tdd_sync (tdd_sync), + .tdd_sync_cntr (tdd_sync_cntr1), + .tdd_tx_valid (tdd_tx1_valid), + .tdd_rx_valid (tdd_rx1_valid), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[6]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[6]), + .up_rack (up_rack_s[6])); + + axi_adrv9001_tdd #( + .BASE_ADDRESS (6'h13), + .ENABLED(TDD_DISABLE == 0 && (DISABLE_RX2_SSI == 0 || DISABLE_TX2_SSI == 0)) + ) i_tdd_2 ( + .clk (rx2_clk), + .rst (rx2_rst_loc), + .tdd_rx_vco_en (), + .tdd_tx_vco_en (), + .tdd_rx_rf_en (tdd_rx2_rf_en_loc), + .tdd_tx_rf_en (tdd_tx2_rf_en_loc), + .tdd_enabled (tdd_if2_mode_loc), + .tdd_status (8'h0), + .tdd_sync (tdd_sync), + .tdd_sync_cntr (tdd_sync_cntr2), + .tdd_tx_valid (tdd_tx2_valid), + .tdd_rx_valid (tdd_rx2_valid), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[7]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[7]), + .up_rack (up_rack_s[7])); + + assign tdd_rx2_rf_en = rx1_r1_mode ? tdd_rx2_rf_en_loc : tdd_rx1_rf_en; + assign tdd_tx2_rf_en = tx1_r1_mode ? tdd_tx2_rf_en_loc : tdd_tx1_rf_en; + assign tdd_if2_mode = tx1_r1_mode||rx1_r1_mode ? tdd_if2_mode_loc : tdd_if1_mode; + + assign tdd_sync_cntr = tdd_sync_cntr1 | tdd_sync_cntr2; + +endmodule diff --git a/adi_library/axi_adrv9001/axi_adrv9001_hw.tcl b/adi_library/axi_adrv9001/axi_adrv9001_hw.tcl new file mode 100644 index 00000000..f12e76a7 --- /dev/null +++ b/adi_library/axi_adrv9001/axi_adrv9001_hw.tcl @@ -0,0 +1,252 @@ +############################################################################### +## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +package require quartus::device + +source ../../scripts/adi_env.tcl +source ../scripts/adi_ip_intel.tcl + +ad_ip_create axi_adrv9001 {AXI ADRV9001 Interface} axi_adrv9001_elab +set_module_property VALIDATION_CALLBACK info_param_validate + +ad_ip_files axi_adrv9001 [list\ + "$ad_hdl_dir/library/intel/common/ad_mul.v" \ + "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine.v" \ + "$ad_hdl_dir/library/common/ad_dds_1.v" \ + "$ad_hdl_dir/library/common/ad_dds_2.v" \ + "$ad_hdl_dir/library/common/ad_dds.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_tdd_cntrl.v" \ + "$ad_hdl_dir/library/common/ad_tdd_control.v" \ + "$ad_hdl_dir/library/common/ad_addsub.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/up_dac_common.v" \ + "$ad_hdl_dir/library/common/up_dac_channel.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ + "$ad_hdl_dir/library/common/ad_pngen.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc" \ + "$ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc" \ + "$ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc" \ + "$ad_hdl_dir/library/intel/common/up_rst_constr.sdc" \ + "$ad_hdl_dir/library/util_cdc/sync_bits.v" \ + "$ad_hdl_dir/library/util_cdc/util_cdc_constr.tcl" \ + "intel/adrv9001_rx.v" \ + "intel/adrv9001_tx.v" \ + "adrv9001_pack.v" \ + "adrv9001_aligner4.v" \ + "adrv9001_aligner8.v" \ + "adrv9001_rx_link.v" \ + "adrv9001_tx_link.v" \ + "axi_adrv9001_rx.v" \ + "axi_adrv9001_rx_channel.v" \ + "axi_adrv9001_if.v" \ + "axi_adrv9001_tx.v" \ + "axi_adrv9001_tx_channel.v" \ + "axi_adrv9001_core.v" \ + "axi_adrv9001_constr.sdc" \ + "axi_adrv9001_tdd.v" \ + "axi_adrv9001.v" ] + +# parameters + +ad_ip_parameter ID INTEGER 0 +ad_ip_parameter CMOS_LVDS_N INTEGER 0 +ad_ip_parameter IO_DELAY_GROUP STRING {dev_if_delay_group} + +adi_add_auto_fpga_spec_params + +# interfaces + +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn + +#ad_interface clock delay_clk input 1 +ad_interface clock adc_1_clk output 1 +ad_interface clock adc_2_clk output 1 +ad_interface clock dac_1_clk output 1 +ad_interface clock dac_2_clk output 1 + +ad_interface reset adc_1_rst output 1 if_adc_1_clk +ad_interface reset adc_2_rst output 1 if_adc_2_clk +ad_interface reset dac_1_rst output 1 if_dac_1_clk +ad_interface reset dac_2_rst output 1 if_dac_2_clk + +add_interface adc_1_ch_0 conduit end +add_interface_port adc_1_ch_0 adc_1_enable_i0 enable Output 1 +add_interface_port adc_1_ch_0 adc_1_valid_i0 valid Output 1 +add_interface_port adc_1_ch_0 adc_1_data_i0 data Output 16 + +add_interface adc_1_ch_1 conduit end +add_interface_port adc_1_ch_1 adc_1_enable_q0 enable Output 1 +add_interface_port adc_1_ch_1 adc_1_valid_q0 valid Output 1 +add_interface_port adc_1_ch_1 adc_1_data_q0 data Output 16 + +add_interface adc_1_ch_2 conduit end +add_interface_port adc_1_ch_2 adc_1_enable_i1 enable Output 1 +add_interface_port adc_1_ch_2 adc_1_valid_i1 valid Output 1 +add_interface_port adc_1_ch_2 adc_1_data_i1 data Output 16 + +add_interface adc_1_ch_3 conduit end +add_interface_port adc_1_ch_3 adc_1_enable_q1 enable Output 1 +add_interface_port adc_1_ch_3 adc_1_valid_q1 valid Output 1 +add_interface_port adc_1_ch_3 adc_1_data_q1 data Output 16 + +ad_interface signal adc_1_dovf input 1 ovf + +set_interface_property adc_1_ch_0 associatedClock if_adc_1_clk +set_interface_property adc_1_ch_1 associatedClock if_adc_1_clk +set_interface_property adc_1_ch_2 associatedClock if_adc_1_clk +set_interface_property adc_1_ch_3 associatedClock if_adc_1_clk +set_interface_property adc_1_ch_0 associatedReset adc_1_rst +set_interface_property adc_1_ch_1 associatedReset adc_1_rst +set_interface_property adc_1_ch_2 associatedReset adc_1_rst +set_interface_property adc_1_ch_3 associatedReset adc_1_rst + +add_interface adc_2_ch_0 conduit end +add_interface_port adc_2_ch_0 adc_2_enable_i0 enable Output 1 +add_interface_port adc_2_ch_0 adc_2_valid_i0 valid Output 1 +add_interface_port adc_2_ch_0 adc_2_data_i0 data Output 16 + +add_interface adc_2_ch_1 conduit end +add_interface_port adc_2_ch_1 adc_2_enable_q0 enable Output 1 +add_interface_port adc_2_ch_1 adc_2_valid_q0 valid Output 1 +add_interface_port adc_2_ch_1 adc_2_data_q0 data Output 16 + +ad_interface signal adc_2_dovf input 1 ovf + +set_interface_property adc_2_ch_0 associatedClock if_adc_2_clk +set_interface_property adc_2_ch_1 associatedClock if_adc_2_clk +set_interface_property adc_2_ch_0 associatedReset adc_2_rst +set_interface_property adc_2_ch_1 associatedReset adc_2_rst + +# DAC interfaces +add_interface dac_1_ch_0 conduit end +add_interface_port dac_1_ch_0 dac_1_enable_i0 enable Output 1 +add_interface_port dac_1_ch_0 dac_1_valid_i0 valid Output 1 +add_interface_port dac_1_ch_0 dac_1_data_i0 data Input 16 + +add_interface dac_1_ch_1 conduit end +add_interface_port dac_1_ch_1 dac_1_enable_q0 enable Output 1 +add_interface_port dac_1_ch_1 dac_1_valid_q0 valid Output 1 +add_interface_port dac_1_ch_1 dac_1_data_q0 data Input 16 + +add_interface dac_1_ch_2 conduit end +add_interface_port dac_1_ch_2 dac_1_enable_i1 enable Output 1 +add_interface_port dac_1_ch_2 dac_1_valid_i1 valid Output 1 +add_interface_port dac_1_ch_2 dac_1_data_i1 data Input 16 + +add_interface dac_1_ch_3 conduit end +add_interface_port dac_1_ch_3 dac_1_enable_q1 enable Output 1 +add_interface_port dac_1_ch_3 dac_1_valid_q1 valid Output 1 +add_interface_port dac_1_ch_3 dac_1_data_q1 data Input 16 + +set_interface_property dac_1_ch_0 associatedClock if_dac_1_clk +set_interface_property dac_1_ch_1 associatedClock if_dac_1_clk +set_interface_property dac_1_ch_2 associatedClock if_dac_1_clk +set_interface_property dac_1_ch_3 associatedClock if_dac_1_clk +set_interface_property dac_1_ch_0 associatedReset dac_1_rst +set_interface_property dac_1_ch_1 associatedReset dac_1_rst +set_interface_property dac_1_ch_2 associatedReset dac_1_rst +set_interface_property dac_1_ch_3 associatedReset dac_1_rst + +ad_interface signal dac_1_dunf input 1 unf + +add_interface dac_2_ch_0 conduit end +add_interface_port dac_2_ch_0 dac_2_enable_i0 enable Output 1 +add_interface_port dac_2_ch_0 dac_2_valid_i0 valid Output 1 +add_interface_port dac_2_ch_0 dac_2_data_i0 data Input 16 + +add_interface dac_2_ch_1 conduit end +add_interface_port dac_2_ch_1 dac_2_enable_q0 enable Output 1 +add_interface_port dac_2_ch_1 dac_2_valid_q0 valid Output 1 +add_interface_port dac_2_ch_1 dac_2_data_q0 data Input 16 + +ad_interface signal dac_2_dunf input 1 unf + +set_interface_property dac_2_ch_0 associatedClock if_dac_2_clk +set_interface_property dac_2_ch_1 associatedClock if_dac_2_clk +set_interface_property dac_2_ch_0 associatedReset dac_2_rst +set_interface_property dac_2_ch_1 associatedReset dac_2_rst + +add_interface tdd_if conduit end +add_interface_port tdd_if gpio_rx1_enable_in rx1_enable_in Input 1 +add_interface_port tdd_if gpio_rx2_enable_in rx2_enable_in Input 1 +add_interface_port tdd_if gpio_tx1_enable_in tx1_enable_in Input 1 +add_interface_port tdd_if gpio_tx2_enable_in tx2_enable_in Input 1 +add_interface_port tdd_if tdd_sync tdd_sync_in Input 1 + +# updates + +proc axi_adrv9001_elab {} { + set m_fpga_technology [get_parameter_value "FPGA_TECHNOLOGY"] + set m_cmos_lvds_n [get_parameter_value "CMOS_LVDS_N"] + + add_hdl_instance adrv9001_gpio_in altera_gpio + set_instance_parameter_value adrv9001_gpio_in {DEVICE_FAMILY} {Arria 10} + set_instance_parameter_value adrv9001_gpio_in {PIN_TYPE_GUI} {Input} + set_instance_parameter_value adrv9001_gpio_in {SIZE} {1} + set_instance_parameter_value adrv9001_gpio_in {gui_io_reg_mode} {DDIO} + + add_hdl_instance adrv9001_gpio_out altera_gpio + set_instance_parameter_value adrv9001_gpio_out {DEVICE_FAMILY} {Arria 10} + set_instance_parameter_value adrv9001_gpio_out {PIN_TYPE_GUI} {Output} + set_instance_parameter_value adrv9001_gpio_out {SIZE} {1} + set_instance_parameter_value adrv9001_gpio_out {gui_io_reg_mode} {DDIO} + + add_hdl_instance periphery_clk_buf altclkctrl + set_instance_parameter_value periphery_clk_buf {DEVICE_FAMILY} {Arria 10} + set_instance_parameter_value periphery_clk_buf {CLOCK_TYPE} {Periphery Clock} + + add_interface device_if conduit end + set_interface_property device_if associatedClock none + set_interface_property device_if associatedReset none + + if {$m_cmos_lvds_n == 1} { + + add_interface_port device_if rx1_dclk_in_p_dclk_in rx1_dclk_in_p_dclk_in Input 1 + add_interface_port device_if rx1_idata_in_n_idata0 rx1_idata_in_n_idata0 Input 1 + add_interface_port device_if rx1_idata_in_p_idata1 rx1_idata_in_p_idata1 Input 1 + add_interface_port device_if rx1_qdata_in_n_qdata2 rx1_qdata_in_n_qdata2 Input 1 + add_interface_port device_if rx1_qdata_in_p_qdata3 rx1_qdata_in_p_qdata3 Input 1 + add_interface_port device_if rx1_strobe_in_p_strobe_in rx1_strobe_in_p_strobe_in Input 1 + add_interface_port device_if rx1_enable rx1_enable Output 1 + + add_interface_port device_if rx2_dclk_in_p_dclk_in rx2_dclk_in_p_dclk_in Input 1 + add_interface_port device_if rx2_idata_in_n_idata0 rx2_idata_in_n_idata0 Input 1 + add_interface_port device_if rx2_idata_in_p_idata1 rx2_idata_in_p_idata1 Input 1 + add_interface_port device_if rx2_qdata_in_n_qdata2 rx2_qdata_in_n_qdata2 Input 1 + add_interface_port device_if rx2_qdata_in_p_qdata3 rx2_qdata_in_p_qdata3 Input 1 + add_interface_port device_if rx2_strobe_in_p_strobe_in rx2_strobe_in_p_strobe_in Input 1 + add_interface_port device_if rx2_enable rx2_enable Output 1 + + add_interface_port device_if tx1_dclk_out_p_dclk_out tx1_dclk_out_p_dclk_out Output 1 + add_interface_port device_if tx1_dclk_in_p_dclk_in tx1_dclk_in_p_dclk_in Input 1 + add_interface_port device_if tx1_idata_out_n_idata0 tx1_idata_out_n_idata0 Output 1 + add_interface_port device_if tx1_idata_out_p_idata1 tx1_idata_out_p_idata1 Output 1 + add_interface_port device_if tx1_qdata_out_n_qdata2 tx1_qdata_out_n_qdata2 Output 1 + add_interface_port device_if tx1_qdata_out_p_qdata3 tx1_qdata_out_p_qdata3 Output 1 + add_interface_port device_if tx1_strobe_out_p_strobe_out tx1_strobe_out_p_strobe_out Output 1 + add_interface_port device_if tx1_enable tx1_enable Output 1 + + add_interface_port device_if tx2_dclk_out_p_dclk_out tx2_dclk_out_p_dclk_out Output 1 + add_interface_port device_if tx2_dclk_in_p_dclk_in tx2_dclk_in_p_dclk_in Input 1 + add_interface_port device_if tx2_idata_out_n_idata0 tx2_idata_out_n_idata0 Output 1 + add_interface_port device_if tx2_idata_out_p_idata1 tx2_idata_out_p_idata1 Output 1 + add_interface_port device_if tx2_qdata_out_n_qdata2 tx2_qdata_out_n_qdata2 Output 1 + add_interface_port device_if tx2_qdata_out_p_qdata3 tx2_qdata_out_p_qdata3 Output 1 + add_interface_port device_if tx2_strobe_out_p_strobe_out tx2_strobe_out_p_strobe_out Output 1 + add_interface_port device_if tx2_enable tx2_enable Output 1 + } +} + diff --git a/adi_library/axi_adrv9001/axi_adrv9001_if.v b/adi_library/axi_adrv9001/axi_adrv9001_if.v new file mode 100644 index 00000000..bfe46777 --- /dev/null +++ b/adi_library/axi_adrv9001/axi_adrv9001_if.v @@ -0,0 +1,487 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adrv9001_if #( + parameter CMOS_LVDS_N = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter NUM_LANES = 3, + parameter DRP_WIDTH = 5, + parameter RX_USE_BUFG = 0, + parameter TX_USE_BUFG = 0, + parameter DISABLE_RX2_SSI = 0, + parameter DISABLE_TX2_SSI = 0, + parameter IODELAY_CTRL = 1, + parameter IODELAY_ENABLE = 1, + parameter IO_DELAY_GROUP = "dev_if_delay_group", + parameter USE_RX_CLK_FOR_TX = 0 +) ( + input ref_clk, + input tx_output_enable, + + input mssi_sync, + + // device interface + input rx1_dclk_in_n_NC, + input rx1_dclk_in_p_dclk_in, + input rx1_idata_in_n_idata0, + input rx1_idata_in_p_idata1, + input rx1_qdata_in_n_qdata2, + input rx1_qdata_in_p_qdata3, + input rx1_strobe_in_n_NC, + input rx1_strobe_in_p_strobe_in, + + input rx2_dclk_in_n_NC, + input rx2_dclk_in_p_dclk_in, + input rx2_idata_in_n_idata0, + input rx2_idata_in_p_idata1, + input rx2_qdata_in_n_qdata2, + input rx2_qdata_in_p_qdata3, + input rx2_strobe_in_n_NC, + input rx2_strobe_in_p_strobe_in, + + output tx1_dclk_out_n_NC, + output tx1_dclk_out_p_dclk_out, + input tx1_dclk_in_n_NC, + input tx1_dclk_in_p_dclk_in, + output tx1_idata_out_n_idata0, + output tx1_idata_out_p_idata1, + output tx1_qdata_out_n_qdata2, + output tx1_qdata_out_p_qdata3, + output tx1_strobe_out_n_NC, + output tx1_strobe_out_p_strobe_out, + + output tx2_dclk_out_n_NC, + output tx2_dclk_out_p_dclk_out, + input tx2_dclk_in_n_NC, + input tx2_dclk_in_p_dclk_in, + output tx2_idata_out_n_idata0, + output tx2_idata_out_p_idata1, + output tx2_qdata_out_n_qdata2, + output tx2_qdata_out_p_qdata3, + output tx2_strobe_out_n_NC, + output tx2_strobe_out_p_strobe_out, + + // delay interface (for IDELAY macros) + input delay_clk, + input delay_rx1_rst, + input delay_rx2_rst, + output delay_rx1_locked, + output delay_rx2_locked, + + input up_clk, + + input [NUM_LANES-1:0] up_rx1_dld, + input [DRP_WIDTH*NUM_LANES-1:0] up_rx1_dwdata, + output [DRP_WIDTH*NUM_LANES-1:0] up_rx1_drdata, + + input [NUM_LANES-1:0] up_rx2_dld, + input [DRP_WIDTH*NUM_LANES-1:0] up_rx2_dwdata, + output [DRP_WIDTH*NUM_LANES-1:0] up_rx2_drdata, + + // upper layer data interface + + output [ 31:0] adc_clk_ratio, + output [ 31:0] dac_clk_ratio, + + output rx1_clk, + input rx1_rst, + output rx1_data_valid, + output [15:0] rx1_data_i, + output [15:0] rx1_data_q, + + input rx1_single_lane, + input rx1_sdr_ddr_n, + input rx1_symb_op, + input rx1_symb_8_16b, + + output rx2_clk, + input rx2_rst, + output rx2_data_valid, + output [15:0] rx2_data_i, + output [15:0] rx2_data_q, + + input rx2_single_lane, + input rx2_sdr_ddr_n, + input rx2_symb_op, + input rx2_symb_8_16b, + + output tx1_clk, + input tx1_rst, + input tx1_data_valid, + input [15:0] tx1_data_i, + input [15:0] tx1_data_q, + + input tx1_single_lane, + input tx1_sdr_ddr_n, + input tx1_symb_op, + input tx1_symb_8_16b, + + output tx2_clk, + input tx2_rst, + input tx2_data_valid, + input [15:0] tx2_data_i, + input [15:0] tx2_data_q, + + input tx2_single_lane, + input tx2_sdr_ddr_n, + input tx2_symb_op, + input tx2_symb_8_16b +); + + // Tx has an extra lane to drive the clock + localparam TX_NUM_LANES = NUM_LANES + 1; + + wire adc_1_clk_div; + wire [7:0] adc_1_data_0; + wire [7:0] adc_1_data_1; + wire [7:0] adc_1_data_2; + wire [7:0] adc_1_data_3; + wire [7:0] adc_1_data_strobe; + wire adc_1_clk; + wire adc_1_valid; + wire adc_1_ssi_rst; + + wire adc_2_clk_div; + wire [7:0] adc_2_data_0; + wire [7:0] adc_2_data_1; + wire [7:0] adc_2_data_2; + wire [7:0] adc_2_data_3; + wire [7:0] adc_2_data_strobe; + wire adc_2_clk; + wire adc_2_valid; + wire adc_2_ssi_rst; + + wire dac_1_clk_div; + wire [7:0] dac_1_data_0; + wire [7:0] dac_1_data_1; + wire [7:0] dac_1_data_2; + wire [7:0] dac_1_data_3; + wire [7:0] dac_1_data_strobe; + wire [7:0] dac_1_data_clk; + wire dac_1_data_valid; + + wire dac_2_clk_div; + wire [7:0] dac_2_data_0; + wire [7:0] dac_2_data_1; + wire [7:0] dac_2_data_2; + wire [7:0] dac_2_data_3; + wire [7:0] dac_2_data_strobe; + wire [7:0] dac_2_data_clk; + wire dac_2_data_valid; + + wire rx_ssi_sync_out; + + adrv9001_rx #( + .CMOS_LVDS_N (CMOS_LVDS_N), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .NUM_LANES (NUM_LANES), + .DRP_WIDTH (DRP_WIDTH), + .IODELAY_CTRL (IODELAY_CTRL), + .IODELAY_ENABLE (IODELAY_ENABLE), + .USE_BUFG (RX_USE_BUFG), + .IO_DELAY_GROUP ({IO_DELAY_GROUP,"_rx"}) + ) i_rx_1_phy ( + .rx_dclk_in_n_NC (rx1_dclk_in_n_NC), + .rx_dclk_in_p_dclk_in (rx1_dclk_in_p_dclk_in), + .rx_idata_in_n_idata0 (rx1_idata_in_n_idata0), + .rx_idata_in_p_idata1 (rx1_idata_in_p_idata1), + .rx_qdata_in_n_qdata2 (rx1_qdata_in_n_qdata2), + .rx_qdata_in_p_qdata3 (rx1_qdata_in_p_qdata3), + .rx_strobe_in_n_NC (rx1_strobe_in_n_NC), + .rx_strobe_in_p_strobe_in (rx1_strobe_in_p_strobe_in), + + .adc_rst (rx1_rst), + .adc_clk (adc_1_clk), + .adc_clk_div (adc_1_clk_div), + .adc_data_0 (adc_1_data_0), + .adc_data_1 (adc_1_data_1), + .adc_data_2 (adc_1_data_2), + .adc_data_3 (adc_1_data_3), + .adc_data_strobe (adc_1_data_strobe), + .adc_valid (adc_1_valid), + + .adc_clk_ratio (adc_clk_ratio), + + .up_clk (up_clk), + .up_adc_dld (up_rx1_dld), + .up_adc_dwdata (up_rx1_dwdata), + .up_adc_drdata (up_rx1_drdata), + .delay_clk (delay_clk), + .delay_rst (delay_rx1_rst), + .delay_locked (delay_rx1_locked), + + .mssi_sync (mssi_sync), + .ssi_sync_out (rx_ssi_sync_out), + .ssi_sync_in (rx_ssi_sync_out), + .ssi_rst (adc_1_ssi_rst)); + + adrv9001_rx_link #( + .CMOS_LVDS_N (CMOS_LVDS_N) + ) i_rx_1_link ( + .adc_rst (rx1_rst), + .adc_clk_div (adc_1_clk_div), + .adc_data_0 (adc_1_data_0), + .adc_data_1 (adc_1_data_1), + .adc_data_2 (adc_1_data_2), + .adc_data_3 (adc_1_data_3), + .adc_data_strobe (adc_1_data_strobe), + .adc_valid (adc_1_valid), + // ADC interface + .rx_clk (rx1_clk), + .rx_data_valid (rx1_data_valid), + .rx_data_i (rx1_data_i), + .rx_data_q (rx1_data_q), + .rx_single_lane (rx1_single_lane), + .rx_sdr_ddr_n (rx1_sdr_ddr_n), + .rx_symb_op (rx1_symb_op), + .rx_symb_8_16b (rx1_symb_8_16b)); + + generate if (DISABLE_RX2_SSI == 0) begin + adrv9001_rx #( + .CMOS_LVDS_N (CMOS_LVDS_N), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .NUM_LANES (NUM_LANES), + .DRP_WIDTH (DRP_WIDTH), + .IODELAY_CTRL (0), + .IODELAY_ENABLE (IODELAY_ENABLE), + .USE_BUFG (RX_USE_BUFG), + .IO_DELAY_GROUP ({IO_DELAY_GROUP,"_rx"}) + ) i_rx_2_phy ( + .rx_dclk_in_n_NC (rx2_dclk_in_n_NC), + .rx_dclk_in_p_dclk_in (rx2_dclk_in_p_dclk_in), + .rx_idata_in_n_idata0 (rx2_idata_in_n_idata0), + .rx_idata_in_p_idata1 (rx2_idata_in_p_idata1), + .rx_qdata_in_n_qdata2 (rx2_qdata_in_n_qdata2), + .rx_qdata_in_p_qdata3 (rx2_qdata_in_p_qdata3), + .rx_strobe_in_n_NC (rx2_strobe_in_n_NC), + .rx_strobe_in_p_strobe_in (rx2_strobe_in_p_strobe_in), + + .adc_rst (rx2_rst), + .adc_clk (adc_2_clk), + .adc_clk_div (adc_2_clk_div), + .adc_data_0 (adc_2_data_0), + .adc_data_1 (adc_2_data_1), + .adc_data_2 (adc_2_data_2), + .adc_data_3 (adc_2_data_3), + .adc_data_strobe (adc_2_data_strobe), + .adc_valid (adc_2_valid), + + .up_clk (up_clk), + .up_adc_dld (up_rx2_dld), + .up_adc_dwdata (up_rx2_dwdata), + .up_adc_drdata (up_rx2_drdata), + .delay_clk (delay_clk), + .delay_rst (delay_rx2_rst), + .delay_locked (delay_rx2_locked), + + .mssi_sync (1'b0), + .ssi_sync_out (), + .ssi_sync_in (rx_ssi_sync_out), + .ssi_rst (adc_2_ssi_rst)); + + adrv9001_rx_link #( + .CMOS_LVDS_N (CMOS_LVDS_N) + ) i_rx_2_link ( + .adc_rst (rx2_rst), + .adc_clk_div (adc_2_clk_div), + .adc_data_0 (adc_2_data_0), + .adc_data_1 (adc_2_data_1), + .adc_data_2 (adc_2_data_2), + .adc_data_3 (adc_2_data_3), + .adc_data_strobe (adc_2_data_strobe), + .adc_valid (adc_2_valid), + // ADC interface + .rx_clk (rx2_clk), + .rx_data_valid (rx2_data_valid), + .rx_data_i (rx2_data_i), + .rx_data_q (rx2_data_q), + .rx_single_lane (rx2_single_lane), + .rx_sdr_ddr_n (rx2_sdr_ddr_n), + .rx_symb_op (rx2_symb_op), + .rx_symb_8_16b (rx2_symb_8_16b)); + end else begin + assign delay_rx2_locked = 1'b1; + assign up_rx2_drdata = 'h0; + assign rx2_clk = 1'b0; + assign rx2_data_valid = 1'b0; + assign rx2_data_i = 16'b0; + assign rx2_data_q = 16'b0; + end + endgenerate + + adrv9001_tx #( + .CMOS_LVDS_N (CMOS_LVDS_N), + .NUM_LANES (TX_NUM_LANES), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .USE_BUFG (TX_USE_BUFG), + .USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX) + ) i_tx_1_phy ( + .ref_clk (ref_clk), + .up_clk (up_clk), + + .tx_output_enable(tx_output_enable), + + .tx_dclk_out_n_NC (tx1_dclk_out_n_NC), + .tx_dclk_out_p_dclk_out (tx1_dclk_out_p_dclk_out), + .tx_dclk_in_n_NC (tx1_dclk_in_n_NC), + .tx_dclk_in_p_dclk_in (tx1_dclk_in_p_dclk_in), + .tx_idata_out_n_idata0 (tx1_idata_out_n_idata0), + .tx_idata_out_p_idata1 (tx1_idata_out_p_idata1), + .tx_qdata_out_n_qdata2 (tx1_qdata_out_n_qdata2), + .tx_qdata_out_p_qdata3 (tx1_qdata_out_p_qdata3), + .tx_strobe_out_n_NC (tx1_strobe_out_n_NC), + .tx_strobe_out_p_strobe_out (tx1_strobe_out_p_strobe_out), + + .rx_clk_div (adc_1_clk_div), + .rx_clk (adc_1_clk), + .rx_ssi_rst (adc_1_ssi_rst), + + .dac_rst (tx1_rst), + .dac_clk_div (dac_1_clk_div), + + .dac_data_0 (dac_1_data_0), + .dac_data_1 (dac_1_data_1), + .dac_data_2 (dac_1_data_2), + .dac_data_3 (dac_1_data_3), + .dac_data_strb (dac_1_data_strobe), + .dac_data_clk (dac_1_data_clk), + .dac_data_valid (dac_1_data_valid), + + .dac_clk_ratio (dac_clk_ratio), + + .mssi_sync (mssi_sync)); + + adrv9001_tx_link #( + .CMOS_LVDS_N (CMOS_LVDS_N), + .CLK_DIV_IS_FAST_CLK (FPGA_TECHNOLOGY >= 100) + ) i_tx_1_link ( + .dac_clk_div (dac_1_clk_div), + .dac_data_0 (dac_1_data_0), + .dac_data_1 (dac_1_data_1), + .dac_data_2 (dac_1_data_2), + .dac_data_3 (dac_1_data_3), + .dac_data_strobe (dac_1_data_strobe), + .dac_data_clk (dac_1_data_clk), + .dac_data_valid (dac_1_data_valid), + // DAC interface + .tx_clk (tx1_clk), + .tx_rst (tx1_rst), + .tx_data_valid (tx1_data_valid), + .tx_data_i (tx1_data_i), + .tx_data_q (tx1_data_q), + .tx_sdr_ddr_n (tx1_sdr_ddr_n), + .tx_single_lane (tx1_single_lane), + .tx_symb_op (tx1_symb_op), + .tx_symb_8_16b (tx1_symb_8_16b)); + + generate if (DISABLE_TX2_SSI == 0) begin + adrv9001_tx #( + .CMOS_LVDS_N (CMOS_LVDS_N), + .NUM_LANES (TX_NUM_LANES), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .USE_BUFG (TX_USE_BUFG), + .USE_RX_CLK_FOR_TX (USE_RX_CLK_FOR_TX) + ) i_tx_2_phy ( + .ref_clk (ref_clk), + .up_clk (up_clk), + + .tx_output_enable(tx_output_enable), + + .tx_dclk_out_n_NC (tx2_dclk_out_n_NC), + .tx_dclk_out_p_dclk_out (tx2_dclk_out_p_dclk_out), + .tx_dclk_in_n_NC (tx2_dclk_in_n_NC), + .tx_dclk_in_p_dclk_in (tx2_dclk_in_p_dclk_in), + .tx_idata_out_n_idata0 (tx2_idata_out_n_idata0), + .tx_idata_out_p_idata1 (tx2_idata_out_p_idata1), + .tx_qdata_out_n_qdata2 (tx2_qdata_out_n_qdata2), + .tx_qdata_out_p_qdata3 (tx2_qdata_out_p_qdata3), + .tx_strobe_out_n_NC (tx2_strobe_out_n_NC), + .tx_strobe_out_p_strobe_out (tx2_strobe_out_p_strobe_out), + + .rx_clk_div (adc_2_clk_div), + .rx_clk (adc_2_clk), + .rx_ssi_rst (adc_2_ssi_rst), + + .dac_rst (tx2_rst), + .dac_clk_div (dac_2_clk_div), + + .dac_data_0 (dac_2_data_0), + .dac_data_1 (dac_2_data_1), + .dac_data_2 (dac_2_data_2), + .dac_data_3 (dac_2_data_3), + .dac_data_strb (dac_2_data_strobe), + .dac_data_clk (dac_2_data_clk), + .dac_data_valid (dac_2_data_valid), + + .mssi_sync (mssi_sync)); + + adrv9001_tx_link #( + .CMOS_LVDS_N (CMOS_LVDS_N), + .CLK_DIV_IS_FAST_CLK (FPGA_TECHNOLOGY >= 100) + ) i_tx_2_link ( + .dac_clk_div (dac_2_clk_div), + .dac_data_0 (dac_2_data_0), + .dac_data_1 (dac_2_data_1), + .dac_data_2 (dac_2_data_2), + .dac_data_3 (dac_2_data_3), + .dac_data_strobe (dac_2_data_strobe), + .dac_data_clk (dac_2_data_clk), + .dac_data_valid (dac_2_data_valid), + // DAC interface + .tx_clk (tx2_clk), + .tx_rst (tx2_rst), + .tx_data_valid (tx2_data_valid), + .tx_data_i (tx2_data_i), + .tx_data_q (tx2_data_q), + .tx_sdr_ddr_n (tx2_sdr_ddr_n), + .tx_single_lane (tx2_single_lane), + .tx_symb_op (tx2_symb_op), + .tx_symb_8_16b (tx2_symb_8_16b)); + end else begin + assign tx2_clk = 1'b0; + assign tx2_dclk_out_n_NC = 1'b0; + assign tx2_dclk_out_p_dclk_out = 1'b0; + assign tx2_idata_out_n_idata0 = 1'b0; + assign tx2_idata_out_p_idata1 = 1'b0; + assign tx2_qdata_out_n_qdata2 = 1'b0; + assign tx2_qdata_out_p_qdata3 = 1'b0; + assign tx2_strobe_out_n_NC = 1'b0; + assign tx2_strobe_out_p_strobe_out = 1'b0; + end + endgenerate + +endmodule diff --git a/adi_library/axi_adrv9001/axi_adrv9001_ip.tcl b/adi_library/axi_adrv9001/axi_adrv9001_ip.tcl new file mode 100644 index 00000000..df85553d --- /dev/null +++ b/adi_library/axi_adrv9001/axi_adrv9001_ip.tcl @@ -0,0 +1,121 @@ +############################################################################### +## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create axi_adrv9001 +adi_ip_files axi_adrv9001 [list \ + "$ad_hdl_dir/library/xilinx/common/ad_serdes_clk.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_serdes_in.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_serdes_out.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ + "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine.v" \ + "$ad_hdl_dir/library/common/ad_dds_1.v" \ + "$ad_hdl_dir/library/common/ad_dds_2.v" \ + "$ad_hdl_dir/library/common/ad_dds.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/up_tdd_cntrl.v" \ + "$ad_hdl_dir/library/common/ad_tdd_control.v" \ + "$ad_hdl_dir/library/common/ad_addsub.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/up_dac_common.v" \ + "$ad_hdl_dir/library/common/up_dac_channel.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ + "$ad_hdl_dir/library/common/ad_pngen.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "adrv9001_rx.v" \ + "adrv9001_tx.v" \ + "adrv9001_pack.v" \ + "adrv9001_aligner4.v" \ + "adrv9001_aligner8.v" \ + "adrv9001_rx_link.v" \ + "adrv9001_tx_link.v" \ + "axi_adrv9001_rx.v" \ + "axi_adrv9001_rx_channel.v" \ + "axi_adrv9001_if.v" \ + "axi_adrv9001_tx.v" \ + "axi_adrv9001_tx_channel.v" \ + "axi_adrv9001_core.v" \ + "axi_adrv9001_constr.xdc" \ + "axi_adrv9001_tdd.v" \ + "axi_adrv9001.v" ] + +adi_ip_properties axi_adrv9001 + +adi_init_bd_tcl +adi_ip_bd axi_adrv9001 "bd/bd.tcl" + +adi_ip_add_core_dependencies [list \ + analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \ +] + +set cc [ipx::current_core] + +ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 $cc +ipx::infer_bus_interface adc_1_clk xilinx.com:signal:clock_rtl:1.0 $cc +ipx::infer_bus_interface adc_2_clk xilinx.com:signal:clock_rtl:1.0 $cc +ipx::infer_bus_interface dac_1_clk xilinx.com:signal:clock_rtl:1.0 $cc +ipx::infer_bus_interface dac_2_clk xilinx.com:signal:clock_rtl:1.0 $cc +ipx::infer_bus_interface adc_1_rst xilinx.com:signal:reset_rtl:1.0 $cc +ipx::infer_bus_interface adc_2_rst xilinx.com:signal:reset_rtl:1.0 $cc +ipx::infer_bus_interface dac_1_rst xilinx.com:signal:reset_rtl:1.0 $cc +ipx::infer_bus_interface dac_2_rst xilinx.com:signal:reset_rtl:1.0 $cc + +ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces adc_1_rst -of_objects $cc] +ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces adc_2_rst -of_objects $cc] +ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces dac_1_rst -of_objects $cc] +ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces dac_2_rst -of_objects $cc] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INDEPENDENT_1R1T_SUPPORT')) == 1 && spirit:decode(id('MODELPARAM_VALUE.DISABLE_TX2_SSI')) == 0} \ + [ipx::get_ports dac_2* -of_objects $cc] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INDEPENDENT_1R1T_SUPPORT')) == 1 && spirit:decode(id('MODELPARAM_VALUE.DISABLE_RX2_SSI')) == 0} \ + [ipx::get_ports adc_2* -of_objects $cc] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.DISABLE_TX2_SSI')) == 0} \ + [ipx::get_ports *tx2_* -of_objects $cc] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.DISABLE_RX2_SSI')) == 0} \ + [ipx::get_ports *rx2_* -of_objects $cc] + +set_property driver_value 0 [ipx::get_ports *_sync_in* -of_objects $cc] + +## Customize XGUI layout + +set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] + +ipgui::add_param -name "EXT_SYNC" -component $cc -parent $page0 +set_property -dict [list \ + "display_name" "External sync" \ + "tooltip" "NOTE: If active enables the external synchronization features for Rx and Tx. The external sync signals must be synchronous with to ref_clk" \ + "widget" "checkBox" \ +] [ipgui::get_guiparamspec -name "EXT_SYNC" -component $cc] + +adi_set_ports_dependency "adc_sync_in" \ + "(spirit:decode(id('MODELPARAM_VALUE.EXT_SYNC')) == 1)" +adi_set_ports_dependency "dac_sync_in" \ + "(spirit:decode(id('MODELPARAM_VALUE.EXT_SYNC')) == 1)" + +adi_add_auto_fpga_spec_params +ipx::create_xgui_files $cc + +ipx::save_core $cc diff --git a/adi_library/axi_adrv9001/axi_adrv9001_rx.v b/adi_library/axi_adrv9001/axi_adrv9001_rx.v new file mode 100644 index 00000000..68b4dc90 --- /dev/null +++ b/adi_library/axi_adrv9001/axi_adrv9001_rx.v @@ -0,0 +1,417 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adrv9001_rx #( + parameter ID = 0, + parameter ENABLED = 1, + parameter CMOS_LVDS_N = 0, + parameter COMMON_BASE_ADDR = 'h00, + parameter CHANNEL_BASE_ADDR = 'h01, + parameter MODE_R1 = 1, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter DATAFORMAT_DISABLE = 0, + parameter DCFILTER_DISABLE = 0, + parameter IQCORRECTION_DISABLE = 1 +) ( + + // adc interface + output adc_rst, + input adc_clk, + input adc_valid_A, + input [ 15:0] adc_data_i_A, + input [ 15:0] adc_data_q_A, + + input adc_valid_B, + input [ 15:0] adc_data_i_B, + input [ 15:0] adc_data_q_B, + + output adc_single_lane, + output adc_sdr_ddr_n, + output adc_symb_op, + output adc_symb_8_16b, + output up_adc_r1_mode, + + input [ 31:0] adc_clk_ratio, + + // dac loopback interface + input dac_data_valid_A, + input [ 15:0] dac_data_i_A, + input [ 15:0] dac_data_q_A, + + input dac_data_valid_B, + input [ 15:0] dac_data_i_B, + input [ 15:0] dac_data_q_B, + + // dma interface + output adc_valid, + + output adc_enable_i0, + output [ 15:0] adc_data_i0, + output adc_enable_q0, + output [ 15:0] adc_data_q0, + + output adc_enable_i1, + output [ 15:0] adc_data_i1, + output adc_enable_q1, + output [ 15:0] adc_data_q1, + + input adc_dovf, + + output adc_sync, + + // processor interface + input up_rstn, + input up_clk, + input up_wreq, + input [ 13:0] up_waddr, + input [ 31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [ 13:0] up_raddr, + output reg [ 31:0] up_rdata, + output reg up_rack +); + + generate + if (ENABLED == 0) begin : core_disabled + + assign adc_rst = 1'b0; + assign adc_single_lane = 1'b0; + assign adc_sdr_ddr_n = 1'b0; + assign adc_symb_op = 1'b0; + assign adc_symb_8_16b = 1'b0; + assign up_adc_r1_mode = 1'b0; + assign adc_valid = 1'b0; + assign adc_enable_i0 = 1'b0; + assign adc_data_i0 = 16'b0; + assign adc_enable_q0 = 1'b0; + assign adc_data_q0 = 16'b0; + assign adc_enable_i1 = 1'b0; + assign adc_data_i1 = 16'b0; + assign adc_enable_q1 = 1'b0; + assign adc_data_q1 = 16'b0; + + always @(*) begin + up_wack = 1'b0; + up_rdata = 32'b0; + up_rack = 1'b0; + end + + end else begin : core_enabled + + // configuration settings + + localparam CONFIG = (CMOS_LVDS_N * 128) + + (MODE_R1 * 16) + + (DATAFORMAT_DISABLE * 4) + + (DCFILTER_DISABLE * 2) + + (IQCORRECTION_DISABLE * 1); + + // internal registers + + reg up_status_pn_err = 'd0; + reg up_status_pn_oos = 'd0; + reg up_status_or = 'd0; + + // internal signals + + wire [ 15:0] adc_data_iq_i0_s; + wire [ 15:0] adc_data_iq_q0_s; + wire [ 15:0] adc_data_iq_i1_s; + wire [ 15:0] adc_data_iq_q1_s; + wire [ 4:0] adc_num_lanes; + wire [ 3:0] up_adc_pn_err_s; + wire [ 3:0] up_adc_pn_oos_s; + wire [ 3:0] up_adc_or_s; + wire [ 4:0] up_wack_s; + wire [ 4:0] up_rack_s; + wire [ 31:0] up_rdata_s[0:4]; + wire adc_valid_out_i0; + wire adc_valid_out_i1; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_status_pn_err <= 'd0; + up_status_pn_oos <= 'd0; + up_status_or <= 'd0; + up_wack <= 'd0; + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_status_pn_err <= up_adc_r1_mode ? | up_adc_pn_err_s[1:0] : | up_adc_pn_err_s[3:0]; + up_status_pn_oos <= up_adc_r1_mode ? | up_adc_pn_oos_s[1:0] : | up_adc_pn_oos_s[3:0]; + up_status_or <= | up_adc_or_s; + up_wack <= | up_wack_s; + up_rack <= | up_rack_s; + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | + up_rdata_s[3] | up_rdata_s[4]; + end + end + + // channel width is 32 bits + + assign adc_valid = adc_enable_i0 ? adc_valid_out_i0 : adc_valid_out_i1; + + // channel 0 (i) + + axi_adrv9001_rx_channel #( + .Q_OR_I_N (0), + .COMMON_ID (CHANNEL_BASE_ADDR), + .DISABLE (0), + .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), + .DCFILTER_DISABLE (DCFILTER_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE), + .DATA_WIDTH (16) + ) i_rx_channel_0 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_valid_in (adc_valid_A), + .adc_data_in (adc_data_i_A[15:0]), + .adc_valid_out (adc_valid_out_i0), + .adc_data_out (adc_data_i0), + .adc_data_iq_in (adc_data_iq_q0_s), + .adc_data_iq_out (adc_data_iq_i0_s), + .adc_enable (adc_enable_i0), + .dac_valid_in (dac_data_valid_A), + .dac_data_in (dac_data_i_A), + .up_adc_pn_err (up_adc_pn_err_s[0]), + .up_adc_pn_oos (up_adc_pn_oos_s[0]), + .up_adc_or (up_adc_or_s[0]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // channel 1 (q) + + axi_adrv9001_rx_channel #( + .Q_OR_I_N (1), + .COMMON_ID (CHANNEL_BASE_ADDR), + .CHANNEL_ID (1), + .DISABLE (0), + .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), + .DCFILTER_DISABLE (DCFILTER_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE), + .DATA_WIDTH (16) + ) i_rx_channel_1 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_valid_in (adc_valid_A), + .adc_data_in (adc_data_q_A[15:0]), + .adc_valid_out (), + .adc_data_out (adc_data_q0), + .adc_data_iq_in (adc_data_iq_i0_s), + .adc_data_iq_out (adc_data_iq_q0_s), + .adc_enable (adc_enable_q0), + .dac_valid_in (dac_data_valid_A), + .dac_data_in (dac_data_q_A), + .up_adc_pn_err (up_adc_pn_err_s[1]), + .up_adc_pn_oos (up_adc_pn_oos_s[1]), + .up_adc_or (up_adc_or_s[1]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // channel 2 (i) + + axi_adrv9001_rx_channel #( + .Q_OR_I_N (0), + .COMMON_ID (CHANNEL_BASE_ADDR), + .CHANNEL_ID (2), + .DISABLE (MODE_R1), + .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), + .DCFILTER_DISABLE (DCFILTER_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE), + .DATA_WIDTH (16) + ) i_rx_channel_2 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_valid_in (adc_valid_B), + .adc_data_in (adc_data_i_B[15:0]), + .adc_valid_out (adc_valid_out_i1), + .adc_data_out (adc_data_i1), + .adc_data_iq_in (adc_data_iq_q1_s), + .adc_data_iq_out (adc_data_iq_i1_s), + .adc_enable (adc_enable_i1), + .dac_valid_in (dac_data_valid_B), + .dac_data_in (dac_data_i_B), + .up_adc_pn_err (up_adc_pn_err_s[2]), + .up_adc_pn_oos (up_adc_pn_oos_s[2]), + .up_adc_or (up_adc_or_s[2]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + // channel 3 (q) + + axi_adrv9001_rx_channel #( + .Q_OR_I_N (1), + .COMMON_ID (CHANNEL_BASE_ADDR), + .CHANNEL_ID (3), + .DISABLE (MODE_R1), + .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), + .DCFILTER_DISABLE (DCFILTER_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE), + .DATA_WIDTH (16) + ) i_rx_channel_3 ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_valid_in (adc_valid_B), + .adc_data_in (adc_data_q_B[15:0]), + .adc_valid_out (), + .adc_data_out (adc_data_q1), + .adc_data_iq_in (adc_data_iq_i1_s), + .adc_data_iq_out (adc_data_iq_q1_s), + .adc_enable (adc_enable_q1), + .dac_valid_in (dac_data_valid_B), + .dac_data_in (dac_data_q_B), + .up_adc_pn_err (up_adc_pn_err_s[3]), + .up_adc_pn_oos (up_adc_pn_oos_s[3]), + .up_adc_or (up_adc_or_s[3]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[3]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[3]), + .up_rack (up_rack_s[3])); + + // common processor control + + up_adc_common #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .COMMON_ID (COMMON_BASE_ADDR), + .CONFIG(CONFIG), + .DRP_DISABLE(1), + .USERPORTS_DISABLE(1), + .GPIO_DISABLE(1), + .START_CODE_DISABLE(1) + ) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (1'b1), + .adc_sync_status (1'd0), + .adc_status_ovf (adc_dovf), + .adc_clk_ratio (adc_clk_ratio), + .adc_start_code (), + .adc_sref_sync (), + .adc_sync (adc_sync), + .adc_ext_sync_arm (), + .adc_ext_sync_disarm (), + .adc_ext_sync_manual_req (), + .adc_num_lanes (adc_num_lanes), + .adc_custom_control (), + .adc_crc_enable (), + .adc_sdr_ddr_n (adc_sdr_ddr_n), + .adc_symb_op (adc_symb_op), + .adc_symb_8_16b (adc_symb_8_16b), + .up_pps_rcounter(32'h0), + .up_pps_status(1'b0), + .up_pps_irq_mask(), + .up_adc_r1_mode (up_adc_r1_mode), + .up_adc_ce (), + .up_status_pn_err (up_status_pn_err), + .up_status_pn_oos (up_status_pn_oos), + .up_status_or (up_status_or), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .adc_config_wr (), + .adc_config_ctrl (), + .adc_config_rd ('d0), + .adc_ctrl_status ('d0), + .up_usr_chanmax_out (), + .up_usr_chanmax_in (8'd3), + .up_adc_gpio_in (32'd0), + .up_adc_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[4]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[4]), + .up_rack (up_rack_s[4])); + + assign adc_single_lane = adc_num_lanes[0]; + + end + endgenerate + +endmodule diff --git a/adi_library/axi_adrv9001/axi_adrv9001_rx_channel.v b/adi_library/axi_adrv9001/axi_adrv9001_rx_channel.v new file mode 100644 index 00000000..e8abe201 --- /dev/null +++ b/adi_library/axi_adrv9001/axi_adrv9001_rx_channel.v @@ -0,0 +1,326 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adrv9001_rx_channel #( + parameter Q_OR_I_N = 0, + parameter COMMON_ID = 0, + parameter CHANNEL_ID = 0, + parameter DISABLE = 0, + parameter DATAFORMAT_DISABLE = 0, + parameter DCFILTER_DISABLE = 0, + parameter IQCORRECTION_DISABLE = 0, + parameter DATA_WIDTH = 16 +) ( + + // adc interface + input adc_clk, + input adc_rst, + input adc_valid_in, + input [(DATA_WIDTH-1):0] adc_data_in, + output adc_valid_out, + output [(DATA_WIDTH-1):0] adc_data_out, + input [(DATA_WIDTH-1):0] adc_data_iq_in, + output [(DATA_WIDTH-1):0] adc_data_iq_out, + output adc_enable, + + input dac_valid_in, + input [(DATA_WIDTH-1):0] dac_data_in, + + // channel interface + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, + + // processor interface + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + localparam NUM_OF_SAMPLES = DATA_WIDTH/16; + + // internal signals + + wire [(NUM_OF_SAMPLES-1):0] adc_dfmt_valid_s; + wire [(DATA_WIDTH-1):0] adc_dfmt_data_s; + wire [(NUM_OF_SAMPLES-1):0] adc_dcfilter_valid_s; + wire [(DATA_WIDTH-1):0] adc_dcfilter_data_s; + wire [(NUM_OF_SAMPLES-1):0] adc_valid_out_s; + wire adc_pn_err_s; + wire adc_pn_oos_s; + wire [3:0] adc_pnseq_sel; + wire adc_dfmt_se_s; + wire adc_dfmt_type_s; + wire adc_dfmt_enable_s; + wire adc_dcfilt_enb_s; + wire [15:0] adc_dcfilt_offset_s; + wire [15:0] adc_dcfilt_coeff_s; + wire adc_iqcor_enb_s; + wire [15:0] adc_iqcor_coeff_1_s; + wire [15:0] adc_iqcor_coeff_2_s; + wire [(DATA_WIDTH-1):0] adc_data_pn; + wire [(DATA_WIDTH-1):0] pn7_data; + wire [(DATA_WIDTH-1):0] pn15_data; + wire [ 3:0] adc_data_sel_s; + wire [15:0] adc_data_in_s; + wire adc_valid_in_s; + + reg [15:0] full_ramp_counter = 'd0; + + reg adc_valid_in_d = 'h0; + reg adc_valid_in_2d = 'h0; + reg [(DATA_WIDTH-1):0] adc_data_in_d = 'h0; + reg [(DATA_WIDTH-1):0] adc_data_in_2d = 'h0; + + reg dac_valid_in_d = 'h0; + reg dac_valid_in_2d = 'h0; + reg [(DATA_WIDTH-1):0] dac_data_in_d = 'h0; + reg [(DATA_WIDTH-1):0] dac_data_in_2d = 'h0; + + // variables + genvar n; + + // input pipeline stage to protect logic if data comes from an async clock domain + always @(posedge adc_clk) begin + adc_valid_in_d <= adc_valid_in; + adc_valid_in_2d <= adc_valid_in_d; + adc_data_in_d <= adc_data_in; + adc_data_in_2d <= adc_data_in_d; + end + always @(posedge adc_clk) begin + dac_valid_in_d <= dac_valid_in; + dac_valid_in_2d <= dac_valid_in_d; + dac_data_in_d <= dac_data_in; + dac_data_in_2d <= dac_data_in_d; + end + + assign adc_data_in_s = (adc_data_sel_s == 4'h0) ? adc_data_in_2d : dac_data_in_2d; + assign adc_valid_in_s = (adc_data_sel_s == 4'h0) ? adc_valid_in_2d : dac_valid_in_2d; + + // iq correction inputs + + generate + for (n = 0; n < NUM_OF_SAMPLES; n = n + 1) begin: g_datafmt + if (DISABLE == 1 || DATAFORMAT_DISABLE == 1) begin + assign adc_dfmt_valid_s[n] = adc_valid_in_s; + assign adc_dfmt_data_s[((16*n)+15):(16*n)] = adc_data_in_s[((16*n)+15):(16*n)]; + end else begin + ad_datafmt #( + .DATA_WIDTH (16) + ) i_ad_datafmt ( + .clk (adc_clk), + .valid (adc_valid_in_s), + .data (adc_data_in_s[((16*n)+15):(16*n)]), + .valid_out (adc_dfmt_valid_s[n]), + .data_out (adc_dfmt_data_s[((16*n)+15):(16*n)]), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + end + end + + for (n = 0; n < NUM_OF_SAMPLES; n = n + 1) begin: g_dcfilter + if (DISABLE == 1 || DCFILTER_DISABLE == 1) begin + assign adc_dcfilter_valid_s[n] = adc_dfmt_valid_s[n]; + assign adc_dcfilter_data_s[((16*n)+15):(16*n)] = adc_dfmt_data_s[((16*n)+15):(16*n)]; + end else begin + ad_dcfilter i_ad_dcfilter ( + .clk (adc_clk), + .valid (adc_dfmt_valid_s[n]), + .data (adc_dfmt_data_s[((16*n)+15):(16*n)]), + .valid_out (adc_dcfilter_valid_s[n]), + .data_out (adc_dcfilter_data_s[((16*n)+15):(16*n)]), + .dcfilt_enb (adc_dcfilt_enb_s), + .dcfilt_coeff (adc_dcfilt_coeff_s), + .dcfilt_offset (adc_dcfilt_offset_s)); + end + end + + assign adc_valid_out = adc_valid_out_s[0]; + assign adc_data_iq_out = adc_dcfilter_data_s; + + for (n = 0; n < NUM_OF_SAMPLES; n = n + 1) begin: g_iqcor + if (DISABLE == 1 || IQCORRECTION_DISABLE == 1) begin + assign adc_valid_out_s[n] = adc_dcfilter_valid_s[n]; + assign adc_data_out[((16*n)+15):(16*n)] = adc_dcfilter_data_s[((16*n)+15):(16*n)]; + end else begin + ad_iqcor #( + .Q_OR_I_N (Q_OR_I_N) + ) i_ad_iqcor ( + .clk (adc_clk), + .valid (adc_dcfilter_valid_s[n]), + .data_in (adc_dcfilter_data_s[((16*n)+15):(16*n)]), + .data_iq (adc_data_iq_in[((16*n)+15):(16*n)]), + .valid_out (adc_valid_out_s[n]), + .data_out (adc_data_out[((16*n)+15):(16*n)]), + .iqcor_enable (adc_iqcor_enb_s), + .iqcor_coeff_1 (adc_iqcor_coeff_1_s), + .iqcor_coeff_2 (adc_iqcor_coeff_2_s)); + end + end + + if (DISABLE == 1) begin + assign adc_enable = 1'b0; + assign up_adc_pn_err = 1'b0; + assign up_adc_pn_oos = 1'b0; + assign up_adc_or = 1'b0; + assign up_wack = 1'b0; + assign up_rdata = 32'b0; + assign up_rack = 1'b0; + end else begin + // pn oos & pn err + + // PN7 x^7 + x^6 + 1 + ad_pngen #( + .POL_MASK ( (1<<7) | (1<<6) ), + .POL_W (7), + .DW (16) + ) PN7_gen ( + .clk (adc_clk), + .reset (adc_rst), + .clk_en (adc_valid_in_s), + .pn_init (adc_pn_oos_s), + .pn_data_in (adc_data_in_s), + .pn_data_out (pn7_data)); + + // PN15 x^15 + x^14 + 1 + ad_pngen #( + .POL_MASK ( (1<<15) | (1<<14) ), + .POL_W (15), + .DW (16) + ) PN15_gen ( + .clk (adc_clk), + .reset (adc_rst), + .clk_en (adc_valid_in_s), + .pn_init (adc_pn_oos_s), + .pn_data_in (adc_data_in_s), + .pn_data_out (pn15_data)); + + // reference nibble ramp and full ramp generator + // next value is always the currently received value incremented + always @(posedge adc_clk) begin + if (adc_valid_in_s) begin + full_ramp_counter <= adc_data_in_s + 16'd1; + end + end + + assign adc_data_pn = adc_pnseq_sel == 4'd4 ? pn7_data : + adc_pnseq_sel == 4'd5 ? pn15_data : + adc_pnseq_sel == 4'd10 ? {4{full_ramp_counter[3:0]}} : + adc_pnseq_sel == 4'd11 ? full_ramp_counter : 'h0; + assign valid_seq_sel = adc_pnseq_sel == 4'd4 || adc_pnseq_sel == 4'd5 || + adc_pnseq_sel == 4'd10 || adc_pnseq_sel == 4'd11; + + ad_pnmon #( + .DATA_WIDTH (DATA_WIDTH), + .OOS_THRESHOLD (8), + .ALLOW_ZERO_MASKING(1) + ) i_pnmon ( + .adc_clk (adc_clk), + .adc_valid_in (adc_valid_in_s), + .adc_data_in (adc_data_in_s), + .adc_data_pn (adc_data_pn), + .adc_pattern_has_zero (adc_pnseq_sel[3]), + .adc_pn_oos (adc_pn_oos_s), + .adc_pn_err (adc_pn_err_s)); + + up_adc_channel #( + .COMMON_ID (COMMON_ID), + .CHANNEL_ID (CHANNEL_ID), + .USERPORTS_DISABLE(1), + .DATAFORMAT_DISABLE(DATAFORMAT_DISABLE), + .DCFILTER_DISABLE(DCFILTER_DISABLE), + .IQCORRECTION_DISABLE(IQCORRECTION_DISABLE) + ) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (adc_iqcor_enb_s), + .adc_dcfilt_enb (adc_dcfilt_enb_s), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_dcfilt_offset (adc_dcfilt_offset_s), + .adc_dcfilt_coeff (adc_dcfilt_coeff_s), + .adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s), + .adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s), + .adc_pnseq_sel (adc_pnseq_sel), + .adc_data_sel (adc_data_sel_s), + .adc_pn_err (adc_pn_err_s & valid_seq_sel), + .adc_pn_oos (adc_pn_oos_s & valid_seq_sel), + .adc_or (1'd0), + .adc_read_data ('d0), + .adc_status_header ('d0), + .adc_crc_err ('d0), + .up_adc_pn_err (up_adc_pn_err), + .up_adc_pn_oos (up_adc_pn_oos), + .up_adc_or (up_adc_or), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + end + endgenerate + +endmodule diff --git a/adi_library/axi_adrv9001/axi_adrv9001_tdd.v b/adi_library/axi_adrv9001/axi_adrv9001_tdd.v new file mode 100644 index 00000000..55685098 --- /dev/null +++ b/adi_library/axi_adrv9001/axi_adrv9001_tdd.v @@ -0,0 +1,272 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module axi_adrv9001_tdd #( + parameter ID = 0, + parameter ENABLED = 1, + parameter BASE_ADDRESS = 6'h20 +) ( + + // clock + + input clk, + input rst, + + // control signals from the tdd control + + output tdd_rx_vco_en, + output tdd_tx_vco_en, + output tdd_rx_rf_en, + output tdd_tx_rf_en, + + // status signal + + output tdd_enabled, + input [ 7:0] tdd_status, + + // sync signal + + input tdd_sync, + output reg tdd_sync_cntr, + + // tx/rx data flow control + + output reg tdd_tx_valid = 1'b1, + output reg tdd_rx_valid = 1'b1, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + generate + if (ENABLED == 1) begin + + // internal signals + + wire tdd_enable_s; + wire tdd_secondary_s; + wire [ 7:0] tdd_burst_count_s; + wire tdd_rx_only_s; + wire tdd_tx_only_s; + wire tdd_gated_rx_dmapath_s; + wire tdd_gated_tx_dmapath_s; + wire [23:0] tdd_counter_init_s; + wire [23:0] tdd_frame_length_s; + wire tdd_terminal_type_s; + wire tdd_sync_enable_s; + wire [23:0] tdd_vco_rx_on_1_s; + wire [23:0] tdd_vco_rx_off_1_s; + wire [23:0] tdd_vco_tx_on_1_s; + wire [23:0] tdd_vco_tx_off_1_s; + wire [23:0] tdd_rx_on_1_s; + wire [23:0] tdd_rx_off_1_s; + wire [23:0] tdd_rx_dp_on_1_s; + wire [23:0] tdd_rx_dp_off_1_s; + wire [23:0] tdd_tx_on_1_s; + wire [23:0] tdd_tx_off_1_s; + wire [23:0] tdd_tx_dp_on_1_s; + wire [23:0] tdd_tx_dp_off_1_s; + wire [23:0] tdd_vco_rx_on_2_s; + wire [23:0] tdd_vco_rx_off_2_s; + wire [23:0] tdd_vco_tx_on_2_s; + wire [23:0] tdd_vco_tx_off_2_s; + wire [23:0] tdd_rx_on_2_s; + wire [23:0] tdd_rx_off_2_s; + wire [23:0] tdd_rx_dp_on_2_s; + wire [23:0] tdd_rx_dp_off_2_s; + wire [23:0] tdd_tx_on_2_s; + wire [23:0] tdd_tx_off_2_s; + wire [23:0] tdd_tx_dp_on_2_s; + wire [23:0] tdd_tx_dp_off_2_s; + + wire [23:0] tdd_counter_status; + + wire tdd_rx_dp_en_s; + wire tdd_tx_dp_en_s; + + assign tdd_enabled = tdd_enable_s; + + // syncronization control signal + + always @(posedge clk) begin + if (tdd_enable_s == 1'b1) begin + tdd_sync_cntr <= ~tdd_terminal_type_s; + end else begin + tdd_sync_cntr <= 1'b0; + end + end + + // tx/rx data flow control + + always @(posedge clk) begin + if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin + tdd_tx_valid <= tdd_tx_dp_en_s; + end else begin + tdd_tx_valid <= 1'b1; + end + end + + always @(posedge clk) begin + if((tdd_enable_s == 1) && (tdd_gated_tx_dmapath_s == 1)) begin + tdd_rx_valid <= tdd_rx_dp_en_s; + end else begin + tdd_rx_valid <= 1'b1; + end + end + + // instantiations + + up_tdd_cntrl #( + .BASE_ADDRESS (BASE_ADDRESS) + ) i_up_tdd_cntrl( + .clk(clk), + .rst(rst), + .tdd_enable(tdd_enable_s), + .tdd_secondary(tdd_secondary_s), + .tdd_burst_count(tdd_burst_count_s), + .tdd_tx_only(tdd_tx_only_s), + .tdd_rx_only(tdd_rx_only_s), + .tdd_gated_rx_dmapath(tdd_gated_rx_dmapath_s), + .tdd_gated_tx_dmapath(tdd_gated_tx_dmapath_s), + .tdd_counter_init(tdd_counter_init_s), + .tdd_frame_length(tdd_frame_length_s), + .tdd_terminal_type(tdd_terminal_type_s), + .tdd_vco_rx_on_1(tdd_vco_rx_on_1_s), + .tdd_vco_rx_off_1(tdd_vco_rx_off_1_s), + .tdd_vco_tx_on_1(tdd_vco_tx_on_1_s), + .tdd_vco_tx_off_1(tdd_vco_tx_off_1_s), + .tdd_rx_on_1(tdd_rx_on_1_s), + .tdd_rx_off_1(tdd_rx_off_1_s), + .tdd_rx_dp_on_1(tdd_rx_dp_on_1_s), + .tdd_rx_dp_off_1(tdd_rx_dp_off_1_s), + .tdd_tx_on_1(tdd_tx_on_1_s), + .tdd_tx_off_1(tdd_tx_off_1_s), + .tdd_tx_dp_on_1(tdd_tx_dp_on_1_s), + .tdd_tx_dp_off_1(tdd_tx_dp_off_1_s), + .tdd_vco_rx_on_2(tdd_vco_rx_on_2_s), + .tdd_vco_rx_off_2(tdd_vco_rx_off_2_s), + .tdd_vco_tx_on_2(tdd_vco_tx_on_2_s), + .tdd_vco_tx_off_2(tdd_vco_tx_off_2_s), + .tdd_rx_on_2(tdd_rx_on_2_s), + .tdd_rx_off_2(tdd_rx_off_2_s), + .tdd_rx_dp_on_2(tdd_rx_dp_on_2_s), + .tdd_rx_dp_off_2(tdd_rx_dp_off_2_s), + .tdd_tx_on_2(tdd_tx_on_2_s), + .tdd_tx_off_2(tdd_tx_off_2_s), + .tdd_tx_dp_on_2(tdd_tx_dp_on_2_s), + .tdd_tx_dp_off_2(tdd_tx_dp_off_2_s), + .tdd_status(tdd_status), + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_wack(up_wack), + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata), + .up_rack(up_rack)); + + // the TX_DATA_PATH_DELAY and CONTROL_PATH_DELAY are specificly defined + // for the axi_adrv9001 core + + ad_tdd_control #( + .TX_DATA_PATH_DELAY(), + .CONTROL_PATH_DELAY() + ) i_tdd_control( + .clk(clk), + .rst(rst), + .tdd_enable(tdd_enable_s), + .tdd_secondary(tdd_secondary_s), + .tdd_counter_init(tdd_counter_init_s), + .tdd_frame_length(tdd_frame_length_s), + .tdd_burst_count(tdd_burst_count_s), + .tdd_rx_only(tdd_rx_only_s), + .tdd_tx_only(tdd_tx_only_s), + .tdd_sync (tdd_sync), + .tdd_vco_rx_on_1(tdd_vco_rx_on_1_s), + .tdd_vco_rx_off_1(tdd_vco_rx_off_1_s), + .tdd_vco_tx_on_1(tdd_vco_tx_on_1_s), + .tdd_vco_tx_off_1(tdd_vco_tx_off_1_s), + .tdd_rx_on_1(tdd_rx_on_1_s), + .tdd_rx_off_1(tdd_rx_off_1_s), + .tdd_rx_dp_on_1(tdd_rx_dp_on_1_s), + .tdd_rx_dp_off_1(tdd_rx_dp_off_1_s), + .tdd_tx_on_1(tdd_tx_on_1_s), + .tdd_tx_off_1(tdd_tx_off_1_s), + .tdd_tx_dp_on_1(tdd_tx_dp_on_1_s), + .tdd_tx_dp_off_1(tdd_tx_dp_off_1_s), + .tdd_vco_rx_on_2(tdd_vco_rx_on_2_s), + .tdd_vco_rx_off_2(tdd_vco_rx_off_2_s), + .tdd_vco_tx_on_2(tdd_vco_tx_on_2_s), + .tdd_vco_tx_off_2(tdd_vco_tx_off_2_s), + .tdd_rx_on_2(tdd_rx_on_2_s), + .tdd_rx_off_2(tdd_rx_off_2_s), + .tdd_rx_dp_on_2(tdd_rx_dp_on_2_s), + .tdd_rx_dp_off_2(tdd_rx_dp_off_2_s), + .tdd_tx_on_2(tdd_tx_on_2_s), + .tdd_tx_off_2(tdd_tx_off_2_s), + .tdd_tx_dp_on_2(tdd_tx_dp_on_2_s), + .tdd_tx_dp_off_2(tdd_tx_dp_off_2_s), + .tdd_rx_dp_en(tdd_rx_dp_en_s), + .tdd_tx_dp_en(tdd_tx_dp_en_s), + .tdd_rx_vco_en(tdd_rx_vco_en), + .tdd_tx_vco_en(tdd_tx_vco_en), + .tdd_rx_rf_en(tdd_rx_rf_en), + .tdd_tx_rf_en(tdd_tx_rf_en), + .tdd_counter_status(tdd_counter_status)); + end else begin + assign up_wack = 1'b0; + assign up_rack = 1'b0; + assign up_rdata = 32'h0; + assign tdd_rx_rf_en = 1'b1; + assign tdd_tx_rf_en = 1'b1; + assign tdd_enabled = 1'b0; + end + endgenerate + +endmodule diff --git a/adi_library/axi_adrv9001/axi_adrv9001_tx.v b/adi_library/axi_adrv9001/axi_adrv9001_tx.v new file mode 100644 index 00000000..00b337fe --- /dev/null +++ b/adi_library/axi_adrv9001/axi_adrv9001_tx.v @@ -0,0 +1,431 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adrv9001_tx #( + parameter ID = 0, + parameter ENABLED = 1, + parameter CMOS_LVDS_N = 0, + parameter USE_RX_CLK_FOR_TX = 0, + parameter COMMON_BASE_ADDR = 'h10, + parameter CHANNEL_BASE_ADDR = 'h11, + parameter MODE_R1 = 1, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter EXT_SYNC = 0, + parameter DISABLE = 0, + parameter DDS_DISABLE = 0, + parameter IQCORRECTION_DISABLE = 0, + parameter DAC_DDS_TYPE = 1, + parameter DAC_DDS_CORDIC_DW = 20, + parameter DAC_DDS_CORDIC_PHASE_DW = 18 +) ( + + // dac interface + output dac_rst, + input dac_clk, + output dac_data_valid_A, + output [15:0] dac_data_i_A, + output [15:0] dac_data_q_A, + + output dac_data_valid_B, + output [15:0] dac_data_i_B, + output [15:0] dac_data_q_B, + + output dac_single_lane, + output dac_sdr_ddr_n, + output dac_symb_op, + output dac_symb_8_16b, + output up_dac_r1_mode, + + input tdd_tx_valid, + + input [ 31:0] dac_clk_ratio, + + // master/slave + input dac_sync_in, + output dac_sync_out, + output dac_ext_sync_arm, + + // dma interface + output dac_valid, + + output dac_enable_i0, + input [ 15:0] dac_data_i0, + output dac_enable_q0, + input [ 15:0] dac_data_q0, + + output dac_enable_i1, + input [ 15:0] dac_data_i1, + output dac_enable_q1, + input [ 15:0] dac_data_q1, + + input dac_dunf, + + // processor interface + input up_rstn, + input up_clk, + input up_wreq, + input [ 13:0] up_waddr, + input [ 31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [ 13:0] up_raddr, + output reg [ 31:0] up_rdata, + output reg up_rack +); + + generate + if (ENABLED == 0) begin : core_disabled + + assign dac_rst = 1'b0; + assign dac_data_valid_A = 1'b0; + assign dac_data_i_A = 16'b0; + assign dac_data_q_A = 16'b0; + assign dac_data_valid_B = 1'b0; + assign dac_data_i_B = 16'b0; + assign dac_data_q_B = 16'b0; + assign dac_single_lane = 1'b0; + assign dac_sdr_ddr_n = 1'b0; + assign dac_symb_op = 1'b0; + assign dac_symb_8_16b = 1'b0; + assign up_dac_r1_mode = 1'b0; + assign dac_sync_out = 1'b0; + assign dac_valid = 1'b0; + assign dac_enable_i0 = 1'b0; + assign dac_enable_q0 = 1'b0; + assign dac_enable_i1 = 1'b0; + assign dac_enable_q1 = 1'b0; + + always @(*) begin + up_wack = 1'b0; + up_rdata = 32'b0; + up_rack = 1'b0; + end + + end else begin : core_enabled + + // configuration settings + + localparam CONFIG = (USE_RX_CLK_FOR_TX * 1024) + + (CMOS_LVDS_N * 128) + + (MODE_R1 * 16) + + (DDS_DISABLE * 64) + + (IQCORRECTION_DISABLE * 1); + + // internal registers + + reg dac_data_sync = 'd0; + reg [15:0] dac_rate_cnt = 'd0; + reg dac_valid_int = 'd0; + + // internal signals + + wire dac_data_sync_s; + wire [ 15:0] dac_data_iq_i0_s; + wire [ 15:0] dac_data_iq_q0_s; + wire [ 15:0] dac_data_iq_i1_s; + wire [ 15:0] dac_data_iq_q1_s; + wire dac_dds_format_s; + wire [ 15:0] dac_datarate_s; + wire [4:0] dac_num_lanes; + wire [ 4:0] up_wack_s; + wire [ 4:0] up_rack_s; + wire [ 31:0] up_rdata_s[0:4]; + + // master/slave + + assign dac_data_sync_s = (EXT_SYNC == 0) ? dac_sync_out : dac_sync_in; + + always @(posedge dac_clk) begin + dac_data_sync <= dac_data_sync_s; + end + + // rate counters and data sync signals + + always @(posedge dac_clk) begin + if (dac_rst == 1'b1) begin + dac_rate_cnt <= 16'b0; + end else begin + if ((dac_data_sync == 1'b1) || (dac_rate_cnt == 16'd0)) begin + dac_rate_cnt <= dac_datarate_s; + end else begin + dac_rate_cnt <= dac_rate_cnt - 1'b1; + end + end + end + + // dma interface + + assign dac_data_valid_A = dac_valid_int; + assign dac_data_valid_B = dac_valid_int; + + always @(posedge dac_clk) begin + if (dac_rst == 1'b1) begin + dac_valid_int <= 1'b0; + end else begin + dac_valid_int <= (dac_rate_cnt == 16'd0) ? tdd_tx_valid : 1'b0; + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_wack <= | up_wack_s; + up_rack <= | up_rack_s; + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | + up_rdata_s[3] | up_rdata_s[4]; + end + end + + // dac channel 0 + + axi_adrv9001_tx_channel #( + .CHANNEL_ID (0), + .COMMON_ID (CHANNEL_BASE_ADDR), + .Q_OR_I_N (0), + .DISABLE (DISABLE), + .DDS_DISABLE (DDS_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW) + ) i_tx_channel_0 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_data_in_req (dac_valid), + .dac_data_in (dac_data_i0), + .dac_data_out_req (dac_data_valid_A), + .dac_data_out (dac_data_i_A[15:0]), + .dac_data_iq_in (dac_data_iq_q0_s), + .dac_data_iq_out (dac_data_iq_i0_s), + .dac_enable (dac_enable_i0), + .dac_data_sync (dac_data_sync), + .dac_dds_format (dac_dds_format_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // dac channel 1 + + axi_adrv9001_tx_channel #( + .CHANNEL_ID (1), + .COMMON_ID (CHANNEL_BASE_ADDR), + .Q_OR_I_N (1), + .DISABLE (DISABLE), + .DDS_DISABLE (DDS_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW) + ) i_tx_channel_1 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_data_in_req (), + .dac_data_in (dac_data_q0), + .dac_data_out_req (dac_data_valid_A), + .dac_data_out (dac_data_q_A[15:0]), + .dac_data_iq_in (dac_data_iq_i0_s), + .dac_data_iq_out (dac_data_iq_q0_s), + .dac_enable (dac_enable_q0), + .dac_data_sync (dac_data_sync), + .dac_dds_format (dac_dds_format_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // dac channel 2 - disabled in 1R1T mode + + axi_adrv9001_tx_channel #( + .CHANNEL_ID (2), + .COMMON_ID (CHANNEL_BASE_ADDR), + .Q_OR_I_N (0), + .DISABLE (MODE_R1), + .DDS_DISABLE (DDS_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW) + ) i_tx_channel_2 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_data_in_req (), + .dac_data_in (dac_data_i1), + .dac_data_out_req (dac_data_valid_B), + .dac_data_out (dac_data_i_B[15:0]), + .dac_data_iq_in (dac_data_iq_q1_s), + .dac_data_iq_out (dac_data_iq_i1_s), + .dac_enable (dac_enable_i1), + .dac_data_sync (dac_data_sync), + .dac_dds_format (dac_dds_format_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + // dac channel 3 - disabled in 1R1T mode + + axi_adrv9001_tx_channel #( + .CHANNEL_ID (3), + .COMMON_ID (CHANNEL_BASE_ADDR), + .Q_OR_I_N (1), + .DISABLE (MODE_R1), + .DDS_DISABLE (DDS_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE), + .DAC_DDS_TYPE (DAC_DDS_TYPE), + .DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW), + .DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW) + ) i_tx_channel_3 ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_data_in_req (), + .dac_data_in (dac_data_q1), + .dac_data_out_req (dac_data_valid_B), + .dac_data_out (dac_data_q_B[15:0]), + .dac_data_iq_in (dac_data_iq_i1_s), + .dac_data_iq_out (dac_data_iq_q1_s), + .dac_enable (dac_enable_q1), + .dac_data_sync (dac_data_sync), + .dac_dds_format (dac_dds_format_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[3]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[3]), + .up_rack (up_rack_s[3])); + + // dac common processor interface + + up_dac_common #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .CONFIG(CONFIG), + .CLK_EDGE_SEL(0), + .COMMON_ID(COMMON_BASE_ADDR), + .DRP_DISABLE(1), + .USERPORTS_DISABLE(1), + .GPIO_DISABLE(1) + ) i_up_dac_common ( + .mmcm_rst (), + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_num_lanes (dac_num_lanes), + .dac_sdr_ddr_n (dac_sdr_ddr_n), + .dac_symb_op (dac_symb_op), + .dac_symb_8_16b (dac_symb_8_16b), + .dac_sync (dac_sync_out), + .dac_ext_sync_arm (dac_ext_sync_arm), + .dac_frame (), + .dac_clksel (), + .dac_custom_wr(), + .dac_custom_rd(32'b0), + .dac_custom_control(), + .dac_status_if_busy(1'b0), + .dac_par_type (), + .dac_par_enb (), + .dac_r1_mode (), + .up_dac_r1_mode (up_dac_r1_mode), + .dac_datafmt (dac_dds_format_s), + .dac_datarate (dac_datarate_s), + .dac_status (1'b1), + .dac_status_unf (dac_dunf), + .dac_clk_ratio (dac_clk_ratio), + .up_dac_ce (), + .up_pps_rcounter(32'h0), + .up_pps_status(1'b0), + .up_pps_irq_mask(), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .up_usr_chanmax (), + .dac_usr_chanmax (8'd3), + .up_dac_gpio_in (32'd0), + .up_dac_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[4]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[4]), + .up_rack (up_rack_s[4])); + + assign dac_single_lane = dac_num_lanes[0]; + + end + endgenerate + +endmodule diff --git a/adi_library/axi_adrv9001/axi_adrv9001_tx_channel.v b/adi_library/axi_adrv9001/axi_adrv9001_tx_channel.v new file mode 100644 index 00000000..b23a148e --- /dev/null +++ b/adi_library/axi_adrv9001/axi_adrv9001_tx_channel.v @@ -0,0 +1,252 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adrv9001_tx_channel #( + parameter COMMON_ID = 6'h11, + parameter CHANNEL_ID = 32'h0, + parameter Q_OR_I_N = 0, + parameter DISABLE = 0, + parameter DDS_DISABLE = 0, + parameter IQCORRECTION_DISABLE = 0, + parameter DAC_DDS_TYPE = 1, + parameter DAC_DDS_CORDIC_DW = 20, + parameter DAC_DDS_CORDIC_PHASE_DW = 18 +) ( + + // dac interface + input dac_clk, + input dac_rst, + output dac_data_in_req, + input [15:0] dac_data_in, + input dac_data_out_req, + output [15:0] dac_data_out, + input [15:0] dac_data_iq_in, + output reg [15:0] dac_data_iq_out, + + // processor interface + output reg dac_enable = 1'b0, + input dac_data_sync, + input dac_dds_format, + + // bus interface + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // internal registers + + reg [15:0] dac_pat_data = 'd0; + reg [15:0] full_ramp_counter = 'd0; + + // internal signals + + wire [15:0] dac_dds_data_s; + wire [15:0] dac_dds_scale_1_s; + wire [15:0] dac_dds_init_1_s; + wire [15:0] dac_dds_incr_1_s; + wire [15:0] dac_dds_scale_2_s; + wire [15:0] dac_dds_init_2_s; + wire [15:0] dac_dds_incr_2_s; + wire [15:0] dac_pat_data_1_s; + wire [15:0] dac_pat_data_2_s; + wire [ 3:0] dac_data_sel_s; + wire dac_iqcor_enb_s; + wire [15:0] dac_iqcor_coeff_1_s; + wire [15:0] dac_iqcor_coeff_2_s; + wire [15:0] pn7_data; + wire [15:0] pn15_data; + // dac iq correction + + generate + if (DISABLE == 1 || IQCORRECTION_DISABLE == 1) begin + + assign dac_data_out = dac_data_iq_out; + assign dac_data_in_req = dac_data_out_req; + + end else begin + ad_iqcor #( + .Q_OR_I_N (Q_OR_I_N) + ) i_ad_iqcor_0 ( + .clk (dac_clk), + .valid (dac_data_out_req), + .data_in (dac_data_iq_out[15:0]), + .data_iq (dac_data_iq_in[15:0]), + .valid_out (dac_data_in_req), + .data_out (dac_data_out[15:0]), + .iqcor_enable (dac_iqcor_enb_s), + .iqcor_coeff_1 (dac_iqcor_coeff_1_s), + .iqcor_coeff_2 (dac_iqcor_coeff_2_s)); + end + + if (DISABLE == 1) begin + assign up_wack = 1'b0; + assign up_rdata = 32'b0; + assign up_rack = 1'b0; + end else begin + + // PN7 x^7 + x^6 + 1 + ad_pngen #( + .POL_MASK ((1<<7) | (1<<6)), + .POL_W (7), + .DW (16) + ) PN7_gen ( + .clk (dac_clk), + .reset (dac_rst), + .clk_en (dac_data_in_req), + .pn_init (1'b0), + .pn_data_out (pn7_data)); + + // PN15 x^15 + x^14 + 1 + ad_pngen #( + .POL_MASK ((1<<15) | (1<<14)), + .POL_W (15), + .DW (16) + ) PN15_gen ( + .clk (dac_clk), + .reset (dac_rst), + .clk_en (dac_data_in_req), + .pn_init (1'b0), + .pn_data_out (pn15_data)); + + // full ramp generator + always @(posedge dac_clk) begin + if (dac_data_sync) begin + full_ramp_counter <= 'h0; + end else if (dac_data_in_req) begin + full_ramp_counter <= full_ramp_counter + 16'd1; + end + end + + // dac mux + + always @(posedge dac_clk) begin + dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; + case (dac_data_sel_s) + 4'hB: dac_data_iq_out <= full_ramp_counter; // full ramp + 4'hA: dac_data_iq_out <= {4{full_ramp_counter[3:0]}}; // nibble ramp + 4'h7: dac_data_iq_out <= pn15_data; + 4'h6: dac_data_iq_out <= pn7_data; + 4'h3: dac_data_iq_out <= 16'd0; + 4'h2: dac_data_iq_out <= dac_data_in; + 4'h1: dac_data_iq_out <= dac_pat_data_1_s; + default: dac_data_iq_out <= dac_dds_data_s; + endcase + end + + // dds + + ad_dds #( + .DISABLE (DDS_DISABLE), + .DDS_DW (16), + .PHASE_DW (16), + .DDS_TYPE (DAC_DDS_TYPE), + .CORDIC_DW (DAC_DDS_CORDIC_DW), + .CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW), + .CLK_RATIO (1) + ) i_dds ( + .clk (dac_clk), + .dac_dds_format (dac_dds_format), + .dac_data_sync (dac_data_sync), + .dac_valid (dac_data_out_req), + .tone_1_scale (dac_dds_scale_1_s), + .tone_2_scale (dac_dds_scale_2_s), + .tone_1_init_offset (dac_dds_init_1_s), + .tone_2_init_offset (dac_dds_init_2_s), + .tone_1_freq_word (dac_dds_incr_1_s), + .tone_2_freq_word (dac_dds_incr_2_s), + .dac_dds_data (dac_dds_data_s)); + + // single channel processor + + up_dac_channel #( + .COMMON_ID(COMMON_ID), + .CHANNEL_ID (CHANNEL_ID), + .DDS_DISABLE(DDS_DISABLE), + .USERPORTS_DISABLE(1), + .IQCORRECTION_DISABLE(IQCORRECTION_DISABLE) + ) i_up_dac_channel ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_dds_scale_1 (dac_dds_scale_1_s), + .dac_dds_init_1 (dac_dds_init_1_s), + .dac_dds_incr_1 (dac_dds_incr_1_s), + .dac_dds_scale_2 (dac_dds_scale_2_s), + .dac_dds_init_2 (dac_dds_init_2_s), + .dac_dds_incr_2 (dac_dds_incr_2_s), + .dac_pat_data_1 (dac_pat_data_1_s), + .dac_pat_data_2 (dac_pat_data_2_s), + .dac_data_sel (dac_data_sel_s), + .dac_iq_mode (), + .dac_iqcor_enb (dac_iqcor_enb_s), + .dac_iqcor_coeff_1 (dac_iqcor_coeff_1_s), + .dac_iqcor_coeff_2 (dac_iqcor_coeff_2_s), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_interpolation_m (), + .up_usr_interpolation_n (), + .dac_usr_datatype_be (1'b0), + .dac_usr_datatype_signed (1'b1), + .dac_usr_datatype_shift (8'd0), + .dac_usr_datatype_total_bits (8'd16), + .dac_usr_datatype_bits (8'd16), + .dac_usr_interpolation_m (16'd1), + .dac_usr_interpolation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + end + endgenerate + +endmodule diff --git a/adi_library/axi_adrv9001/bd/bd.tcl b/adi_library/axi_adrv9001/bd/bd.tcl new file mode 100644 index 00000000..dceb9498 --- /dev/null +++ b/adi_library/axi_adrv9001/bd/bd.tcl @@ -0,0 +1,47 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + DEV_PACKAGE \ + SPEED_GRADE \ + FPGA_FAMILY \ + FPGA_TECHNOLOGY" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/axi_adrv9001/component.xml b/adi_library/axi_adrv9001/component.xml new file mode 100644 index 00000000..d2bf9f65 --- /dev/null +++ b/adi_library/axi_adrv9001/component.xml @@ -0,0 +1,3224 @@ + + + analog.com + user + axi_adrv9001 + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + delay_clk + + + + + + + CLK + + + delay_clk + + + + + + adc_1_clk + + + + + + + CLK + + + adc_1_clk + + + + + + ASSOCIATED_RESET + adc_1_rst + + + + + adc_2_clk + + + + + + + CLK + + + adc_2_clk + + + + + + ASSOCIATED_RESET + adc_2_rst + + + + + dac_1_clk + + + + + + + CLK + + + dac_1_clk + + + + + + ASSOCIATED_RESET + dac_1_rst + + + + + dac_2_clk + + + + + + + CLK + + + dac_2_clk + + + + + + ASSOCIATED_RESET + dac_2_rst + + + + + adc_1_rst + + + + + + + RST + + + adc_1_rst + + + + + + POLARITY + + + + + + adc_2_rst + + + + + + + RST + + + adc_2_rst + + + + + + POLARITY + + + + + + dac_1_rst + + + + + + + RST + + + dac_1_rst + + + + + + POLARITY + + + + + + dac_2_rst + + + + + + + RST + + + dac_2_rst + + + + + + POLARITY + + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_adrv9001 + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + e336bf6f + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_adrv9001 + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 4b659020 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_xpgui_view_fileset + + + + viewChecksum + 7d3a131e + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_blockdiagram_view_fileset + + + + + + ref_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + mssi_sync + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + tx_output_enable + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_sync_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dac_sync_in + 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+ + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + dac_2_dunf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + tdd_sync + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + tdd_sync_cntr + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + gpio_rx1_enable_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + gpio_rx2_enable_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + gpio_tx1_enable_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + gpio_tx2_enable_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + CMOS_LVDS_N + Cmos Lvds N + 0 + + + TDD_DISABLE + Tdd Disable + 0 + + + DDS_DISABLE + Dds Disable + 0 + + + INDEPENDENT_1R1T_SUPPORT + Independent 1r1t Support + 1 + + + COMMON_2R2T_SUPPORT + Common 2r2t Support + 1 + + + DISABLE_RX2_SSI + Disable Rx2 Ssi + 0 + + + DISABLE_TX2_SSI + Disable Tx2 Ssi + 0 + + + RX_USE_BUFG + Rx Use Bufg + 0 + + + TX_USE_BUFG + Tx Use Bufg + 0 + + + IODELAY_CTRL + Iodelay Ctrl + 1 + + + IODELAY_ENABLE + Iodelay Enable + 1 + + + IO_DELAY_GROUP + Io Delay Group + dev_if_delay_group + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + EXT_SYNC + Ext Sync + 0 + + + USE_RX_CLK_FOR_TX + Use Rx Clk For Tx + 0 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_00ecfe9a + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + + + choice_pairs_19f99f31 + 0 + 10 + 11 + 12 + 13 + 14 + 20 + 21 + 22 + 23 + 24 + 25 + 30 + + + choice_pairs_28f798a2 + 0 + 1 + 2 + 3 + 4 + + + choice_pairs_fc01a186 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../xilinx/common/up_clock_mon_constr.xdc + xdc + + + axi_adrv9001_constr.xdc + xdc + + + ../common/ad_addsub.v + verilogSource + + + ../common/ad_datafmt.v + verilogSource + + + ../common/ad_dds.v + verilogSource + + + ../common/ad_dds_1.v + verilogSource + + + ../common/ad_dds_2.v + verilogSource + + + ../common/ad_dds_cordic_pipe.v + verilogSource + + + ../common/ad_dds_sine.v + verilogSource + + + ../common/ad_dds_sine_cordic.v + verilogSource + + + ../xilinx/common/ad_mul.v + verilogSource + + + ../common/ad_pngen.v + verilogSource + + + ../common/ad_pnmon.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../xilinx/common/ad_serdes_in.v + verilogSource + + + ../xilinx/common/ad_serdes_out.v + verilogSource + + + ../common/ad_tdd_control.v + verilogSource + + + adrv9001_aligner4.v + verilogSource + + + adrv9001_aligner8.v + verilogSource + + + adrv9001_pack.v + verilogSource + + + adrv9001_rx.v + verilogSource + + + adrv9001_rx_link.v + verilogSource + + + adrv9001_tx.v + verilogSource + + + adrv9001_tx_link.v + verilogSource + + + axi_adrv9001_core.v + verilogSource + + + axi_adrv9001_if.v + verilogSource + + + axi_adrv9001_rx.v + verilogSource + + + axi_adrv9001_rx_channel.v + verilogSource + + + axi_adrv9001_tdd.v + verilogSource + + + axi_adrv9001_tx.v + verilogSource + + + axi_adrv9001_tx_channel.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_dac_channel.v + verilogSource + + + ../common/up_dac_common.v + verilogSource + + + ../common/up_delay_cntrl.v + verilogSource + + + ../common/up_tdd_cntrl.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_adrv9001.v + verilogSource + CHECKSUM_3a205996 + + + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_addsub.v + verilogSource + + + ../common/ad_datafmt.v + verilogSource + + + ../common/ad_dds.v + verilogSource + + + ../common/ad_dds_1.v + verilogSource + + + ../common/ad_dds_2.v + verilogSource + + + ../common/ad_dds_cordic_pipe.v + verilogSource + + + ../common/ad_dds_sine.v + verilogSource + + + ../common/ad_dds_sine_cordic.v + verilogSource + + + ../xilinx/common/ad_mul.v + verilogSource + + + ../common/ad_pngen.v + verilogSource + + + ../common/ad_pnmon.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../xilinx/common/ad_serdes_in.v + verilogSource + + + ../xilinx/common/ad_serdes_out.v + verilogSource + + + ../common/ad_tdd_control.v + verilogSource + + + adrv9001_aligner4.v + verilogSource + + + adrv9001_aligner8.v + verilogSource + + + adrv9001_pack.v + verilogSource + + + adrv9001_rx.v + verilogSource + + + adrv9001_rx_link.v + verilogSource + + + adrv9001_tx.v + verilogSource + + + adrv9001_tx_link.v + verilogSource + + + axi_adrv9001_core.v + verilogSource + + + axi_adrv9001_if.v + verilogSource + + + axi_adrv9001_rx.v + verilogSource + + + axi_adrv9001_rx_channel.v + verilogSource + + + axi_adrv9001_tdd.v + verilogSource + + + axi_adrv9001_tx.v + verilogSource + + + axi_adrv9001_tx_channel.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_dac_channel.v + verilogSource + + + ../common/up_dac_common.v + verilogSource + + + ../common/up_delay_cntrl.v + verilogSource + + + ../common/up_tdd_cntrl.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_adrv9001.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axi_adrv9001_v1_0.tcl + tclSource + CHECKSUM_372ea539 + XGUI_VERSION_2 + + + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + axi_adrv9001_v1_0 + + + ID + Id + 0 + + + CMOS_LVDS_N + Cmos Lvds N + 0 + + + TDD_DISABLE + Tdd Disable + 0 + + + DDS_DISABLE + Dds Disable + 0 + + + INDEPENDENT_1R1T_SUPPORT + Independent 1r1t Support + 1 + + + COMMON_2R2T_SUPPORT + Common 2r2t Support + 1 + + + DISABLE_RX2_SSI + Disable Rx2 Ssi + 0 + + + DISABLE_TX2_SSI + Disable Tx2 Ssi + 0 + + + RX_USE_BUFG + Rx Use Bufg + 0 + + + TX_USE_BUFG + Tx Use Bufg + 0 + + + IODELAY_CTRL + Iodelay Ctrl + 1 + + + IODELAY_ENABLE + Iodelay Enable + 1 + + + IO_DELAY_GROUP + Io Delay Group + dev_if_delay_group + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + EXT_SYNC + External sync + 0 + + + USE_RX_CLK_FOR_TX + Use Rx Clk For Tx + 0 + + + Component_Name + axi_adrv9001_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_adrv9001_v1_0 + level_2 + package_project + + XPM_CDC + + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:45:00Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_adrv9001/intel/adrv9001_rx.v b/adi_library/axi_adrv9001/intel/adrv9001_rx.v new file mode 100644 index 00000000..8b01f1e4 --- /dev/null +++ b/adi_library/axi_adrv9001/intel/adrv9001_rx.v @@ -0,0 +1,156 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module adrv9001_rx #( + parameter CMOS_LVDS_N = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter NUM_LANES = 3, + parameter DRP_WIDTH = 5, + parameter IODELAY_ENABLE = 0, + parameter IODELAY_CTRL = 0, + parameter USE_BUFG = 0, + parameter IO_DELAY_GROUP = "dev_if_delay_group" +) ( + + // device interface + input rx_dclk_in_n_NC, + input rx_dclk_in_p_dclk_in, + input rx_idata_in_n_idata0, + input rx_idata_in_p_idata1, + input rx_qdata_in_n_qdata2, + input rx_qdata_in_p_qdata3, + input rx_strobe_in_n_NC, + input rx_strobe_in_p_strobe_in, + + // internal reset and clocks + input adc_rst, + output adc_clk, + output adc_clk_div, + output [7:0] adc_data_0, + output [7:0] adc_data_1, + output [7:0] adc_data_2, + output [7:0] adc_data_3, + output [7:0] adc_data_strobe, + output adc_valid, + + output [31:0] adc_clk_ratio, + + // delay interface (for IDELAY macros) + input up_clk, + input [NUM_LANES-1:0] up_adc_dld, + input [DRP_WIDTH*NUM_LANES-1:0] up_adc_dwdata, + output [DRP_WIDTH*NUM_LANES-1:0] up_adc_drdata, + input delay_clk, + input delay_rst, + output delay_locked, + + input mssi_sync, + output ssi_sync_out, + input ssi_sync_in, + output ssi_rst +); + + reg [3:0] valid_gen = 4'b0001; + + wire [4:0] gpio_in; + wire [39:0] deser_out; + + periphery_clk_buf rx_clk_buf( + .inclk (rx_dclk_in_p_dclk_in), + .outclk (rx_clk) + ); + + assign gpio_in = {rx_strobe_in_p_strobe_in, + rx_qdata_in_p_qdata3, + rx_qdata_in_n_qdata2, + rx_idata_in_p_idata1, + rx_idata_in_n_idata0}; + + assign {adc_data_strobe, + adc_data_3, + adc_data_2, + adc_data_1, + adc_data_0} = deser_out; + + genvar i; + generate + for (i = 0; i <= 4; i = i + 1) begin: g_ddr_i + + reg [7:0] shift_reg = 8'b0; + wire [1:0] gpio_out; + + // DDR input + adrv9001_gpio_in gpio_rx_in ( + .ck (rx_clk), + .dout (gpio_out), + .pad_in (gpio_in[i]) + ); + + // Temporal ordering: + // MSB - oldest received bit; + // LSB - newest received bit; + always @(posedge rx_clk) begin + shift_reg <= {shift_reg[5:0],gpio_out[0],gpio_out[1]}; + end + + assign deser_out[i*8+:8] = shift_reg; + + end + endgenerate + + always @(posedge rx_clk) begin + if (adc_rst) begin + valid_gen <= 4'b0001; + end else begin + valid_gen <= {valid_gen[2:0],valid_gen[3]}; + end + end + + assign adc_valid = valid_gen[3]; + // No clock divider, qualifier used instead + assign adc_clk_div = rx_clk; + assign adc_clk = rx_clk; + assign adc_clk_ratio = 1; + + // Drive unused signals + assign delay_locked = 'b0; + assign up_adc_drdata = 'b0; + + assign ssi_sync_out = 'b0; + assign ssi_rst = 'b0; + +endmodule diff --git a/adi_library/axi_adrv9001/intel/adrv9001_tx.v b/adi_library/axi_adrv9001/intel/adrv9001_tx.v new file mode 100644 index 00000000..0f466352 --- /dev/null +++ b/adi_library/axi_adrv9001/intel/adrv9001_tx.v @@ -0,0 +1,140 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module adrv9001_tx #( + parameter CMOS_LVDS_N = 0, + parameter NUM_LANES = 4, + parameter FPGA_TECHNOLOGY = 0, + parameter USE_BUFG = 0, + parameter USE_RX_CLK_FOR_TX = 0 +) ( + input ref_clk, + input up_clk, + + input mssi_sync, + input tx_output_enable, + + // physical interface (transmit) + output tx_dclk_out_n_NC, + output tx_dclk_out_p_dclk_out, + input tx_dclk_in_n_NC, + input tx_dclk_in_p_dclk_in, + output tx_idata_out_n_idata0, + output tx_idata_out_p_idata1, + output tx_qdata_out_n_qdata2, + output tx_qdata_out_p_qdata3, + output tx_strobe_out_n_NC, + output tx_strobe_out_p_strobe_out, + + input rx_clk_div, + input rx_clk, + input rx_ssi_rst, + + // internal resets and clocks + + output [31:0] dac_clk_ratio, + + input dac_rst, + output dac_clk_div, + + input [7:0] dac_data_0, + input [7:0] dac_data_1, + input [7:0] dac_data_2, + input [7:0] dac_data_3, + input [7:0] dac_data_strb, + input [7:0] dac_data_clk, + input dac_data_valid +); + + wire [6*8-1:0] serdes_in; + wire [5:0] gpio_out; + + periphery_clk_buf tx_clk_buf( + .inclk (tx_dclk_in_p_dclk_in), + .outclk (tx_clk) + ); + + assign serdes_in = {dac_data_clk, + dac_data_strb, + dac_data_3, + dac_data_2, + dac_data_1, + dac_data_0}; + + assign {tx_dclk_out_p_dclk_out, + tx_strobe_out_p_strobe_out, + tx_qdata_out_p_qdata3, + tx_qdata_out_n_qdata2, + tx_idata_out_p_idata1, + tx_idata_out_n_idata0} = gpio_out; + + genvar i; + generate + for (i = 0; i <= 5; i = i + 1) begin: g_ddr_o + + reg [7:0] shift_reg = 8'b0; + wire [1:0] gpio_in; + + // DDR output + adrv9001_gpio_out gpio_tx_out ( + .ck(tx_clk), + .din(gpio_in), + .pad_out(gpio_out[i]) + ); + + always @(posedge tx_clk) begin + if (dac_data_valid) begin + shift_reg <= serdes_in[i*8+:8]; + end else begin + shift_reg <= {shift_reg[5:0],2'b0}; + end + end + // Order of transmission: + // gpio_in[0] - first + // gpio_in[1] - last + assign gpio_in = {shift_reg[6],shift_reg[7]}; + + end + endgenerate + + // No clock divider, qualifier used instead + assign dac_clk_div = tx_clk; + assign dac_clk = tx_clk; + + assign dac_clk_ratio = 1; + +endmodule diff --git a/adi_library/axi_adrv9001/temporary_case_dependencies.mk b/adi_library/axi_adrv9001/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/axi_adrv9001/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/axi_adrv9001/xgui/axi_adrv9001_v1_0.tcl b/adi_library/axi_adrv9001/xgui/axi_adrv9001_v1_0.tcl new file mode 100644 index 00000000..0e4058db --- /dev/null +++ b/adi_library/axi_adrv9001/xgui/axi_adrv9001_v1_0.tcl @@ -0,0 +1,299 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "CMOS_LVDS_N" -parent ${Page_0} + ipgui::add_param $IPINST -name "COMMON_2R2T_SUPPORT" -parent ${Page_0} + ipgui::add_param $IPINST -name "DDS_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "DISABLE_RX2_SSI" -parent ${Page_0} + ipgui::add_param $IPINST -name "DISABLE_TX2_SSI" -parent ${Page_0} + set EXT_SYNC [ipgui::add_param $IPINST -name "EXT_SYNC" -parent ${Page_0} -widget checkBox] + set_property tooltip {NOTE: If active enables the external synchronization features for Rx and Tx. The external sync signals must be synchronous with to ref_clk} ${EXT_SYNC} + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "INDEPENDENT_1R1T_SUPPORT" -parent ${Page_0} + ipgui::add_param $IPINST -name "IODELAY_CTRL" -parent ${Page_0} + ipgui::add_param $IPINST -name "IODELAY_ENABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "IO_DELAY_GROUP" -parent ${Page_0} + ipgui::add_param $IPINST -name "RX_USE_BUFG" -parent ${Page_0} + ipgui::add_param $IPINST -name "TDD_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "TX_USE_BUFG" -parent ${Page_0} + ipgui::add_param $IPINST -name "USE_RX_CLK_FOR_TX" -parent ${Page_0} + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.CMOS_LVDS_N { PARAM_VALUE.CMOS_LVDS_N } { + # Procedure called to update CMOS_LVDS_N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CMOS_LVDS_N { PARAM_VALUE.CMOS_LVDS_N } { + # Procedure called to validate CMOS_LVDS_N + return true +} + +proc update_PARAM_VALUE.COMMON_2R2T_SUPPORT { PARAM_VALUE.COMMON_2R2T_SUPPORT } { + # Procedure called to update COMMON_2R2T_SUPPORT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.COMMON_2R2T_SUPPORT { PARAM_VALUE.COMMON_2R2T_SUPPORT } { + # Procedure called to validate COMMON_2R2T_SUPPORT + return true +} + +proc update_PARAM_VALUE.DDS_DISABLE { PARAM_VALUE.DDS_DISABLE } { + # Procedure called to update DDS_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DDS_DISABLE { PARAM_VALUE.DDS_DISABLE } { + # Procedure called to validate DDS_DISABLE + return true +} + +proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to validate DEV_PACKAGE + return true +} + +proc update_PARAM_VALUE.DISABLE_RX2_SSI { PARAM_VALUE.DISABLE_RX2_SSI } { + # Procedure called to update DISABLE_RX2_SSI when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DISABLE_RX2_SSI { PARAM_VALUE.DISABLE_RX2_SSI } { + # Procedure called to validate DISABLE_RX2_SSI + return true +} + +proc update_PARAM_VALUE.DISABLE_TX2_SSI { PARAM_VALUE.DISABLE_TX2_SSI } { + # Procedure called to update DISABLE_TX2_SSI when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DISABLE_TX2_SSI { PARAM_VALUE.DISABLE_TX2_SSI } { + # Procedure called to validate DISABLE_TX2_SSI + return true +} + +proc update_PARAM_VALUE.EXT_SYNC { PARAM_VALUE.EXT_SYNC } { + # Procedure called to update EXT_SYNC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.EXT_SYNC { PARAM_VALUE.EXT_SYNC } { + # Procedure called to validate EXT_SYNC + return true +} + +proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to validate FPGA_FAMILY + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.INDEPENDENT_1R1T_SUPPORT { PARAM_VALUE.INDEPENDENT_1R1T_SUPPORT } { + # Procedure called to update INDEPENDENT_1R1T_SUPPORT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.INDEPENDENT_1R1T_SUPPORT { PARAM_VALUE.INDEPENDENT_1R1T_SUPPORT } { + # Procedure called to validate INDEPENDENT_1R1T_SUPPORT + return true +} + +proc update_PARAM_VALUE.IODELAY_CTRL { PARAM_VALUE.IODELAY_CTRL } { + # Procedure called to update IODELAY_CTRL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IODELAY_CTRL { PARAM_VALUE.IODELAY_CTRL } { + # Procedure called to validate IODELAY_CTRL + return true +} + +proc update_PARAM_VALUE.IODELAY_ENABLE { PARAM_VALUE.IODELAY_ENABLE } { + # Procedure called to update IODELAY_ENABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IODELAY_ENABLE { PARAM_VALUE.IODELAY_ENABLE } { + # Procedure called to validate IODELAY_ENABLE + return true +} + +proc update_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to update IO_DELAY_GROUP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to validate IO_DELAY_GROUP + return true +} + +proc update_PARAM_VALUE.RX_USE_BUFG { PARAM_VALUE.RX_USE_BUFG } { + # Procedure called to update RX_USE_BUFG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RX_USE_BUFG { PARAM_VALUE.RX_USE_BUFG } { + # Procedure called to validate RX_USE_BUFG + return true +} + +proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to validate SPEED_GRADE + return true +} + +proc update_PARAM_VALUE.TDD_DISABLE { PARAM_VALUE.TDD_DISABLE } { + # Procedure called to update TDD_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TDD_DISABLE { PARAM_VALUE.TDD_DISABLE } { + # Procedure called to validate TDD_DISABLE + return true +} + +proc update_PARAM_VALUE.TX_USE_BUFG { PARAM_VALUE.TX_USE_BUFG } { + # Procedure called to update TX_USE_BUFG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TX_USE_BUFG { PARAM_VALUE.TX_USE_BUFG } { + # Procedure called to validate TX_USE_BUFG + return true +} + +proc update_PARAM_VALUE.USE_RX_CLK_FOR_TX { PARAM_VALUE.USE_RX_CLK_FOR_TX } { + # Procedure called to update USE_RX_CLK_FOR_TX when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.USE_RX_CLK_FOR_TX { PARAM_VALUE.USE_RX_CLK_FOR_TX } { + # Procedure called to validate USE_RX_CLK_FOR_TX + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.CMOS_LVDS_N { MODELPARAM_VALUE.CMOS_LVDS_N PARAM_VALUE.CMOS_LVDS_N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CMOS_LVDS_N}] ${MODELPARAM_VALUE.CMOS_LVDS_N} +} + +proc update_MODELPARAM_VALUE.TDD_DISABLE { MODELPARAM_VALUE.TDD_DISABLE PARAM_VALUE.TDD_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TDD_DISABLE}] ${MODELPARAM_VALUE.TDD_DISABLE} +} + +proc update_MODELPARAM_VALUE.DDS_DISABLE { MODELPARAM_VALUE.DDS_DISABLE PARAM_VALUE.DDS_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DDS_DISABLE}] ${MODELPARAM_VALUE.DDS_DISABLE} +} + +proc update_MODELPARAM_VALUE.INDEPENDENT_1R1T_SUPPORT { MODELPARAM_VALUE.INDEPENDENT_1R1T_SUPPORT PARAM_VALUE.INDEPENDENT_1R1T_SUPPORT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.INDEPENDENT_1R1T_SUPPORT}] ${MODELPARAM_VALUE.INDEPENDENT_1R1T_SUPPORT} +} + +proc update_MODELPARAM_VALUE.COMMON_2R2T_SUPPORT { MODELPARAM_VALUE.COMMON_2R2T_SUPPORT PARAM_VALUE.COMMON_2R2T_SUPPORT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.COMMON_2R2T_SUPPORT}] ${MODELPARAM_VALUE.COMMON_2R2T_SUPPORT} +} + +proc update_MODELPARAM_VALUE.DISABLE_RX2_SSI { MODELPARAM_VALUE.DISABLE_RX2_SSI PARAM_VALUE.DISABLE_RX2_SSI } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DISABLE_RX2_SSI}] ${MODELPARAM_VALUE.DISABLE_RX2_SSI} +} + +proc update_MODELPARAM_VALUE.DISABLE_TX2_SSI { MODELPARAM_VALUE.DISABLE_TX2_SSI PARAM_VALUE.DISABLE_TX2_SSI } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DISABLE_TX2_SSI}] ${MODELPARAM_VALUE.DISABLE_TX2_SSI} +} + +proc update_MODELPARAM_VALUE.RX_USE_BUFG { MODELPARAM_VALUE.RX_USE_BUFG PARAM_VALUE.RX_USE_BUFG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RX_USE_BUFG}] ${MODELPARAM_VALUE.RX_USE_BUFG} +} + +proc update_MODELPARAM_VALUE.TX_USE_BUFG { MODELPARAM_VALUE.TX_USE_BUFG PARAM_VALUE.TX_USE_BUFG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TX_USE_BUFG}] ${MODELPARAM_VALUE.TX_USE_BUFG} +} + +proc update_MODELPARAM_VALUE.IODELAY_CTRL { MODELPARAM_VALUE.IODELAY_CTRL PARAM_VALUE.IODELAY_CTRL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IODELAY_CTRL}] ${MODELPARAM_VALUE.IODELAY_CTRL} +} + +proc update_MODELPARAM_VALUE.IODELAY_ENABLE { MODELPARAM_VALUE.IODELAY_ENABLE PARAM_VALUE.IODELAY_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IODELAY_ENABLE}] ${MODELPARAM_VALUE.IODELAY_ENABLE} +} + +proc update_MODELPARAM_VALUE.IO_DELAY_GROUP { MODELPARAM_VALUE.IO_DELAY_GROUP PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IO_DELAY_GROUP}] ${MODELPARAM_VALUE.IO_DELAY_GROUP} +} + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY} +} + +proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE} +} + +proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE} +} + +proc update_MODELPARAM_VALUE.EXT_SYNC { MODELPARAM_VALUE.EXT_SYNC PARAM_VALUE.EXT_SYNC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.EXT_SYNC}] ${MODELPARAM_VALUE.EXT_SYNC} +} + +proc update_MODELPARAM_VALUE.USE_RX_CLK_FOR_TX { MODELPARAM_VALUE.USE_RX_CLK_FOR_TX PARAM_VALUE.USE_RX_CLK_FOR_TX } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.USE_RX_CLK_FOR_TX}] ${MODELPARAM_VALUE.USE_RX_CLK_FOR_TX} +} + diff --git a/adi_library/axi_clkgen/Makefile b/adi_library/axi_clkgen/Makefile new file mode 100644 index 00000000..40b28ec2 --- /dev/null +++ b/adi_library/axi_clkgen/Makefile @@ -0,0 +1,18 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_clkgen + +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clkgen.v +GENERIC_DEPS += axi_clkgen.v + +XILINX_DEPS += ../xilinx/common/ad_mmcm_drp.v +XILINX_DEPS += axi_clkgen_ip.tcl +XILINX_DEPS += bd/bd.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_clkgen/axi_clkgen.v b/adi_library/axi_clkgen/axi_clkgen.v new file mode 100644 index 00000000..80dc440f --- /dev/null +++ b/adi_library/axi_clkgen/axi_clkgen.v @@ -0,0 +1,222 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// software programmable clock generator (still needs a reference input!) + +`timescale 1ns/100ps + +module axi_clkgen #( + + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter FPGA_VOLTAGE = 0, + parameter CLKSEL_EN = 0, + parameter real CLKIN_PERIOD = 5.000, + parameter real CLKIN2_PERIOD = 5.000, + parameter integer VCO_DIV = 11, + parameter real VCO_MUL = 49.000, + parameter real CLK0_DIV = 6.000, + parameter real CLK0_PHASE = 0.000, + parameter integer CLK1_DIV = 6, + parameter real CLK1_PHASE = 0.000 +) ( + + // clocks + + input clk, + input clk2, + output clk_0, + output clk_1, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot +); + + // reset and clocks + + wire mmcm_rst; + wire clk_sel_s; + wire up_clk_sel_s; + wire up_rstn; + wire up_clk; + + // internal signals + + wire up_drp_sel_s; + wire up_drp_wr_s; + wire [11:0] up_drp_addr_s; + wire [15:0] up_drp_wdata_s; + wire [15:0] up_drp_rdata_s; + wire up_drp_ready_s; + wire up_drp_locked_s; + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire up_wack_s; + wire up_rreq_s; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_s; + wire up_rack_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + + // processor interface + + up_clkgen #( + .ID(ID), + .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), + .FPGA_FAMILY(FPGA_FAMILY), + .SPEED_GRADE(SPEED_GRADE), + .DEV_PACKAGE(DEV_PACKAGE), + .FPGA_VOLTAGE(FPGA_VOLTAGE) + ) i_up_clkgen ( + .mmcm_rst (mmcm_rst), + .clk_sel (up_clk_sel_s), + .up_drp_sel (up_drp_sel_s), + .up_drp_wr (up_drp_wr_s), + .up_drp_addr (up_drp_addr_s), + .up_drp_wdata (up_drp_wdata_s), + .up_drp_rdata (up_drp_rdata_s), + .up_drp_ready (up_drp_ready_s), + .up_drp_locked (up_drp_locked_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + + // If CLKSEL_EN is not active, the clk0 port of the MMCM is used, this + // should be used when the MMCM has only one active clock source + + generate if (CLKSEL_EN == 1) begin + assign clk_sel_s = up_clk_sel_s; + end else begin + assign clk_sel_s = 1'b1; + end + endgenerate + + // mmcm instantiations + + ad_mmcm_drp #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .MMCM_CLKIN_PERIOD (CLKIN_PERIOD), + .MMCM_CLKIN2_PERIOD (CLKIN2_PERIOD), + .MMCM_VCO_DIV (VCO_DIV), + .MMCM_VCO_MUL (VCO_MUL), + .MMCM_CLK0_DIV (CLK0_DIV), + .MMCM_CLK0_PHASE (CLK0_PHASE), + .MMCM_CLK1_DIV (CLK1_DIV), + .MMCM_CLK1_PHASE (CLK1_PHASE) + ) i_mmcm_drp ( + .clk (clk), + .clk2 (clk2), + .clk_sel(clk_sel_s), + .mmcm_rst (mmcm_rst), + .mmcm_clk_0 (clk_0), + .mmcm_clk_1 (clk_1), + .mmcm_clk_2 (), + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_drp_sel (up_drp_sel_s), + .up_drp_wr (up_drp_wr_s), + .up_drp_addr (up_drp_addr_s), + .up_drp_wdata (up_drp_wdata_s), + .up_drp_rdata (up_drp_rdata_s), + .up_drp_ready (up_drp_ready_s), + .up_drp_locked (up_drp_locked_s)); + +endmodule diff --git a/adi_library/axi_clkgen/axi_clkgen.xpr b/adi_library/axi_clkgen/axi_clkgen.xpr new file mode 100644 index 00000000..1a213ce4 --- /dev/null +++ b/adi_library/axi_clkgen/axi_clkgen.xpr @@ -0,0 +1,441 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_clkgen/axi_clkgen_ip.tcl b/adi_library/axi_clkgen/axi_clkgen_ip.tcl new file mode 100644 index 00000000..d3f56b99 --- /dev/null +++ b/adi_library/axi_clkgen/axi_clkgen_ip.tcl @@ -0,0 +1,62 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_clkgen +adi_ip_files axi_clkgen [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mmcm_drp.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_clkgen.v" \ + "$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \ + "bd/bd.tcl" \ + "axi_clkgen.v" ] + +adi_ip_properties axi_clkgen +adi_ip_bd axi_clkgen "bd/bd.tcl" + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_clkgen} [ipx::current_core] + +ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface clk2 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface clk_0 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface clk_1 xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + +set cc [ipx::current_core] +set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] + +set param [ipx::add_user_parameter ENABLE_CLKIN2 $cc] +set_property -dict {value_resolve_type user value_format bool value false} $param + +set param [ipgui::add_param -name {ENABLE_CLKIN2} -component $cc -parent $page0] +set_property -dict [list \ + display_name {Enable secondary clock input} \ + widget {checkBox} \ +] $param + +set param [ipx::add_user_parameter ENABLE_CLKOUT1 $cc] +set_property -dict {value_resolve_type user value_format bool value false} $param + +set param [ipgui::add_param -name {ENABLE_CLKOUT1} -component $cc -parent $page0] +set_property -dict [list \ + display_name {Enable secondary clock output} \ + widget {checkBox} \ +] $param + +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + +set_property enablement_tcl_expr {$ENABLE_CLKIN2} [ipx::get_user_parameters CLKIN2_PERIOD -of_objects $cc] +set_property enablement_tcl_expr {$ENABLE_CLKOUT1} [ipx::get_user_parameters CLK1_DIV -of_objects $cc] +set_property enablement_tcl_expr {$ENABLE_CLKOUT1} [ipx::get_user_parameters CLK1_PHASE -of_objects $cc] + +adi_set_ports_dependency clk2 ENABLE_CLKIN2 0 +adi_set_ports_dependency clk_1 ENABLE_CLKOUT1 + +ipx::create_xgui_files $cc +ipx::save_core $cc diff --git a/adi_library/axi_clkgen/bd/bd.tcl b/adi_library/axi_clkgen/bd/bd.tcl new file mode 100644 index 00000000..4fdb2dc4 --- /dev/null +++ b/adi_library/axi_clkgen/bd/bd.tcl @@ -0,0 +1,124 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_override $ip \ + "CLKIN_PERIOD \ + CLKIN2_PERIOD \ + FPGA_VOLTAGE" + + bd::mark_propagate_only $ip \ + "FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE \ + FPGA_VOLTAGE" + + adi_auto_assign_device_spec $cellpath +} + +proc axi_clkgen_get_infer_period {ip param clk_name} { + set param_src [get_property "CONFIG.$param.VALUE_SRC" $ip] + if {[string equal $param_src "USER"]} { + return; + } + + set clk [get_bd_pins "$ip/$clk_name"] + set clk_freq [get_property CONFIG.FREQ_HZ $clk] + + if {$clk_freq != {}} { + set clk_period [expr 1000000000.0 / $clk_freq] + set_property "CONFIG.$param" [format "%.6f" $clk_period] $ip + } +} + +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + +proc propagate {cellpath otherinfo} { + set ip [get_bd_cells $cellpath] + + set vco_mul [get_property CONFIG.VCO_MUL $ip] + set vco_div [get_property CONFIG.VCO_DIV $ip] + set clk0_div [get_property CONFIG.CLK0_DIV $ip] + set clk1_div [get_property CONFIG.CLK1_DIV $ip] + + if {$vco_mul == {} || $vco_mul < 1} { + set vco_mul 1 + } + if {$vco_div == {} || $vco_div < 1} { + set vco_div 1 + } + if {$clk0_div == {} || $clk0_div < 1} { + set clk0_div 1 + } + if {$clk1_div == {} || $clk0_div < 1} { + set clk1_div 1 + } + + set clk [get_bd_pins "$ip/clk"] + set clk_freq [get_property CONFIG.FREQ_HZ $clk] + if {[get_property "CONFIG.ENABLE_CLKIN2" $ip] == "true"} { + set clk2 [get_bd_pins "$ip/clk"] + set clk2_freq [get_property CONFIG.FREQ_HZ $clk2] + # Use the larger of the two + if {$clk_freq == {} || $clk2_freq > $clk_freq} { + set clk_freq $clk2_freq + } + } + + if {$clk_freq != {}} { + set clk0_out [get_bd_pins "$ip/clk_0"] + set clk0_out_freq [expr ($clk_freq + 0.0) * $vco_mul / ($vco_div * $clk0_div)] + set_property CONFIG.FREQ_HZ $clk0_out_freq $clk0_out + + if {[get_property "CONFIG.ENABLE_CLKOUT1" $ip] == "true"} { + set clk1_out [get_bd_pins "$ip/clk_1"] + set clk1_out_freq [expr ($clk_freq + 0.0) * $vco_mul / ($vco_div * $clk1_div)] + set_property CONFIG.FREQ_HZ $clk1_out_freq $clk1_out + } + } +} + +proc post_propagate {cellpath otherinfo} { + set ip [get_bd_cells $cellpath] + + axi_clkgen_get_infer_period $ip CLKIN_PERIOD clk + if {[get_property "CONFIG.ENABLE_CLKIN2" $ip] == "true"} { + axi_clkgen_get_infer_period $ip CLKIN2_PERIOD clk2 + } +} diff --git a/adi_library/axi_clkgen/component.xml b/adi_library/axi_clkgen/component.xml new file mode 100644 index 00000000..265aa1e5 --- /dev/null +++ b/adi_library/axi_clkgen/component.xml @@ -0,0 +1,1161 @@ + + + analog.com + user + axi_clkgen + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + clk + + + + + + + CLK + + + clk + + + + + + clk2 + + + + + + + CLK + + + clk2 + + + + + + clk_0 + + + + + + + CLK + + + clk_0 + + + + + + clk_1 + + + + + + + CLK + + + clk_1 + + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_clkgen + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 4fffa083 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_clkgen + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 4fffa083 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 6f7527fe + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + clk2 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + clk_0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + clk_1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + FPGA_VOLTAGE + Fpga Voltage + 0 + + + CLKSEL_EN + Clksel En + 0 + + + CLKIN_PERIOD + Clkin Period + 5 + + + CLKIN2_PERIOD + Clkin2 Period + 5 + + + + false + + + + + + VCO_DIV + Vco Div + 11 + + + VCO_MUL + Vco Mul + 49 + + + CLK0_DIV + Clk0 Div + 6 + + + CLK0_PHASE + Clk0 Phase + 0 + + + CLK1_DIV + Clk1 Div + 6 + + + + false + + + + + + CLK1_PHASE + Clk1 Phase + 0 + + + + false + + + + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_00ecfe9a + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + + + choice_pairs_19f99f31 + 0 + 10 + 11 + 12 + 13 + 14 + 20 + 21 + 22 + 23 + 24 + 25 + 30 + + + choice_pairs_28f798a2 + 0 + 1 + 2 + 3 + 4 + + + choice_pairs_fc01a186 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/ad_mmcm_drp.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clkgen.v + verilogSource + + + ../scripts/adi_xilinx_device_info_enc.tcl + tclSource + + + bd/bd.tcl + tclSource + + + axi_clkgen.v + verilogSource + CHECKSUM_bfbf5736 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../xilinx/common/ad_mmcm_drp.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clkgen.v + verilogSource + + + ../scripts/adi_xilinx_device_info_enc.tcl + tclSource + + + bd/bd.tcl + tclSource + + + axi_clkgen.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_clkgen_v1_0.tcl + tclSource + CHECKSUM_4919e9d5 + XGUI_VERSION_2 + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + xilinx_utilityxitfiles_view_fileset + + gui/axi_clkgen_v1_0.gtcl + GTCL + + + + axi_clkgen_v1_0 + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + FPGA_VOLTAGE + Fpga Voltage + 0 + + + CLKSEL_EN + Clksel En + 0 + + + CLKIN_PERIOD + Clkin Period + 5 + + + CLKIN2_PERIOD + Clkin2 Period + 5 + + + + false + + + + + + VCO_DIV + Vco Div + 11 + + + VCO_MUL + Vco Mul + 49 + + + CLK0_DIV + Clk0 Div + 6 + + + CLK0_PHASE + Clk0 Phase + 0 + + + CLK1_DIV + Clk1 Div + 6 + + + + false + + + + + + CLK1_PHASE + Clk1 Phase + 0 + + + + false + + + + + + Component_Name + axi_clkgen_v1_0 + + + ENABLE_CLKIN2 + Enable secondary clock input + false + + + ENABLE_CLKOUT1 + Enable secondary clock output + false + + + + + + virtex7 + + + /Analog_Devices + + axi_clkgen_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_clkgen + 1 + 2024-01-14T03:45:11Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_clkgen/gui/axi_clkgen_v1_0.gtcl b/adi_library/axi_clkgen/gui/axi_clkgen_v1_0.gtcl new file mode 100644 index 00000000..5492f118 --- /dev/null +++ b/adi_library/axi_clkgen/gui/axi_clkgen_v1_0.gtcl @@ -0,0 +1,4 @@ +# This file is automatically written. Do not modify. +proc gen_USERPARAMETER_CLKIN2_PERIOD_ENABLEMENT {ENABLE_CLKIN2 } {expr $ENABLE_CLKIN2} +proc gen_USERPARAMETER_CLK1_DIV_ENABLEMENT {ENABLE_CLKOUT1 } {expr $ENABLE_CLKOUT1} +proc gen_USERPARAMETER_CLK1_PHASE_ENABLEMENT {ENABLE_CLKOUT1 } {expr $ENABLE_CLKOUT1} diff --git a/adi_library/axi_clkgen/xgui/axi_clkgen_v1_0.tcl b/adi_library/axi_clkgen/xgui/axi_clkgen_v1_0.tcl new file mode 100644 index 00000000..c0803e7e --- /dev/null +++ b/adi_library/axi_clkgen/xgui/axi_clkgen_v1_0.tcl @@ -0,0 +1,289 @@ + +# Loading additional proc with user specified bodies to compute parameter values. +source [file join [file dirname [file dirname [info script]]] gui/axi_clkgen_v1_0.gtcl] + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "CLK0_DIV" -parent ${Page_0} + ipgui::add_param $IPINST -name "CLK0_PHASE" -parent ${Page_0} + ipgui::add_param $IPINST -name "CLK1_DIV" -parent ${Page_0} + ipgui::add_param $IPINST -name "CLK1_PHASE" -parent ${Page_0} + ipgui::add_param $IPINST -name "CLKIN2_PERIOD" -parent ${Page_0} + ipgui::add_param $IPINST -name "CLKIN_PERIOD" -parent ${Page_0} + ipgui::add_param $IPINST -name "CLKSEL_EN" -parent ${Page_0} + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "VCO_DIV" -parent ${Page_0} + ipgui::add_param $IPINST -name "VCO_MUL" -parent ${Page_0} + ipgui::add_param $IPINST -name "ENABLE_CLKIN2" -parent ${Page_0} + ipgui::add_param $IPINST -name "ENABLE_CLKOUT1" -parent ${Page_0} + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "FPGA_VOLTAGE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.CLK1_DIV { PARAM_VALUE.CLK1_DIV PARAM_VALUE.ENABLE_CLKOUT1 } { + # Procedure called to update CLK1_DIV when any of the dependent parameters in the arguments change + + set CLK1_DIV ${PARAM_VALUE.CLK1_DIV} + set ENABLE_CLKOUT1 ${PARAM_VALUE.ENABLE_CLKOUT1} + set values(ENABLE_CLKOUT1) [get_property value $ENABLE_CLKOUT1] + if { [gen_USERPARAMETER_CLK1_DIV_ENABLEMENT $values(ENABLE_CLKOUT1)] } { + set_property enabled true $CLK1_DIV + } else { + set_property enabled false $CLK1_DIV + } +} + +proc validate_PARAM_VALUE.CLK1_DIV { PARAM_VALUE.CLK1_DIV } { + # Procedure called to validate CLK1_DIV + return true +} + +proc update_PARAM_VALUE.CLK1_PHASE { PARAM_VALUE.CLK1_PHASE PARAM_VALUE.ENABLE_CLKOUT1 } { + # Procedure called to update CLK1_PHASE when any of the dependent parameters in the arguments change + + set CLK1_PHASE ${PARAM_VALUE.CLK1_PHASE} + set ENABLE_CLKOUT1 ${PARAM_VALUE.ENABLE_CLKOUT1} + set values(ENABLE_CLKOUT1) [get_property value $ENABLE_CLKOUT1] + if { [gen_USERPARAMETER_CLK1_PHASE_ENABLEMENT $values(ENABLE_CLKOUT1)] } { + set_property enabled true $CLK1_PHASE + } else { + set_property enabled false $CLK1_PHASE + } +} + +proc validate_PARAM_VALUE.CLK1_PHASE { PARAM_VALUE.CLK1_PHASE } { + # Procedure called to validate CLK1_PHASE + return true +} + +proc update_PARAM_VALUE.CLKIN2_PERIOD { PARAM_VALUE.CLKIN2_PERIOD PARAM_VALUE.ENABLE_CLKIN2 } { + # Procedure called to update CLKIN2_PERIOD when any of the dependent parameters in the arguments change + + set CLKIN2_PERIOD ${PARAM_VALUE.CLKIN2_PERIOD} + set ENABLE_CLKIN2 ${PARAM_VALUE.ENABLE_CLKIN2} + set values(ENABLE_CLKIN2) [get_property value $ENABLE_CLKIN2] + if { [gen_USERPARAMETER_CLKIN2_PERIOD_ENABLEMENT $values(ENABLE_CLKIN2)] } { + set_property enabled true $CLKIN2_PERIOD + } else { + set_property enabled false $CLKIN2_PERIOD + } +} + +proc validate_PARAM_VALUE.CLKIN2_PERIOD { PARAM_VALUE.CLKIN2_PERIOD } { + # Procedure called to validate CLKIN2_PERIOD + return true +} + +proc update_PARAM_VALUE.CLK0_DIV { PARAM_VALUE.CLK0_DIV } { + # Procedure called to update CLK0_DIV when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CLK0_DIV { PARAM_VALUE.CLK0_DIV } { + # Procedure called to validate CLK0_DIV + return true +} + +proc update_PARAM_VALUE.CLK0_PHASE { PARAM_VALUE.CLK0_PHASE } { + # Procedure called to update CLK0_PHASE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CLK0_PHASE { PARAM_VALUE.CLK0_PHASE } { + # Procedure called to validate CLK0_PHASE + return true +} + +proc update_PARAM_VALUE.CLKIN_PERIOD { PARAM_VALUE.CLKIN_PERIOD } { + # Procedure called to update CLKIN_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CLKIN_PERIOD { PARAM_VALUE.CLKIN_PERIOD } { + # Procedure called to validate CLKIN_PERIOD + return true +} + +proc update_PARAM_VALUE.CLKSEL_EN { PARAM_VALUE.CLKSEL_EN } { + # Procedure called to update CLKSEL_EN when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CLKSEL_EN { PARAM_VALUE.CLKSEL_EN } { + # Procedure called to validate CLKSEL_EN + return true +} + +proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to validate DEV_PACKAGE + return true +} + +proc update_PARAM_VALUE.ENABLE_CLKIN2 { PARAM_VALUE.ENABLE_CLKIN2 } { + # Procedure called to update ENABLE_CLKIN2 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ENABLE_CLKIN2 { PARAM_VALUE.ENABLE_CLKIN2 } { + # Procedure called to validate ENABLE_CLKIN2 + return true +} + +proc update_PARAM_VALUE.ENABLE_CLKOUT1 { PARAM_VALUE.ENABLE_CLKOUT1 } { + # Procedure called to update ENABLE_CLKOUT1 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ENABLE_CLKOUT1 { PARAM_VALUE.ENABLE_CLKOUT1 } { + # Procedure called to validate ENABLE_CLKOUT1 + return true +} + +proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to validate FPGA_FAMILY + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.FPGA_VOLTAGE { PARAM_VALUE.FPGA_VOLTAGE } { + # Procedure called to update FPGA_VOLTAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_VOLTAGE { PARAM_VALUE.FPGA_VOLTAGE } { + # Procedure called to validate FPGA_VOLTAGE + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to validate SPEED_GRADE + return true +} + +proc update_PARAM_VALUE.VCO_DIV { PARAM_VALUE.VCO_DIV } { + # Procedure called to update VCO_DIV when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.VCO_DIV { PARAM_VALUE.VCO_DIV } { + # Procedure called to validate VCO_DIV + return true +} + +proc update_PARAM_VALUE.VCO_MUL { PARAM_VALUE.VCO_MUL } { + # Procedure called to update VCO_MUL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.VCO_MUL { PARAM_VALUE.VCO_MUL } { + # Procedure called to validate VCO_MUL + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY} +} + +proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE} +} + +proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE} +} + +proc update_MODELPARAM_VALUE.FPGA_VOLTAGE { MODELPARAM_VALUE.FPGA_VOLTAGE PARAM_VALUE.FPGA_VOLTAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_VOLTAGE}] ${MODELPARAM_VALUE.FPGA_VOLTAGE} +} + +proc update_MODELPARAM_VALUE.CLKSEL_EN { MODELPARAM_VALUE.CLKSEL_EN PARAM_VALUE.CLKSEL_EN } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CLKSEL_EN}] ${MODELPARAM_VALUE.CLKSEL_EN} +} + +proc update_MODELPARAM_VALUE.CLKIN_PERIOD { MODELPARAM_VALUE.CLKIN_PERIOD PARAM_VALUE.CLKIN_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CLKIN_PERIOD}] ${MODELPARAM_VALUE.CLKIN_PERIOD} +} + +proc update_MODELPARAM_VALUE.CLKIN2_PERIOD { MODELPARAM_VALUE.CLKIN2_PERIOD PARAM_VALUE.CLKIN2_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CLKIN2_PERIOD}] ${MODELPARAM_VALUE.CLKIN2_PERIOD} +} + +proc update_MODELPARAM_VALUE.VCO_DIV { MODELPARAM_VALUE.VCO_DIV PARAM_VALUE.VCO_DIV } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.VCO_DIV}] ${MODELPARAM_VALUE.VCO_DIV} +} + +proc update_MODELPARAM_VALUE.VCO_MUL { MODELPARAM_VALUE.VCO_MUL PARAM_VALUE.VCO_MUL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.VCO_MUL}] ${MODELPARAM_VALUE.VCO_MUL} +} + +proc update_MODELPARAM_VALUE.CLK0_DIV { MODELPARAM_VALUE.CLK0_DIV PARAM_VALUE.CLK0_DIV } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CLK0_DIV}] ${MODELPARAM_VALUE.CLK0_DIV} +} + +proc update_MODELPARAM_VALUE.CLK0_PHASE { MODELPARAM_VALUE.CLK0_PHASE PARAM_VALUE.CLK0_PHASE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CLK0_PHASE}] ${MODELPARAM_VALUE.CLK0_PHASE} +} + +proc update_MODELPARAM_VALUE.CLK1_DIV { MODELPARAM_VALUE.CLK1_DIV PARAM_VALUE.CLK1_DIV } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CLK1_DIV}] ${MODELPARAM_VALUE.CLK1_DIV} +} + +proc update_MODELPARAM_VALUE.CLK1_PHASE { MODELPARAM_VALUE.CLK1_PHASE PARAM_VALUE.CLK1_PHASE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CLK1_PHASE}] ${MODELPARAM_VALUE.CLK1_PHASE} +} + diff --git a/adi_library/axi_clock_monitor/Makefile b/adi_library/axi_clock_monitor/Makefile new file mode 100755 index 00000000..bb2b0451 --- /dev/null +++ b/adi_library/axi_clock_monitor/Makefile @@ -0,0 +1,20 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_clock_monitor + +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += axi_clock_monitor.v + +XILINX_DEPS += ../common/up_clock_mon.v +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += axi_clock_monitor_ip.tcl + +INTEL_DEPS += ../intel/common/up_clock_mon_constr.sdc +INTEL_DEPS += ../intel/common/up_rst_constr.sdc +INTEL_DEPS += axi_clock_monitor_hw.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_clock_monitor/README.md b/adi_library/axi_clock_monitor/README.md new file mode 100644 index 00000000..f1989aa0 --- /dev/null +++ b/adi_library/axi_clock_monitor/README.md @@ -0,0 +1 @@ +https://wiki.analog.com/resources/fpga/docs/axi_clock_monitor \ No newline at end of file diff --git a/adi_library/axi_clock_monitor/axi_clock_monitor.v b/adi_library/axi_clock_monitor/axi_clock_monitor.v new file mode 100755 index 00000000..2128cc06 --- /dev/null +++ b/adi_library/axi_clock_monitor/axi_clock_monitor.v @@ -0,0 +1,269 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_clock_monitor #( + + parameter ID = 0, + parameter NUM_OF_CLOCKS = 1 +) ( + + // clocks + + input clock_0, + input clock_1, + input clock_2, + input clock_3, + input clock_4, + input clock_5, + input clock_6, + input clock_7, + input clock_8, + input clock_9, + input clock_10, + input clock_11, + input clock_12, + input clock_13, + input clock_14, + input clock_15, + + output reset, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready +); + + // local parameters + + localparam PCORE_VERSION = 1; + + // internal registers + + reg pass = 'd0; + reg up_wack_int = 'd0; + reg up_rack_int = 'd0; + reg up_scratch = 'd0; + reg up_reset_core = 'd0; + reg [31:0] up_rdata_int = 'd0; + + // internal signals + + wire up_clk; + wire up_rstn; + wire up_wreq_s; + wire up_rreq_s; + wire up_waddr_s; + wire up_raddr_s; + + wire clock [0:15]; + wire [20:0] clk_mon_count [0:15]; + + wire up_wreq_i_s; + wire [13:0] up_waddr_i_s; + wire [31:0] up_wdata_i_s; + wire up_wack_o_s; + wire up_rreq_i_s; + wire [13:0] up_raddr_i_s; + wire [31:0] up_rdata_o_s; + wire up_rack_o_s; + + // loop variables + + genvar n; + + generate + assign clock[0 ] = clock_0; + assign clock[1 ] = clock_1; + assign clock[2 ] = clock_2; + assign clock[3 ] = clock_3; + assign clock[4 ] = clock_4; + assign clock[5 ] = clock_5; + assign clock[6 ] = clock_6; + assign clock[7 ] = clock_7; + assign clock[8 ] = clock_8; + assign clock[9 ] = clock_9; + assign clock[10] = clock_10; + assign clock[11] = clock_11; + assign clock[12] = clock_12; + assign clock[13] = clock_13; + assign clock[14] = clock_14; + assign clock[15] = clock_15; + endgenerate + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + assign reset = up_reset_core; + + // decode block select + + assign up_wreq_s = (up_waddr_i_s[13:8] == ID) ? up_wreq_i_s : 1'b0; + assign up_rreq_s = (up_raddr_i_s[13:8] == ID) ? up_rreq_i_s : 1'b0; + + // processor write interface + + assign up_wack_o_s = up_wack_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack_int <= 'd0; + up_reset_core <= 'd0; + end else begin + up_wack_int <= up_wreq_s; + if (up_wreq_s == 1'b1) begin + case (up_waddr_i_s[7:0]) + 8'h004: up_reset_core <= up_wdata_i_s[0]; + default: pass <= 1'h0; + endcase + end + end + end + + // processor read interface + + assign up_rack_o_s = up_rack_int; + assign up_rdata_o_s = up_rdata_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack_int <= 'd0; + up_rdata_int <= 'd0; + end else begin + up_rack_int <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr_i_s) + /* Standard registers */ + 14'h000: up_rdata_int <= PCORE_VERSION; + 14'h001: up_rdata_int <= ID; + + /* Core configuration */ + 14'h003: up_rdata_int <= NUM_OF_CLOCKS; + 14'h004: up_rdata_int <= {31'h00, up_reset_core}; + + /* Clock ratios registers*/ + 14'h010: up_rdata_int <= {11'h00, clk_mon_count[ 0]}; + 14'h011: up_rdata_int <= {11'h00, clk_mon_count[ 1]}; + 14'h012: up_rdata_int <= {11'h00, clk_mon_count[ 2]}; + 14'h013: up_rdata_int <= {11'h00, clk_mon_count[ 3]}; + 14'h014: up_rdata_int <= {11'h00, clk_mon_count[ 4]}; + 14'h015: up_rdata_int <= {11'h00, clk_mon_count[ 5]}; + 14'h016: up_rdata_int <= {11'h00, clk_mon_count[ 6]}; + 14'h017: up_rdata_int <= {11'h00, clk_mon_count[ 7]}; + 14'h018: up_rdata_int <= {11'h00, clk_mon_count[ 8]}; + 14'h019: up_rdata_int <= {11'h00, clk_mon_count[ 9]}; + 14'h01a: up_rdata_int <= {11'h00, clk_mon_count[10]}; + 14'h01b: up_rdata_int <= {11'h00, clk_mon_count[11]}; + 14'h01c: up_rdata_int <= {11'h00, clk_mon_count[12]}; + 14'h01d: up_rdata_int <= {11'h00, clk_mon_count[13]}; + 14'h01e: up_rdata_int <= {11'h00, clk_mon_count[14]}; + 14'h01f: up_rdata_int <= {11'h00, clk_mon_count[15]}; + + default: up_rdata_int <= 'h00; + endcase + end + end + end + + // clock monitors + + generate + for (n = 0; n < NUM_OF_CLOCKS; n = n + 1) begin: clk_mon + up_clock_mon #( + .TOTAL_WIDTH(21) + ) i_clock_mon ( + .up_rstn(~up_reset_core), + .up_clk(up_clk), + .up_d_count(clk_mon_count[n]), + .d_rst(1'b0), + .d_clk(clock[n])); + end + for (n = NUM_OF_CLOCKS; n < 16; n = n + 1) begin: clk_mon_z + assign clk_mon_count[n] = 21'd0; + end + endgenerate + + // axi interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_i_s), + .up_waddr (up_waddr_i_s), + .up_wdata (up_wdata_i_s), + .up_wack (up_wack_o_s), + .up_rreq (up_rreq_i_s), + .up_raddr (up_raddr_i_s), + .up_rdata (up_rdata_o_s), + .up_rack (up_rack_o_s)); + +endmodule diff --git a/adi_library/axi_clock_monitor/axi_clock_monitor.xpr b/adi_library/axi_clock_monitor/axi_clock_monitor.xpr new file mode 100644 index 00000000..930cf0c4 --- /dev/null +++ b/adi_library/axi_clock_monitor/axi_clock_monitor.xpr @@ -0,0 +1,419 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_clock_monitor/axi_clock_monitor_hw.tcl b/adi_library/axi_clock_monitor/axi_clock_monitor_hw.tcl new file mode 100755 index 00000000..ebd5bfdd --- /dev/null +++ b/adi_library/axi_clock_monitor/axi_clock_monitor_hw.tcl @@ -0,0 +1,44 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl + +ad_ip_create axi_clock_monitor {axi_clock_monitor} p_axi_clock_monitor + +# files +set_module_property NAME axi_clock_monitor + +ad_ip_files axi_clock_monitor [list \ + $ad_hdl_dir/library/common/up_axi.v \ + $ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_rst_constr.sdc \ + axi_clock_monitor.v \ +] + +# parameters + +add_parameter NUM_OF_CLOCKS INTEGER 0 +set_parameter_property NUM_OF_CLOCKS DEFAULT_VALUE 8 +set_parameter_property NUM_OF_CLOCKS DISPLAY_NAME NUM_OF_CLOCKS +set_parameter_property NUM_OF_CLOCKS UNITS None +set_parameter_property NUM_OF_CLOCKS HDL_PARAMETER true + +# interfaces + +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn + +ad_interface reset output 1 if_reset + +proc p_axi_clock_monitor {} { + set num_of_clock [get_parameter_value NUM_OF_CLOCKS] + + for {set n 0} {$n < $num_of_clock} {incr n} { + ad_interface clock clock_${n} input 1 + } +} + diff --git a/adi_library/axi_clock_monitor/axi_clock_monitor_ip.tcl b/adi_library/axi_clock_monitor/axi_clock_monitor_ip.tcl new file mode 100755 index 00000000..8b8ab990 --- /dev/null +++ b/adi_library/axi_clock_monitor/axi_clock_monitor_ip.tcl @@ -0,0 +1,56 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_clock_monitor +adi_ip_files axi_clock_monitor [list \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "axi_clock_monitor.v" ] + +adi_ip_properties axi_clock_monitor + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_clock_monitor} [ipx::current_core] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 1} \ + [ipx::get_ports *_1* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 2} \ + [ipx::get_ports *_2* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 3} \ + [ipx::get_ports *_3* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 4} \ + [ipx::get_ports *_4* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 5} \ + [ipx::get_ports *_5* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 6} \ + [ipx::get_ports *_6* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 7} \ + [ipx::get_ports *_7* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 8 } \ + [ipx::get_ports *_8* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 9 } \ + [ipx::get_ports *_9* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 10} \ + [ipx::get_ports *_10* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 11} \ + [ipx::get_ports *_11* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 12} \ + [ipx::get_ports *_12* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 13} \ + [ipx::get_ports *_13* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 14} \ + [ipx::get_ports *_14* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLOCKS')) > 15} \ + [ipx::get_ports *_15* -of_objects [ipx::current_core]] + +ipx::infer_bus_interface reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] + + diff --git a/adi_library/axi_clock_monitor/component.xml b/adi_library/axi_clock_monitor/component.xml new file mode 100644 index 00000000..25f4a23c --- /dev/null +++ b/adi_library/axi_clock_monitor/component.xml @@ -0,0 +1,1096 @@ + + + analog.com + user + axi_clock_monitor + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + reset + + + + + + + RST + + + reset + + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_clock_monitor + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 17b5e71c + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_clock_monitor + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + b0e420e2 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + fb7ff6a0 + + + + + + + clock_0 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + clock_1 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + clock_2 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + clock_3 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + clock_4 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + clock_5 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + clock_6 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + clock_7 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + clock_8 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + clock_9 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + clock_10 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + clock_11 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + clock_12 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + clock_13 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + clock_14 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + clock_15 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + reset + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + NUM_OF_CLOCKS + Num Of Clocks + 1 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/up_clock_mon_constr.xdc + xdc + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + axi_clock_monitor.v + verilogSource + CHECKSUM_3b1ac4a2 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + axi_clock_monitor.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_clock_monitor_v1_0.tcl + tclSource + CHECKSUM_fb7ff6a0 + XGUI_VERSION_2 + + + + axi_clock_monitor_v1_0 + + + ID + Id + 0 + + + NUM_OF_CLOCKS + Num Of Clocks + 1 + + + Component_Name + axi_clock_monitor_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_clock_monitor_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_clock_monitor + 1 + 2024-01-14T03:45:20Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_clock_monitor/xgui/axi_clock_monitor_v1_0.tcl b/adi_library/axi_clock_monitor/xgui/axi_clock_monitor_v1_0.tcl new file mode 100644 index 00000000..4146095c --- /dev/null +++ b/adi_library/axi_clock_monitor/xgui/axi_clock_monitor_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_OF_CLOCKS" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.NUM_OF_CLOCKS { PARAM_VALUE.NUM_OF_CLOCKS } { + # Procedure called to update NUM_OF_CLOCKS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_CLOCKS { PARAM_VALUE.NUM_OF_CLOCKS } { + # Procedure called to validate NUM_OF_CLOCKS + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.NUM_OF_CLOCKS { MODELPARAM_VALUE.NUM_OF_CLOCKS PARAM_VALUE.NUM_OF_CLOCKS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_CLOCKS}] ${MODELPARAM_VALUE.NUM_OF_CLOCKS} +} + diff --git a/adi_library/axi_dac_interpolate/Makefile b/adi_library/axi_dac_interpolate/Makefile new file mode 100644 index 00000000..297738d8 --- /dev/null +++ b/adi_library/axi_dac_interpolate/Makefile @@ -0,0 +1,23 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_dac_interpolate + +GENERIC_DEPS += ../common/ad_iqcor.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += axi_dac_interpolate.v +GENERIC_DEPS += axi_dac_interpolate_filter.v +GENERIC_DEPS += axi_dac_interpolate_reg.v +GENERIC_DEPS += cic_interp.v +GENERIC_DEPS += fir_interp.v + +XILINX_DEPS += ../xilinx/common/ad_mul.v +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += axi_dac_interpolate_constr.xdc +XILINX_DEPS += axi_dac_interpolate_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_dac_interpolate/axi_dac_interpolate.v b/adi_library/axi_dac_interpolate/axi_dac_interpolate.v new file mode 100644 index 00000000..238d0e01 --- /dev/null +++ b/adi_library/axi_dac_interpolate/axi_dac_interpolate.v @@ -0,0 +1,341 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dac_interpolate #( + + parameter CORRECTION_DISABLE = 1 +) ( + input dac_clk, + input dac_rst, + + input [15:0] dac_data_a, + input [15:0] dac_data_b, + input dac_valid_a, + input dac_valid_b, + + input dma_valid_a, + input dma_valid_b, + output dma_ready_a, + output dma_ready_b, + + input dac_enable_a, + input dac_enable_b, + output [15:0] dac_int_data_a, + output [15:0] dac_int_data_b, + output dac_valid_out_a, + output dac_valid_out_b, + output underflow, + + input [ 1:0] trigger_i, + input trigger_adc, + input trigger_la, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [ 6:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [ 6:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready +); + + reg [ 1:0] trigger_i_m1; + reg [ 1:0] trigger_i_m2; + reg [ 1:0] trigger_i_m3; + reg trigger_adc_m1; + reg trigger_adc_m2; + reg trigger_adc_m3; + reg trigger_la_m1; + reg trigger_la_m2; + reg trigger_la_m3; + + reg [ 1:0] any_edge_trigger; + reg [ 1:0] rise_edge_trigger; + reg [ 1:0] fall_edge_trigger; + reg [ 1:0] high_level_trigger; + reg [ 1:0] low_level_trigger; + + // internal signals + + wire up_clk; + wire up_rstn; + wire [ 4:0] up_waddr; + wire [31:0] up_wdata; + wire up_wack; + wire up_wreq; + wire up_rack; + wire [31:0] up_rdata; + wire up_rreq; + wire [ 4:0] up_raddr; + + wire [31:0] interpolation_ratio_a; + wire [31:0] interpolation_ratio_b; + wire [ 2:0] filter_mask_a; + wire [ 2:0] filter_mask_b; + + wire dma_transfer_suspend; + wire flush_dma_s; + wire start_sync_channels; + + wire dac_correction_enable_a; + wire dac_correction_enable_b; + wire [15:0] dac_correction_coefficient_a; + wire [15:0] dac_correction_coefficient_b; + wire [19:0] trigger_config; + + wire en_start_trigger; + wire en_stop_trigger; + wire [ 1:0] en_trigger_pins; + wire en_trigger_adc; + wire en_trigger_la; + + wire [ 1:0] low_level; + wire [ 1:0] high_level; + wire [ 1:0] any_edge; + wire [ 1:0] rise_edge; + wire [ 1:0] fall_edge; + + wire trigger_active; + wire trigger; + wire ext_trigger; + + wire underflow_a; + wire underflow_b; + + wire stop_sync_channels; + wire [ 1:0] raw_transfer_en; + wire [15:0] dac_raw_ch_a_data; + wire [15:0] dac_raw_ch_b_data; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // trigger logic + + assign low_level = trigger_config[1:0]; + assign high_level = trigger_config[3:2]; + assign any_edge = trigger_config[5:4]; + assign rise_edge = trigger_config[7:6]; + assign fall_edge = trigger_config[9:8]; + + assign en_start_trigger = trigger_config[14]; + assign en_stop_trigger = trigger_config[15]; + assign en_trigger_pins = trigger_config[17:16]; + assign en_trigger_adc = trigger_config[18]; + assign en_trigger_la = trigger_config[19]; + + assign trigger_active = |trigger_config[19:16]; + assign trigger = (ext_trigger & en_trigger_pins) | + (trigger_adc_m2 & en_trigger_adc) | + (trigger_la_m2 & en_trigger_la); + + assign ext_trigger = |(any_edge_trigger | + rise_edge_trigger | + fall_edge_trigger | + high_level_trigger | + low_level_trigger); + + // sync + always @(posedge dac_clk) begin + trigger_i_m1 <= trigger_i; + trigger_i_m2 <= trigger_i_m1; + trigger_i_m3 <= trigger_i_m2; + + trigger_adc_m1 <= trigger_adc; + trigger_adc_m2 <= trigger_adc_m1; + + trigger_la_m1 <= trigger_la; + trigger_la_m2 <= trigger_la_m1; + end + + always @(posedge dac_clk) begin + any_edge_trigger <= (trigger_i_m3 ^ trigger_i_m2) & any_edge; + rise_edge_trigger <= (~trigger_i_m3 & trigger_i_m2) & rise_edge; + fall_edge_trigger <= (trigger_i_m3 & ~trigger_i_m2) & fall_edge; + high_level_trigger <= trigger_i_m3 & high_level; + low_level_trigger <= ~trigger_i_m3 & low_level; + end + + assign underflow = underflow_a | underflow_b; + + axi_dac_interpolate_filter #( + .CORRECTION_DISABLE (CORRECTION_DISABLE) + ) i_filter_a ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + + .dac_data (dac_data_a), + .dac_valid (dac_valid_a), + .dac_valid_out (dac_valid_out_a), + + .dac_enable (dac_enable_a), + .dac_int_data (dac_int_data_a), + .dma_ready (dma_ready_a), + .underflow (underflow_a), + + .filter_mask (filter_mask_a), + .interpolation_ratio (interpolation_ratio_a), + .dma_transfer_suspend (dma_transfer_suspend), + .start_sync_channels (start_sync_channels), + .sync_stop_channels (stop_sync_channels), + .flush_dma_in (flush_dma_s), + .raw_transfer_en (raw_transfer_en[0]), + .dac_raw_ch_data (dac_raw_ch_a_data), + .trigger (trigger), + .trigger_active (trigger_active), + .en_start_trigger (en_start_trigger), + .en_stop_trigger (en_stop_trigger), + .dma_valid (dma_valid_a), + .dma_valid_adjacent (dma_valid_b), + .dac_correction_enable(dac_correction_enable_a), + .dac_correction_coefficient(dac_correction_coefficient_a)); + + axi_dac_interpolate_filter #( + .CORRECTION_DISABLE(CORRECTION_DISABLE) + ) i_filter_b ( + .dac_clk (dac_clk), + .dac_rst (dac_rst), + + .dac_data (dac_data_b), + .dac_valid (dac_valid_b), + .dac_valid_out (dac_valid_out_b), + .underflow (underflow_b), + + .dac_enable (dac_enable_b), + .dac_int_data (dac_int_data_b), + .dma_ready (dma_ready_b), + + .filter_mask (filter_mask_b), + .interpolation_ratio (interpolation_ratio_b), + .dma_transfer_suspend (dma_transfer_suspend), + .start_sync_channels (start_sync_channels), + .sync_stop_channels (stop_sync_channels), + .flush_dma_in (flush_dma_s), + .raw_transfer_en (raw_transfer_en[1]), + .dac_raw_ch_data (dac_raw_ch_b_data), + .trigger (trigger), + .trigger_active (trigger_active), + .en_start_trigger (en_start_trigger), + .en_stop_trigger (en_stop_trigger), + .dma_valid (dma_valid_b), + .dma_valid_adjacent (dma_valid_a), + .dac_correction_enable(dac_correction_enable_b), + .dac_correction_coefficient(dac_correction_coefficient_b)); + + axi_dac_interpolate_reg axi_dac_interpolate_reg_inst ( + + .clk (dac_clk), + + .dac_interpolation_ratio_a (interpolation_ratio_a), + .dac_filter_mask_a (filter_mask_a), + .dac_interpolation_ratio_b (interpolation_ratio_b), + .dac_filter_mask_b (filter_mask_b), + + .dma_transfer_suspend (dma_transfer_suspend), + .flush_dma_out (flush_dma_s), + .raw_transfer_en (raw_transfer_en), + .dac_raw_ch_a_data (dac_raw_ch_a_data), + .dac_raw_ch_b_data (dac_raw_ch_b_data), + .start_sync_channels (start_sync_channels), + .dac_correction_enable_a(dac_correction_enable_a), + .dac_correction_enable_b(dac_correction_enable_b), + .dac_correction_coefficient_a(dac_correction_coefficient_a), + .dac_correction_coefficient_b(dac_correction_coefficient_b), + .trigger_config (trigger_config), + .stop_sync_channels (stop_sync_channels), + + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + + up_axi #( + .AXI_ADDRESS_WIDTH(7) + ) i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_dac_interpolate/axi_dac_interpolate.xpr b/adi_library/axi_dac_interpolate/axi_dac_interpolate.xpr new file mode 100644 index 00000000..e323f8c7 --- /dev/null +++ b/adi_library/axi_dac_interpolate/axi_dac_interpolate.xpr @@ -0,0 +1,467 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_dac_interpolate/axi_dac_interpolate_constr.xdc b/adi_library/axi_dac_interpolate/axi_dac_interpolate_constr.xdc new file mode 100644 index 00000000..9abe44a4 --- /dev/null +++ b/adi_library/axi_dac_interpolate/axi_dac_interpolate_constr.xdc @@ -0,0 +1,12 @@ +############################################################################### +## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_i_m*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_adc_m*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *trigger_la_m*}] + +set_false_path -to [get_cells -hier -filter {name =~ *trigger_i_m1_reg* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *trigger_adc_m1_reg* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *trigger_la_m1_reg* && IS_SEQUENTIAL}] diff --git a/adi_library/axi_dac_interpolate/axi_dac_interpolate_filter.v b/adi_library/axi_dac_interpolate/axi_dac_interpolate_filter.v new file mode 100644 index 00000000..de4148bd --- /dev/null +++ b/adi_library/axi_dac_interpolate/axi_dac_interpolate_filter.v @@ -0,0 +1,291 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dac_interpolate_filter #( + + parameter CORRECTION_DISABLE = 1 +) ( + input dac_clk, + input dac_rst, + + input [15:0] dac_data, + input dac_valid, + + input dac_enable, + output reg [15:0] dac_int_data, + output dma_ready, + output dac_valid_out, + output underflow, + + input [ 2:0] filter_mask, + input [31:0] interpolation_ratio, + input [15:0] dac_correction_coefficient, + input dac_correction_enable, + input dma_transfer_suspend, + input start_sync_channels, + input sync_stop_channels, + input flush_dma_in, + input raw_transfer_en, + input [15:0] dac_raw_ch_data, + input trigger, + input trigger_active, + input en_start_trigger, + input en_stop_trigger, + input dma_valid, + input dma_valid_adjacent +); + + // local parameters + + localparam [1:0] IDLE = 0; + localparam [1:0] WAIT = 1; + localparam [1:0] TRANSFER = 2; + localparam [1:0] FLUSHING = 3; + + // internal registers + + reg dac_int_ready; + reg dac_filt_int_valid; + reg [15:0] interp_rate_cic; + reg [ 2:0] filter_mask_d1; + reg cic_change_rate; + reg [31:0] interpolation_counter; + + reg dma_data_valid = 1'b0; + reg dma_data_valid_adjacent = 1'b0; + + reg filter_enable = 1'b0; + reg [15:0] dma_valid_m = 16'd0; + reg stop_transfer = 1'd0; + + reg transfer = 1'd0; + reg [ 1:0] transfer_sm = 2'd0; + reg [ 1:0] transfer_sm_next = 2'd0; + reg raw_dma_n = 1'd0; + + // internal signals + + wire dac_valid_corrected; + wire [15:0] dac_data_corrected; + wire dac_fir_valid; + wire [35:0] dac_fir_data; + + wire dac_cic_valid; + wire [109:0] dac_cic_data; + + wire dma_valid_ch_sync; + wire dma_valid_ch; + wire flush_dma; + + wire [15:0] iqcor_data_in; + wire iqcor_valid_in; + + wire transfer_start; + wire transfer_ready; + + // Once enabled the raw value will be selected until the DMA has valid data. + // This is a workaround for when DAC channels are start/stopped independent + // of each other and working in cyclic mode at a lower samplerate. It is + // used to solve a system limitation(delay) between the application and + // Linux kernel, which resulted in a pulse at the beginning of a new buffer + // consisting in the last sample on the DMA bus. + always @(posedge dac_clk) begin + raw_dma_n <= raw_transfer_en | flush_dma ? 1'b1 : raw_dma_n & !dma_valid; + end + + assign reset_filt = !raw_dma_n & dma_transfer_suspend; + + assign iqcor_data_in = raw_dma_n ? dac_raw_ch_data : dac_data; + assign iqcor_valid_in = raw_dma_n ? 1'b1 : dac_valid; + + ad_iqcor #( + .Q_OR_I_N (0), + .DISABLE(CORRECTION_DISABLE), + .SCALE_ONLY(1) + ) i_ad_iqcor ( + .clk (dac_clk), + .valid (iqcor_valid_in), + .data_in (iqcor_data_in), + .data_iq (16'h0), + .valid_out (dac_valid_corrected), + .data_out (dac_data_corrected), + .iqcor_enable (dac_correction_enable), + .iqcor_coeff_1 (dac_correction_coefficient), + .iqcor_coeff_2 (16'h0)); + + fir_interp fir_interpolation ( + .clk (dac_clk), + .clk_enable (dac_cic_valid), + .reset (dac_rst | reset_filt), + .filter_in (dac_data_corrected), + .filter_out (dac_fir_data), + .ce_out (dac_fir_valid)); + + cic_interp cic_interpolation ( + .clk (dac_clk), + .clk_enable (dac_valid_corrected), + .reset (dac_rst | cic_change_rate | reset_filt), + .rate (interp_rate_cic), + .load_rate (1'b0), + .filter_in (dac_fir_data[30:0]), + .filter_out (dac_cic_data), + .ce_out (dac_cic_valid)); + + always @(posedge dac_clk) begin + filter_mask_d1 <= filter_mask; + if (filter_mask_d1 != filter_mask) begin + cic_change_rate <= 1'b1; + end else begin + cic_change_rate <= 1'b0; + end + end + + // - for start synchronized, wait until the DMA has valid data on both channels + // - for non synchronized channels the start of transmission gets the 2 data + // paths randomly ready, only when using data buffers + + always @(posedge dac_clk) begin + if (dac_filt_int_valid & transfer_ready) begin + if (interpolation_counter == interpolation_ratio) begin + interpolation_counter <= 0; + dac_int_ready <= 1'b1; + end else begin + interpolation_counter <= interpolation_counter + 1; + dac_int_ready <= 1'b0; + end + end else begin + dac_int_ready <= 1'b0; + interpolation_counter <= 0; + end + end + + assign transfer_ready = start_sync_channels ? + dma_valid & dma_valid_adjacent : + dma_valid; + assign transfer_start = !(en_start_trigger ^ trigger) & transfer_ready; + + always @(posedge dac_clk) begin + stop_transfer <= transfer_sm == IDLE ? 1'b0 : + stop_transfer | + dma_transfer_suspend | + (en_stop_trigger & trigger) | + (sync_stop_channels & dma_valid & dma_valid_adjacent); + end + + // transfer state machine + always @(posedge dac_clk) begin + case (transfer_sm) + IDLE: begin + transfer <= 1'b0; + if (dac_int_ready) begin + transfer_sm_next <= WAIT; + end + end + WAIT: begin + transfer <= 1'b0; + if (transfer_start) begin + transfer_sm_next <= TRANSFER; + end + end + TRANSFER: begin + transfer <= 1'b1; + if (stop_transfer) begin + if (flush_dma_in) begin + transfer_sm_next <= FLUSHING; + end else begin + transfer_sm_next <= WAIT; + end + end else if (dma_valid == 1'b0) begin + transfer_sm_next <= IDLE; + end + end + FLUSHING: begin + transfer <= 1'b1; + if (dma_valid == 1'b0) begin + transfer_sm_next <= IDLE; + end + end + endcase + transfer_sm <= transfer_sm_next; + end + + assign flush_dma = transfer_sm_next == FLUSHING ? 1'b1 : raw_transfer_en & flush_dma_in; + assign dma_ready = transfer_sm_next == TRANSFER ? dac_int_ready : flush_dma; + assign underflow = dac_enable & dma_ready & ~dma_valid & !flush_dma; + + assign dma_valid_ch = transfer | raw_transfer_en; + + always @(posedge dac_clk) begin + if (dac_rst == 1'b1) begin + dma_valid_m <= 'd0; + end else begin + dma_valid_m <= {dma_valid_m[14:0], dma_valid_ch}; + end + end + + assign dac_valid_out = dma_valid_m[2]; + + always @(posedge dac_clk) begin + case (filter_mask) + 3'b000: filter_enable <= 1'b0; + default: filter_enable <= 1'b1; + endcase + end + + always @(*) begin + case (filter_enable) + 1'b0: dac_int_data = dac_data_corrected; + default: dac_int_data = dac_cic_data[31:16]; + endcase + + case (filter_mask) + 1'b0: dac_filt_int_valid = dac_valid_corrected & !dma_transfer_suspend; + default: dac_filt_int_valid = dac_fir_valid; + endcase + + case (filter_mask) + 16'h1: interp_rate_cic = 16'd5; + 16'h2: interp_rate_cic = 16'd50; + 16'h3: interp_rate_cic = 16'd500; + 16'h6: interp_rate_cic = 16'd5000; + 16'h7: interp_rate_cic = 16'd50000; + default: interp_rate_cic = 16'd1; + endcase + + end + +endmodule diff --git a/adi_library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl b/adi_library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl new file mode 100644 index 00000000..08af40eb --- /dev/null +++ b/adi_library/axi_dac_interpolate/axi_dac_interpolate_ip.tcl @@ -0,0 +1,32 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_dac_interpolate +adi_ip_files axi_dac_interpolate [list \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/ad_iqcor.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "axi_dac_interpolate_constr.xdc" \ + "cic_interp.v" \ + "fir_interp.v" \ + "axi_dac_interpolate_reg.v" \ + "axi_dac_interpolate_filter.v" \ + "axi_dac_interpolate.v" ] + +adi_ip_properties axi_dac_interpolate + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_dac_interpolate} [ipx::current_core] + +ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/axi_dac_interpolate/axi_dac_interpolate_reg.v b/adi_library/axi_dac_interpolate/axi_dac_interpolate_reg.v new file mode 100644 index 00000000..512f9b00 --- /dev/null +++ b/adi_library/axi_dac_interpolate/axi_dac_interpolate_reg.v @@ -0,0 +1,217 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dac_interpolate_reg( + + input clk, + + output [31:0] dac_interpolation_ratio_a, + output [ 2:0] dac_filter_mask_a, + output [31:0] dac_interpolation_ratio_b, + output [ 2:0] dac_filter_mask_b, + output dma_transfer_suspend, + output flush_dma_out, + output [ 1:0] raw_transfer_en, + output [15:0] dac_raw_ch_a_data, + output [15:0] dac_raw_ch_b_data, + output start_sync_channels, + output stop_sync_channels, + output dac_correction_enable_a, + output dac_correction_enable_b, + output [15:0] dac_correction_coefficient_a, + output [15:0] dac_correction_coefficient_b, + output [19:0] trigger_config, + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [ 4:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [ 4:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack +); + + // internal registers + + reg [31:0] up_version = {16'h0002, /* MAJOR */ + 8'h03, /* MINOR */ + 8'h00}; /* PATCH */ + reg [31:0] up_scratch = 32'h0; + + reg [31:0] up_interpolation_ratio_a = 32'h0; + reg [ 2:0] up_filter_mask_a = 3'h0; + reg [31:0] up_interpolation_ratio_b = 32'h0; + reg [ 2:0] up_filter_mask_b = 3'h0; + reg [ 5:0] up_flags = 6'ha; + reg [ 1:0] up_config = 2'h0; + reg [15:0] up_correction_coefficient_a = 16'h0; + reg [15:0] up_correction_coefficient_b = 16'h0; + reg [19:0] up_trigger_config = 20'h0; + reg [15:0] up_dac_raw_ch_a_data; + reg [15:0] up_dac_raw_ch_b_data; + + wire [ 5:0] flags; + + assign dma_transfer_suspend = flags[0]; + assign start_sync_channels = flags[1]; + assign stop_sync_channels = flags[2]; + assign flush_dma_out = flags[3]; + assign raw_transfer_en = flags[5:4]; //5-b; 4-a + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_scratch <= 'd0; + up_interpolation_ratio_a <= 'd0; + up_filter_mask_a <= 'd0; + up_interpolation_ratio_b <= 'd0; + up_filter_mask_b <= 'd0; + up_flags <= 'ha; + up_config <= 'd0; + up_correction_coefficient_a <= 'd0; + up_correction_coefficient_b <= 'd0; + up_trigger_config <= 'd0; + up_dac_raw_ch_a_data <= 16'd0; + up_dac_raw_ch_b_data <= 16'd0; + end else begin + up_wack <= up_wreq; + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin + up_scratch <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h10)) begin + up_interpolation_ratio_a <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h11)) begin + up_filter_mask_a <= up_wdata[2:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h12)) begin + up_interpolation_ratio_b <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h13)) begin + up_filter_mask_b <= up_wdata[2:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h14)) begin + up_flags <= up_wdata[5:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h15)) begin + up_config <= up_wdata[1:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h16)) begin + up_correction_coefficient_a <= up_wdata[15:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h17)) begin + up_correction_coefficient_b <= up_wdata[15:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h18)) begin + up_trigger_config <= up_wdata[19:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h19)) begin + up_dac_raw_ch_a_data <= up_wdata[15:0]; + up_dac_raw_ch_b_data <= up_wdata[31:16]; + end + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq; + if (up_rreq == 1'b1) begin + case (up_raddr[4:0]) + 5'h0: up_rdata <= up_version; + 5'h1: up_rdata <= up_scratch; + 5'h10: up_rdata <= up_interpolation_ratio_a; + 5'h11: up_rdata <= {29'h0,up_filter_mask_a}; + 5'h12: up_rdata <= up_interpolation_ratio_b; + 5'h13: up_rdata <= {29'h0,up_filter_mask_b}; + 5'h14: up_rdata <= {26'h0,up_flags}; + 5'h15: up_rdata <= {30'h0,up_config}; + 5'h16: up_rdata <= {16'h0,up_correction_coefficient_a}; + 5'h17: up_rdata <= {16'h0,up_correction_coefficient_b}; + 5'h18: up_rdata <= {12'h0,up_trigger_config}; + 5'h19: up_rdata <= {up_dac_raw_ch_b_data, up_dac_raw_ch_a_data}; + default: up_rdata <= 0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + up_xfer_cntrl #( + .DATA_WIDTH(162) + ) i_xfer_cntrl ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_cntrl ({ up_config[1], // 1 + up_config[0], // 1 + up_correction_coefficient_b,// 16 + up_correction_coefficient_a,// 16 + up_trigger_config, // 20 + up_flags, // 6 + up_dac_raw_ch_a_data, // 16 + up_dac_raw_ch_b_data, // 16 + up_interpolation_ratio_b, // 32 + up_interpolation_ratio_a, // 32 + up_filter_mask_b, // 3 + up_filter_mask_a}), // 3 + + .up_xfer_done (), + .d_rst (1'b0), + .d_clk (clk), + .d_data_cntrl ({ dac_correction_enable_b, // 1 + dac_correction_enable_a, // 1 + dac_correction_coefficient_b, // 16 + dac_correction_coefficient_a, // 16 + trigger_config, // 20 + flags, // 6 + dac_raw_ch_a_data, // 16 + dac_raw_ch_b_data, // 16 + dac_interpolation_ratio_b, // 32 + dac_interpolation_ratio_a, // 32 + dac_filter_mask_b, // 3 + dac_filter_mask_a})); // 3 + +endmodule diff --git a/adi_library/axi_dac_interpolate/cic_interp.v b/adi_library/axi_dac_interpolate/cic_interp.v new file mode 100644 index 00000000..2328ed76 --- /dev/null +++ b/adi_library/axi_dac_interpolate/cic_interp.v @@ -0,0 +1,604 @@ +// ------------------------------------------------------------- +// +// Module: cic_interp +// Generated by MATLAB(R) 9.0 and the Filter Design HDL Coder 3.0. +// Generated on: 2016-07-05 11:08:04 +// ------------------------------------------------------------- + +// ------------------------------------------------------------- +// HDL Code Generation Options: +// +// OptimizeForHDL: on +// EDAScriptGeneration: off +// AddPipelineRegisters: on +// Name: cic_interp +// AddRatePort: on +// InputDataType: numerictype(1,31,30) +// TargetLanguage: Verilog +// TestBenchName: cicinterpfilt_copy_tb +// TestBenchStimulus: step ramp chirp noise +// GenerateHDLTestBench: off + +// ------------------------------------------------------------- +// HDL Implementation : Fully parallel +// ------------------------------------------------------------- +// Filter Settings: +// +// Discrete-Time FIR Multirate Filter (real) +// ----------------------------------------- +// Filter Structure : Cascaded Integrator-Comb Interpolator +// Interpolation Factor : 50000 +// Differential Delay : 1 +// Number of Sections : 6 +// Stable : Yes +// Linear Phase : No +// +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module cic_interp ( + input clk, + input clk_enable, + input reset, + input signed [30:0] filter_in, //sfix31_En30 + input [15:0] rate, //ufix16 + input load_rate, + output signed [109:0] filter_out, //sfix110_En30 + output ce_out +); + +//////////////////////////////////////////////////////////////// +//Module Architecture: cic_interp +//////////////////////////////////////////////////////////////// + // Local Functions + // Type Definitions + // Constants + parameter signed [35:0] zeroconst = 36'h000000000; //sfix36_En30 + // Signals + wire [15:0] rate_unsigned; // ufix16 + reg [15:0] cur_count = 0; // ufix16 + wire phase_0; // boolean + // + reg signed [30:0] input_register = 0; // sfix31_En30 + // -- Section 1 Signals + wire signed [30:0] section_in1; // sfix31_En30 + wire signed [31:0] section_cast1; // sfix32_En30 + reg signed [31:0] diff1 = 0; // sfix32_En30 + wire signed [31:0] section_out1; // sfix32_En30 + wire signed [31:0] sub_cast; // sfix32_En30 + wire signed [31:0] sub_cast_1; // sfix32_En30 + wire signed [32:0] sub_temp; // sfix33_En30 + reg signed [31:0] cic_pipeline1 = 0; // sfix32_En30 + // -- Section 2 Signals + wire signed [31:0] section_in2; // sfix32_En30 + wire signed [32:0] section_cast2; // sfix33_En30 + reg signed [32:0] diff2 = 0; // sfix33_En30 + wire signed [32:0] section_out2; // sfix33_En30 + wire signed [32:0] sub_cast_2; // sfix33_En30 + wire signed [32:0] sub_cast_3; // sfix33_En30 + wire signed [33:0] sub_temp_1; // sfix34_En30 + reg signed [32:0] cic_pipeline2 = 0; // sfix33_En30 + // -- Section 3 Signals + wire signed [32:0] section_in3; // sfix33_En30 + wire signed [33:0] section_cast3; // sfix34_En30 + reg signed [33:0] diff3 = 0; // sfix34_En30 + wire signed [33:0] section_out3; // sfix34_En30 + wire signed [33:0] sub_cast_4; // sfix34_En30 + wire signed [33:0] sub_cast_5; // sfix34_En30 + wire signed [34:0] sub_temp_2; // sfix35_En30 + reg signed [33:0] cic_pipeline3 = 0; // sfix34_En30 + // -- Section 4 Signals + wire signed [33:0] section_in4; // sfix34_En30 + wire signed [34:0] section_cast4; // sfix35_En30 + reg signed [34:0] diff4 = 0; // sfix35_En30 + wire signed [34:0] section_out4; // sfix35_En30 + wire signed [34:0] sub_cast_6; // sfix35_En30 + wire signed [34:0] sub_cast_7; // sfix35_En30 + wire signed [35:0] sub_temp_3; // sfix36_En30 + reg signed [34:0] cic_pipeline4 = 0; // sfix35_En30 + // -- Section 5 Signals + wire signed [34:0] section_in5; // sfix35_En30 + wire signed [35:0] section_cast5; // sfix36_En30 + reg signed [35:0] diff5 = 0; // sfix36_En30 + wire signed [35:0] section_out5; // sfix36_En30 + wire signed [35:0] sub_cast_8; // sfix36_En30 + wire signed [35:0] sub_cast_9; // sfix36_En30 + wire signed [36:0] sub_temp_4; // sfix37_En30 + reg signed [35:0] cic_pipeline5 = 0; // sfix36_En30 + // -- Section 6 Signals + wire signed [35:0] section_in6; // sfix36_En30 + reg signed [35:0] diff6 = 0; // sfix36_En30 + wire signed [35:0] section_out6; // sfix36_En30 + wire signed [35:0] sub_cast_10; // sfix36_En30 + wire signed [35:0] sub_cast_11; // sfix36_En30 + wire signed [36:0] sub_temp_5; // sfix37_En30 + reg signed [35:0] cic_pipeline6 = 0; // sfix36_En30 + wire signed [35:0] upsampling; // sfix36_En30 + // -- Section 7 Signals + wire signed [35:0] section_in7; // sfix36_En30 + wire signed [35:0] sum1; // sfix36_En30 + reg signed [35:0] section_out7 = 0; // sfix36_En30 + wire signed [35:0] add_cast; // sfix36_En30 + wire signed [35:0] add_cast_1; // sfix36_En30 + wire signed [36:0] add_temp; // sfix37_En30 + // -- Section 8 Signals + wire signed [35:0] section_in8; // sfix36_En30 + wire signed [50:0] section_cast8; // sfix51_En30 + wire signed [50:0] sum2; // sfix51_En30 + reg signed [50:0] section_out8 = 0; // sfix51_En30 + wire signed [50:0] add_cast_2; // sfix51_En30 + wire signed [50:0] add_cast_3; // sfix51_En30 + wire signed [51:0] add_temp_1; // sfix52_En30 + // -- Section 9 Signals + wire signed [50:0] section_in9; // sfix51_En30 + wire signed [65:0] section_cast9; // sfix66_En30 + wire signed [65:0] sum3; // sfix66_En30 + reg signed [65:0] section_out9 = 0; // sfix66_En30 + wire signed [65:0] add_cast_4; // sfix66_En30 + wire signed [65:0] add_cast_5; // sfix66_En30 + wire signed [66:0] add_temp_2; // sfix67_En30 + // -- Section 10 Signals + wire signed [65:0] section_in10; // sfix66_En30 + wire signed [79:0] section_cast10; // sfix80_En30 + wire signed [79:0] sum4; // sfix80_En30 + reg signed [79:0] section_out10 = 0; // sfix80_En30 + wire signed [79:0] add_cast_6; // sfix80_En30 + wire signed [79:0] add_cast_7; // sfix80_En30 + wire signed [80:0] add_temp_3; // sfix81_En30 + // -- Section 11 Signals + wire signed [79:0] section_in11; // sfix80_En30 + wire signed [94:0] section_cast11; // sfix95_En30 + wire signed [94:0] sum5; // sfix95_En30 + reg signed [94:0] section_out11 = 0; // sfix95_En30 + wire signed [94:0] add_cast_8; // sfix95_En30 + wire signed [94:0] add_cast_9; // sfix95_En30 + wire signed [95:0] add_temp_4; // sfix96_En30 + // -- Section 12 Signals + wire signed [94:0] section_in12; // sfix95_En30 + wire signed [109:0] section_cast12; // sfix110_En30 + wire signed [109:0] sum6; // sfix110_En30 + reg signed [109:0] section_out12 = 0; // sfix110_En30 + wire signed [109:0] add_cast_10; // sfix110_En30 + wire signed [109:0] add_cast_11; // sfix110_En30 + wire signed [110:0] add_temp_5; // sfix111_En30 + reg [6:0] bitgain = 0; // ufix7 + wire signed [109:0] output_typeconvert; // sfix110_En30 + wire signed [109:0] muxinput_14; // sfix110_En16 + wire signed [109:0] muxinput_34; // sfix110_E4 + wire signed [109:0] muxinput_54; // sfix110_E24 + wire signed [109:0] muxinput_74; // sfix110_E44 + wire signed [109:0] muxinput_94; // sfix110_E64 + // + reg signed [109:0] output_register = 0; // sfix110_En30 + + // Block Statements + assign rate_unsigned = rate; + + always @ (posedge clk or posedge reset) + begin: ce_output + if (reset == 1'b1) begin + cur_count <= 16'b0000000000000000; + end + else begin + if (clk_enable == 1'b1) begin + if (load_rate == 1'b1) begin + cur_count <= 16'b0000000000000001; + end + else if (cur_count == rate_unsigned - 1) begin + cur_count <= 16'b0000000000000000; + end + else begin + cur_count <= cur_count + 1; + end + end + end + end // ce_output + + assign phase_0 = (cur_count == 16'b0000000000000000 && clk_enable == 1'b1)? 1 : 0; + + // ------------------ Input Register ------------------ + + always @ (posedge clk or posedge reset) + begin: input_reg_process + if (reset == 1'b1) begin + input_register <= 0; + end + else begin + if (phase_0 == 1'b1) begin + input_register <= filter_in; + end + end + end // input_reg_process + + // ------------------ Section # 1 : Comb ------------------ + + assign section_in1 = input_register; + + assign section_cast1 = $signed({{1{section_in1[30]}}, section_in1}); + + assign sub_cast = section_cast1; + assign sub_cast_1 = diff1; + assign sub_temp = sub_cast - sub_cast_1; + assign section_out1 = sub_temp[31:0]; + + always @ (posedge clk or posedge reset) + begin: comb_delay_section1 + if (reset == 1'b1) begin + diff1 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + diff1 <= section_cast1; + end + end + end // comb_delay_section1 + + always @ (posedge clk or posedge reset) + begin: cic_pipeline_process_section1 + if (reset == 1'b1) begin + cic_pipeline1 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + cic_pipeline1 <= section_out1; + end + end + end // cic_pipeline_process_section1 + + // ------------------ Section # 2 : Comb ------------------ + + assign section_in2 = cic_pipeline1; + + assign section_cast2 = $signed({{1{section_in2[31]}}, section_in2}); + + assign sub_cast_2 = section_cast2; + assign sub_cast_3 = diff2; + assign sub_temp_1 = sub_cast_2 - sub_cast_3; + assign section_out2 = sub_temp_1[32:0]; + + always @ (posedge clk or posedge reset) + begin: comb_delay_section2 + if (reset == 1'b1) begin + diff2 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + diff2 <= section_cast2; + end + end + end // comb_delay_section2 + + always @ (posedge clk or posedge reset) + begin: cic_pipeline_process_section2 + if (reset == 1'b1) begin + cic_pipeline2 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + cic_pipeline2 <= section_out2; + end + end + end // cic_pipeline_process_section2 + + // ------------------ Section # 3 : Comb ------------------ + + assign section_in3 = cic_pipeline2; + + assign section_cast3 = $signed({{1{section_in3[32]}}, section_in3}); + + assign sub_cast_4 = section_cast3; + assign sub_cast_5 = diff3; + assign sub_temp_2 = sub_cast_4 - sub_cast_5; + assign section_out3 = sub_temp_2[33:0]; + + always @ (posedge clk or posedge reset) + begin: comb_delay_section3 + if (reset == 1'b1) begin + diff3 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + diff3 <= section_cast3; + end + end + end // comb_delay_section3 + + always @ (posedge clk or posedge reset) + begin: cic_pipeline_process_section3 + if (reset == 1'b1) begin + cic_pipeline3 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + cic_pipeline3 <= section_out3; + end + end + end // cic_pipeline_process_section3 + + // ------------------ Section # 4 : Comb ------------------ + + assign section_in4 = cic_pipeline3; + + assign section_cast4 = $signed({{1{section_in4[33]}}, section_in4}); + + assign sub_cast_6 = section_cast4; + assign sub_cast_7 = diff4; + assign sub_temp_3 = sub_cast_6 - sub_cast_7; + assign section_out4 = sub_temp_3[34:0]; + + always @ (posedge clk or posedge reset) + begin: comb_delay_section4 + if (reset == 1'b1) begin + diff4 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + diff4 <= section_cast4; + end + end + end // comb_delay_section4 + + always @ (posedge clk or posedge reset) + begin: cic_pipeline_process_section4 + if (reset == 1'b1) begin + cic_pipeline4 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + cic_pipeline4 <= section_out4; + end + end + end // cic_pipeline_process_section4 + + // ------------------ Section # 5 : Comb ------------------ + + assign section_in5 = cic_pipeline4; + + assign section_cast5 = $signed({{1{section_in5[34]}}, section_in5}); + + assign sub_cast_8 = section_cast5; + assign sub_cast_9 = diff5; + assign sub_temp_4 = sub_cast_8 - sub_cast_9; + assign section_out5 = sub_temp_4[35:0]; + + always @ (posedge clk or posedge reset) + begin: comb_delay_section5 + if (reset == 1'b1) begin + diff5 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + diff5 <= section_cast5; + end + end + end // comb_delay_section5 + + always @ (posedge clk or posedge reset) + begin: cic_pipeline_process_section5 + if (reset == 1'b1) begin + cic_pipeline5 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + cic_pipeline5 <= section_out5; + end + end + end // cic_pipeline_process_section5 + + // ------------------ Section # 6 : Comb ------------------ + + assign section_in6 = cic_pipeline5; + + assign sub_cast_10 = section_in6; + assign sub_cast_11 = diff6; + assign sub_temp_5 = sub_cast_10 - sub_cast_11; + assign section_out6 = sub_temp_5[35:0]; + + always @ (posedge clk or posedge reset) + begin: comb_delay_section6 + if (reset == 1'b1) begin + diff6 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + diff6 <= section_in6; + end + end + end // comb_delay_section6 + + always @ (posedge clk or posedge reset) + begin: cic_pipeline_process_section6 + if (reset == 1'b1) begin + cic_pipeline6 <= 0; + end + else begin + if (phase_0 == 1'b1) begin + cic_pipeline6 <= section_out6; + end + end + end // cic_pipeline_process_section6 + + assign upsampling = (phase_0 == 1'b1) ? cic_pipeline6 : + zeroconst; + // ------------------ Section # 7 : Integrator ------------------ + + assign section_in7 = upsampling; + + assign add_cast = section_in7; + assign add_cast_1 = section_out7; + assign add_temp = add_cast + add_cast_1; + assign sum1 = add_temp[35:0]; + + always @ (posedge clk or posedge reset) + begin: integrator_delay_section7 + if (reset == 1'b1) begin + section_out7 <= 0; + end + else begin + if (clk_enable == 1'b1) begin + section_out7 <= sum1; + end + end + end // integrator_delay_section7 + + // ------------------ Section # 8 : Integrator ------------------ + + assign section_in8 = section_out7; + + assign section_cast8 = $signed({{15{section_in8[35]}}, section_in8}); + + assign add_cast_2 = section_cast8; + assign add_cast_3 = section_out8; + assign add_temp_1 = add_cast_2 + add_cast_3; + assign sum2 = add_temp_1[50:0]; + + always @ (posedge clk or posedge reset) + begin: integrator_delay_section8 + if (reset == 1'b1) begin + section_out8 <= 0; + end + else begin + if (clk_enable == 1'b1) begin + section_out8 <= sum2; + end + end + end // integrator_delay_section8 + + // ------------------ Section # 9 : Integrator ------------------ + + assign section_in9 = section_out8; + + assign section_cast9 = $signed({{15{section_in9[50]}}, section_in9}); + + assign add_cast_4 = section_cast9; + assign add_cast_5 = section_out9; + assign add_temp_2 = add_cast_4 + add_cast_5; + assign sum3 = add_temp_2[65:0]; + + always @ (posedge clk or posedge reset) + begin: integrator_delay_section9 + if (reset == 1'b1) begin + section_out9 <= 0; + end + else begin + if (clk_enable == 1'b1) begin + section_out9 <= sum3; + end + end + end // integrator_delay_section9 + + // ------------------ Section # 10 : Integrator ------------------ + + assign section_in10 = section_out9; + + assign section_cast10 = $signed({{14{section_in10[65]}}, section_in10}); + + assign add_cast_6 = section_cast10; + assign add_cast_7 = section_out10; + assign add_temp_3 = add_cast_6 + add_cast_7; + assign sum4 = add_temp_3[79:0]; + + always @ (posedge clk or posedge reset) + begin: integrator_delay_section10 + if (reset == 1'b1) begin + section_out10 <= 0; + end + else begin + if (clk_enable == 1'b1) begin + section_out10 <= sum4; + end + end + end // integrator_delay_section10 + + // ------------------ Section # 11 : Integrator ------------------ + + assign section_in11 = section_out10; + + assign section_cast11 = $signed({{15{section_in11[79]}}, section_in11}); + + assign add_cast_8 = section_cast11; + assign add_cast_9 = section_out11; + assign add_temp_4 = add_cast_8 + add_cast_9; + assign sum5 = add_temp_4[94:0]; + + always @ (posedge clk or posedge reset) + begin: integrator_delay_section11 + if (reset == 1'b1) begin + section_out11 <= 0; + end + else begin + if (clk_enable == 1'b1) begin + section_out11 <= sum5; + end + end + end // integrator_delay_section11 + + // ------------------ Section # 12 : Integrator ------------------ + + assign section_in12 = section_out11; + + assign section_cast12 = $signed({{15{section_in12[94]}}, section_in12}); + + assign add_cast_10 = section_cast12; + assign add_cast_11 = section_out12; + assign add_temp_5 = add_cast_10 + add_cast_11; + assign sum6 = add_temp_5[109:0]; + + always @ (posedge clk or posedge reset) + begin: integrator_delay_section12 + if (reset == 1'b1) begin + section_out12 <= 0; + end + else begin + if (clk_enable == 1'b1) begin + section_out12 <= sum6; + end + end + end // integrator_delay_section12 + + always @(rate_unsigned) + begin + case(rate_unsigned) + 16'b0000000000000101 : bitgain = 7'b0001110; + 16'b0000000000110010 : bitgain = 7'b0100010; + 16'b0000000111110100 : bitgain = 7'b0110110; + 16'b0001001110001000 : bitgain = 7'b1001010; + 16'b1100001101010000 : bitgain = 7'b1011110; + default : bitgain = 7'b1011110; + endcase + end + + assign muxinput_14 = $signed({{10{section_out12[109]}}, section_out12[109:10]}); + + assign muxinput_34 = $signed({{27{section_out12[109]}}, section_out12[109:27]}); + + assign muxinput_54 = $signed({{43{section_out12[109]}}, section_out12[109:43]}); + + assign muxinput_74 = $signed({{60{section_out12[109]}}, section_out12[109:60]}); + + assign muxinput_94 = $signed({{77{section_out12[109]}}, section_out12[109:77]}); + + assign output_typeconvert = (bitgain == 7'b0001110) ? muxinput_14 : + (bitgain == 7'b0100010) ? muxinput_34 : + (bitgain == 7'b0110110) ? muxinput_54 : + (bitgain == 7'b1001010) ? muxinput_74 : + muxinput_94; + // ------------------ Output Register ------------------ + + always @ (posedge clk or posedge reset) + begin: output_reg_process + if (reset == 1'b1) begin + output_register <= 0; + end + else begin + if (clk_enable == 1'b1) begin + output_register <= output_typeconvert; + end + end + end // output_reg_process + + // Assignment Statements + assign ce_out = phase_0; + assign filter_out = output_register; +endmodule diff --git a/adi_library/axi_dac_interpolate/component.xml b/adi_library/axi_dac_interpolate/component.xml new file mode 100644 index 00000000..73375eab --- /dev/null +++ b/adi_library/axi_dac_interpolate/component.xml @@ -0,0 +1,1120 @@ + + + analog.com + user + axi_dac_interpolate + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + dac_clk + + + + + + + CLK + + + dac_clk + + + + + + ASSOCIATED_RESET + dac_rst + + + + + dac_rst + + + + + + + RST + + + dac_rst + + + + + + + + s_axi + + axi_lite + 0 + 128 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_dac_interpolate + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 5150ad67 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_dac_interpolate + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 1edce4b6 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 18feff19 + + + + + + + dac_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_rst + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_data_a + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + dac_data_b + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + dac_valid_a + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_valid_b + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_valid_a + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_valid_b + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_ready_a + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_ready_b + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_enable_a + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_enable_b + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_int_data_a + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_int_data_b + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_valid_out_a + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_valid_out_b + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + underflow + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + trigger_i + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + trigger_adc + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + trigger_la + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 6 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 6 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + CORRECTION_DISABLE + Correction Disable + 1 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + axi_dac_interpolate_constr.xdc + xdc + + + ../common/ad_iqcor.v + verilogSource + + + ../xilinx/common/ad_mul.v + verilogSource + + + axi_dac_interpolate_filter.v + verilogSource + + + axi_dac_interpolate_reg.v + verilogSource + + + cic_interp.v + verilogSource + + + fir_interp.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + axi_dac_interpolate.v + verilogSource + CHECKSUM_c33a1894 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_iqcor.v + verilogSource + + + ../xilinx/common/ad_mul.v + verilogSource + + + axi_dac_interpolate_filter.v + verilogSource + + + axi_dac_interpolate_reg.v + verilogSource + + + cic_interp.v + verilogSource + + + fir_interp.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + axi_dac_interpolate.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_dac_interpolate_v1_0.tcl + tclSource + CHECKSUM_18feff19 + XGUI_VERSION_2 + + + + axi_dac_interpolate_v1_0 + + + CORRECTION_DISABLE + Correction Disable + 1 + + + Component_Name + axi_dac_interpolate_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_dac_interpolate_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_dac_interpolate + 1 + 2024-01-14T03:45:32Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_dac_interpolate/fir_interp.v b/adi_library/axi_dac_interpolate/fir_interp.v new file mode 100644 index 00000000..8b2b43ad --- /dev/null +++ b/adi_library/axi_dac_interpolate/fir_interp.v @@ -0,0 +1,381 @@ +// ------------------------------------------------------------- +// +// Module: fir_interp +// Generated by MATLAB(R) 9.0 and the Filter Design HDL Coder 3.0. +// Generated on: 2016-07-05 15:54:12 +// ------------------------------------------------------------- + +// ------------------------------------------------------------- +// HDL Code Generation Options: +// +// FIRAdderStyle: tree +// OptimizeForHDL: on +// EDAScriptGeneration: off +// AddPipelineRegisters: on +// Name: fir_interp +// TargetLanguage: Verilog +// TestBenchName: fo_copy_tb +// TestBenchStimulus: step ramp chirp noise +// GenerateHDLTestBench: off + +// ------------------------------------------------------------- +// HDL Implementation : Fully parallel +// Multipliers : 12 +// Folding Factor : 1 +// ------------------------------------------------------------- +// Filter Settings: +// +// Discrete-Time FIR Multirate Filter (real) +// ----------------------------------------- +// Filter Structure : Direct-Form FIR Polyphase Interpolator +// Interpolation Factor : 2 +// Polyphase Length : 12 +// Filter Length : 24 +// Stable : Yes +// Linear Phase : Yes (Type 2) +// +// Arithmetic : fixed +// Numerator : s16,15 -> [-1 1) +// ------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +module fir_interp ( + input clk, + input clk_enable, + input reset, + input signed [15:0] filter_in, //sfix16_En15 + output signed [35:0] filter_out, //sfix36_En30 + output ce_out +); + +//////////////////////////////////////////////////////////////// +//Module Architecture: fir_interp +//////////////////////////////////////////////////////////////// + // Local Functions + // Type Definitions + // Constants + parameter signed [15:0] coeffphase1_1 = 16'b1111111110101001; //sfix16_En15 + parameter signed [15:0] coeffphase1_2 = 16'b1111111101111010; //sfix16_En15 + parameter signed [15:0] coeffphase1_3 = 16'b0000010011111111; //sfix16_En15 + parameter signed [15:0] coeffphase1_4 = 16'b1111101010101110; //sfix16_En15 + parameter signed [15:0] coeffphase1_5 = 16'b1111001001101000; //sfix16_En15 + parameter signed [15:0] coeffphase1_6 = 16'b0011011010110011; //sfix16_En15 + parameter signed [15:0] coeffphase1_7 = 16'b0101011100111111; //sfix16_En15 + parameter signed [15:0] coeffphase1_8 = 16'b0000110010011010; //sfix16_En15 + parameter signed [15:0] coeffphase1_9 = 16'b1111000000000010; //sfix16_En15 + parameter signed [15:0] coeffphase1_10 = 16'b0000001110101000; //sfix16_En15 + parameter signed [15:0] coeffphase1_11 = 16'b0000000111110010; //sfix16_En15 + parameter signed [15:0] coeffphase1_12 = 16'b1111111100011100; //sfix16_En15 + parameter signed [15:0] coeffphase2_1 = 16'b1111111100011100; //sfix16_En15 + parameter signed [15:0] coeffphase2_2 = 16'b0000000111110010; //sfix16_En15 + parameter signed [15:0] coeffphase2_3 = 16'b0000001110101000; //sfix16_En15 + parameter signed [15:0] coeffphase2_4 = 16'b1111000000000010; //sfix16_En15 + parameter signed [15:0] coeffphase2_5 = 16'b0000110010011010; //sfix16_En15 + parameter signed [15:0] coeffphase2_6 = 16'b0101011100111111; //sfix16_En15 + parameter signed [15:0] coeffphase2_7 = 16'b0011011010110011; //sfix16_En15 + parameter signed [15:0] coeffphase2_8 = 16'b1111001001101000; //sfix16_En15 + parameter signed [15:0] coeffphase2_9 = 16'b1111101010101110; //sfix16_En15 + parameter signed [15:0] coeffphase2_10 = 16'b0000010011111111; //sfix16_En15 + parameter signed [15:0] coeffphase2_11 = 16'b1111111101111010; //sfix16_En15 + parameter signed [15:0] coeffphase2_12 = 16'b1111111110101001; //sfix16_En15 + + // Signals + reg [1:0] cur_count = 0; // ufix2 + wire phase_1; // boolean + reg signed [15:0] delay_pipeline [0:11]; // sfix16_En15 + wire signed [31:0] product; // sfix32_En30 + wire signed [15:0] product_mux; // sfix16_En15 + wire signed [31:0] product_1; // sfix32_En30 + wire signed [15:0] product_mux_1; // sfix16_En15 + wire signed [31:0] product_2; // sfix32_En30 + wire signed [15:0] product_mux_2; // sfix16_En15 + wire signed [31:0] product_3; // sfix32_En30 + wire signed [15:0] product_mux_3; // sfix16_En15 + wire signed [31:0] product_4; // sfix32_En30 + wire signed [15:0] product_mux_4; // sfix16_En15 + wire signed [31:0] product_5; // sfix32_En30 + wire signed [15:0] product_mux_5; // sfix16_En15 + wire signed [31:0] product_6; // sfix32_En30 + wire signed [15:0] product_mux_6; // sfix16_En15 + wire signed [31:0] product_7; // sfix32_En30 + wire signed [15:0] product_mux_7; // sfix16_En15 + wire signed [31:0] product_8; // sfix32_En30 + wire signed [15:0] product_mux_8; // sfix16_En15 + wire signed [31:0] product_9; // sfix32_En30 + wire signed [15:0] product_mux_9; // sfix16_En15 + wire signed [31:0] product_10; // sfix32_En30 + wire signed [15:0] product_mux_10; // sfix16_En15 + wire signed [31:0] product_11; // sfix32_En30 + wire signed [15:0] product_mux_11; // sfix16_En15 + wire signed [35:0] sumvector1 [0:5] ; // sfix36_En30 + wire signed [31:0] add_signext; // sfix32_En30 + wire signed [31:0] add_signext_1; // sfix32_En30 + wire signed [32:0] add_temp; // sfix33_En30 + wire signed [31:0] add_signext_2; // sfix32_En30 + wire signed [31:0] add_signext_3; // sfix32_En30 + wire signed [32:0] add_temp_1; // sfix33_En30 + wire signed [31:0] add_signext_4; // sfix32_En30 + wire signed [31:0] add_signext_5; // sfix32_En30 + wire signed [32:0] add_temp_2; // sfix33_En30 + wire signed [31:0] add_signext_6; // sfix32_En30 + wire signed [31:0] add_signext_7; // sfix32_En30 + wire signed [32:0] add_temp_3; // sfix33_En30 + wire signed [31:0] add_signext_8; // sfix32_En30 + wire signed [31:0] add_signext_9; // sfix32_En30 + wire signed [32:0] add_temp_4; // sfix33_En30 + wire signed [31:0] add_signext_10; // sfix32_En30 + wire signed [31:0] add_signext_11; // sfix32_En30 + wire signed [32:0] add_temp_5; // sfix33_En30 + reg signed [35:0] sumdelay_pipeline1 [0:5]; // sfix36_En30 + wire signed [35:0] sumvector2 [0:2] ; // sfix36_En30 + wire signed [35:0] add_signext_12; // sfix36_En30 + wire signed [35:0] add_signext_13; // sfix36_En30 + wire signed [36:0] add_temp_6; // sfix37_En30 + wire signed [35:0] add_signext_14; // sfix36_En30 + wire signed [35:0] add_signext_15; // sfix36_En30 + wire signed [36:0] add_temp_7; // sfix37_En30 + wire signed [35:0] add_signext_16; // sfix36_En30 + wire signed [35:0] add_signext_17; // sfix36_En30 + wire signed [36:0] add_temp_8; // sfix37_En30 + reg signed [35:0] sumdelay_pipeline2 [0:2]; // sfix36_En30 + wire signed [35:0] sumvector3 [0:1] ; // sfix36_En30 + wire signed [35:0] add_signext_18; // sfix36_En30 + wire signed [35:0] add_signext_19; // sfix36_En30 + wire signed [36:0] add_temp_9; // sfix37_En30 + reg signed [35:0] sumdelay_pipeline3 [0:1]; // sfix36_En30 + wire signed [35:0] sum4; // sfix36_En30 + wire signed [35:0] add_signext_20; // sfix36_En30 + wire signed [35:0] add_signext_21; // sfix36_En30 + wire signed [36:0] add_temp_10; // sfix37_En30 + reg signed [35:0] output_register = 0; // sfix36_En30 + + // Block Statements + always @ (posedge clk or posedge reset) + begin: ce_output + if (reset == 1'b1) begin + cur_count <= 2'b00; + end + else begin + if (clk_enable == 1'b1) begin + if (cur_count == 2'b01) begin + cur_count <= 2'b00; + end + else begin + cur_count <= cur_count + 1; + end + end + end + end // ce_output + + assign phase_1 = (cur_count == 2'b01 && clk_enable == 1'b1)? 1 : 0; + + // ---------------- Delay Registers ---------------- + + always @( posedge clk or posedge reset) + begin: Delay_Pipeline_process + if (reset == 1'b1) begin + delay_pipeline[0] <= 0; + delay_pipeline[1] <= 0; + delay_pipeline[2] <= 0; + delay_pipeline[3] <= 0; + delay_pipeline[4] <= 0; + delay_pipeline[5] <= 0; + delay_pipeline[6] <= 0; + delay_pipeline[7] <= 0; + delay_pipeline[8] <= 0; + delay_pipeline[9] <= 0; + delay_pipeline[10] <= 0; + delay_pipeline[11] <= 0; + end + else begin + if (phase_1 == 1'b1) begin + delay_pipeline[0] <= filter_in; + delay_pipeline[1] <= delay_pipeline[0]; + delay_pipeline[2] <= delay_pipeline[1]; + delay_pipeline[3] <= delay_pipeline[2]; + delay_pipeline[4] <= delay_pipeline[3]; + delay_pipeline[5] <= delay_pipeline[4]; + delay_pipeline[6] <= delay_pipeline[5]; + delay_pipeline[7] <= delay_pipeline[6]; + delay_pipeline[8] <= delay_pipeline[7]; + delay_pipeline[9] <= delay_pipeline[8]; + delay_pipeline[10] <= delay_pipeline[9]; + delay_pipeline[11] <= delay_pipeline[10]; + end + end + end // Delay_Pipeline_process + + assign product_mux = (cur_count == 2'b00) ? coeffphase1_12 : + coeffphase2_12; + assign product = delay_pipeline[11] * product_mux; + + assign product_mux_1 = (cur_count == 2'b00) ? coeffphase1_11 : + coeffphase2_11; + assign product_1 = delay_pipeline[10] * product_mux_1; + + assign product_mux_2 = (cur_count == 2'b00) ? coeffphase1_10 : + coeffphase2_10; + assign product_2 = delay_pipeline[9] * product_mux_2; + + assign product_mux_3 = (cur_count == 2'b00) ? coeffphase1_9 : + coeffphase2_9; + assign product_3 = delay_pipeline[8] * product_mux_3; + + assign product_mux_4 = (cur_count == 2'b00) ? coeffphase1_8 : + coeffphase2_8; + assign product_4 = delay_pipeline[7] * product_mux_4; + + assign product_mux_5 = (cur_count == 2'b00) ? coeffphase1_7 : + coeffphase2_7; + assign product_5 = delay_pipeline[6] * product_mux_5; + + assign product_mux_6 = (cur_count == 2'b00) ? coeffphase1_6 : + coeffphase2_6; + assign product_6 = delay_pipeline[5] * product_mux_6; + + assign product_mux_7 = (cur_count == 2'b00) ? coeffphase1_5 : + coeffphase2_5; + assign product_7 = delay_pipeline[4] * product_mux_7; + + assign product_mux_8 = (cur_count == 2'b00) ? coeffphase1_4 : + coeffphase2_4; + assign product_8 = delay_pipeline[3] * product_mux_8; + + assign product_mux_9 = (cur_count == 2'b00) ? coeffphase1_3 : + coeffphase2_3; + assign product_9 = delay_pipeline[2] * product_mux_9; + + assign product_mux_10 = (cur_count == 2'b00) ? coeffphase1_2 : + coeffphase2_2; + assign product_10 = delay_pipeline[1] * product_mux_10; + + assign product_mux_11 = (cur_count == 2'b00) ? coeffphase1_1 : + coeffphase2_1; + assign product_11 = delay_pipeline[0] * product_mux_11; + + assign add_signext = product; + assign add_signext_1 = product_1; + assign add_temp = add_signext + add_signext_1; + assign sumvector1[0] = $signed({{3{add_temp[32]}}, add_temp}); + + assign add_signext_2 = product_2; + assign add_signext_3 = product_3; + assign add_temp_1 = add_signext_2 + add_signext_3; + assign sumvector1[1] = $signed({{3{add_temp_1[32]}}, add_temp_1}); + + assign add_signext_4 = product_4; + assign add_signext_5 = product_5; + assign add_temp_2 = add_signext_4 + add_signext_5; + assign sumvector1[2] = $signed({{3{add_temp_2[32]}}, add_temp_2}); + + assign add_signext_6 = product_6; + assign add_signext_7 = product_7; + assign add_temp_3 = add_signext_6 + add_signext_7; + assign sumvector1[3] = $signed({{3{add_temp_3[32]}}, add_temp_3}); + + assign add_signext_8 = product_8; + assign add_signext_9 = product_9; + assign add_temp_4 = add_signext_8 + add_signext_9; + assign sumvector1[4] = $signed({{3{add_temp_4[32]}}, add_temp_4}); + + assign add_signext_10 = product_10; + assign add_signext_11 = product_11; + assign add_temp_5 = add_signext_10 + add_signext_11; + assign sumvector1[5] = $signed({{3{add_temp_5[32]}}, add_temp_5}); + + always @ (posedge clk or posedge reset) + begin: sumdelay_pipeline_process1 + if (reset == 1'b1) begin + sumdelay_pipeline1[0] <= 0; + sumdelay_pipeline1[1] <= 0; + sumdelay_pipeline1[2] <= 0; + sumdelay_pipeline1[3] <= 0; + sumdelay_pipeline1[4] <= 0; + sumdelay_pipeline1[5] <= 0; + end + else begin + if (clk_enable == 1'b1) begin + sumdelay_pipeline1[0] <= sumvector1[0]; + sumdelay_pipeline1[1] <= sumvector1[1]; + sumdelay_pipeline1[2] <= sumvector1[2]; + sumdelay_pipeline1[3] <= sumvector1[3]; + sumdelay_pipeline1[4] <= sumvector1[4]; + sumdelay_pipeline1[5] <= sumvector1[5]; + end + end + end // sumdelay_pipeline_process1 + + assign add_signext_12 = sumdelay_pipeline1[0]; + assign add_signext_13 = sumdelay_pipeline1[1]; + assign add_temp_6 = add_signext_12 + add_signext_13; + assign sumvector2[0] = add_temp_6[35:0]; + + assign add_signext_14 = sumdelay_pipeline1[2]; + assign add_signext_15 = sumdelay_pipeline1[3]; + assign add_temp_7 = add_signext_14 + add_signext_15; + assign sumvector2[1] = add_temp_7[35:0]; + + assign add_signext_16 = sumdelay_pipeline1[4]; + assign add_signext_17 = sumdelay_pipeline1[5]; + assign add_temp_8 = add_signext_16 + add_signext_17; + assign sumvector2[2] = add_temp_8[35:0]; + + always @ (posedge clk or posedge reset) + begin: sumdelay_pipeline_process2 + if (reset == 1'b1) begin + sumdelay_pipeline2[0] <= 0; + sumdelay_pipeline2[1] <= 0; + sumdelay_pipeline2[2] <= 0; + end + else begin + if (clk_enable == 1'b1) begin + sumdelay_pipeline2[0] <= sumvector2[0]; + sumdelay_pipeline2[1] <= sumvector2[1]; + sumdelay_pipeline2[2] <= sumvector2[2]; + end + end + end // sumdelay_pipeline_process2 + + assign add_signext_18 = sumdelay_pipeline2[0]; + assign add_signext_19 = sumdelay_pipeline2[1]; + assign add_temp_9 = add_signext_18 + add_signext_19; + assign sumvector3[0] = add_temp_9[35:0]; + + assign sumvector3[1] = sumdelay_pipeline2[2]; + + always @ (posedge clk or posedge reset) + begin: sumdelay_pipeline_process3 + if (reset == 1'b1) begin + sumdelay_pipeline3[0] <= 0; + sumdelay_pipeline3[1] <= 0; + end + else begin + if (clk_enable == 1'b1) begin + sumdelay_pipeline3[0] <= sumvector3[0]; + sumdelay_pipeline3[1] <= sumvector3[1]; + end + end + end // sumdelay_pipeline_process3 + + assign add_signext_20 = sumdelay_pipeline3[0]; + assign add_signext_21 = sumdelay_pipeline3[1]; + assign add_temp_10 = add_signext_20 + add_signext_21; + assign sum4 = add_temp_10[35:0]; + + always @ (posedge clk or posedge reset) + begin: Output_Register_process + if (reset == 1'b1) begin + output_register <= 0; + end + else begin + if (clk_enable == 1'b1) begin + output_register <= sum4; + end + end + end // Output_Register_process + + // Assignment Statements + assign ce_out = phase_1; + assign filter_out = output_register; +endmodule diff --git a/adi_library/axi_dac_interpolate/m2k_interp.m b/adi_library/axi_dac_interpolate/m2k_interp.m new file mode 100644 index 00000000..ff846ef4 --- /dev/null +++ b/adi_library/axi_dac_interpolate/m2k_interp.m @@ -0,0 +1,43 @@ +clear all; +close all; + +interp_rate = 50000; + +h_cic = dsp.CICInterpolator('InterpolationFactor', interp_rate, 'NumSections',6 );%, ... + %'FixedPointDataType','Specify word and fraction lengths', ... + %'SectionWordLengths', [12 20 28 35 43 51], ... + %'SectionFractionLengths', [11 11 11 11 11 11], ... + %'OutputWordLength', 12, ... + %'OutputFractionLength', 11); + +gainCIC = (h_cic.InterpolationFactor*h_cic.DifferentialDelay)^h_cic.NumSections +[h1, w1] = h_cic.freqz(); + +fs = 1; +fPass = 0.20; +fStop = 0.50; +ast = 70; +prip = 0.05; +CICCompInterp = dsp.CICCompensationInterpolator(h_cic, ... + 'InterpolationFactor',2,'PassbandFrequency',fPass, ... + 'StopbandFrequency',fStop,'StopbandAttenuation',ast, ... + 'SampleRate',fs); + +[h2, w2] = CICCompInterp.freqz(); +CICCompInterp.coeffs() + +FC = dsp.FilterCascade(CICCompInterp, h_cic); +[h3, w3] = FC.freqz(); + +subplot(211); hold on; +plot(w1/pi, 20*log10(abs(h1)/gainCIC)); +plot(w2/pi, 20*log10(abs(h2))); +hold off; grid + +subplot(212); plot(w3/pi, 20*log10(abs(h3)/gainCIC/sum(CICCompInterp.coeffs().Numerator))); grid + +nt = numerictype(1,16,15); +fdhdltool(CICCompInterp, nt); +nt = numerictype(1,36,30); +fdhdltool(h_cic,nt); + diff --git a/adi_library/axi_dac_interpolate/xgui/axi_dac_interpolate_v1_0.tcl b/adi_library/axi_dac_interpolate/xgui/axi_dac_interpolate_v1_0.tcl new file mode 100644 index 00000000..dd6d1dbb --- /dev/null +++ b/adi_library/axi_dac_interpolate/xgui/axi_dac_interpolate_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "CORRECTION_DISABLE" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.CORRECTION_DISABLE { PARAM_VALUE.CORRECTION_DISABLE } { + # Procedure called to update CORRECTION_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CORRECTION_DISABLE { PARAM_VALUE.CORRECTION_DISABLE } { + # Procedure called to validate CORRECTION_DISABLE + return true +} + + +proc update_MODELPARAM_VALUE.CORRECTION_DISABLE { MODELPARAM_VALUE.CORRECTION_DISABLE PARAM_VALUE.CORRECTION_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CORRECTION_DISABLE}] ${MODELPARAM_VALUE.CORRECTION_DISABLE} +} + diff --git a/adi_library/axi_dmac/Makefile b/adi_library/axi_dmac/Makefile new file mode 100644 index 00000000..d66b31ef --- /dev/null +++ b/adi_library/axi_dmac/Makefile @@ -0,0 +1,60 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_dmac + +GENERIC_DEPS += ../common/ad_mem_asym.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += address_generator.v +GENERIC_DEPS += axi_dmac.v +GENERIC_DEPS += axi_dmac_burst_memory.v +GENERIC_DEPS += axi_dmac_regmap.v +GENERIC_DEPS += axi_dmac_regmap_request.v +GENERIC_DEPS += axi_dmac_reset_manager.v +GENERIC_DEPS += axi_dmac_resize_dest.v +GENERIC_DEPS += axi_dmac_resize_src.v +GENERIC_DEPS += axi_dmac_response_manager.v +GENERIC_DEPS += axi_dmac_transfer.v +GENERIC_DEPS += axi_register_slice.v +GENERIC_DEPS += data_mover.v +GENERIC_DEPS += dest_axi_mm.v +GENERIC_DEPS += dest_axi_stream.v +GENERIC_DEPS += dest_fifo_inf.v +GENERIC_DEPS += dmac_2d_transfer.v +GENERIC_DEPS += dmac_sg.v +GENERIC_DEPS += inc_id.vh +GENERIC_DEPS += request_arb.v +GENERIC_DEPS += request_generator.v +GENERIC_DEPS += resp.vh +GENERIC_DEPS += response_generator.v +GENERIC_DEPS += response_handler.v +GENERIC_DEPS += splitter.v +GENERIC_DEPS += src_axi_mm.v +GENERIC_DEPS += src_axi_stream.v +GENERIC_DEPS += src_fifo_inf.v + +XILINX_DEPS += axi_dmac_constr.ttcl +XILINX_DEPS += axi_dmac_ip.tcl +XILINX_DEPS += axi_dmac_pkg_sv.ttcl +XILINX_DEPS += bd/bd.tcl + +XILINX_DEPS += ../interfaces/fifo_rd.xml +XILINX_DEPS += ../interfaces/fifo_rd_rtl.xml +XILINX_DEPS += ../interfaces/fifo_wr.xml +XILINX_DEPS += ../interfaces/fifo_wr_rtl.xml + +XILINX_LIB_DEPS += util_axis_fifo +XILINX_LIB_DEPS += util_cdc + +INTEL_DEPS += ../util_axis_fifo/util_axis_fifo.v +INTEL_DEPS += ../util_axis_fifo/util_axis_fifo_address_generator.v +INTEL_DEPS += ../util_cdc/sync_bits.v +INTEL_DEPS += ../util_cdc/sync_event.v +INTEL_DEPS += ../util_cdc/sync_gray.v +INTEL_DEPS += axi_dmac_constr.sdc +INTEL_DEPS += axi_dmac_hw.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_dmac/address_generator.v b/adi_library/axi_dmac/address_generator.v new file mode 100644 index 00000000..8a8d7035 --- /dev/null +++ b/adi_library/axi_dmac/address_generator.v @@ -0,0 +1,187 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module address_generator #( + + parameter ID_WIDTH = 3, + parameter DMA_DATA_WIDTH = 64, + parameter DMA_ADDR_WIDTH = 32, + parameter BEATS_PER_BURST_WIDTH = 4, + parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8), + parameter LENGTH_WIDTH = 8, + parameter CACHE_COHERENT = 0 +) ( + input clk, + input resetn, + + input req_valid, + output reg req_ready, + input [DMA_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH] req_address, + + output reg [ID_WIDTH-1:0] id, + input [ID_WIDTH-1:0] request_id, + + input bl_valid, + output reg bl_ready, + input [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length, + + input eot, + + input enable, + output reg enabled, + + input addr_ready, + output reg addr_valid, + output [DMA_ADDR_WIDTH-1:0] addr, + output [LENGTH_WIDTH-1:0] len, + output [ 2:0] size, + output [ 1:0] burst, + output [ 2:0] prot, + output [ 3:0] cache +); + + localparam MAX_BEATS_PER_BURST = {1'b1,{BEATS_PER_BURST_WIDTH{1'b0}}}; + localparam MAX_LENGTH = {BEATS_PER_BURST_WIDTH{1'b1}}; + +`include "inc_id.vh" + + assign burst = 2'b01; + assign prot = 3'b000; + // If CACHE_COHERENT is set, signal downstream that this transaction must be + // looked up in cache. Otherwise default to "normal non-cachable bufferable". + assign cache = CACHE_COHERENT ? 4'b1110 : 4'b0011; + assign size = DMA_DATA_WIDTH == 1024 ? 3'b111 : + DMA_DATA_WIDTH == 512 ? 3'b110 : + DMA_DATA_WIDTH == 256 ? 3'b101 : + DMA_DATA_WIDTH == 128 ? 3'b100 : + DMA_DATA_WIDTH == 64 ? 3'b011 : + DMA_DATA_WIDTH == 32 ? 3'b010 : + DMA_DATA_WIDTH == 16 ? 3'b001 : 3'b000; + + reg [LENGTH_WIDTH-1:0] length = 'h0; + reg [DMA_ADDR_WIDTH-BYTES_PER_BEAT_WIDTH-1:0] address = 'h00; + reg [BEATS_PER_BURST_WIDTH-1:0] last_burst_len = 'h00; + assign addr = {address, {BYTES_PER_BEAT_WIDTH{1'b0}}}; + assign len = length; + + reg addr_valid_d1; + reg last = 1'b0; + + // If we already asserted addr_valid we have to wait until it is accepted before + // we can disable the address generator. + always @(posedge clk) begin + if (resetn == 1'b0) begin + enabled <= 1'b0; + end else if (enable == 1'b1) begin + enabled <= 1'b1; + end else if (addr_valid == 1'b0) begin + enabled <= 1'b0; + end + end + + always @(posedge clk) begin + if (bl_valid == 1'b1 && bl_ready == 1'b1) begin + last_burst_len <= measured_last_burst_length; + end + end + + always @(posedge clk) begin + if (addr_valid == 1'b0) begin + last <= eot; + if (eot == 1'b1) begin + length <= last_burst_len; + end else begin + length <= MAX_LENGTH; + end + end + end + + always @(posedge clk) begin + if (req_ready == 1'b1) begin + address <= req_address; + end else if (addr_valid == 1'b1 && addr_ready == 1'b1) begin + address <= address + MAX_BEATS_PER_BURST; + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + bl_ready <= 1'b1; + end else begin + if (bl_ready == 1'b1) begin + bl_ready <= ~bl_valid; + end else if (addr_valid == 1'b0 && eot == 1'b1) begin + // assert bl_ready only when the addr_valid asserts in the next cycle + if (id != request_id && enable == 1'b1) begin + bl_ready <= 1'b1; + end + end + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + req_ready <= 1'b1; + addr_valid <= 1'b0; + end else begin + if (req_ready == 1'b1) begin + req_ready <= ~req_valid; + end else if (addr_valid == 1'b1 && addr_ready == 1'b1) begin + addr_valid <= 1'b0; + req_ready <= last; + end else if (id != request_id && enable == 1'b1) begin + // if eot wait until the last_burst_len gets synced over + if (eot == 1'b0 || (eot == 1'b1 && bl_ready == 1'b0)) begin + addr_valid <= 1'b1; + end + end + end + end + + always @(posedge clk) begin + addr_valid_d1 <= addr_valid; + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + id <= 'h0; + end else if (addr_valid == 1'b1 && addr_valid_d1 == 1'b0) begin + id <= inc_id(id); + end + end + +endmodule diff --git a/adi_library/axi_dmac/axi_dmac.v b/adi_library/axi_dmac/axi_dmac.v new file mode 100644 index 00000000..f78316f2 --- /dev/null +++ b/adi_library/axi_dmac/axi_dmac.v @@ -0,0 +1,722 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dmac #( + + parameter ID = 0, + parameter DMA_DATA_WIDTH_SRC = 64, + parameter DMA_DATA_WIDTH_DEST = 64, + parameter DMA_DATA_WIDTH_SG = 64, + parameter DMA_LENGTH_WIDTH = 24, + parameter DMA_2D_TRANSFER = 0, + parameter DMA_SG_TRANSFER = 0, + parameter ASYNC_CLK_REQ_SRC = 1, + parameter ASYNC_CLK_SRC_DEST = 1, + parameter ASYNC_CLK_DEST_REQ = 1, + parameter ASYNC_CLK_REQ_SG = 1, + parameter ASYNC_CLK_SRC_SG = 1, + parameter ASYNC_CLK_DEST_SG = 1, + parameter AXI_SLICE_DEST = 0, + parameter AXI_SLICE_SRC = 0, + parameter SYNC_TRANSFER_START = 0, + parameter CYCLIC = 1, + parameter DMA_AXI_PROTOCOL_DEST = 0, + parameter DMA_AXI_PROTOCOL_SRC = 0, + parameter DMA_AXI_PROTOCOL_SG = 0, + parameter DMA_TYPE_DEST = 0, + parameter DMA_TYPE_SRC = 2, + parameter DMA_AXI_ADDR_WIDTH = 32, + parameter MAX_BYTES_PER_BURST = 128, + parameter FIFO_SIZE = 8, // In bursts + parameter AXI_ID_WIDTH_SRC = 1, + parameter AXI_ID_WIDTH_DEST = 1, + parameter AXI_ID_WIDTH_SG = 1, + parameter DMA_AXIS_ID_W = 8, + parameter DMA_AXIS_DEST_W = 4, + parameter DISABLE_DEBUG_REGISTERS = 0, + parameter ENABLE_DIAGNOSTICS_IF = 0, + parameter ALLOW_ASYM_MEM = 0, + parameter CACHE_COHERENT_DEST = 0 +) ( + + // Slave AXI interface + input s_axi_aclk, + input s_axi_aresetn, + + input s_axi_awvalid, + input [10:0] s_axi_awaddr, + output s_axi_awready, + input [2:0] s_axi_awprot, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [10:0] s_axi_araddr, + output s_axi_arready, + input [2:0] s_axi_arprot, + output s_axi_rvalid, + input s_axi_rready, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + + // Interrupt + output irq, + + // Master AXI interface + input m_dest_axi_aclk, + input m_dest_axi_aresetn, + + // Write address + output [DMA_AXI_ADDR_WIDTH-1:0] m_dest_axi_awaddr, + output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_awlen, + output [ 2:0] m_dest_axi_awsize, + output [ 1:0] m_dest_axi_awburst, + output [ 2:0] m_dest_axi_awprot, + output [ 3:0] m_dest_axi_awcache, + output m_dest_axi_awvalid, + input m_dest_axi_awready, + output [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_awid, + output [DMA_AXI_PROTOCOL_DEST:0] m_dest_axi_awlock, + + // Write data + output [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_wdata, + output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_dest_axi_wstrb, + input m_dest_axi_wready, + output m_dest_axi_wvalid, + output m_dest_axi_wlast, + output [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_wid, + + // Write response + input m_dest_axi_bvalid, + input [ 1:0] m_dest_axi_bresp, + output m_dest_axi_bready, + input [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_bid, + + // Unused read interface + output m_dest_axi_arvalid, + output [DMA_AXI_ADDR_WIDTH-1:0] m_dest_axi_araddr, + output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_arlen, + output [ 2:0] m_dest_axi_arsize, + output [ 1:0] m_dest_axi_arburst, + output [ 3:0] m_dest_axi_arcache, + output [ 2:0] m_dest_axi_arprot, + input m_dest_axi_arready, + input m_dest_axi_rvalid, + input [ 1:0] m_dest_axi_rresp, + input [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata, + output m_dest_axi_rready, + output [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_arid, + output [DMA_AXI_PROTOCOL_DEST:0] m_dest_axi_arlock, + input [AXI_ID_WIDTH_DEST-1:0] m_dest_axi_rid, + input m_dest_axi_rlast, + + // Master AXI interface + input m_src_axi_aclk, + input m_src_axi_aresetn, + + // Read address + input m_src_axi_arready, + output m_src_axi_arvalid, + output [DMA_AXI_ADDR_WIDTH-1:0] m_src_axi_araddr, + output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_arlen, + output [ 2:0] m_src_axi_arsize, + output [ 1:0] m_src_axi_arburst, + output [ 2:0] m_src_axi_arprot, + output [ 3:0] m_src_axi_arcache, + output [AXI_ID_WIDTH_SRC-1:0] m_src_axi_arid, + output [DMA_AXI_PROTOCOL_SRC:0] m_src_axi_arlock, + + // Read data and response + input [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata, + output m_src_axi_rready, + input m_src_axi_rvalid, + input [ 1:0] m_src_axi_rresp, + input [AXI_ID_WIDTH_SRC-1:0] m_src_axi_rid, + input m_src_axi_rlast, + + // Unused write interface + output m_src_axi_awvalid, + output [DMA_AXI_ADDR_WIDTH-1:0] m_src_axi_awaddr, + output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_awlen, + output [ 2:0] m_src_axi_awsize, + output [ 1:0] m_src_axi_awburst, + output [ 3:0] m_src_axi_awcache, + output [ 2:0] m_src_axi_awprot, + input m_src_axi_awready, + output m_src_axi_wvalid, + output [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_wdata, + output [(DMA_DATA_WIDTH_SRC/8)-1:0] m_src_axi_wstrb, + output m_src_axi_wlast, + input m_src_axi_wready, + input m_src_axi_bvalid, + input [ 1:0] m_src_axi_bresp, + output m_src_axi_bready, + output [AXI_ID_WIDTH_SRC-1:0] m_src_axi_awid, + output [DMA_AXI_PROTOCOL_SRC:0] m_src_axi_awlock, + output [AXI_ID_WIDTH_SRC-1:0] m_src_axi_wid, + input [AXI_ID_WIDTH_SRC-1:0] m_src_axi_bid, + + // Master AXI interface + input m_sg_axi_aclk, + input m_sg_axi_aresetn, + + // Read address + input m_sg_axi_arready, + output m_sg_axi_arvalid, + output [DMA_AXI_ADDR_WIDTH-1:0] m_sg_axi_araddr, + output [7-(4*DMA_AXI_PROTOCOL_SG):0] m_sg_axi_arlen, + output [ 2:0] m_sg_axi_arsize, + output [ 1:0] m_sg_axi_arburst, + output [ 2:0] m_sg_axi_arprot, + output [ 3:0] m_sg_axi_arcache, + output [AXI_ID_WIDTH_SG-1:0] m_sg_axi_arid, + output [DMA_AXI_PROTOCOL_SG:0] m_sg_axi_arlock, + + // Read data and response + input [DMA_DATA_WIDTH_SG-1:0] m_sg_axi_rdata, + output m_sg_axi_rready, + input m_sg_axi_rvalid, + input [ 1:0] m_sg_axi_rresp, + input [AXI_ID_WIDTH_SG-1:0] m_sg_axi_rid, + input m_sg_axi_rlast, + + // Unused write interface + output m_sg_axi_awvalid, + output [DMA_AXI_ADDR_WIDTH-1:0] m_sg_axi_awaddr, + output [7-(4*DMA_AXI_PROTOCOL_SG):0] m_sg_axi_awlen, + output [ 2:0] m_sg_axi_awsize, + output [ 1:0] m_sg_axi_awburst, + output [ 3:0] m_sg_axi_awcache, + output [ 2:0] m_sg_axi_awprot, + input m_sg_axi_awready, + output m_sg_axi_wvalid, + output [DMA_DATA_WIDTH_SG-1:0] m_sg_axi_wdata, + output [(DMA_DATA_WIDTH_SG/8)-1:0] m_sg_axi_wstrb, + output m_sg_axi_wlast, + input m_sg_axi_wready, + input m_sg_axi_bvalid, + input [ 1:0] m_sg_axi_bresp, + output m_sg_axi_bready, + output [AXI_ID_WIDTH_SG-1:0] m_sg_axi_awid, + output [DMA_AXI_PROTOCOL_SG:0] m_sg_axi_awlock, + output [AXI_ID_WIDTH_SG-1:0] m_sg_axi_wid, + input [AXI_ID_WIDTH_SG-1:0] m_sg_axi_bid, + + // Slave streaming AXI interface + input s_axis_aclk, + output s_axis_ready, + input s_axis_valid, + input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data, + input [DMA_DATA_WIDTH_SRC/8-1:0] s_axis_strb, + input [DMA_DATA_WIDTH_SRC/8-1:0] s_axis_keep, + input [0:0] s_axis_user, + input [DMA_AXIS_ID_W-1:0] s_axis_id, + input [DMA_AXIS_DEST_W-1:0] s_axis_dest, + input s_axis_last, + output s_axis_xfer_req, + + // Master streaming AXI interface + input m_axis_aclk, + input m_axis_ready, + output m_axis_valid, + output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data, + output [DMA_DATA_WIDTH_DEST/8-1:0] m_axis_strb, + output [DMA_DATA_WIDTH_DEST/8-1:0] m_axis_keep, + output [0:0] m_axis_user, + output [DMA_AXIS_ID_W-1:0] m_axis_id, + output [DMA_AXIS_DEST_W-1:0] m_axis_dest, + output m_axis_last, + output m_axis_xfer_req, + + // Input FIFO interface + input fifo_wr_clk, + input fifo_wr_en, + input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din, + output fifo_wr_overflow, + input fifo_wr_sync, + output fifo_wr_xfer_req, + + // Input FIFO interface + input fifo_rd_clk, + input fifo_rd_en, + output fifo_rd_valid, + output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout, + output fifo_rd_underflow, + output fifo_rd_xfer_req, + + // Diagnostics interface + output [7:0] dest_diag_level_bursts +); + + localparam DMA_TYPE_AXI_MM = 0; + localparam DMA_TYPE_AXI_STREAM = 1; + localparam DMA_TYPE_FIFO = 2; + + localparam HAS_DEST_ADDR = DMA_TYPE_DEST == DMA_TYPE_AXI_MM; + localparam HAS_SRC_ADDR = DMA_TYPE_SRC == DMA_TYPE_AXI_MM; + + // Argh... "[Synth 8-2722] system function call clog2 is not allowed here" + localparam BYTES_PER_BEAT_WIDTH_DEST = DMA_DATA_WIDTH_DEST > 1024 ? 8 : + DMA_DATA_WIDTH_DEST > 512 ? 7 : + DMA_DATA_WIDTH_DEST > 256 ? 6 : + DMA_DATA_WIDTH_DEST > 128 ? 5 : + DMA_DATA_WIDTH_DEST > 64 ? 4 : + DMA_DATA_WIDTH_DEST > 32 ? 3 : + DMA_DATA_WIDTH_DEST > 16 ? 2 : + DMA_DATA_WIDTH_DEST > 8 ? 1 : 0; + localparam BYTES_PER_BEAT_WIDTH_SRC = DMA_DATA_WIDTH_SRC > 1024 ? 8 : + DMA_DATA_WIDTH_SRC > 512 ? 7 : + DMA_DATA_WIDTH_SRC > 256 ? 6 : + DMA_DATA_WIDTH_SRC > 128 ? 5 : + DMA_DATA_WIDTH_SRC > 64 ? 4 : + DMA_DATA_WIDTH_SRC > 32 ? 3 : + DMA_DATA_WIDTH_SRC > 16 ? 2 : + DMA_DATA_WIDTH_SRC > 8 ? 1 : 0; + localparam BYTES_PER_BEAT_WIDTH_SG = DMA_DATA_WIDTH_SG > 1024 ? 8 : + DMA_DATA_WIDTH_SG > 512 ? 7 : + DMA_DATA_WIDTH_SG > 256 ? 6 : + DMA_DATA_WIDTH_SG > 128 ? 5 : + DMA_DATA_WIDTH_SG > 64 ? 4 : + DMA_DATA_WIDTH_SG > 32 ? 3 : + DMA_DATA_WIDTH_SG > 16 ? 2 : + DMA_DATA_WIDTH_SG > 8 ? 1 : 0; + localparam ID_WIDTH = (FIFO_SIZE) > 64 ? 8 : + (FIFO_SIZE) > 32 ? 7 : + (FIFO_SIZE) > 16 ? 6 : + (FIFO_SIZE) > 8 ? 5 : + (FIFO_SIZE) > 4 ? 4 : + (FIFO_SIZE) > 2 ? 3 : + (FIFO_SIZE) > 1 ? 2 : 1; + localparam DBG_ID_PADDING = ID_WIDTH > 8 ? 0 : 8 - ID_WIDTH; + + /* AXI3 supports a maximum of 16 beats per burst. AXI4 supports a maximum of + 256 beats per burst. If either bus is AXI3 set the maximum number of beats + per burst to 16. For non AXI interfaces the maximum beats per burst is in + theory unlimted. Set it to 1024 to provide a reasonable upper threshold */ + localparam BEATS_PER_BURST_LIMIT_DEST = + (DMA_TYPE_DEST == DMA_TYPE_AXI_MM) ? + (DMA_AXI_PROTOCOL_DEST == 1 ? 16 : 256) : + 1024; + localparam BYTES_PER_BURST_LIMIT_DEST = + BEATS_PER_BURST_LIMIT_DEST * DMA_DATA_WIDTH_DEST / 8; + localparam BEATS_PER_BURST_LIMIT_SRC = + (DMA_TYPE_SRC == DMA_TYPE_AXI_MM) ? + (DMA_AXI_PROTOCOL_SRC == 1 ? 16 : 256) : + 1024; + localparam BYTES_PER_BURST_LIMIT_SRC = + BEATS_PER_BURST_LIMIT_SRC * DMA_DATA_WIDTH_SRC / 8; + + /* The smaller bus limits the maximum bytes per burst. */ + localparam BYTES_PER_BURST_LIMIT = + (BYTES_PER_BURST_LIMIT_DEST < BYTES_PER_BURST_LIMIT_SRC) ? + BYTES_PER_BURST_LIMIT_DEST : BYTES_PER_BURST_LIMIT_SRC; + + /* Make sure the requested MAX_BYTES_PER_BURST does not exceed what the + interfaces can support. Limit the value if necessary. */ + localparam REAL_MAX_BYTES_PER_BURST = + BYTES_PER_BURST_LIMIT < MAX_BYTES_PER_BURST ? + BYTES_PER_BURST_LIMIT : MAX_BYTES_PER_BURST; + + /* MM has no alignment requirements */ + localparam DMA_LENGTH_ALIGN_SRC = + DMA_TYPE_SRC == DMA_TYPE_AXI_MM ? 0 : BYTES_PER_BEAT_WIDTH_SRC; + localparam DMA_LENGTH_ALIGN_DEST = + DMA_TYPE_DEST == DMA_TYPE_AXI_MM ? 0 : BYTES_PER_BEAT_WIDTH_DEST; + + /* Choose the larger of the two */ + localparam DMA_LENGTH_ALIGN = + DMA_LENGTH_ALIGN_SRC < DMA_LENGTH_ALIGN_DEST ? + DMA_LENGTH_ALIGN_DEST : DMA_LENGTH_ALIGN_SRC; + + localparam BYTES_PER_BURST_WIDTH = + REAL_MAX_BYTES_PER_BURST > 2048 ? 12 : + REAL_MAX_BYTES_PER_BURST > 1024 ? 11 : + REAL_MAX_BYTES_PER_BURST > 512 ? 10 : + REAL_MAX_BYTES_PER_BURST > 256 ? 9 : + REAL_MAX_BYTES_PER_BURST > 128 ? 8 : + REAL_MAX_BYTES_PER_BURST > 64 ? 7 : + REAL_MAX_BYTES_PER_BURST > 32 ? 6 : + REAL_MAX_BYTES_PER_BURST > 16 ? 5 : + REAL_MAX_BYTES_PER_BURST > 8 ? 4 : + REAL_MAX_BYTES_PER_BURST > 4 ? 3 : + REAL_MAX_BYTES_PER_BURST > 2 ? 2 : 1; + + // ID signals from the DMAC, just for debugging + wire [ID_WIDTH-1:0] dest_request_id; + wire [ID_WIDTH-1:0] dest_data_id; + wire [ID_WIDTH-1:0] dest_address_id; + wire [ID_WIDTH-1:0] dest_response_id; + wire [ID_WIDTH-1:0] src_request_id; + wire [ID_WIDTH-1:0] src_data_id; + wire [ID_WIDTH-1:0] src_address_id; + wire [ID_WIDTH-1:0] src_response_id; + wire [11:0] dbg_status; + wire [31:0] dbg_ids0; + wire [31:0] dbg_ids1; + + wire up_req_eot; + wire [31:0] up_req_sg_desc_id; + wire [BYTES_PER_BURST_WIDTH-1:0] up_req_measured_burst_length; + wire up_response_partial; + wire up_response_valid; + wire up_response_ready; + + wire ctrl_enable; + wire ctrl_pause; + wire ctrl_hwdesc; + + wire up_dma_req_valid; + wire up_dma_req_ready; + wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] up_dma_req_dest_address; + wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] up_dma_req_src_address; + wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SG] up_dma_req_sg_address; + wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_x_length; + wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_y_length; + wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_dest_stride; + wire [DMA_LENGTH_WIDTH-1:0] up_dma_req_src_stride; + wire up_dma_req_sync_transfer_start; + wire up_dma_req_last; + + assign dbg_ids0 = { + {DBG_ID_PADDING{1'b0}}, dest_response_id, + {DBG_ID_PADDING{1'b0}}, dest_data_id, + {DBG_ID_PADDING{1'b0}}, dest_address_id, + {DBG_ID_PADDING{1'b0}}, dest_request_id + }; + + assign dbg_ids1 = { + {DBG_ID_PADDING{1'b0}}, src_response_id, + {DBG_ID_PADDING{1'b0}}, src_data_id, + {DBG_ID_PADDING{1'b0}}, src_address_id, + {DBG_ID_PADDING{1'b0}}, src_request_id + }; + + axi_dmac_regmap #( + .ID(ID), + .DISABLE_DEBUG_REGISTERS(DISABLE_DEBUG_REGISTERS), + .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST), + .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC), + .BYTES_PER_BEAT_WIDTH_SG(BYTES_PER_BEAT_WIDTH_SG), + .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH), + .DMA_TYPE_DEST(DMA_TYPE_DEST), + .DMA_TYPE_SRC(DMA_TYPE_SRC), + .DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH), + .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH), + .DMA_LENGTH_ALIGN(DMA_LENGTH_ALIGN), + .DMA_CYCLIC(CYCLIC), + .HAS_DEST_ADDR(HAS_DEST_ADDR), + .HAS_SRC_ADDR(HAS_SRC_ADDR), + .DMA_2D_TRANSFER(DMA_2D_TRANSFER), + .DMA_SG_TRANSFER(DMA_SG_TRANSFER), + .SYNC_TRANSFER_START(SYNC_TRANSFER_START), + .CACHE_COHERENT_DEST(CACHE_COHERENT_DEST) + ) i_regmap ( + .s_axi_aclk(s_axi_aclk), + .s_axi_aresetn(s_axi_aresetn), + + .s_axi_awvalid(s_axi_awvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awready(s_axi_awready), + .s_axi_awprot(s_axi_awprot), + .s_axi_wvalid(s_axi_wvalid), + .s_axi_wdata(s_axi_wdata), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wready(s_axi_wready), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_bresp(s_axi_bresp), + .s_axi_bready(s_axi_bready), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_araddr(s_axi_araddr), + .s_axi_arready(s_axi_arready), + .s_axi_arprot(s_axi_arprot), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_rready(s_axi_rready), + .s_axi_rresp(s_axi_rresp), + .s_axi_rdata(s_axi_rdata), + + // Interrupt + .irq(irq), + + // Control interface + .ctrl_enable(ctrl_enable), + .ctrl_pause(ctrl_pause), + .ctrl_hwdesc(ctrl_hwdesc), + + // Request interface + .request_valid(up_dma_req_valid), + .request_ready(up_dma_req_ready), + .request_dest_address(up_dma_req_dest_address), + .request_src_address(up_dma_req_src_address), + .request_sg_address(up_dma_req_sg_address), + .request_x_length(up_dma_req_x_length), + .request_y_length(up_dma_req_y_length), + .request_dest_stride(up_dma_req_dest_stride), + .request_src_stride(up_dma_req_src_stride), + .request_sync_transfer_start(up_dma_req_sync_transfer_start), + .request_last(up_dma_req_last), + + // DMA response interface + .response_eot(up_req_eot), + .response_sg_desc_id(up_req_sg_desc_id), + .response_measured_burst_length(up_req_measured_burst_length), + .response_partial(up_response_partial), + .response_valid(up_response_valid), + .response_ready(up_response_ready), + + // Debug interface + .dbg_dest_addr(m_dest_axi_awaddr), + .dbg_src_addr(m_src_axi_araddr), + .dbg_status(dbg_status), + .dbg_ids0(dbg_ids0), + .dbg_ids1(dbg_ids1)); + + axi_dmac_transfer #( + .DMA_DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC), + .DMA_DATA_WIDTH_DEST(DMA_DATA_WIDTH_DEST), + .DMA_DATA_WIDTH_SG(DMA_DATA_WIDTH_SG), + .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH), + .DMA_LENGTH_ALIGN(DMA_LENGTH_ALIGN), + .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST), + .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC), + .BYTES_PER_BEAT_WIDTH_SG(BYTES_PER_BEAT_WIDTH_SG), + .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH), + .DMA_TYPE_DEST(DMA_TYPE_DEST), + .DMA_TYPE_SRC(DMA_TYPE_SRC), + .DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH), + .DMA_2D_TRANSFER(DMA_2D_TRANSFER), + .DMA_SG_TRANSFER(DMA_SG_TRANSFER), + .ASYNC_CLK_REQ_SRC(ASYNC_CLK_REQ_SRC), + .ASYNC_CLK_SRC_DEST(ASYNC_CLK_SRC_DEST), + .ASYNC_CLK_DEST_REQ(ASYNC_CLK_DEST_REQ), + .ASYNC_CLK_REQ_SG(ASYNC_CLK_REQ_SG), + .AXI_SLICE_DEST(AXI_SLICE_DEST), + .AXI_SLICE_SRC(AXI_SLICE_SRC), + .MAX_BYTES_PER_BURST(REAL_MAX_BYTES_PER_BURST), + .FIFO_SIZE(FIFO_SIZE), + .ID_WIDTH(ID_WIDTH), + .AXI_LENGTH_WIDTH_SRC(8-(4*DMA_AXI_PROTOCOL_SRC)), + .AXI_LENGTH_WIDTH_DEST(8-(4*DMA_AXI_PROTOCOL_DEST)), + .AXI_LENGTH_WIDTH_SG(8-(4*DMA_AXI_PROTOCOL_SG)), + .ENABLE_DIAGNOSTICS_IF(ENABLE_DIAGNOSTICS_IF), + .ALLOW_ASYM_MEM(ALLOW_ASYM_MEM), + .CACHE_COHERENT_DEST(CACHE_COHERENT_DEST) + ) i_transfer ( + .ctrl_clk(s_axi_aclk), + .ctrl_resetn(s_axi_aresetn), + + .ctrl_enable(ctrl_enable), + .ctrl_pause(ctrl_pause), + .ctrl_hwdesc(ctrl_hwdesc), + + .req_valid(up_dma_req_valid), + .req_ready(up_dma_req_ready), + .req_dest_address(up_dma_req_dest_address), + .req_src_address(up_dma_req_src_address), + .req_sg_address(up_dma_req_sg_address), + .req_x_length(up_dma_req_x_length), + .req_y_length(up_dma_req_y_length), + .req_dest_stride(up_dma_req_dest_stride), + .req_src_stride(up_dma_req_src_stride), + .req_sync_transfer_start(up_dma_req_sync_transfer_start), + .req_last(up_dma_req_last), + + .req_eot(up_req_eot), + .req_sg_desc_id(up_req_sg_desc_id), + .req_measured_burst_length(up_req_measured_burst_length), + .req_response_partial(up_response_partial), + .req_response_valid(up_response_valid), + .req_response_ready(up_response_ready), + + .m_dest_axi_aclk(m_dest_axi_aclk), + .m_dest_axi_aresetn(m_dest_axi_aresetn), + .m_src_axi_aclk(m_src_axi_aclk), + .m_src_axi_aresetn(m_src_axi_aresetn), + .m_sg_axi_aclk(m_sg_axi_aclk), + .m_sg_axi_aresetn(m_sg_axi_aresetn), + + .m_axi_awaddr(m_dest_axi_awaddr), + .m_axi_awlen(m_dest_axi_awlen), + .m_axi_awsize(m_dest_axi_awsize), + .m_axi_awburst(m_dest_axi_awburst), + .m_axi_awprot(m_dest_axi_awprot), + .m_axi_awcache(m_dest_axi_awcache), + .m_axi_awvalid(m_dest_axi_awvalid), + .m_axi_awready(m_dest_axi_awready), + + .m_axi_wdata(m_dest_axi_wdata), + .m_axi_wstrb(m_dest_axi_wstrb), + .m_axi_wready(m_dest_axi_wready), + .m_axi_wvalid(m_dest_axi_wvalid), + .m_axi_wlast(m_dest_axi_wlast), + + .m_axi_bvalid(m_dest_axi_bvalid), + .m_axi_bresp(m_dest_axi_bresp), + .m_axi_bready(m_dest_axi_bready), + + .m_axi_arready(m_src_axi_arready), + .m_axi_arvalid(m_src_axi_arvalid), + .m_axi_araddr(m_src_axi_araddr), + .m_axi_arlen(m_src_axi_arlen), + .m_axi_arsize(m_src_axi_arsize), + .m_axi_arburst(m_src_axi_arburst), + .m_axi_arprot(m_src_axi_arprot), + .m_axi_arcache(m_src_axi_arcache), + + .m_axi_rdata(m_src_axi_rdata), + .m_axi_rready(m_src_axi_rready), + .m_axi_rvalid(m_src_axi_rvalid), + .m_axi_rlast(m_src_axi_rlast), + .m_axi_rresp(m_src_axi_rresp), + + .m_sg_axi_arready(m_sg_axi_arready), + .m_sg_axi_arvalid(m_sg_axi_arvalid), + .m_sg_axi_araddr(m_sg_axi_araddr), + .m_sg_axi_arlen(m_sg_axi_arlen), + .m_sg_axi_arsize(m_sg_axi_arsize), + .m_sg_axi_arburst(m_sg_axi_arburst), + .m_sg_axi_arprot(m_sg_axi_arprot), + .m_sg_axi_arcache(m_sg_axi_arcache), + + .m_sg_axi_rdata(m_sg_axi_rdata), + .m_sg_axi_rready(m_sg_axi_rready), + .m_sg_axi_rvalid(m_sg_axi_rvalid), + .m_sg_axi_rlast(m_sg_axi_rlast), + .m_sg_axi_rresp(m_sg_axi_rresp), + + .s_axis_aclk(s_axis_aclk), + .s_axis_ready(s_axis_ready), + .s_axis_valid(s_axis_valid), + .s_axis_data(s_axis_data), + .s_axis_user(s_axis_user), + .s_axis_last(s_axis_last), + .s_axis_xfer_req(s_axis_xfer_req), + + .m_axis_aclk(m_axis_aclk), + .m_axis_ready(m_axis_ready), + .m_axis_valid(m_axis_valid), + .m_axis_data(m_axis_data), + .m_axis_last(m_axis_last), + .m_axis_xfer_req(m_axis_xfer_req), + + .fifo_wr_clk(fifo_wr_clk), + .fifo_wr_en(fifo_wr_en), + .fifo_wr_din(fifo_wr_din), + .fifo_wr_overflow(fifo_wr_overflow), + .fifo_wr_sync(fifo_wr_sync), + .fifo_wr_xfer_req(fifo_wr_xfer_req), + + .fifo_rd_clk(fifo_rd_clk), + .fifo_rd_en(fifo_rd_en), + .fifo_rd_valid(fifo_rd_valid), + .fifo_rd_dout(fifo_rd_dout), + .fifo_rd_underflow(fifo_rd_underflow), + .fifo_rd_xfer_req(fifo_rd_xfer_req), + + // DBG + .dbg_dest_request_id(dest_request_id), + .dbg_dest_address_id(dest_address_id), + .dbg_dest_data_id(dest_data_id), + .dbg_dest_response_id(dest_response_id), + .dbg_src_request_id(src_request_id), + .dbg_src_address_id(src_address_id), + .dbg_src_data_id(src_data_id), + .dbg_src_response_id(src_response_id), + .dbg_status(dbg_status), + + .dest_diag_level_bursts(dest_diag_level_bursts)); + + assign m_dest_axi_arvalid = 1'b0; + assign m_dest_axi_rready = 1'b0; + assign m_dest_axi_araddr = 'h0; + assign m_dest_axi_arlen = 'h0; + assign m_dest_axi_arsize = 'h0; + assign m_dest_axi_arburst = 'h0; + assign m_dest_axi_arcache = 'h0; + assign m_dest_axi_arprot = 'h0; + assign m_dest_axi_awid = 'h0; + assign m_dest_axi_awlock = 'h0; + assign m_dest_axi_wid = 'h0; + assign m_dest_axi_arid = 'h0; + assign m_dest_axi_arlock = 'h0; + + assign m_src_axi_awvalid = 1'b0; + assign m_src_axi_wvalid = 1'b0; + assign m_src_axi_bready = 1'b0; + assign m_src_axi_awaddr = 'h0; + assign m_src_axi_awlen = 'h0; + assign m_src_axi_awsize = 'h0; + assign m_src_axi_awburst = 'h0; + assign m_src_axi_awcache = 'h0; + assign m_src_axi_awprot = 'h0; + assign m_src_axi_wdata = 'h0; + assign m_src_axi_wstrb = 'h0; + assign m_src_axi_wlast = 'h0; + assign m_src_axi_awid = 'h0; + assign m_src_axi_awlock = 'h0; + assign m_src_axi_wid = 'h0; + assign m_src_axi_arid = 'h0; + assign m_src_axi_arlock = 'h0; + + assign m_sg_axi_awvalid = 1'b0; + assign m_sg_axi_wvalid = 1'b0; + assign m_sg_axi_bready = 1'b0; + assign m_sg_axi_awaddr = 'h0; + assign m_sg_axi_awlen = 'h0; + assign m_sg_axi_awsize = 'h0; + assign m_sg_axi_awburst = 'h0; + assign m_sg_axi_awcache = 'h0; + assign m_sg_axi_awprot = 'h0; + assign m_sg_axi_wdata = 'h0; + assign m_sg_axi_wstrb = 'h0; + assign m_sg_axi_wlast = 'h0; + assign m_sg_axi_awid = 'h0; + assign m_sg_axi_awlock = 'h0; + assign m_sg_axi_wid = 'h0; + assign m_sg_axi_arid = 'h0; + assign m_sg_axi_arlock = 'h0; + + assign m_axis_keep = {DMA_DATA_WIDTH_DEST/8{1'b1}}; + assign m_axis_strb = {DMA_DATA_WIDTH_DEST/8{1'b1}}; + assign m_axis_id = 'h0; + assign m_axis_dest = 'h0; + assign m_axis_user = 'h0; + +endmodule diff --git a/adi_library/axi_dmac/axi_dmac.xpr b/adi_library/axi_dmac/axi_dmac.xpr new file mode 100644 index 00000000..3d6e5351 --- /dev/null +++ b/adi_library/axi_dmac/axi_dmac.xpr @@ -0,0 +1,604 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_dmac/axi_dmac_burst_memory.v b/adi_library/axi_dmac/axi_dmac_burst_memory.v new file mode 100644 index 00000000..5e0123b1 --- /dev/null +++ b/adi_library/axi_dmac/axi_dmac_burst_memory.v @@ -0,0 +1,453 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dmac_burst_memory #( + parameter DATA_WIDTH_SRC = 64, + parameter DATA_WIDTH_DEST = 64, + parameter ID_WIDTH = 3, + parameter MAX_BYTES_PER_BURST = 128, + parameter ASYNC_CLK = 1, + parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(DATA_WIDTH_SRC/8), + parameter BYTES_PER_BURST_WIDTH = $clog2(MAX_BYTES_PER_BURST), + parameter DMA_LENGTH_ALIGN = 3, + parameter ENABLE_DIAGNOSTICS_IF = 0, + parameter ALLOW_ASYM_MEM = 0 +) ( + input src_clk, + input src_reset, + + input src_data_valid, + input [DATA_WIDTH_SRC-1:0] src_data, + input src_data_last, + input [BYTES_PER_BEAT_WIDTH_SRC-1:0] src_data_valid_bytes, + input src_data_partial_burst, + + output [ID_WIDTH-1:0] src_data_request_id, + + input dest_clk, + input dest_reset, + + output dest_data_valid, + input dest_data_ready, + output [DATA_WIDTH_DEST-1:0] dest_data, + output dest_data_last, + output [DATA_WIDTH_DEST/8-1:0] dest_data_strb, + + output [BYTES_PER_BURST_WIDTH-1:0] dest_burst_info_length, + output dest_burst_info_partial, + output [ID_WIDTH-1:0] dest_burst_info_id, + output reg dest_burst_info_write = 1'b0, + + output [ID_WIDTH-1:0] dest_request_id, + input [ID_WIDTH-1:0] dest_data_request_id, + output [ID_WIDTH-1:0] dest_data_response_id, + + // Diagnostics interface + output [7:0] dest_diag_level_bursts +); + + localparam DATA_WIDTH_MEM = DATA_WIDTH_SRC > DATA_WIDTH_DEST ? + DATA_WIDTH_SRC : DATA_WIDTH_DEST; + localparam MEM_RATIO = DATA_WIDTH_SRC > DATA_WIDTH_DEST ? + DATA_WIDTH_SRC / DATA_WIDTH_DEST : DATA_WIDTH_DEST / DATA_WIDTH_SRC; + + // A burst can have up to 256 beats + localparam BURST_LEN = MAX_BYTES_PER_BURST / (DATA_WIDTH_MEM / 8); + localparam BURST_LEN_WIDTH = BURST_LEN > 128 ? 8 : + BURST_LEN > 64 ? 7 : + BURST_LEN > 32 ? 6 : + BURST_LEN > 16 ? 5 : + BURST_LEN > 8 ? 4 : + BURST_LEN > 4 ? 3 : + BURST_LEN > 2 ? 2 : 1; + + localparam AUX_FIFO_SIZE = 2**(ID_WIDTH-1); + + localparam MEM_RATIO_WIDTH = + (ALLOW_ASYM_MEM == 0 || MEM_RATIO == 1) ? 0 : + MEM_RATIO == 2 ? 1 : + MEM_RATIO == 4 ? 2 : 3; + + localparam BURST_LEN_WIDTH_SRC = BURST_LEN_WIDTH + + (DATA_WIDTH_SRC < DATA_WIDTH_MEM ? MEM_RATIO_WIDTH : 0); + localparam BURST_LEN_WIDTH_DEST = BURST_LEN_WIDTH + + (DATA_WIDTH_DEST < DATA_WIDTH_MEM ? MEM_RATIO_WIDTH : 0); + localparam DATA_WIDTH_MEM_SRC = DATA_WIDTH_MEM >> + (DATA_WIDTH_SRC < DATA_WIDTH_MEM ? MEM_RATIO_WIDTH : 0); + localparam DATA_WIDTH_MEM_DEST = DATA_WIDTH_MEM >> + (DATA_WIDTH_DEST < DATA_WIDTH_MEM ? MEM_RATIO_WIDTH : 0); + + localparam ADDRESS_WIDTH_SRC = BURST_LEN_WIDTH_SRC + ID_WIDTH - 1; + localparam ADDRESS_WIDTH_DEST = BURST_LEN_WIDTH_DEST + ID_WIDTH - 1; + + localparam BYTES_PER_BEAT_WIDTH_MEM_SRC = BYTES_PER_BURST_WIDTH - BURST_LEN_WIDTH_SRC; + localparam BYTES_PER_BEAT_WIDTH_DEST = BYTES_PER_BURST_WIDTH - BURST_LEN_WIDTH_DEST; + + /* + * The burst memory is separated into 2**(ID_WIDTH-1) segments. Each segment can + * hold up to BURST_LEN beats. The addresses that are used to access the memory + * are split into two parts. The MSBs index the segment and the LSBs index a + * beat in a specific segment. + * + * src_id and dest_id are used to index the segment of the burst memory on the + * write and read side respectively. The IDs are 1 bit wider than the address of + * the burst memory. So we can't use them directly as an index into the burst + * memory. Since the IDs are gray counted we also can't just leave out the MSB + * like with a binary counter. But XOR-ing the two MSBs of a gray counter gives + * us a gray counter of 1 bit less. Use this to generate the segment index. + * These addresses are captured in the src_id_reduced and dest_id_reduced + * signals. + * + * src_beat_counter and dest_beat_counter are used to index the beat on the + * write and read side respectively. They will be incremented for each beat that + * is written/read. Note that the beat counters are not reset to 0 on the last + * beat of a burst. This means the first beat of a burst might not be stored at + * offset 0 in the segment memory. But this is OK since the beat counter + * increments modulo the segment size and both the write and read side agree on + * the order. + */ + + reg [ID_WIDTH-1:0] src_id_next; + reg [ID_WIDTH-1:0] src_id = 'h0; + reg src_id_reduced_msb = 1'b0; + reg [BURST_LEN_WIDTH_SRC-1:0] src_beat_counter = 'h00; + + reg [ID_WIDTH-1:0] dest_id_next = 'h0; + reg dest_id_reduced_msb_next = 1'b0; + reg dest_id_reduced_msb = 1'b0; + reg [ID_WIDTH-1:0] dest_id = 'h0; + reg [BURST_LEN_WIDTH_DEST-1:0] dest_beat_counter = 'h00; + wire [BURST_LEN_WIDTH_DEST-1:0] dest_burst_len; + reg dest_valid = 1'b0; + reg dest_mem_data_valid = 1'b0; + reg dest_mem_data_last = 1'b0; + reg [DATA_WIDTH_MEM_DEST/8-1:0] dest_mem_data_strb = {DATA_WIDTH_MEM_DEST/8{1'b1}}; + + reg [BYTES_PER_BURST_WIDTH+1-1-DMA_LENGTH_ALIGN:0] burst_len_mem[0:AUX_FIFO_SIZE-1]; + + wire [BYTES_PER_BURST_WIDTH+1-1:0] src_burst_len_data; + reg [BYTES_PER_BURST_WIDTH+1-1:0] dest_burst_len_data = {DMA_LENGTH_ALIGN{1'b1}}; + + wire src_beat; + wire src_last_beat; + wire [ID_WIDTH-1:0] src_dest_id; + wire [ADDRESS_WIDTH_SRC-1:0] src_waddr; + wire [ID_WIDTH-2:0] src_id_reduced; + wire src_mem_data_valid; + wire src_mem_data_last; + wire [DATA_WIDTH_MEM_SRC-1:0] src_mem_data; + wire [BYTES_PER_BEAT_WIDTH_MEM_SRC-1:0] src_mem_data_valid_bytes; + wire src_mem_data_partial_burst; + + wire dest_beat; + wire dest_last_beat; + wire dest_last; + wire [ID_WIDTH-1:0] dest_src_id; + wire [ADDRESS_WIDTH_DEST-1:0] dest_raddr; + wire [ID_WIDTH-2:0] dest_id_reduced_next; + wire [ID_WIDTH-1:0] dest_id_next_inc; + wire [ID_WIDTH-2:0] dest_id_reduced; + wire dest_burst_valid; + wire dest_burst_ready; + wire dest_ready; + wire [DATA_WIDTH_MEM_DEST-1:0] dest_mem_data; + wire dest_mem_data_ready; + + `include "inc_id.vh" + + generate if (ID_WIDTH >= 3) begin + assign src_id_reduced = {src_id_reduced_msb,src_id[ID_WIDTH-3:0]}; + assign dest_id_reduced_next = {dest_id_reduced_msb_next,dest_id_next[ID_WIDTH-3:0]}; + assign dest_id_reduced = {dest_id_reduced_msb,dest_id[ID_WIDTH-3:0]}; + end else begin + assign src_id_reduced = src_id_reduced_msb; + assign dest_id_reduced_next = dest_id_reduced_msb_next; + assign dest_id_reduced = dest_id_reduced_msb; + end endgenerate + + assign src_beat = src_mem_data_valid; + assign src_last_beat = src_beat & src_mem_data_last; + assign src_waddr = {src_id_reduced,src_beat_counter}; + + assign src_data_request_id = src_dest_id; + + always @(*) begin + if (src_last_beat == 1'b1) begin + src_id_next = inc_id(src_id); + end else begin + src_id_next = src_id; + end + end + + always @(posedge src_clk) begin + if (src_reset == 1'b1) begin + src_id <= 'h00; + src_id_reduced_msb <= 1'b0; + end else begin + src_id <= src_id_next; + src_id_reduced_msb <= ^src_id_next[ID_WIDTH-1-:2]; + end + end + + always @(posedge src_clk) begin + if (src_reset == 1'b1 || src_last_beat == 1'b1) begin + src_beat_counter <= 'h00; + end else if (src_beat == 1'b1) begin + src_beat_counter <= src_beat_counter + 1'b1; + end + end + + always @(posedge src_clk) begin + if (src_last_beat == 1'b1) begin + burst_len_mem[src_id_reduced] <= src_burst_len_data[BYTES_PER_BURST_WIDTH:DMA_LENGTH_ALIGN]; + end + end + + assign dest_ready = ~dest_mem_data_valid | dest_mem_data_ready; + assign dest_last = dest_beat_counter == dest_burst_len; + + assign dest_beat = dest_valid & dest_ready; + assign dest_last_beat = dest_last & dest_beat; + assign dest_raddr = {dest_id_reduced,dest_beat_counter}; + + assign dest_burst_valid = dest_data_request_id != dest_id_next; + assign dest_burst_ready = ~dest_valid | dest_last_beat; + + /* + * The data valid signal for the destination side is asserted if there are one + * or more pending bursts. It is de-asserted if there are no more pending burst + * and it is the last beat of the current burst + */ + always @(posedge dest_clk) begin + if (dest_reset == 1'b1) begin + dest_valid <= 1'b0; + end else if (dest_burst_valid == 1'b1) begin + dest_valid <= 1'b1; + end else if (dest_last_beat == 1'b1) begin + dest_valid <= 1'b0; + end + end + + /* + * The output register of the memory creates a extra clock cycle of latency on + * the data path. We need to handle this more the handshaking signals. If data + * is available in the memory it will be available one clock cycle later in the + * output register. + */ + always @(posedge dest_clk) begin + if (dest_reset == 1'b1) begin + dest_mem_data_valid <= 1'b0; + end else if (dest_valid == 1'b1) begin + dest_mem_data_valid <= 1'b1; + end else if (dest_mem_data_ready == 1'b1) begin + dest_mem_data_valid <= 1'b0; + end + end + + /* + * This clears dest_data_last after the last beat. Strictly speaking this is not + * necessary if this followed AXI handshaking rules since dest_data_last would + * be qualified by dest_data_valid and it is OK to retain the previous value of + * dest_data_last when dest_data_valid is not asserted. But clearing the signal + * here doesn't cost much and can simplify some of the more congested + * combinatorical logic further up the pipeline since we can assume that + * fifo_last == 1'b1 implies fifo_valid == 1'b1. + */ + always @(posedge dest_clk) begin + if (dest_reset == 1'b1) begin + dest_mem_data_last <= 1'b0; + end else if (dest_beat == 1'b1) begin + dest_mem_data_last <= dest_last; + end else if (dest_mem_data_ready == 1'b1) begin + dest_mem_data_last <= 1'b0; + end + end + + always @(posedge dest_clk) begin + if (dest_beat == 1'b1) begin + if (dest_last == 1'b1) begin + dest_mem_data_strb <= {DATA_WIDTH_MEM_DEST/8{1'b1}} >> ~dest_burst_len_data[BYTES_PER_BEAT_WIDTH_DEST-1:0]; + end else begin + dest_mem_data_strb <= {DATA_WIDTH_MEM_DEST/8{1'b1}}; + end + end + end + + assign dest_id_next_inc = inc_id(dest_id_next); + + always @(posedge dest_clk) begin + if (dest_reset == 1'b1) begin + dest_id_next <= 'h00; + dest_id_reduced_msb_next <= 1'b0; + end else if (dest_burst_valid == 1'b1 && dest_burst_ready == 1'b1) begin + dest_id_next <= dest_id_next_inc; + dest_id_reduced_msb_next <= ^dest_id_next_inc[ID_WIDTH-1-:2]; + end + end + + always @(posedge dest_clk) begin + if (dest_burst_valid == 1'b1 && dest_burst_ready == 1'b1) begin + dest_burst_len_data[BYTES_PER_BURST_WIDTH:DMA_LENGTH_ALIGN] <= burst_len_mem[dest_id_reduced_next]; + end + end + + always @(posedge dest_clk) begin + if (dest_burst_ready == 1'b1) begin + dest_id <= dest_id_next; + dest_id_reduced_msb <= dest_id_reduced_msb_next; + end + end + + always @(posedge dest_clk) begin + if (dest_reset == 1'b1 || dest_last_beat == 1'b1) begin + dest_beat_counter <= 'h00; + end else if (dest_beat == 1'b1) begin + dest_beat_counter <= dest_beat_counter + 1'b1; + end + end + + assign dest_burst_info_length = dest_burst_len_data[BYTES_PER_BURST_WIDTH-1:0]; + assign dest_burst_info_partial = dest_burst_len_data[BYTES_PER_BURST_WIDTH]; + assign dest_burst_info_id = dest_id; + + always @(posedge dest_clk) begin + dest_burst_info_write <= (dest_burst_valid == 1'b1 && dest_burst_ready == 1'b1); + end + + assign dest_burst_len = dest_burst_len_data[BYTES_PER_BURST_WIDTH-1 -: BURST_LEN_WIDTH_DEST]; + + axi_dmac_resize_src #( + .DATA_WIDTH_SRC (DATA_WIDTH_SRC), + .BYTES_PER_BEAT_WIDTH_SRC (BYTES_PER_BEAT_WIDTH_SRC), + .DATA_WIDTH_MEM (DATA_WIDTH_MEM_SRC), + .BYTES_PER_BEAT_WIDTH_MEM (BYTES_PER_BEAT_WIDTH_MEM_SRC) + ) i_resize_src ( + .clk (src_clk), + .reset (src_reset), + + .src_data_valid (src_data_valid), + .src_data (src_data), + .src_data_last (src_data_last), + .src_data_valid_bytes (src_data_valid_bytes), + .src_data_partial_burst (src_data_partial_burst), + + .mem_data_valid (src_mem_data_valid), + .mem_data (src_mem_data), + .mem_data_last (src_mem_data_last), + .mem_data_valid_bytes (src_mem_data_valid_bytes), + .mem_data_partial_burst (src_mem_data_partial_burst)); + + assign src_burst_len_data = {src_mem_data_partial_burst, + src_beat_counter, + src_mem_data_valid_bytes}; + + ad_mem_asym #( + .A_ADDRESS_WIDTH (ADDRESS_WIDTH_SRC), + .A_DATA_WIDTH (DATA_WIDTH_MEM_SRC), + .B_ADDRESS_WIDTH (ADDRESS_WIDTH_DEST), + .B_DATA_WIDTH (DATA_WIDTH_MEM_DEST) + ) i_mem ( + .clka (src_clk), + .wea (src_beat), + .addra (src_waddr), + .dina (src_mem_data), + + .clkb (dest_clk), + .reb (dest_beat), + .addrb (dest_raddr), + .doutb (dest_mem_data)); + + axi_dmac_resize_dest #( + .DATA_WIDTH_DEST (DATA_WIDTH_DEST), + .DATA_WIDTH_MEM (DATA_WIDTH_MEM_DEST) + ) i_resize_dest ( + .clk (dest_clk), + .reset (dest_reset), + + .mem_data_valid (dest_mem_data_valid), + .mem_data_ready (dest_mem_data_ready), + .mem_data (dest_mem_data), + .mem_data_last (dest_mem_data_last), + .mem_data_strb (dest_mem_data_strb), + + .dest_data_valid (dest_data_valid), + .dest_data_ready (dest_data_ready), + .dest_data (dest_data), + .dest_data_last (dest_data_last), + .dest_data_strb (dest_data_strb)); + + sync_bits #( + .NUM_OF_BITS (ID_WIDTH), + .ASYNC_CLK (ASYNC_CLK) + ) i_dest_sync_id ( + .in_bits (src_id), + .out_clk (dest_clk), + .out_resetn (1'b1), + .out_bits (dest_src_id)); + + sync_bits #( + .NUM_OF_BITS (ID_WIDTH), + .ASYNC_CLK (ASYNC_CLK) + ) i_src_sync_id ( + .in_bits (dest_id), + .out_clk (src_clk), + .out_resetn (1'b1), + .out_bits (src_dest_id)); + + assign dest_request_id = dest_src_id; + assign dest_data_response_id = dest_id; + + generate if (ENABLE_DIAGNOSTICS_IF == 1) begin + + reg [ID_WIDTH-1:0] _dest_diag_level_bursts = 'h0; + + // calculate buffer fullness in bursts + always @(posedge dest_clk) begin + if (dest_reset == 1'b1) begin + _dest_diag_level_bursts <= 'h0; + end else begin + _dest_diag_level_bursts <= g2b(dest_src_id) - g2b(dest_id); + end + end + assign dest_diag_level_bursts = {{{8-ID_WIDTH}{1'b0}},_dest_diag_level_bursts}; + + end else begin + assign dest_diag_level_bursts = 'h0; + end + endgenerate + +endmodule diff --git a/adi_library/axi_dmac/axi_dmac_constr.sdc b/adi_library/axi_dmac/axi_dmac_constr.sdc new file mode 100644 index 00000000..2f119333 --- /dev/null +++ b/adi_library/axi_dmac/axi_dmac_constr.sdc @@ -0,0 +1,37 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_false_path -to [get_registers *axi_dmac*cdc_sync_stage1*] +set_false_path -from [get_registers *axi_dmac*cdc_sync_fifo_ram*] +set_false_path -from [get_registers *axi_dmac*eot_mem*] +set_false_path -from [get_registers *axi_dmac*bl_mem*] + +# Burst memory +set_false_path -from [get_registers *axi_dmac*burst_len_mem*] + +# Reset manager +set_false_path \ + -from [get_registers {*|axi_dmac_transfer:i_transfer|axi_dmac_reset_manager:i_reset_manager|do_reset}] \ + -to [get_pins -compatibility_mode {*|axi_dmac_transfer:i_transfer|axi_dmac_reset_manager:i_reset_manager|reset_gen[*].reset_async[*]|clrn}] + +set_false_path \ + -from [get_registers {*|axi_dmac_transfer:i_transfer|axi_dmac_reset_manager:i_reset_manager|reset_gen[*].reset_async[0]}] \ + -to [get_registers {*|axi_dmac_transfer:i_transfer|axi_dmac_reset_manager:i_reset_manager|reset_gen[*].reset_async[3]}] + +set_false_path \ + -from [get_registers {*|axi_dmac_transfer:i_transfer|axi_dmac_reset_manager:i_reset_manager|reset_gen[*].reset_async[0]}] \ + -to [get_pins -compatibility_mode {*|axi_dmac_transfer:i_transfer|axi_dmac_reset_manager:i_reset_manager|reset_gen[*].reset_sync_in|clrn}] + +set_false_path \ + -from [get_registers {*|axi_dmac_transfer:i_transfer|axi_dmac_reset_manager:i_reset_manager|reset_gen[*].reset_sync[0]}] \ + -to [get_pins -compatibility_mode {*|axi_dmac_transfer:i_transfer|axi_dmac_reset_manager:i_reset_manager|reset_gen[*].reset_sync_in|clrn}] + +# Debug signals +set_false_path -from [get_registers *axi_dmac*|*i_request_arb*|cdc_sync_stage2*] -to [get_registers *axi_dmac*up_rdata*] +set_false_path -from [get_registers *axi_dmac*|*i_request_arb*|*id*] -to [get_registers *axi_dmac*up_rdata*] +set_false_path -from [get_registers *axi_dmac*|*i_request_arb*|address*] -to [get_registers *axi_dmac*up_rdata*] +set_false_path \ + -from [get_registers {*|axi_dmac_transfer:i_transfer|axi_dmac_reset_manager:i_reset_manager|reset_gen[*].reset_sync[0]}] \ + -to [get_registers {*|axi_dmac_regmap:i_regmap|up_rdata[*]}] diff --git a/adi_library/axi_dmac/axi_dmac_constr.ttcl b/adi_library/axi_dmac/axi_dmac_constr.ttcl new file mode 100644 index 00000000..e90fe6ba --- /dev/null +++ b/adi_library/axi_dmac/axi_dmac_constr.ttcl @@ -0,0 +1,344 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName [ttcl_add $ComponentName "_constr"] :> +<: setFileExtension ".xdc" :> +<: setFileProcessingOrder late :> +<: set async_dest_req [getBooleanValue "ASYNC_CLK_DEST_REQ"] :> +<: set async_req_src [getBooleanValue "ASYNC_CLK_REQ_SRC"] :> +<: set async_src_dest [getBooleanValue "ASYNC_CLK_SRC_DEST"] :> +<: set async_req_sg [getBooleanValue "ASYNC_CLK_REQ_SG"] :> +<: set async_src_sg [getBooleanValue "ASYNC_CLK_SRC_SG"] :> +<: set async_dest_sg [getBooleanValue "ASYNC_CLK_DEST_SG"] :> +<: set sg_enabled [getBooleanValue "DMA_SG_TRANSFER"] :> +<: set disable_debug_registers [getBooleanValue "DISABLE_DEBUG_REGISTERS"] :> + +set req_clk_ports_base {s_axi_aclk} +set src_clk_ports_base {fifo_wr_clk s_axis_aclk m_src_axi_aclk} +set dest_clk_ports_base {fifo_rd_clk m_axis_aclk m_dest_axi_aclk} +set req_clk_ports $req_clk_ports_base +set src_clk_ports $src_clk_ports_base +set dest_clk_ports $dest_clk_ports_base +<: if {[expr {!$async_req_src}]} { :> +set req_clk_ports "$req_clk_ports $src_clk_ports_base" +set src_clk_ports "$src_clk_ports $req_clk_ports_base" +<: } :> +<: if {[expr {!$async_src_dest}]} { :> +set src_clk_ports "$src_clk_ports $dest_clk_ports_base" +set dest_clk_ports "$dest_clk_ports $src_clk_ports_base" +<: } :> +<: if {[expr {!$async_dest_req}]} { :> +set req_clk_ports "$req_clk_ports $dest_clk_ports_base" +set dest_clk_ports "$dest_clk_ports $req_clk_ports_base" +<: } :> +<: if {$sg_enabled} { :> +set sg_clk_ports_base {m_sg_axi_aclk} +set sg_clk_ports $sg_clk_ports_base +<: if {[expr {!$async_req_sg}]} { :> +set req_clk_ports "$req_clk_ports $sg_clk_ports_base" +set sg_clk_ports "$sg_clk_ports $req_clk_ports_base" +<: } :> +<: if {[expr {!$async_src_sg}]} { :> +set src_clk_ports "$src_clk_ports $sg_clk_ports_base" +set sg_clk_ports "$sg_clk_ports $src_clk_ports_base" +<: } :> +<: if {[expr {!$async_dest_sg}]} { :> +set dest_clk_ports "$dest_clk_ports $sg_clk_ports_base" +set sg_clk_ports "$sg_clk_ports $dest_clk_ports_base" +<: } :> +set sg_clk [get_clocks -of_objects [get_ports -quiet $sg_clk_ports]] +<: } :> +set req_clk [get_clocks -of_objects [get_ports -quiet $req_clk_ports]] +set src_clk [get_clocks -of_objects [get_ports -quiet $src_clk_ports]] +set dest_clk [get_clocks -of_objects [get_ports -quiet $dest_clk_ports]] + +<: if {$async_req_src || $async_src_dest || $async_dest_req || ($async_req_sg && $sg_enabled)} { :> +set_property ASYNC_REG TRUE \ + [get_cells -quiet -hier *cdc_sync_stage1_reg*] \ + [get_cells -quiet -hier *cdc_sync_stage2_reg*] + +<: } :> +<: if {$async_req_src} { :> +set_max_delay -quiet -datapath_only \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_src_request_id* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $req_clk] + +set_false_path -quiet \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_status_src* && IS_SEQUENTIAL}] + +set_false_path -quiet \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_control_src* && IS_SEQUENTIAL}] + +set_max_delay -quiet -datapath_only \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_src_req_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $req_clk] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_src_req_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ + -filter {NAME =~ *i_src_req_fifo* && IS_SEQUENTIAL}] \ + -to $src_clk \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from $req_clk \ + -through [get_cells -quiet -hier DP \ + -filter {NAME =~ *i_request_arb/eot_mem_src_reg*}] \ + -to $src_clk \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_rewind_req_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_rewind_req_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $req_clk] + +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ + -filter {NAME =~ *i_rewind_req_fifo* && IS_SEQUENTIAL}] \ + -to $req_clk \ + [get_property -min PERIOD $req_clk] + +set_false_path -quiet \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *sync_rewind/i_sync_out* && IS_SEQUENTIAL}] + +set_false_path -quiet \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *sync_rewind/i_sync_in* && IS_SEQUENTIAL}] + +<: } :> +<: if {$async_dest_req} { :> +set_max_delay -quiet -datapath_only \ + -from $dest_clk \ + -to [get_cells -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_req_response_id* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $dest_clk] + +set_false_path -quiet \ + -from $dest_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_status_dest* && IS_SEQUENTIAL}] + +set_false_path -quiet \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_control_dest* && IS_SEQUENTIAL}] + +set_max_delay -quiet -datapath_only \ + -from $dest_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_dest_response_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_dest_response_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $req_clk] + +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ + -filter {NAME =~ *i_dest_response_fifo* && IS_SEQUENTIAL}] \ + -to $req_clk \ + [get_property -min PERIOD $req_clk] + +<: } :> +<: if {$async_src_dest} { :> +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_dest_request_id* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_store_and_forward/i_dest_sync_id* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from $dest_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_store_and_forward/i_src_sync_id* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -through [get_cells -quiet -hier \ + -filter {IS_SEQUENTIAL && NAME =~ *i_store_and_forward/burst_len_mem_reg*}] \ + -to $dest_clk \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_dest_req_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from $dest_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_dest_req_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ + -filter {NAME =~ *i_dest_req_fifo* && IS_SEQUENTIAL}] \ + -to $dest_clk \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_src_dest_bl_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from $dest_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_src_dest_bl_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ + -filter {NAME =~ *i_src_dest_bl_fifo* && IS_SEQUENTIAL}] \ + -to $dest_clk \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -through [get_cells -quiet -hier DP \ + -filter {NAME =~ *i_request_arb/eot_mem_dest_reg*}] \ + -to $dest_clk \ + [get_property -min PERIOD $dest_clk] + +<: } :> +<: if {$async_req_sg && $sg_enabled} { :> +set_false_path -quiet \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_sg_enable* && IS_SEQUENTIAL}] + +set_max_delay -quiet -datapath_only \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sg_addr_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $req_clk] + +set_max_delay -quiet -datapath_only \ + -from $sg_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sg_addr_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $sg_clk] + +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ + -filter {NAME =~ *i_sg_addr_fifo* && IS_SEQUENTIAL}] \ + -to $sg_clk \ + [get_property -min PERIOD $sg_clk] + +set_max_delay -quiet -datapath_only \ + -from $sg_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sg_desc_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $sg_clk] + +set_max_delay -quiet -datapath_only \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sg_desc_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $req_clk] + +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ + -filter {NAME =~ *i_sg_desc_fifo* && IS_SEQUENTIAL}] \ + -to $req_clk \ + [get_property -min PERIOD $req_clk] + +set_false_path \ + -to [get_pins -hierarchical * -filter {NAME=~*i_waddr_sync_gray/cdc_sync_stage1_reg[*]/D}] + +set_false_path \ + -to [get_pins -hierarchical * -filter {NAME=~*i_raddr_sync_gray/cdc_sync_stage1_reg[*]/D}] + +<: } :> +# Reset signals +set_false_path -quiet \ + -from [get_cells -quiet -hier *do_reset_reg* \ + -filter {NAME =~ *i_reset_manager* && IS_SEQUENTIAL}] \ + -to [get_pins -quiet -hier *reset_async_reg*/PRE] + +set_false_path -quiet \ + -from [get_cells -quiet -hier *reset_async_reg[0] \ + -filter {NAME =~ *i_reset_manager* && IS_SEQUENTIAL}] \ + -to [get_cells -quiet -hier *reset_async_reg[3]* \ + -filter {NAME =~ *i_reset_manager* && IS_SEQUENTIAL}] + +set_false_path -quiet \ + -from [get_cells -quiet -hier *reset_async_reg[0] \ + -filter {NAME =~ *i_reset_manager* && IS_SEQUENTIAL}] \ + -to [get_pins -quiet -hier *reset_sync_in_reg*/PRE \ + -filter {NAME =~ *i_reset_manager*}] + +set_false_path -quiet \ + -from [get_cells -quiet -hier *reset_sync_reg[0] \ + -filter {NAME =~ *i_reset_manager* && IS_SEQUENTIAL}] \ + -to [get_pins -quiet -hier *reset_sync_in_reg*/PRE \ + -filter {NAME =~ *i_reset_manager*}] + +set_property -dict { \ + SHREG_EXTRACT NO \ + ASYNC_REG TRUE \ + } [get_cells -quiet -hier *reset_async_reg*] + +set_property -dict { \ + SHREG_EXTRACT NO \ + ASYNC_REG TRUE \ + } [get_cells -quiet -hier *reset_sync_reg*] + +# Ignore timing for debug signals to register map +<: if {!$disable_debug_registers} { :> +set_false_path -quiet \ + -from [get_cells -quiet -hier *cdc_sync_stage2_reg* \ + -filter {name =~ *i_sync_src_request_id* && IS_SEQUENTIAL}] \ + -to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}] +set_false_path -quiet \ + -from [get_cells -quiet -hier *cdc_sync_stage2_reg* \ + -filter {name =~ *i_dest_sync_id* && IS_SEQUENTIAL}] \ + -to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}] +set_false_path -quiet \ + -from [get_cells -quiet -hier *id_reg* -filter {name =~ *i_request_arb* && IS_SEQUENTIAL}] \ + -to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}] +set_false_path -quiet \ + -from [get_cells -quiet -hier *address_reg* -filter {name =~ *i_addr_gen* && IS_SEQUENTIAL}] \ + -to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}] +set_false_path -quiet \ + -from [get_cells -quiet -hier *reset_sync_reg* -filter {name =~ *i_reset_manager* && IS_SEQUENTIAL}] \ + -to [get_cells -quiet -hier *up_rdata_reg* -filter {IS_SEQUENTIAL}] +<: } :> diff --git a/adi_library/axi_dmac/axi_dmac_hw.tcl b/adi_library/axi_dmac/axi_dmac_hw.tcl new file mode 100644 index 00000000..b8bde93a --- /dev/null +++ b/adi_library/axi_dmac/axi_dmac_hw.tcl @@ -0,0 +1,653 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +source ../../scripts/adi_env.tcl +source ../scripts/adi_ip_intel.tcl + +set_module_property NAME axi_dmac +set_module_property DESCRIPTION "AXI DMA Controller" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME axi_dmac +set_module_property ELABORATION_CALLBACK axi_dmac_elaborate +set_module_property VALIDATION_CALLBACK axi_dmac_validate + +# files + +ad_ip_files axi_dmac [list \ + $ad_hdl_dir/library/util_cdc/sync_bits.v \ + $ad_hdl_dir/library/util_cdc/sync_event.v \ + $ad_hdl_dir/library/util_cdc/sync_gray.v \ + $ad_hdl_dir/library/common/up_axi.v \ + $ad_hdl_dir/library/util_axis_fifo/util_axis_fifo.v \ + $ad_hdl_dir/library/util_axis_fifo/util_axis_fifo_address_generator.v \ + $ad_hdl_dir/library/common/ad_mem_asym.v \ + inc_id.vh \ + resp.vh \ + axi_dmac_burst_memory.v \ + axi_dmac_regmap.v \ + axi_dmac_regmap_request.v \ + axi_dmac_reset_manager.v \ + axi_dmac_resize_dest.v \ + axi_dmac_resize_src.v \ + axi_dmac_response_manager.v \ + axi_dmac_transfer.v \ + address_generator.v \ + data_mover.v \ + request_arb.v \ + request_generator.v \ + response_handler.v \ + axi_register_slice.v \ + dmac_2d_transfer.v \ + dmac_sg.v \ + dest_axi_mm.v \ + dest_axi_stream.v \ + dest_fifo_inf.v \ + src_axi_mm.v \ + src_axi_stream.v \ + src_fifo_inf.v \ + splitter.v \ + response_generator.v \ + axi_dmac.v \ + axi_dmac_constr.sdc \ +] + +# Disable dual-clock RAM read-during-write behaviour warning. +set_qip_strings { "set_instance_assignment -name MESSAGE_DISABLE 276027 -entity axi_dmac_burst_memory" } + +# parameters + +set group "General Configuration" + +add_parameter ID INTEGER 0 +set_parameter_property ID DISPLAY_NAME "Core ID" +set_parameter_property ID HDL_PARAMETER true +set_parameter_property ID GROUP $group + +add_parameter DMA_LENGTH_WIDTH INTEGER 24 +set_parameter_property DMA_LENGTH_WIDTH DISPLAY_NAME "DMA Transfer Length Register Width" +set_parameter_property DMA_LENGTH_WIDTH UNITS Bits +set_parameter_property DMA_LENGTH_WIDTH HDL_PARAMETER true +set_parameter_property DMA_LENGTH_WIDTH ALLOWED_RANGES {8:32} +set_parameter_property DMA_LENGTH_WIDTH GROUP $group + +add_parameter FIFO_SIZE INTEGER 8 +set_parameter_property FIFO_SIZE DISPLAY_NAME "Store-and-Forward Memory Size (In Bursts)" +set_parameter_property FIFO_SIZE HDL_PARAMETER true +set_parameter_property FIFO_SIZE ALLOWED_RANGES {2 4 8 16 32} +set_parameter_property FIFO_SIZE GROUP $group + +add_parameter MAX_BYTES_PER_BURST INTEGER 128 +set_parameter_property MAX_BYTES_PER_BURST DISPLAY_NAME "Maximum bytes per burst" +set_parameter_property MAX_BYTES_PER_BURST HDL_PARAMETER true +set_parameter_property MAX_BYTES_PER_BURST GROUP $group + +add_parameter DMA_AXI_ADDR_WIDTH INTEGER 32 +set_parameter_property DMA_AXI_ADDR_WIDTH DISPLAY_NAME "DMA AXI Address Width" +set_parameter_property DMA_AXI_ADDR_WIDTH UNITS Bits +set_parameter_property DMA_AXI_ADDR_WIDTH HDL_PARAMETER true +set_parameter_property DMA_AXI_ADDR_WIDTH ALLOWED_RANGES {16:64} +set_parameter_property DMA_AXI_ADDR_WIDTH GROUP $group + +foreach {suffix group} { \ + "SRC" "Source" \ + "DEST" "Destination" \ + } { + + add_display_item "Endpoint Configuration" $group "group" + + add_parameter DMA_TYPE_$suffix INTEGER 0 + set_parameter_property DMA_TYPE_$suffix DISPLAY_NAME "Type" + set_parameter_property DMA_TYPE_$suffix HDL_PARAMETER true + set_parameter_property DMA_TYPE_$suffix ALLOWED_RANGES \ + { "0:Memory-Mapped AXI" "1:Streaming AXI" "2:FIFO Interface" } + set_parameter_property DMA_TYPE_$suffix GROUP $group + + add_parameter DMA_AXI_PROTOCOL_$suffix INTEGER 1 + set_parameter_property DMA_AXI_PROTOCOL_$suffix DISPLAY_NAME "AXI Protocol" + set_parameter_property DMA_AXI_PROTOCOL_$suffix HDL_PARAMETER true + set_parameter_property DMA_AXI_PROTOCOL_$suffix ALLOWED_RANGES { "0:AXI4" "1:AXI3" } + set_parameter_property DMA_AXI_PROTOCOL_$suffix GROUP $group + + add_parameter DMA_DATA_WIDTH_$suffix INTEGER 64 + set_parameter_property DMA_DATA_WIDTH_$suffix DISPLAY_NAME "Bus Width" + set_parameter_property DMA_DATA_WIDTH_$suffix UNITS Bits + set_parameter_property DMA_DATA_WIDTH_$suffix HDL_PARAMETER true + set_parameter_property DMA_DATA_WIDTH_$suffix ALLOWED_RANGES {16 32 64 128 256 512 1024} + set_parameter_property DMA_DATA_WIDTH_$suffix GROUP $group + + add_parameter AXI_SLICE_$suffix INTEGER 0 + set_parameter_property AXI_SLICE_$suffix DISPLAY_NAME "Insert Register Slice" + set_parameter_property AXI_SLICE_$suffix DISPLAY_HINT boolean + set_parameter_property AXI_SLICE_$suffix HDL_PARAMETER true + set_parameter_property AXI_SLICE_$suffix GROUP $group +} + +# FIFO interface +set_parameter_property DMA_TYPE_SRC DEFAULT_VALUE 2 + +# Scatter-Gather interface +add_parameter DMA_AXI_PROTOCOL_SG INTEGER 1 +set_parameter_property DMA_AXI_PROTOCOL_SG DISPLAY_NAME "AXI Protocol" +set_parameter_property DMA_AXI_PROTOCOL_SG HDL_PARAMETER true +set_parameter_property DMA_AXI_PROTOCOL_SG ALLOWED_RANGES { "0:AXI4" "1:AXI3" } +set_parameter_property DMA_AXI_PROTOCOL_SG VISIBLE true +set_parameter_property DMA_AXI_PROTOCOL_SG GROUP $group + +add_parameter DMA_DATA_WIDTH_SG INTEGER 64 +set_parameter_property DMA_DATA_WIDTH_SG DISPLAY_NAME "Bus Width" +set_parameter_property DMA_DATA_WIDTH_SG UNITS Bits +set_parameter_property DMA_DATA_WIDTH_SG HDL_PARAMETER true +set_parameter_property DMA_DATA_WIDTH_SG ALLOWED_RANGES {64} +set_parameter_property DMA_DATA_WIDTH_SG VISIBLE true +set_parameter_property DMA_DATA_WIDTH_SG GROUP $group + +set group "Features" + +add_parameter CYCLIC INTEGER 1 +set_parameter_property CYCLIC DISPLAY_NAME "Cyclic Transfer Support" +set_parameter_property CYCLIC DISPLAY_HINT boolean +set_parameter_property CYCLIC HDL_PARAMETER true +set_parameter_property CYCLIC GROUP $group + +add_parameter DMA_2D_TRANSFER INTEGER 0 +set_parameter_property DMA_2D_TRANSFER DISPLAY_NAME "2D Transfer Support" +set_parameter_property DMA_2D_TRANSFER DISPLAY_HINT boolean +set_parameter_property DMA_2D_TRANSFER HDL_PARAMETER true +set_parameter_property DMA_2D_TRANSFER GROUP $group + +add_parameter DMA_SG_TRANSFER INTEGER 0 +set_parameter_property DMA_SG_TRANSFER DISPLAY_NAME "SG Transfer Support" +set_parameter_property DMA_SG_TRANSFER DISPLAY_HINT boolean +set_parameter_property DMA_SG_TRANSFER HDL_PARAMETER true +set_parameter_property DMA_SG_TRANSFER GROUP $group + +add_parameter SYNC_TRANSFER_START INTEGER 0 +set_parameter_property SYNC_TRANSFER_START DISPLAY_NAME "Transfer Start Synchronization Support" +set_parameter_property SYNC_TRANSFER_START DISPLAY_HINT boolean +set_parameter_property SYNC_TRANSFER_START HDL_PARAMETER true +set_parameter_property SYNC_TRANSFER_START GROUP $group + +set group "Clock Domain Configuration" + +add_parameter AUTO_ASYNC_CLK BOOLEAN 1 +set_parameter_property AUTO_ASYNC_CLK DISPLAY_NAME "Automatically Detect Clock Domains" +set_parameter_property AUTO_ASYNC_CLK HDL_PARAMETER false +set_parameter_property AUTO_ASYNC_CLK GROUP $group + +foreach {p name} { \ + ASYNC_CLK_REQ_SRC "Request and Source" \ + ASYNC_CLK_SRC_DEST "Source and Destination" \ + ASYNC_CLK_DEST_REQ "Destination and Request" \ + ASYNC_CLK_REQ_SG "Request and Scatter-Gather" \ + ASYNC_CLK_SRC_SG "Source and Scatter-Gather" \ + ASYNC_CLK_DEST_SG "Destination and Scatter-Gather" \ + } { + + add_parameter ${p}_MANUAL INTEGER 1 + set_parameter_property ${p}_MANUAL DISPLAY_NAME [concat $name "Clock Asynchronous"] + set_parameter_property ${p}_MANUAL DISPLAY_HINT boolean + set_parameter_property ${p}_MANUAL HDL_PARAMETER false + set_parameter_property ${p}_MANUAL VISIBLE false + set_parameter_property ${p}_MANUAL GROUP $group + + add_parameter $p INTEGER 1 + set_parameter_property $p DISPLAY_NAME [concat $name "Clock Asynchronous"] + set_parameter_property $p DISPLAY_HINT boolean + set_parameter_property $p HDL_PARAMETER true + set_parameter_property $p DERIVED true + set_parameter_property $p GROUP $group +} + +add_parameter CLK_DOMAIN_REQ INTEGER +set_parameter_property CLK_DOMAIN_REQ HDL_PARAMETER false +set_parameter_property CLK_DOMAIN_REQ SYSTEM_INFO {CLOCK_DOMAIN s_axi_clock} +set_parameter_property CLK_DOMAIN_REQ VISIBLE false +set_parameter_property CLK_DOMAIN_REQ GROUP $group + +set src_clks { \ + {CLK_DOMAIN_SRC_AXI m_src_axi_clock} \ + {CLK_DOMAIN_SRC_SAXI if_s_axis_aclk} \ + {CLK_DOMAIN_SRC_FIFO if_fifo_wr_clk} \ +} + +set dest_clks { \ + {CLK_DOMAIN_DEST_AXI m_dest_axi_clock} \ + {CLK_DOMAIN_DEST_SAXI if_m_axis_aclk} \ + {CLK_DOMAIN_DEST_FIFO if_fifo_rd_clk} \ +} + +foreach domain [list {*}$src_clks {*}$dest_clks] { + lassign $domain p clk + add_parameter $p INTEGER + set_parameter_property $p HDL_PARAMETER false + set_parameter_property $p SYSTEM_INFO [list CLOCK_DOMAIN $clk] + set_parameter_property $p VISIBLE false + set_parameter_property $p GROUP $group +} + +add_parameter CLK_DOMAIN_SG INTEGER +set_parameter_property CLK_DOMAIN_SG HDL_PARAMETER false +set_parameter_property CLK_DOMAIN_SG SYSTEM_INFO {CLOCK_DOMAIN m_sg_axi_clock} +set_parameter_property CLK_DOMAIN_SG VISIBLE false +set_parameter_property CLK_DOMAIN_SG GROUP $group + +# axi4 slave + +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 11 + +add_interface interrupt_sender interrupt end +set_interface_property interrupt_sender associatedAddressablePoint s_axi +set_interface_property interrupt_sender associatedClock s_axi_clock +set_interface_property interrupt_sender associatedReset s_axi_reset +set_interface_property interrupt_sender ENABLED true +set_interface_property interrupt_sender EXPORT_OF "" +set_interface_property interrupt_sender PORT_NAME_MAP "" +set_interface_property interrupt_sender CMSIS_SVD_VARIABLES "" +set_interface_property interrupt_sender SVD_ADDRESS_GROUP "" + +add_interface_port interrupt_sender irq irq Output 1 + +proc axi_dmac_validate {} { + set auto_clk [get_parameter_value AUTO_ASYNC_CLK] + set type_src [get_parameter_value DMA_TYPE_SRC] + set type_dest [get_parameter_value DMA_TYPE_DEST] + + set max_burst 32768 + + if {$auto_clk == true} { + global src_clks dest_clks + + set req_domain [get_parameter_value CLK_DOMAIN_REQ] + set src_domain [get_parameter_value [lindex $src_clks $type_src 0]] + set dest_domain [get_parameter_value [lindex $dest_clks $type_dest 0]] + set sg_domain [get_parameter_value CLK_DOMAIN_SG] + + if {$req_domain != 0 && $req_domain == $src_domain} { + set_parameter_value ASYNC_CLK_REQ_SRC 0 + } else { + set_parameter_value ASYNC_CLK_REQ_SRC 1 + } + + if {$src_domain != 0 && $src_domain == $dest_domain} { + set_parameter_value ASYNC_CLK_SRC_DEST 0 + } else { + set_parameter_value ASYNC_CLK_SRC_DEST 1 + } + + if {$dest_domain != 0 && $dest_domain == $req_domain} { + set_parameter_value ASYNC_CLK_DEST_REQ 0 + } else { + set_parameter_value ASYNC_CLK_DEST_REQ 1 + } + + if {$sg_domain != 0 && $sg_domain == $req_domain} { + set_parameter_value ASYNC_CLK_REQ_SG 0 + } else { + set_parameter_value ASYNC_CLK_REQ_SG 1 + } + + if {$sg_domain != 0 && $sg_domain == $src_domain} { + set_parameter_value ASYNC_CLK_SRC_SG 0 + } else { + set_parameter_value ASYNC_CLK_SRC_SG 1 + } + + if {$sg_domain != 0 && $sg_domain == $dest_domain} { + set_parameter_value ASYNC_CLK_DEST_SG 0 + } else { + set_parameter_value ASYNC_CLK_DEST_SG 1 + } + } else { + foreach p {ASYNC_CLK_REQ_SRC ASYNC_CLK_SRC_DEST ASYNC_CLK_DEST_REQ ASYNC_CLK_REQ_SG ASYNC_CLK_SRC_SG ASYNC_CLK_DEST_SG} { + set_parameter_value $p [get_parameter_value ${p}_MANUAL] + } + } + + foreach p {ASYNC_CLK_REQ_SRC ASYNC_CLK_SRC_DEST ASYNC_CLK_DEST_REQ ASYNC_CLK_REQ_SG ASYNC_CLK_SRC_SG ASYNC_CLK_DEST_SG} { + set_parameter_property ${p}_MANUAL VISIBLE [expr $auto_clk ? false : true] + set_parameter_property $p VISIBLE $auto_clk + } + foreach suffix {SRC DEST} { + if {[get_parameter_value DMA_TYPE_$suffix] == 0} { + set show_axi_protocol true + set proto [get_parameter_value DMA_AXI_PROTOCOL_$suffix] + set width [get_parameter_value DMA_DATA_WIDTH_$suffix] + if {$proto == 0} { + set max_burst [expr min($max_burst, $width * 256 / 8)] + } else { + set max_burst [expr min($max_burst, $width * 16 / 8)] + } + } else { + set show_axi_protocol false + } + set_parameter_property DMA_AXI_PROTOCOL_$suffix VISIBLE $show_axi_protocol + } + + set_parameter_property MAX_BYTES_PER_BURST ALLOWED_RANGES "1:$max_burst" +} + +# conditional interfaces + +# axi4 destination/source + +add_interface m_dest_axi_clock clock end +add_interface_port m_dest_axi_clock m_dest_axi_aclk clk Input 1 + +add_interface m_dest_axi_reset reset end +set_interface_property m_dest_axi_reset associatedClock m_dest_axi_clock +add_interface_port m_dest_axi_reset m_dest_axi_aresetn reset_n Input 1 + + +add_interface m_src_axi_clock clock end +add_interface_port m_src_axi_clock m_src_axi_aclk clk Input 1 + +add_interface m_src_axi_reset reset end +set_interface_property m_src_axi_reset associatedClock m_src_axi_clock +add_interface_port m_src_axi_reset m_src_axi_aresetn reset_n Input 1 + +# axi4 scatter-gather + +add_interface m_sg_axi_clock clock end +add_interface_port m_sg_axi_clock m_sg_axi_aclk clk Input 1 + +add_interface m_sg_axi_reset reset end +set_interface_property m_sg_axi_reset associatedClock m_sg_axi_clock +add_interface_port m_sg_axi_reset m_sg_axi_aresetn reset_n Input 1 + +# axis destination/source + +ad_interface clock m_axis_aclk input 1 clk +ad_interface signal m_axis_xfer_req output 1 xfer_req + +add_interface m_axis axi4stream start +set_interface_property m_axis associatedClock if_m_axis_aclk +set_interface_property m_axis associatedReset s_axi_reset +add_interface_port m_axis m_axis_valid tvalid Output 1 +add_interface_port m_axis m_axis_last tlast Output 1 +add_interface_port m_axis m_axis_ready tready Input 1 +add_interface_port m_axis m_axis_data tdata Output DMA_DATA_WIDTH_DEST +add_interface_port m_axis m_axis_user tuser Output 1 +add_interface_port m_axis m_axis_id tid Output DMA_AXIS_ID_W +add_interface_port m_axis m_axis_dest tdest Output DMA_AXIS_DEST_W +add_interface_port m_axis m_axis_strb tstrb Output DMA_DATA_WIDTH_DEST/8 +add_interface_port m_axis m_axis_keep tkeep Output DMA_DATA_WIDTH_DEST/8 + +ad_interface clock s_axis_aclk input 1 clk +ad_interface signal s_axis_xfer_req output 1 xfer_req + +add_interface s_axis axi4stream end +set_interface_property s_axis associatedClock if_s_axis_aclk +set_interface_property s_axis associatedReset s_axi_reset +add_interface_port s_axis s_axis_valid tvalid Input 1 +add_interface_port s_axis s_axis_last tlast Input 1 +add_interface_port s_axis s_axis_ready tready Output 1 +add_interface_port s_axis s_axis_data tdata Input DMA_DATA_WIDTH_SRC +add_interface_port s_axis s_axis_user tuser Input 1 +add_interface_port s_axis s_axis_id tid Input DMA_AXIS_ID_W +add_interface_port s_axis s_axis_dest tdest Input DMA_AXIS_DEST_W +add_interface_port s_axis s_axis_strb tstrb Input DMA_DATA_WIDTH_SRC/8 +add_interface_port s_axis s_axis_keep tkeep Input DMA_DATA_WIDTH_SRC/8 + +# fifo destination/source + +ad_interface clock fifo_rd_clk input 1 clk +ad_interface signal fifo_rd_en input 1 valid +ad_interface signal fifo_rd_valid output 1 valid +ad_interface signal fifo_rd_dout output DMA_DATA_WIDTH_DEST data +ad_interface signal fifo_rd_underflow output 1 unf +ad_interface signal fifo_rd_xfer_req output 1 xfer_req + +ad_interface clock fifo_wr_clk input 1 clk +ad_interface signal fifo_wr_en input 1 valid +ad_interface signal fifo_wr_din input DMA_DATA_WIDTH_SRC data +ad_interface signal fifo_wr_overflow output 1 ovf +ad_interface signal fifo_wr_sync input 1 sync +ad_interface signal fifo_wr_xfer_req output 1 xfer_req + +proc add_axi_master_interface {axi_type port suffix} { + add_interface $port $axi_type start + set_interface_property $port associatedClock ${port}_clock + set_interface_property $port associatedReset ${port}_reset + set_interface_property $port readIssuingCapability 1 + add_interface_port $port ${port}_awvalid awvalid Output 1 + add_interface_port $port ${port}_awaddr awaddr Output 32 + add_interface_port $port ${port}_awready awready Input 1 + add_interface_port $port ${port}_wvalid wvalid Output 1 + add_interface_port $port ${port}_wdata wdata Output DMA_DATA_WIDTH_${suffix} + add_interface_port $port ${port}_wstrb wstrb Output DMA_DATA_WIDTH_${suffix}/8 + add_interface_port $port ${port}_wready wready Input 1 + add_interface_port $port ${port}_bvalid bvalid Input 1 + add_interface_port $port ${port}_bresp bresp Input 2 + add_interface_port $port ${port}_bready bready Output 1 + add_interface_port $port ${port}_arvalid arvalid Output 1 + add_interface_port $port ${port}_araddr araddr Output 32 + add_interface_port $port ${port}_arready arready Input 1 + add_interface_port $port ${port}_rvalid rvalid Input 1 + add_interface_port $port ${port}_rresp rresp Input 2 + add_interface_port $port ${port}_rdata rdata Input DMA_DATA_WIDTH_${suffix} + add_interface_port $port ${port}_rready rready Output 1 + add_interface_port $port ${port}_awlen awlen Output "8-(4*DMA_AXI_PROTOCOL_${suffix})" + add_interface_port $port ${port}_awsize awsize Output 3 + add_interface_port $port ${port}_awburst awburst Output 2 + add_interface_port $port ${port}_awcache awcache Output 4 + add_interface_port $port ${port}_awprot awprot Output 3 + add_interface_port $port ${port}_wlast wlast Output 1 + add_interface_port $port ${port}_arlen arlen Output "8-(4*DMA_AXI_PROTOCOL_${suffix})" + add_interface_port $port ${port}_arsize arsize Output 3 + add_interface_port $port ${port}_arburst arburst Output 2 + add_interface_port $port ${port}_arcache arcache Output 4 + add_interface_port $port ${port}_arprot arprot Output 3 + # Some signals are mandatory in Intel's implementation of AXI3 + # awid, awlock, wid, bid, arid, arlock, rid, rlast + # Hide them in AXI4 + add_interface_port $port ${port}_awid awid Output 1 + add_interface_port $port ${port}_awlock awlock Output "1+DMA_AXI_PROTOCOL_${suffix}" + add_interface_port $port ${port}_wid wid Output 1 + add_interface_port $port ${port}_arid arid Output 1 + add_interface_port $port ${port}_arlock arlock Output "1+DMA_AXI_PROTOCOL_${suffix}" + add_interface_port $port ${port}_rid rid Input 1 + add_interface_port $port ${port}_bid bid Input 1 + add_interface_port $port ${port}_rlast rlast Input 1 + if {$axi_type == "axi4"} { + set_port_property ${port}_awid TERMINATION true + set_port_property ${port}_awlock TERMINATION true + set_port_property ${port}_wid TERMINATION true + set_port_property ${port}_arid TERMINATION true + set_port_property ${port}_arlock TERMINATION true + set_port_property ${port}_rid TERMINATION true + set_port_property ${port}_bid TERMINATION true + if {$port == "m_dest_axi"} { + set_port_property ${port}_rlast TERMINATION true + } + } +} +proc axi_dmac_elaborate {} { + set fifo_size [get_parameter_value FIFO_SIZE] + set disabled_intfs {} + + # add axi3 or axi4 interface depending on user selection + foreach {suffix port} {SRC m_src_axi DEST m_dest_axi SG m_sg_axi} { + if {[get_parameter_value DMA_AXI_PROTOCOL_${suffix}] == 0} { + set axi_type axi4 + } else { + set axi_type axi + } + add_axi_master_interface $axi_type $port $suffix + } + + # axi4 destination/source + + if {[get_parameter_value DMA_TYPE_DEST] == 0} { + set_interface_property m_dest_axi writeIssuingCapability $fifo_size + set_interface_property m_dest_axi combinedIssuingCapability $fifo_size + } else { + lappend disabled_intfs m_dest_axi_clock m_dest_axi_reset m_dest_axi + } + + if {[get_parameter_value DMA_TYPE_SRC] == 0} { + set_interface_property m_src_axi readIssuingCapability $fifo_size + set_interface_property m_src_axi combinedIssuingCapability $fifo_size + } else { + lappend disabled_intfs m_src_axi_clock m_src_axi_reset m_src_axi + } + + if {[get_parameter_value DMA_SG_TRANSFER] == 1} { + set_interface_property m_sg_axi readIssuingCapability $fifo_size + set_interface_property m_sg_axi combinedIssuingCapability $fifo_size + } else { + lappend disabled_intfs m_sg_axi_clock m_sg_axi_reset m_sg_axi + } + + # axis destination/source + + if {[get_parameter_value DMA_TYPE_DEST] != 1} { + lappend disabled_intfs if_m_axis_aclk if_m_axis_xfer_req m_axis + } else { + if {[get_parameter_value HAS_AXIS_TSTRB] == 0} { + set_port_property m_axis_strb termination true + } + if {[get_parameter_value HAS_AXIS_TKEEP] == 0} { + set_port_property m_axis_keep termination true + } + if {[get_parameter_value HAS_AXIS_TLAST] == 0} { + set_port_property m_axis_last termination true + } + if {[get_parameter_value HAS_AXIS_TID] == 0} { + set_port_property m_axis_id termination true + } + if {[get_parameter_value HAS_AXIS_TDEST] == 0} { + set_port_property m_axis_dest termination true + } + if {[get_parameter_value HAS_AXIS_TUSER] == 0} { + set_port_property m_axis_user termination true + } + } + + if {[get_parameter_value DMA_TYPE_SRC] != 1} { + lappend disabled_intfs if_s_axis_aclk if_s_axis_xfer_req s_axis + } else { + if {[get_parameter_value HAS_AXIS_TSTRB] == 0} { + set_port_property s_axis_strb termination true + set_port_property s_axis_strb termination_value 0xFF + } + if {[get_parameter_value HAS_AXIS_TKEEP] == 0} { + set_port_property s_axis_keep termination true + set_port_property s_axis_keep termination_value 0xFF + } + if {[get_parameter_value HAS_AXIS_TLAST] == 0} { + set_port_property s_axis_last termination true + set_port_property s_axis_last termination_value 0 + } + if {[get_parameter_value HAS_AXIS_TID] == 0} { + set_port_property s_axis_id termination true + set_port_property s_axis_id termination_value 0 + } + if {[get_parameter_value HAS_AXIS_TDEST] == 0} { + set_port_property s_axis_dest termination true + set_port_property s_axis_dest termination_value 0 + } + if {[get_parameter_value HAS_AXIS_TUSER] == 0} { + if {[get_parameter_value SYNC_TRANSFER_START] == 0} { + set_port_property s_axis_user termination true + set_port_property s_axis_user termination_value 0 + } + } + } + + # fifo destination/source + + if {[get_parameter_value DMA_TYPE_DEST] != 2} { + lappend disabled_intfs \ + if_fifo_rd_clk if_fifo_rd_en if_fifo_rd_valid if_fifo_rd_dout \ + if_fifo_rd_underflow if_fifo_rd_xfer_req + } + + if {[get_parameter_value DMA_TYPE_SRC] != 2} { + lappend disabled_intfs \ + if_fifo_wr_clk if_fifo_wr_en if_fifo_wr_din if_fifo_wr_overflow \ + if_fifo_wr_sync if_fifo_wr_xfer_req + } + + if {[get_parameter_value DMA_TYPE_SRC] == 2 && + [get_parameter_value SYNC_TRANSFER_START] == 0} { + set_port_property fifo_wr_sync termination true + set_port_property fifo_wr_sync termination_value 1 + } + + if {[get_parameter_value ENABLE_DIAGNOSTICS_IF] != 1} { + lappend disabled_intfs diagnostics_if + } + + foreach intf $disabled_intfs { + set_interface_property $intf ENABLED false + } +} + +set group "Debug" + +add_parameter DISABLE_DEBUG_REGISTERS INTEGER 0 +set_parameter_property DISABLE_DEBUG_REGISTERS DISPLAY_NAME "Disable debug registers" +set_parameter_property DISABLE_DEBUG_REGISTERS DISPLAY_HINT boolean +set_parameter_property DISABLE_DEBUG_REGISTERS HDL_PARAMETER false +set_parameter_property DISABLE_DEBUG_REGISTERS GROUP $group + +add_parameter ENABLE_DIAGNOSTICS_IF INTEGER 0 +set_parameter_property ENABLE_DIAGNOSTICS_IF DISPLAY_NAME "Enable Diagnostics Interface" +set_parameter_property ENABLE_DIAGNOSTICS_IF DISPLAY_HINT boolean +set_parameter_property ENABLE_DIAGNOSTICS_IF HDL_PARAMETER true +set_parameter_property ENABLE_DIAGNOSTICS_IF GROUP $group + +add_interface diagnostics_if conduit end +add_interface_port diagnostics_if dest_diag_level_bursts dest_diag_level_bursts Output "8" + +set group "AXI Stream interface common configuration" + +add_parameter HAS_AXIS_TSTRB INTEGER 0 +set_parameter_property HAS_AXIS_TSTRB DISPLAY_NAME "AXI Stream interface has TSTRB" +set_parameter_property HAS_AXIS_TSTRB DISPLAY_HINT boolean +set_parameter_property HAS_AXIS_TSTRB HDL_PARAMETER false +set_parameter_property HAS_AXIS_TSTRB GROUP $group + +add_parameter HAS_AXIS_TKEEP INTEGER 0 +set_parameter_property HAS_AXIS_TKEEP DISPLAY_NAME "AXI Stream interface has TKEEP" +set_parameter_property HAS_AXIS_TKEEP DISPLAY_HINT boolean +set_parameter_property HAS_AXIS_TKEEP HDL_PARAMETER false +set_parameter_property HAS_AXIS_TKEEP GROUP $group + +add_parameter HAS_AXIS_TLAST INTEGER 0 +set_parameter_property HAS_AXIS_TLAST DISPLAY_NAME "AXI Stream interface has TLAST" +set_parameter_property HAS_AXIS_TLAST DISPLAY_HINT boolean +set_parameter_property HAS_AXIS_TLAST HDL_PARAMETER false +set_parameter_property HAS_AXIS_TLAST GROUP $group + +add_parameter HAS_AXIS_TID INTEGER 0 +set_parameter_property HAS_AXIS_TID DISPLAY_NAME "AXI Stream interface has TID" +set_parameter_property HAS_AXIS_TID DISPLAY_HINT boolean +set_parameter_property HAS_AXIS_TID HDL_PARAMETER false +set_parameter_property HAS_AXIS_TID GROUP $group + +add_parameter DMA_AXIS_ID_W INTEGER 8 +set_parameter_property DMA_AXIS_ID_W DISPLAY_NAME "AXI Stream TID width" +set_parameter_property DMA_AXIS_ID_W HDL_PARAMETER true +set_parameter_property DMA_AXIS_ID_W GROUP $group + +add_parameter HAS_AXIS_TDEST INTEGER 0 +set_parameter_property HAS_AXIS_TDEST DISPLAY_NAME "AXI Stream interface has TDEST" +set_parameter_property HAS_AXIS_TDEST DISPLAY_HINT boolean +set_parameter_property HAS_AXIS_TDEST HDL_PARAMETER false +set_parameter_property HAS_AXIS_TDEST GROUP $group + +add_parameter DMA_AXIS_DEST_W INTEGER 4 +set_parameter_property DMA_AXIS_DEST_W DISPLAY_NAME "AXI Stream TDEST width" +set_parameter_property DMA_AXIS_DEST_W HDL_PARAMETER true +set_parameter_property DMA_AXIS_DEST_W GROUP $group + +add_parameter HAS_AXIS_TUSER INTEGER 0 +set_parameter_property HAS_AXIS_TUSER DISPLAY_NAME "AXI Stream interface has TUSER" +set_parameter_property HAS_AXIS_TUSER DISPLAY_HINT boolean +set_parameter_property HAS_AXIS_TUSER HDL_PARAMETER false +set_parameter_property HAS_AXIS_TUSER GROUP $group diff --git a/adi_library/axi_dmac/axi_dmac_ip.tcl b/adi_library/axi_dmac/axi_dmac_ip.tcl new file mode 100644 index 00000000..d3e1cf00 --- /dev/null +++ b/adi_library/axi_dmac/axi_dmac_ip.tcl @@ -0,0 +1,527 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create axi_dmac +adi_ip_files axi_dmac [list \ + "$ad_hdl_dir/library/common/ad_mem_asym.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "inc_id.vh" \ + "resp.vh" \ + "axi_dmac_burst_memory.v" \ + "axi_dmac_regmap.v" \ + "axi_dmac_regmap_request.v" \ + "axi_dmac_reset_manager.v" \ + "axi_dmac_resize_dest.v" \ + "axi_dmac_resize_src.v" \ + "axi_dmac_response_manager.v" \ + "axi_dmac_transfer.v" \ + "address_generator.v" \ + "data_mover.v" \ + "request_arb.v" \ + "request_generator.v" \ + "response_handler.v" \ + "axi_register_slice.v" \ + "dmac_2d_transfer.v" \ + "dmac_sg.v" \ + "dest_axi_mm.v" \ + "dest_axi_stream.v" \ + "dest_fifo_inf.v" \ + "src_axi_mm.v" \ + "src_axi_stream.v" \ + "src_fifo_inf.v" \ + "splitter.v" \ + "response_generator.v" \ + "axi_dmac.v" \ + "axi_dmac_constr.ttcl" \ + "axi_dmac_pkg_sv.ttcl" \ + "bd/bd.tcl" ] + +adi_ip_properties axi_dmac +adi_ip_infer_mm_interfaces axi_dmac +adi_ip_ttcl axi_dmac "axi_dmac_constr.ttcl" +adi_ip_sim_ttcl axi_dmac "axi_dmac_pkg_sv.ttcl" +adi_ip_bd axi_dmac "bd/bd.tcl" + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_dmac} [ipx::current_core] + +adi_ip_add_core_dependencies [list \ + analog.com:$VIVADO_IP_LIBRARY:util_axis_fifo:1.0 \ + analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \ +] + +set_property display_name "ADI AXI DMA Controller" [ipx::current_core] +set_property description "ADI AXI DMA Controller" [ipx::current_core] + +adi_add_bus "s_axis" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"s_axis_ready" "TREADY"} \ + {"s_axis_valid" "TVALID"} \ + {"s_axis_data" "TDATA"} \ + {"s_axis_strb" "TSTRB"} \ + {"s_axis_keep" "TKEEP"} \ + {"s_axis_user" "TUSER"} \ + {"s_axis_id" "TID"} \ + {"s_axis_dest" "TDEST"} \ + {"s_axis_last" "TLAST"}] +adi_add_bus_clock "s_axis_aclk" "s_axis" + +adi_add_bus "m_axis" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"m_axis_ready" "TREADY"} \ + {"m_axis_valid" "TVALID"} \ + {"m_axis_data" "TDATA"} \ + {"m_axis_strb" "TSTRB"} \ + {"m_axis_keep" "TKEEP"} \ + {"m_axis_user" "TUSER"} \ + {"m_axis_id" "TID"} \ + {"m_axis_dest" "TDEST"} \ + {"m_axis_last" "TLAST"}] +adi_add_bus_clock "m_axis_aclk" "m_axis" + +adi_set_bus_dependency "m_src_axi" "m_src_axi" \ + "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_SRC')) = 0)" +adi_set_bus_dependency "m_dest_axi" "m_dest_axi" \ + "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 0)" +adi_set_bus_dependency "m_sg_axi" "m_sg_axi" \ + "(spirit:decode(id('MODELPARAM_VALUE.DMA_SG_TRANSFER')) = 1)" +adi_set_bus_dependency "s_axis" "s_axis" \ + "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_SRC')) = 1)" +adi_set_bus_dependency "m_axis" "m_axis" \ + "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 1)" +adi_set_ports_dependency "fifo_rd" \ + "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 2)" +adi_set_ports_dependency "dest_diag_level_bursts" \ + "(spirit:decode(id('MODELPARAM_VALUE.ENABLE_DIAGNOSTICS_IF')) = 1)" + +# These are in the design to keep the Intel tools happy which can't handle +# uni-directional AXI interfaces. The Xilinx tools can and do a better job when +# they know that the interface is uni-directional, so disable the ports. +set dummy_axi_ports [list \ + "m_dest_axi_arvalid" \ + "m_dest_axi_arready" \ + "m_dest_axi_araddr" \ + "m_dest_axi_arlen" \ + "m_dest_axi_arsize" \ + "m_dest_axi_arburst" \ + "m_dest_axi_arcache" \ + "m_dest_axi_arprot" \ + "m_dest_axi_rready" \ + "m_dest_axi_rvalid" \ + "m_dest_axi_rresp" \ + "m_dest_axi_rdata" \ + "m_src_axi_awvalid" \ + "m_src_axi_awready" \ + "m_src_axi_awaddr" \ + "m_src_axi_awlen" \ + "m_src_axi_awsize" \ + "m_src_axi_awburst" \ + "m_src_axi_awcache" \ + "m_src_axi_awprot" \ + "m_src_axi_wvalid" \ + "m_src_axi_wready" \ + "m_src_axi_wdata" \ + "m_src_axi_wstrb" \ + "m_src_axi_wlast" \ + "m_src_axi_bready" \ + "m_src_axi_bvalid" \ + "m_src_axi_bresp" \ + "m_sg_axi_awvalid" \ + "m_sg_axi_awready" \ + "m_sg_axi_awaddr" \ + "m_sg_axi_awlen" \ + "m_sg_axi_awsize" \ + "m_sg_axi_awburst" \ + "m_sg_axi_awcache" \ + "m_sg_axi_awprot" \ + "m_sg_axi_wvalid" \ + "m_sg_axi_wready" \ + "m_sg_axi_wdata" \ + "m_sg_axi_wstrb" \ + "m_sg_axi_wlast" \ + "m_sg_axi_bready" \ + "m_sg_axi_bvalid" \ + "m_sg_axi_bresp" \ +] + +# These are in the design to keep the Intel tools happy which require +# certain signals in AXI3 mode even if these are defined as optinal in the standard. +lappend dummy_axi_ports \ + "m_dest_axi_awid" \ + "m_dest_axi_awlock" \ + "m_dest_axi_wid" \ + "m_dest_axi_bid" \ + "m_dest_axi_arid" \ + "m_dest_axi_arlock" \ + "m_dest_axi_rid" \ + "m_dest_axi_rlast" \ + "m_src_axi_arid" \ + "m_src_axi_arlock" \ + "m_src_axi_rid" \ + "m_src_axi_awid" \ + "m_src_axi_awlock" \ + "m_src_axi_wid" \ + "m_src_axi_bid" \ + "m_sg_axi_arid" \ + "m_sg_axi_arlock" \ + "m_sg_axi_rid" \ + "m_sg_axi_awid" \ + "m_sg_axi_awlock" \ + "m_sg_axi_wid" \ + "m_sg_axi_bid" + + +foreach p $dummy_axi_ports { + adi_set_ports_dependency $p "false" +} + +set_property master_address_space_ref m_dest_axi \ + [ipx::get_bus_interfaces m_dest_axi \ + -of_objects [ipx::current_core]] +set_property master_address_space_ref m_src_axi \ + [ipx::get_bus_interfaces m_src_axi \ + -of_objects [ipx::current_core]] +set_property master_address_space_ref m_sg_axi \ + [ipx::get_bus_interfaces m_sg_axi \ + -of_objects [ipx::current_core]] + +adi_add_bus "fifo_wr" "slave" \ + "analog.com:interface:fifo_wr_rtl:1.0" \ + "analog.com:interface:fifo_wr:1.0" \ + { \ + {"fifo_wr_en" "EN"} \ + {"fifo_wr_din" "DATA"} \ + {"fifo_wr_overflow" "OVERFLOW"} \ + {"fifo_wr_sync" "SYNC"} \ + {"fifo_wr_xfer_req" "XFER_REQ"} \ + } + +adi_add_bus_clock "fifo_wr_clk" "fifo_wr" + +adi_set_bus_dependency "fifo_wr" "fifo_wr" \ + "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_SRC')) = 2)" + +adi_add_bus "fifo_rd" "slave" \ + "analog.com:interface:fifo_rd_rtl:1.0" \ + "analog.com:interface:fifo_rd:1.0" \ + { + {"fifo_rd_en" "EN"} \ + {"fifo_rd_dout" "DATA"} \ + {"fifo_rd_valid" "VALID"} \ + {"fifo_rd_underflow" "UNDERFLOW"} \ + } + +adi_add_bus_clock "fifo_rd_clk" "fifo_rd" + +adi_set_bus_dependency "fifo_rd" "fifo_rd" \ + "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE_DEST')) = 2)" + +foreach port {"m_dest_axi_aresetn" "m_src_axi_aresetn" "m_sg_axi_aresetn" \ + "s_axis_valid" "s_axis_data" "s_axis_last" "m_axis_ready" \ + "fifo_wr_en" "fifo_wr_din" "fifo_rd_en"} { + set_property DRIVER_VALUE "0" [ipx::get_ports $port] +} + +foreach port {"s_axis_user" "fifo_wr_sync"} { + set_property DRIVER_VALUE "1" [ipx::get_ports $port] +} + +# Infer interrupt +ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core] + +set cc [ipx::current_core] + +# The core does not issue narrow bursts +foreach intf [ipx::get_bus_interfaces m_*_axi -of_objects $cc] { + set para [ipx::add_bus_parameter SUPPORTS_NARROW_BURST $intf] + set_property "VALUE" "0" $para +} + +set_property -dict [list \ + "value_validation_type" "list" \ + "value_validation_list" "2 4 8 16 32" \ + ] \ + [ipx::get_user_parameters FIFO_SIZE -of_objects $cc] + +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "8" \ + "value_validation_range_maximum" "32" \ + ] \ + [ipx::get_user_parameters DMA_LENGTH_WIDTH -of_objects $cc] + +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "16" \ + "value_validation_range_maximum" "64" \ + ] \ + [ipx::get_user_parameters DMA_AXI_ADDR_WIDTH -of_objects $cc] + +foreach {k v} { \ + "ASYNC_CLK_REQ_SRC" "true" \ + "ASYNC_CLK_SRC_DEST" "true" \ + "ASYNC_CLK_DEST_REQ" "true" \ + "ASYNC_CLK_REQ_SG" "true" \ + "ASYNC_CLK_SRC_SG" "true" \ + "ASYNC_CLK_DEST_SG" "true" \ + "CYCLIC" "false" \ + "DMA_2D_TRANSFER" "false" \ + "DMA_SG_TRANSFER" "false" \ + "SYNC_TRANSFER_START" "false" \ + "AXI_SLICE_SRC" "false" \ + "AXI_SLICE_DEST" "false" \ + "DISABLE_DEBUG_REGISTERS" "false" \ + "ENABLE_DIAGNOSTICS_IF" "false" \ + "CACHE_COHERENT_DEST" "false" \ + } { \ + set_property -dict [list \ + "value_format" "bool" \ + "value" $v \ + ] \ + [ipx::get_user_parameters $k -of_objects $cc] + set_property -dict [list \ + "value_format" "bool" \ + "value" $v \ + ] \ + [ipx::get_hdl_parameters $k -of_objects $cc] +} + +foreach dir {"SRC" "DEST"} { + set_property -dict [list \ + "value_validation_type" "list" \ + "value_validation_list" "16 32 64 128 256 512 1024 2048" \ + ] \ + [ipx::get_user_parameters DMA_DATA_WIDTH_${dir} -of_objects $cc] + + set_property -dict [list \ + "value_validation_type" "pairs" \ + "value_validation_pairs" {"AXI3" "1" "AXI4" "0"} \ + "enablement_tcl_expr" "\$DMA_TYPE_${dir} == 0" \ + ] \ + [ipx::get_user_parameters DMA_AXI_PROTOCOL_${dir} -of_objects $cc] + + set_property -dict [list \ + "value_validation_type" "pairs" \ + "value_validation_pairs" { \ + "Memory-Mapped AXI" "0" \ + "Streaming AXI" "1" \ + "FIFO Interface" "2" \ + } \ + ] \ + [ipx::get_user_parameters DMA_TYPE_${dir} -of_objects $cc] +} + +set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] +set g [ipgui::add_group -name {DMA Endpoint Configuration} -component $cc \ + -parent $page0 -display_name {DMA Endpoint Configuration} \ + -layout "horizontal"] +set src_group [ipgui::add_group -name {Source} -component $cc -parent $g \ + -display_name {Source}] +set dest_group [ipgui::add_group -name {Destination} -component $cc -parent $g \ + -display_name {Destination}] +set sg_group [ipgui::add_group -name {Scatter-Gather} -component $cc -parent $g \ + -display_name {Scatter-Gather}] + +foreach {dir group} [list "SRC" $src_group "DEST" $dest_group] { + set p [ipgui::get_guiparamspec -name "DMA_TYPE_${dir}" -component $cc] + ipgui::move_param -component $cc -order 0 $p -parent $group + set_property -dict [list \ + "widget" "comboBox" \ + "display_name" "Type" \ + ] $p + + set p [ipgui::get_guiparamspec -name "DMA_AXI_PROTOCOL_${dir}" -component $cc] + ipgui::move_param -component $cc -order 1 $p -parent $group + set_property -dict [list \ + "widget" "comboBox" \ + "display_name" "AXI Protocol" \ + ] $p + + set p [ipgui::get_guiparamspec -name "DMA_DATA_WIDTH_${dir}" -component $cc] + ipgui::move_param -component $cc -order 2 $p -parent $group + set_property -dict [list \ + "display_name" "Bus Width" \ + "tooltip" "Bus Width: For Memory-Mapped interface the valid range is 32-1024 bits" \ + ] $p + + set p [ipgui::get_guiparamspec -name "AXI_SLICE_${dir}" -component $cc] + ipgui::move_param -component $cc -order 3 $p -parent $group + set_property -dict [list \ + "display_name" "Insert Register Slice" \ + ] $p +} + +set p [ipgui::get_guiparamspec -name "SYNC_TRANSFER_START" -component $cc] +ipgui::move_param -component $cc -order 4 $p -parent $src_group +set_property -dict [list \ + "display_name" "Transfer Start Synchronization Support" \ +] $p +set_property -dict [list \ + "enablement_tcl_expr" "\$DMA_TYPE_SRC != 0" \ +] [ipx::get_user_parameters SYNC_TRANSFER_START -of_objects $cc] + +set p [ipgui::get_guiparamspec -name "CACHE_COHERENT_DEST" -component $cc] +ipgui::move_param -component $cc -order 4 $p -parent $dest_group +set_property -dict [list \ + "tooltip" "Assume destination port ensures cache coherency (e.g. Ultrascale HPC port)" \ +] $p +set_property -dict [list \ + "display_name" "Assume cache coherent" \ + "enablement_tcl_expr" "\$DMA_TYPE_DEST == 0 && \$DMA_AXI_PROTOCOL_DEST == 0" \ + "value_tcl_expr" "\$DMA_TYPE_DEST == 0 && \$DMA_AXI_PROTOCOL_DEST == 0" \ + "enablement_value" "false" \ +] [ipx::get_user_parameters CACHE_COHERENT_DEST -of_objects $cc] + +set p [ipgui::get_guiparamspec -name "DMA_AXI_PROTOCOL_SG" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $sg_group +set_property -dict [list \ + "display_name" "AXI Protocol" \ +] $p +set_property -dict [list \ + "enablement_tcl_expr" "\$DMA_SG_TRANSFER == true" \ +] [ipx::get_user_parameters DMA_AXI_PROTOCOL_SG -of_objects $cc] +set_property -dict [list \ + "value_validation_type" "pairs" \ + "value_validation_pairs" {"AXI3" "1" "AXI4" "0"} \ +] [ipx::get_user_parameters DMA_AXI_PROTOCOL_SG -of_objects $cc] + +set p [ipgui::get_guiparamspec -name "DMA_DATA_WIDTH_SG" -component $cc] +ipgui::move_param -component $cc -order 1 $p -parent $sg_group +set_property -dict [list \ + "display_name" "Bus Width" \ +] $p +set_property -dict [list \ + "enablement_tcl_expr" "\$DMA_SG_TRANSFER == true" \ +] [ipx::get_user_parameters DMA_DATA_WIDTH_SG -of_objects $cc] +set_property -dict [list \ + "value_validation_type" "list" \ + "value_validation_list" "64" \ +] [ipx::get_user_parameters DMA_DATA_WIDTH_SG -of_objects $cc] + +set general_group [ipgui::add_group -name "General Configuration" -component $cc \ + -parent $page0 -display_name "General Configuration"] + +set p [ipgui::get_guiparamspec -name "ID" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $general_group +set_property -dict [list \ + "display_name" "Core ID" \ +] $p + +set p [ipgui::get_guiparamspec -name "DMA_LENGTH_WIDTH" -component $cc] +ipgui::move_param -component $cc -order 1 $p -parent $general_group +set_property -dict [list \ + "display_name" "DMA Transfer Length Register Width" \ +] $p + +set p [ipgui::get_guiparamspec -name "FIFO_SIZE" -component $cc] +ipgui::move_param -component $cc -order 2 $p -parent $general_group +set_property -dict [list \ + "widget" "comboBox" \ + "display_name" "Store-and-Forward Memory Size (In Bursts)" \ +] $p + +set p [ipgui::get_guiparamspec -name "MAX_BYTES_PER_BURST" -component $cc] +ipgui::move_param -component $cc -order 3 $p -parent $general_group +set_property -dict [list \ + "display_name" "Maximum Bytes per Burst" \ +] $p + +set p [ipgui::get_guiparamspec -name "DMA_AXI_ADDR_WIDTH" -component $cc] +ipgui::move_param -component $cc -order 4 $p -parent $general_group +set_property -dict [list \ + "display_name" "DMA AXI Address Width" \ +] $p + +set feature_group [ipgui::add_group -name "Features" -component $cc \ + -parent $page0 -display_name "Features"] + +set p [ipgui::get_guiparamspec -name "CYCLIC" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $feature_group +set_property -dict [list \ + "display_name" "Cyclic Transfer Support" \ +] $p + +set p [ipgui::get_guiparamspec -name "DMA_2D_TRANSFER" -component $cc] +ipgui::move_param -component $cc -order 1 $p -parent $feature_group +set_property -dict [list \ + "display_name" "2D Transfer Support" \ +] $p + +set p [ipgui::get_guiparamspec -name "DMA_SG_TRANSFER" -component $cc] +ipgui::move_param -component $cc -order 2 $p -parent $feature_group +set_property -dict [list \ + "display_name" "SG Transfer Support" \ +] $p + +set clk_group [ipgui::add_group -name {Clock Domain Configuration} -component $cc \ + -parent $page0 -display_name {Clock Domain Configuration}] + +set p [ipgui::get_guiparamspec -name "ASYNC_CLK_REQ_SRC" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $clk_group +set_property -dict [list \ + "display_name" "Request and Source Clock Asynchronous" \ +] $p + +set p [ipgui::get_guiparamspec -name "ASYNC_CLK_SRC_DEST" -component $cc] +ipgui::move_param -component $cc -order 1 $p -parent $clk_group +set_property -dict [list \ + "display_name" "Source and Destination Clock Asynchronous" \ +] $p + +set p [ipgui::get_guiparamspec -name "ASYNC_CLK_DEST_REQ" -component $cc] +ipgui::move_param -component $cc -order 2 $p -parent $clk_group +set_property -dict [list \ + "display_name" "Destination and Request Clock Asynchronous" \ +] $p + +set p [ipgui::get_guiparamspec -name "ASYNC_CLK_REQ_SG" -component $cc] +ipgui::move_param -component $cc -order 3 $p -parent $clk_group +set_property -dict [list \ + "display_name" "Request and Scatter-Gather Clock Asynchronous" \ +] $p + +set p [ipgui::get_guiparamspec -name "ASYNC_CLK_SRC_SG" -component $cc] +ipgui::move_param -component $cc -order 4 $p -parent $clk_group +set_property -dict [list \ + "display_name" "Source and Scatter-Gather Clock Asynchronous" \ +] $p + +set p [ipgui::get_guiparamspec -name "ASYNC_CLK_DEST_SG" -component $cc] +ipgui::move_param -component $cc -order 5 $p -parent $clk_group +set_property -dict [list \ + "display_name" "Destination and Scatter-Gather Clock Asynchronous" \ +] $p + +set dbg_group [ipgui::add_group -name {Debug} -component $cc \ + -parent $page0 -display_name {Debug}] + +set p [ipgui::get_guiparamspec -name "DISABLE_DEBUG_REGISTERS" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $dbg_group +set_property -dict [list \ + "display_name" "Disable Debug Registers" \ +] $p + +set p [ipgui::get_guiparamspec -name "ENABLE_DIAGNOSTICS_IF" -component $cc] +ipgui::move_param -component $cc -order 1 $p -parent $dbg_group +set_property -dict [list \ + "display_name" "Enable Diagnostics Interface" \ +] $p + +ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "AXI_ID_WIDTH_SRC" -component $cc] +ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "AXI_ID_WIDTH_DEST" -component $cc] +ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "AXI_ID_WIDTH_SG" -component $cc] +ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "ALLOW_ASYM_MEM" -component $cc] +ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DMA_AXIS_ID_W" -component $cc] +ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DMA_AXIS_DEST_W" -component $cc] + +ipx::create_xgui_files [ipx::current_core] +ipx::save_core $cc diff --git a/adi_library/axi_dmac/axi_dmac_pkg_sv.ttcl b/adi_library/axi_dmac/axi_dmac_pkg_sv.ttcl new file mode 100644 index 00000000..2b09bcd3 --- /dev/null +++ b/adi_library/axi_dmac/axi_dmac_pkg_sv.ttcl @@ -0,0 +1,83 @@ +############################################################################### +## Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +# SPDX short identifier: ADIBSD +############################################################################### + +<: :> +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./sim/" :> +<: setFileName ${ComponentName}_pkg :> +<: setFileExtension ".sv" :> +<: set id [get_property MODELPARAM_VALUE.ID] :> +<: set dma_data_width_src [get_property MODELPARAM_VALUE.DMA_DATA_WIDTH_SRC] :> +<: set dma_data_width_dest [get_property MODELPARAM_VALUE.DMA_DATA_WIDTH_DEST] :> +<: set dma_data_width_sg [get_property MODELPARAM_VALUE.DMA_DATA_WIDTH_SG] :> +<: set dma_length_width [get_property MODELPARAM_VALUE.DMA_LENGTH_WIDTH] :> +<: set dma_2d_transfer [get_property MODELPARAM_VALUE.DMA_2D_TRANSFER] :> +<: set dma_sg_transfer [get_property MODELPARAM_VALUE.DMA_SG_TRANSFER] :> +<: set async_clk_req_src [get_property MODELPARAM_VALUE.ASYNC_CLK_REQ_SRC] :> +<: set async_clk_src_dest [get_property MODELPARAM_VALUE.ASYNC_CLK_SRC_DEST] :> +<: set async_clk_dest_req [get_property MODELPARAM_VALUE.ASYNC_CLK_DEST_REQ] :> +<: set async_clk_req_sg [get_property MODELPARAM_VALUE.ASYNC_CLK_REQ_SG] :> +<: set async_clk_src_sg [get_property MODELPARAM_VALUE.ASYNC_CLK_SRC_SG] :> +<: set async_clk_dest_sg [get_property MODELPARAM_VALUE.ASYNC_CLK_DEST_SG] :> +<: set axi_slice_dest [get_property MODELPARAM_VALUE.AXI_SLICE_DEST] :> +<: set axi_slice_src [get_property MODELPARAM_VALUE.AXI_SLICE_SRC] :> +<: set sync_transfer_start [get_property MODELPARAM_VALUE.SYNC_TRANSFER_START] :> +<: set cyclic [get_property MODELPARAM_VALUE.CYCLIC] :> +<: set dma_axi_protocol_dest [get_property MODELPARAM_VALUE.DMA_AXI_PROTOCOL_DEST] :> +<: set dma_axi_protocol_src [get_property MODELPARAM_VALUE.DMA_AXI_PROTOCOL_SRC] :> +<: set dma_axi_protocol_sg [get_property MODELPARAM_VALUE.DMA_AXI_PROTOCOL_SG] :> +<: set dma_type_dest [get_property MODELPARAM_VALUE.DMA_TYPE_DEST] :> +<: set dma_type_src [get_property MODELPARAM_VALUE.DMA_TYPE_SRC] :> +<: set dma_axi_addr_width [get_property MODELPARAM_VALUE.DMA_AXI_ADDR_WIDTH] :> +<: set max_bytes_per_burst [get_property MODELPARAM_VALUE.MAX_BYTES_PER_BURST] :> +<: set fifo_size [get_property MODELPARAM_VALUE.FIFO_SIZE] :> +<: set axi_id_width_src [get_property MODELPARAM_VALUE.AXI_ID_WIDTH_SRC] :> +<: set axi_id_width_dest [get_property MODELPARAM_VALUE.AXI_ID_WIDTH_DEST] :> +<: set axi_id_width_sg [get_property MODELPARAM_VALUE.AXI_ID_WIDTH_SG] :> +<: set disable_debug_registers [get_property MODELPARAM_VALUE.DISABLE_DEBUG_REGISTERS] :> + +<: proc b2i {b} { if {$b==true} {return 1} else {return 0}} :> +/////////////////////////////////////////////////////////////////////////// +//NOTE: This file has been automatically generated by Vivado. +/////////////////////////////////////////////////////////////////////////// + +package <=: ComponentName :>_pkg; + +/////////////////////////////////////////////////////////////////////////// +// These parameters are named after the component for use in your verification +// environment. +/////////////////////////////////////////////////////////////////////////// + parameter <=: ComponentName :>_ID = <=: $id :>; + parameter <=: ComponentName :>_DMA_DATA_WIDTH_SRC = <=: $dma_data_width_src :>; + parameter <=: ComponentName :>_DMA_DATA_WIDTH_DEST = <=: $dma_data_width_dest :>; + parameter <=: ComponentName :>_DMA_DATA_WIDTH_SG = <=: $dma_data_width_sg :>; + parameter <=: ComponentName :>_DMA_LENGTH_WIDTH = <=: $dma_length_width :>; + parameter <=: ComponentName :>_DMA_2D_TRANSFER = <=: b2i $dma_2d_transfer :>; + parameter <=: ComponentName :>_DMA_SG_TRANSFER = <=: b2i $dma_sg_transfer :>; + parameter <=: ComponentName :>_ASYNC_CLK_REQ_SRC = <=: b2i $async_clk_req_src :>; + parameter <=: ComponentName :>_ASYNC_CLK_SRC_DEST = <=: b2i $async_clk_src_dest :>; + parameter <=: ComponentName :>_ASYNC_CLK_DEST_REQ = <=: b2i $async_clk_dest_req :>; + parameter <=: ComponentName :>_ASYNC_CLK_REQ_SG = <=: b2i $async_clk_req_sg :>; + parameter <=: ComponentName :>_ASYNC_CLK_SRC_SG = <=: b2i $async_clk_src_sg :>; + parameter <=: ComponentName :>_ASYNC_CLK_DEST_SG = <=: b2i $async_clk_dest_sg :>; + parameter <=: ComponentName :>_AXI_SLICE_DEST = <=: b2i $axi_slice_dest :>; + parameter <=: ComponentName :>_AXI_SLICE_SRC = <=: b2i $axi_slice_src :>; + parameter <=: ComponentName :>_SYNC_TRANSFER_START = <=: b2i $sync_transfer_start :>; + parameter <=: ComponentName :>_CYCLIC = <=: b2i $cyclic :>; + parameter <=: ComponentName :>_DMA_AXI_PROTOCOL_DEST = <=: $dma_axi_protocol_dest :>; + parameter <=: ComponentName :>_DMA_AXI_PROTOCOL_SRC = <=: $dma_axi_protocol_src :>; + parameter <=: ComponentName :>_DMA_AXI_PROTOCOL_SG = <=: $dma_axi_protocol_sg :>; + parameter <=: ComponentName :>_DMA_TYPE_DEST = <=: $dma_type_dest :>; + parameter <=: ComponentName :>_DMA_TYPE_SRC = <=: $dma_type_src :>; + parameter <=: ComponentName :>_DMA_AXI_ADDR_WIDTH = <=: $dma_axi_addr_width :>; + parameter <=: ComponentName :>_MAX_BYTES_PER_BURST = <=: $max_bytes_per_burst :>; + parameter <=: ComponentName :>_FIFO_SIZE = <=: $fifo_size :>; + parameter <=: ComponentName :>_AXI_ID_WIDTH_SRC = <=: $axi_id_width_src :>; + parameter <=: ComponentName :>_AXI_ID_WIDTH_DEST = <=: $axi_id_width_dest :>; + parameter <=: ComponentName :>_AXI_ID_WIDTH_SG = <=: $axi_id_width_sg :>; + parameter <=: ComponentName :>_DISABLE_DEBUG_REGISTERS = <=: b2i $disable_debug_registers :>; +////////////////////////////////////////////////////////////////////////// + +endpackage : <=: ComponentName :>_pkg diff --git a/adi_library/axi_dmac/axi_dmac_regmap.v b/adi_library/axi_dmac/axi_dmac_regmap.v new file mode 100644 index 00000000..19c264c7 --- /dev/null +++ b/adi_library/axi_dmac/axi_dmac_regmap.v @@ -0,0 +1,325 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dmac_regmap #( + parameter ID = 0, + parameter DISABLE_DEBUG_REGISTERS = 0, + parameter BYTES_PER_BEAT_WIDTH_DEST = 1, + parameter BYTES_PER_BEAT_WIDTH_SRC = 1, + parameter BYTES_PER_BEAT_WIDTH_SG = 1, + parameter BYTES_PER_BURST_WIDTH = 7, + parameter DMA_TYPE_DEST = 0, + parameter DMA_TYPE_SRC = 2, + parameter DMA_AXI_ADDR_WIDTH = 32, + parameter DMA_LENGTH_WIDTH = 24, + parameter DMA_LENGTH_ALIGN = 3, + parameter DMA_CYCLIC = 0, + parameter HAS_DEST_ADDR = 1, + parameter HAS_SRC_ADDR = 1, + parameter DMA_2D_TRANSFER = 0, + parameter DMA_SG_TRANSFER = 0, + parameter SYNC_TRANSFER_START = 0, + parameter CACHE_COHERENT_DEST = 0 +) ( + + // Slave AXI interface + input s_axi_aclk, + input s_axi_aresetn, + + input s_axi_awvalid, + output s_axi_awready, + input [10:0] s_axi_awaddr, + input [2:0] s_axi_awprot, + + input s_axi_wvalid, + output s_axi_wready, + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + + output s_axi_bvalid, + input s_axi_bready, + output [1:0] s_axi_bresp, + + input s_axi_arvalid, + output s_axi_arready, + input [10:0] s_axi_araddr, + input [2:0] s_axi_arprot, + + output s_axi_rvalid, + input s_axi_rready, + output [1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + + // Interrupt + output reg irq, + + // Control interface + output reg ctrl_enable = 1'b0, + output reg ctrl_pause = 1'b0, + output reg ctrl_hwdesc = 1'b0, + + // DMA request interface + output request_valid, + input request_ready, + output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] request_dest_address, + output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] request_src_address, + output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SG] request_sg_address, + output [DMA_LENGTH_WIDTH-1:0] request_x_length, + output [DMA_LENGTH_WIDTH-1:0] request_y_length, + output [DMA_LENGTH_WIDTH-1:0] request_dest_stride, + output [DMA_LENGTH_WIDTH-1:0] request_src_stride, + output request_sync_transfer_start, + output request_last, + + // DMA response interface + input response_eot, + input [31:0] response_sg_desc_id, + input [BYTES_PER_BURST_WIDTH-1:0] response_measured_burst_length, + input response_partial, + input response_valid, + output response_ready, + + // Debug interface + input [DMA_AXI_ADDR_WIDTH-1:0] dbg_src_addr, + input [DMA_AXI_ADDR_WIDTH-1:0] dbg_dest_addr, + input [11:0] dbg_status, + input [31:0] dbg_ids0, + input [31:0] dbg_ids1 +); + + localparam PCORE_VERSION = 'h00040561; + localparam HAS_ADDR_HIGH = DMA_AXI_ADDR_WIDTH > 32; + localparam ADDR_LOW_MSB = HAS_ADDR_HIGH ? 31 : DMA_AXI_ADDR_WIDTH-1; + + // Register interface signals + reg [31:0] up_rdata = 32'h00; + reg up_wack = 1'b0; + reg up_rack = 1'b0; + + wire up_wreq; + wire up_rreq; + wire [31:0] up_wdata; + wire [8:0] up_waddr; + wire [8:0] up_raddr; + wire [31:0] up_rdata_request; + + // Scratch register + reg [31:0] up_scratch = 32'h00; + + // Start and end of transfer + wire up_eot; // Asserted for one cycle when a transfer has been completed + wire up_sot; // Asserted for one cycle when a transfer has been queued + + // Interupt handling + reg [1:0] up_irq_mask = 2'h3; + reg [1:0] up_irq_source = 2'h0; + + wire [1:0] up_irq_pending; + wire [1:0] up_irq_trigger; + wire [1:0] up_irq_source_clear; + + // IRQ handling + assign up_irq_pending = ~up_irq_mask & up_irq_source; + assign up_irq_trigger = {up_eot, up_sot}; + assign up_irq_source_clear = (up_wreq == 1'b1 && up_waddr == 9'h021) ? up_wdata[1:0] : 2'b00; + + always @(posedge s_axi_aclk) begin + if (s_axi_aresetn == 1'b0) begin + irq <= 1'b0; + end else begin + irq <= |up_irq_pending; + end + end + + always @(posedge s_axi_aclk) begin + if (s_axi_aresetn == 1'b0) begin + up_irq_source <= 2'b00; + end else begin + up_irq_source <= up_irq_trigger | (up_irq_source & ~up_irq_source_clear); + end + end + + // Register Interface + + always @(posedge s_axi_aclk) begin + if (s_axi_aresetn == 1'b0) begin + ctrl_enable <= 1'b0; + ctrl_pause <= 1'b0; + ctrl_hwdesc <= 1'b0; + up_irq_mask <= 2'b11; + up_scratch <= 32'h00; + up_wack <= 1'b0; + end else begin + up_wack <= up_wreq; + + if (up_wreq == 1'b1) begin + case (up_waddr) + 9'h002: begin + up_scratch <= up_wdata; + end + 9'h020: begin + up_irq_mask <= up_wdata[1:0]; + end + 9'h100: begin + ctrl_hwdesc <= up_wdata[2] & DMA_SG_TRANSFER; + ctrl_pause <= up_wdata[1]; + ctrl_enable <= up_wdata[0]; + end + endcase + end + end + end + + always @(posedge s_axi_aclk) begin + if (s_axi_aresetn == 1'b0) begin + up_rack <= 'd0; + end else begin + up_rack <= up_rreq; + end + end + + always @(posedge s_axi_aclk) begin + if (up_rreq == 1'b1) begin + case (up_raddr) + 9'h000: up_rdata <= PCORE_VERSION; + 9'h001: up_rdata <= ID; + 9'h002: up_rdata <= up_scratch; + 9'h003: up_rdata <= 32'h444d4143; // "DMAC" + 9'h004: up_rdata <= {8'b0, + 4'b0,BYTES_PER_BURST_WIDTH[3:0], + 2'b0,DMA_TYPE_SRC[1:0],BYTES_PER_BEAT_WIDTH_SRC[3:0], + 2'b0,DMA_TYPE_DEST[1:0],BYTES_PER_BEAT_WIDTH_DEST[3:0]}; + 9'h005: up_rdata <= {31'd0, CACHE_COHERENT_DEST}; + 9'h020: up_rdata <= up_irq_mask; + 9'h021: up_rdata <= up_irq_pending; + 9'h022: up_rdata <= up_irq_source; + 9'h100: up_rdata <= {ctrl_hwdesc, ctrl_pause, ctrl_enable}; + 9'h10d: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_dest_addr[ADDR_LOW_MSB:0]; + 9'h10e: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_src_addr[ADDR_LOW_MSB:0]; + 9'h10f: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_status; + 9'h110: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_ids0; + 9'h111: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_ids1; + 9'h126: up_rdata <= (HAS_ADDR_HIGH && !DISABLE_DEBUG_REGISTERS) ? dbg_dest_addr[DMA_AXI_ADDR_WIDTH-1:32] : 32'h00; + 9'h127: up_rdata <= (HAS_ADDR_HIGH && !DISABLE_DEBUG_REGISTERS) ? dbg_src_addr[DMA_AXI_ADDR_WIDTH-1:32] : 32'h00; + default: up_rdata <= up_rdata_request; + endcase + end + end + + axi_dmac_regmap_request #( + .DISABLE_DEBUG_REGISTERS(DISABLE_DEBUG_REGISTERS), + .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST), + .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC), + .BYTES_PER_BEAT_WIDTH_SG(BYTES_PER_BEAT_WIDTH_SG), + .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH), + .DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH), + .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH), + .DMA_LENGTH_ALIGN(DMA_LENGTH_ALIGN), + .DMA_CYCLIC(DMA_CYCLIC), + .HAS_DEST_ADDR(HAS_DEST_ADDR), + .HAS_SRC_ADDR(HAS_SRC_ADDR), + .DMA_2D_TRANSFER(DMA_2D_TRANSFER), + .DMA_SG_TRANSFER(DMA_SG_TRANSFER), + .SYNC_TRANSFER_START(SYNC_TRANSFER_START) + ) i_regmap_request ( + .clk(s_axi_aclk), + .reset(~s_axi_aresetn), + + .up_sot(up_sot), + .up_eot(up_eot), + + .up_wreq(up_wreq), + .up_rreq(up_rreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_raddr(up_raddr), + .up_rdata(up_rdata_request), + + .ctrl_enable(ctrl_enable), + .ctrl_hwdesc(ctrl_hwdesc), + + .request_valid(request_valid), + .request_ready(request_ready), + .request_dest_address(request_dest_address), + .request_src_address(request_src_address), + .request_sg_address(request_sg_address), + .request_x_length(request_x_length), + .request_y_length(request_y_length), + .request_dest_stride(request_dest_stride), + .request_src_stride(request_src_stride), + .request_sync_transfer_start(request_sync_transfer_start), + .request_last(request_last), + + .response_eot(response_eot), + .response_sg_desc_id(response_sg_desc_id), + .response_measured_burst_length(response_measured_burst_length), + .response_partial(response_partial), + .response_valid(response_valid), + .response_ready(response_ready)); + + up_axi #( + .AXI_ADDRESS_WIDTH (11) + ) i_up_axi ( + .up_rstn(s_axi_aresetn), + .up_clk(s_axi_aclk), + .up_axi_awvalid(s_axi_awvalid), + .up_axi_awaddr(s_axi_awaddr), + .up_axi_awready(s_axi_awready), + .up_axi_wvalid(s_axi_wvalid), + .up_axi_wdata(s_axi_wdata), + .up_axi_wstrb(s_axi_wstrb), + .up_axi_wready(s_axi_wready), + .up_axi_bvalid(s_axi_bvalid), + .up_axi_bresp(s_axi_bresp), + .up_axi_bready(s_axi_bready), + .up_axi_arvalid(s_axi_arvalid), + .up_axi_araddr(s_axi_araddr), + .up_axi_arready(s_axi_arready), + .up_axi_rvalid(s_axi_rvalid), + .up_axi_rresp(s_axi_rresp), + .up_axi_rdata(s_axi_rdata), + .up_axi_rready(s_axi_rready), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_wack(up_wack), + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata), + .up_rack(up_rack)); + +endmodule diff --git a/adi_library/axi_dmac/axi_dmac_regmap_request.v b/adi_library/axi_dmac/axi_dmac_regmap_request.v new file mode 100644 index 00000000..6f1c491a --- /dev/null +++ b/adi_library/axi_dmac/axi_dmac_regmap_request.v @@ -0,0 +1,356 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dmac_regmap_request #( + parameter DISABLE_DEBUG_REGISTERS = 0, + parameter BYTES_PER_BEAT_WIDTH_DEST = 1, + parameter BYTES_PER_BEAT_WIDTH_SRC = 1, + parameter BYTES_PER_BEAT_WIDTH_SG = 1, + parameter BYTES_PER_BURST_WIDTH = 7, + parameter DMA_AXI_ADDR_WIDTH = 32, + parameter DMA_LENGTH_WIDTH = 24, + parameter DMA_LENGTH_ALIGN = 3, + parameter DMA_CYCLIC = 0, + parameter HAS_DEST_ADDR = 1, + parameter HAS_SRC_ADDR = 1, + parameter DMA_2D_TRANSFER = 0, + parameter DMA_SG_TRANSFER = 0, + parameter SYNC_TRANSFER_START = 0 +) ( + input clk, + input reset, + + // Interrupts + output up_sot, + output up_eot, + + // Register map interface + input up_wreq, + input up_rreq, + input [8:0] up_waddr, + input [31:0] up_wdata, + input [8:0] up_raddr, + output reg [31:0] up_rdata, + + // Control interface + input ctrl_enable, + input ctrl_hwdesc, + + // DMA request interface + output request_valid, + input request_ready, + output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] request_dest_address, + output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] request_src_address, + output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SG] request_sg_address, + output [DMA_LENGTH_WIDTH-1:0] request_x_length, + output [DMA_LENGTH_WIDTH-1:0] request_y_length, + output [DMA_LENGTH_WIDTH-1:0] request_dest_stride, + output [DMA_LENGTH_WIDTH-1:0] request_src_stride, + output request_sync_transfer_start, + output request_last, + + // DMA response interface + input response_eot, + input [31:0] response_sg_desc_id, + input [BYTES_PER_BURST_WIDTH-1:0] response_measured_burst_length, + input response_partial, + input response_valid, + output reg response_ready = 1'b1 +); + + localparam MEASURED_LENGTH_WIDTH = DMA_2D_TRANSFER ? 32 : DMA_LENGTH_WIDTH; + localparam HAS_ADDR_HIGH = DMA_AXI_ADDR_WIDTH > 32; + localparam ADDR_LOW_MSB = HAS_ADDR_HIGH ? 31 : DMA_AXI_ADDR_WIDTH-1; + localparam ADDR_HIGH_MSB = HAS_ADDR_HIGH ? DMA_AXI_ADDR_WIDTH-32-1 : 0; + + // DMA transfer signals + reg up_dma_req_valid = 1'b0; + wire up_dma_req_ready; + + reg [1:0] up_transfer_id = 2'b0; + reg [1:0] up_transfer_id_eot = 2'b0; + reg [3:0] up_transfer_done_bitmap = 4'b0; + + reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] up_dma_dest_address = 'h00; + reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] up_dma_src_address = 'h00; + reg [DMA_LENGTH_WIDTH-1:0] up_dma_x_length = {DMA_LENGTH_ALIGN{1'b1}}; + reg up_dma_cyclic = DMA_CYCLIC ? 1'b1 : 1'b0; + reg up_dma_last = 1'b1; + reg up_dma_enable_tlen_reporting = 1'b0; + + wire up_tlf_s_ready; + reg up_tlf_s_valid = 1'b0; + + wire [MEASURED_LENGTH_WIDTH+2-1:0] up_tlf_data; + wire up_tlf_valid; + wire up_tlf_rd; + reg up_partial_length_valid = 1'b0; + + reg [MEASURED_LENGTH_WIDTH-1:0] up_measured_transfer_length = 'h0; + reg up_clear_tl = 1'b0; + reg [1:0] up_transfer_id_eot_d = 'h0; + wire up_bl_partial; + + assign request_dest_address = up_dma_dest_address; + assign request_src_address = up_dma_src_address; + assign request_x_length = up_dma_x_length; + assign request_sync_transfer_start = SYNC_TRANSFER_START ? 1'b1 : 1'b0; + assign request_last = up_dma_last; + + always @(posedge clk) begin + if (reset == 1'b1) begin + up_dma_dest_address <= 'h00; + up_dma_src_address <= 'h00; + up_dma_x_length[DMA_LENGTH_WIDTH-1:DMA_LENGTH_ALIGN] <= 'h00; + up_dma_req_valid <= 1'b0; + up_dma_cyclic <= DMA_CYCLIC ? 1'b1 : 1'b0; + up_dma_last <= 1'b1; + up_dma_enable_tlen_reporting <= 1'b0; + end else begin + if (ctrl_enable == 1'b1) begin + if (up_wreq == 1'b1 && up_waddr == 9'h102) begin + up_dma_req_valid <= up_dma_req_valid | up_wdata[0]; + end else if (up_sot == 1'b1) begin + up_dma_req_valid <= 1'b0; + end + end else begin + up_dma_req_valid <= 1'b0; + end + + if (up_wreq == 1'b1) begin + case (up_waddr) + 9'h103: begin + if (DMA_CYCLIC) up_dma_cyclic <= up_wdata[0]; + up_dma_last <= up_wdata[1]; + up_dma_enable_tlen_reporting <= up_wdata[2]; + end + 9'h104: up_dma_dest_address[ADDR_LOW_MSB:BYTES_PER_BEAT_WIDTH_DEST] <= up_wdata[ADDR_LOW_MSB:BYTES_PER_BEAT_WIDTH_DEST]; + 9'h105: up_dma_src_address[ADDR_LOW_MSB:BYTES_PER_BEAT_WIDTH_SRC] <= up_wdata[ADDR_LOW_MSB:BYTES_PER_BEAT_WIDTH_SRC]; + 9'h106: up_dma_x_length[DMA_LENGTH_WIDTH-1:DMA_LENGTH_ALIGN] <= up_wdata[DMA_LENGTH_WIDTH-1:DMA_LENGTH_ALIGN]; + 9'h124: + if (HAS_ADDR_HIGH) begin + up_dma_dest_address[DMA_AXI_ADDR_WIDTH-1:32] <= up_wdata[ADDR_HIGH_MSB:0]; + end + 9'h125: + if (HAS_ADDR_HIGH) begin + up_dma_src_address[DMA_AXI_ADDR_WIDTH-1:32] <= up_wdata[ADDR_HIGH_MSB:0]; + end + endcase + end + end + end + + always @(*) begin + case (up_raddr) + 9'h101: up_rdata <= up_transfer_id; + 9'h102: up_rdata <= up_dma_req_valid; + 9'h103: up_rdata <= {29'h00, up_dma_enable_tlen_reporting, up_dma_last, up_dma_cyclic}; // Flags + 9'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address[ADDR_LOW_MSB:BYTES_PER_BEAT_WIDTH_DEST],{BYTES_PER_BEAT_WIDTH_DEST{1'b0}}} : 'h00; + 9'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address[ADDR_LOW_MSB:BYTES_PER_BEAT_WIDTH_SRC],{BYTES_PER_BEAT_WIDTH_SRC{1'b0}}} : 'h00; + 9'h106: up_rdata <= up_dma_x_length; + 9'h107: up_rdata <= request_y_length; + 9'h108: up_rdata <= request_dest_stride; + 9'h109: up_rdata <= request_src_stride; + 9'h10a: up_rdata <= {up_partial_length_valid,27'b0,up_transfer_done_bitmap}; + 9'h10b: up_rdata <= up_transfer_id_eot; + 9'h10c: up_rdata <= 32'h0; + 9'h112: up_rdata <= up_measured_transfer_length; + 9'h113: up_rdata <= up_tlf_data[MEASURED_LENGTH_WIDTH-1 : 0]; // Length + 9'h114: up_rdata <= up_tlf_data[MEASURED_LENGTH_WIDTH+: 2]; // ID + 9'h115: up_rdata <= response_sg_desc_id; + 9'h11f: up_rdata <= {request_sg_address[ADDR_LOW_MSB:BYTES_PER_BEAT_WIDTH_SG],{BYTES_PER_BEAT_WIDTH_SG{1'b0}}}; + 9'h124: up_rdata <= (HAS_ADDR_HIGH && HAS_DEST_ADDR) ? up_dma_dest_address[DMA_AXI_ADDR_WIDTH-1:32] : 32'h00; + 9'h125: up_rdata <= (HAS_ADDR_HIGH && HAS_SRC_ADDR) ? up_dma_src_address[DMA_AXI_ADDR_WIDTH-1:32] : 32'h00; + 9'h12f: up_rdata <= HAS_ADDR_HIGH ? request_sg_address[DMA_AXI_ADDR_WIDTH-1:32] : 32'h00; + default: up_rdata <= 32'h00; + endcase + end + + generate + if (DMA_2D_TRANSFER == 1) begin + reg [DMA_LENGTH_WIDTH-1:0] up_dma_y_length = 'h00; + reg [DMA_LENGTH_WIDTH-1:0] up_dma_src_stride = 'h00; + reg [DMA_LENGTH_WIDTH-1:0] up_dma_dest_stride = 'h00; + + always @(posedge clk) begin + if (reset == 1'b1) begin + up_dma_y_length <= 'h00; + up_dma_dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] <= 'h00; + up_dma_src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] <= 'h00; + end else if (up_wreq == 1'b1) begin + case (up_waddr) + 9'h107: up_dma_y_length <= up_wdata[DMA_LENGTH_WIDTH-1:0]; + 9'h108: up_dma_dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] <= up_wdata[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST]; + 9'h109: up_dma_src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] <= up_wdata[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC]; + endcase + end + end + assign request_y_length = up_dma_y_length; + assign request_dest_stride = up_dma_dest_stride; + assign request_src_stride = up_dma_src_stride; + end else begin + assign request_y_length = 'h0; + assign request_dest_stride = 'h0; + assign request_src_stride = 'h0; + end + endgenerate + + generate + if (DMA_SG_TRANSFER == 1) begin + reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SG] up_dma_sg_address = 'h00; + + always @(posedge clk) begin + if (reset == 1'b1) begin + up_dma_sg_address <= 'h00; + end else if (up_wreq == 1'b1) begin + case (up_waddr) + 9'h11f: up_dma_sg_address[ADDR_LOW_MSB:BYTES_PER_BEAT_WIDTH_SG] <= up_wdata[ADDR_LOW_MSB:BYTES_PER_BEAT_WIDTH_SG]; + 9'h12f: + if (HAS_ADDR_HIGH) begin + up_dma_sg_address[DMA_AXI_ADDR_WIDTH-1:32] <= up_wdata[ADDR_HIGH_MSB:0]; + end + endcase + end + end + assign request_sg_address = up_dma_sg_address; + end else begin + assign request_sg_address = 'h00; + end + endgenerate + + // In cyclic mode the same transfer is submitted over and over again + assign up_sot = (up_dma_cyclic && !ctrl_hwdesc) ? 1'b0 : up_dma_req_valid & up_dma_req_ready; + assign up_eot = (up_dma_cyclic && !ctrl_hwdesc) ? 1'b0 : response_eot & response_valid & response_ready; + + assign request_valid = up_dma_req_valid; + assign up_dma_req_ready = request_ready; + + // Request ID and Request done bitmap handling + always @(posedge clk) begin + if (ctrl_enable == 1'b0) begin + up_transfer_id <= 2'h0; + up_transfer_id_eot <= 2'h0; + up_transfer_done_bitmap <= 4'h0; + end else begin + if (up_sot == 1'b1) begin + up_transfer_id <= up_transfer_id + 1'b1; + up_transfer_done_bitmap[up_transfer_id] <= 1'b0; + end + + if (up_eot == 1'b1) begin + up_transfer_id_eot <= up_transfer_id_eot + 1'b1; + up_transfer_done_bitmap[up_transfer_id_eot] <= 1'b1; + end + end + end + + assign up_tlf_rd = up_rreq && up_raddr == 'h114; + assign up_bl_partial = response_valid & response_ready & response_partial & up_dma_enable_tlen_reporting; + + always @(posedge clk) begin + if (ctrl_enable == 1'b0) begin + up_partial_length_valid <= 1'b0; + end else begin + if (up_bl_partial == 1'b1) begin + up_partial_length_valid <= 1'b1; + end else if (up_tlf_rd == 1'b1) begin + up_partial_length_valid <= 1'b0; + end else if (up_tlf_valid == 1'b1) begin + up_partial_length_valid <= 1'b1; + end + end + end + + always @(posedge clk) begin + if (ctrl_enable == 1'b0) begin + up_measured_transfer_length <= 'h0; + end else if (response_valid == 1'b1 && response_ready == 1'b1) begin + up_measured_transfer_length <= up_measured_transfer_length + response_measured_burst_length + 1'b1; + end else if (up_clear_tl == 1'b1) begin + up_measured_transfer_length <= 'h0; + end + end + + always @(posedge clk) begin + if (response_valid == 1'b1 && response_ready == 1'b1) begin + up_transfer_id_eot_d <= up_transfer_id_eot; + end + end + + always @(posedge clk) begin + if (ctrl_enable == 1'b0) begin + response_ready <= 1'b1; + end else if (response_ready == 1'b1) begin + response_ready <= ~response_valid; + end else if (up_tlf_s_ready == 1'b1) begin + response_ready <= 1'b1; + end + end + + always @(posedge clk) + begin + if (response_valid == 1'b1 && response_ready == 1'b1) begin + up_tlf_s_valid <= up_bl_partial; + up_clear_tl <= response_eot; + end else if (up_tlf_s_ready == 1'b1) begin + up_tlf_s_valid <= 1'b0; + end + end + + // Buffer the length and transfer ID of partial transfers + util_axis_fifo #( + .DATA_WIDTH(MEASURED_LENGTH_WIDTH + 2), + .ADDRESS_WIDTH(2), + .ASYNC_CLK(0) + ) i_transfer_lenghts_fifo ( + .s_axis_aclk(clk), + .s_axis_aresetn(ctrl_enable), + .s_axis_valid(up_tlf_s_valid), + .s_axis_ready(up_tlf_s_ready), + .s_axis_full(), + .s_axis_data({up_transfer_id_eot_d, up_measured_transfer_length}), + .s_axis_room(), + + .m_axis_aclk(clk), + .m_axis_aresetn(ctrl_enable), + .m_axis_valid(up_tlf_valid), + .m_axis_ready(up_tlf_rd & up_tlf_valid), + .m_axis_data(up_tlf_data), + .m_axis_level(), + .m_axis_empty ()); + +endmodule diff --git a/adi_library/axi_dmac/axi_dmac_reset_manager.v b/adi_library/axi_dmac/axi_dmac_reset_manager.v new file mode 100644 index 00000000..71dd0b73 --- /dev/null +++ b/adi_library/axi_dmac/axi_dmac_reset_manager.v @@ -0,0 +1,346 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dmac_reset_manager #( + parameter ASYNC_CLK_REQ_SRC = 1, + parameter ASYNC_CLK_SRC_DEST = 1, + parameter ASYNC_CLK_DEST_REQ = 1, + parameter ASYNC_CLK_REQ_SG = 1, + parameter DMA_SG_TRANSFER = 0 +) ( + input clk, + input resetn, + + input ctrl_enable, + input ctrl_pause, + input ctrl_hwdesc, + + output req_resetn, + output req_enable, + input req_enabled, + + input dest_clk, + input dest_ext_resetn, + output dest_resetn, + output dest_enable, + input dest_enabled, + + input src_clk, + input src_ext_resetn, + output src_resetn, + output src_enable, + input src_enabled, + + input sg_clk, + input sg_ext_resetn, + output sg_resetn, + output sg_enable, + input sg_enabled, + + output [11:0] dbg_status +); + + /* + * TODO: + * If an external reset is asserted for a domain that domain will go into reset + * immediately. If a transfer is currently active the transfer will be aborted + * and other domains will be shutdown gracefully. The reset manager will stay in + * the shutdown state until all external resets have been de-asserted. + */ + + localparam STATE_DO_RESET = 3'h0; + localparam STATE_RESET = 3'h1; + localparam STATE_DISABLED = 3'h2; + localparam STATE_STARTUP = 3'h3; + localparam STATE_ENABLED = 3'h4; + localparam STATE_SHUTDOWN = 3'h5; + + reg [2:0] state = 3'b000; + reg needs_reset = 1'b0; + reg do_reset = 1'b0; + reg do_enable = 1'b0; + + wire enabled_dest; + wire enabled_src; + wire enabled_sg; + + wire enabled_all; + wire disabled_all; + + generate if (DMA_SG_TRANSFER == 1) begin + assign enabled_all = req_enabled & enabled_src & enabled_dest & (enabled_sg | ~ctrl_hwdesc); + assign disabled_all = ~(req_enabled | enabled_src | enabled_dest | (enabled_sg & ctrl_hwdesc)); + end else begin + assign enabled_all = req_enabled & enabled_src & enabled_dest; + assign disabled_all = ~(req_enabled | enabled_src | enabled_dest); + end endgenerate + + assign req_enable = do_enable; + + assign dbg_status = {needs_reset,req_resetn,src_resetn,dest_resetn,sg_resetn,req_enabled,enabled_src,enabled_dest,enabled_sg,state}; + + always @(posedge clk) begin + if (state == STATE_DO_RESET) begin + do_reset <= 1'b1; + end else begin + do_reset <= 1'b0; + end + end + + always @(posedge clk) begin + if (state == STATE_STARTUP || state == STATE_ENABLED) begin + do_enable <= 1'b1; + end else begin + do_enable <= 1'b0; + end + end + + /* + * If ctrl_enable goes from 1 to 0 a shutdown procedure is initiated. During the + * shutdown procedure all domains are signaled that a shutdown should occur. The + * domains will then complete any active transactions that are required to + * complete according to the interface semantics. Once a domain has completed + * its transactions it will indicate that it has been shutdown. Once all domains + * indicate that they have been disabled a reset pulse will be generated to all + * domains to clear all residual state. The reset pulse is long enough so that it + * is active in all domains for at least 4 clock cycles. + * + * Once the reset signal is de-asserted the DMA is in an idle state and can be + * enabled again. If the DMA receives a enable while it is performing a shutdown + * sequence it will only be re-enabled once the shutdown sequence has + * successfully completed. + * + * If ctrl_pause is asserted all domains will be disabled. But there will be no + * reset, so when the ctrl_pause signal is de-asserted again the DMA will resume + * with its previous state. + * + */ + + /* + * If ctrl_enable goes low, even for a single clock cycle, we want to go through + * a full reset sequence. This might happen when the state machine is busy, e.g. + * going through a startup sequence. To avoid missing the event store it for + * later. + */ + always @(posedge clk) begin + if (state == STATE_RESET) begin + needs_reset <= 1'b0; + end else if (ctrl_enable == 1'b0) begin + needs_reset <= 1'b1; + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + state <= STATE_DO_RESET; + end else begin + case (state) + STATE_DO_RESET: begin + state <= STATE_RESET; + end + STATE_RESET: begin + /* + * Wait for the reset sequence to complete. Stay in this state when + * ctrl_enable == 1'b0, otherwise we'd go through the reset sequence + * again and again. + */ + if (ctrl_enable == 1'b1 && req_resetn == 1'b1) begin + state <= STATE_DISABLED; + end + end + STATE_DISABLED: begin + if (needs_reset == 1'b1) begin + state <= STATE_DO_RESET; + end else if (ctrl_pause == 1'b0) begin + state <= STATE_STARTUP; + end + end + STATE_STARTUP: begin + /* Wait for all domains to be ready */ + if (enabled_all == 1'b1) begin + state <= STATE_ENABLED; + end + end + STATE_ENABLED: begin + if (needs_reset == 1'b1 || ctrl_pause == 1'b1) begin + state <= STATE_SHUTDOWN; + end + end + STATE_SHUTDOWN: begin + /* Wait for all domains to complete outstanding transactions */ + if (disabled_all == 1'b1) begin + state <= STATE_DISABLED; + end + end + endcase + end + end + + /* + * Chain the reset through all clock domains. This makes sure that is asserted + * for at least 4 clock cycles of the slowest domain, no matter what. If + * successive domains have the same clock they'll share their reset signal. + */ + + localparam NUM_RESET_LINKS = DMA_SG_TRANSFER ? 4 : 3; + localparam GEN_ASYNC_RESET = { + ASYNC_CLK_REQ_SG ? 1'b1 : 1'b0, + ASYNC_CLK_REQ_SRC ? 1'b1 : 1'b0, + ASYNC_CLK_SRC_DEST ? 1'b1 : 1'b0, + 1'b1 + }; + + wire [NUM_RESET_LINKS:0] reset_async_chain; + wire [NUM_RESET_LINKS:0] reset_sync_chain; + wire [3:0] reset_chain_clks = {sg_clk, clk, src_clk, dest_clk}; + + assign reset_async_chain[0] = 1'b0; + assign reset_sync_chain[0] = reset_async_chain[3]; + + generate + genvar i; + + for (i = 0; i < NUM_RESET_LINKS; i = i + 1) begin: reset_gen + + if (GEN_ASYNC_RESET[i] == 1'b1) begin + + reg [3:0] reset_async = 4'b1111; + reg [1:0] reset_sync = 2'b11; + reg reset_sync_in = 1'b1; + + always @(posedge reset_chain_clks[i] or posedge reset_sync_chain[i]) begin + if (reset_sync_chain[i] == 1'b1) begin + reset_sync_in <= 1'b1; + end else begin + reset_sync_in <= reset_async[0]; + end + end + + always @(posedge reset_chain_clks[i] or posedge do_reset) begin + if (do_reset == 1'b1) begin + reset_async <= 4'b1111; + end else begin + reset_async <= {reset_async_chain[i], reset_async[3:1]}; + end + end + + always @(posedge reset_chain_clks[i]) begin + reset_sync <= {reset_sync_in,reset_sync[1]}; + end + + assign reset_async_chain[i+1] = reset_async[0]; + assign reset_sync_chain[i+1] = reset_sync[0]; + + end else begin + assign reset_async_chain[i+1] = reset_async_chain[i]; + assign reset_sync_chain[i+1] = reset_sync_chain[i]; + end + end + + endgenerate + + /* De-assertions in the opposite direction of the data flow: dest, src, request */ + assign dest_resetn = ~reset_sync_chain[1]; + assign src_resetn = ~reset_sync_chain[2]; + assign req_resetn = ~reset_sync_chain[3]; + generate if (DMA_SG_TRANSFER == 1) begin + assign sg_resetn = ~reset_sync_chain[4]; + end else begin + assign sg_resetn = 1'b0; + end endgenerate + + sync_bits #( + .NUM_OF_BITS (1), + .ASYNC_CLK (ASYNC_CLK_DEST_REQ) + ) i_sync_control_dest ( + .out_clk (dest_clk), + .out_resetn (1'b1), + .in_bits (do_enable), + .out_bits (dest_enable)); + + sync_bits #( + .NUM_OF_BITS (1), + .ASYNC_CLK (ASYNC_CLK_DEST_REQ) + ) i_sync_status_dest ( + .out_clk (clk), + .out_resetn (1'b1), + .in_bits (dest_enabled), + .out_bits (enabled_dest)); + + sync_bits #( + .NUM_OF_BITS (1), + .ASYNC_CLK (ASYNC_CLK_REQ_SRC) + ) i_sync_control_src ( + .out_clk (src_clk), + .out_resetn (1'b1), + .in_bits (do_enable), + .out_bits (src_enable)); + + sync_bits #( + .NUM_OF_BITS (1), + .ASYNC_CLK (ASYNC_CLK_REQ_SRC) + ) i_sync_status_src ( + .out_clk (clk), + .out_resetn (1'b1), + .in_bits (src_enabled), + .out_bits (enabled_src)); + + generate if (DMA_SG_TRANSFER == 1) begin + sync_bits #( + .NUM_OF_BITS (1), + .ASYNC_CLK (ASYNC_CLK_REQ_SG) + ) i_sync_control_sg ( + .out_clk (sg_clk), + .out_resetn (1'b1), + .in_bits (do_enable), + .out_bits (sg_enable)); + + sync_bits #( + .NUM_OF_BITS (1), + .ASYNC_CLK (ASYNC_CLK_REQ_SG) + ) i_sync_status_sg ( + .out_clk (clk), + .out_resetn (1'b1), + .in_bits (sg_enabled), + .out_bits (enabled_sg)); + + end else begin + assign sg_enable = 1'b0; + assign enabled_sg = 1'b0; + end endgenerate + +endmodule diff --git a/adi_library/axi_dmac/axi_dmac_resize_dest.v b/adi_library/axi_dmac/axi_dmac_resize_dest.v new file mode 100644 index 00000000..d734c11b --- /dev/null +++ b/adi_library/axi_dmac/axi_dmac_resize_dest.v @@ -0,0 +1,138 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dmac_resize_dest #( + parameter DATA_WIDTH_DEST = 64, + parameter DATA_WIDTH_MEM = 64 +) ( + input clk, + input reset, + + input mem_data_valid, + output mem_data_ready, + input [DATA_WIDTH_MEM-1:0] mem_data, + input mem_data_last, + input [DATA_WIDTH_MEM/8-1:0] mem_data_strb, + + output dest_data_valid, + input dest_data_ready, + output [DATA_WIDTH_DEST-1:0] dest_data, + output dest_data_last, + output [DATA_WIDTH_DEST/8-1:0] dest_data_strb +); + + /* + * Resize the data width between the burst memory and the destination interface + * if necessary. + */ + + generate if (DATA_WIDTH_DEST == DATA_WIDTH_MEM) begin + assign dest_data_valid = mem_data_valid; + assign dest_data = mem_data; + assign dest_data_last = mem_data_last; + assign dest_data_strb = mem_data_strb; + assign mem_data_ready = dest_data_ready; + end else begin + + localparam RATIO = DATA_WIDTH_MEM / DATA_WIDTH_DEST; + + reg [$clog2(RATIO)-1:0] count = 'h0; + reg valid = 1'b0; + reg [RATIO-1:0] last = 'h0; + reg [DATA_WIDTH_MEM-1:0] data = 'h0; + reg [DATA_WIDTH_MEM/8-1:0] strb = {DATA_WIDTH_MEM/8{1'b1}}; + + wire last_beat; + + assign last_beat = (count == RATIO - 1) | last[0]; + + always @(posedge clk) begin + if (reset == 1'b1) begin + valid <= 1'b0; + end else if (mem_data_valid == 1'b1) begin + valid <= 1'b1; + end else if (last_beat == 1'b1 && dest_data_ready == 1'b1) begin + valid <= 1'b0; + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + count <= 'h0; + end else if (dest_data_ready == 1'b1 && dest_data_valid == 1'b1) begin + if (last_beat == 1'b1) begin + count <= 'h0; + end else begin + count <= count + 1; + end + end + end + + assign mem_data_ready = ~valid | (dest_data_ready & last_beat); + + integer i; + always @(posedge clk) begin + if (mem_data_ready == 1'b1) begin + data <= mem_data; + + /* + * Skip those words where strb would be completely zero for the output + * word. We assume that strb is thermometer encoded (i.e. a certain number + * of LSBs are 1'b1 followed by all 1'b0 in the MSBs) and by extension + * that if the first strb bit for a word is zero that means that all strb + * bits for a word will be zero. + */ + for (i = 0; i < RATIO-1; i = i + 1) begin + last[i] <= mem_data_last & ~mem_data_strb[(i+1)*(DATA_WIDTH_MEM/8/RATIO)]; + end + last[RATIO-1] <= mem_data_last; + strb <= mem_data_strb; + end else if (dest_data_ready == 1'b1) begin + data[DATA_WIDTH_MEM-DATA_WIDTH_DEST-1:0] <= data[DATA_WIDTH_MEM-1:DATA_WIDTH_DEST]; + strb[(DATA_WIDTH_MEM-DATA_WIDTH_DEST)/8-1:0] <= strb[DATA_WIDTH_MEM/8-1:DATA_WIDTH_DEST/8]; + last[RATIO-2:0] <= last[RATIO-1:1]; + end + end + + assign dest_data_valid = valid; + assign dest_data = data[DATA_WIDTH_DEST-1:0]; + assign dest_data_strb = strb[DATA_WIDTH_DEST/8-1:0]; + assign dest_data_last = last[0]; + + end endgenerate + +endmodule diff --git a/adi_library/axi_dmac/axi_dmac_resize_src.v b/adi_library/axi_dmac/axi_dmac_resize_src.v new file mode 100644 index 00000000..761446f9 --- /dev/null +++ b/adi_library/axi_dmac/axi_dmac_resize_src.v @@ -0,0 +1,146 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +/* + * Resize the data width between the source interface and the burst memory + * if necessary. + */ + +`timescale 1ns/100ps + +module axi_dmac_resize_src #( + parameter DATA_WIDTH_SRC = 64, + parameter BYTES_PER_BEAT_WIDTH_SRC = 3, + parameter DATA_WIDTH_MEM = 64, + parameter BYTES_PER_BEAT_WIDTH_MEM = 3 +) ( + input clk, + input reset, + + input src_data_valid, + input [DATA_WIDTH_SRC-1:0] src_data, + input src_data_last, + input [BYTES_PER_BEAT_WIDTH_SRC-1:0] src_data_valid_bytes, + input src_data_partial_burst, + + output mem_data_valid, + output [DATA_WIDTH_MEM-1:0] mem_data, + output mem_data_last, + output [BYTES_PER_BEAT_WIDTH_MEM-1:0] mem_data_valid_bytes, + output mem_data_partial_burst +); + + generate if (DATA_WIDTH_SRC == DATA_WIDTH_MEM) begin + assign mem_data_valid = src_data_valid; + assign mem_data = src_data; + assign mem_data_last = src_data_last; + assign mem_data_valid_bytes = src_data_valid_bytes; + assign mem_data_partial_burst = src_data_partial_burst; + end else begin + + localparam RATIO = DATA_WIDTH_MEM / DATA_WIDTH_SRC; + localparam RATIO_WIDTH = RATIO > 64 ? 7 : + RATIO > 32 ? 6 : + RATIO > 16 ? 5 : + RATIO > 8 ? 4 : + RATIO > 4 ? 3 : + RATIO > 2 ? 2 : 1; + + reg [RATIO-1:0] mask = 'h1; + reg valid = 1'b0; + reg last = 1'b0; + reg [DATA_WIDTH_MEM-1:0] data = 'h0; + reg [BYTES_PER_BEAT_WIDTH_SRC-1:0] valid_bytes = 'h00; + reg partial_burst = 1'b0; + reg [RATIO_WIDTH-1:0] num_beats = {RATIO_WIDTH{1'b1}}; + + always @(posedge clk) begin + if (reset == 1'b1) begin + valid <= 1'b0; + mask <= 'h1; + end else if (src_data_valid == 1'b1) begin + valid <= mask[RATIO-1] || src_data_last; + if (src_data_last) begin + mask <= 'h1; + end else begin + mask <= {mask[RATIO-2:0],mask[RATIO-1]}; + end + end else begin + valid <= 1'b0; + end + end + + // This counter will hold the number of source beat in a destination beat + // minus one + always @(posedge clk) begin + if (reset == 1'b1) begin + num_beats <= {RATIO_WIDTH{1'b1}}; + end else if (valid == 1'b1 && last == 1'b1) begin + if (src_data_valid == 1'b1) begin + num_beats <= {RATIO_WIDTH{1'b0}}; + end else begin + num_beats <= {RATIO_WIDTH{1'b1}}; + end + end else if (src_data_valid == 1'b1) begin + num_beats <= num_beats + 1'b1; + end + end + + integer i; + + always @(posedge clk) begin + for (i = 0; i < RATIO; i = i+1) begin + if (mask[i] == 1'b1) begin + data[i*DATA_WIDTH_SRC+:DATA_WIDTH_SRC] <= src_data; + end + end + + // Compensate for the one clock cycle pipeline delay of the data + last <= src_data_last; + if (src_data_valid == 1'b1) begin + valid_bytes <= src_data_valid_bytes; + partial_burst <= src_data_partial_burst; + end + end + + assign mem_data_valid = valid; + assign mem_data = data; + assign mem_data_last = last; + assign mem_data_valid_bytes = {num_beats,valid_bytes}; + assign mem_data_partial_burst = partial_burst; + + end endgenerate + +endmodule diff --git a/adi_library/axi_dmac/axi_dmac_response_manager.v b/adi_library/axi_dmac/axi_dmac_response_manager.v new file mode 100644 index 00000000..c51ac780 --- /dev/null +++ b/adi_library/axi_dmac/axi_dmac_response_manager.v @@ -0,0 +1,282 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dmac_response_manager #( + parameter DMA_DATA_WIDTH_SRC = 64, + parameter DMA_DATA_WIDTH_DEST = 64, + parameter DMA_LENGTH_WIDTH = 24, + parameter BYTES_PER_BURST_WIDTH = 7, + parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(DMA_DATA_WIDTH_SRC/8), + parameter ASYNC_CLK_DEST_REQ = 1 +) ( + + // Interface to destination side + input dest_clk, + input dest_resetn, + + input dest_response_valid, + output dest_response_ready, + input [1:0] dest_response_resp, + input dest_response_partial, + input dest_response_resp_eot, + input [BYTES_PER_BURST_WIDTH-1:0] dest_response_data_burst_length, + + // Interface to processor + input req_clk, + input req_resetn, + + output response_eot, + output reg [BYTES_PER_BURST_WIDTH-1:0] measured_burst_length = 'h0, + output response_partial, + output reg response_valid = 1'b0, + input response_ready, + + // Interface to requester side + input completion_req_valid, + output reg completion_req_ready = 1'b1, + input completion_req_last, + input [1:0] completion_transfer_id +); + + localparam STATE_IDLE = 3'h0; + localparam STATE_ACC = 3'h1; + localparam STATE_WRITE_RESPR = 3'h2; + localparam STATE_ZERO_COMPL = 3'h3; + localparam STATE_WRITE_ZRCMPL = 3'h4; + + reg [2:0] state = STATE_IDLE; + reg [2:0] nx_state; + + localparam DEST_SRC_RATIO = DMA_DATA_WIDTH_DEST/DMA_DATA_WIDTH_SRC; + + localparam DEST_SRC_RATIO_WIDTH = DEST_SRC_RATIO > 64 ? 7 : + DEST_SRC_RATIO > 32 ? 6 : + DEST_SRC_RATIO > 16 ? 5 : + DEST_SRC_RATIO > 8 ? 4 : + DEST_SRC_RATIO > 4 ? 3 : + DEST_SRC_RATIO > 2 ? 2 : + DEST_SRC_RATIO > 1 ? 1 : 0; + + localparam BYTES_PER_BEAT_WIDTH = DEST_SRC_RATIO_WIDTH + BYTES_PER_BEAT_WIDTH_SRC; + localparam BURST_LEN_WIDTH = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH; + + wire do_acc_st; + wire do_compl; + reg req_eot = 1'b0; + reg req_response_partial = 1'b0; + reg [BYTES_PER_BURST_WIDTH-1:0] req_response_dest_data_burst_length = 'h0; + + wire response_dest_valid; + reg response_dest_ready = 1'b1; + wire [1:0] response_dest_resp; + wire response_dest_resp_eot; + wire [BYTES_PER_BURST_WIDTH-1:0] response_dest_data_burst_length; + + wire completion_req; + + reg [1:0] to_complete_count = 'h0; + reg [1:0] transfer_id = 'h0; + reg completion_req_last_found = 1'b0; + + util_axis_fifo #( + .DATA_WIDTH(BYTES_PER_BURST_WIDTH+1+1), + .ADDRESS_WIDTH(0), + .ASYNC_CLK(ASYNC_CLK_DEST_REQ) + ) i_dest_response_fifo ( + .s_axis_aclk(dest_clk), + .s_axis_aresetn(dest_resetn), + .s_axis_valid(dest_response_valid), + .s_axis_ready(dest_response_ready), + .s_axis_full(), + .s_axis_data({dest_response_data_burst_length, + dest_response_partial, + dest_response_resp_eot}), + .s_axis_room(), + + .m_axis_aclk(req_clk), + .m_axis_aresetn(req_resetn), + .m_axis_valid(response_dest_valid), + .m_axis_ready(response_dest_ready), + .m_axis_data({response_dest_data_burst_length, + response_dest_partial, + response_dest_resp_eot}), + .m_axis_level(), + .m_axis_empty()); + + always @(posedge req_clk) + begin + if (response_dest_valid & response_dest_ready) begin + req_eot <= response_dest_resp_eot; + req_response_partial <= response_dest_partial; + req_response_dest_data_burst_length <= response_dest_data_burst_length; + end + end + + always @(posedge req_clk) + begin + if (req_resetn == 1'b0) begin + response_dest_ready <= 1'b1; + end else begin + response_dest_ready <= (nx_state == STATE_IDLE); + end + end + + assign response_eot = (state == STATE_WRITE_RESPR) ? req_eot : 1'b0; + assign response_partial = (state == STATE_WRITE_RESPR) ? req_response_partial : 1'b0; + + always @(posedge req_clk) + begin + if (req_resetn == 1'b0) begin + response_valid <= 1'b0; + end else begin + if (nx_state == STATE_WRITE_RESPR || nx_state == STATE_WRITE_ZRCMPL) begin + response_valid <= 1'b1; + end else if (response_ready == 1'b1) begin + response_valid <= 1'b0; + end + end + end + + always @(posedge req_clk) + begin + if (state == STATE_ZERO_COMPL) begin + measured_burst_length <= {BYTES_PER_BURST_WIDTH{1'b1}}; + end else if (state == STATE_ACC) begin + measured_burst_length <= req_response_dest_data_burst_length; + end + end + + always @(*) begin + nx_state = state; + case (state) + STATE_IDLE: begin + if (response_dest_valid == 1'b1) begin + nx_state = STATE_ACC; + end else if (|to_complete_count) begin + if (transfer_id == completion_transfer_id) + nx_state = STATE_ZERO_COMPL; + end + end + STATE_ACC: begin + nx_state = STATE_WRITE_RESPR; + end + STATE_WRITE_RESPR: begin + if (response_ready == 1'b1) begin + if (|to_complete_count && transfer_id == completion_transfer_id) begin + nx_state = STATE_ZERO_COMPL; + end else begin + nx_state = STATE_IDLE; + end + end + end + STATE_ZERO_COMPL: begin + if (|to_complete_count) begin + nx_state = STATE_WRITE_ZRCMPL; + end else begin + if (completion_req_last_found == 1'b1) begin + nx_state = STATE_IDLE; + end + end + end + STATE_WRITE_ZRCMPL:begin + if (response_ready == 1'b1) begin + nx_state = STATE_ZERO_COMPL; + end + end + default: begin + nx_state = STATE_IDLE; + end + endcase + end + + always @(posedge req_clk) begin + if (req_resetn == 1'b0) begin + state <= STATE_IDLE; + end else begin + state <= nx_state; + end + end + + assign do_compl = (state == STATE_WRITE_ZRCMPL) && response_ready; + + // Once the last completion request from request generator is received + // we can wait for completions from the destination side + always @(posedge req_clk) begin + if (req_resetn == 1'b0) begin + completion_req_last_found <= 1'b0; + end else if (completion_req) begin + completion_req_last_found <= completion_req_last; + end else if (state ==STATE_ZERO_COMPL && ~(|to_complete_count)) begin + completion_req_last_found <= 1'b0; + end + end + + // Once the last completion is received wit until all completions are done + always @(posedge req_clk) begin + if (req_resetn == 1'b0) begin + completion_req_ready <= 1'b1; + end else if (completion_req_valid && completion_req_last) begin + completion_req_ready <= 1'b0; + end else if (to_complete_count == 0) begin + completion_req_ready <= 1'b1; + end + end + + assign completion_req = completion_req_ready && completion_req_valid; + + // Track transfers so we can tell when did the destination completed all its + // transfers + always @(posedge req_clk) begin + if (req_resetn == 1'b0) begin + transfer_id <= 'h0; + end else if ((state == STATE_ACC && req_eot) || do_compl) begin + transfer_id <= transfer_id + 1; + end + end + + // Count how many transfers we need to complete + always @(posedge req_clk) begin + if (req_resetn == 1'b0) begin + to_complete_count <= 'h0; + end else if (completion_req & ~do_compl) begin + to_complete_count <= to_complete_count + 1; + end else if (~completion_req & do_compl) begin + to_complete_count <= to_complete_count - 1; + end + end + +endmodule diff --git a/adi_library/axi_dmac/axi_dmac_transfer.v b/adi_library/axi_dmac/axi_dmac_transfer.v new file mode 100644 index 00000000..b3c55bea --- /dev/null +++ b/adi_library/axi_dmac/axi_dmac_transfer.v @@ -0,0 +1,617 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dmac_transfer #( + parameter DMA_DATA_WIDTH_SRC = 64, + parameter DMA_DATA_WIDTH_DEST = 64, + parameter DMA_DATA_WIDTH_SG = 64, + parameter DMA_LENGTH_WIDTH = 24, + parameter DMA_LENGTH_ALIGN = 3, + parameter BYTES_PER_BEAT_WIDTH_DEST = $clog2(DMA_DATA_WIDTH_DEST/8), + parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(DMA_DATA_WIDTH_SRC/8), + parameter BYTES_PER_BEAT_WIDTH_SG = $clog2(DMA_DATA_WIDTH_SG/8), + parameter DMA_TYPE_DEST = 0, + parameter DMA_TYPE_SRC = 2, + parameter DMA_AXI_ADDR_WIDTH = 32, + parameter DMA_2D_TRANSFER = 0, + parameter DMA_SG_TRANSFER = 0, + parameter ASYNC_CLK_REQ_SRC = 1, + parameter ASYNC_CLK_SRC_DEST = 1, + parameter ASYNC_CLK_DEST_REQ = 1, + parameter ASYNC_CLK_REQ_SG = 1, + parameter AXI_SLICE_DEST = 0, + parameter AXI_SLICE_SRC = 0, + parameter MAX_BYTES_PER_BURST = 128, + parameter BYTES_PER_BURST_WIDTH = 7, + parameter FIFO_SIZE = 8, + parameter ID_WIDTH = $clog2(FIFO_SIZE*2), + parameter AXI_LENGTH_WIDTH_SRC = 8, + parameter AXI_LENGTH_WIDTH_DEST = 8, + parameter AXI_LENGTH_WIDTH_SG = 8, + parameter ENABLE_DIAGNOSTICS_IF = 0, + parameter ALLOW_ASYM_MEM = 0, + parameter CACHE_COHERENT_DEST = 0 +) ( + input ctrl_clk, + input ctrl_resetn, + + input ctrl_enable, + input ctrl_pause, + input ctrl_hwdesc, + + input req_valid, + output req_ready, + + input [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address, + input [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] req_src_address, + input [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SG] req_sg_address, + input [DMA_LENGTH_WIDTH-1:0] req_x_length, + input [DMA_LENGTH_WIDTH-1:0] req_y_length, + input [DMA_LENGTH_WIDTH-1:0] req_dest_stride, + input [DMA_LENGTH_WIDTH-1:0] req_src_stride, + input req_sync_transfer_start, + input req_last, + + output req_eot, + output [31:0] req_sg_desc_id, + output [BYTES_PER_BURST_WIDTH-1:0] req_measured_burst_length, + output req_response_partial, + output req_response_valid, + input req_response_ready, + + // Master AXI interface + input m_dest_axi_aclk, + input m_dest_axi_aresetn, + input m_src_axi_aclk, + input m_src_axi_aresetn, + input m_sg_axi_aclk, + input m_sg_axi_aresetn, + + // Write address + output [DMA_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output [AXI_LENGTH_WIDTH_DEST-1:0] m_axi_awlen, + output [2:0] m_axi_awsize, + output [1:0] m_axi_awburst, + output [2:0] m_axi_awprot, + output [3:0] m_axi_awcache, + output m_axi_awvalid, + input m_axi_awready, + + // Write data + output [DMA_DATA_WIDTH_DEST-1:0] m_axi_wdata, + output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_axi_wstrb, + input m_axi_wready, + output m_axi_wvalid, + output m_axi_wlast, + + // Write response + input m_axi_bvalid, + input [1:0] m_axi_bresp, + output m_axi_bready, + + // Read address + input m_axi_arready, + output m_axi_arvalid, + output [DMA_AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output [AXI_LENGTH_WIDTH_SRC-1:0] m_axi_arlen, + output [2:0] m_axi_arsize, + output [1:0] m_axi_arburst, + output [2:0] m_axi_arprot, + output [3:0] m_axi_arcache, + + // Read data and response + input [DMA_DATA_WIDTH_SRC-1:0] m_axi_rdata, + input m_axi_rlast, + output m_axi_rready, + input m_axi_rvalid, + input [1:0] m_axi_rresp, + + // Read address + input m_sg_axi_arready, + output m_sg_axi_arvalid, + output [DMA_AXI_ADDR_WIDTH-1:0] m_sg_axi_araddr, + output [AXI_LENGTH_WIDTH_SG-1:0] m_sg_axi_arlen, + output [2:0] m_sg_axi_arsize, + output [1:0] m_sg_axi_arburst, + output [2:0] m_sg_axi_arprot, + output [3:0] m_sg_axi_arcache, + + // Read data and response + input [DMA_DATA_WIDTH_SG-1:0] m_sg_axi_rdata, + input m_sg_axi_rlast, + output m_sg_axi_rready, + input m_sg_axi_rvalid, + input [1:0] m_sg_axi_rresp, + + // Slave streaming AXI interface + input s_axis_aclk, + output s_axis_ready, + input s_axis_valid, + input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data, + input [0:0] s_axis_user, + input s_axis_last, + output s_axis_xfer_req, + + // Master streaming AXI interface + input m_axis_aclk, + input m_axis_ready, + output m_axis_valid, + output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data, + output m_axis_last, + output m_axis_xfer_req, + + // Input FIFO interface + input fifo_wr_clk, + input fifo_wr_en, + input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din, + output fifo_wr_overflow, + input fifo_wr_sync, + output fifo_wr_xfer_req, + + // Input FIFO interface + input fifo_rd_clk, + input fifo_rd_en, + output fifo_rd_valid, + output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout, + output fifo_rd_underflow, + output fifo_rd_xfer_req, + + output [ID_WIDTH-1:0] dbg_dest_request_id, + output [ID_WIDTH-1:0] dbg_dest_address_id, + output [ID_WIDTH-1:0] dbg_dest_data_id, + output [ID_WIDTH-1:0] dbg_dest_response_id, + output [ID_WIDTH-1:0] dbg_src_request_id, + output [ID_WIDTH-1:0] dbg_src_address_id, + output [ID_WIDTH-1:0] dbg_src_data_id, + output [ID_WIDTH-1:0] dbg_src_response_id, + output [11:0] dbg_status, + + // Diagnostics interface + output [7:0] dest_diag_level_bursts +); + + wire dma_req_valid; + wire dma_req_ready; + wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] dma_req_dest_address; + wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] dma_req_src_address; + wire [DMA_LENGTH_WIDTH-1:0] dma_req_length; + wire [BYTES_PER_BURST_WIDTH-1:0] dma_req_measured_burst_length; + wire dma_req_eot; + wire dma_response_valid; + wire dma_response_ready; + wire dma_response_partial; + wire dma_req_sync_transfer_start; + wire dma_req_last; + + wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] dma_sg_out_dest_address; + wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] dma_sg_out_src_address; + wire [DMA_LENGTH_WIDTH-1:0] dma_sg_x_length; + wire [DMA_LENGTH_WIDTH-1:0] dma_sg_y_length; + wire [DMA_LENGTH_WIDTH-1:0] dma_sg_src_stride; + wire [DMA_LENGTH_WIDTH-1:0] dma_sg_dst_stride; + wire [31:0] dma_sg_hwdesc_id; + wire dma_sg_hwdesc_eot; + wire dma_sg_in_req_valid; + wire dma_sg_in_req_ready; + wire dma_sg_out_req_valid; + wire dma_sg_out_req_ready; + + wire req_clk = ctrl_clk; + wire req_resetn; + + wire req_enable; + + wire dest_clk; + wire dest_ext_resetn; + wire dest_resetn; + wire dest_enable; + wire dest_enabled; + + wire src_clk; + wire src_ext_resetn; + wire src_resetn; + wire src_enable; + wire src_enabled; + + wire sg_clk; + wire sg_ext_resetn; + wire sg_resetn; + wire sg_enable; + wire sg_enabled; + + wire req_valid_gated; + wire req_ready_gated; + + wire abort_req; + wire dma_eot; + + axi_dmac_reset_manager #( + .ASYNC_CLK_REQ_SRC (ASYNC_CLK_REQ_SRC), + .ASYNC_CLK_SRC_DEST (ASYNC_CLK_SRC_DEST), + .ASYNC_CLK_DEST_REQ (ASYNC_CLK_DEST_REQ), + .ASYNC_CLK_REQ_SG (ASYNC_CLK_REQ_SG), + .DMA_SG_TRANSFER (DMA_SG_TRANSFER) + ) i_reset_manager ( + .clk (ctrl_clk), + .resetn (ctrl_resetn), + + .ctrl_enable (ctrl_enable), + .ctrl_pause (ctrl_pause), + .ctrl_hwdesc (ctrl_hwdesc), + + .req_resetn (req_resetn), + .req_enable (req_enable), + .req_enabled (req_enable), + + .dest_clk (dest_clk), + .dest_ext_resetn (dest_ext_resetn), + .dest_resetn (dest_resetn), + .dest_enable (dest_enable), + .dest_enabled (dest_enabled), + + .src_clk (src_clk), + .src_ext_resetn (src_ext_resetn), + .src_resetn (src_resetn), + .src_enable (src_enable), + .src_enabled (src_enabled), + + .sg_clk (sg_clk), + .sg_ext_resetn (sg_ext_resetn), + .sg_resetn (sg_resetn), + .sg_enable (sg_enable), + .sg_enabled (sg_enabled), + + .dbg_status (dbg_status)); + + /* + * Things become a lot easier if we gate incoming requests in a central place + * before they are propagated downstream. Otherwise we'd need to take special + * care to not accidentally accept requests while the DMA is going through a + * shutdown and reset phase. + */ + assign req_valid_gated = req_enable & req_valid; + assign req_ready = req_enable & req_ready_gated; + + assign req_eot = ctrl_hwdesc ? (dma_eot & dma_sg_hwdesc_eot) : dma_eot; + assign req_sg_desc_id = ctrl_hwdesc ? dma_sg_hwdesc_id : 'h00; + assign dma_sg_in_req_valid = ctrl_hwdesc ? req_valid_gated : 1'b0; + + /* SG Interface */ + generate if (DMA_SG_TRANSFER == 1) begin + + dmac_sg #( + .DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH), + .DMA_DATA_WIDTH(DMA_DATA_WIDTH_SG), + .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH), + .AXI_LENGTH_WIDTH(AXI_LENGTH_WIDTH_SG), + .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST), + .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC), + .BYTES_PER_BEAT_WIDTH_SG(BYTES_PER_BEAT_WIDTH_SG), + .ASYNC_CLK_REQ_SG(ASYNC_CLK_REQ_SG) + ) i_dmac_sg ( + .req_clk(req_clk), + .req_resetn(req_resetn), + .req_enable(req_enable), + + .sg_clk(sg_clk), + .sg_ext_resetn(sg_ext_resetn), + .sg_resetn(sg_resetn), + .sg_enable(sg_enable), + .sg_enabled(sg_enabled), + + .req_in_valid(dma_sg_in_req_valid), + .req_in_ready(dma_sg_in_req_ready), + + .req_out_valid(dma_sg_out_req_valid), + .req_out_ready(dma_sg_out_req_ready), + + .req_desc_address(req_sg_address), + + .out_dest_address(dma_sg_out_dest_address), + .out_src_address(dma_sg_out_src_address), + + .out_x_length(dma_sg_x_length), + .out_y_length(dma_sg_y_length), + .out_dest_stride(dma_sg_dst_stride), + .out_src_stride(dma_sg_src_stride), + .resp_out_id(dma_sg_hwdesc_id), + .resp_out_eot(dma_sg_hwdesc_eot), + .resp_in_valid(dma_eot), + + .m_axi_aclk(m_sg_axi_aclk), + .m_axi_aresetn(m_sg_axi_aresetn), + + .m_axi_arready(m_sg_axi_arready), + .m_axi_arvalid(m_sg_axi_arvalid), + .m_axi_araddr(m_sg_axi_araddr), + .m_axi_arlen(m_sg_axi_arlen), + .m_axi_arsize(m_sg_axi_arsize), + .m_axi_arburst(m_sg_axi_arburst), + .m_axi_arprot(m_sg_axi_arprot), + .m_axi_arcache(m_sg_axi_arcache), + + .m_axi_rdata(m_sg_axi_rdata), + .m_axi_rlast(m_sg_axi_rlast), + .m_axi_rready(m_sg_axi_rready), + .m_axi_rvalid(m_sg_axi_rvalid), + .m_axi_rresp(m_sg_axi_rresp)); + + end else begin + + assign sg_clk = 1'b0; + assign sg_ext_resetn = 1'b0; + assign sg_enabled = 1'b0; + assign dma_sg_in_req_ready = 1'b0; + assign dma_sg_out_req_valid = 1'b0; + assign dma_sg_hwdesc_eot = 1'b0; + assign dma_sg_out_dest_address = 'h00; + assign dma_sg_out_src_address = 'h00; + assign dma_sg_x_length = 'h00; + assign dma_sg_y_length = 'h00; + assign dma_sg_dst_stride = 'h00; + assign dma_sg_src_stride = 'h00; + assign dma_sg_hwdesc_id = 'h00; + + end endgenerate + + /* 2D Interface */ + generate if (DMA_2D_TRANSFER == 1) begin + + wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] dma_2d_dest_address; + wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] dma_2d_src_address; + wire [DMA_LENGTH_WIDTH-1:0] dma_2d_x_length; + wire [DMA_LENGTH_WIDTH-1:0] dma_2d_y_length; + wire [DMA_LENGTH_WIDTH-1:0] dma_2d_src_stride; + wire [DMA_LENGTH_WIDTH-1:0] dma_2d_dst_stride; + wire dma_2d_eot; + + wire dma_2d_req_valid; + wire dma_2d_req_ready; + + assign dma_2d_dest_address = ctrl_hwdesc ? dma_sg_out_dest_address : req_dest_address; + assign dma_2d_src_address = ctrl_hwdesc ? dma_sg_out_src_address : req_src_address; + assign dma_2d_x_length = ctrl_hwdesc ? dma_sg_x_length : req_x_length; + assign dma_2d_y_length = ctrl_hwdesc ? dma_sg_y_length : req_y_length; + assign dma_2d_src_stride = ctrl_hwdesc ? dma_sg_src_stride : req_src_stride; + assign dma_2d_dst_stride = ctrl_hwdesc ? dma_sg_dst_stride : req_dest_stride; + + assign dma_2d_req_valid = ctrl_hwdesc ? dma_sg_out_req_valid : req_valid_gated; + assign req_ready_gated = ctrl_hwdesc ? dma_sg_in_req_ready : dma_2d_req_ready; + assign dma_eot = dma_2d_eot; + assign dma_sg_out_req_ready = dma_2d_req_ready; + + dmac_2d_transfer #( + .DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH), + .DMA_LENGTH_WIDTH (DMA_LENGTH_WIDTH), + .BYTES_PER_BURST_WIDTH (BYTES_PER_BURST_WIDTH), + .BYTES_PER_BEAT_WIDTH_DEST (BYTES_PER_BEAT_WIDTH_DEST), + .BYTES_PER_BEAT_WIDTH_SRC (BYTES_PER_BEAT_WIDTH_SRC) + ) i_2d_transfer ( + .req_aclk (req_clk), + .req_aresetn (req_resetn), + + .req_eot (dma_2d_eot), + .req_measured_burst_length (req_measured_burst_length), + .req_response_partial (req_response_partial), + .req_response_valid (req_response_valid), + .req_response_ready (req_response_ready), + + .req_valid (dma_2d_req_valid), + .req_ready (dma_2d_req_ready), + .req_dest_address (dma_2d_dest_address), + .req_src_address (dma_2d_src_address), + .req_x_length (dma_2d_x_length), + .req_y_length (dma_2d_y_length), + .req_dest_stride (dma_2d_dst_stride), + .req_src_stride (dma_2d_src_stride), + .req_sync_transfer_start (req_sync_transfer_start), + .req_last (req_last), + + .out_abort_req (abort_req), + .out_req_valid (dma_req_valid), + .out_req_ready (dma_req_ready), + .out_req_dest_address (dma_req_dest_address), + .out_req_src_address (dma_req_src_address), + .out_req_length (dma_req_length), + .out_req_sync_transfer_start (dma_req_sync_transfer_start), + .out_req_last (dma_req_last), + .out_eot (dma_req_eot), + .out_measured_burst_length (dma_req_measured_burst_length), + .out_response_partial (dma_response_partial), + .out_response_valid (dma_response_valid), + .out_response_ready (dma_response_ready)); + + end else begin + + /* Request */ + assign dma_req_valid = ctrl_hwdesc ? dma_sg_out_req_valid : req_valid_gated; + assign req_ready_gated = ctrl_hwdesc ? dma_sg_in_req_ready : dma_req_ready; + assign dma_eot = dma_req_eot; + assign dma_sg_out_req_ready = dma_req_ready; + + assign dma_req_dest_address = ctrl_hwdesc ? dma_sg_out_dest_address : req_dest_address; + assign dma_req_src_address = ctrl_hwdesc ? dma_sg_out_src_address : req_src_address; + assign dma_req_length = ctrl_hwdesc ? dma_sg_x_length : req_x_length; + assign dma_req_sync_transfer_start = req_sync_transfer_start; + assign dma_req_last = req_last; + + /* Response */ + assign req_measured_burst_length = dma_req_measured_burst_length; + assign req_response_partial = dma_response_partial; + assign req_response_valid = dma_response_valid; + assign dma_response_ready = req_response_ready; + + end endgenerate + + request_arb #( + .DMA_DATA_WIDTH_SRC (DMA_DATA_WIDTH_SRC), + .DMA_DATA_WIDTH_DEST (DMA_DATA_WIDTH_DEST), + .DMA_LENGTH_WIDTH (DMA_LENGTH_WIDTH), + .DMA_LENGTH_ALIGN (DMA_LENGTH_ALIGN), + .BYTES_PER_BEAT_WIDTH_DEST (BYTES_PER_BEAT_WIDTH_DEST), + .BYTES_PER_BEAT_WIDTH_SRC (BYTES_PER_BEAT_WIDTH_SRC), + .DMA_TYPE_DEST (DMA_TYPE_DEST), + .DMA_TYPE_SRC (DMA_TYPE_SRC), + .DMA_AXI_ADDR_WIDTH (DMA_AXI_ADDR_WIDTH), + .ASYNC_CLK_REQ_SRC (ASYNC_CLK_REQ_SRC), + .ASYNC_CLK_SRC_DEST (ASYNC_CLK_SRC_DEST), + .ASYNC_CLK_DEST_REQ (ASYNC_CLK_DEST_REQ), + .AXI_SLICE_DEST (AXI_SLICE_DEST), + .AXI_SLICE_SRC (AXI_SLICE_SRC), + .MAX_BYTES_PER_BURST (MAX_BYTES_PER_BURST), + .BYTES_PER_BURST_WIDTH (BYTES_PER_BURST_WIDTH), + .FIFO_SIZE (FIFO_SIZE), + .ID_WIDTH (ID_WIDTH), + .AXI_LENGTH_WIDTH_DEST (AXI_LENGTH_WIDTH_DEST), + .AXI_LENGTH_WIDTH_SRC (AXI_LENGTH_WIDTH_SRC), + .ENABLE_DIAGNOSTICS_IF(ENABLE_DIAGNOSTICS_IF), + .ALLOW_ASYM_MEM (ALLOW_ASYM_MEM), + .CACHE_COHERENT_DEST(CACHE_COHERENT_DEST) + ) i_request_arb ( + .req_clk (req_clk), + .req_resetn (req_resetn), + + .req_valid (dma_req_valid), + .req_ready (dma_req_ready), + .req_dest_address (dma_req_dest_address), + .req_src_address (dma_req_src_address), + .req_length (dma_req_length), + .req_xlast (dma_req_last), + .req_sync_transfer_start (dma_req_sync_transfer_start), + + .eot (dma_req_eot), + .measured_burst_length(dma_req_measured_burst_length), + .response_partial (dma_response_partial), + .response_valid (dma_response_valid), + .response_ready (dma_response_ready), + + .abort_req (abort_req), + + .req_enable (req_enable), + + .dest_clk (dest_clk), + .dest_ext_resetn (dest_ext_resetn), + .dest_resetn (dest_resetn), + .dest_enable (dest_enable), + .dest_enabled (dest_enabled), + + .src_clk (src_clk), + .src_ext_resetn (src_ext_resetn), + .src_resetn (src_resetn), + .src_enable (src_enable), + .src_enabled (src_enabled), + + .m_dest_axi_aclk (m_dest_axi_aclk), + .m_dest_axi_aresetn (m_dest_axi_aresetn), + .m_src_axi_aclk (m_src_axi_aclk), + .m_src_axi_aresetn (m_src_axi_aresetn), + + .m_axi_awvalid (m_axi_awvalid), + .m_axi_awready (m_axi_awready), + .m_axi_awaddr (m_axi_awaddr), + .m_axi_awlen (m_axi_awlen), + .m_axi_awsize (m_axi_awsize), + .m_axi_awburst (m_axi_awburst), + .m_axi_awprot (m_axi_awprot), + .m_axi_awcache (m_axi_awcache), + + .m_axi_wvalid (m_axi_wvalid), + .m_axi_wready (m_axi_wready), + .m_axi_wdata (m_axi_wdata), + .m_axi_wstrb (m_axi_wstrb), + .m_axi_wlast (m_axi_wlast), + + .m_axi_bvalid (m_axi_bvalid), + .m_axi_bready (m_axi_bready), + .m_axi_bresp (m_axi_bresp), + + .m_axi_arvalid (m_axi_arvalid), + .m_axi_arready (m_axi_arready), + .m_axi_araddr (m_axi_araddr), + .m_axi_arlen (m_axi_arlen), + .m_axi_arsize (m_axi_arsize), + .m_axi_arburst (m_axi_arburst), + .m_axi_arprot (m_axi_arprot), + .m_axi_arcache (m_axi_arcache), + + .m_axi_rready (m_axi_rready), + .m_axi_rvalid (m_axi_rvalid), + .m_axi_rdata (m_axi_rdata), + .m_axi_rlast (m_axi_rlast), + .m_axi_rresp (m_axi_rresp), + + .s_axis_aclk (s_axis_aclk), + .s_axis_ready (s_axis_ready), + .s_axis_valid (s_axis_valid), + .s_axis_data (s_axis_data), + .s_axis_user (s_axis_user), + .s_axis_last (s_axis_last), + .s_axis_xfer_req (s_axis_xfer_req), + + .m_axis_aclk (m_axis_aclk), + .m_axis_ready (m_axis_ready), + .m_axis_valid (m_axis_valid), + .m_axis_data (m_axis_data), + .m_axis_last (m_axis_last), + .m_axis_xfer_req (m_axis_xfer_req), + + .fifo_wr_clk (fifo_wr_clk), + .fifo_wr_en (fifo_wr_en), + .fifo_wr_din (fifo_wr_din), + .fifo_wr_overflow (fifo_wr_overflow), + .fifo_wr_sync (fifo_wr_sync), + .fifo_wr_xfer_req (fifo_wr_xfer_req), + + .fifo_rd_clk (fifo_rd_clk), + .fifo_rd_en (fifo_rd_en), + .fifo_rd_valid (fifo_rd_valid), + .fifo_rd_dout (fifo_rd_dout), + .fifo_rd_underflow (fifo_rd_underflow), + .fifo_rd_xfer_req (fifo_rd_xfer_req), + + .dbg_dest_request_id (dbg_dest_request_id), + .dbg_dest_address_id (dbg_dest_address_id), + .dbg_dest_data_id (dbg_dest_data_id), + .dbg_dest_response_id (dbg_dest_response_id), + .dbg_src_request_id (dbg_src_request_id), + .dbg_src_address_id (dbg_src_address_id), + .dbg_src_data_id (dbg_src_data_id), + .dbg_src_response_id (dbg_src_response_id), + + .dest_diag_level_bursts(dest_diag_level_bursts)); + +endmodule diff --git a/adi_library/axi_dmac/axi_register_slice.v b/adi_library/axi_dmac/axi_register_slice.v new file mode 100644 index 00000000..e5712224 --- /dev/null +++ b/adi_library/axi_dmac/axi_register_slice.v @@ -0,0 +1,135 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_register_slice #( + + parameter DATA_WIDTH = 32, + parameter FORWARD_REGISTERED = 0, + parameter BACKWARD_REGISTERED = 0 +) ( + input clk, + input resetn, + + input s_axi_valid, + output s_axi_ready, + input [DATA_WIDTH-1:0] s_axi_data, + + output m_axi_valid, + input m_axi_ready, + output [DATA_WIDTH-1:0] m_axi_data +); + + /* + s_axi_data -> bwd_data -> fwd_data(1) -> m_axi_data + s_axi_valid -> bwd_valid -> fwd_valid(1) -> m_axi_valid + s_axi_ready <- bwd_ready(2) <- fwd_ready <- m_axi_ready + + (1) FORWARD_REGISTERED inserts a set of FF before m_axi_data and m_axi_valid + (2) BACKWARD_REGISTERED insters a FF before s_axi_ready + */ + + wire [DATA_WIDTH-1:0] bwd_data_s; + wire bwd_valid_s; + wire bwd_ready_s; + wire [DATA_WIDTH-1:0] fwd_data_s; + wire fwd_valid_s; + wire fwd_ready_s; + + generate if (FORWARD_REGISTERED == 1) begin + reg fwd_valid = 1'b0; + reg [DATA_WIDTH-1:0] fwd_data = 'h00; + + assign fwd_ready_s = ~fwd_valid | m_axi_ready; + assign fwd_valid_s = fwd_valid; + assign fwd_data_s = fwd_data; + + always @(posedge clk) begin + if (~fwd_valid | m_axi_ready) + fwd_data <= bwd_data_s; + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + fwd_valid <= 1'b0; + end else begin + if (bwd_valid_s) + fwd_valid <= 1'b1; + else if (m_axi_ready) + fwd_valid <= 1'b0; + end + end + end else begin + assign fwd_data_s = bwd_data_s; + assign fwd_valid_s = bwd_valid_s; + assign fwd_ready_s = m_axi_ready; + end + endgenerate + + generate if (BACKWARD_REGISTERED == 1) begin + reg bwd_ready = 1'b1; + reg [DATA_WIDTH-1:0] bwd_data = 'h00; + + assign bwd_valid_s = ~bwd_ready | s_axi_valid; + assign bwd_data_s = bwd_ready ? s_axi_data : bwd_data; + assign bwd_ready_s = bwd_ready; + + always @(posedge clk) begin + if (bwd_ready) + bwd_data <= s_axi_data; + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + bwd_ready <= 1'b1; + end else begin + if (fwd_ready_s) + bwd_ready <= 1'b1; + else if (s_axi_valid) + bwd_ready <= 1'b0; + end + end + end else begin + assign bwd_valid_s = s_axi_valid; + assign bwd_data_s = s_axi_data; + assign bwd_ready_s = fwd_ready_s; + end endgenerate + + assign m_axi_data = fwd_data_s; + assign m_axi_valid = fwd_valid_s; + assign s_axi_ready = bwd_ready_s; + +endmodule diff --git a/adi_library/axi_dmac/bd/bd.tcl b/adi_library/axi_dmac/bd/bd.tcl new file mode 100644 index 00000000..85a51d82 --- /dev/null +++ b/adi_library/axi_dmac/bd/bd.tcl @@ -0,0 +1,206 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_override $ip \ + "ASYNC_CLK_REQ_SRC ASYNC_CLK_SRC_DEST ASYNC_CLK_DEST_REQ ASYNC_CLK_REQ_SG ASYNC_CLK_SRC_SG ASYNC_CLK_DEST_SG" + + bd::mark_propagate_override $ip \ + "DMA_AXI_ADDR_WIDTH" + + # On ZYNQ the core is most likely connected to the AXI3 HP ports so use AXI3 + # as the default. + set family [string tolower [get_property FAMILY [get_property PART [current_project]]]] + if {$family == "zynq"} { + set axi_protocol 1 + } else { + set axi_protocol 0 + } + + foreach dir {SRC DEST} { + # Change the protocol by first enabling the parameter - setting the type to AXI MM + set old [get_property "CONFIG.DMA_TYPE_${dir}" $ip] + set_property "CONFIG.DMA_TYPE_${dir}" "0" $ip + set_property "CONFIG.DMA_AXI_PROTOCOL_${dir}" $axi_protocol $ip + set_property "CONFIG.DMA_TYPE_${dir}" $old $ip + } + + # Change the protocol by first enabling the parameter - enabling the SG transfers + set old [get_property "CONFIG.DMA_SG_TRANSFER" $ip] + set_property "CONFIG.DMA_SG_TRANSFER" "true" $ip + set_property "CONFIG.DMA_AXI_PROTOCOL_SG" $axi_protocol $ip + set_property "CONFIG.DMA_SG_TRANSFER" $old $ip + + # Versions earlier than 2017.3 infer sub-optimal asymmetric memory + # See https://www.xilinx.com/support/answers/69179.html + regexp {^[0-9]+\.[0-9]+} [version -short] short_version + if {[expr $short_version > 2017.2]} { + set_property "CONFIG.ALLOW_ASYM_MEM" 1 $ip + } +} + +proc post_config_ip {cellpath otherinfo} { + set ip [get_bd_cells $cellpath] + + # Update AXI interface properties according to configuration + set max_bytes_per_burst [get_property "CONFIG.MAX_BYTES_PER_BURST" $ip] + set fifo_size [get_property "CONFIG.FIFO_SIZE" $ip] + + foreach dir {"SRC" "DEST"} { + set type [get_property "CONFIG.DMA_TYPE_$dir" $ip] + if {$type != 0} { + continue + } + + set axi_protocol [get_property "CONFIG.DMA_AXI_PROTOCOL_$dir" $ip] + set data_width [get_property "CONFIG.DMA_DATA_WIDTH_$dir" $ip] + set max_beats_per_burst [expr {int(ceil($max_bytes_per_burst * 8.0 / $data_width))}] + + if {$axi_protocol == 0} { + set axi_protocol_str "AXI4" + if {$max_beats_per_burst > 256} { + set max_beats_per_burst 256 + } + } else { + set axi_protocol_str "AXI3" + if {$max_beats_per_burst > 16} { + set max_beats_per_burst 16 + } + } + + set intf [get_bd_intf_pins [format "%s/m_%s_axi" $cellpath [string tolower $dir]]] + set_property CONFIG.PROTOCOL $axi_protocol_str $intf + set_property CONFIG.MAX_BURST_LENGTH $max_beats_per_burst $intf + + # The core issues as many requests as the amount of data the FIFO can hold + if {$dir == "SRC"} { + set_property CONFIG.NUM_WRITE_OUTSTANDING 0 $intf + set_property CONFIG.NUM_READ_OUTSTANDING $fifo_size $intf + } else { + set_property CONFIG.NUM_WRITE_OUTSTANDING $fifo_size $intf + set_property CONFIG.NUM_READ_OUTSTANDING 0 $intf + } + } + + # SG interface configuration + set sg_enabled [get_property CONFIG.DMA_SG_TRANSFER $ip] + if {$sg_enabled == "true"} { + set axi_protocol [get_property "CONFIG.DMA_AXI_PROTOCOL_SG" $ip] + + if {$axi_protocol == 0} { + set axi_protocol_str "AXI4" + set max_beats_per_burst 256 + } else { + set axi_protocol_str "AXI3" + set max_beats_per_burst 16 + } + + set intf [get_bd_intf_pins [format "%s/m_sg_axi" $cellpath]] + set_property CONFIG.PROTOCOL $axi_protocol_str $intf + set_property CONFIG.MAX_BURST_LENGTH $max_beats_per_burst $intf + + set_property CONFIG.NUM_WRITE_OUTSTANDING 0 $intf + set_property CONFIG.NUM_READ_OUTSTANDING 0 $intf + } +} + +proc axi_dmac_detect_async_clk { cellpath ip param_name clk_a clk_b } { + set param_src [get_property "CONFIG.$param_name.VALUE_SRC" $ip] + if {[string equal $param_src "USER"]} { + return; + } + + set clk_domain_a [get_property CONFIG.CLK_DOMAIN $clk_a] + set clk_domain_b [get_property CONFIG.CLK_DOMAIN $clk_b] + set clk_freq_a [get_property CONFIG.FREQ_HZ $clk_a] + set clk_freq_b [get_property CONFIG.FREQ_HZ $clk_b] + set clk_phase_a [get_property CONFIG.PHASE $clk_a] + set clk_phase_b [get_property CONFIG.PHASE $clk_b] + + # Only mark it as sync if we can make sure that it is sync, if the + # relationship of the clocks is unknown mark it as async + if {$clk_domain_a != {} && $clk_domain_b != {} && \ + $clk_domain_a == $clk_domain_b && $clk_freq_a == $clk_freq_b && \ + $clk_phase_a == $clk_phase_b} { + set clk_async 0 + } else { + set clk_async 1 + } + + set_property "CONFIG.$param_name" $clk_async $ip + +# if {$clk_async == 0} { +# bd::send_msg -of $cellpath -type INFO -msg_id 1 -text "$clk_a and $clk_b are synchronous" +# } else { +# bd::send_msg -of $cellpath -type INFO -msg_id 1 -text "$clk_a and $clk_b are asynchronous" +# } +} + +proc propagate {cellpath otherinfo} { + set ip [get_bd_cells $cellpath] + set src_type [get_property CONFIG.DMA_TYPE_SRC $ip] + set dest_type [get_property CONFIG.DMA_TYPE_DEST $ip] + set sg_enabled [get_property CONFIG.DMA_SG_TRANSFER $ip] + + set req_clk [get_bd_pins "$ip/s_axi_aclk"] + + if {$src_type == 2} { + set src_clk [get_bd_pins "$ip/fifo_wr_clk"] + } elseif {$src_type == 1} { + set src_clk [get_bd_pins "$ip/s_axis_aclk"] + } else { + set src_clk [get_bd_pins "$ip/m_src_axi_aclk"] + } + + if {$dest_type == 2} { + set dest_clk [get_bd_pins "$ip/fifo_rd_clk"] + } elseif {$dest_type == 1} { + set dest_clk [get_bd_pins "$ip/m_axis_aclk"] + } else { + set dest_clk [get_bd_pins "$ip/m_dest_axi_aclk"] + } + + axi_dmac_detect_async_clk $cellpath $ip "ASYNC_CLK_REQ_SRC" $req_clk $src_clk + axi_dmac_detect_async_clk $cellpath $ip "ASYNC_CLK_SRC_DEST" $src_clk $dest_clk + axi_dmac_detect_async_clk $cellpath $ip "ASYNC_CLK_DEST_REQ" $dest_clk $req_clk + + if {$sg_enabled == "true"} { + set sg_clk [get_bd_pins "$ip/m_sg_axi_aclk"] + axi_dmac_detect_async_clk $cellpath $ip "ASYNC_CLK_REQ_SG" $req_clk $sg_clk + axi_dmac_detect_async_clk $cellpath $ip "ASYNC_CLK_SRC_SG" $src_clk $sg_clk + axi_dmac_detect_async_clk $cellpath $ip "ASYNC_CLK_DEST_SG" $dest_clk $sg_clk + } +} + +proc post_propagate {cellpath otherinfo} { + set ip [get_bd_cells $cellpath] + + set addr_width 16 + + foreach dir {"SRC" "DEST"} { + set type [get_property "CONFIG.DMA_TYPE_$dir" $ip] + if {$type != 0} { + continue + } + + set intf [get_bd_intf_pins [format "%s/m_%s_axi" $cellpath [string tolower $dir]]] + set addr_segs [get_bd_addr_segs -of_objects [get_bd_addr_spaces $intf]] + + if {$addr_segs != {}} { + foreach addr_seg $addr_segs { + set range [get_property "range" $addr_seg] + set offset [get_property "offset" $addr_seg] + set addr_width [expr max(int(ceil(log($range - 1 + $offset) / log(2))), $addr_width)] + } + } else { + set addr_width 32 + } + + } + + set_property "CONFIG.DMA_AXI_ADDR_WIDTH" $addr_width $ip +} diff --git a/adi_library/axi_dmac/component.xml b/adi_library/axi_dmac/component.xml new file mode 100644 index 00000000..c8c7f6af --- /dev/null +++ b/adi_library/axi_dmac/component.xml @@ -0,0 +1,6841 @@ + + + analog.com + user + axi_dmac + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + m_dest_axi + + + + + + + + + AWID + + + m_dest_axi_awid + + + + + AWADDR + + + m_dest_axi_awaddr + + + + + AWLEN + + + m_dest_axi_awlen + + + + + AWSIZE + + + m_dest_axi_awsize + + + + + AWBURST + + + m_dest_axi_awburst + + + + + AWLOCK + + + m_dest_axi_awlock + + + + + AWCACHE + + + m_dest_axi_awcache + + + + + AWPROT + + + m_dest_axi_awprot + + + + + AWVALID + + + m_dest_axi_awvalid + + + + + AWREADY + + + m_dest_axi_awready + + + + + WID + + + m_dest_axi_wid + + + + + WDATA + + + m_dest_axi_wdata + + + + + WSTRB + + + m_dest_axi_wstrb + + + + + WLAST + + + m_dest_axi_wlast + + + + + WVALID + + + m_dest_axi_wvalid + + + + + WREADY + + + m_dest_axi_wready + + + + + BID + + + m_dest_axi_bid + + + + + BRESP + + + m_dest_axi_bresp + + + + + BVALID + + + m_dest_axi_bvalid + + + + + BREADY + + + m_dest_axi_bready + + + + + ARID + + + m_dest_axi_arid + + + + + ARADDR + + + m_dest_axi_araddr + + + + + ARLEN + + + m_dest_axi_arlen + + + + + ARSIZE + + + m_dest_axi_arsize + + + + + ARBURST + + + m_dest_axi_arburst + + + + + ARLOCK + + + m_dest_axi_arlock + + + + + ARCACHE + + + m_dest_axi_arcache + + + + + ARPROT + + + m_dest_axi_arprot + + + + + ARVALID + + + m_dest_axi_arvalid + + + + + ARREADY + + + m_dest_axi_arready + + + + + RID + + + m_dest_axi_rid + + + + + RDATA + + + m_dest_axi_rdata + + + + + RRESP + + + m_dest_axi_rresp + + + + + RLAST + + + m_dest_axi_rlast + + + + + RVALID + + + m_dest_axi_rvalid + + + + + RREADY + + + m_dest_axi_rready + + + + + + SUPPORTS_NARROW_BURST + 0 + + + + + + true + + + + + + m_sg_axi + + + + + + + + + AWID + + + m_sg_axi_awid + + + + + AWADDR + + + m_sg_axi_awaddr + + + + + AWLEN + + + m_sg_axi_awlen + + + + + AWSIZE + + + m_sg_axi_awsize + + + + + AWBURST + + + m_sg_axi_awburst + + + + + AWLOCK + + + m_sg_axi_awlock + + + + + AWCACHE + + + m_sg_axi_awcache + + + + + AWPROT + + + m_sg_axi_awprot + + + + + AWVALID + + + m_sg_axi_awvalid + + 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request_arb.v + verilogSource + + + request_generator.v + verilogSource + + + resp.vh + verilogSource + true + + + response_generator.v + verilogSource + + + response_handler.v + verilogSource + + + splitter.v + verilogSource + + + src_axi_mm.v + verilogSource + + + src_axi_stream.v + verilogSource + + + src_fifo_inf.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + bd/bd.tcl + tclSource + + + axi_dmac.v + verilogSource + CHECKSUM_b602bf53 + + + + xilinx_anylanguagesynthesis_analog_com_user_util_axis_fifo_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + axi_dmac_pkg_sv.ttcl + ttcl + + + ../common/ad_mem_asym.v + verilogSource + + + inc_id.vh + verilogSource + true + + + address_generator.v + verilogSource + + + axi_dmac_burst_memory.v + verilogSource + + + axi_dmac_regmap.v + verilogSource + + + axi_dmac_regmap_request.v + verilogSource + + + axi_dmac_reset_manager.v + verilogSource + + + axi_dmac_resize_dest.v + verilogSource + + + axi_dmac_resize_src.v + verilogSource + + + axi_dmac_response_manager.v + verilogSource + + + axi_dmac_transfer.v + verilogSource + + + axi_register_slice.v + verilogSource + + + data_mover.v + verilogSource + + + dest_axi_mm.v + verilogSource + + + dest_axi_stream.v + verilogSource + + + dest_fifo_inf.v + verilogSource + + + dmac_2d_transfer.v + verilogSource + + + dmac_sg.v + verilogSource + + + request_arb.v + verilogSource + + + request_generator.v + verilogSource + + + resp.vh + verilogSource + true + + + response_generator.v + verilogSource + + + response_handler.v + verilogSource + + + splitter.v + verilogSource + + + src_axi_mm.v + verilogSource + + + src_axi_stream.v + verilogSource + + + src_fifo_inf.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + bd/bd.tcl + tclSource + + + axi_dmac.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_axis_fifo_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axi_dmac_v1_0.tcl + tclSource + CHECKSUM_57e931f4 + XGUI_VERSION_2 + + + + xilinx_xpgui_analog_com_user_util_axis_fifo_1_0__ref_view_fileset + + + + + + + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + xilinx_blockdiagram_analog_com_user_util_axis_fifo_1_0__ref_view_fileset + + + + + + + + xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + xilinx_utilityxitfiles_view_fileset + + gui/axi_dmac_v1_0.gtcl + GTCL + + + + ADI AXI DMA Controller + + + ID + Core ID + 0 + + + DMA_DATA_WIDTH_SRC + Bus Width + 64 + + + DMA_DATA_WIDTH_DEST + Bus Width + 64 + + + DMA_DATA_WIDTH_SG + Bus Width + 64 + + + + false + + + + + + DMA_LENGTH_WIDTH + DMA Transfer Length Register Width + 24 + + + DMA_2D_TRANSFER + 2D Transfer Support + false + + + DMA_SG_TRANSFER + SG Transfer Support + false + + + ASYNC_CLK_REQ_SRC + Request and Source Clock Asynchronous + true + + + ASYNC_CLK_SRC_DEST + Source and Destination Clock Asynchronous + true + + + ASYNC_CLK_DEST_REQ + Destination and Request Clock Asynchronous + true + + + ASYNC_CLK_REQ_SG + Request and Scatter-Gather Clock Asynchronous + true + + + ASYNC_CLK_SRC_SG + Source and Scatter-Gather Clock Asynchronous + true + + + ASYNC_CLK_DEST_SG + Destination and Scatter-Gather Clock Asynchronous + true + + + AXI_SLICE_DEST + Insert Register Slice + false + + + AXI_SLICE_SRC + Insert Register Slice + false + + + SYNC_TRANSFER_START + Transfer Start Synchronization Support + false + + + + true + + + + + + CYCLIC + Cyclic Transfer Support + false + + + DMA_AXI_PROTOCOL_DEST + AXI Protocol + 0 + + + + true + + + + + + DMA_AXI_PROTOCOL_SRC + AXI Protocol + 0 + + + + false + + + + + + DMA_AXI_PROTOCOL_SG + AXI Protocol + 0 + + + + false + + + + + + DMA_TYPE_DEST + Type + 0 + + + DMA_TYPE_SRC + Type + 2 + + + DMA_AXI_ADDR_WIDTH + DMA AXI Address Width + 32 + + + MAX_BYTES_PER_BURST + Maximum Bytes per Burst + 128 + + + FIFO_SIZE + Store-and-Forward Memory Size (In Bursts) + 8 + + + AXI_ID_WIDTH_SRC + Axi Id Width Src + 1 + + + AXI_ID_WIDTH_DEST + Axi Id Width Dest + 1 + + + AXI_ID_WIDTH_SG + Axi Id Width Sg + 1 + + + DMA_AXIS_ID_W + Dma Axis Id W + 8 + + + DMA_AXIS_DEST_W + Dma Axis Dest W + 4 + + + DISABLE_DEBUG_REGISTERS + Disable Debug Registers + false + + + ENABLE_DIAGNOSTICS_IF + Enable Diagnostics Interface + false + + + ALLOW_ASYM_MEM + Allow Asym Mem + 0 + + + CACHE_COHERENT_DEST + Assume cache coherent + true + + + + true + + + + + + Component_Name + axi_dmac_v1_0 + + + + + + virtex7 + + + /Analog_Devices + + ADI AXI DMA Controller + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_dmac + 1 + 2024-01-14T03:46:09Z + + + 2023.2.1 + + + + + + + + diff --git a/adi_library/axi_dmac/data_mover.v b/adi_library/axi_dmac/data_mover.v new file mode 100644 index 00000000..10980008 --- /dev/null +++ b/adi_library/axi_dmac/data_mover.v @@ -0,0 +1,272 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module data_mover #( + + parameter ID_WIDTH = 3, + parameter DATA_WIDTH = 64, + parameter BEATS_PER_BURST_WIDTH = 4, + parameter ALLOW_ABORT = 0 +) ( + input clk, + input resetn, + + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, + input eot, + + output rewind_req_valid, + input rewind_req_ready, + output [ID_WIDTH+3-1:0] rewind_req_data, + + output reg bl_valid = 'b0, + input bl_ready, + output reg [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length, + + output block_descr_to_dst, + + output [ID_WIDTH-1:0] source_id, + output source_eot, + + output xfer_req, + + output s_axi_ready, + input s_axi_valid, + input [DATA_WIDTH-1:0] s_axi_data, + input s_axi_last, + input s_axi_sync, + + output m_axi_valid, + output [DATA_WIDTH-1:0] m_axi_data, + output m_axi_last, + output m_axi_partial_burst, + + input req_valid, + output req_ready, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + input req_sync_transfer_start, + input req_xlast +); + + localparam BEAT_COUNTER_MAX = {BEATS_PER_BURST_WIDTH{1'b1}}; + +`include "inc_id.vh" + + reg [BEATS_PER_BURST_WIDTH-1:0] last_burst_length = 'h00; + reg [BEATS_PER_BURST_WIDTH-1:0] beat_counter = 'h00; + reg [BEATS_PER_BURST_WIDTH-1:0] beat_counter_minus_one = 'h0; + reg [ID_WIDTH-1:0] id = 'h00; + reg [ID_WIDTH-1:0] id_next = 'h00; + + reg pending_burst = 1'b0; + reg active = 1'b0; + reg last_eot = 1'b0; + reg last_non_eot = 1'b0; + + reg needs_sync = 1'b0; + wire has_sync = ~needs_sync | s_axi_sync; + + wire s_axi_sync_valid = has_sync & s_axi_valid; + wire transfer_abort_s; + + wire last_load; + wire last; + wire early_tlast; + + assign xfer_req = active; + + assign response_id = id; + + assign source_id = id; + assign source_eot = eot || early_tlast; + + assign last = eot ? last_eot : last_non_eot; + + assign s_axi_ready = (pending_burst & active) & ~transfer_abort_s; + assign m_axi_valid = s_axi_sync_valid & s_axi_ready; + assign m_axi_data = s_axi_data; + assign m_axi_last = last || early_tlast; + assign m_axi_partial_burst = early_tlast; + + assign block_descr_to_dst = transfer_abort_s; + + generate if (ALLOW_ABORT == 1) begin + wire programmed_last; + + reg transfer_abort = 1'b0; + reg req_xlast_d = 1'b0; + reg [1:0] transfer_id = 2'b0; + + assign programmed_last = (last == 1'b1 && eot == 1'b1 && req_xlast_d == 1'b1); + /* + * A 'last' on the external interface indicates the end of an packet. If such a + * 'last' indicator is observed before the end of the current transfer stop + * accepting data on the external interface until a new descriptor is + * received that is the first segment of a transfer. + */ + always @(posedge clk) begin + if (resetn == 1'b0) begin + transfer_abort <= 1'b0; + end else if (req_valid == 1'b1 && req_ready == 1'b1 && req_xlast_d == 1'b1) begin + transfer_abort <= 1'b0; + end else if (m_axi_valid == 1'b1) begin + if (programmed_last == 1'b1) begin + transfer_abort <= 1'b0; + end else if (s_axi_last == 1'b1) begin + transfer_abort <= 1'b1; + end + end + end + + always @(posedge clk) begin + if (req_ready == 1'b1 && req_valid == 1'b1) begin + req_xlast_d <= req_xlast; + end + end + + assign transfer_abort_s = transfer_abort; + assign early_tlast = (s_axi_ready == 1'b1) && (m_axi_valid == 1'b1) && + (s_axi_last == 1'b1) && (programmed_last == 1'b0); + + assign rewind_req_valid = early_tlast; + assign rewind_req_data = {transfer_id,req_xlast_d,id_next}; + + // The width of the id must fit the number of transfers that can be in flight + // in the burst memory + always @(posedge clk) begin + if (resetn == 1'b0) begin + transfer_id <= 2'b0; + end else if (req_valid == 1'b1 && req_ready == 1'b1) begin + transfer_id <= transfer_id + 1'b1; + end + end + + end else begin + assign transfer_abort_s = 1'b0; + assign early_tlast = 1'b0; + assign rewind_req_valid = 1'b0; + assign rewind_req_data = 'h0; + end endgenerate + + /* + * If req_sync_transfer_start is set all incoming beats will be skipped until + * one has s_axi_sync set. This will be the first beat that is passsed through. + */ + always @(posedge clk) begin + if (req_ready == 1'b1) begin + needs_sync <= req_sync_transfer_start; + end else if (m_axi_valid == 1'b1) begin + needs_sync <= 1'b0; + end + end + + // If we want to support zero delay between transfers we have to assert + // req_ready on the same cycle on which the last load happens. + // In case early tlast happens accept the new descriptor only when the rewind + // request got accepted. + // In case the data mover is not active accept a new descriptor only when the + // upstream logic incremented its id (pending_burst is set). + assign last_load = m_axi_valid && last_eot && eot; + assign req_ready = (last_load && ~early_tlast) || + ((~active && ~transfer_abort_s) && pending_burst) || + (transfer_abort_s && rewind_req_ready); + + always @(posedge clk) begin + if (req_ready) begin + last_eot <= req_last_burst_length == 'h0; + last_non_eot <= 1'b0; + beat_counter <= 'h1; + end else if (m_axi_valid == 1'b1) begin + last_eot <= beat_counter == last_burst_length; + last_non_eot <= beat_counter == BEAT_COUNTER_MAX; + beat_counter <= beat_counter + 1'b1; + end + end + + always @(posedge clk) begin + if (req_ready) + last_burst_length <= req_last_burst_length; + end + + always @(posedge clk) begin + if (req_ready) begin + beat_counter_minus_one <= 'h0; + end else if (m_axi_valid == 1'b1) begin + beat_counter_minus_one <= beat_counter; + end + end + + always @(posedge clk) begin + if (last_load || early_tlast) begin + bl_valid <= 1'b1; + measured_last_burst_length <= beat_counter_minus_one; + end else if (bl_ready) begin + bl_valid <= 1'b0; + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + active <= 1'b0; + end else if (req_valid == 1'b1 && req_ready == 1'b1) begin + active <= 1'b1; + end else if (last_load == 1'b1) begin + active <= 1'b0; + end + end + + always @(*) + begin + if (m_axi_valid == 1'b1 && (last == 1'b1 || early_tlast == 1'b1)) + id_next <= inc_id(id); + else + id_next <= id; + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + id <= 'h0; + end else begin + id <= id_next; + end + end + + always @(posedge clk) begin + pending_burst <= id_next != request_id; + end + +endmodule diff --git a/adi_library/axi_dmac/dest_axi_mm.v b/adi_library/axi_dmac/dest_axi_mm.v new file mode 100644 index 00000000..b826a350 --- /dev/null +++ b/adi_library/axi_dmac/dest_axi_mm.v @@ -0,0 +1,190 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module dest_axi_mm #( + + parameter ID_WIDTH = 3, + parameter DMA_DATA_WIDTH = 64, + parameter DMA_ADDR_WIDTH = 32, + parameter BYTES_PER_BEAT_WIDTH = $clog2(DMA_DATA_WIDTH/8), + parameter BEATS_PER_BURST_WIDTH = 4, + parameter MAX_BYTES_PER_BURST = 128, + parameter BYTES_PER_BURST_WIDTH = $clog2(MAX_BYTES_PER_BURST), + parameter AXI_LENGTH_WIDTH = 8, + parameter CACHE_COHERENT = 0 +) ( + input m_axi_aclk, + input m_axi_aresetn, + + input req_valid, + output req_ready, + input [DMA_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH] req_address, + + input bl_valid, + output bl_ready, + input [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length, + + input enable, + output enabled, + + output response_valid, + input response_ready, + output [1:0] response_resp, + output response_resp_eot, + output response_resp_partial, + output [BYTES_PER_BURST_WIDTH-1:0] response_data_burst_length, + + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, + + output [ID_WIDTH-1:0] address_id, + input address_eot, + input response_eot, + + input fifo_valid, + output fifo_ready, + input [DMA_DATA_WIDTH-1:0] fifo_data, + input [DMA_DATA_WIDTH/8-1:0] fifo_strb, + input fifo_last, + + input [BYTES_PER_BURST_WIDTH-1:0] dest_burst_info_length, + input dest_burst_info_partial, + input [ID_WIDTH-1:0] dest_burst_info_id, + input dest_burst_info_write, + // Write address + input m_axi_awready, + output m_axi_awvalid, + output [DMA_ADDR_WIDTH-1:0] m_axi_awaddr, + output [AXI_LENGTH_WIDTH-1:0] m_axi_awlen, + output [ 2:0] m_axi_awsize, + output [ 1:0] m_axi_awburst, + output [ 2:0] m_axi_awprot, + output [ 3:0] m_axi_awcache, + + // Write data + output [DMA_DATA_WIDTH-1:0] m_axi_wdata, + output [(DMA_DATA_WIDTH/8)-1:0] m_axi_wstrb, + input m_axi_wready, + output m_axi_wvalid, + output m_axi_wlast, + + // Write response + input m_axi_bvalid, + input [ 1:0] m_axi_bresp, + output m_axi_bready +); + + wire address_enabled; + + address_generator #( + .ID_WIDTH(ID_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), + .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH), + .DMA_DATA_WIDTH(DMA_DATA_WIDTH), + .LENGTH_WIDTH(AXI_LENGTH_WIDTH), + .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH), + .CACHE_COHERENT(CACHE_COHERENT) + ) i_addr_gen ( + .clk(m_axi_aclk), + .resetn(m_axi_aresetn), + + .enable(enable), + .enabled(address_enabled), + + .id(address_id), + .request_id(request_id), + + .req_valid(req_valid), + .req_ready(req_ready), + .req_address(req_address), + + .bl_valid(bl_valid), + .bl_ready(bl_ready), + .measured_last_burst_length(measured_last_burst_length), + + .eot(address_eot), + + .addr_ready(m_axi_awready), + .addr_valid(m_axi_awvalid), + .addr(m_axi_awaddr), + .len(m_axi_awlen), + .size(m_axi_awsize), + .burst(m_axi_awburst), + .prot(m_axi_awprot), + .cache(m_axi_awcache)); + + assign m_axi_wvalid = fifo_valid; + assign fifo_ready = m_axi_wready; + assign m_axi_wlast = fifo_last; + assign m_axi_wdata = fifo_data; + assign m_axi_wstrb = fifo_strb; + + response_handler #( + .ID_WIDTH(ID_WIDTH) + ) i_response_handler ( + .clk(m_axi_aclk), + .resetn(m_axi_aresetn), + .bvalid(m_axi_bvalid), + .bready(m_axi_bready), + .bresp(m_axi_bresp), + + .enable(address_enabled), + .enabled(enabled), + + .id(response_id), + .request_id(address_id), + + .eot(response_eot), + + .resp_valid(response_valid), + .resp_ready(response_ready), + .resp_resp(response_resp), + .resp_eot(response_resp_eot)); + + reg [BYTES_PER_BURST_WIDTH+1-1:0] bl_mem [0:2**(ID_WIDTH)-1]; + + assign {response_resp_partial, + response_data_burst_length} = bl_mem[response_id]; + + always @(posedge m_axi_aclk) begin + if (dest_burst_info_write) begin + bl_mem[dest_burst_info_id] <= {dest_burst_info_partial, + dest_burst_info_length}; + end + end + +endmodule diff --git a/adi_library/axi_dmac/dest_axi_stream.v b/adi_library/axi_dmac/dest_axi_stream.v new file mode 100644 index 00000000..2f38f9e1 --- /dev/null +++ b/adi_library/axi_dmac/dest_axi_stream.v @@ -0,0 +1,155 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module dest_axi_stream #( + + parameter ID_WIDTH = 3, + parameter S_AXIS_DATA_WIDTH = 64, + parameter BEATS_PER_BURST_WIDTH = 4 +) ( + input s_axis_aclk, + input s_axis_aresetn, + + input enable, + output enabled, + output xfer_req, + + output [ID_WIDTH-1:0] response_id, + output [ID_WIDTH-1:0] data_id, + input data_eot, + input response_eot, + + input m_axis_ready, + output m_axis_valid, + output [S_AXIS_DATA_WIDTH-1:0] m_axis_data, + output m_axis_last, + + output fifo_ready, + input fifo_valid, + input [S_AXIS_DATA_WIDTH-1:0] fifo_data, + input fifo_last, + + input req_valid, + output req_ready, + input req_xlast, + + output response_valid, + input response_ready, + output response_resp_eot, + output [1:0] response_resp +); + +`include "inc_id.vh" + + reg data_enabled = 1'b0; + reg req_xlast_d = 1'b0; + reg active = 1'b0; + + reg [ID_WIDTH-1:0] id = 'h0; + + // Last beat of the burst + wire fifo_last_beat; + // Last beat of the segment + wire fifo_eot_beat; + + // fifo_last == 1'b1 implies fifo_valid == 1'b1 + assign fifo_last_beat = fifo_ready & fifo_last; + assign fifo_eot_beat = fifo_last_beat & data_eot; + + assign req_ready = fifo_eot_beat | ~active; + assign data_id = id; + assign xfer_req = active; + + assign m_axis_valid = fifo_valid & active; + assign fifo_ready = m_axis_ready & active; + assign m_axis_last = req_xlast_d & fifo_last & data_eot; + assign m_axis_data = fifo_data; + + always @(posedge s_axis_aclk) begin + if (s_axis_aresetn == 1'b0) begin + data_enabled <= 1'b0; + end else if (enable == 1'b1) begin + data_enabled <= 1'b1; + end else if (m_axis_valid == 1'b0 || m_axis_ready == 1'b1) begin + data_enabled <= 1'b0; + end + end + + always @(posedge s_axis_aclk) begin + if (req_ready == 1'b1) begin + req_xlast_d <= req_xlast; + end + end + + always @(posedge s_axis_aclk) begin + if (s_axis_aresetn == 1'b0) begin + active <= 1'b0; + end else if (req_valid == 1'b1) begin + active <= 1'b1; + end else if (fifo_eot_beat == 1'b1) begin + active <= 1'b0; + end + end + + always @(posedge s_axis_aclk) begin + if (s_axis_aresetn == 1'b0) begin + id <= 'h00; + end else if (fifo_last_beat == 1'b1) begin + id <= inc_id(id); + end + end + + response_generator #( + .ID_WIDTH(ID_WIDTH) + ) i_response_generator ( + .clk(s_axis_aclk), + .resetn(s_axis_aresetn), + + .enable(data_enabled), + .enabled(enabled), + + .request_id(id), + .response_id(response_id), + + .eot(response_eot), + + .resp_valid(response_valid), + .resp_ready(response_ready), + .resp_eot(response_resp_eot), + .resp_resp(response_resp)); + +endmodule diff --git a/adi_library/axi_dmac/dest_fifo_inf.v b/adi_library/axi_dmac/dest_fifo_inf.v new file mode 100644 index 00000000..65b9fdca --- /dev/null +++ b/adi_library/axi_dmac/dest_fifo_inf.v @@ -0,0 +1,143 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module dest_fifo_inf #( + + parameter ID_WIDTH = 3, + parameter DATA_WIDTH = 64, + parameter BEATS_PER_BURST_WIDTH = 4 +) ( + input clk, + input resetn, + + input enable, + output enabled, + + input req_valid, + output req_ready, + + output [ID_WIDTH-1:0] response_id, + output reg [ID_WIDTH-1:0] data_id = 'h0, + input data_eot, + input response_eot, + + input en, + output reg [DATA_WIDTH-1:0] dout, + output reg valid, + output reg underflow, + + output xfer_req, + + output fifo_ready, + input fifo_valid, + input [DATA_WIDTH-1:0] fifo_data, + input fifo_last, + + output response_valid, + input response_ready, + output response_resp_eot, + output [1:0] response_resp +); + +`include "inc_id.vh" + + reg active = 1'b0; + + // Last beat of the burst + wire fifo_last_beat; + // Last beat of the segment + wire fifo_eot_beat; + + assign enabled = enable; + assign fifo_ready = en & (fifo_valid | ~enable); + + // fifo_last == 1'b1 implies fifo_valid == 1'b1 + assign fifo_last_beat = fifo_ready & fifo_last; + assign fifo_eot_beat = fifo_last_beat & data_eot; + + assign req_ready = fifo_eot_beat | ~active; + assign xfer_req = active; + + always @(posedge clk) begin + if (en) begin + dout <= fifo_valid ? fifo_data : {DATA_WIDTH{1'b0}}; + valid <= fifo_valid & enable; + underflow <= ~(fifo_valid & enable); + end else begin + valid <= 1'b0; + underflow <= 1'b0; + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + data_id <= 'h00; + end else if (fifo_last_beat == 1'b1) begin + data_id <= inc_id(data_id); + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + active <= 1'b0; + end else if (req_valid == 1'b1) begin + active <= 1'b1; + end else if (fifo_eot_beat == 1'b1) begin + active <= 1'b0; + end + end + + response_generator #( + .ID_WIDTH(ID_WIDTH) + ) i_response_generator ( + .clk(clk), + .resetn(resetn), + + .enable(enable), + .enabled(), + + .request_id(data_id), + .response_id(response_id), + + .eot(response_eot), + + .resp_valid(response_valid), + .resp_ready(response_ready), + .resp_eot(response_resp_eot), + .resp_resp(response_resp)); + +endmodule diff --git a/adi_library/axi_dmac/dmac_2d_transfer.v b/adi_library/axi_dmac/dmac_2d_transfer.v new file mode 100644 index 00000000..cf87ca39 --- /dev/null +++ b/adi_library/axi_dmac/dmac_2d_transfer.v @@ -0,0 +1,198 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module dmac_2d_transfer #( + + parameter DMA_AXI_ADDR_WIDTH = 32, + parameter DMA_LENGTH_WIDTH = 24, + parameter BYTES_PER_BURST_WIDTH = 7, + parameter BYTES_PER_BEAT_WIDTH_SRC = 3, + parameter BYTES_PER_BEAT_WIDTH_DEST = 3 +) ( + input req_aclk, + input req_aresetn, + + input req_valid, + output reg req_ready, + + input [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address, + input [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] req_src_address, + input [DMA_LENGTH_WIDTH-1:0] req_x_length, + input [DMA_LENGTH_WIDTH-1:0] req_y_length, + input [DMA_LENGTH_WIDTH-1:0] req_dest_stride, + input [DMA_LENGTH_WIDTH-1:0] req_src_stride, + input req_sync_transfer_start, + input req_last, + + output reg req_eot, + output reg [BYTES_PER_BURST_WIDTH-1:0] req_measured_burst_length, + output reg req_response_partial, + output reg req_response_valid, + input req_response_ready, + + input out_abort_req, + + output reg out_req_valid, + input out_req_ready, + output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] out_req_dest_address, + output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] out_req_src_address, + output [DMA_LENGTH_WIDTH-1:0] out_req_length, + output reg out_req_sync_transfer_start, + output out_req_last, + + input out_eot, + input [BYTES_PER_BURST_WIDTH-1:0] out_measured_burst_length, + input out_response_partial, + input out_response_valid, + output reg out_response_ready = 1'b1 +); + + // internal registers + + reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] dest_address = 'h00; + reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] src_address = 'h00; + reg [DMA_LENGTH_WIDTH-1:0] x_length = 'h00; + reg [DMA_LENGTH_WIDTH-1:0] y_length = 'h00; + reg [DMA_LENGTH_WIDTH-1:0] dest_stride = 'h0; + reg [DMA_LENGTH_WIDTH-1:0] src_stride = 'h00; + + reg gen_last = 'h0; + + reg [1:0] req_id = 'h00; + reg [1:0] eot_id = 'h00; + reg [3:0] last_req = 'h00; + + // internal signals + + wire out_last; + + // signal name changes + + assign out_req_dest_address = dest_address; + assign out_req_src_address = src_address; + assign out_req_length = x_length; + assign out_last = y_length == 'h00; + + always @(posedge req_aclk) begin + if (req_aresetn == 1'b0) begin + req_id <= 2'b0; + eot_id <= 2'b0; + req_eot <= 1'b0; + end else begin + if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin + req_id <= req_id + 1'b1; + end + + if (out_eot == 1'b1 && out_response_valid == 1'b1 && out_response_ready == 1'b1) begin + eot_id <= eot_id + 1'b1; + req_eot <= last_req[eot_id]; + end else begin + req_eot <= 1'b0; + end + end + end + + always @(posedge req_aclk) begin + if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin + last_req[req_id] <= out_last; + end + end + + always @(posedge req_aclk) begin + if (out_response_valid == 1'b1 && out_response_ready == 1'b1) begin + req_measured_burst_length <= out_measured_burst_length; + req_response_partial <= out_response_partial; + end + end + + always @(posedge req_aclk) begin + if (out_response_valid == 1'b1 && out_response_ready == 1'b1) begin + req_response_valid <= 1'b1; + end else if (req_response_ready == 1'b1) begin + req_response_valid <= 1'b0; + end + end + + always @(posedge req_aclk) begin + if (req_aresetn == 1'b0) begin + out_response_ready <= 1'b1; + end else if (out_response_ready == 1'b1) begin + out_response_ready <= ~out_response_valid; + end else if (req_response_ready == 1'b1) begin + out_response_ready <= 1'b1; + end + end + + always @(posedge req_aclk) begin + if (req_ready == 1'b1 && req_valid == 1'b1) begin + dest_address <= req_dest_address; + src_address <= req_src_address; + x_length <= req_x_length; + y_length <= req_y_length; + dest_stride <= req_dest_stride; + src_stride <= req_src_stride; + out_req_sync_transfer_start <= req_sync_transfer_start; + gen_last <= req_last; + end else if (out_abort_req == 1'b1) begin + y_length <= 0; + end else if (out_req_valid == 1'b1 && out_req_ready == 1'b1) begin + dest_address <= dest_address + dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST]; + src_address <= src_address + src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC]; + y_length <= y_length - 1'b1; + out_req_sync_transfer_start <= 1'b0; + end + end + + always @(posedge req_aclk) begin + if (req_aresetn == 1'b0) begin + req_ready <= 1'b1; + out_req_valid <= 1'b0; + end else begin + if (req_ready == 1'b1 && req_valid == 1'b1) begin + req_ready <= 1'b0; + out_req_valid <= 1'b1; + end else if (out_req_valid == 1'b1 && out_req_ready == 1'b1 && + out_last == 1'b1) begin + out_req_valid <= 1'b0; + req_ready <= 1'b1; + end + end + end + + assign out_req_last = out_last & gen_last; + +endmodule diff --git a/adi_library/axi_dmac/dmac_sg.v b/adi_library/axi_dmac/dmac_sg.v new file mode 100644 index 00000000..03c676f9 --- /dev/null +++ b/adi_library/axi_dmac/dmac_sg.v @@ -0,0 +1,336 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module dmac_sg #( + parameter DMA_AXI_ADDR_WIDTH = 32, + parameter DMA_DATA_WIDTH = 64, + parameter DMA_LENGTH_WIDTH = 24, + parameter AXI_LENGTH_WIDTH = 8, + parameter BYTES_PER_BEAT_WIDTH_DEST = 3, + parameter BYTES_PER_BEAT_WIDTH_SRC = 3, + parameter BYTES_PER_BEAT_WIDTH_SG = 3, + parameter ASYNC_CLK_REQ_SG = 1 +) ( + input req_clk, + input req_resetn, + input req_enable, + + output sg_clk, + input sg_resetn, + output sg_ext_resetn, + input sg_enable, + output sg_enabled, + + input req_in_valid, + output req_in_ready, + + output req_out_valid, + input req_out_ready, + + output resp_out_eot, + input resp_in_valid, + + input [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SG] req_desc_address, + + output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] out_dest_address, + output [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] out_src_address, + output [DMA_LENGTH_WIDTH-1:0] out_x_length, + output [DMA_LENGTH_WIDTH-1:0] out_y_length, + output [DMA_LENGTH_WIDTH-1:0] out_dest_stride, + output [DMA_LENGTH_WIDTH-1:0] out_src_stride, + output [31:0] resp_out_id, + + // Master AXI interface + input m_axi_aclk, + input m_axi_aresetn, + + // Read address + input m_axi_arready, + output m_axi_arvalid, + output [DMA_AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output [AXI_LENGTH_WIDTH-1:0] m_axi_arlen, + output [ 2:0] m_axi_arsize, + output [ 1:0] m_axi_arburst, + output [ 2:0] m_axi_arprot, + output [ 3:0] m_axi_arcache, + + // Read data and response + input [DMA_DATA_WIDTH-1:0] m_axi_rdata, + input m_axi_rlast, + output m_axi_rready, + input m_axi_rvalid, + input [ 1:0] m_axi_rresp +); + + localparam STATE_IDLE = 0; + localparam STATE_SEND_ADDR = 1; + localparam STATE_RECV_DESC = 2; + localparam STATE_DESC_READY = 3; + + localparam MASK_LAST_HWDESC = 1 << 0; + localparam MASK_EOT_IRQ = 1 << 1; + + localparam DMA_ADDRESS_WIDTH_DEST = DMA_AXI_ADDR_WIDTH - BYTES_PER_BEAT_WIDTH_DEST; + localparam DMA_ADDRESS_WIDTH_SRC = DMA_AXI_ADDR_WIDTH - BYTES_PER_BEAT_WIDTH_SRC; + localparam DMA_ADDRESS_WIDTH_SG = DMA_AXI_ADDR_WIDTH - BYTES_PER_BEAT_WIDTH_SG; + localparam DMA_DESCRIPTOR_WIDTH = DMA_ADDRESS_WIDTH_DEST + DMA_ADDRESS_WIDTH_SRC + 4*DMA_LENGTH_WIDTH; + + wire [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SG] first_desc_address; + reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] dest_addr; + reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] src_addr; + reg [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SG] next_desc_addr; + reg [DMA_LENGTH_WIDTH-1:0] x_length; + reg [DMA_LENGTH_WIDTH-1:0] y_length; + reg [DMA_LENGTH_WIDTH-1:0] dest_stride; + reg [DMA_LENGTH_WIDTH-1:0] src_stride; + + reg [1:0] hwdesc_state; + reg [2:0] hwdesc_counter; + reg [1:0] hwdesc_flags; + reg [31:0] hwdesc_id; + + wire sg_in_valid; + wire sg_in_ready; + wire sg_out_valid; + wire sg_out_ready; + wire fetch_valid; + wire fetch_ready; + wire fifo_in_valid; + wire fifo_in_ready; + wire fifo_out_valid; + wire fifo_out_ready; + wire [32:0] fifo_in_data; + wire [32:0] fifo_out_data; + + assign sg_clk = m_axi_aclk; + assign sg_ext_resetn = m_axi_aresetn; + assign sg_enabled = sg_enable | ~sg_in_ready; + + assign sg_in_ready = hwdesc_state == STATE_IDLE; + assign fetch_valid = hwdesc_state == STATE_DESC_READY; + assign m_axi_arvalid = hwdesc_state == STATE_SEND_ADDR; + assign m_axi_rready = hwdesc_state == STATE_RECV_DESC; + + assign m_axi_arsize = 3'h3; + assign m_axi_arburst = 2'h1; + assign m_axi_arprot = 3'h0; + assign m_axi_arcache = 4'h3; + assign m_axi_arlen = 'h5; + assign m_axi_araddr = {next_desc_addr, {BYTES_PER_BEAT_WIDTH_SG{1'b0}}}; + + util_axis_fifo #( + .DATA_WIDTH(DMA_ADDRESS_WIDTH_SG), + .ADDRESS_WIDTH(0), + .ASYNC_CLK(ASYNC_CLK_REQ_SG) + ) i_sg_addr_fifo ( + .s_axis_aclk(req_clk), + .s_axis_aresetn(req_resetn), + .s_axis_valid(req_in_valid), + .s_axis_ready(req_in_ready), + .s_axis_full(), + .s_axis_data(req_desc_address), + .s_axis_room(), + + .m_axis_aclk(sg_clk), + .m_axis_aresetn(sg_resetn), + .m_axis_valid(sg_in_valid), + .m_axis_ready(sg_in_ready), + .m_axis_data(first_desc_address), + .m_axis_level(), + .m_axis_empty()); + + always @(posedge sg_clk) begin + if (sg_resetn == 1'b0) begin + hwdesc_counter <= 'h0; + end else if (m_axi_rvalid) begin + hwdesc_counter <= hwdesc_counter + 1'b1; + end else if (hwdesc_state == STATE_DESC_READY) begin + hwdesc_counter <= 'h0; + end + end + + // Read the descriptor data + always @(posedge sg_clk) begin + if (sg_resetn == 1'b0) begin + hwdesc_flags <= 'h00; + hwdesc_id <= 'h00; + dest_addr <= 'h00; + src_addr <= 'h00; + next_desc_addr <= 'h00; + y_length <= 'h00; + x_length <= 'h00; + src_stride <= 'h00; + dest_stride <= 'h00; + end else begin + if (sg_in_valid && sg_in_ready) begin + next_desc_addr <= first_desc_address; + end + if (m_axi_rvalid) begin + case (hwdesc_counter) + 0: begin + hwdesc_id <= m_axi_rdata[63:32]; + hwdesc_flags <= m_axi_rdata[1:0]; + end + 1: dest_addr <= m_axi_rdata[DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST]; + 2: src_addr <= m_axi_rdata[DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC]; + 3: next_desc_addr <= m_axi_rdata[DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SG]; + 4: begin + x_length <= m_axi_rdata[63:32]; + y_length <= m_axi_rdata[31:0]; + end + 5: begin + dest_stride <= m_axi_rdata[63:32]; + src_stride <= m_axi_rdata[31:0]; + end + endcase + end + end + end + + // Descriptor FSM + always @(posedge sg_clk) begin + if (sg_resetn == 1'b0) begin + hwdesc_state <= STATE_IDLE; + end else begin + case (hwdesc_state) + STATE_IDLE: begin + if (sg_in_valid == 1'b1 && sg_enable == 1'b1) begin + hwdesc_state <= STATE_SEND_ADDR; + end + end + + STATE_SEND_ADDR: begin + if (m_axi_arready) begin + hwdesc_state <= STATE_RECV_DESC; + end + end + + STATE_RECV_DESC: begin + if (m_axi_rvalid == 1'b1 && m_axi_rlast == 1'b1) begin + hwdesc_state <= STATE_DESC_READY; + end + end + + STATE_DESC_READY: begin + if (sg_enable == 1'b0) begin + hwdesc_state <= STATE_IDLE; + end else if (fetch_ready == 1'b1) begin + if (hwdesc_flags & MASK_LAST_HWDESC) begin + hwdesc_state <= STATE_IDLE; + end else begin + hwdesc_state <= STATE_SEND_ADDR; + end + end + end + endcase + end + end + + util_axis_fifo #( + .DATA_WIDTH(DMA_DESCRIPTOR_WIDTH), + .ADDRESS_WIDTH(0), + .ASYNC_CLK(ASYNC_CLK_REQ_SG) + ) i_sg_desc_fifo ( + .s_axis_aclk(sg_clk), + .s_axis_aresetn(sg_resetn), + .s_axis_valid(sg_out_valid), + .s_axis_ready(sg_out_ready), + .s_axis_full(), + .s_axis_data({ + dest_addr, + src_addr, + x_length, + y_length, + dest_stride, + src_stride}), + .s_axis_room(), + + .m_axis_aclk(req_clk), + .m_axis_aresetn(req_resetn), + .m_axis_valid(req_out_valid), + .m_axis_ready(req_out_ready), + .m_axis_data({ + out_dest_address, + out_src_address, + out_x_length, + out_y_length, + out_dest_stride, + out_src_stride}), + .m_axis_level(), + .m_axis_empty()); + + splitter #( + .NUM_M(2) + ) i_req_splitter ( + .clk(sg_clk), + .resetn(sg_resetn), + .s_valid(fetch_valid), + .s_ready(fetch_ready), + .m_valid({ + sg_out_valid, + fifo_in_valid}), + .m_ready({ + sg_out_ready, + fifo_in_ready})); + + assign fifo_in_data = {hwdesc_flags & MASK_EOT_IRQ ? 1'b1 : 1'b0, hwdesc_id}; + assign fifo_out_ready = resp_in_valid; + assign resp_out_eot = fifo_out_data[32]; + assign resp_out_id = fifo_out_data[31:0]; + + // Save the descriptor IDs and the eot descriptor flag in an async fifo + // Extract them one by one when the destination responds with an eot + util_axis_fifo #( + .DATA_WIDTH(33), + .ADDRESS_WIDTH(2), + .ASYNC_CLK(ASYNC_CLK_REQ_SG) + ) i_fifo ( + .s_axis_aclk(sg_clk), + .s_axis_aresetn(sg_resetn), + + .s_axis_valid(fifo_in_valid), + .s_axis_ready(fifo_in_ready), + .s_axis_data(fifo_in_data), + + .m_axis_aclk(req_clk), + .m_axis_aresetn(req_resetn), + + .m_axis_valid(fifo_out_valid), + .m_axis_ready(fifo_out_ready), + .m_axis_data(fifo_out_data)); + +endmodule diff --git a/adi_library/axi_dmac/gui/axi_dmac_v1_0.gtcl b/adi_library/axi_dmac/gui/axi_dmac_v1_0.gtcl new file mode 100644 index 00000000..64e1de72 --- /dev/null +++ b/adi_library/axi_dmac/gui/axi_dmac_v1_0.gtcl @@ -0,0 +1,8 @@ +# This file is automatically written. Do not modify. +proc gen_USERPARAMETER_DMA_DATA_WIDTH_SG_ENABLEMENT {DMA_SG_TRANSFER } {expr $DMA_SG_TRANSFER == true} +proc gen_USERPARAMETER_SYNC_TRANSFER_START_ENABLEMENT {DMA_TYPE_SRC } {expr $DMA_TYPE_SRC != 0} +proc gen_USERPARAMETER_DMA_AXI_PROTOCOL_DEST_ENABLEMENT {DMA_TYPE_DEST } {expr $DMA_TYPE_DEST == 0} +proc gen_USERPARAMETER_DMA_AXI_PROTOCOL_SRC_ENABLEMENT {DMA_TYPE_SRC } {expr $DMA_TYPE_SRC == 0} +proc gen_USERPARAMETER_DMA_AXI_PROTOCOL_SG_ENABLEMENT {DMA_SG_TRANSFER } {expr $DMA_SG_TRANSFER == true} +proc gen_USERPARAMETER_CACHE_COHERENT_DEST_ENABLEMENT {DMA_TYPE_DEST DMA_AXI_PROTOCOL_DEST } {expr $DMA_TYPE_DEST == 0 && $DMA_AXI_PROTOCOL_DEST == 0} +proc gen_USERPARAMETER_CACHE_COHERENT_DEST_VALUE {DMA_TYPE_DEST DMA_AXI_PROTOCOL_DEST } {expr $DMA_TYPE_DEST == 0 && $DMA_AXI_PROTOCOL_DEST == 0} diff --git a/adi_library/axi_dmac/inc_id.vh b/adi_library/axi_dmac/inc_id.vh new file mode 100644 index 00000000..4213143a --- /dev/null +++ b/adi_library/axi_dmac/inc_id.vh @@ -0,0 +1,67 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +function [ID_WIDTH-1:0] g2b; + input [ID_WIDTH-1:0] g; + reg [ID_WIDTH-1:0] b; + integer i; + begin + b[ID_WIDTH-1] = g[ID_WIDTH-1]; + for (i = ID_WIDTH - 2; i >= 0; i = i - 1) + b[i] = b[i + 1] ^ g[i]; + g2b = b; + end +endfunction + +function [ID_WIDTH-1:0] b2g; + input [ID_WIDTH-1:0] b; + reg [ID_WIDTH-1:0] g; + integer i; + begin + g[ID_WIDTH-1] = b[ID_WIDTH-1]; + for (i = ID_WIDTH - 2; i >= 0; i = i -1) + g[i] = b[i + 1] ^ b[i]; + b2g = g; + end +endfunction + +function [ID_WIDTH-1:0] inc_id; +input [ID_WIDTH-1:0] id; +begin + inc_id = b2g(g2b(id) + 1); +end +endfunction diff --git a/adi_library/axi_dmac/request_arb.v b/adi_library/axi_dmac/request_arb.v new file mode 100644 index 00000000..c733f4fe --- /dev/null +++ b/adi_library/axi_dmac/request_arb.v @@ -0,0 +1,1170 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module request_arb #( + parameter DMA_DATA_WIDTH_SRC = 64, + parameter DMA_DATA_WIDTH_DEST = 64, + parameter DMA_LENGTH_WIDTH = 24, + parameter DMA_LENGTH_ALIGN = 3, + parameter BYTES_PER_BEAT_WIDTH_DEST = $clog2(DMA_DATA_WIDTH_DEST/8), + parameter BYTES_PER_BEAT_WIDTH_SRC = $clog2(DMA_DATA_WIDTH_SRC/8), + parameter DMA_TYPE_DEST = 0, + parameter DMA_TYPE_SRC = 2, + parameter DMA_AXI_ADDR_WIDTH = 32, + parameter ASYNC_CLK_REQ_SRC = 1, + parameter ASYNC_CLK_SRC_DEST = 1, + parameter ASYNC_CLK_DEST_REQ = 1, + parameter AXI_SLICE_DEST = 0, + parameter AXI_SLICE_SRC = 0, + parameter MAX_BYTES_PER_BURST = 128, + parameter BYTES_PER_BURST_WIDTH = 7, + parameter FIFO_SIZE = 8, + parameter ID_WIDTH = $clog2(FIFO_SIZE*2), + parameter AXI_LENGTH_WIDTH_SRC = 8, + parameter AXI_LENGTH_WIDTH_DEST = 8, + parameter ENABLE_DIAGNOSTICS_IF = 0, + parameter ALLOW_ASYM_MEM = 0, + parameter CACHE_COHERENT_DEST = 0 +) ( + input req_clk, + input req_resetn, + + input req_valid, + output req_ready, + input [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address, + input [DMA_AXI_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC] req_src_address, + input [DMA_LENGTH_WIDTH-1:0] req_length, + input req_xlast, + input req_sync_transfer_start, + + output eot, + output [BYTES_PER_BURST_WIDTH-1:0] measured_burst_length, + output response_partial, + output response_valid, + input response_ready, + + output abort_req, + + // Master AXI interface + input m_dest_axi_aclk, + input m_dest_axi_aresetn, + input m_src_axi_aclk, + input m_src_axi_aresetn, + + // Write address + output [DMA_AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output [AXI_LENGTH_WIDTH_DEST-1:0] m_axi_awlen, + output [ 2:0] m_axi_awsize, + output [ 1:0] m_axi_awburst, + output [ 2:0] m_axi_awprot, + output [ 3:0] m_axi_awcache, + output m_axi_awvalid, + input m_axi_awready, + + // Write data + output [DMA_DATA_WIDTH_DEST-1:0] m_axi_wdata, + output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_axi_wstrb, + input m_axi_wready, + output m_axi_wvalid, + output m_axi_wlast, + + // Write response + input m_axi_bvalid, + input [ 1:0] m_axi_bresp, + output m_axi_bready, + + // Read address + input m_axi_arready, + output m_axi_arvalid, + output [DMA_AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output [AXI_LENGTH_WIDTH_SRC-1:0] m_axi_arlen, + output [ 2:0] m_axi_arsize, + output [ 1:0] m_axi_arburst, + output [ 2:0] m_axi_arprot, + output [ 3:0] m_axi_arcache, + + // Read data and response + input [DMA_DATA_WIDTH_SRC-1:0] m_axi_rdata, + output m_axi_rready, + input m_axi_rvalid, + input m_axi_rlast, + input [ 1:0] m_axi_rresp, + + // Slave streaming AXI interface + input s_axis_aclk, + output s_axis_ready, + input s_axis_valid, + input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data, + input s_axis_last, + input [0:0] s_axis_user, + output s_axis_xfer_req, + + // Master streaming AXI interface + input m_axis_aclk, + input m_axis_ready, + output m_axis_valid, + output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data, + output m_axis_last, + output m_axis_xfer_req, + + // Input FIFO interface + input fifo_wr_clk, + input fifo_wr_en, + input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din, + output fifo_wr_overflow, + input fifo_wr_sync, + output fifo_wr_xfer_req, + + // Input FIFO interface + input fifo_rd_clk, + input fifo_rd_en, + output fifo_rd_valid, + output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout, + output fifo_rd_underflow, + output fifo_rd_xfer_req, + + output [ID_WIDTH-1:0] dbg_dest_request_id, + output [ID_WIDTH-1:0] dbg_dest_address_id, + output [ID_WIDTH-1:0] dbg_dest_data_id, + output [ID_WIDTH-1:0] dbg_dest_response_id, + output [ID_WIDTH-1:0] dbg_src_request_id, + output [ID_WIDTH-1:0] dbg_src_address_id, + output [ID_WIDTH-1:0] dbg_src_data_id, + output [ID_WIDTH-1:0] dbg_src_response_id, + + input req_enable, + + output dest_clk, + input dest_resetn, + output dest_ext_resetn, + input dest_enable, + output dest_enabled, + + output src_clk, + input src_resetn, + output src_ext_resetn, + input src_enable, + output src_enabled, + + // Diagnostics interface + output [7:0] dest_diag_level_bursts +); + + localparam DMA_TYPE_MM_AXI = 0; + localparam DMA_TYPE_STREAM_AXI = 1; + localparam DMA_TYPE_FIFO = 2; + + localparam DMA_ADDRESS_WIDTH_DEST = DMA_AXI_ADDR_WIDTH - BYTES_PER_BEAT_WIDTH_DEST; + localparam DMA_ADDRESS_WIDTH_SRC = DMA_AXI_ADDR_WIDTH - BYTES_PER_BEAT_WIDTH_SRC; + + // Bytes per burst is the same for both dest and src, but bytes per beat may + // differ, so beats per burst may also differ + + localparam BEATS_PER_BURST_WIDTH_SRC = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH_SRC; + localparam BEATS_PER_BURST_WIDTH_DEST = BYTES_PER_BURST_WIDTH - BYTES_PER_BEAT_WIDTH_DEST; + + localparam BURSTS_PER_TRANSFER_WIDTH = DMA_LENGTH_WIDTH - BYTES_PER_BURST_WIDTH; + + reg eot_mem_src[0:2**ID_WIDTH-1]; + reg eot_mem_dest[0:2**ID_WIDTH-1]; + wire request_eot; + wire source_eot; + + wire [ID_WIDTH-1:0] request_id; + wire [ID_WIDTH-1:0] source_id; + wire [ID_WIDTH-1:0] response_id; + + wire req_gen_valid; + wire req_gen_ready; + wire src_dest_valid; + wire src_dest_ready; + wire req_src_valid; + wire req_src_ready; + + wire dest_req_valid; + wire dest_req_ready; + wire [DMA_ADDRESS_WIDTH_DEST-1:0] dest_req_dest_address; + wire dest_req_xlast; + + wire dest_response_valid; + wire dest_response_ready; + wire [1:0] dest_response_resp; + wire dest_response_resp_eot; + wire [BYTES_PER_BURST_WIDTH-1:0] dest_response_data_burst_length; + wire dest_response_partial; + + wire [ID_WIDTH-1:0] dest_request_id; + wire [ID_WIDTH-1:0] dest_data_request_id; + wire [ID_WIDTH-1:0] dest_data_response_id; + wire [ID_WIDTH-1:0] dest_response_id; + + wire dest_valid; + wire dest_ready; + wire [DMA_DATA_WIDTH_DEST-1:0] dest_data; + wire [DMA_DATA_WIDTH_DEST/8-1:0] dest_strb; + wire dest_last; + wire dest_fifo_valid; + wire dest_fifo_ready; + wire [DMA_DATA_WIDTH_DEST-1:0] dest_fifo_data; + wire [DMA_DATA_WIDTH_DEST/8-1:0] dest_fifo_strb; + wire dest_fifo_last; + + wire src_req_valid; + wire src_req_ready; + wire [DMA_ADDRESS_WIDTH_DEST-1:0] src_req_dest_address; + wire [DMA_ADDRESS_WIDTH_SRC-1:0] src_req_src_address; + wire [BEATS_PER_BURST_WIDTH_SRC-1:0] src_req_last_burst_length; + wire [BYTES_PER_BEAT_WIDTH_SRC-1:0] src_req_last_beat_bytes; + wire src_req_sync_transfer_start; + wire src_req_xlast; + + reg [DMA_ADDRESS_WIDTH_DEST-1:0] src_req_dest_address_cur = 'h0; + reg src_req_xlast_cur = 1'b0; + + /* TODO + wire src_response_valid; + wire src_response_ready; + wire src_response_empty; + wire [1:0] src_response_resp; + */ + + wire [ID_WIDTH-1:0] src_request_id; + reg [ID_WIDTH-1:0] src_throttled_request_id; + wire [ID_WIDTH-1:0] src_data_request_id; + wire [ID_WIDTH-1:0] src_response_id; + + wire src_valid; + wire [DMA_DATA_WIDTH_SRC-1:0] src_data; + wire [BYTES_PER_BEAT_WIDTH_SRC-1:0] src_valid_bytes; + wire src_last; + wire src_partial_burst; + wire block_descr_to_dst; + wire src_fifo_valid; + wire [DMA_DATA_WIDTH_SRC-1:0] src_fifo_data; + wire [BYTES_PER_BEAT_WIDTH_SRC-1:0] src_fifo_valid_bytes; + wire src_fifo_last; + wire src_fifo_partial_burst; + + wire src_bl_valid; + wire src_bl_ready; + wire [BEATS_PER_BURST_WIDTH_SRC-1:0] src_burst_length; + + wire [BYTES_PER_BURST_WIDTH-1:0] dest_burst_info_length; + wire dest_burst_info_partial; + wire [ID_WIDTH-1:0] dest_burst_info_id; + wire dest_burst_info_write; + + reg src_dest_valid_hs = 1'b0; + wire src_dest_valid_hs_masked; + wire src_dest_ready_hs; + + wire req_rewind_req_valid; + wire req_rewind_req_ready; + wire [ID_WIDTH+3-1:0] req_rewind_req_data; + + wire completion_req_valid; + wire completion_req_ready; + wire completion_req_last; + wire [1:0] completion_transfer_id; + + wire rewind_req_valid; + wire rewind_req_ready; + wire [ID_WIDTH+3-1:0] rewind_req_data; + + reg src_throttler_enabled = 1'b1; + wire rewind_state; + + /* Unused for now + wire response_src_valid; + wire response_src_ready = 1'b1; + wire [1:0] response_src_resp; + */ + + assign dbg_dest_request_id = dest_request_id; + assign dbg_dest_response_id = dest_response_id; + assign dbg_src_request_id = src_request_id; + assign dbg_src_response_id = src_response_id; + + always @(posedge req_clk) + begin + eot_mem_src[request_id] <= request_eot; + end + + always @(posedge src_clk) + begin + eot_mem_dest[source_id] <= source_eot; + end + + generate if (DMA_TYPE_DEST == DMA_TYPE_MM_AXI) begin + + wire dest_bl_valid; + wire dest_bl_ready; + wire [BEATS_PER_BURST_WIDTH_DEST-1:0] dest_burst_length; + wire [BEATS_PER_BURST_WIDTH_SRC-1:0] dest_src_burst_length; + + assign dest_clk = m_dest_axi_aclk; + assign dest_ext_resetn = m_dest_axi_aresetn; + + wire [ID_WIDTH-1:0] dest_address_id; + wire dest_address_eot = eot_mem_dest[dest_address_id]; + wire dest_response_eot = eot_mem_dest[dest_response_id]; + + assign dbg_dest_address_id = dest_address_id; + assign dbg_dest_data_id = dest_data_response_id; + + assign dest_data_request_id = dest_address_id; + + dest_axi_mm #( + .ID_WIDTH(ID_WIDTH), + .DMA_DATA_WIDTH(DMA_DATA_WIDTH_DEST), + .DMA_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST), + .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_DEST), + .MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST), + .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH), + .AXI_LENGTH_WIDTH(AXI_LENGTH_WIDTH_DEST), + .CACHE_COHERENT(CACHE_COHERENT_DEST) + ) i_dest_dma_mm ( + .m_axi_aclk(m_dest_axi_aclk), + .m_axi_aresetn(dest_resetn), + + .enable(dest_enable), + .enabled(dest_enabled), + + .req_valid(dest_req_valid), + .req_ready(dest_req_ready), + .req_address(dest_req_dest_address), + + .bl_valid(dest_bl_valid), + .bl_ready(dest_bl_ready), + .measured_last_burst_length(dest_burst_length), + + .response_valid(dest_response_valid), + .response_ready(dest_response_ready), + .response_resp(dest_response_resp), + .response_resp_eot(dest_response_resp_eot), + .response_resp_partial(dest_response_partial), + .response_data_burst_length(dest_response_data_burst_length), + + .request_id(dest_request_id), + .response_id(dest_response_id), + + .address_id(dest_address_id), + + .address_eot(dest_address_eot), + .response_eot(dest_response_eot), + + .fifo_valid(dest_valid), + .fifo_ready(dest_ready), + .fifo_data(dest_data), + .fifo_strb(dest_strb), + .fifo_last(dest_last), + + .dest_burst_info_length(dest_burst_info_length), + .dest_burst_info_partial(dest_burst_info_partial), + .dest_burst_info_id(dest_burst_info_id), + .dest_burst_info_write(dest_burst_info_write), + + .m_axi_awready(m_axi_awready), + .m_axi_awvalid(m_axi_awvalid), + .m_axi_awaddr(m_axi_awaddr), + .m_axi_awlen(m_axi_awlen), + .m_axi_awsize(m_axi_awsize), + .m_axi_awburst(m_axi_awburst), + .m_axi_awprot(m_axi_awprot), + .m_axi_awcache(m_axi_awcache), + .m_axi_wready(m_axi_wready), + .m_axi_wvalid(m_axi_wvalid), + .m_axi_wdata(m_axi_wdata), + .m_axi_wstrb(m_axi_wstrb), + .m_axi_wlast(m_axi_wlast), + + .m_axi_bvalid(m_axi_bvalid), + .m_axi_bresp(m_axi_bresp), + .m_axi_bready(m_axi_bready)); + + util_axis_fifo #( + .DATA_WIDTH(BEATS_PER_BURST_WIDTH_SRC), + .ADDRESS_WIDTH(0), + .ASYNC_CLK(ASYNC_CLK_SRC_DEST) + ) i_src_dest_bl_fifo ( + .s_axis_aclk(src_clk), + .s_axis_aresetn(src_resetn), + .s_axis_valid(src_bl_valid), + .s_axis_ready(src_bl_ready), + .s_axis_full(), + .s_axis_data(src_burst_length), + .s_axis_room(), + + .m_axis_aclk(dest_clk), + .m_axis_aresetn(dest_resetn), + .m_axis_valid(dest_bl_valid), + .m_axis_ready(dest_bl_ready), + .m_axis_data(dest_src_burst_length), + .m_axis_level(), + .m_axis_empty()); + + // Adapt burst length from source width to destination width by either + // truncation or completion with ones. + if (BEATS_PER_BURST_WIDTH_SRC == BEATS_PER_BURST_WIDTH_DEST) begin + assign dest_burst_length = dest_src_burst_length; + end + + if (BEATS_PER_BURST_WIDTH_SRC < BEATS_PER_BURST_WIDTH_DEST) begin + assign dest_burst_length = {dest_src_burst_length, + {BEATS_PER_BURST_WIDTH_DEST - BEATS_PER_BURST_WIDTH_SRC{1'b1}}}; + end + + if (BEATS_PER_BURST_WIDTH_SRC > BEATS_PER_BURST_WIDTH_DEST) begin + assign dest_burst_length = dest_src_burst_length[BEATS_PER_BURST_WIDTH_SRC-1 -: BEATS_PER_BURST_WIDTH_DEST]; + end + + end else begin + + assign m_axi_awvalid = 1'b0; + assign m_axi_awaddr = 'h00; + assign m_axi_awlen = 'h00; + assign m_axi_awsize = 'h00; + assign m_axi_awburst = 'h00; + assign m_axi_awprot = 'h00; + assign m_axi_awcache = 'h00; + + assign m_axi_wvalid = 1'b0; + assign m_axi_wdata = 'h00; + assign m_axi_wstrb = 'h00; + assign m_axi_wlast = 1'b0; + + assign m_axi_bready = 1'b0; + + assign src_bl_ready = 1'b1; + + assign dest_response_partial = 1'b0; + assign dest_response_data_burst_length = 'h0; + + end + + if (DMA_TYPE_DEST == DMA_TYPE_STREAM_AXI) begin + + assign dest_clk = m_axis_aclk; + assign dest_ext_resetn = 1'b1; + + wire [ID_WIDTH-1:0] data_id; + + wire data_eot = eot_mem_dest[data_id]; + wire response_eot = eot_mem_dest[dest_response_id]; + + assign dest_data_request_id = dest_request_id; + + assign dbg_dest_address_id = 'h00; + assign dbg_dest_data_id = data_id; + + dest_axi_stream #( + .ID_WIDTH(ID_WIDTH), + .S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_DEST), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST) + ) i_dest_dma_stream ( + .s_axis_aclk(m_axis_aclk), + .s_axis_aresetn(dest_resetn), + + .enable(dest_enable), + .enabled(dest_enabled), + + .req_valid(dest_req_valid), + .req_ready(dest_req_ready), + .req_xlast(dest_req_xlast), + + .response_valid(dest_response_valid), + .response_ready(dest_response_ready), + .response_resp(dest_response_resp), + .response_resp_eot(dest_response_resp_eot), + + .response_id(dest_response_id), + .data_id(data_id), + .xfer_req(m_axis_xfer_req), + + .data_eot(data_eot), + .response_eot(response_eot), + + .fifo_valid(dest_valid), + .fifo_ready(dest_ready), + .fifo_data(dest_data), + .fifo_last(dest_last), + + .m_axis_valid(m_axis_valid), + .m_axis_ready(m_axis_ready), + .m_axis_data(m_axis_data), + .m_axis_last(m_axis_last)); + + end else begin + + assign m_axis_valid = 1'b0; + assign m_axis_last = 1'b0; + assign m_axis_xfer_req = 1'b0; + assign m_axis_data = 'h00; + + end + + if (DMA_TYPE_DEST == DMA_TYPE_FIFO) begin + + assign dest_clk = fifo_rd_clk; + assign dest_ext_resetn = 1'b1; + + wire [ID_WIDTH-1:0] data_id; + + wire data_eot = eot_mem_dest[data_id]; + wire response_eot = eot_mem_dest[dest_response_id]; + + assign dest_data_request_id = dest_request_id; + + assign dbg_dest_address_id = 'h00; + assign dbg_dest_data_id = data_id; + + dest_fifo_inf #( + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(DMA_DATA_WIDTH_DEST), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_DEST) + ) i_dest_dma_fifo ( + .clk(fifo_rd_clk), + .resetn(dest_resetn), + + .enable(dest_enable), + .enabled(dest_enabled), + + .req_valid(dest_req_valid), + .req_ready(dest_req_ready), + + .response_valid(dest_response_valid), + .response_ready(dest_response_ready), + .response_resp(dest_response_resp), + .response_resp_eot(dest_response_resp_eot), + + .response_id(dest_response_id), + .data_id(data_id), + + .data_eot(data_eot), + .response_eot(response_eot), + + .fifo_valid(dest_valid), + .fifo_ready(dest_ready), + .fifo_data(dest_data), + .fifo_last(dest_last), + + .en(fifo_rd_en), + .valid(fifo_rd_valid), + .dout(fifo_rd_dout), + .underflow(fifo_rd_underflow), + .xfer_req(fifo_rd_xfer_req)); + + end else begin + + assign fifo_rd_valid = 1'b0; + assign fifo_rd_dout = 'h0; + assign fifo_rd_underflow = 1'b0; + assign fifo_rd_xfer_req = 1'b0; + + end endgenerate + + generate if (DMA_TYPE_SRC == DMA_TYPE_MM_AXI) begin + + wire [ID_WIDTH-1:0] src_data_id; + wire [ID_WIDTH-1:0] src_address_id; + wire src_address_eot = eot_mem_src[src_address_id]; + + assign source_id = src_address_id; + assign source_eot = src_address_eot; + + assign src_clk = m_src_axi_aclk; + assign src_ext_resetn = m_src_axi_aresetn; + + assign dbg_src_address_id = src_address_id; + assign dbg_src_data_id = src_data_id; + + src_axi_mm #( + .ID_WIDTH(ID_WIDTH), + .DMA_DATA_WIDTH(DMA_DATA_WIDTH_SRC), + .DMA_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC), + .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH_SRC), + .AXI_LENGTH_WIDTH(AXI_LENGTH_WIDTH_SRC) + ) i_src_dma_mm ( + .m_axi_aclk(m_src_axi_aclk), + .m_axi_aresetn(src_resetn), + + .enable(src_enable), + .enabled(src_enabled), + + .req_valid(src_req_valid), + .req_ready(src_req_ready), + .req_address(src_req_src_address), + .req_last_burst_length(src_req_last_burst_length), + .req_last_beat_bytes(src_req_last_beat_bytes), + + .bl_valid(src_bl_valid), + .bl_ready(src_bl_ready), + .measured_last_burst_length(src_burst_length), + + /* TODO + .response_valid(src_response_valid), + .response_ready(src_response_ready), + .response_resp(src_response_resp), + */ + + .request_id(src_throttled_request_id), + .response_id(src_response_id), + .address_id(src_address_id), + .data_id(src_data_id), + + .address_eot(src_address_eot), + + .fifo_valid(src_valid), + .fifo_data(src_data), + .fifo_valid_bytes(src_valid_bytes), + .fifo_last(src_last), + + .m_axi_arready(m_axi_arready), + .m_axi_arvalid(m_axi_arvalid), + .m_axi_araddr(m_axi_araddr), + .m_axi_arlen(m_axi_arlen), + .m_axi_arsize(m_axi_arsize), + .m_axi_arburst(m_axi_arburst), + .m_axi_arprot(m_axi_arprot), + .m_axi_arcache(m_axi_arcache), + + .m_axi_rready(m_axi_rready), + .m_axi_rvalid(m_axi_rvalid), + .m_axi_rdata(m_axi_rdata), + .m_axi_rlast(m_axi_rlast), + .m_axi_rresp(m_axi_rresp)); + + end else begin + + assign m_axi_arvalid = 1'b0; + assign m_axi_araddr = 'h00; + assign m_axi_arlen = 'h00; + assign m_axi_arsize = 'h00; + assign m_axi_arburst = 'h00; + assign m_axi_arcache = 'h00; + assign m_axi_arprot = 'h00; + assign m_axi_rready = 1'b0; + + end + + if (DMA_TYPE_SRC == DMA_TYPE_STREAM_AXI) begin + + assign src_clk = s_axis_aclk; + assign src_ext_resetn = 1'b1; + + wire src_eot = eot_mem_src[src_response_id]; + + assign dbg_src_address_id = 'h00; + assign dbg_src_data_id = 'h00; + + /* TODO + assign src_response_valid = 1'b0; + assign src_response_resp = 2'b0; + */ + + src_axi_stream #( + .ID_WIDTH(ID_WIDTH), + .S_AXIS_DATA_WIDTH(DMA_DATA_WIDTH_SRC), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC) + ) i_src_dma_stream ( + .s_axis_aclk(s_axis_aclk), + .s_axis_aresetn(src_resetn), + + .enable(src_enable), + .enabled(src_enabled), + + .req_valid(src_req_valid), + .req_ready(src_req_ready), + .req_last_burst_length(src_req_last_burst_length), + .req_sync_transfer_start(src_req_sync_transfer_start), + .req_xlast(src_req_xlast), + + .request_id(src_throttled_request_id), + .response_id(src_response_id), + + .eot(src_eot), + + .rewind_req_valid(rewind_req_valid), + .rewind_req_ready(rewind_req_ready), + .rewind_req_data(rewind_req_data), + + .bl_valid(src_bl_valid), + .bl_ready(src_bl_ready), + .measured_last_burst_length(src_burst_length), + + .block_descr_to_dst(block_descr_to_dst), + + .source_id(source_id), + .source_eot(source_eot), + + .fifo_valid(src_valid), + .fifo_data(src_data), + .fifo_last(src_last), + .fifo_partial_burst(src_partial_burst), + + .s_axis_valid(s_axis_valid), + .s_axis_ready(s_axis_ready), + .s_axis_data(s_axis_data), + .s_axis_last(s_axis_last), + .s_axis_user(s_axis_user), + .s_axis_xfer_req(s_axis_xfer_req)); + + assign src_valid_bytes = {BYTES_PER_BEAT_WIDTH_SRC{1'b1}}; + + util_axis_fifo #( + .DATA_WIDTH(ID_WIDTH + 3), + .ADDRESS_WIDTH(0), + .ASYNC_CLK(ASYNC_CLK_REQ_SRC) + ) i_rewind_req_fifo ( + .s_axis_aclk(src_clk), + .s_axis_aresetn(src_resetn), + .s_axis_valid(rewind_req_valid), + .s_axis_ready(rewind_req_ready), + .s_axis_full(), + .s_axis_data(rewind_req_data), + .s_axis_room(), + + .m_axis_aclk(req_clk), + .m_axis_aresetn(req_resetn), + .m_axis_valid(req_rewind_req_valid), + .m_axis_ready(req_rewind_req_ready), + .m_axis_data(req_rewind_req_data), + .m_axis_level(), + .m_axis_empty()); + + wire src_throttler_enable; + + sync_event #( + .ASYNC_CLK(ASYNC_CLK_REQ_SRC) + ) sync_rewind ( + .in_clk(req_clk), + .in_event(rewind_state), + .out_clk(src_clk), + .out_event(src_throttler_enable)); + + always @(posedge src_clk) begin + if (src_resetn == 1'b0) begin + src_throttler_enabled <= 'b1; + end else if (rewind_req_valid) begin + src_throttler_enabled <= 'b0; + end else if (src_throttler_enable) begin + src_throttler_enabled <= 'b1; + end + end + + end else begin + + assign s_axis_ready = 1'b0; + assign s_axis_xfer_req = 1'b0; + assign rewind_req_valid = 1'b0; + assign rewind_req_data = 'h0; + + assign req_rewind_req_valid = 'b0; + assign req_rewind_req_data = 'h0; + + assign src_partial_burst = 1'b0; + assign block_descr_to_dst = 1'b0; + + end + + if (DMA_TYPE_SRC == DMA_TYPE_FIFO) begin + + wire src_eot = eot_mem_src[src_response_id]; + + assign source_id = src_response_id; + assign source_eot = src_eot; + + assign src_clk = fifo_wr_clk; + assign src_ext_resetn = 1'b1; + + assign dbg_src_address_id = 'h00; + assign dbg_src_data_id = 'h00; + + /* TODO + assign src_response_valid = 1'b0; + assign src_response_resp = 2'b0; + */ + + src_fifo_inf #( + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(DMA_DATA_WIDTH_SRC), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH_SRC) + ) i_src_dma_fifo ( + .clk(fifo_wr_clk), + .resetn(src_resetn), + + .enable(src_enable), + .enabled(src_enabled), + + .req_valid(src_req_valid), + .req_ready(src_req_ready), + .req_last_burst_length(src_req_last_burst_length), + .req_sync_transfer_start(src_req_sync_transfer_start), + + .request_id(src_throttled_request_id), + .response_id(src_response_id), + + .eot(src_eot), + + .bl_valid(src_bl_valid), + .bl_ready(src_bl_ready), + .measured_last_burst_length(src_burst_length), + + .fifo_valid(src_valid), + .fifo_data(src_data), + .fifo_last(src_last), + + .en(fifo_wr_en), + .din(fifo_wr_din), + .overflow(fifo_wr_overflow), + .sync(fifo_wr_sync), + .xfer_req(fifo_wr_xfer_req)); + + assign src_valid_bytes = {BYTES_PER_BEAT_WIDTH_SRC{1'b1}}; + + end else begin + + assign fifo_wr_overflow = 1'b0; + assign fifo_wr_xfer_req = 1'b0; + + end endgenerate + + sync_bits #( + .NUM_OF_BITS(ID_WIDTH), + .ASYNC_CLK(ASYNC_CLK_REQ_SRC) + ) i_sync_src_request_id ( + .out_clk(src_clk), + .out_resetn(1'b1), + .in_bits(request_id), + .out_bits(src_request_id)); + + `include "inc_id.vh" + + function compare_id; + input [ID_WIDTH-1:0] a; + input [ID_WIDTH-1:0] b; + begin + compare_id = a[ID_WIDTH-1] == b[ID_WIDTH-1]; + if (ID_WIDTH >= 2) begin + if (a[ID_WIDTH-2] == b[ID_WIDTH-2]) begin + compare_id = 1'b1; + end + end + if (ID_WIDTH >= 3) begin + if (a[ID_WIDTH-3:0] != b[ID_WIDTH-3:0]) begin + compare_id = 1'b1; + end + end + end + endfunction + + /* + * Make sure that we do not request more data than what fits into the + * store-and-forward burst memory. + * Throttler must be blocked during rewind since it does not tolerate + * a decrement of the request ID. + */ + always @(posedge src_clk) begin + if (src_resetn == 1'b0) begin + src_throttled_request_id <= 'h00; + end else if (rewind_req_valid) begin + src_throttled_request_id <= rewind_req_data[ID_WIDTH-1:0]; + end else if (src_throttled_request_id != src_request_id && + compare_id(src_throttled_request_id, src_data_request_id) && + src_throttler_enabled) begin + src_throttled_request_id <= inc_id(src_throttled_request_id); + end + end + + sync_bits #( + .NUM_OF_BITS(ID_WIDTH), + .ASYNC_CLK(ASYNC_CLK_DEST_REQ) + ) i_sync_req_response_id ( + .out_clk(req_clk), + .out_resetn(1'b1), + .in_bits(dest_response_id), + .out_bits(response_id)); + + axi_register_slice #( + .DATA_WIDTH(DMA_DATA_WIDTH_SRC + BYTES_PER_BEAT_WIDTH_SRC + 2), + .FORWARD_REGISTERED(AXI_SLICE_SRC), + .BACKWARD_REGISTERED(0) + ) i_src_slice ( + .clk(src_clk), + .resetn(src_resetn), + .s_axi_valid(src_valid), + .s_axi_ready(), + .s_axi_data({src_data,src_valid_bytes,src_last,src_partial_burst}), + .m_axi_valid(src_fifo_valid), + .m_axi_ready(1'b1), /* No backpressure */ + .m_axi_data({src_fifo_data,src_fifo_valid_bytes,src_fifo_last,src_fifo_partial_burst})); + + axi_dmac_burst_memory #( + .DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC), + .DATA_WIDTH_DEST(DMA_DATA_WIDTH_DEST), + .ID_WIDTH(ID_WIDTH), + .MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST), + .ASYNC_CLK(ASYNC_CLK_SRC_DEST), + .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC), + .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH), + .DMA_LENGTH_ALIGN(DMA_LENGTH_ALIGN), + .ENABLE_DIAGNOSTICS_IF(ENABLE_DIAGNOSTICS_IF), + .ALLOW_ASYM_MEM(ALLOW_ASYM_MEM) + ) i_store_and_forward ( + .src_clk(src_clk), + .src_reset(~src_resetn), + .src_data_valid(src_fifo_valid), + .src_data(src_fifo_data), + .src_data_last(src_fifo_last), + .src_data_valid_bytes(src_fifo_valid_bytes), + .src_data_partial_burst(src_fifo_partial_burst), + + .src_data_request_id(src_data_request_id), + + .dest_clk(dest_clk), + .dest_reset(~dest_resetn), + .dest_data_valid(dest_fifo_valid), + .dest_data_ready(dest_fifo_ready), + .dest_data(dest_fifo_data), + .dest_data_last(dest_fifo_last), + .dest_data_strb(dest_fifo_strb), + + .dest_burst_info_length(dest_burst_info_length), + .dest_burst_info_partial(dest_burst_info_partial), + .dest_burst_info_id(dest_burst_info_id), + .dest_burst_info_write(dest_burst_info_write), + + .dest_request_id(dest_request_id), + .dest_data_request_id(dest_data_request_id), + .dest_data_response_id(dest_data_response_id), + + .dest_diag_level_bursts(dest_diag_level_bursts)); + + axi_register_slice #( + .DATA_WIDTH(DMA_DATA_WIDTH_DEST + DMA_DATA_WIDTH_DEST / 8 + 1), + .FORWARD_REGISTERED(AXI_SLICE_DEST), + .BACKWARD_REGISTERED(AXI_SLICE_DEST) + ) i_dest_slice ( + .clk(dest_clk), + .resetn(dest_resetn), + .s_axi_valid(dest_fifo_valid), + .s_axi_ready(dest_fifo_ready), + .s_axi_data({ + dest_fifo_last, + dest_fifo_strb, + dest_fifo_data}), + .m_axi_valid(dest_valid), + .m_axi_ready(dest_ready), + .m_axi_data({ + dest_last, + dest_strb, + dest_data})); + + // Don't let the request generator run in advance more than one descriptor + // The descriptor FIFO should not block the start of the request generator + // since it becomes ready earlier. + assign req_gen_valid = req_valid & req_ready; + assign req_src_valid = req_valid & req_ready; + assign req_ready = req_gen_ready & req_src_ready; + + util_axis_fifo #( + .DATA_WIDTH(DMA_ADDRESS_WIDTH_DEST + 1), + .ADDRESS_WIDTH(0), + .ASYNC_CLK(ASYNC_CLK_SRC_DEST) + ) i_dest_req_fifo ( + .s_axis_aclk(src_clk), + .s_axis_aresetn(src_resetn), + .s_axis_valid(src_dest_valid_hs_masked), + .s_axis_ready(src_dest_ready_hs), + .s_axis_full(), + .s_axis_data({ + src_req_dest_address_cur, + src_req_xlast_cur}), + .s_axis_room(), + + .m_axis_aclk(dest_clk), + .m_axis_aresetn(dest_resetn), + .m_axis_valid(dest_req_valid), + .m_axis_ready(dest_req_ready), + .m_axis_data({ + dest_req_dest_address, + dest_req_xlast}), + .m_axis_level(), + .m_axis_empty()); + + util_axis_fifo #( + .DATA_WIDTH(DMA_ADDRESS_WIDTH_DEST + DMA_ADDRESS_WIDTH_SRC + BYTES_PER_BURST_WIDTH + 2), + .ADDRESS_WIDTH(0), + .ASYNC_CLK(ASYNC_CLK_REQ_SRC) + ) i_src_req_fifo ( + .s_axis_aclk(req_clk), + .s_axis_aresetn(req_resetn), + .s_axis_valid(req_src_valid), + .s_axis_ready(req_src_ready), + .s_axis_full(), + .s_axis_data({ + req_dest_address, + req_src_address, + req_length[BYTES_PER_BURST_WIDTH-1:0], + req_sync_transfer_start, + req_xlast}), + .s_axis_room(), + + .m_axis_aclk(src_clk), + .m_axis_aresetn(src_resetn), + .m_axis_valid(src_req_spltr_valid), + .m_axis_ready(src_req_spltr_ready), + .m_axis_data({ + src_req_dest_address, + src_req_src_address, + src_req_last_burst_length, + src_req_last_beat_bytes, + src_req_sync_transfer_start, + src_req_xlast}), + .m_axis_level(), + .m_axis_empty()); + + // Save the descriptor in the source clock domain since the submission to + // destination is delayed. + always @(posedge src_clk) begin + if (src_req_valid == 1'b1 && src_req_ready == 1'b1) begin + src_req_dest_address_cur <= src_req_dest_address; + src_req_xlast_cur <= src_req_xlast; + end + end + + always @(posedge src_clk) begin + if (src_resetn == 1'b0) begin + src_dest_valid_hs <= 1'b0; + end else if (src_req_valid == 1'b1 && src_req_ready == 1'b1) begin + src_dest_valid_hs <= 1'b1; + end else if (src_dest_ready_hs == 1'b1) begin + src_dest_valid_hs <= 1'b0; + end + end + + // Forward the descriptor to the destination only after the source decided to + // do so + assign src_dest_valid_hs_masked = src_dest_valid_hs == 1'b1 && block_descr_to_dst == 1'b0; + assign src_req_spltr_ready = src_req_ready && src_dest_ready_hs; + assign src_req_valid = src_req_spltr_valid && src_req_spltr_ready; + + /* Unused for now + util_axis_fifo #( + .DATA_WIDTH(2), + .ADDRESS_WIDTH(0), + .ASYNC_CLK(ASYNC_CLK_REQ_SRC) + ) i_src_response_fifo ( + .s_axis_aclk(src_clk), + .s_axis_aresetn(src_resetn), + .s_axis_valid(src_response_valid), + .s_axis_ready(src_response_ready), + .s_axis_empty(src_response_empty), + .s_axis_data(src_response_resp), + .m_axis_aclk(req_clk), + .m_axis_aresetn(req_resetn), + .m_axis_valid(response_src_valid), + .m_axis_ready(response_src_ready), + .m_axis_data(response_src_resp)); + assign src_response_empty = 1'b1; + assign src_response_ready = 1'b1; + */ + + request_generator #( + .ID_WIDTH(ID_WIDTH), + .BURSTS_PER_TRANSFER_WIDTH(BURSTS_PER_TRANSFER_WIDTH) + ) i_req_gen ( + .clk(req_clk), + .resetn(req_resetn), + + .request_id(request_id), + .response_id(response_id), + + .rewind_req_valid(req_rewind_req_valid), + .rewind_req_ready(req_rewind_req_ready), + .rewind_req_data(req_rewind_req_data), + .rewind_state(rewind_state), + + .abort_req(abort_req), + + .completion_req_valid(completion_req_valid), + .completion_req_ready(completion_req_ready), + .completion_req_last(completion_req_last), + .completion_transfer_id(completion_transfer_id), + + .req_valid(req_gen_valid), + .req_ready(req_gen_ready), + .req_burst_count(req_length[DMA_LENGTH_WIDTH-1:BYTES_PER_BURST_WIDTH]), + .req_xlast(req_xlast), + + .enable(req_enable), + + .eot(request_eot)); + + axi_dmac_response_manager #( + .DMA_DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC), + .DMA_DATA_WIDTH_DEST(DMA_DATA_WIDTH_DEST), + .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH), + .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH), + .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC), + .ASYNC_CLK_DEST_REQ(ASYNC_CLK_DEST_REQ) + ) i_response_manager( + .dest_clk(dest_clk), + .dest_resetn(dest_resetn), + .dest_response_valid(dest_response_valid), + .dest_response_ready(dest_response_ready), + .dest_response_resp(dest_response_resp), + .dest_response_partial(dest_response_partial), + .dest_response_resp_eot(dest_response_resp_eot), + .dest_response_data_burst_length(dest_response_data_burst_length), + + .req_clk(req_clk), + .req_resetn(req_resetn), + .response_eot(eot), + .measured_burst_length(measured_burst_length), + .response_partial(response_partial), + .response_valid(response_valid), + .response_ready(response_ready), + + .completion_req_valid(completion_req_valid), + .completion_req_ready(completion_req_ready), + .completion_req_last(completion_req_last), + .completion_transfer_id(completion_transfer_id)); + +endmodule diff --git a/adi_library/axi_dmac/request_generator.v b/adi_library/axi_dmac/request_generator.v new file mode 100644 index 00000000..2951e244 --- /dev/null +++ b/adi_library/axi_dmac/request_generator.v @@ -0,0 +1,258 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module request_generator #( + + parameter ID_WIDTH = 3, + parameter BURSTS_PER_TRANSFER_WIDTH = 17 +) ( + input clk, + input resetn, + + output [ID_WIDTH-1:0] request_id, + input [ID_WIDTH-1:0] response_id, + + input rewind_req_valid, + output rewind_req_ready, + input [ID_WIDTH+3-1:0] rewind_req_data, + output rewind_state, + + output abort_req, + + output reg completion_req_valid = 1'b0, + input completion_req_ready, + output completion_req_last, + output [1:0] completion_transfer_id, + + input req_valid, + output reg req_ready, + input [BURSTS_PER_TRANSFER_WIDTH-1:0] req_burst_count, + input req_xlast, + + input enable, + + output eot +); + + `include "inc_id.vh" + + localparam STATE_IDLE = 3'h0; + localparam STATE_GEN_ID = 3'h1; + localparam STATE_REWIND_ID = 3'h2; + localparam STATE_CONSUME = 3'h3; + localparam STATE_WAIT_LAST = 3'h4; + + reg [2:0] state = STATE_IDLE; + reg [2:0] nx_state; + + reg [1:0] rew_transfer_id = 1'b0; + reg rew_req_xlast; + reg [ID_WIDTH-1:0] rew_id = 'h0; + + reg cur_transfer_id = 1'b0; + reg cur_req_xlast; + + wire transfer_id_match; + reg nx_completion_req_valid; + + /* + * Here we only need to count the number of bursts, which means we can ignore + * the lower bits of the byte count. The last last burst may not contain the + * maximum number of bytes, but the address_generator and data_mover will take + * care that only the requested ammount of bytes is transfered. + */ + + reg [BURSTS_PER_TRANSFER_WIDTH-1:0] burst_count = 'h00; + reg [BURSTS_PER_TRANSFER_WIDTH-1:0] cur_burst_length = 'h00; + reg [ID_WIDTH-1:0] id; + wire [ID_WIDTH-1:0] id_next = inc_id(id); + wire incr_en; + wire incr_id; + + assign eot = burst_count == 'h00; + assign request_id = id; + + assign incr_en = (response_id != id_next) && (enable == 1'b1); + assign incr_id = (state == STATE_GEN_ID) && (incr_en == 1'b1); + + always @(posedge clk) begin + if (state == STATE_IDLE) begin + burst_count <= req_burst_count; + end else if (state == STATE_REWIND_ID) begin + burst_count <= cur_burst_length; + end else if (incr_id == 1'b1) begin + burst_count <= burst_count - 1'b1; + end + end + always @(posedge clk) begin + if (req_ready == 1'b1 & req_valid == 1'b1) begin + cur_req_xlast <= req_xlast; + cur_burst_length <= req_burst_count; + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + id <= 'h0; + end else if (state == STATE_REWIND_ID) begin + id <= rew_id; + end else if (incr_id == 1'b1) begin + id <= id_next; + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + req_ready <= 1'b0; + end else begin + req_ready <= (nx_state == STATE_IDLE || nx_state == STATE_CONSUME); + end + end + + assign transfer_id_match = cur_transfer_id == rew_transfer_id[0]; + + always @(posedge clk) begin + if (resetn == 1'b0) begin + cur_transfer_id <= 1'b0; + end else if (req_valid == 1'b1 && req_ready == 1'b1) begin + cur_transfer_id <= ~cur_transfer_id; + end + end + + /* + * Once rewind request is received we need to stop incrementing the burst ID. + * + * If the current segment matches the segment that was interrupted and + * if it was a last segment we ignore consecutive segments until the last + * segment is received, in other case we can jump to the next segment. + * + * If the current segment is newer than the one got interrupted and the + * interrupted one was a last segment we need to replay the current + * segment with the adjusted burst ID. If the interrupted segment was not last + * we need to consume/ignore all segments until a last segment is received. + * + * Completion requests are generated for every segment that is + * consumed/ignored. These are handled by the response_manager once the + * interrupted segment got transferred to the destination. + */ + always @(*) begin + nx_state = state; + nx_completion_req_valid = 0; + case (state) + STATE_IDLE: begin + if (rewind_req_valid == 1'b1 && rewind_req_ready == 1'b1) begin + nx_state = STATE_REWIND_ID; + end else if (req_valid == 1'b1) begin + nx_state = STATE_GEN_ID; + end + end + STATE_GEN_ID: begin + if (rewind_req_valid == 1'b1 && rewind_req_ready == 1'b1) begin + nx_state = STATE_REWIND_ID; + end else if (eot == 1'b1 && incr_en == 1'b1) begin + nx_state = STATE_IDLE; + end + end + STATE_REWIND_ID: begin + if (transfer_id_match) begin + if (rew_req_xlast) begin + nx_state = STATE_IDLE; + end else begin + nx_state = STATE_CONSUME; + end + end else begin + if (rew_req_xlast) begin + nx_state = STATE_GEN_ID; + end else if (cur_req_xlast) begin + nx_state = STATE_IDLE; + nx_completion_req_valid = 1; + end else begin + nx_state = STATE_CONSUME; + nx_completion_req_valid = 1; + end + end + end + STATE_CONSUME: begin + if (req_valid) begin + nx_completion_req_valid = 1; + nx_state = STATE_WAIT_LAST; + end + end + STATE_WAIT_LAST:begin + if (cur_req_xlast) begin + nx_state = STATE_IDLE; + end else begin + nx_state = STATE_CONSUME; + end + end + + default: begin + nx_state = STATE_IDLE; + end + endcase + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + state <= STATE_IDLE; + end else begin + state <= nx_state; + end + end + + always @(posedge clk) begin + if (rewind_req_valid == 1'b1 && rewind_req_ready == 1'b1) begin + {rew_transfer_id, rew_req_xlast, rew_id} <= rewind_req_data; + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + completion_req_valid <= 1'b0; + end else begin + completion_req_valid <= nx_completion_req_valid; + end + end + assign completion_req_last = cur_req_xlast; + assign completion_transfer_id = rew_transfer_id; + + assign rewind_state = (state == STATE_REWIND_ID); + assign rewind_req_ready = completion_req_ready; + + assign abort_req = (state == STATE_REWIND_ID) && !rew_req_xlast && !cur_req_xlast; + +endmodule diff --git a/adi_library/axi_dmac/resp.vh b/adi_library/axi_dmac/resp.vh new file mode 100644 index 00000000..a3a73835 --- /dev/null +++ b/adi_library/axi_dmac/resp.vh @@ -0,0 +1,4 @@ +localparam RESP_OKAY = 2'b00; +localparam RESP_EXOKAY = 2'b01; +localparam RESP_SLVERR = 2'b10; +localparam RESP_DECERR = 2'b11; diff --git a/adi_library/axi_dmac/response_generator.v b/adi_library/axi_dmac/response_generator.v new file mode 100644 index 00000000..85623361 --- /dev/null +++ b/adi_library/axi_dmac/response_generator.v @@ -0,0 +1,86 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module response_generator #( + + parameter ID_WIDTH = 3 +) ( + input clk, + input resetn, + + input enable, + output reg enabled, + + input [ID_WIDTH-1:0] request_id, + output reg [ID_WIDTH-1:0] response_id, + + input eot, + + output resp_valid, + input resp_ready, + output resp_eot, + output [1:0] resp_resp +); + +`include "inc_id.vh" +`include "resp.vh" + + assign resp_resp = RESP_OKAY; + assign resp_eot = eot; + + assign resp_valid = request_id != response_id && enabled; + + // We have to wait for all responses before we can disable the response handler + always @(posedge clk) begin + if (resetn == 1'b0) begin + enabled <= 1'b0; + end else if (enable == 1'b1) begin + enabled <= 1'b1; + end else if (request_id == response_id) begin + enabled <= 1'b0; + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + response_id <= 'h0; + end else if (resp_valid == 1'b1 && resp_ready == 1'b1) begin + response_id <= inc_id(response_id); + end + end + +endmodule diff --git a/adi_library/axi_dmac/response_handler.v b/adi_library/axi_dmac/response_handler.v new file mode 100644 index 00000000..dae85697 --- /dev/null +++ b/adi_library/axi_dmac/response_handler.v @@ -0,0 +1,93 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module response_handler #( + + parameter ID_WIDTH = 3 +) ( + input clk, + input resetn, + + input bvalid, + output bready, + input [1:0] bresp, + + output reg [ID_WIDTH-1:0] id, + input [ID_WIDTH-1:0] request_id, + + input enable, + output reg enabled, + + input eot, + + output resp_valid, + input resp_ready, + output resp_eot, + output [1:0] resp_resp +); + + `include "resp.vh" + `include "inc_id.vh" + + assign resp_resp = bresp; + assign resp_eot = eot; + + wire active = id != request_id; + + assign bready = active && resp_ready; + assign resp_valid = active && bvalid; + + // We have to wait for all responses before we can disable the response handler + always @(posedge clk) begin + if (resetn == 1'b0) begin + enabled <= 1'b0; + end else if (enable == 1'b1) begin + enabled <= 1'b1; + end else if (request_id == id) begin + enabled <= 1'b0; + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + id <= 'h0; + end else if (bready == 1'b1 && bvalid == 1'b1) begin + id <= inc_id(id); + end + end + +endmodule diff --git a/adi_library/axi_dmac/splitter.v b/adi_library/axi_dmac/splitter.v new file mode 100644 index 00000000..93e2cfe3 --- /dev/null +++ b/adi_library/axi_dmac/splitter.v @@ -0,0 +1,68 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module splitter #( + + parameter NUM_M = 2 +) ( + input clk, + input resetn, + + input s_valid, + output s_ready, + + output [NUM_M-1:0] m_valid, + input [NUM_M-1:0] m_ready +); + + reg [NUM_M-1:0] acked; + + assign s_ready = &(m_ready | acked); + assign m_valid = s_valid ? ~acked : {NUM_M{1'b0}}; + + always @(posedge clk) begin + if (resetn == 1'b0) begin + acked <= {NUM_M{1'b0}}; + end else begin + if (s_valid & s_ready) + acked <= {NUM_M{1'b0}}; + else + acked <= acked | (m_ready & m_valid); + end + end + +endmodule diff --git a/adi_library/axi_dmac/src_axi_mm.v b/adi_library/axi_dmac/src_axi_mm.v new file mode 100644 index 00000000..e3cd4e02 --- /dev/null +++ b/adi_library/axi_dmac/src_axi_mm.v @@ -0,0 +1,236 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module src_axi_mm #( + + parameter ID_WIDTH = 3, + parameter DMA_DATA_WIDTH = 64, + parameter DMA_ADDR_WIDTH = 32, + parameter BYTES_PER_BEAT_WIDTH = 3, + parameter BEATS_PER_BURST_WIDTH = 4, + parameter AXI_LENGTH_WIDTH = 8 +) ( + input m_axi_aclk, + input m_axi_aresetn, + + input req_valid, + output req_ready, + input [DMA_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH] req_address, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + input [BYTES_PER_BEAT_WIDTH-1:0] req_last_beat_bytes, + + input enable, + output reg enabled = 1'b0, + + output bl_valid, + input bl_ready, + output [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length, +/* + output response_valid, + input response_ready, + output [1:0] response_resp, +*/ + + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, + + output [ID_WIDTH-1:0] data_id, + output [ID_WIDTH-1:0] address_id, + input address_eot, + + output fifo_valid, + output [DMA_DATA_WIDTH-1:0] fifo_data, + output [BYTES_PER_BEAT_WIDTH-1:0] fifo_valid_bytes, + output fifo_last, + + // Read address + input m_axi_arready, + output m_axi_arvalid, + output [DMA_ADDR_WIDTH-1:0] m_axi_araddr, + output [AXI_LENGTH_WIDTH-1:0] m_axi_arlen, + output [ 2:0] m_axi_arsize, + output [ 1:0] m_axi_arburst, + output [ 2:0] m_axi_arprot, + output [ 3:0] m_axi_arcache, + + // Read data and response + input [DMA_DATA_WIDTH-1:0] m_axi_rdata, + output m_axi_rready, + input m_axi_rvalid, + input m_axi_rlast, + input [ 1:0] m_axi_rresp +); + + `include "inc_id.vh" + + reg [ID_WIDTH-1:0] id = 'h00; + + wire address_enabled; + wire req_ready_ag; + wire req_valid_ag; + wire bl_ready_ag; + wire bl_valid_ag; + + assign data_id = id; + assign response_id = id; + + assign measured_last_burst_length = req_last_burst_length; + + reg [BYTES_PER_BEAT_WIDTH-1:0] last_beat_bytes; + reg [BYTES_PER_BEAT_WIDTH-1:0] last_beat_bytes_mem[0:2**ID_WIDTH-1]; + + assign fifo_valid_bytes = last_beat_bytes_mem[data_id]; + + always @(posedge m_axi_aclk) begin + if (bl_ready_ag == 1'b1 && bl_valid_ag == 1'b1) begin + last_beat_bytes <= req_last_beat_bytes; + end + end + + always @(posedge m_axi_aclk) begin + last_beat_bytes_mem[address_id] <= address_eot ? last_beat_bytes : + {BYTES_PER_BEAT_WIDTH{1'b1}}; + end + + splitter #( + .NUM_M(3) + ) i_req_splitter ( + .clk(m_axi_aclk), + .resetn(m_axi_aresetn), + .s_valid(req_valid), + .s_ready(req_ready), + .m_valid({ + bl_valid, + bl_valid_ag, + req_valid_ag}), + .m_ready({ + bl_ready, + bl_ready_ag, + req_ready_ag})); + + address_generator #( + .ID_WIDTH(ID_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), + .BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH), + .DMA_DATA_WIDTH(DMA_DATA_WIDTH), + .LENGTH_WIDTH(AXI_LENGTH_WIDTH), + .DMA_ADDR_WIDTH(DMA_ADDR_WIDTH) + ) i_addr_gen ( + .clk(m_axi_aclk), + .resetn(m_axi_aresetn), + + .enable(enable), + .enabled(address_enabled), + + .request_id(request_id), + .id(address_id), + + .req_valid(req_valid_ag), + .req_ready(req_ready_ag), + .req_address(req_address), + + .bl_valid(bl_valid_ag), + .bl_ready(bl_ready_ag), + .measured_last_burst_length(req_last_burst_length), + + .eot(address_eot), + + .addr_ready(m_axi_arready), + .addr_valid(m_axi_arvalid), + .addr(m_axi_araddr), + .len(m_axi_arlen), + .size(m_axi_arsize), + .burst(m_axi_arburst), + .prot(m_axi_arprot), + .cache(m_axi_arcache)); + + assign fifo_valid = m_axi_rvalid; + assign fifo_data = m_axi_rdata; + assign fifo_last = m_axi_rlast; + + /* + * There is a requirement that data_id <= address_id (modulo 2**ID_WIDTH). We + * know that we will never receive data before we have requested it so there is + * an implicit dependency between data_id and address_id and no need to + * explicitly track it. + */ + always @(posedge m_axi_aclk) begin + if (m_axi_aresetn == 1'b0) begin + id <= 'h00; + end else if (m_axi_rvalid == 1'b1 && m_axi_rlast == 1'b1) begin + id <= inc_id(id); + end + end + + /* + * We won't be receiving data before we've requested it and we won't request + * data unless there is room in the store-and-forward memory. + */ + assign m_axi_rready = 1'b1; + + /* + * We need to complete all bursts for which an address has been put onto the + * AXI-MM interface. + */ + always @(posedge m_axi_aclk) begin + if (m_axi_aresetn == 1'b0) begin + enabled <= 1'b0; + end else if (address_enabled == 1'b1) begin + enabled <= 1'b1; + end else if (id == address_id) begin + enabled <= 1'b0; + end + end + + /* TODO + `include "resp.vh" + + assign response_valid = 1'b0; + assign response_resp = RESP_OKAY; + + reg [1:0] rresp; + + always @(posedge m_axi_aclk) + begin + if (m_axi_rvalid && m_axi_rready) begin + if (m_axi_rresp != 2'b0) + rresp <= m_axi_rresp; + end + end + */ + +endmodule diff --git a/adi_library/axi_dmac/src_axi_stream.v b/adi_library/axi_dmac/src_axi_stream.v new file mode 100644 index 00000000..d83c151c --- /dev/null +++ b/adi_library/axi_dmac/src_axi_stream.v @@ -0,0 +1,134 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module src_axi_stream #( + + parameter ID_WIDTH = 3, + parameter S_AXIS_DATA_WIDTH = 64, + parameter LENGTH_WIDTH = 24, + parameter BEATS_PER_BURST_WIDTH = 4 +) ( + input s_axis_aclk, + input s_axis_aresetn, + + input enable, + output enabled, + + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, + input eot, + + output rewind_req_valid, + input rewind_req_ready, + output [ID_WIDTH+3-1:0] rewind_req_data, + + output bl_valid, + input bl_ready, + output [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length, + + output block_descr_to_dst, + + output [ID_WIDTH-1:0] source_id, + output source_eot, + + output s_axis_ready, + input s_axis_valid, + input [S_AXIS_DATA_WIDTH-1:0] s_axis_data, + input [0:0] s_axis_user, + input s_axis_last, + output s_axis_xfer_req, + + output fifo_valid, + output [S_AXIS_DATA_WIDTH-1:0] fifo_data, + output fifo_last, + output fifo_partial_burst, + + input req_valid, + output req_ready, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + input req_sync_transfer_start, + input req_xlast +); + + assign enabled = enable; + + data_mover #( + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(S_AXIS_DATA_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH), + .ALLOW_ABORT(1) + ) i_data_mover ( + .clk(s_axis_aclk), + .resetn(s_axis_aresetn), + + .xfer_req(s_axis_xfer_req), + + .request_id(request_id), + .response_id(response_id), + .eot(eot), + + .rewind_req_valid(rewind_req_valid), + .rewind_req_ready(rewind_req_ready), + .rewind_req_data(rewind_req_data), + + .bl_valid(bl_valid), + .bl_ready(bl_ready), + .measured_last_burst_length(measured_last_burst_length), + + .block_descr_to_dst(block_descr_to_dst), + + .source_id(source_id), + .source_eot(source_eot), + + .req_valid(req_valid), + .req_ready(req_ready), + .req_last_burst_length(req_last_burst_length), + .req_sync_transfer_start(req_sync_transfer_start), + .req_xlast(req_xlast), + + .s_axi_valid(s_axis_valid), + .s_axi_ready(s_axis_ready), + .s_axi_data(s_axis_data), + .s_axi_last(s_axis_last), + .s_axi_sync(s_axis_user[0]), + + .m_axi_valid(fifo_valid), + .m_axi_data(fifo_data), + .m_axi_last(fifo_last), + .m_axi_partial_burst(fifo_partial_burst)); + +endmodule diff --git a/adi_library/axi_dmac/src_fifo_inf.v b/adi_library/axi_dmac/src_fifo_inf.v new file mode 100644 index 00000000..b5af3bfa --- /dev/null +++ b/adi_library/axi_dmac/src_fifo_inf.v @@ -0,0 +1,124 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module src_fifo_inf #( + + parameter ID_WIDTH = 3, + parameter DATA_WIDTH = 64, + parameter BEATS_PER_BURST_WIDTH = 4 +) ( + input clk, + input resetn, + + input enable, + output enabled, + + input [ID_WIDTH-1:0] request_id, + output [ID_WIDTH-1:0] response_id, + input eot, + + output bl_valid, + input bl_ready, + output [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length, + + input en, + input [DATA_WIDTH-1:0] din, + output reg overflow, + input sync, + output xfer_req, + + output fifo_valid, + output [DATA_WIDTH-1:0] fifo_data, + output fifo_last, + + input req_valid, + output req_ready, + input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length, + input req_sync_transfer_start +); + + wire ready; + wire valid; + + assign enabled = enable; + + assign valid = en & ready; + + always @(posedge clk) + begin + if (enable) begin + overflow <= en & ~ready; + end else begin + overflow <= en; + end + end + + data_mover #( + .ID_WIDTH(ID_WIDTH), + .DATA_WIDTH(DATA_WIDTH), + .BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH) + ) i_data_mover ( + .clk(clk), + .resetn(resetn), + + .xfer_req(xfer_req), + + .request_id(request_id), + .response_id(response_id), + .eot(eot), + + .bl_valid(bl_valid), + .bl_ready(bl_ready), + .measured_last_burst_length(measured_last_burst_length), + + .req_valid(req_valid), + .req_ready(req_ready), + .req_last_burst_length(req_last_burst_length), + .req_sync_transfer_start(req_sync_transfer_start), + .req_xlast(1'b0), + + .s_axi_ready(ready), + .s_axi_valid(valid), + .s_axi_data(din), + .s_axi_sync(sync), + .s_axi_last(1'b0), + + .m_axi_valid(fifo_valid), + .m_axi_data(fifo_data), + .m_axi_last(fifo_last)); + +endmodule diff --git a/adi_library/axi_dmac/tb/axi_read_slave.v b/adi_library/axi_dmac/tb/axi_read_slave.v new file mode 100644 index 00000000..2aa47b0e --- /dev/null +++ b/adi_library/axi_dmac/tb/axi_read_slave.v @@ -0,0 +1,100 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_read_slave #( + parameter DATA_WIDTH = 32, + parameter READ_ACCEPTANCE = 4, + parameter MIN_LATENCY = 48, + parameter MAX_LATENCY = 48 +) ( + input clk, + input reset, + + input arvalid, + output arready, + input [31:0] araddr, + input [7:0] arlen, + input [2:0] arsize, + input [1:0] arburst, + input [2:0] arprot, + input [3:0] arcache, + + output rvalid, + input rready, + output [DATA_WIDTH-1:0] rdata, + output [1:0] rresp, + output rlast +); + + reg [DATA_WIDTH-1:0] data = 'h00; + + wire [31:0] beat_addr; + + assign rresp = 2'b00; + assign rdata = data; + + always @(*) begin: gen_data + integer i; + for (i = 0; i < DATA_WIDTH; i = i + 8) begin + data[i+:8] <= beat_addr[7:0] + i / 8; + end + end + + axi_slave #( + .DATA_WIDTH(DATA_WIDTH), + .ACCEPTANCE(READ_ACCEPTANCE), + .MIN_LATENCY(MIN_LATENCY), + .MAX_LATENCY(MAX_LATENCY) + ) i_axi_slave ( + .clk(clk), + .reset(reset), + + .valid(arvalid), + .ready(arready), + .addr(araddr), + .len(arlen), + .size(arsize), + .burst(arburst), + .prot(arprot), + .cache(arcache), + + .beat_stb(rvalid), + .beat_ack(rvalid & rready), + .beat_last(rlast), + .beat_addr(beat_addr)); + +endmodule diff --git a/adi_library/axi_dmac/tb/axi_slave.v b/adi_library/axi_dmac/tb/axi_slave.v new file mode 100644 index 00000000..fc5199a1 --- /dev/null +++ b/adi_library/axi_dmac/tb/axi_slave.v @@ -0,0 +1,113 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_slave #( + parameter DATA_WIDTH = 32, + parameter ACCEPTANCE = 3, + parameter MIN_LATENCY = 16, + parameter MAX_LATENCY = 32 +) ( + input clk, + input reset, + + input valid, + output ready, + input [31:0] addr, + input [7:0] len, + input [2:0] size, + input [1:0] burst, + input [2:0] prot, + input [3:0] cache, + + output beat_stb, + input beat_ack, + output [31:0] beat_addr, + output beat_last +); + + reg [31:0] timestamp = 'h00; + + always @(posedge clk) begin + if (reset == 1'b1) begin + timestamp <= 'h00; + end else begin + timestamp <= timestamp + 1'b1; + end + end + + reg [32+32+8-1:0] req_fifo[0:15]; + reg [3:0] req_fifo_rd = 'h00; + reg [3:0] req_fifo_wr = 'h00; + wire [3:0] req_fifo_level = req_fifo_wr - req_fifo_rd; + + assign ready = req_fifo_level < ACCEPTANCE; + + always @(posedge clk) begin + if (reset == 1'b1) begin + req_fifo_wr <= 'h00; + end else begin + if (valid == 1'b1 && ready == 1'b1) begin + req_fifo[req_fifo_wr][71:40] <= timestamp + {$random} % (MAX_LATENCY - MIN_LATENCY + 1) + MIN_LATENCY; + req_fifo[req_fifo_wr][39:0] <= {addr,len}; + req_fifo_wr <= req_fifo_wr + 1'b1; + end + end + end + + reg [7:0] beat_counter = 'h00; + + assign beat_stb = req_fifo_level != 0 && timestamp > req_fifo[req_fifo_rd][71:40]; + assign beat_last = beat_stb ? beat_counter == req_fifo[req_fifo_rd][0+:8] : 1'b0; + assign beat_addr = req_fifo[req_fifo_rd][8+:32] + beat_counter * DATA_WIDTH / 8; + + always @(posedge clk) begin + if (reset == 1'b1) begin + beat_counter <= 'h00; + req_fifo_rd <= 'h00; + end else begin + if (beat_ack == 1'b1) begin + if (beat_last == 1'b1) begin + beat_counter <= 'h00; + req_fifo_rd <= req_fifo_rd + 1'b1; + end else begin + beat_counter <= beat_counter + 1'b1; + end + end + end + end + +endmodule diff --git a/adi_library/axi_dmac/tb/axi_write_slave.v b/adi_library/axi_dmac/tb/axi_write_slave.v new file mode 100644 index 00000000..06523220 --- /dev/null +++ b/adi_library/axi_dmac/tb/axi_write_slave.v @@ -0,0 +1,144 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_write_slave #( + parameter DATA_WIDTH = 32, + parameter WRITE_ACCEPTANCE = 3 +) ( + input clk, + input reset, + + input awvalid, + output awready, + input [31:0] awaddr, + input [7:0] awlen, + input [2:0] awsize, + input [1:0] awburst, + input [2:0] awprot, + input [3:0] awcache, + + input wvalid, + output wready, + input [DATA_WIDTH-1:0] wdata, + input [DATA_WIDTH/8-1:0] wstrb, + input wlast, + + output reg bvalid, + input bready, + output [1:0] bresp +); + + wire beat_last; + + axi_slave #( + .ACCEPTANCE(WRITE_ACCEPTANCE) + ) i_axi_slave ( + .clk(clk), + .reset(reset), + + .valid(awvalid), + .ready(awready), + .addr(awaddr), + .len(awlen), + .size(awsize), + .burst(awburst), + .prot(awprot), + .cache(awcache), + + .beat_stb(wready), + .beat_ack(wvalid & wready), + .beat_last(beat_last)); + + reg [4:0] resp_count = 'h00; + wire [4:0] resp_count_next; + reg [DATA_WIDTH-1:0] data_cmp = 'h00; + reg failed = 'b0; + + assign bresp = 2'b00; + + wire resp_count_dec = bvalid & bready; + wire resp_count_inc = wvalid & wready & beat_last; + assign resp_count_next = resp_count - resp_count_dec + resp_count_inc; + + always @(posedge clk) begin + if (reset == 1'b1) begin + resp_count <= 'h00; + end else begin + resp_count <= resp_count - resp_count_dec + resp_count_inc; + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + bvalid <= 1'b0; + end else if (bvalid == 1'b0 || bready == 1'b1) begin + if (resp_count_next != 'h00) begin + bvalid <= {$random} % 4 == 0; + end else begin + bvalid <= 1'b0; + end + end + end + + integer byte_count; + + always @(*) begin: count + integer i; + byte_count = 0; + for (i = 0; i < DATA_WIDTH / 8; i = i + 1) begin + byte_count = byte_count + wstrb[i]; + end + end + + always @(posedge clk) begin: gen_data_cmp + integer i; + if (reset) begin + for (i = 0; i < DATA_WIDTH; i = i + 8) begin + data_cmp[i+:8] <= i/8; + end + failed <= 'b0; + end else if (wvalid & wready) begin + for (i = 0; i < DATA_WIDTH; i = i + 8) begin + if (data_cmp[i+:8] !== wdata[i+:8] && wstrb[i/8] == 1'b1) begin + failed <= 1'b1; + end + data_cmp[i+:8] <= data_cmp[i+:8] + byte_count; + end + end + end + +endmodule diff --git a/adi_library/axi_dmac/tb/dma_read_shutdown_tb b/adi_library/axi_dmac/tb/dma_read_shutdown_tb new file mode 100755 index 00000000..0d590000 --- /dev/null +++ b/adi_library/axi_dmac/tb/dma_read_shutdown_tb @@ -0,0 +1,19 @@ +#!/bin/bash + +SOURCE="$0.v" +SOURCE+=" axi_read_slave.v axi_slave.v" +SOURCE+=" ../axi_dmac_transfer.v ../request_arb.v ../request_generator.v ../splitter.v" +SOURCE+=" ../dmac_2d_transfer.v" +SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v" +SOURCE+=" ../axi_dmac_burst_memory.v" +SOURCE+=" ../axi_dmac_reset_manager.v ../axi_register_slice.v" +SOURCE+=" ../dest_fifo_inf.v" +SOURCE+=" ../axi_dmac_response_manager.v" +SOURCE+=" ../src_axi_mm.v ../address_generator.v ../response_generator.v" +SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v" +SOURCE+=" ../../util_cdc/sync_bits.v" +SOURCE+=" ../../util_cdc/sync_event.v" +SOURCE+=" ../../common/ad_mem_asym.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/axi_dmac/tb/dma_read_shutdown_tb.v b/adi_library/axi_dmac/tb/dma_read_shutdown_tb.v new file mode 100644 index 00000000..c7568c5d --- /dev/null +++ b/adi_library/axi_dmac/tb/dma_read_shutdown_tb.v @@ -0,0 +1,161 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module dma_read_shutdown_tb; + parameter VCD_FILE = {`__FILE__,"cd"}; + + `include "tb_base.v" + + localparam TRANSFER_ADDR = 32'h80000000; + localparam TRANSFER_LEN = 24'h2ff; + + reg fifo_clk = 1'b0; + + wire awvalid; + wire awready; + wire [31:0] araddr; + wire [7:0] arlen; + wire [2:0] arsize; + wire [1:0] arburst; + wire [2:0] arprot; + wire [3:0] arcache; + + wire rlast; + wire rvalid; + wire rready; + wire [1:0] rresp; + wire [31:0] rdata; + + /* Twice as fast as the AXI clk so we have lots of read requests */ + always @(*) #5 fifo_clk <= ~fifo_clk; + + axi_read_slave #( + .DATA_WIDTH(32) + ) i_read_slave ( + .clk(clk), + .reset(reset), + + .arvalid(arvalid), + .arready(arready), + .araddr(araddr), + .arlen(arlen), + .arsize(arsize), + .arburst(arburst), + .arprot(arprot), + .arcache(arcache), + + .rready(rready), + .rvalid(rvalid), + .rdata(rdata), + .rresp(rresp), + .rlast(rlast)); + + wire [11:0] dbg_status; + + reg ctrl_enable = 1'b0; + + initial begin + #1000 + @(posedge clk) ctrl_enable <= 1'b1; + #3000 + @(posedge clk) ctrl_enable <= 1'b0; + end + + always @(posedge clk) begin + /* + * When disabled the DMA should eventually end up in an idle state and all + * requests that were sent out need to be accepted + */ + failed <= ctrl_enable == 1'b0 && ( + dbg_status !== 12'h701 || + i_read_slave.i_axi_slave.req_fifo_level !== 'h00); + end + + axi_dmac_transfer #( + .DMA_TYPE_SRC(0), + .DMA_TYPE_DEST(2), + .DMA_DATA_WIDTH_SRC(32), + .DMA_DATA_WIDTH_DEST(32), + .FIFO_SIZE(8), + .DMA_LENGTH_ALIGN(2) + ) i_transfer ( + .m_src_axi_aclk (clk), + .m_src_axi_aresetn(resetn), + + .m_axi_arvalid(arvalid), + .m_axi_arready(arready), + .m_axi_araddr(araddr), + .m_axi_arlen(arlen), + .m_axi_arsize(arsize), + .m_axi_arburst(arburst), + .m_axi_arprot(arprot), + .m_axi_arcache(arcache), + + .m_axi_rready(rready), + .m_axi_rvalid(rvalid), + .m_axi_rdata(rdata), + .m_axi_rlast(rlast), + .m_axi_rresp(rresp), + + .ctrl_clk(clk), + .ctrl_resetn(resetn), + + .ctrl_enable(ctrl_enable), + .ctrl_pause(1'b0), + + .req_eot(), + + .req_valid(1'b1), + .req_ready(), + .req_dest_address(TRANSFER_ADDR[31:2]), + .req_src_address(TRANSFER_ADDR[31:2]), + .req_x_length(TRANSFER_LEN), + .req_y_length(24'h00), + .req_dest_stride(24'h00), + .req_src_stride(24'h00), + .req_sync_transfer_start(1'b0), + .req_last(1'b0), + + .fifo_rd_clk(fifo_clk), + .fifo_rd_en(1'b1), + .fifo_rd_valid(), + .fifo_rd_underflow(), + .fifo_rd_dout(), + + .dbg_status(dbg_status)); + +endmodule diff --git a/adi_library/axi_dmac/tb/dma_read_tb b/adi_library/axi_dmac/tb/dma_read_tb new file mode 100755 index 00000000..8cbd2ffa --- /dev/null +++ b/adi_library/axi_dmac/tb/dma_read_tb @@ -0,0 +1,18 @@ +#!/bin/bash + +SOURCE="dma_read_tb.v" +SOURCE+=" axi_read_slave.v axi_slave.v" +SOURCE+=" ../axi_dmac_transfer.v ../dmac_2d_transfer.v ../request_arb.v ../request_generator.v ../splitter.v" +SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v" +SOURCE+=" ../axi_dmac_burst_memory.v" +SOURCE+=" ../axi_dmac_reset_manager.v ../axi_register_slice.v" +SOURCE+=" ../dest_fifo_inf.v" +SOURCE+=" ../axi_dmac_response_manager.v" +SOURCE+=" ../src_axi_mm.v ../address_generator.v ../response_generator.v" +SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v" +SOURCE+=" ../../util_cdc/sync_bits.v" +SOURCE+=" ../../util_cdc/sync_event.v" +SOURCE+=" ../../common/ad_mem_asym.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/axi_dmac/tb/dma_read_tb.v b/adi_library/axi_dmac/tb/dma_read_tb.v new file mode 100644 index 00000000..29e8ae42 --- /dev/null +++ b/adi_library/axi_dmac/tb/dma_read_tb.v @@ -0,0 +1,192 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module dma_read_tb; + parameter VCD_FILE = {`__FILE__,"cd"}; + parameter WIDTH_DEST = 32; + parameter WIDTH_SRC = 32; + parameter REQ_LEN_INC = 4; + parameter REQ_LEN_INIT = 4; + + `include "tb_base.v" + + localparam TRANSFER_ADDR = 32'h80000000; + + reg req_valid = 1'b1; + wire req_ready; + reg [23:0] req_length = REQ_LEN_INIT - 1; + + wire awvalid; + wire awready; + wire [31:0] araddr; + wire [7:0] arlen; + wire [2:0] arsize; + wire [1:0] arburst; + wire [2:0] arprot; + wire [3:0] arcache; + + wire rlast; + wire rvalid; + wire rready; + wire [1:0] rresp; + wire [WIDTH_SRC-1:0] rdata; + + always @(posedge clk) begin + if (reset != 1'b1 && req_ready == 1'b1) begin + req_valid <= 1'b1; + req_length <= req_length + REQ_LEN_INC; + end + end + + axi_read_slave #( + .DATA_WIDTH(WIDTH_SRC) + ) i_read_slave ( + .clk(clk), + .reset(reset), + + .arvalid(arvalid), + .arready(arready), + .araddr(araddr), + .arlen(arlen), + .arsize(arsize), + .arburst(arburst), + .arprot(arprot), + .arcache(arcache), + + .rready(rready), + .rvalid(rvalid), + .rdata(rdata), + .rresp(rresp), + .rlast(rlast)); + + wire fifo_rd_en = 1'b1; + wire fifo_rd_valid; + wire fifo_rd_underflow; + wire [WIDTH_DEST-1:0] fifo_rd_dout; + reg [WIDTH_DEST-1:0] fifo_rd_dout_cmp = 'h00; + reg fifo_rd_dout_mismatch = 1'b0; + reg [23:0] fifo_rd_req_length = REQ_LEN_INIT; + reg [23:0] fifo_rd_beat_counter = 'h00; + + axi_dmac_transfer #( + .DMA_TYPE_SRC(0), + .DMA_TYPE_DEST(2), + .DMA_DATA_WIDTH_SRC(WIDTH_SRC), + .DMA_DATA_WIDTH_DEST(WIDTH_DEST), + .DMA_LENGTH_ALIGN($clog2(WIDTH_DEST/8)), + .FIFO_SIZE(8) + ) transfer ( + .m_src_axi_aclk(clk), + .m_src_axi_aresetn(resetn), + + .m_axi_arvalid(arvalid), + .m_axi_arready(arready), + .m_axi_araddr(araddr), + .m_axi_arlen(arlen), + .m_axi_arsize(arsize), + .m_axi_arburst(arburst), + .m_axi_arprot(arprot), + .m_axi_arcache(arcache), + + .m_axi_rready(rready), + .m_axi_rvalid(rvalid), + .m_axi_rdata(rdata), + .m_axi_rlast(rlast), + .m_axi_rresp(rresp), + + .ctrl_clk(clk), + .ctrl_resetn(resetn), + + .ctrl_enable(1'b1), + .ctrl_pause(1'b0), + + .req_eot(eot), + + .req_valid(req_valid), + .req_ready(req_ready), + .req_dest_address(TRANSFER_ADDR[31:$clog2(WIDTH_DEST/8)]), + .req_src_address(TRANSFER_ADDR[31:$clog2(WIDTH_SRC/8)]), + .req_x_length(req_length), + .req_y_length(24'h00), + .req_dest_stride(24'h00), + .req_src_stride(24'h00), + .req_sync_transfer_start(1'b0), + + .fifo_rd_clk(clk), + .fifo_rd_en(fifo_rd_en), + .fifo_rd_valid(fifo_rd_valid), + .fifo_rd_underflow(fifo_rd_underflow), + .fifo_rd_dout(fifo_rd_dout)); + + always @(posedge clk) begin: dout + integer i; + + if (reset == 1'b1) begin + for (i = 0; i < WIDTH_DEST; i = i + 8) begin + fifo_rd_dout_cmp[i+:8] <= TRANSFER_ADDR[7:0] + i / 8; + end + fifo_rd_dout_mismatch <= 1'b0; + fifo_rd_req_length <= REQ_LEN_INIT; + fifo_rd_beat_counter <= 'h00; + end else begin + fifo_rd_dout_mismatch <= 1'b0; + + if (fifo_rd_valid == 1'b1) begin + if (fifo_rd_beat_counter + WIDTH_DEST / 8 < fifo_rd_req_length) begin + for (i = 0; i < WIDTH_DEST; i = i + 8) begin + fifo_rd_dout_cmp[i+:8] <= fifo_rd_dout_cmp[i+:8] + WIDTH_DEST / 8; + end + fifo_rd_beat_counter <= fifo_rd_beat_counter + WIDTH_DEST / 8; + end else begin + for (i = 0; i < WIDTH_DEST; i = i + 8) begin + fifo_rd_dout_cmp[i+:8] <= TRANSFER_ADDR[7:0] + i / 8; + end + fifo_rd_beat_counter <= 'h00; + fifo_rd_req_length <= fifo_rd_req_length + REQ_LEN_INC; + end + if (fifo_rd_dout_cmp != fifo_rd_dout) begin + fifo_rd_dout_mismatch <= 1'b1; + end + end + end + end + + always @(posedge clk) begin + failed <= failed | fifo_rd_dout_mismatch; + end + +endmodule diff --git a/adi_library/axi_dmac/tb/dma_write_shutdown_tb b/adi_library/axi_dmac/tb/dma_write_shutdown_tb new file mode 100755 index 00000000..c785231d --- /dev/null +++ b/adi_library/axi_dmac/tb/dma_write_shutdown_tb @@ -0,0 +1,19 @@ +#!/bin/bash + +SOURCE="$0.v" +SOURCE+=" axi_write_slave.v axi_slave.v" +SOURCE+=" ../axi_dmac_transfer.v ../request_arb.v ../request_generator.v ../splitter.v" +SOURCE+=" ../dmac_2d_transfer.v" +SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v" +SOURCE+=" ../axi_dmac_burst_memory.v" +SOURCE+=" ../axi_dmac_reset_manager.v ../data_mover.v ../axi_register_slice.v" +SOURCE+=" ../src_fifo_inf.v" +SOURCE+=" ../axi_dmac_response_manager.v" +SOURCE+=" ../dest_axi_mm.v ../response_handler.v ../address_generator.v" +SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v" +SOURCE+=" ../../util_cdc/sync_bits.v" +SOURCE+=" ../../util_cdc/sync_event.v" +SOURCE+=" ../../common/ad_mem_asym.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/axi_dmac/tb/dma_write_shutdown_tb.v b/adi_library/axi_dmac/tb/dma_write_shutdown_tb.v new file mode 100644 index 00000000..eaefcb2a --- /dev/null +++ b/adi_library/axi_dmac/tb/dma_write_shutdown_tb.v @@ -0,0 +1,168 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module dma_write_shutdown_tb; + parameter VCD_FILE = {`__FILE__,"cd"}; + + `include "tb_base.v" + + localparam TRANSFER_ADDR = 32'h80000000; + localparam TRANSFER_LEN = 24'h2ff; + + reg fifo_clk = 1'b0; + + wire awvalid; + wire awready; + wire [31:0] awaddr; + wire [7:0] awlen; + wire [2:0] awsize; + wire [1:0] awburst; + wire [2:0] awprot; + wire [3:0] awcache; + + wire wlast; + wire wvalid; + wire wready; + wire [3:0] wstrb; + wire [31:0] wdata; + + wire bready; + wire bvalid; + wire [1:0] bresp; + + wire [11:0] dbg_status; + + /* Twice as fast as the AXI clk so the FIFO fills up */ + always @(*) #5 fifo_clk <= ~fifo_clk; + + axi_write_slave #( + .DATA_WIDTH(32) + ) i_write_slave ( + .clk(clk), + .reset(reset), + + .awvalid(awvalid), + .awready(awready), + .awaddr(awaddr), + .awlen(awlen), + .awsize(awsize), + .awburst(awburst), + .awprot(awprot), + .awcache(awcache), + + .wready(wready), + .wvalid(wvalid), + .wdata(wdata), + .wstrb(wstrb), + .wlast(wlast), + + .bvalid(bvalid), + .bready(bready), + .bresp(bresp)); + + reg ctrl_enable = 1'b0; + + initial begin + #1000 + @(posedge clk) ctrl_enable <= 1'b1; + #3000 + @(posedge clk) ctrl_enable <= 1'b0; + end + + always @(posedge clk) begin + failed <= ctrl_enable == 1'b0 && ( + dbg_status !== 12'h701 || + i_write_slave.i_axi_slave.req_fifo_level !== 'h00); + end + + axi_dmac_transfer #( + .DMA_DATA_WIDTH_SRC(32), + .DMA_DATA_WIDTH_DEST(32), + .FIFO_SIZE(8), + .DMA_LENGTH_ALIGN(2) + ) i_transfer ( + .m_dest_axi_aclk (clk), + .m_dest_axi_aresetn(resetn), + + .m_axi_awvalid(awvalid), + .m_axi_awready(awready), + .m_axi_awaddr(awaddr), + .m_axi_awlen(awlen), + .m_axi_awsize(awsize), + .m_axi_awburst(awburst), + .m_axi_awprot(awprot), + .m_axi_awcache(awcache), + + .m_axi_wready(wready), + .m_axi_wvalid(wvalid), + .m_axi_wdata(wdata), + .m_axi_wstrb(wstrb), + .m_axi_wlast(wlast), + + .m_axi_bvalid(bvalid), + .m_axi_bready(bready), + .m_axi_bresp(bresp), + + .ctrl_clk(clk), + .ctrl_resetn(resetn), + + .ctrl_enable(ctrl_enable), + .ctrl_pause(1'b0), + + .req_eot(), + .req_response_ready(1'b1), + + .req_valid(1'b1), + .req_ready(), + .req_dest_address(TRANSFER_ADDR[31:2]), + .req_src_address(TRANSFER_ADDR[31:2]), + .req_x_length(TRANSFER_LEN), + .req_y_length(24'h00), + .req_dest_stride(24'h00), + .req_src_stride(24'h00), + .req_sync_transfer_start(1'b0), + .req_last(1'b0), + + .fifo_wr_clk(fifo_clk), + .fifo_wr_en(1'b1), + .fifo_wr_din(32'h00), + .fifo_wr_sync(1'b1), + .fifo_wr_xfer_req(), + + .dbg_status(dbg_status)); + +endmodule diff --git a/adi_library/axi_dmac/tb/dma_write_tb b/adi_library/axi_dmac/tb/dma_write_tb new file mode 100755 index 00000000..ed7a8aa1 --- /dev/null +++ b/adi_library/axi_dmac/tb/dma_write_tb @@ -0,0 +1,18 @@ +#!/bin/bash + +SOURCE="dma_write_tb.v" +SOURCE+=" axi_write_slave.v axi_slave.v" +SOURCE+=" ../axi_dmac_transfer.v ../dmac_2d_transfer.v ../request_arb.v ../request_generator.v ../splitter.v" +SOURCE+=" ../axi_dmac_resize_src.v ../axi_dmac_resize_dest.v" +SOURCE+=" ../axi_dmac_burst_memory.v" +SOURCE+=" ../axi_dmac_reset_manager.v ../data_mover.v ../axi_register_slice.v" +SOURCE+=" ../src_fifo_inf.v" +SOURCE+=" ../axi_dmac_response_manager.v" +SOURCE+=" ../dest_axi_mm.v ../response_handler.v ../address_generator.v" +SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v" +SOURCE+=" ../../util_cdc/sync_bits.v" +SOURCE+=" ../../util_cdc/sync_event.v" +SOURCE+=" ../../common/ad_mem_asym.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/axi_dmac/tb/dma_write_tb.v b/adi_library/axi_dmac/tb/dma_write_tb.v new file mode 100644 index 00000000..21319135 --- /dev/null +++ b/adi_library/axi_dmac/tb/dma_write_tb.v @@ -0,0 +1,190 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module dma_write_tb; + parameter VCD_FILE = {`__FILE__,"cd"}; + parameter WIDTH_DEST = 32; + parameter WIDTH_SRC = 32; + parameter REQ_LEN_INC = 4; + parameter REQ_LEN_INIT = 4; + + `include "tb_base.v" + + localparam TRANSFER_ADDR = 32'h80000000; + + reg req_valid = 1'b1; + wire req_ready; + reg [23:0] req_length = REQ_LEN_INIT - 1; + wire awvalid; + wire awready; + wire [31:0] awaddr; + wire [7:0] awlen; + wire [2:0] awsize; + wire [1:0] awburst; + wire [2:0] awprot; + wire [3:0] awcache; + + wire wlast; + wire wvalid; + wire wready; + wire [WIDTH_DEST/8-1:0] wstrb; + wire [WIDTH_DEST-1:0] wdata; + + reg [WIDTH_SRC-1:0] fifo_wr_din = 'b0; + reg fifo_wr_rq = 'b0; + wire fifo_wr_xfer_req; + + wire bready; + wire bvalid; + wire [1:0] bresp; + + always @(posedge clk) begin + if (reset != 1'b1 && req_ready == 1'b1) begin + req_valid <= 1'b1; + req_length <= req_length + REQ_LEN_INC; + end + end + + axi_write_slave #( + .DATA_WIDTH(WIDTH_DEST) + ) i_write_slave ( + .clk(clk), + .reset(reset), + + .awvalid(awvalid), + .awready(awready), + .awaddr(awaddr), + .awlen(awlen), + .awsize(awsize), + .awburst(awburst), + .awprot(awprot), + .awcache(awcache), + + .wready(wready), + .wvalid(wvalid), + .wdata(wdata), + .wstrb(wstrb), + .wlast(wlast), + + .bvalid(bvalid), + .bready(bready), + .bresp(bresp)); + + axi_dmac_transfer #( + .DMA_DATA_WIDTH_SRC(WIDTH_SRC), + .DMA_DATA_WIDTH_DEST(WIDTH_DEST), + .DMA_LENGTH_ALIGN($clog2(WIDTH_SRC/8)) + ) i_transfer ( + .m_dest_axi_aclk (clk), + .m_dest_axi_aresetn(resetn), + + .m_axi_awvalid(awvalid), + .m_axi_awready(awready), + .m_axi_awaddr(awaddr), + .m_axi_awlen(awlen), + .m_axi_awsize(awsize), + .m_axi_awburst(awburst), + .m_axi_awprot(awprot), + .m_axi_awcache(awcache), + + .m_axi_wready(wready), + .m_axi_wvalid(wvalid), + .m_axi_wdata(wdata), + .m_axi_wstrb(wstrb), + .m_axi_wlast(wlast), + + .m_axi_bvalid(bvalid), + .m_axi_bready(bready), + .m_axi_bresp(bresp), + + .ctrl_clk(clk), + .ctrl_resetn(resetn), + + .ctrl_enable(1'b1), + .ctrl_pause(1'b0), + + .req_eot(eot), + .req_response_ready(1'b1), + + .req_valid(req_valid), + .req_ready(req_ready), + .req_dest_address(TRANSFER_ADDR[31:$clog2(WIDTH_DEST/8)]), + .req_src_address(TRANSFER_ADDR[31:$clog2(WIDTH_SRC/8)]), + .req_x_length(req_length), + .req_y_length(24'h00), + .req_dest_stride(24'h00), + .req_src_stride(24'h00), + .req_sync_transfer_start(1'b0), + + .fifo_wr_clk(clk), + .fifo_wr_en(fifo_wr_en), + .fifo_wr_din(fifo_wr_din), + .fifo_wr_overflow(fifo_wr_overflow), + .fifo_wr_sync(1'b1), + .fifo_wr_xfer_req(fifo_wr_xfer_req)); + + always @(posedge clk) begin: fifo_wr + integer i; + + if (reset == 1'b1) begin + for (i = 0; i < WIDTH_SRC; i = i + 8) begin + fifo_wr_din[i+:8] <= i / 8; + end + fifo_wr_rq <= 'b0; + end else begin + if (fifo_wr_en == 1'b1) begin + for (i = 0; i < WIDTH_SRC; i = i + 8) begin + fifo_wr_din[i+:8] <= fifo_wr_din[i+:8] + WIDTH_SRC / 8; + end + end + fifo_wr_rq <= (($random % 4) == 0); + end + end + + assign fifo_wr_en = fifo_wr_rq & fifo_wr_xfer_req; + + always @(posedge clk) begin + if (reset) begin + failed <= 'b0; + end else begin + failed <= failed | + i_write_slave.failed | + fifo_wr_overflow; + end + end + +endmodule diff --git a/adi_library/axi_dmac/tb/regmap_tb b/adi_library/axi_dmac/tb/regmap_tb new file mode 100755 index 00000000..3cd6d143 --- /dev/null +++ b/adi_library/axi_dmac/tb/regmap_tb @@ -0,0 +1,10 @@ +#!/bin/bash + +SOURCE="regmap_tb.v" +SOURCE+=" ../axi_dmac_regmap.v ../axi_dmac_regmap_request.v" +SOURCE+=" ../../common/up_axi.v" +SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v" +SOURCE+=" ../../util_axis_fifo/util_axis_fifo_address_generator.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/axi_dmac/tb/regmap_tb.v b/adi_library/axi_dmac/tb/regmap_tb.v new file mode 100644 index 00000000..ae34be53 --- /dev/null +++ b/adi_library/axi_dmac/tb/regmap_tb.v @@ -0,0 +1,426 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module regmap_tb; + parameter VCD_FILE = {`__FILE__,"cd"}; + + `define TIMEOUT 1000000 + `include "tb_base.v" + + localparam DMA_LENGTH_WIDTH = 24; + localparam BYTES_PER_BEAT = 1; + localparam DMA_AXI_ADDR_WIDTH = 32; + + localparam LENGTH_ALIGN = 2; + localparam LENGTH_MASK = {DMA_LENGTH_WIDTH{1'b1}}; + localparam LENGTH_ALIGN_MASK = {LENGTH_ALIGN{1'b1}}; + localparam STRIDE_MASK = {{DMA_LENGTH_WIDTH-BYTES_PER_BEAT{1'b1}},{BYTES_PER_BEAT{1'b0}}}; + localparam ADDR_MASK = {{DMA_AXI_ADDR_WIDTH-BYTES_PER_BEAT{1'b1}},{BYTES_PER_BEAT{1'b0}}}; + + localparam VAL_DBG_SRC_ADDR = 32'h76543210; + localparam VAL_DBG_DEST_ADDR = 32'hfedcba98; + localparam VAL_DBG_STATUS = 12'ha5; + localparam VAL_DBG_IDS0 = 32'h01234567; + localparam VAL_DBG_IDS1 = 32'h89abcdef; + + localparam AW = 11; + localparam NUM_REGS = 'h200; + + wire s_axi_aclk = clk; + wire s_axi_aresetn = ~reset; + + reg s_axi_awvalid = 1'b0; + reg s_axi_wvalid = 1'b0; + reg [AW-1:0] s_axi_awaddr = 'h00; + reg [31:0] s_axi_wdata = 'h00; + wire [1:0] s_axi_bresp; + wire s_axi_awready; + wire s_axi_wready; + wire s_axi_bready = 1'b1; + wire [3:0] s_axi_wstrb = 4'b1111; + wire [2:0] s_axi_awprot = 3'b000; + wire [2:0] s_axi_arprot = 3'b000; + wire [1:0] s_axi_rresp; + wire [31:0] s_axi_rdata; + + task write_reg; + input [31:0] addr; + input [31:0] value; + begin + @(posedge s_axi_aclk) + s_axi_awvalid <= 1'b1; + s_axi_wvalid <= 1'b1; + s_axi_awaddr <= addr; + s_axi_wdata <= value; + @(posedge s_axi_aclk) + while (s_axi_awvalid || s_axi_wvalid) begin + @(posedge s_axi_aclk) + if (s_axi_awready) + s_axi_awvalid <= 1'b0; + if (s_axi_wready) + s_axi_wvalid <= 1'b0; + end + end + endtask + + reg [31:0] expected_reg_mem[0:NUM_REGS-1]; + + reg [AW-1:0] s_axi_araddr = 'h0; + reg s_axi_arvalid = 'h0; + reg s_axi_rready = 'h0; + wire s_axi_arready; + wire s_axi_rvalid; + + task read_reg; + input [31:0] addr; + output [31:0] value; + begin + s_axi_arvalid <= 1'b1; + s_axi_araddr <= addr; + s_axi_rready <= 1'b1; + @(posedge s_axi_aclk) #0; + while (s_axi_arvalid) begin + if (s_axi_arready == 1'b1) begin + s_axi_arvalid <= 1'b0; + end + @(posedge s_axi_aclk) #0; + end + + while (s_axi_rready) begin + if (s_axi_rvalid == 1'b1) begin + value <= s_axi_rdata; + s_axi_rready <= 1'b0; + end + @(posedge s_axi_aclk) #0; + end + end + endtask + + task read_reg_check; + input [31:0] addr; + output match; + reg [31:0] value; + reg [31:0] expected; + input [255:0] message; + begin + read_reg(addr, value); + expected = expected_reg_mem[addr[11:2]]; + match <= value === expected; + if (value !== expected) begin + $display("%0s: Register mismatch for %x. Expected %x, got %x", + message, addr, expected, value); + end + end + endtask + + reg read_match = 1'b1; + + always @(posedge clk) begin + if (read_match == 1'b0) begin + failed <= 1'b1; + end + end + + task set_reset_reg_value; + input [31:0] addr; + input [31:0] value; + begin + expected_reg_mem[addr[AW-1:2]] <= value; + end + endtask + + task initialize_expected_reg_mem; + integer i; + begin + for (i = 0; i < NUM_REGS; i = i + 1) + expected_reg_mem[i] <= 'h00; + /* Non zero power-on-reset values */ + set_reset_reg_value('h00, 32'h00040361); /* PCORE version register */ + set_reset_reg_value('h0c, 32'h444d4143); /* PCORE magic register */ + set_reset_reg_value('h10, 32'h00002101); /* Interface Description*/ + set_reset_reg_value('h80, 'h3); /* IRQ mask */ + + set_reset_reg_value('h40c, 'h3); /* Flags */ + set_reset_reg_value('h418, LENGTH_ALIGN_MASK); /* Length alignment */ + + set_reset_reg_value('h434, VAL_DBG_DEST_ADDR); + set_reset_reg_value('h438, VAL_DBG_SRC_ADDR); + set_reset_reg_value('h43c, VAL_DBG_STATUS); + set_reset_reg_value('h440, VAL_DBG_IDS0); + set_reset_reg_value('h444, VAL_DBG_IDS1); + end + endtask + + task check_all_registers; + input [255:0] message; + integer i; + begin + for (i = 0; i < NUM_REGS*4; i = i + 4) begin + read_reg_check(i, read_match, message); + end + end + endtask + + task write_reg_and_update; + input [31:0] addr; + input [31:0] value; + integer i; + begin + write_reg(addr, value); + expected_reg_mem[addr[AW-1:2]] <= value; + end + endtask + + task invert_register; + input [31:0] addr; + reg [31:0] value; + begin + read_reg(addr, value); + write_reg(addr, ~value); + end + endtask + + task invert_all_registers; + integer i; + begin + for (i = 0; i < NUM_REGS*4; i = i + 4) begin + invert_register(i); + end + end + endtask + + reg request_ready = 1'b0; + wire [31:BYTES_PER_BEAT] request_dest_address; + wire [31:BYTES_PER_BEAT] request_src_address; + wire [DMA_LENGTH_WIDTH-1:0] request_x_length; + wire [DMA_LENGTH_WIDTH-1:0] request_y_length; + wire [DMA_LENGTH_WIDTH-1:0] request_dest_stride; + wire [DMA_LENGTH_WIDTH-1:0] request_src_stride; + wire request_last; + + reg response_eot = 1'b0; + + wire [6:0] response_measured_burst_length = 'hff; + wire ctrl_enable; + wire ctrl_pause; + wire request_valid; + wire request_sync_transfer_start; + wire response_partial = 1'b1; + + reg response_valid = 1'b0; + wire response_ready; + + always @(posedge clk) begin + if (request_valid & request_ready) begin + response_valid <= 1'b1; + end else if (response_ready) begin + response_valid <= 1'b0; + end + end + + integer i; + initial begin + initialize_expected_reg_mem(); + @(posedge s_axi_aresetn) + set_reset_reg_value('h44c, 32'hxxxxxxxx); + set_reset_reg_value('h450, 2'bX); + check_all_registers("Initial"); + + /* Check scratch */ + write_reg_and_update('h08, 32'h12345678); + check_all_registers("Scratch"); + + /* Check IRQ mask */ + write_reg_and_update('h80, 32'h0); + check_all_registers("IRQ mask"); + + /* Check transfer registers */ + write_reg_and_update('h40c, 'h7); + write_reg_and_update('h410, ADDR_MASK); + write_reg_and_update('h414, ADDR_MASK); + write_reg_and_update('h418, LENGTH_MASK); + write_reg_and_update('h41c, LENGTH_MASK); + write_reg_and_update('h420, STRIDE_MASK); + write_reg_and_update('h424, STRIDE_MASK); + + check_all_registers("Transfer setup 1"); + + /* Check transfer registers */ + write_reg_and_update('h40c, {$random} & 'h7); + write_reg_and_update('h410, {$random} & ADDR_MASK); + write_reg_and_update('h414, {$random} & ADDR_MASK); + write_reg_and_update('h418, {$random} & LENGTH_MASK | LENGTH_ALIGN_MASK); + write_reg_and_update('h41c, {$random} & LENGTH_MASK); + write_reg_and_update('h420, {$random} & STRIDE_MASK); + write_reg_and_update('h424, {$random} & STRIDE_MASK); + + check_all_registers("Transfer setup 2"); + + /* Start transfer */ + write_reg_and_update('h400, 'h01); + write_reg_and_update('h408, 'h01); + set_reset_reg_value('h428, 32'h00000000); + set_reset_reg_value('h448, 24'h000000); + set_reset_reg_value('h44c, 32'hxxxxxxxx); + set_reset_reg_value('h450, 2'bX); + + check_all_registers("Transfer submitted"); + + @(posedge clk) request_ready <= 1'b1; + + /* Interrupt pending */ + set_reset_reg_value('h84, 'h01); + set_reset_reg_value('h88, 'h01); + + /* Transfer ID */ + set_reset_reg_value('h404, 'h01); + + /* Tansfer pending */ + set_reset_reg_value('h408, 'h00); + set_reset_reg_value('h428, 32'h80000000); + set_reset_reg_value('h448, 24'h000080); + set_reset_reg_value('h44c, 32'h00000080); + set_reset_reg_value('h450, 'h0); + check_all_registers("Transfer accepted"); + + @(posedge clk) response_eot <= 1'b1; + @(posedge clk) response_eot <= 1'b0; + + /* Interrupt registers */ + set_reset_reg_value('h84, 'h01); + set_reset_reg_value('h88, 'h01); + + set_reset_reg_value('h428, 'h00); + set_reset_reg_value('h42c, 'h00); + set_reset_reg_value('h44c, 32'h00000080); + set_reset_reg_value('h450, 'h0); + set_reset_reg_value('h448, 24'h000080); + + check_all_registers("Transfer completed"); + + /* Clear interrupts */ + write_reg('h84, 'h01); + set_reset_reg_value('h84, 'h00); + set_reset_reg_value('h88, 'h00); + + check_all_registers("Clear interrupts 1"); + + write_reg('h84, 'h02); + set_reset_reg_value('h84, 'h00); + set_reset_reg_value('h88, 'h00); + + check_all_registers("Clear interrupts 2"); + + /* Check that reset works for all registers */ + do_trigger_reset(); + initialize_expected_reg_mem(); + write_reg_and_update('h40c, 'h00); + set_reset_reg_value('h44c, 32'h00000080); + check_all_registers("Reset 1"); + invert_all_registers(); + do_trigger_reset(); + write_reg_and_update('h40c, 'h00); + set_reset_reg_value('h44c, 32'h00000080); + check_all_registers("Reset 2"); + end + + axi_dmac_regmap #( + .ID(0), + .DISABLE_DEBUG_REGISTERS(0), + .BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT), + .BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT), + .DMA_AXI_ADDR_WIDTH(DMA_AXI_ADDR_WIDTH), + .DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH), + .DMA_LENGTH_ALIGN(LENGTH_ALIGN), + .DMA_CYCLIC(1), + .BYTES_PER_BURST_WIDTH(7), + .HAS_DEST_ADDR(1), + .HAS_SRC_ADDR(1), + .DMA_2D_TRANSFER(1), + .SYNC_TRANSFER_START(0) + ) i_axi ( + .s_axi_aclk(s_axi_aclk), + .s_axi_aresetn(s_axi_aresetn), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awready(s_axi_awready), + .s_axi_awprot(s_axi_awprot), + .s_axi_wvalid(s_axi_wvalid), + .s_axi_wdata(s_axi_wdata), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wready(s_axi_wready), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_bresp(s_axi_bresp), + .s_axi_bready(s_axi_bready), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_araddr(s_axi_araddr), + .s_axi_arready(s_axi_arready), + .s_axi_arprot(s_axi_arprot), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_rready(s_axi_rready), + .s_axi_rresp(s_axi_rresp), + .s_axi_rdata(s_axi_rdata), + + .ctrl_enable(ctrl_enable), + .ctrl_pause(ctrl_pause), + + .request_valid(request_valid), + .request_ready(request_ready), + .request_dest_address(request_dest_address), + .request_src_address(request_src_address), + .request_x_length(request_x_length), + .request_y_length(request_y_length), + .request_dest_stride(request_dest_stride), + .request_src_stride(request_src_stride), + .request_last(request_last), + .request_sync_transfer_start(request_sync_transfer_start), + + .irq(irq), + + .response_eot(response_eot), + .response_measured_burst_length(response_measured_burst_length), + .response_partial(response_partial), + .response_valid(response_valid), + .response_ready(response_ready), + + .dbg_src_addr(VAL_DBG_SRC_ADDR), + .dbg_dest_addr(VAL_DBG_DEST_ADDR), + .dbg_status(VAL_DBG_STATUS), + .dbg_ids0(VAL_DBG_IDS0), + .dbg_ids1(VAL_DBG_IDS1)); + +endmodule diff --git a/adi_library/axi_dmac/tb/reset_manager_tb b/adi_library/axi_dmac/tb/reset_manager_tb new file mode 100755 index 00000000..dfd815bf --- /dev/null +++ b/adi_library/axi_dmac/tb/reset_manager_tb @@ -0,0 +1,8 @@ +#!/bin/bash + +SOURCE="$0.v" +SOURCE+=" ../axi_dmac_reset_manager.v" +SOURCE+=" ../../util_cdc/sync_bits.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/axi_dmac/tb/reset_manager_tb.v b/adi_library/axi_dmac/tb/reset_manager_tb.v new file mode 100644 index 00000000..b14c1c7a --- /dev/null +++ b/adi_library/axi_dmac/tb/reset_manager_tb.v @@ -0,0 +1,118 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module reset_manager_tb; + parameter VCD_FILE = {`__FILE__,"cd"}; + + `define TIMEOUT 1000000 + `include "tb_base.v" + + reg clk_a = 1'b0; + reg clk_b = 1'b0; + reg clk_c = 1'b0; + + reg [5:0] resetn_shift = 'h0; + + reg [10:0] counter = 'h00; + + reg ctrl_enable = 1'b0; + reg ctrl_pause = 1'b0; + + always #10 clk_a <= ~clk_a; + always #3 clk_b <= ~clk_b; + always #7 clk_c <= ~clk_c; + + always @(posedge clk_a) begin + counter <= counter + 1'b1; + if (counter == 'h60 || counter == 'h150 || counter == 'h185) begin + ctrl_enable <= 1'b1; + end else if (counter == 'h100 || counter == 'h110 || counter == 'h180) begin + ctrl_enable <= 1'b0; + end + + if (counter == 'h160) begin + ctrl_pause = 1'b1; + end else if (counter == 'h190) begin + ctrl_pause = 1'b0; + end + end + + reg [15:0] req_enabled_shift; + wire req_enable; + wire req_enabled = req_enabled_shift[15]; + + reg [15:0] dest_enabled_shift; + wire dest_enable; + wire dest_enabled = dest_enabled_shift[15]; + + reg [15:0] src_enabled_shift; + wire src_enable; + wire src_enabled = src_enabled_shift[15]; + + always @(posedge clk_a) begin + req_enabled_shift <= {req_enabled_shift[14:0],req_enable}; + end + + always @(posedge clk_b) begin + dest_enabled_shift <= {dest_enabled_shift[14:0],dest_enable}; + end + + always @(posedge clk_c) begin + src_enabled_shift <= {src_enabled_shift[14:0],src_enable}; + end + + axi_dmac_reset_manager i_reset_manager ( + .clk(clk_a), + .resetn(resetn), + + .ctrl_pause(ctrl_pause), + .ctrl_enable(ctrl_enable), + + .req_enable(req_enable), + .req_enabled(req_enabled), + + .dest_clk(clk_b), + .dest_ext_resetn(1'b0), + .dest_enable(dest_enable), + .dest_enabled(dest_enabled), + + .src_clk(clk_c), + .src_ext_resetn(1'b0), + .src_enable(src_enable), + .src_enabled(src_enabled)); + +endmodule diff --git a/adi_library/axi_dmac/tb/tb_base.v b/adi_library/axi_dmac/tb/tb_base.v new file mode 100644 index 00000000..f12267d2 --- /dev/null +++ b/adi_library/axi_dmac/tb/tb_base.v @@ -0,0 +1,76 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + + reg clk = 1'b0; + reg [3:0] reset_shift = 4'b1111; + reg trigger_reset = 1'b0; + wire reset; + wire resetn = ~reset; + + reg failed = 1'b0; + + initial + begin + $dumpfile (VCD_FILE); + $dumpvars; +`ifdef TIMEOUT + #`TIMEOUT +`else + #100000 +`endif + if (failed == 1'b0) + $display("SUCCESS"); + else + $display("FAILED"); + $finish; + end + + always @(*) #10 clk <= ~clk; + always @(posedge clk) begin + if (trigger_reset == 1'b1) begin + reset_shift <= 3'b111; + end else begin + reset_shift <= {reset_shift[2:0],1'b0}; + end + end + + assign reset = reset_shift[3]; + + task do_trigger_reset; + begin + @(posedge clk) trigger_reset <= 1'b1; + @(posedge clk) trigger_reset <= 1'b0; + end + endtask diff --git a/adi_library/axi_dmac/xgui/axi_dmac_v1_0.tcl b/adi_library/axi_dmac/xgui/axi_dmac_v1_0.tcl new file mode 100644 index 00000000..70acb061 --- /dev/null +++ b/adi_library/axi_dmac/xgui/axi_dmac_v1_0.tcl @@ -0,0 +1,602 @@ + +# Loading additional proc with user specified bodies to compute parameter values. +source [file join [file dirname [file dirname [info script]]] gui/axi_dmac_v1_0.gtcl] + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + #Adding Group + set DMA_Endpoint_Configuration [ipgui::add_group $IPINST -name "DMA Endpoint Configuration" -parent ${Page_0} -layout horizontal] + #Adding Group + set Source [ipgui::add_group $IPINST -name "Source" -parent ${DMA_Endpoint_Configuration}] + ipgui::add_param $IPINST -name "DMA_TYPE_SRC" -parent ${Source} -widget comboBox + ipgui::add_param $IPINST -name "DMA_AXI_PROTOCOL_SRC" -parent ${Source} -widget comboBox + set DMA_DATA_WIDTH_SRC [ipgui::add_param $IPINST -name "DMA_DATA_WIDTH_SRC" -parent ${Source}] + set_property tooltip {Bus Width: For Memory-Mapped interface the valid range is 32-1024 bits} ${DMA_DATA_WIDTH_SRC} + ipgui::add_param $IPINST -name "AXI_SLICE_SRC" -parent ${Source} + ipgui::add_param $IPINST -name "SYNC_TRANSFER_START" -parent ${Source} + + #Adding Group + set Destination [ipgui::add_group $IPINST -name "Destination" -parent ${DMA_Endpoint_Configuration}] + ipgui::add_param $IPINST -name "DMA_TYPE_DEST" -parent ${Destination} -widget comboBox + ipgui::add_param $IPINST -name "DMA_AXI_PROTOCOL_DEST" -parent ${Destination} -widget comboBox + set DMA_DATA_WIDTH_DEST [ipgui::add_param $IPINST -name "DMA_DATA_WIDTH_DEST" -parent ${Destination}] + set_property tooltip {Bus Width: For Memory-Mapped interface the valid range is 32-1024 bits} ${DMA_DATA_WIDTH_DEST} + ipgui::add_param $IPINST -name "AXI_SLICE_DEST" -parent ${Destination} + set CACHE_COHERENT_DEST [ipgui::add_param $IPINST -name "CACHE_COHERENT_DEST" -parent ${Destination}] + set_property tooltip {Assume destination port ensures cache coherency (e.g. Ultrascale HPC port)} ${CACHE_COHERENT_DEST} + + #Adding Group + set Scatter-Gather [ipgui::add_group $IPINST -name "Scatter-Gather" -parent ${DMA_Endpoint_Configuration}] + ipgui::add_param $IPINST -name "DMA_AXI_PROTOCOL_SG" -parent ${Scatter-Gather} + ipgui::add_param $IPINST -name "DMA_DATA_WIDTH_SG" -parent ${Scatter-Gather} + + + #Adding Group + set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${Page_0}] + ipgui::add_param $IPINST -name "ID" -parent ${General_Configuration} + ipgui::add_param $IPINST -name "DMA_LENGTH_WIDTH" -parent ${General_Configuration} + ipgui::add_param $IPINST -name "FIFO_SIZE" -parent ${General_Configuration} -widget comboBox + ipgui::add_param $IPINST -name "MAX_BYTES_PER_BURST" -parent ${General_Configuration} + ipgui::add_param $IPINST -name "DMA_AXI_ADDR_WIDTH" -parent ${General_Configuration} + + #Adding Group + set Features [ipgui::add_group $IPINST -name "Features" -parent ${Page_0}] + ipgui::add_param $IPINST -name "CYCLIC" -parent ${Features} + ipgui::add_param $IPINST -name "DMA_2D_TRANSFER" -parent ${Features} + ipgui::add_param $IPINST -name "DMA_SG_TRANSFER" -parent ${Features} + + #Adding Group + set Clock_Domain_Configuration [ipgui::add_group $IPINST -name "Clock Domain Configuration" -parent ${Page_0}] + ipgui::add_param $IPINST -name "ASYNC_CLK_REQ_SRC" -parent ${Clock_Domain_Configuration} + ipgui::add_param $IPINST -name "ASYNC_CLK_SRC_DEST" -parent ${Clock_Domain_Configuration} + ipgui::add_param $IPINST -name "ASYNC_CLK_DEST_REQ" -parent ${Clock_Domain_Configuration} + ipgui::add_param $IPINST -name "ASYNC_CLK_REQ_SG" -parent ${Clock_Domain_Configuration} + ipgui::add_param $IPINST -name "ASYNC_CLK_SRC_SG" -parent ${Clock_Domain_Configuration} + ipgui::add_param $IPINST -name "ASYNC_CLK_DEST_SG" -parent ${Clock_Domain_Configuration} + + #Adding Group + set Debug [ipgui::add_group $IPINST -name "Debug" -parent ${Page_0}] + ipgui::add_param $IPINST -name "DISABLE_DEBUG_REGISTERS" -parent ${Debug} + ipgui::add_param $IPINST -name "ENABLE_DIAGNOSTICS_IF" -parent ${Debug} + + + +} + +proc update_PARAM_VALUE.CACHE_COHERENT_DEST { PARAM_VALUE.CACHE_COHERENT_DEST PARAM_VALUE.DMA_TYPE_DEST PARAM_VALUE.DMA_AXI_PROTOCOL_DEST } { + # Procedure called to update CACHE_COHERENT_DEST when any of the dependent parameters in the arguments change + + set CACHE_COHERENT_DEST ${PARAM_VALUE.CACHE_COHERENT_DEST} + set DMA_TYPE_DEST ${PARAM_VALUE.DMA_TYPE_DEST} + set DMA_AXI_PROTOCOL_DEST ${PARAM_VALUE.DMA_AXI_PROTOCOL_DEST} + set values(DMA_TYPE_DEST) [get_property value $DMA_TYPE_DEST] + set values(DMA_AXI_PROTOCOL_DEST) [get_property value $DMA_AXI_PROTOCOL_DEST] + if { [gen_USERPARAMETER_CACHE_COHERENT_DEST_ENABLEMENT $values(DMA_TYPE_DEST) $values(DMA_AXI_PROTOCOL_DEST)] } { + set_property enabled true $CACHE_COHERENT_DEST + } else { + set_property enabled false $CACHE_COHERENT_DEST + set_property value [gen_USERPARAMETER_CACHE_COHERENT_DEST_VALUE $values(DMA_TYPE_DEST) $values(DMA_AXI_PROTOCOL_DEST)] $CACHE_COHERENT_DEST + } +} + +proc validate_PARAM_VALUE.CACHE_COHERENT_DEST { PARAM_VALUE.CACHE_COHERENT_DEST } { + # Procedure called to validate CACHE_COHERENT_DEST + return true +} + +proc update_PARAM_VALUE.DMA_AXI_PROTOCOL_DEST { PARAM_VALUE.DMA_AXI_PROTOCOL_DEST PARAM_VALUE.DMA_TYPE_DEST } { + # Procedure called to update DMA_AXI_PROTOCOL_DEST when any of the dependent parameters in the arguments change + + set DMA_AXI_PROTOCOL_DEST ${PARAM_VALUE.DMA_AXI_PROTOCOL_DEST} + set DMA_TYPE_DEST ${PARAM_VALUE.DMA_TYPE_DEST} + set values(DMA_TYPE_DEST) [get_property value $DMA_TYPE_DEST] + if { [gen_USERPARAMETER_DMA_AXI_PROTOCOL_DEST_ENABLEMENT $values(DMA_TYPE_DEST)] } { + set_property enabled true $DMA_AXI_PROTOCOL_DEST + } else { + set_property enabled false $DMA_AXI_PROTOCOL_DEST + } +} + +proc validate_PARAM_VALUE.DMA_AXI_PROTOCOL_DEST { PARAM_VALUE.DMA_AXI_PROTOCOL_DEST } { + # Procedure called to validate DMA_AXI_PROTOCOL_DEST + return true +} + +proc update_PARAM_VALUE.DMA_AXI_PROTOCOL_SG { PARAM_VALUE.DMA_AXI_PROTOCOL_SG PARAM_VALUE.DMA_SG_TRANSFER } { + # Procedure called to update DMA_AXI_PROTOCOL_SG when any of the dependent parameters in the arguments change + + set DMA_AXI_PROTOCOL_SG ${PARAM_VALUE.DMA_AXI_PROTOCOL_SG} + set DMA_SG_TRANSFER ${PARAM_VALUE.DMA_SG_TRANSFER} + set values(DMA_SG_TRANSFER) [get_property value $DMA_SG_TRANSFER] + if { [gen_USERPARAMETER_DMA_AXI_PROTOCOL_SG_ENABLEMENT $values(DMA_SG_TRANSFER)] } { + set_property enabled true $DMA_AXI_PROTOCOL_SG + } else { + set_property enabled false $DMA_AXI_PROTOCOL_SG + } +} + +proc validate_PARAM_VALUE.DMA_AXI_PROTOCOL_SG { PARAM_VALUE.DMA_AXI_PROTOCOL_SG } { + # Procedure called to validate DMA_AXI_PROTOCOL_SG + return true +} + +proc update_PARAM_VALUE.DMA_AXI_PROTOCOL_SRC { PARAM_VALUE.DMA_AXI_PROTOCOL_SRC PARAM_VALUE.DMA_TYPE_SRC } { + # Procedure called to update DMA_AXI_PROTOCOL_SRC when any of the dependent parameters in the arguments change + + set DMA_AXI_PROTOCOL_SRC ${PARAM_VALUE.DMA_AXI_PROTOCOL_SRC} + set DMA_TYPE_SRC ${PARAM_VALUE.DMA_TYPE_SRC} + set values(DMA_TYPE_SRC) [get_property value $DMA_TYPE_SRC] + if { [gen_USERPARAMETER_DMA_AXI_PROTOCOL_SRC_ENABLEMENT $values(DMA_TYPE_SRC)] } { + set_property enabled true $DMA_AXI_PROTOCOL_SRC + } else { + set_property enabled false $DMA_AXI_PROTOCOL_SRC + } +} + +proc validate_PARAM_VALUE.DMA_AXI_PROTOCOL_SRC { PARAM_VALUE.DMA_AXI_PROTOCOL_SRC } { + # Procedure called to validate DMA_AXI_PROTOCOL_SRC + return true +} + +proc update_PARAM_VALUE.DMA_DATA_WIDTH_SG { PARAM_VALUE.DMA_DATA_WIDTH_SG PARAM_VALUE.DMA_SG_TRANSFER } { + # Procedure called to update DMA_DATA_WIDTH_SG when any of the dependent parameters in the arguments change + + set DMA_DATA_WIDTH_SG ${PARAM_VALUE.DMA_DATA_WIDTH_SG} + set DMA_SG_TRANSFER ${PARAM_VALUE.DMA_SG_TRANSFER} + set values(DMA_SG_TRANSFER) [get_property value $DMA_SG_TRANSFER] + if { [gen_USERPARAMETER_DMA_DATA_WIDTH_SG_ENABLEMENT $values(DMA_SG_TRANSFER)] } { + set_property enabled true $DMA_DATA_WIDTH_SG + } else { + set_property enabled false $DMA_DATA_WIDTH_SG + } +} + +proc validate_PARAM_VALUE.DMA_DATA_WIDTH_SG { PARAM_VALUE.DMA_DATA_WIDTH_SG } { + # Procedure called to validate DMA_DATA_WIDTH_SG + return true +} + +proc update_PARAM_VALUE.SYNC_TRANSFER_START { PARAM_VALUE.SYNC_TRANSFER_START PARAM_VALUE.DMA_TYPE_SRC } { + # Procedure called to update SYNC_TRANSFER_START when any of the dependent parameters in the arguments change + + set SYNC_TRANSFER_START ${PARAM_VALUE.SYNC_TRANSFER_START} + set DMA_TYPE_SRC ${PARAM_VALUE.DMA_TYPE_SRC} + set values(DMA_TYPE_SRC) [get_property value $DMA_TYPE_SRC] + if { [gen_USERPARAMETER_SYNC_TRANSFER_START_ENABLEMENT $values(DMA_TYPE_SRC)] } { + set_property enabled true $SYNC_TRANSFER_START + } else { + set_property enabled false $SYNC_TRANSFER_START + } +} + +proc validate_PARAM_VALUE.SYNC_TRANSFER_START { PARAM_VALUE.SYNC_TRANSFER_START } { + # Procedure called to validate SYNC_TRANSFER_START + return true +} + +proc update_PARAM_VALUE.ALLOW_ASYM_MEM { PARAM_VALUE.ALLOW_ASYM_MEM } { + # Procedure called to update ALLOW_ASYM_MEM when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ALLOW_ASYM_MEM { PARAM_VALUE.ALLOW_ASYM_MEM } { + # Procedure called to validate ALLOW_ASYM_MEM + return true +} + +proc update_PARAM_VALUE.ASYNC_CLK_DEST_REQ { PARAM_VALUE.ASYNC_CLK_DEST_REQ } { + # Procedure called to update ASYNC_CLK_DEST_REQ when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASYNC_CLK_DEST_REQ { PARAM_VALUE.ASYNC_CLK_DEST_REQ } { + # Procedure called to validate ASYNC_CLK_DEST_REQ + return true +} + +proc update_PARAM_VALUE.ASYNC_CLK_DEST_SG { PARAM_VALUE.ASYNC_CLK_DEST_SG } { + # Procedure called to update ASYNC_CLK_DEST_SG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASYNC_CLK_DEST_SG { PARAM_VALUE.ASYNC_CLK_DEST_SG } { + # Procedure called to validate ASYNC_CLK_DEST_SG + return true +} + +proc update_PARAM_VALUE.ASYNC_CLK_REQ_SG { PARAM_VALUE.ASYNC_CLK_REQ_SG } { + # Procedure called to update ASYNC_CLK_REQ_SG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASYNC_CLK_REQ_SG { PARAM_VALUE.ASYNC_CLK_REQ_SG } { + # Procedure called to validate ASYNC_CLK_REQ_SG + return true +} + +proc update_PARAM_VALUE.ASYNC_CLK_REQ_SRC { PARAM_VALUE.ASYNC_CLK_REQ_SRC } { + # Procedure called to update ASYNC_CLK_REQ_SRC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASYNC_CLK_REQ_SRC { PARAM_VALUE.ASYNC_CLK_REQ_SRC } { + # Procedure called to validate ASYNC_CLK_REQ_SRC + return true +} + +proc update_PARAM_VALUE.ASYNC_CLK_SRC_DEST { PARAM_VALUE.ASYNC_CLK_SRC_DEST } { + # Procedure called to update ASYNC_CLK_SRC_DEST when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASYNC_CLK_SRC_DEST { PARAM_VALUE.ASYNC_CLK_SRC_DEST } { + # Procedure called to validate ASYNC_CLK_SRC_DEST + return true +} + +proc update_PARAM_VALUE.ASYNC_CLK_SRC_SG { PARAM_VALUE.ASYNC_CLK_SRC_SG } { + # Procedure called to update ASYNC_CLK_SRC_SG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASYNC_CLK_SRC_SG { PARAM_VALUE.ASYNC_CLK_SRC_SG } { + # Procedure called to validate ASYNC_CLK_SRC_SG + return true +} + +proc update_PARAM_VALUE.AXI_ID_WIDTH_DEST { PARAM_VALUE.AXI_ID_WIDTH_DEST } { + # Procedure called to update AXI_ID_WIDTH_DEST when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_ID_WIDTH_DEST { PARAM_VALUE.AXI_ID_WIDTH_DEST } { + # Procedure called to validate AXI_ID_WIDTH_DEST + return true +} + +proc update_PARAM_VALUE.AXI_ID_WIDTH_SG { PARAM_VALUE.AXI_ID_WIDTH_SG } { + # Procedure called to update AXI_ID_WIDTH_SG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_ID_WIDTH_SG { PARAM_VALUE.AXI_ID_WIDTH_SG } { + # Procedure called to validate AXI_ID_WIDTH_SG + return true +} + +proc update_PARAM_VALUE.AXI_ID_WIDTH_SRC { PARAM_VALUE.AXI_ID_WIDTH_SRC } { + # Procedure called to update AXI_ID_WIDTH_SRC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_ID_WIDTH_SRC { PARAM_VALUE.AXI_ID_WIDTH_SRC } { + # Procedure called to validate AXI_ID_WIDTH_SRC + return true +} + +proc update_PARAM_VALUE.AXI_SLICE_DEST { PARAM_VALUE.AXI_SLICE_DEST } { + # Procedure called to update AXI_SLICE_DEST when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_SLICE_DEST { PARAM_VALUE.AXI_SLICE_DEST } { + # Procedure called to validate AXI_SLICE_DEST + return true +} + +proc update_PARAM_VALUE.AXI_SLICE_SRC { PARAM_VALUE.AXI_SLICE_SRC } { + # Procedure called to update AXI_SLICE_SRC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_SLICE_SRC { PARAM_VALUE.AXI_SLICE_SRC } { + # Procedure called to validate AXI_SLICE_SRC + return true +} + +proc update_PARAM_VALUE.CYCLIC { PARAM_VALUE.CYCLIC } { + # Procedure called to update CYCLIC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CYCLIC { PARAM_VALUE.CYCLIC } { + # Procedure called to validate CYCLIC + return true +} + +proc update_PARAM_VALUE.DISABLE_DEBUG_REGISTERS { PARAM_VALUE.DISABLE_DEBUG_REGISTERS } { + # Procedure called to update DISABLE_DEBUG_REGISTERS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DISABLE_DEBUG_REGISTERS { PARAM_VALUE.DISABLE_DEBUG_REGISTERS } { + # Procedure called to validate DISABLE_DEBUG_REGISTERS + return true +} + +proc update_PARAM_VALUE.DMA_2D_TRANSFER { PARAM_VALUE.DMA_2D_TRANSFER } { + # Procedure called to update DMA_2D_TRANSFER when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_2D_TRANSFER { PARAM_VALUE.DMA_2D_TRANSFER } { + # Procedure called to validate DMA_2D_TRANSFER + return true +} + +proc update_PARAM_VALUE.DMA_AXIS_DEST_W { PARAM_VALUE.DMA_AXIS_DEST_W } { + # Procedure called to update DMA_AXIS_DEST_W when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_AXIS_DEST_W { PARAM_VALUE.DMA_AXIS_DEST_W } { + # Procedure called to validate DMA_AXIS_DEST_W + return true +} + +proc update_PARAM_VALUE.DMA_AXIS_ID_W { PARAM_VALUE.DMA_AXIS_ID_W } { + # Procedure called to update DMA_AXIS_ID_W when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_AXIS_ID_W { PARAM_VALUE.DMA_AXIS_ID_W } { + # Procedure called to validate DMA_AXIS_ID_W + return true +} + +proc update_PARAM_VALUE.DMA_AXI_ADDR_WIDTH { PARAM_VALUE.DMA_AXI_ADDR_WIDTH } { + # Procedure called to update DMA_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_AXI_ADDR_WIDTH { PARAM_VALUE.DMA_AXI_ADDR_WIDTH } { + # Procedure called to validate DMA_AXI_ADDR_WIDTH + return true +} + +proc update_PARAM_VALUE.DMA_DATA_WIDTH_DEST { PARAM_VALUE.DMA_DATA_WIDTH_DEST } { + # Procedure called to update DMA_DATA_WIDTH_DEST when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_DATA_WIDTH_DEST { PARAM_VALUE.DMA_DATA_WIDTH_DEST } { + # Procedure called to validate DMA_DATA_WIDTH_DEST + return true +} + +proc update_PARAM_VALUE.DMA_DATA_WIDTH_SRC { PARAM_VALUE.DMA_DATA_WIDTH_SRC } { + # Procedure called to update DMA_DATA_WIDTH_SRC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_DATA_WIDTH_SRC { PARAM_VALUE.DMA_DATA_WIDTH_SRC } { + # Procedure called to validate DMA_DATA_WIDTH_SRC + return true +} + +proc update_PARAM_VALUE.DMA_LENGTH_WIDTH { PARAM_VALUE.DMA_LENGTH_WIDTH } { + # Procedure called to update DMA_LENGTH_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_LENGTH_WIDTH { PARAM_VALUE.DMA_LENGTH_WIDTH } { + # Procedure called to validate DMA_LENGTH_WIDTH + return true +} + +proc update_PARAM_VALUE.DMA_SG_TRANSFER { PARAM_VALUE.DMA_SG_TRANSFER } { + # Procedure called to update DMA_SG_TRANSFER when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_SG_TRANSFER { PARAM_VALUE.DMA_SG_TRANSFER } { + # Procedure called to validate DMA_SG_TRANSFER + return true +} + +proc update_PARAM_VALUE.DMA_TYPE_DEST { PARAM_VALUE.DMA_TYPE_DEST } { + # Procedure called to update DMA_TYPE_DEST when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_TYPE_DEST { PARAM_VALUE.DMA_TYPE_DEST } { + # Procedure called to validate DMA_TYPE_DEST + return true +} + +proc update_PARAM_VALUE.DMA_TYPE_SRC { PARAM_VALUE.DMA_TYPE_SRC } { + # Procedure called to update DMA_TYPE_SRC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_TYPE_SRC { PARAM_VALUE.DMA_TYPE_SRC } { + # Procedure called to validate DMA_TYPE_SRC + return true +} + +proc update_PARAM_VALUE.ENABLE_DIAGNOSTICS_IF { PARAM_VALUE.ENABLE_DIAGNOSTICS_IF } { + # Procedure called to update ENABLE_DIAGNOSTICS_IF when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ENABLE_DIAGNOSTICS_IF { PARAM_VALUE.ENABLE_DIAGNOSTICS_IF } { + # Procedure called to validate ENABLE_DIAGNOSTICS_IF + return true +} + +proc update_PARAM_VALUE.FIFO_SIZE { PARAM_VALUE.FIFO_SIZE } { + # Procedure called to update FIFO_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FIFO_SIZE { PARAM_VALUE.FIFO_SIZE } { + # Procedure called to validate FIFO_SIZE + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.MAX_BYTES_PER_BURST { PARAM_VALUE.MAX_BYTES_PER_BURST } { + # Procedure called to update MAX_BYTES_PER_BURST when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.MAX_BYTES_PER_BURST { PARAM_VALUE.MAX_BYTES_PER_BURST } { + # Procedure called to validate MAX_BYTES_PER_BURST + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.DMA_DATA_WIDTH_SRC { MODELPARAM_VALUE.DMA_DATA_WIDTH_SRC PARAM_VALUE.DMA_DATA_WIDTH_SRC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_DATA_WIDTH_SRC}] ${MODELPARAM_VALUE.DMA_DATA_WIDTH_SRC} +} + +proc update_MODELPARAM_VALUE.DMA_DATA_WIDTH_DEST { MODELPARAM_VALUE.DMA_DATA_WIDTH_DEST PARAM_VALUE.DMA_DATA_WIDTH_DEST } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_DATA_WIDTH_DEST}] ${MODELPARAM_VALUE.DMA_DATA_WIDTH_DEST} +} + +proc update_MODELPARAM_VALUE.DMA_DATA_WIDTH_SG { MODELPARAM_VALUE.DMA_DATA_WIDTH_SG PARAM_VALUE.DMA_DATA_WIDTH_SG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_DATA_WIDTH_SG}] ${MODELPARAM_VALUE.DMA_DATA_WIDTH_SG} +} + +proc update_MODELPARAM_VALUE.DMA_LENGTH_WIDTH { MODELPARAM_VALUE.DMA_LENGTH_WIDTH PARAM_VALUE.DMA_LENGTH_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_LENGTH_WIDTH}] ${MODELPARAM_VALUE.DMA_LENGTH_WIDTH} +} + +proc update_MODELPARAM_VALUE.DMA_2D_TRANSFER { MODELPARAM_VALUE.DMA_2D_TRANSFER PARAM_VALUE.DMA_2D_TRANSFER } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_2D_TRANSFER}] ${MODELPARAM_VALUE.DMA_2D_TRANSFER} +} + +proc update_MODELPARAM_VALUE.DMA_SG_TRANSFER { MODELPARAM_VALUE.DMA_SG_TRANSFER PARAM_VALUE.DMA_SG_TRANSFER } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_SG_TRANSFER}] ${MODELPARAM_VALUE.DMA_SG_TRANSFER} +} + +proc update_MODELPARAM_VALUE.ASYNC_CLK_REQ_SRC { MODELPARAM_VALUE.ASYNC_CLK_REQ_SRC PARAM_VALUE.ASYNC_CLK_REQ_SRC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK_REQ_SRC}] ${MODELPARAM_VALUE.ASYNC_CLK_REQ_SRC} +} + +proc update_MODELPARAM_VALUE.ASYNC_CLK_SRC_DEST { MODELPARAM_VALUE.ASYNC_CLK_SRC_DEST PARAM_VALUE.ASYNC_CLK_SRC_DEST } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK_SRC_DEST}] ${MODELPARAM_VALUE.ASYNC_CLK_SRC_DEST} +} + +proc update_MODELPARAM_VALUE.ASYNC_CLK_DEST_REQ { MODELPARAM_VALUE.ASYNC_CLK_DEST_REQ PARAM_VALUE.ASYNC_CLK_DEST_REQ } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK_DEST_REQ}] ${MODELPARAM_VALUE.ASYNC_CLK_DEST_REQ} +} + +proc update_MODELPARAM_VALUE.ASYNC_CLK_REQ_SG { MODELPARAM_VALUE.ASYNC_CLK_REQ_SG PARAM_VALUE.ASYNC_CLK_REQ_SG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK_REQ_SG}] ${MODELPARAM_VALUE.ASYNC_CLK_REQ_SG} +} + +proc update_MODELPARAM_VALUE.ASYNC_CLK_SRC_SG { MODELPARAM_VALUE.ASYNC_CLK_SRC_SG PARAM_VALUE.ASYNC_CLK_SRC_SG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK_SRC_SG}] ${MODELPARAM_VALUE.ASYNC_CLK_SRC_SG} +} + +proc update_MODELPARAM_VALUE.ASYNC_CLK_DEST_SG { MODELPARAM_VALUE.ASYNC_CLK_DEST_SG PARAM_VALUE.ASYNC_CLK_DEST_SG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK_DEST_SG}] ${MODELPARAM_VALUE.ASYNC_CLK_DEST_SG} +} + +proc update_MODELPARAM_VALUE.AXI_SLICE_DEST { MODELPARAM_VALUE.AXI_SLICE_DEST PARAM_VALUE.AXI_SLICE_DEST } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_SLICE_DEST}] ${MODELPARAM_VALUE.AXI_SLICE_DEST} +} + +proc update_MODELPARAM_VALUE.AXI_SLICE_SRC { MODELPARAM_VALUE.AXI_SLICE_SRC PARAM_VALUE.AXI_SLICE_SRC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_SLICE_SRC}] ${MODELPARAM_VALUE.AXI_SLICE_SRC} +} + +proc update_MODELPARAM_VALUE.SYNC_TRANSFER_START { MODELPARAM_VALUE.SYNC_TRANSFER_START PARAM_VALUE.SYNC_TRANSFER_START } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SYNC_TRANSFER_START}] ${MODELPARAM_VALUE.SYNC_TRANSFER_START} +} + +proc update_MODELPARAM_VALUE.CYCLIC { MODELPARAM_VALUE.CYCLIC PARAM_VALUE.CYCLIC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CYCLIC}] ${MODELPARAM_VALUE.CYCLIC} +} + +proc update_MODELPARAM_VALUE.DMA_AXI_PROTOCOL_DEST { MODELPARAM_VALUE.DMA_AXI_PROTOCOL_DEST PARAM_VALUE.DMA_AXI_PROTOCOL_DEST } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_AXI_PROTOCOL_DEST}] ${MODELPARAM_VALUE.DMA_AXI_PROTOCOL_DEST} +} + +proc update_MODELPARAM_VALUE.DMA_AXI_PROTOCOL_SRC { MODELPARAM_VALUE.DMA_AXI_PROTOCOL_SRC PARAM_VALUE.DMA_AXI_PROTOCOL_SRC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_AXI_PROTOCOL_SRC}] ${MODELPARAM_VALUE.DMA_AXI_PROTOCOL_SRC} +} + +proc update_MODELPARAM_VALUE.DMA_AXI_PROTOCOL_SG { MODELPARAM_VALUE.DMA_AXI_PROTOCOL_SG PARAM_VALUE.DMA_AXI_PROTOCOL_SG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_AXI_PROTOCOL_SG}] ${MODELPARAM_VALUE.DMA_AXI_PROTOCOL_SG} +} + +proc update_MODELPARAM_VALUE.DMA_TYPE_DEST { MODELPARAM_VALUE.DMA_TYPE_DEST PARAM_VALUE.DMA_TYPE_DEST } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_TYPE_DEST}] ${MODELPARAM_VALUE.DMA_TYPE_DEST} +} + +proc update_MODELPARAM_VALUE.DMA_TYPE_SRC { MODELPARAM_VALUE.DMA_TYPE_SRC PARAM_VALUE.DMA_TYPE_SRC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_TYPE_SRC}] ${MODELPARAM_VALUE.DMA_TYPE_SRC} +} + +proc update_MODELPARAM_VALUE.DMA_AXI_ADDR_WIDTH { MODELPARAM_VALUE.DMA_AXI_ADDR_WIDTH PARAM_VALUE.DMA_AXI_ADDR_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.DMA_AXI_ADDR_WIDTH} +} + +proc update_MODELPARAM_VALUE.MAX_BYTES_PER_BURST { MODELPARAM_VALUE.MAX_BYTES_PER_BURST PARAM_VALUE.MAX_BYTES_PER_BURST } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.MAX_BYTES_PER_BURST}] ${MODELPARAM_VALUE.MAX_BYTES_PER_BURST} +} + +proc update_MODELPARAM_VALUE.FIFO_SIZE { MODELPARAM_VALUE.FIFO_SIZE PARAM_VALUE.FIFO_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FIFO_SIZE}] ${MODELPARAM_VALUE.FIFO_SIZE} +} + +proc update_MODELPARAM_VALUE.AXI_ID_WIDTH_SRC { MODELPARAM_VALUE.AXI_ID_WIDTH_SRC PARAM_VALUE.AXI_ID_WIDTH_SRC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_ID_WIDTH_SRC}] ${MODELPARAM_VALUE.AXI_ID_WIDTH_SRC} +} + +proc update_MODELPARAM_VALUE.AXI_ID_WIDTH_DEST { MODELPARAM_VALUE.AXI_ID_WIDTH_DEST PARAM_VALUE.AXI_ID_WIDTH_DEST } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_ID_WIDTH_DEST}] ${MODELPARAM_VALUE.AXI_ID_WIDTH_DEST} +} + +proc update_MODELPARAM_VALUE.AXI_ID_WIDTH_SG { MODELPARAM_VALUE.AXI_ID_WIDTH_SG PARAM_VALUE.AXI_ID_WIDTH_SG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_ID_WIDTH_SG}] ${MODELPARAM_VALUE.AXI_ID_WIDTH_SG} +} + +proc update_MODELPARAM_VALUE.DMA_AXIS_ID_W { MODELPARAM_VALUE.DMA_AXIS_ID_W PARAM_VALUE.DMA_AXIS_ID_W } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_AXIS_ID_W}] ${MODELPARAM_VALUE.DMA_AXIS_ID_W} +} + +proc update_MODELPARAM_VALUE.DMA_AXIS_DEST_W { MODELPARAM_VALUE.DMA_AXIS_DEST_W PARAM_VALUE.DMA_AXIS_DEST_W } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_AXIS_DEST_W}] ${MODELPARAM_VALUE.DMA_AXIS_DEST_W} +} + +proc update_MODELPARAM_VALUE.DISABLE_DEBUG_REGISTERS { MODELPARAM_VALUE.DISABLE_DEBUG_REGISTERS PARAM_VALUE.DISABLE_DEBUG_REGISTERS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DISABLE_DEBUG_REGISTERS}] ${MODELPARAM_VALUE.DISABLE_DEBUG_REGISTERS} +} + +proc update_MODELPARAM_VALUE.ENABLE_DIAGNOSTICS_IF { MODELPARAM_VALUE.ENABLE_DIAGNOSTICS_IF PARAM_VALUE.ENABLE_DIAGNOSTICS_IF } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ENABLE_DIAGNOSTICS_IF}] ${MODELPARAM_VALUE.ENABLE_DIAGNOSTICS_IF} +} + +proc update_MODELPARAM_VALUE.ALLOW_ASYM_MEM { MODELPARAM_VALUE.ALLOW_ASYM_MEM PARAM_VALUE.ALLOW_ASYM_MEM } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ALLOW_ASYM_MEM}] ${MODELPARAM_VALUE.ALLOW_ASYM_MEM} +} + +proc update_MODELPARAM_VALUE.CACHE_COHERENT_DEST { MODELPARAM_VALUE.CACHE_COHERENT_DEST PARAM_VALUE.CACHE_COHERENT_DEST } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CACHE_COHERENT_DEST}] ${MODELPARAM_VALUE.CACHE_COHERENT_DEST} +} + diff --git a/adi_library/axi_fan_control/Makefile b/adi_library/axi_fan_control/Makefile new file mode 100644 index 00000000..774932ab --- /dev/null +++ b/adi_library/axi_fan_control/Makefile @@ -0,0 +1,15 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_fan_control + +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/util_pulse_gen.v +GENERIC_DEPS += axi_fan_control.v + +XILINX_DEPS += axi_fan_control_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_fan_control/axi_fan_control.v b/adi_library/axi_fan_control/axi_fan_control.v new file mode 100644 index 00000000..cd03f6c0 --- /dev/null +++ b/adi_library/axi_fan_control/axi_fan_control.v @@ -0,0 +1,768 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +`timescale 1ns / 1ps + +module axi_fan_control #( + parameter ID = 0, + parameter PWM_FREQUENCY_HZ = 5000, + parameter INTERNAL_SYSMONE = 0, + parameter AVG_POW = 7, //do not exceede 7 + + //temperature thresholds defined to match sysmon reg values + parameter TACHO_TOL_PERCENT = 25, + parameter TACHO_T25 = 1470000, // 14.7 ms + parameter TACHO_T50 = 820000, // 8.2 ms + parameter TACHO_T75 = 480000, // 4.8 ms + parameter TACHO_T100 = 340000, // 3.4 ms + parameter TEMP_00_H = 05, + parameter TEMP_25_L = 20, + parameter TEMP_25_H = 40, + parameter TEMP_50_L = 60, + parameter TEMP_50_H = 70, + parameter TEMP_75_L = 80, + parameter TEMP_75_H = 90, + parameter TEMP_00_L = 95 +) ( + input [ 9:0] temp_in, + input tacho, + output reg irq, + output pwm, + + //axi interface + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready +); + + //local parameters + localparam [31:0] CORE_VERSION = {16'h0001, /* MAJOR */ + 8'h00, /* MINOR */ + 8'h61}; /* PATCH */ // 0.0.0 + localparam [31:0] CORE_MAGIC = 32'h46414E43; // FANC + + localparam CLK_FREQUENCY = 100000000; + localparam PWM_PERIOD = CLK_FREQUENCY / PWM_FREQUENCY_HZ; + localparam OVERFLOW_LIM = CLK_FREQUENCY * 5; + localparam AVERAGE_DIV = 2**AVG_POW; + + localparam THRESH_PWM_000 = (INTERNAL_SYSMONE == 1) ? (((TEMP_00_H + 280.2308787) * 65535) / 509.3140064) : ((TEMP_00_H * 41 + 11195) / 20); + localparam THRESH_PWM_025_L = (INTERNAL_SYSMONE == 1) ? (((TEMP_25_L + 280.2308787) * 65535) / 509.3140064) : ((TEMP_25_L * 41 + 11195) / 20); + localparam THRESH_PWM_025_H = (INTERNAL_SYSMONE == 1) ? (((TEMP_25_H + 280.2308787) * 65535) / 509.3140064) : ((TEMP_25_H * 41 + 11195) / 20); + localparam THRESH_PWM_050_L = (INTERNAL_SYSMONE == 1) ? (((TEMP_50_L + 280.2308787) * 65535) / 509.3140064) : ((TEMP_50_L * 41 + 11195) / 20); + localparam THRESH_PWM_050_H = (INTERNAL_SYSMONE == 1) ? (((TEMP_50_H + 280.2308787) * 65535) / 509.3140064) : ((TEMP_50_H * 41 + 11195) / 20); + localparam THRESH_PWM_075_L = (INTERNAL_SYSMONE == 1) ? (((TEMP_75_L + 280.2308787) * 65535) / 509.3140064) : ((TEMP_75_L * 41 + 11195) / 20); + localparam THRESH_PWM_075_H = (INTERNAL_SYSMONE == 1) ? (((TEMP_75_H + 280.2308787) * 65535) / 509.3140064) : ((TEMP_75_H * 41 + 11195) / 20); + localparam THRESH_PWM_100 = (INTERNAL_SYSMONE == 1) ? (((TEMP_00_L + 280.2308787) * 65535) / 509.3140064) : ((TEMP_00_L * 41 + 11195) / 20); + + //pwm params + localparam PWM_ONTIME_25 = PWM_PERIOD / 4; + localparam PWM_ONTIME_50 = PWM_PERIOD / 2; + localparam PWM_ONTIME_75 = PWM_PERIOD * 3 / 4; + + //tacho params + localparam TACHO_T25_TOL = TACHO_T25 * TACHO_TOL_PERCENT / 100; + localparam TACHO_T50_TOL = TACHO_T50 * TACHO_TOL_PERCENT / 100; + localparam TACHO_T75_TOL = TACHO_T75 * TACHO_TOL_PERCENT / 100; + localparam TACHO_T100_TOL = TACHO_T100 * TACHO_TOL_PERCENT / 100; + + //state machine states + localparam INIT = 8'h00; + localparam DRP_WAIT_EOC = 8'h01; + localparam DRP_WAIT_DRDY = 8'h02; + localparam DRP_WAIT_FSM_EN = 8'h03; + localparam DRP_READ_TEMP = 8'h04; + localparam DRP_READ_TEMP_WAIT_DRDY = 8'h05; + localparam GET_TACHO = 8'h06; + localparam EVAL_TEMP = 8'h07; + localparam SET_PWM = 8'h08; + localparam EVAL_TACHO = 8'h09; + + reg [31:0] up_scratch = 'd0; + reg [7:0] state = INIT; + reg [7:0] drp_daddr = 'h0; + reg [15:0] drp_di = 'h0; + reg [1:0] drp_den_reg = 'h0; + reg [1:0] drp_dwe_reg = 'h0; + reg [15:0] sysmone_temp = 'h0; + reg temp_increase_alarm = 'h0; + reg tacho_alarm = 'h0; + + reg [31:0] up_tacho_val = 'h0; + reg [31:0] up_tacho_tol = 'h0; + reg up_tacho_en = 'h0; + reg [7:0] tacho_avg_cnt = 'h0; + reg [31:0] tacho_avg_sum = 'h0; + reg [31:0] tacho_meas = 'h0; + reg tacho_delayed = 'h0; + reg tacho_meas_new = 'h0; + reg tacho_meas_ack = 'h0; + reg tacho_edge_det = 'h0; + reg [31:0] up_tacho_avg_sum = 'h0; + + reg [31:0] counter_reg = 'h0; + reg [31:0] pwm_width = 'h0; + reg [31:0] pwm_width_req = 'h0; + reg counter_overflow = 'h0; + reg pwm_change_done = 1'b1; + reg pulse_gen_load_config = 'h0; + reg tacho_meas_int = 'h0; + + reg [15:0] presc_reg = 'h0; + reg [31:0] up_pwm_width = 'd0; + + reg [31:0] up_temp_00_h = THRESH_PWM_000 ; + reg [31:0] up_temp_25_l = THRESH_PWM_025_L; + reg [31:0] up_temp_25_h = THRESH_PWM_025_H; + reg [31:0] up_temp_50_l = THRESH_PWM_050_L; + reg [31:0] up_temp_50_h = THRESH_PWM_050_H; + reg [31:0] up_temp_75_l = THRESH_PWM_075_L; + reg [31:0] up_temp_75_h = THRESH_PWM_075_H; + reg [31:0] up_temp_100_l = THRESH_PWM_100 ; + + reg [31:0] up_tacho_25 = TACHO_T25; + reg [31:0] up_tacho_50 = TACHO_T50; + reg [31:0] up_tacho_75 = TACHO_T75; + reg [31:0] up_tacho_100 = TACHO_T100; + reg [31:0] up_tacho_25_tol = TACHO_T25 * TACHO_TOL_PERCENT / 100; + reg [31:0] up_tacho_50_tol = TACHO_T50 * TACHO_TOL_PERCENT / 100; + reg [31:0] up_tacho_75_tol = TACHO_T75 * TACHO_TOL_PERCENT / 100; + reg [31:0] up_tacho_100_tol = TACHO_T100 * TACHO_TOL_PERCENT / 100; + + reg up_wack = 'd0; + reg [31:0] up_rdata = 'd0; + reg up_rack = 'd0; + reg up_resetn = 1'b0; + reg [3:0] up_irq_mask = 4'b1111; + reg [3:0] up_irq_source = 4'h0; + + wire counter_resetn; + wire [15:0] drp_do; + wire drp_drdy; + wire drp_eoc; + wire drp_eos; + + wire pwm_change_done_int; + wire pulse_gen_out; + wire up_clk; + wire up_rreq_s; + wire [7:0] up_raddr_s; + wire up_wreq_s; + wire [7:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire [3:0] up_irq_pending; + wire [3:0] up_irq_trigger; + wire [3:0] up_irq_source_clear; + + assign up_clk = s_axi_aclk; + assign pwm = ~pulse_gen_out & up_resetn; //reverse polarity because the board is also reversing it + assign pwm_change_done_int = counter_overflow & !pwm_change_done; + + //IRQ handling + assign up_irq_pending = ~up_irq_mask & up_irq_source; + assign up_irq_trigger = {tacho_meas_int, temp_increase_alarm, tacho_alarm, pwm_change_done_int}; + assign up_irq_source_clear = (up_wreq_s == 1'b1 && up_waddr_s == 8'h11) ? up_wdata_s[3:0] : 4'b0000; + + //switching the reset signal for the counter + //counter is used to measure tacho and to provide delay between pwm_ontime changes + assign counter_resetn = (pwm_change_done ) ? (!tacho_edge_det) : ((!pwm_change_done) & (!counter_overflow)); + + up_axi #( + .AXI_ADDRESS_WIDTH(10) + ) i_up_axi ( + .up_rstn (s_axi_aresetn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + + generate + if (INTERNAL_SYSMONE == 1) begin + SYSMONE4 #( + .COMMON_N_SOURCE(16'hFFFF), + .INIT_40(16'h1000), // config reg 0 + .INIT_41(16'h2F9F), // config reg 1 + .INIT_42(16'h1400), // config reg 2 + .INIT_43(16'h200F), // config reg 3 + .INIT_44(16'h0000), // config reg 4 + .INIT_45(16'hE200), // Analog Bus Register + .INIT_46(16'h0000), // Sequencer Channel selection (Vuser0-3) + .INIT_47(16'h0000), // Sequencer Average selection (Vuser0-3) + .INIT_48(16'h0101), // Sequencer channel selection + .INIT_49(16'h0000), // Sequencer channel selection + .INIT_4A(16'h0000), // Sequencer Average selection + .INIT_4B(16'h0000), // Sequencer Average selection + .INIT_4C(16'h0000), // Sequencer Bipolar selection + .INIT_4D(16'h0000), // Sequencer Bipolar selection + .INIT_4E(16'h0000), // Sequencer Acq time selection + .INIT_4F(16'h0000), // Sequencer Acq time selection + .INIT_50(16'hB794), // Temp alarm trigger + .INIT_51(16'h4E81), // Vccint upper alarm limit + .INIT_52(16'hA147), // Vccaux upper alarm limit + .INIT_53(16'hBF13), // Temp alarm OT upper + .INIT_54(16'hAB02), // Temp alarm reset + .INIT_55(16'h4963), // Vccint lower alarm limit + .INIT_56(16'h9555), // Vccaux lower alarm limit + .INIT_57(16'hB00A), // Temp alarm OT reset + .INIT_58(16'h4E81), // VCCBRAM upper alarm limit + .INIT_5C(16'h4963), // VCCBRAM lower alarm limit + .INIT_59(16'h4963), // vccpsintlp upper alarm limit + .INIT_5D(16'h451E), // vccpsintlp lower alarm limit + .INIT_5A(16'h4963), // vccpsintfp upper alarm limit + .INIT_5E(16'h451E), // vccpsintfp lower alarm limit + .INIT_5B(16'h9A74), // vccpsaux upper alarm limit + .INIT_5F(16'h91EB), // vccpsaux lower alarm limit + .INIT_60(16'h4D39), // Vuser0 upper alarm limit + .INIT_61(16'h4DA7), // Vuser1 upper alarm limit + .INIT_62(16'h9A74), // Vuser2 upper alarm limit + .INIT_63(16'h9A74), // Vuser3 upper alarm limit + .INIT_68(16'h4C5E), // Vuser0 lower alarm limit + .INIT_69(16'h4BF2), // Vuser1 lower alarm limit + .INIT_6A(16'h98BF), // Vuser2 lower alarm limit + .INIT_6B(16'h98BF), // Vuser3 lower alarm limit + .INIT_7A(16'h0000), // DUAL0 Register + .INIT_7B(16'h0000), // DUAL1 Register + .INIT_7C(16'h0000), // DUAL2 Register + .INIT_7D(16'h0000), // DUAL3 Register + .SIM_DEVICE("ZYNQ_ULTRASCALE"), + .SIM_MONITOR_FILE("design.txt") + ) inst_sysmon ( + .DADDR(drp_daddr), + .DCLK(up_clk), + .DEN(drp_den_reg[0]), + .DI(drp_di), + .DWE(drp_dwe_reg[0]), + .RESET(!up_resetn), + .DO(drp_do), + .DRDY(drp_drdy), + .EOC(drp_eoc), + .EOS(drp_eos)); + end + endgenerate + + //pulse generator instance + util_pulse_gen #( + .PULSE_WIDTH(0), + .PULSE_PERIOD(0) + ) util_pulse_gen_i( + .clk (up_clk), + .rstn (up_resetn), + .pulse_width (pwm_width), + .pulse_period (PWM_PERIOD), + .load_config (pulse_gen_load_config), + .pulse (pulse_gen_out)); + + //state machine + always @(posedge up_clk) + if (up_resetn == 1'b0) begin + tacho_alarm <= 'h0; + drp_den_reg <= 'h0; + drp_dwe_reg <= 'h0; + drp_di <= 'h0; + tacho_avg_cnt <= 'h0; + tacho_avg_sum <= 'h0; + tacho_meas_ack <= 'h0; + pulse_gen_load_config <= 'h0; + sysmone_temp <= 'h0; + pwm_width_req <= 'h0; + pwm_width <= 'h0; + up_tacho_avg_sum <= 'h0; + temp_increase_alarm <= 'h0; + tacho_meas_int <= 1'b0; + state <= INIT; + end else begin + + case (state) + + INIT : begin + if (INTERNAL_SYSMONE == 1) begin + drp_daddr <= 8'h40; + // performing read + drp_den_reg <= 2'h2; + if (drp_eoc == 1'b1) begin + state <= DRP_WAIT_EOC; + end + end else begin + state <= DRP_READ_TEMP; + end + end + + DRP_WAIT_EOC : begin + if (drp_eoc == 1'b1) begin + //Clearing AVG bits for Configreg0 + drp_di <= drp_do & 16'h03FF; + drp_daddr <= 8'h40; + drp_den_reg <= 2'h2; + // performing write + drp_dwe_reg <= 2'h2; + state <= DRP_WAIT_DRDY; + end else begin + drp_den_reg <= {1'b0, drp_den_reg[1]}; + drp_dwe_reg <= {1'b0, drp_dwe_reg[1]}; + end + end + + DRP_WAIT_DRDY : begin + if (drp_drdy == 1'b1) begin + state <= DRP_READ_TEMP; + end else begin + drp_den_reg <= {1'b0, drp_den_reg[1]}; + drp_dwe_reg <= {1'b0, drp_dwe_reg[1]}; + end + end + + DRP_WAIT_FSM_EN : begin + tacho_meas_int <= 1'b0; + tacho_alarm <= 1'b0; + pulse_gen_load_config <= 1'b0; + if (presc_reg[15] == 1'b1) begin + state <= DRP_READ_TEMP; + end + end + + DRP_READ_TEMP : begin + if (INTERNAL_SYSMONE == 1) begin + drp_daddr <= 8'h00; + // performing read + drp_den_reg <= 2'h2; + if (drp_eos == 1'b1) begin + state <= DRP_READ_TEMP_WAIT_DRDY; + end + end else begin + state <= DRP_READ_TEMP_WAIT_DRDY; + end + end + + DRP_READ_TEMP_WAIT_DRDY : begin + if (INTERNAL_SYSMONE == 1) begin + if (drp_drdy == 1'b1) begin + sysmone_temp <= drp_do; + state <= GET_TACHO; + end else begin + drp_den_reg <= {1'b0, drp_den_reg[1]}; + drp_dwe_reg <= {1'b0, drp_dwe_reg[1]}; + end + end else begin + sysmone_temp <= temp_in; + state <= GET_TACHO; + end + end + + GET_TACHO : begin + //adding up tacho measurements in order to obtain a mean value from 32 samples + if ((tacho_avg_cnt == AVERAGE_DIV) || (counter_overflow) || (!pwm_change_done)) begin + //once a set measurements has been obtained, reset the values + tacho_avg_sum <= 1'b0; + tacho_avg_cnt <= 1'b0; + tacho_meas_ack <= 1'b0; + end else if ((tacho_meas_new) && (pwm_change_done)) begin + //tacho_meas_new and tacho_meas_ack ensure the value is read at the right time and only once + tacho_avg_sum <= tacho_avg_sum + tacho_meas; + tacho_avg_cnt <= tacho_avg_cnt + 1'b1; + //acknowledge tha the current values has been added + tacho_meas_ack <= 1'b1; + end else begin + tacho_meas_ack <= 1'b0; + end + state <= EVAL_TEMP; + end + + EVAL_TEMP : begin + //pwm section + //the pwm only has to be changed when passing through these temperature intervals + if (sysmone_temp < up_temp_00_h) begin + //PWM DUTY should be 0% + pwm_width_req <= 1'b0; + end else if ((sysmone_temp > up_temp_25_l) && (sysmone_temp < up_temp_25_h)) begin + //PWM DUTY should be 25% + pwm_width_req <= PWM_ONTIME_25; + end else if ((sysmone_temp > up_temp_50_l) && (sysmone_temp < up_temp_50_h)) begin + //PWM DUTY should be 50% + pwm_width_req <= PWM_ONTIME_50; + end else if ((sysmone_temp > up_temp_75_l) && (sysmone_temp < up_temp_75_h)) begin + //PWM DUTY should be 75% + pwm_width_req <= PWM_ONTIME_75; + end else if (sysmone_temp > up_temp_100_l) begin + //PWM DUTY should be 100% + pwm_width_req <= PWM_PERIOD; + //default to 100% duty cycle after reset if not within temperature intervals described above + end else if ((sysmone_temp != 'h0) && (pwm_width == 'h0)) begin + pwm_width_req <= PWM_PERIOD; + end else begin + //if no changes are needed make sure to mantain current pwm + pwm_width_req <= pwm_width; + end + state <= SET_PWM; + end + + SET_PWM : begin + if ((up_pwm_width != pwm_width) && (up_pwm_width >= pwm_width_req) && (up_pwm_width <= PWM_PERIOD) && (pwm_change_done)) begin + pwm_width <= up_pwm_width; + pulse_gen_load_config <= 1'b1; + //clear alarm when pwm duty changes + end else if ((pwm_width != pwm_width_req) && (pwm_width_req > up_pwm_width) && (pwm_change_done)) begin + pwm_width <= pwm_width_req; + pulse_gen_load_config <= 1'b1; + temp_increase_alarm <= 1'b1; + //clear alarm when pwm duty changes + end + state <= EVAL_TACHO; + end + + EVAL_TACHO : begin + temp_increase_alarm <= 1'b0; + //tacho section + //check if the fan is turning then see if it is turning correctly + if(counter_overflow & pwm_change_done) begin + //if overflow is 1 then the fan is not turning so do something + tacho_alarm <= 1'b1; + end else if (tacho_avg_cnt == AVERAGE_DIV) begin + //check rpm according to the current pwm duty cycle + //tacho_alarm is only asserted for certain known pwm duty cycles and + //for timeout + up_tacho_avg_sum <= tacho_avg_sum [AVG_POW + 24 : AVG_POW]; + tacho_meas_int <= 1'b1; + if ((pwm_width == PWM_ONTIME_25) && (up_tacho_en == 0)) begin + if ((tacho_avg_sum [AVG_POW + 24 : AVG_POW] > up_tacho_25 + up_tacho_25_tol) || (tacho_avg_sum [AVG_POW + 24 : AVG_POW] < up_tacho_25 - up_tacho_25_tol)) begin + //the fan is turning but not as expected + tacho_alarm <= 1'b1; + end + end else if ((pwm_width == PWM_ONTIME_50) && (up_tacho_en == 0)) begin + if ((tacho_avg_sum [AVG_POW + 24 : AVG_POW] > up_tacho_50 + up_tacho_50_tol) || (tacho_avg_sum [AVG_POW + 24 : AVG_POW] < up_tacho_50 - up_tacho_50_tol)) begin + //the fan is turning but not as expected + tacho_alarm <= 1'b1; + end + end else if ((pwm_width == PWM_ONTIME_75) && (up_tacho_en == 0)) begin + if ((tacho_avg_sum [AVG_POW + 24 : AVG_POW] > up_tacho_75 + up_tacho_75_tol) || (tacho_avg_sum [AVG_POW + 24 : AVG_POW] < up_tacho_75 - up_tacho_75_tol)) begin + //the fan is turning but not as expected + tacho_alarm <= 1'b1; + end + end else if ((pwm_width == PWM_PERIOD) && (up_tacho_en == 0)) begin + if ((tacho_avg_sum [AVG_POW + 24 : AVG_POW] > up_tacho_100 + up_tacho_100_tol) || (tacho_avg_sum [AVG_POW + 24 : AVG_POW] < up_tacho_100 - up_tacho_100_tol)) begin + //the fan is turning but not as expected + tacho_alarm <= 1'b1; + end + end else if ((pwm_width == up_pwm_width) && up_tacho_en) begin + if ((tacho_avg_sum [AVG_POW + 24 : AVG_POW] > up_tacho_val + up_tacho_tol) || (tacho_avg_sum [AVG_POW + 24 : AVG_POW] < up_tacho_val - up_tacho_tol)) begin + //the fan is turning but not as expected + tacho_alarm <= 1'b1; + end + end + end + state <= DRP_WAIT_FSM_EN; + end + default : + state <= DRP_WAIT_FSM_EN; + endcase + end + + //axi registers write + always @(posedge up_clk) begin + if (up_resetn == 1'b0) begin + up_pwm_width <= 'd0; + up_tacho_val <= 'd0; + up_tacho_tol <= 'd0; + up_tacho_en <= 'd0; + up_scratch <= 'd0; + up_temp_00_h <= THRESH_PWM_000; + up_temp_25_l <= THRESH_PWM_025_L; + up_temp_25_h <= THRESH_PWM_025_H; + up_temp_50_l <= THRESH_PWM_050_L; + up_temp_50_h <= THRESH_PWM_050_H; + up_temp_75_l <= THRESH_PWM_075_L; + up_temp_75_h <= THRESH_PWM_075_H; + up_temp_100_l <= THRESH_PWM_100; + up_tacho_25 <= TACHO_T25; + up_tacho_50 <= TACHO_T50; + up_tacho_75 <= TACHO_T75; + up_tacho_100 <= TACHO_T100; + up_tacho_25_tol <= TACHO_T25 * TACHO_TOL_PERCENT / 100; + up_tacho_50_tol <= TACHO_T50 * TACHO_TOL_PERCENT / 100; + up_tacho_75_tol <= TACHO_T75 * TACHO_TOL_PERCENT / 100; + up_tacho_100_tol <= TACHO_T100 * TACHO_TOL_PERCENT / 100; + up_irq_mask <= 4'b1111; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h02)) begin + up_scratch <= up_wdata_s; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h21)) begin + up_pwm_width <= up_wdata_s; + up_tacho_en <= 1'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h22)) begin + up_tacho_val <= up_wdata_s; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h23)) begin + up_tacho_tol <= up_wdata_s; + up_tacho_en <= 1'b1; + end else if (temp_increase_alarm) begin + up_tacho_en <= 1'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h40)) begin + up_temp_00_h <= up_wdata_s; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h41)) begin + up_temp_25_l <= up_wdata_s; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h42)) begin + up_temp_25_h <= up_wdata_s; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h43)) begin + up_temp_50_l <= up_wdata_s; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h44)) begin + up_temp_50_h <= up_wdata_s; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h45)) begin + up_temp_75_l <= up_wdata_s; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h46)) begin + up_temp_75_h <= up_wdata_s; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h47)) begin + up_temp_100_l <= up_wdata_s; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h50)) begin + up_tacho_25 <= up_wdata_s; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h51)) begin + up_tacho_50 <= up_wdata_s; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h52)) begin + up_tacho_75 <= up_wdata_s; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h53)) begin + up_tacho_100 <= up_wdata_s; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h54)) begin + up_tacho_25_tol <= up_wdata_s; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h55)) begin + up_tacho_50_tol <= up_wdata_s; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h56)) begin + up_tacho_75_tol <= up_wdata_s; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h57)) begin + up_tacho_100_tol <= up_wdata_s; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h10)) begin + up_irq_mask <= up_wdata_s[3:0]; + end + end + end + + //writing reset + always @(posedge up_clk) begin + if (s_axi_aresetn == 1'b0) begin + up_wack <= 'd0; + up_resetn <= 1'd0; + end else begin + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h20)) begin + up_resetn <= up_wdata_s[0]; + end else begin + up_resetn <= 1'd1; + end + end + end + + //axi registers read + always @(posedge up_clk) begin + if (s_axi_aresetn == 1'b0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr_s) + 8'h00: up_rdata <= CORE_VERSION; + 8'h01: up_rdata <= ID; + 8'h02: up_rdata <= up_scratch; + 8'h03: up_rdata <= CORE_MAGIC; + 8'h10: up_rdata <= up_irq_mask; + 8'h11: up_rdata <= up_irq_pending; + 8'h12: up_rdata <= up_irq_source; + 8'h20: up_rdata <= up_resetn; + 8'h21: up_rdata <= pwm_width; + 8'h22: up_rdata <= up_tacho_val; + 8'h23: up_rdata <= up_tacho_tol; + 8'h24: up_rdata <= INTERNAL_SYSMONE; + 8'h30: up_rdata <= PWM_PERIOD; + 8'h31: up_rdata <= up_tacho_avg_sum; + 8'h32: up_rdata <= sysmone_temp; + 8'h40: up_rdata <= up_temp_00_h; + 8'h41: up_rdata <= up_temp_25_l; + 8'h42: up_rdata <= up_temp_25_h; + 8'h43: up_rdata <= up_temp_50_l; + 8'h44: up_rdata <= up_temp_50_h; + 8'h45: up_rdata <= up_temp_75_l; + 8'h46: up_rdata <= up_temp_75_h; + 8'h47: up_rdata <= up_temp_100_l; + 8'h50: up_rdata <= up_tacho_25; + 8'h51: up_rdata <= up_tacho_50; + 8'h52: up_rdata <= up_tacho_75; + 8'h53: up_rdata <= up_tacho_100; + 8'h54: up_rdata <= up_tacho_25_tol; + 8'h55: up_rdata <= up_tacho_50_tol; + 8'h56: up_rdata <= up_tacho_75_tol; + 8'h57: up_rdata <= up_tacho_100_tol; + default: up_rdata <= 0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + //IRQ handling + always @(posedge up_clk) begin + if (up_resetn == 1'b0) begin + irq <= 1'b0; + end else begin + irq <= |up_irq_pending; + end + end + + always @(posedge up_clk) begin + if (up_resetn == 1'b0) begin + up_irq_source <= 4'b0000; + end else begin + up_irq_source <= up_irq_trigger | (up_irq_source & ~up_irq_source_clear); + end + end + + //tacho measurement logic + always @(posedge up_clk) begin + if (up_resetn == 1'b0) begin + tacho_edge_det <= 'h0; + tacho_meas <= 'h0; + tacho_meas_new <= 'h0; + tacho_delayed <= 'h0; + end else begin + //edge detection of tacho signal + tacho_delayed <= tacho; + tacho_edge_det <= tacho & ~tacho_delayed; + if ((tacho_edge_det == 1'b1) && (pwm_change_done)) begin + //measurement is recorded + tacho_meas <= counter_reg; + //signal indicates new measurement completed + tacho_meas_new <= 1'b1; + end else if(tacho_meas_ack == 1'b1) begin + //acknowledge received from state machine + //resetting new measurement flag + tacho_meas_new <= 'h0; + end + end + end + + //pwm change proc + always @(posedge up_clk) begin + if (up_resetn == 1'b0) begin + pwm_change_done <= 1'b1; + end else if (counter_overflow) begin + pwm_change_done <= 1'b1; + end else if (pulse_gen_load_config) begin + pwm_change_done <= 'h0; + end + end + + //tacho measurement and pwm change delay counter + always @(posedge up_clk) begin + if ((up_resetn & counter_resetn) == 1'b0) begin + counter_reg <= 'h0; + counter_overflow <= 1'b0; + end else begin + if (counter_reg == OVERFLOW_LIM) begin + counter_reg <= 'h0; + counter_overflow <= 1'b1; + end else begin + counter_reg <= counter_reg + 1'b1; + end + end + end + + //prescaler; sets the rate at which the fsm is run + always @(posedge up_clk) begin + if (up_resetn == 1'b0) begin + presc_reg <= 'h0; + end else begin + if (presc_reg == 'h8000) begin + presc_reg <= 'h0; + end else begin + presc_reg <= presc_reg + 1'b1; + end + end + end +endmodule diff --git a/adi_library/axi_fan_control/axi_fan_control.xpr b/adi_library/axi_fan_control/axi_fan_control.xpr new file mode 100644 index 00000000..b7f37186 --- /dev/null +++ b/adi_library/axi_fan_control/axi_fan_control.xpr @@ -0,0 +1,413 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_fan_control/axi_fan_control_ip.tcl b/adi_library/axi_fan_control/axi_fan_control_ip.tcl new file mode 100644 index 00000000..2cd52515 --- /dev/null +++ b/adi_library/axi_fan_control/axi_fan_control_ip.tcl @@ -0,0 +1,22 @@ +############################################################################### +## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_fan_control +adi_ip_files axi_fan_control [list \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/util_pulse_gen.v" \ + "axi_fan_control.v"] + +adi_ip_properties axi_fan_control + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_fan_control} [ipx::current_core] + +set cc [ipx::current_core] + +ipx::save_core $cc diff --git a/adi_library/axi_fan_control/component.xml b/adi_library/axi_fan_control/component.xml new file mode 100644 index 00000000..d78c8a0b --- /dev/null +++ b/adi_library/axi_fan_control/component.xml @@ -0,0 +1,956 @@ + + + analog.com + user + axi_fan_control + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_fan_control + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 5cc2597a + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_fan_control + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 5cc2597a + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + c9d9f988 + + + + + + + temp_in + + in + + 9 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + tacho + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + irq + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + pwm + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + PWM_FREQUENCY_HZ + Pwm Frequency Hz + 5000 + + + INTERNAL_SYSMONE + Internal Sysmone + 0 + + + AVG_POW + Avg Pow + 7 + + + TACHO_TOL_PERCENT + Tacho Tol Percent + 25 + + + TACHO_T25 + Tacho T25 + 1470000 + + + TACHO_T50 + Tacho T50 + 820000 + + + TACHO_T75 + Tacho T75 + 480000 + + + TACHO_T100 + Tacho T100 + 340000 + + + TEMP_00_H + Temp 00 H + 5 + + + TEMP_25_L + Temp 25 L + 20 + + + TEMP_25_H + Temp 25 H + 40 + + + TEMP_50_L + Temp 50 L + 60 + + + TEMP_50_H + Temp 50 H + 70 + + + TEMP_75_L + Temp 75 L + 80 + + + TEMP_75_H + Temp 75 H + 90 + + + TEMP_00_L + Temp 00 L + 95 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../common/up_axi.v + verilogSource + + + ../common/util_pulse_gen.v + verilogSource + + + axi_fan_control.v + verilogSource + CHECKSUM_f52f26c6 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/up_axi.v + verilogSource + + + ../common/util_pulse_gen.v + verilogSource + + + axi_fan_control.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_fan_control_v1_0.tcl + tclSource + CHECKSUM_c9d9f988 + XGUI_VERSION_2 + + + + axi_fan_control_v1_0 + + + ID + Id + 0 + + + PWM_FREQUENCY_HZ + Pwm Frequency Hz + 5000 + + + INTERNAL_SYSMONE + Internal Sysmone + 0 + + + AVG_POW + Avg Pow + 7 + + + TACHO_TOL_PERCENT + Tacho Tol Percent + 25 + + + TACHO_T25 + Tacho T25 + 1470000 + + + TACHO_T50 + Tacho T50 + 820000 + + + TACHO_T75 + Tacho T75 + 480000 + + + TACHO_T100 + Tacho T100 + 340000 + + + TEMP_00_H + Temp 00 H + 5 + + + TEMP_25_L + Temp 25 L + 20 + + + TEMP_25_H + Temp 25 H + 40 + + + TEMP_50_L + Temp 50 L + 60 + + + TEMP_50_H + Temp 50 H + 70 + + + TEMP_75_L + Temp 75 L + 80 + + + TEMP_75_H + Temp 75 H + 90 + + + TEMP_00_L + Temp 00 L + 95 + + + Component_Name + axi_fan_control_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_fan_control_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_fan_control + 1 + 2024-01-14T03:46:18Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_fan_control/readme.rst b/adi_library/axi_fan_control/readme.rst new file mode 100644 index 00000000..400bca73 --- /dev/null +++ b/adi_library/axi_fan_control/readme.rst @@ -0,0 +1,8 @@ +=============== +AXI Fan Control +=============== + +Fan controller IP core + +Link to `wiki-page +`_ diff --git a/adi_library/axi_fan_control/xgui/axi_fan_control_v1_0.tcl b/adi_library/axi_fan_control/xgui/axi_fan_control_v1_0.tcl new file mode 100644 index 00000000..6c23f374 --- /dev/null +++ b/adi_library/axi_fan_control/xgui/axi_fan_control_v1_0.tcl @@ -0,0 +1,265 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "AVG_POW" -parent ${Page_0} + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "INTERNAL_SYSMONE" -parent ${Page_0} + ipgui::add_param $IPINST -name "PWM_FREQUENCY_HZ" -parent ${Page_0} + ipgui::add_param $IPINST -name "TACHO_T100" -parent ${Page_0} + ipgui::add_param $IPINST -name "TACHO_T25" -parent ${Page_0} + ipgui::add_param $IPINST -name "TACHO_T50" -parent ${Page_0} + ipgui::add_param $IPINST -name "TACHO_T75" -parent ${Page_0} + ipgui::add_param $IPINST -name "TACHO_TOL_PERCENT" -parent ${Page_0} + ipgui::add_param $IPINST -name "TEMP_00_H" -parent ${Page_0} + ipgui::add_param $IPINST -name "TEMP_00_L" -parent ${Page_0} + ipgui::add_param $IPINST -name "TEMP_25_H" -parent ${Page_0} + ipgui::add_param $IPINST -name "TEMP_25_L" -parent ${Page_0} + ipgui::add_param $IPINST -name "TEMP_50_H" -parent ${Page_0} + ipgui::add_param $IPINST -name "TEMP_50_L" -parent ${Page_0} + ipgui::add_param $IPINST -name "TEMP_75_H" -parent ${Page_0} + ipgui::add_param $IPINST -name "TEMP_75_L" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.AVG_POW { PARAM_VALUE.AVG_POW } { + # Procedure called to update AVG_POW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AVG_POW { PARAM_VALUE.AVG_POW } { + # Procedure called to validate AVG_POW + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.INTERNAL_SYSMONE { PARAM_VALUE.INTERNAL_SYSMONE } { + # Procedure called to update INTERNAL_SYSMONE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.INTERNAL_SYSMONE { PARAM_VALUE.INTERNAL_SYSMONE } { + # Procedure called to validate INTERNAL_SYSMONE + return true +} + +proc update_PARAM_VALUE.PWM_FREQUENCY_HZ { PARAM_VALUE.PWM_FREQUENCY_HZ } { + # Procedure called to update PWM_FREQUENCY_HZ when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PWM_FREQUENCY_HZ { PARAM_VALUE.PWM_FREQUENCY_HZ } { + # Procedure called to validate PWM_FREQUENCY_HZ + return true +} + +proc update_PARAM_VALUE.TACHO_T100 { PARAM_VALUE.TACHO_T100 } { + # Procedure called to update TACHO_T100 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TACHO_T100 { PARAM_VALUE.TACHO_T100 } { + # Procedure called to validate TACHO_T100 + return true +} + +proc update_PARAM_VALUE.TACHO_T25 { PARAM_VALUE.TACHO_T25 } { + # Procedure called to update TACHO_T25 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TACHO_T25 { PARAM_VALUE.TACHO_T25 } { + # Procedure called to validate TACHO_T25 + return true +} + +proc update_PARAM_VALUE.TACHO_T50 { PARAM_VALUE.TACHO_T50 } { + # Procedure called to update TACHO_T50 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TACHO_T50 { PARAM_VALUE.TACHO_T50 } { + # Procedure called to validate TACHO_T50 + return true +} + +proc update_PARAM_VALUE.TACHO_T75 { PARAM_VALUE.TACHO_T75 } { + # Procedure called to update TACHO_T75 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TACHO_T75 { PARAM_VALUE.TACHO_T75 } { + # Procedure called to validate TACHO_T75 + return true +} + +proc update_PARAM_VALUE.TACHO_TOL_PERCENT { PARAM_VALUE.TACHO_TOL_PERCENT } { + # Procedure called to update TACHO_TOL_PERCENT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TACHO_TOL_PERCENT { PARAM_VALUE.TACHO_TOL_PERCENT } { + # Procedure called to validate TACHO_TOL_PERCENT + return true +} + +proc update_PARAM_VALUE.TEMP_00_H { PARAM_VALUE.TEMP_00_H } { + # Procedure called to update TEMP_00_H when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TEMP_00_H { PARAM_VALUE.TEMP_00_H } { + # Procedure called to validate TEMP_00_H + return true +} + +proc update_PARAM_VALUE.TEMP_00_L { PARAM_VALUE.TEMP_00_L } { + # Procedure called to update TEMP_00_L when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TEMP_00_L { PARAM_VALUE.TEMP_00_L } { + # Procedure called to validate TEMP_00_L + return true +} + +proc update_PARAM_VALUE.TEMP_25_H { PARAM_VALUE.TEMP_25_H } { + # Procedure called to update TEMP_25_H when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TEMP_25_H { PARAM_VALUE.TEMP_25_H } { + # Procedure called to validate TEMP_25_H + return true +} + +proc update_PARAM_VALUE.TEMP_25_L { PARAM_VALUE.TEMP_25_L } { + # Procedure called to update TEMP_25_L when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TEMP_25_L { PARAM_VALUE.TEMP_25_L } { + # Procedure called to validate TEMP_25_L + return true +} + +proc update_PARAM_VALUE.TEMP_50_H { PARAM_VALUE.TEMP_50_H } { + # Procedure called to update TEMP_50_H when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TEMP_50_H { PARAM_VALUE.TEMP_50_H } { + # Procedure called to validate TEMP_50_H + return true +} + +proc update_PARAM_VALUE.TEMP_50_L { PARAM_VALUE.TEMP_50_L } { + # Procedure called to update TEMP_50_L when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TEMP_50_L { PARAM_VALUE.TEMP_50_L } { + # Procedure called to validate TEMP_50_L + return true +} + +proc update_PARAM_VALUE.TEMP_75_H { PARAM_VALUE.TEMP_75_H } { + # Procedure called to update TEMP_75_H when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TEMP_75_H { PARAM_VALUE.TEMP_75_H } { + # Procedure called to validate TEMP_75_H + return true +} + +proc update_PARAM_VALUE.TEMP_75_L { PARAM_VALUE.TEMP_75_L } { + # Procedure called to update TEMP_75_L when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TEMP_75_L { PARAM_VALUE.TEMP_75_L } { + # Procedure called to validate TEMP_75_L + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.PWM_FREQUENCY_HZ { MODELPARAM_VALUE.PWM_FREQUENCY_HZ PARAM_VALUE.PWM_FREQUENCY_HZ } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PWM_FREQUENCY_HZ}] ${MODELPARAM_VALUE.PWM_FREQUENCY_HZ} +} + +proc update_MODELPARAM_VALUE.INTERNAL_SYSMONE { MODELPARAM_VALUE.INTERNAL_SYSMONE PARAM_VALUE.INTERNAL_SYSMONE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.INTERNAL_SYSMONE}] ${MODELPARAM_VALUE.INTERNAL_SYSMONE} +} + +proc update_MODELPARAM_VALUE.AVG_POW { MODELPARAM_VALUE.AVG_POW PARAM_VALUE.AVG_POW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AVG_POW}] ${MODELPARAM_VALUE.AVG_POW} +} + +proc update_MODELPARAM_VALUE.TACHO_TOL_PERCENT { MODELPARAM_VALUE.TACHO_TOL_PERCENT PARAM_VALUE.TACHO_TOL_PERCENT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TACHO_TOL_PERCENT}] ${MODELPARAM_VALUE.TACHO_TOL_PERCENT} +} + +proc update_MODELPARAM_VALUE.TACHO_T25 { MODELPARAM_VALUE.TACHO_T25 PARAM_VALUE.TACHO_T25 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TACHO_T25}] ${MODELPARAM_VALUE.TACHO_T25} +} + +proc update_MODELPARAM_VALUE.TACHO_T50 { MODELPARAM_VALUE.TACHO_T50 PARAM_VALUE.TACHO_T50 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TACHO_T50}] ${MODELPARAM_VALUE.TACHO_T50} +} + +proc update_MODELPARAM_VALUE.TACHO_T75 { MODELPARAM_VALUE.TACHO_T75 PARAM_VALUE.TACHO_T75 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TACHO_T75}] ${MODELPARAM_VALUE.TACHO_T75} +} + +proc update_MODELPARAM_VALUE.TACHO_T100 { MODELPARAM_VALUE.TACHO_T100 PARAM_VALUE.TACHO_T100 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TACHO_T100}] ${MODELPARAM_VALUE.TACHO_T100} +} + +proc update_MODELPARAM_VALUE.TEMP_00_H { MODELPARAM_VALUE.TEMP_00_H PARAM_VALUE.TEMP_00_H } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TEMP_00_H}] ${MODELPARAM_VALUE.TEMP_00_H} +} + +proc update_MODELPARAM_VALUE.TEMP_25_L { MODELPARAM_VALUE.TEMP_25_L PARAM_VALUE.TEMP_25_L } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TEMP_25_L}] ${MODELPARAM_VALUE.TEMP_25_L} +} + +proc update_MODELPARAM_VALUE.TEMP_25_H { MODELPARAM_VALUE.TEMP_25_H PARAM_VALUE.TEMP_25_H } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TEMP_25_H}] ${MODELPARAM_VALUE.TEMP_25_H} +} + +proc update_MODELPARAM_VALUE.TEMP_50_L { MODELPARAM_VALUE.TEMP_50_L PARAM_VALUE.TEMP_50_L } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TEMP_50_L}] ${MODELPARAM_VALUE.TEMP_50_L} +} + +proc update_MODELPARAM_VALUE.TEMP_50_H { MODELPARAM_VALUE.TEMP_50_H PARAM_VALUE.TEMP_50_H } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TEMP_50_H}] ${MODELPARAM_VALUE.TEMP_50_H} +} + +proc update_MODELPARAM_VALUE.TEMP_75_L { MODELPARAM_VALUE.TEMP_75_L PARAM_VALUE.TEMP_75_L } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TEMP_75_L}] ${MODELPARAM_VALUE.TEMP_75_L} +} + +proc update_MODELPARAM_VALUE.TEMP_75_H { MODELPARAM_VALUE.TEMP_75_H PARAM_VALUE.TEMP_75_H } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TEMP_75_H}] ${MODELPARAM_VALUE.TEMP_75_H} +} + +proc update_MODELPARAM_VALUE.TEMP_00_L { MODELPARAM_VALUE.TEMP_00_L PARAM_VALUE.TEMP_00_L } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TEMP_00_L}] ${MODELPARAM_VALUE.TEMP_00_L} +} + diff --git a/adi_library/axi_fmcadc5_sync/Makefile b/adi_library/axi_fmcadc5_sync/Makefile new file mode 100644 index 00000000..48ea6dcb --- /dev/null +++ b/adi_library/axi_fmcadc5_sync/Makefile @@ -0,0 +1,18 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_fmcadc5_sync + +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += axi_fmcadc5_sync.v +GENERIC_DEPS += axi_fmcadc5_sync_calcor.v + +XILINX_DEPS += ../xilinx/common/ad_data_out.v +XILINX_DEPS += ../xilinx/common/ad_mul.v +XILINX_DEPS += axi_fmcadc5_sync_constr.xdc +XILINX_DEPS += axi_fmcadc5_sync_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync.v b/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync.v new file mode 100644 index 00000000..e88ed496 --- /dev/null +++ b/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync.v @@ -0,0 +1,820 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// this module is a helper core for linux. as much as possible, try not to use this core. +// best thing to do is look at no-os and implement a proper frame work in linux. +// most controls are scattered around other cores, here we collect them to provide a common access. + +`timescale 1ns/100ps + +module axi_fmcadc5_sync #( + + parameter integer ID = 0, + parameter [ 7:0] FPGA_TECHNOLOGY = 0, + parameter [ 7:0] FPGA_FAMILY = 0, + parameter [ 7:0] SPEED_GRADE = 0, + parameter [ 7:0] DEV_PACKAGE = 0, + parameter DELAY_REFCLK_FREQUENCY = 200 +) ( + // receive interface + + input rx_clk, + output rx_sysref, + input rx_sync_0, + input rx_sync_1, + output rx_sysref_p, + output rx_sysref_n, + output rx_sync_0_p, + output rx_sync_0_n, + output rx_sync_1_p, + output rx_sync_1_n, + input rx_enable_0, + input [255:0] rx_data_0, + input rx_enable_1, + input [255:0] rx_data_1, + output rx_enable, + output [511:0] rx_data, + + // calibration signal + + output vcal, + + // switching regulator clocks + + output psync, + + // delay interface + + input delay_rst, + input delay_clk, + + // spi override + + input [ 7:0] spi_csn_o, + input spi_clk_o, + input spi_sdo_o, + + output [ 7:0] spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [ 15:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [ 31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [ 15:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot +); + + // version + + localparam [31:0] PCORE_VERSION = 32'h00040063; + + // internal registers + + reg [ 7:0] up_psync_count = 'd0; + reg up_psync = 'd0; + reg up_cal_done_t_m1 = 'd0; + reg up_cal_done_t_m2 = 'd0; + reg up_cal_done_t_m3 = 'd0; + reg [ 15:0] up_cal_max_0 = 'd0; + reg [ 15:0] up_cal_min_0 = 'd0; + reg [ 15:0] up_cal_max_1 = 'd0; + reg [ 15:0] up_cal_min_1 = 'd0; + reg up_cal_enable = 'd0; + reg up_cor_enable = 'd0; + reg up_cor_enable_t = 'd0; + reg [ 15:0] up_cor_scale_0 = 'd0; + reg [ 15:0] up_cor_offset_0 = 'd0; + reg [ 15:0] up_cor_scale_1 = 'd0; + reg [ 15:0] up_cor_offset_1 = 'd0; + reg [ 7:0] up_vcal_8 = 'd0; + reg up_vcal = 'd0; + reg [ 7:0] up_vcal_cnt = 'd0; + reg up_vcal_enable = 'd0; + reg up_sysref_ack_t_m1 = 'd0; + reg up_sysref_ack_t_m2 = 'd0; + reg up_sysref_ack_t_m3 = 'd0; + reg up_sysref_control_t = 'd0; + reg [ 1:0] up_sysref_mode_e = 'd0; + reg up_sysref_mode_i = 'd0; + reg up_sysref_req_t = 'd0; + reg up_sysref_status = 'd0; + reg up_sync_control_t = 'd0; + reg up_sync_mode = 'd0; + reg up_sync_disable_1 = 'd0; + reg up_sync_disable_0 = 'd0; + reg up_sync_status_t_m1 = 'd0; + reg up_sync_status_t_m2 = 'd0; + reg up_sync_status_t_m3 = 'd0; + reg up_sync_status_1 = 'd0; + reg up_sync_status_0 = 'd0; + reg up_delay_ld = 'd0; + reg [ 4:0] up_delay_wdata = 'd0; + reg [ 7:0] up_spi_csn_int = 'd0; + reg up_spi_clk_int = 'd0; + reg up_spi_mosi_int = 'd0; + reg up_spi_gnt = 'd0; + reg up_spi_req = 'd0; + reg [ 7:0] up_spi_csn = 'd0; + reg [ 5:0] up_spi_cnt = 'd0; + reg [ 31:0] up_spi_clk_32 = 'd0; + reg [ 31:0] up_spi_out_32 = 'd0; + reg [ 31:0] up_spi_in_32 = 'd0; + reg [ 7:0] up_spi_out = 'd0; + reg [ 31:0] up_scratch = 'd0; + reg [ 31:0] up_timer = 'd0; + reg up_wack = 'd0; + reg up_rack = 'd0; + reg [ 31:0] up_rdata = 'd0; + reg rx_cal_enable_m1 = 'd0; + reg rx_cal_enable = 'd0; + reg rx_cor_enable_t_m1 = 'd0; + reg rx_cor_enable_t_m2 = 'd0; + reg rx_cor_enable_t_m3 = 'd0; + reg rx_cor_enable = 'd0; + reg [ 15:0] rx_cor_scale_0 = 'd0; + reg [ 15:0] rx_cor_offset_0 = 'd0; + reg [ 15:0] rx_cor_scale_1 = 'd0; + reg [ 15:0] rx_cor_offset_1 = 'd0; + reg [ 15:0] rx_cor_scale_d_0 = 'd0; + reg [ 15:0] rx_cor_offset_d_0 = 'd0; + reg [ 15:0] rx_cor_scale_d_1 = 'd0; + reg [ 15:0] rx_cor_offset_d_1 = 'd0; + reg [ 7:0] rx_sysref_cnt = 'd0; + reg rx_sysref_control_t_m1 = 'd0; + reg rx_sysref_control_t_m2 = 'd0; + reg rx_sysref_control_t_m3 = 'd0; + reg [ 1:0] rx_sysref_mode_e = 'd0; + reg rx_sysref_mode_i = 'd0; + reg rx_sysref_req_t_m1 = 'd0; + reg rx_sysref_req_t_m2 = 'd0; + reg rx_sysref_req_t_m3 = 'd0; + reg rx_sysref_req = 'd0; + reg rx_sysref_e = 'd0; + reg rx_sysref_i = 'd0; + reg rx_sysref_ack_t = 'd0; + reg rx_sysref_enb_e = 'd0; + reg rx_sysref_enb_i = 'd0; + reg rx_sync_control_t_m1 = 'd0; + reg rx_sync_control_t_m2 = 'd0; + reg rx_sync_control_t_m3 = 'd0; + reg rx_sync_mode = 'd0; + reg rx_sync_disable_1 = 'd0; + reg rx_sync_disable_0 = 'd0; + reg rx_sync_out_1 = 'd0; + reg rx_sync_out_0 = 'd0; + reg [ 7:0] rx_sync_cnt = 'd0; + reg rx_sync_hold_1 = 'd0; + reg rx_sync_hold_0 = 'd0; + reg rx_sync_status_t = 'd0; + reg rx_sync_status_1 = 'd0; + reg rx_sync_status_0 = 'd0; + + // internal signals + + wire up_cal_done_t_s; + wire up_sysref_ack_t_s; + wire up_sync_status_t_s; + wire up_spi_gnt_s; + wire [ 31:0] up_spi_out_32_s; + wire [ 7:0] up_spi_in_s; + wire rx_cor_enable_t_s; + wire rx_cal_done_t_s; + wire [ 15:0] rx_cal_max_0_s; + wire [ 15:0] rx_cal_min_0_s; + wire [ 15:0] rx_cal_max_1_s; + wire [ 15:0] rx_cal_min_1_s; + wire rx_sysref_control_t_s; + wire rx_sysref_req_t_s; + wire rx_sysref_enb_e_s; + wire rx_sync_control_t_s; + wire [ 4:0] up_delay_rdata_s; + wire up_delay_locked_s; + wire up_wreq_s; + wire [ 13:0] up_waddr_s; + wire [ 31:0] up_wdata_s; + wire up_rreq_s; + wire [ 13:0] up_raddr_s; + wire up_rstn; + wire up_clk; + + // signal name changes + + assign up_rstn = s_axi_aresetn; + assign up_clk = s_axi_aclk; + + // switching regulator clocks (~602K) + + assign psync = up_psync; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_psync_count <= 7'd0; + up_psync <= 1'b0; + end else begin + if (up_psync_count >= 7'h52) begin + up_psync_count <= 7'd0; + end else begin + up_psync_count <= up_psync_count + 1'b1; + end + if (up_psync_count >= 7'h4f) begin + up_psync <= ~up_psync; + end + end + end + + // calibration (offset & gain only) + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_cal_done_t_m1 <= 1'd0; + up_cal_done_t_m2 <= 1'd0; + up_cal_done_t_m3 <= 1'd0; + end else begin + up_cal_done_t_m1 <= rx_cal_done_t_s; + up_cal_done_t_m2 <= up_cal_done_t_m1; + up_cal_done_t_m3 <= up_cal_done_t_m2; + end + end + + assign up_cal_done_t_s = up_cal_done_t_m3 ^ up_cal_done_t_m2; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_cal_max_0 <= 16'd0; + up_cal_min_0 <= 16'd0; + up_cal_max_1 <= 16'd0; + up_cal_min_1 <= 16'd0; + end else begin + if (up_cal_done_t_s == 1'b1) begin + up_cal_max_0 <= rx_cal_max_0_s; + up_cal_min_0 <= rx_cal_min_0_s; + up_cal_max_1 <= rx_cal_max_1_s; + up_cal_min_1 <= rx_cal_min_1_s; + end + end + end + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_cal_enable <= 1'd0; + up_cor_enable <= 1'd0; + up_cor_enable_t <= 1'd0; + up_cor_scale_0 <= 16'd0; + up_cor_offset_0 <= 16'd0; + up_cor_scale_1 <= 16'd0; + up_cor_offset_1 <= 16'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0060)) begin + up_cal_enable <= up_wdata_s[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0061)) begin + up_cor_enable <= up_wdata_s[0]; + up_cor_enable_t <= ~up_cor_enable_t; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0068)) begin + up_cor_scale_0 <= up_wdata_s[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0069)) begin + up_cor_offset_0 <= up_wdata_s[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h006a)) begin + up_cor_scale_1 <= up_wdata_s[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h006b)) begin + up_cor_offset_1 <= up_wdata_s[15:0]; + end + end + end + + // calibration signal register(s) + + assign vcal = up_vcal; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_vcal_8 <= 8'd0; + up_vcal <= 1'd0; + up_vcal_cnt <= 8'd0; + up_vcal_enable <= 1'd0; + end else begin + if (up_vcal_8 >= up_vcal_cnt) begin + up_vcal_8 <= 8'd0; + up_vcal <= ~up_vcal & up_vcal_enable; + end else begin + up_vcal_8 <= up_vcal_8 + 1'b1; + up_vcal <= up_vcal; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0050)) begin + up_vcal_cnt <= up_wdata_s[7:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0051)) begin + up_vcal_enable <= up_wdata_s[0]; + end + end + end + + // sysref register(s) + + assign up_sysref_ack_t_s = up_sysref_ack_t_m3 ^ up_sysref_ack_t_m2; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_sysref_ack_t_m1 <= 1'd0; + up_sysref_ack_t_m2 <= 1'd0; + up_sysref_ack_t_m3 <= 1'd0; + end else begin + up_sysref_ack_t_m1 <= rx_sysref_ack_t; + up_sysref_ack_t_m2 <= up_sysref_ack_t_m1; + up_sysref_ack_t_m3 <= up_sysref_ack_t_m2; + end + end + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_sysref_control_t <= 1'd0; + up_sysref_mode_e <= 2'd0; + up_sysref_mode_i <= 1'd0; + up_sysref_req_t <= 1'd0; + up_sysref_status <= 1'b0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0040)) begin + up_sysref_control_t <= ~up_sysref_control_t; + up_sysref_mode_e <= up_wdata_s[5:4]; + up_sysref_mode_i <= up_wdata_s[0]; + end + if (up_sysref_status == 1'b1) begin + if (up_sysref_ack_t_s == 1'b1) begin + up_sysref_req_t <= up_sysref_req_t; + up_sysref_status <= 1'b0; + end + end else if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0041)) begin + if (up_wdata_s[0] == 1'b1) begin + up_sysref_req_t <= ~up_sysref_req_t; + up_sysref_status <= 1'b1; + end + end + end + end + + // sync register(s) + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_sync_control_t <= 1'd0; + up_sync_mode <= 1'd0; + up_sync_disable_1 <= 1'd0; + up_sync_disable_0 <= 1'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0030)) begin + up_sync_control_t <= ~up_sync_control_t; + up_sync_mode <= up_wdata_s[2]; + up_sync_disable_1 <= up_wdata_s[1]; + up_sync_disable_0 <= up_wdata_s[0]; + end + end + end + + // simple current status (no persistence) + + assign up_sync_status_t_s = up_sync_status_t_m3 ^ up_sync_status_t_m2; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_sync_status_t_m1 <= 1'd0; + up_sync_status_t_m2 <= 1'd0; + up_sync_status_t_m3 <= 1'd0; + up_sync_status_1 <= 1'd0; + up_sync_status_0 <= 1'd0; + end else begin + up_sync_status_t_m1 <= rx_sync_status_t; + up_sync_status_t_m2 <= up_sync_status_t_m1; + up_sync_status_t_m3 <= up_sync_status_t_m2; + if (up_sync_status_t_s == 1'b1) begin + up_sync_status_1 <= rx_sync_status_1; + up_sync_status_0 <= rx_sync_status_0; + end + end + end + + // delay register(s) + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_delay_ld <= 1'd0; + up_delay_wdata <= 5'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0020)) begin + up_delay_ld <= 1'b1; + end else begin + up_delay_ld <= 1'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0020)) begin + up_delay_wdata <= up_wdata_s[4:0]; + end + end + end + + // switching must be glitchless + + assign spi_csn = up_spi_csn_int; + assign spi_clk = up_spi_clk_int; + assign spi_mosi = up_spi_mosi_int; + + always @(negedge up_clk) begin + if (up_spi_gnt == 1'b1) begin + up_spi_csn_int <= up_spi_csn; + up_spi_clk_int <= up_spi_clk_32[31]; + up_spi_mosi_int <= up_spi_out_32[31]; + end else begin + up_spi_csn_int <= spi_csn_o; + up_spi_clk_int <= spi_clk_o; + up_spi_mosi_int <= spi_sdo_o; + end + end + + assign up_spi_gnt_s = (&spi_csn_o) & ~spi_clk_o; + + always @(posedge up_clk or negedge up_rstn) begin + if (up_rstn == 1'b0) begin + up_spi_gnt <= 1'd0; + end else begin + if (up_spi_gnt_s == 1'b1) begin + up_spi_gnt <= up_spi_req; + end + end + end + + // spi data stretching + + assign up_spi_out_32_s[31:28] = {4{up_wdata_s[7]}}; + assign up_spi_out_32_s[27:24] = {4{up_wdata_s[6]}}; + assign up_spi_out_32_s[23:20] = {4{up_wdata_s[5]}}; + assign up_spi_out_32_s[19:16] = {4{up_wdata_s[4]}}; + assign up_spi_out_32_s[15:12] = {4{up_wdata_s[3]}}; + assign up_spi_out_32_s[11: 8] = {4{up_wdata_s[2]}}; + assign up_spi_out_32_s[ 7: 4] = {4{up_wdata_s[1]}}; + assign up_spi_out_32_s[ 3: 0] = {4{up_wdata_s[0]}}; + + assign up_spi_in_s[7] = up_spi_in_32[28]; + assign up_spi_in_s[6] = up_spi_in_32[24]; + assign up_spi_in_s[5] = up_spi_in_32[20]; + assign up_spi_in_s[4] = up_spi_in_32[16]; + assign up_spi_in_s[3] = up_spi_in_32[12]; + assign up_spi_in_s[2] = up_spi_in_32[ 8]; + assign up_spi_in_s[1] = up_spi_in_32[ 4]; + assign up_spi_in_s[0] = up_spi_in_32[ 0]; + + // spi register(s) + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_spi_req <= 1'd0; + up_spi_csn <= {8{1'b1}}; + up_spi_cnt <= 6'd0; + up_spi_clk_32 <= 32'd0; + up_spi_out_32 <= 32'd0; + up_spi_in_32 <= 32'd0; + up_spi_out <= 8'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0010)) begin + up_spi_req <= up_wdata_s[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0012)) begin + up_spi_csn <= up_wdata_s[7:0]; + end + if (up_spi_cnt[5] == 1'b1) begin + up_spi_cnt <= up_spi_cnt + 1'b1; + up_spi_clk_32 <= {up_spi_clk_32[30:0], 1'd0}; + up_spi_out_32 <= {up_spi_out_32[30:0], 1'd0}; + up_spi_in_32 <= {up_spi_in_32[30:0], spi_miso}; + up_spi_out <= up_spi_out; + end else if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0013)) begin + up_spi_cnt <= 6'h20; + up_spi_clk_32 <= {8{4'h6}}; + up_spi_out_32 <= up_spi_out_32_s; + up_spi_in_32 <= {31'd0, spi_miso}; + up_spi_out <= up_wdata_s[7:0]; + end + end + end + + // scratch register(s) + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_scratch <= 'd0; + up_timer <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0002)) begin + up_scratch <= up_wdata_s; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 14'h0003)) begin + up_timer <= up_wdata_s; + end else if (up_timer > 0) begin + up_timer <= up_timer - 1'b1; + end + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_wack <= up_wreq_s; + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr_s) + 14'h0000: up_rdata <= PCORE_VERSION; + 14'h0001: up_rdata <= ID; + 14'h0002: up_rdata <= up_scratch; + 14'h0003: up_rdata <= up_timer; + 14'h0007: up_rdata <= {FPGA_TECHNOLOGY,FPGA_FAMILY,SPEED_GRADE,DEV_PACKAGE}; // [8,8,8,8] + 14'h0010: up_rdata <= {31'd0, up_spi_req}; + 14'h0011: up_rdata <= {31'd0, up_spi_gnt}; + 14'h0012: up_rdata <= {24'd0, up_spi_csn}; + 14'h0013: up_rdata <= {24'd0, up_spi_out}; + 14'h0014: up_rdata <= {24'd0, up_spi_in_s}; + 14'h0015: up_rdata <= {31'd0, up_spi_cnt[5]}; + 14'h0020: up_rdata <= {27'd0, up_delay_wdata}; + 14'h0021: up_rdata <= {27'd0, up_delay_rdata_s}; + 14'h0022: up_rdata <= {31'd0, up_delay_locked_s}; + 14'h0030: up_rdata <= {29'd0, up_sync_mode, up_sync_disable_1, up_sync_disable_0}; + 14'h0031: up_rdata <= {30'd0, up_sync_status_1, up_sync_status_0}; + 14'h0040: up_rdata <= {26'd0, up_sysref_mode_e, 3'b0, up_sysref_mode_i}; + 14'h0041: up_rdata <= {31'd0, up_sysref_status}; + 14'h0050: up_rdata <= {24'd0, up_vcal_cnt}; + 14'h0051: up_rdata <= {31'd0, up_vcal_enable}; + 14'h0060: up_rdata <= {30'd0, up_cal_enable}; + 14'h0061: up_rdata <= {30'd0, up_cor_enable}; + 14'h0064: up_rdata <= {16'd0, up_cal_max_0}; + 14'h0065: up_rdata <= {16'd0, up_cal_min_0}; + 14'h0066: up_rdata <= {16'd0, up_cal_max_1}; + 14'h0067: up_rdata <= {16'd0, up_cal_min_1}; + 14'h0068: up_rdata <= {16'd0, up_cor_scale_0}; + 14'h0069: up_rdata <= {16'd0, up_cor_offset_0}; + 14'h006a: up_rdata <= {16'd0, up_cor_scale_1}; + 14'h006b: up_rdata <= {16'd0, up_cor_offset_1}; + default: up_rdata <= 0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + // calibration at receive clock + + always @(posedge rx_clk) begin + rx_cal_enable_m1 <= up_cal_enable; + rx_cal_enable <= rx_cal_enable_m1; + rx_cor_enable_t_m1 <= up_cor_enable_t; + rx_cor_enable_t_m2 <= rx_cor_enable_t_m1; + rx_cor_enable_t_m3 <= rx_cor_enable_t_m2; + end + + assign rx_cor_enable_t_s = rx_cor_enable_t_m3 ^ rx_cor_enable_t_m2; + + always @(posedge rx_clk) begin + if (rx_cor_enable_t_s == 1'b1) begin + rx_cor_enable <= up_cor_enable; + rx_cor_scale_0 <= up_cor_scale_0; + rx_cor_offset_0 <= up_cor_offset_0; + rx_cor_scale_1 <= up_cor_scale_1; + rx_cor_offset_1 <= up_cor_offset_1; + end + end + + always @(posedge rx_clk) begin + if (rx_cor_enable == 1'b0) begin + rx_cor_scale_d_0 <= 16'h8000; + rx_cor_offset_d_0 <= 16'h0000; + rx_cor_scale_d_1 <= 16'h8000; + rx_cor_offset_d_1 <= 16'h0000; + end else begin + rx_cor_scale_d_0 <= rx_cor_scale_0; + rx_cor_offset_d_0 <= rx_cor_offset_0; + rx_cor_scale_d_1 <= rx_cor_scale_1; + rx_cor_offset_d_1 <= rx_cor_offset_1; + end + end + + axi_fmcadc5_sync_calcor i_calcor ( + .rx_clk (rx_clk), + .rx_enable_0 (rx_enable_0), + .rx_data_0 (rx_data_0), + .rx_enable_1 (rx_enable_1), + .rx_data_1 (rx_data_1), + .rx_enable (rx_enable), + .rx_data (rx_data), + .rx_cal_enable (rx_cal_enable), + .rx_cal_done_t (rx_cal_done_t_s), + .rx_cal_max_0 (rx_cal_max_0_s), + .rx_cal_min_0 (rx_cal_min_0_s), + .rx_cal_max_1 (rx_cal_max_1_s), + .rx_cal_min_1 (rx_cal_min_1_s), + .rx_cor_scale_0 (rx_cor_scale_d_0), + .rx_cor_offset_0 (rx_cor_offset_d_0), + .rx_cor_scale_1 (rx_cor_scale_d_1), + .rx_cor_offset_1 (rx_cor_offset_d_1)); + + // sysref-control at receive clock + + always @(posedge rx_clk) begin + rx_sysref_cnt <= rx_sysref_cnt + 1'b1; + end + + assign rx_sysref_control_t_s = rx_sysref_control_t_m3 ^ rx_sysref_control_t_m2; + assign rx_sysref_req_t_s = rx_sysref_req_t_m3 ^ rx_sysref_req_t_m2; + + always @(posedge rx_clk) begin + rx_sysref_control_t_m1 <= up_sysref_control_t; + rx_sysref_control_t_m2 <= rx_sysref_control_t_m1; + rx_sysref_control_t_m3 <= rx_sysref_control_t_m2; + if (rx_sysref_control_t_s == 1'b1) begin + rx_sysref_mode_e <= up_sysref_mode_e; + rx_sysref_mode_i <= up_sysref_mode_i; + end + rx_sysref_req_t_m1 <= up_sysref_req_t; + rx_sysref_req_t_m2 <= rx_sysref_req_t_m1; + rx_sysref_req_t_m3 <= rx_sysref_req_t_m2; + if ((rx_sysref_cnt == 8'd0) || (rx_sysref_req_t_s == 1'b1)) begin + rx_sysref_req <= rx_sysref_req_t_s; + end + end + + assign rx_sysref_enb_e_s = (rx_sysref_mode_e == 2'b10) ? rx_sysref_req : + ((rx_sysref_mode_e == 2'b00) ? 1'b1 : 1'b0); + + always @(posedge rx_clk) begin + rx_sysref_e <= rx_sysref_cnt[7] & rx_sysref_enb_e; + rx_sysref_i <= rx_sysref_cnt[7] & rx_sysref_enb_i; + if (rx_sysref_cnt == 8'd0) begin + if (rx_sysref_enb_e == 1'b1) begin + rx_sysref_ack_t <= ~rx_sysref_ack_t; + end + rx_sysref_enb_e <= rx_sysref_enb_e_s; + rx_sysref_enb_i <= ~rx_sysref_mode_i; + end + end + + // sync-control at receive clock + + assign rx_sync_control_t_s = rx_sync_control_t_m3 ^ rx_sync_control_t_m2; + + always @(posedge rx_clk) begin + rx_sync_control_t_m1 <= up_sync_control_t; + rx_sync_control_t_m2 <= rx_sync_control_t_m1; + rx_sync_control_t_m3 <= rx_sync_control_t_m2; + if (rx_sync_control_t_s == 1'b1) begin + rx_sync_mode <= up_sync_mode; + rx_sync_disable_1 <= up_sync_disable_1; + rx_sync_disable_0 <= up_sync_disable_0; + end + if (rx_sync_mode == 1'b1) begin + rx_sync_out_1 <= ~rx_sync_disable_1 & rx_sync_1 & rx_sync_0; + rx_sync_out_0 <= ~rx_sync_disable_0 & rx_sync_1 & rx_sync_0; + end else begin + rx_sync_out_1 <= ~rx_sync_disable_1 & rx_sync_1; + rx_sync_out_0 <= ~rx_sync_disable_0 & rx_sync_0; + end + end + + always @(posedge rx_clk) begin + rx_sync_cnt <= rx_sync_cnt + 1'b1; + if ((rx_sync_cnt == 8'd0) || (rx_sync_1 == 1'b0)) begin + rx_sync_hold_1 <= rx_sync_1; + end + if ((rx_sync_cnt == 8'd0) || (rx_sync_0 == 1'b0)) begin + rx_sync_hold_0 <= rx_sync_0; + end + if (rx_sync_cnt == 8'd0) begin + rx_sync_status_t <= ~rx_sync_status_t; + rx_sync_status_1 <= rx_sync_hold_1; + rx_sync_status_0 <= rx_sync_hold_0; + end + end + + // sync buffers + + OBUFDS i_obufds_rx_sync_1 ( + .I (rx_sync_out_1), + .O (rx_sync_1_p), + .OB (rx_sync_1_n)); + + OBUFDS i_obufds_rx_sync_0 ( + .I (rx_sync_out_0), + .O (rx_sync_0_p), + .OB (rx_sync_0_n)); + + // sysref delay control + + assign rx_sysref = rx_sysref_i; + + ad_data_out #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .SINGLE_ENDED (0), + .IODELAY_ENABLE (1), + .IODELAY_CTRL (1), + .IODELAY_GROUP ("FMCADC5_SYSREF_IODELAY_GROUP"), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_rx_sysref ( + .tx_clk (rx_clk), + .tx_data_p (rx_sysref_e), + .tx_data_n (rx_sysref_e), + .tx_data_out_p (rx_sysref_p), + .tx_data_out_n (rx_sysref_n), + .up_clk (up_clk), + .up_dld (up_delay_ld), + .up_dwdata (up_delay_wdata), + .up_drdata (up_delay_rdata_s), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (up_delay_locked_s)); + + // up == micro("u") processor + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync.xpr b/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync.xpr new file mode 100644 index 00000000..373bc04b --- /dev/null +++ b/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync.xpr @@ -0,0 +1,440 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v b/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v new file mode 100644 index 00000000..f5646531 --- /dev/null +++ b/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync_calcor.v @@ -0,0 +1,325 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// poor man's version of calibration & correction (scale & offset only) +// assumes linear frequency response on all discrete components +// looking for a rich man's version? fidus.com (FSF-AD15000A) + +`timescale 1ns/100ps + +module axi_fmcadc5_sync_calcor ( + + // receive interface + + input rx_clk, + input rx_enable_0, + input [255:0] rx_data_0, + input rx_enable_1, + input [255:0] rx_data_1, + output rx_enable, + output [511:0] rx_data, + + // calibration signals + + input rx_cal_enable, + output rx_cal_done_t, + output [ 15:0] rx_cal_max_0, + output [ 15:0] rx_cal_min_0, + output [ 15:0] rx_cal_max_1, + output [ 15:0] rx_cal_min_1, + input [ 15:0] rx_cor_scale_0, + input [ 15:0] rx_cor_offset_0, + input [ 15:0] rx_cor_scale_1, + input [ 15:0] rx_cor_offset_1 +); + + // internal registers + + reg rx_enable_int = 'd0; + reg [ 15:0] rx_cor_data_0[0:15]; + reg [ 15:0] rx_cor_data_1[0:15]; + reg rx_cal_done_int_t = 'd0; + reg [ 15:0] rx_cal_max_0_6 = 'd0; + reg [ 15:0] rx_cal_min_0_6 = 'd0; + reg [ 15:0] rx_cal_max_1_6 = 'd0; + reg [ 15:0] rx_cal_min_1_6 = 'd0; + reg [ 15:0] rx_cal_max_0_5 = 'd0; + reg [ 15:0] rx_cal_min_0_5 = 'd0; + reg [ 15:0] rx_cal_max_1_5 = 'd0; + reg [ 15:0] rx_cal_min_1_5 = 'd0; + reg [ 15:0] rx_cal_max_0_4[0:1]; + reg [ 15:0] rx_cal_min_0_4[0:1]; + reg [ 15:0] rx_cal_max_1_4[0:1]; + reg [ 15:0] rx_cal_min_1_4[0:1]; + reg [ 15:0] rx_cal_max_0_3[0:3]; + reg [ 15:0] rx_cal_min_0_3[0:3]; + reg [ 15:0] rx_cal_max_1_3[0:3]; + reg [ 15:0] rx_cal_min_1_3[0:3]; + reg [ 15:0] rx_cal_max_0_2[0:7]; + reg [ 15:0] rx_cal_min_0_2[0:7]; + reg [ 15:0] rx_cal_max_1_2[0:7]; + reg [ 15:0] rx_cal_min_1_2[0:7]; + reg [ 15:0] rx_cal_max_0_1[0:15]; + reg [ 15:0] rx_cal_min_0_1[0:15]; + reg [ 15:0] rx_cal_max_1_1[0:15]; + reg [ 15:0] rx_cal_min_1_1[0:15]; + + // internal signals + + wire [ 33:0] rx_cor_data_0_s[0:15]; + wire [ 33:0] rx_cor_data_1_s[0:15]; + wire [ 15:0] rx_data_0_s[0:15]; + wire [ 15:0] rx_data_1_s[0:15]; + + // iterations + + genvar n; + + // offset & gain + + assign rx_enable = rx_enable_int; + + always @(posedge rx_clk) begin + rx_enable_int = rx_enable_0 & rx_enable_1; + end + + generate + for (n = 0; n <= 15; n = n + 1) begin: g_rx_cal_data + assign rx_data[((n*32)+15):((n*32)+ 0)] = rx_cor_data_0_s[n][30:15]; + assign rx_data[((n*32)+31):((n*32)+16)] = rx_cor_data_1_s[n][30:15]; + end + endgenerate + + // gain + + generate + for (n = 0; n <= 15; n = n + 1) begin: g_rx_gain + ad_mul #( + .DELAY_DATA_WIDTH(1) + ) i_rx_gain_0 ( + .clk (rx_clk), + .data_a ({rx_cor_data_0[n][15], rx_cor_data_0[n]}), + .data_b ({1'b0, rx_cor_scale_0}), + .data_p (rx_cor_data_0_s[n]), + .ddata_in (1'd0), + .ddata_out ()); + + ad_mul #( + .DELAY_DATA_WIDTH(1) + ) i_rx_gain_1 ( + .clk (rx_clk), + .data_a ({rx_cor_data_1[n][15], rx_cor_data_1[n]}), + .data_b ({1'b0, rx_cor_scale_1}), + .data_p (rx_cor_data_1_s[n]), + .ddata_in (1'd0), + .ddata_out ()); + end + endgenerate + + // offset + + generate + for (n = 0; n <= 15; n = n + 1) begin: g_rx_offset + always @(posedge rx_clk) begin + rx_cor_data_0[n] <= rx_data_0_s[n] + rx_cor_offset_0; + rx_cor_data_1[n] <= rx_data_1_s[n] + rx_cor_offset_1; + end + end + endgenerate + + // calibration peaks (average would be better) + + assign rx_cal_done_t = rx_cal_done_int_t; + assign rx_cal_max_0 = rx_cal_max_0_6; + assign rx_cal_min_0 = rx_cal_min_0_6; + assign rx_cal_max_1 = rx_cal_max_1_6; + assign rx_cal_min_1 = rx_cal_min_1_6; + + always @(posedge rx_clk) begin + if (rx_cal_enable == 1'b1) begin + rx_cal_done_int_t <= ~rx_cal_done_int_t; + rx_cal_max_0_6 <= rx_cal_max_0_5; + rx_cal_min_0_6 <= rx_cal_min_0_5; + rx_cal_max_1_6 <= rx_cal_max_1_5; + rx_cal_min_1_6 <= rx_cal_min_1_5; + end + end + + // run-time peaks + + always @(posedge rx_clk) begin + if (rx_cal_max_0_4[1] > rx_cal_max_0_4[0]) begin + rx_cal_max_0_5 <= rx_cal_max_0_4[1]; + end else begin + rx_cal_max_0_5 <= rx_cal_max_0_4[0]; + end + if (rx_cal_min_0_4[1] < rx_cal_min_0_4[0]) begin + rx_cal_min_0_5 <= rx_cal_min_0_4[1]; + end else begin + rx_cal_min_0_5 <= rx_cal_min_0_4[0]; + end + if (rx_cal_max_1_4[1] > rx_cal_max_1_4[0]) begin + rx_cal_max_1_5 <= rx_cal_max_1_4[1]; + end else begin + rx_cal_max_1_5 <= rx_cal_max_1_4[0]; + end + if (rx_cal_min_1_4[1] < rx_cal_min_1_4[0]) begin + rx_cal_min_1_5 <= rx_cal_min_1_4[1]; + end else begin + rx_cal_min_1_5 <= rx_cal_min_1_4[0]; + end + end + + // peak iterations + + generate + for (n = 0; n <= 1; n = n + 1) begin: g_rx_peak_4 + always @(posedge rx_clk) begin + if (rx_cal_max_0_3[((n*2)+1)] > rx_cal_max_0_3[(n*2)]) begin + rx_cal_max_0_4[n] <= rx_cal_max_0_3[((n*2)+1)]; + end else begin + rx_cal_max_0_4[n] <= rx_cal_max_0_3[(n*2)]; + end + if (rx_cal_min_0_3[((n*2)+1)] < rx_cal_min_0_3[(n*2)]) begin + rx_cal_min_0_4[n] <= rx_cal_min_0_3[((n*2)+1)]; + end else begin + rx_cal_min_0_4[n] <= rx_cal_min_0_3[(n*2)]; + end + if (rx_cal_max_1_3[((n*2)+1)] > rx_cal_max_1_3[(n*2)]) begin + rx_cal_max_1_4[n] <= rx_cal_max_1_3[((n*2)+1)]; + end else begin + rx_cal_max_1_4[n] <= rx_cal_max_1_3[(n*2)]; + end + if (rx_cal_min_1_3[((n*2)+1)] < rx_cal_min_1_3[(n*2)]) begin + rx_cal_min_1_4[n] <= rx_cal_min_1_3[((n*2)+1)]; + end else begin + rx_cal_min_1_4[n] <= rx_cal_min_1_3[(n*2)]; + end + end + end + endgenerate + + generate + for (n = 0; n <= 3; n = n + 1) begin: g_rx_peak_3 + always @(posedge rx_clk) begin + if (rx_cal_max_0_2[((n*2)+1)] > rx_cal_max_0_2[(n*2)]) begin + rx_cal_max_0_3[n] <= rx_cal_max_0_2[((n*2)+1)]; + end else begin + rx_cal_max_0_3[n] <= rx_cal_max_0_2[(n*2)]; + end + if (rx_cal_min_0_2[((n*2)+1)] < rx_cal_min_0_2[(n*2)]) begin + rx_cal_min_0_3[n] <= rx_cal_min_0_2[((n*2)+1)]; + end else begin + rx_cal_min_0_3[n] <= rx_cal_min_0_2[(n*2)]; + end + if (rx_cal_max_1_2[((n*2)+1)] > rx_cal_max_1_2[(n*2)]) begin + rx_cal_max_1_3[n] <= rx_cal_max_1_2[((n*2)+1)]; + end else begin + rx_cal_max_1_3[n] <= rx_cal_max_1_2[(n*2)]; + end + if (rx_cal_min_1_2[((n*2)+1)] < rx_cal_min_1_2[(n*2)]) begin + rx_cal_min_1_3[n] <= rx_cal_min_1_2[((n*2)+1)]; + end else begin + rx_cal_min_1_3[n] <= rx_cal_min_1_2[(n*2)]; + end + end + end + endgenerate + + generate + for (n = 0; n <= 7; n = n + 1) begin: g_rx_peak_2 + always @(posedge rx_clk) begin + if (rx_cal_max_0_1[((n*2)+1)] > rx_cal_max_0_1[(n*2)]) begin + rx_cal_max_0_2[n] <= rx_cal_max_0_1[((n*2)+1)]; + end else begin + rx_cal_max_0_2[n] <= rx_cal_max_0_1[(n*2)]; + end + if (rx_cal_min_0_1[((n*2)+1)] < rx_cal_min_0_1[(n*2)]) begin + rx_cal_min_0_2[n] <= rx_cal_min_0_1[((n*2)+1)]; + end else begin + rx_cal_min_0_2[n] <= rx_cal_min_0_1[(n*2)]; + end + if (rx_cal_max_1_1[((n*2)+1)] > rx_cal_max_1_1[(n*2)]) begin + rx_cal_max_1_2[n] <= rx_cal_max_1_1[((n*2)+1)]; + end else begin + rx_cal_max_1_2[n] <= rx_cal_max_1_1[(n*2)]; + end + if (rx_cal_min_1_1[((n*2)+1)] < rx_cal_min_1_1[(n*2)]) begin + rx_cal_min_1_2[n] <= rx_cal_min_1_1[((n*2)+1)]; + end else begin + rx_cal_min_1_2[n] <= rx_cal_min_1_1[(n*2)]; + end + end + end + endgenerate + + generate + for (n = 0; n <= 15; n = n + 1) begin: g_rx_peak_1 + always @(posedge rx_clk) begin + if (rx_cal_enable == 1'b0) begin + rx_cal_max_0_1[n] <= 16'h0000; + end else if ((rx_data_0_s[n] > rx_cal_max_0_1[n]) && + (rx_data_0_s[n][15] == 1'b0)) begin + rx_cal_max_0_1[n] <= rx_data_0_s[n]; + end + if (rx_cal_enable == 1'b0) begin + rx_cal_min_0_1[n] <= 16'hffff; + end else if ((rx_data_0_s[n] < rx_cal_min_0_1[n]) && + (rx_data_0_s[n][15] == 1'b1)) begin + rx_cal_min_0_1[n] <= rx_data_0_s[n]; + end + if (rx_cal_enable == 1'b0) begin + rx_cal_max_1_1[n] <= 16'h0000; + end else if ((rx_data_1_s[n] > rx_cal_max_1_1[n]) && + (rx_data_1_s[n][15] == 1'b0)) begin + rx_cal_max_1_1[n] <= rx_data_1_s[n]; + end + if (rx_cal_enable == 1'b0) begin + rx_cal_min_1_1[n] <= 16'hffff; + end else if ((rx_data_1_s[n] < rx_cal_min_1_1[n]) && + (rx_data_1_s[n][15] == 1'b1)) begin + rx_cal_min_1_1[n] <= rx_data_1_s[n]; + end + end + end + endgenerate + + generate + for (n = 0; n <= 15; n = n + 1) begin: g_rx_data + assign rx_data_0_s[n] = {{4{rx_data_0[((n*16)+11)]}}, rx_data_0[((n*16)+11):(n*16)]}; + assign rx_data_1_s[n] = {{4{rx_data_1[((n*16)+11)]}}, rx_data_1[((n*16)+11):(n*16)]}; + end + endgenerate + +endmodule diff --git a/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync_constr.xdc b/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync_constr.xdc new file mode 100644 index 00000000..efc47c16 --- /dev/null +++ b/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync_constr.xdc @@ -0,0 +1,50 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_cal_done_t_m1* && IS_SEQUENTIAL}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_sysref_ack_t_m1* && IS_SEQUENTIAL}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_sync_status_t_m1* && IS_SEQUENTIAL}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_sync_status_1* && IS_SEQUENTIAL}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_sync_status_0* && IS_SEQUENTIAL}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_cal_enable_m1* && IS_SEQUENTIAL}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_cor_enable_t_m1* && IS_SEQUENTIAL}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sysref_control_t_m1* && IS_SEQUENTIAL}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sysref_mode_e* && IS_SEQUENTIAL}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sysref_mode_i* && IS_SEQUENTIAL}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sysref_req_t_m1* && IS_SEQUENTIAL}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sync_control_t_m1* && IS_SEQUENTIAL}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sync_mode* && IS_SEQUENTIAL}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sync_disable_1* && IS_SEQUENTIAL}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rx_sync_disable_0* && IS_SEQUENTIAL}] + +set_false_path -to [get_cells -hier -filter {name =~ *up_cal_done_t_m1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *up_cal_max_0* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *up_cal_min_0* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *up_cal_max_1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *up_cal_min_1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *up_sysref_ack_t_m1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *up_sync_status_t_m1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *up_sync_status_1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *up_sync_status_0* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *rx_cal_enable_m1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *rx_cor_enable_t_m1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *rx_cor_enable* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *rx_cor_scale_0* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *rx_cor_offset_0* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *rx_cor_scale_1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *rx_cor_offset_1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *rx_sysref_control_t_m1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *rx_sysref_mode_e* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *rx_sysref_mode_i* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *rx_sysref_req_t_m1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *rx_sync_control_t_m1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *rx_sync_mode* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *rx_sync_disable_1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *rx_sync_disable_0* && IS_SEQUENTIAL}] + +# Define spi clock +create_generated_clock -name forwarded_spi_clk \ + -source [get_pins -hier up_spi_clk_int_reg/C] \ + -divide_by 2 [get_pins -hier up_spi_clk_int_reg/Q] diff --git a/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl b/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl new file mode 100644 index 00000000..11ba4c2b --- /dev/null +++ b/adi_library/axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl @@ -0,0 +1,33 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_fmcadc5_sync +adi_ip_files axi_fmcadc5_sync [list \ + "$ad_hdl_dir/library/xilinx/common/ad_data_out.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "axi_fmcadc5_sync_constr.xdc" \ + "axi_fmcadc5_sync_calcor.v" \ + "axi_fmcadc5_sync.v" ] + +adi_ip_properties axi_fmcadc5_sync + +adi_init_bd_tcl +adi_ip_bd axi_fmcadc5_sync "bd/bd.tcl" + +ipx::infer_bus_interface rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + +ipx::infer_bus_interface delay_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface delay_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/axi_fmcadc5_sync/bd/bd.tcl b/adi_library/axi_fmcadc5_sync/bd/bd.tcl new file mode 100644 index 00000000..dceb9498 --- /dev/null +++ b/adi_library/axi_fmcadc5_sync/bd/bd.tcl @@ -0,0 +1,47 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + DEV_PACKAGE \ + SPEED_GRADE \ + FPGA_FAMILY \ + FPGA_TECHNOLOGY" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/axi_fmcadc5_sync/component.xml b/adi_library/axi_fmcadc5_sync/component.xml new file mode 100644 index 00000000..1a009d3a --- /dev/null +++ b/adi_library/axi_fmcadc5_sync/component.xml @@ -0,0 +1,1320 @@ + + + analog.com + user + axi_fmcadc5_sync + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + rx_clk + + + + + + + CLK + + + rx_clk + + + + + + delay_clk + + + + + + + CLK + + + delay_clk + + + + + + ASSOCIATED_RESET + delay_rst + + + + + delay_rst + + + + + + + RST + + + delay_rst + + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_fmcadc5_sync + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + bc167762 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_fmcadc5_sync + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + bb8328f0 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 804b322e + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + + + rx_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_sysref + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_sync_0 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + rx_sync_1 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + rx_sysref_p + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_sysref_n + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_sync_0_p + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_sync_0_n + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_sync_1_p + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_sync_1_n + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_enable_0 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_data_0 + + in + + 255 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + rx_enable_1 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_data_1 + + in + + 255 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + rx_enable + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_data + + out + + 511 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + vcal + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + psync + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + delay_rst + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + delay_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + spi_csn_o + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + spi_clk_o + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + spi_sdo_o + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + spi_csn + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + spi_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + spi_mosi + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + spi_miso + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + DELAY_REFCLK_FREQUENCY + Delay Refclk Frequency + 200 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_00ecfe9a + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + + + choice_pairs_19f99f31 + 0 + 10 + 11 + 12 + 13 + 14 + 20 + 21 + 22 + 23 + 24 + 25 + 30 + + + choice_pairs_28f798a2 + 0 + 1 + 2 + 3 + 4 + + + choice_pairs_fc01a186 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + + + xilinx_anylanguagesynthesis_view_fileset + + axi_fmcadc5_sync_constr.xdc + xdc + + + ../xilinx/common/ad_data_out.v + verilogSource + + + ../xilinx/common/ad_mul.v + verilogSource + + + axi_fmcadc5_sync_calcor.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + axi_fmcadc5_sync.v + verilogSource + CHECKSUM_b6a370b0 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../xilinx/common/ad_data_out.v + verilogSource + + + ../xilinx/common/ad_mul.v + verilogSource + + + axi_fmcadc5_sync_calcor.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + axi_fmcadc5_sync.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_fmcadc5_sync_v1_0.tcl + tclSource + CHECKSUM_243d7c29 + XGUI_VERSION_2 + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + axi_fmcadc5_sync_v1_0 + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + DELAY_REFCLK_FREQUENCY + Delay Refclk Frequency + 200 + + + Component_Name + axi_fmcadc5_sync_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_fmcadc5_sync_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:46:28Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_fmcadc5_sync/temporary_case_dependencies.mk b/adi_library/axi_fmcadc5_sync/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/axi_fmcadc5_sync/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/axi_fmcadc5_sync/xgui/axi_fmcadc5_sync_v1_0.tcl b/adi_library/axi_fmcadc5_sync/xgui/axi_fmcadc5_sync_v1_0.tcl new file mode 100644 index 00000000..ca987acc --- /dev/null +++ b/adi_library/axi_fmcadc5_sync/xgui/axi_fmcadc5_sync_v1_0.tcl @@ -0,0 +1,103 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DELAY_REFCLK_FREQUENCY" -parent ${Page_0} + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } { + # Procedure called to update DELAY_REFCLK_FREQUENCY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } { + # Procedure called to validate DELAY_REFCLK_FREQUENCY + return true +} + +proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to validate DEV_PACKAGE + return true +} + +proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to validate FPGA_FAMILY + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to validate SPEED_GRADE + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY} +} + +proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE} +} + +proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE} +} + +proc update_MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY { MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY PARAM_VALUE.DELAY_REFCLK_FREQUENCY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DELAY_REFCLK_FREQUENCY}] ${MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY} +} + diff --git a/adi_library/axi_generic_adc/Makefile b/adi_library/axi_generic_adc/Makefile new file mode 100644 index 00000000..05c11607 --- /dev/null +++ b/adi_library/axi_generic_adc/Makefile @@ -0,0 +1,21 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_generic_adc + +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_adc_channel.v +GENERIC_DEPS += ../common/up_adc_common.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_generic_adc.v + +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += axi_generic_adc_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_generic_adc/axi_generic_adc.v b/adi_library/axi_generic_adc/axi_generic_adc.v new file mode 100644 index 00000000..551d3e8b --- /dev/null +++ b/adi_library/axi_generic_adc/axi_generic_adc.v @@ -0,0 +1,269 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_generic_adc #( + + parameter NUM_OF_CHANNELS = 2, + parameter ID = 0 +) ( + input adc_clk, + output [NUM_OF_CHANNELS-1:0] adc_enable, + input adc_dovf, + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot +); + + reg [31:0] up_rdata = 'd0; + reg up_rack = 'd0; + reg up_wack = 'd0; + + wire adc_rst; + wire up_rstn; + wire up_clk; + wire [13:0] up_waddr_s; + wire [13:0] up_raddr_s; + + // internal signals + + wire up_sel_s; + wire up_wr_s; + wire [13:0] up_addr_s; + wire [31:0] up_wdata_s; + wire [31:0] up_rdata_s[0:NUM_OF_CHANNELS]; + wire up_rack_s[0:NUM_OF_CHANNELS]; + wire up_wack_s[0:NUM_OF_CHANNELS]; + + reg [31:0] up_rdata_r; + reg up_rack_r; + reg up_wack_r; + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + integer j; + always @(*) begin + up_rdata_r = 'h00; + up_rack_r = 'h00; + up_wack_r = 'h00; + for (j = 0; j <= NUM_OF_CHANNELS; j=j+1) begin + up_rack_r = up_rack_r | up_rack_s[j]; + up_wack_r = up_wack_r | up_wack_s[j]; + up_rdata_r = up_rdata_r | up_rdata_s[j]; + end + end + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_rdata <= up_rdata_r; + up_rack <= up_rack_r; + up_wack <= up_wack_r; + end + end + + up_adc_common #( + .ID(ID) + ) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status ('h00), + .adc_sync_status (1'b1), + .adc_status_ovf (adc_dovf), + .adc_clk_ratio (32'd1), + .adc_start_code (), + .adc_sref_sync (), + .adc_sync (), + .adc_ext_sync_arm (), + .adc_ext_sync_disarm (), + .adc_ext_sync_manual_req (), + .adc_num_lanes (), + .adc_custom_control (), + .adc_crc_enable (), + .adc_sdr_ddr_n (), + .adc_symb_op (), + .adc_symb_8_16b (), + .up_pps_rcounter (32'b0), + .up_pps_status (1'b0), + .up_pps_irq_mask (), + .up_adc_r1_mode (), + .up_adc_ce (), + .up_status_pn_err (1'b0), + .up_status_pn_oos (1'b0), + .up_status_or (1'b0), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .adc_config_wr (), + .adc_config_ctrl (), + .adc_config_rd ('d0), + .adc_ctrl_status ('d0), + .up_usr_chanmax_out (), + .up_usr_chanmax_in (NUM_OF_CHANNELS), + .up_adc_gpio_in (32'b0), + .up_adc_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[NUM_OF_CHANNELS]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[NUM_OF_CHANNELS]), + .up_rack (up_rack_s[NUM_OF_CHANNELS])); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + + generate + genvar i; + + for (i = 0; i < NUM_OF_CHANNELS; i=i+1) begin + up_adc_channel #( + .CHANNEL_ID(i) + ) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable[i]), + .adc_iqcor_enb (), + .adc_dcfilt_enb (), + .adc_dfmt_se (), + .adc_dfmt_type (), + .adc_dfmt_enable (), + .adc_dcfilt_offset (), + .adc_dcfilt_coeff (), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pnseq_sel (), + .adc_data_sel (), + .adc_pn_err (1'b0), + .adc_pn_oos (1'b0), + .adc_or (1'b0), + .adc_read_data ('d0), + .adc_status_header ('d0), + .adc_crc_err ('d0), + .up_adc_pn_err (), + .up_adc_pn_oos (), + .up_adc_or (), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd32), + .adc_usr_datatype_bits (8'd32), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[i]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[i]), + .up_rack (up_rack_s[i])); + end + + endgenerate + +endmodule diff --git a/adi_library/axi_generic_adc/axi_generic_adc.xpr b/adi_library/axi_generic_adc/axi_generic_adc.xpr new file mode 100644 index 00000000..7f39b0af --- /dev/null +++ b/adi_library/axi_generic_adc/axi_generic_adc.xpr @@ -0,0 +1,454 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_generic_adc/axi_generic_adc_ip.tcl b/adi_library/axi_generic_adc/axi_generic_adc_ip.tcl new file mode 100644 index 00000000..3e56643b --- /dev/null +++ b/adi_library/axi_generic_adc/axi_generic_adc_ip.tcl @@ -0,0 +1,31 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_generic_adc +adi_ip_files axi_generic_adc [list \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "axi_generic_adc.v" \ +] + +adi_ip_properties axi_generic_adc + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_adc_ip} [ipx::current_core] + +ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] + + diff --git a/adi_library/axi_generic_adc/component.xml b/adi_library/axi_generic_adc/component.xml new file mode 100644 index 00000000..8e05c1db --- /dev/null +++ b/adi_library/axi_generic_adc/component.xml @@ -0,0 +1,853 @@ + + + analog.com + user + axi_generic_adc + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + adc_clk + + + + + + + CLK + + + adc_clk + + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_generic_adc + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + eb75f9bd + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_generic_adc + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + daf9ad57 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 642cc3fd + + + + + + + adc_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_enable + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_dovf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + NUM_OF_CHANNELS + Num Of Channels + 2 + + + ID + Id + 0 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../common/ad_rst.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_generic_adc.v + verilogSource + CHECKSUM_0f8af5eb + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_rst.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_generic_adc.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_generic_adc_v1_0.tcl + tclSource + CHECKSUM_642cc3fd + XGUI_VERSION_2 + + + + axi_generic_adc_v1_0 + + + NUM_OF_CHANNELS + Num Of Channels + 2 + + + ID + Id + 0 + + + Component_Name + axi_generic_adc_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_generic_adc_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_adc_ip + 1 + 2024-01-14T03:46:40Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_generic_adc/xgui/axi_generic_adc_v1_0.tcl b/adi_library/axi_generic_adc/xgui/axi_generic_adc_v1_0.tcl new file mode 100644 index 00000000..4fe6aad6 --- /dev/null +++ b/adi_library/axi_generic_adc/xgui/axi_generic_adc_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_OF_CHANNELS" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to update NUM_OF_CHANNELS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to validate NUM_OF_CHANNELS + return true +} + + +proc update_MODELPARAM_VALUE.NUM_OF_CHANNELS { MODELPARAM_VALUE.NUM_OF_CHANNELS PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_CHANNELS}] ${MODELPARAM_VALUE.NUM_OF_CHANNELS} +} + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + diff --git a/adi_library/axi_gpreg/Makefile b/adi_library/axi_gpreg/Makefile new file mode 100644 index 00000000..5ef3a5c9 --- /dev/null +++ b/adi_library/axi_gpreg/Makefile @@ -0,0 +1,20 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_gpreg + +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += axi_gpreg.v +GENERIC_DEPS += axi_gpreg_clock_mon.v +GENERIC_DEPS += axi_gpreg_io.v + +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += axi_gpreg_constr.ttcl +XILINX_DEPS += axi_gpreg_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_gpreg/axi_gpreg.v b/adi_library/axi_gpreg/axi_gpreg.v new file mode 100644 index 00000000..7650e01f --- /dev/null +++ b/adi_library/axi_gpreg/axi_gpreg.v @@ -0,0 +1,349 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_gpreg #( + + parameter integer ID = 0, + parameter integer NUM_OF_IO = 8, + parameter integer NUM_OF_CLK_MONS = 8, + parameter integer BUF_ENABLE_0 = 1, + parameter integer BUF_ENABLE_1 = 1, + parameter integer BUF_ENABLE_2 = 1, + parameter integer BUF_ENABLE_3 = 1, + parameter integer BUF_ENABLE_4 = 1, + parameter integer BUF_ENABLE_5 = 1, + parameter integer BUF_ENABLE_6 = 1, + parameter integer BUF_ENABLE_7 = 1 +) ( + + // io + + output [ 31:0] up_gp_ioenb_0, + output [ 31:0] up_gp_out_0, + input [ 31:0] up_gp_in_0, + output [ 31:0] up_gp_ioenb_1, + output [ 31:0] up_gp_out_1, + input [ 31:0] up_gp_in_1, + output [ 31:0] up_gp_ioenb_2, + output [ 31:0] up_gp_out_2, + input [ 31:0] up_gp_in_2, + output [ 31:0] up_gp_ioenb_3, + output [ 31:0] up_gp_out_3, + input [ 31:0] up_gp_in_3, + output [ 31:0] up_gp_ioenb_4, + output [ 31:0] up_gp_out_4, + input [ 31:0] up_gp_in_4, + output [ 31:0] up_gp_ioenb_5, + output [ 31:0] up_gp_out_5, + input [ 31:0] up_gp_in_5, + output [ 31:0] up_gp_ioenb_6, + output [ 31:0] up_gp_out_6, + input [ 31:0] up_gp_in_6, + output [ 31:0] up_gp_ioenb_7, + output [ 31:0] up_gp_out_7, + input [ 31:0] up_gp_in_7, + + // clock monitors + + input d_clk_0, + input d_clk_1, + input d_clk_2, + input d_clk_3, + input d_clk_4, + input d_clk_5, + input d_clk_6, + input d_clk_7, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [ 15:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [ 31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [ 15:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot +); + + // version + + localparam [31:0] PCORE_VERSION = 32'h00040063; + localparam integer BUF_ENABLE[7:0] = {BUF_ENABLE_7, BUF_ENABLE_6, BUF_ENABLE_5, BUF_ENABLE_4, + BUF_ENABLE_3, BUF_ENABLE_2, BUF_ENABLE_1, BUF_ENABLE_0}; + + // internal registers + + reg up_wack_d = 'd0; + reg up_rack_d = 'd0; + reg [ 31:0] up_rdata_d = 'd0; + reg up_wack = 'd0; + reg [ 31:0] up_scratch = 'd0; + reg up_rack = 'd0; + reg [ 31:0] up_rdata = 'd0; + + // internal signals + + wire up_rstn; + wire up_clk; + wire up_wreq; + wire [ 13:0] up_waddr; + wire [ 31:0] up_wdata; + wire up_rreq; + wire [ 13:0] up_raddr; + wire up_wreq_s; + wire up_rreq_s; + wire [ 31:0] up_gp_ioenb_s[7:0]; + wire [ 31:0] up_gp_out_s[7:0]; + wire [ 31:0] up_gp_in_s[7:0]; + wire [ 7:0] d_clk_s; + wire [ 16:0] up_wack_s; + wire [ 16:0] up_rack_s; + wire [ 31:0] up_rdata_s[16:0]; + + // signal name changes + + assign up_rstn = s_axi_aresetn; + assign up_clk = s_axi_aclk; + + // split-up interfaces + + assign up_gp_ioenb_0 = up_gp_ioenb_s[0]; + assign up_gp_out_0 = up_gp_out_s[0]; + assign up_gp_in_s[0] = up_gp_in_0; + assign up_gp_ioenb_1 = up_gp_ioenb_s[1]; + assign up_gp_out_1 = up_gp_out_s[1]; + assign up_gp_in_s[1] = up_gp_in_1; + assign up_gp_ioenb_2 = up_gp_ioenb_s[2]; + assign up_gp_out_2 = up_gp_out_s[2]; + assign up_gp_in_s[2] = up_gp_in_2; + assign up_gp_ioenb_3 = up_gp_ioenb_s[3]; + assign up_gp_out_3 = up_gp_out_s[3]; + assign up_gp_in_s[3] = up_gp_in_3; + assign up_gp_ioenb_4 = up_gp_ioenb_s[4]; + assign up_gp_out_4 = up_gp_out_s[4]; + assign up_gp_in_s[4] = up_gp_in_4; + assign up_gp_ioenb_5 = up_gp_ioenb_s[5]; + assign up_gp_out_5 = up_gp_out_s[5]; + assign up_gp_in_s[5] = up_gp_in_5; + assign up_gp_ioenb_6 = up_gp_ioenb_s[6]; + assign up_gp_out_6 = up_gp_out_s[6]; + assign up_gp_in_s[6] = up_gp_in_6; + assign up_gp_ioenb_7 = up_gp_ioenb_s[7]; + assign up_gp_out_7 = up_gp_out_s[7]; + assign up_gp_in_s[7] = up_gp_in_7; + + assign d_clk_s[0] = d_clk_0; + assign d_clk_s[1] = d_clk_1; + assign d_clk_s[2] = d_clk_2; + assign d_clk_s[3] = d_clk_3; + assign d_clk_s[4] = d_clk_4; + assign d_clk_s[5] = d_clk_5; + assign d_clk_s[6] = d_clk_6; + assign d_clk_s[7] = d_clk_7; + + // up signals + + always @(posedge up_clk or negedge up_rstn) begin + if (up_rstn == 1'b0) begin + up_wack_d <= 1'd0; + up_rack_d <= 1'd0; + up_rdata_d <= 32'd0; + end else begin + up_wack_d <= | up_wack_s; + up_rack_d <= | up_rack_s; + up_rdata_d <= up_rdata_s[ 0] | up_rdata_s[ 1] | up_rdata_s[ 2] | + up_rdata_s[ 3] | up_rdata_s[ 4] | up_rdata_s[ 5] | up_rdata_s[ 6] | + up_rdata_s[ 7] | up_rdata_s[ 8] | up_rdata_s[ 9] | up_rdata_s[10] | + up_rdata_s[11] | up_rdata_s[12] | up_rdata_s[13] | up_rdata_s[14] | + up_rdata_s[15] | up_rdata_s[16]; + end + end + + // generic register map + + assign up_wack_s[16] = up_wack; + assign up_rack_s[16] = up_rack; + assign up_rdata_s[16] = up_rdata; + + // decode block select + + assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0; + assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0; + + // processor write interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_scratch <= 'd0; + end else begin + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin + up_scratch <= up_wdata; + end + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[7:0]) + 8'h00: up_rdata <= PCORE_VERSION; + 8'h01: up_rdata <= ID; + 8'h02: up_rdata <= up_scratch; + default: up_rdata <= 0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + // instantiations + + genvar n; + generate + // gpio + + if (NUM_OF_IO < 8) begin + for (n = NUM_OF_IO; n < 8; n = n + 1) begin: g_unused_io + assign up_gp_ioenb_s[n] = 32'd0; + assign up_gp_out_s[n] = 32'd0; + assign up_wack_s[n] = 1'd0; + assign up_rdata_s[n] = 32'd0; + assign up_rack_s[n] = 1'd0; + end + end + + for (n = 0; n < NUM_OF_IO; n = n + 1) begin: g_io + axi_gpreg_io #( + .ID (16+n) + ) i_gpreg_io ( + .up_gp_ioenb (up_gp_ioenb_s[n]), + .up_gp_out (up_gp_out_s[n]), + .up_gp_in (up_gp_in_s[n]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[n]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[n]), + .up_rack (up_rack_s[n])); + end + + // clock monitors + + if (NUM_OF_CLK_MONS < 8) begin + for (n = NUM_OF_CLK_MONS; n < 8; n = n + 1) begin: g_unused_clock_mon + assign up_wack_s[(8+n)] = 1'd0; + assign up_rdata_s[(8+n)] = 32'd0; + assign up_rack_s[(8+n)] = 1'd0; + end + end + + for (n = 0; n < NUM_OF_CLK_MONS; n = n + 1) begin: g_clock_mon + axi_gpreg_clock_mon #( + .ID (32+n), + .BUF_ENABLE (BUF_ENABLE[n]) + ) i_gpreg_clock_mon ( + .d_clk (d_clk_s[n]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_s[(8+n)]), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_s[(8+n)]), + .up_rack (up_rack_s[(8+n)])); + end + endgenerate + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack_d), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata_d), + .up_rack (up_rack_d)); + +endmodule diff --git a/adi_library/axi_gpreg/axi_gpreg.xpr b/adi_library/axi_gpreg/axi_gpreg.xpr new file mode 100644 index 00000000..e0c02ecb --- /dev/null +++ b/adi_library/axi_gpreg/axi_gpreg.xpr @@ -0,0 +1,441 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_gpreg/axi_gpreg_clock_mon.v b/adi_library/axi_gpreg/axi_gpreg_clock_mon.v new file mode 100644 index 00000000..022aab7e --- /dev/null +++ b/adi_library/axi_gpreg/axi_gpreg_clock_mon.v @@ -0,0 +1,141 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_gpreg_clock_mon #( + + parameter ID = 0, + parameter BUF_ENABLE = 0 +) ( + + // clock + + input d_clk, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack +); + + // internal registers + + reg up_d_preset = 'd0; + reg up_d_resetn = 'd0; + + // internal signals + + wire up_wreq_s; + wire up_rreq_s; + wire [31:0] up_d_count_s; + wire d_rst; + wire d_clk_g; + + // decode block select + + assign up_wreq_s = (up_waddr[13:4] == ID) ? up_wreq : 1'b0; + assign up_rreq_s = (up_raddr[13:4] == ID) ? up_rreq : 1'b0; + + // processor write interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_d_preset <= 1'd1; + up_wack <= 'd0; + up_d_resetn <= 'd0; + end else begin + up_d_preset <= ~up_d_resetn; + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin + up_d_resetn <= up_wdata[0]; + end + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[3:0]) + 4'b0000: up_rdata <= {31'd0, up_d_resetn}; + 4'b0010: up_rdata <= up_d_count_s; + default: up_rdata <= 32'd0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + // clock monitor + + up_clock_mon i_clock_mon ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_d_count (up_d_count_s), + .d_rst (d_rst), + .d_clk (d_clk_g)); + + ad_rst i_d_rst_reg ( + .rst_async (up_d_preset), + .clk (d_clk_g), + .rstn (), + .rst (d_rst)); + + generate + if (BUF_ENABLE == 1) begin + BUFG i_bufg ( + .I (d_clk), + .O (d_clk_g)); + end else begin + assign d_clk_g = d_clk; + end + endgenerate + +endmodule diff --git a/adi_library/axi_gpreg/axi_gpreg_constr.ttcl b/adi_library/axi_gpreg/axi_gpreg_constr.ttcl new file mode 100644 index 00000000..34a545c6 --- /dev/null +++ b/adi_library/axi_gpreg/axi_gpreg_constr.ttcl @@ -0,0 +1,23 @@ +############################################################################### +## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName [ttcl_add $ComponentName "_constr"] :> +<: setFileExtension ".xdc" :> +<: setFileProcessingOrder late :> +<: set num_of_clk_mons [getBooleanValue "NUM_OF_CLK_MONS"] :> + +<: if { $num_of_clk_mons > 0 } { :> + +set_property ASYNC_REG true [get_cells -hierarchical -filter {name =~ *up_count_running_m*}] +set_property ASYNC_REG true [get_cells -hierarchical -filter {name =~ *d_count_run_m*}] +set_property ASYNC_REG true [get_cells -hierarchical -filter {name =~ *up_d_count_reg*}] + +set_false_path -from [get_cells -hierarchical -filter {name =~ *d_count_run_m3_reg* && IS_SEQUENTIAL}] -to [get_cells -hierarchical -filter {name =~ *up_count_running_m1_reg* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hierarchical -filter {name =~ *up_count_run_reg* && IS_SEQUENTIAL}] -to [get_cells -hierarchical -filter {name =~ *d_count_run_m1_reg* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hierarchical -filter {name =~ *d_count_reg* && IS_SEQUENTIAL}] -to [get_cells -hierarchical -filter {name =~ *up_d_count_reg* && IS_SEQUENTIAL}] + +<: } :> diff --git a/adi_library/axi_gpreg/axi_gpreg_io.v b/adi_library/axi_gpreg/axi_gpreg_io.v new file mode 100644 index 00000000..1483e68a --- /dev/null +++ b/adi_library/axi_gpreg/axi_gpreg_io.v @@ -0,0 +1,114 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_gpreg_io #( + + parameter ID = 0 +) ( + + // gpio + + output reg [31:0] up_gp_ioenb, + output reg [31:0] up_gp_out, + input [31:0] up_gp_in, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack +); + + // internal registers + + // internal signals + + wire up_wreq_s; + wire up_rreq_s; + + // decode block select + + assign up_wreq_s = (up_waddr[13:4] == ID) ? up_wreq : 1'b0; + assign up_rreq_s = (up_raddr[13:4] == ID) ? up_rreq : 1'b0; + + // processor write interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_gp_ioenb <= {32{1'b1}}; + up_gp_out <= 'd0; + end else begin + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin + up_gp_ioenb <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin + up_gp_out <= up_wdata; + end + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[3:0]) + 4'b0000: up_rdata <= up_gp_ioenb; + 4'b0001: up_rdata <= up_gp_out; + 4'b0010: up_rdata <= up_gp_in; + default: up_rdata <= 32'd0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + +endmodule diff --git a/adi_library/axi_gpreg/axi_gpreg_ip.tcl b/adi_library/axi_gpreg/axi_gpreg_ip.tcl new file mode 100644 index 00000000..8ca8881f --- /dev/null +++ b/adi_library/axi_gpreg/axi_gpreg_ip.tcl @@ -0,0 +1,63 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_gpreg +adi_ip_files axi_gpreg [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "axi_gpreg_io.v" \ + "axi_gpreg_constr.ttcl" \ + "axi_gpreg_clock_mon.v" \ + "axi_gpreg.v" ] + +set_property FILE_TYPE SystemVerilog [get_files "axi_gpreg.v"] + +adi_ip_properties axi_gpreg +adi_ip_ttcl axi_gpreg "axi_gpreg_constr.ttcl" + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 0} \ + [ipx::get_ports up_gp_*_0 -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 1} \ + [ipx::get_ports up_gp_*_1 -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 2} \ + [ipx::get_ports up_gp_*_2 -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 3} \ + [ipx::get_ports up_gp_*_3 -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 4} \ + [ipx::get_ports up_gp_*_4 -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 5} \ + [ipx::get_ports up_gp_*_5 -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 6} \ + [ipx::get_ports up_gp_*_6 -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_IO')) > 7} \ + [ipx::get_ports up_gp_*_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 0} \ + [ipx::get_ports d_clk_0 -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 1} \ + [ipx::get_ports d_clk_1 -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 2} \ + [ipx::get_ports d_clk_2 -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 3} \ + [ipx::get_ports d_clk_3 -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 4} \ + [ipx::get_ports d_clk_4 -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 5} \ + [ipx::get_ports d_clk_5 -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 6} \ + [ipx::get_ports d_clk_6 -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CLK_MONS')) > 7} \ + [ipx::get_ports d_clk_7 -of_objects [ipx::current_core]] + +set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]] + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/axi_gpreg/component.xml b/adi_library/axi_gpreg/component.xml new file mode 100644 index 00000000..41366da0 --- /dev/null +++ b/adi_library/axi_gpreg/component.xml @@ -0,0 +1,1638 @@ + + + analog.com + user + axi_gpreg + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + SystemVerilog + axi_gpreg + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + c4ab9d05 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + SystemVerilog + axi_gpreg + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 5ca46b5b + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 1616057c + + + + + + + up_gp_ioenb_0 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + up_gp_out_0 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + up_gp_in_0 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + up_gp_ioenb_1 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + up_gp_out_1 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + up_gp_in_1 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + up_gp_ioenb_2 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + up_gp_out_2 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + up_gp_in_2 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + up_gp_ioenb_3 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + up_gp_out_3 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + up_gp_in_3 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + up_gp_ioenb_4 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + up_gp_out_4 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + up_gp_in_4 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + up_gp_ioenb_5 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + up_gp_out_5 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + up_gp_in_5 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + up_gp_ioenb_6 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + up_gp_out_6 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + up_gp_in_6 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + up_gp_ioenb_7 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + up_gp_out_7 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + up_gp_in_7 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + d_clk_0 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + d_clk_1 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + d_clk_2 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + d_clk_3 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + d_clk_4 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + d_clk_5 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + d_clk_6 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + d_clk_7 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + NUM_OF_IO + Num Of Io + 8 + + + NUM_OF_CLK_MONS + Num Of Clk Mons + 8 + + + BUF_ENABLE_0 + Buf Enable 0 + 1 + + + BUF_ENABLE_1 + Buf Enable 1 + 1 + + + BUF_ENABLE_2 + Buf Enable 2 + 1 + + + BUF_ENABLE_3 + Buf Enable 3 + 1 + + + BUF_ENABLE_4 + Buf Enable 4 + 1 + + + BUF_ENABLE_5 + Buf Enable 5 + 1 + + + BUF_ENABLE_6 + Buf Enable 6 + 1 + + + BUF_ENABLE_7 + Buf Enable 7 + 1 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + axi_gpreg_constr.ttcl + ttcl + + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../common/ad_rst.v + verilogSource + + + axi_gpreg_clock_mon.v + verilogSource + + + axi_gpreg_io.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + axi_gpreg.v + systemVerilogSource + CHECKSUM_eb2994e4 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_rst.v + verilogSource + + + axi_gpreg_clock_mon.v + verilogSource + + + axi_gpreg_io.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + axi_gpreg.v + systemVerilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_gpreg_v1_0.tcl + tclSource + CHECKSUM_1616057c + XGUI_VERSION_2 + + + + axi_gpreg_v1_0 + + + ID + Id + 0 + + + NUM_OF_IO + Num Of Io + 8 + + + NUM_OF_CLK_MONS + Num Of Clk Mons + 8 + + + BUF_ENABLE_0 + Buf Enable 0 + 1 + + + BUF_ENABLE_1 + Buf Enable 1 + 1 + + + BUF_ENABLE_2 + Buf Enable 2 + 1 + + + BUF_ENABLE_3 + Buf Enable 3 + 1 + + + BUF_ENABLE_4 + Buf Enable 4 + 1 + + + BUF_ENABLE_5 + Buf Enable 5 + 1 + + + BUF_ENABLE_6 + Buf Enable 6 + 1 + + + BUF_ENABLE_7 + Buf Enable 7 + 1 + + + Component_Name + axi_gpreg_v1_0 + + + + + + virtex7 + + + /Analog_Devices + + axi_gpreg_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:46:51Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_gpreg/xgui/axi_gpreg_v1_0.tcl b/adi_library/axi_gpreg/xgui/axi_gpreg_v1_0.tcl new file mode 100644 index 00000000..8c8a116a --- /dev/null +++ b/adi_library/axi_gpreg/xgui/axi_gpreg_v1_0.tcl @@ -0,0 +1,175 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "BUF_ENABLE_0" -parent ${Page_0} + ipgui::add_param $IPINST -name "BUF_ENABLE_1" -parent ${Page_0} + ipgui::add_param $IPINST -name "BUF_ENABLE_2" -parent ${Page_0} + ipgui::add_param $IPINST -name "BUF_ENABLE_3" -parent ${Page_0} + ipgui::add_param $IPINST -name "BUF_ENABLE_4" -parent ${Page_0} + ipgui::add_param $IPINST -name "BUF_ENABLE_5" -parent ${Page_0} + ipgui::add_param $IPINST -name "BUF_ENABLE_6" -parent ${Page_0} + ipgui::add_param $IPINST -name "BUF_ENABLE_7" -parent ${Page_0} + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_OF_CLK_MONS" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_OF_IO" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.BUF_ENABLE_0 { PARAM_VALUE.BUF_ENABLE_0 } { + # Procedure called to update BUF_ENABLE_0 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BUF_ENABLE_0 { PARAM_VALUE.BUF_ENABLE_0 } { + # Procedure called to validate BUF_ENABLE_0 + return true +} + +proc update_PARAM_VALUE.BUF_ENABLE_1 { PARAM_VALUE.BUF_ENABLE_1 } { + # Procedure called to update BUF_ENABLE_1 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BUF_ENABLE_1 { PARAM_VALUE.BUF_ENABLE_1 } { + # Procedure called to validate BUF_ENABLE_1 + return true +} + +proc update_PARAM_VALUE.BUF_ENABLE_2 { PARAM_VALUE.BUF_ENABLE_2 } { + # Procedure called to update BUF_ENABLE_2 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BUF_ENABLE_2 { PARAM_VALUE.BUF_ENABLE_2 } { + # Procedure called to validate BUF_ENABLE_2 + return true +} + +proc update_PARAM_VALUE.BUF_ENABLE_3 { PARAM_VALUE.BUF_ENABLE_3 } { + # Procedure called to update BUF_ENABLE_3 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BUF_ENABLE_3 { PARAM_VALUE.BUF_ENABLE_3 } { + # Procedure called to validate BUF_ENABLE_3 + return true +} + +proc update_PARAM_VALUE.BUF_ENABLE_4 { PARAM_VALUE.BUF_ENABLE_4 } { + # Procedure called to update BUF_ENABLE_4 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BUF_ENABLE_4 { PARAM_VALUE.BUF_ENABLE_4 } { + # Procedure called to validate BUF_ENABLE_4 + return true +} + +proc update_PARAM_VALUE.BUF_ENABLE_5 { PARAM_VALUE.BUF_ENABLE_5 } { + # Procedure called to update BUF_ENABLE_5 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BUF_ENABLE_5 { PARAM_VALUE.BUF_ENABLE_5 } { + # Procedure called to validate BUF_ENABLE_5 + return true +} + +proc update_PARAM_VALUE.BUF_ENABLE_6 { PARAM_VALUE.BUF_ENABLE_6 } { + # Procedure called to update BUF_ENABLE_6 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BUF_ENABLE_6 { PARAM_VALUE.BUF_ENABLE_6 } { + # Procedure called to validate BUF_ENABLE_6 + return true +} + +proc update_PARAM_VALUE.BUF_ENABLE_7 { PARAM_VALUE.BUF_ENABLE_7 } { + # Procedure called to update BUF_ENABLE_7 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BUF_ENABLE_7 { PARAM_VALUE.BUF_ENABLE_7 } { + # Procedure called to validate BUF_ENABLE_7 + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.NUM_OF_CLK_MONS { PARAM_VALUE.NUM_OF_CLK_MONS } { + # Procedure called to update NUM_OF_CLK_MONS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_CLK_MONS { PARAM_VALUE.NUM_OF_CLK_MONS } { + # Procedure called to validate NUM_OF_CLK_MONS + return true +} + +proc update_PARAM_VALUE.NUM_OF_IO { PARAM_VALUE.NUM_OF_IO } { + # Procedure called to update NUM_OF_IO when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_IO { PARAM_VALUE.NUM_OF_IO } { + # Procedure called to validate NUM_OF_IO + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.NUM_OF_IO { MODELPARAM_VALUE.NUM_OF_IO PARAM_VALUE.NUM_OF_IO } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_IO}] ${MODELPARAM_VALUE.NUM_OF_IO} +} + +proc update_MODELPARAM_VALUE.NUM_OF_CLK_MONS { MODELPARAM_VALUE.NUM_OF_CLK_MONS PARAM_VALUE.NUM_OF_CLK_MONS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_CLK_MONS}] ${MODELPARAM_VALUE.NUM_OF_CLK_MONS} +} + +proc update_MODELPARAM_VALUE.BUF_ENABLE_0 { MODELPARAM_VALUE.BUF_ENABLE_0 PARAM_VALUE.BUF_ENABLE_0 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BUF_ENABLE_0}] ${MODELPARAM_VALUE.BUF_ENABLE_0} +} + +proc update_MODELPARAM_VALUE.BUF_ENABLE_1 { MODELPARAM_VALUE.BUF_ENABLE_1 PARAM_VALUE.BUF_ENABLE_1 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BUF_ENABLE_1}] ${MODELPARAM_VALUE.BUF_ENABLE_1} +} + +proc update_MODELPARAM_VALUE.BUF_ENABLE_2 { MODELPARAM_VALUE.BUF_ENABLE_2 PARAM_VALUE.BUF_ENABLE_2 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BUF_ENABLE_2}] ${MODELPARAM_VALUE.BUF_ENABLE_2} +} + +proc update_MODELPARAM_VALUE.BUF_ENABLE_3 { MODELPARAM_VALUE.BUF_ENABLE_3 PARAM_VALUE.BUF_ENABLE_3 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BUF_ENABLE_3}] ${MODELPARAM_VALUE.BUF_ENABLE_3} +} + +proc update_MODELPARAM_VALUE.BUF_ENABLE_4 { MODELPARAM_VALUE.BUF_ENABLE_4 PARAM_VALUE.BUF_ENABLE_4 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BUF_ENABLE_4}] ${MODELPARAM_VALUE.BUF_ENABLE_4} +} + +proc update_MODELPARAM_VALUE.BUF_ENABLE_5 { MODELPARAM_VALUE.BUF_ENABLE_5 PARAM_VALUE.BUF_ENABLE_5 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BUF_ENABLE_5}] ${MODELPARAM_VALUE.BUF_ENABLE_5} +} + +proc update_MODELPARAM_VALUE.BUF_ENABLE_6 { MODELPARAM_VALUE.BUF_ENABLE_6 PARAM_VALUE.BUF_ENABLE_6 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BUF_ENABLE_6}] ${MODELPARAM_VALUE.BUF_ENABLE_6} +} + +proc update_MODELPARAM_VALUE.BUF_ENABLE_7 { MODELPARAM_VALUE.BUF_ENABLE_7 PARAM_VALUE.BUF_ENABLE_7 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BUF_ENABLE_7}] ${MODELPARAM_VALUE.BUF_ENABLE_7} +} + diff --git a/adi_library/axi_hdmi_rx/Makefile b/adi_library/axi_hdmi_rx/Makefile new file mode 100644 index 00000000..bcafa93b --- /dev/null +++ b/adi_library/axi_hdmi_rx/Makefile @@ -0,0 +1,29 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_hdmi_rx + +GENERIC_DEPS += ../common/ad_csc.v +GENERIC_DEPS += ../common/ad_csc_CrYCb2RGB.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/ad_ss_422to444.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_hdmi_rx.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_hdmi_rx.v +GENERIC_DEPS += axi_hdmi_rx_core.v +GENERIC_DEPS += axi_hdmi_rx_es.v +GENERIC_DEPS += axi_hdmi_rx_tpm.v + +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_hdmi_rx_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_hdmi_rx/axi_hdmi_rx.v b/adi_library/axi_hdmi_rx/axi_hdmi_rx.v new file mode 100644 index 00000000..3640be4a --- /dev/null +++ b/adi_library/axi_hdmi_rx/axi_hdmi_rx.v @@ -0,0 +1,202 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_hdmi_rx #( + + parameter ID = 0, + parameter IO_INTERFACE = 1 +) ( + + // hdmi interface + + input hdmi_rx_clk, + input [15:0] hdmi_rx_data, + + // dma interface + + output hdmi_clk, + output hdmi_dma_sof, + output hdmi_dma_de, + output [63:0] hdmi_dma_data, + input hdmi_dma_ovf, + input hdmi_dma_unf, + + // processor interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot +); + + // internal signals + + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire up_wack_s; + wire up_rreq_s; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_s; + wire up_rack_s; + wire hdmi_edge_sel_s; + wire hdmi_bgr_s; + wire hdmi_packed_s; + wire hdmi_csc_bypass_s; + wire [15:0] hdmi_vs_count_s; + wire [15:0] hdmi_hs_count_s; + wire hdmi_tpm_oos_s; + wire hdmi_vs_oos_s; + wire hdmi_hs_oos_s; + wire hdmi_vs_mismatch_s; + wire hdmi_hs_mismatch_s; + wire [15:0] hdmi_vs_s; + wire [15:0] hdmi_hs_s; + wire hdmi_rst; + wire [15:0] hdmi_data; + + // signal name changes + + assign hdmi_clk = hdmi_rx_clk; + assign hdmi_data = hdmi_rx_data; + assign up_rstn = s_axi_aresetn; + assign up_clk = s_axi_aclk; + + // axi interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + + // processor interface + + up_hdmi_rx i_up ( + .hdmi_clk (hdmi_clk), + .hdmi_rst (hdmi_rst), + .hdmi_edge_sel (hdmi_edge_sel_s), + .hdmi_bgr (hdmi_bgr_s), + .hdmi_packed (hdmi_packed_s), + .hdmi_csc_bypass (hdmi_csc_bypass_s), + .hdmi_vs_count (hdmi_vs_count_s), + .hdmi_hs_count (hdmi_hs_count_s), + .hdmi_dma_ovf (hdmi_dma_ovf), + .hdmi_dma_unf (hdmi_dma_unf), + .hdmi_tpm_oos (hdmi_tpm_oos_s), + .hdmi_vs_oos (hdmi_vs_oos_s), + .hdmi_hs_oos (hdmi_hs_oos_s), + .hdmi_vs_mismatch (hdmi_vs_mismatch_s), + .hdmi_hs_mismatch (hdmi_hs_mismatch_s), + .hdmi_vs (hdmi_vs_s), + .hdmi_hs (hdmi_hs_s), + .hdmi_clk_ratio (32'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + + // hdmi interface + + axi_hdmi_rx_core i_rx_core ( + .hdmi_clk (hdmi_clk), + .hdmi_rst (hdmi_rst), + .hdmi_data (hdmi_data), + .hdmi_edge_sel (hdmi_edge_sel_s), + .hdmi_bgr (hdmi_bgr_s), + .hdmi_packed (hdmi_packed_s), + .hdmi_csc_bypass (hdmi_csc_bypass_s), + .hdmi_vs_count (hdmi_vs_count_s), + .hdmi_hs_count (hdmi_hs_count_s), + .hdmi_tpm_oos (hdmi_tpm_oos_s), + .hdmi_vs_oos (hdmi_vs_oos_s), + .hdmi_hs_oos (hdmi_hs_oos_s), + .hdmi_vs_mismatch (hdmi_vs_mismatch_s), + .hdmi_hs_mismatch (hdmi_hs_mismatch_s), + .hdmi_vs (hdmi_vs_s), + .hdmi_hs (hdmi_hs_s), + .hdmi_dma_sof (hdmi_dma_sof), + .hdmi_dma_de (hdmi_dma_de), + .hdmi_dma_data (hdmi_dma_data)); + +endmodule diff --git a/adi_library/axi_hdmi_rx/axi_hdmi_rx.xpr b/adi_library/axi_hdmi_rx/axi_hdmi_rx.xpr new file mode 100644 index 00000000..1207c764 --- /dev/null +++ b/adi_library/axi_hdmi_rx/axi_hdmi_rx.xpr @@ -0,0 +1,507 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_hdmi_rx/axi_hdmi_rx_core.v b/adi_library/axi_hdmi_rx/axi_hdmi_rx_core.v new file mode 100644 index 00000000..a74e5c59 --- /dev/null +++ b/adi_library/axi_hdmi_rx/axi_hdmi_rx_core.v @@ -0,0 +1,355 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// Receive HDMI, hdmi embedded syncs data in, video dma data out. + +`timescale 1ns/100ps + +module axi_hdmi_rx_core #( + + parameter IO_INTERFACE = 1 +) ( + + // hdmi interface + + input hdmi_clk, + input hdmi_rst, + input [15:0] hdmi_data, + input hdmi_edge_sel, + input hdmi_bgr, + input hdmi_packed, + input hdmi_csc_bypass, + input [15:0] hdmi_vs_count, + input [15:0] hdmi_hs_count, + output hdmi_tpm_oos, + output reg hdmi_vs_oos, + output reg hdmi_hs_oos, + output reg hdmi_vs_mismatch, + output reg hdmi_hs_mismatch, + output reg [15:0] hdmi_vs, + output reg [15:0] hdmi_hs, + + // dma interface + + output reg hdmi_dma_sof, + output reg hdmi_dma_de, + output reg [63:0] hdmi_dma_data +); + + // internal registers + + reg hdmi_dma_de_cnt = 'd0; + reg hdmi_dma_sof_int = 'd0; + reg hdmi_dma_de_int = 'd0; + reg [31:0] hdmi_dma_data_int = 'd0; + reg hdmi_sof_422 = 'd0; + reg hdmi_de_422 = 'd0; + reg hdmi_de_422_cnt = 'd0; + reg [15:0] hdmi_data_422 = 'd0; + reg hdmi_sof_444 = 'd0; + reg hdmi_de_444 = 'd0; + reg [23:0] hdmi_data_444 = 'd0; + reg [ 1:0] hdmi_de_444_cnt = 'd0; + reg [15:0] hdmi_data_444_hold = 'd0; + reg hdmi_sof_444_p = 'd0; + reg hdmi_de_444_p = 'd0; + reg [31:0] hdmi_data_444_p = 'd0; + reg hdmi_dma_enable = 'd0; + reg hdmi_hs_de_d = 'd0; + reg hdmi_vs_de_d = 'd0; + reg hdmi_sof = 'd0; + reg [15:0] hdmi_hs_rcv = 'd0; + reg [15:0] hdmi_hs_cur = 'd0; + reg hdmi_hs_oos_int = 'd0; + reg [15:0] hdmi_vs_rcv = 'd0; + reg [15:0] hdmi_vs_cur = 'd0; + reg hdmi_vs_oos_int = 'd0; + reg [15:0] hdmi_data_p = 'd0; + + // internal signals + + wire [15:0] hdmi_data_p_s; + wire [15:0] hdmi_data_n_s; + wire hdmi_sof_s; + wire hdmi_sof_ss_s; + wire hdmi_de_ss_s; + wire [23:0] hdmi_data_ss_s; + wire hdmi_sof_444_s; + wire hdmi_de_444_s; + wire [23:0] hdmi_data_444_s; + wire [15:0] hdmi_data_de_s; + wire hdmi_hs_de_s; + wire hdmi_vs_de_s; + + // dma interface + + always @(posedge hdmi_clk) begin + if(hdmi_dma_sof_int == 1'b1) begin + hdmi_dma_sof <= 1'b1; + end else if (hdmi_dma_de == 1'b1) begin + hdmi_dma_sof <= 1'b0; + end + + if(hdmi_dma_sof_int == 1'b1) begin + hdmi_dma_de_cnt <= 1'b0; + end else if (hdmi_dma_de_int == 1'b1) begin + hdmi_dma_de_cnt <= ~hdmi_dma_de_cnt; + end + + hdmi_dma_de <= hdmi_dma_de_cnt & hdmi_dma_de_int; + if (hdmi_dma_de_int == 1'b1) begin + hdmi_dma_data[63:32] <= hdmi_dma_data_int; + hdmi_dma_data[31: 0] <= hdmi_dma_data[63:32]; + end + end + + // 32 bit interface + + always @(posedge hdmi_clk) begin + if (hdmi_dma_enable == 1'b0) begin + hdmi_dma_sof_int <= 1'd0; + hdmi_dma_de_int <= 1'd0; + hdmi_dma_data_int <= 32'd0; + hdmi_de_422_cnt <= 1'b0; + end else if (hdmi_csc_bypass == 1'b1) begin + if (hdmi_packed == 1'b0) begin + hdmi_dma_sof_int <= hdmi_sof_422; + hdmi_dma_de_int <= hdmi_de_422; + hdmi_dma_data_int <= {16'd0, hdmi_data_422}; + end else begin + hdmi_dma_sof_int <= hdmi_sof_422; + hdmi_dma_de_int <= hdmi_de_422_cnt && hdmi_de_422; + if (hdmi_de_422) begin + hdmi_de_422_cnt <= hdmi_de_422_cnt + 1'b1; + hdmi_dma_data_int <= {hdmi_data_422, hdmi_dma_data_int[31:16]}; + end + end + end else begin + if (hdmi_packed == 1'b0) begin + hdmi_dma_sof_int <= hdmi_sof_444; + hdmi_dma_de_int <= hdmi_de_444; + hdmi_dma_data_int <= {8'd0, hdmi_data_444}; + end else begin + hdmi_dma_sof_int <= hdmi_sof_444_p; + hdmi_dma_de_int <= hdmi_de_444_p; + hdmi_dma_data_int <= hdmi_data_444_p; + end + end + end + + // sof, enable and data on 422 and 444 domains + + always @(posedge hdmi_clk) begin + hdmi_sof_422 <= hdmi_sof; + hdmi_de_422 <= hdmi_hs_de_s & hdmi_vs_de_s; + hdmi_data_422 <= hdmi_data_de_s; + hdmi_sof_444 <= hdmi_sof_444_s; + hdmi_de_444 <= hdmi_de_444_s; + if (hdmi_bgr == 1'b1) begin + hdmi_data_444[23:16] <= hdmi_data_444_s[ 7: 0]; + hdmi_data_444[15: 8] <= hdmi_data_444_s[15: 8]; + hdmi_data_444[ 7: 0] <= hdmi_data_444_s[23:16]; + end else begin + hdmi_data_444[23:16] <= hdmi_data_444_s[23:16]; + hdmi_data_444[15: 8] <= hdmi_data_444_s[15: 8]; + hdmi_data_444[ 7: 0] <= hdmi_data_444_s[ 7: 0]; + end + if (hdmi_sof_444 == 1'b1) begin + hdmi_de_444_cnt <= (hdmi_de_444 == 1'b1) ? 2'b1 : 2'b0; + end else if (hdmi_de_444 == 1'b1) begin + hdmi_de_444_cnt <= hdmi_de_444_cnt + 1'b1; + end + hdmi_data_444_hold <= hdmi_data_444[23:8]; + hdmi_sof_444_p <= hdmi_sof_444; + hdmi_de_444_p <= hdmi_de_444_cnt[0] | hdmi_de_444_cnt[1]; + case (hdmi_de_444_cnt) + 2'b11: hdmi_data_444_p <= {hdmi_data_444[23:0], hdmi_data_444_hold[15: 8]}; + 2'b10: hdmi_data_444_p <= {hdmi_data_444[15:0], hdmi_data_444_hold[15: 0]}; + 2'b01: hdmi_data_444_p <= {hdmi_data_444[ 7:0], hdmi_data_444_p[23: 0]}; + default: hdmi_data_444_p <= {8'd0, hdmi_data_444}; + endcase + end + + always @(posedge hdmi_clk) begin + if (hdmi_rst == 1'b1) begin + hdmi_dma_enable <= 1'b0; + end else if (hdmi_sof_s == 1'b1) begin + hdmi_dma_enable <= ~(hdmi_vs_oos | hdmi_hs_oos); + end + end + + // horizontal and vertical sync counters, active video size & mismatch + + always @(posedge hdmi_clk) begin + if (hdmi_rst == 1'b1) begin + hdmi_vs <= 'd0; + hdmi_hs <= 'd0; + hdmi_vs_oos <= 1'd1; + hdmi_hs_oos <= 1'd1; + hdmi_vs_mismatch <= 1'd1; + hdmi_hs_mismatch <= 1'd1; + end else if (hdmi_sof == 1'b1) begin + hdmi_vs <= hdmi_vs_cur; + hdmi_hs <= hdmi_hs_cur; + hdmi_vs_oos <= hdmi_vs_oos_int; + hdmi_hs_oos <= hdmi_hs_oos_int; + if (hdmi_vs_count == hdmi_vs_cur) begin + hdmi_vs_mismatch <= hdmi_vs_oos_int; + end else begin + hdmi_vs_mismatch <= 1'b1; + end + if (hdmi_hs_count == hdmi_hs_cur) begin + hdmi_hs_mismatch <= hdmi_hs_oos_int; + end else begin + hdmi_hs_mismatch <= 1'b1; + end + end + end + + assign hdmi_sof_s = hdmi_vs_de_s & ~hdmi_vs_de_d; + + always @(posedge hdmi_clk) begin + hdmi_hs_de_d <= hdmi_hs_de_s; + hdmi_vs_de_d <= hdmi_vs_de_s; + hdmi_sof <= hdmi_sof_s; + if ((hdmi_hs_de_s == 1'b1) && (hdmi_hs_de_d == 1'b0)) begin + hdmi_hs_rcv <= 'd1; + hdmi_hs_cur <= hdmi_hs_rcv; + if (hdmi_hs_cur == hdmi_hs_rcv) begin + hdmi_hs_oos_int <= 1'b0; + end else begin + hdmi_hs_oos_int <= 1'b1; + end + end else if (hdmi_hs_de_s == 1'b1) begin + hdmi_hs_rcv <= hdmi_hs_rcv + 1'b1; + hdmi_hs_cur <= hdmi_hs_cur; + hdmi_hs_oos_int <= hdmi_hs_oos_int; + end + if ((hdmi_vs_de_s == 1'b1) && (hdmi_vs_de_d == 1'b0)) begin + hdmi_vs_rcv <= 'd0; + hdmi_vs_cur <= hdmi_vs_rcv; + if (hdmi_vs_cur == hdmi_vs_rcv) begin + hdmi_vs_oos_int <= 1'b0; + end else begin + hdmi_vs_oos_int <= 1'b1; + end + end else if ((hdmi_vs_de_s == 1'b1) && (hdmi_hs_de_s == 1'b1) && + (hdmi_hs_de_d == 1'b0)) begin + hdmi_vs_rcv <= hdmi_vs_rcv + 1'b1; + hdmi_vs_cur <= hdmi_vs_cur; + hdmi_vs_oos_int <= hdmi_vs_oos_int; + end + end + + // hdmi input data registers + // use iddr if interfacing off-chip (keeps iob) + // use same edge (or register falling edge again) + + genvar n; + generate + if (IO_INTERFACE == 0) begin + for (n = 0; n < 16; n = n + 1) begin: g_hdmi_data + IDDR #( + .DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"), + .INIT_Q1 (1'b0), + .INIT_Q2 (1'b0), + .SRTYPE ("ASYNC") + ) i_rx_data_iddr ( + .CE (1'b1), + .R (1'b0), + .S (1'b0), + .C (hdmi_clk), + .D (hdmi_data[n]), + .Q1 (hdmi_data_p_s[n]), + .Q2 (hdmi_data_n_s[n])); + end + end else begin + assign hdmi_data_p_s = hdmi_data; + assign hdmi_data_n_s = hdmi_data; + end + endgenerate + + always @(posedge hdmi_clk) begin + if (hdmi_edge_sel == 1'b1) begin + hdmi_data_p <= hdmi_data_n_s; + end else begin + hdmi_data_p <= hdmi_data_p_s; + end + end + + // super sampling, 422 to 444 + + ad_ss_422to444 #( + .CR_CB_N(0), + .DELAY_DATA_WIDTH(2) + ) i_ss ( + .clk (hdmi_clk), + .s422_de (hdmi_de_422), + .s422_sync ({hdmi_sof_422, hdmi_de_422}), + .s422_data (hdmi_data_422), + .s444_sync ({hdmi_sof_ss_s, hdmi_de_ss_s}), + .s444_data (hdmi_data_ss_s)); + + // color space conversion, CrYCb to RGB + + ad_csc_CrYCb2RGB #( + .DELAY_DATA_WIDTH(2) + ) i_csc ( + .clk (hdmi_clk), + .CrYCb_sync ({hdmi_sof_ss_s, hdmi_de_ss_s}), + .CrYCb_data (hdmi_data_ss_s), + .RGB_sync ({hdmi_sof_444_s, hdmi_de_444_s}), + .RGB_data (hdmi_data_444_s)); + + // embedded sync + + axi_hdmi_rx_es #( + .DATA_WIDTH(16) + ) i_es ( + .hdmi_clk (hdmi_clk), + .hdmi_data (hdmi_data_p), + .hdmi_vs_de (hdmi_vs_de_s), + .hdmi_hs_de (hdmi_hs_de_s), + .hdmi_data_de (hdmi_data_de_s)); + + // test pattern matcher + + axi_hdmi_rx_tpm i_tpm ( + .hdmi_clk (hdmi_clk), + .hdmi_sof (hdmi_sof_422), + .hdmi_de (hdmi_de_422), + .hdmi_data (hdmi_data_422), + .hdmi_tpm_oos(hdmi_tpm_oos)); + +endmodule diff --git a/adi_library/axi_hdmi_rx/axi_hdmi_rx_es.v b/adi_library/axi_hdmi_rx/axi_hdmi_rx_es.v new file mode 100644 index 00000000..8de1ad25 --- /dev/null +++ b/adi_library/axi_hdmi_rx/axi_hdmi_rx_es.v @@ -0,0 +1,133 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// Receive HDMI, hdmi embedded syncs data in, video dma data out. + +`timescale 1ns/100ps + +module axi_hdmi_rx_es #( + + parameter DATA_WIDTH = 32 +) ( + + // hdmi interface + + input hdmi_clk, + input [(DATA_WIDTH-1):0] hdmi_data, + output reg hdmi_vs_de, + output reg hdmi_hs_de, + output reg [(DATA_WIDTH-1):0] hdmi_data_de +); + + localparam BYTE_WIDTH = DATA_WIDTH/8; + + // internal registers + + reg [(DATA_WIDTH-1):0] hdmi_data_d = 'd0; + reg hdmi_hs_de_rcv_d = 'd0; + reg hdmi_vs_de_rcv_d = 'd0; + reg [(DATA_WIDTH-1):0] hdmi_data_2d = 'd0; + reg hdmi_hs_de_rcv_2d = 'd0; + reg hdmi_vs_de_rcv_2d = 'd0; + reg [(DATA_WIDTH-1):0] hdmi_data_3d = 'd0; + reg hdmi_hs_de_rcv_3d = 'd0; + reg hdmi_vs_de_rcv_3d = 'd0; + reg [(DATA_WIDTH-1):0] hdmi_data_4d = 'd0; + reg hdmi_hs_de_rcv_4d = 'd0; + reg hdmi_vs_de_rcv_4d = 'd0; + reg [ 1:0] hdmi_preamble_cnt = 'd0; + reg hdmi_hs_de_rcv = 'd0; + reg hdmi_vs_de_rcv = 'd0; + + // internal signals + + wire [(DATA_WIDTH-1):0] hdmi_ff_s; + wire [(DATA_WIDTH-1):0] hdmi_00_s; + wire [(DATA_WIDTH-1):0] hdmi_b6_s; + wire [(DATA_WIDTH-1):0] hdmi_9d_s; + wire [(DATA_WIDTH-1):0] hdmi_ab_s; + wire [(DATA_WIDTH-1):0] hdmi_80_s; + + // es constants + + assign hdmi_ff_s = {BYTE_WIDTH{8'hff}}; + assign hdmi_00_s = {BYTE_WIDTH{8'h00}}; + assign hdmi_b6_s = {BYTE_WIDTH{8'hb6}}; + assign hdmi_9d_s = {BYTE_WIDTH{8'h9d}}; + assign hdmi_ab_s = {BYTE_WIDTH{8'hab}}; + assign hdmi_80_s = {BYTE_WIDTH{8'h80}}; + + // delay to get rid of eav's 4 bytes + + always @(posedge hdmi_clk) begin + hdmi_data_d <= hdmi_data; + hdmi_hs_de_rcv_d <= hdmi_hs_de_rcv; + hdmi_vs_de_rcv_d <= hdmi_vs_de_rcv; + hdmi_data_2d <= hdmi_data_d; + hdmi_hs_de_rcv_2d <= hdmi_hs_de_rcv_d; + hdmi_vs_de_rcv_2d <= hdmi_vs_de_rcv_d; + hdmi_data_3d <= hdmi_data_2d; + hdmi_hs_de_rcv_3d <= hdmi_hs_de_rcv_2d; + hdmi_vs_de_rcv_3d <= hdmi_vs_de_rcv_2d; + hdmi_data_4d <= hdmi_data_3d; + hdmi_hs_de_rcv_4d <= hdmi_hs_de_rcv_3d; + hdmi_vs_de_rcv_4d <= hdmi_vs_de_rcv_3d; + hdmi_data_de <= hdmi_data_4d; + hdmi_hs_de <= hdmi_hs_de_rcv & hdmi_hs_de_rcv_4d; + hdmi_vs_de <= hdmi_vs_de_rcv & hdmi_vs_de_rcv_4d; + end + + // check for sav and eav and generate the corresponding enables + + always @(posedge hdmi_clk) begin + if ((hdmi_data == hdmi_ff_s) || (hdmi_data == hdmi_00_s)) begin + hdmi_preamble_cnt <= hdmi_preamble_cnt + 1'b1; + end else begin + hdmi_preamble_cnt <= 'd0; + end + if (hdmi_preamble_cnt == 3'b11) begin + if ((hdmi_data == hdmi_b6_s) || (hdmi_data == hdmi_9d_s)) begin + hdmi_hs_de_rcv <= 1'b0; + end else if ((hdmi_data == hdmi_ab_s) || (hdmi_data == hdmi_80_s)) begin + hdmi_hs_de_rcv <= 1'b1; + end + if (hdmi_data == hdmi_b6_s) begin + hdmi_vs_de_rcv <= 1'b0; + end else if (hdmi_data == hdmi_9d_s) begin + hdmi_vs_de_rcv <= 1'b1; + end + end + end + +endmodule diff --git a/adi_library/axi_hdmi_rx/axi_hdmi_rx_ip.tcl b/adi_library/axi_hdmi_rx/axi_hdmi_rx_ip.tcl new file mode 100644 index 00000000..6fd3a71c --- /dev/null +++ b/adi_library/axi_hdmi_rx/axi_hdmi_rx_ip.tcl @@ -0,0 +1,38 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +#ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_hdmi_rx +adi_ip_files axi_hdmi_rx [list \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/ad_csc.v" \ + "$ad_hdl_dir/library/common/ad_ss_422to444.v" \ + "$ad_hdl_dir/library/common/ad_csc_CrYCb2RGB.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_hdmi_rx.v" \ + "axi_hdmi_rx.v" \ + "axi_hdmi_rx_es.v" \ + "axi_hdmi_rx_tpm.v" \ + "axi_hdmi_rx_core.v" ] + +adi_ip_properties axi_hdmi_rx + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_hdmi_rx} [ipx::current_core] + +ipx::infer_bus_interface hdmi_rx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface hdmi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/axi_hdmi_rx/axi_hdmi_rx_tpm.v b/adi_library/axi_hdmi_rx/axi_hdmi_rx_tpm.v new file mode 100644 index 00000000..7774c885 --- /dev/null +++ b/adi_library/axi_hdmi_rx/axi_hdmi_rx_tpm.v @@ -0,0 +1,83 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_hdmi_rx_tpm ( + input hdmi_clk, + input hdmi_sof, + input hdmi_de, + input [15:0] hdmi_data, + + output reg hdmi_tpm_oos +); + + wire [15:0] hdmi_tpm_lr_data_s; + wire hdmi_tpm_lr_mismatch_s; + wire [15:0] hdmi_tpm_fr_data_s; + wire hdmi_tpm_fr_mismatch_s; + + reg [15:0] hdmi_tpm_data = 'd0; + reg hdmi_tpm_lr_mismatch = 'd0; + reg hdmi_tpm_fr_mismatch = 'd0; + + // Limited range + assign hdmi_tpm_lr_data_s[15:8] = (hdmi_tpm_data[15:8] < 8'h10) ? 8'h10 : + ((hdmi_tpm_data[15:8] > 8'heb) ? 8'heb : hdmi_tpm_data[15:8]); + assign hdmi_tpm_lr_data_s[ 7:0] = (hdmi_tpm_data[ 7:0] < 8'h10) ? 8'h10 : + ((hdmi_tpm_data[ 7:0] > 8'heb) ? 8'heb : hdmi_tpm_data[ 7:0]); + assign hdmi_tpm_lr_mismatch_s = (hdmi_tpm_lr_data_s == hdmi_data) ? 1'b0 : 1'b1; + + // Full range + assign hdmi_tpm_fr_data_s[15:8] = (hdmi_tpm_data[15:8] < 8'h01) ? 8'h01 : + ((hdmi_tpm_data[15:8] > 8'hfe) ? 8'hfe : hdmi_tpm_data[15:8]); + assign hdmi_tpm_fr_data_s[ 7:0] = (hdmi_tpm_data[ 7:0] < 8'h01) ? 8'h01 : + ((hdmi_tpm_data[ 7:0] > 8'hfe) ? 8'hfe : hdmi_tpm_data[ 7:0]); + assign hdmi_tpm_fr_mismatch_s = (hdmi_tpm_fr_data_s == hdmi_data) ? 1'b0 : 1'b1; + + always @(posedge hdmi_clk) begin + if (hdmi_sof == 1'b1) begin + hdmi_tpm_data <= 16'd0; + hdmi_tpm_lr_mismatch <= 1'd0; + hdmi_tpm_fr_mismatch <= 1'd0; + hdmi_tpm_oos <= hdmi_tpm_lr_mismatch & hdmi_tpm_fr_mismatch; + end else if (hdmi_de == 1'b1) begin + hdmi_tpm_data <= hdmi_tpm_data + 1'b1; + hdmi_tpm_lr_mismatch <= hdmi_tpm_lr_mismatch | hdmi_tpm_lr_mismatch_s; + hdmi_tpm_fr_mismatch <= hdmi_tpm_fr_mismatch | hdmi_tpm_fr_mismatch_s; + end + end + +endmodule diff --git a/adi_library/axi_hdmi_rx/component.xml b/adi_library/axi_hdmi_rx/component.xml new file mode 100644 index 00000000..8b6f964a --- /dev/null +++ b/adi_library/axi_hdmi_rx/component.xml @@ -0,0 +1,993 @@ + + + analog.com + user + axi_hdmi_rx + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + hdmi_rx_clk + + + + + + + CLK + + + hdmi_rx_clk + + + + + + hdmi_clk + + + + + + + CLK + + + hdmi_clk + + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_hdmi_rx + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 0b5ab183 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_hdmi_rx + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + e96ea91a + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 5d051268 + + + + + + + hdmi_rx_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + hdmi_rx_data + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + hdmi_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + hdmi_dma_sof + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + hdmi_dma_de + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + hdmi_dma_data + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + hdmi_dma_ovf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + hdmi_dma_unf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + IO_INTERFACE + Io Interface + 1 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../xilinx/common/up_clock_mon_constr.xdc + xdc + + + ../common/ad_csc.v + verilogSource + + + ../common/ad_csc_CrYCb2RGB.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../common/ad_ss_422to444.v + verilogSource + + + axi_hdmi_rx_core.v + verilogSource + + + axi_hdmi_rx_es.v + verilogSource + + + axi_hdmi_rx_tpm.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_hdmi_rx.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_hdmi_rx.v + verilogSource + CHECKSUM_2587e0a1 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_csc.v + verilogSource + + + ../common/ad_csc_CrYCb2RGB.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../common/ad_ss_422to444.v + verilogSource + + + axi_hdmi_rx_core.v + verilogSource + + + axi_hdmi_rx_es.v + verilogSource + + + axi_hdmi_rx_tpm.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_hdmi_rx.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_hdmi_rx.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_hdmi_rx_v1_0.tcl + tclSource + CHECKSUM_5d051268 + XGUI_VERSION_2 + + + + axi_hdmi_rx_v1_0 + + + ID + Id + 0 + + + IO_INTERFACE + Io Interface + 1 + + + Component_Name + axi_hdmi_rx_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_hdmi_rx_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_hdmi_rx + 1 + 2024-01-14T03:47:06Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_hdmi_rx/xgui/axi_hdmi_rx_v1_0.tcl b/adi_library/axi_hdmi_rx/xgui/axi_hdmi_rx_v1_0.tcl new file mode 100644 index 00000000..07bc3908 --- /dev/null +++ b/adi_library/axi_hdmi_rx/xgui/axi_hdmi_rx_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "IO_INTERFACE" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.IO_INTERFACE { PARAM_VALUE.IO_INTERFACE } { + # Procedure called to update IO_INTERFACE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IO_INTERFACE { PARAM_VALUE.IO_INTERFACE } { + # Procedure called to validate IO_INTERFACE + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.IO_INTERFACE { MODELPARAM_VALUE.IO_INTERFACE PARAM_VALUE.IO_INTERFACE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IO_INTERFACE}] ${MODELPARAM_VALUE.IO_INTERFACE} +} + diff --git a/adi_library/axi_hdmi_tx/Makefile b/adi_library/axi_hdmi_tx/Makefile new file mode 100644 index 00000000..c4f71c9c --- /dev/null +++ b/adi_library/axi_hdmi_tx/Makefile @@ -0,0 +1,41 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_hdmi_tx + +GENERIC_DEPS += ../common/ad_csc.v +GENERIC_DEPS += ../common/ad_csc_RGB2CrYCb.v +GENERIC_DEPS += ../common/ad_mem.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/ad_ss_444to422.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_hdmi_tx.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_hdmi_tx.v +GENERIC_DEPS += axi_hdmi_tx_core.v +GENERIC_DEPS += axi_hdmi_tx_es.v +GENERIC_DEPS += axi_hdmi_tx_vdma.v + +XILINX_DEPS += ../xilinx/common/ad_mul.v +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_hdmi_tx_constr.xdc +XILINX_DEPS += axi_hdmi_tx_ip.tcl + +INTEL_DEPS += ../../library/scripts/adi_intel_device_info_enc.tcl +INTEL_DEPS += ../intel/common/ad_mul.v +INTEL_DEPS += ../intel/common/up_clock_mon_constr.sdc +INTEL_DEPS += ../intel/common/up_rst_constr.sdc +INTEL_DEPS += ../intel/common/up_xfer_cntrl_constr.sdc +INTEL_DEPS += ../intel/common/up_xfer_status_constr.sdc +INTEL_DEPS += axi_hdmi_tx_constr.sdc +INTEL_DEPS += axi_hdmi_tx_hw.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_hdmi_tx/axi_hdmi_tx.v b/adi_library/axi_hdmi_tx/axi_hdmi_tx.v new file mode 100644 index 00000000..55b60265 --- /dev/null +++ b/adi_library/axi_hdmi_tx/axi_hdmi_tx.v @@ -0,0 +1,364 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_hdmi_tx #( + + parameter ID = 0, + parameter CR_CB_N = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter INTERFACE = "16_BIT", + parameter OUT_CLK_POLARITY = 0 +) ( + + // hdmi interface + + input reference_clk, + output hdmi_out_clk, + output vga_out_clk, + + // 16-bit interface + + output hdmi_16_hsync, + output hdmi_16_vsync, + output hdmi_16_data_e, + output [15:0] hdmi_16_data, + output [15:0] hdmi_16_es_data, + + // 24-bit interface + + output hdmi_24_hsync, + output hdmi_24_vsync, + output hdmi_24_data_e, + output [23:0] hdmi_24_data, + + // VGA interface + + output vga_hsync, + output vga_vsync, + output [7:0] vga_red, + output [7:0] vga_green, + output [7:0] vga_blue, + + // 36-bit interface + + output hdmi_36_hsync, + output hdmi_36_vsync, + output hdmi_36_data_e, + output [35:0] hdmi_36_data, + + // vdma interface + + input vdma_clk, + input vdma_end_of_frame, + input vdma_valid, + input [63:0] vdma_data, + output vdma_ready, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready +); + + /* 0 = Launch on rising edge, 1 = Launch on falling edge */ + + localparam EMBEDDED_SYNC = (INTERFACE == "16_BIT_EMBEDDED_SYNC") ? 1 : 0; + localparam XILINX_7SERIES = 1; + localparam XILINX_ULTRASCALE = 2; + localparam XILINX_ULTRASCALE_PLUS = 3; + localparam INTEL_5SERIES = 101; + + // reset and clocks + + wire up_rstn; + wire up_clk; + wire reference_rst; + wire vdma_rst; + + // internal signals + + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire up_wack_s; + wire up_rreq_s; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_s; + wire up_rack_s; + wire hdmi_csc_bypass_s; + wire hdmi_ss_bypass_s; + wire [ 1:0] hdmi_srcsel_s; + wire [23:0] hdmi_const_rgb_s; + wire [15:0] hdmi_hl_active_s; + wire [15:0] hdmi_hl_width_s; + wire [15:0] hdmi_hs_width_s; + wire [15:0] hdmi_he_max_s; + wire [15:0] hdmi_he_min_s; + wire [15:0] hdmi_vf_active_s; + wire [15:0] hdmi_vf_width_s; + wire [15:0] hdmi_vs_width_s; + wire [15:0] hdmi_ve_max_s; + wire [15:0] hdmi_ve_min_s; + wire [23:0] hdmi_clip_max_s; + wire [23:0] hdmi_clip_min_s; + wire hdmi_fs_toggle_s; + wire [ 8:0] hdmi_raddr_g_s; + wire hdmi_tpm_oos_s; + wire hdmi_status_s; + wire vdma_wr_s; + wire [ 8:0] vdma_waddr_s; + wire [47:0] vdma_wdata_s; + wire vdma_fs_ret_toggle_s; + wire [ 8:0] vdma_fs_waddr_s; + wire vdma_ovf_s; + wire vdma_unf_s; + wire vdma_tpm_oos_s; + + // signal name changes + + assign up_rstn = s_axi_aresetn; + assign up_clk = s_axi_aclk; + assign vga_out_clk = hdmi_out_clk; + + // axi interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + + // processor interface + + up_hdmi_tx i_up ( + .hdmi_clk (reference_clk), + .hdmi_rst (reference_rst), + .hdmi_csc_bypass (hdmi_csc_bypass_s), + .hdmi_ss_bypass (hdmi_ss_bypass_s), + .hdmi_srcsel (hdmi_srcsel_s), + .hdmi_const_rgb (hdmi_const_rgb_s), + .hdmi_hl_active (hdmi_hl_active_s), + .hdmi_hl_width (hdmi_hl_width_s), + .hdmi_hs_width (hdmi_hs_width_s), + .hdmi_he_max (hdmi_he_max_s), + .hdmi_he_min (hdmi_he_min_s), + .hdmi_vf_active (hdmi_vf_active_s), + .hdmi_vf_width (hdmi_vf_width_s), + .hdmi_vs_width (hdmi_vs_width_s), + .hdmi_ve_max (hdmi_ve_max_s), + .hdmi_ve_min (hdmi_ve_min_s), + .hdmi_clip_max (hdmi_clip_max_s), + .hdmi_clip_min (hdmi_clip_min_s), + .hdmi_status (hdmi_status_s), + .hdmi_tpm_oos (hdmi_tpm_oos_s), + .hdmi_clk_ratio (32'd1), + .vdma_clk (vdma_clk), + .vdma_rst (vdma_rst), + .vdma_ovf (vdma_ovf_s), + .vdma_unf (vdma_unf_s), + .vdma_tpm_oos (vdma_tpm_oos_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + + // vdma interface + + axi_hdmi_tx_vdma i_vdma ( + .hdmi_fs_toggle (hdmi_fs_toggle_s), + .hdmi_raddr_g (hdmi_raddr_g_s), + .vdma_clk (vdma_clk), + .vdma_rst (vdma_rst), + .vdma_valid (vdma_valid), + .vdma_data (vdma_data), + .vdma_ready (vdma_ready), + .vdma_end_of_frame (vdma_end_of_frame), + .vdma_wr (vdma_wr_s), + .vdma_waddr (vdma_waddr_s), + .vdma_wdata (vdma_wdata_s), + .vdma_fs_ret_toggle (vdma_fs_ret_toggle_s), + .vdma_fs_waddr (vdma_fs_waddr_s), + .vdma_tpm_oos (vdma_tpm_oos_s), + .vdma_ovf (vdma_ovf_s), + .vdma_unf (vdma_unf_s)); + + // hdmi interface + + axi_hdmi_tx_core #( + .INTERFACE(INTERFACE), + .CR_CB_N(CR_CB_N), + .EMBEDDED_SYNC(EMBEDDED_SYNC) + ) i_tx_core ( + .reference_clk (reference_clk), + .reference_rst (reference_rst), + .hdmi_16_hsync (hdmi_16_hsync), + .hdmi_16_vsync (hdmi_16_vsync), + .hdmi_16_data_e (hdmi_16_data_e), + .hdmi_16_data (hdmi_16_data), + .hdmi_16_es_data (hdmi_16_es_data), + .hdmi_24_hsync (hdmi_24_hsync), + .hdmi_24_vsync (hdmi_24_vsync), + .hdmi_24_data_e (hdmi_24_data_e), + .hdmi_24_data (hdmi_24_data), + .vga_hsync(vga_hsync), + .vga_vsync(vga_vsync), + .vga_red(vga_red), + .vga_green(vga_green), + .vga_blue(vga_blue), + .hdmi_36_hsync (hdmi_36_hsync), + .hdmi_36_vsync (hdmi_36_vsync), + .hdmi_36_data_e (hdmi_36_data_e), + .hdmi_36_data (hdmi_36_data), + .hdmi_fs_toggle (hdmi_fs_toggle_s), + .hdmi_raddr_g (hdmi_raddr_g_s), + .hdmi_tpm_oos (hdmi_tpm_oos_s), + .hdmi_status (hdmi_status_s), + .vdma_clk (vdma_clk), + .vdma_wr (vdma_wr_s), + .vdma_waddr (vdma_waddr_s), + .vdma_wdata (vdma_wdata_s), + .vdma_fs_ret_toggle (vdma_fs_ret_toggle_s), + .vdma_fs_waddr (vdma_fs_waddr_s), + .hdmi_csc_bypass (hdmi_csc_bypass_s), + .hdmi_ss_bypass (hdmi_ss_bypass_s), + .hdmi_srcsel (hdmi_srcsel_s), + .hdmi_const_rgb (hdmi_const_rgb_s), + .hdmi_hl_active (hdmi_hl_active_s), + .hdmi_hl_width (hdmi_hl_width_s), + .hdmi_hs_width (hdmi_hs_width_s), + .hdmi_he_max (hdmi_he_max_s), + .hdmi_he_min (hdmi_he_min_s), + .hdmi_vf_active (hdmi_vf_active_s), + .hdmi_vf_width (hdmi_vf_width_s), + .hdmi_vs_width (hdmi_vs_width_s), + .hdmi_ve_max (hdmi_ve_max_s), + .hdmi_ve_min (hdmi_ve_min_s), + .hdmi_clip_max (hdmi_clip_max_s), + .hdmi_clip_min (hdmi_clip_min_s)); + + // hdmi output clock + + generate + if (FPGA_TECHNOLOGY == XILINX_ULTRASCALE || FPGA_TECHNOLOGY == XILINX_ULTRASCALE_PLUS) begin + ODDRE1 #( + .SRVAL(1'b0) + ) i_clk_oddr ( + .SR (1'b0), + .D1 (~OUT_CLK_POLARITY), + .D2 (OUT_CLK_POLARITY), + .C (reference_clk), + .Q (hdmi_out_clk)); + end + if (FPGA_TECHNOLOGY == INTEL_5SERIES) begin + altddio_out #( + .WIDTH(1) + ) i_clk_oddr ( + .aclr (1'b0), + .aset (1'b0), + .sclr (1'b0), + .sset (1'b0), + .oe (1'b1), + .outclocken (1'b1), + .datain_h (~OUT_CLK_POLARITY), + .datain_l (OUT_CLK_POLARITY), + .outclock (reference_clk), + .oe_out (), + .dataout (hdmi_out_clk)); + end + if (FPGA_TECHNOLOGY == XILINX_7SERIES) begin + ODDR #( + .INIT(1'b0) + ) i_clk_oddr ( + .R (1'b0), + .S (1'b0), + .CE (1'b1), + .D1 (~OUT_CLK_POLARITY), + .D2 (OUT_CLK_POLARITY), + .C (reference_clk), + .Q (hdmi_out_clk)); + end + endgenerate + +endmodule diff --git a/adi_library/axi_hdmi_tx/axi_hdmi_tx.xpr b/adi_library/axi_hdmi_tx/axi_hdmi_tx.xpr new file mode 100644 index 00000000..2683c9cd --- /dev/null +++ b/adi_library/axi_hdmi_tx/axi_hdmi_tx.xpr @@ -0,0 +1,535 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_hdmi_tx/axi_hdmi_tx_constr.sdc b/adi_library/axi_hdmi_tx/axi_hdmi_tx_constr.sdc new file mode 100644 index 00000000..81d58953 --- /dev/null +++ b/adi_library/axi_hdmi_tx/axi_hdmi_tx_constr.sdc @@ -0,0 +1,13 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_false_path -from [get_registers *hdmi_fs_toggle*] -to [get_registers *vdma_fs_toggle_m1] +set_false_path -from [get_registers *hdmi_raddr_g*] -to [get_registers *vdma_raddr_g_m1*] +set_false_path -from [get_registers *vdma_fs_ret_toggle*] -to [get_registers *hdmi_fs_ret_toggle_m1] +set_false_path -from [get_registers *vdma_fs_waddr*] -to [get_registers *hdmi_fs_waddr*] + +set_false_path -from [get_registers *up_xfer_status:i_vdma_xfer_status|up_xfer_toggle*] -to [get_registers *up_xfer_status:i_vdma_xfer_status|d_xfer_state_m1*] +set_false_path -from [get_registers *up_xfer_status:i_vdma_xfer_status|d_xfer_toggle*] -to [get_registers *up_xfer_status:i_vdma_xfer_status|up_xfer_toggle_m1*] +set_false_path -from [get_registers *up_xfer_status:i_vdma_xfer_status|d_xfer_data*] -to [get_registers *up_xfer_status:i_vdma_xfer_status|up_data_status*] diff --git a/adi_library/axi_hdmi_tx/axi_hdmi_tx_constr.xdc b/adi_library/axi_hdmi_tx/axi_hdmi_tx_constr.xdc new file mode 100644 index 00000000..572f7a93 --- /dev/null +++ b/adi_library/axi_hdmi_tx/axi_hdmi_tx_constr.xdc @@ -0,0 +1,14 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *vdma_fs_toggle*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *vdma_raddr_g*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *hdmi_fs_ret_toggle*}] + +set_false_path -from [get_cells -hier -filter {name =~ *hdmi_fs_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *vdma_fs_toggle_m1_reg && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *hdmi_raddr_g* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *vdma_raddr_g_m1* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *vdma_fs_ret_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *hdmi_fs_ret_toggle_m1_reg && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *vdma_fs_waddr* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *hdmi_fs_waddr* && IS_SEQUENTIAL}] + diff --git a/adi_library/axi_hdmi_tx/axi_hdmi_tx_core.v b/adi_library/axi_hdmi_tx/axi_hdmi_tx_core.v new file mode 100644 index 00000000..ccbe3c8d --- /dev/null +++ b/adi_library/axi_hdmi_tx/axi_hdmi_tx_core.v @@ -0,0 +1,596 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// Transmit HDMI, video dma data in, hdmi separate syncs data out. + +`timescale 1ns/100ps + +module axi_hdmi_tx_core #( + + parameter CR_CB_N = 0, + parameter EMBEDDED_SYNC = 0, + parameter INTERFACE = "16_BIT" +) ( + + // hdmi interface + + input reference_clk, + input reference_rst, + + // 16-bit interface + + output reg hdmi_16_hsync, + output reg hdmi_16_vsync, + output reg hdmi_16_data_e, + output reg [15:0] hdmi_16_data, + output reg [15:0] hdmi_16_es_data, + + // 24-bit interface + + output reg hdmi_24_hsync, + output reg hdmi_24_vsync, + output reg hdmi_24_data_e, + output reg [23:0] hdmi_24_data, + + // VGA interface + + output reg vga_hsync, + output reg vga_vsync, + output reg [7:0] vga_red, + output reg [7:0] vga_green, + output reg [7:0] vga_blue, + + // 36-bit interface + + output reg hdmi_36_hsync, + output reg hdmi_36_vsync, + output reg hdmi_36_data_e, + output reg [35:0] hdmi_36_data, + + // control signals + + output reg hdmi_fs_toggle, + output reg [ 8:0] hdmi_raddr_g, + output reg hdmi_tpm_oos, + output reg hdmi_status, + + // vdma interface + + input vdma_clk, + input vdma_wr, + input [ 8:0] vdma_waddr, + input [47:0] vdma_wdata, + input vdma_fs_ret_toggle, + input [ 8:0] vdma_fs_waddr, + + // processor interface + + input hdmi_csc_bypass, + input hdmi_ss_bypass, + input [ 1:0] hdmi_srcsel, + input [23:0] hdmi_const_rgb, + input [15:0] hdmi_hl_active, + input [15:0] hdmi_hl_width, + input [15:0] hdmi_hs_width, + input [15:0] hdmi_he_max, + input [15:0] hdmi_he_min, + input [15:0] hdmi_vf_active, + input [15:0] hdmi_vf_width, + input [15:0] hdmi_vs_width, + input [15:0] hdmi_ve_max, + input [15:0] hdmi_ve_min, + input [23:0] hdmi_clip_max, + input [23:0] hdmi_clip_min +); + + // internal registers + + reg hdmi_enable = 'd0; + reg [15:0] hdmi_hs_count = 'd0; + reg [15:0] hdmi_vs_count = 'd0; + reg hdmi_fs = 'd0; + reg hdmi_fs_ret_toggle_m1 = 'd0; + reg hdmi_fs_ret_toggle_m2 = 'd0; + reg hdmi_fs_ret_toggle_m3 = 'd0; + reg hdmi_fs_ret = 'd0; + reg [ 8:0] hdmi_fs_waddr = 'd0; + reg hdmi_hs = 'd0; + reg hdmi_vs = 'd0; + reg hdmi_hs_de = 'd0; + reg hdmi_vs_de = 'd0; + reg [ 9:0] hdmi_raddr = 'd0; + reg hdmi_hs_d = 'd0; + reg hdmi_vs_d = 'd0; + reg hdmi_hs_de_d = 'd0; + reg hdmi_vs_de_d = 'd0; + reg hdmi_de_d = 'd0; + reg hdmi_data_sel_d = 'd0; + reg hdmi_hs_2d = 'd0; + reg hdmi_vs_2d = 'd0; + reg hdmi_hs_de_2d = 'd0; + reg hdmi_vs_de_2d = 'd0; + reg hdmi_de_2d = 'd0; + reg hdmi_data_sel_2d = 'd0; + reg [47:0] hdmi_data_2d = 'd0; + reg [23:0] hdmi_tpm_data = 'd0; + reg hdmi_hsync = 'd0; + reg hdmi_vsync = 'd0; + reg hdmi_hsync_data_e = 'd0; + reg hdmi_vsync_data_e = 'd0; + reg hdmi_data_e = 'd0; + reg [23:0] hdmi_data = 'd0; + reg hdmi_24_csc_hsync = 'd0; + reg hdmi_24_csc_vsync = 'd0; + reg hdmi_24_csc_hsync_data_e = 'd0; + reg hdmi_24_csc_vsync_data_e = 'd0; + reg hdmi_24_csc_data_e = 'd0; + reg [23:0] hdmi_24_csc_data = 'd0; + reg hdmi_16_hsync_d = 'd0; + reg hdmi_16_vsync_d = 'd0; + reg hdmi_16_hsync_data_e_d = 'd0; + reg hdmi_16_vsync_data_e_d = 'd0; + reg hdmi_16_data_e_d = 'd0; + reg [15:0] hdmi_16_data_d = 'd0; + reg hdmi_es_hs_de = 'd0; + reg hdmi_es_vs_de = 'd0; + reg [15:0] hdmi_es_data = 'd0; + reg [23:0] hdmi_clip_data = 'd0; + reg hdmi_clip_hs_de_d = 'd0; + reg hdmi_clip_vs_de_d = 'd0; + reg hdmi_clip_hs_d = 'd0; + reg hdmi_clip_vs_d = 'd0; + reg hdmi_clip_de_d = 'd0; + + // internal wires + + wire [15:0] hdmi_hl_width_s; + wire [15:0] hdmi_vf_width_s; + wire [15:0] hdmi_he_width_s; + wire [15:0] hdmi_ve_width_s; + wire hdmi_fs_ret_s; + wire hdmi_de_s; + wire [47:0] hdmi_rdata_s; + wire [23:0] hdmi_data_2d_s; + wire hdmi_tpm_mismatch_s; + wire [23:0] hdmi_tpg_data_s; + wire hdmi_csc_hsync_s; + wire hdmi_csc_vsync_s; + wire hdmi_csc_hsync_data_e_s; + wire hdmi_csc_vsync_data_e_s; + wire hdmi_csc_data_e_s; + wire [23:0] hdmi_csc_data_s; + wire hdmi_ss_hsync_s; + wire hdmi_ss_vsync_s; + wire hdmi_ss_hsync_data_e_s; + wire hdmi_ss_vsync_data_e_s; + wire hdmi_ss_data_e_s; + wire [15:0] hdmi_ss_data_s; + wire [15:0] hdmi_es_data_s; + + // binary to grey conversion + + function [8:0] b2g; + input [8:0] b; + reg [8:0] g; + begin + g[8] = b[8]; + g[7] = b[8] ^ b[7]; + g[6] = b[7] ^ b[6]; + g[5] = b[6] ^ b[5]; + g[4] = b[5] ^ b[4]; + g[3] = b[4] ^ b[3]; + g[2] = b[3] ^ b[2]; + g[1] = b[2] ^ b[1]; + g[0] = b[1] ^ b[0]; + b2g = g; + end + endfunction + + // status and enable + + always @(posedge reference_clk) begin + if (reference_rst == 1'b1) begin + hdmi_status <= 1'b0; + hdmi_enable <= 1'b0; + end else begin + hdmi_status <= 1'b1; + hdmi_enable <= hdmi_srcsel[1] | hdmi_srcsel[0]; + end + end + + // calculate useful limits + + assign hdmi_hl_width_s = hdmi_hl_width - 1'b1; + assign hdmi_vf_width_s = hdmi_vf_width - 1'b1; + assign hdmi_he_width_s = hdmi_hl_width - (hdmi_hl_active + 1'b1); + assign hdmi_ve_width_s = hdmi_vf_width - (hdmi_vf_active + 1'b1); + + // hdmi counters + + always @(posedge reference_clk) begin + if (hdmi_hs_count >= hdmi_hl_width_s) begin + hdmi_hs_count <= 0; + end else begin + hdmi_hs_count <= hdmi_hs_count + 1'b1; + end + if (hdmi_hs_count >= hdmi_hl_width_s) begin + if (hdmi_vs_count >= hdmi_vf_width_s) begin + hdmi_vs_count <= 0; + end else begin + hdmi_vs_count <= hdmi_vs_count + 1'b1; + end + end + end + + // hdmi start of frame + + always @(posedge reference_clk) begin + if (reference_rst == 1'b1) begin + hdmi_fs_toggle <= 1'b0; + hdmi_fs <= 1'b0; + end else begin + if (EMBEDDED_SYNC == 1) begin + if ((hdmi_hs_count == 1) && (hdmi_vs_count == hdmi_ve_width_s)) begin + hdmi_fs <= hdmi_enable; + end else begin + hdmi_fs <= 1'b0; + end + end else begin + if ((hdmi_hs_count == 1) && (hdmi_vs_count == hdmi_vs_width)) begin + hdmi_fs <= hdmi_enable; + end else begin + hdmi_fs <= 1'b0; + end + end + if (hdmi_fs == 1'b1) begin + hdmi_fs_toggle <= ~hdmi_fs_toggle; + end + end + end + + // hdmi sof write address + + assign hdmi_fs_ret_s = hdmi_fs_ret_toggle_m2 ^ hdmi_fs_ret_toggle_m3; + + always @(posedge reference_clk or posedge reference_rst) begin + if (reference_rst == 1'b1) begin + hdmi_fs_ret_toggle_m1 <= 1'd0; + hdmi_fs_ret_toggle_m2 <= 1'd0; + hdmi_fs_ret_toggle_m3 <= 1'd0; + end else begin + hdmi_fs_ret_toggle_m1 <= vdma_fs_ret_toggle; + hdmi_fs_ret_toggle_m2 <= hdmi_fs_ret_toggle_m1; + hdmi_fs_ret_toggle_m3 <= hdmi_fs_ret_toggle_m2; + end + end + + always @(posedge reference_clk) begin + hdmi_fs_ret <= hdmi_fs_ret_s; + hdmi_fs_waddr <= vdma_fs_waddr; + end + + // hdmi sync signals + + always @(posedge reference_clk) begin + if (EMBEDDED_SYNC == 1) begin + hdmi_hs <= 1'b0; + if (hdmi_hs_count <= hdmi_he_width_s) begin + hdmi_hs_de <= 1'b0; + end else begin + hdmi_hs_de <= hdmi_enable; + end + if (hdmi_vs_count <= hdmi_ve_width_s) begin + hdmi_vs_de <= 1'b0; + end else begin + hdmi_vs_de <= hdmi_enable; + end + end else begin + if (hdmi_hs_count < hdmi_hs_width) begin + hdmi_hs <= hdmi_enable; + end else begin + hdmi_hs <= 1'b0; + end + if (hdmi_vs_count < hdmi_vs_width) begin + hdmi_vs <= hdmi_enable; + end else begin + hdmi_vs <= 1'b0; + end + if ((hdmi_hs_count < hdmi_he_min) || (hdmi_hs_count >= hdmi_he_max)) begin + hdmi_hs_de <= 1'b0; + end else begin + hdmi_hs_de <= hdmi_enable; + end + if ((hdmi_vs_count < hdmi_ve_min) || (hdmi_vs_count >= hdmi_ve_max)) begin + hdmi_vs_de <= 1'b0; + end else begin + hdmi_vs_de <= hdmi_enable; + end + end + end + + // hdmi read data + + assign hdmi_de_s = hdmi_hs_de & hdmi_vs_de; + + always @(posedge reference_clk) begin + if (reference_rst == 1'b1) begin + hdmi_raddr <= 10'd0; + end else if (hdmi_fs == 1'b1) begin + hdmi_raddr <= {hdmi_fs_waddr, 1'b0}; + end else if (hdmi_de_s == 1'b1) begin + hdmi_raddr <= hdmi_raddr + 1'b1; + end + hdmi_raddr_g <= b2g(hdmi_raddr[9:1]); + end + + // control and data pipe line + + always @(posedge reference_clk) begin + hdmi_hs_d <= hdmi_hs; + hdmi_vs_d <= hdmi_vs; + hdmi_hs_de_d <= hdmi_hs_de; + hdmi_vs_de_d <= hdmi_vs_de; + hdmi_de_d <= hdmi_de_s; + hdmi_data_sel_d <= hdmi_raddr[0]; + hdmi_hs_2d <= hdmi_hs_d; + hdmi_vs_2d <= hdmi_vs_d; + hdmi_hs_de_2d <= hdmi_hs_de_d; + hdmi_vs_de_2d <= hdmi_vs_de_d; + hdmi_de_2d <= hdmi_de_d; + hdmi_data_sel_2d <= hdmi_data_sel_d; + hdmi_data_2d <= hdmi_rdata_s; + end + + // hdmi data count (may be used to monitor or insert) + + assign hdmi_data_2d_s = (hdmi_data_sel_2d == 1'b1) ? hdmi_data_2d[47:24] : hdmi_data_2d[23:0]; + assign hdmi_tpm_mismatch_s = (hdmi_data_2d_s == hdmi_tpm_data) ? 1'b0 : hdmi_de_2d; + assign hdmi_tpg_data_s = hdmi_tpm_data; + + always @(posedge reference_clk) begin + if ((reference_rst == 1'b1) || (hdmi_fs_ret == 1'b1)) begin + hdmi_tpm_data <= 'd0; + end else if (hdmi_de_2d == 1'b1) begin + hdmi_tpm_data <= hdmi_tpm_data + 1'b1; + end + hdmi_tpm_oos <= hdmi_tpm_mismatch_s; + + end + + // hdmi data select + + always @(posedge reference_clk) begin + hdmi_hsync <= hdmi_hs_2d; + hdmi_vsync <= hdmi_vs_2d; + hdmi_hsync_data_e <= hdmi_hs_de_2d; + hdmi_vsync_data_e <= hdmi_vs_de_2d; + hdmi_data_e <= hdmi_de_2d; + case (hdmi_srcsel) + 2'b11: hdmi_data <= hdmi_const_rgb; + 2'b10: hdmi_data <= hdmi_tpg_data_s; + 2'b01: hdmi_data <= hdmi_data_2d_s; + default: hdmi_data <= 24'd0; + endcase + end + + // Color space conversion bypass (RGB/YCbCr) + + always @(posedge reference_clk) begin + if (hdmi_csc_bypass == 1'b1) begin + hdmi_24_csc_hsync <= hdmi_hsync; + hdmi_24_csc_vsync <= hdmi_vsync; + hdmi_24_csc_hsync_data_e <= hdmi_hsync_data_e; + hdmi_24_csc_vsync_data_e <= hdmi_vsync_data_e; + hdmi_24_csc_data_e <= hdmi_data_e; + hdmi_24_csc_data <= hdmi_data; + end else begin + hdmi_24_csc_hsync <= hdmi_csc_hsync_s; + hdmi_24_csc_vsync <= hdmi_csc_vsync_s; + hdmi_24_csc_hsync_data_e <= hdmi_csc_hsync_data_e_s; + hdmi_24_csc_vsync_data_e <= hdmi_csc_vsync_data_e_s; + hdmi_24_csc_data_e <= hdmi_csc_data_e_s; + hdmi_24_csc_data <= hdmi_csc_data_s; + end + end + + // hdmi clipping + + always @(posedge reference_clk) begin + hdmi_clip_hs_d <= hdmi_24_csc_hsync; + hdmi_clip_vs_d <= hdmi_24_csc_vsync; + hdmi_clip_hs_de_d <= hdmi_24_csc_hsync_data_e; + hdmi_clip_vs_de_d <= hdmi_24_csc_vsync_data_e; + hdmi_clip_de_d <= hdmi_24_csc_data_e; + + // Cr (red-diff) / red + + if (hdmi_24_csc_data[23:16] > hdmi_clip_max[23:16]) begin + hdmi_clip_data[23:16] <= hdmi_clip_max[23:16]; + end else if (hdmi_24_csc_data[23:16] < hdmi_clip_min[23:16]) begin + hdmi_clip_data[23:16] <= hdmi_clip_min[23:16]; + end else begin + hdmi_clip_data[23:16] <= hdmi_24_csc_data[23:16]; + end + + // Y (luma) / green + + if (hdmi_24_csc_data[15:8] > hdmi_clip_max[15:8]) begin + hdmi_clip_data[15:8] <= hdmi_clip_max[15:8]; + end else if (hdmi_24_csc_data[15:8] < hdmi_clip_min[15:8]) begin + hdmi_clip_data[15:8] <= hdmi_clip_min[15:8]; + end else begin + hdmi_clip_data[15:8] <= hdmi_24_csc_data[15:8]; + end + + // Cb (blue-diff) / blue + + if (hdmi_24_csc_data[7:0] > hdmi_clip_max[7:0]) begin + hdmi_clip_data[7:0] <= hdmi_clip_max[7:0]; + end else if (hdmi_24_csc_data[7:0] < hdmi_clip_min[7:0]) begin + hdmi_clip_data[7:0] <= hdmi_clip_min[7:0]; + end else begin + hdmi_clip_data[7:0] <= hdmi_24_csc_data[7:0]; + end + end + + // hdmi csc 16, 24 and 36 outputs + + always @(posedge reference_clk) begin + + hdmi_36_hsync <= hdmi_clip_hs_d; + hdmi_36_vsync <= hdmi_clip_vs_d; + hdmi_36_data_e <= hdmi_clip_de_d; + hdmi_36_data[35:24] <= {hdmi_clip_data[23:16], hdmi_clip_data[23:20]}; + hdmi_36_data[23:12] <= {hdmi_clip_data[15: 8], hdmi_clip_data[15:12]}; + hdmi_36_data[11: 0] <= {hdmi_clip_data[ 7: 0], hdmi_clip_data[ 7: 4]}; + + hdmi_24_hsync <= hdmi_clip_hs_d; + hdmi_24_vsync <= hdmi_clip_vs_d; + hdmi_24_data_e <= hdmi_clip_de_d; + hdmi_24_data <= hdmi_clip_data; + + //VGA INTERFACE SIGNALS + vga_hsync <= hdmi_clip_hs_d; + vga_vsync <= hdmi_clip_vs_d; + vga_red <= hdmi_clip_data[23:16]; + vga_green <= hdmi_clip_data[15:8]; + vga_blue <= hdmi_clip_data[7:0]; + + hdmi_16_hsync <= hdmi_16_hsync_d; + hdmi_16_vsync <= hdmi_16_vsync_d; + hdmi_16_data_e <= hdmi_16_data_e_d; + hdmi_16_data <= hdmi_16_data_d; + hdmi_16_es_data <= hdmi_es_data_s; + + if (hdmi_ss_bypass == 1'b1) begin + hdmi_16_hsync_d <= hdmi_clip_hs_d; + hdmi_16_vsync_d <= hdmi_clip_vs_d; + hdmi_16_hsync_data_e_d <= hdmi_clip_hs_de_d; + hdmi_16_vsync_data_e_d <= hdmi_clip_vs_de_d; + hdmi_16_data_e_d <= hdmi_clip_de_d; + hdmi_16_data_d <= hdmi_clip_data[15:0]; // Ignore the upper 8 bit + end else begin + hdmi_16_hsync_d <= hdmi_ss_hsync_s; + hdmi_16_vsync_d <= hdmi_ss_vsync_s; + hdmi_16_hsync_data_e_d <= hdmi_ss_hsync_data_e_s; + hdmi_16_vsync_data_e_d <= hdmi_ss_vsync_data_e_s; + hdmi_16_data_e_d <= hdmi_ss_data_e_s; + hdmi_16_data_d <= hdmi_ss_data_s; + end + end + + // hdmi embedded sync + + always @(posedge reference_clk) begin + hdmi_es_hs_de <= hdmi_16_hsync_data_e_d; + hdmi_es_vs_de <= hdmi_16_vsync_data_e_d; + if (hdmi_16_data_e_d == 1'b0) begin + hdmi_es_data[15:8] <= 8'h80; + end else begin + hdmi_es_data[15:8] <= hdmi_16_data_d[15:8]; + end + if (hdmi_16_data_e_d == 1'b0) begin + hdmi_es_data[7:0] <= 8'h80; + end else begin + hdmi_es_data[7:0] <= hdmi_16_data_d[7:0]; + end + end + + // data memory + + ad_mem #( + .DATA_WIDTH(48), + .ADDRESS_WIDTH(9) + ) i_mem ( + .clka (vdma_clk), + .wea (vdma_wr), + .addra (vdma_waddr), + .dina (vdma_wdata), + .clkb (reference_clk), + .reb (1'b1), + .addrb (hdmi_raddr[9:1]), + .doutb (hdmi_rdata_s)); + + // color space coversion, RGB to CrYCb + + ad_csc_RGB2CrYCb #( + .DELAY_DATA_WIDTH(5) + ) i_csc_RGB2CrYCb ( + .clk (reference_clk), + .RGB_sync ({hdmi_hsync, + hdmi_vsync, + hdmi_hsync_data_e, + hdmi_vsync_data_e, + hdmi_data_e}), + .RGB_data (hdmi_data), + .CrYCb_sync ({hdmi_csc_hsync_s, + hdmi_csc_vsync_s, + hdmi_csc_hsync_data_e_s, + hdmi_csc_vsync_data_e_s, + hdmi_csc_data_e_s}), + .CrYCb_data (hdmi_csc_data_s)); + + // sub sampling, 444 to 422 + + ad_ss_444to422 #( + .DELAY_DATA_WIDTH(5), + .CR_CB_N(CR_CB_N) + ) i_ss_444to422 ( + .clk (reference_clk), + .s444_de (hdmi_clip_de_d), + .s444_sync ({hdmi_clip_hs_d, + hdmi_clip_vs_d, + hdmi_clip_hs_de_d, + hdmi_clip_vs_de_d, + hdmi_clip_de_d}), + .s444_data (hdmi_clip_data), + .s422_sync ({hdmi_ss_hsync_s, + hdmi_ss_vsync_s, + hdmi_ss_hsync_data_e_s, + hdmi_ss_vsync_data_e_s, + hdmi_ss_data_e_s}), + .s422_data (hdmi_ss_data_s)); + + // embedded sync + + axi_hdmi_tx_es #( + .DATA_WIDTH(16) + ) i_es ( + .reference_clk (reference_clk), + .hdmi_hs_de (hdmi_es_hs_de), + .hdmi_vs_de (hdmi_es_vs_de), + .hdmi_data_de (hdmi_es_data), + .hdmi_data (hdmi_es_data_s)); + +endmodule diff --git a/adi_library/axi_hdmi_tx/axi_hdmi_tx_es.v b/adi_library/axi_hdmi_tx/axi_hdmi_tx_es.v new file mode 100644 index 00000000..69e85f4d --- /dev/null +++ b/adi_library/axi_hdmi_tx/axi_hdmi_tx_es.v @@ -0,0 +1,106 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// Transmit HDMI, video dma data in, hdmi separate syncs data out. + +`timescale 1ns/100ps + +module axi_hdmi_tx_es #( + + parameter DATA_WIDTH = 32 +) ( + + // hdmi interface + + input reference_clk, + input hdmi_hs_de, + input hdmi_vs_de, + input [(DATA_WIDTH-1):0] hdmi_data_de, + output reg [(DATA_WIDTH-1):0] hdmi_data +); + + localparam BYTE_WIDTH = DATA_WIDTH/8; + + // internal registers + + reg hdmi_hs_de_d = 'd0; + reg [(DATA_WIDTH-1):0] hdmi_data_d = 'd0; + reg hdmi_hs_de_2d = 'd0; + reg [(DATA_WIDTH-1):0] hdmi_data_2d = 'd0; + reg hdmi_hs_de_3d = 'd0; + reg [(DATA_WIDTH-1):0] hdmi_data_3d = 'd0; + reg hdmi_hs_de_4d = 'd0; + reg [(DATA_WIDTH-1):0] hdmi_data_4d = 'd0; + reg hdmi_hs_de_5d = 'd0; + reg [(DATA_WIDTH-1):0] hdmi_data_5d = 'd0; + + // internal wires + + wire [(DATA_WIDTH-1):0] hdmi_sav_s; + wire [(DATA_WIDTH-1):0] hdmi_eav_s; + + // hdmi embedded sync insertion + + assign hdmi_sav_s = (hdmi_vs_de == 1) ? {BYTE_WIDTH{8'h80}} : {BYTE_WIDTH{8'hab}}; + assign hdmi_eav_s = (hdmi_vs_de == 1) ? {BYTE_WIDTH{8'h9d}} : {BYTE_WIDTH{8'hb6}}; + + always @(posedge reference_clk) begin + hdmi_hs_de_d <= hdmi_hs_de; + case ({hdmi_hs_de_4d, hdmi_hs_de_3d, hdmi_hs_de_2d, + hdmi_hs_de_d, hdmi_hs_de}) + 5'b11000: hdmi_data_d <= {BYTE_WIDTH{8'h00}}; + 5'b11100: hdmi_data_d <= {BYTE_WIDTH{8'h00}}; + 5'b11110: hdmi_data_d <= {BYTE_WIDTH{8'hff}}; + 5'b10000: hdmi_data_d <= hdmi_eav_s; + default: hdmi_data_d <= hdmi_data_de; + endcase + hdmi_hs_de_2d <= hdmi_hs_de_d; + hdmi_data_2d <= hdmi_data_d; + hdmi_hs_de_3d <= hdmi_hs_de_2d; + hdmi_data_3d <= hdmi_data_2d; + hdmi_hs_de_4d <= hdmi_hs_de_3d; + hdmi_data_4d <= hdmi_data_3d; + hdmi_hs_de_5d <= hdmi_hs_de_4d; + hdmi_data_5d <= hdmi_data_4d; + case ({hdmi_hs_de_5d, hdmi_hs_de_4d, hdmi_hs_de_3d, + hdmi_hs_de_2d, hdmi_hs_de_d}) + 5'b00111: hdmi_data <= {BYTE_WIDTH{8'h00}}; + 5'b00011: hdmi_data <= {BYTE_WIDTH{8'h00}}; + 5'b00001: hdmi_data <= {BYTE_WIDTH{8'hff}}; + 5'b01111: hdmi_data <= hdmi_sav_s; + default: hdmi_data <= hdmi_data_5d; + endcase + end + +endmodule diff --git a/adi_library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl b/adi_library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl new file mode 100644 index 00000000..8cd5e7e8 --- /dev/null +++ b/adi_library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl @@ -0,0 +1,145 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +package require quartus::device + +source ../../scripts/adi_env.tcl +source ../scripts/adi_ip_intel.tcl +source $ad_hdl_dir/library/scripts/adi_intel_device_info_enc.tcl + +set_module_property NAME axi_hdmi_tx +set_module_property DESCRIPTION "AXI HDMI Transmit Interface" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME axi_hdmi_tx +set_module_property VALIDATION_CALLBACK info_param_validate +set_module_property ELABORATION_CALLBACK add_out_interface + +# files + +ad_ip_files axi_hdmi_tx [list \ + $ad_hdl_dir/library/common/ad_mem.v \ + $ad_hdl_dir/library/common/ad_rst.v \ + $ad_hdl_dir/library/common/ad_csc.v \ + $ad_hdl_dir/library/common/ad_csc_RGB2CrYCb.v \ + $ad_hdl_dir/library/common/ad_ss_444to422.v \ + $ad_hdl_dir/library/common/up_axi.v \ + $ad_hdl_dir/library/common/up_xfer_cntrl.v \ + $ad_hdl_dir/library/common/up_xfer_status.v \ + $ad_hdl_dir/library/common/up_clock_mon.v \ + $ad_hdl_dir/library/common/up_hdmi_tx.v \ + $ad_hdl_dir/library/intel/common/ad_mul.v \ + $ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_rst_constr.sdc \ + axi_hdmi_tx_vdma.v \ + axi_hdmi_tx_es.v \ + axi_hdmi_tx_core.v \ + axi_hdmi_tx.v \ + axi_hdmi_tx_constr.sdc \ + ] + +# parameters + +add_parameter ID INTEGER 0 +set_parameter_property ID DEFAULT_VALUE 0 +set_parameter_property ID DISPLAY_NAME ID +set_parameter_property ID UNITS None +set_parameter_property ID HDL_PARAMETER true + +add_parameter CR_CB_N INTEGER 0 +set_parameter_property CR_CB_N DEFAULT_VALUE 0 +set_parameter_property CR_CB_N DISPLAY_NAME CR_CB_N +set_parameter_property CR_CB_N UNITS None +set_parameter_property CR_CB_N HDL_PARAMETER true + +add_parameter INTERFACE STRING "16_BIT" +set_parameter_property INTERFACE DEFAULT_VALUE "16_BIT" +set_parameter_property INTERFACE DISPLAY_NAME INTERFACE +set_parameter_property INTERFACE TYPE STRING +set_parameter_property INTERFACE ALLOWED_RANGES { "16_BIT" "24_BIT" "36_BIT" "16_BIT_EMBEDDED_SYNC" "VGA_INTERFACE" } +set_parameter_property INTERFACE HDL_PARAMETER false + +add_parameter DEVICE STRING "" +set_parameter_property DEVICE SYSTEM_INFO {DEVICE} +set_parameter_property DEVICE HDL_PARAMETER false +set_parameter_property DEVICE VISIBLE false + +adi_add_device_spec_param "FPGA_TECHNOLOGY" + +# axi4 slave + +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn + +# reference clock interface + +add_interface reference_clk clock end +add_interface_port reference_clk reference_clk clk Input 1 + +# streaming dma + +add_interface vdma_clock clock end +add_interface_port vdma_clock vdma_clk clk Input 1 + +add_interface vdma_if axi4stream end +set_interface_property vdma_if associatedClock vdma_clock +set_interface_property vdma_if associatedReset s_axi_reset +add_interface_port vdma_if vdma_valid tvalid Input 1 +add_interface_port vdma_if vdma_data tdata Input 64 +add_interface_port vdma_if vdma_ready tready Output 1 +add_interface_port vdma_if vdma_end_of_frame tlast Input 1 + +proc add_out_interface {} { + + set interface [get_parameter_value INTERFACE] + switch $interface { + "16_BIT" { + add_interface hdmi_if conduit end + set_interface_property hdmi_if associatedClock reference_clk + add_interface_port hdmi_if hdmi_out_clk h_clk Output 1 + add_interface_port hdmi_if hdmi_16_hsync h16_hsync Output 1 + add_interface_port hdmi_if hdmi_16_vsync h16_vsync Output 1 + add_interface_port hdmi_if hdmi_16_data_e h16_data_e Output 1 + add_interface_port hdmi_if hdmi_16_data h16_data Output 16 + } + "24_BIT" { + add_interface hdmi_if conduit end + set_interface_property hdmi_if associatedClock reference_clk + add_interface_port hdmi_if hdmi_out_clk h_clk Output 1 + add_interface_port hdmi_if hdmi_24_hsync h24_hsync Output 1 + add_interface_port hdmi_if hdmi_24_vsync h24_vsync Output 1 + add_interface_port hdmi_if hdmi_24_data_e h24_data_e Output 1 + add_interface_port hdmi_if hdmi_24_data h24_data Output 24 + } + "36_BIT" { + add_interface hdmi_if conduit end + set_interface_property hdmi_if associatedClock reference_clk + add_interface_port hdmi_if hdmi_out_clk h_clk Output 1 + add_interface_port hdmi_if hdmi_36_hsync h36_hsync Output 1 + add_interface_port hdmi_if hdmi_36_vsync h36_vsync Output 1 + add_interface_port hdmi_if hdmi_36_data_e h36_data_e Output 1 + add_interface_port hdmi_if hdmi_36_data h36_data Output 36 + } + "16_BIT_EMBEDDED_SYNC" { + add_interface hdmi_if conduit end + set_interface_property hdmi_if associatedClock reference_clk + add_interface_port hdmi_if hdmi_out_clk h_clk Output 1 + add_interface_port hdmi_if hdmi_16_es_data h16_es_data Output 16 + } + "VGA_INTERFACE" { + add_interface vga_if conduit end + set_interface_property vga_if associatedClock reference_clk + add_interface_port vga_if vga_out_clk vga_clk Output 1 + add_interface_port vga_if vga_hsync vga_hsync Output 1 + add_interface_port vga_if vga_vsync vga_vsync Output 1 + add_interface_port vga_if vga_red vga_red Output 8 + add_interface_port vga_if vga_green vga_green Output 8 + add_interface_port vga_if vga_blue vga_blue Output 8 + } + } +} + diff --git a/adi_library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl b/adi_library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl new file mode 100644 index 00000000..26345efd --- /dev/null +++ b/adi_library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl @@ -0,0 +1,92 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_hdmi_tx +adi_ip_files axi_hdmi_tx [list \ + "$ad_hdl_dir/library/common/ad_mem.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/ad_csc.v" \ + "$ad_hdl_dir/library/common/ad_csc_RGB2CrYCb.v" \ + "$ad_hdl_dir/library/common/ad_ss_444to422.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_hdmi_tx.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "axi_hdmi_tx_constr.xdc" \ + "axi_hdmi_tx_vdma.v" \ + "axi_hdmi_tx_es.v" \ + "axi_hdmi_tx_core.v" \ + "axi_hdmi_tx.v" ] + +adi_ip_properties axi_hdmi_tx + +adi_init_bd_tcl +adi_ip_bd axi_hdmi_tx "bd/bd.tcl" + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_hdmi_tx} [ipx::current_core] + +set_property driver_value 0 [ipx::get_ports *hsync* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *vsync* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *data* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *es_data* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *red* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *green* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *blue* -of_objects [ipx::current_core]] + +set_property driver_value 0 [ipx::get_ports *vdma_end_of_frame* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *vdma_valid* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *vdma_data* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *vdma_ready* -of_objects [ipx::current_core]] + +set_property value_format string [ipx::get_user_parameters INTERFACE -of_objects [ipx::current_core]] +set_property value_format string [ipx::get_hdl_parameters INTERFACE -of_objects [ipx::current_core]] +set_property value_validation_list {16_BIT 24_BIT 36_BIT 16_BIT_EMBEDDED_SYNC VGA_INTERFACE} \ + [ipx::get_user_parameters INTERFACE -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "16_BIT" || spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "24_BIT" || spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "36_BIT" || spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "16_BIT_EMBEDDED_SYNC" } \ + [ipx::get_ports *hdmi_out_clk* -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "16_BIT"} \ + [ipx::get_ports *hdmi_16* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "24_BIT"} \ + [ipx::get_ports *hdmi_24* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "36_BIT"} \ + [ipx::get_ports *hdmi_36* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "16_BIT_EMBEDDED_SYNC"} \ + [ipx::get_ports *hdmi_16_es_data* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.INTERFACE')) == "VGA_INTERFACE"} \ + [ipx::get_ports *vga* -of_objects [ipx::current_core]] + +adi_add_bus "s_axis" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"vdma_ready" "TREADY"} \ + {"vdma_valid" "TVALID"} \ + {"vdma_data" "TDATA"} \ + {"vdma_end_of_frame" "TLAST"} ] + +ipx::infer_bus_interface reference_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface hdmi_out_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface vga_out_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface vdma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + +ipx::associate_bus_interfaces -busif s_axis -clock vdma_clk [ipx::current_core] + + +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/axi_hdmi_tx/axi_hdmi_tx_vdma.v b/adi_library/axi_hdmi_tx/axi_hdmi_tx_vdma.v new file mode 100644 index 00000000..2308ec2c --- /dev/null +++ b/adi_library/axi_hdmi_tx/axi_hdmi_tx_vdma.v @@ -0,0 +1,233 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// Transmit HDMI, video dma data in, hdmi separate syncs data out. + +`timescale 1ns/100ps + +module axi_hdmi_tx_vdma ( + + // hdmi interface + + input hdmi_fs_toggle, + input [ 8:0] hdmi_raddr_g, + + // vdma interface + + input vdma_clk, + input vdma_rst, + input vdma_end_of_frame, + input vdma_valid, + input [63:0] vdma_data, + output reg vdma_ready, + output reg vdma_wr, + output reg [ 8:0] vdma_waddr, + output reg [47:0] vdma_wdata, + output reg vdma_fs_ret_toggle, + output reg [ 8:0] vdma_fs_waddr, + output reg vdma_tpm_oos, + output reg vdma_ovf, + output reg vdma_unf +); + + localparam BUF_THRESHOLD_LO = 9'd3; + localparam BUF_THRESHOLD_HI = 9'd509; + localparam RDY_THRESHOLD_LO = 9'd450; + localparam RDY_THRESHOLD_HI = 9'd500; + + // internal registers + + reg vdma_fs_toggle_m1 = 1'd0; + reg vdma_fs_toggle_m2 = 1'd0; + reg vdma_fs_toggle_m3 = 1'd0; + reg [22:0] vdma_tpm_data = 23'd0; + reg [ 8:0] vdma_raddr_g_m1 = 9'd0; + reg [ 8:0] vdma_raddr_g_m2 = 9'd0; + reg [ 8:0] vdma_raddr = 9'd0; + reg [ 8:0] vdma_addr_diff = 9'd0; + reg vdma_almost_full = 1'd0; + reg vdma_almost_empty = 1'd0; + reg hdmi_fs = 1'd0; + reg vdma_fs = 1'd0; + reg vdma_end_of_frame_d = 1'd0; + reg vdma_active_frame = 1'd0; + + // internal wires + + wire [47:0] vdma_tpm_data_s; + wire vdma_tpm_oos_s; + wire [ 9:0] vdma_addr_diff_s; + wire vdma_ovf_s; + wire vdma_unf_s; + + // grey to binary conversion + + function [8:0] g2b; + input [8:0] g; + reg [8:0] b; + begin + b[8] = g[8]; + b[7] = b[8] ^ g[7]; + b[6] = b[7] ^ g[6]; + b[5] = b[6] ^ g[5]; + b[4] = b[5] ^ g[4]; + b[3] = b[4] ^ g[3]; + b[2] = b[3] ^ g[2]; + b[1] = b[2] ^ g[1]; + b[0] = b[1] ^ g[0]; + g2b = b; + end + endfunction + + // hdmi frame sync + + always @(posedge vdma_clk) begin + if (vdma_rst == 1'b1) begin + vdma_fs_toggle_m1 <= 1'd0; + vdma_fs_toggle_m2 <= 1'd0; + vdma_fs_toggle_m3 <= 1'd0; + end else begin + vdma_fs_toggle_m1 <= hdmi_fs_toggle; + vdma_fs_toggle_m2 <= vdma_fs_toggle_m1; + vdma_fs_toggle_m3 <= vdma_fs_toggle_m2; + end + hdmi_fs <= vdma_fs_toggle_m2 ^ vdma_fs_toggle_m3; + end + + // dma frame sync + + always @(posedge vdma_clk) begin + if (vdma_rst == 1'b1) begin + vdma_end_of_frame_d <= 1'b0; + vdma_fs <= 1'b0; + end else begin + vdma_end_of_frame_d <= vdma_end_of_frame; + vdma_fs <= vdma_end_of_frame_d; + end + end + + // sync dma and hdmi frames + + always @(posedge vdma_clk) begin + if (vdma_rst == 1'b1) begin + vdma_fs_ret_toggle = 1'b0; + vdma_fs_waddr <= 9'b0; + end else begin + if (vdma_fs) begin + vdma_fs_ret_toggle <= ~vdma_fs_ret_toggle; + vdma_fs_waddr <= vdma_waddr ; + end + end + end + + // accept new frame from dma + + always @(posedge vdma_clk) begin + if (vdma_rst == 1'b1) begin + vdma_active_frame <= 1'b0; + end else begin + if ((vdma_active_frame == 1'b1) && (vdma_end_of_frame == 1'b1)) begin + vdma_active_frame <= 1'b0; + end else if ((vdma_active_frame == 1'b0) && (hdmi_fs == 1'b1)) begin + vdma_active_frame <= 1'b1; + end + end + end + + // vdma write + + always @(posedge vdma_clk) begin + vdma_wr <= vdma_valid & vdma_ready; + if (vdma_rst == 1'b1) begin + vdma_waddr <= 9'd0; + end else if (vdma_wr == 1'b1) begin + vdma_waddr <= vdma_waddr + 1'b1; + end + vdma_wdata <= {vdma_data[55:32], vdma_data[23:0]}; + end + + // test error conditions + + assign vdma_tpm_data_s = {vdma_tpm_data, 1'b1, vdma_tpm_data, 1'b0}; + assign vdma_tpm_oos_s = (vdma_wdata == vdma_tpm_data_s) ? 1'b0 : vdma_wr; + + always @(posedge vdma_clk) begin + if ((vdma_rst == 1'b1) || (vdma_fs == 1'b1)) begin + vdma_tpm_data <= 23'd0; + vdma_tpm_oos <= 1'd0; + end else if (vdma_wr == 1'b1) begin + vdma_tpm_data <= vdma_tpm_data + 1'b1; + vdma_tpm_oos <= vdma_tpm_oos_s; + end + end + + // overflow or underflow status + + assign vdma_addr_diff_s = {1'b1, vdma_waddr} - vdma_raddr; + assign vdma_ovf_s = (vdma_addr_diff < BUF_THRESHOLD_LO) ? vdma_almost_full : 1'b0; + assign vdma_unf_s = (vdma_addr_diff > BUF_THRESHOLD_HI) ? vdma_almost_empty : 1'b0; + + always @(posedge vdma_clk) begin + if (vdma_rst == 1'b1) begin + vdma_raddr_g_m1 <= 9'd0; + vdma_raddr_g_m2 <= 9'd0; + end else begin + vdma_raddr_g_m1 <= hdmi_raddr_g; + vdma_raddr_g_m2 <= vdma_raddr_g_m1; + end + end + + always @(posedge vdma_clk) begin + vdma_raddr <= g2b(vdma_raddr_g_m2); + vdma_addr_diff <= vdma_addr_diff_s[8:0]; + if (vdma_addr_diff >= RDY_THRESHOLD_HI) begin + vdma_ready <= 1'b0; + end else if (vdma_addr_diff <= RDY_THRESHOLD_LO) begin + vdma_ready <= vdma_active_frame; + end + if (vdma_addr_diff > BUF_THRESHOLD_HI) begin + vdma_almost_full <= 1'b1; + end else begin + vdma_almost_full <= 1'b0; + end + if (vdma_addr_diff < BUF_THRESHOLD_LO) begin + vdma_almost_empty <= 1'b1; + end else begin + vdma_almost_empty <= 1'b0; + end + vdma_ovf <= vdma_ovf_s; + vdma_unf <= vdma_unf_s; + end + +endmodule diff --git a/adi_library/axi_hdmi_tx/bd/bd.tcl b/adi_library/axi_hdmi_tx/bd/bd.tcl new file mode 100644 index 00000000..ba898b2b --- /dev/null +++ b/adi_library/axi_hdmi_tx/bd/bd.tcl @@ -0,0 +1,44 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + FPGA_TECHNOLOGY" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/axi_hdmi_tx/component.xml b/adi_library/axi_hdmi_tx/component.xml new file mode 100644 index 00000000..4853c0b9 --- /dev/null +++ b/adi_library/axi_hdmi_tx/component.xml @@ -0,0 +1,1608 @@ + + + analog.com + user + axi_hdmi_tx + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s_axis + + + + + + + TREADY + + + vdma_ready + + + + + TVALID + + + vdma_valid + + + + + TDATA + + + vdma_data + + + + + TLAST + + + vdma_end_of_frame + + + + + + reference_clk + + + + + + + CLK + + + reference_clk + + + + + + hdmi_out_clk + + + + + + + CLK + + + hdmi_out_clk + + + + + + vga_out_clk + + + + + + + CLK + + + vga_out_clk + + + + + + vdma_clk + + + + + + + CLK + + + vdma_clk + + + + + + ASSOCIATED_BUSIF + s_axis + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_hdmi_tx + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 9d6d3555 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_hdmi_tx + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 6b939f5e + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 70073919 + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + + + reference_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + hdmi_out_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + vga_out_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + hdmi_16_hsync + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + hdmi_16_vsync + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + hdmi_16_data_e + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + hdmi_16_data + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + hdmi_16_es_data + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + hdmi_24_hsync + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + hdmi_24_vsync + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + hdmi_24_data_e + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + hdmi_24_data + + out + + 23 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + vga_hsync + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + vga_vsync + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + vga_red + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + vga_green + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + vga_blue + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + hdmi_36_hsync + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + hdmi_36_vsync + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + hdmi_36_data_e + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + hdmi_36_data + + out + + 35 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + vdma_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + vdma_end_of_frame + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + vdma_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + vdma_data + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + vdma_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + CR_CB_N + Cr Cb N + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + INTERFACE + Interface + 16_BIT + + + OUT_CLK_POLARITY + Out Clk Polarity + 0 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_list_dcfc42bd + 16_BIT + 24_BIT + 36_BIT + 16_BIT_EMBEDDED_SYNC + VGA_INTERFACE + + + choice_pairs_28f798a2 + 0 + 1 + 2 + 3 + 4 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../xilinx/common/up_clock_mon_constr.xdc + xdc + + + axi_hdmi_tx_constr.xdc + xdc + + + ../common/ad_csc.v + verilogSource + + + ../common/ad_csc_RGB2CrYCb.v + verilogSource + + + ../common/ad_mem.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../common/ad_ss_444to422.v + verilogSource + + + axi_hdmi_tx_core.v + verilogSource + + + axi_hdmi_tx_es.v + verilogSource + + + axi_hdmi_tx_vdma.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_hdmi_tx.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_hdmi_tx.v + verilogSource + CHECKSUM_cc010272 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_csc.v + verilogSource + + + ../common/ad_csc_RGB2CrYCb.v + verilogSource + + + ../common/ad_mem.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + ../common/ad_ss_444to422.v + verilogSource + + + axi_hdmi_tx_core.v + verilogSource + + + axi_hdmi_tx_es.v + verilogSource + + + axi_hdmi_tx_vdma.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_hdmi_tx.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_hdmi_tx.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_hdmi_tx_v1_0.tcl + tclSource + CHECKSUM_a6d814f3 + XGUI_VERSION_2 + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + axi_hdmi_tx_v1_0 + + + ID + Id + 0 + + + CR_CB_N + Cr Cb N + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + INTERFACE + Interface + 16_BIT + + + OUT_CLK_POLARITY + Out Clk Polarity + 0 + + + Component_Name + axi_hdmi_tx_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_hdmi_tx_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_hdmi_tx + 1 + 2024-01-14T03:47:23Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_hdmi_tx/temporary_case_dependencies.mk b/adi_library/axi_hdmi_tx/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/axi_hdmi_tx/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/axi_hdmi_tx/xgui/axi_hdmi_tx_v1_0.tcl b/adi_library/axi_hdmi_tx/xgui/axi_hdmi_tx_v1_0.tcl new file mode 100644 index 00000000..1baf4f23 --- /dev/null +++ b/adi_library/axi_hdmi_tx/xgui/axi_hdmi_tx_v1_0.tcl @@ -0,0 +1,88 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "CR_CB_N" -parent ${Page_0} + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "INTERFACE" -parent ${Page_0} + ipgui::add_param $IPINST -name "OUT_CLK_POLARITY" -parent ${Page_0} + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.CR_CB_N { PARAM_VALUE.CR_CB_N } { + # Procedure called to update CR_CB_N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CR_CB_N { PARAM_VALUE.CR_CB_N } { + # Procedure called to validate CR_CB_N + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.INTERFACE { PARAM_VALUE.INTERFACE } { + # Procedure called to update INTERFACE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.INTERFACE { PARAM_VALUE.INTERFACE } { + # Procedure called to validate INTERFACE + return true +} + +proc update_PARAM_VALUE.OUT_CLK_POLARITY { PARAM_VALUE.OUT_CLK_POLARITY } { + # Procedure called to update OUT_CLK_POLARITY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_CLK_POLARITY { PARAM_VALUE.OUT_CLK_POLARITY } { + # Procedure called to validate OUT_CLK_POLARITY + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.CR_CB_N { MODELPARAM_VALUE.CR_CB_N PARAM_VALUE.CR_CB_N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CR_CB_N}] ${MODELPARAM_VALUE.CR_CB_N} +} + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.INTERFACE { MODELPARAM_VALUE.INTERFACE PARAM_VALUE.INTERFACE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.INTERFACE}] ${MODELPARAM_VALUE.INTERFACE} +} + +proc update_MODELPARAM_VALUE.OUT_CLK_POLARITY { MODELPARAM_VALUE.OUT_CLK_POLARITY PARAM_VALUE.OUT_CLK_POLARITY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_CLK_POLARITY}] ${MODELPARAM_VALUE.OUT_CLK_POLARITY} +} + diff --git a/adi_library/axi_i2s_adi/Makefile b/adi_library/axi_i2s_adi/Makefile new file mode 100644 index 00000000..973fd145 --- /dev/null +++ b/adi_library/axi_i2s_adi/Makefile @@ -0,0 +1,27 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_i2s_adi + +GENERIC_DEPS += ../common/axi_ctrlif.vhd +GENERIC_DEPS += ../common/axi_streaming_dma_rx_fifo.vhd +GENERIC_DEPS += ../common/axi_streaming_dma_tx_fifo.vhd +GENERIC_DEPS += ../common/dma_fifo.vhd +GENERIC_DEPS += ../common/pl330_dma_fifo.vhd +GENERIC_DEPS += axi_i2s_adi.vhd +GENERIC_DEPS += fifo_synchronizer.vhd +GENERIC_DEPS += i2s_clkgen.vhd +GENERIC_DEPS += i2s_controller.vhd +GENERIC_DEPS += i2s_rx.vhd +GENERIC_DEPS += i2s_tx.vhd + +XILINX_DEPS += axi_i2s_adi_constr.xdc +XILINX_DEPS += axi_i2s_adi_ip.tcl + +XILINX_DEPS += ../axi_i2s_adi/i2s.xml +XILINX_DEPS += ../axi_i2s_adi/i2s_rtl.xml + +include ../scripts/library.mk diff --git a/adi_library/axi_i2s_adi/axi_i2s_adi.vhd b/adi_library/axi_i2s_adi/axi_i2s_adi.vhd new file mode 100644 index 00000000..b31859ea --- /dev/null +++ b/adi_library/axi_i2s_adi/axi_i2s_adi.vhd @@ -0,0 +1,482 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +-- +-- In this HDL repository, there are many different and unique modules, consisting +-- of various HDL (Verilog or VHDL) components. The individual modules are +-- developed independently, and may be accompanied by separate and unique license +-- terms. +-- +-- The user should read each of these license terms, and understand the +-- freedoms and responsibilities that he or she has by using this source/core. +-- +-- This core is distributed in the hope that it will be useful, but WITHOUT ANY +-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +-- A PARTICULAR PURPOSE. +-- +-- Redistribution and use of source or resulting binaries, with or without modification +-- of this file, are permitted under one of the following two license terms: +-- +-- 1. The GNU General Public License version 2 as published by the +-- Free Software Foundation, which can be found in the top level directory +-- of this repository (LICENSE_GPL2), and also online at: +-- +-- +-- OR +-- +-- 2. An ADI specific BSD license, which can be found in the top level directory +-- of this repository (LICENSE_ADIBSD), and also on-line at: +-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +-- This will allow to generate bit files and not release the source code, +-- as long as it attaches to an ADI device. +-- +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +library work; +use work.i2s_controller; + +library work; +use work.axi_streaming_dma_rx_fifo; +use work.axi_streaming_dma_tx_fifo; +use work.pl330_dma_fifo; +use work.axi_ctrlif; + +entity axi_i2s_adi is + generic + ( + -- ADD USER GENERICS BELOW THIS LINE --------------- + SLOT_WIDTH : integer := 24; + LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge) + BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge) + -- ADD USER GENERICS ABOVE THIS LINE --------------- + + -- DO NOT EDIT BELOW THIS LINE --------------------- + -- Bus protocol parameters, do not add to or delete + S_AXI_DATA_WIDTH : integer := 32; + S_AXI_ADDRESS_WIDTH : integer := 32; + DEVICE_FAMILY : string := "virtex6"; + -- DO NOT EDIT ABOVE THIS LINE --------------------- + DMA_TYPE : integer := 0; + NUM_OF_CHANNEL : integer := 1; + HAS_TX : integer := 1; + HAS_RX : integer := 1 + ); + port + ( + -- Serial Data interface + data_clk_i : in std_logic; + bclk_o : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0); + lrclk_o : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0); + sdata_o : out std_logic_vector(NUM_OF_CHANNEL - 1 downto 0); + sdata_i : in std_logic_vector(NUM_OF_CHANNEL - 1 downto 0); + + -- AXI Streaming DMA TX interface + s_axis_aclk : in std_logic; + s_axis_aresetn : in std_logic; + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(31 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- AXI Streaming DMA RX interface + m_axis_aclk : in std_logic; + m_axis_tready : in std_logic; + m_axis_tdata : out std_logic_vector(31 downto 0); + m_axis_tlast : out std_logic; + m_axis_tvalid : out std_logic; + m_axis_tkeep : out std_logic_vector(3 downto 0); + + --PL330 DMA TX interface + dma_req_tx_aclk : in std_logic; + dma_req_tx_rstn : in std_logic; + dma_req_tx_davalid : in std_logic; + dma_req_tx_datype : in std_logic_vector(1 downto 0); + dma_req_tx_daready : out std_logic; + dma_req_tx_drvalid : out std_logic; + dma_req_tx_drtype : out std_logic_vector(1 downto 0); + dma_req_tx_drlast : out std_logic; + dma_req_tx_drready : in std_logic; + + -- PL330 DMA RX interface + dma_req_rx_aclk : in std_logic; + dma_req_rx_rstn : in std_logic; + dma_req_rx_davalid : in std_logic; + dma_req_rx_datype : in std_logic_vector(1 downto 0); + dma_req_rx_daready : out std_logic; + dma_req_rx_drvalid : out std_logic; + dma_req_rx_drtype : out std_logic_vector(1 downto 0); + dma_req_rx_drlast : out std_logic; + dma_req_rx_drready : in std_logic; + + -- AXI bus interface + s_axi_aclk : in std_logic; + s_axi_aresetn : in std_logic; + s_axi_awaddr : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0); + s_axi_awvalid : in std_logic; + s_axi_wdata : in std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0); + s_axi_wstrb : in std_logic_vector((S_AXI_DATA_WIDTH/8)-1 downto 0); + s_axi_wvalid : in std_logic; + s_axi_bready : in std_logic; + s_axi_araddr : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0); + s_axi_arvalid : in std_logic; + s_axi_rready : in std_logic; + s_axi_arready : out std_logic; + s_axi_rdata : out std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0); + s_axi_rresp : out std_logic_vector(1 downto 0); + s_axi_rvalid : out std_logic; + s_axi_wready : out std_logic; + s_axi_bresp : out std_logic_vector(1 downto 0); + s_axi_bvalid : out std_logic; + s_axi_awready : out std_logic; + s_axi_awprot : in std_logic_vector(2 downto 0); + s_axi_arprot : in std_logic_vector(2 downto 0) + + ); +end entity axi_i2s_adi; + +architecture Behavioral of axi_i2s_adi is + +------------------------------------------ +-- Signals for user logic slave model s/w accessible register example +------------------------------------------ +signal i2s_reset : std_logic; +signal tx_fifo_reset : std_logic; +signal tx_enable : Boolean; +signal tx_data : std_logic_vector(SLOT_WIDTH - 1 downto 0); +signal tx_ack : std_logic; +signal tx_stb : std_logic; + +signal rx_enable : Boolean; +signal rx_fifo_reset : std_logic; +signal rx_data : std_logic_vector(SLOT_WIDTH - 1 downto 0); +signal rx_ack : std_logic; +signal rx_stb : std_logic; + +signal const_1 : std_logic; + +signal bclk_div_rate : natural range 0 to 255; +signal lrclk_div_rate : natural range 0 to 255; + +signal period_len : integer range 0 to 65535; + +signal I2S_RESET_REG : std_logic_vector(31 downto 0); +signal I2S_CONTROL_REG : std_logic_vector(31 downto 0); +signal I2S_CLK_CONTROL_REG : std_logic_vector(31 downto 0); +signal PERIOD_LEN_REG : std_logic_vector(31 downto 0); + +constant FIFO_AWIDTH : integer := integer(ceil(log2(real(NUM_OF_CHANNEL * 8)))); + +-- Audio samples FIFO +constant RAM_ADDR_WIDTH : integer := 7; +type RAM_TYPE is array (0 to (2**RAM_ADDR_WIDTH - 1)) of std_logic_vector(31 downto 0); + +-- RX FIFO signals +signal audio_fifo_rx : RAM_TYPE; +signal audio_fifo_rx_wr_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1; +signal audio_fifo_rx_rd_addr : integer range 0 to 2**RAM_ADDR_WIDTH-1; +signal tvalid : std_logic := '0'; +signal rx_tlast : std_logic; +signal drain_tx_dma : std_logic; + +signal rx_sample : std_logic_vector(23 downto 0); + +signal wr_data : std_logic_vector(31 downto 0); +signal rd_data : std_logic_vector(31 downto 0); +signal wr_addr : integer range 0 to 11; +signal rd_addr : integer range 0 to 11; +signal wr_stb : std_logic; +signal rd_ack : std_logic; +signal tx_fifo_stb : std_logic; +signal rx_fifo_ack : std_logic; +signal cnt : integer range 0 to 2**16-1; +begin + + const_1 <= '1'; + + process (s_axi_aclk) + begin + if rising_edge(s_axi_aclk) then + if s_axi_aresetn = '0' then + cnt <= 0; + else + cnt <= (cnt + 1) mod 2**16; + end if; + end if; + end process; + + streaming_dma_tx_gen: if DMA_TYPE = 0 and HAS_TX = 1 generate + tx_fifo : entity axi_streaming_dma_tx_fifo + generic map( + RAM_ADDR_WIDTH => FIFO_AWIDTH, + FIFO_DWIDTH => 24 + ) + port map( + clk => s_axi_aclk, + resetn => s_axi_aresetn, + fifo_reset => tx_fifo_reset, + enable => tx_enable, + + s_axis_aclk => s_axis_aclk, + s_axis_tready => s_axis_tready, + s_axis_tdata => s_axis_tdata(31 downto 8), + s_axis_tlast => s_axis_tlast, + s_axis_tvalid => s_axis_tvalid, + + out_stb => tx_stb, + out_ack => tx_ack, + out_data => tx_data + ); + end generate; + + no_streaming_dma_tx_gen: if DMA_TYPE /= 0 or HAS_TX /= 1 generate + s_axis_tready <= '0'; + end generate; + + streaming_dma_rx_gen: if DMA_TYPE = 0 and HAS_RX = 1 generate + rx_fifo : entity axi_streaming_dma_rx_fifo + generic map( + RAM_ADDR_WIDTH => FIFO_AWIDTH, + FIFO_DWIDTH => 24 + ) + port map( + clk => s_axi_aclk, + resetn => s_axi_aresetn, + fifo_reset => tx_fifo_reset, + enable => tx_enable, + + period_len => period_len, + + in_stb => rx_stb, + in_ack => rx_ack, + in_data => rx_data, + + m_axis_aclk => m_axis_aclk, + m_axis_tready => m_axis_tready, + m_axis_tdata => m_axis_tdata(31 downto 8), + m_axis_tlast => m_axis_tlast, + m_axis_tvalid => m_axis_tvalid, + m_axis_tkeep => m_axis_tkeep + ); + + m_axis_tdata(7 downto 0) <= (others => '0'); + end generate; + + no_streaming_dma_rx_gen: if DMA_TYPE /= 0 or HAS_RX /= 1 generate + m_axis_tdata <= (others => '0'); + m_axis_tlast <= '0'; + m_axis_tvalid <= '0'; + m_axis_tkeep <= (others => '0'); + end generate; + + + + pl330_dma_tx_gen: if DMA_TYPE = 1 and HAS_TX = 1 generate + tx_fifo_stb <= '1' when wr_addr = 11 and wr_stb = '1' else '0'; + + tx_fifo: entity pl330_dma_fifo + generic map( + RAM_ADDR_WIDTH => FIFO_AWIDTH, + FIFO_DWIDTH => 24, + FIFO_DIRECTION => 0 + ) + port map ( + clk => s_axi_aclk, + resetn => s_axi_aresetn, + fifo_reset => tx_fifo_reset, + enable => tx_enable, + + in_data => wr_data(31 downto 8), + in_stb => tx_fifo_stb, + + out_ack => tx_ack, + out_stb => tx_stb, + out_data => tx_data, + + dclk => dma_req_tx_aclk, + dresetn => dma_req_tx_rstn, + davalid => dma_req_tx_davalid, + daready => dma_req_tx_daready, + datype => dma_req_tx_datype, + drvalid => dma_req_tx_drvalid, + drready => dma_req_tx_drready, + drtype => dma_req_tx_drtype, + drlast => dma_req_tx_drlast + ); + end generate; + + no_pl330_dma_tx_gen: if DMA_TYPE /= 1 or HAS_TX /= 1 generate + dma_req_tx_daready <= '0'; + dma_req_tx_drvalid <= '0'; + dma_req_tx_drtype <= (others => '0'); + dma_req_tx_drlast <= '0'; + end generate; + + pl330_dma_rx_gen: if DMA_TYPE = 1 and HAS_RX = 1 generate + rx_fifo_ack <= '1' when rd_addr = 10 and rd_ack = '1' else '0'; + + rx_fifo: entity pl330_dma_fifo + generic map( + RAM_ADDR_WIDTH => FIFO_AWIDTH, + FIFO_DWIDTH => 24, + FIFO_DIRECTION => 1 + ) + port map ( + clk => s_axi_aclk, + resetn => s_axi_aresetn, + fifo_reset => rx_fifo_reset, + enable => rx_enable, + + in_ack => rx_ack, + in_stb => rx_stb, + in_data => rx_data, + + out_data => rx_sample, + out_ack => rx_fifo_ack, + + dclk => dma_req_rx_aclk, + dresetn => dma_req_rx_rstn, + davalid => dma_req_rx_davalid, + daready => dma_req_rx_daready, + datype => dma_req_rx_datype, + drvalid => dma_req_rx_drvalid, + drready => dma_req_rx_drready, + drtype => dma_req_rx_drtype, + drlast => dma_req_rx_drlast + ); + + end generate; + + no_pl330_dma_rx_gen: if DMA_TYPE /= 1 or HAS_RX /= 1 generate + dma_req_rx_daready <= '0'; + dma_req_rx_drvalid <= '0'; + dma_req_rx_drtype <= (others => '0'); + dma_req_rx_drlast <= '0'; + end generate; + + ctrl : entity i2s_controller + generic map ( + C_SLOT_WIDTH => SLOT_WIDTH, + C_BCLK_POL => BCLK_POL, + C_LRCLK_POL => LRCLK_POL, + C_NUM_CH => NUM_OF_CHANNEL, + C_HAS_TX => HAS_TX, + C_HAS_RX => HAS_RX + ) + port map ( + clk => s_axi_aclk, + resetn => s_axi_aresetn, + + data_clk => data_clk_i, + bclk_o => bclk_o, + lrclk_o => lrclk_o, + sdata_o => sdata_o, + sdata_i => sdata_i, + + tx_enable => tx_enable, + tx_ack => tx_ack, + tx_stb => tx_stb, + tx_data => tx_data, + + rx_enable => rx_enable, + rx_ack => rx_ack, + rx_stb => rx_stb, + rx_data => rx_data, + + bclk_div_rate => bclk_div_rate, + lrclk_div_rate => lrclk_div_rate + ); + + i2s_reset <= I2S_RESET_REG(0); + tx_fifo_reset <= I2S_RESET_REG(1); + rx_fifo_reset <= I2S_RESET_REG(2); + tx_enable <= I2S_CONTROL_REG(0) = '1'; + rx_enable <= I2S_CONTROL_REG(1) = '1'; + bclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(7 downto 0))); + lrclk_div_rate <= to_integer(unsigned(I2S_CLK_CONTROL_REG(23 downto 16))); + period_len <= to_integer(unsigned(PERIOD_LEN_REG(15 downto 0))); + + ctrlif: entity axi_ctrlif + generic map ( + C_S_AXI_ADDR_WIDTH => S_AXI_ADDRESS_WIDTH, + C_S_AXI_DATA_WIDTH => S_AXI_DATA_WIDTH, + C_NUM_REG => 12 + ) + port map( + s_axi_aclk => s_axi_aclk, + s_axi_aresetn => s_axi_aresetn, + s_axi_awaddr => s_axi_awaddr, + s_axi_awvalid => s_axi_awvalid, + s_axi_wdata => s_axi_wdata, + s_axi_wstrb => s_axi_wstrb, + s_axi_wvalid => s_axi_wvalid, + s_axi_bready => s_axi_bready, + s_axi_araddr => s_axi_araddr, + s_axi_arvalid => s_axi_arvalid, + s_axi_rready => s_axi_rready, + s_axi_arready => s_axi_arready, + s_axi_rdata => s_axi_rdata, + s_axi_rresp => s_axi_rresp, + s_axi_rvalid => s_axi_rvalid, + s_axi_wready => s_axi_wready, + s_axi_bresp => s_axi_bresp, + s_axi_bvalid => s_axi_bvalid, + s_axi_awready => s_axi_awready, + + rd_addr => rd_addr, + rd_data => rd_data, + rd_ack => rd_ack, + rd_stb => const_1, + + wr_addr => wr_addr, + wr_data => wr_data, + wr_ack => const_1, + wr_stb => wr_stb + ); + + process(rd_addr, I2S_CONTROL_REG, I2S_CLK_CONTROL_REG, PERIOD_LEN_REG, rx_sample, cnt) + begin + case rd_addr is + when 1 => rd_data <= I2S_CONTROL_REG and x"00000003"; + when 2 => rd_data <= I2S_CLK_CONTROL_REG and x"00ff00ff"; + when 6 => rd_data <= PERIOD_LEN_REG and x"0000ffff"; + when 10 => rd_data <= rx_sample & std_logic_vector(to_unsigned(cnt, 8)); + when others => rd_data <= (others => '0'); + end case; + end process; + + process(s_axi_aclk) is + begin + if rising_edge(s_axi_aclk) then + if s_axi_aresetn = '0' then + I2S_RESET_REG <= (others => '0'); + I2S_CONTROL_REG <= (others => '0'); + I2S_CLK_CONTROL_REG <= (others => '0'); + PERIOD_LEN_REG <= (others => '0'); + else + -- Auto-clear the Reset Register bits + I2S_RESET_REG(0) <= '0'; + I2S_RESET_REG(1) <= '0'; + I2S_RESET_REG(2) <= '0'; + if wr_stb = '1' then + case wr_addr is + when 0 => I2S_RESET_REG <= wr_data; + when 1 => I2S_CONTROL_REG <= wr_data; + when 2 => I2S_CLK_CONTROL_REG <= wr_data; + when 6 => PERIOD_LEN_REG <= wr_data; + when others => null; + end case; + end if; + end if; + end if; + end process; + +end Behavioral; diff --git a/adi_library/axi_i2s_adi/axi_i2s_adi.xpr b/adi_library/axi_i2s_adi/axi_i2s_adi.xpr new file mode 100644 index 00000000..5dc837ad --- /dev/null +++ b/adi_library/axi_i2s_adi/axi_i2s_adi.xpr @@ -0,0 +1,464 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_i2s_adi/axi_i2s_adi_constr.xdc b/adi_library/axi_i2s_adi/axi_i2s_adi_constr.xdc new file mode 100644 index 00000000..43e54e9f --- /dev/null +++ b/adi_library/axi_i2s_adi/axi_i2s_adi_constr.xdc @@ -0,0 +1,31 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set ctrl_clk [get_clocks -of_objects [get_ports s_axi_aclk]] +set data_clk [get_clocks -of_objects [get_ports data_clk_i]] + +set_property ASYNC_REG TRUE \ + [get_cells -hier cdc_sync_stage1_*_reg] \ + [get_cells -hier cdc_sync_stage2_*_reg] + +set_false_path \ + -from [get_cells -hier cdc_sync_stage0_*_reg -filter {IS_SEQUENTIAL}] \ + -to [get_cells -hier cdc_sync_stage1_*_reg -filter {IS_SEQUENTIAL}] + +# TX FIFO +set_max_delay \ + -from $ctrl_clk \ + -to [get_cells -hier out_data_reg* -filter {IS_SEQUENTIAL && NAME =~ *tx_sync*}] \ + [get_property PERIOD $data_clk] -datapath_only + +# RX FIFO +set_max_delay \ + -from $data_clk \ + -to [get_cells -hier out_data_reg* -filter {IS_SEQUENTIAL && NAME =~ *rx_sync*}] \ + [get_property PERIOD $ctrl_clk] -datapath_only + +# Reset +set_false_path \ + -to [get_pins -hier data_reset_vec_reg*/PRE] diff --git a/adi_library/axi_i2s_adi/axi_i2s_adi_ip.tcl b/adi_library/axi_i2s_adi/axi_i2s_adi_ip.tcl new file mode 100644 index 00000000..1b88ab0d --- /dev/null +++ b/adi_library/axi_i2s_adi/axi_i2s_adi_ip.tcl @@ -0,0 +1,243 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_i2s_adi +adi_ip_files axi_i2s_adi [list \ + "$ad_hdl_dir/library/common/axi_ctrlif.vhd" \ + "$ad_hdl_dir/library/common/axi_streaming_dma_tx_fifo.vhd" \ + "$ad_hdl_dir/library/common/axi_streaming_dma_rx_fifo.vhd" \ + "$ad_hdl_dir/library/common/pl330_dma_fifo.vhd" \ + "$ad_hdl_dir/library/common/dma_fifo.vhd" \ + "i2s_controller.vhd" \ + "i2s_rx.vhd" \ + "i2s_tx.vhd" \ + "i2s_clkgen.vhd" \ + "fifo_synchronizer.vhd" \ + "axi_i2s_adi.vhd" \ + "axi_i2s_adi_constr.xdc" \ +] + +adi_ip_properties axi_i2s_adi + +set_property PROCESSING_ORDER LATE [ipx::get_files axi_i2s_adi_constr.xdc \ + -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \ + -filter {NAME =~ *synthesis*}]] + +adi_ip_infer_streaming_interfaces axi_i2s_adi + +set_property display_name "ADI AXI I2S Controller" [ipx::current_core] +set_property description "ADI AXI I2S Controller" [ipx::current_core] + +adi_add_bus "dma_ack_rx" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { \ + {"dma_req_rx_davalid" "TVALID"} \ + {"dma_req_rx_daready" "TREADY"} \ + {"dma_req_rx_datype" "TUSER"} \ + } + +adi_add_bus "dma_req_rx" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { \ + {"dma_req_rx_drvalid" "TVALID"} \ + {"dma_req_rx_drready" "TREADY"} \ + {"dma_req_rx_drtype" "TUSER"} \ + {"dma_req_rx_drlast" "TLAST"} \ + } +# Clock and reset are for both dma_req and dma_ack +adi_add_bus_clock "dma_req_rx_aclk" "dma_req_rx:dma_ack_rx" "dma_req_rx_rstn" + +adi_add_bus "dma_ack_tx" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { \ + {"dma_req_tx_davalid" "TVALID"} \ + {"dma_req_tx_daready" "TREADY"} \ + {"dma_req_tx_datype" "TUSER"} \ + } +adi_add_bus "dma_req_tx" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { \ + {"dma_req_tx_drvalid" "TVALID"} \ + {"dma_req_tx_drready" "TREADY"} \ + {"dma_req_tx_drtype" "TUSER"} \ + {"dma_req_tx_drlast" "TLAST"} \ + } +# Clock and reset are for both dma_req and dma_ack +adi_add_bus_clock "dma_req_tx_aclk" "dma_req_tx:dma_ack_tx" "dma_req_tx_rstn" + +adi_add_bus "i2s" "master" \ + "analog.com:interface:i2s_rtl:1.0" \ + "analog.com:interface:i2s:1.0" \ + { \ + {"bclk_o" "BCLK"} \ + {"lrclk_o" "LRCLK"} \ + {"sdata_o" "SDATA_OUT"} \ + {"sdata_i" "SDATA_IN"} \ + } +adi_add_bus_clock "data_clk_i" "i2s" + +adi_set_bus_dependency "s_axis" "s_axis" \ + "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.HAS_TX')) = 1)" +adi_set_bus_dependency "m_axis" "m_axis" \ + "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0 and spirit:decode(id('MODELPARAM_VALUE.HAS_RX')) = 1)" + +adi_set_bus_dependency "dma_ack_tx" "dma_req_tx_da" \ + "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_TX')) = 1)" +adi_set_bus_dependency "dma_req_tx" "dma_req_tx_dr" \ + "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_TX')) = 1)" +adi_set_ports_dependency "dma_req_tx_aclk" \ + "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_TX')) = 1)" +adi_set_ports_dependency "dma_req_tx_rstn" \ + "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_TX')) = 1)" +adi_set_bus_dependency "dma_ack_rx" "dma_req_rx_da" \ + "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_RX')) = 1)" +adi_set_bus_dependency "dma_req_rx" "dma_req_rx_dr" \ + "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_RX')) = 1)" +adi_set_ports_dependency "dma_req_rx_aclk" \ + "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_RX')) = 1)" +adi_set_ports_dependency "dma_req_rx_rstn" \ + "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1 and spirit:decode(id('MODELPARAM_VALUE.HAS_RX')) = 1)" + +# Tie-off optional inputs to 0 +set_property driver_value 0 [ipx::get_ports -filter "direction==in && enablement_dependency!={}" -of_objects [ipx::current_core]] + +set cc [ipx::current_core] + +set_property -dict [list \ + "value_validation_type" "list" \ + "value_validation_list" "16 20 24 32" \ + ] \ + [ipx::get_user_parameters SLOT_WIDTH -of_objects $cc] + +set_property -dict [list \ + "value_validation_type" "pairs" \ + "value_validation_pairs" { \ + "Falling Edge" "0" \ + "Rising Edge" "1" \ + } \ +] \ +[ipx::get_user_parameters LRCLK_POL -of_objects $cc] + +set_property -dict [list \ + "value_validation_type" "pairs" \ + "value_validation_pairs" { \ + "Falling Edge" "0" \ + "Rising Edge" "1" \ + } \ +] \ +[ipx::get_user_parameters BCLK_POL -of_objects $cc] + +set_property -dict [list \ + "value_validation_type" "pairs" \ + "value_validation_pairs" { \ + "AXI Stream" "0" \ + "PL330" "1" \ + } \ +] \ +[ipx::get_user_parameters DMA_TYPE -of_objects $cc] + +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "0" \ + "value_validation_range_maximum" "1" \ + ] \ + [ipx::get_user_parameters HAS_RX -of_objects $cc] + +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "0" \ + "value_validation_range_maximum" "1" \ + ] \ + [ipx::get_user_parameters HAS_TX -of_objects $cc] + +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "1" \ + "value_validation_range_maximum" "32" \ + ] \ + [ipx::get_user_parameters NUM_OF_CHANNEL -of_objects $cc] + +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "1" \ + "value_validation_range_maximum" "32" \ + ] \ + [ipx::get_user_parameters S_AXI_ADDRESS_WIDTH -of_objects $cc] + +set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] + +set i2s_group [ipgui::add_group -name "I2S Configuration" -component $cc \ + -parent $page0 -display_name "I2S Configuration"] + +set p [ipgui::get_guiparamspec -name "SLOT_WIDTH" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $i2s_group +set_property -dict [list \ + "widget" "comboBox" \ + "display_name" "Slot Width" \ +] $p + +set p [ipgui::get_guiparamspec -name "LRCLK_POL" -component $cc] +ipgui::move_param -component $cc -order 1 $p -parent $i2s_group +set_property -dict [list \ + "widget" "comboBox" \ + "display_name" "Left-Right Clock Polarity" \ +] $p + +set p [ipgui::get_guiparamspec -name "BCLK_POL" -component $cc] +ipgui::move_param -component $cc -order 2 $p -parent $i2s_group +set_property -dict [list \ + "widget" "comboBox" \ + "display_name" "Bit Clock Polarity" \ +] $p + +set general_group [ipgui::add_group -name "General Configuration" -component $cc \ + -parent $page0 -display_name "General Configuration"] + +set p [ipgui::get_guiparamspec -name "HAS_RX" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $general_group +set_property -dict [list \ + "widget" "checkBox" \ + "display_name" "Enable I2S Receiver Support" \ +] $p + +set p [ipgui::get_guiparamspec -name "HAS_TX" -component $cc] +ipgui::move_param -component $cc -order 1 $p -parent $general_group +set_property -dict [list \ + "widget" "checkBox" \ + "display_name" "Enable I2S Transmitter Support" \ +] $p + +set p [ipgui::get_guiparamspec -name "DMA_TYPE" -component $cc] +ipgui::move_param -component $cc -order 2 $p -parent $general_group +set_property -dict [list \ + "widget" "comboBox" \ + "display_name" "DMA Interface Type" \ +] $p + +set p [ipgui::get_guiparamspec -name "NUM_OF_CHANNEL" -component $cc] +ipgui::move_param -component $cc -order 3 $p -parent $general_group +set_property -dict [list \ + "display_name" "Number of Audio Channels" \ +] $p + +set p [ipgui::get_guiparamspec -name "S_AXI_ADDRESS_WIDTH" -component $cc] +ipgui::move_param -component $cc -order 4 $p -parent $general_group +set_property -dict [list \ + "display_name" "AXI Address Width" \ +] $p + +ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "S_AXI_DATA_WIDTH" -component $cc] +ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "DEVICE_FAMILY" -component $cc] + +ipx::create_xgui_files $cc +ipx::save_core $cc diff --git a/adi_library/axi_i2s_adi/component.xml b/adi_library/axi_i2s_adi/component.xml new file mode 100644 index 00000000..a650c258 --- /dev/null +++ b/adi_library/axi_i2s_adi/component.xml @@ -0,0 +1,2313 @@ + + + analog.com + user + axi_i2s_adi + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TKEEP + + + m_axis_tkeep + + + + + TLAST + + + m_axis_tlast + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + + true + + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TLAST + + + s_axis_tlast + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + + true + + + + + + dma_req_rx_aclk + + + + + + + CLK + + + dma_req_rx_aclk + + + + + + ASSOCIATED_RESET + dma_req_rx_rstn + + + + + dma_req_tx_aclk + + + + + + + CLK + + + dma_req_tx_aclk + + + + + + ASSOCIATED_RESET + dma_req_tx_rstn + + + + + m_axis_aclk + + + + + + + CLK + + + m_axis_aclk + + + + + + ASSOCIATED_BUSIF + m_axis + + + + + s_axis_aclk + + + + + + + CLK + + + s_axis_aclk + + + + + + ASSOCIATED_BUSIF + s_axis + + + ASSOCIATED_RESET + s_axis_aresetn + + + + + dma_req_rx_rstn + + + + + + + RST + + + dma_req_rx_rstn + + + + + + POLARITY + ACTIVE_LOW + + + + + dma_req_tx_rstn + + + + + + + RST + + + dma_req_tx_rstn + + + + + + POLARITY + ACTIVE_LOW + + + + + s_axis_aresetn + + + + + + + RST + + + s_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + dma_ack_rx + + + + + + + TVALID + + + dma_req_rx_davalid + + + + + TREADY + + + dma_req_rx_daready + + + + + TUSER + + + dma_req_rx_datype + + + + + + + false + + + + + + dma_req_rx + + + + + + + TVALID + + + dma_req_rx_drvalid + + + + + TREADY + + + dma_req_rx_drready + + + + + TUSER + + + dma_req_rx_drtype + + + + + TLAST + + + dma_req_rx_drlast + + + + + + + false + + + + + + dma_req_rx_dma_ack_rx_signal_clock + dma_req_rx_dma_ack_rx_signal_clock + + + + + + + CLK + + + dma_req_rx_aclk + + + + + + ASSOCIATED_BUSIF + dma_req_rx:dma_ack_rx + + + ASSOCIATED_RESET + dma_req_rx_rstn + + + + + dma_req_rx_dma_ack_rx_signal_reset + dma_req_rx_dma_ack_rx_signal_reset + + + + + + + RST + + + dma_req_rx_rstn + + + + + + POLARITY + ACTIVE_LOW + + + + + dma_ack_tx + + + + + + + TVALID + + + dma_req_tx_davalid + + + + + TREADY + + + dma_req_tx_daready + + + + + TUSER + + + dma_req_tx_datype + + + + + + + false + + + + + + dma_req_tx + + + + + + + TVALID + + + dma_req_tx_drvalid + + + + + TREADY + + + dma_req_tx_drready + + + + + TUSER + + + dma_req_tx_drtype + + + + + TLAST + + + dma_req_tx_drlast + + + + + + + false + + + + + + dma_req_tx_dma_ack_tx_signal_clock + dma_req_tx_dma_ack_tx_signal_clock + + + + + + + CLK + + + dma_req_tx_aclk + + + + + + ASSOCIATED_BUSIF + dma_req_tx:dma_ack_tx + + + ASSOCIATED_RESET + dma_req_tx_rstn + + + + + dma_req_tx_dma_ack_tx_signal_reset + dma_req_tx_dma_ack_tx_signal_reset + + + + + + + RST + + + dma_req_tx_rstn + + + + + + POLARITY + ACTIVE_LOW + + + + + i2s + + + + + + + BCLK + + + bclk_o + + + + + LRCLK + + + lrclk_o + + + + + SDATA_OUT + + + sdata_o + + + + + SDATA_IN + + + sdata_i + + + + + + i2s_signal_clock + i2s_signal_clock + + + + + + + CLK + + + data_clk_i + + + + + + ASSOCIATED_BUSIF + i2s + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + axi_i2s_adi + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + a333f569 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + axi_i2s_adi + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + fcea8f7f + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 4823b664 + + + + + + + data_clk_i + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + bclk_o + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + lrclk_o + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sdata_o + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sdata_i + + in + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axis_tdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axis_tlast + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axis_tready + + in + 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xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_tx_davalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_tx_datype + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_tx_daready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_tx_drvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_tx_drtype + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_tx_drlast + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_tx_drready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_rx_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_rx_rstn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_rx_davalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_rx_datype + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_rx_daready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_rx_drvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_rx_drtype + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_rx_drlast + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_rx_drready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + SLOT_WIDTH + Slot Width + 24 + + + LRCLK_POL + Lrclk Pol + 0 + + + BCLK_POL + Bclk Pol + 0 + + + S_AXI_DATA_WIDTH + S Axi Data Width + 32 + + + S_AXI_ADDRESS_WIDTH + S Axi Address Width + 32 + + + DEVICE_FAMILY + Device Family + virtex6 + + + DMA_TYPE + Dma Type + 0 + + + NUM_OF_CHANNEL + Num Of Channel + 1 + + + HAS_TX + Has Tx + 1 + + + HAS_RX + Has Rx + 1 + + + + + + choice_list_388a2eb3 + 16 + 20 + 24 + 32 + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_2af915b7 + 0 + 1 + + + choice_pairs_c9229ef9 + 0 + 1 + + + + + xilinx_anylanguagesynthesis_view_fileset + + axi_i2s_adi_constr.xdc + xdc + + processing_order + late + + + + ../common/axi_ctrlif.vhd + vhdlSource + + + fifo_synchronizer.vhd + vhdlSource + + + i2s_clkgen.vhd + vhdlSource + + + i2s_tx.vhd + vhdlSource + + + i2s_rx.vhd + vhdlSource + + + i2s_controller.vhd + vhdlSource + + + ../common/dma_fifo.vhd + vhdlSource + + + ../common/axi_streaming_dma_rx_fifo.vhd + vhdlSource + + + ../common/axi_streaming_dma_tx_fifo.vhd + vhdlSource + + + ../common/pl330_dma_fifo.vhd + vhdlSource + + + axi_i2s_adi.vhd + vhdlSource + CHECKSUM_e6503276 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/axi_ctrlif.vhd + vhdlSource + + + fifo_synchronizer.vhd + vhdlSource + + + i2s_clkgen.vhd + vhdlSource + + + i2s_tx.vhd + vhdlSource + + + i2s_rx.vhd + vhdlSource + + + i2s_controller.vhd + vhdlSource + + + ../common/dma_fifo.vhd + vhdlSource + + + ../common/axi_streaming_dma_rx_fifo.vhd + vhdlSource + + + ../common/axi_streaming_dma_tx_fifo.vhd + vhdlSource + + + ../common/pl330_dma_fifo.vhd + vhdlSource + + + axi_i2s_adi.vhd + vhdlSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_i2s_adi_v1_0.tcl + tclSource + CHECKSUM_aab16c86 + XGUI_VERSION_2 + + + + ADI AXI I2S Controller + + + SLOT_WIDTH + Slot Width + 24 + + + LRCLK_POL + Left-Right Clock Polarity + 0 + + + BCLK_POL + Bit Clock Polarity + 0 + + + S_AXI_DATA_WIDTH + S Axi Data Width + 32 + + + S_AXI_ADDRESS_WIDTH + AXI Address Width + 32 + + + DEVICE_FAMILY + Device Family + virtex6 + + + DMA_TYPE + DMA Interface Type + 0 + + + NUM_OF_CHANNEL + Number of Audio Channels + 1 + + + HAS_TX + Enable I2S Transmitter Support + 1 + + + HAS_RX + Enable I2S Receiver Support + 1 + + + Component_Name + axi_i2s_adi_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + ADI AXI I2S Controller + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:47:36Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_i2s_adi/fifo_synchronizer.vhd b/adi_library/axi_i2s_adi/fifo_synchronizer.vhd new file mode 100644 index 00000000..336e74d9 --- /dev/null +++ b/adi_library/axi_i2s_adi/fifo_synchronizer.vhd @@ -0,0 +1,129 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +-- +-- In this HDL repository, there are many different and unique modules, consisting +-- of various HDL (Verilog or VHDL) components. The individual modules are +-- developed independently, and may be accompanied by separate and unique license +-- terms. +-- +-- The user should read each of these license terms, and understand the +-- freedoms and responsibilities that he or she has by using this source/core. +-- +-- This core is distributed in the hope that it will be useful, but WITHOUT ANY +-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +-- A PARTICULAR PURPOSE. +-- +-- Redistribution and use of source or resulting binaries, with or without modification +-- of this file, are permitted under one of the following two license terms: +-- +-- 1. The GNU General Public License version 2 as published by the +-- Free Software Foundation, which can be found in the top level directory +-- of this repository (LICENSE_GPL2), and also online at: +-- +-- +-- OR +-- +-- 2. An ADI specific BSD license, which can be found in the top level directory +-- of this repository (LICENSE_ADIBSD), and also on-line at: +-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +-- This will allow to generate bit files and not release the source code, +-- as long as it attaches to an ADI device. +-- +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; + +entity fifo_synchronizer is + generic ( + DEPTH : integer := 4; + WIDTH : integer := 2 + ); + port ( + + in_clk : in std_logic; + in_resetn : in std_logic; + in_data : in std_logic_vector(WIDTH - 1 downto 0); + in_tick : in std_logic; + + out_clk : in std_logic; + out_resetn : in std_logic; + out_data : out std_logic_vector(WIDTH - 1 downto 0); + out_tick : out std_logic + ); + +end fifo_synchronizer; + +architecture impl of fifo_synchronizer is + type DATA_SYNC_FIFO_TYPE is array (0 to DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0); + signal fifo: DATA_SYNC_FIFO_TYPE; + + signal rd_addr : natural range 0 to DEPTH - 1; + signal wr_addr : natural range 0 to DEPTH - 1; + + signal cdc_sync_stage0_tick : std_logic := '0'; + signal cdc_sync_stage1_tick : std_logic; + signal cdc_sync_stage2_tick : std_logic; + signal cdc_sync_stage3_tick : std_logic; + signal tick : std_logic; +begin + + process (in_clk) + begin + if rising_edge(in_clk) then + if in_tick = '1' then + cdc_sync_stage0_tick <= not cdc_sync_stage0_tick; + fifo(wr_addr) <= in_data; + end if; + end if; + end process; + + process (in_clk) + begin + if rising_edge(in_clk) then + if in_resetn = '0' then + wr_addr <= 0; + else + if in_tick = '1' then + wr_addr <= (wr_addr + 1) mod DEPTH; + end if; + end if; + end if; + end process; + + process (out_clk) + begin + if rising_edge(out_clk) then + cdc_sync_stage1_tick <= cdc_sync_stage0_tick; + cdc_sync_stage2_tick <= cdc_sync_stage1_tick; + cdc_sync_stage3_tick <= cdc_sync_stage2_tick; + end if; + end process; + + tick <= cdc_sync_stage2_tick xor cdc_sync_stage3_tick; + out_tick <= tick; + + process (out_clk) + begin + if rising_edge(out_clk) then + if tick = '1' then + out_data <= fifo(rd_addr); + end if; + end if; + end process; + + process (out_clk) + begin + if rising_edge(out_clk) then + if out_resetn = '0' then + rd_addr <= 0; + else + if tick = '1' then + rd_addr <= (rd_addr + 1) mod DEPTH; + end if; + end if; + end if; + end process; +end; diff --git a/adi_library/axi_i2s_adi/i2s.xml b/adi_library/axi_i2s_adi/i2s.xml new file mode 100644 index 00000000..feb8ac55 --- /dev/null +++ b/adi_library/axi_i2s_adi/i2s.xml @@ -0,0 +1,13 @@ + + + analog.com + interface + i2s + 1.0 + false + false + 1 + 1 + diff --git a/adi_library/axi_i2s_adi/i2s_clkgen.vhd b/adi_library/axi_i2s_adi/i2s_clkgen.vhd new file mode 100644 index 00000000..9fe1bac1 --- /dev/null +++ b/adi_library/axi_i2s_adi/i2s_clkgen.vhd @@ -0,0 +1,130 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +-- +-- In this HDL repository, there are many different and unique modules, consisting +-- of various HDL (Verilog or VHDL) components. The individual modules are +-- developed independently, and may be accompanied by separate and unique license +-- terms. +-- +-- The user should read each of these license terms, and understand the +-- freedoms and responsibilities that he or she has by using this source/core. +-- +-- This core is distributed in the hope that it will be useful, but WITHOUT ANY +-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +-- A PARTICULAR PURPOSE. +-- +-- Redistribution and use of source or resulting binaries, with or without modification +-- of this file, are permitted under one of the following two license terms: +-- +-- 1. The GNU General Public License version 2 as published by the +-- Free Software Foundation, which can be found in the top level directory +-- of this repository (LICENSE_GPL2), and also online at: +-- +-- +-- OR +-- +-- 2. An ADI specific BSD license, which can be found in the top level directory +-- of this repository (LICENSE_ADIBSD), and also on-line at: +-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +-- This will allow to generate bit files and not release the source code, +-- as long as it attaches to an ADI device. +-- +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; + +entity i2s_clkgen is + port( + clk : in std_logic; -- System clock + resetn : in std_logic; -- System reset + + enable : in Boolean ; -- Enable clockgen + + tick : in std_logic; + + bclk_div_rate : in natural range 0 to 255; + lrclk_div_rate : in natural range 0 to 255; + + bclk : out std_logic; -- Bit Clock + lrclk : out std_logic; -- Frame Clock + channel_sync : out std_logic; + frame_sync : out std_logic + ); +end i2s_clkgen; + +architecture Behavioral of i2s_clkgen is + signal reset_int : Boolean; + + signal prev_bclk_div_rate : natural range 0 to 255; + signal prev_lrclk_div_rate : natural range 0 to 255; + + signal bclk_count : natural range 0 to 255; + signal lrclk_count : natural range 0 to 255; + + signal bclk_int : std_logic; + signal lrclk_int : std_logic; + + signal lrclk_tick : Boolean; +begin + + reset_int <= resetn = '0' or not enable; + + bclk <= bclk_int; + lrclk <= lrclk_int; + +----------------------------------------------------------------------------------- +-- Serial clock generation BCLK_O +----------------------------------------------------------------------------------- + bclk_gen: process(clk) + begin + if rising_edge(clk) then + prev_bclk_div_rate <= bclk_div_rate; + if reset_int then -- or (bclk_div_rate /= prev_bclk_div_rate) then + bclk_int <= '1'; + bclk_count <= bclk_div_rate; + else + if tick = '1' then + if bclk_count = bclk_div_rate then + bclk_count <= 0; + bclk_int <= not bclk_int; + else + bclk_count <= bclk_count + 1; + end if; + end if; + end if; + end if; + end process bclk_gen; + + lrclk_tick <= tick = '1' and bclk_count = bclk_div_rate and bclk_int = '1'; + + channel_sync <= '1' when lrclk_count = 1 else '0'; + frame_sync <= '1' when lrclk_count = 1 and lrclk_int = '0' else '0'; + +----------------------------------------------------------------------------------- +-- Frame clock generator LRCLK_O +----------------------------------------------------------------------------------- + lrclk_gen: process(clk) + begin + if rising_edge(clk) then + prev_lrclk_div_rate <= lrclk_div_rate; + -- Reset + if reset_int then -- or lrclk_div_rate /= prev_lrclk_div_rate then + lrclk_int <= '1'; + lrclk_count <= lrclk_div_rate; + else + if lrclk_tick then + if lrclk_count = lrclk_div_rate then + lrclk_count <= 0; + lrclk_int <= not lrclk_int; + else + lrclk_count <= lrclk_count + 1; + end if; + end if; + end if; + end if; + end process lrclk_gen; + +end Behavioral; diff --git a/adi_library/axi_i2s_adi/i2s_controller.vhd b/adi_library/axi_i2s_adi/i2s_controller.vhd new file mode 100644 index 00000000..9eb439bb --- /dev/null +++ b/adi_library/axi_i2s_adi/i2s_controller.vhd @@ -0,0 +1,292 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +-- +-- In this HDL repository, there are many different and unique modules, consisting +-- of various HDL (Verilog or VHDL) components. The individual modules are +-- developed independently, and may be accompanied by separate and unique license +-- terms. +-- +-- The user should read each of these license terms, and understand the +-- freedoms and responsibilities that he or she has by using this source/core. +-- +-- This core is distributed in the hope that it will be useful, but WITHOUT ANY +-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +-- A PARTICULAR PURPOSE. +-- +-- Redistribution and use of source or resulting binaries, with or without modification +-- of this file, are permitted under one of the following two license terms: +-- +-- 1. The GNU General Public License version 2 as published by the +-- Free Software Foundation, which can be found in the top level directory +-- of this repository (LICENSE_GPL2), and also online at: +-- +-- +-- OR +-- +-- 2. An ADI specific BSD license, which can be found in the top level directory +-- of this repository (LICENSE_ADIBSD), and also on-line at: +-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +-- This will allow to generate bit files and not release the source code, +-- as long as it attaches to an ADI device. +-- +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; + +library work; +use work.fifo_synchronizer; +use work.i2s_clkgen; +use work.i2s_tx; +use work.i2s_rx; + +entity i2s_controller is + generic( + C_SLOT_WIDTH : integer := 24; -- Width of one Slot + C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge) + C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge) + C_NUM_CH : integer := 1; + C_HAS_TX : integer := 1; + C_HAS_RX : integer := 1 + ); + port( + clk : in std_logic; -- System clock + resetn : in std_logic; -- System reset + + data_clk : in std_logic; -- Data clock should be less than clk / 4 + bclk_o : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Bit Clock + lrclk_o : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Frame Clock + sdata_o : out std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Output + sdata_i : in std_logic_vector(C_NUM_CH - 1 downto 0); -- Serial Data Input + + tx_enable : in Boolean; -- Enable TX + tx_ack : out std_logic; -- Request new Slot Data + tx_stb : in std_logic; -- Request new Slot Data + tx_data : in std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data in + + rx_enable : in Boolean; -- Enable RX + rx_ack : in std_logic; + rx_stb : out std_logic; -- Valid Slot Data + rx_data : out std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data out + + -- Runtime parameter + bclk_div_rate : in natural range 0 to 255; + lrclk_div_rate : in natural range 0 to 255 + ); +end i2s_controller; + +architecture Behavioral of i2s_controller is +constant NUM_TX : integer := C_HAS_TX * C_NUM_CH; +constant NUM_RX : integer := C_HAS_RX * C_NUM_CH; + +signal enable : Boolean; + +signal cdc_sync_stage0_tick : std_logic := '0'; +signal cdc_sync_stage1_tick : std_logic; +signal cdc_sync_stage2_tick : std_logic; +signal cdc_sync_stage3_tick : std_logic; + +signal BCLK_O_int : std_logic; +signal LRCLK_O_int : std_logic; + +signal tx_bclk : std_logic; +signal tx_lrclk : std_logic; +signal tx_sdata : std_logic_vector(C_NUM_CH - 1 downto 0); +signal tx_tick : std_logic; +signal tx_channel_sync : std_logic; +signal tx_frame_sync : std_logic; + +signal const_1 : std_logic; +signal bclk_tick : std_logic; + +signal rx_bclk : std_logic; +signal rx_lrclk : std_logic; +signal rx_sdata : std_logic_vector(NUM_RX - 1 downto 0); +signal rx_channel_sync : std_logic; +signal rx_frame_sync : std_logic; + +signal tx_sync_fifo_out : std_logic_vector(3 + NUM_TX downto 0); +signal tx_sync_fifo_in : std_logic_vector(3 + NUM_TX downto 0); +signal rx_sync_fifo_out : std_logic_vector(3 + NUM_RX downto 0); +signal rx_sync_fifo_in : std_logic_vector(3 + NUM_RX downto 0); + +signal data_resetn : std_logic; +signal data_reset_vec : std_logic_vector(2 downto 0); + +begin + enable <= rx_enable or tx_enable; + + const_1 <= '1'; + process (data_clk, resetn) + begin + if resetn = '0' then + data_reset_vec <= (others => '1'); + elsif rising_edge(data_clk) then + data_reset_vec(2 downto 1) <= data_reset_vec(1 downto 0); + data_reset_vec(0) <= '0'; + end if; + end process; + + data_resetn <= not data_reset_vec(2); + + -- Generate tick signal in the DATA_CLK_I domain + process (data_clk) + begin + if rising_edge(data_clk) then + cdc_sync_stage0_tick <= not cdc_sync_stage0_tick; + end if; + end process; + + process (clk) + begin + if rising_edge(clk) then + cdc_sync_stage1_tick <= cdc_sync_stage0_tick; + cdc_sync_stage2_tick <= cdc_sync_stage1_tick; + cdc_sync_stage3_tick <= cdc_sync_stage2_tick; + end if; + end process; + + tx_tick <= cdc_sync_stage2_tick xor cdc_sync_stage3_tick; + + tx_sync_fifo_in(0) <= tx_channel_sync; + tx_sync_fifo_in(1) <= tx_frame_sync; + tx_sync_fifo_in(2) <= tx_bclk; + tx_sync_fifo_in(3) <= tx_lrclk; + tx_sync_fifo_in(3 + NUM_TX downto 4) <= tx_sdata; + + + process (data_clk) + begin + if rising_edge(data_clk) then + if data_resetn = '0' then + bclk_o <= (others => '1'); + lrclk_o <= (others => '1'); + sdata_o <= (others => '0'); + else + if C_BCLK_POL = 0 then + bclk_o <= (others => tx_sync_fifo_out(2)); + else + bclk_o <= (others => not tx_sync_fifo_out(2)); + end if; + + if C_LRCLK_POL = 0 then + lrclk_o <= (others => tx_sync_fifo_out(3)); + else + lrclk_o <= (others => not tx_sync_fifo_out(3)); + end if; + + if C_HAS_TX = 1 then + sdata_o <= tx_sync_fifo_out(3 + NUM_TX downto 4); + end if; + + if C_HAS_RX = 1 then + rx_sync_fifo_in(3 downto 0) <= tx_sync_fifo_out(3 downto 0); + rx_sync_fifo_in(3 + NUM_RX downto 4) <= sdata_i; + end if; + end if; + end if; + end process; + + tx_sync: entity fifo_synchronizer + generic map ( + DEPTH => 4, + WIDTH => NUM_TX + 4 + ) + port map ( + in_resetn => resetn, + in_clk => clk, + in_data => tx_sync_fifo_in, + in_tick => tx_tick, + + out_resetn => data_resetn, + out_clk => data_clk, + out_data => tx_sync_fifo_out + ); + + clkgen: entity i2s_clkgen + port map( + clk => clk, + resetn => resetn, + enable => enable, + tick => tx_tick, + + bclk_div_rate => bclk_div_rate, + lrclk_div_rate => lrclk_div_rate, + + channel_sync => tx_channel_sync, + frame_sync => tx_frame_sync, + + bclk => tx_bclk, + lrclk => tx_lrclk + ); + + tx_gen: if C_HAS_TX = 1 generate + tx: entity i2s_tx + generic map ( + C_SLOT_WIDTH => C_SLOT_WIDTH, + C_NUM => NUM_TX + ) + port map ( + clk => clk, + resetn => resetn, + enable => tx_enable, + + channel_sync => tx_channel_sync, + frame_sync => tx_frame_sync, + bclk => tx_bclk, + sdata => tx_sdata, + + ack => tx_ack, + stb => tx_stb, + data => tx_data + ); + end generate; + + rx_gen: if C_HAS_RX = 1 generate + rx: entity i2s_rx + generic map ( + C_SLOT_WIDTH => C_SLOT_WIDTH, + C_NUM => NUM_RX + ) + port map ( + clk => clk, + resetn => resetn, + enable => rx_enable, + + channel_sync => rx_channel_sync, + frame_sync => rx_frame_sync, + bclk => rx_bclk, + sdata => rx_sdata, + + ack => rx_ack, + stb => rx_stb, + data => rx_data + ); + + rx_channel_sync <= rx_sync_fifo_out(0); + rx_frame_sync <= rx_sync_fifo_out(1); + rx_bclk <= rx_sync_fifo_out(2); + rx_lrclk <= rx_sync_fifo_out(3); + rx_sdata <= rx_sync_fifo_out(3 + NUM_RX downto 4); + + rx_sync: entity fifo_synchronizer + generic map ( + DEPTH => 4, + WIDTH => NUM_RX + 4 + ) + port map ( + in_resetn => data_resetn, + in_clk => data_clk, + in_data => rx_sync_fifo_in, + in_tick => const_1, + + out_resetn => resetn, + out_clk => clk, + out_data => rx_sync_fifo_out + ); + + end generate; + +end Behavioral; diff --git a/adi_library/axi_i2s_adi/i2s_rtl.xml b/adi_library/axi_i2s_adi/i2s_rtl.xml new file mode 100644 index 00000000..5a77e9b9 --- /dev/null +++ b/adi_library/axi_i2s_adi/i2s_rtl.xml @@ -0,0 +1,61 @@ + + + analog.com + interface + i2s_rtl + 1.0 + + + + BCLK + + + required + 1 + + + required + 1 + in + + + + + LRCLK + + + required + 1 + + + required + 1 + in + + + + + SDATA_OUT + + + + in + + + + + SDATA_IN + + + in + + + + + + diff --git a/adi_library/axi_i2s_adi/i2s_rx.vhd b/adi_library/axi_i2s_adi/i2s_rx.vhd new file mode 100644 index 00000000..77ab45c6 --- /dev/null +++ b/adi_library/axi_i2s_adi/i2s_rx.vhd @@ -0,0 +1,177 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +-- +-- In this HDL repository, there are many different and unique modules, consisting +-- of various HDL (Verilog or VHDL) components. The individual modules are +-- developed independently, and may be accompanied by separate and unique license +-- terms. +-- +-- The user should read each of these license terms, and understand the +-- freedoms and responsibilities that he or she has by using this source/core. +-- +-- This core is distributed in the hope that it will be useful, but WITHOUT ANY +-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +-- A PARTICULAR PURPOSE. +-- +-- Redistribution and use of source or resulting binaries, with or without modification +-- of this file, are permitted under one of the following two license terms: +-- +-- 1. The GNU General Public License version 2 as published by the +-- Free Software Foundation, which can be found in the top level directory +-- of this repository (LICENSE_GPL2), and also online at: +-- +-- +-- OR +-- +-- 2. An ADI specific BSD license, which can be found in the top level directory +-- of this repository (LICENSE_ADIBSD), and also on-line at: +-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +-- This will allow to generate bit files and not release the source code, +-- as long as it attaches to an ADI device. +-- +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity i2s_rx is + generic( + C_SLOT_WIDTH : integer := 24; -- Width of one Slot + C_NUM : integer := 1 + ); + port( + clk : in std_logic; -- System clock + resetn : in std_logic; -- System reset + enable : in Boolean; -- Enable RX + + bclk : in std_logic; -- Bit Clock + channel_sync : in std_logic; -- Channel Sync + frame_sync : in std_logic; -- Frame Sync + sdata : in std_logic_vector(C_NUM - 1 downto 0); -- Serial Data Output + + stb : out std_logic; -- Data available + ack : in std_logic; -- Data has been consumed + data : out std_logic_vector(C_SLOT_WIDTH-1 downto 0) -- Slot Data in + ); +end i2s_rx; + +architecture Behavioral of i2s_rx is + type mem is array (0 to C_NUM - 1) of std_logic_vector(31 downto 0); + type mem_latched is array (0 to C_NUM - 1) of std_logic_vector(C_SLOT_WIDTH - 1 downto 0); + signal data_int : mem; + signal data_latched : mem_latched; + signal reset_int : Boolean; + signal enable_int : Boolean; + + signal bit_sync : std_logic; + signal channel_sync_int : std_logic; + signal frame_sync_int : std_logic; + + signal bclk_d1 : std_logic; + + type sequencer_state_type is (IDLE, ACTIVE); + signal sequencer_state : sequencer_state_type; + signal seq : natural range 0 to C_NUM - 1; + + signal ovf_frame_cnt : natural range 0 to 1; +begin + + reset_int <= (resetn = '0') or not enable; + + process (clk) + begin + if rising_edge(clk) then + if resetn = '0' then + bclk_d1 <= '0'; + else + bclk_d1 <= bclk; + end if; + end if; + end process; + + bit_sync <= (bclk xor bclk_d1) and bclk; + channel_sync_int <= channel_sync and bit_sync; + frame_sync_int <= frame_sync and bit_sync; + + stb <= '1' when sequencer_state = ACTIVE else '0'; + + sequencer: process (clk) + begin + if rising_edge(clk) then + if reset_int or not enable_int then + sequencer_state <= IDLE; + ovf_frame_cnt <= 0; + seq <= 0; + else + case sequencer_state is + when IDLE => + if channel_sync_int = '1' then + if ovf_frame_cnt = 0 then + sequencer_state <= ACTIVE; + else + ovf_frame_cnt <= (ovf_frame_cnt + 1) mod 2; + end if; + end if; + when ACTIVE => + -- The unlikely event the last ack came in in the same clock + -- cyclce as the channel sync signal will still be treated + -- as an overflow. This keeps the logic simple + if ack = '1' then + if seq = C_NUM - 1 then + sequencer_state <= IDLE; + seq <= 0; + else + seq <= seq + 1; + end if; + end if; + if channel_sync_int = '1' then + ovf_frame_cnt <= (ovf_frame_cnt + 1) mod 2; + end if; + end case; + end if; + end if; + end process; + + data <= data_latched(seq); + + gen: for i in 0 to C_NUM - 1 generate + + unserialize_data: process(clk) + begin + if rising_edge(clk) then + if reset_int then + data_int(i) <= (others => '0'); + elsif bit_sync = '1' then + if channel_sync = '1' then + if sequencer_state = IDLE then + data_latched(i) <= data_int(i)(31 downto 32 - C_SLOT_WIDTH); +-- data_latched(i) <= data_int(i)(31 downto 32 - +-- C_SLOT_WIDTH + 8) & +-- std_logic_vector(to_unsigned(i+1,8)); + end if; + end if; + data_int(i) <= data_int(i)(30 downto 0) & sdata(i); + end if; + end if; + end process unserialize_data; + end generate; + + enable_sync: process (clk) + begin + if rising_edge(clk) then + if reset_int then + enable_int <= False; + else + if enable and frame_sync_int = '1' then + enable_int <= True; + elsif not enable then + enable_int <= False; + end if; + end if; + end if; + end process enable_sync; + +end Behavioral; diff --git a/adi_library/axi_i2s_adi/i2s_tx.vhd b/adi_library/axi_i2s_adi/i2s_tx.vhd new file mode 100644 index 00000000..10ca3ce4 --- /dev/null +++ b/adi_library/axi_i2s_adi/i2s_tx.vhd @@ -0,0 +1,131 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +-- +-- In this HDL repository, there are many different and unique modules, consisting +-- of various HDL (Verilog or VHDL) components. The individual modules are +-- developed independently, and may be accompanied by separate and unique license +-- terms. +-- +-- The user should read each of these license terms, and understand the +-- freedoms and responsibilities that he or she has by using this source/core. +-- +-- This core is distributed in the hope that it will be useful, but WITHOUT ANY +-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +-- A PARTICULAR PURPOSE. +-- +-- Redistribution and use of source or resulting binaries, with or without modification +-- of this file, are permitted under one of the following two license terms: +-- +-- 1. The GNU General Public License version 2 as published by the +-- Free Software Foundation, which can be found in the top level directory +-- of this repository (LICENSE_GPL2), and also online at: +-- +-- +-- OR +-- +-- 2. An ADI specific BSD license, which can be found in the top level directory +-- of this repository (LICENSE_ADIBSD), and also on-line at: +-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +-- This will allow to generate bit files and not release the source code, +-- as long as it attaches to an ADI device. +-- +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; + +entity i2s_tx is + generic( + C_SLOT_WIDTH : integer := 24; -- Width of one Slot + C_NUM : integer := 1 + ); + port( + clk : in std_logic; -- System clock + resetn : in std_logic; -- System reset + enable : in Boolean; -- Enable TX + + bclk : in std_logic; -- Bit Clock + channel_sync : in std_logic; -- Channel Sync + frame_sync : in std_logic; -- Frame Sync + sdata : out std_logic_vector(C_NUM - 1 downto 0); -- Serial Data Output + + ack : out std_logic; -- Request new Slot Data + stb : in std_logic; -- Request new Slot Data + data : in std_logic_vector(C_SLOT_WIDTH-1 downto 0) -- Slot Data in + ); +end i2s_tx; + +architecture Behavioral of i2s_tx is + type mem is array (0 to C_NUM - 1) of std_logic_vector(31 downto 0); + signal data_int : mem; + signal reset_int : Boolean; + signal enable_int : Boolean; + + signal bit_sync : std_logic; + signal channel_sync_int : std_logic; + signal frame_sync_int : std_logic; + signal channel_sync_int_d1 : std_logic; + + signal bclk_d1 : std_logic; +begin + + reset_int <= resetn = '0' or not enable; + + process (clk) + begin + if rising_edge(clk) then + if resetn = '0' then + bclk_d1 <= '0'; + channel_sync_int_d1 <= '0'; + else + bclk_d1 <= bclk; + channel_sync_int_d1 <= channel_sync_int; + end if; + end if; + end process; + + bit_sync <= (bclk xor bclk_d1) and not bclk; + channel_sync_int <= channel_sync and bit_sync; + frame_sync_int <= frame_sync and bit_sync; + + ack <= '1' when channel_sync_int_d1 = '1' and enable_int else '0'; + + gen: for i in 0 to C_NUM - 1 generate + + serialize_data: process(clk) + begin + if rising_edge(clk) then + if reset_int then + data_int(i)(31 downto 0) <= (others => '0'); + elsif bit_sync = '1' then + if channel_sync_int = '1' then + data_int(i)(31 downto 32-C_SLOT_WIDTH) <= data; + data_int(i)(31-C_SLOT_WIDTH downto 0) <= (others => '0'); + else + data_int(i) <= data_int(i)(30 downto 0) & '0'; + end if; + end if; + end if; + end process serialize_data; + sdata(i) <= data_int(i)(31) when enable_int else '0'; + + end generate; + + enable_sync: process (clk) + begin + if rising_edge(clk) then + if reset_int then + enable_int <= False; + else + if enable and frame_sync_int = '1' and stb = '1' then + enable_int <= True; + elsif not enable then + enable_int <= False; + end if; + end if; + end if; + end process; + +end Behavioral; diff --git a/adi_library/axi_i2s_adi/xgui/axi_i2s_adi_v1_0.tcl b/adi_library/axi_i2s_adi/xgui/axi_i2s_adi_v1_0.tcl new file mode 100644 index 00000000..ff4ad2cd --- /dev/null +++ b/adi_library/axi_i2s_adi/xgui/axi_i2s_adi_v1_0.tcl @@ -0,0 +1,164 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + #Adding Group + set I2S_Configuration [ipgui::add_group $IPINST -name "I2S Configuration" -parent ${Page_0}] + ipgui::add_param $IPINST -name "SLOT_WIDTH" -parent ${I2S_Configuration} -widget comboBox + ipgui::add_param $IPINST -name "LRCLK_POL" -parent ${I2S_Configuration} -widget comboBox + ipgui::add_param $IPINST -name "BCLK_POL" -parent ${I2S_Configuration} -widget comboBox + + #Adding Group + set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${Page_0}] + ipgui::add_param $IPINST -name "HAS_RX" -parent ${General_Configuration} -widget checkBox + ipgui::add_param $IPINST -name "HAS_TX" -parent ${General_Configuration} -widget checkBox + ipgui::add_param $IPINST -name "DMA_TYPE" -parent ${General_Configuration} -widget comboBox + ipgui::add_param $IPINST -name "NUM_OF_CHANNEL" -parent ${General_Configuration} + ipgui::add_param $IPINST -name "S_AXI_ADDRESS_WIDTH" -parent ${General_Configuration} + + + +} + +proc update_PARAM_VALUE.BCLK_POL { PARAM_VALUE.BCLK_POL } { + # Procedure called to update BCLK_POL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BCLK_POL { PARAM_VALUE.BCLK_POL } { + # Procedure called to validate BCLK_POL + return true +} + +proc update_PARAM_VALUE.DEVICE_FAMILY { PARAM_VALUE.DEVICE_FAMILY } { + # Procedure called to update DEVICE_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEVICE_FAMILY { PARAM_VALUE.DEVICE_FAMILY } { + # Procedure called to validate DEVICE_FAMILY + return true +} + +proc update_PARAM_VALUE.DMA_TYPE { PARAM_VALUE.DMA_TYPE } { + # Procedure called to update DMA_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_TYPE { PARAM_VALUE.DMA_TYPE } { + # Procedure called to validate DMA_TYPE + return true +} + +proc update_PARAM_VALUE.HAS_RX { PARAM_VALUE.HAS_RX } { + # Procedure called to update HAS_RX when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.HAS_RX { PARAM_VALUE.HAS_RX } { + # Procedure called to validate HAS_RX + return true +} + +proc update_PARAM_VALUE.HAS_TX { PARAM_VALUE.HAS_TX } { + # Procedure called to update HAS_TX when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.HAS_TX { PARAM_VALUE.HAS_TX } { + # Procedure called to validate HAS_TX + return true +} + +proc update_PARAM_VALUE.LRCLK_POL { PARAM_VALUE.LRCLK_POL } { + # Procedure called to update LRCLK_POL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.LRCLK_POL { PARAM_VALUE.LRCLK_POL } { + # Procedure called to validate LRCLK_POL + return true +} + +proc update_PARAM_VALUE.NUM_OF_CHANNEL { PARAM_VALUE.NUM_OF_CHANNEL } { + # Procedure called to update NUM_OF_CHANNEL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_CHANNEL { PARAM_VALUE.NUM_OF_CHANNEL } { + # Procedure called to validate NUM_OF_CHANNEL + return true +} + +proc update_PARAM_VALUE.SLOT_WIDTH { PARAM_VALUE.SLOT_WIDTH } { + # Procedure called to update SLOT_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SLOT_WIDTH { PARAM_VALUE.SLOT_WIDTH } { + # Procedure called to validate SLOT_WIDTH + return true +} + +proc update_PARAM_VALUE.S_AXI_ADDRESS_WIDTH { PARAM_VALUE.S_AXI_ADDRESS_WIDTH } { + # Procedure called to update S_AXI_ADDRESS_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.S_AXI_ADDRESS_WIDTH { PARAM_VALUE.S_AXI_ADDRESS_WIDTH } { + # Procedure called to validate S_AXI_ADDRESS_WIDTH + return true +} + +proc update_PARAM_VALUE.S_AXI_DATA_WIDTH { PARAM_VALUE.S_AXI_DATA_WIDTH } { + # Procedure called to update S_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.S_AXI_DATA_WIDTH { PARAM_VALUE.S_AXI_DATA_WIDTH } { + # Procedure called to validate S_AXI_DATA_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.SLOT_WIDTH { MODELPARAM_VALUE.SLOT_WIDTH PARAM_VALUE.SLOT_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SLOT_WIDTH}] ${MODELPARAM_VALUE.SLOT_WIDTH} +} + +proc update_MODELPARAM_VALUE.LRCLK_POL { MODELPARAM_VALUE.LRCLK_POL PARAM_VALUE.LRCLK_POL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LRCLK_POL}] ${MODELPARAM_VALUE.LRCLK_POL} +} + +proc update_MODELPARAM_VALUE.BCLK_POL { MODELPARAM_VALUE.BCLK_POL PARAM_VALUE.BCLK_POL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BCLK_POL}] ${MODELPARAM_VALUE.BCLK_POL} +} + +proc update_MODELPARAM_VALUE.S_AXI_DATA_WIDTH { MODELPARAM_VALUE.S_AXI_DATA_WIDTH PARAM_VALUE.S_AXI_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.S_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.S_AXI_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.S_AXI_ADDRESS_WIDTH { MODELPARAM_VALUE.S_AXI_ADDRESS_WIDTH PARAM_VALUE.S_AXI_ADDRESS_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.S_AXI_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.S_AXI_ADDRESS_WIDTH} +} + +proc update_MODELPARAM_VALUE.DEVICE_FAMILY { MODELPARAM_VALUE.DEVICE_FAMILY PARAM_VALUE.DEVICE_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEVICE_FAMILY}] ${MODELPARAM_VALUE.DEVICE_FAMILY} +} + +proc update_MODELPARAM_VALUE.DMA_TYPE { MODELPARAM_VALUE.DMA_TYPE PARAM_VALUE.DMA_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_TYPE}] ${MODELPARAM_VALUE.DMA_TYPE} +} + +proc update_MODELPARAM_VALUE.NUM_OF_CHANNEL { MODELPARAM_VALUE.NUM_OF_CHANNEL PARAM_VALUE.NUM_OF_CHANNEL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_CHANNEL}] ${MODELPARAM_VALUE.NUM_OF_CHANNEL} +} + +proc update_MODELPARAM_VALUE.HAS_TX { MODELPARAM_VALUE.HAS_TX PARAM_VALUE.HAS_TX } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.HAS_TX}] ${MODELPARAM_VALUE.HAS_TX} +} + +proc update_MODELPARAM_VALUE.HAS_RX { MODELPARAM_VALUE.HAS_RX PARAM_VALUE.HAS_RX } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.HAS_RX}] ${MODELPARAM_VALUE.HAS_RX} +} + diff --git a/adi_library/axi_intr_monitor/Makefile b/adi_library/axi_intr_monitor/Makefile new file mode 100644 index 00000000..29f20bfa --- /dev/null +++ b/adi_library/axi_intr_monitor/Makefile @@ -0,0 +1,14 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_intr_monitor + +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += axi_intr_monitor.v + +XILINX_DEPS += axi_intr_monitor_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_intr_monitor/axi_intr_monitor.v b/adi_library/axi_intr_monitor/axi_intr_monitor.v new file mode 100644 index 00000000..0b01628f --- /dev/null +++ b/adi_library/axi_intr_monitor/axi_intr_monitor.v @@ -0,0 +1,221 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_intr_monitor ( + output irq, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot +); + + parameter VERSION = 32'h00010000; + + reg [31:0] up_rdata = 'd0; + reg up_wack = 'd0; + reg up_rack = 'd0; + reg pwm_gen_clk = 'd0; + reg [31:0] scratch = 'd0; + reg [31:0] control = 'd0; + reg interrupt = 'd0; + reg [31:0] counter_to_interrupt = 'd0; + reg [31:0] counter_to_interrupt_cnt = 'd0; + reg [31:0] counter_from_interrupt = 'd0; + reg [31:0] counter_interrupt_handling = 'd0; + reg [31:0] min_interrupt_handling = 'd0; + reg [31:0] max_interrupt_handling = 'd0; + reg interrupt_d1 = 'd0; + reg arm_counter = 'd0; + reg counter_active = 'd0; + + wire up_rreq_s; + wire up_wreq_s; + wire [13:0] up_raddr_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + + assign irq = interrupt; + + always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin + if (s_axi_aresetn == 1'b0 || control[0] == 1'b0) begin + counter_to_interrupt_cnt <= 0; + counter_interrupt_handling <= 'd0; + counter_from_interrupt <= 32'h0; + min_interrupt_handling <= 'd0; + max_interrupt_handling <= 'd0; + interrupt_d1 <= 0; + counter_active <= 1'b0; + end else begin + interrupt_d1 <= irq; + + if (arm_counter == 1'b1) begin + counter_to_interrupt_cnt <= counter_to_interrupt; + counter_active <= 1'b1; + end else if (counter_to_interrupt_cnt > 0) begin + counter_to_interrupt_cnt <= counter_to_interrupt_cnt - 1; + end else begin + counter_active <= 1'b0; + end + + if (irq == 1'b1 && interrupt_d1 == 1'b0) begin + counter_from_interrupt <= 32'h0; + end else begin + counter_from_interrupt <= counter_from_interrupt + 1; + end + + if (irq == 1'b0 && interrupt_d1 == 1'b1) begin + counter_interrupt_handling <= counter_from_interrupt; + if (min_interrupt_handling > counter_from_interrupt) begin + min_interrupt_handling <= counter_from_interrupt; + end + if (max_interrupt_handling < counter_from_interrupt) begin + max_interrupt_handling <= counter_from_interrupt; + end + end + end + end + + always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin + if (s_axi_aresetn == 0) begin + up_wack <= 1'b0; + scratch <= 'd0; + control <= 'd0; + interrupt <= 'd0; + counter_to_interrupt <= 'd0; + arm_counter <= 'd0; + end else begin + up_wack <= up_wreq_s; + arm_counter <= 1'b0; + if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h1)) begin + scratch <= up_wdata_s; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h2)) begin + control <= up_wdata_s; + end + if (control[0] == 1'b0) begin + interrupt <= 1'b0; + end else if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h3)) begin + interrupt <= interrupt & ~up_wdata_s[0]; + end else begin + if (counter_to_interrupt_cnt == 32'h0 && counter_active == 1'b1) begin + interrupt <= 1'b1; + end + end + if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h4)) begin + counter_to_interrupt <= up_wdata_s; + arm_counter <= 1'b1; + end + end + end + + always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin + if (s_axi_aresetn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr_s[3:0]) + 4'h0: up_rdata <= VERSION; + 4'h1: up_rdata <= scratch; + 4'h2: up_rdata <= control; + 4'h3: up_rdata <= {31'h0,interrupt}; + 4'h4: up_rdata <= counter_to_interrupt; + 4'h5: up_rdata <= counter_from_interrupt; + 4'h6: up_rdata <= counter_interrupt_handling; + 4'h7: up_rdata <= min_interrupt_handling; + 4'h8: up_rdata <= max_interrupt_handling; + default: up_rdata <= 0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + // up bus interface + + up_axi i_up_axi ( + .up_rstn(s_axi_aresetn), + .up_clk(s_axi_aclk), + .up_axi_awvalid(s_axi_awvalid), + .up_axi_awaddr(s_axi_awaddr), + .up_axi_awready(s_axi_awready), + .up_axi_wvalid(s_axi_wvalid), + .up_axi_wdata(s_axi_wdata), + .up_axi_wstrb(s_axi_wstrb), + .up_axi_wready(s_axi_wready), + .up_axi_bvalid(s_axi_bvalid), + .up_axi_bresp(s_axi_bresp), + .up_axi_bready(s_axi_bready), + .up_axi_arvalid(s_axi_arvalid), + .up_axi_araddr(s_axi_araddr), + .up_axi_arready(s_axi_arready), + .up_axi_rvalid(s_axi_rvalid), + .up_axi_rresp(s_axi_rresp), + .up_axi_rdata(s_axi_rdata), + .up_axi_rready(s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_intr_monitor/axi_intr_monitor.xpr b/adi_library/axi_intr_monitor/axi_intr_monitor.xpr new file mode 100644 index 00000000..a67f5463 --- /dev/null +++ b/adi_library/axi_intr_monitor/axi_intr_monitor.xpr @@ -0,0 +1,406 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_intr_monitor/axi_intr_monitor_ip.tcl b/adi_library/axi_intr_monitor/axi_intr_monitor_ip.tcl new file mode 100644 index 00000000..ddeb4b20 --- /dev/null +++ b/adi_library/axi_intr_monitor/axi_intr_monitor_ip.tcl @@ -0,0 +1,21 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_intr_monitor +adi_ip_files axi_intr_monitor [list \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "axi_intr_monitor.v" ] + +adi_ip_properties axi_intr_monitor + +ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] + + diff --git a/adi_library/axi_intr_monitor/component.xml b/adi_library/axi_intr_monitor/component.xml new file mode 100644 index 00000000..32eef112 --- /dev/null +++ b/adi_library/axi_intr_monitor/component.xml @@ -0,0 +1,774 @@ + + + analog.com + user + axi_intr_monitor + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + irq + + + + + + + INTERRUPT + + + irq + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_intr_monitor + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 0f4cf392 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_intr_monitor + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 0f4cf392 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 38991a6b + + + + + + + irq + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + VERSION + Version + 0x00010000 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_list_9ca20931 + LEVEL_HIGH + LEVEL_LOW + EDGE_RISING + EDGE_FALLING + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../common/up_axi.v + verilogSource + + + axi_intr_monitor.v + verilogSource + CHECKSUM_23db8f82 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/up_axi.v + verilogSource + + + axi_intr_monitor.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_intr_monitor_v1_0.tcl + tclSource + CHECKSUM_38991a6b + XGUI_VERSION_2 + + + + axi_intr_monitor_v1_0 + + + VERSION + Version + 0x00010000 + + + Component_Name + axi_intr_monitor_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_intr_monitor_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:47:44Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_intr_monitor/xgui/axi_intr_monitor_v1_0.tcl b/adi_library/axi_intr_monitor/xgui/axi_intr_monitor_v1_0.tcl new file mode 100644 index 00000000..a32231a1 --- /dev/null +++ b/adi_library/axi_intr_monitor/xgui/axi_intr_monitor_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "VERSION" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.VERSION { PARAM_VALUE.VERSION } { + # Procedure called to update VERSION when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.VERSION { PARAM_VALUE.VERSION } { + # Procedure called to validate VERSION + return true +} + + +proc update_MODELPARAM_VALUE.VERSION { MODELPARAM_VALUE.VERSION PARAM_VALUE.VERSION } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.VERSION}] ${MODELPARAM_VALUE.VERSION} +} + diff --git a/adi_library/axi_laser_driver/Makefile b/adi_library/axi_laser_driver/Makefile new file mode 100644 index 00000000..0d1de874 --- /dev/null +++ b/adi_library/axi_laser_driver/Makefile @@ -0,0 +1,30 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_laser_driver + +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += axi_laser_driver.v +GENERIC_DEPS += axi_laser_driver_regmap.v + +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += axi_laser_driver_constr.xdc +XILINX_DEPS += axi_laser_driver_ip.tcl + +XILINX_LIB_DEPS += axi_pulse_gen +XILINX_LIB_DEPS += util_cdc + +INTEL_DEPS += ../axi_pulse_gen/axi_pulse_gen_constr.sdc +INTEL_DEPS += ../axi_pulse_gen/axi_pulse_gen_regmap.v +INTEL_DEPS += ../common/ad_rst.v +INTEL_DEPS += ../common/up_axi.v +INTEL_DEPS += ../common/util_pulse_gen.v +INTEL_DEPS += ../util_cdc/sync_bits.v +INTEL_DEPS += ../util_cdc/sync_event.v +INTEL_DEPS += axi_laser_driver_constr.sdc +INTEL_DEPS += axi_laser_driver_hw.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_laser_driver/axi_laser_driver.v b/adi_library/axi_laser_driver/axi_laser_driver.v new file mode 100644 index 00000000..1bf55198 --- /dev/null +++ b/adi_library/axi_laser_driver/axi_laser_driver.v @@ -0,0 +1,303 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +`timescale 1ns/100ps + +module axi_laser_driver #( + + parameter ID = 0, + parameter ASYNC_CLK_EN = 1, + parameter PULSE_WIDTH = 7, + parameter PULSE_PERIOD = 10 +) ( + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + + // external clock and control/status signals + + input ext_clk, + output driver_en_n, + output driver_pulse, + input driver_otw_n, + output driver_dp_reset, + output reg [ 7:0] tia_chsel, + + // interrupt + + output irq +); + + // internal signals + + reg up_wack = 1'b0; + reg up_rack = 1'b0; + reg [31:0] up_rdata = 32'b0; + reg driver_pulse_int_d = 1'b0; + reg [ 1:0] sequence_counter = 2'b00; + + // internal signals + + wire clk; + wire up_clk; + wire up_rstn; + wire up_rreq_s; + wire up_rack_ld_s; + wire up_rack_pwm_s; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_ld_s; + wire [31:0] up_rdata_pwm_s; + wire up_wreq_s; + wire up_wack_ld_s; + wire up_wack_pwm_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire [31:0] pulse_width_s; + wire [31:0] pulse_period_s; + wire load_config_s; + wire pulse_gen_resetn; + wire [31:0] pulse_counter_s; + wire driver_pulse_int_s; + wire [31:0] up_ext_clk_count_s; + wire sequence_en_s; + wire auto_sequence_s; + wire [31:0] sequence_offset_s; + wire [ 1:0] auto_seq0_s; + wire [ 1:0] auto_seq1_s; + wire [ 1:0] auto_seq2_s; + wire [ 1:0] auto_seq3_s; + wire [ 7:0] manual_select_s; + + // local parameters + + localparam [31:0] CORE_VERSION = {16'h0001, /* MAJOR */ + 8'h00, /* MINOR */ + 8'h61}; /* PATCH */ // 1.00.a + localparam [31:0] CORE_MAGIC = 32'h4C534452; // LSDR + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // register maps + + axi_pulse_gen_regmap #( + .ID (ID), + .CORE_MAGIC (CORE_MAGIC), + .CORE_VERSION (CORE_VERSION), + .ASYNC_CLK_EN (ASYNC_CLK_EN), + .PULSE_WIDTH (PULSE_WIDTH), + .PULSE_PERIOD (PULSE_PERIOD) + ) i_pwm_regmap ( + .ext_clk (ext_clk), + .clk_out (clk), + .pulse_gen_resetn (pulse_gen_resetn), + .pulse_width (pulse_width_s), + .pulse_period (pulse_period_s), + .load_config (load_config_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_pwm_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_pwm_s), + .up_rack (up_rack_pwm_s)); + + axi_laser_driver_regmap #( + .ID (ID), + .LASER_DRIVER_ID (1) + ) i_laser_driver_regmap ( + .clk (clk), + .driver_en_n (driver_en_n), + .driver_otw_n (driver_otw_n), + .pulse (driver_pulse_int_s), + .up_ext_clk_count (up_ext_clk_count_s), + .irq (irq), + .sequence_en (sequence_en_s), + .auto_sequence (auto_sequence_s), + .sequence_offset (sequence_offset_s), + .auto_seq0 (auto_seq0_s), + .auto_seq1 (auto_seq1_s), + .auto_seq2 (auto_seq2_s), + .auto_seq3 (auto_seq3_s), + .manual_select (manual_select_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_ld_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_ld_s), + .up_rack (up_rack_ld_s)); + + // read interface merge + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_wack <= up_wack_ld_s | up_wack_pwm_s; + up_rack <= up_rack_ld_s | up_rack_pwm_s; + up_rdata <= up_rdata_ld_s | up_rdata_pwm_s; + end + end + + // generic PWM generator's + + util_pulse_gen #( + .PULSE_WIDTH(PULSE_WIDTH), + .PULSE_PERIOD(PULSE_PERIOD) + ) i_laser_driver_pulse ( + .clk (clk), + .rstn (pulse_gen_resetn), + .pulse_width (pulse_width_s), + .pulse_period (pulse_period_s), + .load_config (load_config_s), + .pulse (driver_pulse_int_s), + .pulse_counter (pulse_counter_s)); + + // data path reset generation + // this logic will generate a reset signal right before the generated pulse + // in order to use it for resetting the cpack module, to synchronize it to + // the driver pulse + always @(posedge clk) begin + driver_pulse_int_d <= driver_pulse_int_s; + end + assign driver_dp_reset = driver_pulse_int_s & ~driver_pulse_int_d; + assign driver_pulse = driver_pulse_int_d; + + // clock monitor for the external clock + + up_clock_mon i_clock_mon ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_d_count (up_ext_clk_count_s), + .d_rst (~pulse_gen_resetn), + .d_clk (ext_clk)); + + // TIA sequencer + + always @(posedge clk) begin + if (sequence_en_s == 1'b0) begin + sequence_counter <= 2'b00; + end else begin + if (pulse_counter_s == sequence_offset_s) begin + if (auto_sequence_s) begin + sequence_counter <= sequence_counter + 1'b1; + end + end + end + end + + always @(posedge clk) begin + if (sequence_en_s == 1'b0) begin + tia_chsel <= 8'h00; + end else begin + if (pulse_counter_s == sequence_offset_s) begin + if (auto_sequence_s) begin + case (sequence_counter) + 2'b00 : tia_chsel <= {auto_seq0_s, auto_seq0_s, auto_seq0_s, auto_seq0_s}; + 2'b01 : tia_chsel <= {auto_seq1_s, auto_seq1_s, auto_seq1_s, auto_seq1_s}; + 2'b10 : tia_chsel <= {auto_seq2_s, auto_seq2_s, auto_seq2_s, auto_seq2_s}; + 2'b11 : tia_chsel <= {auto_seq3_s, auto_seq3_s, auto_seq3_s, auto_seq3_s}; + default : tia_chsel <= 8'h00; + endcase + end else begin + tia_chsel <= manual_select_s; + end + end + end + end + + // AXI Memory Mapped Wrapper + + up_axi #( + .AXI_ADDRESS_WIDTH(16) + ) i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_laser_driver/axi_laser_driver.xpr b/adi_library/axi_laser_driver/axi_laser_driver.xpr new file mode 100644 index 00000000..e91e80b9 --- /dev/null +++ b/adi_library/axi_laser_driver/axi_laser_driver.xpr @@ -0,0 +1,425 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_laser_driver/axi_laser_driver_constr.sdc b/adi_library/axi_laser_driver/axi_laser_driver_constr.sdc new file mode 100644 index 00000000..1ae5b3c0 --- /dev/null +++ b/adi_library/axi_laser_driver/axi_laser_driver_constr.sdc @@ -0,0 +1,20 @@ +############################################################################### +## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_false_path \ + -to [get_registers *i_driver_otw_sync|cdc_sync_stage1*] + +set_false_path \ + -to [get_registers *i_pulse_sync|cdc_sync_stage1*] + +set_false_path \ + -to [get_registers *i_sequencer_sync|cdc_sync_stage1[*]] + +set_false_path \ + -to [get_registers *i_sequence_offset_sync|cdc_sync_stage1[*]] + +set_false_path \ + -to [get_registers *i_sequence_control_sync|cdc_sync_stage1[*]] + diff --git a/adi_library/axi_laser_driver/axi_laser_driver_constr.xdc b/adi_library/axi_laser_driver/axi_laser_driver_constr.xdc new file mode 100644 index 00000000..a459e75d --- /dev/null +++ b/adi_library/axi_laser_driver/axi_laser_driver_constr.xdc @@ -0,0 +1,24 @@ +############################################################################### +## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property ASYNC_REG TRUE \ + [get_cells -hier {*cdc_sync_stage1_reg*}] \ + [get_cells -hier {*cdc_sync_stage2_reg*}] + +set_false_path \ + -to [get_pins -hierarchical * -filter {NAME=~*i_driver_otw_sync/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -to [get_pins -hierarchical * -filter {NAME=~*i_pulse_sync/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -to [get_pins -hierarchical * -filter {NAME=~*i_sequencer_sync/cdc_sync_stage1_reg[*]/D}] + +set_false_path \ + -to [get_pins -hierarchical * -filter {NAME=~*i_sequence_offset_sync/cdc_sync_stage1_reg[*]/D}] + +set_false_path \ + -to [get_pins -hierarchical * -filter {NAME=~*i_sequence_control_sync/cdc_sync_stage1_reg[*]/D}] + diff --git a/adi_library/axi_laser_driver/axi_laser_driver_hw.tcl b/adi_library/axi_laser_driver/axi_laser_driver_hw.tcl new file mode 100644 index 00000000..41b624f9 --- /dev/null +++ b/adi_library/axi_laser_driver/axi_laser_driver_hw.tcl @@ -0,0 +1,85 @@ +############################################################################### +## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +source ../../scripts/adi_env.tcl +source ../scripts/adi_ip_intel.tcl + +set_module_property NAME axi_laser_driver +set_module_property DESCRIPTION "AXI Laser Driver IP for Lidar prototyping platform " +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME axi_laser_driver + +# source files + +ad_ip_files axi_laser_driver [list \ + "$ad_hdl_dir/library/util_cdc/sync_bits.v" \ + "$ad_hdl_dir/library/util_cdc/sync_event.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/util_pulse_gen.v" \ + "$ad_hdl_dir/library/axi_pulse_gen/axi_pulse_gen_regmap.v" \ + "$ad_hdl_dir/library/axi_pulse_gen/axi_pulse_gen_constr.sdc" \ + "axi_laser_driver_constr.sdc" \ + "axi_laser_driver_regmap.v" \ + "axi_laser_driver.v"] + +# IP parameters + +add_parameter ID INTEGER 0 +set_parameter_property ID DEFAULT_VALUE 0 +set_parameter_property ID DISPLAY_NAME "Core ID" +set_parameter_property ID UNITS None +set_parameter_property ID HDL_PARAMETER true + +add_parameter ASYNC_CLK_EN INTEGER 0 +set_parameter_property ASYNC_CLK_EN DEFAULT_VALUE 0 +set_parameter_property ASYNC_CLK_EN DISPLAY_NAME "Asynchronous Clocks" +set_parameter_property ASYNC_CLK_EN DISPLAY_HINT boolean +set_parameter_property ASYNC_CLK_EN ALLOWED_RANGES { "0:Disabled" "1:Enabled"} +set_parameter_property ASYNC_CLK_EN HDL_PARAMETER true + +add_parameter PULSE_WIDTH INTEGER 0 +set_parameter_property PULSE_WIDTH DEFAULT_VALUE 0 +set_parameter_property PULSE_WIDTH DISPLAY_NAME "PWM pulse width" +set_parameter_property PULSE_WIDTH UNITS None +set_parameter_property PULSE_WIDTH HDL_PARAMETER true + +add_parameter PULSE_PERIOD INTEGER 0 +set_parameter_property PULSE_PERIOD DEFAULT_VALUE 0 +set_parameter_property PULSE_PERIOD DISPLAY_NAME "PWM period" +set_parameter_property PULSE_PERIOD UNITS None +set_parameter_property PULSE_PERIOD HDL_PARAMETER true + +# AXI4 Memory Mapped Interface + +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 15 + +# Interrupt interface + +add_interface interrupt_sender interrupt end +set_interface_property interrupt_sender associatedAddressablePoint s_axi +set_interface_property interrupt_sender associatedClock s_axi_clock +set_interface_property interrupt_sender associatedReset s_axi_reset +set_interface_property interrupt_sender ENABLED true +set_interface_property interrupt_sender EXPORT_OF "" +set_interface_property interrupt_sender PORT_NAME_MAP "" +set_interface_property interrupt_sender CMSIS_SVD_VARIABLES "" +set_interface_property interrupt_sender SVD_ADDRESS_GROUP "" + +add_interface_port interrupt_sender irq irq Output 1 + +# external clock and control/status ports + +ad_interface clock ext_clk input 1 + +ad_interface signal driver_en_n output 1 +ad_interface signal driver_pulse output 1 +ad_interface signal driver_otw_n input 1 +ad_interface reset driver_dp_reset output 1 if_ext_clk +ad_interface signal tia_chsel output 8 + diff --git a/adi_library/axi_laser_driver/axi_laser_driver_ip.tcl b/adi_library/axi_laser_driver/axi_laser_driver_ip.tcl new file mode 100644 index 00000000..8c4ba927 --- /dev/null +++ b/adi_library/axi_laser_driver/axi_laser_driver_ip.tcl @@ -0,0 +1,105 @@ +############################################################################### +## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create axi_laser_driver +adi_ip_files axi_laser_driver [list \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "axi_laser_driver_constr.xdc" \ + "axi_laser_driver_regmap.v" \ + "axi_laser_driver.v"] + +adi_ip_properties axi_laser_driver +adi_ip_ttcl axi_laser_driver "../axi_pulse_gen/axi_pulse_gen_constr.ttcl" + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_laser_driver} [ipx::current_core] + +adi_ip_add_core_dependencies [list \ + analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \ + analog.com:$VIVADO_IP_LIBRARY:axi_pulse_gen:1.0 \ +] + +set cc [ipx::current_core] + +set_property display_name "ADI AXI Laser Driver" $cc +set_property description "ADI AXI Laser Driver" $cc + +## define ext_clk port as a clock interface +adi_add_bus ext_clk slave \ + "xilinx.com:signal:clock_rtl:1.0" \ + "xilinx.com:signal:clock:1.0" \ + [list {"ext_clk" "CLK"} ] + +adi_set_ports_dependency "ext_clk" \ + "(spirit:decode(id('MODELPARAM_VALUE.ASYNC_CLK_EN')) = 1)" 0 + +## Parameter validation + +set_property -dict [list \ + "value_format" "bool" \ + "value" "true" \ + ] \ +[ipx::get_user_parameters ASYNC_CLK_EN -of_objects $cc] + +set_property -dict [list \ + "value_format" "bool" \ + "value" "true" \ + ] \ +[ipx::get_hdl_parameters ASYNC_CLK_EN -of_objects $cc] + +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "0" \ + "value_validation_range_maximum" "2147483647" \ + ] \ +[ipx::get_user_parameters PULSE_WIDTH -of_objects $cc] + +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "0" \ + "value_validation_range_maximum" "2147483647" \ + ] \ +[ipx::get_user_parameters PULSE_PERIOD -of_objects $cc] + +## Customize XGUI layout + +## Remove the automatically generated GUI page +ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] +ipx::save_core $cc + +## Create a new GUI page + +ipgui::add_page -name {AXI Pulse Generator} -component $cc -display_name {AXI Pulse Generator} +set page0 [ipgui::get_pagespec -name "AXI Pulse Generator" -component $cc] + +ipgui::add_param -name "ASYNC_CLK_EN" -component $cc -parent $page0 +set_property -dict [list \ + "display_name" "ASYNC_CLK_EN" \ + "tooltip" "External clock for the counter" \ + "widget" "checkBox" \ +] [ipgui::get_guiparamspec -name "ASYNC_CLK_EN" -component $cc] + +ipgui::add_param -name "PULSE_WIDTH" -component $cc -parent $page0 +set_property -dict [list \ + "display_name" "Pulse width" \ + "tooltip" "Pulse width of the generated signal. The unit interval is the system or external clock period." \ +] [ipgui::get_guiparamspec -name "PULSE_WIDTH" -component $cc] + +ipgui::add_param -name "PULSE_PERIOD" -component $cc -parent $page0 +set_property -dict [list \ + "display_name" "Pulse period" \ + "tooltip" "Period of the generated signal. The unit interval is the system or external clock period." \ +] [ipgui::get_guiparamspec -name "PULSE_PERIOD" -component $cc] + +## Save the modifications + +ipx::create_xgui_files $cc +ipx::save_core $cc diff --git a/adi_library/axi_laser_driver/axi_laser_driver_regmap.v b/adi_library/axi_laser_driver/axi_laser_driver_regmap.v new file mode 100644 index 00000000..fb84faec --- /dev/null +++ b/adi_library/axi_laser_driver/axi_laser_driver_regmap.v @@ -0,0 +1,281 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +`timescale 1ns/100ps + +module axi_laser_driver_regmap #( + + parameter ID = 0, + parameter LASER_DRIVER_ID = 1 +) ( + + // control and status signals + + input clk, + output driver_en_n, + input driver_otw_n, + + input pulse, + output reg irq, + + input [31:0] up_ext_clk_count, + + // TIA sequencer + + output sequence_en, + output auto_sequence, + output [31:0] sequence_offset, + + output [ 1:0] auto_seq0, + output [ 1:0] auto_seq1, + output [ 1:0] auto_seq2, + output [ 1:0] auto_seq3, + + output [ 7:0] manual_select, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack +); + + // internal registers + + reg up_driver_en_n = 1'b0; + reg [2:0] up_irq_mask = 3'b111; + reg [2:0] up_irq_source = 3'b000; + reg up_driver_otw_n_int = 1'b1; + + reg up_sequence_en = 1'b0; + reg up_auto_sequence = 1'b1; + reg [31:0] up_sequence_offset = 32'b0; + reg [ 1:0] up_auto_seq0 = 2'b00; + reg [ 1:0] up_auto_seq1 = 2'b01; + reg [ 1:0] up_auto_seq2 = 2'b10; + reg [ 1:0] up_auto_seq3 = 2'b11; + reg [ 7:0] up_manual_select = 8'h00; + + // internal signals + + wire up_wreq_int_s; + wire up_rreq_int_s; + wire up_driver_otw_n_s; + wire [2:0] up_irq_pending_s; + wire [2:0] up_irq_trigger_s; + wire [2:0] up_irq_source_clear_s; + wire up_pulse_s; + + wire up_driver_otw_n_enter_s; + wire up_driver_otw_n_exit_s; + + // map the laser driver registers into the address space + + assign up_wreq_int_s = (up_waddr[13:5] == LASER_DRIVER_ID) ? up_wreq : 1'b0; + assign up_rreq_int_s = (up_raddr[13:5] == LASER_DRIVER_ID) ? up_rreq : 1'b0; + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 1'b0; + up_driver_en_n <= 1'b1; // by default laser is disabled + up_irq_mask <= 3'b111; + up_sequence_en <= 1'b0; + up_auto_sequence <= 1'b1; + up_sequence_offset <= 32'h19; // 25*4ns is the default offset for TIA selection + up_auto_seq0 <= 2'b00; + up_auto_seq1 <= 2'b01; + up_auto_seq2 <= 2'b10; + up_auto_seq3 <= 2'b11; + up_manual_select <= 8'h00; + end else begin + up_wack <= up_wreq_int_s; + if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin + up_driver_en_n <= up_wdata[0]; + end + if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'h8)) begin + up_irq_mask <= up_wdata[2:0]; + end + if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'hB)) begin + up_sequence_en <= up_wdata[0]; + up_auto_sequence <= up_wdata[1]; + end + if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'hC)) begin + up_sequence_offset <= up_wdata; + end + if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'hD)) begin + up_auto_seq0 <= up_wdata[1:0]; + up_auto_seq1 <= up_wdata[5:4]; + up_auto_seq2 <= up_wdata[9:8]; + up_auto_seq3 <= up_wdata[13:12]; + end + if ((up_wreq_int_s == 1'b1) && (up_waddr[3:0] == 4'hE)) begin + up_manual_select <= {up_wdata[13:12], + up_wdata[9:8], + up_wdata[5:4], + up_wdata[1:0]}; + end + end + end + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 1'b0; + up_rdata <= 32'b0; + end else begin + up_rack <= up_rreq_int_s; + if (up_rreq_int_s == 1'b1) begin + case (up_raddr[4:0]) + 5'h00: up_rdata <= {31'h0, up_driver_en_n}; + 5'h01: up_rdata <= {31'h0, up_driver_otw_n_s}; + 5'h02: up_rdata <= up_ext_clk_count; + 5'h08: up_rdata <= {29'h0, up_irq_mask}; + 5'h09: up_rdata <= {29'h0, up_irq_source}; + 5'h0A: up_rdata <= {29'h0, up_irq_pending_s}; + 5'h0B: up_rdata <= {30'h0, up_auto_sequence, up_sequence_en}; + 5'h0C: up_rdata <= up_sequence_offset; + 5'h0D: up_rdata <= {18'h0, up_auto_seq3, + 2'h0, up_auto_seq2, + 2'h0, up_auto_seq1, + 2'h0, up_auto_seq0}; + 5'h0E: up_rdata <= {18'h0, up_manual_select[7:6], + 2'h0, up_manual_select[5:4], + 2'h0, up_manual_select[3:2], + 2'h0, up_manual_select[1:0]}; + + default: up_rdata <= 0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + assign driver_en_n = up_driver_en_n; + + always @(posedge up_clk) begin + up_driver_otw_n_int <= up_driver_otw_n_s; + end + // negative edge of otw_n - system enters into an over temperature state + assign up_driver_otw_n_enter_s = ~up_driver_otw_n_s & up_driver_otw_n_int; + // positive edge of otw_n - system exits from an over temperature state + assign up_driver_otw_n_exit_s = up_driver_otw_n_s & ~up_driver_otw_n_int; + + // Interrupt handling - it can be generated by a generated pulse or an over + // temperature warning signal + + assign up_irq_pending_s = ~up_irq_mask & up_irq_source; + assign up_irq_trigger_s = {up_driver_otw_n_exit_s, up_driver_otw_n_enter_s, up_pulse_s}; + assign up_irq_source_clear_s = (up_wreq_int_s == 1'b1 && up_waddr[3:0] == 4'hA) ? up_wdata[2:0] : 3'b000; + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + irq <= 1'b0; + end else begin + irq <= |up_irq_pending_s; + end + end + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_irq_source <= 3'b000; + end else begin + up_irq_source <= up_irq_trigger_s | (up_irq_source & ~up_irq_source_clear_s); + end + end + + // CDC logic + + sync_bits #( + .NUM_OF_BITS (1), + .ASYNC_CLK (1) + ) i_driver_otw_sync ( + .in_bits (driver_otw_n), + .out_clk (up_clk), + .out_resetn (1'b1), + .out_bits (up_driver_otw_n_s)); + + sync_bits #( + .NUM_OF_BITS (1), + .ASYNC_CLK (1) + ) i_pulse_sync ( + .in_bits (pulse), + .out_clk (up_clk), + .out_resetn (1'b1), + .out_bits (up_pulse_s)); + + sync_bits #( + .NUM_OF_BITS (2), + .ASYNC_CLK (1) + ) i_sequence_control_sync ( + .in_bits ({up_auto_sequence, up_sequence_en}), + .out_clk (clk), + .out_resetn (1'b1), + .out_bits ({auto_sequence, sequence_en})); + + sync_bits #( + .NUM_OF_BITS (16), + .ASYNC_CLK (1) + ) i_sequencer_sync ( + .in_bits ({up_auto_seq3, + up_auto_seq2, + up_auto_seq1, + up_auto_seq0, + up_manual_select + }), + .out_clk (clk), + .out_resetn (1'b1), + .out_bits ({auto_seq3, + auto_seq2, + auto_seq1, + auto_seq0, + manual_select + })); + + sync_bits #( + .NUM_OF_BITS (32), + .ASYNC_CLK (1) + ) i_sequence_offset_sync ( + .in_bits (up_sequence_offset), + .out_clk (clk), + .out_resetn (1'b1), + .out_bits (sequence_offset)); + +endmodule diff --git a/adi_library/axi_laser_driver/component.xml b/adi_library/axi_laser_driver/component.xml new file mode 100644 index 00000000..f09e9988 --- /dev/null +++ b/adi_library/axi_laser_driver/component.xml @@ -0,0 +1,977 @@ + + + analog.com + user + axi_laser_driver + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + ext_clk + + + + + + + CLK + + + ext_clk + + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_laser_driver + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_analog_com_user_axi_pulse_gen_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 6f3005fd + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_laser_driver + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_axi_pulse_gen_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 0bdfec18 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_xpgui_analog_com_user_axi_pulse_gen_1_0__ref_view_fileset + + + xilinx_xpgui_view_fileset + + + + viewChecksum + ce5d3fb0 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + ext_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + driver_en_n + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + driver_pulse + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + driver_otw_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + driver_dp_reset + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + tia_chsel + + out + + 7 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + irq + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + ID + Id + 0 + + + ASYNC_CLK_EN + Async Clk En + true + + + PULSE_WIDTH + Pulse Width + 7 + + + PULSE_PERIOD + Pulse Period + 10 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../axi_pulse_gen/axi_pulse_gen_constr.ttcl + ttcl + + + ../xilinx/common/up_clock_mon_constr.xdc + xdc + + + axi_laser_driver_constr.xdc + xdc + + + axi_laser_driver_regmap.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + axi_laser_driver.v + verilogSource + CHECKSUM_8a5a13b8 + + + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_analog_com_user_axi_pulse_gen_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + axi_laser_driver_regmap.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + axi_laser_driver.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_axi_pulse_gen_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axi_laser_driver_v1_0.tcl + tclSource + CHECKSUM_5aee8db5 + XGUI_VERSION_2 + + + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + xilinx_xpgui_analog_com_user_axi_pulse_gen_1_0__ref_view_fileset + + + + + + + + ADI AXI Laser Driver + + + ID + Id + 0 + + + ASYNC_CLK_EN + ASYNC_CLK_EN + true + + + PULSE_WIDTH + Pulse width + 7 + + + PULSE_PERIOD + Pulse period + 10 + + + Component_Name + axi_laser_driver_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + ADI AXI Laser Driver + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_laser_driver + 1 + 2024-01-14T03:48:03Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_laser_driver/xgui/axi_laser_driver_v1_0.tcl b/adi_library/axi_laser_driver/xgui/axi_laser_driver_v1_0.tcl new file mode 100644 index 00000000..eea2c81e --- /dev/null +++ b/adi_library/axi_laser_driver/xgui/axi_laser_driver_v1_0.tcl @@ -0,0 +1,72 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set AXI_Pulse_Generator [ipgui::add_page $IPINST -name "AXI Pulse Generator"] + set ASYNC_CLK_EN [ipgui::add_param $IPINST -name "ASYNC_CLK_EN" -parent ${AXI_Pulse_Generator}] + set_property tooltip {External clock for the counter} ${ASYNC_CLK_EN} + set PULSE_WIDTH [ipgui::add_param $IPINST -name "PULSE_WIDTH" -parent ${AXI_Pulse_Generator}] + set_property tooltip {Pulse width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_WIDTH} + set PULSE_PERIOD [ipgui::add_param $IPINST -name "PULSE_PERIOD" -parent ${AXI_Pulse_Generator}] + set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_PERIOD} + + +} + +proc update_PARAM_VALUE.ASYNC_CLK_EN { PARAM_VALUE.ASYNC_CLK_EN } { + # Procedure called to update ASYNC_CLK_EN when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASYNC_CLK_EN { PARAM_VALUE.ASYNC_CLK_EN } { + # Procedure called to validate ASYNC_CLK_EN + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.PULSE_PERIOD { PARAM_VALUE.PULSE_PERIOD } { + # Procedure called to update PULSE_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_PERIOD { PARAM_VALUE.PULSE_PERIOD } { + # Procedure called to validate PULSE_PERIOD + return true +} + +proc update_PARAM_VALUE.PULSE_WIDTH { PARAM_VALUE.PULSE_WIDTH } { + # Procedure called to update PULSE_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_WIDTH { PARAM_VALUE.PULSE_WIDTH } { + # Procedure called to validate PULSE_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.ASYNC_CLK_EN { MODELPARAM_VALUE.ASYNC_CLK_EN PARAM_VALUE.ASYNC_CLK_EN } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK_EN}] ${MODELPARAM_VALUE.ASYNC_CLK_EN} +} + +proc update_MODELPARAM_VALUE.PULSE_WIDTH { MODELPARAM_VALUE.PULSE_WIDTH PARAM_VALUE.PULSE_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_WIDTH}] ${MODELPARAM_VALUE.PULSE_WIDTH} +} + +proc update_MODELPARAM_VALUE.PULSE_PERIOD { MODELPARAM_VALUE.PULSE_PERIOD PARAM_VALUE.PULSE_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_PERIOD}] ${MODELPARAM_VALUE.PULSE_PERIOD} +} + diff --git a/adi_library/axi_logic_analyzer/Makefile b/adi_library/axi_logic_analyzer/Makefile new file mode 100644 index 00000000..bf3b244a --- /dev/null +++ b/adi_library/axi_logic_analyzer/Makefile @@ -0,0 +1,23 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_logic_analyzer + +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_logic_analyzer.v +GENERIC_DEPS += axi_logic_analyzer_reg.v +GENERIC_DEPS += axi_logic_analyzer_trigger.v + +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_logic_analyzer_constr.xdc +XILINX_DEPS += axi_logic_analyzer_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_logic_analyzer/axi_logic_analyzer.v b/adi_library/axi_logic_analyzer/axi_logic_analyzer.v new file mode 100644 index 00000000..64be9645 --- /dev/null +++ b/adi_library/axi_logic_analyzer/axi_logic_analyzer.v @@ -0,0 +1,528 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_logic_analyzer ( + + // interface + + input clk, + output clk_out, + + input [15:0] data_i, + output reg [15:0] data_o, + output [15:0] data_t, + input [ 1:0] trigger_i, + + output adc_valid, + output reg [15:0] adc_data, + + input [15:0] dac_data, + input dac_valid, + output reg dac_read, + + input [ 2:0] external_rate, + input external_valid, + input external_decimation_en, + input trigger_in, + output trigger_out, + output trigger_out_adc, + output [31:0] fifo_depth, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [ 6:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [ 6:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [31:0] s_axi_rdata, + output [ 1:0] s_axi_rresp, + input s_axi_rready +); + + // internal registers + + reg [15:0] data_r = 'd0; + reg [ 1:0] trigger_m1 = 'd0; + reg [31:0] downsampler_counter_la = 'd0; + reg [31:0] upsampler_counter_pg = 'd0; + + reg sample_valid_la = 'd0; + + reg [15:0] io_selection; // 1 - input, 0 - output + + reg [31:0] delay_counter = 'd0; + reg triggered = 'd0; + + reg up_triggered; + reg up_triggered_d1; + reg up_triggered_d2; + + reg up_triggered_set; + reg up_triggered_reset; + reg up_triggered_reset_d1; + reg up_triggered_reset_d2; + + reg streaming_on; + + reg [ 1:0] trigger_i_m1 = 2'd0; + reg [ 1:0] trigger_i_m2 = 2'd0; + reg [ 1:0] trigger_i_m3 = 2'd0; + reg trigger_adc_m1 = 1'd0; + reg trigger_adc_m2 = 1'd0; + reg trigger_la_m2 = 1'd0; + reg pg_trigered = 1'd0; + + reg [ 1:0] any_edge_trigger = 1'd0; + reg [ 1:0] rise_edge_trigger = 1'd0; + reg [ 1:0] fall_edge_trigger = 1'd0; + reg [ 1:0] high_level_trigger = 1'd0; + reg [ 1:0] low_level_trigger = 1'd0; + + reg [31:0] trigger_holdoff_counter = 32'd0; + reg [ 3:0] adc_data_delay = 4'd0; + + reg [16:0] data_fixed_delay [0:15]; + reg [15:0] data_dynamic_delay [0:15]; + + // internal signals + + wire up_clk; + wire up_rstn; + wire [ 4:0] up_waddr; + wire [31:0] up_wdata; + wire up_wack; + wire up_wreq; + wire up_rack; + wire [31:0] up_rdata; + wire up_rreq; + wire [ 4:0] up_raddr; + + wire reset; + + wire [31:0] divider_counter_la; + wire [31:0] divider_counter_pg; + + wire [17:0] edge_detect_enable; + wire [17:0] rise_edge_enable; + wire [17:0] fall_edge_enable; + wire [17:0] low_level_enable; + wire [17:0] high_level_enable; + wire [ 6:0] trigger_logic; // 0-OR,1-AND + wire clock_select; + wire [15:0] overwrite_enable; + wire [15:0] overwrite_data; + + wire [15:0] io_selection_s; // 1 - input, 0 - output + wire [15:0] od_pp_n; // 0 - push/pull, 1 - open drain + + wire trigger_out_s; + wire [31:0] trigger_delay; + wire trigger_out_delayed; + + wire [19:0] pg_trigger_config; + + wire [ 1:0] pg_en_trigger_pins; + wire pg_en_trigger_adc; + wire pg_en_trigger_la; + + wire [ 1:0] pg_low_level; + wire [ 1:0] pg_high_level; + wire [ 1:0] pg_any_edge; + wire [ 1:0] pg_rise_edge; + wire [ 1:0] pg_fall_edge; + + wire [31:0] trigger_holdoff; + wire trigger_out_holdoff; + + wire streaming; + + wire [ 3:0] in_data_delay; + wire [ 3:0] up_data_delay; + wire master_delay_ctrl; + wire [ 9:0] data_delay_control; + wire [15:0] adc_data_mn; + + genvar i; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + assign trigger_out = trigger_delay == 32'h0 ? trigger_out_holdoff | streaming_on : trigger_out_delayed | streaming_on; + + assign trigger_out_delayed = delay_counter == 32'h0 ? 1 : 0; + + always @(posedge clk_out) begin + if (trigger_delay == 0) begin + if (streaming == 1'b1 && sample_valid_la == 1'b1 && trigger_out_holdoff == 1'b1) begin + streaming_on <= 1'b1; + end else if (streaming == 1'b0) begin + streaming_on <= 1'b0; + end + end else begin + if (streaming == 1'b1 && sample_valid_la == 1'b1 && trigger_out_delayed == 1'b1) begin + streaming_on <= 1'b1; + end else if (streaming == 1'b0) begin + streaming_on <= 1'b0; + end + end + end + + always @(posedge clk_out) begin + if (sample_valid_la == 1'b1 && trigger_out_holdoff == 1'b1) begin + up_triggered_set <= 1'b1; + end else if (up_triggered_reset == 1'b1) begin + up_triggered_set <= 1'b0; + end + up_triggered_reset_d1 <= up_triggered; + up_triggered_reset_d2 <= up_triggered_reset_d1; + up_triggered_reset <= up_triggered_reset_d2; + end + + always @(posedge up_clk) begin + up_triggered_d1 <= up_triggered_set; + up_triggered_d2 <= up_triggered_d1; + up_triggered <= up_triggered_d2; + end + + generate + for (i = 0 ; i < 16; i = i + 1) begin + assign data_t[i] = od_pp_n[i] ? io_selection[i] | data_o[i] : io_selection[i]; + always @(posedge clk_out) begin + data_o[i] <= overwrite_enable[i] ? overwrite_data[i] : data_r[i]; + end + always @(posedge clk_out) begin + if(dac_valid == 1'b1) begin + data_r[i] <= dac_data[i]; + end + if (io_selection_s[i] == 1'b1) begin + io_selection[i] <= 1'b1; + end else begin + if(dac_valid == 1'b1 || overwrite_enable[i] == 1'b1) begin + io_selection[i] <= 1'b0; + end + end + end + end + endgenerate + + BUFGMUX_CTRL BUFGMUX_CTRL_inst ( + .O (clk_out), + .I0 (clk), + .I1 (data_i[0]), + .S (clock_select)); + + // - synchronization + // - compensate for m2k adc path delay + + // 17 clock cycles delay + generate + for (i = 0 ; i < 16; i = i + 1) begin + always @(posedge clk_out) begin + if (reset == 1'b1) begin + data_fixed_delay[i] <= 'd0; + end else begin + data_fixed_delay[i] <= {data_fixed_delay[i][15:0], data_i[i]}; + end + end + end + + // dynamic sample delay (1 to 16) + for (i = 0 ; i < 16; i = i + 1) begin + always @(posedge clk_out) begin + if (sample_valid_la == 1'b1) begin + data_dynamic_delay[i] <= {data_dynamic_delay[i][14:0], data_fixed_delay[i][16]}; + end + end + assign adc_data_mn[i] = data_dynamic_delay[i][in_data_delay[3:0]]; + end + endgenerate + + // adc path 'rate delay' given by axi_adc_decimate + always @(posedge clk_out) begin + case (external_rate) + 3'd0: adc_data_delay <= 4'd1; // 100MSPS + 3'd1: adc_data_delay <= 4'd3; // 10MSPS + default: adc_data_delay <= 4'd1; // <= 1MSPS + endcase + end + + assign up_data_delay = data_delay_control[3:0]; + assign rate_gen_select = data_delay_control[8]; + + // select if the delay taps number is chosen by the user or automatically + assign master_delay_ctrl = data_delay_control[9]; + assign in_data_delay = master_delay_ctrl ? up_data_delay : + external_decimation_en ? 4'd0 : adc_data_delay; + + always @(posedge clk_out) begin + if (sample_valid_la == 1'b1) begin + adc_data <= adc_data_mn; + end + end + + assign adc_valid = sample_valid_la; + + always @(posedge clk_out) begin + trigger_m1 <= trigger_i; + end + + // downsampler logic analyzer + + always @(posedge clk_out) begin + if (reset == 1'b1) begin + sample_valid_la <= 1'b0; + downsampler_counter_la <= 32'h0; + end else begin + if (rate_gen_select) begin + downsampler_counter_la <= 32'h0; + sample_valid_la <= external_valid; + end else if (downsampler_counter_la < divider_counter_la ) begin + downsampler_counter_la <= downsampler_counter_la + 1; + sample_valid_la <= 1'b0; + end else begin + downsampler_counter_la <= 32'h0; + sample_valid_la <= 1'b1; + end + end + end + + // pattern generator instrument triggering + + assign pg_any_edge = pg_trigger_config[1:0]; + assign pg_rise_edge = pg_trigger_config[3:2]; + assign pg_fall_edge = pg_trigger_config[5:4]; + assign pg_low_level = pg_trigger_config[7:6]; + assign pg_high_level = pg_trigger_config[9:8]; + + assign pg_en_trigger_pins = pg_trigger_config[17:16]; + assign pg_en_trigger_adc = pg_trigger_config[18]; + assign pg_en_trigger_la = pg_trigger_config[19]; + + assign trigger_active = |pg_trigger_config[19:16]; + assign trigger = (ext_trigger & pg_en_trigger_pins) | + (trigger_adc_m2 & pg_en_trigger_adc) | + (trigger_out_s & pg_en_trigger_la); + + assign ext_trigger = |(any_edge_trigger | + rise_edge_trigger | + fall_edge_trigger | + high_level_trigger | + low_level_trigger); + + // sync + always @(posedge clk) begin + trigger_i_m1 <= trigger_i; + trigger_i_m2 <= trigger_i_m1; + trigger_i_m3 <= trigger_i_m2; + + trigger_adc_m1 <= trigger_in; + trigger_adc_m2 <= trigger_adc_m1; + end + + always @(posedge clk) begin + any_edge_trigger <= (trigger_i_m3 ^ trigger_i_m2) & pg_any_edge; + rise_edge_trigger <= (~trigger_i_m3 & trigger_i_m2) & pg_rise_edge; + fall_edge_trigger <= (trigger_i_m3 & ~trigger_i_m2) & pg_fall_edge; + high_level_trigger <= trigger_i_m3 & pg_high_level; + low_level_trigger <= ~trigger_i_m3 & pg_low_level; + end + + // upsampler pattern generator + + always @(posedge clk_out) begin + if (reset == 1'b1) begin + upsampler_counter_pg <= 32'h0; + dac_read <= 1'b0; + end else begin + dac_read <= 1'b0; + pg_trigered <= trigger_active ? (trigger | pg_trigered) : 1'b0; + if (trigger_active & !pg_trigered) begin + upsampler_counter_pg <= 32'h0; + dac_read <= 1'b0; + end else if (upsampler_counter_pg < divider_counter_pg) begin + upsampler_counter_pg <= upsampler_counter_pg + 1; + end else begin + upsampler_counter_pg <= 32'h0; + dac_read <= 1'b1; + end + end + end + + always @(posedge clk_out) begin + if(trigger_delay == 32'h0) begin + delay_counter <= 32'h0; + end else begin + if (adc_valid == 1'b1) begin + triggered <= trigger_out_holdoff | triggered; + if (delay_counter == 32'h0) begin + delay_counter <= trigger_delay; + triggered <= 1'b0; + end else begin + if(triggered == 1'b1 || trigger_out_holdoff == 1'b1) begin + delay_counter <= delay_counter - 1; + end + end + end + end + end + + // hold off trigger + assign trigger_out_holdoff = (trigger_holdoff_counter != 0) ? 0 : trigger_out_s; + assign holdoff_cnt_en = |trigger_holdoff; + + always @(posedge clk) begin + if (reset == 1'b1) begin + trigger_holdoff_counter <= 0; + end else begin + if (trigger_holdoff_counter != 0) begin + trigger_holdoff_counter <= trigger_holdoff_counter - 1'b1; + end else if (trigger_out_holdoff == 1'b1) begin + trigger_holdoff_counter <= trigger_holdoff; + end else begin + trigger_holdoff_counter <= trigger_holdoff_counter; + end + end + end + + axi_logic_analyzer_trigger i_trigger ( + .clk (clk_out), + .reset (reset), + + .data (adc_data_mn), + .data_valid(sample_valid_la), + .trigger_i (trigger_m1), + .trigger_in (trigger_in), + + .edge_detect_enable (edge_detect_enable), + .rise_edge_enable (rise_edge_enable), + .fall_edge_enable (fall_edge_enable), + .low_level_enable (low_level_enable), + .high_level_enable (high_level_enable), + .trigger_logic (trigger_logic), + .trigger_out_adc (trigger_out_adc), + .trigger_out (trigger_out_s)); + + axi_logic_analyzer_reg i_registers ( + .clk (clk_out), + .reset (reset), + + .divider_counter_la (divider_counter_la), + .divider_counter_pg (divider_counter_pg), + .io_selection (io_selection_s), + + .edge_detect_enable (edge_detect_enable), + .rise_edge_enable (rise_edge_enable), + .fall_edge_enable (fall_edge_enable), + .low_level_enable (low_level_enable), + .high_level_enable (high_level_enable), + .fifo_depth (fifo_depth), + .trigger_delay (trigger_delay), + .trigger_holdoff (trigger_holdoff), + .trigger_logic (trigger_logic), + .clock_select (clock_select), + .overwrite_enable (overwrite_enable), + .overwrite_data (overwrite_data), + .input_data (adc_data_mn), + .od_pp_n (od_pp_n), + .triggered (up_triggered), + .pg_trigger_config (pg_trigger_config), + .streaming(streaming), + .data_delay_control (data_delay_control), + + // bus interface + + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + + // axi interface + + up_axi #( + .AXI_ADDRESS_WIDTH(7) + ) i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_logic_analyzer/axi_logic_analyzer.xpr b/adi_library/axi_logic_analyzer/axi_logic_analyzer.xpr new file mode 100644 index 00000000..50bbd119 --- /dev/null +++ b/adi_library/axi_logic_analyzer/axi_logic_analyzer.xpr @@ -0,0 +1,465 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc b/adi_library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc new file mode 100644 index 00000000..eb4962b7 --- /dev/null +++ b/adi_library/axi_logic_analyzer/axi_logic_analyzer_constr.xdc @@ -0,0 +1,15 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_d*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_triggered_reset_d*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *data_fixed_delay*}] + +set_false_path -to [get_pins BUFGMUX_CTRL_inst/S*] + +set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_d1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *up_triggered_reset_d1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *data_fixed_delay* && IS_SEQUENTIAL}] + diff --git a/adi_library/axi_logic_analyzer/axi_logic_analyzer_ip.tcl b/adi_library/axi_logic_analyzer/axi_logic_analyzer_ip.tcl new file mode 100644 index 00000000..404334e4 --- /dev/null +++ b/adi_library/axi_logic_analyzer/axi_logic_analyzer_ip.tcl @@ -0,0 +1,32 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_logic_analyzer +adi_ip_files axi_logic_analyzer [list \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "axi_logic_analyzer_constr.xdc" \ + "axi_logic_analyzer_reg.v" \ + "axi_logic_analyzer_trigger.v" \ + "axi_logic_analyzer.v" ] + +adi_ip_properties axi_logic_analyzer + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_logic_analyzer} [ipx::current_core] + +ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface clk_out xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/axi_logic_analyzer/axi_logic_analyzer_reg.v b/adi_library/axi_logic_analyzer/axi_logic_analyzer_reg.v new file mode 100644 index 00000000..5b860b8f --- /dev/null +++ b/adi_library/axi_logic_analyzer/axi_logic_analyzer_reg.v @@ -0,0 +1,314 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_logic_analyzer_reg ( + + input clk, + output reset, + + output [31:0] divider_counter_la, + output [31:0] divider_counter_pg, + output [15:0] io_selection, + + output [17:0] edge_detect_enable, + output [17:0] rise_edge_enable, + output [17:0] fall_edge_enable, + output [17:0] low_level_enable, + output [17:0] high_level_enable, + output [31:0] fifo_depth, + output [31:0] trigger_delay, + output [ 6:0] trigger_logic, + output clock_select, + output [15:0] overwrite_enable, + output [15:0] overwrite_data, + input [15:0] input_data, + output [15:0] od_pp_n, + + output [31:0] trigger_holdoff, + output [19:0] pg_trigger_config, + + input triggered, + output streaming, + output [ 9:0] data_delay_control, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [ 4:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [ 4:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack +); + + // internal registers + + reg [31:0] up_version = 32'h00020100; + reg [31:0] up_scratch = 0; + reg [31:0] up_divider_counter_la = 0; + reg [31:0] up_divider_counter_pg = 0; + reg [15:0] up_io_selection = 16'h0; + + reg [17:0] up_edge_detect_enable = 0; + reg [17:0] up_rise_edge_enable = 0; + reg [17:0] up_fall_edge_enable = 0; + reg [17:0] up_low_level_enable = 0; + reg [17:0] up_high_level_enable = 0; + reg [31:0] up_fifo_depth = 0; + reg [31:0] up_trigger_delay = 0; + reg [ 6:0] up_trigger_logic = 0; + reg up_clock_select = 0; + reg [15:0] up_overwrite_enable = 0; + reg [15:0] up_overwrite_data = 0; + reg [15:0] up_od_pp_n = 0; + reg [31:0] up_trigger_holdoff = 32'h0; + reg [19:0] up_pg_trigger_config = 20'h0; + reg up_triggered = 0; + reg up_streaming = 0; + reg [ 9:0] up_data_delay_control = 10'd0; + + wire [15:0] up_input_data; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_scratch <= 'd0; + up_divider_counter_la <= 'd0; + up_divider_counter_pg <= 'd0; + up_edge_detect_enable <= 'd0; + up_rise_edge_enable <= 'd0; + up_fall_edge_enable <= 'd0; + up_low_level_enable <= 'd0; + up_high_level_enable <= 'd0; + up_fifo_depth <= 'd0; + up_trigger_delay <= 'd0; + up_trigger_logic <= 'd0; + up_clock_select <= 'd0; + up_overwrite_enable <= 'd0; + up_overwrite_data <= 'd0; + up_io_selection <= 16'h0; + up_od_pp_n <= 16'h0; + up_triggered <= 1'd0; + up_streaming <= 1'd0; + up_trigger_holdoff <= 32'h0; + up_pg_trigger_config <= 20'd0; + up_data_delay_control <= 10'h0; + end else begin + up_wack <= up_wreq; + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h1)) begin + up_scratch <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h2)) begin + up_divider_counter_la <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h3)) begin + up_divider_counter_pg <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h4)) begin + up_io_selection <= up_wdata[15:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h5)) begin + up_edge_detect_enable <= up_wdata[17:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h6)) begin + up_rise_edge_enable <= up_wdata[17:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h7)) begin + up_fall_edge_enable <= up_wdata[17:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h8)) begin + up_low_level_enable <= up_wdata[17:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h9)) begin + up_high_level_enable <= up_wdata[17:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'ha)) begin + up_fifo_depth <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hb)) begin + up_trigger_logic <= up_wdata[6:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hc)) begin + up_clock_select <= up_wdata[0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'hd)) begin + up_overwrite_enable <= up_wdata[15:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'he)) begin + up_overwrite_data <= up_wdata[15:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h10)) begin + up_od_pp_n <= up_wdata[15:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h11)) begin + up_trigger_delay <= up_wdata; + end + if (triggered == 1'b1) begin + up_triggered <= 1'b1; + end else if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h12)) begin + up_triggered <= up_triggered & ~up_wdata[0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h13)) begin + up_streaming <= up_wdata[0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h14)) begin + up_trigger_holdoff <= up_wdata[31:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h15)) begin + up_pg_trigger_config <= up_wdata[19:0]; + end + if ((up_wreq == 1'b1) && (up_waddr[4:0] == 5'h16)) begin + up_data_delay_control <= up_wdata[9:0]; + end + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq; + if (up_rreq == 1'b1) begin + case (up_raddr[4:0]) + 5'h0: up_rdata <= up_version; + 5'h1: up_rdata <= up_scratch; + 5'h2: up_rdata <= up_divider_counter_la; + 5'h3: up_rdata <= up_divider_counter_pg; + 5'h4: up_rdata <= {16'h0,up_io_selection}; + 5'h5: up_rdata <= {14'h0,up_edge_detect_enable}; + 5'h6: up_rdata <= {14'h0,up_rise_edge_enable}; + 5'h7: up_rdata <= {14'h0,up_fall_edge_enable}; + 5'h8: up_rdata <= {14'h0,up_low_level_enable}; + 5'h9: up_rdata <= {14'h0,up_high_level_enable}; + 5'ha: up_rdata <= up_fifo_depth; + 5'hb: up_rdata <= {25'h0,up_trigger_logic}; + 5'hc: up_rdata <= {31'h0,up_clock_select}; + 5'hd: up_rdata <= {16'h0,up_overwrite_enable}; + 5'he: up_rdata <= {16'h0,up_overwrite_data}; + 5'hf: up_rdata <= {16'h0,up_input_data}; + 5'h10: up_rdata <= {16'h0,up_od_pp_n}; + 5'h11: up_rdata <= up_trigger_delay; + 5'h12: up_rdata <= {31'h0,up_triggered}; + 5'h13: up_rdata <= {31'h0,up_streaming}; + 5'h14: up_rdata <= up_trigger_holdoff; + 5'h15: up_rdata <= {12'h0,up_pg_trigger_config}; + 5'h16: up_rdata <= {22'h0,up_data_delay_control}; + default: up_rdata <= 0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + ad_rst i_core_rst_reg ( + .rst_async(~up_rstn), + .clk(clk), + .rstn(), + .rst(reset)); + + up_xfer_cntrl #( + .DATA_WIDTH(353) + ) i_xfer_cntrl ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_cntrl ({ up_streaming, // 1 + up_od_pp_n, // 16 + up_overwrite_data, // 16 + up_overwrite_enable, // 16 + up_clock_select, // 1 + up_trigger_logic, // 7 + up_fifo_depth, // 32 + up_trigger_delay, // 32 + up_trigger_holdoff, // 32 + up_high_level_enable, // 18 + up_low_level_enable, // 18 + up_fall_edge_enable, // 18 + up_rise_edge_enable, // 18 + up_edge_detect_enable, // 18 + up_io_selection, // 16 + up_pg_trigger_config, // 20 + up_divider_counter_pg, // 32 + up_divider_counter_la, // 32 + up_data_delay_control}), // 10 + + .up_xfer_done (), + .d_rst (1'b0), + .d_clk (clk), + .d_data_cntrl ({ streaming, // 1 + od_pp_n, // 16 + overwrite_data, // 16 + overwrite_enable, // 16 + clock_select, // 1 + trigger_logic, // 7 + fifo_depth, // 32 + trigger_delay, // 32 + trigger_holdoff, // 32 + high_level_enable, // 18 + low_level_enable, // 18 + fall_edge_enable, // 18 + rise_edge_enable, // 18 + edge_detect_enable, // 18 + io_selection, // 16 + pg_trigger_config, // 20 + divider_counter_pg, // 32 + divider_counter_la, // 32 + data_delay_control})); // 10 + + up_xfer_status #( + .DATA_WIDTH(16) + ) i_xfer_status ( + // up interface + + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_data_status(up_input_data), + + // device interface + + .d_rst(1'd0), + .d_clk(clk), + .d_data_status(input_data)); + +endmodule diff --git a/adi_library/axi_logic_analyzer/axi_logic_analyzer_trigger.v b/adi_library/axi_logic_analyzer/axi_logic_analyzer_trigger.v new file mode 100644 index 00000000..38293dfa --- /dev/null +++ b/adi_library/axi_logic_analyzer/axi_logic_analyzer_trigger.v @@ -0,0 +1,187 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_logic_analyzer_trigger ( + + input clk, + input reset, + + input [15:0] data, + input data_valid, + input [ 1:0] trigger_i, + input trigger_in, + + input [17:0] edge_detect_enable, + input [17:0] rise_edge_enable, + input [17:0] fall_edge_enable, + input [17:0] low_level_enable, + input [17:0] high_level_enable, + + input [ 6:0] trigger_logic, + + output reg trigger_out, + output reg trigger_out_adc +); + + reg [ 1:0] ext_t_m = 'd0; + reg [ 1:0] ext_t_low_level_hold = 'd0; + reg [ 1:0] ext_t_high_level_hold = 'd0; + reg [ 1:0] ext_t_edge_detect_hold = 'd0; + reg [ 1:0] ext_t_rise_edge_hold = 'd0; + reg [ 1:0] ext_t_fall_edge_hold = 'd0; + reg ext_t_low_level_ack = 'd0; + reg ext_t_high_level_ack = 'd0; + reg ext_t_edge_detect_ack = 'd0; + reg ext_t_rise_edge_ack = 'd0; + reg ext_t_fall_edge_ack = 'd0; + reg [ 15:0] data_m1 = 'd0; + reg [ 15:0] low_level = 'd0; + reg [ 15:0] high_level = 'd0; + reg [ 15:0] edge_detect = 'd0; + reg [ 15:0] rise_edge = 'd0; + reg [ 15:0] fall_edge = 'd0; + reg [ 15:0] low_level_m = 'd0; + reg [ 15:0] high_level_m = 'd0; + reg [ 15:0] edge_detect_m = 'd0; + reg [ 15:0] rise_edge_m = 'd0; + reg [ 15:0] fall_edge_m = 'd0; + + reg trigger_active; + reg trigger_active_mux; + reg trigger_active_d1; + + always @(posedge clk) begin + if (data_valid == 1'b1) begin + trigger_active_d1 <= trigger_active_mux; + trigger_out <= trigger_active_d1; + trigger_out_adc <= trigger_active_mux; + end + end + + // trigger logic: + // 0 OR + // 1 AND + + always @(posedge clk) begin + if (data_valid == 1'b1) begin + case (trigger_logic[0]) + 0: trigger_active = |(({ext_t_edge_detect_hold, edge_detect_m} & edge_detect_enable) | + ({ext_t_rise_edge_hold, rise_edge_m} & rise_edge_enable) | + ({ext_t_fall_edge_hold, fall_edge_m} & fall_edge_enable) | + ({ext_t_low_level_hold, low_level_m} & low_level_enable) | + ({ext_t_high_level_hold , high_level_m} & high_level_enable)); + 1: trigger_active = &(({ext_t_edge_detect_hold, edge_detect_m} | ~edge_detect_enable) & + ({ext_t_rise_edge_hold, rise_edge_m} | ~rise_edge_enable) & + ({ext_t_fall_edge_hold, fall_edge_m} | ~fall_edge_enable) & + ({ext_t_low_level_hold, low_level_m} | ~low_level_enable) & + ({ext_t_high_level_hold , high_level_m} | ~high_level_enable)); + default: trigger_active = 1'b1; + endcase + end + end + + always @(*) begin + case (trigger_logic[6:4]) + 3'd0: trigger_active_mux = trigger_active; + 3'd1: trigger_active_mux = trigger_in; + 3'd2: trigger_active_mux = trigger_active & trigger_in; + 3'd3: trigger_active_mux = trigger_active | trigger_in; + 3'd4: trigger_active_mux = trigger_active ^ trigger_in; + 3'd7: trigger_active_mux = 1'b0; // trigger disable + default: trigger_active_mux = 1'b0; + endcase + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + data_m1 <= 'd0; + edge_detect <= 'd0; + rise_edge <= 'd0; + fall_edge <= 'd0; + low_level <= 'd0; + high_level <= 'd0; + end else begin + if (data_valid == 1'b1) begin + data_m1 <= data; + edge_detect <= data_m1 ^ data; + rise_edge <= (data_m1 ^ data) & data; + fall_edge <= (data_m1 ^ data) & ~data; + low_level <= ~data; + high_level <= data; + + edge_detect_m <= edge_detect; + rise_edge_m <= rise_edge; + fall_edge_m <= fall_edge; + low_level_m <= low_level; + high_level_m <= high_level; + end + end + end + + // external trigger detect + + always @(posedge clk) begin + if (reset == 1'b1) begin + ext_t_m <= 'd0; + ext_t_edge_detect_hold <= 'd0; + ext_t_rise_edge_hold <= 'd0; + ext_t_fall_edge_hold <= 'd0; + ext_t_low_level_hold <= 'd0; + ext_t_high_level_hold <= 'd0; + end else begin + ext_t_m <= trigger_i; + + ext_t_edge_detect_hold <= ext_t_edge_detect_ack ? 2'b0 : + (ext_t_m ^ trigger_i) | ext_t_edge_detect_hold; + ext_t_rise_edge_hold <= ext_t_rise_edge_ack ? 2'b0 : + ((ext_t_m ^ trigger_i) & trigger_i) | ext_t_rise_edge_hold; + ext_t_fall_edge_hold <= ext_t_fall_edge_ack ? 2'b0 : + ((ext_t_m ^ trigger_i) & ~trigger_i) | ext_t_fall_edge_hold; + ext_t_low_level_hold <= ext_t_low_level_ack ? 2'b0 : + (~trigger_i) | ext_t_low_level_hold; + ext_t_high_level_hold <= ext_t_high_level_ack ? 2'b0 : + (trigger_i) | ext_t_high_level_hold; + + ext_t_edge_detect_ack <= data_valid & ( |ext_t_edge_detect_hold); + ext_t_rise_edge_ack <= data_valid & ( |ext_t_rise_edge_hold); + ext_t_fall_edge_ack <= data_valid & ( |ext_t_fall_edge_hold); + ext_t_low_level_ack <= data_valid & ( |ext_t_low_level_hold); + ext_t_high_level_ack <= data_valid & ( |ext_t_high_level_hold); + end + end + +endmodule diff --git a/adi_library/axi_logic_analyzer/component.xml b/adi_library/axi_logic_analyzer/component.xml new file mode 100644 index 00000000..6223a54a --- /dev/null +++ b/adi_library/axi_logic_analyzer/component.xml @@ -0,0 +1,1079 @@ + + + analog.com + user + axi_logic_analyzer + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + clk + + + + + + + CLK + + + clk + + + + + + clk_out + + + + + + + CLK + + + clk_out + + + + + + + + s_axi + + axi_lite + 0 + 128 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_logic_analyzer + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + b8e921af + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_logic_analyzer + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + ed2a0402 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f92e9879 + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + clk_out + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_i + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_o + + out + + 15 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_t + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + trigger_i + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data + + out + + 15 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_data + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + dac_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_read + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + external_rate + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + external_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + external_decimation_en + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + trigger_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + trigger_out + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + trigger_out_adc + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + fifo_depth + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 6 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 6 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + axi_logic_analyzer_constr.xdc + xdc + + + ../common/ad_rst.v + verilogSource + + + axi_logic_analyzer_reg.v + verilogSource + + + axi_logic_analyzer_trigger.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_logic_analyzer.v + verilogSource + CHECKSUM_27451ef3 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_rst.v + verilogSource + + + axi_logic_analyzer_reg.v + verilogSource + + + axi_logic_analyzer_trigger.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_logic_analyzer.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_logic_analyzer_v1_0.tcl + tclSource + CHECKSUM_f92e9879 + XGUI_VERSION_2 + + + + axi_logic_analyzer_v1_0 + + + Component_Name + axi_logic_analyzer_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_logic_analyzer_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_logic_analyzer + 1 + 2024-01-14T03:48:14Z + + + 2023.2.1 + + + + + + diff --git a/adi_library/axi_logic_analyzer/xgui/axi_logic_analyzer_v1_0.tcl b/adi_library/axi_logic_analyzer/xgui/axi_logic_analyzer_v1_0.tcl new file mode 100644 index 00000000..0db18e9a --- /dev/null +++ b/adi_library/axi_logic_analyzer/xgui/axi_logic_analyzer_v1_0.tcl @@ -0,0 +1,10 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + + diff --git a/adi_library/axi_ltc235x/.timestamp_intel b/adi_library/axi_ltc235x/.timestamp_intel new file mode 100644 index 00000000..e69de29b diff --git a/adi_library/axi_ltc235x/Makefile b/adi_library/axi_ltc235x/Makefile new file mode 100644 index 00000000..2321a36f --- /dev/null +++ b/adi_library/axi_ltc235x/Makefile @@ -0,0 +1,26 @@ +############################################################################### +## Copyright (C) 2018-2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +############################################################################### + +LIBRARY_NAME := axi_ltc235x + +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_adc_channel.v +GENERIC_DEPS += ../common/up_adc_common.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_ltc235x.v +GENERIC_DEPS += axi_ltc235x_cmos.v +GENERIC_DEPS += axi_ltc235x_lvds.v + +INTEL_DEPS += ../intel/common/up_clock_mon_constr.sdc +INTEL_DEPS += ../intel/common/up_rst_constr.sdc +INTEL_DEPS += ../intel/common/up_xfer_cntrl_constr.sdc +INTEL_DEPS += ../intel/common/up_xfer_status_constr.sdc +INTEL_DEPS += axi_ltc235x_hw.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_ltc235x/axi_ltc235x.v b/adi_library/axi_ltc235x/axi_ltc235x.v new file mode 100644 index 00000000..999be47d --- /dev/null +++ b/adi_library/axi_ltc235x/axi_ltc235x.v @@ -0,0 +1,512 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ltc235x #( + + parameter ID = 0, + parameter XILINX_INTEL_N = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter LVDS_CMOS_N = 0, + parameter LANE_0_ENABLE = 1, + parameter LANE_1_ENABLE = 1, + parameter LANE_2_ENABLE = 1, + parameter LANE_3_ENABLE = 1, + parameter LANE_4_ENABLE = 1, + parameter LANE_5_ENABLE = 1, + parameter LANE_6_ENABLE = 1, + parameter LANE_7_ENABLE = 1, + parameter EXTERNAL_CLK = 0, + parameter LTC235X_FAMILY = 0, + parameter NUM_CHANNELS = 8, + parameter DATA_WIDTH = 18 +) ( + + // physical data interface + + input external_clk, + + // common + input busy, + output lvds_cmos_n, + + // cmos + output sdi, + output scki, + input scko, + input [ 7:0] sdo, + + // lvds + output sdi_p, + output sdi_n, + output scki_p, + output scki_n, + input scko_p, + input scko_n, + input sdo_p, + input sdo_n, + + // AXI Slave Memory Map + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + + // Write FIFO interface + + input adc_dovf, + output adc_valid_0, + output adc_valid_1, + output adc_valid_2, + output adc_valid_3, + output adc_valid_4, + output adc_valid_5, + output adc_valid_6, + output adc_valid_7, + output adc_enable_0, + output adc_enable_1, + output adc_enable_2, + output adc_enable_3, + output adc_enable_4, + output adc_enable_5, + output adc_enable_6, + output adc_enable_7, + output [31:0] adc_data_0, + output [31:0] adc_data_1, + output [31:0] adc_data_2, + output [31:0] adc_data_3, + output [31:0] adc_data_4, + output [31:0] adc_data_5, + output [31:0] adc_data_6, + output [31:0] adc_data_7 +); + + // localparam + + localparam [ 7:0] ACTIVE_LANES = { + LANE_7_ENABLE == 1 ? 1'b1 : 1'b0, + LANE_6_ENABLE == 1 ? 1'b1 : 1'b0, + LANE_5_ENABLE == 1 ? 1'b1 : 1'b0, + LANE_4_ENABLE == 1 ? 1'b1 : 1'b0, + LANE_3_ENABLE == 1 ? 1'b1 : 1'b0, + LANE_2_ENABLE == 1 ? 1'b1 : 1'b0, + LANE_1_ENABLE == 1 ? 1'b1 : 1'b0, + LANE_0_ENABLE == 1 ? 1'b1 : 1'b0}; + localparam [ 0:0] RD_RAW_DATA = 1'b1; + localparam [ 0:0] CMOS_OR_LVDS_N = ~LVDS_CMOS_N[0]; + localparam [31:0] CONFIG = {18'd0, RD_RAW_DATA, 5'b0, CMOS_OR_LVDS_N, 7'b0}; // truncated value with size 45 to match size of target (32) + + // internal registers + + reg up_wack = 1'b0; + reg up_rack = 1'b0; + reg [31:0] up_rdata = 32'b0; + + // internal signals + + wire [23:0] softspan_24; + wire [ 2:0] softspan_3[0:7]; + + wire adc_valid; + + wire up_clk; + wire up_rstn; + wire up_rreq_s; + wire [13:0] up_raddr_s; + wire up_wreq_s; + wire [13:0] up_waddr_s; + + wire adc_clk_s; + + wire [13:0] up_addr_s; + wire [31:0] up_wdata_s; + wire [31:0] up_rdata_s[0:8]; + wire [ 8:0] up_rack_s; + wire [ 8:0] up_wack_s; + + // read raw, feature + wire rd_req_s; + wire wr_req_s; + wire [15:0] wr_data_s; + wire [15:0] rd_data_s; + wire rd_valid_s; + + wire adc_rst_s; + + wire [ 7:0] adc_enable; + wire [ 2:0] adc_status_header[0:7]; + wire [31:0] adc_data[0:7]; + + // defaults + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + assign lvds_cmos_n = LVDS_CMOS_N[0]; + + assign adc_valid_0 = adc_valid; + assign adc_valid_1 = adc_valid; + assign adc_valid_2 = adc_valid; + assign adc_valid_3 = adc_valid; + assign adc_valid_4 = adc_valid; + assign adc_valid_5 = adc_valid; + assign adc_valid_6 = adc_valid; + assign adc_valid_7 = adc_valid; + + assign adc_enable_0 = adc_enable[0]; + assign adc_enable_1 = adc_enable[1]; + assign adc_enable_2 = adc_enable[2]; + assign adc_enable_3 = adc_enable[3]; + assign adc_enable_4 = adc_enable[4]; + assign adc_enable_5 = adc_enable[5]; + assign adc_enable_6 = adc_enable[6]; + assign adc_enable_7 = adc_enable[7]; + + assign adc_data_0 = adc_data[0]; + assign adc_data_1 = adc_data[1]; + assign adc_data_2 = adc_data[2]; + assign adc_data_3 = adc_data[3]; + assign adc_data_4 = adc_data[4]; + assign adc_data_5 = adc_data[5]; + assign adc_data_6 = adc_data[6]; + assign adc_data_7 = adc_data[7]; + + generate + if (NUM_CHANNELS == 8) begin + assign softspan_24 = {softspan_3[7], softspan_3[6], softspan_3[5], softspan_3[4], softspan_3[3], softspan_3[2], softspan_3[1], softspan_3[0]}; + end else if (NUM_CHANNELS == 4) begin + assign softspan_24 = {softspan_3[3], softspan_3[2], softspan_3[1], softspan_3[0], 12'b0}; + end else begin + assign softspan_24 = {softspan_3[1], softspan_3[0], 18'b0}; + end + endgenerate + + // processor read/write interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_wack <= |up_wack_s; + up_rack <= |up_rack_s; + up_rdata <= up_rdata_s[0] | + up_rdata_s[1] | + up_rdata_s[2] | + up_rdata_s[3] | + up_rdata_s[4] | + up_rdata_s[5] | + up_rdata_s[6] | + up_rdata_s[7] | + up_rdata_s[8]; + end + end + + // CMOS/LVDS INTERFACE + generate + if (EXTERNAL_CLK == 1'b1) begin + assign adc_clk_s = external_clk; + end else begin + assign adc_clk_s = up_clk; + end + + if (LVDS_CMOS_N == 1) begin + axi_ltc235x_lvds #( + .XILINX_INTEL_N (XILINX_INTEL_N), + .LTC235X_FAMILY (LTC235X_FAMILY), + .NUM_CHANNELS (NUM_CHANNELS), + .DATA_WIDTH (DATA_WIDTH) + ) i_ltc235x_lvds ( + .rst (adc_rst_s), + .clk (adc_clk_s), + .adc_enable (adc_enable), + .softspan_next (softspan_24), + .scki_p (scki_p), + .scki_n (scki_n), + .sdi_p (sdi_p), + .sdi_n (sdi_n), + .scko_p (scko_p), + .scko_n (scko_n), + .sdo_p (sdo_p), + .sdo_n (sdo_n), + .busy (busy), + .adc_ch0_id (adc_status_header[0]), + .adc_ch1_id (adc_status_header[1]), + .adc_ch2_id (adc_status_header[2]), + .adc_ch3_id (adc_status_header[3]), + .adc_ch4_id (adc_status_header[4]), + .adc_ch5_id (adc_status_header[5]), + .adc_ch6_id (adc_status_header[6]), + .adc_ch7_id (adc_status_header[7]), + .adc_data_0 (adc_data_0), + .adc_data_1 (adc_data_1), + .adc_data_2 (adc_data_2), + .adc_data_3 (adc_data_3), + .adc_data_4 (adc_data_4), + .adc_data_5 (adc_data_5), + .adc_data_6 (adc_data_6), + .adc_data_7 (adc_data_7), + .adc_softspan_0 (), + .adc_softspan_1 (), + .adc_softspan_2 (), + .adc_softspan_3 (), + .adc_softspan_4 (), + .adc_softspan_5 (), + .adc_softspan_6 (), + .adc_softspan_7 (), + .adc_valid (adc_valid)); + end else begin + axi_ltc235x_cmos #( + .LTC235X_FAMILY (LTC235X_FAMILY), + .ACTIVE_LANES (ACTIVE_LANES), + .NUM_CHANNELS (NUM_CHANNELS), + .DATA_WIDTH (DATA_WIDTH) + ) i_ltc235x_cmos ( + .rst (adc_rst_s), + .clk (adc_clk_s), + .adc_enable (adc_enable), + .softspan_next (softspan_24), + .scki (scki), + .sdi (sdi), + .scko (scko), + .sdo (sdo), + .busy (busy), + .adc_ch0_id (adc_status_header[0]), + .adc_ch1_id (adc_status_header[1]), + .adc_ch2_id (adc_status_header[2]), + .adc_ch3_id (adc_status_header[3]), + .adc_ch4_id (adc_status_header[4]), + .adc_ch5_id (adc_status_header[5]), + .adc_ch6_id (adc_status_header[6]), + .adc_ch7_id (adc_status_header[7]), + .adc_data_0 (adc_data_0), + .adc_data_1 (adc_data_1), + .adc_data_2 (adc_data_2), + .adc_data_3 (adc_data_3), + .adc_data_4 (adc_data_4), + .adc_data_5 (adc_data_5), + .adc_data_6 (adc_data_6), + .adc_data_7 (adc_data_7), + .adc_softspan_0 (), + .adc_softspan_1 (), + .adc_softspan_2 (), + .adc_softspan_3 (), + .adc_softspan_4 (), + .adc_softspan_5 (), + .adc_softspan_6 (), + .adc_softspan_7 (), + .adc_valid (adc_valid)); + end + endgenerate + + // regmap adc channels + + generate + genvar i; + for (i = 0; i < NUM_CHANNELS; i=i+1) begin : regmap_channels + up_adc_channel #( + .CHANNEL_ID(i) + ) i_up_adc_channel ( + .adc_clk (adc_clk_s), + .adc_rst (adc_rst_s), + .adc_enable (adc_enable[i]), + .adc_iqcor_enb (), + .adc_dcfilt_enb (), + .adc_dfmt_se (), + .adc_dfmt_type (), + .adc_dfmt_enable (), + .adc_dcfilt_offset (), + .adc_dcfilt_coeff (), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pnseq_sel (), + .adc_data_sel (), + .adc_pn_err (1'b0), + .adc_pn_oos (1'b0), + .adc_or (1'b0), + .adc_read_data (adc_data[i]), + .adc_status_header({5'd0, adc_status_header[i]}), + .adc_crc_err(1'b0), + .adc_softspan (softspan_3[i]), + .up_adc_crc_err (), + .up_adc_pn_err (), + .up_adc_pn_oos (), + .up_adc_or (), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd32), + .adc_usr_datatype_bits (8'd32), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[i]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[i]), + .up_rack (up_rack_s[i])); + end + endgenerate + + // up adc common + + up_adc_common #( + .ID(ID), + .CONFIG(CONFIG) + ) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk_s), + .adc_rst (adc_rst_s), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status ('h1), + .adc_sync_status (1'b1), + .adc_status_ovf (adc_dovf), + .adc_clk_ratio (32'd1), + .adc_start_code (), + .adc_sref_sync (), + .adc_sync (), + .adc_ext_sync_arm(), + .adc_ext_sync_disarm(), + .adc_ext_sync_manual_req(), + .adc_num_lanes(), + .adc_custom_control(), + .adc_crc_enable(), + .adc_sdr_ddr_n(), + .adc_symb_op(), + .adc_symb_8_16b(), + .up_pps_rcounter (32'b0), + .up_pps_status (1'b0), + .up_pps_irq_mask (), + .up_adc_r1_mode(), + .up_adc_ce (), + .up_status_pn_err (1'b0), + .up_status_pn_oos (1'b0), + .up_status_or (1'b0), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .adc_config_wr (), + .adc_config_ctrl (), + .adc_config_rd (32'd0), + .adc_ctrl_status (1'd0), + .up_usr_chanmax_out (), + .up_usr_chanmax_in (8), + .up_adc_gpio_in (32'b0), + .up_adc_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[8]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[8]), + .up_rack (up_rack_s[8])); + + // up bus interface + + up_axi #( + .AXI_ADDRESS_WIDTH (16) + ) i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ltc235x/axi_ltc235x_cmos.v b/adi_library/axi_ltc235x/axi_ltc235x_cmos.v new file mode 100644 index 00000000..1eedd7ef --- /dev/null +++ b/adi_library/axi_ltc235x/axi_ltc235x_cmos.v @@ -0,0 +1,529 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ltc235x_cmos #( + parameter ACTIVE_LANES = 8'b1111_1111, + parameter LTC235X_FAMILY = 0, + parameter NUM_CHANNELS = 8, // 8 for 2358, 4 for 2357, 2 for 2353 + parameter DATA_WIDTH = 18 // 18 or 16 based on -18/-16 +) ( + + input rst, + input clk, + input [ 7:0] adc_enable, + input [23:0] softspan_next, + + // physical interface + + output scki, + output sdi, + input scko, + input [ 7:0] sdo, + input busy, + + // FIFO interface + + output [ 2:0] adc_ch0_id, + output [ 2:0] adc_ch1_id, + output [ 2:0] adc_ch2_id, + output [ 2:0] adc_ch3_id, + output [ 2:0] adc_ch4_id, + output [ 2:0] adc_ch5_id, + output [ 2:0] adc_ch6_id, + output [ 2:0] adc_ch7_id, + + output [31:0] adc_data_0, + output [31:0] adc_data_1, + output [31:0] adc_data_2, + output [31:0] adc_data_3, + output [31:0] adc_data_4, + output [31:0] adc_data_5, + output [31:0] adc_data_6, + output [31:0] adc_data_7, + + output [ 2:0] adc_softspan_0, + output [ 2:0] adc_softspan_1, + output [ 2:0] adc_softspan_2, + output [ 2:0] adc_softspan_3, + output [ 2:0] adc_softspan_4, + output [ 2:0] adc_softspan_5, + output [ 2:0] adc_softspan_6, + output [ 2:0] adc_softspan_7, + + output reg adc_valid +); + + localparam DW = 24; // packet size + localparam BW = DW - 1; + + // internal registers + + reg busy_m1; + reg busy_m2; + reg busy_m3; + + reg [ 4:0] scki_counter = 5'h0; + reg [ 4:0] data_counter = 5'h0; + + reg scki_i; + reg scki_d; + + reg [BW:0] adc_lane_0; + reg [BW:0] adc_lane_1; + reg [BW:0] adc_lane_2; + reg [BW:0] adc_lane_3; + reg [BW:0] adc_lane_4; + reg [BW:0] adc_lane_5; + reg [BW:0] adc_lane_6; + reg [BW:0] adc_lane_7; + + reg [BW:0] adc_data_init[7:0]; + reg [BW:0] adc_data_store[7:0]; + + reg [ 2:0] lane_0_ch = 3'd0; + reg [ 2:0] lane_1_ch = 3'd0; + reg [ 2:0] lane_2_ch = 3'd0; + reg [ 2:0] lane_3_ch = 3'd0; + reg [ 2:0] lane_4_ch = 3'd0; + reg [ 2:0] lane_5_ch = 3'd0; + reg [ 2:0] lane_6_ch = 3'd0; + reg [ 2:0] lane_7_ch = 3'd0; + + reg [ 3:0] adc_lane0_shift; + reg [ 3:0] adc_lane1_shift; + reg [ 3:0] adc_lane2_shift; + reg [ 3:0] adc_lane3_shift; + reg [ 3:0] adc_lane4_shift; + reg [ 3:0] adc_lane5_shift; + reg [ 3:0] adc_lane6_shift; + reg [ 3:0] adc_lane7_shift; + + reg [ 3:0] adc_lane0_shift_d; + reg [ 3:0] adc_lane1_shift_d; + reg [ 3:0] adc_lane2_shift_d; + reg [ 3:0] adc_lane3_shift_d; + reg [ 3:0] adc_lane4_shift_d; + reg [ 3:0] adc_lane5_shift_d; + reg [ 3:0] adc_lane6_shift_d; + reg [ 3:0] adc_lane7_shift_d; + + reg adc_valid_init; + reg adc_valid_init_d; + + reg [ 7:0] ch_data_lock = 8'hff; + reg [ 7:0] ch_capture; + reg [ 7:0] ch_captured; + + reg scko_d; + reg [ 7:0] sdo_d; + + reg [ 4:0] sdi_index = 5'd23; + + reg [23:0] softspan_next_int; + + // internal wires + + wire start_transfer_s; + + wire scki_cnt_rst; + + wire acquire_data; + + wire [17:0] adc_data_raw_s [7:0]; + wire [31:0] adc_data_sign_s [7:0]; + wire [31:0] adc_data_zero_s [7:0]; + wire [31:0] adc_data_s [7:0]; + wire [ 2:0] adc_ch_id_s [7:0]; + wire [ 2:0] adc_softspan_s [7:0]; + + always @(posedge clk) begin + if (rst == 1'b1) begin + busy_m1 <= 1'b0; + busy_m2 <= 1'b0; + end else begin + busy_m1 <= busy; + busy_m2 <= busy_m1; + busy_m3 <= busy_m2; + end + end + + assign start_transfer_s = busy_m3 & ~busy_m2; + + // reading clock logic + always @(posedge clk) begin + if (rst) begin + scki_counter <= 5'h0; + scki_i <= 1'b1; + scki_d <= 1'b0; + end else begin + scki_d <= scki_i; + if (acquire_data == 1'b0) begin + scki_counter <= 5'h0; + scki_i <= 1'b1; + end else if (scki_cnt_rst & (scki_d & ~scki_i)) begin // end of a capture + scki_counter <= 5'h1; + scki_i <= 1'b1; + end else if (scki_i == 1'b0) begin + scki_counter <= scki_counter + 5'd1; + scki_i <= 1'b1; + end else begin + scki_counter <= scki_counter; + scki_i <= ~scki_i; + end + end + end + + assign scki_cnt_rst = (scki_counter == DW); + assign scki = scki_i | ~acquire_data; + + /* + The device sends each channel data on one of the 8 lines. + Data is stored in the device in a ring buffer. After the first packet is read + and no new conversion is requested if the reading process is restarted, + the new data on the lines will be from the next index from the ring buffer. + e.g For second read process without a conversion start + line 0 = channel 1, line 1 = channel 2, line 2 = channel 3; so on and so forth. + + The ring buffer contains the crc data on the 8(last position.) + e.g for a 4'th reading cycle: + line 0 = ch 3 + line 1 = ch 4 + line 2 = ch 5 + line 3 = ch 6 + line 4 = ch 7 + line 5 = crc + line 6 = ch 0 + line 7 = ch 1 + + Because there is no rule for a specific number of lanes to be enabled at a given time + the interface can handle every combination of enabled lanes with enabled channels. + The valid signal will only be asserted after all enabled channels are stored. + This means that the user must adjust the sampling frequency based on the + interface clock frequency and the maximum position/index + difference +1 of a channel data and the first enabled lane that will + pass that channels data, maximum difference is 8(e.g line 0 to line 7). + e.g. If only lanes 1 and 2(0 to 7) are enabled, + 1. The user wants to capture the 6'th(0 to 7) channel, 5 reading cycles are required. + 2. The user wants to capture channel 0, 8 reading cycles are required. + */ + + // capture data per lane in rx buffers adc_lane_X on every edge of scko + // ignore when busy forced scko to 0 + always @(posedge clk) begin + scko_d <= scko; + sdo_d <= sdo; + if (scko != scko_d && scki != scki_d) begin + adc_lane_0 <= {adc_lane_0[BW-1:0], sdo_d[0]}; + adc_lane_1 <= {adc_lane_1[BW-1:0], sdo_d[1]}; + adc_lane_2 <= {adc_lane_2[BW-1:0], sdo_d[2]}; + adc_lane_3 <= {adc_lane_3[BW-1:0], sdo_d[3]}; + adc_lane_4 <= {adc_lane_4[BW-1:0], sdo_d[4]}; + adc_lane_5 <= {adc_lane_5[BW-1:0], sdo_d[5]}; + adc_lane_6 <= {adc_lane_6[BW-1:0], sdo_d[6]}; + adc_lane_7 <= {adc_lane_7[BW-1:0], sdo_d[7]}; + end + end + + // store the data from the rx buffers when all bits are received + // when data transaction window is done + // index is based by lane + always @(posedge clk) begin + if (rst == 1'b1) begin + adc_data_init[0] <= 'h0; + adc_data_init[1] <= 'h0; + adc_data_init[2] <= 'h0; + adc_data_init[3] <= 'h0; + adc_data_init[4] <= 'h0; + adc_data_init[5] <= 'h0; + adc_data_init[6] <= 'h0; + adc_data_init[7] <= 'h0; + data_counter <= 5'h0; + end else begin + data_counter <= scki_counter; + if (data_counter == DW) begin + adc_data_init[0] <= adc_lane_0; + adc_data_init[1] <= adc_lane_1; + adc_data_init[2] <= adc_lane_2; + adc_data_init[3] <= adc_lane_3; + adc_data_init[4] <= adc_lane_4; + adc_data_init[5] <= adc_lane_5; + adc_data_init[6] <= adc_lane_6; + adc_data_init[7] <= adc_lane_7; + end + end + end + + // lane_x_ch - channel corresponds to which lane, e.g. lane_0_ch stores the current channel lane 0 has + // ch_data_lock[i] - locks ch i, e.g. ch_data_lock[7] = 1 means data from channel 7 has already been sent to an active lane, channel 7 should now be locked + // dont acquire data if all channels are all already locked + always @(posedge clk) begin + if (start_transfer_s) begin + lane_0_ch <= 3'd0; + lane_1_ch <= 3'd1; + lane_2_ch <= 3'd2; + lane_3_ch <= 3'd3; + lane_4_ch <= 3'd4; + lane_5_ch <= 3'd5; + lane_6_ch <= 3'd6; + lane_7_ch <= 3'd7; + ch_data_lock <= 8'd0; + end else if (acquire_data == 1'b1 && (scki_cnt_rst & (~scki_d & scki_i))) begin + lane_0_ch <= lane_0_ch + 3'd1; + lane_1_ch <= lane_1_ch + 3'd1; + lane_2_ch <= lane_2_ch + 3'd1; + lane_3_ch <= lane_3_ch + 3'd1; + lane_4_ch <= lane_4_ch + 3'd1; + lane_5_ch <= lane_5_ch + 3'd1; + lane_6_ch <= lane_6_ch + 3'd1; + lane_7_ch <= lane_7_ch + 3'd1; + ch_data_lock[lane_0_ch] <= ACTIVE_LANES[0] ? 1'b1 : ch_data_lock[lane_0_ch]; + ch_data_lock[lane_1_ch] <= ACTIVE_LANES[1] ? 1'b1 : ch_data_lock[lane_1_ch]; + ch_data_lock[lane_2_ch] <= ACTIVE_LANES[2] ? 1'b1 : ch_data_lock[lane_2_ch]; + ch_data_lock[lane_3_ch] <= ACTIVE_LANES[3] ? 1'b1 : ch_data_lock[lane_3_ch]; + ch_data_lock[lane_4_ch] <= ACTIVE_LANES[4] ? 1'b1 : ch_data_lock[lane_4_ch]; + ch_data_lock[lane_5_ch] <= ACTIVE_LANES[5] ? 1'b1 : ch_data_lock[lane_5_ch]; + ch_data_lock[lane_6_ch] <= ACTIVE_LANES[6] ? 1'b1 : ch_data_lock[lane_6_ch]; + ch_data_lock[lane_7_ch] <= ACTIVE_LANES[7] ? 1'b1 : ch_data_lock[lane_7_ch]; + end + end + + assign acquire_data = ~((ch_data_lock[0] | ~adc_enable[0]) & + (ch_data_lock[1] | ~adc_enable[1]) & + (ch_data_lock[2] | ~adc_enable[2]) & + (ch_data_lock[3] | ~adc_enable[3]) & + (ch_data_lock[4] | ~adc_enable[4]) & + (ch_data_lock[5] | ~adc_enable[5]) & + (ch_data_lock[6] | ~adc_enable[6]) & + (ch_data_lock[7] | ~adc_enable[7])); + + // hold lane status and lane channel + // for datasyncing with valid signal + always @(posedge clk) begin + if (rst == 1'b1 || adc_valid == 1'b1) begin + adc_lane0_shift <= 4'd0; + adc_lane1_shift <= 4'd0; + adc_lane2_shift <= 4'd0; + adc_lane3_shift <= 4'd0; + adc_lane4_shift <= 4'd0; + adc_lane5_shift <= 4'd0; + adc_lane6_shift <= 4'd0; + adc_lane7_shift <= 4'd0; + adc_lane0_shift_d <= 4'd0; + adc_lane1_shift_d <= 4'd0; + adc_lane2_shift_d <= 4'd0; + adc_lane3_shift_d <= 4'd0; + adc_lane4_shift_d <= 4'd0; + adc_lane5_shift_d <= 4'd0; + adc_lane6_shift_d <= 4'd0; + adc_lane7_shift_d <= 4'd0; + end else begin + adc_lane0_shift <= {ACTIVE_LANES[0], lane_0_ch}; + adc_lane1_shift <= {ACTIVE_LANES[1], lane_1_ch}; + adc_lane2_shift <= {ACTIVE_LANES[2], lane_2_ch}; + adc_lane3_shift <= {ACTIVE_LANES[3], lane_3_ch}; + adc_lane4_shift <= {ACTIVE_LANES[4], lane_4_ch}; + adc_lane5_shift <= {ACTIVE_LANES[5], lane_5_ch}; + adc_lane6_shift <= {ACTIVE_LANES[6], lane_6_ch}; + adc_lane7_shift <= {ACTIVE_LANES[7], lane_7_ch}; + adc_lane0_shift_d <= adc_lane0_shift; + adc_lane1_shift_d <= adc_lane1_shift; + adc_lane2_shift_d <= adc_lane2_shift; + adc_lane3_shift_d <= adc_lane3_shift; + adc_lane4_shift_d <= adc_lane4_shift; + adc_lane5_shift_d <= adc_lane5_shift; + adc_lane6_shift_d <= adc_lane6_shift; + adc_lane7_shift_d <= adc_lane7_shift; + end + end + + // stores the data from the rx buffer, but now based on ch + // index is based on ch, not lane anymore + always @(posedge clk) begin + if (rst == 1'b1) begin + adc_data_store[0] <= 'd0; + adc_data_store[1] <= 'd0; + adc_data_store[2] <= 'd0; + adc_data_store[3] <= 'd0; + adc_data_store[4] <= 'd0; + adc_data_store[5] <= 'd0; + adc_data_store[6] <= 'd0; + adc_data_store[7] <= 'd0; + end else begin + if (!adc_valid_init_d & adc_valid_init) begin + if (adc_lane0_shift_d[3] == 1'b1) begin + adc_data_store[adc_lane0_shift_d[2:0]] <= adc_data_init[0]; + end + if (adc_lane1_shift_d[3] == 1'b1) begin + adc_data_store[adc_lane1_shift_d[2:0]] <= adc_data_init[1]; + end + if (adc_lane2_shift_d[3] == 1'b1) begin + adc_data_store[adc_lane2_shift_d[2:0]] <= adc_data_init[2]; + end + if (adc_lane3_shift_d[3] == 1'b1) begin + adc_data_store[adc_lane3_shift_d[2:0]] <= adc_data_init[3]; + end + if (adc_lane4_shift_d[3] == 1'b1) begin + adc_data_store[adc_lane4_shift_d[2:0]] <= adc_data_init[4]; + end + if (adc_lane5_shift_d[3] == 1'b1) begin + adc_data_store[adc_lane5_shift_d[2:0]] <= adc_data_init[5]; + end + if (adc_lane6_shift_d[3] == 1'b1) begin + adc_data_store[adc_lane6_shift_d[2:0]] <= adc_data_init[6]; + end + if (adc_lane7_shift_d[3] == 1'b1) begin + adc_data_store[adc_lane7_shift_d[2:0]] <= adc_data_init[7]; + end + end + end + end + + // extract info from the data bits + genvar i; + generate + for (i=0; i < 8; i=i+1) begin: format + assign adc_data_raw_s[i] = adc_data_store[i][BW:DW-DATA_WIDTH]; + assign adc_data_sign_s[i] = {{(32-DATA_WIDTH){adc_data_raw_s[i][DATA_WIDTH-1]}}, adc_data_raw_s[i]}; + assign adc_data_zero_s[i] = {{(32-DATA_WIDTH){1'b0}}, adc_data_raw_s[i]}; + assign adc_data_s[i] = (adc_softspan_s[i] == 3'b0)? 32'h0 : + (adc_softspan_s[i][1])? adc_data_sign_s[i] : + adc_data_zero_s[i] ; + if (NUM_CHANNELS == 8) begin + assign adc_ch_id_s[i] = adc_data_store[i][5:3]; + end else if (NUM_CHANNELS == 4) begin + assign adc_ch_id_s[i] = {1'b0, adc_data_store[i][4:3]}; + end else begin + assign adc_ch_id_s[i] = {2'b0, adc_data_store[i][3]}; + end + assign adc_softspan_s[i] = adc_data_store[i][2:0]; + end + endgenerate + + // assign extracted adc data to corresponding outputs + assign adc_data_0 = adc_data_s[0]; + assign adc_data_1 = adc_data_s[1]; + assign adc_data_2 = adc_data_s[2]; + assign adc_data_3 = adc_data_s[3]; + assign adc_data_4 = adc_data_s[4]; + assign adc_data_5 = adc_data_s[5]; + assign adc_data_6 = adc_data_s[6]; + assign adc_data_7 = adc_data_s[7]; + + // assign extracted adc channel id to corresponding outputs + assign adc_ch0_id = adc_ch_id_s[0]; + assign adc_ch1_id = adc_ch_id_s[1]; + assign adc_ch2_id = adc_ch_id_s[2]; + assign adc_ch3_id = adc_ch_id_s[3]; + assign adc_ch4_id = adc_ch_id_s[4]; + assign adc_ch5_id = adc_ch_id_s[5]; + assign adc_ch6_id = adc_ch_id_s[6]; + assign adc_ch7_id = adc_ch_id_s[7]; + + // assign extracted adc channel id to corresponding outputs + assign adc_softspan_0 = adc_softspan_s[0]; + assign adc_softspan_1 = adc_softspan_s[1]; + assign adc_softspan_2 = adc_softspan_s[2]; + assign adc_softspan_3 = adc_softspan_s[3]; + assign adc_softspan_4 = adc_softspan_s[4]; + assign adc_softspan_5 = adc_softspan_s[5]; + assign adc_softspan_6 = adc_softspan_s[6]; + assign adc_softspan_7 = adc_softspan_s[7]; + + // initial valid signal + always @(posedge clk) begin + if (rst == 1'b1) begin + adc_valid_init <= 1'b0; + end else begin + if (data_counter == DW && adc_valid_init == 1'b0) begin + adc_valid_init <= 1'b1; + end else begin + adc_valid_init <= 1'b0; + end + end + end + + // delayed both valid signal and data_lock signal + // for datasyncing with valid signal + always @(posedge clk) begin + if (rst == 1'b1 || adc_valid == 1'b1) begin + adc_valid <= 1'b0; + adc_valid_init_d <= 1'b0; + ch_capture <= 8'd0; + ch_captured <= 8'd0; + end else begin + ch_capture <= ch_data_lock; + ch_captured <= ch_capture; + adc_valid_init_d <= adc_valid_init; + adc_valid <= adc_valid_init_d & + (ch_captured[0] | ~adc_enable[0]) & + (ch_captured[1] | ~adc_enable[1]) & + (ch_captured[2] | ~adc_enable[2]) & + (ch_captured[3] | ~adc_enable[3]) & + (ch_captured[4] | ~adc_enable[4]) & + (ch_captured[5] | ~adc_enable[5]) & + (ch_captured[6] | ~adc_enable[6]) & + (ch_captured[7] | ~adc_enable[7]); + end + end + + // every negedge of scki, update index of sdi + always @(posedge clk) begin + if (start_transfer_s || rst) begin + sdi_index <= 5'd23; + end else begin + if (scki && !scki_d && sdi_index != 5'b11111) begin + sdi_index <= sdi_index - 5'b1; + end + end + end + + // update next softspan configuration every after busy + always @(posedge clk) begin + if (rst == 1'b1) begin + softspan_next_int <= 24'hff_ffff; + end else begin + if (busy_m3 & ~busy_m2) begin + softspan_next_int <= softspan_next; + end else begin + softspan_next_int <= softspan_next_int; + end + end + end + + assign sdi = (sdi_index != 5'b11111)? softspan_next_int[sdi_index] : 1'b0; + +endmodule diff --git a/adi_library/axi_ltc235x/axi_ltc235x_hw.tcl b/adi_library/axi_ltc235x/axi_ltc235x_hw.tcl new file mode 100644 index 00000000..3a1cdc40 --- /dev/null +++ b/adi_library/axi_ltc235x/axi_ltc235x_hw.tcl @@ -0,0 +1,97 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### +# ip + +package require qsys 14.0 +package require quartus::device + +source ../../scripts/adi_env.tcl +source ../scripts/adi_ip_intel.tcl + +ad_ip_create axi_ltc235x {AXI LTC235x Interface} axi_ltc235x_elab +set_module_property AUTHOR {Geronimo, John Erasmus Mari F.} +set_module_property VALIDATION_CALLBACK info_param_validate +ad_ip_files axi_ltc235x [list \ + $ad_hdl_dir/library/common/up_axi.v \ + $ad_hdl_dir/library/common/up_adc_common.v \ + $ad_hdl_dir/library/common/ad_rst.v \ + $ad_hdl_dir/library/common/up_xfer_cntrl.v \ + $ad_hdl_dir/library/common/up_xfer_status.v \ + $ad_hdl_dir/library/common/up_clock_mon.v \ + $ad_hdl_dir/library/common/up_adc_channel.v \ + $ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_rst_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \ + axi_ltc235x_cmos.v \ + axi_ltc235x_lvds.v \ + axi_ltc235x.v] +add_documentation_link "AXI_LTC235x IP core" https://wiki.analog.com/resources/fpga/docs/axi_ltc235x + +ad_ip_parameter ID INTEGER 0 +ad_ip_parameter XILINX_INTEL_N INTEGER 0 +ad_ip_parameter LVDS_CMOS_N INTEGER 0 +ad_ip_parameter LANE_0_ENABLE INTEGER 1 +ad_ip_parameter LANE_1_ENABLE INTEGER 1 +ad_ip_parameter LANE_2_ENABLE INTEGER 1 +ad_ip_parameter LANE_3_ENABLE INTEGER 1 +ad_ip_parameter LANE_4_ENABLE INTEGER 1 +ad_ip_parameter LANE_5_ENABLE INTEGER 1 +ad_ip_parameter LANE_6_ENABLE INTEGER 1 +ad_ip_parameter LANE_7_ENABLE INTEGER 1 +ad_ip_parameter EXTERNAL_CLK INTEGER 0 +ad_ip_parameter LTC235X_FAMILY INTEGER 0 +ad_ip_parameter NUM_CHANNELS INTEGER 8 +ad_ip_parameter DATA_WIDTH INTEGER 18 + +adi_add_auto_fpga_spec_params + +proc axi_ltc235x_elab {} { + # interfaces + + # physical interface + add_interface device_if conduit end + # common + add_interface_port device_if busy busy Input 1 + add_interface_port device_if lvds_cmos_n lvds_cmos_n Output 1 + + set interface [get_parameter_value LVDS_CMOS_N] + switch $interface { + "0" { ;# cmos + add_interface_port device_if scki scki Output 1 + add_interface_port device_if scko scko Input 1 + add_interface_port device_if sdi sdi Output 1 + add_interface_port device_if sdo sdo Input 8} + "1" { ;# lvds + add_interface_port device_if scki_p scki_p Output 1 + add_interface_port device_if scki_n scki_n Output 1 + add_interface_port device_if scko_p scko_p Input 1 + add_interface_port device_if scko_n scko_n Input 1 + add_interface_port device_if sdi_p sdi_p Output 1 + add_interface_port device_if sdi_n sdi_n Output 1 + add_interface_port device_if sdo_p sdo_p Input 1 + add_interface_port device_if sdo_n sdo_n Input 1} + } + + # clock + ad_interface clock external_clk input 1 + + # axi + ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn + + # others + ad_interface signal adc_dovf Input 1 ovf + + set num_channels [get_parameter_value NUM_CHANNELS] + for {set i 0} {$i < $num_channels} {incr i} { + add_interface adc_ch_$i conduit end + add_interface_port adc_ch_$i adc_enable_$i enable Output 1 + add_interface_port adc_ch_$i adc_valid_$i valid Output 1 + add_interface_port adc_ch_$i adc_data_$i data Output 32 + + set_interface_property adc_ch_$i associatedClock if_external_clk + set_interface_property adc_ch_$i associatedReset "" + } +} diff --git a/adi_library/axi_ltc235x/axi_ltc235x_lvds.v b/adi_library/axi_ltc235x/axi_ltc235x_lvds.v new file mode 100644 index 00000000..ba5adb3a --- /dev/null +++ b/adi_library/axi_ltc235x/axi_ltc235x_lvds.v @@ -0,0 +1,407 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ltc235x_lvds #( + parameter XILINX_INTEL_N = 0, + parameter LTC235X_FAMILY = 0, + parameter NUM_CHANNELS = 8, // 8 for 2358, 4 for 2357, 2 for 2353 + parameter DATA_WIDTH = 18 // 18 or 16 based on -18/-16 +) ( + + input rst, + input clk, + input [ 7:0] adc_enable, + input [23:0] softspan_next, + + // physical interface + + output scki_p, + output scki_n, + output sdi_p, + output sdi_n, + input scko_p, + input scko_n, + input sdo_p, + input sdo_n, + input busy, + + // FIFO interface + + output [ 2:0] adc_ch0_id, + output [ 2:0] adc_ch1_id, + output [ 2:0] adc_ch2_id, + output [ 2:0] adc_ch3_id, + output [ 2:0] adc_ch4_id, + output [ 2:0] adc_ch5_id, + output [ 2:0] adc_ch6_id, + output [ 2:0] adc_ch7_id, + + output [31:0] adc_data_0, + output [31:0] adc_data_1, + output [31:0] adc_data_2, + output [31:0] adc_data_3, + output [31:0] adc_data_4, + output [31:0] adc_data_5, + output [31:0] adc_data_6, + output [31:0] adc_data_7, + + output [ 2:0] adc_softspan_0, + output [ 2:0] adc_softspan_1, + output [ 2:0] adc_softspan_2, + output [ 2:0] adc_softspan_3, + output [ 2:0] adc_softspan_4, + output [ 2:0] adc_softspan_5, + output [ 2:0] adc_softspan_6, + output [ 2:0] adc_softspan_7, + + output reg adc_valid +); + + // local parameters + + localparam DW = 24; // packet size per channel + localparam DW_8 = 24 * 8; // packet size for all 8 channels + localparam BW = DW - 1; + localparam BW_8 = DW_8 - 1; + + // internal registers + + reg busy_m1; + reg busy_m2; + reg busy_m3; + + reg [ 8:0] scki_counter = 9'h0; + reg [ 8:0] data_counter = 9'h0; + + reg scki_i; + reg scki_d; + + reg [BW_8:0] adc_lane; + reg [BW_8:0] adc_data_init; + reg [ BW:0] adc_data_store[7:0]; + + reg adc_valid_init; + reg adc_valid_init_d; + + reg ch_data_lock = 1; + reg ch_capture; + reg ch_captured; + + reg scko_d; + reg sdo_d; + + reg [ 4:0] sdi_index = 5'd23; + + reg [23:0] softspan_next_int; + + // internal wires + + wire start_transfer_s; + + wire scki_cnt_rst; + + wire acquire_data; + + wire [DATA_WIDTH-1:0] adc_data_raw_s [7:0]; + wire [31:0] adc_data_sign_s [7:0]; + wire [31:0] adc_data_zero_s [7:0]; + wire [31:0] adc_data_s [7:0]; + wire [ 2:0] adc_ch_id_s [7:0]; + wire [ 2:0] adc_softspan_s [7:0]; + + wire scki_s; + wire sdi_s; + wire scko_s; + wire sdo_s; + + generate + if (XILINX_INTEL_N == 0) begin + assign scki_p = scki_s; + assign scki_n = 1'b0; + assign sdi_p = sdi_s; + assign sdi_n = 1'b0; + assign scko_s = scko_p; + assign sdo_s = sdo_p; + end else begin + OBUFDS obufds_scki ( + .O(scki_n), + .OB(scki_p), + .I(scki_s)); + + OBUFDS obufds_sdi ( + .O(sdi_n), + .OB(sdi_p), + .I(sdi_s)); + + IBUFDS #( + .CCIO_EN_M("TRUE"), + .CCIO_EN_S("TRUE") + ) ibufds_scko ( + .O(scko_s), + .I(scko_p), + .IB(scko_n)); + + IBUFDS #( + .CCIO_EN_M("TRUE"), + .CCIO_EN_S("TRUE") + ) ibufds_sdo ( + .O(sdo_s), + .I(sdo_p), + .IB(sdo_n)); + end + endgenerate + + always @(posedge clk) begin + if (rst == 1'b1) begin + busy_m1 <= 1'b0; + busy_m2 <= 1'b0; + end else begin + busy_m1 <= busy; + busy_m2 <= busy_m1; + busy_m3 <= busy_m2; + end + end + + assign start_transfer_s = busy_m3 & ~busy_m2; + + // reading clock logic + always @(posedge clk) begin + if (rst) begin + scki_counter <= 9'h0; + scki_i <= 1'b0; + scki_d <= 1'b0; + end else begin + scki_d <= scki_i; + if (acquire_data == 1'b0) begin + scki_counter <= 9'h0; + scki_i <= 1'b0; + end else if (scki_cnt_rst & (scki_d != scki_i)) begin // end of a capture + scki_counter <= 9'h1; + scki_i <= 1'b0; + end else begin + scki_counter <= scki_counter + 9'd1; + scki_i <= ~scki_i; + end + end + end + + assign scki_cnt_rst = (scki_counter == DW_8); + assign scki_s = scki_i & acquire_data; + + // capture data per lane in rx buffer on every edge of scko_s + // ignore when busy forced scko_s to 0 + always @(posedge clk) begin + scko_d <= scko_s; + sdo_d <= sdo_s; + if (scko_s != scko_d && scki_s != scki_d) begin + adc_lane <= {adc_lane[BW_8-1:0], sdo_d}; + end + end + + // store the data from the rx buffers when all bits are received + // when data transaction window is done + always @(posedge clk) begin + if (rst == 1'b1) begin + adc_data_init <= 'h0; + data_counter <= 9'h0; + end else begin + data_counter <= scki_counter; + if (data_counter == DW_8) begin + adc_data_init <= adc_lane; + end + end + end + + // ch_data_lock - locks all the channel, means dont acquire data if all ch's are lock while acquire_data = 0 + always @(posedge clk) begin + if (start_transfer_s) begin + ch_data_lock <= 1'd0; + end else if (acquire_data == 1'b1 && (scki_cnt_rst & (scki_d != scki_i))) begin + ch_data_lock <= 1'd1; + end + end + + assign acquire_data = ~((ch_data_lock | ~adc_enable[0]) & + (ch_data_lock | ~adc_enable[1]) & + (ch_data_lock | ~adc_enable[2]) & + (ch_data_lock | ~adc_enable[3]) & + (ch_data_lock | ~adc_enable[4]) & + (ch_data_lock | ~adc_enable[5]) & + (ch_data_lock | ~adc_enable[6]) & + (ch_data_lock | ~adc_enable[7])); + + // stores the data from the rx buffer, but now based on ch + // from the whole buffer into the per channel buffer + always @(posedge clk) begin + if (rst == 1'b1) begin + adc_data_store[0] <= 'd0; + adc_data_store[1] <= 'd0; + adc_data_store[2] <= 'd0; + adc_data_store[3] <= 'd0; + adc_data_store[4] <= 'd0; + adc_data_store[5] <= 'd0; + adc_data_store[6] <= 'd0; + adc_data_store[7] <= 'd0; + end else begin + if (!adc_valid_init_d & adc_valid_init) begin + adc_data_store[0] <= adc_data_init[BW + DW * 7: DW * 7]; + adc_data_store[1] <= adc_data_init[BW + DW * 6: DW * 6]; + adc_data_store[2] <= adc_data_init[BW + DW * 5: DW * 5]; + adc_data_store[3] <= adc_data_init[BW + DW * 4: DW * 4]; + adc_data_store[4] <= adc_data_init[BW + DW * 3: DW * 3]; + adc_data_store[5] <= adc_data_init[BW + DW * 2: DW * 2]; + adc_data_store[6] <= adc_data_init[BW + DW * 1: DW * 1]; + adc_data_store[7] <= adc_data_init[BW + DW * 0: DW * 0]; + end + end + end + + // extract info from the data bits + genvar i; + generate + for (i=0; i < 8; i=i+1) begin: format + assign adc_data_raw_s[i] = adc_data_store[i][BW:DW-DATA_WIDTH]; + assign adc_data_sign_s[i] = {{(32-DATA_WIDTH){adc_data_raw_s[i][DATA_WIDTH-1]}}, adc_data_raw_s[i]}; + assign adc_data_zero_s[i] = {{(32-DATA_WIDTH){1'b0}}, adc_data_raw_s[i]}; + assign adc_data_s[i] = (adc_softspan_s[i] == 3'b0)? 32'h0 : + (adc_softspan_s[i][1])? adc_data_sign_s[i] : + adc_data_zero_s[i] ; + if (NUM_CHANNELS == 8) begin + assign adc_ch_id_s[i] = adc_data_store[i][5:3]; + end else if (NUM_CHANNELS == 4) begin + assign adc_ch_id_s[i] = {1'b0, adc_data_store[i][4:3]}; + end else begin + assign adc_ch_id_s[i] = {2'b0, adc_data_store[i][3]}; + end + assign adc_softspan_s[i] = adc_data_store[i][2:0]; + end + endgenerate + + // assign extracted adc data to corresponding outputs + assign adc_data_0 = adc_data_s[0]; + assign adc_data_1 = adc_data_s[1]; + assign adc_data_2 = adc_data_s[2]; + assign adc_data_3 = adc_data_s[3]; + assign adc_data_4 = adc_data_s[4]; + assign adc_data_5 = adc_data_s[5]; + assign adc_data_6 = adc_data_s[6]; + assign adc_data_7 = adc_data_s[7]; + + // assign extracted adc channel id to corresponding outputs + assign adc_ch0_id = adc_ch_id_s[0]; + assign adc_ch1_id = adc_ch_id_s[1]; + assign adc_ch2_id = adc_ch_id_s[2]; + assign adc_ch3_id = adc_ch_id_s[3]; + assign adc_ch4_id = adc_ch_id_s[4]; + assign adc_ch5_id = adc_ch_id_s[5]; + assign adc_ch6_id = adc_ch_id_s[6]; + assign adc_ch7_id = adc_ch_id_s[7]; + + // assign extracted adc channel id to corresponding outputs + assign adc_softspan_0 = adc_softspan_s[0]; + assign adc_softspan_1 = adc_softspan_s[1]; + assign adc_softspan_2 = adc_softspan_s[2]; + assign adc_softspan_3 = adc_softspan_s[3]; + assign adc_softspan_4 = adc_softspan_s[4]; + assign adc_softspan_5 = adc_softspan_s[5]; + assign adc_softspan_6 = adc_softspan_s[6]; + assign adc_softspan_7 = adc_softspan_s[7]; + + // initial valid signal + always @(posedge clk) begin + if (rst == 1'b1) begin + adc_valid_init <= 1'b0; + end else begin + if (data_counter == DW_8 && adc_valid_init == 1'b0) begin + adc_valid_init <= 1'b1; + end else begin + adc_valid_init <= 1'b0; + end + end + end + + // delayed both valid signal and data_lock signal + // for datasyncing with valid signal + always @(posedge clk) begin + if (rst == 1'b1 || adc_valid == 1'b1) begin + adc_valid <= 1'b0; + adc_valid_init_d <= 1'b0; + ch_capture <= 1'd0; + ch_captured <= 1'd0; + end else begin + ch_capture <= ch_data_lock; + ch_captured <= ch_capture; + adc_valid_init_d <= adc_valid_init; + adc_valid <= adc_valid_init_d & + (ch_captured | ~adc_enable[0]) & + (ch_captured | ~adc_enable[1]) & + (ch_captured | ~adc_enable[2]) & + (ch_captured | ~adc_enable[3]) & + (ch_captured | ~adc_enable[4]) & + (ch_captured | ~adc_enable[5]) & + (ch_captured | ~adc_enable[6]) & + (ch_captured | ~adc_enable[7]); + end + end + + // every negedge of clk, update index of sdi_s + always @(negedge clk) begin + if (start_transfer_s || rst) begin + sdi_index <= 5'd23; + end else begin + if (scki_s != scki_d && sdi_index != 5'b11111) begin + sdi_index <= sdi_index - 5'b1; + end + end + end + + // update next softspan configuration every after busy + always @(posedge clk) begin + if (rst == 1'b1) begin + softspan_next_int <= 24'hff_ffff; + end else begin + if (busy_m3 & ~busy_m2) begin + softspan_next_int <= softspan_next; + end else begin + softspan_next_int <= softspan_next_int; + end + end + end + + assign sdi_s = (sdi_index != 5'b11111)? softspan_next_int[sdi_index] : 1'b0; + +endmodule diff --git a/adi_library/axi_ltc2387/Makefile b/adi_library/axi_ltc2387/Makefile new file mode 100644 index 00000000..c4518f00 --- /dev/null +++ b/adi_library/axi_ltc2387/Makefile @@ -0,0 +1,30 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_ltc2387 + +GENERIC_DEPS += ../common/ad_datafmt.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_adc_channel.v +GENERIC_DEPS += ../common/up_adc_common.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/up_clock_mon.v +GENERIC_DEPS += ../common/up_delay_cntrl.v +GENERIC_DEPS += ../common/up_xfer_cntrl.v +GENERIC_DEPS += ../common/up_xfer_status.v +GENERIC_DEPS += axi_ltc2387.v +GENERIC_DEPS += axi_ltc2387_channel.v +GENERIC_DEPS += axi_ltc2387_if.v + +XILINX_DEPS += ../xilinx/common/ad_data_clk.v +XILINX_DEPS += ../xilinx/common/ad_data_in.v +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += axi_ltc2387_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_ltc2387/axi_ltc2387.v b/adi_library/axi_ltc2387/axi_ltc2387.v new file mode 100644 index 00000000..11aec198 --- /dev/null +++ b/adi_library/axi_ltc2387/axi_ltc2387.v @@ -0,0 +1,340 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ltc2387 #( + + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 1, + parameter FPGA_FAMILY = 1, + parameter SPEED_GRADE = 1, + parameter DEV_PACKAGE = 1, + parameter IO_DELAY_GROUP = "adc_if_delay_group", + parameter IODELAY_CTRL = 1, + parameter DELAY_REFCLK_FREQUENCY = 200, + parameter USERPORTS_DISABLE = 0, + parameter DATAFORMAT_DISABLE = 0, + parameter ADC_INIT_DELAY = 22, + parameter ADC_RES = 16, + parameter OUT_RES = 16, + parameter TWOLANES = 1 +) ( + input delay_clk, + + // adc interface + + input ref_clk, + input clk_gate, + input dco_p, + input dco_n, + input da_p, + input da_n, + input db_p, + input db_n, + + // dma interface + + output adc_valid, + output [OUT_RES-1:0] adc_data, + input adc_dovf, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + input [ 2:0] s_axi_awprot, + input [ 2:0] s_axi_arprot +); + + // internal signals + + wire [15:0] adc_data_s; + wire adc_or_s; + wire [ 1:0] up_dld_s; + wire [ 9:0] up_dwdata_s; + wire [ 9:0] up_drdata_s; + wire delay_locked_s; + wire up_status_pn_err_s; + wire up_status_pn_oos_s; + wire up_status_or_s; + wire up_rreq_s; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_s[0:2]; + wire up_rack_s[0:2]; + wire up_wack_s[0:2]; + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + + // internal registers + + reg up_wack = 'd0; + reg [31:0] up_rdata = 'd0; + reg up_rack = 'd0; + + // internal signals + + wire adc_rst; + wire adc_clk; + wire adc_enable; + wire up_clk; + wire up_rstn; + wire delay_rst; + wire adc_valid_ch_s; + wire [ADC_RES-1:0] adc_data_ch_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + assign adc_clk = ref_clk; + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rdata <= 32'd0; + up_rack <= 1'd0; + up_wack <= 1'd0; + end else begin + up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2]; + up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2]; + up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2]; + end + end + + // main (device interface) + + axi_ltc2387_if #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IO_DELAY_GROUP (IO_DELAY_GROUP), + .DELAY_REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY), + .RESOLUTION (ADC_RES), + .IODELAY_CTRL (IODELAY_CTRL), + .TWOLANES (TWOLANES) + ) i_if ( + .clk (ref_clk), + .clk_gate (clk_gate), + .da_p (da_p), + .da_n (da_n), + .db_p (db_p), + .db_n (db_n), + .dco_p (dco_p), + .dco_n (dco_n), + .adc_valid (adc_valid_ch_s), + .adc_data (adc_data_ch_s), + .up_clk (up_clk), + .up_dld (up_dld_s), + .up_dwdata (up_dwdata_s), + .up_drdata (up_drdata_s), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s)); + + // channel + + axi_ltc2387_channel #( + .ADC_RES (ADC_RES), + .OUT_RES (OUT_RES), + .TWOLANES (TWOLANES), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE) + ) i_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_data_in (adc_data_ch_s), + .adc_valid_in (adc_valid_ch_s), + .adc_enable (adc_enable), + .adc_valid (adc_valid), + .adc_data (adc_data), + .up_adc_pn_err (up_status_pn_err_s), + .up_adc_pn_oos (up_status_pn_oos_s), + .up_adc_or (up_status_or_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + // adc delay control + + up_delay_cntrl #( + .INIT_DELAY (ADC_INIT_DELAY), + .DATA_WIDTH (2), + .BASE_ADDRESS (6'h02) + ) i_delay_cntrl ( + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked_s), + .up_dld (up_dld_s), + .up_dwdata (up_dwdata_s), + .up_drdata (up_drdata_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[2]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[2]), + .up_rack (up_rack_s[2])); + + // common processor control + + up_adc_common #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .CONFIG (0), + .COMMON_ID (6'h00), + .DRP_DISABLE (6'h00), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .GPIO_DISABLE (0), + .START_CODE_DISABLE (0) + ) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (delay_locked_s), + .adc_sync_status (1'd0), + .adc_status_ovf (adc_dovf), + .adc_clk_ratio (32'b1), + .adc_start_code (), + .adc_sref_sync (), + .adc_sync (), + .adc_ext_sync_arm(), + .adc_ext_sync_disarm(), + .adc_ext_sync_manual_req(), + .adc_num_lanes (), + .adc_custom_control(), + .adc_crc_enable (), + .adc_sdr_ddr_n (), + .adc_symb_op (), + .adc_symb_8_16b (), + .up_pps_rcounter (32'd0), + .up_pps_status (1'd0), + .up_pps_irq_mask (), + .up_adc_r1_mode (), + .up_adc_ce (), + .up_status_pn_err (up_status_pn_err_s), + .up_status_pn_oos (up_status_pn_oos_s), + .up_status_or (up_status_or_s), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'b0), + .up_drp_ready (1'b0), + .up_drp_locked (1'b1), + .adc_config_wr (), + .adc_config_ctrl (), + .adc_config_rd ('d0), + .adc_ctrl_status ('d0), + .up_usr_chanmax_out (), + .up_usr_chanmax_in (8'd1), + .up_adc_gpio_in (32'd0), + .up_adc_gpio_out (), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[1]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[1]), + .up_rack (up_rack_s[1])); + + // up bus interface + + up_axi i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ltc2387/axi_ltc2387.xpr b/adi_library/axi_ltc2387/axi_ltc2387.xpr new file mode 100644 index 00000000..ad9ed70e --- /dev/null +++ b/adi_library/axi_ltc2387/axi_ltc2387.xpr @@ -0,0 +1,515 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_ltc2387/axi_ltc2387_channel.v b/adi_library/axi_ltc2387/axi_ltc2387_channel.v new file mode 100644 index 00000000..8bad30f6 --- /dev/null +++ b/adi_library/axi_ltc2387/axi_ltc2387_channel.v @@ -0,0 +1,210 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_ltc2387_channel #( + + parameter ADC_RES = 16, + parameter OUT_RES = 16, + parameter TWOLANES = 1, + parameter USERPORTS_DISABLE = 0, + parameter DATAFORMAT_DISABLE = 0 +) ( + + // adc interface + + input adc_clk, + input adc_rst, + input adc_valid_in, + input [ADC_RES-1:0] adc_data_in, + + // dma interface + + output adc_enable, + output adc_valid, + output [OUT_RES-1:0] adc_data, + + // error monitoring + + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // internal signals + + wire adc_dfmt_valid_s; + wire [15:0] adc_dfmt_data_s; + wire adc_dcfilter_valid_s; + wire adc_iqcor_enb_s; + wire adc_dcfilt_enb_s; + wire adc_dfmt_se_s; + wire adc_dfmt_type_s; + wire adc_dfmt_enable_s; + wire [15:0] adc_dcfilt_offset_s; + wire [15:0] adc_dcfilt_coeff_s; + wire [15:0] adc_iqcor_coeff_1_s; + wire [15:0] adc_iqcor_coeff_2_s; + wire [ 3:0] adc_pnseq_sel_s; + wire [ 3:0] adc_data_sel_s; + reg adc_pn_err; + wire adc_pn_err_s; + + wire [ADC_RES-1:0] test_pattern; + wire [15:0] expected_pattern; + + assign adc_pn_err_s = adc_pn_err; + + // expected pattern + + generate + if (TWOLANES == 1) begin + assign expected_pattern = 16'b1100110000111111; + end else begin + assign expected_pattern = 16'b1010000001111111; + end + if (ADC_RES == 16) begin + assign test_pattern = expected_pattern; + end else if (ADC_RES == 18) begin + assign test_pattern = expected_pattern << 2; + end + endgenerate + + always @(posedge adc_clk) begin + if (test_pattern == adc_data) begin + adc_pn_err <= 1'b0; + end else begin + adc_pn_err <= 1'b1; + end + end + + // min DMA bus width according to ADC_RES + + generate + if (ADC_RES == 18) begin + ad_datafmt #( + .DATA_WIDTH (18), + .BITS_PER_SAMPLE (32), + .DISABLE (DATAFORMAT_DISABLE) + ) i_ad_datafmt ( + .clk (adc_clk), + .valid (adc_valid_in), + .data (adc_data_in), + .valid_out (adc_valid), + .data_out (adc_data), + .dfmt_enable (adc_dfmt_enable_s), + .dfmt_type (adc_dfmt_type_s), + .dfmt_se (adc_dfmt_se_s)); + end else if (ADC_RES == 16) begin + assign adc_data = adc_data_in; + assign adc_valid = adc_valid_in; + end else begin + assign adc_data = 'd0; + assign adc_valid = 1'd0; + end + endgenerate + + // adc channel regmap + + up_adc_channel #( + .CHANNEL_ID (0), + .USERPORTS_DISABLE (USERPORTS_DISABLE), + .DATAFORMAT_DISABLE (DATAFORMAT_DISABLE), + .DCFILTER_DISABLE (1'b1), + .IQCORRECTION_DISABLE (1'b1) + ) i_up_adc_channel ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), + .adc_enable (adc_enable), + .adc_iqcor_enb (adc_iqcor_enb_s), + .adc_dcfilt_enb (adc_dcfilt_enb_s), + .adc_dfmt_se (adc_dfmt_se_s), + .adc_dfmt_type (adc_dfmt_type_s), + .adc_dfmt_enable (adc_dfmt_enable_s), + .adc_dcfilt_offset (adc_dcfilt_offset_s), + .adc_dcfilt_coeff (adc_dcfilt_coeff_s), + .adc_iqcor_coeff_1 (adc_iqcor_coeff_1_s), + .adc_iqcor_coeff_2 (adc_iqcor_coeff_2_s), + .adc_pnseq_sel (adc_pnseq_sel_s), + .adc_data_sel (), + .adc_pn_err (adc_pn_err_s), + .adc_pn_oos (1'b0), + .adc_or (1'b0), + .adc_read_data ('d0), + .adc_status_header ('d0), + .adc_crc_err ('d0), + .up_adc_pn_err (up_adc_pn_err), + .up_adc_pn_oos (up_adc_pn_oos), + .up_adc_or (up_adc_or), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/axi_ltc2387/axi_ltc2387_if.v b/adi_library/axi_ltc2387/axi_ltc2387_if.v new file mode 100644 index 00000000..0efd5e1f --- /dev/null +++ b/adi_library/axi_ltc2387/axi_ltc2387_if.v @@ -0,0 +1,236 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// This is the LVDS/DDR interface, note that overrange is independent of data path, +// software will not be able to relate overrange to a specific sample! + +`timescale 1ns/100ps + +module axi_ltc2387_if #( + + parameter FPGA_TECHNOLOGY = 1, + parameter IO_DELAY_GROUP = "adc_if_delay_group", + parameter IODELAY_CTRL = 1, + parameter DELAY_REFCLK_FREQUENCY = 200, + parameter [0:0] TWOLANES = 1, // 0 for Single Lane, 1 for Two Lanes + parameter RESOLUTION = 16 // 16 or 18 bits +) ( + + // delay interface + + input up_clk, + input [ 1:0] up_dld, + input [ 9:0] up_dwdata, + output [ 9:0] up_drdata, + input delay_clk, + input delay_rst, + output delay_locked, + + // adc interface + + input clk, + input clk_gate, + input dco_p, + input dco_n, + input da_p, + input da_n, + input db_p, + input db_n, + + output adc_valid, + output reg [RESOLUTION-1:0] adc_data +); + + localparam ONE_L_WIDTH = (RESOLUTION == 18) ? 9 : 8; + localparam TWO_L_WIDTH = (RESOLUTION == 18) ? 5 : 4; + localparam WIDTH = (TWOLANES == 0) ? ONE_L_WIDTH : TWO_L_WIDTH; + + // internal wires + + wire da_p_int_s; + wire da_n_int_s; + wire db_p_int_s; + wire db_n_int_s; + wire dco; + wire dco_s; + wire [17:0] adc_data_int; + + // internal registers + + reg [WIDTH:0] adc_data_da_p = 'b0; + reg [WIDTH:0] adc_data_da_n = 'b0; + reg [WIDTH:0] adc_data_db_p = 'b0; + reg [WIDTH:0] adc_data_db_n = 'b0; + reg [2:0] clk_gate_d = 'b0; + + // assignments + + // adc_valid is 1 for the current sample that is sent + assign adc_valid = clk_gate_d[1] & ~clk_gate_d[0]; + + always @(posedge clk) begin + clk_gate_d <= {clk_gate_d[1:0], clk_gate}; + if (clk_gate_d[1] == 1'b1 && clk_gate_d[0] == 1'b0) begin + if (RESOLUTION == 18) begin + adc_data <= adc_data_int; + end else begin + adc_data <= adc_data_int[15:0]; + end + end + end + + always @(posedge dco) begin + adc_data_da_p <= {adc_data_da_p[WIDTH-1:0], da_p_int_s}; + adc_data_da_n <= {adc_data_da_n[WIDTH-1:0], da_n_int_s}; + adc_data_db_p <= {adc_data_db_p[WIDTH-1:0], db_p_int_s}; + adc_data_db_n <= {adc_data_db_n[WIDTH-1:0], db_n_int_s}; + end + + // bits rearrangement + + if (!TWOLANES) begin + assign adc_data_int[17] = adc_data_da_p[7]; + assign adc_data_int[16] = adc_data_da_n[7]; + assign adc_data_int[15] = adc_data_da_p[6]; + assign adc_data_int[14] = adc_data_da_n[6]; + assign adc_data_int[13] = adc_data_da_p[5]; + assign adc_data_int[12] = adc_data_da_n[5]; + assign adc_data_int[11] = adc_data_da_p[4]; + assign adc_data_int[10] = adc_data_da_n[4]; + assign adc_data_int[9] = adc_data_da_p[3]; + assign adc_data_int[8] = adc_data_da_n[3]; + assign adc_data_int[7] = adc_data_da_p[2]; + assign adc_data_int[6] = adc_data_da_n[2]; + assign adc_data_int[5] = adc_data_da_p[1]; + assign adc_data_int[4] = adc_data_da_n[1]; + assign adc_data_int[3] = adc_data_da_p[0]; + assign adc_data_int[2] = adc_data_da_n[0]; + assign adc_data_int[1] = da_p_int_s; + assign adc_data_int[0] = da_n_int_s; + end else begin + if (RESOLUTION == 18) begin + assign adc_data_int[17] = adc_data_da_p[3]; + assign adc_data_int[16] = adc_data_db_p[3]; + assign adc_data_int[15] = adc_data_da_n[3]; + assign adc_data_int[14] = adc_data_db_n[3]; + assign adc_data_int[13] = adc_data_da_p[2]; + assign adc_data_int[12] = adc_data_db_p[2]; + assign adc_data_int[11] = adc_data_da_n[2]; + assign adc_data_int[10] = adc_data_db_n[2]; + assign adc_data_int[9] = adc_data_da_p[1]; + assign adc_data_int[8] = adc_data_db_p[1]; + assign adc_data_int[7] = adc_data_da_n[1]; + assign adc_data_int[6] = adc_data_db_n[1]; + assign adc_data_int[5] = adc_data_da_p[0]; + assign adc_data_int[4] = adc_data_db_p[0]; + assign adc_data_int[3] = adc_data_da_n[0]; + assign adc_data_int[2] = adc_data_db_n[0]; + assign adc_data_int[1] = da_p_int_s; + assign adc_data_int[0] = db_p_int_s; + end else begin + assign adc_data_int[15] = adc_data_da_p[2]; + assign adc_data_int[14] = adc_data_db_p[2]; + assign adc_data_int[13] = adc_data_da_n[2]; + assign adc_data_int[12] = adc_data_db_n[2]; + assign adc_data_int[11] = adc_data_da_p[1]; + assign adc_data_int[10] = adc_data_db_p[1]; + assign adc_data_int[9] = adc_data_da_n[1]; + assign adc_data_int[8] = adc_data_db_n[1]; + assign adc_data_int[7] = adc_data_da_p[0]; + assign adc_data_int[6] = adc_data_db_p[0]; + assign adc_data_int[5] = adc_data_da_n[0]; + assign adc_data_int[4] = adc_data_db_n[0]; + assign adc_data_int[3] = da_p_int_s; + assign adc_data_int[2] = db_p_int_s; + assign adc_data_int[1] = da_n_int_s; + assign adc_data_int[0] = db_n_int_s; + end + end + + // data interface - differential to single ended + + ad_data_in #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IDDR_CLK_EDGE ("OPPOSITE_EDGE"), + .IODELAY_CTRL (IODELAY_CTRL), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_rx_da ( + .rx_clk (dco), + .rx_data_in_p (da_p), + .rx_data_in_n (da_n), + .rx_data_p (da_p_int_s), + .rx_data_n (da_n_int_s), + .up_clk (up_clk), + .up_dld (up_dld[0]), + .up_dwdata (up_dwdata[4:0]), + .up_drdata (up_drdata[4:0]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked (delay_locked)); + + ad_data_in #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .IDDR_CLK_EDGE ("OPPOSITE_EDGE"), + .IODELAY_CTRL (0), + .IODELAY_GROUP (IO_DELAY_GROUP), + .REFCLK_FREQUENCY (DELAY_REFCLK_FREQUENCY) + ) i_rx_db ( + .rx_clk (dco), + .rx_data_in_p (db_p), + .rx_data_in_n (db_n), + .rx_data_p (db_p_int_s), + .rx_data_n (db_n_int_s), + .up_clk (up_clk), + .up_dld (up_dld[1]), + .up_dwdata (up_dwdata[9:5]), + .up_drdata (up_drdata[9:5]), + .delay_clk (delay_clk), + .delay_rst (delay_rst), + .delay_locked ()); + + // clock + + IBUFGDS i_rx_clk_ibuf ( + .I (dco_p), + .IB (dco_n), + .O (dco_s)); + + BUFR i_clk_gbuf ( + .CLR (1'b0), + .CE (1'b1), + .I (dco_s), + .O (dco)); + +endmodule diff --git a/adi_library/axi_ltc2387/axi_ltc2387_ip.tcl b/adi_library/axi_ltc2387/axi_ltc2387_ip.tcl new file mode 100644 index 00000000..8a488e46 --- /dev/null +++ b/adi_library/axi_ltc2387/axi_ltc2387_ip.tcl @@ -0,0 +1,66 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_ltc2387 + +adi_ip_files axi_ltc2387 [list \ + "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_in.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_delay_cntrl.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "axi_ltc2387_if.v" \ + "axi_ltc2387_channel.v" \ + "axi_ltc2387.v" ] + +adi_ip_properties axi_ltc2387 + +ipx::infer_bus_interface ref_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface dco_p xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface dco_n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + +set cc [ipx::current_core] + +set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] + +ipgui::add_param -name "ADC_RES" -component $cc -parent $page0 +set_property -dict [list \ + "display_name" "ADC resolution" \ + "tooltip" "ADC resolution" \ +] [ipgui::get_guiparamspec -name "ADC_RES" -component $cc] + +set_property -dict [list \ + "value_validation_type" "list" \ + "value_validation_list" "16 18" \ + ] \ +[ipx::get_user_parameters ADC_RES -of_objects $cc] + +ipgui::add_param -name "OUT_RES" -component $cc -parent $page0 +set_property -dict [list \ + "display_name" "Output data width" \ + "tooltip" "Memory interface" \ +] [ipgui::get_guiparamspec -name "OUT_RES" -component $cc] + +set_property -dict [list \ + "value_validation_type" "list" \ + "value_validation_list" "16 32" \ + ] \ +[ipx::get_user_parameters OUT_RES -of_objects $cc] + +ipx::save_core [ipx::current_core] diff --git a/adi_library/axi_ltc2387/component.xml b/adi_library/axi_ltc2387/component.xml new file mode 100644 index 00000000..1dc87934 --- /dev/null +++ b/adi_library/axi_ltc2387/component.xml @@ -0,0 +1,1184 @@ + + + analog.com + user + axi_ltc2387 + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + ref_clk + + + + + + + CLK + + + ref_clk + + + + + + dco_p + + + + + + + CLK + + + dco_p + + + + + + dco_n + + + + + + + CLK + + + dco_n + + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_ltc2387 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + d5c839f9 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_ltc2387 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + cd03700f + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 08121607 + + + + + + + delay_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ref_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + clk_gate + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dco_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dco_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + da_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + da_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + db_p + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + db_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_dovf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 1 + + + FPGA_FAMILY + Fpga Family + 1 + + + SPEED_GRADE + Speed Grade + 1 + + + DEV_PACKAGE + Dev Package + 1 + + + IO_DELAY_GROUP + Io Delay Group + adc_if_delay_group + + + IODELAY_CTRL + Iodelay Ctrl + 1 + + + DELAY_REFCLK_FREQUENCY + Delay Refclk Frequency + 200 + + + USERPORTS_DISABLE + Userports Disable + 0 + + + DATAFORMAT_DISABLE + Dataformat Disable + 0 + + + ADC_INIT_DELAY + Adc Init Delay + 22 + + + ADC_RES + Adc Res + 16 + + + OUT_RES + Out Res + 16 + + + TWOLANES + Twolanes + 1 + + + + + + choice_list_5d7f73a0 + 16 + 18 + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_list_8f9cf83c + 16 + 32 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../xilinx/common/up_clock_mon_constr.xdc + xdc + + + ../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../xilinx/common/ad_data_in.v + verilogSource + + + ../common/ad_datafmt.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + axi_ltc2387_channel.v + verilogSource + + + axi_ltc2387_if.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_delay_cntrl.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ltc2387.v + verilogSource + CHECKSUM_e2e76c94 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../xilinx/common/ad_data_in.v + verilogSource + + + ../common/ad_datafmt.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + axi_ltc2387_channel.v + verilogSource + + + axi_ltc2387_if.v + verilogSource + + + ../common/up_adc_channel.v + verilogSource + + + ../common/up_adc_common.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/up_clock_mon.v + verilogSource + + + ../common/up_delay_cntrl.v + verilogSource + + + ../common/up_xfer_cntrl.v + verilogSource + + + ../common/up_xfer_status.v + verilogSource + + + axi_ltc2387.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_ltc2387_v1_0.tcl + tclSource + CHECKSUM_08121607 + XGUI_VERSION_2 + + + + axi_ltc2387_v1_0 + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 1 + + + FPGA_FAMILY + Fpga Family + 1 + + + SPEED_GRADE + Speed Grade + 1 + + + DEV_PACKAGE + Dev Package + 1 + + + IO_DELAY_GROUP + Io Delay Group + adc_if_delay_group + + + IODELAY_CTRL + Iodelay Ctrl + 1 + + + DELAY_REFCLK_FREQUENCY + Delay Refclk Frequency + 200 + + + USERPORTS_DISABLE + Userports Disable + 0 + + + DATAFORMAT_DISABLE + Dataformat Disable + 0 + + + ADC_INIT_DELAY + Adc Init Delay + 22 + + + ADC_RES + ADC resolution + 16 + + + OUT_RES + Output data width + 16 + + + TWOLANES + Twolanes + 1 + + + Component_Name + axi_ltc2387_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_ltc2387_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:48:30Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_ltc2387/xgui/axi_ltc2387_v1_0.tcl b/adi_library/axi_ltc2387/xgui/axi_ltc2387_v1_0.tcl new file mode 100644 index 00000000..0948f741 --- /dev/null +++ b/adi_library/axi_ltc2387/xgui/axi_ltc2387_v1_0.tcl @@ -0,0 +1,220 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ADC_INIT_DELAY" -parent ${Page_0} + ipgui::add_param $IPINST -name "ADC_RES" -parent ${Page_0} + ipgui::add_param $IPINST -name "DATAFORMAT_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "DELAY_REFCLK_FREQUENCY" -parent ${Page_0} + ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${Page_0} + ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${Page_0} + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${Page_0} + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "IODELAY_CTRL" -parent ${Page_0} + ipgui::add_param $IPINST -name "IO_DELAY_GROUP" -parent ${Page_0} + ipgui::add_param $IPINST -name "OUT_RES" -parent ${Page_0} + ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${Page_0} + ipgui::add_param $IPINST -name "TWOLANES" -parent ${Page_0} + ipgui::add_param $IPINST -name "USERPORTS_DISABLE" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.ADC_INIT_DELAY { PARAM_VALUE.ADC_INIT_DELAY } { + # Procedure called to update ADC_INIT_DELAY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADC_INIT_DELAY { PARAM_VALUE.ADC_INIT_DELAY } { + # Procedure called to validate ADC_INIT_DELAY + return true +} + +proc update_PARAM_VALUE.ADC_RES { PARAM_VALUE.ADC_RES } { + # Procedure called to update ADC_RES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADC_RES { PARAM_VALUE.ADC_RES } { + # Procedure called to validate ADC_RES + return true +} + +proc update_PARAM_VALUE.DATAFORMAT_DISABLE { PARAM_VALUE.DATAFORMAT_DISABLE } { + # Procedure called to update DATAFORMAT_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATAFORMAT_DISABLE { PARAM_VALUE.DATAFORMAT_DISABLE } { + # Procedure called to validate DATAFORMAT_DISABLE + return true +} + +proc update_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } { + # Procedure called to update DELAY_REFCLK_FREQUENCY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DELAY_REFCLK_FREQUENCY { PARAM_VALUE.DELAY_REFCLK_FREQUENCY } { + # Procedure called to validate DELAY_REFCLK_FREQUENCY + return true +} + +proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to validate DEV_PACKAGE + return true +} + +proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to validate FPGA_FAMILY + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.IODELAY_CTRL { PARAM_VALUE.IODELAY_CTRL } { + # Procedure called to update IODELAY_CTRL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IODELAY_CTRL { PARAM_VALUE.IODELAY_CTRL } { + # Procedure called to validate IODELAY_CTRL + return true +} + +proc update_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to update IO_DELAY_GROUP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IO_DELAY_GROUP { PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to validate IO_DELAY_GROUP + return true +} + +proc update_PARAM_VALUE.OUT_RES { PARAM_VALUE.OUT_RES } { + # Procedure called to update OUT_RES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_RES { PARAM_VALUE.OUT_RES } { + # Procedure called to validate OUT_RES + return true +} + +proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to validate SPEED_GRADE + return true +} + +proc update_PARAM_VALUE.TWOLANES { PARAM_VALUE.TWOLANES } { + # Procedure called to update TWOLANES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TWOLANES { PARAM_VALUE.TWOLANES } { + # Procedure called to validate TWOLANES + return true +} + +proc update_PARAM_VALUE.USERPORTS_DISABLE { PARAM_VALUE.USERPORTS_DISABLE } { + # Procedure called to update USERPORTS_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.USERPORTS_DISABLE { PARAM_VALUE.USERPORTS_DISABLE } { + # Procedure called to validate USERPORTS_DISABLE + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY} +} + +proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE} +} + +proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE} +} + +proc update_MODELPARAM_VALUE.IO_DELAY_GROUP { MODELPARAM_VALUE.IO_DELAY_GROUP PARAM_VALUE.IO_DELAY_GROUP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IO_DELAY_GROUP}] ${MODELPARAM_VALUE.IO_DELAY_GROUP} +} + +proc update_MODELPARAM_VALUE.IODELAY_CTRL { MODELPARAM_VALUE.IODELAY_CTRL PARAM_VALUE.IODELAY_CTRL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IODELAY_CTRL}] ${MODELPARAM_VALUE.IODELAY_CTRL} +} + +proc update_MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY { MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY PARAM_VALUE.DELAY_REFCLK_FREQUENCY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DELAY_REFCLK_FREQUENCY}] ${MODELPARAM_VALUE.DELAY_REFCLK_FREQUENCY} +} + +proc update_MODELPARAM_VALUE.USERPORTS_DISABLE { MODELPARAM_VALUE.USERPORTS_DISABLE PARAM_VALUE.USERPORTS_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.USERPORTS_DISABLE}] ${MODELPARAM_VALUE.USERPORTS_DISABLE} +} + +proc update_MODELPARAM_VALUE.DATAFORMAT_DISABLE { MODELPARAM_VALUE.DATAFORMAT_DISABLE PARAM_VALUE.DATAFORMAT_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATAFORMAT_DISABLE}] ${MODELPARAM_VALUE.DATAFORMAT_DISABLE} +} + +proc update_MODELPARAM_VALUE.ADC_INIT_DELAY { MODELPARAM_VALUE.ADC_INIT_DELAY PARAM_VALUE.ADC_INIT_DELAY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADC_INIT_DELAY}] ${MODELPARAM_VALUE.ADC_INIT_DELAY} +} + +proc update_MODELPARAM_VALUE.ADC_RES { MODELPARAM_VALUE.ADC_RES PARAM_VALUE.ADC_RES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADC_RES}] ${MODELPARAM_VALUE.ADC_RES} +} + +proc update_MODELPARAM_VALUE.OUT_RES { MODELPARAM_VALUE.OUT_RES PARAM_VALUE.OUT_RES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_RES}] ${MODELPARAM_VALUE.OUT_RES} +} + +proc update_MODELPARAM_VALUE.TWOLANES { MODELPARAM_VALUE.TWOLANES PARAM_VALUE.TWOLANES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TWOLANES}] ${MODELPARAM_VALUE.TWOLANES} +} + diff --git a/adi_library/axi_pulse_gen/.lock b/adi_library/axi_pulse_gen/.lock new file mode 100644 index 00000000..e69de29b diff --git a/adi_library/axi_pulse_gen/Makefile b/adi_library/axi_pulse_gen/Makefile new file mode 100644 index 00000000..41d5fdd8 --- /dev/null +++ b/adi_library/axi_pulse_gen/Makefile @@ -0,0 +1,21 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_pulse_gen + +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../common/util_pulse_gen.v +GENERIC_DEPS += axi_pulse_gen.v +GENERIC_DEPS += axi_pulse_gen_regmap.v + +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += axi_pulse_gen_constr.ttcl +XILINX_DEPS += axi_pulse_gen_ip.tcl + +XILINX_LIB_DEPS += util_cdc + +include ../scripts/library.mk diff --git a/adi_library/axi_pulse_gen/axi_pulse_gen.v b/adi_library/axi_pulse_gen/axi_pulse_gen.v new file mode 100644 index 00000000..3aebe0a8 --- /dev/null +++ b/adi_library/axi_pulse_gen/axi_pulse_gen.v @@ -0,0 +1,166 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +`timescale 1ns/100ps + +module axi_pulse_gen #( + parameter ID = 0, + parameter [0:0] ASYNC_CLK_EN = 1, + parameter PULSE_WIDTH = 7, + parameter PULSE_PERIOD = 10 +) ( + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + input ext_clk, + output pulse +); + + // local parameters + + localparam [31:0] CORE_VERSION = {16'h0000, /* MAJOR */ + 8'h01, /* MINOR */ + 8'h00}; /* PATCH */ // 0.01.0 + localparam [31:0] CORE_MAGIC = 32'h504c5347; // PLSG + + // internal signals + + wire clk; + wire up_clk; + wire up_rstn; + wire up_rreq_s; + wire up_wack_s; + wire up_rack_s; + wire [13:0] up_raddr_s; + wire [31:0] up_rdata_s; + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire [31:0] pulse_width_s; + wire [31:0] pulse_period_s; + wire load_config_s; + wire pulse_gen_resetn; + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + axi_pulse_gen_regmap #( + .ID (ID), + .ASYNC_CLK_EN (ASYNC_CLK_EN), + .CORE_MAGIC (CORE_MAGIC), + .CORE_VERSION (CORE_VERSION), + .PULSE_WIDTH (PULSE_WIDTH), + .PULSE_PERIOD (PULSE_PERIOD) + ) i_regmap ( + .ext_clk (ext_clk), + .clk_out (clk), + .pulse_gen_resetn (pulse_gen_resetn), + .pulse_width (pulse_width_s), + .pulse_period (pulse_period_s), + .load_config (load_config_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + + util_pulse_gen #( + .PULSE_WIDTH(PULSE_WIDTH), + .PULSE_PERIOD(PULSE_PERIOD) + ) util_pulse_gen_i ( + .clk (clk), + .rstn (pulse_gen_resetn), + .pulse_width (pulse_width_s), + .pulse_period (pulse_period_s), + .load_config (load_config_s), + .pulse (pulse)); + + up_axi #( + .AXI_ADDRESS_WIDTH(16) + ) i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + +endmodule diff --git a/adi_library/axi_pulse_gen/axi_pulse_gen.xpr b/adi_library/axi_pulse_gen/axi_pulse_gen.xpr new file mode 100644 index 00000000..f48d8491 --- /dev/null +++ b/adi_library/axi_pulse_gen/axi_pulse_gen.xpr @@ -0,0 +1,434 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_pulse_gen/axi_pulse_gen_constr.sdc b/adi_library/axi_pulse_gen/axi_pulse_gen_constr.sdc new file mode 100644 index 00000000..ed14b00f --- /dev/null +++ b/adi_library/axi_pulse_gen/axi_pulse_gen_constr.sdc @@ -0,0 +1,8 @@ +############################################################################### +## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_false_path -to [get_registers *axi_pulse_gen_regmap*cdc_sync_stage1*] +set_false_path -to [get_registers *axi_pulse_gen_regmap*sync_data*out_data*] + diff --git a/adi_library/axi_pulse_gen/axi_pulse_gen_constr.ttcl b/adi_library/axi_pulse_gen/axi_pulse_gen_constr.ttcl new file mode 100644 index 00000000..de4449cb --- /dev/null +++ b/adi_library/axi_pulse_gen/axi_pulse_gen_constr.ttcl @@ -0,0 +1,47 @@ +############################################################################### +## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName [ttcl_add $ComponentName "_constr"] :> +<: setFileExtension ".xdc" :> +<: setFileProcessingOrder late :> +<: set async_clock [getBooleanValue "ASYNC_CLK_EN"] :> + +## False path definitions for ASYNC mode +<: if { $async_clock } { :> + +set_property ASYNC_REG TRUE \ + [get_cells -hier {*cdc_sync_stage1_reg*}] \ + [get_cells -hier {*cdc_sync_stage2_reg*}] + + set_false_path -from [get_cells -hierarchical * -filter {NAME=~*i_pulse_period_sync/cdc_hold_reg*}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_pulse_period_sync/out_data_reg*}] \ + + set_false_path -from [get_cells -hierarchical * -filter {NAME=~*i_pulse_width_sync/cdc_hold_reg*}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_pulse_width_sync/out_data_reg*}] \ + + set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*i_pulse_period_sync/out_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*i_pulse_period_sync/i_sync_in/cdc_sync_stage1_reg[0]/D}] + set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*i_pulse_period_sync/in_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*i_pulse_period_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}] + + set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*i_pulse_width_sync/out_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*i_pulse_width_sync/i_sync_in/cdc_sync_stage1_reg[0]/D}] + set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*i_pulse_width_sync/in_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*i_pulse_width_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}] + + set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/out_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/i_sync_in/cdc_sync_stage1_reg[0]/D}] + set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/in_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}] + +<: } :> diff --git a/adi_library/axi_pulse_gen/axi_pulse_gen_ip.tcl b/adi_library/axi_pulse_gen/axi_pulse_gen_ip.tcl new file mode 100644 index 00000000..900ed1c9 --- /dev/null +++ b/adi_library/axi_pulse_gen/axi_pulse_gen_ip.tcl @@ -0,0 +1,105 @@ +############################################################################### +## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create axi_pulse_gen +adi_ip_files axi_pulse_gen [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/common/util_pulse_gen.v" \ + "axi_pulse_gen_constr.ttcl" \ + "axi_pulse_gen_regmap.v" \ + "axi_pulse_gen.v"] + +adi_ip_properties axi_pulse_gen +adi_ip_ttcl axi_pulse_gen "axi_pulse_gen_constr.ttcl" + +adi_ip_add_core_dependencies [list \ + analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \ +] + + +set cc [ipx::current_core] + +set_property display_name "ADI AXI Pulse Generator" $cc +set_property description "ADI AXI Pulse Generator" $cc + +## define ext_clk port as a clock interface +adi_add_bus ext_clk slave \ + "xilinx.com:signal:clock_rtl:1.0" \ + "xilinx.com:signal:clock:1.0" \ + [list {"ext_clk" "CLK"} ] + +adi_set_ports_dependency "ext_clk" \ + "(spirit:decode(id('MODELPARAM_VALUE.ASYNC_CLK_EN')) = 1)" 0 + +## Parameter validation + +set_property -dict [list \ + "value_format" "bool" \ + "value" "true" \ + ] \ +[ipx::get_user_parameters ASYNC_CLK_EN -of_objects $cc] + +set_property -dict [list \ + "value_format" "bool" \ + "value" "true" \ + ] \ +[ipx::get_hdl_parameters ASYNC_CLK_EN -of_objects $cc] + +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "0" \ + "value_validation_range_maximum" "2147483647" \ + ] \ +[ipx::get_user_parameters PULSE_WIDTH -of_objects $cc] + +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "0" \ + "value_validation_range_maximum" "2147483647" \ + ] \ +[ipx::get_user_parameters PULSE_PERIOD -of_objects $cc] + +## Customize XGUI layout + +## Remove the automatically generated GUI page +ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] +ipx::save_core $cc + +## Create a new GUI page + +ipgui::add_page -name {AXI Pulse Generator} -component $cc -display_name {AXI Pulse Generator} +set page0 [ipgui::get_pagespec -name "AXI Pulse Generator" -component $cc] + +ipgui::add_param -name "ASYNC_CLK_EN" -component $cc -parent $page0 +set_property -dict [list \ + "display_name" "ASYNC_CLK_EN" \ + "tooltip" "External clock for the counter" \ + "widget" "checkBox" \ +] [ipgui::get_guiparamspec -name "ASYNC_CLK_EN" -component $cc] + +ipgui::add_param -name "PULSE_WIDTH" -component $cc -parent $page0 +set_property -dict [list \ + "display_name" "Pulse width" \ + "tooltip" "Pulse width of the generated signal. The unit interval is the system or external clock period." \ +] [ipgui::get_guiparamspec -name "PULSE_WIDTH" -component $cc] + +ipgui::add_param -name "PULSE_PERIOD" -component $cc -parent $page0 +set_property -dict [list \ + "display_name" "Pulse period" \ + "tooltip" "Period of the generated signal. The unit interval is the system or external clock period." \ +] [ipgui::get_guiparamspec -name "PULSE_PERIOD" -component $cc] + +## Save the modifications + +ipx::create_xgui_files $cc +ipx::save_core $cc diff --git a/adi_library/axi_pulse_gen/axi_pulse_gen_regmap.v b/adi_library/axi_pulse_gen/axi_pulse_gen_regmap.v new file mode 100644 index 00000000..e276276f --- /dev/null +++ b/adi_library/axi_pulse_gen/axi_pulse_gen_regmap.v @@ -0,0 +1,181 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +`timescale 1ns/100ps + +module axi_pulse_gen_regmap #( + + parameter ID = 0, + parameter [31:0] CORE_MAGIC = 0, + parameter [31:0] CORE_VERSION = 0, + parameter [ 0:0] ASYNC_CLK_EN = 1, + parameter PULSE_WIDTH = 7, + parameter PULSE_PERIOD = 10 +) ( + + // external clock + + input ext_clk, + + // control and status signals + + output clk_out, + output pulse_gen_resetn, + output [31:0] pulse_width, + output [31:0] pulse_period, + output load_config, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack +); + + // internal registers + + reg [31:0] up_scratch = 'd0; + reg [31:0] up_pulse_width = 'd0; + reg [31:0] up_pulse_period = 'd0; + reg up_load_config = 1'b0; + reg up_reset; + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_scratch <= 'd0; + up_pulse_period <= PULSE_PERIOD; + up_pulse_width <= PULSE_WIDTH; + up_load_config <= 1'b0; + up_reset <= 1'b1; + end else begin + up_wack <= up_wreq; + if ((up_wreq == 1'b1) && (up_waddr == 14'h2)) begin + up_scratch <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr == 14'h4)) begin + up_reset <= up_wdata[0]; + up_load_config <= up_wdata[1]; + end else begin + up_load_config <= 1'b0; + end + if ((up_wreq == 1'b1) && (up_waddr == 14'h5)) begin + up_pulse_period <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr == 14'h6)) begin + up_pulse_width <= up_wdata; + end + end + end + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq; + if (up_rreq == 1'b1) begin + case (up_raddr) + 14'h0: up_rdata <= CORE_VERSION; + 14'h1: up_rdata <= ID; + 14'h2: up_rdata <= up_scratch; + 14'h3: up_rdata <= CORE_MAGIC; + 14'h4: up_rdata <= up_reset; + 14'h5: up_rdata <= up_pulse_period; + 14'h6: up_rdata <= up_pulse_width; + default: up_rdata <= 0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + generate + if (ASYNC_CLK_EN) begin : counter_external_clock + + assign clk_out = ext_clk; + + ad_rst i_d_rst_reg ( + .rst_async (up_reset), + .clk (clk_out), + .rstn (pulse_gen_resetn), + .rst ()); + + sync_data #( + .NUM_OF_BITS (32), + .ASYNC_CLK (1) + ) i_pulse_period_sync ( + .in_clk (up_clk), + .in_data (up_pulse_period), + .out_clk (clk_out), + .out_data (pulse_period)); + + sync_data #( + .NUM_OF_BITS (32), + .ASYNC_CLK (1) + ) i_pulse_width_sync ( + .in_clk (up_clk), + .in_data (up_pulse_width), + .out_clk (clk_out), + .out_data (pulse_width)); + + sync_event #( + .NUM_OF_EVENTS (1), + .ASYNC_CLK (1) + ) i_load_config_sync ( + .in_clk (up_clk), + .in_event (up_load_config), + .out_clk (clk_out), + .out_event (load_config)); + + end else begin : counter_sys_clock // counter is running on system clk + + assign clk_out = up_clk; + assign pulse_gen_resetn = ~up_reset; + assign pulse_period = up_pulse_period; + assign pulse_width = up_pulse_width; + assign load_config = up_load_config; + + end + endgenerate + +endmodule diff --git a/adi_library/axi_pulse_gen/component.xml b/adi_library/axi_pulse_gen/component.xml new file mode 100644 index 00000000..e777f6fc --- /dev/null +++ b/adi_library/axi_pulse_gen/component.xml @@ -0,0 +1,859 @@ + + + analog.com + user + axi_pulse_gen + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + ext_clk + + + + + + + CLK + + + ext_clk + + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_pulse_gen + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 64faf65c + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_pulse_gen + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 4ac547b1 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_xpgui_view_fileset + + + + viewChecksum + ce5d3fb0 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + ext_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + pulse + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + ID + Id + 0 + + + ASYNC_CLK_EN + Async Clk En + true + + + PULSE_WIDTH + Pulse Width + 7 + + + PULSE_PERIOD + Pulse Period + 10 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + axi_pulse_gen_constr.ttcl + ttcl + + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../common/ad_rst.v + verilogSource + + + axi_pulse_gen_regmap.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/util_pulse_gen.v + verilogSource + + + axi_pulse_gen.v + verilogSource + CHECKSUM_63db955a + + + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_rst.v + verilogSource + + + axi_pulse_gen_regmap.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + ../common/util_pulse_gen.v + verilogSource + + + axi_pulse_gen.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axi_pulse_gen_v1_0.tcl + tclSource + CHECKSUM_5aee8db5 + XGUI_VERSION_2 + + + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + ADI AXI Pulse Generator + + + ID + Id + 0 + + + ASYNC_CLK_EN + ASYNC_CLK_EN + true + + + PULSE_WIDTH + Pulse width + 7 + + + PULSE_PERIOD + Pulse period + 10 + + + Component_Name + axi_pulse_gen_v1_0 + + + + + + virtex7 + + + /Analog_Devices + + ADI AXI Pulse Generator + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:47:54Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_pulse_gen/xgui/axi_pulse_gen_v1_0.tcl b/adi_library/axi_pulse_gen/xgui/axi_pulse_gen_v1_0.tcl new file mode 100644 index 00000000..eea2c81e --- /dev/null +++ b/adi_library/axi_pulse_gen/xgui/axi_pulse_gen_v1_0.tcl @@ -0,0 +1,72 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set AXI_Pulse_Generator [ipgui::add_page $IPINST -name "AXI Pulse Generator"] + set ASYNC_CLK_EN [ipgui::add_param $IPINST -name "ASYNC_CLK_EN" -parent ${AXI_Pulse_Generator}] + set_property tooltip {External clock for the counter} ${ASYNC_CLK_EN} + set PULSE_WIDTH [ipgui::add_param $IPINST -name "PULSE_WIDTH" -parent ${AXI_Pulse_Generator}] + set_property tooltip {Pulse width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_WIDTH} + set PULSE_PERIOD [ipgui::add_param $IPINST -name "PULSE_PERIOD" -parent ${AXI_Pulse_Generator}] + set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_PERIOD} + + +} + +proc update_PARAM_VALUE.ASYNC_CLK_EN { PARAM_VALUE.ASYNC_CLK_EN } { + # Procedure called to update ASYNC_CLK_EN when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASYNC_CLK_EN { PARAM_VALUE.ASYNC_CLK_EN } { + # Procedure called to validate ASYNC_CLK_EN + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.PULSE_PERIOD { PARAM_VALUE.PULSE_PERIOD } { + # Procedure called to update PULSE_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_PERIOD { PARAM_VALUE.PULSE_PERIOD } { + # Procedure called to validate PULSE_PERIOD + return true +} + +proc update_PARAM_VALUE.PULSE_WIDTH { PARAM_VALUE.PULSE_WIDTH } { + # Procedure called to update PULSE_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_WIDTH { PARAM_VALUE.PULSE_WIDTH } { + # Procedure called to validate PULSE_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.ASYNC_CLK_EN { MODELPARAM_VALUE.ASYNC_CLK_EN PARAM_VALUE.ASYNC_CLK_EN } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK_EN}] ${MODELPARAM_VALUE.ASYNC_CLK_EN} +} + +proc update_MODELPARAM_VALUE.PULSE_WIDTH { MODELPARAM_VALUE.PULSE_WIDTH PARAM_VALUE.PULSE_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_WIDTH}] ${MODELPARAM_VALUE.PULSE_WIDTH} +} + +proc update_MODELPARAM_VALUE.PULSE_PERIOD { MODELPARAM_VALUE.PULSE_PERIOD PARAM_VALUE.PULSE_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_PERIOD}] ${MODELPARAM_VALUE.PULSE_PERIOD} +} + diff --git a/adi_library/axi_pwm_gen/Makefile b/adi_library/axi_pwm_gen/Makefile new file mode 100644 index 00000000..e79670d4 --- /dev/null +++ b/adi_library/axi_pwm_gen/Makefile @@ -0,0 +1,27 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_pwm_gen + +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += axi_pwm_gen.sv +GENERIC_DEPS += axi_pwm_gen_1.v +GENERIC_DEPS += axi_pwm_gen_regmap.sv + +XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += axi_pwm_gen_constr.ttcl +XILINX_DEPS += axi_pwm_gen_ip.tcl + +XILINX_LIB_DEPS += util_cdc + +INTEL_DEPS += ../intel/common/up_rst_constr.sdc +INTEL_DEPS += ../util_cdc/sync_bits.v +INTEL_DEPS += ../util_cdc/sync_data.v +INTEL_DEPS += axi_pwm_gen_constr.sdc +INTEL_DEPS += axi_pwm_gen_hw.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_pwm_gen/axi_pwm_gen.sv b/adi_library/axi_pwm_gen/axi_pwm_gen.sv new file mode 100644 index 00000000..929dfeb1 --- /dev/null +++ b/adi_library/axi_pwm_gen/axi_pwm_gen.sv @@ -0,0 +1,394 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +`timescale 1ns/100ps + +module axi_pwm_gen #( + + parameter ID = 0, + parameter ASYNC_CLK_EN = 1, + parameter N_PWMS = 1, + parameter PWM_EXT_SYNC = 0, + parameter EXT_ASYNC_SYNC = 0, + parameter PULSE_0_WIDTH = 7, + parameter PULSE_1_WIDTH = 7, + parameter PULSE_2_WIDTH = 7, + parameter PULSE_3_WIDTH = 7, + parameter PULSE_4_WIDTH = 7, + parameter PULSE_5_WIDTH = 7, + parameter PULSE_6_WIDTH = 7, + parameter PULSE_7_WIDTH = 7, + parameter PULSE_8_WIDTH = 7, + parameter PULSE_9_WIDTH = 7, + parameter PULSE_10_WIDTH = 7, + parameter PULSE_11_WIDTH = 7, + parameter PULSE_12_WIDTH = 7, + parameter PULSE_13_WIDTH = 7, + parameter PULSE_14_WIDTH = 7, + parameter PULSE_15_WIDTH = 7, + parameter PULSE_0_PERIOD = 10, + parameter PULSE_1_PERIOD = 10, + parameter PULSE_2_PERIOD = 10, + parameter PULSE_3_PERIOD = 10, + parameter PULSE_4_PERIOD = 10, + parameter PULSE_5_PERIOD = 10, + parameter PULSE_6_PERIOD = 10, + parameter PULSE_7_PERIOD = 10, + parameter PULSE_8_PERIOD = 10, + parameter PULSE_9_PERIOD = 10, + parameter PULSE_10_PERIOD = 10, + parameter PULSE_11_PERIOD = 10, + parameter PULSE_12_PERIOD = 10, + parameter PULSE_13_PERIOD = 10, + parameter PULSE_14_PERIOD = 10, + parameter PULSE_15_PERIOD = 10, + parameter PULSE_0_OFFSET = 0, + parameter PULSE_1_OFFSET = 0, + parameter PULSE_2_OFFSET = 0, + parameter PULSE_3_OFFSET = 0, + parameter PULSE_4_OFFSET = 0, + parameter PULSE_5_OFFSET = 0, + parameter PULSE_6_OFFSET = 0, + parameter PULSE_7_OFFSET = 0, + parameter PULSE_8_OFFSET = 0, + parameter PULSE_9_OFFSET = 0, + parameter PULSE_10_OFFSET = 0, + parameter PULSE_11_OFFSET = 0, + parameter PULSE_12_OFFSET = 0, + parameter PULSE_13_OFFSET = 0, + parameter PULSE_14_OFFSET = 0, + parameter PULSE_15_OFFSET = 0 +) ( + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + input ext_clk, + input ext_sync, + + output pwm_0, + output pwm_1, + output pwm_2, + output pwm_3, + output pwm_4, + output pwm_5, + output pwm_6, + output pwm_7, + output pwm_8, + output pwm_9, + output pwm_10, + output pwm_11, + output pwm_12, + output pwm_13, + output pwm_14, + output pwm_15 +); + + // local parameters + + localparam PWMS = N_PWMS-1; + localparam [31:0] CORE_VERSION = {16'h0002, /* MAJOR */ + 8'h00, /* MINOR */ + 8'h00}; /* PATCH */ + localparam [31:0] CORE_MAGIC = 32'h601a3471; // PLSG + localparam reg [31:0] PULSE_WIDTH_G[15:0] = '{PULSE_0_WIDTH, + PULSE_1_WIDTH, + PULSE_2_WIDTH, + PULSE_3_WIDTH, + PULSE_4_WIDTH, + PULSE_5_WIDTH, + PULSE_6_WIDTH, + PULSE_7_WIDTH, + PULSE_8_WIDTH, + PULSE_9_WIDTH, + PULSE_10_WIDTH, + PULSE_11_WIDTH, + PULSE_12_WIDTH, + PULSE_13_WIDTH, + PULSE_14_WIDTH, + PULSE_15_WIDTH}; + + localparam reg [31:0] PULSE_PERIOD_G[0:15] = '{PULSE_0_PERIOD, + PULSE_1_PERIOD, + PULSE_2_PERIOD, + PULSE_3_PERIOD, + PULSE_4_PERIOD, + PULSE_5_PERIOD, + PULSE_6_PERIOD, + PULSE_7_PERIOD, + PULSE_8_PERIOD, + PULSE_9_PERIOD, + PULSE_10_PERIOD, + PULSE_11_PERIOD, + PULSE_12_PERIOD, + PULSE_13_PERIOD, + PULSE_14_PERIOD, + PULSE_15_PERIOD}; + + localparam reg [31:0] PULSE_OFFSET_G[0:15] = '{PULSE_0_OFFSET, + PULSE_1_OFFSET, + PULSE_2_OFFSET, + PULSE_3_OFFSET, + PULSE_4_OFFSET, + PULSE_5_OFFSET, + PULSE_6_OFFSET, + PULSE_7_OFFSET, + PULSE_8_OFFSET, + PULSE_9_OFFSET, + PULSE_10_OFFSET, + PULSE_11_OFFSET, + PULSE_12_OFFSET, + PULSE_13_OFFSET, + PULSE_14_OFFSET, + PULSE_15_OFFSET}; + + // internal registers + + reg [PWMS:0] sync; + reg [31:0] offset_cnt = 32'd0; + reg offset_alignment = 1'b0; + reg pause_cnt_d = 1'b0; + + // internal signals + + wire clk; + wire up_clk; + wire up_rstn; + wire up_rreq_s; + wire up_wack_s; + wire up_rack_s; + wire [ 13:0] up_raddr_s; + wire [ 31:0] up_rdata_s; + wire up_wreq_s; + wire [ 13:0] up_waddr_s; + wire [ 31:0] up_wdata_s; + wire [ 15:0] pwm; + wire [ 31:0] pwm_width_s[0:PWMS]; + wire [ 31:0] pwm_period_s[0:PWMS]; + wire [ 31:0] pwm_offset_s[0:PWMS]; + wire [ 15:0] pwm_armed; + wire load_config_s; + wire pwm_gen_resetn; + wire ext_sync_s; + wire pause_cnt; + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + axi_pwm_gen_regmap #( + .ID (ID), + .ASYNC_CLK_EN (ASYNC_CLK_EN), + .CORE_MAGIC (CORE_MAGIC), + .CORE_VERSION (CORE_VERSION), + .N_PWMS (PWMS), + .PULSE_WIDTH_G (PULSE_WIDTH_G), + .PULSE_PERIOD_G (PULSE_PERIOD_G), + .PULSE_OFFSET_G (PULSE_OFFSET_G) + ) i_regmap ( + .ext_clk (ext_clk), + .clk_out (clk), + .pwm_gen_resetn (pwm_gen_resetn), + .pwm_width (pwm_width_s), + .pwm_period (pwm_period_s), + .pwm_offset (pwm_offset_s), + .load_config (load_config_s), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + + // external sync + + generate + + reg ext_sync_m0 = 1'b1; + reg ext_sync_m1 = 1'b1; + + if (EXT_ASYNC_SYNC) begin + always @(posedge clk) begin + if (pwm_gen_resetn == 1'b0) begin + ext_sync_m0 <= 1'b1; + ext_sync_m1 <= 1'b1; + end else begin + ext_sync_m0 <= (PWM_EXT_SYNC == 1) ? ext_sync : 0; + ext_sync_m1 <= ext_sync_m0; + end + end + assign ext_sync_s = ext_sync_m1; + end else begin + assign ext_sync_s = (PWM_EXT_SYNC == 1) ? ext_sync : 0; + end + + endgenerate + + // offset counter + + always @(posedge clk) begin + if (offset_alignment == 1'b1 || pwm_gen_resetn == 1'b0) begin + offset_cnt <= 32'd0; + end else begin + offset_cnt <= offset_cnt + 1'b1; + end + + if (pwm_gen_resetn == 1'b0) begin + offset_alignment <= 1'b0; + end else begin + // when using external sync an offset alignment can be done only + // after all pwm counters are paused(load_config)/reseated + offset_alignment <= (load_config_s == 1'b1) ? 1'b1 : + offset_alignment & + (ext_sync_s ? 1'b1 : !pause_cnt); + end + end + + assign pause_cnt = ((pwm_armed[1] | + pwm_armed[2] | + pwm_armed[3] | + pwm_armed[4] | + pwm_armed[5] | + pwm_armed[6] | + pwm_armed[7] | + pwm_armed[8] | + pwm_armed[9] | + pwm_armed[10] | + pwm_armed[11] | + pwm_armed[12] | + pwm_armed[13] | + pwm_armed[14] | + pwm_armed[15] ) ? 1'b1 : 1'b0); + genvar i; + generate + for (i = 0; i <= 15; i = i + 1) begin: pwm_cnt + if (i <= PWMS) begin + axi_pwm_gen_1 #( + .PULSE_WIDTH (PULSE_WIDTH_G[i]), + .PULSE_PERIOD (PULSE_PERIOD_G[i]) + ) i_axi_pwm_gen_1 ( + .clk (clk), + .rstn (pwm_gen_resetn), + .pulse_width (pwm_width_s[i]), + .pulse_period (pwm_period_s[i]), + .load_config (load_config_s), + .sync (sync[i]), + .pulse (pwm[i]), + .pulse_armed (pwm_armed[i])); + always @(posedge clk) begin + if (pwm_gen_resetn == 1'b0) begin + sync[i] <= 1'b1; + end else begin + sync[i] <= (offset_cnt == pwm_offset_s[i]) ? offset_alignment : 1'b1; + end + end + end else begin + assign pwm[i] = 1'b0; + assign pwm_armed[i] = 1'b0; + end + end + endgenerate + + assign pwm_0 = pwm[0]; + assign pwm_1 = pwm[1]; + assign pwm_2 = pwm[2]; + assign pwm_3 = pwm[3]; + assign pwm_4 = pwm[4]; + assign pwm_5 = pwm[5]; + assign pwm_6 = pwm[6]; + assign pwm_7 = pwm[7]; + assign pwm_8 = pwm[8]; + assign pwm_9 = pwm[9]; + assign pwm_10 = pwm[10]; + assign pwm_11 = pwm[11]; + assign pwm_12 = pwm[12]; + assign pwm_13 = pwm[13]; + assign pwm_14 = pwm[14]; + assign pwm_15 = pwm[15]; + + up_axi #( + .AXI_ADDRESS_WIDTH(16) + ) i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + +endmodule diff --git a/adi_library/axi_pwm_gen/axi_pwm_gen.xpr b/adi_library/axi_pwm_gen/axi_pwm_gen.xpr new file mode 100644 index 00000000..7f7146e1 --- /dev/null +++ b/adi_library/axi_pwm_gen/axi_pwm_gen.xpr @@ -0,0 +1,434 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_pwm_gen/axi_pwm_gen_1.v b/adi_library/axi_pwm_gen/axi_pwm_gen_1.v new file mode 100644 index 00000000..8e26215f --- /dev/null +++ b/adi_library/axi_pwm_gen/axi_pwm_gen_1.v @@ -0,0 +1,154 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +`timescale 1ns/1ps + +module axi_pwm_gen_1 #( + // the width and period are defined in number of clock cycles + parameter PULSE_WIDTH = 7, + parameter PULSE_PERIOD = 100000000 +) ( + input clk, + input rstn, + + input [31:0] pulse_width, + input [31:0] pulse_period, + input load_config, + input sync, + + output pulse, + output pulse_armed +); + + // internal registers + + reg [31:0] pulse_period_cnt = 32'h0; + reg [31:0] pulse_period_read = PULSE_PERIOD; + reg [31:0] pulse_width_read = PULSE_WIDTH; + reg [31:0] pulse_period_d = PULSE_PERIOD; + reg [31:0] pulse_width_d = PULSE_WIDTH; + reg phase_align_armed = 1'b1; + reg pulse_i = 1'b0; + reg busy = 1'b0; + + // internal wires + + wire phase_align; + wire end_of_period; + wire end_of_pulse; + wire pulse_enable; + + // enable pwm + + assign pulse_enable = (pulse_period_d != 32'd0) ? 1'b1 : 1'b0; + + // flop the desired period + + always @(posedge clk) begin + if (rstn == 1'b0) begin + pulse_period_d <= pulse_period; + pulse_width_d <= pulse_width; + pulse_period_read <= pulse_period; + pulse_width_read <= pulse_width; + end else begin + // load the input period/width values + if (load_config) begin + pulse_period_read <= pulse_period; + pulse_width_read <= pulse_width; + end + // update the current period/width at the end of the period + if (end_of_period | ~pulse_enable) begin + pulse_period_d <= pulse_period_read; + pulse_width_d <= pulse_width_read; + end + end + end + + // phase align to the first sync pulse until another load_config + + always @(posedge clk) begin + if (rstn == 1'b0) begin + phase_align_armed <= 1'b1; + end else begin + if (load_config == 1'b1) begin + phase_align_armed <= sync; + end else begin + phase_align_armed <= phase_align_armed & sync; + end + end + end + + always @(posedge clk) begin + if (rstn == 1'b0) begin + busy <= 1'b0; + end else begin + if (end_of_period) begin + busy <= 1'b0; + end else if ( ~(phase_align_armed & sync)) begin + busy <= 1'b1; + end + end + end + + assign phase_align = phase_align_armed & sync & busy; + + // a free running counter + + always @(posedge clk) begin + if (rstn == 1'b0 || phase_align == 1'b1 || end_of_period == 1'b1) begin + pulse_period_cnt <= 32'd1; + end else begin + if (pulse_enable == 1'b1) begin + pulse_period_cnt <= pulse_period_cnt + 1'b1; + end + end + end + + assign end_of_period = (pulse_period_cnt == pulse_period_d) ? 1'b1 : 1'b0; + assign end_of_pulse = (pulse_period_cnt == pulse_width_d) ? 1'b1 : 1'b0; + + // generate pulse with a specified width + + always @ (posedge clk) begin + if ((rstn == 1'b0) || (end_of_pulse == 1'b1)) begin + pulse_i <= 1'b0; + end else if ((end_of_period == 1'b1 || phase_align == 1'b1) && pulse_enable == 1'b1) begin + pulse_i <= 1'b1; + end + end + + assign pulse = pulse_i & !(phase_align_armed & sync); + assign pulse_armed = phase_align_armed; + +endmodule diff --git a/adi_library/axi_pwm_gen/axi_pwm_gen_constr.sdc b/adi_library/axi_pwm_gen/axi_pwm_gen_constr.sdc new file mode 100644 index 00000000..38d4230b --- /dev/null +++ b/adi_library/axi_pwm_gen/axi_pwm_gen_constr.sdc @@ -0,0 +1,11 @@ +############################################################################### +## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set script_dir [file dirname [info script]] + +source "$script_dir/util_cdc_constr.tcl" + +set_false_path -to [get_registers *axi_pwm_gen_regmap*cdc_sync_stage1*] +set_false_path -to [get_registers *axi_pwm_gen_regmap*sync_data*out_data*] diff --git a/adi_library/axi_pwm_gen/axi_pwm_gen_constr.ttcl b/adi_library/axi_pwm_gen/axi_pwm_gen_constr.ttcl new file mode 100644 index 00000000..91c96e4f --- /dev/null +++ b/adi_library/axi_pwm_gen/axi_pwm_gen_constr.ttcl @@ -0,0 +1,37 @@ +############################################################################### +## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +# SPDX short identifier: ADIBSD +############################################################################### + +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName [ttcl_add $ComponentName "_constr"] :> +<: setFileExtension ".xdc" :> +<: setFileProcessingOrder late :> +<: set async_clock [getBooleanValue "ASYNC_CLK_EN"] :> + +## False path definitions for ASYNC mode +<: if { $async_clock } { :> + +set_property ASYNC_REG TRUE \ + [get_cells -hier {*cdc_sync_stage1_reg*}] \ + [get_cells -hier {*cdc_sync_stage2_reg*}] + + set_false_path -from [get_cells -hierarchical * -filter {NAME=~*i_pwm_props/cdc_hold_reg*}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_pwm_props/out_data_reg*}] \ + + set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*i_pwm_props/out_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*i_pwm_props/i_sync_in/cdc_sync_stage1_reg[0]/D}] + set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*i_pwm_props/in_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*i_pwm_props/i_sync_out/cdc_sync_stage1_reg[0]/D}] + + set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/out_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/i_sync_in/cdc_sync_stage1_reg[0]/D}] + set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/in_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}] + +<: } :> diff --git a/adi_library/axi_pwm_gen/axi_pwm_gen_hw.tcl b/adi_library/axi_pwm_gen/axi_pwm_gen_hw.tcl new file mode 100644 index 00000000..558e2325 --- /dev/null +++ b/adi_library/axi_pwm_gen/axi_pwm_gen_hw.tcl @@ -0,0 +1,94 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +package require qsys 14.0 +package require quartus::device + +source ../../scripts/adi_env.tcl +source ../scripts/adi_ip_intel.tcl + +ad_ip_create axi_pwm_gen {AXI PWM GEN} +ad_ip_files axi_pwm_gen [list \ + $ad_hdl_dir/library/util_cdc/sync_data.v \ + $ad_hdl_dir/library/util_cdc/sync_bits.v \ + $ad_hdl_dir/library/common/ad_rst.v \ + $ad_hdl_dir/library/common/up_axi.v \ + $ad_hdl_dir/library/intel/common/up_rst_constr.sdc \ + $ad_hdl_dir/library/util_cdc/util_cdc_constr.tcl \ + axi_pwm_gen_constr.sdc \ + axi_pwm_gen_regmap.sv \ + axi_pwm_gen_1.v \ + axi_pwm_gen.sv] + +# parameters + +ad_ip_parameter ID INTEGER 0 +ad_ip_parameter ASYNC_CLK_EN INTEGER 1 +ad_ip_parameter N_PWMS INTEGER 1 +ad_ip_parameter PWM_EXT_SYNC INTEGER 0 +ad_ip_parameter EXT_ASYNC_SYNC INTEGER 0 +ad_ip_parameter PULSE_0_WIDTH INTEGER 7 +ad_ip_parameter PULSE_1_WIDTH INTEGER 7 +ad_ip_parameter PULSE_2_WIDTH INTEGER 7 +ad_ip_parameter PULSE_3_WIDTH INTEGER 7 +ad_ip_parameter PULSE_4_WIDTH INTEGER 7 +ad_ip_parameter PULSE_5_WIDTH INTEGER 7 +ad_ip_parameter PULSE_6_WIDTH INTEGER 7 +ad_ip_parameter PULSE_7_WIDTH INTEGER 7 +ad_ip_parameter PULSE_8_WIDTH INTEGER 7 +ad_ip_parameter PULSE_9_WIDTH INTEGER 7 +ad_ip_parameter PULSE_10_WIDTH INTEGER 7 +ad_ip_parameter PULSE_11_WIDTH INTEGER 7 +ad_ip_parameter PULSE_12_WIDTH INTEGER 7 +ad_ip_parameter PULSE_13_WIDTH INTEGER 7 +ad_ip_parameter PULSE_14_WIDTH INTEGER 7 +ad_ip_parameter PULSE_15_WIDTH INTEGER 7 +ad_ip_parameter PULSE_0_PERIOD INTEGER 10 +ad_ip_parameter PULSE_1_PERIOD INTEGER 10 +ad_ip_parameter PULSE_2_PERIOD INTEGER 10 +ad_ip_parameter PULSE_3_PERIOD INTEGER 10 +ad_ip_parameter PULSE_4_PERIOD INTEGER 10 +ad_ip_parameter PULSE_5_PERIOD INTEGER 10 +ad_ip_parameter PULSE_6_PERIOD INTEGER 10 +ad_ip_parameter PULSE_7_PERIOD INTEGER 10 +ad_ip_parameter PULSE_8_PERIOD INTEGER 10 +ad_ip_parameter PULSE_9_PERIOD INTEGER 10 +ad_ip_parameter PULSE_10_PERIOD INTEGER 10 +ad_ip_parameter PULSE_11_PERIOD INTEGER 10 +ad_ip_parameter PULSE_12_PERIOD INTEGER 10 +ad_ip_parameter PULSE_13_PERIOD INTEGER 10 +ad_ip_parameter PULSE_14_PERIOD INTEGER 10 +ad_ip_parameter PULSE_15_PERIOD INTEGER 10 +ad_ip_parameter PULSE_0_OFFSET INTEGER 0 +ad_ip_parameter PULSE_1_OFFSET INTEGER 0 +ad_ip_parameter PULSE_2_OFFSET INTEGER 0 +ad_ip_parameter PULSE_3_OFFSET INTEGER 0 +ad_ip_parameter PULSE_4_OFFSET INTEGER 0 +ad_ip_parameter PULSE_5_OFFSET INTEGER 0 +ad_ip_parameter PULSE_6_OFFSET INTEGER 0 +ad_ip_parameter PULSE_7_OFFSET INTEGER 0 +ad_ip_parameter PULSE_8_OFFSET INTEGER 0 +ad_ip_parameter PULSE_9_OFFSET INTEGER 0 +ad_ip_parameter PULSE_10_OFFSET INTEGER 0 +ad_ip_parameter PULSE_11_OFFSET INTEGER 0 +ad_ip_parameter PULSE_12_OFFSET INTEGER 0 +ad_ip_parameter PULSE_13_OFFSET INTEGER 0 +ad_ip_parameter PULSE_14_OFFSET INTEGER 0 +ad_ip_parameter PULSE_15_OFFSET INTEGER 0 + +# interfaces + +# axi +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 16 + +# external clock and external sync +ad_interface clock ext_clk input 1 +ad_interface signal ext_sync input 1 + +# output signals +for {set i 0} {$i < 16} {incr i} { + ad_interface signal pwm_$i output 1 if_pwm +} diff --git a/adi_library/axi_pwm_gen/axi_pwm_gen_ip.tcl b/adi_library/axi_pwm_gen/axi_pwm_gen_ip.tcl new file mode 100644 index 00000000..7dd86435 --- /dev/null +++ b/adi_library/axi_pwm_gen/axi_pwm_gen_ip.tcl @@ -0,0 +1,158 @@ +############################################################################### +## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create axi_pwm_gen +adi_ip_files axi_pwm_gen [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "axi_pwm_gen_constr.ttcl" \ + "axi_pwm_gen_regmap.sv" \ + "axi_pwm_gen_1.v" \ + "axi_pwm_gen.sv"] + +adi_ip_properties axi_pwm_gen +adi_ip_ttcl axi_pwm_gen "axi_pwm_gen_constr.ttcl" + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen} [ipx::current_core] + +adi_ip_add_core_dependencies [list \ + analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \ +] + +set cc [ipx::current_core] + +set_property display_name "ADI AXI PWM Generator" $cc +set_property description "ADI AXI PWM Generator" $cc + +## define ext_clk port as a clock interface +adi_add_bus ext_clk slave \ + "xilinx.com:signal:clock_rtl:1.0" \ + "xilinx.com:signal:clock:1.0" \ + [list {"ext_clk" "CLK"} ] + +adi_set_ports_dependency "ext_clk" \ + "(spirit:decode(id('MODELPARAM_VALUE.ASYNC_CLK_EN')) = 1)" 0 + +## Parameter validation + +set_property -dict [list \ + "value_format" "bool" \ + "value" "true" \ + ] \ +[ipx::get_user_parameters ASYNC_CLK_EN -of_objects $cc] + +set_property -dict [list \ + "value_format" "bool" \ + "value" "true" \ + ] \ +[ipx::get_hdl_parameters ASYNC_CLK_EN -of_objects $cc] + +## Customize XGUI layout + +## Remove the automatically generated GUI page +ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] +ipx::save_core $cc + +## Create a new GUI page + +ipgui::add_page -name {AXI PWM Generator} -component $cc -display_name {AXI PWM Generator} +set page0 [ipgui::get_pagespec -name "AXI PWM Generator" -component $cc] + +ipgui::add_param -name "ASYNC_CLK_EN" -component $cc -parent $page0 +set_property -dict [list \ + "display_name" "ASYNC_CLK_EN" \ + "tooltip" "External clock for the counter" \ + "widget" "checkBox" \ +] [ipgui::get_guiparamspec -name "ASYNC_CLK_EN" -component $cc] + +ipgui::add_param -name "EXT_ASYNC_SYNC" -component $cc -parent $page0 +set_property -dict [list \ + "display_name" "External sync signal is asynchronous" \ + "tooltip" "NOTE: If active the ext_sync will be delayed 2 clock cycles." \ + "widget" "checkBox" \ +] [ipgui::get_guiparamspec -name "EXT_ASYNC_SYNC" -component $cc] + +ipgui::add_param -name "N_PWMS" -component $cc -parent $page0 +set_property -dict [list \ + "display_name" "Number of pwms" \ +] [ipgui::get_guiparamspec -name "N_PWMS" -component $cc] + +ipgui::add_param -name "PWM_EXT_SYNC" -component $cc -parent $page0 +set_property -dict [list \ + "display_name" "External sync" \ + "tooltip" "NOTE: If active the whole pwm gen module will be waiting for the ext_sync to be set low. A load config or reset must be used before deaserting the ext_sync" \ + "widget" "checkBox" \ +] [ipgui::get_guiparamspec -name "PWM_EXT_SYNC" -component $cc] + +ipgui::add_param -name "EXT_ASYNC_SYNC" -component $cc -parent $page0 +set_property -dict [list \ + "display_name" "External sync signal is asynchronous" \ + "tooltip" "NOTE: If active the ext_sync will be delayed 2 clock cycles." \ + "widget" "checkBox" \ +] [ipgui::get_guiparamspec -name "EXT_ASYNC_SYNC" -component $cc] + +# Maximum 16 pwms +for {set i 0} {$i < 16} {incr i} { + ipgui::add_param -name "PULSE_${i}_WIDTH" -component $cc -parent $page0 + set_property -dict [list \ + "display_name" "PULSE $i width" \ + "tooltip" "PULSE width of the generated signal. The unit interval is the system or external clock period." \ + ] [ipgui::get_guiparamspec -name "PULSE_${i}_WIDTH" -component $cc] + + set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "0" \ + "value_validation_range_maximum" "2147483647" \ + ] \ + [ipx::get_user_parameters PULSE_${i}_WIDTH -of_objects $cc] + + ipgui::add_param -name "PULSE_${i}_PERIOD" -component $cc -parent $page0 + set_property -dict [list \ + "display_name" "PULSE ${i} period" \ + "tooltip" "Period of the generated signal. The unit interval is the system or external clock period." \ + ] [ipgui::get_guiparamspec -name "PULSE_${i}_PERIOD" -component $cc] + + set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "0" \ + "value_validation_range_maximum" "2147483647" \ + ] \ + [ipx::get_user_parameters PULSE_${i}_PERIOD -of_objects $cc] + + ipgui::add_param -name "PULSE_${i}_OFFSET" -component $cc -parent $page0 + set_property -dict [list \ + "display_name" "PULSE ${i} offset" \ + "tooltip" "Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period." \ + ] [ipgui::get_guiparamspec -name "PULSE_${i}_OFFSET" -component $cc] + + set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "0" \ + "value_validation_range_maximum" "2147483647" \ + ] \ + [ipx::get_user_parameters PULSE_${i}_OFFSET -of_objects $cc] +} + +for {set i 0} {$i < 16} {incr i} { + adi_set_ports_dependency "pwm_$i" \ + "(spirit:decode(id('MODELPARAM_VALUE.N_PWMS')) > $i)" +} + +adi_set_ports_dependency "ext_sync" \ + "(spirit:decode(id('MODELPARAM_VALUE.PWM_EXT_SYNC')) == 1)" + +set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects $cc] + +## Save the modifications + +ipx::create_xgui_files $cc +ipx::save_core $cc diff --git a/adi_library/axi_pwm_gen/axi_pwm_gen_regmap.sv b/adi_library/axi_pwm_gen/axi_pwm_gen_regmap.sv new file mode 100644 index 00000000..91a70304 --- /dev/null +++ b/adi_library/axi_pwm_gen/axi_pwm_gen_regmap.sv @@ -0,0 +1,202 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +`timescale 1ns/100ps + +module axi_pwm_gen_regmap #( + + parameter ID = 0, + parameter CORE_MAGIC = 0, + parameter CORE_VERSION = 0, + parameter ASYNC_CLK_EN = 1, + parameter N_PWMS = 0, + parameter reg [31:0] PULSE_WIDTH_G[0:15] = '{16{32'd0}}, + parameter reg [31:0] PULSE_PERIOD_G[0:15] = '{16{32'd0}}, + parameter reg [31:0] PULSE_OFFSET_G[0:15] = '{16{32'd0}} +) ( + + // external clock + + input ext_clk, + + // control and status signals + + output clk_out, + output pwm_gen_resetn, + output [31:0] pwm_width[0:N_PWMS], + output [31:0] pwm_period[0:N_PWMS], + output [31:0] pwm_offset[0:N_PWMS], + output load_config, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack +); + + // internal registers + + reg [31:0] up_scratch = 'd0; + reg [31:0] up_pwm_width[0:N_PWMS] = PULSE_WIDTH_G[0:N_PWMS]; + reg [31:0] up_pwm_period[0:N_PWMS] = PULSE_PERIOD_G[0:N_PWMS]; + reg [31:0] up_pwm_offset[0:N_PWMS] = PULSE_OFFSET_G[0:N_PWMS]; + reg up_load_config = 1'b0; + reg up_reset = 1'b1; + + genvar n; + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_scratch <= 'd0; + up_pwm_width = PULSE_WIDTH_G[0:N_PWMS]; + up_pwm_period = PULSE_PERIOD_G[0:N_PWMS]; + up_pwm_offset = PULSE_OFFSET_G[0:N_PWMS]; + up_load_config <= 1'b0; + up_reset <= 1'b1; + end else begin + up_wack <= up_wreq; + if ((up_wreq == 1'b1) && (up_waddr == 14'h2)) begin + up_scratch <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr == 14'h4)) begin + up_reset <= up_wdata[0]; + up_load_config <= up_wdata[1]; + end else begin + up_load_config <= 1'b0; + end + for (int i = 0; i <= N_PWMS; i++) begin + if ((up_wreq == 1'b1) && (up_waddr == 14'h10 + i)) begin + up_pwm_period[i] <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr == 14'h20 + i)) begin + up_pwm_width[i] <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr == 14'h30 + i)) begin + up_pwm_offset[i] <= up_wdata; + end + end + end + end + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq; + if (up_rreq == 1'b1) begin + if (up_raddr[13:4] == 10'd0) begin + case (up_raddr) + 14'h0: up_rdata <= CORE_VERSION; + 14'h1: up_rdata <= ID; + 14'h2: up_rdata <= up_scratch; + 14'h3: up_rdata <= CORE_MAGIC; + 14'h4: up_rdata <= up_reset; + 14'h5: up_rdata <= N_PWMS +1; + default: up_rdata <= 0; + endcase + end else if (up_raddr[3:0] > N_PWMS) begin + up_rdata <= 32'b0; + end else if (up_raddr[13:4] == 10'd1) begin + up_rdata <= up_pwm_period[up_raddr[3:0]]; + end else if (up_raddr[13:4] == 10'd2) begin + up_rdata <= up_pwm_width[up_raddr[3:0]]; + end else if (up_raddr[13:4] == 10'd3) begin + up_rdata <= up_pwm_offset[up_raddr[3:0]]; + end + end else begin + up_rdata <= 32'd0; + end + end + end + + generate + if (ASYNC_CLK_EN) begin : counter_external_clock + + assign clk_out = ext_clk; + + ad_rst i_d_rst_reg ( + .rst_async (up_reset), + .clk (clk_out), + .rstn (pwm_gen_resetn), + .rst ()); + + for (n = 0; n <= N_PWMS; n = n + 1) begin: up_to_adc_cdc + sync_data #( + .NUM_OF_BITS (96), + .ASYNC_CLK (1)) + i_pwm_props ( + .in_clk (up_clk), + .in_data ({up_pwm_period[n], + up_pwm_width[n], + up_pwm_offset[n]}), + .out_clk (clk_out), + .out_data ({pwm_period[n], + pwm_width[n], + pwm_offset[n]})); + end + + sync_event #( + .NUM_OF_EVENTS (1), + .ASYNC_CLK (1) + ) i_load_config_sync ( + .in_clk (up_clk), + .in_event (up_load_config), + .out_clk (clk_out), + .out_event (load_config)); + + end else begin : counter_sys_clock // counter is running on system clk + + assign clk_out = up_clk; + assign pwm_gen_resetn = ~up_reset; + for (n = 0; n <= N_PWMS; n = n + 1) begin: up_cd + assign pwm_period[n] = up_pwm_period[n]; + assign pwm_width[n] = up_pwm_width[n]; + assign pwm_offset[n] = up_pwm_offset[n]; + end + assign load_config = up_load_config; + + end + endgenerate + +endmodule diff --git a/adi_library/axi_pwm_gen/component.xml b/adi_library/axi_pwm_gen/component.xml new file mode 100644 index 00000000..b7f6cb16 --- /dev/null +++ b/adi_library/axi_pwm_gen/component.xml @@ -0,0 +1,1685 @@ + + + analog.com + user + axi_pwm_gen + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + ext_clk + + + + + + + CLK + + + ext_clk + + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + SystemVerilog + axi_pwm_gen + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 4382ad15 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + SystemVerilog + axi_pwm_gen + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 968239ce + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_xpgui_view_fileset + + + + viewChecksum + 69a79a78 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + ext_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + ext_sync + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + pwm_0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + pwm_1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + pwm_2 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + pwm_3 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + pwm_4 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + pwm_5 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + pwm_6 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + pwm_7 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + pwm_8 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + pwm_9 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + pwm_10 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + pwm_11 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + pwm_12 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + pwm_13 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + pwm_14 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + pwm_15 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + + + ID + Id + 0 + + + ASYNC_CLK_EN + Async Clk En + true + + + N_PWMS + N Pwms + 1 + + + PWM_EXT_SYNC + Pwm Ext Sync + 0 + + + EXT_ASYNC_SYNC + Ext Async Sync + 0 + + + PULSE_0_WIDTH + Pulse 0 Width + 7 + + + PULSE_1_WIDTH + Pulse 1 Width + 7 + + + PULSE_2_WIDTH + Pulse 2 Width + 7 + + + PULSE_3_WIDTH + Pulse 3 Width + 7 + + + PULSE_4_WIDTH + Pulse 4 Width + 7 + + + PULSE_5_WIDTH + Pulse 5 Width + 7 + + + PULSE_6_WIDTH + Pulse 6 Width + 7 + + + PULSE_7_WIDTH + Pulse 7 Width + 7 + + + PULSE_8_WIDTH + Pulse 8 Width + 7 + + + PULSE_9_WIDTH + Pulse 9 Width + 7 + + + PULSE_10_WIDTH + Pulse 10 Width + 7 + + + PULSE_11_WIDTH + Pulse 11 Width + 7 + + + PULSE_12_WIDTH + Pulse 12 Width + 7 + + + PULSE_13_WIDTH + Pulse 13 Width + 7 + + + PULSE_14_WIDTH + Pulse 14 Width + 7 + + + PULSE_15_WIDTH + Pulse 15 Width + 7 + + + PULSE_0_PERIOD + Pulse 0 Period + 10 + + + PULSE_1_PERIOD + Pulse 1 Period + 10 + + + PULSE_2_PERIOD + Pulse 2 Period + 10 + + + PULSE_3_PERIOD + Pulse 3 Period + 10 + + + PULSE_4_PERIOD + Pulse 4 Period + 10 + + + PULSE_5_PERIOD + Pulse 5 Period + 10 + + + PULSE_6_PERIOD + Pulse 6 Period + 10 + + + PULSE_7_PERIOD + Pulse 7 Period + 10 + + + PULSE_8_PERIOD + Pulse 8 Period + 10 + + + PULSE_9_PERIOD + Pulse 9 Period + 10 + + + PULSE_10_PERIOD + Pulse 10 Period + 10 + + + PULSE_11_PERIOD + Pulse 11 Period + 10 + + + PULSE_12_PERIOD + Pulse 12 Period + 10 + + + PULSE_13_PERIOD + Pulse 13 Period + 10 + + + PULSE_14_PERIOD + Pulse 14 Period + 10 + + + PULSE_15_PERIOD + Pulse 15 Period + 10 + + + PULSE_0_OFFSET + Pulse 0 Offset + 0 + + + PULSE_1_OFFSET + Pulse 1 Offset + 0 + + + PULSE_2_OFFSET + Pulse 2 Offset + 0 + + + PULSE_3_OFFSET + Pulse 3 Offset + 0 + + + PULSE_4_OFFSET + Pulse 4 Offset + 0 + + + PULSE_5_OFFSET + Pulse 5 Offset + 0 + + + PULSE_6_OFFSET + Pulse 6 Offset + 0 + + + PULSE_7_OFFSET + Pulse 7 Offset + 0 + + + PULSE_8_OFFSET + Pulse 8 Offset + 0 + + + PULSE_9_OFFSET + Pulse 9 Offset + 0 + + + PULSE_10_OFFSET + Pulse 10 Offset + 0 + + + PULSE_11_OFFSET + Pulse 11 Offset + 0 + + + PULSE_12_OFFSET + Pulse 12 Offset + 0 + + + PULSE_13_OFFSET + Pulse 13 Offset + 0 + + + PULSE_14_OFFSET + Pulse 14 Offset + 0 + + + PULSE_15_OFFSET + Pulse 15 Offset + 0 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + axi_pwm_gen_constr.ttcl + ttcl + + + ../xilinx/common/ad_rst_constr.xdc + xdc + + + ../common/ad_rst.v + verilogSource + + + axi_pwm_gen_1.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + axi_pwm_gen_regmap.sv + systemVerilogSource + + + axi_pwm_gen.sv + systemVerilogSource + CHECKSUM_bb2ebc50 + + + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_rst.v + verilogSource + + + axi_pwm_gen_1.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + axi_pwm_gen_regmap.sv + systemVerilogSource + + + axi_pwm_gen.sv + systemVerilogSource + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axi_pwm_gen_v1_0.tcl + tclSource + CHECKSUM_1a7791fc + XGUI_VERSION_2 + + + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + ADI AXI PWM Generator + + + ID + Id + 0 + + + ASYNC_CLK_EN + ASYNC_CLK_EN + true + + + N_PWMS + Number of pwms + 1 + + + PWM_EXT_SYNC + External sync + 0 + + + EXT_ASYNC_SYNC + External sync signal is asynchronous + 0 + + + PULSE_0_WIDTH + PULSE 0 width + 7 + + + PULSE_1_WIDTH + PULSE 1 width + 7 + + + PULSE_2_WIDTH + PULSE 2 width + 7 + + + PULSE_3_WIDTH + PULSE 3 width + 7 + + + PULSE_4_WIDTH + PULSE 4 width + 7 + + + PULSE_5_WIDTH + PULSE 5 width + 7 + + + PULSE_6_WIDTH + PULSE 6 width + 7 + + + PULSE_7_WIDTH + PULSE 7 width + 7 + + + PULSE_8_WIDTH + PULSE 8 width + 7 + + + PULSE_9_WIDTH + PULSE 9 width + 7 + + + PULSE_10_WIDTH + PULSE 10 width + 7 + + + PULSE_11_WIDTH + PULSE 11 width + 7 + + + PULSE_12_WIDTH + PULSE 12 width + 7 + + + PULSE_13_WIDTH + PULSE 13 width + 7 + + + PULSE_14_WIDTH + PULSE 14 width + 7 + + + PULSE_15_WIDTH + PULSE 15 width + 7 + + + PULSE_0_PERIOD + PULSE 0 period + 10 + + + PULSE_1_PERIOD + PULSE 1 period + 10 + + + PULSE_2_PERIOD + PULSE 2 period + 10 + + + PULSE_3_PERIOD + PULSE 3 period + 10 + + + PULSE_4_PERIOD + PULSE 4 period + 10 + + + PULSE_5_PERIOD + PULSE 5 period + 10 + + + PULSE_6_PERIOD + PULSE 6 period + 10 + + + PULSE_7_PERIOD + PULSE 7 period + 10 + + + PULSE_8_PERIOD + PULSE 8 period + 10 + + + PULSE_9_PERIOD + PULSE 9 period + 10 + + + PULSE_10_PERIOD + PULSE 10 period + 10 + + + PULSE_11_PERIOD + PULSE 11 period + 10 + + + PULSE_12_PERIOD + PULSE 12 period + 10 + + + PULSE_13_PERIOD + PULSE 13 period + 10 + + + PULSE_14_PERIOD + PULSE 14 period + 10 + + + PULSE_15_PERIOD + PULSE 15 period + 10 + + + PULSE_0_OFFSET + PULSE 0 offset + 0 + + + PULSE_1_OFFSET + PULSE 1 offset + 0 + + + PULSE_2_OFFSET + PULSE 2 offset + 0 + + + PULSE_3_OFFSET + PULSE 3 offset + 0 + + + PULSE_4_OFFSET + PULSE 4 offset + 0 + + + PULSE_5_OFFSET + PULSE 5 offset + 0 + + + PULSE_6_OFFSET + PULSE 6 offset + 0 + + + PULSE_7_OFFSET + PULSE 7 offset + 0 + + + PULSE_8_OFFSET + PULSE 8 offset + 0 + + + PULSE_9_OFFSET + PULSE 9 offset + 0 + + + PULSE_10_OFFSET + PULSE 10 offset + 0 + + + PULSE_11_OFFSET + PULSE 11 offset + 0 + + + PULSE_12_OFFSET + PULSE 12 offset + 0 + + + PULSE_13_OFFSET + PULSE 13 offset + 0 + + + PULSE_14_OFFSET + PULSE 14 offset + 0 + + + PULSE_15_OFFSET + PULSE 15 offset + 0 + + + Component_Name + axi_pwm_gen_v1_0 + + + + + + virtex7 + + + /Analog_Devices + + ADI AXI PWM Generator + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen + 1 + 2024-01-14T03:48:40Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_pwm_gen/xgui/axi_pwm_gen_v1_0.tcl b/adi_library/axi_pwm_gen/xgui/axi_pwm_gen_v1_0.tcl new file mode 100644 index 00000000..10280d1e --- /dev/null +++ b/adi_library/axi_pwm_gen/xgui/axi_pwm_gen_v1_0.tcl @@ -0,0 +1,855 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set AXI_PWM_Generator [ipgui::add_page $IPINST -name "AXI PWM Generator"] + set ASYNC_CLK_EN [ipgui::add_param $IPINST -name "ASYNC_CLK_EN" -parent ${AXI_PWM_Generator}] + set_property tooltip {External clock for the counter} ${ASYNC_CLK_EN} + set EXT_ASYNC_SYNC [ipgui::add_param $IPINST -name "EXT_ASYNC_SYNC" -parent ${AXI_PWM_Generator} -widget checkBox] + set_property tooltip {NOTE: If active the ext_sync will be delayed 2 clock cycles.} ${EXT_ASYNC_SYNC} + ipgui::add_param $IPINST -name "N_PWMS" -parent ${AXI_PWM_Generator} + set PWM_EXT_SYNC [ipgui::add_param $IPINST -name "PWM_EXT_SYNC" -parent ${AXI_PWM_Generator} -widget checkBox] + set_property tooltip {NOTE: If active the whole pwm gen module will be waiting for the ext_sync to be set low. A load config or reset must be used before deaserting the ext_sync} ${PWM_EXT_SYNC} + set PULSE_0_WIDTH [ipgui::add_param $IPINST -name "PULSE_0_WIDTH" -parent ${AXI_PWM_Generator}] + set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_0_WIDTH} + set PULSE_0_PERIOD [ipgui::add_param $IPINST -name "PULSE_0_PERIOD" -parent ${AXI_PWM_Generator}] + set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_0_PERIOD} + set PULSE_0_OFFSET [ipgui::add_param $IPINST -name "PULSE_0_OFFSET" -parent ${AXI_PWM_Generator}] + set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_0_OFFSET} + set PULSE_1_WIDTH [ipgui::add_param $IPINST -name "PULSE_1_WIDTH" -parent ${AXI_PWM_Generator}] + set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_1_WIDTH} + set PULSE_1_PERIOD [ipgui::add_param $IPINST -name "PULSE_1_PERIOD" -parent ${AXI_PWM_Generator}] + set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_1_PERIOD} + set PULSE_1_OFFSET [ipgui::add_param $IPINST -name "PULSE_1_OFFSET" -parent ${AXI_PWM_Generator}] + set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_1_OFFSET} + set PULSE_2_WIDTH [ipgui::add_param $IPINST -name "PULSE_2_WIDTH" -parent ${AXI_PWM_Generator}] + set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_2_WIDTH} + set PULSE_2_PERIOD [ipgui::add_param $IPINST -name "PULSE_2_PERIOD" -parent ${AXI_PWM_Generator}] + set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_2_PERIOD} + set PULSE_2_OFFSET [ipgui::add_param $IPINST -name "PULSE_2_OFFSET" -parent ${AXI_PWM_Generator}] + set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_2_OFFSET} + set PULSE_3_WIDTH [ipgui::add_param $IPINST -name "PULSE_3_WIDTH" -parent ${AXI_PWM_Generator}] + set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_3_WIDTH} + set PULSE_3_PERIOD [ipgui::add_param $IPINST -name "PULSE_3_PERIOD" -parent ${AXI_PWM_Generator}] + set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_3_PERIOD} + set PULSE_3_OFFSET [ipgui::add_param $IPINST -name "PULSE_3_OFFSET" -parent ${AXI_PWM_Generator}] + set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_3_OFFSET} + set PULSE_4_WIDTH [ipgui::add_param $IPINST -name "PULSE_4_WIDTH" -parent ${AXI_PWM_Generator}] + set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_4_WIDTH} + set PULSE_4_PERIOD [ipgui::add_param $IPINST -name "PULSE_4_PERIOD" -parent ${AXI_PWM_Generator}] + set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_4_PERIOD} + set PULSE_4_OFFSET [ipgui::add_param $IPINST -name "PULSE_4_OFFSET" -parent ${AXI_PWM_Generator}] + set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_4_OFFSET} + set PULSE_5_WIDTH [ipgui::add_param $IPINST -name "PULSE_5_WIDTH" -parent ${AXI_PWM_Generator}] + set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_5_WIDTH} + set PULSE_5_PERIOD [ipgui::add_param $IPINST -name "PULSE_5_PERIOD" -parent ${AXI_PWM_Generator}] + set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_5_PERIOD} + set PULSE_5_OFFSET [ipgui::add_param $IPINST -name "PULSE_5_OFFSET" -parent ${AXI_PWM_Generator}] + set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_5_OFFSET} + set PULSE_6_WIDTH [ipgui::add_param $IPINST -name "PULSE_6_WIDTH" -parent ${AXI_PWM_Generator}] + set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_6_WIDTH} + set PULSE_6_PERIOD [ipgui::add_param $IPINST -name "PULSE_6_PERIOD" -parent ${AXI_PWM_Generator}] + set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_6_PERIOD} + set PULSE_6_OFFSET [ipgui::add_param $IPINST -name "PULSE_6_OFFSET" -parent ${AXI_PWM_Generator}] + set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_6_OFFSET} + set PULSE_7_WIDTH [ipgui::add_param $IPINST -name "PULSE_7_WIDTH" -parent ${AXI_PWM_Generator}] + set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_7_WIDTH} + set PULSE_7_PERIOD [ipgui::add_param $IPINST -name "PULSE_7_PERIOD" -parent ${AXI_PWM_Generator}] + set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_7_PERIOD} + set PULSE_7_OFFSET [ipgui::add_param $IPINST -name "PULSE_7_OFFSET" -parent ${AXI_PWM_Generator}] + set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_7_OFFSET} + set PULSE_8_WIDTH [ipgui::add_param $IPINST -name "PULSE_8_WIDTH" -parent ${AXI_PWM_Generator}] + set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_8_WIDTH} + set PULSE_8_PERIOD [ipgui::add_param $IPINST -name "PULSE_8_PERIOD" -parent ${AXI_PWM_Generator}] + set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_8_PERIOD} + set PULSE_8_OFFSET [ipgui::add_param $IPINST -name "PULSE_8_OFFSET" -parent ${AXI_PWM_Generator}] + set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_8_OFFSET} + set PULSE_9_WIDTH [ipgui::add_param $IPINST -name "PULSE_9_WIDTH" -parent ${AXI_PWM_Generator}] + set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_9_WIDTH} + set PULSE_9_PERIOD [ipgui::add_param $IPINST -name "PULSE_9_PERIOD" -parent ${AXI_PWM_Generator}] + set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_9_PERIOD} + set PULSE_9_OFFSET [ipgui::add_param $IPINST -name "PULSE_9_OFFSET" -parent ${AXI_PWM_Generator}] + set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_9_OFFSET} + set PULSE_10_WIDTH [ipgui::add_param $IPINST -name "PULSE_10_WIDTH" -parent ${AXI_PWM_Generator}] + set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_10_WIDTH} + set PULSE_10_PERIOD [ipgui::add_param $IPINST -name "PULSE_10_PERIOD" -parent ${AXI_PWM_Generator}] + set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_10_PERIOD} + set PULSE_10_OFFSET [ipgui::add_param $IPINST -name "PULSE_10_OFFSET" -parent ${AXI_PWM_Generator}] + set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_10_OFFSET} + set PULSE_11_WIDTH [ipgui::add_param $IPINST -name "PULSE_11_WIDTH" -parent ${AXI_PWM_Generator}] + set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_11_WIDTH} + set PULSE_11_PERIOD [ipgui::add_param $IPINST -name "PULSE_11_PERIOD" -parent ${AXI_PWM_Generator}] + set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_11_PERIOD} + set PULSE_11_OFFSET [ipgui::add_param $IPINST -name "PULSE_11_OFFSET" -parent ${AXI_PWM_Generator}] + set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_11_OFFSET} + set PULSE_12_WIDTH [ipgui::add_param $IPINST -name "PULSE_12_WIDTH" -parent ${AXI_PWM_Generator}] + set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_12_WIDTH} + set PULSE_12_PERIOD [ipgui::add_param $IPINST -name "PULSE_12_PERIOD" -parent ${AXI_PWM_Generator}] + set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_12_PERIOD} + set PULSE_12_OFFSET [ipgui::add_param $IPINST -name "PULSE_12_OFFSET" -parent ${AXI_PWM_Generator}] + set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_12_OFFSET} + set PULSE_13_WIDTH [ipgui::add_param $IPINST -name "PULSE_13_WIDTH" -parent ${AXI_PWM_Generator}] + set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_13_WIDTH} + set PULSE_13_PERIOD [ipgui::add_param $IPINST -name "PULSE_13_PERIOD" -parent ${AXI_PWM_Generator}] + set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_13_PERIOD} + set PULSE_13_OFFSET [ipgui::add_param $IPINST -name "PULSE_13_OFFSET" -parent ${AXI_PWM_Generator}] + set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_13_OFFSET} + set PULSE_14_WIDTH [ipgui::add_param $IPINST -name "PULSE_14_WIDTH" -parent ${AXI_PWM_Generator}] + set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_14_WIDTH} + set PULSE_14_PERIOD [ipgui::add_param $IPINST -name "PULSE_14_PERIOD" -parent ${AXI_PWM_Generator}] + set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_14_PERIOD} + set PULSE_14_OFFSET [ipgui::add_param $IPINST -name "PULSE_14_OFFSET" -parent ${AXI_PWM_Generator}] + set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_14_OFFSET} + set PULSE_15_WIDTH [ipgui::add_param $IPINST -name "PULSE_15_WIDTH" -parent ${AXI_PWM_Generator}] + set_property tooltip {PULSE width of the generated signal. The unit interval is the system or external clock period.} ${PULSE_15_WIDTH} + set PULSE_15_PERIOD [ipgui::add_param $IPINST -name "PULSE_15_PERIOD" -parent ${AXI_PWM_Generator}] + set_property tooltip {Period of the generated signal. The unit interval is the system or external clock period.} ${PULSE_15_PERIOD} + set PULSE_15_OFFSET [ipgui::add_param $IPINST -name "PULSE_15_OFFSET" -parent ${AXI_PWM_Generator}] + set_property tooltip {Offset of the generated signal referenced to PULSE 1. The unit interval is the system or external clock period.} ${PULSE_15_OFFSET} + + +} + +proc update_PARAM_VALUE.ASYNC_CLK_EN { PARAM_VALUE.ASYNC_CLK_EN } { + # Procedure called to update ASYNC_CLK_EN when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASYNC_CLK_EN { PARAM_VALUE.ASYNC_CLK_EN } { + # Procedure called to validate ASYNC_CLK_EN + return true +} + +proc update_PARAM_VALUE.EXT_ASYNC_SYNC { PARAM_VALUE.EXT_ASYNC_SYNC } { + # Procedure called to update EXT_ASYNC_SYNC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.EXT_ASYNC_SYNC { PARAM_VALUE.EXT_ASYNC_SYNC } { + # Procedure called to validate EXT_ASYNC_SYNC + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.N_PWMS { PARAM_VALUE.N_PWMS } { + # Procedure called to update N_PWMS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N_PWMS { PARAM_VALUE.N_PWMS } { + # Procedure called to validate N_PWMS + return true +} + +proc update_PARAM_VALUE.PULSE_0_OFFSET { PARAM_VALUE.PULSE_0_OFFSET } { + # Procedure called to update PULSE_0_OFFSET when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_0_OFFSET { PARAM_VALUE.PULSE_0_OFFSET } { + # Procedure called to validate PULSE_0_OFFSET + return true +} + +proc update_PARAM_VALUE.PULSE_0_PERIOD { PARAM_VALUE.PULSE_0_PERIOD } { + # Procedure called to update PULSE_0_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_0_PERIOD { PARAM_VALUE.PULSE_0_PERIOD } { + # Procedure called to validate PULSE_0_PERIOD + return true +} + +proc update_PARAM_VALUE.PULSE_0_WIDTH { PARAM_VALUE.PULSE_0_WIDTH } { + # Procedure called to update PULSE_0_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_0_WIDTH { PARAM_VALUE.PULSE_0_WIDTH } { + # Procedure called to validate PULSE_0_WIDTH + return true +} + +proc update_PARAM_VALUE.PULSE_10_OFFSET { PARAM_VALUE.PULSE_10_OFFSET } { + # Procedure called to update PULSE_10_OFFSET when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_10_OFFSET { PARAM_VALUE.PULSE_10_OFFSET } { + # Procedure called to validate PULSE_10_OFFSET + return true +} + +proc update_PARAM_VALUE.PULSE_10_PERIOD { PARAM_VALUE.PULSE_10_PERIOD } { + # Procedure called to update PULSE_10_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_10_PERIOD { PARAM_VALUE.PULSE_10_PERIOD } { + # Procedure called to validate PULSE_10_PERIOD + return true +} + +proc update_PARAM_VALUE.PULSE_10_WIDTH { PARAM_VALUE.PULSE_10_WIDTH } { + # Procedure called to update PULSE_10_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_10_WIDTH { PARAM_VALUE.PULSE_10_WIDTH } { + # Procedure called to validate PULSE_10_WIDTH + return true +} + +proc update_PARAM_VALUE.PULSE_11_OFFSET { PARAM_VALUE.PULSE_11_OFFSET } { + # Procedure called to update PULSE_11_OFFSET when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_11_OFFSET { PARAM_VALUE.PULSE_11_OFFSET } { + # Procedure called to validate PULSE_11_OFFSET + return true +} + +proc update_PARAM_VALUE.PULSE_11_PERIOD { PARAM_VALUE.PULSE_11_PERIOD } { + # Procedure called to update PULSE_11_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_11_PERIOD { PARAM_VALUE.PULSE_11_PERIOD } { + # Procedure called to validate PULSE_11_PERIOD + return true +} + +proc update_PARAM_VALUE.PULSE_11_WIDTH { PARAM_VALUE.PULSE_11_WIDTH } { + # Procedure called to update PULSE_11_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_11_WIDTH { PARAM_VALUE.PULSE_11_WIDTH } { + # Procedure called to validate PULSE_11_WIDTH + return true +} + +proc update_PARAM_VALUE.PULSE_12_OFFSET { PARAM_VALUE.PULSE_12_OFFSET } { + # Procedure called to update PULSE_12_OFFSET when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_12_OFFSET { PARAM_VALUE.PULSE_12_OFFSET } { + # Procedure called to validate PULSE_12_OFFSET + return true +} + +proc update_PARAM_VALUE.PULSE_12_PERIOD { PARAM_VALUE.PULSE_12_PERIOD } { + # Procedure called to update PULSE_12_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_12_PERIOD { PARAM_VALUE.PULSE_12_PERIOD } { + # Procedure called to validate PULSE_12_PERIOD + return true +} + +proc update_PARAM_VALUE.PULSE_12_WIDTH { PARAM_VALUE.PULSE_12_WIDTH } { + # Procedure called to update PULSE_12_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_12_WIDTH { PARAM_VALUE.PULSE_12_WIDTH } { + # Procedure called to validate PULSE_12_WIDTH + return true +} + +proc update_PARAM_VALUE.PULSE_13_OFFSET { PARAM_VALUE.PULSE_13_OFFSET } { + # Procedure called to update PULSE_13_OFFSET when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_13_OFFSET { PARAM_VALUE.PULSE_13_OFFSET } { + # Procedure called to validate PULSE_13_OFFSET + return true +} + +proc update_PARAM_VALUE.PULSE_13_PERIOD { PARAM_VALUE.PULSE_13_PERIOD } { + # Procedure called to update PULSE_13_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_13_PERIOD { PARAM_VALUE.PULSE_13_PERIOD } { + # Procedure called to validate PULSE_13_PERIOD + return true +} + +proc update_PARAM_VALUE.PULSE_13_WIDTH { PARAM_VALUE.PULSE_13_WIDTH } { + # Procedure called to update PULSE_13_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_13_WIDTH { PARAM_VALUE.PULSE_13_WIDTH } { + # Procedure called to validate PULSE_13_WIDTH + return true +} + +proc update_PARAM_VALUE.PULSE_14_OFFSET { PARAM_VALUE.PULSE_14_OFFSET } { + # Procedure called to update PULSE_14_OFFSET when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_14_OFFSET { PARAM_VALUE.PULSE_14_OFFSET } { + # Procedure called to validate PULSE_14_OFFSET + return true +} + +proc update_PARAM_VALUE.PULSE_14_PERIOD { PARAM_VALUE.PULSE_14_PERIOD } { + # Procedure called to update PULSE_14_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_14_PERIOD { PARAM_VALUE.PULSE_14_PERIOD } { + # Procedure called to validate PULSE_14_PERIOD + return true +} + +proc update_PARAM_VALUE.PULSE_14_WIDTH { PARAM_VALUE.PULSE_14_WIDTH } { + # Procedure called to update PULSE_14_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_14_WIDTH { PARAM_VALUE.PULSE_14_WIDTH } { + # Procedure called to validate PULSE_14_WIDTH + return true +} + +proc update_PARAM_VALUE.PULSE_15_OFFSET { PARAM_VALUE.PULSE_15_OFFSET } { + # Procedure called to update PULSE_15_OFFSET when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_15_OFFSET { PARAM_VALUE.PULSE_15_OFFSET } { + # Procedure called to validate PULSE_15_OFFSET + return true +} + +proc update_PARAM_VALUE.PULSE_15_PERIOD { PARAM_VALUE.PULSE_15_PERIOD } { + # Procedure called to update PULSE_15_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_15_PERIOD { PARAM_VALUE.PULSE_15_PERIOD } { + # Procedure called to validate PULSE_15_PERIOD + return true +} + +proc update_PARAM_VALUE.PULSE_15_WIDTH { PARAM_VALUE.PULSE_15_WIDTH } { + # Procedure called to update PULSE_15_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_15_WIDTH { PARAM_VALUE.PULSE_15_WIDTH } { + # Procedure called to validate PULSE_15_WIDTH + return true +} + +proc update_PARAM_VALUE.PULSE_1_OFFSET { PARAM_VALUE.PULSE_1_OFFSET } { + # Procedure called to update PULSE_1_OFFSET when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_1_OFFSET { PARAM_VALUE.PULSE_1_OFFSET } { + # Procedure called to validate PULSE_1_OFFSET + return true +} + +proc update_PARAM_VALUE.PULSE_1_PERIOD { PARAM_VALUE.PULSE_1_PERIOD } { + # Procedure called to update PULSE_1_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_1_PERIOD { PARAM_VALUE.PULSE_1_PERIOD } { + # Procedure called to validate PULSE_1_PERIOD + return true +} + +proc update_PARAM_VALUE.PULSE_1_WIDTH { PARAM_VALUE.PULSE_1_WIDTH } { + # Procedure called to update PULSE_1_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_1_WIDTH { PARAM_VALUE.PULSE_1_WIDTH } { + # Procedure called to validate PULSE_1_WIDTH + return true +} + +proc update_PARAM_VALUE.PULSE_2_OFFSET { PARAM_VALUE.PULSE_2_OFFSET } { + # Procedure called to update PULSE_2_OFFSET when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_2_OFFSET { PARAM_VALUE.PULSE_2_OFFSET } { + # Procedure called to validate PULSE_2_OFFSET + return true +} + +proc update_PARAM_VALUE.PULSE_2_PERIOD { PARAM_VALUE.PULSE_2_PERIOD } { + # Procedure called to update PULSE_2_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_2_PERIOD { PARAM_VALUE.PULSE_2_PERIOD } { + # Procedure called to validate PULSE_2_PERIOD + return true +} + +proc update_PARAM_VALUE.PULSE_2_WIDTH { PARAM_VALUE.PULSE_2_WIDTH } { + # Procedure called to update PULSE_2_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_2_WIDTH { PARAM_VALUE.PULSE_2_WIDTH } { + # Procedure called to validate PULSE_2_WIDTH + return true +} + +proc update_PARAM_VALUE.PULSE_3_OFFSET { PARAM_VALUE.PULSE_3_OFFSET } { + # Procedure called to update PULSE_3_OFFSET when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_3_OFFSET { PARAM_VALUE.PULSE_3_OFFSET } { + # Procedure called to validate PULSE_3_OFFSET + return true +} + +proc update_PARAM_VALUE.PULSE_3_PERIOD { PARAM_VALUE.PULSE_3_PERIOD } { + # Procedure called to update PULSE_3_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_3_PERIOD { PARAM_VALUE.PULSE_3_PERIOD } { + # Procedure called to validate PULSE_3_PERIOD + return true +} + +proc update_PARAM_VALUE.PULSE_3_WIDTH { PARAM_VALUE.PULSE_3_WIDTH } { + # Procedure called to update PULSE_3_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_3_WIDTH { PARAM_VALUE.PULSE_3_WIDTH } { + # Procedure called to validate PULSE_3_WIDTH + return true +} + +proc update_PARAM_VALUE.PULSE_4_OFFSET { PARAM_VALUE.PULSE_4_OFFSET } { + # Procedure called to update PULSE_4_OFFSET when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_4_OFFSET { PARAM_VALUE.PULSE_4_OFFSET } { + # Procedure called to validate PULSE_4_OFFSET + return true +} + +proc update_PARAM_VALUE.PULSE_4_PERIOD { PARAM_VALUE.PULSE_4_PERIOD } { + # Procedure called to update PULSE_4_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_4_PERIOD { PARAM_VALUE.PULSE_4_PERIOD } { + # Procedure called to validate PULSE_4_PERIOD + return true +} + +proc update_PARAM_VALUE.PULSE_4_WIDTH { PARAM_VALUE.PULSE_4_WIDTH } { + # Procedure called to update PULSE_4_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_4_WIDTH { PARAM_VALUE.PULSE_4_WIDTH } { + # Procedure called to validate PULSE_4_WIDTH + return true +} + +proc update_PARAM_VALUE.PULSE_5_OFFSET { PARAM_VALUE.PULSE_5_OFFSET } { + # Procedure called to update PULSE_5_OFFSET when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_5_OFFSET { PARAM_VALUE.PULSE_5_OFFSET } { + # Procedure called to validate PULSE_5_OFFSET + return true +} + +proc update_PARAM_VALUE.PULSE_5_PERIOD { PARAM_VALUE.PULSE_5_PERIOD } { + # Procedure called to update PULSE_5_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_5_PERIOD { PARAM_VALUE.PULSE_5_PERIOD } { + # Procedure called to validate PULSE_5_PERIOD + return true +} + +proc update_PARAM_VALUE.PULSE_5_WIDTH { PARAM_VALUE.PULSE_5_WIDTH } { + # Procedure called to update PULSE_5_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_5_WIDTH { PARAM_VALUE.PULSE_5_WIDTH } { + # Procedure called to validate PULSE_5_WIDTH + return true +} + +proc update_PARAM_VALUE.PULSE_6_OFFSET { PARAM_VALUE.PULSE_6_OFFSET } { + # Procedure called to update PULSE_6_OFFSET when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_6_OFFSET { PARAM_VALUE.PULSE_6_OFFSET } { + # Procedure called to validate PULSE_6_OFFSET + return true +} + +proc update_PARAM_VALUE.PULSE_6_PERIOD { PARAM_VALUE.PULSE_6_PERIOD } { + # Procedure called to update PULSE_6_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_6_PERIOD { PARAM_VALUE.PULSE_6_PERIOD } { + # Procedure called to validate PULSE_6_PERIOD + return true +} + +proc update_PARAM_VALUE.PULSE_6_WIDTH { PARAM_VALUE.PULSE_6_WIDTH } { + # Procedure called to update PULSE_6_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_6_WIDTH { PARAM_VALUE.PULSE_6_WIDTH } { + # Procedure called to validate PULSE_6_WIDTH + return true +} + +proc update_PARAM_VALUE.PULSE_7_OFFSET { PARAM_VALUE.PULSE_7_OFFSET } { + # Procedure called to update PULSE_7_OFFSET when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_7_OFFSET { PARAM_VALUE.PULSE_7_OFFSET } { + # Procedure called to validate PULSE_7_OFFSET + return true +} + +proc update_PARAM_VALUE.PULSE_7_PERIOD { PARAM_VALUE.PULSE_7_PERIOD } { + # Procedure called to update PULSE_7_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_7_PERIOD { PARAM_VALUE.PULSE_7_PERIOD } { + # Procedure called to validate PULSE_7_PERIOD + return true +} + +proc update_PARAM_VALUE.PULSE_7_WIDTH { PARAM_VALUE.PULSE_7_WIDTH } { + # Procedure called to update PULSE_7_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_7_WIDTH { PARAM_VALUE.PULSE_7_WIDTH } { + # Procedure called to validate PULSE_7_WIDTH + return true +} + +proc update_PARAM_VALUE.PULSE_8_OFFSET { PARAM_VALUE.PULSE_8_OFFSET } { + # Procedure called to update PULSE_8_OFFSET when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_8_OFFSET { PARAM_VALUE.PULSE_8_OFFSET } { + # Procedure called to validate PULSE_8_OFFSET + return true +} + +proc update_PARAM_VALUE.PULSE_8_PERIOD { PARAM_VALUE.PULSE_8_PERIOD } { + # Procedure called to update PULSE_8_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_8_PERIOD { PARAM_VALUE.PULSE_8_PERIOD } { + # Procedure called to validate PULSE_8_PERIOD + return true +} + +proc update_PARAM_VALUE.PULSE_8_WIDTH { PARAM_VALUE.PULSE_8_WIDTH } { + # Procedure called to update PULSE_8_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_8_WIDTH { PARAM_VALUE.PULSE_8_WIDTH } { + # Procedure called to validate PULSE_8_WIDTH + return true +} + +proc update_PARAM_VALUE.PULSE_9_OFFSET { PARAM_VALUE.PULSE_9_OFFSET } { + # Procedure called to update PULSE_9_OFFSET when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_9_OFFSET { PARAM_VALUE.PULSE_9_OFFSET } { + # Procedure called to validate PULSE_9_OFFSET + return true +} + +proc update_PARAM_VALUE.PULSE_9_PERIOD { PARAM_VALUE.PULSE_9_PERIOD } { + # Procedure called to update PULSE_9_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_9_PERIOD { PARAM_VALUE.PULSE_9_PERIOD } { + # Procedure called to validate PULSE_9_PERIOD + return true +} + +proc update_PARAM_VALUE.PULSE_9_WIDTH { PARAM_VALUE.PULSE_9_WIDTH } { + # Procedure called to update PULSE_9_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_9_WIDTH { PARAM_VALUE.PULSE_9_WIDTH } { + # Procedure called to validate PULSE_9_WIDTH + return true +} + +proc update_PARAM_VALUE.PWM_EXT_SYNC { PARAM_VALUE.PWM_EXT_SYNC } { + # Procedure called to update PWM_EXT_SYNC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PWM_EXT_SYNC { PARAM_VALUE.PWM_EXT_SYNC } { + # Procedure called to validate PWM_EXT_SYNC + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.ASYNC_CLK_EN { MODELPARAM_VALUE.ASYNC_CLK_EN PARAM_VALUE.ASYNC_CLK_EN } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK_EN}] ${MODELPARAM_VALUE.ASYNC_CLK_EN} +} + +proc update_MODELPARAM_VALUE.N_PWMS { MODELPARAM_VALUE.N_PWMS PARAM_VALUE.N_PWMS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N_PWMS}] ${MODELPARAM_VALUE.N_PWMS} +} + +proc update_MODELPARAM_VALUE.PWM_EXT_SYNC { MODELPARAM_VALUE.PWM_EXT_SYNC PARAM_VALUE.PWM_EXT_SYNC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PWM_EXT_SYNC}] ${MODELPARAM_VALUE.PWM_EXT_SYNC} +} + +proc update_MODELPARAM_VALUE.EXT_ASYNC_SYNC { MODELPARAM_VALUE.EXT_ASYNC_SYNC PARAM_VALUE.EXT_ASYNC_SYNC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.EXT_ASYNC_SYNC}] ${MODELPARAM_VALUE.EXT_ASYNC_SYNC} +} + +proc update_MODELPARAM_VALUE.PULSE_0_WIDTH { MODELPARAM_VALUE.PULSE_0_WIDTH PARAM_VALUE.PULSE_0_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_0_WIDTH}] ${MODELPARAM_VALUE.PULSE_0_WIDTH} +} + +proc update_MODELPARAM_VALUE.PULSE_1_WIDTH { MODELPARAM_VALUE.PULSE_1_WIDTH PARAM_VALUE.PULSE_1_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_1_WIDTH}] ${MODELPARAM_VALUE.PULSE_1_WIDTH} +} + +proc update_MODELPARAM_VALUE.PULSE_2_WIDTH { MODELPARAM_VALUE.PULSE_2_WIDTH PARAM_VALUE.PULSE_2_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_2_WIDTH}] ${MODELPARAM_VALUE.PULSE_2_WIDTH} +} + +proc update_MODELPARAM_VALUE.PULSE_3_WIDTH { MODELPARAM_VALUE.PULSE_3_WIDTH PARAM_VALUE.PULSE_3_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_3_WIDTH}] ${MODELPARAM_VALUE.PULSE_3_WIDTH} +} + +proc update_MODELPARAM_VALUE.PULSE_4_WIDTH { MODELPARAM_VALUE.PULSE_4_WIDTH PARAM_VALUE.PULSE_4_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_4_WIDTH}] ${MODELPARAM_VALUE.PULSE_4_WIDTH} +} + +proc update_MODELPARAM_VALUE.PULSE_5_WIDTH { MODELPARAM_VALUE.PULSE_5_WIDTH PARAM_VALUE.PULSE_5_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_5_WIDTH}] ${MODELPARAM_VALUE.PULSE_5_WIDTH} +} + +proc update_MODELPARAM_VALUE.PULSE_6_WIDTH { MODELPARAM_VALUE.PULSE_6_WIDTH PARAM_VALUE.PULSE_6_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_6_WIDTH}] ${MODELPARAM_VALUE.PULSE_6_WIDTH} +} + +proc update_MODELPARAM_VALUE.PULSE_7_WIDTH { MODELPARAM_VALUE.PULSE_7_WIDTH PARAM_VALUE.PULSE_7_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_7_WIDTH}] ${MODELPARAM_VALUE.PULSE_7_WIDTH} +} + +proc update_MODELPARAM_VALUE.PULSE_8_WIDTH { MODELPARAM_VALUE.PULSE_8_WIDTH PARAM_VALUE.PULSE_8_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_8_WIDTH}] ${MODELPARAM_VALUE.PULSE_8_WIDTH} +} + +proc update_MODELPARAM_VALUE.PULSE_9_WIDTH { MODELPARAM_VALUE.PULSE_9_WIDTH PARAM_VALUE.PULSE_9_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_9_WIDTH}] ${MODELPARAM_VALUE.PULSE_9_WIDTH} +} + +proc update_MODELPARAM_VALUE.PULSE_10_WIDTH { MODELPARAM_VALUE.PULSE_10_WIDTH PARAM_VALUE.PULSE_10_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_10_WIDTH}] ${MODELPARAM_VALUE.PULSE_10_WIDTH} +} + +proc update_MODELPARAM_VALUE.PULSE_11_WIDTH { MODELPARAM_VALUE.PULSE_11_WIDTH PARAM_VALUE.PULSE_11_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_11_WIDTH}] ${MODELPARAM_VALUE.PULSE_11_WIDTH} +} + +proc update_MODELPARAM_VALUE.PULSE_12_WIDTH { MODELPARAM_VALUE.PULSE_12_WIDTH PARAM_VALUE.PULSE_12_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_12_WIDTH}] ${MODELPARAM_VALUE.PULSE_12_WIDTH} +} + +proc update_MODELPARAM_VALUE.PULSE_13_WIDTH { MODELPARAM_VALUE.PULSE_13_WIDTH PARAM_VALUE.PULSE_13_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_13_WIDTH}] ${MODELPARAM_VALUE.PULSE_13_WIDTH} +} + +proc update_MODELPARAM_VALUE.PULSE_14_WIDTH { MODELPARAM_VALUE.PULSE_14_WIDTH PARAM_VALUE.PULSE_14_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_14_WIDTH}] ${MODELPARAM_VALUE.PULSE_14_WIDTH} +} + +proc update_MODELPARAM_VALUE.PULSE_15_WIDTH { MODELPARAM_VALUE.PULSE_15_WIDTH PARAM_VALUE.PULSE_15_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_15_WIDTH}] ${MODELPARAM_VALUE.PULSE_15_WIDTH} +} + +proc update_MODELPARAM_VALUE.PULSE_0_PERIOD { MODELPARAM_VALUE.PULSE_0_PERIOD PARAM_VALUE.PULSE_0_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_0_PERIOD}] ${MODELPARAM_VALUE.PULSE_0_PERIOD} +} + +proc update_MODELPARAM_VALUE.PULSE_1_PERIOD { MODELPARAM_VALUE.PULSE_1_PERIOD PARAM_VALUE.PULSE_1_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_1_PERIOD}] ${MODELPARAM_VALUE.PULSE_1_PERIOD} +} + +proc update_MODELPARAM_VALUE.PULSE_2_PERIOD { MODELPARAM_VALUE.PULSE_2_PERIOD PARAM_VALUE.PULSE_2_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_2_PERIOD}] ${MODELPARAM_VALUE.PULSE_2_PERIOD} +} + +proc update_MODELPARAM_VALUE.PULSE_3_PERIOD { MODELPARAM_VALUE.PULSE_3_PERIOD PARAM_VALUE.PULSE_3_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_3_PERIOD}] ${MODELPARAM_VALUE.PULSE_3_PERIOD} +} + +proc update_MODELPARAM_VALUE.PULSE_4_PERIOD { MODELPARAM_VALUE.PULSE_4_PERIOD PARAM_VALUE.PULSE_4_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_4_PERIOD}] ${MODELPARAM_VALUE.PULSE_4_PERIOD} +} + +proc update_MODELPARAM_VALUE.PULSE_5_PERIOD { MODELPARAM_VALUE.PULSE_5_PERIOD PARAM_VALUE.PULSE_5_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_5_PERIOD}] ${MODELPARAM_VALUE.PULSE_5_PERIOD} +} + +proc update_MODELPARAM_VALUE.PULSE_6_PERIOD { MODELPARAM_VALUE.PULSE_6_PERIOD PARAM_VALUE.PULSE_6_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_6_PERIOD}] ${MODELPARAM_VALUE.PULSE_6_PERIOD} +} + +proc update_MODELPARAM_VALUE.PULSE_7_PERIOD { MODELPARAM_VALUE.PULSE_7_PERIOD PARAM_VALUE.PULSE_7_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_7_PERIOD}] ${MODELPARAM_VALUE.PULSE_7_PERIOD} +} + +proc update_MODELPARAM_VALUE.PULSE_8_PERIOD { MODELPARAM_VALUE.PULSE_8_PERIOD PARAM_VALUE.PULSE_8_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_8_PERIOD}] ${MODELPARAM_VALUE.PULSE_8_PERIOD} +} + +proc update_MODELPARAM_VALUE.PULSE_9_PERIOD { MODELPARAM_VALUE.PULSE_9_PERIOD PARAM_VALUE.PULSE_9_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_9_PERIOD}] ${MODELPARAM_VALUE.PULSE_9_PERIOD} +} + +proc update_MODELPARAM_VALUE.PULSE_10_PERIOD { MODELPARAM_VALUE.PULSE_10_PERIOD PARAM_VALUE.PULSE_10_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_10_PERIOD}] ${MODELPARAM_VALUE.PULSE_10_PERIOD} +} + +proc update_MODELPARAM_VALUE.PULSE_11_PERIOD { MODELPARAM_VALUE.PULSE_11_PERIOD PARAM_VALUE.PULSE_11_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_11_PERIOD}] ${MODELPARAM_VALUE.PULSE_11_PERIOD} +} + +proc update_MODELPARAM_VALUE.PULSE_12_PERIOD { MODELPARAM_VALUE.PULSE_12_PERIOD PARAM_VALUE.PULSE_12_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_12_PERIOD}] ${MODELPARAM_VALUE.PULSE_12_PERIOD} +} + +proc update_MODELPARAM_VALUE.PULSE_13_PERIOD { MODELPARAM_VALUE.PULSE_13_PERIOD PARAM_VALUE.PULSE_13_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_13_PERIOD}] ${MODELPARAM_VALUE.PULSE_13_PERIOD} +} + +proc update_MODELPARAM_VALUE.PULSE_14_PERIOD { MODELPARAM_VALUE.PULSE_14_PERIOD PARAM_VALUE.PULSE_14_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_14_PERIOD}] ${MODELPARAM_VALUE.PULSE_14_PERIOD} +} + +proc update_MODELPARAM_VALUE.PULSE_15_PERIOD { MODELPARAM_VALUE.PULSE_15_PERIOD PARAM_VALUE.PULSE_15_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_15_PERIOD}] ${MODELPARAM_VALUE.PULSE_15_PERIOD} +} + +proc update_MODELPARAM_VALUE.PULSE_0_OFFSET { MODELPARAM_VALUE.PULSE_0_OFFSET PARAM_VALUE.PULSE_0_OFFSET } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_0_OFFSET}] ${MODELPARAM_VALUE.PULSE_0_OFFSET} +} + +proc update_MODELPARAM_VALUE.PULSE_1_OFFSET { MODELPARAM_VALUE.PULSE_1_OFFSET PARAM_VALUE.PULSE_1_OFFSET } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_1_OFFSET}] ${MODELPARAM_VALUE.PULSE_1_OFFSET} +} + +proc update_MODELPARAM_VALUE.PULSE_2_OFFSET { MODELPARAM_VALUE.PULSE_2_OFFSET PARAM_VALUE.PULSE_2_OFFSET } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_2_OFFSET}] ${MODELPARAM_VALUE.PULSE_2_OFFSET} +} + +proc update_MODELPARAM_VALUE.PULSE_3_OFFSET { MODELPARAM_VALUE.PULSE_3_OFFSET PARAM_VALUE.PULSE_3_OFFSET } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_3_OFFSET}] ${MODELPARAM_VALUE.PULSE_3_OFFSET} +} + +proc update_MODELPARAM_VALUE.PULSE_4_OFFSET { MODELPARAM_VALUE.PULSE_4_OFFSET PARAM_VALUE.PULSE_4_OFFSET } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_4_OFFSET}] ${MODELPARAM_VALUE.PULSE_4_OFFSET} +} + +proc update_MODELPARAM_VALUE.PULSE_5_OFFSET { MODELPARAM_VALUE.PULSE_5_OFFSET PARAM_VALUE.PULSE_5_OFFSET } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_5_OFFSET}] ${MODELPARAM_VALUE.PULSE_5_OFFSET} +} + +proc update_MODELPARAM_VALUE.PULSE_6_OFFSET { MODELPARAM_VALUE.PULSE_6_OFFSET PARAM_VALUE.PULSE_6_OFFSET } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_6_OFFSET}] ${MODELPARAM_VALUE.PULSE_6_OFFSET} +} + +proc update_MODELPARAM_VALUE.PULSE_7_OFFSET { MODELPARAM_VALUE.PULSE_7_OFFSET PARAM_VALUE.PULSE_7_OFFSET } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_7_OFFSET}] ${MODELPARAM_VALUE.PULSE_7_OFFSET} +} + +proc update_MODELPARAM_VALUE.PULSE_8_OFFSET { MODELPARAM_VALUE.PULSE_8_OFFSET PARAM_VALUE.PULSE_8_OFFSET } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_8_OFFSET}] ${MODELPARAM_VALUE.PULSE_8_OFFSET} +} + +proc update_MODELPARAM_VALUE.PULSE_9_OFFSET { MODELPARAM_VALUE.PULSE_9_OFFSET PARAM_VALUE.PULSE_9_OFFSET } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_9_OFFSET}] ${MODELPARAM_VALUE.PULSE_9_OFFSET} +} + +proc update_MODELPARAM_VALUE.PULSE_10_OFFSET { MODELPARAM_VALUE.PULSE_10_OFFSET PARAM_VALUE.PULSE_10_OFFSET } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_10_OFFSET}] ${MODELPARAM_VALUE.PULSE_10_OFFSET} +} + +proc update_MODELPARAM_VALUE.PULSE_11_OFFSET { MODELPARAM_VALUE.PULSE_11_OFFSET PARAM_VALUE.PULSE_11_OFFSET } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_11_OFFSET}] ${MODELPARAM_VALUE.PULSE_11_OFFSET} +} + +proc update_MODELPARAM_VALUE.PULSE_12_OFFSET { MODELPARAM_VALUE.PULSE_12_OFFSET PARAM_VALUE.PULSE_12_OFFSET } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_12_OFFSET}] ${MODELPARAM_VALUE.PULSE_12_OFFSET} +} + +proc update_MODELPARAM_VALUE.PULSE_13_OFFSET { MODELPARAM_VALUE.PULSE_13_OFFSET PARAM_VALUE.PULSE_13_OFFSET } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_13_OFFSET}] ${MODELPARAM_VALUE.PULSE_13_OFFSET} +} + +proc update_MODELPARAM_VALUE.PULSE_14_OFFSET { MODELPARAM_VALUE.PULSE_14_OFFSET PARAM_VALUE.PULSE_14_OFFSET } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_14_OFFSET}] ${MODELPARAM_VALUE.PULSE_14_OFFSET} +} + +proc update_MODELPARAM_VALUE.PULSE_15_OFFSET { MODELPARAM_VALUE.PULSE_15_OFFSET PARAM_VALUE.PULSE_15_OFFSET } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_15_OFFSET}] ${MODELPARAM_VALUE.PULSE_15_OFFSET} +} + diff --git a/adi_library/axi_rd_wr_combiner/Makefile b/adi_library/axi_rd_wr_combiner/Makefile new file mode 100644 index 00000000..4cd4112f --- /dev/null +++ b/adi_library/axi_rd_wr_combiner/Makefile @@ -0,0 +1,13 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_rd_wr_combiner + +GENERIC_DEPS += axi_rd_wr_combiner.v + +XILINX_DEPS += axi_rd_wr_combiner_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_rd_wr_combiner/axi_rd_wr_combiner.v b/adi_library/axi_rd_wr_combiner/axi_rd_wr_combiner.v new file mode 100644 index 00000000..e541891a --- /dev/null +++ b/adi_library/axi_rd_wr_combiner/axi_rd_wr_combiner.v @@ -0,0 +1,159 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +/* + * Helper module to combine a read-only and a write-only AXI interface into a + * single read-write AXI interface. Only supports AXI3 at the moment. + */ + +`timescale 1ns/100ps + +module axi_rd_wr_combiner ( + input clk, + + // Master write address + output [31:0] m_axi_awaddr, + output [ 3:0] m_axi_awlen, + output [ 2:0] m_axi_awsize, + output [ 1:0] m_axi_awburst, + output [ 2:0] m_axi_awprot, + output [ 3:0] m_axi_awcache, + output m_axi_awvalid, + input m_axi_awready, + + // Master write data + output [63:0] m_axi_wdata, + output [ 7:0] m_axi_wstrb, + input m_axi_wready, + output m_axi_wvalid, + output m_axi_wlast, + + // Master write response + input m_axi_bvalid, + input [ 1:0] m_axi_bresp, + output m_axi_bready, + + // Master read address + output m_axi_arvalid, + output [31:0] m_axi_araddr, + output [ 3:0] m_axi_arlen, + output [ 2:0] m_axi_arsize, + output [ 1:0] m_axi_arburst, + output [ 3:0] m_axi_arcache, + output [ 2:0] m_axi_arprot, + input m_axi_arready, + + // Master read response + data + input m_axi_rvalid, + input [ 1:0] m_axi_rresp, + input [63:0] m_axi_rdata, + input m_axi_rlast, + output m_axi_rready, + + // Slave write address + input [31:0] s_wr_axi_awaddr, + input [ 3:0] s_wr_axi_awlen, + input [ 2:0] s_wr_axi_awsize, + input [ 1:0] s_wr_axi_awburst, + input [ 2:0] s_wr_axi_awprot, + input [ 3:0] s_wr_axi_awcache, + input s_wr_axi_awvalid, + output s_wr_axi_awready, + + // Salve write data + input [63:0] s_wr_axi_wdata, + input [ 7:0] s_wr_axi_wstrb, + output s_wr_axi_wready, + input s_wr_axi_wvalid, + input s_wr_axi_wlast, + + // Slave write response + output s_wr_axi_bvalid, + output [ 1:0] s_wr_axi_bresp, + input s_wr_axi_bready, + + // Slave read address + input s_rd_axi_arvalid, + input [31:0] s_rd_axi_araddr, + input [ 3:0] s_rd_axi_arlen, + input [ 2:0] s_rd_axi_arsize, + input [ 1:0] s_rd_axi_arburst, + input [ 3:0] s_rd_axi_arcache, + input [ 2:0] s_rd_axi_arprot, + output s_rd_axi_arready, + + // Slave read response + data + output s_rd_axi_rvalid, + output [ 1:0] s_rd_axi_rresp, + output [63:0] s_rd_axi_rdata, + output s_rd_axi_rlast, + input s_rd_axi_rready +); + + assign m_axi_awaddr = s_wr_axi_awaddr; + assign m_axi_awlen = s_wr_axi_awlen; + assign m_axi_awsize = s_wr_axi_awsize; + assign m_axi_awburst = s_wr_axi_awburst; + assign m_axi_awprot = s_wr_axi_awprot; + assign m_axi_awcache = s_wr_axi_awcache; + assign m_axi_awvalid = s_wr_axi_awvalid; + assign s_wr_axi_awready = m_axi_awready; + + assign m_axi_wdata = s_wr_axi_wdata; + assign m_axi_wstrb = s_wr_axi_wstrb; + assign s_wr_axi_wready = m_axi_wready; + assign m_axi_wvalid = s_wr_axi_wvalid; + assign m_axi_wlast = s_wr_axi_wlast; + + assign s_wr_axi_bvalid = m_axi_bvalid; + assign s_wr_axi_bresp = m_axi_bresp; + assign m_axi_bready = s_wr_axi_bready; + + assign m_axi_arvalid = s_rd_axi_arvalid; + assign m_axi_araddr = s_rd_axi_araddr; + assign m_axi_arlen = s_rd_axi_arlen; + assign m_axi_arsize = s_rd_axi_arsize; + assign m_axi_arburst = s_rd_axi_arburst; + assign m_axi_arcache = s_rd_axi_arcache; + assign m_axi_arprot = s_rd_axi_arprot; + assign s_rd_axi_arready = m_axi_arready; + + assign s_rd_axi_rvalid = m_axi_rvalid; + assign s_rd_axi_rresp = m_axi_rresp; + assign s_rd_axi_rdata = m_axi_rdata; + assign s_rd_axi_rlast = m_axi_rlast; + assign m_axi_rready = s_rd_axi_rready; + +endmodule diff --git a/adi_library/axi_rd_wr_combiner/axi_rd_wr_combiner.xpr b/adi_library/axi_rd_wr_combiner/axi_rd_wr_combiner.xpr new file mode 100644 index 00000000..2097a8ba --- /dev/null +++ b/adi_library/axi_rd_wr_combiner/axi_rd_wr_combiner.xpr @@ -0,0 +1,399 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_rd_wr_combiner/axi_rd_wr_combiner_ip.tcl b/adi_library/axi_rd_wr_combiner/axi_rd_wr_combiner_ip.tcl new file mode 100644 index 00000000..786a4252 --- /dev/null +++ b/adi_library/axi_rd_wr_combiner/axi_rd_wr_combiner_ip.tcl @@ -0,0 +1,22 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_rd_wr_combiner +adi_ip_files axi_rd_wr_combiner [list \ + "axi_rd_wr_combiner.v" \ + ] + +adi_ip_properties_lite axi_rd_wr_combiner +adi_ip_infer_mm_interfaces axi_rd_wr_combiner + +# Dummy clock to helper with clock rate and clock domain propagation to the +# interface +adi_add_bus_clock "clk" "m_axi:s_wr_axi:s_rd_axi" + +ipx::save_core [ipx::current_core] diff --git a/adi_library/axi_rd_wr_combiner/component.xml b/adi_library/axi_rd_wr_combiner/component.xml new file mode 100644 index 00000000..f7184dce --- /dev/null +++ b/adi_library/axi_rd_wr_combiner/component.xml @@ -0,0 +1,1699 @@ + + + analog.com + user + axi_rd_wr_combiner + 1.0 + + + m_axi + + + + + + + + + AWADDR + + + m_axi_awaddr + + + + + AWLEN + + + m_axi_awlen + + + + + AWSIZE + + + m_axi_awsize + + + + + AWBURST + + + m_axi_awburst + + + + + AWCACHE + + + m_axi_awcache + + + + + AWPROT + + + m_axi_awprot + + + + + AWVALID + + + m_axi_awvalid + + + + + AWREADY + + + m_axi_awready + + + + + WDATA + + + m_axi_wdata + + + + + WSTRB + + + m_axi_wstrb + + + + + WLAST + + + m_axi_wlast + + + + + WVALID + + + m_axi_wvalid + + + + + WREADY + + + m_axi_wready + + + + + BRESP + + + m_axi_bresp + + + + + BVALID + + + m_axi_bvalid + + + + + BREADY + + + m_axi_bready + + + + + ARADDR + + + m_axi_araddr + + + + + ARLEN + + + m_axi_arlen + + + + + ARSIZE + + + m_axi_arsize + + + + + ARBURST + + + m_axi_arburst + + + + + ARCACHE + + + m_axi_arcache + + + + + ARPROT + + + m_axi_arprot + + + + + ARVALID + + + m_axi_arvalid + + + + + ARREADY + + + m_axi_arready + + + + + RDATA + + + m_axi_rdata + + + + + RRESP + + + m_axi_rresp + + + + + RLAST + + + m_axi_rlast + + + + + RVALID + + + m_axi_rvalid + + + + + RREADY + + + m_axi_rready + + + + + + s_rd_axi + + + + + + + + + ARADDR + + + s_rd_axi_araddr + + + + + ARLEN + + + s_rd_axi_arlen + + + + + ARSIZE + + + s_rd_axi_arsize + + + + + ARBURST + + + s_rd_axi_arburst + + + + + ARCACHE + + + s_rd_axi_arcache + + + + + ARPROT + + + s_rd_axi_arprot + + + + + ARVALID + + + s_rd_axi_arvalid + + + + + ARREADY + + + s_rd_axi_arready + + + + + RDATA + + + s_rd_axi_rdata + + + + + RRESP + + + s_rd_axi_rresp + + + + + RLAST + + + s_rd_axi_rlast + + + + + RVALID + + + s_rd_axi_rvalid + + + + + RREADY + + + s_rd_axi_rready + + + + + + s_wr_axi + + + + + + + + + AWADDR + + + s_wr_axi_awaddr + + + + + AWLEN + + + s_wr_axi_awlen + + + + + AWSIZE + + + s_wr_axi_awsize + + + + + AWBURST + + + s_wr_axi_awburst + + + + + AWCACHE + + + s_wr_axi_awcache + + + + + AWPROT + + + s_wr_axi_awprot + + + + + AWVALID + + + s_wr_axi_awvalid + + + + + AWREADY + + + s_wr_axi_awready + + + + + WDATA + + + s_wr_axi_wdata + + + + + WSTRB + + + s_wr_axi_wstrb + + + + + WLAST + + + s_wr_axi_wlast + + + + + WVALID + + + s_wr_axi_wvalid + + + + + WREADY + + + s_wr_axi_wready + + + + + BRESP + + + s_wr_axi_bresp + + + + + BVALID + + + s_wr_axi_bvalid + + + + + BREADY + + + s_wr_axi_bready + + + + + + clk + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_BUSIF + m_axi:s_rd_axi:s_wr_axi + + + + + m_axi_s_wr_axi_s_rd_axi_signal_clock + m_axi_s_wr_axi_s_rd_axi_signal_clock + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_BUSIF + m_axi:s_wr_axi:s_rd_axi + + + + + + + m_axi + m_axi + 0x100000000 + 64 + + + + + s_rd_axi + s_rd_axi + + reg0 + reg0 + 0x0 + 0x100000000 + 64 + register + + + + s_wr_axi + s_wr_axi + + reg0 + reg0 + 0x0 + 0x100000000 + 64 + register + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_rd_wr_combiner + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + e6333660 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_rd_wr_combiner + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + e6333660 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f92e9879 + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_awaddr + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_awlen + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_awsize + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_awburst + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_awprot + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_awcache + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_awvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_awready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_wdata + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_wstrb + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_wready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_wvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_wlast + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_bvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_bresp + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_bready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_araddr + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arlen + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arsize + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arburst + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arcache + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arprot + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axi_arready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_rvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_rresp + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_rdata + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_rlast + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axi_rready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_wr_axi_awaddr + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_wr_axi_awlen + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_wr_axi_awsize + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_wr_axi_awburst + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_wr_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_wr_axi_awcache + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 3 + + + + + s_wr_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_wr_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_wr_axi_wdata + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_wr_axi_wstrb + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_wr_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_wr_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_wr_axi_wlast + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_wr_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_wr_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_wr_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_rd_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_rd_axi_araddr + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_rd_axi_arlen + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_rd_axi_arsize + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_rd_axi_arburst + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_rd_axi_arcache + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 3 + + + + + s_rd_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_rd_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_rd_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_rd_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_rd_axi_rdata + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_rd_axi_rlast + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_rd_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + + xilinx_anylanguagesynthesis_view_fileset + + axi_rd_wr_combiner.v + verilogSource + CHECKSUM_e6333660 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + axi_rd_wr_combiner.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_rd_wr_combiner_v1_0.tcl + tclSource + CHECKSUM_f92e9879 + XGUI_VERSION_2 + + + + axi_rd_wr_combiner_v1_0 + + + Component_Name + axi_rd_wr_combiner_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_rd_wr_combiner_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:48:48Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_rd_wr_combiner/xgui/axi_rd_wr_combiner_v1_0.tcl b/adi_library/axi_rd_wr_combiner/xgui/axi_rd_wr_combiner_v1_0.tcl new file mode 100644 index 00000000..0db18e9a --- /dev/null +++ b/adi_library/axi_rd_wr_combiner/xgui/axi_rd_wr_combiner_v1_0.tcl @@ -0,0 +1,10 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + + diff --git a/adi_library/axi_spdif_rx/Makefile b/adi_library/axi_spdif_rx/Makefile new file mode 100644 index 00000000..26f53b51 --- /dev/null +++ b/adi_library/axi_spdif_rx/Makefile @@ -0,0 +1,21 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_spdif_rx + +GENERIC_DEPS += ../common/axi_ctrlif.vhd +GENERIC_DEPS += ../common/axi_streaming_dma_rx_fifo.vhd +GENERIC_DEPS += ../common/dma_fifo.vhd +GENERIC_DEPS += ../common/pl330_dma_fifo.vhd +GENERIC_DEPS += axi_spdif_rx.vhd +GENERIC_DEPS += rx_decode.vhd +GENERIC_DEPS += rx_package.vhd +GENERIC_DEPS += rx_phase_det.vhd +GENERIC_DEPS += rx_status_reg.vhd + +XILINX_DEPS += axi_spdif_rx_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_spdif_rx/axi_spdif_rx.vhd b/adi_library/axi_spdif_rx/axi_spdif_rx.vhd new file mode 100644 index 00000000..88179897 --- /dev/null +++ b/adi_library/axi_spdif_rx/axi_spdif_rx.vhd @@ -0,0 +1,433 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +-- +-- In this HDL repository, there are many different and unique modules, consisting +-- of various HDL (Verilog or VHDL) components. The individual modules are +-- developed independently, and may be accompanied by separate and unique license +-- terms. +-- +-- The user should read each of these license terms, and understand the +-- freedoms and responsibilities that he or she has by using this source/core. +-- +-- This core is distributed in the hope that it will be useful, but WITHOUT ANY +-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +-- A PARTICULAR PURPOSE. +-- +-- Redistribution and use of source or resulting binaries, with or without modification +-- of this file, are permitted under one of the following two license terms: +-- +-- 1. The GNU General Public License version 2 as published by the +-- Free Software Foundation, which can be found in the top level directory +-- of this repository (LICENSE_GPL2), and also online at: +-- +-- +-- OR +-- +-- 2. An ADI specific BSD license, which can be found in the top level directory +-- of this repository (LICENSE_ADIBSD), and also on-line at: +-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +-- This will allow to generate bit files and not release the source code, +-- as long as it attaches to an ADI device. +-- +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +library work; +use work.rx_package.all; +use work.axi_ctrlif; +use work.axi_streaming_dma_rx_fifo; +use work.pl330_dma_fifo; + +entity axi_spdif_rx is + generic + ( + C_S_AXI_DATA_WIDTH : integer := 32; + C_S_AXI_ADDR_WIDTH : integer := 32; + C_DMA_TYPE : integer := 0 + ); + port + ( + --SPDIF ports + rx_int_o : out std_logic; + spdif_rx_i : in std_logic; + spdif_rx_i_dbg : out std_logic; + + --AXI Lite inter face + s_axi_aclk : in std_logic; + s_axi_aresetn : in std_logic; + s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_awvalid : in std_logic; + s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + s_axi_wvalid : in std_logic; + s_axi_bready : in std_logic; + s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_arvalid : in std_logic; + s_axi_rready : in std_logic; + s_axi_arready : out std_logic; + s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_rresp : out std_logic_vector(1 downto 0); + s_axi_rvalid : out std_logic; + s_axi_wready : out std_logic; + s_axi_bresp : out std_logic_vector(1 downto 0); + s_axi_bvalid : out std_logic; + s_axi_awready : out std_logic; + s_axi_awprot : in std_logic_vector(2 downto 0); + s_axi_arprot : in std_logic_vector(2 downto 0); + + + --AXI STREAM interface + m_axis_aclk : in std_logic; + m_axis_tready : in std_logic; + m_axis_tdata : out std_logic_vector(31 downto 0); + m_axis_tlast : out std_logic; + m_axis_tvalid : out std_logic; + m_axis_tkeep : out std_logic_vector(3 downto 0); + + --PL330 DMA interface + dma_req_aclk : in std_logic; + dma_req_rstn : in std_logic; + dma_req_davalid : in std_logic; + dma_req_datype : in std_logic_vector(1 downto 0); + dma_req_daready : out std_logic; + dma_req_drvalid : out std_logic; + dma_req_drtype : out std_logic_vector(1 downto 0); + dma_req_drlast : out std_logic; + dma_req_drready : in std_logic + ); +end entity axi_spdif_rx; + +------------------------------------------------------------------------------ +-- Architecture section +------------------------------------------------------------------------------ + +architecture IMP of axi_spdif_rx is + + signal wr_data : std_logic_vector(31 downto 0); + signal rd_data : std_logic_vector(31 downto 0); + signal wr_addr : integer range 0 to 3; + signal rd_addr : integer range 0 to 3; + signal wr_stb : std_logic; + signal rd_ack : std_logic; + + signal version_reg : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal control_reg : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + signal chstatus_reg : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + + signal sampled_data : std_logic_vector(31 downto 0); + + signal sample_ack : std_logic; + signal sample_din : std_logic_vector(31 downto 0); + signal sample_wr : std_logic; + + signal conf_rxen : std_logic; + signal conf_sample : std_logic; + signal conf_chas : std_logic; + signal conf_valid : std_logic; + signal conf_blken : std_logic; + signal conf_valen : std_logic; + signal conf_useren : std_logic; + signal conf_staten : std_logic; + signal conf_paren : std_logic; + signal config_rd : std_logic; + signal config_wr : std_logic; + + signal conf_mode : std_logic_vector(3 downto 0); + signal conf_bits : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0); + signal conf_dout : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0); + + signal fifo_data_out : std_logic_vector(31 downto 0); + signal fifo_data_ack : std_logic; + signal fifo_reset : std_logic; + signal tx_fifo_stb : std_logic; + + signal enable : boolean; + + signal lock : std_logic; + + signal rx_data : std_logic; + signal rx_data_en : std_logic; + signal rx_block_start : std_logic; + signal rx_channel_a : std_logic; + signal rx_error : std_logic; + signal lock_evt : std_logic; + signal ud_a_en : std_logic; + signal ud_b_en : std_logic; + signal cs_a_en : std_logic; + signal cs_b_en : std_logic; + signal rx_frame_start : std_logic; + + signal istat_lsbf : std_logic; + signal istat_hsbf : std_logic; + signal istat_paritya : std_logic; + signal istat_parityb : std_logic; + + signal sbuf_wr_adr : std_logic_vector(C_S_AXI_ADDR_WIDTH - 2 downto 0); + +begin + + ------------------------------------------------------------------------------- + -- Version Register + ------------------------------------------------------------------------------- + version_reg(31 downto 20) <= (others => '0'); + version_reg(19 downto 16) <= "0001"; + version_reg(15 downto 12) <= (others => '0'); + version_reg(11 downto 5) <= std_logic_vector(to_unsigned(C_S_AXI_ADDR_WIDTH,7)); + version_reg(4) <= '1'; + version_reg(3 downto 0) <= "0001"; + -------------------------------------------------------------------------------- + + -------------------------------------------------------------------------------- + -- Control Register + -------------------------------------------------------------------------------- + conf_mode(3 downto 0) <= control_reg(23 downto 20); + conf_paren <= control_reg(19); + conf_staten <= control_reg(18); + conf_useren <= control_reg(17); + conf_valen <= control_reg(16); + conf_blken <= control_reg(5); + conf_valid <= control_reg(4); + conf_chas <= control_reg(3); + conf_sample <= control_reg(1); + conf_rxen <= control_reg(0); + -------------------------------------------------------------------------------- + + fifo_reset <= not conf_sample; + enable <= conf_sample = '1'; + + streaming_dma_gen: if C_DMA_TYPE = 0 generate + fifo: entity axi_streaming_dma_rx_fifo + generic map ( + RAM_ADDR_WIDTH => 3, + FIFO_DWIDTH => 32 + ) + port map ( + clk => s_axi_aclk, + resetn => s_axi_aresetn, + fifo_reset => fifo_reset, + + enable => enable, + period_len => 11, + + m_axis_aclk => m_axis_aclk, + m_axis_tready => m_axis_tready, + m_axis_tdata => m_axis_tdata, + m_axis_tlast => m_axis_tlast, + m_axis_tvalid => m_axis_tvalid, + m_axis_tkeep => m_axis_tkeep, + + -- Write port + in_stb => sample_wr, + in_ack => sample_ack, + in_data => sample_din + ); + end generate; + + no_streaming_dma_gen: if C_DMA_TYPE /= 0 generate + m_axis_tvalid <= '0'; + m_axis_tlast <= '0'; + m_axis_tkeep <= "0000"; + m_axis_tdata <= (others => '0'); + end generate; + + pl330_dma_gen: if C_DMA_TYPE = 1 generate + tx_fifo_stb <= '1' when wr_addr = 3 and wr_stb = '1' else '0'; + + fifo: entity pl330_dma_fifo + generic map( + RAM_ADDR_WIDTH => 3, + FIFO_DWIDTH => 32, + FIFO_DIRECTION => 0 + ) + port map ( + clk => s_axi_aclk, + resetn => s_axi_aresetn, + fifo_reset => fifo_reset, + enable => enable, + + in_data => sample_din, + in_stb => sample_wr, + + out_ack => tx_fifo_stb, + out_data => sampled_data, + + dclk => dma_req_aclk, + dresetn => dma_req_rstn, + davalid => dma_req_davalid, + daready => dma_req_daready, + datype => dma_req_datype, + drvalid => dma_req_drvalid, + drready => dma_req_drready, + drtype => dma_req_drtype, + drlast => dma_req_drlast + ); + end generate; + + no_pl330_dma_gen: if C_DMA_TYPE /= 1 generate + dma_req_daready <= '0'; + dma_req_drvalid <= '0'; + dma_req_drtype <= (others => '0'); + dma_req_drlast <= '0'; + end generate; + + -------------------------------------------------------------------------------- + -- Status Register + -------------------------------------------------------------------------------- + STAT: rx_status_reg + generic map + ( + DATA_WIDTH => C_S_AXI_DATA_WIDTH + ) + port map + ( + up_clk => s_axi_aclk, + status_rd => rd_ack, + lock => lock, + chas => conf_chas, + rx_block_start => rx_block_start, + ch_data => rx_data, + cs_a_en => cs_a_en, + cs_b_en => cs_b_en, + status_dout => chstatus_reg + ); + -------------------------------------------------------------------------------- + + -------------------------------------------------------------------------------- + -- Phase decoder + -------------------------------------------------------------------------------- + PDET: rx_phase_det + generic map + ( + AXI_FREQ => 100 -- WishBone frequency in MHz + ) + port map + ( + up_clk => s_axi_aclk, + rxen => conf_rxen, + spdif => spdif_rx_i, + lock => lock, + lock_evt => lock_evt, + rx_data => rx_data, + rx_data_en => rx_data_en, + rx_block_start => rx_block_start, + rx_frame_start => rx_frame_start, + rx_channel_a => rx_channel_a, + rx_error => rx_error, + ud_a_en => ud_a_en, + ud_b_en => ud_b_en, + cs_a_en => cs_a_en, + cs_b_en => cs_b_en + ); + spdif_rx_i_dbg <= spdif_rx_i; + -------------------------------------------------------------------------------- + + -------------------------------------------------------------------------------- + -- Rx Decoder + -------------------------------------------------------------------------------- + FDEC: rx_decode + generic map + ( + DATA_WIDTH => C_S_AXI_DATA_WIDTH, + ADDR_WIDTH => C_S_AXI_ADDR_WIDTH + ) + port map + ( + up_clk => s_axi_aclk, + conf_rxen => conf_rxen, + conf_sample => conf_sample, + conf_valid => conf_valid, + conf_mode => conf_mode, + conf_blken => conf_blken, + conf_valen => conf_valen, + conf_useren => conf_useren, + conf_staten => conf_staten, + conf_paren => conf_paren, + lock => lock, + rx_data => rx_data, + rx_data_en => rx_data_en, + rx_block_start => rx_block_start, + rx_frame_start => rx_frame_start, + rx_channel_a => rx_channel_a, + wr_en => sample_wr, + wr_addr => sbuf_wr_adr, + wr_data => sample_din, + stat_paritya => istat_paritya, + stat_parityb => istat_parityb, + stat_lsbf => istat_lsbf, + stat_hsbf => istat_hsbf + ); + rx_int_o <= sample_wr; + + ctrlif: entity axi_ctrlif + generic map ( + C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, + C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, + C_NUM_REG => 4 + ) + port map( + s_axi_aclk => s_axi_aclk, + s_axi_aresetn => s_axi_aresetn, + s_axi_awaddr => s_axi_awaddr, + s_axi_awvalid => s_axi_awvalid, + s_axi_wdata => s_axi_wdata, + s_axi_wstrb => s_axi_wstrb, + s_axi_wvalid => s_axi_wvalid, + s_axi_bready => s_axi_bready, + s_axi_araddr => s_axi_araddr, + s_axi_arvalid => s_axi_arvalid, + s_axi_rready => s_axi_rready, + s_axi_arready => s_axi_arready, + s_axi_rdata => s_axi_rdata, + s_axi_rresp => s_axi_rresp, + s_axi_rvalid => s_axi_rvalid, + s_axi_wready => s_axi_wready, + s_axi_bresp => s_axi_bresp, + s_axi_bvalid => s_axi_bvalid, + s_axi_awready => s_axi_awready, + + rd_addr => rd_addr, + rd_data => rd_data, + rd_ack => rd_ack, + rd_stb => '1', + + wr_addr => wr_addr, + wr_data => wr_data, + wr_ack => '1', + wr_stb => wr_stb + ); + + process (s_axi_aclk) + begin + if rising_edge(s_axi_aclk) then + if s_axi_aresetn = '0' then + control_reg <= (others => '0'); + else + if wr_stb = '1' then + case wr_addr is + when 1 => control_reg <= wr_data; + when others => null; + end case; + end if; + end if; + end if; + end process; + + process (rd_addr, version_reg, control_reg, chstatus_reg, sampled_data) + begin + case rd_addr is + when 0 => rd_data <= version_reg; + when 1 => rd_data <= control_reg; + when 2 => rd_data <= chstatus_reg; + when 3 => rd_data <= sampled_data; + when others => rd_data <= (others => '0'); + end case; + end process; + +end IMP; diff --git a/adi_library/axi_spdif_rx/axi_spdif_rx.xpr b/adi_library/axi_spdif_rx/axi_spdif_rx.xpr new file mode 100644 index 00000000..1844a6ca --- /dev/null +++ b/adi_library/axi_spdif_rx/axi_spdif_rx.xpr @@ -0,0 +1,446 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_spdif_rx/axi_spdif_rx_ip.tcl b/adi_library/axi_spdif_rx/axi_spdif_rx_ip.tcl new file mode 100644 index 00000000..277f0a14 --- /dev/null +++ b/adi_library/axi_spdif_rx/axi_spdif_rx_ip.tcl @@ -0,0 +1,55 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_spdif_rx +adi_ip_files axi_spdif_rx [list \ + "$ad_hdl_dir/library/common/axi_ctrlif.vhd" \ + "$ad_hdl_dir/library/common/axi_streaming_dma_rx_fifo.vhd" \ + "$ad_hdl_dir/library/common/pl330_dma_fifo.vhd" \ + "$ad_hdl_dir/library/common/dma_fifo.vhd" \ + "rx_phase_det.vhd" \ + "rx_package.vhd" \ + "rx_decode.vhd" \ + "rx_status_reg.vhd" \ + "axi_spdif_rx.vhd" ] + +adi_ip_properties axi_spdif_rx +adi_ip_infer_streaming_interfaces axi_spdif_rx + +adi_add_bus "dma_ack" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"dma_req_davalid" "TVALID"} \ + {"dma_req_daready" "TREADY"} \ + {"dma_req_datype" "TUSER"} ] +adi_add_bus "dma_req" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"dma_req_drvalid" "TVALID"} \ + {"dma_req_drready" "TREADY"} \ + {"dma_req_drtype" "TUSER"} \ + {"dma_req_drlast" "TLAST"} ] + +# Clock and reset are for both dma_req and dma_ack +adi_add_bus_clock "dma_req_aclk" "dma_req:dma_ack" "dma_req_rstn" + +adi_set_bus_dependency "m_axis" "m_axis" \ + "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 0)" + +adi_set_bus_dependency "dma_ack" "dma_req_da" \ + "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)" +adi_set_bus_dependency "dma_req" "dma_req_dr" \ + "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)" +adi_set_ports_dependency "dma_req_aclk" \ + "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)" +adi_set_ports_dependency "dma_req_rstn" \ + "(spirit:decode(id('MODELPARAM_VALUE.C_DMA_TYPE')) = 1)" + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/axi_spdif_rx/component.xml b/adi_library/axi_spdif_rx/component.xml new file mode 100644 index 00000000..d1c1c173 --- /dev/null +++ b/adi_library/axi_spdif_rx/component.xml @@ -0,0 +1,1459 @@ + + + analog.com + user + axi_spdif_rx + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + m_axis + + + + + + + TDATA + + + m_axis_tdata + + + + + TKEEP + + + m_axis_tkeep + + + + + TLAST + + + m_axis_tlast + + + + + TVALID + + + m_axis_tvalid + + + + + TREADY + + + m_axis_tready + + + + + + + true + + + + + + dma_req_aclk + + + + + + + CLK + + + dma_req_aclk + + + + + + ASSOCIATED_RESET + dma_req_rstn + + + + + m_axis_aclk + + + + + + + CLK + + + m_axis_aclk + + + + + + ASSOCIATED_BUSIF + m_axis + + + + + dma_req_rstn + + + + + + + RST + + + dma_req_rstn + + + + + + POLARITY + ACTIVE_LOW + + + + + dma_ack + + + + + + + TVALID + + + dma_req_davalid + + + + + TREADY + + + dma_req_daready + + + + + TUSER + + + dma_req_datype + + + + + + + false + + + + + + dma_req + + + + + + + TVALID + + + dma_req_drvalid + + + + + TREADY + + + dma_req_drready + + + + + TUSER + + + dma_req_drtype + + + + + TLAST + + + dma_req_drlast + + + + + + + false + + + + + + dma_req_dma_ack_signal_clock + dma_req_dma_ack_signal_clock + + + + + + + CLK + + + dma_req_aclk + + + + + + ASSOCIATED_BUSIF + dma_req:dma_ack + + + ASSOCIATED_RESET + dma_req_rstn + + + + + dma_req_dma_ack_signal_reset + dma_req_dma_ack_signal_reset + + + + + + + RST + + + dma_req_rstn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + axi_spdif_rx + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 2df62c64 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + axi_spdif_rx + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 2df62c64 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 8815501a + + + + + + + rx_int_o + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + spdif_rx_i + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + spdif_rx_i_dbg + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axis_tready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axis_tdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axis_tlast + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axis_tvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + m_axis_tkeep + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + dma_req_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dma_req_rstn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dma_req_davalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_datype + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_daready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_drvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_drtype + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_drlast + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_drready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + + + C_S_AXI_DATA_WIDTH + C S Axi Data Width + 32 + + + C_S_AXI_ADDR_WIDTH + C S Axi Addr Width + 32 + + + C_DMA_TYPE + C Dma Type + 0 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../common/axi_ctrlif.vhd + vhdlSource + + + rx_package.vhd + vhdlSource + + + ../common/dma_fifo.vhd + vhdlSource + + + ../common/axi_streaming_dma_rx_fifo.vhd + vhdlSource + + + ../common/pl330_dma_fifo.vhd + vhdlSource + + + rx_decode.vhd + vhdlSource + + + rx_phase_det.vhd + vhdlSource + + + rx_status_reg.vhd + vhdlSource + + + axi_spdif_rx.vhd + vhdlSource + CHECKSUM_9b31708f + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/axi_ctrlif.vhd + vhdlSource + + + rx_package.vhd + vhdlSource + + + ../common/dma_fifo.vhd + vhdlSource + + + ../common/axi_streaming_dma_rx_fifo.vhd + vhdlSource + + + ../common/pl330_dma_fifo.vhd + vhdlSource + + + rx_decode.vhd + vhdlSource + + + rx_phase_det.vhd + vhdlSource + + + rx_status_reg.vhd + vhdlSource + + + axi_spdif_rx.vhd + vhdlSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_spdif_rx_v1_0.tcl + tclSource + CHECKSUM_8815501a + XGUI_VERSION_2 + + + + axi_spdif_rx_v1_0 + + + C_S_AXI_DATA_WIDTH + C S Axi Data Width + 32 + + + C_S_AXI_ADDR_WIDTH + C S Axi Addr Width + 32 + + + C_DMA_TYPE + C Dma Type + 0 + + + Component_Name + axi_spdif_rx_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_spdif_rx_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:49:00Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_spdif_rx/rx_cap_reg.vhd b/adi_library/axi_spdif_rx/rx_cap_reg.vhd new file mode 100644 index 00000000..ad7c2453 --- /dev/null +++ b/adi_library/axi_spdif_rx/rx_cap_reg.vhd @@ -0,0 +1,176 @@ +---------------------------------------------------------------------- +---- ---- +---- WISHBONE SPDIF IP Core ---- +---- ---- +---- This file is part of the SPDIF project ---- +---- http://www.opencores.org/cores/spdif_interface/ ---- +---- ---- +---- Description ---- +---- SPDIF receiver channel status capture module ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.4 2004/07/19 16:58:37 gedra +-- Fixed bug. +-- +-- Revision 1.3 2004/06/27 16:16:55 gedra +-- Signal renaming and bug fix. +-- +-- Revision 1.2 2004/06/26 14:14:47 gedra +-- Converted to numeric_std and fixed a few bugs. +-- +-- Revision 1.1 2004/06/05 17:16:46 gedra +-- Channel status/user data capture register +-- +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.rx_package.all; + +entity rx_cap_reg is + port ( + clk: in std_logic; -- clock + rst: in std_logic; -- reset + --cap_ctrl_wr: in std_logic; -- control register write + --cap_ctrl_rd: in std_logic; -- control register read + --cap_data_rd: in std_logic; -- data register read + cap_reg: in std_logic_vector(31 downto 0); + cap_din: in std_logic_vector(31 downto 0); -- write data + rx_block_start: in std_logic; -- start of block signal + ch_data: in std_logic; -- channel status/user data + ud_a_en: in std_logic; -- user data ch. A enable + ud_b_en: in std_logic; -- user data ch. B enable + cs_a_en: in std_logic; -- channel status ch. A enable + cs_b_en: in std_logic; -- channel status ch. B enable + cap_dout: out std_logic_vector(31 downto 0); -- read data + cap_evt: out std_logic); -- capture event (interrupt) +end rx_cap_reg; + +architecture rtl of rx_cap_reg is + + signal cap_ctrl_bits, cap_ctrl_dout: std_logic_vector(31 downto 0); + signal cap_reg_1, cap_new : std_logic_vector(31 downto 0); + signal bitlen, cap_len : integer range 0 to 63; + signal bitpos, cur_pos : integer range 0 to 255; + signal chid, cdata, compared : std_logic; + signal d_enable : std_logic_vector(3 downto 0); + +begin + +-- Data bus or'ing + cap_dout <= cap_reg_1;-- when cap_data_rd = '1' else cap_ctrl_dout; + + chid <= cap_reg(6); + cdata <= cap_reg(7); + +-- capture data register + CDAT: process (clk, rst) + begin + if rst = '1' then + cap_reg_1 <= (others => '0'); -- + cap_new <= (others => '0'); + cur_pos <= 0; + cap_len <= 0; + cap_evt <= '0'; + compared <= '0'; + bitpos <= 0; + bitlen <= 0; + else + if rising_edge(clk) then + bitlen <= to_integer(unsigned(cap_reg(5 downto 0))); + bitpos <= to_integer(unsigned(cap_reg(15 downto 8))); + if bitlen > 0 then -- bitlen = 0 disables the capture function + -- bit counter, 0 to 191 + if rx_block_start = '1' then + cur_pos <= 0; + cap_len <= 0; + cap_new <= (others => '0'); + compared <= '0'; + elsif cs_b_en = '1' then -- ch. status #2 comes last, count then + cur_pos <= cur_pos + 1; + end if; + -- capture bits + if cur_pos >= bitpos and cap_len < bitlen then + case d_enable is + when "0001" => -- user data channel A + if cdata = '0' and chid = '0' then + cap_new(cap_len) <= ch_data; + cap_len <= cap_len + 1; + end if; + when "0010" => -- user data channel B + if cdata = '0' and chid = '1' then + cap_new(cap_len) <= ch_data; + cap_len <= cap_len + 1; + end if; + when "0100" => -- channel status ch. A + if cdata = '1' and chid = '0' then + cap_new(cap_len) <= ch_data; + cap_len <= cap_len + 1; + end if; + when "1000" => -- channel status ch. B + if cdata = '1' and chid = '1' then + cap_new(cap_len) <= ch_data; + cap_len <= cap_len + 1; + end if; + when others => null; + end case; + end if; + -- if all bits captured, check with previous data + if cap_len = bitlen and compared = '0' then + compared <= '1'; + -- event generated if captured bits differ + if cap_reg_1 /= cap_new then + cap_evt <= '1'; + end if; + cap_reg_1 <= cap_new; + else + cap_evt <= '0'; + end if; + end if; + end if; + end if; + end process CDAT; + + d_enable(0) <= ud_a_en; + d_enable(1) <= ud_b_en; + d_enable(2) <= cs_a_en; + d_enable(3) <= cs_b_en; + +end rtl; diff --git a/adi_library/axi_spdif_rx/rx_decode.vhd b/adi_library/axi_spdif_rx/rx_decode.vhd new file mode 100644 index 00000000..a8f2585c --- /dev/null +++ b/adi_library/axi_spdif_rx/rx_decode.vhd @@ -0,0 +1,265 @@ +---------------------------------------------------------------------- +---- ---- +---- WISHBONE SPDIF IP Core ---- +---- ---- +---- This file is part of the SPDIF project ---- +---- http://www.opencores.org/cores/spdif_interface/ ---- +---- ---- +---- Description ---- +---- Sample decoder. Extract sample words and write to sample ---- +---- buffer. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.4 2004/07/11 16:19:50 gedra +-- Bug-fix. +-- +-- Revision 1.3 2004/06/26 14:14:47 gedra +-- Converted to numeric_std and fixed a few bugs. +-- +-- Revision 1.2 2004/06/16 19:04:09 gedra +-- Fixed a few bugs. +-- +-- Revision 1.1 2004/06/13 18:07:47 gedra +-- Frame decoder and sample extractor +-- +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity rx_decode is + generic (DATA_WIDTH: integer range 16 to 32; + ADDR_WIDTH: integer range 8 to 64); + port ( + up_clk: in std_logic; + conf_rxen: in std_logic; + conf_sample: in std_logic; + conf_valid: in std_logic; + conf_mode: in std_logic_vector(3 downto 0); + conf_blken: in std_logic; + conf_valen: in std_logic; + conf_useren: in std_logic; + conf_staten: in std_logic; + conf_paren: in std_logic; + lock: in std_logic; + rx_data: in std_logic; + rx_data_en: in std_logic; + rx_block_start: in std_logic; + rx_frame_start: in std_logic; + rx_channel_a: in std_logic; + wr_en: out std_logic; + wr_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0); + wr_data: out std_logic_vector(DATA_WIDTH - 1 downto 0); + stat_paritya: out std_logic; + stat_parityb: out std_logic; + stat_lsbf: out std_logic; + stat_hsbf: out std_logic); +end rx_decode; + +architecture rtl of rx_decode is + + signal adr_cnt : integer range 0 to 2**(ADDR_WIDTH - 1) - 1; + type samp_states is (IDLE, CHA_SYNC, GET_SAMP, PAR_CHK); + signal sampst : samp_states; + signal bit_cnt, par_cnt : integer range 0 to 31; + signal samp_start : integer range 0 to 15; + signal tmp_data : std_logic_vector(31 downto 0); + signal tmp_stat : std_logic_vector(4 downto 0); + signal valid, next_is_a, blk_start : std_logic; + +begin + +-- output data + OD32: if DATA_WIDTH = 32 generate + --wr_data(31 downto 27) <= tmp_stat; + wr_data(31 downto 0) <= tmp_data(31 downto 0); + end generate OD32; + OD16: if DATA_WIDTH = 16 generate + wr_data(15 downto 0) <= tmp_data(15 downto 0); + end generate OD16; + +-- State machine extracting audio samples + SAEX: process (up_clk, conf_rxen) + begin -- process SAEX + if conf_rxen = '0' then + adr_cnt <= 0; + next_is_a <= '1'; + wr_en <= '0'; + wr_addr <= (others => '0'); + tmp_data <= (others => '0'); + par_cnt <= 0; + blk_start <= '0'; + stat_paritya <= '0'; + stat_parityb <= '0'; + stat_lsbf <= '0'; + stat_hsbf <= '0'; + valid <= '0'; + bit_cnt <= 0; + sampst <= IDLE; + tmp_stat <= (others => '0'); + elsif rising_edge(up_clk) then + --extract and store samples + case sampst is + when IDLE => + next_is_a <= '1'; + if lock = '1' and conf_sample = '1' then + sampst <= CHA_SYNC; + end if; + when CHA_SYNC => + wr_addr <= std_logic_vector(to_unsigned(adr_cnt, ADDR_WIDTH - 1)); + wr_en <= '0'; + bit_cnt <= 0; + valid <= '0'; + par_cnt <= 0; + stat_paritya <= '0'; + stat_parityb <= '0'; + stat_lsbf <= '0'; + stat_hsbf <= '0'; + --tmp_data(31 downto 0) <= (others => '0'); + if rx_block_start = '1' and conf_blken = '1' then + blk_start <= '1'; + end if; + if rx_frame_start = '1' then --and rx_channel_a = '1' then --next_is_a then + next_is_a <= rx_channel_a; + if(rx_channel_a = '1') then + tmp_data(31 downto 0) <= (others => '0'); + end if; + sampst <= GET_SAMP; + end if; + when GET_SAMP => + tmp_stat(0) <= blk_start; + if rx_data_en = '1' then + bit_cnt <= bit_cnt + 1; + -- audio part + if bit_cnt >= samp_start and bit_cnt <= 23 then + if(next_is_a = '1') then + tmp_data(bit_cnt - samp_start) <= rx_data; + else + tmp_data(bit_cnt + 16 - samp_start) <= rx_data; + end if; + end if; + -- status bits + case bit_cnt is + when 24 => -- validity bit + valid <= rx_data; + if conf_valen = '1' then + tmp_stat(1) <= rx_data; + else + tmp_stat(1) <= '0'; + end if; + when 25 => -- user data + if conf_useren = '1' then + tmp_stat(2) <= rx_data; + else + tmp_stat(2) <= '0'; + end if; + when 26 => -- channel status + if conf_staten = '1' then + tmp_stat(3) <= rx_data; + else + tmp_stat(3) <= '0'; + end if; + when 27 => -- parity bit + if conf_paren = '1' then + tmp_stat(4) <= rx_data; + else + tmp_stat(4) <= '0'; + end if; + when others => + null; + end case; + -- parity: count number of 1's + if rx_data = '1' then + par_cnt <= par_cnt + 1; + end if; + end if; + if bit_cnt = 28 then + sampst <= PAR_CHK; + end if; + when PAR_CHK => + blk_start <= '0'; + if (((valid = '0' and conf_valid = '1') or conf_valid = '0') and (next_is_a = '0')) then + wr_en <= '1'; + end if; + -- parity check + if par_cnt mod 2 /= 0 then + if rx_channel_a = '1' then + stat_paritya <= '1'; + else + stat_parityb <= '1'; + end if; + end if; + -- address counter + if adr_cnt < 2**(ADDR_WIDTH - 1) - 1 then + adr_cnt <= adr_cnt + 1; + else + adr_cnt <= 0; + stat_hsbf <= '1'; -- signal high buffer full + end if; + if adr_cnt = 2**(ADDR_WIDTH - 2) - 1 then + stat_lsbf <= '1'; -- signal low buffer full + end if; + sampst <= CHA_SYNC; + when others => + sampst <= IDLE; + end case; + end if; + end process SAEX; + +-- determine sample resolution from mode bits in 32bit mode + M32: if DATA_WIDTH = 32 generate + samp_start <= 8 when conf_mode = "0000" else + 7 when conf_mode = "0001" else + 6 when conf_mode = "0010" else + 5 when conf_mode = "0011" else + 4 when conf_mode = "0100" else + 3 when conf_mode = "0101" else + 2 when conf_mode = "0110" else + 1 when conf_mode = "0111" else + 0 when conf_mode = "1000" else + 8; + end generate M32; +-- in 16bit mode only 16bit of audio is supported + M16: if DATA_WIDTH = 16 generate + samp_start <= 8; + end generate M16; + + +end rtl; diff --git a/adi_library/axi_spdif_rx/rx_package.vhd b/adi_library/axi_spdif_rx/rx_package.vhd new file mode 100644 index 00000000..8df4c9fd --- /dev/null +++ b/adi_library/axi_spdif_rx/rx_package.vhd @@ -0,0 +1,248 @@ +---------------------------------------------------------------------- +---- ---- +---- WISHBONE SPDIF IP Core ---- +---- ---- +---- This file is part of the SPDIF project ---- +---- http://www.opencores.org/cores/spdif_interface/ ---- +---- ---- +---- Description ---- +---- SPDIF receiver component package. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.8 2004/06/27 16:16:55 gedra +-- Signal renaming and bug fix. +-- +-- Revision 1.7 2004/06/26 14:14:47 gedra +-- Converted to numeric_std and fixed a few bugs. +-- +-- Revision 1.6 2004/06/23 18:10:17 gedra +-- Added Wishbone bus cycle decoder. +-- +-- Revision 1.5 2004/06/16 19:03:45 gedra +-- Changed status reg. declaration +-- +-- Revision 1.4 2004/06/13 18:08:09 gedra +-- Added frame decoder and sample extractor +-- +-- Revision 1.3 2004/06/10 18:57:36 gedra +-- Cleaned up lint warnings. +-- +-- Revision 1.2 2004/06/09 19:24:50 gedra +-- Added dual port ram. +-- +-- Revision 1.1 2004/06/07 18:06:00 gedra +-- Receiver component declarations. +-- +-- + +library IEEE; +use IEEE.std_logic_1164.all; + +package rx_package is + +-- type declarations + type bus_array is array (0 to 7) of std_logic_vector(31 downto 0); + +-- components + component rx_ver_reg + generic (DATA_WIDTH: integer := 32; + ADDR_WIDTH: integer := 8; + CH_ST_CAPTURE: integer := 1); + port ( + ver_rd: in std_logic; -- version register read + ver_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0)); -- read data + end component; + + component gen_control_reg + generic (DATA_WIDTH: integer; + -- note that this vector is (0 to xx), reverse order + ACTIVE_BIT_MASK: std_logic_vector); + port ( + clk: in std_logic; -- clock + rst: in std_logic; -- reset + ctrl_wr: in std_logic; -- control register write + ctrl_rd: in std_logic; -- control register read + ctrl_din: in std_logic_vector(DATA_WIDTH - 1 downto 0); + ctrl_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0); + ctrl_bits: out std_logic_vector(DATA_WIDTH - 1 downto 0)); + end component; + + component rx_status_reg + generic (DATA_WIDTH: integer := 32); + port ( + up_clk: in std_logic; -- clock + status_rd: in std_logic; -- status register read + lock: in std_logic; -- signal lock status + chas: in std_logic; -- channel A or B select + rx_block_start: in std_logic; -- start of block signal + ch_data: in std_logic; -- channel status/user data + cs_a_en: in std_logic; -- channel status ch. A enable + cs_b_en: in std_logic; -- channel status ch. B enable + status_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0)); + end component; + + component gen_event_reg + generic (DATA_WIDTH: integer := 32); + port ( + clk: in std_logic; -- clock + rst: in std_logic; -- reset + evt_wr: in std_logic; -- event register write + evt_rd: in std_logic; -- event register read + evt_din: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data + event: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- event vector + evt_mask: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- irq mask + evt_en: in std_logic; -- irq enable + evt_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0); -- read data + evt_irq: out std_logic); -- interrupt request + end component; + + component rx_cap_reg + port ( + clk: in std_logic; -- clock + rst: in std_logic; -- reset + --cap_ctrl_wr: in std_logic; -- control register write + --cap_ctrl_rd: in std_logic; -- control register read + --cap_data_rd: in std_logic; -- data register read + cap_reg: in std_logic_vector(31 downto 0); + cap_din: in std_logic_vector(31 downto 0); -- write data + rx_block_start: in std_logic; -- start of block signal + ch_data: in std_logic; -- channel status/user data + ud_a_en: in std_logic; -- user data ch. A enable + ud_b_en: in std_logic; -- user data ch. B enable + cs_a_en: in std_logic; -- channel status ch. A enable + cs_b_en: in std_logic; -- channel status ch. B enable + cap_dout: out std_logic_vector(31 downto 0); -- read data + cap_evt: out std_logic); -- capture event (interrupt) + end component; + + component rx_phase_det + generic (AXI_FREQ: natural := 33); -- WishBone frequency in MHz + port ( + up_clk: in std_logic; + rxen: in std_logic; + spdif: in std_logic; + lock: out std_logic; + lock_evt: out std_logic; -- lock status change event + rx_data: out std_logic; + rx_data_en: out std_logic; + rx_block_start: out std_logic; + rx_frame_start: out std_logic; + rx_channel_a: out std_logic; + rx_error: out std_logic; + ud_a_en: out std_logic; -- user data ch. A enable + ud_b_en: out std_logic; -- user data ch. B enable + cs_a_en: out std_logic; -- channel status ch. A enable + cs_b_en: out std_logic); -- channel status ch. B enable); + end component; + + component dpram + generic (DATA_WIDTH: positive := 32; + RAM_WIDTH: positive := 8); + port ( + clk: in std_logic; + rst: in std_logic; -- reset is optional, not used here + din: in std_logic_vector(DATA_WIDTH - 1 downto 0); + wr_en: in std_logic; + rd_en: in std_logic; + wr_addr: in std_logic_vector(RAM_WIDTH - 1 downto 0); + rd_addr: in std_logic_vector(RAM_WIDTH - 1 downto 0); + dout: out std_logic_vector(DATA_WIDTH - 1 downto 0)); + end component; + + component rx_decode + generic (DATA_WIDTH: integer range 16 to 32 := 32; + ADDR_WIDTH: integer range 8 to 64 := 8); + port ( + up_clk: in std_logic; + conf_rxen: in std_logic; + conf_sample: in std_logic; + conf_valid: in std_logic; + conf_mode: in std_logic_vector(3 downto 0); + conf_blken: in std_logic; + conf_valen: in std_logic; + conf_useren: in std_logic; + conf_staten: in std_logic; + conf_paren: in std_logic; + lock: in std_logic; + rx_data: in std_logic; + rx_data_en: in std_logic; + rx_block_start: in std_logic; + rx_frame_start: in std_logic; + rx_channel_a: in std_logic; + wr_en: out std_logic; + wr_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0); + wr_data: out std_logic_vector(DATA_WIDTH - 1 downto 0); + stat_paritya: out std_logic; + stat_parityb: out std_logic; + stat_lsbf: out std_logic; + stat_hsbf: out std_logic); + end component; + + component rx_wb_decoder + generic (DATA_WIDTH: integer := 32; + ADDR_WIDTH: integer := 8); + port ( + up_clk: in std_logic; -- wishbone clock + wb_rst_i: in std_logic; -- reset signal + wb_sel_i: in std_logic; -- select input + wb_stb_i: in std_logic; -- strobe input + wb_we_i: in std_logic; -- write enable + wb_cyc_i: in std_logic; -- cycle input + wb_bte_i: in std_logic_vector(1 downto 0); -- burts type extension + wb_adr_i: in std_logic_vector(ADDR_WIDTH - 1 downto 0); -- address + wb_cti_i: in std_logic_vector(2 downto 0); -- cycle type identifier + data_out: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- internal bus + wb_ack_o: out std_logic; -- acknowledge + wb_dat_o: out std_logic_vector(DATA_WIDTH - 1 downto 0); -- data out + version_rd: out std_logic; -- Version register read + config_rd: out std_logic; -- Config register read + config_wr: out std_logic; -- Config register write + status_rd: out std_logic; -- Status register read + intmask_rd: out std_logic; -- Interrupt mask register read + intmask_wr: out std_logic; -- Interrupt mask register write + intstat_rd: out std_logic; -- Interrupt status register read + intstat_wr: out std_logic; -- Interrupt status register read + mem_rd: out std_logic; -- Sample memory read + mem_addr: out std_logic_vector(ADDR_WIDTH - 2 downto 0); -- memory addr. + ch_st_cap_rd: out std_logic_vector(7 downto 0); -- Ch. status cap. read + ch_st_cap_wr: out std_logic_vector(7 downto 0); -- Ch. status cap. write + ch_st_data_rd: out std_logic_vector(7 downto 0)); -- Ch. status data read + end component; + +end rx_package; diff --git a/adi_library/axi_spdif_rx/rx_phase_det.vhd b/adi_library/axi_spdif_rx/rx_phase_det.vhd new file mode 100644 index 00000000..f99b1473 --- /dev/null +++ b/adi_library/axi_spdif_rx/rx_phase_det.vhd @@ -0,0 +1,398 @@ +---------------------------------------------------------------------- +---- ---- +---- WISHBONE SPDIF IP Core ---- +---- ---- +---- This file is part of the SPDIF project ---- +---- http://www.opencores.org/cores/spdif_interface/ ---- +---- ---- +---- Description ---- +---- Oversampling phase detector. Decodes bi-phase mark encoded ---- +---- signal. Clock must be at least 8 times higher than bit rate. ---- +---- The SPDIF bitrate must be minimum 100kHz. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.5 2004/07/19 16:58:37 gedra +-- Fixed bug. +-- +-- Revision 1.4 2004/07/12 17:06:41 gedra +-- Fixed bug with lock event generation. +-- +-- Revision 1.3 2004/07/11 16:19:50 gedra +-- Bug-fix. +-- +-- Revision 1.2 2004/06/13 18:08:50 gedra +-- Renamed generic and cleaned some lint's +-- +-- Revision 1.1 2004/06/06 15:43:02 gedra +-- Early version of the bi-phase mark decoder. +-- +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity rx_phase_det is + generic (AXI_FREQ: natural := 100); -- WishBone frequency in MHz + port ( + up_clk: in std_logic; -- wishbone clock + rxen: in std_logic; -- phase detector enable + spdif: in std_logic; -- SPDIF input signal + lock: out std_logic; -- true if locked to spdif input + lock_evt: out std_logic; -- lock status change event + rx_data: out std_logic; -- recevied data + rx_data_en: out std_logic; -- received data enable + rx_block_start: out std_logic; -- start-of-block pulse + rx_frame_start: out std_logic; -- start-of-frame pulse + rx_channel_a: out std_logic; -- 1 if channel A frame is recevied + rx_error: out std_logic; -- signal error was detected + ud_a_en: out std_logic; -- user data ch. A enable + ud_b_en: out std_logic; -- user data ch. B enable + cs_a_en: out std_logic; -- channel status ch. A enable + cs_b_en: out std_logic); -- channel status ch. B enable); +end rx_phase_det; + +architecture rtl of rx_phase_det is + + constant TRANSITIONS : integer := 70; + constant FRAMES_FOR_LOCK : integer := 3; + signal maxpulse, maxp, mp_cnt: integer range 0 to 16 * AXI_FREQ; + signal last_cnt, max_thres : integer range 0 to 16 * AXI_FREQ; + signal minpulse, minp, min_thres: integer range 0 to 8 * AXI_FREQ; + signal zspdif, spdif_in, zspdif_in, trans, ztrans : std_logic; + signal trans_cnt : integer range 0 to TRANSITIONS; + signal valid, p_long, p_short: std_logic; + type pulse_type is (ZERO, SHORT, MED, LONG); + type pulse_array is array (0 to 3) of pulse_type; + signal preamble: pulse_array; + signal new_pulse, short_idx, ilock: std_logic; + type frame_state is (IDLE, HUNT, FRAMESTART, FRAME_RX); + signal framerx : frame_state; + signal frame_cnt : integer range 0 to FRAMES_FOR_LOCK; + signal bit_cnt : integer range 0 to 63; + signal pre_cnt : integer range 0 to 7; + type preamble_types is (NONE, PRE_X, PRE_Y, PRE_Z); + signal new_preamble, last_preamble : preamble_types; + signal irx_channel_a, zilock : std_logic; + +begin + + -- Pulse width analyzer + PHDET: process (up_clk, rxen) + begin + if rxen = '0' then -- reset by configuration register bit + maxpulse <= 0; + maxp <= 0; + mp_cnt <= 0; + zspdif <= '0'; + zspdif_in <= '0'; + spdif_in <= '0'; + trans_cnt <= 0; + minpulse <= 0; + minp <= 8 * AXI_FREQ; + last_cnt <= 0; + trans <= '0'; + valid <= '0'; + preamble <= (ZERO, ZERO, ZERO, ZERO); + max_thres <= 0; + min_thres <= 0; + new_preamble <= NONE; + ztrans <= '0'; + new_pulse <= '0'; + else + if rising_edge(up_clk) then + -- sync spdif signal to wishbone clock + zspdif <= spdif; + spdif_in <= zspdif; + -- find the longest pulse, which is the bi-phase violation + -- also find the shortest pulse + zspdif_in <= spdif_in; + if zspdif_in /= spdif_in then -- input transition + mp_cnt <= 0; + trans <= '1'; + last_cnt <= mp_cnt; + if trans_cnt > 0 then + if mp_cnt > maxp then + maxp <= mp_cnt; + end if; + if mp_cnt < minp then + minp <= mp_cnt; + end if; + end if; + else + trans <= '0'; + if mp_cnt < 16 * AXI_FREQ then + mp_cnt <= mp_cnt + 1; + end if; + end if; + -- transition counting + if trans = '1' then + if trans_cnt < TRANSITIONS then + trans_cnt <= trans_cnt + 1; + else + -- the max/min pulse length is updated after given # of transitions + trans_cnt <= 0; + maxpulse <= maxp; + maxp <= 0; + minpulse <= minp; + minp <= 8 * AXI_FREQ; + min_thres <= maxp / 2; + if maxp < 11 then + max_thres <= maxp - 1; + else + max_thres <= maxp - 3; + end if; + end if; + end if; + -- detection of valid SPDIF signal + if maxpulse > 6 then + valid <= '1'; + else + valid <= '0'; + end if; + -- bit decoding + if trans = '1' then + if (last_cnt < min_thres) and (last_cnt > 0) then + p_short <= '1'; + preamble(0) <= SHORT; + else + p_short <= '0'; + end if; + if last_cnt >= max_thres then + p_long <= '1'; + preamble(0) <= LONG; + else + p_long <= '0'; + end if; + if last_cnt = 0 then + preamble(0) <= ZERO; + end if; + if (last_cnt < max_thres) and (last_cnt >= min_thres) then + preamble(0) <= MED; + end if; + preamble(3) <= preamble(2); + preamble(2) <= preamble(1); + preamble(1) <= preamble(0); + end if; + -- preamble detection + if preamble(3) = LONG and preamble(2) = LONG and preamble(1) = SHORT + and preamble(0) = SHORT then + new_preamble <= PRE_X; + elsif preamble(3) = LONG and preamble(2) = MED and preamble(1) = SHORT + and preamble(0) = MED then + new_preamble <= PRE_Y; + elsif preamble(3) = LONG and preamble(2) = SHORT and preamble(1) = SHORT + and preamble(0) = LONG then + new_preamble <= PRE_Z; + else + new_preamble <= NONE; + end if; + -- delayed transition pulse for the state machine + ztrans <= trans; + new_pulse <= ztrans; + end if; + end if; + end process; + + lock <= ilock; + rx_channel_a <= irx_channel_a; + + -- State machine that hunt for and lock onto sub-frames + FRX: process (up_clk, rxen) + begin + if rxen = '0' then + framerx <= IDLE; + ilock <= '0'; + zilock <= '0'; + rx_data <= '0'; + rx_data_en <= '0'; + rx_block_start <= '0'; + rx_frame_start <= '0'; + irx_channel_a <= '0'; + ud_a_en <= '0'; + ud_b_en <= '0'; + cs_a_en <= '0'; + cs_b_en <= '0'; + rx_error <= '0'; + lock_evt <= '0'; + bit_cnt <= 0; + pre_cnt <= 0; + short_idx <= '0'; + frame_cnt <= 0; + last_preamble <= NONE; + elsif rising_edge(up_clk) then + zilock <= ilock; + if zilock /= ilock then -- generate event for event reg. + lock_evt <= '1'; + else + lock_evt <= '0'; + end if; + case framerx is + when IDLE => -- wait for recevier to be enabled + if valid = '1' then + framerx <= HUNT; + end if; + when HUNT => -- wait for preamble detection + frame_cnt <= 0; + ilock <= '0'; + rx_error <= '0'; + if new_pulse = '1' then + if new_preamble /= NONE then + framerx <= FRAMESTART; + end if; + end if; + when FRAMESTART => -- reset sub-frame bit counter + bit_cnt <= 0; + pre_cnt <= 0; + if frame_cnt < FRAMES_FOR_LOCK then + frame_cnt <= frame_cnt + 1; + else + ilock <= '1'; + end if; + last_preamble <= new_preamble; + short_idx <= '0'; + rx_frame_start <= '1'; + rx_block_start <= '0'; + framerx <= FRAME_RX; + when FRAME_RX => -- receive complete sub-frame + if new_pulse = '1' then + if bit_cnt < 28 then + case preamble(0) is + when ZERO => + short_idx <= '0'; + when SHORT => + if short_idx = '0' then + short_idx <= '1'; + else + -- two short pulses is a logical '1' + bit_cnt <= bit_cnt + 1; + short_idx <= '0'; + rx_data <= '1'; + rx_data_en <= ilock; + -- user data enable for the capture register + if bit_cnt = 25 and ilock = '1' then + ud_a_en <= irx_channel_a; + ud_b_en <= not irx_channel_a; + end if; + -- channel status enable for the capture register + if bit_cnt = 26 and ilock = '1' then + cs_a_en <= irx_channel_a; + cs_b_en <= not irx_channel_a; + end if; + end if; + when MED => + -- medium pulse is logical '0' + bit_cnt <= bit_cnt + 1; + rx_data <= '0'; + rx_data_en <= ilock; + short_idx <= '0'; + -- user data enable for the capture register + if bit_cnt = 25 and ilock = '1' then + ud_a_en <= irx_channel_a; + ud_b_en <= not irx_channel_a; + end if; + -- channel status enable for the capture register + if bit_cnt = 26 and ilock = '1' then + cs_a_en <= irx_channel_a; + cs_b_en <= not irx_channel_a; + end if; + when LONG => + short_idx <= '0'; + when others => + framerx <= HUNT; + end case; + else + -- there should be 4 pulses in preamble + if pre_cnt < 7 then + pre_cnt <= pre_cnt + 1; + else + rx_error <= '1'; + framerx <= HUNT; + end if; + -- check for correct preamble here + if pre_cnt = 3 then + case last_preamble is + when PRE_X => + if new_preamble = PRE_Y then + framerx <= FRAMESTART; + irx_channel_a <= '0'; + else + rx_error <= '1'; + framerx <= HUNT; + end if; + when PRE_Y => + if new_preamble = PRE_X or new_preamble = PRE_Z then + irx_channel_a <= '1'; + -- start of new block? + if new_preamble = PRE_Z then + rx_block_start <= '1'; + end if; + framerx <= FRAMESTART; + else + rx_error <= '1'; + framerx <= HUNT; + end if; + when PRE_Z => + if new_preamble = PRE_Y then + irx_channel_a <= '0'; + framerx <= FRAMESTART; + else + rx_error <= '1'; + framerx <= HUNT; + end if; + when others => + rx_error <= '1'; + framerx <= HUNT; + end case; + end if; + end if; + else + rx_data_en <= '0'; + rx_block_start <= '0'; + rx_frame_start <= '0'; + ud_a_en <= '0'; + ud_b_en <= '0'; + cs_a_en <= '0'; + cs_b_en <= '0'; + end if; + when others => + framerx <= IDLE; + end case; + end if; + end process FRX; + +end rtl; diff --git a/adi_library/axi_spdif_rx/rx_status_reg.vhd b/adi_library/axi_spdif_rx/rx_status_reg.vhd new file mode 100644 index 00000000..afd9576b --- /dev/null +++ b/adi_library/axi_spdif_rx/rx_status_reg.vhd @@ -0,0 +1,150 @@ +---------------------------------------------------------------------- +---- ---- +---- WISHBONE SPDIF IP Core ---- +---- ---- +---- This file is part of the SPDIF project ---- +---- http://www.opencores.org/cores/spdif_interface/ ---- +---- ---- +---- Description ---- +---- SPDIF receiver status register ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.4 2004/06/27 16:16:55 gedra +-- Signal renaming and bug fix. +-- +-- Revision 1.3 2004/06/26 14:14:47 gedra +-- Converted to numeric_std and fixed a few bugs. +-- +-- Revision 1.2 2004/06/16 19:03:10 gedra +-- Added channel status decoding. +-- +-- Revision 1.1 2004/06/05 17:17:12 gedra +-- Recevier status register +-- +-- + +library ieee; +use ieee.std_logic_1164.all; + +entity rx_status_reg is + generic (DATA_WIDTH: integer); + port ( + up_clk: in std_logic; -- clock + status_rd: in std_logic; -- status register read + lock: in std_logic; -- signal lock status + chas: in std_logic; -- channel A or B select + rx_block_start: in std_logic; -- start of block signal + ch_data: in std_logic; -- channel status/user data + cs_a_en: in std_logic; -- channel status ch. A enable + cs_b_en: in std_logic; -- channel status ch. B enable + status_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0)); +end rx_status_reg; + +architecture rtl of rx_status_reg is + + signal status_vector : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal cur_pos : integer range 0 to 255; + signal pro_mode : std_logic; + +begin + + status_dout <= status_vector when status_rd = '1' else (others => '0'); + + D32: if DATA_WIDTH = 32 generate + status_vector(31 downto 16) <= (others => '0'); + end generate D32; + + status_vector(0) <= lock; + status_vector(15 downto 7) <= (others => '0'); + +-- extract channel status bits to be used + CDAT: process (up_clk, lock) + begin + if lock = '0' then + cur_pos <= 0; + pro_mode <= '0'; + status_vector(6 downto 1) <= (others => '0'); + else + if rising_edge(up_clk) then + -- bit counter, 0 to 191 + if rx_block_start = '1' then + cur_pos <= 0; + elsif cs_b_en = '1' then -- ch. status #2 comes last, count then + cur_pos <= cur_pos + 1; + end if; + -- extract status bits used in status register + if (chas = '0' and cs_b_en = '1') or + (chas = '1' and cs_a_en = '1') then + case cur_pos is + when 0 => -- PRO bit + status_vector(1) <= ch_data; + pro_mode <= ch_data; + when 1 => -- AUDIO bit + status_vector(2) <= not ch_data; + when 2 => -- emphasis/copy bit + if pro_mode = '1' then + status_vector(5) <= ch_data; + else + status_vector(6) <= ch_data; + end if; + when 3 => -- emphasis + if pro_mode = '1' then + status_vector(4) <= ch_data; + else + status_vector(5) <= ch_data; + end if; + when 4 => -- emphasis + if pro_mode = '1' then + status_vector(3) <= ch_data; + else + status_vector(4) <= ch_data; + end if; + when 5 => -- emphasis + if pro_mode = '0' then + status_vector(3) <= ch_data; + end if; + when others => + null; + end case; + end if; + end if; + end if; + end process CDAT; + +end rtl; diff --git a/adi_library/axi_spdif_rx/xgui/axi_spdif_rx_v1_0.tcl b/adi_library/axi_spdif_rx/xgui/axi_spdif_rx_v1_0.tcl new file mode 100644 index 00000000..edca41d6 --- /dev/null +++ b/adi_library/axi_spdif_rx/xgui/axi_spdif_rx_v1_0.tcl @@ -0,0 +1,55 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_DMA_TYPE" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_S_AXI_ADDR_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "C_S_AXI_DATA_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.C_DMA_TYPE { PARAM_VALUE.C_DMA_TYPE } { + # Procedure called to update C_DMA_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_DMA_TYPE { PARAM_VALUE.C_DMA_TYPE } { + # Procedure called to validate C_DMA_TYPE + return true +} + +proc update_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } { + # Procedure called to update C_S_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } { + # Procedure called to validate C_S_AXI_ADDR_WIDTH + return true +} + +proc update_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } { + # Procedure called to update C_S_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } { + # Procedure called to validate C_S_AXI_DATA_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH PARAM_VALUE.C_S_AXI_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH PARAM_VALUE.C_S_AXI_ADDR_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_S_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH} +} + +proc update_MODELPARAM_VALUE.C_DMA_TYPE { MODELPARAM_VALUE.C_DMA_TYPE PARAM_VALUE.C_DMA_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_DMA_TYPE}] ${MODELPARAM_VALUE.C_DMA_TYPE} +} + diff --git a/adi_library/axi_spdif_tx/Makefile b/adi_library/axi_spdif_tx/Makefile new file mode 100644 index 00000000..086068ac --- /dev/null +++ b/adi_library/axi_spdif_tx/Makefile @@ -0,0 +1,20 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_spdif_tx + +GENERIC_DEPS += ../common/axi_ctrlif.vhd +GENERIC_DEPS += ../common/axi_streaming_dma_tx_fifo.vhd +GENERIC_DEPS += ../common/dma_fifo.vhd +GENERIC_DEPS += ../common/pl330_dma_fifo.vhd +GENERIC_DEPS += axi_spdif_tx.vhd +GENERIC_DEPS += tx_encoder.vhd +GENERIC_DEPS += tx_package.vhd + +XILINX_DEPS += axi_spdif_tx_constr.xdc +XILINX_DEPS += axi_spdif_tx_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_spdif_tx/axi_spdif_tx.vhd b/adi_library/axi_spdif_tx/axi_spdif_tx.vhd new file mode 100644 index 00000000..6940c543 --- /dev/null +++ b/adi_library/axi_spdif_tx/axi_spdif_tx.vhd @@ -0,0 +1,318 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +-- +-- In this HDL repository, there are many different and unique modules, consisting +-- of various HDL (Verilog or VHDL) components. The individual modules are +-- developed independently, and may be accompanied by separate and unique license +-- terms. +-- +-- The user should read each of these license terms, and understand the +-- freedoms and responsibilities that he or she has by using this source/core. +-- +-- This core is distributed in the hope that it will be useful, but WITHOUT ANY +-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +-- A PARTICULAR PURPOSE. +-- +-- Redistribution and use of source or resulting binaries, with or without modification +-- of this file, are permitted under one of the following two license terms: +-- +-- 1. The GNU General Public License version 2 as published by the +-- Free Software Foundation, which can be found in the top level directory +-- of this repository (LICENSE_GPL2), and also online at: +-- +-- +-- OR +-- +-- 2. An ADI specific BSD license, which can be found in the top level directory +-- of this repository (LICENSE_ADIBSD), and also on-line at: +-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +-- This will allow to generate bit files and not release the source code, +-- as long as it attaches to an ADI device. +-- +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; + +library work; +use work.tx_package.all; +use work.axi_ctrlif; +use work.axi_streaming_dma_tx_fifo; +use work.pl330_dma_fifo; + +entity axi_spdif_tx is + generic ( + S_AXI_DATA_WIDTH : integer := 32; + S_AXI_ADDRESS_WIDTH : integer := 32; + DEVICE_FAMILY : string := "virtex6"; + DMA_TYPE : integer := 0 + ); + port ( + --SPDIF ports + spdif_data_clk : in std_logic; + spdif_tx_o : out std_logic; + + --AXI Lite interface + s_axi_aclk : in std_logic; + s_axi_aresetn : in std_logic; + s_axi_awaddr : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0); + s_axi_awprot : in std_logic_vector(2 downto 0); + s_axi_awvalid : in std_logic; + s_axi_wdata : in std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0); + s_axi_wstrb : in std_logic_vector((S_AXI_DATA_WIDTH/8)-1 downto 0); + s_axi_wvalid : in std_logic; + s_axi_bready : in std_logic; + s_axi_araddr : in std_logic_vector(S_AXI_ADDRESS_WIDTH-1 downto 0); + s_axi_arprot : in std_logic_vector(2 downto 0); + s_axi_arvalid : in std_logic; + s_axi_rready : in std_logic; + s_axi_arready : out std_logic; + s_axi_rdata : out std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0); + s_axi_rresp : out std_logic_vector(1 downto 0); + s_axi_rvalid : out std_logic; + s_axi_wready : out std_logic; + s_axi_bresp : out std_logic_vector(1 downto 0); + s_axi_bvalid : out std_logic; + s_axi_awready : out std_logic; + + --axi streaming interface + s_axis_aclk : in std_logic; + s_axis_aresetn : in std_logic; + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(31 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + --PL330 DMA interface + dma_req_aclk : in std_logic; + dma_req_rstn : in std_logic; + dma_req_davalid : in std_logic; + dma_req_datype : in std_logic_vector(1 downto 0); + dma_req_daready : out std_logic; + dma_req_drvalid : out std_logic; + dma_req_drtype : out std_logic_vector(1 downto 0); + dma_req_drlast : out std_logic; + dma_req_drready : in std_logic + ); +end entity axi_spdif_tx; + +------------------------------------------------------------------------------ +-- Architecture section +------------------------------------------------------------------------------ + +architecture IMP of axi_spdif_tx is + ------------------------------------------ + -- SPDIF signals + ------------------------------------------ + signal config_reg : std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0); + signal chstatus_reg : std_logic_vector(S_AXI_DATA_WIDTH-1 downto 0); + + signal chstat_freq : std_logic_vector(1 downto 0); + signal chstat_gstat, chstat_preem, chstat_copy, chstat_audio : std_logic; + signal sample_data_ack : std_logic; + signal sample_data: std_logic_vector(15 downto 0); + signal conf_mode : std_logic_vector(3 downto 0); + signal conf_ratio : std_logic_vector(7 downto 0); + signal conf_tinten, conf_txdata, conf_txen : std_logic; + signal channel : std_logic; + signal enable : boolean; + + signal fifo_data_out : std_logic_vector(31 downto 0); + signal fifo_data_ack : std_logic; + signal fifo_reset : std_logic; + signal tx_fifo_stb : std_logic; + + -- Register access + signal wr_data : std_logic_vector(31 downto 0); + signal rd_data : std_logic_vector(31 downto 0); + signal wr_addr : integer range 0 to 3; + signal rd_addr : integer range 0 to 3; + signal wr_stb : std_logic; + signal rd_ack : std_logic; +begin + + fifo_reset <= not conf_txdata; + enable <= conf_txdata = '1'; + fifo_data_ack <= channel and sample_data_ack; + + streaming_dma_gen: if DMA_TYPE = 0 generate + fifo: entity axi_streaming_dma_tx_fifo + generic map ( + RAM_ADDR_WIDTH => 3, + FIFO_DWIDTH => 32 + ) + port map ( + clk => s_axi_aclk, + resetn => s_axi_aresetn, + fifo_reset => fifo_reset, + enable => enable, + s_axis_aclk => s_axis_aclk, + s_axis_tready => s_axis_tready, + s_axis_tdata => s_axis_tdata, + s_axis_tvalid => s_axis_tlast, + s_axis_tlast => s_axis_tvalid, + + out_ack => fifo_data_ack, + out_data => fifo_data_out + ); + end generate; + + no_streaming_dma_gen: if DMA_TYPE /= 0 generate + s_axis_tready <= '0'; + end generate; + + pl330_dma_gen: if DMA_TYPE = 1 generate + tx_fifo_stb <= '1' when wr_addr = 3 and wr_stb = '1' else '0'; + + fifo: entity pl330_dma_fifo + generic map( + RAM_ADDR_WIDTH => 3, + FIFO_DWIDTH => 32, + FIFO_DIRECTION => 0 + ) + port map ( + clk => s_axi_aclk, + resetn => s_axi_aresetn, + fifo_reset => fifo_reset, + enable => enable, + + in_data => wr_data, + in_stb => tx_fifo_stb, + + out_ack => fifo_data_ack, + out_data => fifo_data_out, + + dclk => dma_req_aclk, + dresetn => dma_req_rstn, + davalid => dma_req_davalid, + daready => dma_req_daready, + datype => dma_req_datype, + drvalid => dma_req_drvalid, + drready => dma_req_drreadY, + drtype => dma_req_drtype, + drlast => dma_req_drlast + ); + end generate; + + no_pl330_dma_gen: if DMA_TYPE /= 1 generate + dma_req_daready <= '0'; + dma_req_drvalid <= '0'; + dma_req_drtype <= (others => '0'); + dma_req_drlast <= '0'; + end generate; + + sample_data_mux: process (fifo_data_out, channel) is + begin + if channel = '0' then + sample_data <= fifo_data_out(15 downto 0); + else + sample_data <= fifo_data_out(31 downto 16); + end if; + end process; + + -- Configuration signals update + conf_mode(3 downto 0) <= config_reg(23 downto 20); + conf_ratio(7 downto 0) <= config_reg(15 downto 8); + conf_tinten <= config_reg(2); + conf_txdata <= config_reg(1); + conf_txen <= config_reg(0); + + -- Channel status signals update + chstat_freq(1 downto 0) <= chstatus_reg(7 downto 6); + chstat_gstat <= chstatus_reg(3); + chstat_preem <= chstatus_reg(2); + chstat_copy <= chstatus_reg(1); + chstat_audio <= chstatus_reg(0); + + -- Transmit encoder + TENC: tx_encoder + generic map ( + DATA_WIDTH => 16 + ) + port map ( + up_clk => s_axi_aclk, + data_clk => spdif_data_clk, -- data clock + resetn => s_axi_aresetn, -- resetn + conf_mode => conf_mode, -- sample format + conf_ratio => conf_ratio, -- clock divider + conf_txdata => conf_txdata, -- sample data enable + conf_txen => conf_txen, -- spdif signal enable + chstat_freq => chstat_freq, -- sample freq. + chstat_gstat => chstat_gstat, -- generation status + chstat_preem => chstat_preem, -- preemphasis status + chstat_copy => chstat_copy, -- copyright bit + chstat_audio => chstat_audio, -- data format + sample_data => sample_data, -- audio data + sample_data_ack => sample_data_ack, -- sample buffer read + channel => channel, -- which channel should be read + spdif_tx_o => spdif_tx_o -- SPDIF output signal + ); + + ctrlif: entity axi_ctrlif + generic map ( + C_S_AXI_ADDR_WIDTH => S_AXI_ADDRESS_WIDTH, + C_S_AXI_DATA_WIDTH => S_AXI_DATA_WIDTH, + C_NUM_REG => 4 + ) + port map( + s_axi_aclk => s_axi_aclk, + s_axi_aresetn => s_axi_aresetn, + s_axi_awaddr => s_axi_awaddr, + s_axi_awvalid => s_axi_awvalid, + s_axi_wdata => s_axi_wdata, + s_axi_wstrb => s_axi_wstrb, + s_axi_wvalid => s_axi_wvalid, + s_axi_bready => s_axi_bready, + s_axi_araddr => s_axi_araddr, + s_axi_arvalid => s_axi_arvalid, + s_axi_rready => s_axi_rready, + s_axi_arready => s_axi_arready, + s_axi_rdata => s_axi_rdata, + s_axi_rresp => s_axi_rresp, + s_axi_rvalid => s_axi_rvalid, + s_axi_wready => s_axi_wready, + s_axi_bresp => s_axi_bresp, + s_axi_bvalid => s_axi_bvalid, + s_axi_awready => s_axi_awready, + + rd_addr => rd_addr, + rd_data => rd_data, + rd_ack => rd_ack, + rd_stb => '1', + + wr_addr => wr_addr, + wr_data => wr_data, + wr_ack => '1', + wr_stb => wr_stb + ); + + process (s_axi_aclk) + begin + if rising_edge(s_axi_aclk) then + if s_axi_aresetn = '0' then + config_reg <= (others => '0'); + chstatus_reg <= (others => '0'); + else + if wr_stb = '1' then + case wr_addr is + when 0 => config_reg <= wr_data; + when 1 => chstatus_reg <= wr_data; + when others => null; + end case; + end if; + end if; + end if; + end process; + + process (rd_addr, config_reg, chstatus_reg) + begin + case rd_addr is + when 0 => rd_data <= config_reg; + when 1 => rd_data <= chstatus_reg; + when others => rd_data <= (others => '0'); + end case; + end process; + +end IMP; diff --git a/adi_library/axi_spdif_tx/axi_spdif_tx.xpr b/adi_library/axi_spdif_tx/axi_spdif_tx.xpr new file mode 100644 index 00000000..aea857bb --- /dev/null +++ b/adi_library/axi_spdif_tx/axi_spdif_tx.xpr @@ -0,0 +1,440 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_spdif_tx/axi_spdif_tx_constr.xdc b/adi_library/axi_spdif_tx/axi_spdif_tx_constr.xdc new file mode 100644 index 00000000..cb60b14f --- /dev/null +++ b/adi_library/axi_spdif_tx/axi_spdif_tx_constr.xdc @@ -0,0 +1,16 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property ASYNC_REG TRUE \ + [get_cells -hier cdc_sync_stage1_*_reg] \ + [get_cells -hier cdc_sync_stage2_*_reg] + +set_false_path \ + -from [get_cells -hier cdc_sync_stage0_*_reg -filter {PRIMITIVE_SUBGROUP == flop || primitive_subgroup == SDR}] \ + -to [get_cells -hier cdc_sync_stage1_*_reg -filter {PRIMITIVE_SUBGROUP == flop || primitive_subgroup == SDR}] + +set_false_path \ + -from [get_cells -hier spdif_out_reg -filter {PRIMITIVE_SUBGROUP == flop || primitive_subgroup == SDR}] \ + -to [get_cells -hier spdif_tx_o_reg -filter {PRIMITIVE_SUBGROUP == flop || primitive_subgroup == SDR}] diff --git a/adi_library/axi_spdif_tx/axi_spdif_tx_ip.tcl b/adi_library/axi_spdif_tx/axi_spdif_tx_ip.tcl new file mode 100644 index 00000000..f1b55b55 --- /dev/null +++ b/adi_library/axi_spdif_tx/axi_spdif_tx_ip.tcl @@ -0,0 +1,54 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_spdif_tx +adi_ip_files axi_spdif_tx [list \ + "$ad_hdl_dir/library/common/axi_ctrlif.vhd" \ + "$ad_hdl_dir/library/common/axi_streaming_dma_tx_fifo.vhd" \ + "$ad_hdl_dir/library/common/pl330_dma_fifo.vhd" \ + "$ad_hdl_dir/library/common/dma_fifo.vhd" \ + "tx_package.vhd" \ + "tx_encoder.vhd" \ + "axi_spdif_tx.vhd" \ + "axi_spdif_tx_constr.xdc" ] + +adi_ip_properties axi_spdif_tx +adi_ip_infer_streaming_interfaces axi_spdif_tx + +adi_add_bus "dma_ack" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"dma_req_davalid" "TVALID"} \ + {"dma_req_daready" "TREADY"} \ + {"dma_req_datype" "TUSER"} ] +adi_add_bus "dma_req" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"dma_req_drvalid" "TVALID"} \ + {"dma_req_drready" "TREADY"} \ + {"dma_req_drtype" "TUSER"} \ + {"dma_req_drlast" "TLAST"} ] + +# Clock and reset are for both dma_req and dma_ack +adi_add_bus_clock "dma_req_aclk" "dma_req:dma_ack" "dma_req_rstn" + +adi_set_bus_dependency "s_axis" "s_axis" \ + "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 0)" + +adi_set_bus_dependency "dma_ack" "dma_req_da" \ + "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" +adi_set_bus_dependency "dma_req" "dma_req_dr" \ + "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" +adi_set_ports_dependency "dma_req_aclk" \ + "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" +adi_set_ports_dependency "dma_req_rstn" \ + "(spirit:decode(id('MODELPARAM_VALUE.DMA_TYPE')) = 1)" + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/axi_spdif_tx/component.xml b/adi_library/axi_spdif_tx/component.xml new file mode 100644 index 00000000..9040d9e4 --- /dev/null +++ b/adi_library/axi_spdif_tx/component.xml @@ -0,0 +1,1477 @@ + + + analog.com + user + axi_spdif_tx + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s_axis + + + + + + + TDATA + + + s_axis_tdata + + + + + TLAST + + + s_axis_tlast + + + + + TVALID + + + s_axis_tvalid + + + + + TREADY + + + s_axis_tready + + + + + + + true + + + + + + dma_req_aclk + + + + + + + CLK + + + dma_req_aclk + + + + + + ASSOCIATED_RESET + dma_req_rstn + + + + + s_axis_aclk + + + + + + + CLK + + + s_axis_aclk + + + + + + ASSOCIATED_BUSIF + s_axis + + + ASSOCIATED_RESET + s_axis_aresetn + + + + + spdif_data_clk + + + + + + + CLK + + + spdif_data_clk + + + + + + dma_req_rstn + + + + + + + RST + + + dma_req_rstn + + + + + + POLARITY + ACTIVE_LOW + + + + + s_axis_aresetn + + + + + + + RST + + + s_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + dma_ack + + + + + + + TVALID + + + dma_req_davalid + + + + + TREADY + + + dma_req_daready + + + + + TUSER + + + dma_req_datype + + + + + + + false + + + + + + dma_req + + + + + + + TVALID + + + dma_req_drvalid + + + + + TREADY + + + dma_req_drready + + + + + TUSER + + + dma_req_drtype + + + + + TLAST + + + dma_req_drlast + + + + + + + false + + + + + + dma_req_dma_ack_signal_clock + dma_req_dma_ack_signal_clock + + + + + + + CLK + + + dma_req_aclk + + + + + + ASSOCIATED_BUSIF + dma_req:dma_ack + + + ASSOCIATED_RESET + dma_req_rstn + + + + + dma_req_dma_ack_signal_reset + dma_req_dma_ack_signal_reset + + + + + + + RST + + + dma_req_rstn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + axi_spdif_tx + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + f58934d4 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + axi_spdif_tx + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 673f3e79 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + ff8f284a + + + + + + + spdif_data_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + spdif_tx_o + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axis_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axis_tdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axis_tlast + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + s_axis_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + dma_req_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dma_req_rstn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dma_req_davalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_datype + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_daready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_drvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_drtype + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_drlast + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dma_req_drready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + + + S_AXI_DATA_WIDTH + S Axi Data Width + 32 + + + S_AXI_ADDRESS_WIDTH + S Axi Address Width + 32 + + + DEVICE_FAMILY + Device Family + virtex6 + + + DMA_TYPE + Dma Type + 0 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + axi_spdif_tx_constr.xdc + xdc + + + ../common/axi_ctrlif.vhd + vhdlSource + + + tx_package.vhd + vhdlSource + + + ../common/dma_fifo.vhd + vhdlSource + + + ../common/axi_streaming_dma_tx_fifo.vhd + vhdlSource + + + ../common/pl330_dma_fifo.vhd + vhdlSource + + + tx_encoder.vhd + vhdlSource + + + axi_spdif_tx.vhd + vhdlSource + CHECKSUM_34e69c4c + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/axi_ctrlif.vhd + vhdlSource + + + tx_package.vhd + vhdlSource + + + ../common/dma_fifo.vhd + vhdlSource + + + ../common/axi_streaming_dma_tx_fifo.vhd + vhdlSource + + + ../common/pl330_dma_fifo.vhd + vhdlSource + + + tx_encoder.vhd + vhdlSource + + + axi_spdif_tx.vhd + vhdlSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_spdif_tx_v1_0.tcl + tclSource + CHECKSUM_ff8f284a + XGUI_VERSION_2 + + + + axi_spdif_tx_v1_0 + + + S_AXI_DATA_WIDTH + S Axi Data Width + 32 + + + S_AXI_ADDRESS_WIDTH + S Axi Address Width + 32 + + + DEVICE_FAMILY + Device Family + virtex6 + + + DMA_TYPE + Dma Type + 0 + + + Component_Name + axi_spdif_tx_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_spdif_tx_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:49:11Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_spdif_tx/tx_encoder.vhd b/adi_library/axi_spdif_tx/tx_encoder.vhd new file mode 100644 index 00000000..898f81ee --- /dev/null +++ b/adi_library/axi_spdif_tx/tx_encoder.vhd @@ -0,0 +1,495 @@ +---------------------------------------------------------------------- +---- ---- +---- WISHBONE SPDIF IP Core ---- +---- ---- +---- This file is part of the SPDIF project ---- +---- http://www.opencores.org/cores/spdif_interface/ ---- +---- ---- +---- Description ---- +---- SPDIF transmitter signal encoder. Reads out samples from the ---- +---- sample buffer, assembles frames and subframes and encodes ---- +---- serial data as bi-phase mark code. ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- +-- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity tx_encoder is + generic (DATA_WIDTH: integer range 16 to 32 := 32); + port ( + up_clk: in std_logic; -- clock + data_clk : in std_logic; -- data clock + resetn : in std_logic; -- resetn + conf_mode: in std_logic_vector(3 downto 0); -- sample format + conf_ratio: in std_logic_vector(7 downto 0); -- clock divider + conf_txdata: in std_logic; -- sample data enable + conf_txen: in std_logic; -- spdif signal enable + chstat_freq: in std_logic_vector(1 downto 0); -- sample freq. + chstat_gstat: in std_logic; -- generation status + chstat_preem: in std_logic; -- preemphasis status + chstat_copy: in std_logic; -- copyright bit + chstat_audio: in std_logic; -- data format + sample_data: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data + sample_data_ack: out std_logic; -- sample buffer read + channel: out std_logic; + spdif_tx_o: out std_logic); +end tx_encoder; + +architecture rtl of tx_encoder is + + signal spdif_clk_en, spdif_out : std_logic; + signal clk_cnt : integer range 0 to 511; + type buf_states is (IDLE, READ_CHA, READ_CHB, CHA_RDY, CHB_RDY); + signal bufctrl : buf_states; + signal cha_samp_ack, chb_samp_ack : std_logic; + type frame_states is (IDLE, BLOCK_START, CHANNEL_A, CHANNEL_B); + signal framest : frame_states; + signal frame_cnt : integer range 0 to 191; + signal bit_cnt, par_cnt : integer range 0 to 31; + signal inv_preamble, toggle, valid : std_logic; + signal def_user_data, def_ch_status : std_logic_vector(191 downto 0); + signal active_user_data, active_ch_status : std_logic_vector(191 downto 0); + signal audio : std_logic_vector(23 downto 0); + signal par_vector : std_logic_vector(26 downto 0); + signal send_audio : std_logic; + + signal cdc_sync_stage0_tick_counter : std_logic := '0'; + signal cdc_sync_stage1_tick_counter : std_logic := '0'; + signal cdc_sync_stage2_tick_counter : std_logic := '0'; + signal cdc_sync_stage3_tick_counter : std_logic := '0'; + signal tick_counter : std_logic; + + constant X_PREAMBLE : std_logic_vector(0 to 7) := "11100010"; + constant Y_PREAMBLE : std_logic_vector(0 to 7) := "11100100"; + constant Z_PREAMBLE : std_logic_vector(0 to 7) := "11101000"; + + function encode_bit ( + signal bit_cnt : integer; -- sub-frame bit position + signal valid : std_logic; -- validity bit + signal frame_cnt : integer; -- frame counter + signal par_cnt : integer; -- parity counter + signal user_data : std_logic_vector(191 downto 0); + signal ch_status : std_logic_vector(191 downto 0); + signal audio : std_logic_vector(23 downto 0); + signal toggle : std_logic; + signal prev_spdif : std_logic) -- prev. value of spdif signal + + return std_logic is + variable spdif, next_bit : std_logic; + begin + if bit_cnt > 3 and bit_cnt < 28 then -- audio part + next_bit := audio(bit_cnt - 4); + elsif bit_cnt = 28 then -- validity bit + next_bit := valid; + elsif bit_cnt = 29 then -- user data + next_bit := user_data(frame_cnt); + elsif bit_cnt = 30 then + next_bit := ch_status(frame_cnt); -- channel status + elsif bit_cnt = 31 then + if par_cnt mod 2 = 1 then + next_bit := '1'; + else + next_bit := '0'; + end if; + end if; + -- bi-phase mark encoding: + if next_bit = '0' then + if toggle = '0' then + spdif := not prev_spdif; + else + spdif := prev_spdif; + end if; + else + spdif := not prev_spdif; + end if; + return(spdif); + end encode_bit; + +begin + +-- SPDIF clock enable generation. The clock is a fraction of the data clock, +-- determined by the conf_ratio value. + DCLK : process (data_clk) + begin + if rising_edge(data_clk) then + cdc_sync_stage0_tick_counter <= not cdc_sync_stage0_tick_counter; + end if; + end process DCLK; + + process (up_clk) begin + if rising_edge(up_clk) then + cdc_sync_stage1_tick_counter <= cdc_sync_stage0_tick_counter; + cdc_sync_stage2_tick_counter <= cdc_sync_stage1_tick_counter; + cdc_sync_stage3_tick_counter <= cdc_sync_stage2_tick_counter; + end if; + end process; + + tick_counter <= cdc_sync_stage3_tick_counter xor cdc_sync_stage2_tick_counter; + + CGEN: process (up_clk) + begin + if rising_edge(up_clk) then + if resetn = '0' or conf_txen = '0' then + clk_cnt <= 0; + spdif_clk_en <= '0'; + else + spdif_clk_en <= '0'; + + if tick_counter = '1' then + if clk_cnt < to_integer(unsigned(conf_ratio)) then + clk_cnt <= clk_cnt + 1; + else + clk_cnt <= 0; + spdif_clk_en <= '1'; + end if; + end if; + end if; + end if; + end process CGEN; + + SRD: process (up_clk) + begin + if rising_edge(up_clk) then + if resetn = '0' or conf_txdata = '0' then + bufctrl <= IDLE; + sample_data_ack <= '0'; + channel <= '0'; + else + case bufctrl is + when IDLE => + sample_data_ack <= '0'; + if conf_txdata = '1' then + bufctrl <= READ_CHA; + sample_data_ack <='1'; + end if; + when READ_CHA => + channel <= '0'; + sample_data_ack <= '0'; + bufctrl <= CHA_RDY; + when CHA_RDY => + if cha_samp_ack = '1' then + sample_data_ack <= '1'; + bufctrl <= READ_CHB; + end if; + when READ_CHB => + channel <= '1'; + sample_data_ack <= '0'; + bufctrl <= CHB_RDY; + when CHB_RDY => + if chb_samp_ack = '1' then + sample_data_ack <= '1'; + bufctrl <= READ_CHA; + end if; + when others => + bufctrl <= IDLE; + end case; + end if; + end if; + end process SRD; + + TXSYNC: process (data_clk) + begin + if (rising_edge(data_clk)) then + spdif_tx_o <= spdif_out; + end if; + end process TXSYNC; + +-- State machine that generates sub-frames and blocks + + FRST: process (up_clk) + begin + if rising_edge(up_clk) then + if resetn = '0' or conf_txen = '0' then + framest <= IDLE; + frame_cnt <= 0; + bit_cnt <= 0; + spdif_out <= '0'; + inv_preamble <= '0'; + toggle <= '0'; + valid <= '1'; + send_audio <= '0'; + cha_samp_ack <= '0'; + chb_samp_ack <= '0'; + else + if spdif_clk_en = '1' then -- SPDIF clock is twice the bit rate + case framest is + when IDLE => + bit_cnt <= 0; + frame_cnt <= 0; + inv_preamble <= '0'; + toggle <= '0'; + framest <= BLOCK_START; + when BLOCK_START => -- Start of channels status block/Ch. A + chb_samp_ack <= '0'; + toggle <= not toggle; -- Each bit uses two clock enables, + if toggle = '1' then -- counted by the toggle bit. + if bit_cnt < 31 then + bit_cnt <= bit_cnt + 1; + else + bit_cnt <= 0; + if send_audio = '1' then + cha_samp_ack <= '1'; + end if; + framest <= CHANNEL_B; + end if; + end if; + -- Block start uses preamble Z. + if bit_cnt < 4 then + if toggle = '0' then + spdif_out <= Z_PREAMBLE(2 * bit_cnt) xor inv_preamble; + else + spdif_out <= Z_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble; + end if; + par_cnt <= 0; + elsif bit_cnt > 3 and bit_cnt <= 31 then + spdif_out <= encode_bit(bit_cnt, valid, frame_cnt, + par_cnt, active_user_data, + active_ch_status, + audio, toggle, spdif_out); + if bit_cnt = 31 then + inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt, + par_cnt, active_user_data, + active_ch_status, + audio, toggle, spdif_out); + end if; + if toggle = '0' then + if bit_cnt > 3 and bit_cnt < 31 and + par_vector(bit_cnt - 4) = '1' then + par_cnt <= par_cnt + 1; + end if; + end if; + end if; + when CHANNEL_A => -- Sub-frame: channel A. + chb_samp_ack <= '0'; + toggle <= not toggle; + if toggle = '1' then + if bit_cnt < 31 then + bit_cnt <= bit_cnt + 1; + else + bit_cnt <= 0; + if spdif_out = '1' then + inv_preamble <= '1'; + else + inv_preamble <= '0'; + end if; + if send_audio = '1' then + cha_samp_ack <= '1'; + end if; + framest <= CHANNEL_B; + end if; + end if; + -- Channel A uses preable X. + if bit_cnt < 4 then + if toggle = '0' then + spdif_out <= X_PREAMBLE(2 * bit_cnt) xor inv_preamble; + else + spdif_out <= X_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble; + end if; + par_cnt <= 0; + elsif bit_cnt > 3 and bit_cnt <= 31 then + spdif_out <= encode_bit(bit_cnt, valid, frame_cnt, + par_cnt, active_user_data, + active_ch_status, + audio, toggle, spdif_out); + if bit_cnt = 31 then + inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt, + par_cnt, active_user_data, + active_ch_status, + audio, toggle, spdif_out); + end if; + if toggle = '0' then + if bit_cnt > 3 and bit_cnt < 31 and + par_vector(bit_cnt - 4) = '1' then + par_cnt <= par_cnt + 1; + end if; + end if; + end if; + when CHANNEL_B => -- Sub-frame: channel B. + cha_samp_ack <= '0'; + toggle <= not toggle; + if toggle = '1' then + if bit_cnt < 31 then + bit_cnt <= bit_cnt + 1; + else + bit_cnt <= 0; + valid <= not conf_txdata; + if spdif_out = '1' then + inv_preamble <= '1'; + else + inv_preamble <= '0'; + end if; + send_audio <= conf_txdata; -- 1 if audio samples sohuld be sent + if send_audio = '1' then + chb_samp_ack <= '1'; + end if; + if frame_cnt < 191 then -- One block is 192 frames + frame_cnt <= frame_cnt + 1; + framest <= CHANNEL_A; + else + frame_cnt <= 0; + framest <= BLOCK_START; + end if; + end if; + end if; + -- Channel B uses preable Y. + if bit_cnt < 4 then + if toggle = '0' then + spdif_out <= Y_PREAMBLE(2 * bit_cnt) xor inv_preamble; + else + spdif_out <= Y_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble; + end if; + par_cnt <= 0; + elsif bit_cnt > 3 and bit_cnt <= 31 then + spdif_out <= encode_bit(bit_cnt, valid, frame_cnt, + par_cnt, active_user_data, + active_ch_status, + audio, toggle, spdif_out); + if bit_cnt = 31 then + inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt, + par_cnt, active_user_data, + active_ch_status, + audio, toggle, spdif_out); + end if; + if toggle = '0' then + if bit_cnt > 3 and bit_cnt < 31 and + par_vector(bit_cnt - 4) = '1' then + par_cnt <= par_cnt + 1; + end if; + end if; + end if; + when others => + framest <= IDLE; + end case; + end if; + end if; + end if; + end process FRST; + +-- Audio data latching + DA32: if DATA_WIDTH = 32 generate + ALAT: process (up_clk) + begin + if rising_edge(up_clk) then + if send_audio = '0' then + audio(23 downto 0) <= (others => '0'); + else + case to_integer(unsigned(conf_mode)) is + when 0 => -- 16 bit audio + audio(23 downto 8) <= sample_data(15 downto 0); + audio(7 downto 0) <= (others => '0'); + when 1 => -- 17 bit audio + audio(23 downto 7) <= sample_data(16 downto 0); + audio(6 downto 0) <= (others => '0'); + when 2 => -- 18 bit audio + audio(23 downto 6) <= sample_data(17 downto 0); + audio(5 downto 0) <= (others => '0'); + when 3 => -- 19 bit audio + audio(23 downto 5) <= sample_data(18 downto 0); + audio(4 downto 0) <= (others => '0'); + when 4 => -- 20 bit audio + audio(23 downto 4) <= sample_data(19 downto 0); + audio(3 downto 0) <= (others => '0'); + when 5 => -- 21 bit audio + audio(23 downto 3) <= sample_data(20 downto 0); + audio(2 downto 0) <= (others => '0'); + when 6 => -- 22 bit audio + audio(23 downto 2) <= sample_data(21 downto 0); + audio(1 downto 0) <= (others => '0'); + when 7 => -- 23 bit audio + audio(23 downto 1) <= sample_data(22 downto 0); + audio(0) <= '0'; + when 8 => -- 24 bit audio + audio(23 downto 0) <= sample_data(23 downto 0); + when others => -- unsupported modes + audio(23 downto 0) <= (others => '0'); + end case; + end if; + end if; + end process ALAT; + end generate DA32; + + DA16: if DATA_WIDTH = 16 generate + ALAT: process (up_clk) + begin + if rising_edge(up_clk) then + if send_audio = '0' then + audio(23 downto 0) <= (others => '0'); + else + audio(23 downto 8) <= sample_data(15 downto 0); + audio(7 downto 0) <= (others => '0'); + end if; + end if; + end process ALAT; + end generate DA16; + +-- Parity vector. These bits are counted to generate even parity + par_vector(23 downto 0) <= audio(23 downto 0); + par_vector(24) <= valid; + par_vector(25) <= active_user_data(frame_cnt); + par_vector(26) <= active_ch_status(frame_cnt); + +-- Channel status and user datat to be used if buffers are disabled. +-- User data is then all zero, while channel status bits are taken from +-- register TxChStat. + def_user_data(191 downto 0) <= (others => '0'); + def_ch_status(0) <= '0'; -- consumer mode + def_ch_status(1) <= chstat_audio; -- audio bit + def_ch_status(2) <= chstat_copy; -- copy right + def_ch_status(5 downto 3) <= "000" when chstat_preem = '0' + else "001"; -- pre-emphasis + def_ch_status(7 downto 6) <= "00"; + def_ch_status(14 downto 8) <= (others => '0'); + def_ch_status(15) <= chstat_gstat; -- generation status + def_ch_status(23 downto 16) <= (others => '0'); + def_ch_status(27 downto 24) <= "0000" when chstat_freq = "00" else + "0010" when chstat_freq = "01" else + "0011" when chstat_freq = "10" else + "0001"; + def_ch_status(191 downto 28) <= (others => '0'); --191 28 + +-- Generate channel status vector based on configuration register setting. + active_ch_status <= def_ch_status; + +-- Generate user data vector based on configuration register setting. + active_user_data <= def_user_data; + +end rtl; diff --git a/adi_library/axi_spdif_tx/tx_package.vhd b/adi_library/axi_spdif_tx/tx_package.vhd new file mode 100644 index 00000000..2e658590 --- /dev/null +++ b/adi_library/axi_spdif_tx/tx_package.vhd @@ -0,0 +1,88 @@ +---------------------------------------------------------------------- +---- ---- +---- WISHBONE SPDIF IP Core ---- +---- ---- +---- This file is part of the SPDIF project ---- +---- http://www.opencores.org/cores/spdif_interface/ ---- +---- ---- +---- Description ---- +---- SPDIF transmitter component package. ---- +---- ---- +---- ---- +---- To Do: ---- +---- - ---- +---- ---- +---- Author(s): ---- +---- - Geir Drange, gedra@opencores.org ---- +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- +---- ---- +---- This source file may be used and distributed without ---- +---- restriction provided that this copyright statement is not ---- +---- removed from the file and that any derivative work contains ---- +---- the original copyright notice and the associated disclaimer. ---- +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU Lesser General ---- +---- Public License as published by the Free Software Foundation; ---- +---- either version 2.1 of the License, or (at your option) any ---- +---- later version. ---- +---- ---- +---- This source is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU Lesser General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU Lesser General ---- +---- Public License along with this source; if not, download it ---- +---- from http://www.opencores.org/lgpl.shtml ---- +---- ---- +---------------------------------------------------------------------- +-- +-- CVS Revision History +-- +-- $Log: not supported by cvs2svn $ +-- Revision 1.2 2004/07/14 17:58:49 gedra +-- Added new components. +-- +-- Revision 1.1 2004/07/13 18:30:25 gedra +-- Transmitter component declarations. +-- +-- +-- + +library ieee; +use ieee.std_logic_1164.all; + +package tx_package is + + component tx_encoder + generic + ( + DATA_WIDTH: integer range 16 to 32 := 32 + ); + port + ( + up_clk: in std_logic; -- clock + data_clk : in std_logic; -- data clock + resetn : in std_logic; -- resetn + conf_mode: in std_logic_vector(3 downto 0); -- sample format + conf_ratio: in std_logic_vector(7 downto 0); -- clock divider + conf_txdata: in std_logic; -- sample data enable + conf_txen: in std_logic; -- spdif signal enable + chstat_freq: in std_logic_vector(1 downto 0); -- sample freq. + chstat_gstat: in std_logic; -- generation status + chstat_preem: in std_logic; -- preemphasis status + chstat_copy: in std_logic; -- copyright bit + chstat_audio: in std_logic; -- data format + sample_data: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data + sample_data_ack : out std_logic; -- sample buffer read + channel: out std_logic; + spdif_tx_o: out std_logic + ); + end component; + +end tx_package; diff --git a/adi_library/axi_spdif_tx/xgui/axi_spdif_tx_v1_0.tcl b/adi_library/axi_spdif_tx/xgui/axi_spdif_tx_v1_0.tcl new file mode 100644 index 00000000..3cfd752c --- /dev/null +++ b/adi_library/axi_spdif_tx/xgui/axi_spdif_tx_v1_0.tcl @@ -0,0 +1,70 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DEVICE_FAMILY" -parent ${Page_0} + ipgui::add_param $IPINST -name "DMA_TYPE" -parent ${Page_0} + ipgui::add_param $IPINST -name "S_AXI_ADDRESS_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "S_AXI_DATA_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DEVICE_FAMILY { PARAM_VALUE.DEVICE_FAMILY } { + # Procedure called to update DEVICE_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEVICE_FAMILY { PARAM_VALUE.DEVICE_FAMILY } { + # Procedure called to validate DEVICE_FAMILY + return true +} + +proc update_PARAM_VALUE.DMA_TYPE { PARAM_VALUE.DMA_TYPE } { + # Procedure called to update DMA_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_TYPE { PARAM_VALUE.DMA_TYPE } { + # Procedure called to validate DMA_TYPE + return true +} + +proc update_PARAM_VALUE.S_AXI_ADDRESS_WIDTH { PARAM_VALUE.S_AXI_ADDRESS_WIDTH } { + # Procedure called to update S_AXI_ADDRESS_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.S_AXI_ADDRESS_WIDTH { PARAM_VALUE.S_AXI_ADDRESS_WIDTH } { + # Procedure called to validate S_AXI_ADDRESS_WIDTH + return true +} + +proc update_PARAM_VALUE.S_AXI_DATA_WIDTH { PARAM_VALUE.S_AXI_DATA_WIDTH } { + # Procedure called to update S_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.S_AXI_DATA_WIDTH { PARAM_VALUE.S_AXI_DATA_WIDTH } { + # Procedure called to validate S_AXI_DATA_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.S_AXI_DATA_WIDTH { MODELPARAM_VALUE.S_AXI_DATA_WIDTH PARAM_VALUE.S_AXI_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.S_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.S_AXI_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.S_AXI_ADDRESS_WIDTH { MODELPARAM_VALUE.S_AXI_ADDRESS_WIDTH PARAM_VALUE.S_AXI_ADDRESS_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.S_AXI_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.S_AXI_ADDRESS_WIDTH} +} + +proc update_MODELPARAM_VALUE.DEVICE_FAMILY { MODELPARAM_VALUE.DEVICE_FAMILY PARAM_VALUE.DEVICE_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEVICE_FAMILY}] ${MODELPARAM_VALUE.DEVICE_FAMILY} +} + +proc update_MODELPARAM_VALUE.DMA_TYPE { MODELPARAM_VALUE.DMA_TYPE PARAM_VALUE.DMA_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_TYPE}] ${MODELPARAM_VALUE.DMA_TYPE} +} + diff --git a/adi_library/axi_sysid/Makefile b/adi_library/axi_sysid/Makefile new file mode 100644 index 00000000..5df24131 --- /dev/null +++ b/adi_library/axi_sysid/Makefile @@ -0,0 +1,16 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_sysid + +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += axi_sysid.v + +XILINX_DEPS += axi_sysid_ip.tcl + +INTEL_DEPS += axi_sysid_hw.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_sysid/axi_sysid.v b/adi_library/axi_sysid/axi_sysid.v new file mode 100755 index 00000000..dbb52283 --- /dev/null +++ b/adi_library/axi_sysid/axi_sysid.v @@ -0,0 +1,171 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** + +`timescale 1ns / 1ps + +module axi_sysid #( + parameter ROM_WIDTH = 32, + parameter ROM_ADDR_BITS = 9 +) ( + //axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + input [2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + input [2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + + input [ROM_WIDTH-1:0] sys_rom_data, + input [ROM_WIDTH-1:0] pr_rom_data, + output [ROM_ADDR_BITS-1:0] rom_addr +); + + localparam AXI_ADDRESS_WIDTH = 12; + localparam [31:0] CORE_VERSION = {16'h0001, /* MAJOR */ + 8'h01, /* MINOR */ + 8'h61}; /* PATCH */ + localparam [31:0] CORE_MAGIC = 32'h53594944; // SYID + + reg up_wack = 'd0; + reg [31:0] up_rdata_s = 'd0; + reg up_rack_s = 'd0; + reg up_rreq_s_d = 'd0; + reg [31:0] up_scratch = 'd0; + + wire up_clk; + wire up_rstn; + wire up_rreq_s; + wire [(ROM_ADDR_BITS+1):0] up_raddr_s; + wire up_wreq_s; + wire [(ROM_ADDR_BITS+1):0] up_waddr_s; + wire [31:0] up_wdata_s; + wire [31:0] rom_data_s; + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + assign rom_addr = up_raddr_s [ROM_ADDR_BITS-1:0]; + assign rom_data_s = (up_raddr_s [ROM_ADDR_BITS + 1'h1: ROM_ADDR_BITS] == 2'h1) ? sys_rom_data : + (up_raddr_s [ROM_ADDR_BITS + 1'h1: ROM_ADDR_BITS] == 2'h2) ? pr_rom_data : 'h0; + + up_axi #( + .AXI_ADDRESS_WIDTH(ROM_ADDR_BITS+4) + ) i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr[ROM_ADDR_BITS+3:0]), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr[ROM_ADDR_BITS+3:0]), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + + //delaying data read with 1 tck to compensate for the ROM latency + always @(posedge up_clk) begin + up_rreq_s_d <= up_rreq_s; + end + + //axi registers read + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_rack_s <= 'd0; + up_rdata_s <= 'd0; + end else begin + up_rack_s <= up_rreq_s_d; + if (up_rreq_s_d == 1'b1) begin + case (up_raddr_s) + 8'h00: up_rdata_s <= CORE_VERSION; + 8'h01: up_rdata_s <= 0; + 8'h02: up_rdata_s <= up_scratch; + 8'h03: up_rdata_s <= CORE_MAGIC; + 8'h10: up_rdata_s <= ROM_ADDR_BITS; + default: begin + up_rdata_s <= rom_data_s; + end + endcase + end else begin + up_rdata_s <= 32'd0; + end + end + end + + //axi registers write + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_wack <= 'd0; + up_scratch <= 'd0; + end else begin + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h02)) begin + up_scratch <= up_wdata_s; + end + end + end + +endmodule diff --git a/adi_library/axi_sysid/axi_sysid.xpr b/adi_library/axi_sysid/axi_sysid.xpr new file mode 100644 index 00000000..efdcee84 --- /dev/null +++ b/adi_library/axi_sysid/axi_sysid.xpr @@ -0,0 +1,406 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_sysid/axi_sysid_hw.tcl b/adi_library/axi_sysid/axi_sysid_hw.tcl new file mode 100644 index 00000000..0a619287 --- /dev/null +++ b/adi_library/axi_sysid/axi_sysid_hw.tcl @@ -0,0 +1,43 @@ +############################################################################### +## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +source ../../scripts/adi_env.tcl +source ../scripts/adi_ip_intel.tcl + +set_module_property NAME axi_sysid +set_module_property DESCRIPTION "AXI System ID" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME axi_sysid + +# source files + +ad_ip_files axi_sysid [list \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "axi_sysid.v"] + +# IP parameters + +add_parameter ROM_WIDTH INTEGER 32 +set_parameter_property ROM_WIDTH DEFAULT_VALUE 32 +set_parameter_property ROM_WIDTH DISPLAY_NAME "ROM width" +set_parameter_property ROM_WIDTH UNITS None +set_parameter_property ROM_WIDTH HDL_PARAMETER true + +add_parameter ROM_ADDR_BITS INTEGER 9 +set_parameter_property ROM_ADDR_BITS DEFAULT_VALUE 9 +set_parameter_property ROM_ADDR_BITS DISPLAY_NAME "ROM address bits" +set_parameter_property ROM_ADDR_BITS HDL_PARAMETER true + +# AXI4 Memory Mapped Interface + +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 15 + +# external clock and control/status ports + +ad_interface signal sys_rom_data input ROM_WIDTH rom_data +ad_interface signal pr_rom_data input ROM_WIDTH rom_data +ad_interface signal rom_addr output ROM_ADDR_BITS diff --git a/adi_library/axi_sysid/axi_sysid_ip.tcl b/adi_library/axi_sysid/axi_sysid_ip.tcl new file mode 100644 index 00000000..1a214a36 --- /dev/null +++ b/adi_library/axi_sysid/axi_sysid_ip.tcl @@ -0,0 +1,21 @@ +############################################################################### +## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_sysid +adi_ip_files axi_sysid [list \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "axi_sysid.v"] + +adi_ip_properties axi_sysid + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_sysid} [ipx::current_core] + +set cc [ipx::current_core] + +ipx::save_core $cc diff --git a/adi_library/axi_sysid/component.xml b/adi_library/axi_sysid/component.xml new file mode 100644 index 00000000..29996413 --- /dev/null +++ b/adi_library/axi_sysid/component.xml @@ -0,0 +1,799 @@ + + + analog.com + user + axi_sysid + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_sysid + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 9f64853d + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_sysid + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 9f64853d + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 314db68d + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + sys_rom_data + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + pr_rom_data + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + rom_addr + + out + + 8 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + ROM_WIDTH + Rom Width + 32 + + + ROM_ADDR_BITS + Rom Addr Bits + 9 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../common/up_axi.v + verilogSource + + + axi_sysid.v + verilogSource + CHECKSUM_623df4b4 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/up_axi.v + verilogSource + + + axi_sysid.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_sysid_v1_0.tcl + tclSource + CHECKSUM_314db68d + XGUI_VERSION_2 + + + + axi_sysid_v1_0 + + + ROM_WIDTH + Rom Width + 32 + + + ROM_ADDR_BITS + Rom Addr Bits + 9 + + + Component_Name + axi_sysid_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_sysid_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_sysid + 1 + 2024-01-14T03:49:19Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_sysid/readme.rst b/adi_library/axi_sysid/readme.rst new file mode 100644 index 00000000..ba5086ff --- /dev/null +++ b/adi_library/axi_sysid/readme.rst @@ -0,0 +1,5 @@ +============= +AXI System ID +============= + +System Identification IP core diff --git a/adi_library/axi_sysid/xgui/axi_sysid_v1_0.tcl b/adi_library/axi_sysid/xgui/axi_sysid_v1_0.tcl new file mode 100644 index 00000000..4dc38783 --- /dev/null +++ b/adi_library/axi_sysid/xgui/axi_sysid_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ROM_ADDR_BITS" -parent ${Page_0} + ipgui::add_param $IPINST -name "ROM_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.ROM_ADDR_BITS { PARAM_VALUE.ROM_ADDR_BITS } { + # Procedure called to update ROM_ADDR_BITS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ROM_ADDR_BITS { PARAM_VALUE.ROM_ADDR_BITS } { + # Procedure called to validate ROM_ADDR_BITS + return true +} + +proc update_PARAM_VALUE.ROM_WIDTH { PARAM_VALUE.ROM_WIDTH } { + # Procedure called to update ROM_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ROM_WIDTH { PARAM_VALUE.ROM_WIDTH } { + # Procedure called to validate ROM_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.ROM_WIDTH { MODELPARAM_VALUE.ROM_WIDTH PARAM_VALUE.ROM_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ROM_WIDTH}] ${MODELPARAM_VALUE.ROM_WIDTH} +} + +proc update_MODELPARAM_VALUE.ROM_ADDR_BITS { MODELPARAM_VALUE.ROM_ADDR_BITS PARAM_VALUE.ROM_ADDR_BITS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ROM_ADDR_BITS}] ${MODELPARAM_VALUE.ROM_ADDR_BITS} +} + diff --git a/adi_library/axi_tdd/Makefile b/adi_library/axi_tdd/Makefile new file mode 100644 index 00000000..8649c70b --- /dev/null +++ b/adi_library/axi_tdd/Makefile @@ -0,0 +1,26 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_tdd + +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += ../util_cdc/sync_bits.v +GENERIC_DEPS += ../util_cdc/sync_data.v +GENERIC_DEPS += ../util_cdc/sync_event.v +GENERIC_DEPS += axi_tdd.sv +GENERIC_DEPS += axi_tdd_channel.sv +GENERIC_DEPS += axi_tdd_counter.sv +GENERIC_DEPS += axi_tdd_pkg.sv +GENERIC_DEPS += axi_tdd_regmap.sv +GENERIC_DEPS += axi_tdd_sync_gen.sv + +XILINX_DEPS += axi_tdd_constr.ttcl +XILINX_DEPS += axi_tdd_ip.tcl + +INTEL_DEPS += axi_tdd_constr.sdc +INTEL_DEPS += axi_tdd_hw.tcl + +include ../scripts/library.mk diff --git a/adi_library/axi_tdd/axi_tdd.sv b/adi_library/axi_tdd/axi_tdd.sv new file mode 100644 index 00000000..532f1e3f --- /dev/null +++ b/adi_library/axi_tdd/axi_tdd.sv @@ -0,0 +1,293 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module axi_tdd #( + + // Peripheral ID + parameter ID = 0, + + // Number of active channels + parameter CHANNEL_COUNT = 8, + + // Default polarity per channel + parameter DEFAULT_POLARITY = 8'h00, + + // Timing register width, determines how long a single frame can be. + // T_max = (2^REGISTER_WIDTH) / f_clk + parameter REGISTER_WIDTH = 32, + + // Burst count register width. Determines the maximum amount of repetitions + // of a frame. + parameter BURST_COUNT_WIDTH = 32, + + // Synchronization / triggering options. These are not mutually exclusive, and + // both internal and external triggering can be available and selected at + // runtime. + parameter SYNC_INTERNAL = 1, + parameter SYNC_EXTERNAL = 0, + // Whether to insert a CDC stage with false path constraint for the external + // synchronization input. + parameter SYNC_EXTERNAL_CDC = 0, + parameter SYNC_COUNT_WIDTH = 64 +) ( + + input logic clk, + input logic resetn, + + // Sync signal + input logic sync_in, + output logic sync_out, + + // Output channels + output logic [CHANNEL_COUNT-1:0] tdd_channel, + + // AXI BUS + input logic s_axi_aresetn, + input logic s_axi_aclk, + input logic s_axi_awvalid, + input logic [ 9:0] s_axi_awaddr, + input logic [ 2:0] s_axi_awprot, + output logic s_axi_awready, + input logic s_axi_wvalid, + input logic [31:0] s_axi_wdata, + input logic [ 3:0] s_axi_wstrb, + output logic s_axi_wready, + output logic s_axi_bvalid, + output logic [ 1:0] s_axi_bresp, + input logic s_axi_bready, + input logic s_axi_arvalid, + input logic [ 9:0] s_axi_araddr, + input logic [ 2:0] s_axi_arprot, + output logic s_axi_arready, + output logic s_axi_rvalid, + output logic [ 1:0] s_axi_rresp, + output logic [31:0] s_axi_rdata, + input logic s_axi_rready +); + + // Package import + import axi_tdd_pkg::*; + + // Internal up bus, translated by up_axi + logic up_rstn; + logic up_clk; + logic up_wreq; + logic [ 7:0] up_waddr; + logic [31:0] up_wdata; + logic up_wack; + logic up_rreq; + logic [ 7:0] up_raddr; + logic [31:0] up_rdata; + logic up_rack; + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // Control signals + logic tdd_enable; + logic tdd_sync_rst; + logic tdd_sync_int; + logic tdd_sync_ext; + logic tdd_sync_soft; + + // Config wires + logic [BURST_COUNT_WIDTH-1:0] asy_tdd_burst_count; + logic [REGISTER_WIDTH-1:0] asy_tdd_startup_delay; + logic [REGISTER_WIDTH-1:0] asy_tdd_frame_length; + + // Synchronization config + logic [SYNC_COUNT_WIDTH-1:0] asy_tdd_sync_period; + + // Channel config + logic [CHANNEL_COUNT-1:0] tdd_channel_en; + logic [CHANNEL_COUNT-1:0] asy_tdd_channel_pol; + logic [REGISTER_WIDTH-1:0] asy_tdd_channel_on [0:CHANNEL_COUNT-1]; + logic [REGISTER_WIDTH-1:0] asy_tdd_channel_off [0:CHANNEL_COUNT-1]; + + // Current counter value + logic [REGISTER_WIDTH-1:0] tdd_counter; + + // Current FSM state + state_t tdd_cstate; + + // Asserted to indicate the end of a tdd frame. This allows the channels to + // reset outputs which are still open due to a potential misconfiguration. + logic tdd_endof_frame; + + axi_tdd_regmap #( + .ID (ID), + .CHANNEL_COUNT (CHANNEL_COUNT), + .DEFAULT_POLARITY (DEFAULT_POLARITY), + .REGISTER_WIDTH (REGISTER_WIDTH), + .BURST_COUNT_WIDTH (BURST_COUNT_WIDTH), + .SYNC_INTERNAL (SYNC_INTERNAL), + .SYNC_EXTERNAL (SYNC_EXTERNAL), + .SYNC_EXTERNAL_CDC (SYNC_EXTERNAL_CDC), + .SYNC_COUNT_WIDTH (SYNC_COUNT_WIDTH) + ) i_regmap ( + .up_rstn (up_rstn), + .up_clk (up_clk), + + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack), + + .tdd_clk (clk), + .tdd_resetn (resetn), + + .tdd_cstate (tdd_cstate), + + .tdd_enable (tdd_enable), + + .tdd_channel_en (tdd_channel_en), + .asy_tdd_channel_pol (asy_tdd_channel_pol), + + .asy_tdd_burst_count (asy_tdd_burst_count), + .asy_tdd_startup_delay (asy_tdd_startup_delay), + .asy_tdd_frame_length (asy_tdd_frame_length), + + .asy_tdd_channel_on (asy_tdd_channel_on), + .asy_tdd_channel_off (asy_tdd_channel_off), + + .asy_tdd_sync_period (asy_tdd_sync_period), + + .tdd_sync_rst (tdd_sync_rst), + .tdd_sync_int (tdd_sync_int), + .tdd_sync_ext (tdd_sync_ext), + .tdd_sync_soft (tdd_sync_soft)); + + axi_tdd_counter #( + .REGISTER_WIDTH (REGISTER_WIDTH), + .BURST_COUNT_WIDTH (BURST_COUNT_WIDTH) + ) i_counter ( + .clk (clk), + .resetn (resetn), + + .tdd_enable (tdd_enable), + .tdd_sync_rst (tdd_sync_rst), + .tdd_sync (sync_out), + + .asy_tdd_burst_count (asy_tdd_burst_count), + .asy_tdd_startup_delay (asy_tdd_startup_delay), + .asy_tdd_frame_length (asy_tdd_frame_length), + + .tdd_counter (tdd_counter), + .tdd_cstate (tdd_cstate), + .tdd_endof_frame (tdd_endof_frame)); + + axi_tdd_sync_gen #( + .SYNC_INTERNAL (SYNC_INTERNAL), + .SYNC_EXTERNAL (SYNC_EXTERNAL), + .SYNC_EXTERNAL_CDC (SYNC_EXTERNAL_CDC), + .SYNC_COUNT_WIDTH (SYNC_COUNT_WIDTH) + ) i_sync_gen ( + .clk (clk), + .resetn (resetn), + + .sync_in (sync_in), + .sync_out (sync_out), + + .tdd_enable (tdd_enable), + .tdd_sync_int (tdd_sync_int), + .tdd_sync_ext (tdd_sync_ext), + .tdd_sync_soft (tdd_sync_soft), + + .asy_tdd_sync_period (asy_tdd_sync_period)); + + genvar i; + generate + for (i = 0; i < CHANNEL_COUNT; i=i+1) begin + axi_tdd_channel #( + .DEFAULT_POLARITY (DEFAULT_POLARITY[i]), + .REGISTER_WIDTH (REGISTER_WIDTH) + ) i_channel ( + .clk (clk), + .resetn (resetn), + + .tdd_counter (tdd_counter), + .tdd_cstate (tdd_cstate), + .tdd_enable (tdd_enable), + .tdd_endof_frame (tdd_endof_frame), + + .ch_en (tdd_channel_en[i]), + .asy_ch_pol (asy_tdd_channel_pol[i]), + .asy_t_high (asy_tdd_channel_on[i]), + .asy_t_low (asy_tdd_channel_off[i]), + + .out (tdd_channel[i])); + end + endgenerate + + up_axi #( + .AXI_ADDRESS_WIDTH(10) + ) i_up_axi ( + .up_rstn(s_axi_aresetn), + .up_clk(s_axi_aclk), + + .up_axi_awvalid(s_axi_awvalid), + .up_axi_awaddr(s_axi_awaddr), + .up_axi_awready(s_axi_awready), + .up_axi_wvalid(s_axi_wvalid), + .up_axi_wdata(s_axi_wdata), + .up_axi_wstrb(s_axi_wstrb), + .up_axi_wready(s_axi_wready), + .up_axi_bvalid(s_axi_bvalid), + .up_axi_bresp(s_axi_bresp), + .up_axi_bready(s_axi_bready), + .up_axi_arvalid(s_axi_arvalid), + .up_axi_araddr(s_axi_araddr), + .up_axi_arready(s_axi_arready), + .up_axi_rvalid(s_axi_rvalid), + .up_axi_rresp(s_axi_rresp), + .up_axi_rdata(s_axi_rdata), + .up_axi_rready(s_axi_rready), + + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_wack(up_wack), + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata), + .up_rack(up_rack)); + +endmodule diff --git a/adi_library/axi_tdd/axi_tdd.xpr b/adi_library/axi_tdd/axi_tdd.xpr new file mode 100644 index 00000000..bf072537 --- /dev/null +++ b/adi_library/axi_tdd/axi_tdd.xpr @@ -0,0 +1,469 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/axi_tdd/axi_tdd_channel.sv b/adi_library/axi_tdd/axi_tdd_channel.sv new file mode 100644 index 00000000..668dd672 --- /dev/null +++ b/adi_library/axi_tdd/axi_tdd_channel.sv @@ -0,0 +1,168 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +`timescale 1ns/1ps + +module axi_tdd_channel #( + parameter DEFAULT_POLARITY = 0, + parameter REGISTER_WIDTH = 32 +) ( + + input logic clk, + input logic resetn, + + input logic [REGISTER_WIDTH-1:0] tdd_counter, + input axi_tdd_pkg::state_t tdd_cstate, + input logic tdd_enable, + input logic tdd_endof_frame, + + input logic ch_en, + input logic asy_ch_pol, + input logic [REGISTER_WIDTH-1:0] asy_t_high, + input logic [REGISTER_WIDTH-1:0] asy_t_low, + + output logic out +); + + // package import + import axi_tdd_pkg::*; + + // internal registers + logic ch_pol; + logic [REGISTER_WIDTH-1:0] t_high; + logic [REGISTER_WIDTH-1:0] t_low; + logic tdd_ch_en; + logic tdd_ch_set; + logic tdd_ch_rst; + + // initial values + initial begin + tdd_ch_en = 1'b0; + tdd_ch_set = 1'b0; + tdd_ch_rst = 1'b0; + out = 1'b0; + end + + // Connect the enable signal to the enable flop lines + (* direct_enable = "yes" *) logic enable; + assign enable = tdd_enable; + + // Save the async register values only when the module is enabled + always @(posedge clk) begin + if (resetn == 1'b0) begin + ch_pol <= DEFAULT_POLARITY; + end else begin + if (enable) begin + ch_pol <= asy_ch_pol; + end + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + t_high <= '0; + end else begin + if (enable) begin + t_high <= asy_t_high; + end + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + t_low <= '0; + end else begin + if (enable) begin + t_low <= asy_t_low; + end + end + end + + // TDD channel control signals + always @(posedge clk) begin + if (resetn == 1'b0) begin + tdd_ch_en <= 1'b0; + end else begin + if (tdd_cstate == IDLE) begin + tdd_ch_en <= 1'b0; + end else begin + if ((tdd_cstate == ARMED) || (tdd_endof_frame == 1'b1)) begin + tdd_ch_en <= ch_en; + end + end + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + tdd_ch_set <= 1'b0; + end else begin + if ((tdd_cstate == RUNNING) && (tdd_counter == t_high)) begin + tdd_ch_set <= 1'b1; + end else begin + tdd_ch_set <= 1'b0; + end + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + tdd_ch_rst <= 1'b0; + end else begin + if (((tdd_cstate == RUNNING) && (tdd_counter == t_low)) || (tdd_endof_frame == 1'b1)) begin + tdd_ch_rst <= 1'b1; + end else begin + tdd_ch_rst <= 1'b0; + end + end + end + + // TDD channel output + always @(posedge clk) begin + if (resetn == 1'b0) begin + out <= DEFAULT_POLARITY; + end else begin + if ((tdd_ch_en == 1'b0) || (tdd_ch_rst == 1'b1)) begin + out <= ch_pol; + end else begin + if (tdd_ch_set == 1'b1) begin + out <= ~ch_pol; + end else begin + out <= out; + end + end + end + end + +endmodule diff --git a/adi_library/axi_tdd/axi_tdd_constr.sdc b/adi_library/axi_tdd/axi_tdd_constr.sdc new file mode 100644 index 00000000..7f076d20 --- /dev/null +++ b/adi_library/axi_tdd/axi_tdd_constr.sdc @@ -0,0 +1,48 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_false_path \ + -from [get_registers {*|i_regmap|up_tdd_burst_count[*]}] \ + -to [get_registers {*|i_counter|tdd_burst_count[*]}] + +set_false_path \ + -from [get_registers {*|i_regmap|up_tdd_startup_delay[*]}] \ + -to [get_registers {*|i_counter|tdd_startup_delay[*]}] + +set_false_path \ + -from [get_registers {*|i_regmap|up_tdd_frame_length[*]}] \ + -to [get_registers {*|i_counter|tdd_frame_length[*]}] + +set_false_path \ + -to [get_registers {*|i_sync_gen|tdd_sync_m1}] + +set_false_path \ + -from [get_registers {*|i_regmap|up_tdd_sync_period_low[*]}] \ + -to [get_registers {*|i_sync_gen|tdd_sync_period[*]}] + +set_false_path \ + -from [get_registers {*|i_regmap|up_tdd_sync_period_high[*]}] \ + -to [get_registers {*|i_sync_gen|tdd_sync_period[*]}] + +set_false_path \ + -from [get_registers {*|i_regmap|up_tdd_channel_pol[*]}] \ + -to [get_registers {*|[*].i_channel|ch_pol}] + +set_false_path \ + -from [get_registers {*|i_regmap|*up_tdd_channel_on[*][*]}] \ + -to [get_registers {*|[*].i_channel|t_high[*]}] + +set_false_path \ + -from [get_registers {*|i_regmap|*up_tdd_channel_off[*][*]}] \ + -to [get_registers {*|[*].i_channel|t_low[*]}] + +util_cdc_sync_bits_constr {*|axi_tdd_regmap:i_regmap|sync_bits:i_tdd_control_sync} + +util_cdc_sync_bits_constr {*|axi_tdd_regmap:i_regmap|sync_bits:i_tdd_ch_en_sync} + +util_cdc_sync_data_constr {*|axi_tdd_regmap:i_regmap|sync_data:i_tdd_cstate_sync} + +util_cdc_sync_event_constr {*|axi_tdd_regmap:i_regmap|sync_event:i_tdd_soft_sync} + diff --git a/adi_library/axi_tdd/axi_tdd_constr.ttcl b/adi_library/axi_tdd/axi_tdd_constr.ttcl new file mode 100644 index 00000000..367bff2f --- /dev/null +++ b/adi_library/axi_tdd/axi_tdd_constr.ttcl @@ -0,0 +1,107 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName [ttcl_add $ComponentName "_constr"] :> +<: setFileExtension ".xdc" :> +<: setFileProcessingOrder late :> +<: set tdd_sync_int [get_property MODELPARAM_VALUE.SYNC_INTERNAL] :> +<: set tdd_sync_ext [get_property MODELPARAM_VALUE.SYNC_EXTERNAL] :> +<: set tdd_sync_cdc [get_property MODELPARAM_VALUE.SYNC_EXTERNAL_CDC] :> +<: set tdd_sync_width [get_property MODELPARAM_VALUE.SYNC_COUNT_WIDTH] :> + +set_property ASYNC_REG TRUE \ + [get_cells -hier {*cdc_sync_stage1_reg*}] \ + [get_cells -hier {*cdc_sync_stage2_reg*}] + +<: if { $tdd_sync_cdc == 1 } { :> +set_property ASYNC_REG TRUE \ + [get_cells -hier {*tdd_sync_m1_reg*}] \ + [get_cells -hier {*tdd_sync_m2_reg*}] \ + [get_cells -hier {*tdd_sync_m3_reg*}] +set_false_path -to [get_cells -hierarchical * -filter {NAME=~*i_sync_gen/tdd_sync_m1_reg}] +<: } :> + +set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_burst_count_reg[*]}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_counter/tdd_burst_count_reg[*]}] + +set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_startup_delay_reg[*]}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_counter/tdd_startup_delay_reg[*]}] + +set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_frame_length_reg[*]}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_counter/tdd_frame_length_reg[*]}] + +<: if { $tdd_sync_width > 0 } { :> +set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_sync_period_low_reg[*]}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_sync_gen/tdd_sync_period_reg[*]}] +<: } :> + +<: if { $tdd_sync_width > 32 } { :> +set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_sync_period_high_reg[*]}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_sync_gen/tdd_sync_period_reg[*]}] +<: } :> + +set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_channel_pol_reg[*]}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_channel/ch_pol_reg}] + +set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/*up_tdd_channel_on_reg[*][*]}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_channel/t_high_reg[*]}] + +set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/*up_tdd_channel_off_reg[*][*]}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_channel/t_low_reg[*]}] + +set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_enable_reg}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_control_sync/cdc_sync_stage1_reg[0]}] + +set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_sync_rst_reg}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_control_sync/cdc_sync_stage1_reg[1]}] + +<: if { $tdd_sync_int == 1 } { :> +set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_sync_int_reg}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_control_sync/cdc_sync_stage1_reg[2]}] +<: } :> + +<: if { $tdd_sync_ext == 1 } { :> +set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_sync_ext_reg}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_control_sync/cdc_sync_stage1_reg[3]}] +<: } :> + +set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/up_tdd_channel_en_reg[*]}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_ch_en_sync/cdc_sync_stage1_reg[*]}] + +set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_cstate_sync/cdc_hold_reg*}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_cstate_sync/out_data_reg*}] + +set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_cstate_sync/in_toggle_d1_reg}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_cstate_sync/i_sync_out/cdc_sync_stage1_reg[*]}] + +set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_cstate_sync/out_toggle_d1_reg}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_cstate_sync/i_sync_in/cdc_sync_stage1_reg[*]}] + +set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_soft_sync/in_toggle_d1_reg}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_soft_sync/i_sync_out/cdc_sync_stage1_reg[*]}] + +set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_soft_sync/out_toggle_d1_reg}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_regmap/i_tdd_soft_sync/i_sync_in/cdc_sync_stage1_reg[*]}] + diff --git a/adi_library/axi_tdd/axi_tdd_counter.sv b/adi_library/axi_tdd/axi_tdd_counter.sv new file mode 100644 index 00000000..0ba133e8 --- /dev/null +++ b/adi_library/axi_tdd/axi_tdd_counter.sv @@ -0,0 +1,243 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +`timescale 1ns/1ps + +module axi_tdd_counter #( + parameter REGISTER_WIDTH = 32, + parameter BURST_COUNT_WIDTH = 32 +) ( + + input logic clk, + input logic resetn, + + input logic tdd_enable, + input logic tdd_sync_rst, + input logic tdd_sync, + + input logic [BURST_COUNT_WIDTH-1:0] asy_tdd_burst_count, + input logic [REGISTER_WIDTH-1:0] asy_tdd_startup_delay, + input logic [REGISTER_WIDTH-1:0] asy_tdd_frame_length, + + output logic [REGISTER_WIDTH-1:0] tdd_counter, + output axi_tdd_pkg::state_t tdd_cstate, + output logic tdd_endof_frame +); + + // package import + import axi_tdd_pkg::*; + + // internal registers/wires + logic [BURST_COUNT_WIDTH-1:0] tdd_burst_count; + logic [REGISTER_WIDTH-1:0] tdd_startup_delay; + logic [REGISTER_WIDTH-1:0] tdd_frame_length; + logic [BURST_COUNT_WIDTH-1:0] tdd_burst_counter; + logic tdd_delay_done; + logic tdd_delay_skip; + logic tdd_endof_burst; + logic tdd_last_burst; + state_t tdd_cstate_ns; + + // initial values + initial begin + tdd_burst_counter = '0; + tdd_counter = '0; + tdd_cstate = IDLE; + tdd_cstate_ns = IDLE; + tdd_delay_done = 1'b0; + tdd_delay_skip = 1'b0; + tdd_endof_frame = 1'b0; + tdd_last_burst = 1'b0; + end + + // Connect the enable signal to the enable flop lines + (* direct_enable = "yes" *) logic enable; + assign enable = tdd_enable; + + // Save the async register values only when the module is enabled + always @(posedge clk) begin + if (resetn == 1'b0) begin + tdd_burst_count <= '0; + end else begin + if (enable) begin + tdd_burst_count <= asy_tdd_burst_count; + end + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + tdd_startup_delay <= '0; + end else begin + if (enable) begin + tdd_startup_delay <= asy_tdd_startup_delay; + end + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + tdd_frame_length <= '0; + end else begin + if (enable) begin + tdd_frame_length <= asy_tdd_frame_length; + end + end + end + + // TDD counter FSM + always @(posedge clk) begin + if (resetn == 1'b0) begin + tdd_cstate <= IDLE; + end else begin + tdd_cstate <= tdd_cstate_ns; + end + end + + always @* begin + tdd_cstate_ns = tdd_cstate; + case (tdd_cstate) + IDLE : begin + if (tdd_enable == 1'b1) begin + tdd_cstate_ns = ARMED; + end + end + + ARMED : begin + if (tdd_enable == 1'b0) begin + tdd_cstate_ns = IDLE; + end else if (tdd_sync == 1'b1) begin + tdd_cstate_ns = (tdd_delay_skip == 1'b1) ? RUNNING : WAITING; + end + end + + WAITING : begin + if (tdd_delay_done == 1'b1) begin + tdd_cstate_ns = RUNNING; + end + end + + RUNNING : begin + if (tdd_endof_frame == 1'b1) begin + tdd_cstate_ns = (tdd_endof_burst == 1'b1) ? (tdd_enable ? ARMED : IDLE) : + (((tdd_burst_counter == 0) && !tdd_enable) ? IDLE : RUNNING); + end + end + endcase + end + + // TDD control signals + always @(posedge clk) begin + if (resetn == 1'b0) begin + tdd_delay_done <= 1'b0; + end else begin + if (tdd_counter == (tdd_startup_delay - 1'b1)) begin + tdd_delay_done <= 1'b1; + end else begin + tdd_delay_done <= 1'b0; + end + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + tdd_delay_skip <= 1'b0; + end else begin + if (tdd_startup_delay == 0) begin + tdd_delay_skip <= 1'b1; + end else begin + tdd_delay_skip <= 1'b0; + end + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + tdd_endof_frame <= 1'b0; + end else begin + if (tdd_counter == (tdd_frame_length - 1'b1)) begin + tdd_endof_frame <= 1'b1; + end else begin + tdd_endof_frame <= 1'b0; + end + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + tdd_last_burst <= 1'b0; + end else begin + tdd_last_burst <= (tdd_burst_counter == 1) ? 1'b1 : 1'b0; + end + end + + assign tdd_endof_burst = ((tdd_last_burst == 1'b1) && (tdd_endof_frame == 1'b1)) ? 1'b1 : 1'b0; + + // TDD free running counter + always @(posedge clk) begin + if (resetn == 1'b0) begin + tdd_counter <= '0; + end else begin + if ((tdd_sync && tdd_sync_rst) == 1'b1) begin + tdd_counter <= '0; + end else begin + if (tdd_cstate == WAITING) begin + tdd_counter <= (tdd_delay_done == 1'b1) ? '0 : tdd_counter + 1'b1; + end else begin + if (tdd_cstate == RUNNING) begin + tdd_counter <= (tdd_endof_frame == 1'b1) ? '0 : tdd_counter + 1'b1; + end else begin + tdd_counter <= '0; + end + end + end + end + end + + // TDD burst counter + always @(posedge clk) begin + if (resetn == 1'b0) begin + tdd_burst_counter <= '0; + end else begin + if (tdd_cstate == ARMED) begin + tdd_burst_counter <= tdd_burst_count; + end else begin + if ((tdd_cstate == RUNNING) && (tdd_burst_counter != 0) && (tdd_endof_frame == 1'b1)) begin + tdd_burst_counter <= tdd_burst_counter - 1'b1; + end + end + end + end + +endmodule diff --git a/adi_library/axi_tdd/axi_tdd_hw.tcl b/adi_library/axi_tdd/axi_tdd_hw.tcl new file mode 100644 index 00000000..0a2095bc --- /dev/null +++ b/adi_library/axi_tdd/axi_tdd_hw.tcl @@ -0,0 +1,99 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +source ../../scripts/adi_env.tcl +source ../scripts/adi_ip_intel.tcl + +set_module_property NAME axi_tdd +set_module_property DESCRIPTION "AXI TDD Interface" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME axi_tdd + +ad_ip_files axi_tdd [list\ + $ad_hdl_dir/library/common/up_axi.v \ + $ad_hdl_dir/library/util_cdc/sync_bits.v \ + $ad_hdl_dir/library/util_cdc/sync_data.v \ + $ad_hdl_dir/library/util_cdc/sync_event.v \ + axi_tdd_pkg.sv \ + axi_tdd_channel.sv \ + axi_tdd_counter.sv \ + axi_tdd_regmap.sv \ + axi_tdd_sync_gen.sv \ + axi_tdd.sv \ + axi_tdd_constr.sdc] + +# parameters + +set group "General Configuration" + +add_parameter ID INTEGER 0 +set_parameter_property ID DISPLAY_NAME "Core ID" +set_parameter_property ID HDL_PARAMETER true +set_parameter_property ID GROUP $group + +add_parameter CHANNEL_COUNT INTEGER 8 +set_parameter_property CHANNEL_COUNT DISPLAY_NAME "Number of TDD Channels" +set_parameter_property CHANNEL_COUNT HDL_PARAMETER true +set_parameter_property CHANNEL_COUNT ALLOWED_RANGES {1:32} +set_parameter_property CHANNEL_COUNT GROUP $group + +add_parameter DEFAULT_POLARITY INTEGER 0 +set_parameter_property DEFAULT_POLARITY DISPLAY_NAME "Default Channel output Polarity" +set_parameter_property DEFAULT_POLARITY HDL_PARAMETER true +set_parameter_property DEFAULT_POLARITY GROUP $group + +add_parameter REGISTER_WIDTH INTEGER 32 +set_parameter_property REGISTER_WIDTH DISPLAY_NAME "TDD Register Width" +set_parameter_property REGISTER_WIDTH HDL_PARAMETER true +set_parameter_property REGISTER_WIDTH ALLOWED_RANGES {8:32} +set_parameter_property REGISTER_WIDTH GROUP $group + +add_parameter BURST_COUNT_WIDTH INTEGER 32 +set_parameter_property BURST_COUNT_WIDTH DISPLAY_NAME "TDD Burst Counter Width" +set_parameter_property BURST_COUNT_WIDTH HDL_PARAMETER true +set_parameter_property BURST_COUNT_WIDTH ALLOWED_RANGES {8:32} +set_parameter_property BURST_COUNT_WIDTH GROUP $group + +add_parameter SYNC_INTERNAL INTEGER 1 +set_parameter_property SYNC_INTERNAL DISPLAY_NAME "Sync Internal enable" +set_parameter_property SYNC_INTERNAL HDL_PARAMETER true +set_parameter_property SYNC_INTERNAL ALLOWED_RANGES {0:1} +set_parameter_property SYNC_INTERNAL GROUP $group + +add_parameter SYNC_EXTERNAL INTEGER 0 +set_parameter_property SYNC_EXTERNAL DISPLAY_NAME "Sync External enable" +set_parameter_property SYNC_EXTERNAL HDL_PARAMETER true +set_parameter_property SYNC_EXTERNAL ALLOWED_RANGES {0:1} +set_parameter_property SYNC_EXTERNAL GROUP $group + +add_parameter SYNC_EXTERNAL_CDC INTEGER 0 +set_parameter_property SYNC_EXTERNAL_CDC DISPLAY_NAME "Sync External CDC enable" +set_parameter_property SYNC_EXTERNAL_CDC HDL_PARAMETER true +set_parameter_property SYNC_EXTERNAL_CDC ALLOWED_RANGES {0:1} +set_parameter_property SYNC_EXTERNAL_CDC GROUP $group + +add_parameter SYNC_COUNT_WIDTH INTEGER 64 +set_parameter_property SYNC_COUNT_WIDTH DISPLAY_NAME "TDD Sync Counter Width" +set_parameter_property SYNC_COUNT_WIDTH HDL_PARAMETER true +set_parameter_property SYNC_COUNT_WIDTH ALLOWED_RANGES {0:64} +set_parameter_property SYNC_COUNT_WIDTH GROUP $group + +# interfaces + +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn + +add_interface tdd_clock clock end +add_interface_port tdd_clock clk clk Input 1 + +add_interface tdd_reset reset end +set_interface_property tdd_reset associatedClock tdd_clock +add_interface_port tdd_reset resetn reset_n Input 1 + +ad_interface signal sync_in input 1 +ad_interface signal sync_out output 1 +ad_interface signal tdd_channel output 32 + diff --git a/adi_library/axi_tdd/axi_tdd_ip.tcl b/adi_library/axi_tdd/axi_tdd_ip.tcl new file mode 100644 index 00000000..ba53baa3 --- /dev/null +++ b/adi_library/axi_tdd/axi_tdd_ip.tcl @@ -0,0 +1,98 @@ +############################################################################### +## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_tdd +adi_ip_files axi_tdd [list \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/util_cdc/sync_bits.v" \ + "$ad_hdl_dir/library/util_cdc/sync_data.v" \ + "$ad_hdl_dir/library/util_cdc/sync_event.v" \ + "axi_tdd_pkg.sv" \ + "axi_tdd_channel.sv" \ + "axi_tdd_counter.sv" \ + "axi_tdd_regmap.sv" \ + "axi_tdd_sync_gen.sv" \ + "axi_tdd.sv" ] + +adi_ip_properties axi_tdd +adi_ip_ttcl axi_tdd "axi_tdd_constr.ttcl" +set_property display_name "ADI AXI TDD Controller" [ipx::current_core] +set_property description "ADI AXI TDD Controller" [ipx::current_core] +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_tdd} [ipx::current_core] + +adi_init_bd_tcl + +proc add_reset {name polarity} { + set reset_intf [ipx::infer_bus_interface $name xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]] + set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_intf] + set_property value $polarity $reset_polarity +} + +ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + +add_reset rst ACTIVE_HIGH +add_reset s_axi_aresetn ACTIVE_LOW + +ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk -of_objects [ipx::current_core]] +set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF -of_objects [ipx::get_bus_interfaces s_axi_aclk -of_objects [ipx::current_core]]] + +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "1" \ + "value_validation_range_maximum" "32" \ + ] \ + [ipx::get_user_parameters CHANNEL_COUNT -of_objects [ipx::current_core]] + +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "8" \ + "value_validation_range_maximum" "32" \ + ] \ + [ipx::get_user_parameters REGISTER_WIDTH -of_objects [ipx::current_core]] + +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "8" \ + "value_validation_range_maximum" "32" \ + ] \ + [ipx::get_user_parameters BURST_COUNT_WIDTH -of_objects [ipx::current_core]] + +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "0" \ + "value_validation_range_maximum" "64" \ + ] \ + [ipx::get_user_parameters SYNC_COUNT_WIDTH -of_objects [ipx::current_core]] + +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "0" \ + "value_validation_range_maximum" "1" \ + ] \ + [ipx::get_user_parameters SYNC_INTERNAL -of_objects [ipx::current_core]] + +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "0" \ + "value_validation_range_maximum" "1" \ + ] \ + [ipx::get_user_parameters SYNC_EXTERNAL -of_objects [ipx::current_core]] + +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "0" \ + "value_validation_range_maximum" "1" \ + ] \ + [ipx::get_user_parameters SYNC_EXTERNAL_CDC -of_objects [ipx::current_core]] + +ipx::create_xgui_files [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/axi_tdd/axi_tdd_pkg.sv b/adi_library/axi_tdd/axi_tdd_pkg.sv new file mode 100644 index 00000000..5546f74a --- /dev/null +++ b/adi_library/axi_tdd/axi_tdd_pkg.sv @@ -0,0 +1,103 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +package axi_tdd_pkg; + + typedef enum logic [1:0] { + IDLE = 2'b00, + ARMED = 2'b01, + WAITING = 2'b10, + RUNNING = 2'b11} state_t; + + localparam + PCORE_VERSION = 32'h00020061, + PCORE_MAGIC = 32'h5444444E; // "TDDN", big endian + + // register address offset + localparam + ADDR_TDD_VERSION = 8'h00, + ADDR_TDD_ID = 8'h01, + ADDR_TDD_SCRATCH = 8'h02, + ADDR_TDD_IDENTIFICATION = 8'h03, + ADDR_TDD_INTERFACE = 8'h04, + ADDR_TDD_DEF_POLARITY = 8'h05, + ADDR_TDD_CONTROL = 8'h10, + ADDR_TDD_CH_ENABLE = 8'h11, + ADDR_TDD_CH_POLARITY = 8'h12, + ADDR_TDD_BURST_COUNT = 8'h13, + ADDR_TDD_STARTUP_DELAY = 8'h14, + ADDR_TDD_FRAME_LENGTH = 8'h15, + ADDR_TDD_SYNC_CNT_LOW = 8'h16, + ADDR_TDD_SYNC_CNT_HIGH = 8'h17, + ADDR_TDD_STATUS = 8'h18, + ADDR_TDD_CH_ON = 8'h20, + ADDR_TDD_CH_OFF = 8'h21; + + // channel offset values + localparam + CH0 = 0, + CH1 = 1, + CH2 = 2, + CH3 = 3, + CH4 = 4, + CH5 = 5, + CH6 = 6, + CH7 = 7, + CH8 = 8, + CH9 = 9, + CH10 = 10, + CH11 = 11, + CH12 = 12, + CH13 = 13, + CH14 = 14, + CH15 = 15, + CH16 = 16, + CH17 = 17, + CH18 = 18, + CH19 = 19, + CH20 = 20, + CH21 = 21, + CH22 = 22, + CH23 = 23, + CH24 = 24, + CH25 = 25, + CH26 = 26, + CH27 = 27, + CH28 = 28, + CH29 = 29, + CH30 = 30, + CH31 = 31; + +endpackage diff --git a/adi_library/axi_tdd/axi_tdd_regmap.sv b/adi_library/axi_tdd/axi_tdd_regmap.sv new file mode 100644 index 00000000..4dd36c95 --- /dev/null +++ b/adi_library/axi_tdd/axi_tdd_regmap.sv @@ -0,0 +1,445 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +`timescale 1ns/1ps + +module axi_tdd_regmap #( + parameter ID = 0, + parameter CHANNEL_COUNT = 8, + parameter DEFAULT_POLARITY = 8'h00, + parameter REGISTER_WIDTH = 32, + parameter BURST_COUNT_WIDTH = 32, + parameter SYNC_INTERNAL = 1, + parameter SYNC_EXTERNAL = 0, + parameter SYNC_EXTERNAL_CDC = 0, + parameter SYNC_COUNT_WIDTH = 64 +) ( + + // tdd clock + input logic tdd_clk, + input logic tdd_resetn, + + // tdd interface control + input axi_tdd_pkg::state_t tdd_cstate, + output logic tdd_enable, + output logic [CHANNEL_COUNT-1:0] tdd_channel_en, + output logic [CHANNEL_COUNT-1:0] asy_tdd_channel_pol, + output logic [BURST_COUNT_WIDTH-1:0] asy_tdd_burst_count, + output logic [REGISTER_WIDTH-1:0] asy_tdd_startup_delay, + output logic [REGISTER_WIDTH-1:0] asy_tdd_frame_length, + output logic [REGISTER_WIDTH-1:0] asy_tdd_channel_on [0:CHANNEL_COUNT-1], + output logic [REGISTER_WIDTH-1:0] asy_tdd_channel_off [0:CHANNEL_COUNT-1], + output logic [SYNC_COUNT_WIDTH-1:0] asy_tdd_sync_period, + output logic tdd_sync_rst, + output logic tdd_sync_int, + output logic tdd_sync_ext, + output logic tdd_sync_soft, + + // bus interface + input logic up_rstn, + input logic up_clk, + input logic up_wreq, + input logic [ 7:0] up_waddr, + input logic [31:0] up_wdata, + output logic up_wack, + input logic up_rreq, + input logic [ 7:0] up_raddr, + output logic [31:0] up_rdata, + output logic up_rack +); + + // package import + import axi_tdd_pkg::*; + + // local params + localparam CHANNEL_COUNT_EXTRA = CHANNEL_COUNT - 1; + + // internal registers + logic [31:0] up_scratch; + logic [ 1:0] up_tdd_cstate; + logic up_tdd_enable; + logic up_tdd_sync_rst; + logic up_tdd_sync_int; + logic up_tdd_sync_ext; + logic up_tdd_sync_soft; + logic [CHANNEL_COUNT-1:0] up_tdd_channel_en; + logic [CHANNEL_COUNT-1:0] up_tdd_channel_pol; + logic [BURST_COUNT_WIDTH-1:0] up_tdd_burst_count; + logic [REGISTER_WIDTH-1:0] up_tdd_startup_delay; + logic [REGISTER_WIDTH-1:0] up_tdd_frame_length; + logic [REGISTER_WIDTH-1:0] up_tdd_channel_on [0:CHANNEL_COUNT-1]; + logic [REGISTER_WIDTH-1:0] up_tdd_channel_off [0:CHANNEL_COUNT-1]; + + //internal wires + logic [31:0] status_synth_params_s; + logic [31:0] status_def_polarity_s; + logic [31:0] up_tdd_channel_en_s; + logic [31:0] up_tdd_channel_pol_s; + logic [31:0] up_tdd_burst_count_s; + logic [31:0] up_tdd_startup_delay_s; + logic [31:0] up_tdd_frame_length_s; + logic [63:0] up_tdd_sync_period_s; + logic [31:0] up_tdd_channel_on_s [0:31]; + logic [31:0] up_tdd_channel_off_s [0:31]; + + //initial values + initial begin + up_rdata = 32'b0; + up_wack = 1'b0; + up_rack = 1'b0; + up_scratch = 32'b0; + up_tdd_enable = 1'b0; + up_tdd_sync_rst = 1'b0; + up_tdd_sync_int = 1'b0; + up_tdd_sync_ext = 1'b0; + up_tdd_sync_soft = 1'b0; + up_tdd_channel_en = '0; + up_tdd_channel_pol = '0; + up_tdd_burst_count = '0; + up_tdd_startup_delay = '0; + up_tdd_frame_length = '0; + up_tdd_channel_on = '{default:0}; + up_tdd_channel_off = '{default:0}; + end + + //read-only synthesis parameters + assign status_synth_params_s = { + /*31:24 */ 1'b0, 7'(SYNC_COUNT_WIDTH), + /*23:16 */ 2'b0, 6'(BURST_COUNT_WIDTH), + /*15: 8 */ 2'b0, 6'(REGISTER_WIDTH), + /* 7: 0 */ 1'(SYNC_EXTERNAL_CDC), + 1'(SYNC_EXTERNAL), + 1'(SYNC_INTERNAL), + 5'(CHANNEL_COUNT_EXTRA)}; + + assign status_def_polarity_s = {{(32-CHANNEL_COUNT){1'b0}}, DEFAULT_POLARITY}; + + // processor write interface + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 1'b0; + up_scratch <= 32'b0; + up_tdd_enable <= 1'b0; + up_tdd_sync_rst <= 1'b0; + up_tdd_sync_int <= 1'b0; + up_tdd_sync_ext <= 1'b0; + up_tdd_sync_soft <= 1'b0; + up_tdd_channel_en <= '0; + up_tdd_channel_pol <= '0; + up_tdd_startup_delay <= '0; + up_tdd_frame_length <= '0; + up_tdd_burst_count <= '0; + end else begin + up_wack <= up_wreq; + if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_SCRATCH)) begin + up_scratch <= up_wdata; + end + if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_CONTROL)) begin + up_tdd_sync_soft <= up_wdata[4]; + up_tdd_sync_ext <= up_wdata[3] & SYNC_EXTERNAL; + up_tdd_sync_int <= up_wdata[2] & SYNC_INTERNAL; + up_tdd_sync_rst <= up_wdata[1]; + up_tdd_enable <= up_wdata[0]; + end else begin + up_tdd_sync_soft <= 1'b0; + up_tdd_sync_ext <= up_tdd_sync_ext; + up_tdd_sync_int <= up_tdd_sync_int; + up_tdd_sync_rst <= up_tdd_sync_rst; + up_tdd_enable <= up_tdd_enable; + end + if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_CH_ENABLE)) begin + up_tdd_channel_en <= up_wdata[CHANNEL_COUNT-1:0]; + end + if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_CH_POLARITY) && !up_tdd_enable) begin + up_tdd_channel_pol <= up_wdata[CHANNEL_COUNT-1:0]; + end + if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_BURST_COUNT) && !up_tdd_enable) begin + up_tdd_burst_count <= up_wdata[BURST_COUNT_WIDTH-1:0]; + end + if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_STARTUP_DELAY) && !up_tdd_enable) begin + up_tdd_startup_delay <= up_wdata[REGISTER_WIDTH-1:0]; + end + if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_FRAME_LENGTH) && !up_tdd_enable) begin + up_tdd_frame_length <= up_wdata[REGISTER_WIDTH-1:0]; + end + end + end + + assign up_tdd_channel_en_s = {{(32-CHANNEL_COUNT){1'b0}}, up_tdd_channel_en}; + assign up_tdd_channel_pol_s = {{(32-CHANNEL_COUNT){1'b0}}, up_tdd_channel_pol}; + assign up_tdd_burst_count_s = {{(32-BURST_COUNT_WIDTH){1'b0}}, up_tdd_burst_count}; + assign up_tdd_startup_delay_s = {{(32-REGISTER_WIDTH){1'b0}}, up_tdd_startup_delay}; + assign up_tdd_frame_length_s = {{(32-REGISTER_WIDTH){1'b0}}, up_tdd_frame_length}; + + // internal sync counter generation (low and high) + + generate + if (SYNC_COUNT_WIDTH>32) begin + + logic [31:0] up_tdd_sync_period_low; + logic [(SYNC_COUNT_WIDTH-32-1):0] up_tdd_sync_period_high; + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_tdd_sync_period_low <= 32'b0; + up_tdd_sync_period_high <= '0; + end else begin + if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_SYNC_CNT_LOW) && !up_tdd_enable) begin + up_tdd_sync_period_low <= up_wdata[31:0]; + end + if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_SYNC_CNT_HIGH) && !up_tdd_enable) begin + up_tdd_sync_period_high <= up_wdata[(SYNC_COUNT_WIDTH-32-1):0]; + end + end + end + + assign up_tdd_sync_period_s[31:0] = up_tdd_sync_period_low; + assign up_tdd_sync_period_s[63:32] = {{(64-SYNC_COUNT_WIDTH){1'b0}}, up_tdd_sync_period_high}; + assign asy_tdd_sync_period = {up_tdd_sync_period_high, up_tdd_sync_period_low}; //skipping CDC + + end else begin + if (SYNC_COUNT_WIDTH>0) begin + + logic [SYNC_COUNT_WIDTH-1:0] up_tdd_sync_period_low; + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_tdd_sync_period_low <= '0; + end else begin + if ((up_wreq == 1'b1) && (up_waddr == ADDR_TDD_SYNC_CNT_LOW) && !up_tdd_enable) begin + up_tdd_sync_period_low <= up_wdata[(SYNC_COUNT_WIDTH-1):0]; + end + end + end + + assign up_tdd_sync_period_s[31:0] = {{(32-SYNC_COUNT_WIDTH){1'b0}}, up_tdd_sync_period_low}; + assign up_tdd_sync_period_s[63:32] = 32'b0; + assign asy_tdd_sync_period = up_tdd_sync_period_low; //skipping CDC + + end else begin + assign up_tdd_sync_period_s[31:0] = 32'b0; + assign up_tdd_sync_period_s[63:32] = 32'b0; + assign asy_tdd_sync_period = '0; + end + end + endgenerate + + // channel register generation + + genvar i; + generate + + for (i=0; i +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +`timescale 1ns/1ps + +module axi_tdd_sync_gen #( + parameter SYNC_INTERNAL = 1, + parameter SYNC_EXTERNAL = 0, + parameter SYNC_EXTERNAL_CDC = 0, + parameter SYNC_COUNT_WIDTH = 64 +) ( + + input logic clk, + input logic resetn, + + input logic sync_in, + output logic sync_out, + + input logic tdd_enable, + input logic tdd_sync_ext, + input logic tdd_sync_int, + input logic tdd_sync_soft, + input logic [SYNC_COUNT_WIDTH-1:0] asy_tdd_sync_period +); + + // internal signals + logic [1:0] sync_source; + + // Connect the enable signal to the enable flop lines + (* direct_enable = "yes" *) logic enable; + assign enable = tdd_enable; + + // first sync source (external) + generate + if (SYNC_EXTERNAL == 1) begin + if (SYNC_EXTERNAL_CDC == 1) begin + + logic tdd_sync_m1 = 1'b0; + logic tdd_sync_m2 = 1'b0; + logic tdd_sync_m3 = 1'b0; + + // synchronization of sync_in + always @(posedge clk) begin + if (resetn == 1'b0) begin + tdd_sync_m1 <= 1'b0; + tdd_sync_m2 <= 1'b0; + tdd_sync_m3 <= 1'b0; + end else begin + tdd_sync_m1 <= sync_in; + tdd_sync_m2 <= tdd_sync_m1; + tdd_sync_m3 <= tdd_sync_m2; + end + end + + assign sync_source[0] = ~tdd_sync_m3 & tdd_sync_m2; + + end else begin + assign sync_source[0] = sync_in; + end + end else begin + assign sync_source[0] = 1'b0; + end + endgenerate + + // second sync source (internal) + generate + if (SYNC_INTERNAL == 1) begin + + logic tdd_sync_trigger = 1'b0; + logic [SYNC_COUNT_WIDTH-1:0] tdd_sync_counter = '0; + logic [SYNC_COUNT_WIDTH-1:0] tdd_sync_period = '0; + + // Save the async register values only when the module is enabled + always @(posedge clk) begin + if (resetn == 1'b0) begin + tdd_sync_period <= '0; + end else begin + if (enable) begin + tdd_sync_period <= asy_tdd_sync_period; + end + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + tdd_sync_trigger <= 1'b0; + end else begin + if (tdd_sync_counter == (tdd_sync_period - 1'b1)) begin + tdd_sync_trigger <= 1'b1; + end else begin + tdd_sync_trigger <= 1'b0; + end + end + end + + // sync counter + always @(posedge clk) begin + if (resetn == 1'b0) begin + tdd_sync_counter <= '0; + end else begin + if (tdd_enable) begin + tdd_sync_counter <= (tdd_sync_trigger == 1'b1) ? '0 : tdd_sync_counter + 1'b1; + end else begin + tdd_sync_counter <= '0; + end + end + end + + assign sync_source[1] = tdd_sync_trigger; + + end else begin + assign sync_source[1] = 1'b0; + end + endgenerate + + // creating the output sync signal + assign sync_out = (tdd_sync_ext & sync_source[0]) | (tdd_sync_int & sync_source[1]) | tdd_sync_soft; + +endmodule diff --git a/adi_library/axi_tdd/bd/bd.tcl b/adi_library/axi_tdd/bd/bd.tcl new file mode 100644 index 00000000..f0062cf8 --- /dev/null +++ b/adi_library/axi_tdd/bd/bd.tcl @@ -0,0 +1,41 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/axi_tdd/component.xml b/adi_library/axi_tdd/component.xml new file mode 100644 index 00000000..9a37683f --- /dev/null +++ b/adi_library/axi_tdd/component.xml @@ -0,0 +1,993 @@ + + + analog.com + user + axi_tdd + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + clk + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_RESET + rst + + + + + rst + + + + + + + RST + + + rst + + + + + + POLARITY + ACTIVE_HIGH + + + + + + + s_axi + + axi_lite + 0 + 1024 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + SystemVerilog + axi_tdd + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 11c1d0ef + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + SystemVerilog + axi_tdd + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 11c1d0ef + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 931062b4 + + + + + + + clk + + in + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + resetn + + in + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sync_in + + in + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sync_out + + out + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + tdd_channel + + out + + 7 + 0 + + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 9 + 0 + + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 9 + 0 + + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + ID + Id + 0 + + + CHANNEL_COUNT + Channel Count + 8 + + + DEFAULT_POLARITY + Default Polarity + "00000000" + + + REGISTER_WIDTH + Register Width + 32 + + + BURST_COUNT_WIDTH + Burst Count Width + 32 + + + SYNC_INTERNAL + Sync Internal + 1 + + + SYNC_EXTERNAL + Sync External + 0 + + + SYNC_EXTERNAL_CDC + Sync External Cdc + 0 + + + SYNC_COUNT_WIDTH + Sync Count Width + 64 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + axi_tdd_constr.ttcl + ttcl + + + ../util_cdc/sync_bits.v + verilogSource + + + ../util_cdc/sync_data.v + verilogSource + + + ../util_cdc/sync_event.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + axi_tdd_pkg.sv + systemVerilogSource + + + axi_tdd_channel.sv + systemVerilogSource + + + axi_tdd_counter.sv + systemVerilogSource + + + axi_tdd_regmap.sv + systemVerilogSource + + + axi_tdd_sync_gen.sv + systemVerilogSource + + + axi_tdd.sv + systemVerilogSource + CHECKSUM_f31068f0 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../util_cdc/sync_bits.v + verilogSource + + + ../util_cdc/sync_data.v + verilogSource + + + ../util_cdc/sync_event.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + axi_tdd_pkg.sv + systemVerilogSource + + + axi_tdd_channel.sv + systemVerilogSource + + + axi_tdd_counter.sv + systemVerilogSource + + + axi_tdd_regmap.sv + systemVerilogSource + + + axi_tdd_sync_gen.sv + systemVerilogSource + + + axi_tdd.sv + systemVerilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_tdd_v1_0.tcl + tclSource + CHECKSUM_931062b4 + XGUI_VERSION_2 + + + + ADI AXI TDD Controller + + + ID + Id + 0 + + + CHANNEL_COUNT + Channel Count + 8 + + + DEFAULT_POLARITY + Default Polarity + "00000000" + + + REGISTER_WIDTH + Register Width + 32 + + + BURST_COUNT_WIDTH + Burst Count Width + 32 + + + SYNC_INTERNAL + Sync Internal + 1 + + + SYNC_EXTERNAL + Sync External + 0 + + + SYNC_EXTERNAL_CDC + Sync External Cdc + 0 + + + SYNC_COUNT_WIDTH + Sync Count Width + 64 + + + Component_Name + axi_tdd_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + ADI AXI TDD Controller + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_tdd + 1 + 2024-01-14T03:49:32Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/axi_tdd/scripts/axi_tdd.tcl b/adi_library/axi_tdd/scripts/axi_tdd.tcl new file mode 100644 index 00000000..f633267c --- /dev/null +++ b/adi_library/axi_tdd/scripts/axi_tdd.tcl @@ -0,0 +1,67 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +proc ad_tdd_gen_create {ip_name + num_of_channels + {default_polarity 0} + {reg_counter_width 32} + {burst_counter_width 32} + {sync_counter_width 64} + {sync_internal 1} + {sync_external 0} + {sync_external_cdc 0}} { + + create_bd_cell -type hier $ip_name + + # Control interface + create_bd_pin -dir I -type clk "${ip_name}/s_axi_aclk" + create_bd_pin -dir I -type rst "${ip_name}/s_axi_aresetn" + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "${ip_name}/s_axi" + + # Device interface + create_bd_pin -dir I -type clk "${ip_name}/clk" + create_bd_pin -dir I -type rst "${ip_name}/resetn" + create_bd_pin -dir I "${ip_name}/sync_in" + create_bd_pin -dir O "${ip_name}/sync_out" + for {set i 0} {$i < $num_of_channels} {incr i} { + create_bd_pin -dir O "${ip_name}/tdd_channel_${i}" + } + + # Generic TDD core + ad_ip_instance axi_tdd "${ip_name}/tdd_core" [list \ + CHANNEL_COUNT $num_of_channels \ + DEFAULT_POLARITY $default_polarity \ + REGISTER_WIDTH $reg_counter_width \ + BURST_COUNT_WIDTH $burst_counter_width \ + SYNC_COUNT_WIDTH $sync_counter_width \ + SYNC_INTERNAL $sync_internal \ + SYNC_EXTERNAL $sync_external \ + SYNC_EXTERNAL_CDC $sync_external_cdc + ] + + for {set i 0} {$i < $num_of_channels} {incr i} { + ad_ip_instance xlslice "${ip_name}/tdd_ch_slice_${i}" [list \ + DIN_WIDTH $num_of_channels \ + DIN_FROM $i \ + DIN_TO $i \ + ] + } + + # Create connections + ad_connect "${ip_name}/s_axi_aclk" "${ip_name}/tdd_core/s_axi_aclk" + ad_connect "${ip_name}/s_axi_aresetn" "${ip_name}/tdd_core/s_axi_aresetn" + ad_connect "${ip_name}/s_axi" "${ip_name}/tdd_core/s_axi" + + ad_connect ${ip_name}/tdd_core/clk ${ip_name}/clk + ad_connect ${ip_name}/tdd_core/resetn ${ip_name}/resetn + ad_connect ${ip_name}/tdd_core/sync_in ${ip_name}/sync_in + ad_connect ${ip_name}/tdd_core/sync_out ${ip_name}/sync_out + + for {set i 0} {$i < $num_of_channels} {incr i} { + ad_connect ${ip_name}/tdd_core/tdd_channel ${ip_name}/tdd_ch_slice_$i/Din + ad_connect ${ip_name}/tdd_ch_slice_$i/Dout ${ip_name}/tdd_channel_$i + } + +} diff --git a/adi_library/axi_tdd/temporary_case_dependencies.mk b/adi_library/axi_tdd/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/axi_tdd/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/axi_tdd/xgui/axi_tdd_v1_0.tcl b/adi_library/axi_tdd/xgui/axi_tdd_v1_0.tcl new file mode 100644 index 00000000..b94db9c3 --- /dev/null +++ b/adi_library/axi_tdd/xgui/axi_tdd_v1_0.tcl @@ -0,0 +1,145 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "BURST_COUNT_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "CHANNEL_COUNT" -parent ${Page_0} + ipgui::add_param $IPINST -name "DEFAULT_POLARITY" -parent ${Page_0} + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "REGISTER_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "SYNC_COUNT_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "SYNC_EXTERNAL" -parent ${Page_0} + ipgui::add_param $IPINST -name "SYNC_EXTERNAL_CDC" -parent ${Page_0} + ipgui::add_param $IPINST -name "SYNC_INTERNAL" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.BURST_COUNT_WIDTH { PARAM_VALUE.BURST_COUNT_WIDTH } { + # Procedure called to update BURST_COUNT_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BURST_COUNT_WIDTH { PARAM_VALUE.BURST_COUNT_WIDTH } { + # Procedure called to validate BURST_COUNT_WIDTH + return true +} + +proc update_PARAM_VALUE.CHANNEL_COUNT { PARAM_VALUE.CHANNEL_COUNT } { + # Procedure called to update CHANNEL_COUNT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CHANNEL_COUNT { PARAM_VALUE.CHANNEL_COUNT } { + # Procedure called to validate CHANNEL_COUNT + return true +} + +proc update_PARAM_VALUE.DEFAULT_POLARITY { PARAM_VALUE.DEFAULT_POLARITY } { + # Procedure called to update DEFAULT_POLARITY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEFAULT_POLARITY { PARAM_VALUE.DEFAULT_POLARITY } { + # Procedure called to validate DEFAULT_POLARITY + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.REGISTER_WIDTH { PARAM_VALUE.REGISTER_WIDTH } { + # Procedure called to update REGISTER_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.REGISTER_WIDTH { PARAM_VALUE.REGISTER_WIDTH } { + # Procedure called to validate REGISTER_WIDTH + return true +} + +proc update_PARAM_VALUE.SYNC_COUNT_WIDTH { PARAM_VALUE.SYNC_COUNT_WIDTH } { + # Procedure called to update SYNC_COUNT_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SYNC_COUNT_WIDTH { PARAM_VALUE.SYNC_COUNT_WIDTH } { + # Procedure called to validate SYNC_COUNT_WIDTH + return true +} + +proc update_PARAM_VALUE.SYNC_EXTERNAL { PARAM_VALUE.SYNC_EXTERNAL } { + # Procedure called to update SYNC_EXTERNAL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SYNC_EXTERNAL { PARAM_VALUE.SYNC_EXTERNAL } { + # Procedure called to validate SYNC_EXTERNAL + return true +} + +proc update_PARAM_VALUE.SYNC_EXTERNAL_CDC { PARAM_VALUE.SYNC_EXTERNAL_CDC } { + # Procedure called to update SYNC_EXTERNAL_CDC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SYNC_EXTERNAL_CDC { PARAM_VALUE.SYNC_EXTERNAL_CDC } { + # Procedure called to validate SYNC_EXTERNAL_CDC + return true +} + +proc update_PARAM_VALUE.SYNC_INTERNAL { PARAM_VALUE.SYNC_INTERNAL } { + # Procedure called to update SYNC_INTERNAL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SYNC_INTERNAL { PARAM_VALUE.SYNC_INTERNAL } { + # Procedure called to validate SYNC_INTERNAL + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.CHANNEL_COUNT { MODELPARAM_VALUE.CHANNEL_COUNT PARAM_VALUE.CHANNEL_COUNT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CHANNEL_COUNT}] ${MODELPARAM_VALUE.CHANNEL_COUNT} +} + +proc update_MODELPARAM_VALUE.DEFAULT_POLARITY { MODELPARAM_VALUE.DEFAULT_POLARITY PARAM_VALUE.DEFAULT_POLARITY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEFAULT_POLARITY}] ${MODELPARAM_VALUE.DEFAULT_POLARITY} +} + +proc update_MODELPARAM_VALUE.REGISTER_WIDTH { MODELPARAM_VALUE.REGISTER_WIDTH PARAM_VALUE.REGISTER_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.REGISTER_WIDTH}] ${MODELPARAM_VALUE.REGISTER_WIDTH} +} + +proc update_MODELPARAM_VALUE.BURST_COUNT_WIDTH { MODELPARAM_VALUE.BURST_COUNT_WIDTH PARAM_VALUE.BURST_COUNT_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BURST_COUNT_WIDTH}] ${MODELPARAM_VALUE.BURST_COUNT_WIDTH} +} + +proc update_MODELPARAM_VALUE.SYNC_INTERNAL { MODELPARAM_VALUE.SYNC_INTERNAL PARAM_VALUE.SYNC_INTERNAL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SYNC_INTERNAL}] ${MODELPARAM_VALUE.SYNC_INTERNAL} +} + +proc update_MODELPARAM_VALUE.SYNC_EXTERNAL { MODELPARAM_VALUE.SYNC_EXTERNAL PARAM_VALUE.SYNC_EXTERNAL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SYNC_EXTERNAL}] ${MODELPARAM_VALUE.SYNC_EXTERNAL} +} + +proc update_MODELPARAM_VALUE.SYNC_EXTERNAL_CDC { MODELPARAM_VALUE.SYNC_EXTERNAL_CDC PARAM_VALUE.SYNC_EXTERNAL_CDC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SYNC_EXTERNAL_CDC}] ${MODELPARAM_VALUE.SYNC_EXTERNAL_CDC} +} + +proc update_MODELPARAM_VALUE.SYNC_COUNT_WIDTH { MODELPARAM_VALUE.SYNC_COUNT_WIDTH PARAM_VALUE.SYNC_COUNT_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SYNC_COUNT_WIDTH}] ${MODELPARAM_VALUE.SYNC_COUNT_WIDTH} +} + diff --git a/adi_library/cn0363/cn0363_dma_sequencer/Makefile b/adi_library/cn0363/cn0363_dma_sequencer/Makefile new file mode 100644 index 00000000..1a3a98fd --- /dev/null +++ b/adi_library/cn0363/cn0363_dma_sequencer/Makefile @@ -0,0 +1,16 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := cn0363_dma_sequencer + +GENERIC_DEPS += cn0363_dma_sequencer.v + +XILINX_DEPS += cn0363_dma_sequencer_ip.tcl + +XILINX_DEPS += ../../interfaces/fifo_wr.xml +XILINX_DEPS += ../../interfaces/fifo_wr_rtl.xml + +include ../../scripts/library.mk diff --git a/adi_library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v b/adi_library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v new file mode 100644 index 00000000..d96dc3e2 --- /dev/null +++ b/adi_library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v @@ -0,0 +1,197 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module cn0363_dma_sequencer ( + input clk, + input resetn, + + input [31:0] phase, + input phase_valid, + output reg phase_ready, + + input [23:0] data, + input data_valid, + output reg data_ready, + + input [31:0] data_filtered, + input data_filtered_valid, + output reg data_filtered_ready, + + input [31:0] i_q, + input i_q_valid, + output reg i_q_ready, + + input [31:0] i_q_filtered, + input i_q_filtered_valid, + output reg i_q_filtered_ready, + + output overflow, + + output reg [31:0] dma_wr_data, + output reg dma_wr_en, + output reg dma_wr_sync, + input dma_wr_overflow, + input dma_wr_xfer_req, + + input [13:0] channel_enable, + + output processing_resetn +); + + reg [3:0] count = 'h00; + + assign overflow = dma_wr_overflow; + assign processing_resetn = dma_wr_xfer_req; + + always @(posedge clk) begin + if (processing_resetn == 1'b0) begin + count <= 'h0; + end else begin + case (count) + 'h0: if (phase_valid) count <= count + 1; + 'h1: if (data_valid) count <= count + 1; + 'h2: if (data_filtered_valid) count <= count + 1; + 'h3: if (i_q_valid) count <= count + 1; + 'h4: if (i_q_valid) count <= count + 1; + 'h5: if (i_q_filtered_valid) count <= count + 1; + 'h6: if (i_q_filtered_valid) count <= count + 1; + 'h7: if (phase_valid) count <= count + 1; + 'h8: if (data_valid) count <= count + 1; + 'h9: if (data_filtered_valid) count <= count + 1; + 'ha: if (i_q_valid) count <= count + 1; + 'hb: if (i_q_valid) count <= count + 1; + 'hc: if (i_q_filtered_valid) count <= count + 1; + 'hd: if (i_q_filtered_valid) count <= 'h00; + endcase + end + end + + always @(posedge clk) begin + case (count) + 'h0: dma_wr_data <= phase; + 'h1: dma_wr_data <= {8'h00,data[23:0]}; + 'h2: dma_wr_data <= data_filtered; + 'h3: dma_wr_data <= i_q; + 'h4: dma_wr_data <= i_q; + 'h5: dma_wr_data <= i_q_filtered; + 'h6: dma_wr_data <= i_q_filtered; + 'h7: dma_wr_data <= phase; + 'h8: dma_wr_data <= {8'h00,data[23:0]}; + 'h9: dma_wr_data <= data_filtered; + 'ha: dma_wr_data <= i_q; + 'hb: dma_wr_data <= i_q; + 'hc: dma_wr_data <= i_q_filtered; + 'hd: dma_wr_data <= i_q_filtered; + endcase + end + + always @(posedge clk) begin + if (processing_resetn == 1'b0 || channel_enable[count] == 1'b0) begin + dma_wr_en <= 1'b0; + end else begin + case (count) + 'h0: dma_wr_en <= phase_valid; + 'h1: dma_wr_en <= data_valid; + 'h2: dma_wr_en <= data_filtered_valid; + 'h3: dma_wr_en <= i_q_valid; + 'h4: dma_wr_en <= i_q_valid; + 'h5: dma_wr_en <= i_q_filtered_valid; + 'h6: dma_wr_en <= i_q_filtered_valid; + 'h7: dma_wr_en <= phase_valid; + 'h8: dma_wr_en <= data_valid; + 'h9: dma_wr_en <= data_filtered_valid; + 'ha: dma_wr_en <= i_q_valid; + 'hb: dma_wr_en <= i_q_valid; + 'hc: dma_wr_en <= i_q_filtered_valid; + 'hd: dma_wr_en <= i_q_filtered_valid; + endcase + end + end + + always @(posedge clk) begin + if (count == 'h00) begin + dma_wr_sync <= 1'b1; + end else if (dma_wr_en == 1'b1) begin + dma_wr_sync = 1'b0; + end + end + + always @(*) begin + case (count) + 'h0: phase_ready <= 1'b1; + 'h7: phase_ready <= 1'b1; + default: phase_ready <= 1'b0; + endcase + end + + always @(*) begin + case (count) + 'h1: data_ready <= 1'b1; + 'h8: data_ready <= 1'b1; + default: data_ready <= 1'b0; + endcase + end + + always @(*) begin + case (count) + 'h2: data_filtered_ready <= 1'b1; + 'h9: data_filtered_ready <= 1'b1; + default: data_filtered_ready <= 1'b0; + endcase + end + + always @(*) begin + case (count) + 'h3: i_q_ready <= 1'b1; + 'h4: i_q_ready <= 1'b1; + 'ha: i_q_ready <= 1'b1; + 'hb: i_q_ready <= 1'b1; + default: i_q_ready <= 1'b0; + endcase + end + + always @(*) begin + case (count) + 'h5: i_q_filtered_ready <= 1'b1; + 'h6: i_q_filtered_ready <= 1'b1; + 'hc: i_q_filtered_ready <= 1'b1; + 'hd: i_q_filtered_ready <= 1'b1; + default: i_q_filtered_ready <= 1'b0; + endcase + end + +endmodule diff --git a/adi_library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.xpr b/adi_library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.xpr new file mode 100644 index 00000000..83bbb68f --- /dev/null +++ b/adi_library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.xpr @@ -0,0 +1,399 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.tcl b/adi_library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.tcl new file mode 100644 index 00000000..3fdd8e4c --- /dev/null +++ b/adi_library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer_ip.tcl @@ -0,0 +1,76 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create cn0363_dma_sequencer +adi_ip_files cn0363_dma_sequencer [list \ + "cn0363_dma_sequencer.v" +] + +adi_ip_properties_lite cn0363_dma_sequencer + +adi_add_bus "phase" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"phase_valid" "TVALID"} \ + {"phase_ready" "TREADY"} \ + {"phase" "TDATA"} \ + } + +adi_add_bus "data" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"data_valid" "TVALID"} \ + {"data_ready" "TREADY"} \ + {"data" "TDATA"} \ + } + +adi_add_bus "data_filtered" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"data_filtered_valid" "TVALID"} \ + {"data_filtered_ready" "TREADY"} \ + {"data_filtered" "TDATA"} \ + } + +adi_add_bus "i_q" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"i_q_valid" "TVALID"} \ + {"i_q_ready" "TREADY"} \ + {"i_q" "TDATA"} \ + } + +adi_add_bus "i_q_filtered" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"i_q_filtered_valid" "TVALID"} \ + {"i_q_filtered_ready" "TREADY"} \ + {"i_q_filtered" "TDATA"} \ + } + + +adi_add_bus "dma_wr" "master" \ + "analog.com:interface:fifo_wr_rtl:1.0" \ + "analog.com:interface:fifo_wr:1.0" \ + { + {"dma_wr_en" "EN"} \ + {"dma_wr_sync" "SYNC"} \ + {"dma_wr_data" "DATA"} \ + {"dma_wr_overflow" "OVERFLOW"} \ + {"dma_wr_xfer_req" "XFER_REQ"} \ + } + + +adi_add_bus_clock "clk" "phase:data:data_filtered:i_q:i_q_filtered:dma_wr" "processing_resetn" + +ipx::save_core [ipx::current_core] diff --git a/adi_library/cn0363/cn0363_dma_sequencer/component.xml b/adi_library/cn0363/cn0363_dma_sequencer/component.xml new file mode 100644 index 00000000..b28f2c4b --- /dev/null +++ b/adi_library/cn0363/cn0363_dma_sequencer/component.xml @@ -0,0 +1,755 @@ + + + analog.com + user + cn0363_dma_sequencer + 1.0 + + + phase + + + + + + + TVALID + + + phase_valid + + + + + TREADY + + + phase_ready + + + + + TDATA + + + phase + + + + + + data + + + + + + + TVALID + + + data_valid + + + + + TREADY + + + data_ready + + + + + TDATA + + + data + + + + + + data_filtered + + + + + + + TVALID + + + data_filtered_valid + + + + + TREADY + + + data_filtered_ready + + + + + TDATA + + + data_filtered + + + + + + i_q + + + + + + + TVALID + + + i_q_valid + + + + + TREADY + + + i_q_ready + + + + + TDATA + + + i_q + + + + + + i_q_filtered + + + + + + + TVALID + + + i_q_filtered_valid + + + + + TREADY + + + i_q_filtered_ready + + + + + TDATA + + + i_q_filtered + + + + + + dma_wr + + + + + + + EN + + + dma_wr_en + + + + + SYNC + + + dma_wr_sync + + + + + DATA + + + dma_wr_data + + + + + OVERFLOW + + + dma_wr_overflow + + + + + XFER_REQ + + + dma_wr_xfer_req + + + + + + phase_data_data_filtered_i_q_i_q_filtered_dma_wr_signal_clock + phase_data_data_filtered_i_q_i_q_filtered_dma_wr_signal_clock + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_BUSIF + phase:data:data_filtered:i_q:i_q_filtered:dma_wr + + + ASSOCIATED_RESET + processing_resetn + + + + + phase_data_data_filtered_i_q_i_q_filtered_dma_wr_signal_reset + phase_data_data_filtered_i_q_i_q_filtered_dma_wr_signal_reset + + + + + + + RST + + + processing_resetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + cn0363_dma_sequencer + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 9089184b + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + cn0363_dma_sequencer + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 9089184b + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f92e9879 + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + resetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + phase + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + phase_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + phase_ready + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data + + in + + 23 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + data_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_ready + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_filtered + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_filtered_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_filtered_ready + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_q + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_q_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_q_ready + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_q_filtered + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_q_filtered_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + i_q_filtered_ready + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + overflow + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_wr_data + + out + + 31 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_wr_en + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_wr_sync + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_wr_overflow + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_wr_xfer_req + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + channel_enable + + in + + 13 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + processing_resetn + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + xilinx_anylanguagesynthesis_view_fileset + + cn0363_dma_sequencer.v + verilogSource + CHECKSUM_9089184b + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + cn0363_dma_sequencer.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/cn0363_dma_sequencer_v1_0.tcl + tclSource + CHECKSUM_f92e9879 + XGUI_VERSION_2 + + + + cn0363_dma_sequencer_v1_0 + + + Component_Name + cn0363_dma_sequencer_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + cn0363_dma_sequencer_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:49:39Z + + + 2023.2.1 + + + + + + diff --git a/adi_library/cn0363/cn0363_dma_sequencer/xgui/cn0363_dma_sequencer_v1_0.tcl b/adi_library/cn0363/cn0363_dma_sequencer/xgui/cn0363_dma_sequencer_v1_0.tcl new file mode 100644 index 00000000..0db18e9a --- /dev/null +++ b/adi_library/cn0363/cn0363_dma_sequencer/xgui/cn0363_dma_sequencer_v1_0.tcl @@ -0,0 +1,10 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + + diff --git a/adi_library/cn0363/cn0363_phase_data_sync/Makefile b/adi_library/cn0363/cn0363_phase_data_sync/Makefile new file mode 100644 index 00000000..13e19f04 --- /dev/null +++ b/adi_library/cn0363/cn0363_phase_data_sync/Makefile @@ -0,0 +1,13 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := cn0363_phase_data_sync + +GENERIC_DEPS += cn0363_phase_data_sync.v + +XILINX_DEPS += cn0363_phase_data_sync_ip.tcl + +include ../../scripts/library.mk diff --git a/adi_library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v b/adi_library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v new file mode 100644 index 00000000..ab597253 --- /dev/null +++ b/adi_library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v @@ -0,0 +1,166 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module cn0363_phase_data_sync ( + input clk, + input resetn, + + input processing_resetn, + + output s_axis_sample_ready, + input s_axis_sample_valid, + input [7:0] s_axis_sample_data, + + input sample_has_stat, + + input conv_done, + input [31:0] phase, + + output reg m_axis_sample_valid, + input m_axis_sample_ready, + output [23:0] m_axis_sample_data, + + output reg m_axis_phase_valid, + input m_axis_phase_ready, + output [31:0] m_axis_phase_data, + + output reg overflow +); + + reg [1:0] data_counter = 'h00; + + reg [31:0] phase_hold = 'h00; + reg [23:0] sample_hold = 'h00; + reg sample_hold_valid = 1'b0; + reg conv_done_d1 = 1'b0; + + reg synced = 1'b0; + wire sync; + + /* The ADC will do conversions regardless of whether the pipeline is ready or + not. So we'll always accept new samples and assert overflow if necessary if + the pipeline is not ready. */ + assign s_axis_sample_ready = 1'b1; + + // Conversion from offset binary to signed on data + assign m_axis_sample_data = {~sample_hold[23],sample_hold[22:0]}; + assign m_axis_phase_data = phase_hold; + + always @(posedge clk) begin + if (conv_done_d1 == 1'b0 && conv_done == 1'b1) begin + // Is the processing pipeline ready to accept data? + if (m_axis_sample_valid | m_axis_phase_valid | ~processing_resetn) begin + overflow <= 1'b1; + end else begin + phase_hold <= phase; + overflow <= 1'b0; + end + end else begin + overflow <= 1'b0; + end + conv_done_d1 <= conv_done; + end + + always @(posedge clk) begin + if (processing_resetn == 1'b0) begin + m_axis_phase_valid <= 1'b0; + m_axis_sample_valid <= 1'b0; + end else begin + /* Data and phase become valid once we have both */ + if (sample_hold_valid == 1'b1) begin + m_axis_phase_valid <= 1'b1; + m_axis_sample_valid <= 1'b1; + end else begin + if (m_axis_phase_ready == 1'b1) begin + m_axis_phase_valid <= 1'b0; + end + if (m_axis_sample_ready == 1'b1) begin + m_axis_sample_valid <= 1'b0; + end + end + end + end + + /* If the STAT register is included in the sample we get 4 bytes per sample and + * are able to detect channel swaps and synchronize the first output sample to + * the first channel. If the STAT register is not included we only get 3 bytes + * per sample and rely on that the first sample will always be from the first + * channel */ + + always @(posedge clk) begin + sample_hold_valid <= 1'b0; + if (sample_has_stat == 1'b0) begin + if (s_axis_sample_valid == 1'b1 && data_counter == 2'h2) begin + sample_hold_valid <= 1'b1; + end + end else begin + if (s_axis_sample_valid == 1'b1 && data_counter == 2'h3 && + (sync == 1'b1 || synced == 1'b1)) begin + sample_hold_valid <= 1'b1; + end + end + end + + always @(posedge clk) begin + if (s_axis_sample_valid == 1'b1 && data_counter != 2'h3) begin + sample_hold <= {sample_hold[15:0],s_axis_sample_data}; + end + end + + always @(posedge clk) begin + if (s_axis_sample_valid == 1'b1) begin + if (data_counter == 2'h2 && sample_has_stat == 1'b0) begin + data_counter <= 2'h0; + end else begin + data_counter <= data_counter + 1'b1; + end + end + end + + assign sync = s_axis_sample_data[3:0] == 'h00 && data_counter == 'h3; + + always @(posedge clk) begin + if (processing_resetn == 1'b0) begin + synced <= ~sample_has_stat; + end else begin + if (s_axis_sample_valid == 1'b1 && sync == 1'b1) begin + synced <= 1'b1; + end + end + end + +endmodule diff --git a/adi_library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.xpr b/adi_library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.xpr new file mode 100644 index 00000000..03c8c67a --- /dev/null +++ b/adi_library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.xpr @@ -0,0 +1,399 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync_ip.tcl b/adi_library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync_ip.tcl new file mode 100644 index 00000000..8fc92f48 --- /dev/null +++ b/adi_library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync_ip.tcl @@ -0,0 +1,45 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create cn0363_phase_data_sync +adi_ip_files cn0363_phase_data_sync [list \ + "cn0363_phase_data_sync.v" +] + +adi_ip_properties_lite cn0363_phase_data_sync + +adi_add_bus "S_AXIS_SAMPLE" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"s_axis_sample_valid" "TVALID"} \ + {"s_axis_sample_ready" "TREADY"} \ + {"s_axis_sample_data" "TDATA"} \ + } + +adi_add_bus "M_AXIS_SAMPLE" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"m_axis_sample_valid" "TVALID"} \ + {"m_axis_sample_ready" "TREADY"} \ + {"m_axis_sample_data" "TDATA"} \ + } + +adi_add_bus "M_AXIS_PHASE" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"m_axis_phase_valid" "TVALID"} \ + {"m_axis_phase_ready" "TREADY"} \ + {"m_axis_phase_data" "TDATA"} \ + } + +adi_add_bus_clock "clk" "S_AXIS_SAMPLE:M_AXIS_SAMPLE:M_AXIS_PHASE" "resetn" + +ipx::save_core [ipx::current_core] diff --git a/adi_library/cn0363/cn0363_phase_data_sync/component.xml b/adi_library/cn0363/cn0363_phase_data_sync/component.xml new file mode 100644 index 00000000..d584ab91 --- /dev/null +++ b/adi_library/cn0363/cn0363_phase_data_sync/component.xml @@ -0,0 +1,514 @@ + + + analog.com + user + cn0363_phase_data_sync + 1.0 + + + S_AXIS_SAMPLE + + + + + + + TVALID + + + s_axis_sample_valid + + + + + TREADY + + + s_axis_sample_ready + + + + + TDATA + + + s_axis_sample_data + + + + + + M_AXIS_SAMPLE + + + + + + + TVALID + + + m_axis_sample_valid + + + + + TREADY + + + m_axis_sample_ready + + + + + TDATA + + + m_axis_sample_data + + + + + + M_AXIS_PHASE + + + + + + + TVALID + + + m_axis_phase_valid + + + + + TREADY + + + m_axis_phase_ready + + + + + TDATA + + + m_axis_phase_data + + + + + + S_AXIS_SAMPLE_M_AXIS_SAMPLE_M_AXIS_PHASE_signal_clock + S_AXIS_SAMPLE_M_AXIS_SAMPLE_M_AXIS_PHASE_signal_clock + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_BUSIF + S_AXIS_SAMPLE:M_AXIS_SAMPLE:M_AXIS_PHASE + + + ASSOCIATED_RESET + resetn + + + + + S_AXIS_SAMPLE_M_AXIS_SAMPLE_M_AXIS_PHASE_signal_reset + S_AXIS_SAMPLE_M_AXIS_SAMPLE_M_AXIS_PHASE_signal_reset + + + + + + + RST + + + resetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + cn0363_phase_data_sync + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 65377e13 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + cn0363_phase_data_sync + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 65377e13 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f92e9879 + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + resetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + processing_resetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_sample_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_sample_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_sample_data + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + sample_has_stat + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + conv_done + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + phase + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_sample_valid + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_sample_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_sample_data + + out + + 23 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_phase_valid + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_phase_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_phase_data + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + overflow + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + xilinx_anylanguagesynthesis_view_fileset + + cn0363_phase_data_sync.v + verilogSource + CHECKSUM_65377e13 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + cn0363_phase_data_sync.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/cn0363_phase_data_sync_v1_0.tcl + tclSource + CHECKSUM_f92e9879 + XGUI_VERSION_2 + + + + cn0363_phase_data_sync_v1_0 + + + Component_Name + cn0363_phase_data_sync_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + cn0363_phase_data_sync_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:49:46Z + + + 2023.2.1 + + + + + + diff --git a/adi_library/cn0363/cn0363_phase_data_sync/xgui/cn0363_phase_data_sync_v1_0.tcl b/adi_library/cn0363/cn0363_phase_data_sync/xgui/cn0363_phase_data_sync_v1_0.tcl new file mode 100644 index 00000000..0db18e9a --- /dev/null +++ b/adi_library/cn0363/cn0363_phase_data_sync/xgui/cn0363_phase_data_sync_v1_0.tcl @@ -0,0 +1,10 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + + diff --git a/adi_library/common/ad_3w_spi.v b/adi_library/common/ad_3w_spi.v new file mode 100644 index 00000000..bd7cb4b4 --- /dev/null +++ b/adi_library/common/ad_3w_spi.v @@ -0,0 +1,105 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +// +// A 4-wire to 3-wire SPI converter, supporting maximum 8 slaves. +// The expected transfer format is defined in ADI_SPI technical specification +// (https://wiki.analog.com/_media/resources/technical-guides/adispi_rev_1p0_customer.pdf) +// +// 16 bit instruction followed by N x 8 bits of data; the MSB bit of the +// instruction defines the direction of the SDIO during data transfer. (READ +// is 1 and WRITE is 0) +// + +module ad_3w_spi #( + + parameter NUM_OF_SLAVES = 8 +) ( + input [NUM_OF_SLAVES-1:0] spi_csn, + input spi_clk, + input spi_mosi, + output spi_miso, + + inout spi_sdio, + output spi_dir +); + + // internal registers + + reg [ 5:0] spi_count = 'd0; + reg spi_rd_wr_n = 'd0; + reg spi_enable = 'd0; + + // internal signals + + wire spi_csn_s; + wire spi_enable_s; + + // check on rising edge and change on falling edge + + assign spi_csn_s = & spi_csn; + assign spi_dir = ~spi_enable_s; + assign spi_enable_s = spi_enable & ~spi_csn_s; + + always @(posedge spi_clk or posedge spi_csn_s) begin + if (spi_csn_s == 1'b1) begin + spi_count <= 6'd0; + spi_rd_wr_n <= 1'd0; + end else begin + spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count; + if (spi_count == 6'd0) begin + spi_rd_wr_n <= spi_mosi; + end + end + end + + always @(negedge spi_clk or posedge spi_csn_s) begin + if (spi_csn_s == 1'b1) begin + spi_enable <= 1'b0; + end else begin + if (spi_count == 6'd16) begin + spi_enable <= spi_rd_wr_n; + end + end + end + + // io butter + + assign spi_miso = spi_sdio; + assign spi_sdio = (spi_enable_s == 1'b1) ? 1'bz : spi_mosi; + +endmodule diff --git a/adi_library/common/ad_addsub.v b/adi_library/common/ad_addsub.v new file mode 100644 index 00000000..8b515973 --- /dev/null +++ b/adi_library/common/ad_addsub.v @@ -0,0 +1,116 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +// A simple adder/substracter width preconfigured input ports width and turn-around value +// Output = A - B_constant or A + B_constant +// Constraints: Awidth >= Bwidth + +`timescale 1ns/1ps + +module ad_addsub #( + + parameter A_DATA_WIDTH = 32, + parameter B_DATA_VALUE = 32'h1, + parameter ADD_OR_SUB_N = 0 +) ( + input clk, + input [(A_DATA_WIDTH-1):0] A, + input [(A_DATA_WIDTH-1):0] Amax, + output reg [(A_DATA_WIDTH-1):0] out, + input CE +); + + localparam ADDER = 1; + localparam SUBSTRACTER = 0; + + // registers + + reg [A_DATA_WIDTH:0] out_d = 'b0; + reg [A_DATA_WIDTH:0] out_d2 = 'b0; + reg [(A_DATA_WIDTH-1):0] A_d = 'b0; + reg [(A_DATA_WIDTH-1):0] Amax_d = 'b0; + reg [(A_DATA_WIDTH-1):0] Amax_d2 = 'b0; + + // constant regs + + reg [(A_DATA_WIDTH-1):0] B_reg = B_DATA_VALUE; + + // latch the inputs + + always @(posedge clk) begin + A_d <= A; + Amax_d <= Amax; + Amax_d2 <= Amax_d; + end + + // ADDER/SUBSTRACTER + + always @(posedge clk) begin + if ( ADD_OR_SUB_N == ADDER ) begin + out_d <= A_d + B_reg; + end else begin + out_d <= A_d - B_reg; + end + end + + // Resolve + + always @(posedge clk) begin + if ( ADD_OR_SUB_N == ADDER ) begin + if ( out_d > Amax_d2 ) begin + out_d2 <= out_d - Amax_d2; + end else begin + out_d2 <= out_d; + end + end else begin // SUBSTRACTER + if ( out_d[A_DATA_WIDTH] == 1'b1 ) begin + out_d2 <= Amax_d2 + out_d; + end else begin + out_d2 <= out_d; + end + end + end + + // output logic + + always @(posedge clk) begin + if ( CE ) begin + out <= out_d2; + end else begin + out <= 'b0; + end + end + +endmodule diff --git a/adi_library/common/ad_adl5904_rst.v b/adi_library/common/ad_adl5904_rst.v new file mode 100644 index 00000000..1b305f85 --- /dev/null +++ b/adi_library/common/ad_adl5904_rst.v @@ -0,0 +1,76 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_adl5904_rst ( + + input sys_cpu_clk, + input rf_peak_det_n, + output rf_peak_rst +); + + // internal registers + + reg rf_peak_det_n_d = 'd0; + reg rf_peak_det_enb_d = 'd0; + reg rf_peak_rst_enb = 'd0; + reg rf_peak_rst_int = 'd0; + + // internal signals + + wire rf_peak_det_enb_s; + wire rf_peak_rst_1_s; + wire rf_peak_rst_0_s; + + // adl5904 input protection + + assign rf_peak_rst = rf_peak_rst_int; + assign rf_peak_det_enb_s = ~(rf_peak_det_n_d & rf_peak_det_n); + assign rf_peak_rst_1_s = ~rf_peak_det_enb_d & rf_peak_det_enb_s; + assign rf_peak_rst_0_s = rf_peak_det_enb_d & ~rf_peak_det_enb_s; + + always @(posedge sys_cpu_clk) begin + rf_peak_det_n_d <= rf_peak_det_n; + rf_peak_det_enb_d <= rf_peak_det_enb_s; + if (rf_peak_rst_1_s == 1'b1) begin + rf_peak_rst_enb <= 1'b1; + end else if (rf_peak_rst_0_s == 1'b1) begin + rf_peak_rst_enb <= 1'b0; + end + rf_peak_rst_int = ~rf_peak_rst_int & rf_peak_rst_enb; + end + +endmodule diff --git a/adi_library/common/ad_axis_inf_rx.v b/adi_library/common/ad_axis_inf_rx.v new file mode 100644 index 00000000..8da4105a --- /dev/null +++ b/adi_library/common/ad_axis_inf_rx.v @@ -0,0 +1,195 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_axis_inf_rx #( + + parameter DATA_WIDTH = 16 +) ( + + // adi interface + + input clk, + input rst, + input valid, + input last, + input [(DATA_WIDTH-1):0] data, + + // xilinx interface + + output reg inf_valid = 1'b0, + output reg inf_last = 1'b0, + output reg [(DATA_WIDTH-1):0] inf_data = {DATA_WIDTH{1'b0}}, + input inf_ready, + + output int_not_full +); + + // internal registers + + reg [ 2:0] wcnt = 'd0; + reg wlast_0 = 'd0; + reg [(DATA_WIDTH-1):0] wdata_0 = 'd0; + reg wlast_1 = 'd0; + reg [(DATA_WIDTH-1):0] wdata_1 = 'd0; + reg wlast_2 = 'd0; + reg [(DATA_WIDTH-1):0] wdata_2 = 'd0; + reg wlast_3 = 'd0; + reg [(DATA_WIDTH-1):0] wdata_3 = 'd0; + reg wlast_4 = 'd0; + reg [(DATA_WIDTH-1):0] wdata_4 = 'd0; + reg wlast_5 = 'd0; + reg [(DATA_WIDTH-1):0] wdata_5 = 'd0; + reg wlast_6 = 'd0; + reg [(DATA_WIDTH-1):0] wdata_6 = 'd0; + reg wlast_7 = 'd0; + reg [(DATA_WIDTH-1):0] wdata_7 = 'd0; + reg [ 2:0] rcnt = 'd0; + + // internal signals + + wire inf_ready_s; + reg inf_last_s; + reg [(DATA_WIDTH-1):0] inf_data_s; + + // write interface + + always @(posedge clk) begin + if (rst == 1'b1) begin + wcnt <= 'd0; + end else if (valid == 1'b1) begin + wcnt <= wcnt + 1'b1; + end + if ((wcnt == 3'd0) && (valid == 1'b1)) begin + wlast_0 <= last; + wdata_0 <= data; + end + if ((wcnt == 3'd1) && (valid == 1'b1)) begin + wlast_1 <= last; + wdata_1 <= data; + end + if ((wcnt == 3'd2) && (valid == 1'b1)) begin + wlast_2 <= last; + wdata_2 <= data; + end + if ((wcnt == 3'd3) && (valid == 1'b1)) begin + wlast_3 <= last; + wdata_3 <= data; + end + if ((wcnt == 3'd4) && (valid == 1'b1)) begin + wlast_4 <= last; + wdata_4 <= data; + end + if ((wcnt == 3'd5) && (valid == 1'b1)) begin + wlast_5 <= last; + wdata_5 <= data; + end + if ((wcnt == 3'd6) && (valid == 1'b1)) begin + wlast_6 <= last; + wdata_6 <= data; + end + if ((wcnt == 3'd7) && (valid == 1'b1)) begin + wlast_7 <= last; + wdata_7 <= data; + end + end + + // read interface + + assign inf_ready_s = inf_ready | ~inf_valid; + assign int_not_full = inf_ready_s; + + always @(rcnt or wlast_0 or wdata_0 or wlast_1 or wdata_1 or + wlast_2 or wdata_2 or wlast_3 or wdata_3 or wlast_4 or wdata_4 or + wlast_5 or wdata_5 or wlast_6 or wdata_6 or wlast_7 or wdata_7) begin + case (rcnt) + 3'd0: begin + inf_last_s = wlast_0; + inf_data_s = wdata_0; + end + 3'd1: begin + inf_last_s = wlast_1; + inf_data_s = wdata_1; + end + 3'd2: begin + inf_last_s = wlast_2; + inf_data_s = wdata_2; + end + 3'd3: begin + inf_last_s = wlast_3; + inf_data_s = wdata_3; + end + 3'd4: begin + inf_last_s = wlast_4; + inf_data_s = wdata_4; + end + 3'd5: begin + inf_last_s = wlast_5; + inf_data_s = wdata_5; + end + 3'd6: begin + inf_last_s = wlast_6; + inf_data_s = wdata_6; + end + default: begin + inf_last_s = wlast_7; + inf_data_s = wdata_7; + end + endcase + end + + always @(posedge clk) begin + if (rst == 1'b1) begin + rcnt <= 'd0; + inf_valid <= 'd0; + inf_last <= 'b0; + inf_data <= 'd0; + end else if (inf_ready_s == 1'b1) begin + if (rcnt == wcnt) begin + rcnt <= rcnt; + inf_valid <= 1'd0; + inf_last <= 1'b0; + inf_data <= 'd0; + end else begin + rcnt <= rcnt + 1'b1; + inf_valid <= 1'b1; + inf_last <= inf_last_s; + inf_data <= inf_data_s; + end + end + end + +endmodule diff --git a/adi_library/common/ad_b2g.v b/adi_library/common/ad_b2g.v new file mode 100644 index 00000000..5fcadfe4 --- /dev/null +++ b/adi_library/common/ad_b2g.v @@ -0,0 +1,59 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_b2g #( + + parameter DATA_WIDTH = 8 +) ( + input [DATA_WIDTH-1:0] din, + output [DATA_WIDTH-1:0] dout +); + + function [DATA_WIDTH-1:0] b2g; + input [DATA_WIDTH-1:0] b; + integer i; + begin + b2g[DATA_WIDTH-1] = b[DATA_WIDTH-1]; + for (i = DATA_WIDTH-1; i > 0; i = i -1) begin + b2g[i-1] = b[i] ^ b[i-1]; + end + end + endfunction + + assign dout = b2g(din); + +endmodule diff --git a/adi_library/common/ad_bus_mux.v b/adi_library/common/ad_bus_mux.v new file mode 100644 index 00000000..95336bb7 --- /dev/null +++ b/adi_library/common/ad_bus_mux.v @@ -0,0 +1,62 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_bus_mux #( + + // Channel data width + parameter DATA_WIDTH = 16 +) ( + input select_path, + + input valid_in_0, + input enable_in_0, + input [DATA_WIDTH-1:0] data_in_0, + + input valid_in_1, + input enable_in_1, + input [DATA_WIDTH-1:0] data_in_1, + + output valid_out, + output enable_out, + output [DATA_WIDTH-1:0] data_out +); + + assign valid_out = (select_path == 0) ? valid_in_0 : valid_in_1; + assign enable_out = (select_path == 0) ? enable_in_0 : enable_in_1; + assign data_out = (select_path == 0) ? data_in_0 : data_in_1; + +endmodule diff --git a/adi_library/common/ad_csc.v b/adi_library/common/ad_csc.v new file mode 100644 index 00000000..a9aac8b3 --- /dev/null +++ b/adi_library/common/ad_csc.v @@ -0,0 +1,143 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// csc = c1*d[23:16] + c2*d[15:8] + c3*d[7:0] + c4; + +`timescale 1ns/100ps + +module ad_csc #( + + parameter DELAY_DW = 16, + parameter MUL_COEF_DW = 17, + parameter SUM_COEF_DW = 24, + parameter YCbCr_2_RGB = 0 +) ( + + // data + + input clk, + input [ DELAY_DW-1:0] sync, + input [ 23:0] data, + + // constants + + input signed [MUL_COEF_DW-1:0] C1, + input signed [MUL_COEF_DW-1:0] C2, + input signed [MUL_COEF_DW-1:0] C3, + input signed [SUM_COEF_DW-1:0] C4, + + // sync is delay matched + + output [ DELAY_DW-1:0] csc_sync, + output [ 7:0] csc_data +); + + localparam PIXEL_WD = 9; // sign extended + localparam MUL_DW = MUL_COEF_DW + PIXEL_WD -1; + + // internal wires + + reg signed [ 23:0] data_d1; + reg signed [ 23:0] data_d2; + reg signed [ MUL_DW:0] data_1; + reg signed [ MUL_DW:0] data_2; + reg signed [ MUL_DW:0] data_3; + reg signed [ MUL_DW:0] s_data_1; + reg signed [ MUL_DW:0] s_data_2; + reg signed [ MUL_DW:0] s_data_3; + reg [DELAY_DW-1:0] sync_1_m; + reg [DELAY_DW-1:0] sync_2_m; + reg [DELAY_DW-1:0] sync_3_m; + reg [DELAY_DW-1:0] sync_4_m; + reg [ 7:0] csc_data_d; + + wire signed [8:0] color1; + wire signed [8:0] color2; + wire signed [8:0] color3; + + // delay signals + + always @(posedge clk) begin + data_d1 <= data; + data_d2 <= data_d1; + sync_1_m <= sync; + sync_2_m <= sync_1_m; + sync_3_m <= sync_2_m; + sync_4_m <= sync_3_m; + end + + assign color1 = {1'd0, data[23:16]}; + assign color2 = {1'd0, data_d1[15: 8]}; + assign color3 = {1'd0, data_d2[ 7: 0]}; + + // pipeline DSPs for multiplications and additions + + always @(posedge clk) begin + data_1 <= color1 * C1; + data_2 <= color2 * C2; + data_3 <= color3 * C3; + end + + always @(posedge clk) begin + s_data_1 <= data_1 + C4; + s_data_2 <= s_data_1 + data_2; + s_data_3 <= s_data_2 + data_3; + end + + generate + // in RGB to YCbCr there are no overflows or underflows + if (YCbCr_2_RGB) begin + reg [DELAY_DW-1:0] sync_5_m; + // output registers, output is unsigned (0 if sum is < 0) and saturated. + // the inputs are expected to be 1.4.20 format (output is 8bits). + + always @(posedge clk) begin + if (s_data_3[27] == 1'b1) begin + csc_data_d <= 8'h0; + end else if (s_data_3[26:24] != 3'b0) begin + csc_data_d <= 8'hff; + end else begin + csc_data_d <= s_data_3[22:15]; + end + sync_5_m <= sync_4_m; + end + assign csc_data = csc_data_d; + assign csc_sync = sync_5_m; + end else begin + assign csc_data = s_data_3[23:16]; + assign csc_sync = sync_4_m; + end + endgenerate + +endmodule diff --git a/adi_library/common/ad_csc_CrYCb2RGB.v b/adi_library/common/ad_csc_CrYCb2RGB.v new file mode 100644 index 00000000..184966e9 --- /dev/null +++ b/adi_library/common/ad_csc_CrYCb2RGB.v @@ -0,0 +1,115 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// Transmit HDMI, CrYCb to RGB conversion +// The multiplication coefficients are in 1.4.12 format +// The addition coefficients are in 1.12.12 format +// R = (+408.583/256)*Cr + (+298.082/256)*Y + ( 000.000/256)*Cb + (-222.921); +// G = (-208.120/256)*Cr + (+298.082/256)*Y + (-100.291/256)*Cb + (+135.576); +// B = ( 000.000/256)*Cr + (+298.082/256)*Y + (+516.412/256)*Cb + (-276.836); + +`timescale 1ns/100ps + +module ad_csc_CrYCb2RGB #( + + parameter DELAY_DATA_WIDTH = 16 +) ( + + // Cr-Y-Cb inputs + + input clk, + input [DELAY_DATA_WIDTH-1:0] CrYCb_sync, + input [23:0] CrYCb_data, + + // R-G-B outputs + + output [DELAY_DATA_WIDTH-1:0] RGB_sync, + output [23:0] RGB_data +); + + localparam DW = DELAY_DATA_WIDTH - 1; + + // red + + ad_csc #( + .DELAY_DW (DELAY_DATA_WIDTH), + .MUL_COEF_DW (18), + .SUM_COEF_DW (28), + .YCbCr_2_RGB (1) + ) i_csc_R ( + .clk (clk), + .sync (CrYCb_sync), + .data (CrYCb_data), + .C1 ( 18'd52299), + .C2 ( 18'd38154), + .C3 ( 18'd0), + .C4 (-28'd7304675), + .csc_sync (RGB_sync), + .csc_data (RGB_data[23:16])); + + // green + + ad_csc #( + .MUL_COEF_DW (18), + .SUM_COEF_DW (28), + .YCbCr_2_RGB (1) + ) i_csc_G ( + .clk (clk), + .sync (1'd0), + .data (CrYCb_data), + .C1 (-18'd26639), + .C2 ( 18'd38154), + .C3 (-18'd12837), + .C4 ( 28'd4442554), + .csc_sync (), + .csc_data (RGB_data[15:8])); + + // blue + + ad_csc #( + .MUL_COEF_DW (18), + .SUM_COEF_DW (28), + .YCbCr_2_RGB (1) + ) i_csc_B ( + .clk (clk), + .sync (1'd0), + .data (CrYCb_data), + .C1 ( 18'd0), + .C2 ( 18'd38154), + .C3 ( 18'd66101), + .C4 (-28'd9071362), + .csc_sync (), + .csc_data (RGB_data[7:0])); + +endmodule diff --git a/adi_library/common/ad_csc_RGB2CrYCb.v b/adi_library/common/ad_csc_RGB2CrYCb.v new file mode 100644 index 00000000..387bef45 --- /dev/null +++ b/adi_library/common/ad_csc_RGB2CrYCb.v @@ -0,0 +1,108 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// Transmit HDMI, RGB to CrYCb conversion +// The multiplication coefficients are in 1.4.12 format +// The addition coefficients are in 1.12.12 format +// Cr = (+112.439/256)*R + (-094.154/256)*G + (-018.285/256)*B + 128; +// Y = (+065.738/256)*R + (+129.057/256)*G + (+025.064/256)*B + 16; +// Cb = (-037.945/256)*R + (-074.494/256)*G + (+112.439/256)*B + 128; + +`timescale 1ns/100ps + +module ad_csc_RGB2CrYCb #( + + parameter DELAY_DATA_WIDTH = 16 +) ( + + // R-G-B inputs + + input clk, + input [DELAY_DATA_WIDTH-1:0] RGB_sync, + input [23:0] RGB_data, + + // Cr-Y-Cb outputs + + output [DELAY_DATA_WIDTH-1:0] CrYCb_sync, + output [23:0] CrYCb_data +); + + localparam DW = DELAY_DATA_WIDTH - 1; + + // Cr (red-diff) + + ad_csc #( + .DELAY_DW(DELAY_DATA_WIDTH) + ) j_csc_1_Cr ( + .clk (clk), + .sync (RGB_sync), + .data (RGB_data), + .C1 ( 17'd28784), // 112.439 + .C2 (-17'd24103), // -94.154 + .C3 (-17'd4681), // -18.285 + .C4 ( 24'd8388608), // 128 + .csc_sync (CrYCb_sync), + .csc_data (CrYCb_data[23:16])); + + // Y (luma) + + ad_csc #( + .DELAY_DW(0) + ) j_csc_1_Y ( + .clk (clk), + .sync (1'd0), + .data (RGB_data), + .C1 (17'd16829), // 65.739 + .C2 (17'd33039), // 129.057 + .C3 (17'd6416), // 25.064 + .C4 (24'd1048576), // 16 + .csc_sync (), + .csc_data (CrYCb_data[15:8])); + + // Cb (blue-diff) + + ad_csc #( + .DELAY_DW(0) + ) j_csc_1_Cb ( + .clk (clk), + .sync (1'd0), + .data (RGB_data), + .C1 (-17'd9714), // -37.945 + .C2 (-17'd19070), // -74.494 + .C3 ( 17'd28784), // 112.439 + .C4 (24'd8388608), // 128 + .csc_sync (), + .csc_data (CrYCb_data[7:0])); + +endmodule diff --git a/adi_library/common/ad_datafmt.v b/adi_library/common/ad_datafmt.v new file mode 100644 index 00000000..0859e265 --- /dev/null +++ b/adi_library/common/ad_datafmt.v @@ -0,0 +1,108 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// data format (offset binary or 2's complement only) + +`timescale 1ps/1ps + +module ad_datafmt #( + + // data bus width + + parameter DATA_WIDTH = 16, + parameter BITS_PER_SAMPLE = 16, + parameter DISABLE = 0 +) ( + + // data path + + input clk, + input valid, + input [(DATA_WIDTH-1):0] data, + output valid_out, + output [(BITS_PER_SAMPLE-1):0] data_out, + + // control signals + + input dfmt_enable, + input dfmt_type, + input dfmt_se +); + + // internal registers + + reg valid_int = 'd0; + reg [(BITS_PER_SAMPLE-1):0] data_int = 'd0; + + // internal signals + + wire type_s; + wire [(BITS_PER_SAMPLE-1):0] data_out_s; + + // data-path disable + + generate + if (DISABLE == 1) begin + assign valid_out = valid; + assign data_out = data; + end else begin + assign valid_out = valid_int; + assign data_out = data_int; + end + endgenerate + + // if offset-binary convert to 2's complement first + + assign type_s = dfmt_enable & dfmt_type; + + generate + if (DATA_WIDTH < BITS_PER_SAMPLE) begin + wire signext_s; + wire sign_s; + + assign signext_s = dfmt_enable & dfmt_se; + assign sign_s = signext_s & (type_s ^ data[(DATA_WIDTH-1)]); + assign data_out_s[(BITS_PER_SAMPLE-1):DATA_WIDTH] = {((BITS_PER_SAMPLE)-DATA_WIDTH){sign_s}}; + end + endgenerate + + assign data_out_s[(DATA_WIDTH-1)] = type_s ^ data[(DATA_WIDTH-1)]; + assign data_out_s[(DATA_WIDTH-2):0] = data[(DATA_WIDTH-2):0]; + + always @(posedge clk) begin + valid_int <= valid; + data_int <= data_out_s; + end + +endmodule diff --git a/adi_library/common/ad_dds.v b/adi_library/common/ad_dds.v new file mode 100644 index 00000000..2aa40814 --- /dev/null +++ b/adi_library/common/ad_dds.v @@ -0,0 +1,168 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +// single channel dds (dual tone) +module ad_dds #( + + parameter DISABLE = 0, + // range 8-24 + parameter DDS_DW = 16, + // range 8-32 + parameter PHASE_DW = 16, + // set 1 for CORDIC or 2 for Polynomial + parameter DDS_TYPE = 1, + // range 8-24 + parameter CORDIC_DW = 16, + // range 8-24 (make sure CORDIC_PHASE_DW < CORDIC_DW) + parameter CORDIC_PHASE_DW = 16, + // the clock radtio between the device clock(sample rate) and the dac_core clock + // 2^N, 1 1)begin + dac_dds_phase_0[i] <= dac_dds_phase_0[i-1] + tone_1_freq_word; + dac_dds_phase_1[i] <= dac_dds_phase_1[i-1] + tone_2_freq_word; + end + end else if (dac_valid == 1'b1) begin + dac_dds_phase_0[i] <= dac_dds_phase_0[i] + dac_dds_incr_0; + dac_dds_phase_1[i] <= dac_dds_phase_1[i] + dac_dds_incr_1; + end + + if (dac_data_sync == 1'b1 || sync_min_pulse_m[1]) begin + dac_dds_phase_0_m[i] <= 'd0; + dac_dds_phase_1_m[i] <= 'd0; + end else begin + dac_dds_phase_0_m[i] <= dac_dds_phase_0[i]; + dac_dds_phase_1_m[i] <= dac_dds_phase_1[i]; + end + end + + // phase to amplitude convertor + ad_dds_2 #( + .DDS_DW (DDS_DW), + .PHASE_DW (PHASE_DW), + .DDS_TYPE (DDS_TYPE), + .CORDIC_DW (CORDIC_DW), + .CORDIC_PHASE_DW (CORDIC_PHASE_DW) + ) i_dds_2 ( + .clk (clk), + .dds_format (dac_dds_format), + .dds_phase_0 (dac_dds_phase_0_m[i]), + .dds_scale_0 (tone_1_scale), + .dds_phase_1 (dac_dds_phase_1_m[i]), + .dds_scale_1 (tone_2_scale), + .dds_data (dac_dds_data_s[(DDS_DW*i)-1:DDS_DW*(i-1)])); + end + end + endgenerate + +endmodule diff --git a/adi_library/common/ad_dds_1.v b/adi_library/common/ad_dds_1.v new file mode 100644 index 00000000..59b299f4 --- /dev/null +++ b/adi_library/common/ad_dds_1.v @@ -0,0 +1,114 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_dds_1 #( + + // parameters + + parameter DDS_TYPE = 1, + parameter DDS_D_DW = 16, + parameter DDS_P_DW = 16 +) ( + + // interface + + input clk, + input [DDS_P_DW-1:0] angle, + input [ 15:0] scale, + output reg [DDS_D_DW-1:0] dds_data +); + + // local parameters + + localparam DDS_CORDIC_TYPE = 1; + localparam DDS_POLINOMIAL_TYPE = 2; + + // internal signals + + wire [ DDS_D_DW-1:0] sine_s; + wire [DDS_D_DW+17:0] s1_data_s; + + // sine + + generate + if (DDS_TYPE == DDS_CORDIC_TYPE) begin + + ad_dds_sine_cordic #( + .CORDIC_DW(DDS_D_DW), + .PHASE_DW(DDS_P_DW), + .DELAY_DW(1) + ) i_dds_sine ( + .clk (clk), + .angle (angle), + .sine (sine_s), + .cosine (), + .ddata_in (1'b0), + .ddata_out ()); + + end else begin + + ad_dds_sine i_dds_sine ( + .clk (clk), + .angle (angle), + .sine (sine_s), + .ddata_in (1'b0), + .ddata_out ()); + end + endgenerate + + // scale for a sine generator + + ad_mul #( + .A_DATA_WIDTH(DDS_D_DW + 1), + .B_DATA_WIDTH(17), + .DELAY_DATA_WIDTH(1) + ) i_dds_scale ( + .clk (clk), + .data_a ({sine_s[DDS_D_DW-1], sine_s}), + .data_b ({scale[15], scale}), + .data_p (s1_data_s), + .ddata_in (1'b0), + .ddata_out ()); + + // dds data + + always @(posedge clk) begin + //15'h8000 is the maximum scale + dds_data <= s1_data_s[DDS_D_DW+13:14]; + end + +endmodule diff --git a/adi_library/common/ad_dds_2.v b/adi_library/common/ad_dds_2.v new file mode 100644 index 00000000..db7801d6 --- /dev/null +++ b/adi_library/common/ad_dds_2.v @@ -0,0 +1,155 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_dds_2 #( + + // Range = 8-24 + parameter DDS_DW = 16, + // Range = 8-24 + parameter PHASE_DW = 16, + // Set 1 for CORDIC or 2 for Polynomial + parameter DDS_TYPE = 1, + // Range = 8-24 + parameter CORDIC_DW = 16, + // Range = 8-24 ( make sure CORDIC_PHASE_DW < CORDIC_DW) + parameter CORDIC_PHASE_DW = 16 +) ( + + // interface + + input clk, + input dds_format, + input [PHASE_DW-1:0] dds_phase_0, + input [ 15:0] dds_scale_0, + input [PHASE_DW-1:0] dds_phase_1, + input [ 15:0] dds_scale_1, + output [ DDS_DW-1:0] dds_data +); + + // Local parameters + + localparam CORDIC = 1; + localparam POLYNOMIAL = 2; + + // The width for Polynomial DDS is fixed (16) + localparam DDS_D_DW = (DDS_TYPE == CORDIC) ? CORDIC_DW : 16; + localparam DDS_P_DW = (DDS_TYPE == CORDIC) ? CORDIC_PHASE_DW : 16; + // concatenation or truncation width + localparam C_T_WIDTH = (DDS_D_DW > DDS_DW) ? (DDS_D_DW - DDS_DW) : (DDS_DW - DDS_D_DW); + + // internal registers + + reg [ DDS_DW-1:0] dds_data_width = 0; + reg [DDS_D_DW-1:0] dds_data_rownd = 0; + reg [DDS_D_DW-1:0] dds_data_int = 0; + reg [ 15:0] dds_scale_0_d = 0; + reg [ 15:0] dds_scale_1_d = 0; + reg [ DDS_DW-1:0] dds_data_out = 0; + + // internal signals + + wire [DDS_D_DW-1:0] dds_data_0_s; + wire [DDS_D_DW-1:0] dds_data_1_s; + wire [DDS_P_DW-1:0] dds_phase_0_s; + wire [DDS_P_DW-1:0] dds_phase_1_s; + + generate + // dds channel output + assign dds_data = dds_data_out; + + // output data format + always @(posedge clk) begin + dds_data_out[DDS_DW-1] <= dds_data_width[DDS_DW-1] ^ dds_format; + dds_data_out[DDS_DW-2: 0] <= dds_data_width[DDS_DW-2: 0]; + end + + // set desired data width + always @(posedge clk) begin + if (DDS_DW < DDS_D_DW) begin // truncation + // fair rownding + dds_data_rownd <= dds_data_int + {(C_T_WIDTH){dds_data_int[DDS_D_DW-1]}}; + dds_data_width <= dds_data_rownd[DDS_D_DW-1:DDS_D_DW-DDS_DW]; + end else begin // concatenation + dds_data_width <= dds_data_int << C_T_WIDTH; + end + end + + // dual tone + always @(posedge clk) begin + dds_data_int <= dds_data_0_s + dds_data_1_s; + end + + always @(posedge clk) begin + dds_scale_0_d <= dds_scale_0; + dds_scale_1_d <= dds_scale_1; + end + + // phase + if (DDS_P_DW > PHASE_DW) begin + assign dds_phase_0_s = {dds_phase_0,{DDS_P_DW-PHASE_DW{1'b0}}}; + assign dds_phase_1_s = {dds_phase_1,{DDS_P_DW-PHASE_DW{1'b0}}}; + end else begin + assign dds_phase_0_s = dds_phase_0[(PHASE_DW-1):PHASE_DW-DDS_P_DW]; + assign dds_phase_1_s = dds_phase_1[(PHASE_DW-1):PHASE_DW-DDS_P_DW]; + end + + // dds-1 + + ad_dds_1 #( + .DDS_TYPE(DDS_TYPE), + .DDS_D_DW(DDS_D_DW), + .DDS_P_DW(DDS_P_DW) + ) i_dds_1_0 ( + .clk (clk), + .angle (dds_phase_0_s), + .scale (dds_scale_0_d), + .dds_data (dds_data_0_s)); + + // dds-2 + + ad_dds_1 #( + .DDS_TYPE(DDS_TYPE), + .DDS_D_DW(DDS_D_DW), + .DDS_P_DW(DDS_P_DW) + ) i_dds_1_1 ( + .clk (clk), + .angle (dds_phase_1_s), + .scale (dds_scale_1_d), + .dds_data (dds_data_1_s)); + endgenerate + +endmodule diff --git a/adi_library/common/ad_dds_cordic_pipe.v b/adi_library/common/ad_dds_cordic_pipe.v new file mode 100644 index 00000000..2bff8a22 --- /dev/null +++ b/adi_library/common/ad_dds_cordic_pipe.v @@ -0,0 +1,102 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_dds_cordic_pipe#( + + // parameters + + // Range = N/A + parameter P_DW = 16, + // Range = N/A + parameter D_DW = 16, + // Range = N/A + parameter DELAY_DW = 1, + // Range = 0-(DW - 1) + parameter SHIFT = 0 +) ( + + // Interface + + input clk, + (* keep = "TRUE" *) input dir, + (* keep = "TRUE" *) input [ D_DW-1:0] dataa_x, + (* keep = "TRUE" *) input [ D_DW-1:0] dataa_y, + (* keep = "TRUE" *) input [ P_DW-1:0] dataa_z, + (* keep = "TRUE" *) input [ P_DW-1:0] datab_z, + (* keep = "TRUE" *) output reg [ D_DW-1:0] result_x, + (* keep = "TRUE" *) output reg [ D_DW-1:0] result_y, + (* keep = "TRUE" *) output reg [ P_DW-1:0] result_z, + input [DELAY_DW:1] data_delay_in, + output [DELAY_DW:1] data_delay_out +); + + // Registers Declarations + + reg [DELAY_DW:1] data_delay = 'd0; + + // Wires Declarations + + wire [ D_DW-1:0] sgn_shift_x; + wire [ D_DW-1:0] sgn_shift_y; + wire dir_inv = ~dir; + + // Sign shift + + assign sgn_shift_x = {{SHIFT{dataa_x[D_DW-1]}}, dataa_x[D_DW-1:SHIFT]}; + assign sgn_shift_y = {{SHIFT{dataa_y[D_DW-1]}}, dataa_y[D_DW-1:SHIFT]}; + + // Stage rotation + + always @(posedge clk) begin + result_x <= dataa_x + ({D_DW{dir_inv}} ^ sgn_shift_y) + dir_inv; + result_y <= dataa_y + ({D_DW{dir}} ^ sgn_shift_x) + dir; + result_z <= dataa_z + ({P_DW{dir_inv}} ^ datab_z) + dir_inv; + end + + // Delay data (if used) + + generate + if (DELAY_DW > 1) begin + always @(posedge clk) begin + data_delay <= data_delay_in; + end + end + endgenerate + + assign data_delay_out = data_delay; + +endmodule diff --git a/adi_library/common/ad_dds_sine.v b/adi_library/common/ad_dds_sine.v new file mode 100644 index 00000000..68696305 --- /dev/null +++ b/adi_library/common/ad_dds_sine.v @@ -0,0 +1,213 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// this is a sine function (approximate), the basic idea is to approximate sine as a +// polynomial function (there are a lot of stuff about this on the web) + +`timescale 1ns/100ps + +module ad_dds_sine #( + + parameter DELAY_DATA_WIDTH = 16 +) ( + + // sine = sin(angle) + + input clk, + input [15:0] angle, + output [15:0] sine, + input [(DELAY_DATA_WIDTH-1):0] ddata_in, + output [(DELAY_DATA_WIDTH-1):0] ddata_out +); + + // internal registers + + reg [33:0] s1_data_p = 'd0; + reg [33:0] s1_data_n = 'd0; + reg [15:0] s1_angle = 'd0; + reg [(DELAY_DATA_WIDTH-1):0] s1_ddata = 'd0; + reg [18:0] s2_data_0 = 'd0; + reg [18:0] s2_data_1 = 'd0; + reg [(DELAY_DATA_WIDTH-1):0] s2_ddata = 'd0; + reg [18:0] s3_data = 'd0; + reg [(DELAY_DATA_WIDTH-1):0] s3_ddata = 'd0; + reg [33:0] s4_data2_p = 'd0; + reg [33:0] s4_data2_n = 'd0; + reg [16:0] s4_data1_p = 'd0; + reg [16:0] s4_data1_n = 'd0; + reg [(DELAY_DATA_WIDTH-1):0] s4_ddata = 'd0; + reg [16:0] s5_data2_0 = 'd0; + reg [16:0] s5_data2_1 = 'd0; + reg [16:0] s5_data1 = 'd0; + reg [(DELAY_DATA_WIDTH-1):0] s5_ddata = 'd0; + reg [16:0] s6_data2 = 'd0; + reg [16:0] s6_data1 = 'd0; + reg [(DELAY_DATA_WIDTH-1):0] s6_ddata = 'd0; + reg [33:0] s7_data = 'd0; + reg [(DELAY_DATA_WIDTH-1):0] s7_ddata = 'd0; + reg [15:0] sine_int = 'd0; + reg [(DELAY_DATA_WIDTH-1):0] ddata_out_int = 'd0; + + // internal signals + + wire [15:0] angle_s; + wire [33:0] s1_data_s; + wire [(DELAY_DATA_WIDTH-1):0] s1_ddata_s; + wire [15:0] s1_angle_s; + wire [33:0] s4_data2_s; + wire [(DELAY_DATA_WIDTH-1):0] s4_ddata_s; + wire [16:0] s4_data1_s; + wire [33:0] s7_data2_s; + wire [33:0] s7_data1_s; + wire [(DELAY_DATA_WIDTH-1):0] s7_ddata_s; + + // make angle 2's complement + + assign angle_s = {~angle[15], angle[14:0]}; + + // level 1 - intermediate + + ad_mul #( + .DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+16) + ) i_mul_s1 ( + .clk (clk), + .data_a ({angle_s[15], angle_s}), + .data_b ({angle_s[15], angle_s}), + .data_p (s1_data_s), + .ddata_in ({ddata_in, angle_s}), + .ddata_out ({s1_ddata_s, s1_angle_s})); + + // 2's complement versions + + always @(posedge clk) begin + s1_data_p <= s1_data_s; + s1_data_n <= ~s1_data_s + 1'b1; + s1_angle <= s1_angle_s; + s1_ddata <= s1_ddata_s; + end + + // select partial products + + always @(posedge clk) begin + s2_data_0 <= (s1_angle[15] == 1'b0) ? s1_data_n[31:13] : s1_data_p[31:13]; + s2_data_1 <= {s1_angle[15], s1_angle[15:0], 2'b00}; + s2_ddata <= s1_ddata; + end + + // unit-sine + + always @(posedge clk) begin + s3_data <= s2_data_0 + s2_data_1; + s3_ddata <= s2_ddata; + end + + // level 2 - final + + ad_mul #( + .DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+17) + ) i_mul_s2 ( + .clk (clk), + .data_a (s3_data[16:0]), + .data_b (s3_data[16:0]), + .data_p (s4_data2_s), + .ddata_in ({s3_ddata, s3_data[16:0]}), + .ddata_out ({s4_ddata_s, s4_data1_s})); + + // 2's complement versions + + always @(posedge clk) begin + s4_data2_p <= s4_data2_s; + s4_data2_n <= ~s4_data2_s + 1'b1; + s4_data1_p <= s4_data1_s; + s4_data1_n <= ~s4_data1_s + 1'b1; + s4_ddata <= s4_ddata_s; + end + + // select partial products + + always @(posedge clk) begin + s5_data2_0 <= (s4_data1_p[16] == 1'b1) ? s4_data2_n[31:15] : s4_data2_p[31:15]; + s5_data2_1 <= s4_data1_n; + s5_data1 <= s4_data1_p; + s5_ddata <= s4_ddata; + end + + // corrected-sine + + always @(posedge clk) begin + s6_data2 <= s5_data2_0 + s5_data2_1; + s6_data1 <= s5_data1; + s6_ddata <= s5_ddata; + end + + // full-scale + + ad_mul #( + .DELAY_DATA_WIDTH(1) + ) i_mul_s3_2 ( + .clk (clk), + .data_a (s6_data2), + .data_b (17'h1d08), + .data_p (s7_data2_s), + .ddata_in (1'b0), + .ddata_out ()); + + ad_mul #( + .DELAY_DATA_WIDTH(DELAY_DATA_WIDTH) + ) i_mul_s3_1 ( + .clk (clk), + .data_a (s6_data1), + .data_b (17'h7fff), + .data_p (s7_data1_s), + .ddata_in (s6_ddata), + .ddata_out (s7_ddata_s)); + + // corrected sum + + always @(posedge clk) begin + s7_data <= s7_data2_s + s7_data1_s; + s7_ddata <= s7_ddata_s; + end + + // output registers + + assign sine = sine_int; + assign ddata_out = ddata_out_int; + + always @(posedge clk) begin + sine_int <= s7_data[30:15]; + ddata_out_int <= s7_ddata; + end + +endmodule diff --git a/adi_library/common/ad_dds_sine_cordic.v b/adi_library/common/ad_dds_sine_cordic.v new file mode 100644 index 00000000..33f1e10f --- /dev/null +++ b/adi_library/common/ad_dds_sine_cordic.v @@ -0,0 +1,428 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_dds_sine_cordic #( + + // Range = 8-24 + parameter PHASE_DW = 16, + // Range = 8-24 + parameter CORDIC_DW = 16, + // Range = N/A + parameter DELAY_DW = 1 +) ( + + // interface + + input clk, + input [ PHASE_DW-1:0] angle, + output reg [CORDIC_DW-1:0] sine, + output reg [CORDIC_DW-1:0] cosine, + input [ DELAY_DW-1:0] ddata_in, + output reg [ DELAY_DW-1:0] ddata_out +); + + // Local Parameters + localparam LUT_FSCALE = 1 << (PHASE_DW); + + // 1.64676025812 =~ system gain + localparam X_FSCALE = 1 << (CORDIC_DW); + localparam APROX_DW_GAIN_ERR = (CORDIC_DW < 21) ? 4 : + (CORDIC_DW <= 24) ? 7 : 0; + // ((2^N)/2)/1.647... + localparam [CORDIC_DW-1:0] X_VALUE = ((X_FSCALE/2)/(1.64676))-APROX_DW_GAIN_ERR; + + // Registers Declarations + + reg [CORDIC_DW-1:0] x0 = 'd0; + reg [CORDIC_DW-1:0] y0 = 'd0; + reg [ PHASE_DW-1:0] z0 = 'd0; + + // Wires Declarations + + wire [CORDIC_DW-1:0] x_s [0:CORDIC_DW-1]; + wire [CORDIC_DW-1:0] y_s [0:CORDIC_DW-1]; + wire [ PHASE_DW-1:0] z_s [0:CORDIC_DW-1]; + wire [ DELAY_DW-1:0] data_in_d [0:CORDIC_DW-1]; + wire [ PHASE_DW-1:0] atan_table[0:CORDIC_DW-2]; + wire [ 1:0] quadrant; + + // arc tangent LUT + + generate + if (PHASE_DW == 24) begin + assign atan_table[ 0] = 24'd2097152; // 45.0000000000000 + assign atan_table[ 1] = 24'd1238021; // 26.5650511770780 + assign atan_table[ 2] = 24'd654136; // 14.0362434679265 + assign atan_table[ 3] = 24'd332050; // 7.12501634890180 + assign atan_table[ 4] = 24'd166669; // 3.57633437499735 + assign atan_table[ 5] = 24'd83416; // 1.78991060824607 + assign atan_table[ 6] = 24'd41718; // 0.89517371021107 + assign atan_table[ 7] = 24'd20860; // 0.44761417086055 + assign atan_table[ 8] = 24'd10430; // 0.22381050036853 + assign atan_table[ 9] = 24'd5215; // 0.11190567706620 + assign atan_table[10] = 24'd2608; // 0.05595289189380 + assign atan_table[11] = 24'd1304; // 0.02797645261700 + assign atan_table[12] = 24'd652; // 0.01398822714226 + assign atan_table[13] = 24'd326; // 0.00699411367535 + assign atan_table[14] = 24'd163; // 0.00349705685070 + assign atan_table[15] = 24'd81; // 0.00174852842698 + assign atan_table[16] = 24'd41; // 0.00087426421369 + assign atan_table[17] = 24'd20; // 0.00043713210687 + assign atan_table[18] = 24'd10; // 0.00021856605343 + assign atan_table[19] = 24'd5; // 0.00010928302672 + assign atan_table[20] = 24'd3; // 0.00005464151336 + assign atan_table[21] = 24'd1; // 0.00002732075668 + assign atan_table[22] = 24'd1; // 0.00001366037834 + end else if (PHASE_DW == 23) begin + assign atan_table[ 0] = 23'd1048576; // 45.0000000000000 + assign atan_table[ 1] = 23'd619011; // 26.5650511770780 + assign atan_table[ 2] = 23'd327068; // 14.0362434679265 + assign atan_table[ 3] = 23'd166025; // 7.12501634890180 + assign atan_table[ 4] = 23'd83335; // 3.57633437499735 + assign atan_table[ 5] = 23'd41708; // 1.78991060824607 + assign atan_table[ 6] = 23'd20859; // 0.89517371021107 + assign atan_table[ 7] = 23'd10430; // 0.44761417086055 + assign atan_table[ 8] = 23'd5215; // 0.22381050036853 + assign atan_table[ 9] = 23'd2608; // 0.11190567706620 + assign atan_table[10] = 23'd1304; // 0.05595289189380 + assign atan_table[11] = 23'd652; // 0.02797645261700 + assign atan_table[12] = 23'd326; // 0.01398822714226 + assign atan_table[13] = 23'd163; // 0.00699411367535 + assign atan_table[14] = 23'd81; // 0.00349705685070 + assign atan_table[15] = 23'd41; // 0.00174852842698 + assign atan_table[16] = 23'd20; // 0.00087426421369 + assign atan_table[17] = 23'd10; // 0.00043713210687 + assign atan_table[18] = 23'd5; // 0.00021856605343 + assign atan_table[19] = 23'd3; // 0.00010928302672 + assign atan_table[20] = 23'd1; // 0.00005464151336 + assign atan_table[21] = 23'd1; // 0.00002732075668 + end else if (PHASE_DW == 22) begin + assign atan_table[ 0] = 22'd524288; // ... + assign atan_table[ 1] = 22'd309505; + assign atan_table[ 2] = 22'd163534; + assign atan_table[ 3] = 22'd83012; + assign atan_table[ 4] = 22'd41667; + assign atan_table[ 5] = 22'd20854; + assign atan_table[ 6] = 22'd10430; + assign atan_table[ 7] = 22'd5215; + assign atan_table[ 8] = 22'd2608; + assign atan_table[ 9] = 22'd1304; + assign atan_table[10] = 22'd652; + assign atan_table[11] = 22'd326; + assign atan_table[12] = 22'd163; + assign atan_table[13] = 22'd81; + assign atan_table[14] = 22'd41; + assign atan_table[15] = 22'd20; + assign atan_table[16] = 22'd10; + assign atan_table[17] = 22'd5; + assign atan_table[18] = 22'd3; + assign atan_table[19] = 22'd1; + assign atan_table[20] = 22'd1; + end else if (PHASE_DW == 21) begin + assign atan_table[ 0] = 21'd262144; + assign atan_table[ 1] = 21'd154753; + assign atan_table[ 2] = 21'd81767; + assign atan_table[ 3] = 21'd41506; + assign atan_table[ 4] = 21'd20834; + assign atan_table[ 5] = 21'd10427; + assign atan_table[ 6] = 21'd5215; + assign atan_table[ 7] = 21'd2608; + assign atan_table[ 8] = 21'd1304; + assign atan_table[ 9] = 21'd652; + assign atan_table[10] = 21'd326; + assign atan_table[11] = 21'd163; + assign atan_table[12] = 21'd81; + assign atan_table[13] = 21'd41; + assign atan_table[14] = 21'd20; + assign atan_table[15] = 21'd10; + assign atan_table[16] = 21'd5; + assign atan_table[17] = 21'd3; + assign atan_table[18] = 21'd1; + assign atan_table[19] = 21'd1; + end else if (PHASE_DW == 20) begin + assign atan_table[ 0] = 20'd131072; + assign atan_table[ 1] = 20'd77376; + assign atan_table[ 2] = 20'd40884; + assign atan_table[ 3] = 20'd20753; + assign atan_table[ 4] = 20'd10417; + assign atan_table[ 5] = 20'd5213; + assign atan_table[ 6] = 20'd2607; + assign atan_table[ 7] = 20'd1304; + assign atan_table[ 8] = 20'd652; + assign atan_table[ 9] = 20'd326; + assign atan_table[10] = 20'd163; + assign atan_table[11] = 20'd81; + assign atan_table[12] = 20'd41; + assign atan_table[13] = 20'd20; + assign atan_table[14] = 20'd10; + assign atan_table[15] = 20'd5; + assign atan_table[16] = 20'd3; + assign atan_table[17] = 20'd1; + assign atan_table[18] = 20'd1; + end else if (PHASE_DW == 19) begin + assign atan_table[ 0] = 19'd65536; + assign atan_table[ 1] = 19'd38688; + assign atan_table[ 2] = 19'd20442; + assign atan_table[ 3] = 19'd10377; + assign atan_table[ 4] = 19'd5208; + assign atan_table[ 5] = 19'd2607; + assign atan_table[ 6] = 19'd1304; + assign atan_table[ 7] = 19'd652; + assign atan_table[ 8] = 19'd326; + assign atan_table[ 9] = 19'd163; + assign atan_table[10] = 19'd81; + assign atan_table[11] = 19'd41; + assign atan_table[12] = 19'd20; + assign atan_table[13] = 19'd10; + assign atan_table[14] = 19'd5; + assign atan_table[15] = 19'd3; + assign atan_table[16] = 19'd1; + assign atan_table[17] = 19'd1; + end else if (PHASE_DW == 18) begin + assign atan_table[ 0] = 18'd32768; + assign atan_table[ 1] = 18'd19344; + assign atan_table[ 2] = 18'd10221; + assign atan_table[ 3] = 18'd5188; + assign atan_table[ 4] = 18'd2604; + assign atan_table[ 5] = 18'd1303; + assign atan_table[ 6] = 18'd652; + assign atan_table[ 7] = 18'd326; + assign atan_table[ 8] = 18'd163; + assign atan_table[ 9] = 18'd81; + assign atan_table[10] = 18'd41; + assign atan_table[11] = 18'd20; + assign atan_table[12] = 18'd10; + assign atan_table[13] = 18'd5; + assign atan_table[14] = 18'd3; + assign atan_table[15] = 18'd1; + assign atan_table[16] = 18'd1; + end else if (PHASE_DW == 17) begin + assign atan_table[ 0] = 17'd16384; + assign atan_table[ 1] = 17'd9672; + assign atan_table[ 2] = 17'd5110; + assign atan_table[ 3] = 17'd2594; + assign atan_table[ 4] = 17'd1302; + assign atan_table[ 5] = 17'd652; + assign atan_table[ 6] = 17'd326; + assign atan_table[ 7] = 17'd163; + assign atan_table[ 8] = 17'd81; + assign atan_table[ 9] = 17'd41; + assign atan_table[10] = 17'd20; + assign atan_table[11] = 17'd10; + assign atan_table[12] = 17'd5; + assign atan_table[13] = 17'd3; + assign atan_table[14] = 17'd1; + assign atan_table[15] = 17'd1; + end else if (PHASE_DW == 16) begin + assign atan_table[ 0] = 16'd8192; + assign atan_table[ 1] = 16'd4836; + assign atan_table[ 2] = 16'd2555; + assign atan_table[ 3] = 16'd1297; + assign atan_table[ 4] = 16'd651; + assign atan_table[ 5] = 16'd326; + assign atan_table[ 6] = 16'd163; + assign atan_table[ 7] = 16'd81; + assign atan_table[ 8] = 16'd41; + assign atan_table[ 9] = 16'd20; + assign atan_table[10] = 16'd10; + assign atan_table[11] = 16'd5; + assign atan_table[12] = 16'd3; + assign atan_table[13] = 16'd1; + assign atan_table[14] = 16'd1; + end else if (PHASE_DW == 15) begin + assign atan_table[ 0] = 15'd4096; + assign atan_table[ 1] = 15'd2418; + assign atan_table[ 2] = 15'd1278; + assign atan_table[ 3] = 15'd649; + assign atan_table[ 4] = 15'd326; + assign atan_table[ 5] = 15'd163; + assign atan_table[ 6] = 15'd81; + assign atan_table[ 7] = 15'd41; + assign atan_table[ 8] = 15'd20; + assign atan_table[ 9] = 15'd10; + assign atan_table[10] = 15'd5; + assign atan_table[11] = 15'd3; + assign atan_table[12] = 15'd1; + assign atan_table[13] = 15'd1; + end else if (PHASE_DW == 14) begin + assign atan_table[ 0] = 14'd2048; + assign atan_table[ 1] = 14'd1209; + assign atan_table[ 2] = 14'd639; + assign atan_table[ 3] = 14'd324; + assign atan_table[ 4] = 14'd163; + assign atan_table[ 5] = 14'd81; + assign atan_table[ 6] = 14'd41; + assign atan_table[ 7] = 14'd20; + assign atan_table[ 8] = 14'd10; + assign atan_table[ 9] = 14'd5; + assign atan_table[10] = 14'd3; + assign atan_table[11] = 14'd1; + assign atan_table[12] = 14'd1; + end else if (PHASE_DW == 13) begin + assign atan_table[ 0] = 13'd1024; + assign atan_table[ 1] = 13'd605; + assign atan_table[ 2] = 13'd319; + assign atan_table[ 3] = 13'd162; + assign atan_table[ 4] = 13'd81; + assign atan_table[ 5] = 13'd41; + assign atan_table[ 6] = 13'd20; + assign atan_table[ 7] = 13'd10; + assign atan_table[ 8] = 13'd5; + assign atan_table[ 9] = 13'd3; + assign atan_table[10] = 13'd1; + assign atan_table[11] = 13'd1; + end else if (PHASE_DW == 12) begin + assign atan_table[ 0] = 12'd512; + assign atan_table[ 1] = 12'd302; + assign atan_table[ 2] = 12'd160; + assign atan_table[ 3] = 12'd81; + assign atan_table[ 4] = 12'd41; + assign atan_table[ 5] = 12'd20; + assign atan_table[ 6] = 12'd10; + assign atan_table[ 7] = 12'd5; + assign atan_table[ 8] = 12'd3; + assign atan_table[ 9] = 12'd1; + assign atan_table[10] = 12'd1; + end else if (PHASE_DW == 11) begin + assign atan_table[ 0] = 11'd256; + assign atan_table[ 1] = 11'd151; + assign atan_table[ 2] = 11'd80; + assign atan_table[ 3] = 11'd41; + assign atan_table[ 4] = 11'd20; + assign atan_table[ 5] = 11'd10; + assign atan_table[ 6] = 11'd5; + assign atan_table[ 7] = 11'd3; + assign atan_table[ 8] = 11'd1; + assign atan_table[ 9] = 11'd1; + end else if (PHASE_DW == 10) begin + assign atan_table[ 0] = 10'd128; + assign atan_table[ 1] = 10'd76; + assign atan_table[ 2] = 10'd40; + assign atan_table[ 3] = 10'd20; + assign atan_table[ 4] = 10'd10; + assign atan_table[ 5] = 10'd5; + assign atan_table[ 6] = 10'd3; + assign atan_table[ 7] = 10'd1; + assign atan_table[ 8] = 10'd1; + end else if (PHASE_DW == 9) begin + assign atan_table[ 0] = 9'd64; + assign atan_table[ 1] = 9'd38; + assign atan_table[ 2] = 9'd20; + assign atan_table[ 3] = 9'd10; + assign atan_table[ 4] = 9'd5; + assign atan_table[ 5] = 9'd3; + assign atan_table[ 6] = 9'd1; + assign atan_table[ 7] = 9'd1; + end else if (PHASE_DW == 8) begin + assign atan_table[ 0] = 8'd32; + assign atan_table[ 1] = 8'd19; + assign atan_table[ 2] = 8'd10; + assign atan_table[ 3] = 8'd5; + assign atan_table[ 4] = 8'd3; + assign atan_table[ 5] = 8'd1; + assign atan_table[ 6] = 8'd1; + end + endgenerate + + // pre-rotating + + // first two bits represent the quadrant in the unit circle + assign quadrant = angle[PHASE_DW-1:PHASE_DW-2]; + + always @(posedge clk) begin + case (quadrant) + 2'b00, + 2'b11: begin + x0 <= X_VALUE; + y0 <= 0; + z0 <= angle; + end + + 2'b01: begin + x0 <= 0; + y0 <= X_VALUE; + z0 <= {2'b00, angle[PHASE_DW-3:0]}; + end + + 2'b10: begin + x0 <= 0; + y0 <= -X_VALUE; + z0 <= {2'b11, angle[PHASE_DW-3:0]}; + end + endcase + end + + assign x_s[0] = x0; + assign y_s[0] = y0; + assign z_s[0] = z0; + assign data_in_d[0] = ddata_in; + + // cordic pipeline + + genvar i; + + generate + for (i=0; i < PHASE_DW-1; i=i+1) begin: rotation + ad_dds_cordic_pipe #( + .P_DW (PHASE_DW), + .D_DW (CORDIC_DW), + .DELAY_DW (DELAY_DW), + .SHIFT(i) + ) pipe ( + .clk (clk), + .dataa_x (x_s[i]), + .dataa_y (y_s[i]), + .dataa_z (z_s[i]), + .datab_z (atan_table[i]), + .dir (z_s[i][PHASE_DW-1]), + .result_x (x_s[i+1]), + .result_y (y_s[i+1]), + .result_z (z_s[i+1]), + .data_delay_in (data_in_d[i]), + .data_delay_out (data_in_d[i+1])); + end + endgenerate + + // x and y are cos(angle) and sin(angle) + + always @(posedge clk) begin + ddata_out <= data_in_d[PHASE_DW-1]; + sine <= y_s[PHASE_DW-1]; + cosine <= x_s[PHASE_DW-1]; + end + +endmodule diff --git a/adi_library/common/ad_edge_detect.v b/adi_library/common/ad_edge_detect.v new file mode 100644 index 00000000..f1cac88b --- /dev/null +++ b/adi_library/common/ad_edge_detect.v @@ -0,0 +1,82 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +// A simple edge detector circuit + +`timescale 1ns/100ps + +module ad_edge_detect #( + + parameter EDGE = 0 +) ( + input clk, + input rst, + + input signal_in, + output reg signal_out +); + + localparam POS_EDGE = 0; + localparam NEG_EDGE = 1; + localparam ANY_EDGE = 2; + + reg ff_m1 = 0; + reg ff_m2 = 0; + + always @(posedge clk) begin + if (rst == 1) begin + ff_m1 <= 0; + ff_m2 <= 0; + end else begin + ff_m1 <= signal_in; + ff_m2 <= ff_m1; + end + end + + always @(posedge clk) begin + if (rst == 1) begin + signal_out <= 1'b0; + end else begin + if (EDGE == POS_EDGE) begin + signal_out <= ff_m1 & ~ff_m2; + end else if (EDGE == NEG_EDGE) begin + signal_out <= ~ff_m1 & ff_m2; + end else begin + signal_out <= ff_m1 ^ ff_m2; + end + end + end + +endmodule diff --git a/adi_library/common/ad_g2b.v b/adi_library/common/ad_g2b.v new file mode 100644 index 00000000..373b8728 --- /dev/null +++ b/adi_library/common/ad_g2b.v @@ -0,0 +1,59 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_g2b #( + + parameter DATA_WIDTH = 8 +) ( + input [DATA_WIDTH-1:0] din, + output [DATA_WIDTH-1:0] dout +); + + function [DATA_WIDTH-1:0] g2b; + input [DATA_WIDTH-1:0] g; + integer i; + begin + g2b[DATA_WIDTH-1] = g[DATA_WIDTH-1]; + for (i = DATA_WIDTH-1; i > 0; i = i -1) begin + g2b[i-1] = g2b[i] ^ g[i-1]; + end + end + endfunction + + assign dout = g2b(din); + +endmodule diff --git a/adi_library/common/ad_iobuf.v b/adi_library/common/ad_iobuf.v new file mode 100644 index 00000000..c097a3fe --- /dev/null +++ b/adi_library/common/ad_iobuf.v @@ -0,0 +1,56 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_iobuf #( + + parameter DATA_WIDTH = 1 +) ( + input [(DATA_WIDTH-1):0] dio_t, + input [(DATA_WIDTH-1):0] dio_i, + output [(DATA_WIDTH-1):0] dio_o, + inout [(DATA_WIDTH-1):0] dio_p +); + + genvar n; + generate + for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_iobuf + assign dio_o[n] = dio_p[n]; + assign dio_p[n] = (dio_t[n] == 1'b1) ? 1'bz : dio_i[n]; + end + endgenerate + +endmodule diff --git a/adi_library/common/ad_iqcor.v b/adi_library/common/ad_iqcor.v new file mode 100644 index 00000000..02d2ca45 --- /dev/null +++ b/adi_library/common/ad_iqcor.v @@ -0,0 +1,198 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// iq correction = a*(i+x) + b*(q+y); offsets are added in dcfilter. +// if SCALE_ONLY is set to 1, b*(q+y) is set to 0, and the module is used for +// scale correction of channel I + +// Assumption CR smaller or equal to 16 + +`timescale 1ns/100ps + +module ad_iqcor #( + + // select i/q if disabled + + parameter Q_OR_I_N = 0, + parameter SCALE_ONLY = 0, + parameter DISABLE = 0, + parameter CR = 16, // Converter Resolution + parameter DPW = 1 // Data Path Width +) ( + + // data interface + + input clk, + input valid, + input [DPW*CR-1:0] data_in, + input [DPW*CR-1:0] data_iq, + output valid_out, + output [DPW*CR-1:0] data_out, + + // control interface + + input iqcor_enable, + input [15:0] iqcor_coeff_1, + input [15:0] iqcor_coeff_2 +); + + // internal registers + + reg [15:0] iqcor_coeff_1_r = 'd0; + reg [15:0] iqcor_coeff_2_r = 'd0; + + // internal signals + wire [DPW-1:0] valid_int_loc; + wire [DPW*CR-1:0] data_int_loc; + + // data-path disable + + generate + if (DISABLE == 1) begin + assign valid_out = valid; + assign data_out = data_in; + end else begin + assign valid_out = valid_int_loc; + assign data_out = data_int_loc; + end + endgenerate + + // coefficients are flopped to remove warnings from vivado + + always @(posedge clk) begin + iqcor_coeff_1_r <= iqcor_coeff_1; + iqcor_coeff_2_r <= iqcor_coeff_2; + end + + genvar i; + generate + for (i=0; i +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_mem #( + + parameter DATA_WIDTH = 16, + parameter ADDRESS_WIDTH = 5 +) ( + input clka, + input wea, + input [(ADDRESS_WIDTH-1):0] addra, + input [(DATA_WIDTH-1):0] dina, + + input clkb, + input reb, + input [(ADDRESS_WIDTH-1):0] addrb, + output reg [(DATA_WIDTH-1):0] doutb +); + + (* ram_style = "block" *) + reg [(DATA_WIDTH-1):0] m_ram[0:((2**ADDRESS_WIDTH)-1)]; + + always @(posedge clka) begin + if (wea == 1'b1) begin + m_ram[addra] <= dina; + end + end + + always @(posedge clkb) begin + if (reb == 1'b1) begin + doutb <= m_ram[addrb]; + end + end + +endmodule diff --git a/adi_library/common/ad_mem_asym.v b/adi_library/common/ad_mem_asym.v new file mode 100644 index 00000000..f18091ff --- /dev/null +++ b/adi_library/common/ad_mem_asym.v @@ -0,0 +1,147 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +// A simple asymetric memory. The write and read memory space must have the same size. +// 2^A_ADDRESS_WIDTH * A_DATA_WIDTH == 2^B_ADDRESS_WIDTH * B_DATA_WIDTH + +`timescale 1ns/100ps + +module ad_mem_asym #( + + parameter A_ADDRESS_WIDTH = 8, + parameter A_DATA_WIDTH = 256, + parameter B_ADDRESS_WIDTH = 10, + parameter B_DATA_WIDTH = 64, + parameter CASCADE_HEIGHT = -1 +) ( + input clka, + input wea, + input [A_ADDRESS_WIDTH-1:0] addra, + input [A_DATA_WIDTH-1:0] dina, + + input clkb, + input reb, + input [B_ADDRESS_WIDTH-1:0] addrb, + output reg [B_DATA_WIDTH-1:0] doutb +); + + `define max(a,b) {(a) > (b) ? (a) : (b)} + `define min(a,b) {(a) < (b) ? (a) : (b)} + + function integer clog2; + input integer value; + begin + if (value < 2) + clog2 = value; + else begin + value = value - 1; + for (clog2 = 0; value > 0; clog2 = clog2 + 1) + value = value >> 1; + end + end + endfunction + + localparam MEM_ADDRESS_WIDTH = `max(A_ADDRESS_WIDTH, B_ADDRESS_WIDTH); + localparam MIN_WIDTH = `min(A_DATA_WIDTH, B_DATA_WIDTH); + localparam MAX_WIDTH = `max(A_DATA_WIDTH, B_DATA_WIDTH); + localparam MEM_DATA_WIDTH = MIN_WIDTH; + localparam MEM_SIZE = 2 ** MEM_ADDRESS_WIDTH; + localparam MEM_RATIO = MAX_WIDTH / MIN_WIDTH; + localparam MEM_RATIO_LOG2 = clog2(MEM_RATIO); + + // internal registers + + (* ram_style = "block", cascade_height = CASCADE_HEIGHT *) + reg [MEM_DATA_WIDTH-1:0] m_ram[0:MEM_SIZE-1]; + + //--------------------------------------------------------------------------- + // write interface + //--------------------------------------------------------------------------- + + // write data width is narrower than read data width + generate if (A_DATA_WIDTH <= B_DATA_WIDTH) begin + always @(posedge clka) begin + if (wea == 1'b1) begin + m_ram[addra] <= dina; + end + end + end + endgenerate + + // write data width is wider than read data width + generate if (A_DATA_WIDTH > B_DATA_WIDTH) begin + always @(posedge clka) begin : memwrite + integer i; + reg [MEM_RATIO_LOG2-1:0] lsb; + for (i = 0; i < MEM_RATIO; i = i + 1) begin : awrite + lsb = i; + if (wea) begin + m_ram[{addra, lsb}] <= dina[i * MIN_WIDTH +: MIN_WIDTH]; + end + end + end + end + endgenerate + + //--------------------------------------------------------------------------- + // read interface + //--------------------------------------------------------------------------- + + // read data width is narrower than write data width + generate if (A_DATA_WIDTH >= B_DATA_WIDTH) begin + always @(posedge clkb) begin + if (reb == 1'b1) begin + doutb <= m_ram[addrb]; + end + end + end + endgenerate + + // read data width is wider than write data width + generate if (A_DATA_WIDTH < B_DATA_WIDTH) begin + always @(posedge clkb) begin : memread + integer i; + reg [MEM_RATIO_LOG2-1:0] lsb; + for (i = 0; i < MEM_RATIO; i = i + 1) begin : aread + lsb = i; + if (reb == 1'b1) begin + doutb[i*MIN_WIDTH +: MIN_WIDTH] <= m_ram[{addrb, lsb}]; + end + end + end + end + endgenerate + +endmodule diff --git a/adi_library/common/ad_mux.v b/adi_library/common/ad_mux.v new file mode 100644 index 00000000..ffcdd7ad --- /dev/null +++ b/adi_library/common/ad_mux.v @@ -0,0 +1,117 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +// Constraints : CH_CNT must be power of 2 +// Build a large mux from smaller ones defined by the MUX_SZ parameter +// Use EN_REG to add a register at the output of the small muxes to help +// timing closure. + +module ad_mux #( + parameter CH_W = 16, // Width of input channel + parameter CH_CNT = 64, // Number of input channels + parameter REQ_MUX_SZ = 8, // Size of mux which acts as a building block + parameter EN_REG = 1, // Enable register at output of each mux + parameter DW = CH_W*CH_CNT +) ( + input clk, + input [DW-1:0] data_in, + input [$clog2(CH_CNT)-1:0] ch_sel, + output [CH_W-1:0] data_out +); + + `define MIN(A,B) (A> i*CLOG2_MUX_SZ; + + if (EN_REG) begin + reg [CLOG2_CH_CNT-1:0] ch_sel_d; + always @(posedge clk) begin + ch_sel_d <= ch_sel_cur; + end + if (i +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_mux_core #( + parameter CH_W = 16, + parameter CH_CNT = 8, + parameter EN_REG = 0 +) ( + input clk, + input [CH_W*CH_CNT-1:0] data_in, + input [$clog2(CH_CNT)-1:0] ch_sel, + output [CH_W-1:0] data_out +); + + wire [CH_W-1:0] data_out_loc; + + assign data_out_loc = data_in >> CH_W*ch_sel; + + generate if (EN_REG) begin + reg [CH_W-1:0] data_out_reg; + always @(posedge clk) begin + data_out_reg <= data_out_loc; + end + assign data_out = data_out_reg; + end else begin + assign data_out = data_out_loc; + end + endgenerate + +endmodule diff --git a/adi_library/common/ad_pack.v b/adi_library/common/ad_pack.v new file mode 100644 index 00000000..8a7ddbb1 --- /dev/null +++ b/adi_library/common/ad_pack.v @@ -0,0 +1,180 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +// Packer: +// - pack I_W number of data units into O_W number of data units +// - data unit defined in bits by UNIT_W e.g 8 is a byte +// +// Constraints: +// - O_W > I_W +// - no backpressure +// +// Data format: +// idata [U(I_W-1) .... U(0)] +// odata [U(O_W-1) .... U(0)] +// +// e.g +// I_W = 4 +// O_W = 6 +// UNIT_W = 8 +// +// idata : [B3,B2,B1,B0],[B7,B6,B5,B4],[B11,B10,B9,B8] +// odata: [B5,B4,B3,B2,B1,B0],[B11,B10,B9,B8,B7,B6] +// + +module ad_pack #( + parameter I_W = 4, + parameter O_W = 6, + parameter UNIT_W = 8, + parameter I_REG = 0, + parameter O_REG = 1 +) ( + input clk, + input reset, + input [I_W*UNIT_W-1:0] idata, + input ivalid, + + output reg [O_W*UNIT_W-1:0] odata = 'h0, + output reg ovalid = 'b0 +); + + // The Width of the shift reg is an integer multiple of input data width + localparam SH_W = ((O_W/I_W) + ((O_W%I_W) > 0) + ((I_W % (O_W - ((O_W/I_W)*I_W) + ((O_W%I_W) == 0))) > 0))*I_W; + // The Step of the algorithm is the greatest common divisor of O_W and I_W + localparam STEP = gcd(O_W, I_W); + + reg [O_W*UNIT_W-1:0] idata_packed; + reg [I_W*UNIT_W-1:0] idata_d = 'h0; + reg ivalid_d = 'h0; + reg [SH_W*UNIT_W-1:0] idata_dd = 'h0; + reg [SH_W-1:0] in_use = 'b0; + reg [SH_W-1:0] out_mask; + + wire [SH_W*UNIT_W-1:0] idata_dd_nx; + wire [SH_W-1:0] in_use_nx; + wire pack_wr; + + function [31:0] gcd; + input [31:0] a; + input [31:0] b; + begin + while (a != b) begin + if (a > b) begin + a = a-b; + end else begin + b = b-a; + end + end + gcd = a; + end + endfunction + + generate + if (I_REG) begin : i_reg + + always @(posedge clk) begin + ivalid_d <= ivalid; + idata_d <= idata; + end + + end else begin + + always @(*) begin + ivalid_d = ivalid; + idata_d = idata; + end + + end + endgenerate + + assign idata_dd_nx = {idata_d,idata_dd[SH_W*UNIT_W-1:I_W*UNIT_W]}; + assign in_use_nx = {{I_W{ivalid_d}},in_use[SH_W-1:I_W]}; + + always @(posedge clk) begin + if (reset) begin + in_use <= 'h0; + end else if (ivalid_d) begin + in_use <= in_use_nx &(~out_mask); + end + end + + always @(posedge clk) begin + if (ivalid_d) begin + idata_dd <= idata_dd_nx; + end + end + + integer i; + always @(*) begin + out_mask = 'b0; + idata_packed = 'b0; + for (i = SH_W-O_W; i >= 0; i=i-STEP) begin + if (in_use_nx[i]) begin + out_mask = {O_W{1'b1}} << i; + idata_packed = idata_dd_nx >> i*UNIT_W; + end + end + end + + assign pack_wr = ivalid_d & |in_use_nx[SH_W-O_W:0]; + + generate + if (O_REG) begin : o_reg + + always @(posedge clk) begin + if (reset) begin + ovalid <= 1'b0; + end else begin + ovalid <= pack_wr; + end + end + + always @(posedge clk) begin + odata <= idata_packed; + end + + end else begin + + always @(*) begin + ovalid = pack_wr; + odata = idata_packed; + end + + end + endgenerate + +endmodule diff --git a/adi_library/common/ad_perfect_shuffle.v b/adi_library/common/ad_perfect_shuffle.v new file mode 100644 index 00000000..37987e69 --- /dev/null +++ b/adi_library/common/ad_perfect_shuffle.v @@ -0,0 +1,68 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// Each core or library found in this collection may have its own licensing terms. +// The user should keep this in in mind while exploring these cores. +// +// Redistribution and use in source and binary forms, +// with or without modification of this file, are permitted under the terms of either +// (at the option of the user): +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory, or at: +// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html +// +// OR +// +// 2. An ADI specific BSD license as noted in the top level directory, or on-line at: +// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_perfect_shuffle #( + parameter NUM_GROUPS = 2, + parameter WORDS_PER_GROUP = 2, + parameter WORD_WIDTH = 8 +) ( + input [NUM_GROUPS*WORDS_PER_GROUP*WORD_WIDTH-1:0] data_in, + output [NUM_GROUPS*WORDS_PER_GROUP*WORD_WIDTH-1:0] data_out +); + /* + * Performs the perfect shuffle operation. + * + * The perfect shuffle splits the input vector into NUM_GROUPS groups and then + * each group in WORDS_PER_GROUP. The output vector consists of WORDS_PER_GROUP + * groups and each group has NUM_GROUPS words. The data is remapped, so that + * the i-th word of the j-th word in the output vector is the j-th word of the + * i-th group of the input vector. + + * The inverse operation of the perfect shuffle is the perfect shuffle with + * both parameters swapped. + * I.e. [perfect_suffle B A [perfect_shuffle A B data]] == data + * + * Examples: + * NUM_GROUPS = 2, WORDS_PER_GROUP = 4 + * [A B C D a b c d] => [A a B b C c D d] + * NUM_GROUPS = 4, WORDS_PER_GROUP = 2 + * [A a B b C c D d] => [A B C D a b c d] + * NUM_GROUPS = 3, WORDS_PER_GROUP = 2 + * [A B a b 1 2] => [A a 1 B b 2] + */ + generate + genvar i; + genvar j; + for (i = 0; i < NUM_GROUPS; i = i + 1) begin: shuffle_outer + for (j = 0; j < WORDS_PER_GROUP; j = j + 1) begin: shuffle_inner + localparam src_lsb = (j + i * WORDS_PER_GROUP) * WORD_WIDTH; + localparam dst_lsb = (i + j * NUM_GROUPS) * WORD_WIDTH; + + assign data_out[dst_lsb+:WORD_WIDTH] = data_in[src_lsb+:WORD_WIDTH]; + end + end + endgenerate + +endmodule diff --git a/adi_library/common/ad_pngen.v b/adi_library/common/ad_pngen.v new file mode 100644 index 00000000..f7280b3d --- /dev/null +++ b/adi_library/common/ad_pngen.v @@ -0,0 +1,114 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +// Generic parallel PN generator + +module ad_pngen #( + + // PN7 x^7 + x^6 + 1 + parameter POL_MASK = 32'b0000_0000_0000_0000_0000_0000_1100_0000, + parameter POL_W = 7, + + // Number of output bits at every clock cycle + parameter DW = 16 +) ( + input clk, + input reset, + input clk_en, + + // Output stream + output [DW-1:0] pn_data_out, // MSB has the oldest value, + // LSB has the latest value + + // Input stream to synchronize to (Optional) + input pn_init, + input [DW-1:0] pn_data_in +); + + /* We need at least enough bits to store the PN state */ + localparam PN_W = DW > POL_W ? DW : POL_W; + + reg [PN_W-1:0] pn_state = {PN_W{1'b1}}; + + wire [DW-1:0] pn; + wire [DW+POL_W-1:0] pn_full_state; + wire [PN_W-1:0] pn_reset; + wire [PN_W-1:0] pn_state_; + wire [PN_W-1:0] pn_init_data; + + // pn init data selection + generate if (PN_W > DW) begin + reg [PN_W-DW-1:0] pn_data_in_d = 'd0; + always @(posedge clk) begin + pn_data_in_d <= {pn_data_in_d, pn_data_in}; + end + assign pn_init_data = {pn_data_in_d, pn_data_in}; + end else begin + assign pn_init_data = pn_data_in; + end + endgenerate + + // PRBS logic + assign pn_state_ = pn_init ? pn_init_data : pn_state; + generate + genvar i; + for (i = 0; i < DW; i = i + 1) begin: pn_loop + assign pn[i] = ^(pn_full_state[i +: POL_W+1] & POL_MASK); + end + endgenerate + assign pn_full_state = {pn_state_[POL_W-1 : 0],pn}; + + // Reset value logic + assign pn_reset[PN_W-1 -: POL_W] = {POL_W{1'b1}}; + generate + genvar j; + for (j = 0; j < PN_W-POL_W; j = j + 1) begin: pn_reset_loop + assign pn_reset[j] = ^(pn_reset[j +: POL_W+1] & POL_MASK); + end + endgenerate + + always @(posedge clk) begin + if (reset == 1'b1) begin + pn_state <= pn_reset; + end else if (clk_en) begin + pn_state <= pn_full_state[PN_W-1 : 0]; + end + end + + assign pn_data_out = pn_state[PN_W-1 -: DW]; + +endmodule diff --git a/adi_library/common/ad_pnmon.v b/adi_library/common/ad_pnmon.v new file mode 100644 index 00000000..7a223c50 --- /dev/null +++ b/adi_library/common/ad_pnmon.v @@ -0,0 +1,118 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// PN monitors + +`timescale 1ns/100ps + +module ad_pnmon #( + + parameter DATA_WIDTH = 16, + parameter OOS_THRESHOLD = 16, + parameter ALLOW_ZERO_MASKING = 0 +) ( + + // adc interface + + input adc_clk, + input adc_valid_in, + input [(DATA_WIDTH-1):0] adc_data_in, + input [(DATA_WIDTH-1):0] adc_data_pn, + + input adc_pattern_has_zero, + + // pn out of sync and error + + output adc_pn_oos, + output adc_pn_err +); + + localparam CNT_W = $clog2(OOS_THRESHOLD); + + // internal registers + + reg adc_valid_d = 'd0; + reg adc_pn_match_d = 'd0; + reg adc_pn_match_z = 'd0; + reg adc_pn_oos_int = 'd0; + reg adc_pn_err_int = 'd0; + reg [CNT_W-1:0] adc_pn_oos_count = 'd0; + reg adc_valid_zero_d = 'b0; + + // internal signals + + wire adc_pn_match_d_s; + wire adc_pn_match_z_s; + wire adc_pn_match_s; + wire adc_pn_update_s; + wire adc_pn_err_s; + wire adc_valid_zero; + + // make sure data is not 0, sequence will fail. + + assign adc_pn_match_d_s = (adc_data_in == adc_data_pn) ? 1'b1 : 1'b0; + assign adc_pn_match_z_s = (adc_data_in == 'd0) ? 1'b1 : 1'b0; + assign adc_pn_match_s = adc_pn_match_d & ~adc_pn_match_z; + assign adc_pn_update_s = ~(adc_pn_oos_int ^ adc_pn_match_s); + + // Ignore sporadic zeros in middle of pattern if not out of sync + // but OOS_THRESHOLD consecutive zeros would assert out of sync. + assign adc_valid_zero = ALLOW_ZERO_MASKING & adc_pattern_has_zero & + ~adc_pn_oos_int & adc_pn_match_z_s; + assign adc_pn_err_s = ~(adc_pn_oos_int | adc_pn_match_s | adc_valid_zero_d); + + // pn oos and counters (16 to clear and set). + + assign adc_pn_oos = adc_pn_oos_int; + assign adc_pn_err = adc_pn_err_int; + + always @(posedge adc_clk) begin + adc_valid_d <= adc_valid_in; + adc_pn_match_d <= adc_pn_match_d_s; + adc_pn_match_z <= adc_pn_match_z_s; + adc_valid_zero_d <= adc_valid_zero; + if (adc_valid_d == 1'b1) begin + adc_pn_err_int <= adc_pn_err_s; + if ((adc_pn_update_s == 1'b1) && (adc_pn_oos_count >= OOS_THRESHOLD-1)) begin + adc_pn_oos_int <= ~adc_pn_oos_int; + end + if (adc_pn_update_s == 1'b1) begin + adc_pn_oos_count <= adc_pn_oos_count + 1'b1; + end else begin + adc_pn_oos_count <= 'd0; + end + end + end + +endmodule diff --git a/adi_library/common/ad_pps_receiver.v b/adi_library/common/ad_pps_receiver.v new file mode 100644 index 00000000..095bc31a --- /dev/null +++ b/adi_library/common/ad_pps_receiver.v @@ -0,0 +1,131 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +`timescale 1ns/1ps + +module ad_pps_receiver ( + input clk, + input rst, + input gps_pps, + + input up_clk, + input up_rstn, + output reg [31:0] up_pps_rcounter, + output reg up_pps_status, + input up_irq_mask, + output reg up_irq +); + + // ************************************************************************* + // 1PPS reception and reporting counter implementation + // Note: this module should run on the core clock + // ************************************************************************* + + reg [ 2:0] gps_pps_m = 3'b0; + reg [ 2:0] up_pps_m = 3'b0; + reg up_pps_status_m = 1'b0; + reg pps_toggle = 1'b0; + reg [31:0] free_rcounter = 32'b0; + reg [31:0] pps_rcounter = 32'b0; + reg pps_status = 1'b0; + + wire pps_posedge_s; + wire up_pps_posedge_s; + + // gps_pps is asynchronous from the clk + + always @(posedge clk) begin + if (rst == 1'b1) begin + gps_pps_m <= 3'b0; + end else begin + gps_pps_m <= {gps_pps_m[1:0], gps_pps}; + end + end + assign pps_posedge_s = ~gps_pps_m[2] & gps_pps_m[1]; + + always @(posedge clk) begin + if (rst == 1'b1) begin + free_rcounter <= 32'b0; + pps_rcounter <= 32'b0; + pps_status <= 1'b1; + end else if (pps_posedge_s == 1'b1) begin + free_rcounter <= 32'b0; + pps_rcounter <= free_rcounter; + pps_status <= 1'b0; + end else begin + free_rcounter <= free_rcounter + 32'b1; + if (free_rcounter[28] == 1'b1) begin + pps_status <= 1'b1; + end + end + end + + // up_tdd_pps_rcounter CDC + + always @(posedge clk) begin + if (rst == 1'b1) begin + pps_toggle <= 1'b0; + end else if (pps_posedge_s == 1'b1) begin + pps_toggle <= ~pps_toggle; + end + end + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_pps_m <= 3'b0; + up_pps_rcounter <= 1'b0; + up_pps_status_m <= 1'b1; + up_pps_status <= 1'b1; + end else begin + up_pps_m <= {up_pps_m[1:0], pps_toggle}; + up_pps_status_m <= pps_status; + up_pps_status <= up_pps_status_m; + if ((up_pps_m[2] ^ up_pps_m[1]) == 1'b1) begin + up_pps_rcounter <= pps_rcounter; + end + end + end + assign up_pps_posedge_s = ~up_pps_m[2] & up_pps_m[1]; + + // IRQ generation + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_irq <= 1'b0; + end else begin + up_irq <= up_pps_posedge_s & ~up_irq_mask; + end + end + +endmodule diff --git a/adi_library/common/ad_pps_receiver_constr.ttcl b/adi_library/common/ad_pps_receiver_constr.ttcl new file mode 100644 index 00000000..0923c559 --- /dev/null +++ b/adi_library/common/ad_pps_receiver_constr.ttcl @@ -0,0 +1,25 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +# SPDX short identifier: ADIBSD +############################################################################### + +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName [ttcl_add $ComponentName "_pps_constr"] :> +<: setFileExtension ".xdc" :> +<: setFileProcessingOrder late :> +<: set pps_enable [getBooleanValue "PPS_RECEIVER_ENABLE"] :> + +<: if {$pps_enable} { :> + + set_property ASYNC_REG TRUE \ + [get_cells -hier *_pps_m*] \ + [get_cells -hier *_pps_status_m*] + + set_false_path -to [get_cells -hier -filter {name =~ *_pps_m_reg[0] && IS_SEQUENTIAL}] + set_false_path -from [get_cells -hier -filter {name =~ *pps_status_reg && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *up_pps_status_m_reg && IS_SEQUENTIAL}] + set_false_path -to [get_cells -hier -filter {name =~ *up_pps_rcounter_reg* && IS_SEQUENTIAL}] + +<: } :> + diff --git a/adi_library/common/ad_rst.v b/adi_library/common/ad_rst.v new file mode 100644 index 00000000..1aa10890 --- /dev/null +++ b/adi_library/common/ad_rst.v @@ -0,0 +1,75 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_rst ( + + // clock reset + + input rst_async, + input clk, + output rstn, + output reg rst +); + + // internal registers + reg rst_async_d1 = 1'd1; + reg rst_async_d2 = 1'd1; + reg rst_sync = 1'd1; + reg rst_sync_d = 1'd1; + + // simple reset synchronizer + always @(posedge clk or posedge rst_async) begin + if (rst_async) begin + rst_async_d1 <= 1'b1; + rst_async_d2 <= 1'b1; + rst_sync <= 1'b1; + end else begin + rst_async_d1 <= 1'b0; + rst_async_d2 <= rst_async_d1; + rst_sync <= rst_async_d2; + end + end + + // two-stage synchronizer to prevent metastability on the falling edge + always @(posedge clk) begin + rst_sync_d <= rst_sync; + rst <= rst_sync_d; + end + + assign rstn = ~rst; + +endmodule diff --git a/adi_library/common/ad_ss_422to444.v b/adi_library/common/ad_ss_422to444.v new file mode 100644 index 00000000..ec2f66b6 --- /dev/null +++ b/adi_library/common/ad_ss_422to444.v @@ -0,0 +1,137 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// Input must be RGB or CrYCb in that order, output is CrY/CbY + +`timescale 1ns/100ps + +module ad_ss_422to444 #( + + parameter CR_CB_N = 0, + parameter DELAY_DATA_WIDTH = 16 +) ( + + // 422 inputs + + input clk, + input s422_de, + input [DELAY_DATA_WIDTH-1:0] s422_sync, + input [ 15:0] s422_data, + + // 444 outputs + + output reg [DELAY_DATA_WIDTH-1:0] s444_sync, + output reg [ 23:0] s444_data +); + + localparam DW = DELAY_DATA_WIDTH - 1; + + // internal registers + + reg cr_cb_sel = 'd0; + reg s422_de_d = 'd0; + reg [DW:0] s422_sync_d = 'd0; + reg s422_de_2d = 'd0; + reg [7:0] s422_Y_d; + reg [7:0] s422_CbCr_d; + reg [7:0] s422_CbCr_2d; + reg [ 8:0] s422_CbCr_avg; + + // internal wires + + wire [ 7:0] s422_Y; + wire [ 7:0] s422_CbCr; + + // Input format is + // [15:8] Cb/Cr + // [ 7:0] Y + // + // Output format is + // [23:15] Cr + // [16: 8] Y + // [ 7: 0] Cb + + assign s422_Y = s422_data[7:0]; + assign s422_CbCr = s422_data[15:8]; + + // first data on de assertion is cb (0x0), then cr (0x1). + // previous data is held when not current + + always @(posedge clk) begin + if (s422_de_d == 1'b1) begin + cr_cb_sel <= ~cr_cb_sel; + end else begin + cr_cb_sel <= CR_CB_N; + end + end + + // pipe line stages + + always @(posedge clk) begin + s422_de_d <= s422_de; + s422_sync_d <= s422_sync; + s422_de_2d <= s422_de_d; + s422_Y_d <= s422_Y; + + s422_CbCr_d <= s422_CbCr; + s422_CbCr_2d <= s422_CbCr_d; + end + + // If both the left and the right sample are valid do the average, otherwise + // use the only valid. + always @(s422_de_2d, s422_de, s422_CbCr, s422_CbCr_2d) + begin + if (s422_de == 1'b1 && s422_de_2d) + s422_CbCr_avg <= s422_CbCr + s422_CbCr_2d; + else if (s422_de == 1'b1) + s422_CbCr_avg <= {s422_CbCr, 1'b0}; + else + s422_CbCr_avg <= {s422_CbCr_2d, 1'b0}; + end + + // 444 outputs + + always @(posedge clk) begin + s444_sync <= s422_sync_d; + s444_data[15:8] <= s422_Y_d; + if (cr_cb_sel) begin + s444_data[23:16] <= s422_CbCr_d; + s444_data[ 7: 0] <= s422_CbCr_avg[8:1]; + end else begin + s444_data[23:16] <= s422_CbCr_avg[8:1]; + s444_data[ 7: 0] <= s422_CbCr_d; + end + end + +endmodule diff --git a/adi_library/common/ad_ss_444to422.v b/adi_library/common/ad_ss_444to422.v new file mode 100644 index 00000000..7aa6b3c7 --- /dev/null +++ b/adi_library/common/ad_ss_444to422.v @@ -0,0 +1,133 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// Input must be RGB or CrYCb in that order, output is CrY/CbY + +`timescale 1ns/100ps + +module ad_ss_444to422 #( + + parameter CR_CB_N = 0, + parameter DELAY_DATA_WIDTH = 16 +) ( + + // 444 inputs + + input clk, + input s444_de, + input [DELAY_DATA_WIDTH-1:0] s444_sync, + input [23:0] s444_data, + + // 422 outputs + + output reg [DELAY_DATA_WIDTH-1:0] s422_sync, + output reg [15:0] s422_data +); + + localparam DW = DELAY_DATA_WIDTH - 1; + + // internal registers + + reg s444_de_d = 'd0; + reg [DW:0] s444_sync_d = 'd0; + reg [23:0] s444_data_d = 'd0; + reg s444_de_2d = 'd0; + reg [DW:0] s444_sync_2d = 'd0; + reg [23:0] s444_data_2d = 'd0; + reg s444_de_3d = 'd0; + reg [DW:0] s444_sync_3d = 'd0; + reg [23:0] s444_data_3d = 'd0; + reg [ 7:0] cr = 'd0; + reg [ 7:0] cb = 'd0; + reg cr_cb_sel = 'd0; + + // internal wires + + wire [ 9:0] cr_s; + wire [ 9:0] cb_s; + + // fill the data pipe lines, hold the last data on edges + + always @(posedge clk) begin + s444_de_d <= s444_de; + s444_sync_d <= s444_sync; + if (s444_de == 1'b1) begin + s444_data_d <= s444_data; + end + s444_de_2d <= s444_de_d; + s444_sync_2d <= s444_sync_d; + if (s444_de_d == 1'b1) begin + s444_data_2d <= s444_data_d; + end + s444_de_3d <= s444_de_2d; + s444_sync_3d <= s444_sync_2d; + if (s444_de_2d == 1'b1) begin + s444_data_3d <= s444_data_2d; + end + end + + // get the average 0.25*s(n-1) + 0.5*s(n) + 0.25*s(n+1) + + assign cr_s = {2'd0, s444_data_d[23:16]} + + {2'd0, s444_data_3d[23:16]} + + {1'd0, s444_data_2d[23:16], 1'd0}; + + assign cb_s = {2'd0, s444_data_d[7:0]} + + {2'd0, s444_data_3d[7:0]} + + {1'd0, s444_data_2d[7:0], 1'd0}; + + always @(posedge clk) begin + cr <= cr_s[9:2]; + cb <= cb_s[9:2]; + if (s444_de_3d == 1'b1) begin + cr_cb_sel <= ~cr_cb_sel; + end else begin + cr_cb_sel <= CR_CB_N; + end + end + + // 422 outputs + + always @(posedge clk) begin + s422_sync <= s444_sync_3d; + if (s444_de_3d == 1'b0) begin + s422_data <= 'd0; + end else if (cr_cb_sel == 1'b1) begin + s422_data <= {cr, s444_data_3d[15:8]}; + end else begin + s422_data <= {cb, s444_data_3d[15:8]}; + end + end + +endmodule diff --git a/adi_library/common/ad_sysref_gen.v b/adi_library/common/ad_sysref_gen.v new file mode 100644 index 00000000..1367f5a9 --- /dev/null +++ b/adi_library/common/ad_sysref_gen.v @@ -0,0 +1,84 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_sysref_gen ( + input core_clk, + + input sysref_en, + output reg sysref_out +); + + // SYSREF period is multiple of core_clk, and has a duty cycle of 50% + // NOTE: if SYSREF always on (this is a JESD204 IP configuration), + // the period must be a correct multiple of the multiframe period + parameter SYSREF_PERIOD = 128; + + localparam SYSREF_HALFPERIOD = SYSREF_PERIOD/2 - 1; + + reg [ 7:0] counter; + reg sysref_en_m1; + reg sysref_en_m2; + reg sysref_en_int; + + // bring the enable signal to JESD core clock domain + always @(posedge core_clk) begin + sysref_en_m1 <= sysref_en; + sysref_en_m2 <= sysref_en_m1; + sysref_en_int <= sysref_en_m2; + end + + // free running counter for periodic SYSREF generation + always @(posedge core_clk) begin + if (sysref_en_int) begin + counter <= (counter < SYSREF_HALFPERIOD) ? counter + 1'b1 : 8'h0; + end else begin + counter <= 8'h0; + end + end + + // generate SYSREF + always @(posedge core_clk) begin + if (sysref_en_int) begin + if (counter == SYSREF_HALFPERIOD) begin + sysref_out <= ~sysref_out; + end + end else begin + sysref_out <= 1'b0; + end + end + +endmodule diff --git a/adi_library/common/ad_tdd_control.v b/adi_library/common/ad_tdd_control.v new file mode 100644 index 00000000..46d23175 --- /dev/null +++ b/adi_library/common/ad_tdd_control.v @@ -0,0 +1,814 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module ad_tdd_control#( + + parameter integer TX_DATA_PATH_DELAY = 0, + parameter integer CONTROL_PATH_DELAY = 0 +) ( + + // clock and reset + + input clk, + input rst, + + // TDD timing signals + + input tdd_enable, + input tdd_secondary, + input tdd_tx_only, + input tdd_rx_only, + input [ 7:0] tdd_burst_count, + input [23:0] tdd_counter_init, + input [23:0] tdd_frame_length, + input [23:0] tdd_vco_rx_on_1, + input [23:0] tdd_vco_rx_off_1, + input [23:0] tdd_vco_tx_on_1, + input [23:0] tdd_vco_tx_off_1, + input [23:0] tdd_rx_on_1, + input [23:0] tdd_rx_off_1, + input [23:0] tdd_rx_dp_on_1, + input [23:0] tdd_rx_dp_off_1, + input [23:0] tdd_tx_on_1, + input [23:0] tdd_tx_off_1, + input [23:0] tdd_tx_dp_on_1, + input [23:0] tdd_tx_dp_off_1, + input [23:0] tdd_vco_rx_on_2, + input [23:0] tdd_vco_rx_off_2, + input [23:0] tdd_vco_tx_on_2, + input [23:0] tdd_vco_tx_off_2, + input [23:0] tdd_rx_on_2, + input [23:0] tdd_rx_off_2, + input [23:0] tdd_rx_dp_on_2, + input [23:0] tdd_rx_dp_off_2, + input [23:0] tdd_tx_on_2, + input [23:0] tdd_tx_off_2, + input [23:0] tdd_tx_dp_on_2, + input [23:0] tdd_tx_dp_off_2, + input tdd_sync, + + // TDD control signals + + output reg tdd_tx_dp_en, + output reg tdd_rx_dp_en, + output reg tdd_rx_vco_en, + output reg tdd_tx_vco_en, + output reg tdd_rx_rf_en, + output reg tdd_tx_rf_en, + + output [23:0] tdd_counter_status +); + + localparam [ 0:0] ON = 1; + localparam [ 0:0] OFF = 0; + + // tdd control related + + // tdd counter related + + reg [23:0] tdd_counter = 24'h0; + reg [ 5:0] tdd_burst_counter = 6'h0; + + reg tdd_cstate = OFF; + reg tdd_cstate_next = OFF; + + reg counter_at_tdd_vco_rx_on_1 = 1'b0; + reg counter_at_tdd_vco_rx_off_1 = 1'b0; + reg counter_at_tdd_vco_tx_on_1 = 1'b0; + reg counter_at_tdd_vco_tx_off_1 = 1'b0; + reg counter_at_tdd_rx_on_1 = 1'b0; + reg counter_at_tdd_rx_off_1 = 1'b0; + reg counter_at_tdd_rx_dp_on_1 = 1'b0; + reg counter_at_tdd_rx_dp_off_1 = 1'b0; + reg counter_at_tdd_tx_on_1 = 1'b0; + reg counter_at_tdd_tx_off_1 = 1'b0; + reg counter_at_tdd_tx_dp_on_1 = 1'b0; + reg counter_at_tdd_tx_dp_off_1 = 1'b0; + reg counter_at_tdd_vco_rx_on_2 = 1'b0; + reg counter_at_tdd_vco_rx_off_2 = 1'b0; + reg counter_at_tdd_vco_tx_on_2 = 1'b0; + reg counter_at_tdd_vco_tx_off_2 = 1'b0; + reg counter_at_tdd_rx_on_2 = 1'b0; + reg counter_at_tdd_rx_off_2 = 1'b0; + reg counter_at_tdd_rx_dp_on_2 = 1'b0; + reg counter_at_tdd_rx_dp_off_2 = 1'b0; + reg counter_at_tdd_tx_on_2 = 1'b0; + reg counter_at_tdd_tx_off_2 = 1'b0; + reg counter_at_tdd_tx_dp_on_2 = 1'b0; + reg counter_at_tdd_tx_dp_off_2 = 1'b0; + + reg tdd_last_burst = 1'b0; + + reg tdd_sync_d1 = 1'b0; + reg tdd_sync_d2 = 1'b0; + reg tdd_sync_d3 = 1'b0; + + reg tdd_endof_frame = 1'b0; + + // internal signals + + wire [23:0] tdd_vco_rx_on_1_s; + wire [23:0] tdd_vco_rx_off_1_s; + wire [23:0] tdd_vco_tx_on_1_s; + wire [23:0] tdd_vco_tx_off_1_s; + wire [23:0] tdd_rx_on_1_s; + wire [23:0] tdd_rx_off_1_s; + wire [23:0] tdd_tx_on_1_s; + wire [23:0] tdd_tx_off_1_s; + wire [23:0] tdd_tx_dp_on_1_s; + wire [23:0] tdd_tx_dp_off_1_s; + + wire [23:0] tdd_vco_rx_on_2_s; + wire [23:0] tdd_vco_rx_off_2_s; + wire [23:0] tdd_vco_tx_on_2_s; + wire [23:0] tdd_vco_tx_off_2_s; + wire [23:0] tdd_rx_on_2_s; + wire [23:0] tdd_rx_off_2_s; + wire [23:0] tdd_tx_on_2_s; + wire [23:0] tdd_tx_off_2_s; + wire [23:0] tdd_tx_dp_on_2_s; + wire [23:0] tdd_tx_dp_off_2_s; + wire tdd_endof_burst; + wire tdd_txrx_only_en_s; + + assign tdd_counter_status = tdd_counter; + + // synchronization of tdd_sync + always @(posedge clk) begin + if (rst == 1'b1) begin + tdd_sync_d1 <= 1'b0; + tdd_sync_d2 <= 1'b0; + tdd_sync_d3 <= 1'b0; + end else begin + tdd_sync_d1 <= tdd_sync; + tdd_sync_d2 <= tdd_sync_d1; + tdd_sync_d3 <= tdd_sync_d2; + end + end + + // *************************************************************************** + // tdd counter (state machine) + // *************************************************************************** + + always @(posedge clk) begin + if (rst == 1'b1) begin + tdd_cstate <= OFF; + end else begin + tdd_cstate <= tdd_cstate_next; + end + end + + always @* begin + tdd_cstate_next <= tdd_cstate; + + case (tdd_cstate) + ON : begin + if ((tdd_enable == 1'b0) || (tdd_endof_burst == 1'b1)) begin + tdd_cstate_next <= OFF; + end + end + + OFF : begin + if(tdd_enable == 1'b1) begin + tdd_cstate_next <= ((~tdd_sync_d3 & tdd_sync_d2) == 1'b1) ? ON : OFF; + end + end + endcase + end + + always @(posedge clk) begin + if (tdd_counter == (tdd_frame_length - 1'b1)) begin + tdd_endof_frame <= 1'b1; + end else begin + tdd_endof_frame <= 1'b0; + end + end + assign tdd_endof_burst = ((tdd_last_burst == 1'b1) && (tdd_endof_frame == 1'b1)) ? 1'b1 : 1'b0; + + // tdd free running counter + always @(posedge clk) begin + if (rst == 1'b1) begin + tdd_counter <= tdd_counter_init; + end else begin + if (tdd_cstate == ON) begin + if ((~tdd_sync_d3 & tdd_sync_d2) == 1'b1) begin + tdd_counter <= 24'b0; + end else begin + tdd_counter <= (tdd_endof_frame == 1'b1) ? 24'b0 : tdd_counter + 1'b1; + end + end else begin + tdd_counter <= tdd_counter_init; + end + end + end + + // tdd burst counter + always @(posedge clk) begin + if (tdd_cstate == OFF) begin + tdd_burst_counter <= tdd_burst_count; + end else if ((tdd_burst_counter != 0) && (tdd_endof_frame == 1'b1)) begin + tdd_burst_counter <= tdd_burst_counter - 1'b1; + end + end + + always @(posedge clk) begin + tdd_last_burst <= (tdd_burst_counter == 6'b1) ? 1'b1 : 1'b0; + end + + // *************************************************************************** + // generate control signals + // *************************************************************************** + + // start/stop rx vco + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_vco_rx_on_1 <= 1'b0; + end else if(tdd_counter == tdd_vco_rx_on_1_s) begin + counter_at_tdd_vco_rx_on_1 <= 1'b1; + end else begin + counter_at_tdd_vco_rx_on_1 <= 1'b0; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_vco_rx_on_2 <= 1'b0; + end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_rx_on_2_s)) begin + counter_at_tdd_vco_rx_on_2 <= 1'b1; + end else begin + counter_at_tdd_vco_rx_on_2 <= 1'b0; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_vco_rx_off_1 <= 1'b0; + end else if(tdd_counter == tdd_vco_rx_off_1_s) begin + counter_at_tdd_vco_rx_off_1 <= 1'b1; + end else begin + counter_at_tdd_vco_rx_off_1 <= 1'b0; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_vco_rx_off_2 <= 1'b0; + end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_rx_off_2_s)) begin + counter_at_tdd_vco_rx_off_2 <= 1'b1; + end else begin + counter_at_tdd_vco_rx_off_2 <= 1'b0; + end + end + + // start/stop tx vco + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_vco_tx_on_1 <= 1'b0; + end else if(tdd_counter == tdd_vco_tx_on_1_s) begin + counter_at_tdd_vco_tx_on_1 <= 1'b1; + end else begin + counter_at_tdd_vco_tx_on_1 <= 1'b0; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_vco_tx_on_2 <= 1'b0; + end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_tx_on_2_s)) begin + counter_at_tdd_vco_tx_on_2 <= 1'b1; + end else begin + counter_at_tdd_vco_tx_on_2 <= 1'b0; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_vco_tx_off_1 <= 1'b0; + end else if(tdd_counter == tdd_vco_tx_off_1_s) begin + counter_at_tdd_vco_tx_off_1 <= 1'b1; + end else begin + counter_at_tdd_vco_tx_off_1 <= 1'b0; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_vco_tx_off_2 <= 1'b0; + end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_vco_tx_off_2_s)) begin + counter_at_tdd_vco_tx_off_2 <= 1'b1; + end else begin + counter_at_tdd_vco_tx_off_2 <= 1'b0; + end + end + + // start/stop rx rf path + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_rx_on_1 <= 1'b0; + end else if(tdd_counter == tdd_rx_on_1_s) begin + counter_at_tdd_rx_on_1 <= 1'b1; + end else begin + counter_at_tdd_rx_on_1 <= 1'b0; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_rx_on_2 <= 1'b0; + end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_on_2_s)) begin + counter_at_tdd_rx_on_2 <= 1'b1; + end else begin + counter_at_tdd_rx_on_2 <= 1'b0; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_rx_off_1 <= 1'b0; + end else if(tdd_counter == tdd_rx_off_1_s) begin + counter_at_tdd_rx_off_1 <= 1'b1; + end else begin + counter_at_tdd_rx_off_1 <= 1'b0; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_rx_off_2 <= 1'b0; + end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_off_2_s)) begin + counter_at_tdd_rx_off_2 <= 1'b1; + end else begin + counter_at_tdd_rx_off_2 <= 1'b0; + end + end + + // start/stop tx rf path + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_tx_on_1 <= 1'b0; + end else if(tdd_counter == tdd_tx_on_1_s) begin + counter_at_tdd_tx_on_1 <= 1'b1; + end else begin + counter_at_tdd_tx_on_1 <= 1'b0; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_tx_on_2 <= 1'b0; + end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_on_2_s)) begin + counter_at_tdd_tx_on_2 <= 1'b1; + end else begin + counter_at_tdd_tx_on_2 <= 1'b0; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_tx_off_1 <= 1'b0; + end else if(tdd_counter == tdd_tx_off_1_s) begin + counter_at_tdd_tx_off_1 <= 1'b1; + end else begin + counter_at_tdd_tx_off_1 <= 1'b0; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_tx_off_2 <= 1'b0; + end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_off_2_s)) begin + counter_at_tdd_tx_off_2 <= 1'b1; + end else begin + counter_at_tdd_tx_off_2 <= 1'b0; + end + end + + // start/stop tx data path + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_tx_dp_on_1 <= 1'b0; + end else if(tdd_counter == tdd_tx_dp_on_1_s) begin + counter_at_tdd_tx_dp_on_1 <= 1'b1; + end else begin + counter_at_tdd_tx_dp_on_1 <= 1'b0; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_tx_dp_on_2 <= 1'b0; + end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_dp_on_2_s)) begin + counter_at_tdd_tx_dp_on_2 <= 1'b1; + end else begin + counter_at_tdd_tx_dp_on_2 <= 1'b0; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_tx_dp_off_1 <= 1'b0; + end else if(tdd_counter == tdd_tx_dp_off_1_s) begin + counter_at_tdd_tx_dp_off_1 <= 1'b1; + end else begin + counter_at_tdd_tx_dp_off_1 <= 1'b0; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_tx_dp_off_2 <= 1'b0; + end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_tx_dp_off_2_s)) begin + counter_at_tdd_tx_dp_off_2 <= 1'b1; + end else begin + counter_at_tdd_tx_dp_off_2 <= 1'b0; + end + end + + // start/stop rx data path + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_rx_dp_on_1 <= 1'b0; + end else if(tdd_counter == tdd_rx_dp_on_1) begin + counter_at_tdd_rx_dp_on_1 <= 1'b1; + end else begin + counter_at_tdd_rx_dp_on_1 <= 1'b0; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_rx_dp_on_2 <= 1'b0; + end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_dp_on_2)) begin + counter_at_tdd_rx_dp_on_2 <= 1'b1; + end else begin + counter_at_tdd_rx_dp_on_2 <= 1'b0; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_rx_dp_off_1 <= 1'b0; + end else if(tdd_counter == tdd_rx_dp_off_1) begin + counter_at_tdd_rx_dp_off_1 <= 1'b1; + end else begin + counter_at_tdd_rx_dp_off_1 <= 1'b0; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + counter_at_tdd_rx_dp_off_2 <= 1'b0; + end else if((tdd_secondary == 1'b1) && (tdd_counter == tdd_rx_dp_off_2)) begin + counter_at_tdd_rx_dp_off_2 <= 1'b1; + end else begin + counter_at_tdd_rx_dp_off_2 <= 1'b0; + end + end + + // control-path delay compensation + + ad_addsub #( + .A_DATA_WIDTH(24), + .B_DATA_VALUE(CONTROL_PATH_DELAY), + .ADD_OR_SUB_N(0) + ) i_vco_rx_on_1_comp ( + .clk(clk), + .A(tdd_vco_rx_on_1), + .Amax(tdd_frame_length), + .out(tdd_vco_rx_on_1_s), + .CE(1'b1)); + + ad_addsub #( + .A_DATA_WIDTH(24), + .B_DATA_VALUE(CONTROL_PATH_DELAY), + .ADD_OR_SUB_N(0) + ) i_vco_rx_off_1_comp ( + .clk(clk), + .A(tdd_vco_rx_off_1), + .Amax(tdd_frame_length), + .out(tdd_vco_rx_off_1_s), + .CE(1'b1)); + + ad_addsub #( + .A_DATA_WIDTH(24), + .B_DATA_VALUE(CONTROL_PATH_DELAY), + .ADD_OR_SUB_N(0) + ) i_vco_tx_on_1_comp ( + .clk(clk), + .A(tdd_vco_tx_on_1), + .Amax(tdd_frame_length), + .out(tdd_vco_tx_on_1_s), + .CE(1'b1)); + + ad_addsub #( + .A_DATA_WIDTH(24), + .B_DATA_VALUE(CONTROL_PATH_DELAY), + .ADD_OR_SUB_N(0) + ) i_vco_tx_off_1_comp ( + .clk(clk), + .A(tdd_vco_tx_off_1), + .Amax(tdd_frame_length), + .out(tdd_vco_tx_off_1_s), + .CE(1'b1)); + + ad_addsub #( + .A_DATA_WIDTH(24), + .B_DATA_VALUE(CONTROL_PATH_DELAY), + .ADD_OR_SUB_N(0) + ) i_rx_on_1_comp ( + .clk(clk), + .A(tdd_rx_on_1), + .Amax(tdd_frame_length), + .out(tdd_rx_on_1_s), + .CE(1'b1)); + + ad_addsub #( + .A_DATA_WIDTH(24), + .B_DATA_VALUE(CONTROL_PATH_DELAY), + .ADD_OR_SUB_N(0) + ) i_rx_off_1_comp ( + .clk(clk), + .A(tdd_rx_off_1), + .Amax(tdd_frame_length), + .out(tdd_rx_off_1_s), + .CE(1'b1)); + + ad_addsub #( + .A_DATA_WIDTH(24), + .B_DATA_VALUE(CONTROL_PATH_DELAY), + .ADD_OR_SUB_N(0) + ) i_tx_on_1_comp ( + .clk(clk), + .A(tdd_tx_on_1), + .Amax(tdd_frame_length), + .out(tdd_tx_on_1_s), + .CE(1'b1)); + + ad_addsub #( + .A_DATA_WIDTH(24), + .B_DATA_VALUE(CONTROL_PATH_DELAY), + .ADD_OR_SUB_N(0) + ) i_tx_off_1_comp ( + .clk(clk), + .A(tdd_tx_off_1), + .Amax(tdd_frame_length), + .out(tdd_tx_off_1_s), + .CE(1'b1)); + + ad_addsub #( + .A_DATA_WIDTH(24), + .B_DATA_VALUE(CONTROL_PATH_DELAY), + .ADD_OR_SUB_N(0) + ) i_vco_rx_on_2_comp ( + .clk(clk), + .A(tdd_vco_rx_on_2), + .Amax(tdd_frame_length), + .out(tdd_vco_rx_on_2_s), + .CE(1'b1)); + + ad_addsub #( + .A_DATA_WIDTH(24), + .B_DATA_VALUE(CONTROL_PATH_DELAY), + .ADD_OR_SUB_N(0) + ) i_vco_rx_off_2_comp ( + .clk(clk), + .A(tdd_vco_rx_off_2), + .Amax(tdd_frame_length), + .out(tdd_vco_rx_off_2_s), + .CE(1'b1)); + + ad_addsub #( + .A_DATA_WIDTH(24), + .B_DATA_VALUE(CONTROL_PATH_DELAY), + .ADD_OR_SUB_N(0) + ) i_vco_tx_on_2_comp ( + .clk(clk), + .A(tdd_vco_tx_on_2), + .Amax(tdd_frame_length), + .out(tdd_vco_tx_on_2_s), + .CE(1'b1)); + + ad_addsub #( + .A_DATA_WIDTH(24), + .B_DATA_VALUE(CONTROL_PATH_DELAY), + .ADD_OR_SUB_N(0) + ) i_vco_tx_off_2_comp ( + .clk(clk), + .A(tdd_vco_tx_off_2), + .Amax(tdd_frame_length), + .out(tdd_vco_tx_off_2_s), + .CE(1'b1)); + + ad_addsub #( + .A_DATA_WIDTH(24), + .B_DATA_VALUE(CONTROL_PATH_DELAY), + .ADD_OR_SUB_N(0) + ) i_rx_on_2_comp ( + .clk(clk), + .A(tdd_rx_on_2), + .Amax(tdd_frame_length), + .out(tdd_rx_on_2_s), + .CE(1'b1)); + + ad_addsub #( + .A_DATA_WIDTH(24), + .B_DATA_VALUE(CONTROL_PATH_DELAY), + .ADD_OR_SUB_N(0) + ) i_rx_off_2_comp ( + .clk(clk), + .A(tdd_rx_off_2), + .Amax(tdd_frame_length), + .out(tdd_rx_off_2_s), + .CE(1'b1)); + + ad_addsub #( + .A_DATA_WIDTH(24), + .B_DATA_VALUE(CONTROL_PATH_DELAY), + .ADD_OR_SUB_N(0) + ) i_tx_on_2_comp ( + .clk(clk), + .A(tdd_tx_on_2), + .Amax(tdd_frame_length), + .out(tdd_tx_on_2_s), + .CE(1'b1)); + + ad_addsub #( + .A_DATA_WIDTH(24), + .B_DATA_VALUE(CONTROL_PATH_DELAY), + .ADD_OR_SUB_N(0) + ) i_tx_off_2_comp ( + .clk(clk), + .A(tdd_tx_off_2), + .Amax(tdd_frame_length), + .out(tdd_tx_off_2_s), + .CE(1'b1)); + + // internal data-path delay compensation + + ad_addsub #( + .A_DATA_WIDTH(24), + .B_DATA_VALUE(TX_DATA_PATH_DELAY), + .ADD_OR_SUB_N(0) + ) i_tx_dp_on_1_comp ( + .clk(clk), + .A(tdd_tx_dp_on_1), + .Amax(tdd_frame_length), + .out(tdd_tx_dp_on_1_s), + .CE(1'b1)); + + ad_addsub #( + .A_DATA_WIDTH(24), + .B_DATA_VALUE(TX_DATA_PATH_DELAY), + .ADD_OR_SUB_N(0) + ) i_tx_dp_on_2_comp ( + .clk(clk), + .A(tdd_tx_dp_on_2), + .Amax(tdd_frame_length), + .out(tdd_tx_dp_on_2_s), + .CE(1'b1)); + + ad_addsub #( + .A_DATA_WIDTH(24), + .B_DATA_VALUE(TX_DATA_PATH_DELAY), + .ADD_OR_SUB_N(0) + ) i_tx_dp_off_1_comp ( + .clk(clk), + .A(tdd_tx_dp_off_1), + .Amax(tdd_frame_length), + .out(tdd_tx_dp_off_1_s), + .CE(1'b1)); + + ad_addsub #( + .A_DATA_WIDTH(24), + .B_DATA_VALUE(TX_DATA_PATH_DELAY), + .ADD_OR_SUB_N(0) + ) i_tx_dp_off_2_comp ( + .clk(clk), + .A(tdd_tx_dp_off_2), + .Amax(tdd_frame_length), + .out(tdd_tx_dp_off_2_s), + .CE(1'b1)); + + // output logic + + assign tdd_txrx_only_en_s = tdd_tx_only ^ tdd_rx_only; + + always @(posedge clk) begin + if(rst == 1'b1) begin + tdd_rx_vco_en <= 1'b0; + end else if((tdd_cstate == OFF) || (counter_at_tdd_vco_rx_off_1 == 1'b1) || (counter_at_tdd_vco_rx_off_2 == 1'b1)) begin + tdd_rx_vco_en <= 1'b0; + end else if((tdd_cstate == ON) && ((counter_at_tdd_vco_rx_on_1 == 1'b1) || (counter_at_tdd_vco_rx_on_2 == 1'b1))) begin + tdd_rx_vco_en <= 1'b1; + end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin + tdd_rx_vco_en <= tdd_rx_only; + end else begin + tdd_rx_vco_en <= tdd_rx_vco_en; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + tdd_tx_vco_en <= 1'b0; + end else if((tdd_cstate == OFF) || (counter_at_tdd_vco_tx_off_1 == 1'b1) || (counter_at_tdd_vco_tx_off_2 == 1'b1)) begin + tdd_tx_vco_en <= 1'b0; + end else if((tdd_cstate == ON) && ((counter_at_tdd_vco_tx_on_1 == 1'b1) || (counter_at_tdd_vco_tx_on_2 == 1'b1))) begin + tdd_tx_vco_en <= 1'b1; + end else if((tdd_cstate == ON) && (tdd_txrx_only_en_s == 1'b1)) begin + tdd_tx_vco_en <= tdd_tx_only; + end else begin + tdd_tx_vco_en <= tdd_tx_vco_en; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + tdd_rx_rf_en <= 1'b0; + end else if((tdd_cstate == OFF) || (counter_at_tdd_rx_off_1 == 1'b1) || (counter_at_tdd_rx_off_2 == 1'b1)) begin + tdd_rx_rf_en <= 1'b0; + end else if((tdd_cstate == ON) && (tdd_tx_only == 1'b1)) begin + tdd_rx_rf_en <= 1'b0; + end else if((tdd_cstate == ON) && ((counter_at_tdd_rx_on_1 == 1'b1) || (counter_at_tdd_rx_on_2 == 1'b1))) begin + tdd_rx_rf_en <= 1'b1; + end else begin + tdd_rx_rf_en <= tdd_rx_rf_en; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + tdd_tx_rf_en <= 1'b0; + end else if((tdd_cstate == OFF) || (counter_at_tdd_tx_off_1 == 1'b1) || (counter_at_tdd_tx_off_2 == 1'b1)) begin + tdd_tx_rf_en <= 1'b0; + end else if((tdd_cstate == ON) && (tdd_rx_only == 1'b1)) begin + tdd_tx_rf_en <= 1'b0; + end else if((tdd_cstate == ON) && ((counter_at_tdd_tx_on_1 == 1'b1) || (counter_at_tdd_tx_on_2 == 1'b1))) begin + tdd_tx_rf_en <= 1'b1; + end else begin + tdd_tx_rf_en <= tdd_tx_rf_en; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + tdd_tx_dp_en <= 1'b0; + end else if((tdd_cstate == OFF) || (counter_at_tdd_tx_dp_off_1 == 1'b1) || (counter_at_tdd_tx_dp_off_2 == 1'b1)) begin + tdd_tx_dp_en <= 1'b0; + end else if((tdd_cstate == ON) && (tdd_rx_only == 1'b1)) begin + tdd_tx_dp_en <= 1'b0; + end else if((tdd_cstate == ON) && ((counter_at_tdd_tx_dp_on_1 == 1'b1) || (counter_at_tdd_tx_dp_on_2 == 1'b1))) begin + tdd_tx_dp_en <= 1'b1; + end else begin + tdd_tx_dp_en <= tdd_tx_dp_en; + end + end + + always @(posedge clk) begin + if(rst == 1'b1) begin + tdd_rx_dp_en <= 1'b0; + end else if((tdd_cstate == OFF) || (counter_at_tdd_rx_dp_off_1 == 1'b1) || (counter_at_tdd_rx_dp_off_2 == 1'b1)) begin + tdd_rx_dp_en <= 1'b0; + end else if((tdd_cstate == ON) && (tdd_tx_only == 1'b1)) begin + tdd_rx_dp_en <= 1'b0; + end else if((tdd_cstate == ON) && ((counter_at_tdd_rx_dp_on_1 == 1'b1) || (counter_at_tdd_rx_dp_on_2 == 1'b1))) begin + tdd_rx_dp_en <= 1'b1; + end else begin + tdd_rx_dp_en <= tdd_rx_dp_en; + end + end + +endmodule diff --git a/adi_library/common/ad_upack.v b/adi_library/common/ad_upack.v new file mode 100644 index 00000000..ecb62eeb --- /dev/null +++ b/adi_library/common/ad_upack.v @@ -0,0 +1,180 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +// Unpacker: +// - unpack O_W number of data units from I_W number of data units +// - data unit defined in bits by UNIT_W e.g 8 is a byte +// +// Constraints: +// - O_W < I_W +// - LATENCY 1 +// - no backpressure +// +// Data format: +// idata [U(I_W-1) .... U(0)] +// odata [U(O_W-1) .... U(0)] +// +// e.g +// I_W = 6 +// O_W = 4 +// UNIT_W = 8 +// +// idata : [B5,B4,B3,B2,B1,B0],[B11,B10,B9,B8,B7,B6] +// odata : [B3,B2,B1,B0],[B7,B6,B5,B4],[B11,B10,B9,B8] +// + +module ad_upack #( + parameter I_W = 4, + parameter O_W = 3, + parameter UNIT_W = 8, + parameter O_REG = 1 +) ( + input clk, + input reset, + input [I_W*UNIT_W-1:0] idata, + input ivalid, + output iready, + + output reg [O_W*UNIT_W-1:0] odata = 'h0, + output reg ovalid = 'b0 +); + + // The Width of the shift reg is an integer multiple of output data width + localparam SH_W = ((I_W/O_W) + ((I_W%O_W) > 0) + ((O_W % (I_W - ((I_W/O_W)*O_W) + ((I_W%O_W) == 0))) > 0))*O_W; + // The Step of the algorithm is the greatest common divisor of I_W and O_W + localparam STEP = gcd(I_W, O_W); + + localparam LATENCY = 1; // Minimum input latency from iready to ivalid + + integer i; + + reg [SH_W*UNIT_W-1:0] idata_sh; + reg [SH_W*UNIT_W-1:0] idata_d = 'h0; + reg [SH_W*UNIT_W-1:0] idata_d_nx; + reg [SH_W-1:0] in_use = 'h0; + reg [SH_W-1:0] inmask; + + wire [SH_W-1:0] out_mask = {O_W{1'b1}}; + wire [SH_W-1:0] in_use_nx; + wire [SH_W-1:0] unit_valid; + wire [O_W*UNIT_W-1:0] odata_s; + wire ovalid_s; + + function [31:0] gcd; + input [31:0] a; + input [31:0] b; + begin + while (a != b) begin + if (a > b) begin + a = a-b; + end else begin + b = b-a; + end + end + gcd = a; + end + endfunction + + assign unit_valid = (in_use | inmask); + assign in_use_nx = unit_valid >> O_W; + + always @(posedge clk) begin + if (reset) begin + in_use <= 'h0; + end else if (ovalid_s) begin + in_use <= in_use_nx; + end + end + + always @(*) begin + inmask = {I_W{ivalid}}; + for (i = STEP; i < O_W; i=i+STEP) begin + if (in_use[i-1]) begin + inmask = {I_W{ivalid}} << i; + end + end + end + + always @(*) begin + idata_d_nx = idata_d; + if (ivalid) begin + idata_d_nx = {{(SH_W-I_W)*UNIT_W{1'b0}},idata}; + for (i = STEP; i < O_W; i=i+STEP) begin + if (in_use[i-1]) begin + idata_d_nx = (idata << UNIT_W*i) | idata_d; + end + end + end + end + + always @(posedge clk) begin + if (ovalid_s) begin + idata_d <= idata_d_nx >> O_W*UNIT_W; + end + end + + assign iready = ~unit_valid[LATENCY*O_W + O_W -1]; + + assign odata_s = idata_d_nx[O_W*UNIT_W-1:0]; + assign ovalid_s = unit_valid[O_W-1]; + + generate + if (O_REG) begin : o_reg + + always @(posedge clk) begin + if (reset) begin + ovalid <= 1'b0; + end else begin + ovalid <= ovalid_s; + end + end + + always @(posedge clk) begin + odata <= odata_s; + end + + end else begin + + always @(*) begin + odata = odata_s; + ovalid = ovalid_s; + end + + end + endgenerate + +endmodule diff --git a/adi_library/common/ad_xcvr_rx_if.v b/adi_library/common/ad_xcvr_rx_if.v new file mode 100644 index 00000000..8bbd3f86 --- /dev/null +++ b/adi_library/common/ad_xcvr_rx_if.v @@ -0,0 +1,100 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_xcvr_rx_if #( + parameter OCTETS_PER_BEAT = 4, + parameter DW = OCTETS_PER_BEAT * 8 +) ( + + // jesd interface + + input rx_clk, + input [OCTETS_PER_BEAT-1:0] rx_ip_sof, + input [DW-1:0] rx_ip_data, + output reg rx_sof, + output reg [DW-1:0] rx_data +); + + // rx_ip_sof: + // The input beat may contain more than one frame per clock, a sof bit is set for + // each frame. + // Every bit that corresponds to a octet that is at the beginning of a frame + // the bit is set. E.g for OCTETS_PER_BEAT = 4 + // if F=1 all bits are set, + // F=2 sof=4'b0101, + // F=4 sof=4'b0001 + + // + // rx_ip_data: + // The temporal ordering of the octets is from LSB to MSB, + // this means the octet placed in the lowest 8 bits was received first, + // the octet placed in the highest 8 bits was received last. + + // internal registers + + reg [DW-1:0] rx_ip_data_d = 'd0; + reg [OCTETS_PER_BEAT-1:0] rx_ip_sof_hold = 'd0; + reg [OCTETS_PER_BEAT-1:0] rx_ip_sof_d = 'd0; + + always @(posedge rx_clk) begin + rx_ip_data_d <= rx_ip_data; + rx_ip_sof_d <= rx_ip_sof; + if (|rx_ip_sof) begin + rx_ip_sof_hold <= rx_ip_sof; + end + rx_sof <= |rx_ip_sof_d; + end + + wire [OCTETS_PER_BEAT*DW-1:0] rx_data_s; + assign rx_data_s[0 +: DW] = rx_ip_data; + generate + genvar i; + for (i = 1; i < OCTETS_PER_BEAT; i = i + 1) begin : g_rx_data_opt + assign rx_data_s[i*DW +: DW] = {rx_ip_data[i*8-1 : 0], rx_ip_data_d[DW-1 : i*8]}; + end + endgenerate + + integer j; + always @(posedge rx_clk) begin + for (j = OCTETS_PER_BEAT-1; j >= 0; j = j - 1) begin + if (rx_ip_sof_hold[j] == 1'b1) begin + rx_data <= rx_data_s[j*DW +: DW]; + end + end + end + +endmodule diff --git a/adi_library/common/axi_ctrlif.vhd b/adi_library/common/axi_ctrlif.vhd new file mode 100644 index 00000000..ddf25aeb --- /dev/null +++ b/adi_library/common/axi_ctrlif.vhd @@ -0,0 +1,148 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +-- +-- In this HDL repository, there are many different and unique modules, consisting +-- of various HDL (Verilog or VHDL) components. The individual modules are +-- developed independently, and may be accompanied by separate and unique license +-- terms. +-- +-- The user should read each of these license terms, and understand the +-- freedoms and responsibilities that he or she has by using this source/core. +-- +-- This core is distributed in the hope that it will be useful, but WITHOUT ANY +-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +-- A PARTICULAR PURPOSE. +-- +-- Redistribution and use of source or resulting binaries, with or without modification +-- of this file, are permitted under one of the following two license terms: +-- +-- 1. The GNU General Public License version 2 as published by the +-- Free Software Foundation, which can be found in the top level directory +-- of this repository (LICENSE_GPL2), and also online at: +-- +-- +-- OR +-- +-- 2. An ADI specific BSD license, which can be found in the top level directory +-- of this repository (LICENSE_ADIBSD), and also on-line at: +-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +-- This will allow to generate bit files and not release the source code, +-- as long as it attaches to an ADI device. +-- +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity axi_ctrlif is + generic + ( + C_NUM_REG : integer := 32; + C_S_AXI_DATA_WIDTH : integer := 32; + C_S_AXI_ADDR_WIDTH : integer := 32; + C_FAMILY : string := "virtex6" + ); + port + ( + -- AXI bus interface + s_axi_aclk : in std_logic; + s_axi_aresetn : in std_logic; + s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_awvalid : in std_logic; + s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); + s_axi_wvalid : in std_logic; + s_axi_bready : in std_logic; + s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); + s_axi_arvalid : in std_logic; + s_axi_rready : in std_logic; + s_axi_arready : out std_logic; + s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + s_axi_rresp : out std_logic_vector(1 downto 0); + s_axi_rvalid : out std_logic; + s_axi_wready : out std_logic; + s_axi_bresp : out std_logic_vector(1 downto 0); + s_axi_bvalid : out std_logic; + s_axi_awready : out std_logic; + + rd_addr : out integer range 0 to C_NUM_REG - 1; + rd_data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + rd_ack : out std_logic; + rd_stb : in std_logic; + + wr_addr : out integer range 0 to C_NUM_REG - 1; + wr_data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); + wr_ack : in std_logic; + wr_stb : out std_logic + ); +end entity axi_ctrlif; + + +architecture Behavioral of axi_ctrlif is + type state_type is (IDLE, RESP, ACK); + signal rd_state : state_type; + signal wr_state : state_type; +begin + process (s_axi_aclk) + begin + if rising_edge(s_axi_aclk) then + if s_axi_aresetn = '0' then + rd_state <= IDLE; + else + case rd_state is + when IDLE => + if s_axi_arvalid = '1' then + rd_state <= RESP; + rd_addr <= to_integer(unsigned(s_axi_araddr((C_S_AXI_ADDR_WIDTH-1) downto 2))); + end if; + when RESP => + if rd_stb = '1' and s_axi_rready = '1' then + rd_state <= IDLE; + end if; + when others => null; + end case; + end if; + end if; + end process; + + s_axi_arready <= '1' when rd_state = IDLE else '0'; + s_axi_rvalid <= '1' when rd_state = RESP and rd_stb = '1' else '0'; + s_axi_rresp <= "00"; + rd_ack <= '1' when rd_state = RESP and s_axi_rready = '1' else '0'; + s_axi_rdata <= rd_data; + + process (s_axi_aclk) + begin + if rising_edge(s_axi_aclk) then + if s_axi_aresetn = '0' then + wr_state <= IDLE; + else + case wr_state is + when IDLE => + if s_axi_awvalid = '1' and s_axi_wvalid = '1' and wr_ack = '1' then + wr_state <= ACK; + end if; + when ACK => + wr_state <= RESP; + when RESP => + if s_axi_bready = '1' then + wr_state <= IDLE; + end if; + end case; + end if; + end if; + end process; + + wr_stb <= '1' when s_axi_awvalid = '1' and s_axi_wvalid = '1' and wr_state = IDLE else '0'; + wr_data <= s_axi_wdata; + wr_addr <= to_integer(unsigned(s_axi_awaddr((C_S_AXI_ADDR_WIDTH-1) downto 2))); + + s_axi_awready <= '1' when wr_state = ACK else '0'; + s_axi_wready <= '1' when wr_state = ACK else '0'; + + s_axi_bresp <= "00"; + s_axi_bvalid <= '1' when wr_state = RESP else '0'; +end; diff --git a/adi_library/common/axi_streaming_dma_rx_fifo.vhd b/adi_library/common/axi_streaming_dma_rx_fifo.vhd new file mode 100644 index 00000000..b0e26a89 --- /dev/null +++ b/adi_library/common/axi_streaming_dma_rx_fifo.vhd @@ -0,0 +1,117 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +-- +-- In this HDL repository, there are many different and unique modules, consisting +-- of various HDL (Verilog or VHDL) components. The individual modules are +-- developed independently, and may be accompanied by separate and unique license +-- terms. +-- +-- The user should read each of these license terms, and understand the +-- freedoms and responsibilities that he or she has by using this source/core. +-- +-- This core is distributed in the hope that it will be useful, but WITHOUT ANY +-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +-- A PARTICULAR PURPOSE. +-- +-- Redistribution and use of source or resulting binaries, with or without modification +-- of this file, are permitted under one of the following two license terms: +-- +-- 1. The GNU General Public License version 2 as published by the +-- Free Software Foundation, which can be found in the top level directory +-- of this repository (LICENSE_GPL2), and also online at: +-- +-- +-- OR +-- +-- 2. An ADI specific BSD license, which can be found in the top level directory +-- of this repository (LICENSE_ADIBSD), and also on-line at: +-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +-- This will allow to generate bit files and not release the source code, +-- as long as it attaches to an ADI device. +-- +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; + +library work; +use work.dma_fifo; + +entity axi_streaming_dma_rx_fifo is + generic ( + RAM_ADDR_WIDTH : integer := 3; + FIFO_DWIDTH : integer := 32 + ); + port ( + clk : in std_logic; + resetn : in std_logic; + fifo_reset : in std_logic; + + -- Enable DMA interface + enable : in Boolean; + + period_len : in integer range 0 to 65535; + + -- Read port + m_axis_aclk : in std_logic; + m_axis_tready : in std_logic; + m_axis_tdata : out std_logic_vector(FIFO_DWIDTH-1 downto 0); + m_axis_tlast : out std_logic; + m_axis_tvalid : out std_logic; + m_axis_tkeep : out std_logic_vector(3 downto 0); + + -- Write port + in_stb : in std_logic; + in_ack : out std_logic; + in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0) + ); +end; + +architecture imp of axi_streaming_dma_rx_fifo is + signal out_stb : std_logic; + + signal period_count : integer range 0 to 65535; + signal last : std_logic; +begin + + m_axis_tvalid <= out_stb; + + fifo: entity dma_fifo + generic map ( + RAM_ADDR_WIDTH => RAM_ADDR_WIDTH, + FIFO_DWIDTH => FIFO_DWIDTH + ) + port map ( + clk => clk, + resetn => resetn, + fifo_reset => fifo_reset, + in_stb => in_stb, + in_ack => in_ack, + in_data => in_data, + out_stb => out_stb, + out_ack => m_axis_tready, + out_data => m_axis_tdata + ); + + m_axis_tkeep <= "1111"; + m_axis_tlast <= '1' when period_count = 0 else '0'; + + period_counter: process(m_axis_aclk) is + begin + if rising_edge(m_axis_aclk) then + if resetn = '0' then + period_count <= period_len; + else + if out_stb = '1' and m_axis_tready = '1' then + if period_count = 0 then + period_count <= period_len; + else + period_count <= period_count - 1; + end if; + end if; + end if; + end if; + end process; +end; diff --git a/adi_library/common/axi_streaming_dma_tx_fifo.vhd b/adi_library/common/axi_streaming_dma_tx_fifo.vhd new file mode 100644 index 00000000..20671b02 --- /dev/null +++ b/adi_library/common/axi_streaming_dma_tx_fifo.vhd @@ -0,0 +1,111 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +-- +-- In this HDL repository, there are many different and unique modules, consisting +-- of various HDL (Verilog or VHDL) components. The individual modules are +-- developed independently, and may be accompanied by separate and unique license +-- terms. +-- +-- The user should read each of these license terms, and understand the +-- freedoms and responsibilities that he or she has by using this source/core. +-- +-- This core is distributed in the hope that it will be useful, but WITHOUT ANY +-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +-- A PARTICULAR PURPOSE. +-- +-- Redistribution and use of source or resulting binaries, with or without modification +-- of this file, are permitted under one of the following two license terms: +-- +-- 1. The GNU General Public License version 2 as published by the +-- Free Software Foundation, which can be found in the top level directory +-- of this repository (LICENSE_GPL2), and also online at: +-- +-- +-- OR +-- +-- 2. An ADI specific BSD license, which can be found in the top level directory +-- of this repository (LICENSE_ADIBSD), and also on-line at: +-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +-- This will allow to generate bit files and not release the source code, +-- as long as it attaches to an ADI device. +-- +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; + +library work; +use work.dma_fifo; + +entity axi_streaming_dma_tx_fifo is + generic ( + RAM_ADDR_WIDTH : integer := 3; + FIFO_DWIDTH : integer := 32 + ); + port ( + clk : in std_logic; + resetn : in std_logic; + fifo_reset : in std_logic; + + -- Enable DMA interface + enable : in Boolean; + + -- Write port + s_axis_aclk : in std_logic; + s_axis_tready : out std_logic; + s_axis_tdata : in std_logic_vector(FIFO_DWIDTH-1 downto 0); + s_axis_tlast : in std_logic; + s_axis_tvalid : in std_logic; + + -- Read port + out_stb : out std_logic; + out_ack : in std_logic; + out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0) + ); +end; + +architecture imp of axi_streaming_dma_tx_fifo is + signal in_ack : std_logic; + signal drain_dma : Boolean; +begin + + fifo: entity dma_fifo + generic map ( + RAM_ADDR_WIDTH => RAM_ADDR_WIDTH, + FIFO_DWIDTH => FIFO_DWIDTH + ) + port map ( + clk => clk, + resetn => resetn, + fifo_reset => fifo_reset, + in_stb => s_axis_tvalid, + in_ack => in_ack, + in_data => s_axis_tdata, + out_stb => out_stb, + out_ack => out_ack, + out_data => out_data + ); + + drain_process: process (s_axis_aclk) is + variable enable_d1 : Boolean; + begin + if rising_edge(s_axis_aclk) then + if resetn = '0' then + drain_dma <= False; + else + if s_axis_tlast = '1' then + drain_dma <= False; + elsif not enable_d1 and enable then + drain_dma <= False; + elsif enable_d1 and not enable then + drain_dma <= True; + end if; + enable_d1 := enable; + end if; + end if; + end process; + + s_axis_tready <= '1' when in_ack = '1' or drain_dma else '0'; +end; diff --git a/adi_library/common/dma_fifo.vhd b/adi_library/common/dma_fifo.vhd new file mode 100644 index 00000000..7143d9cc --- /dev/null +++ b/adi_library/common/dma_fifo.vhd @@ -0,0 +1,112 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +-- +-- In this HDL repository, there are many different and unique modules, consisting +-- of various HDL (Verilog or VHDL) components. The individual modules are +-- developed independently, and may be accompanied by separate and unique license +-- terms. +-- +-- The user should read each of these license terms, and understand the +-- freedoms and responsibilities that he or she has by using this source/core. +-- +-- This core is distributed in the hope that it will be useful, but WITHOUT ANY +-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +-- A PARTICULAR PURPOSE. +-- +-- Redistribution and use of source or resulting binaries, with or without modification +-- of this file, are permitted under one of the following two license terms: +-- +-- 1. The GNU General Public License version 2 as published by the +-- Free Software Foundation, which can be found in the top level directory +-- of this repository (LICENSE_GPL2), and also online at: +-- +-- +-- OR +-- +-- 2. An ADI specific BSD license, which can be found in the top level directory +-- of this repository (LICENSE_ADIBSD), and also on-line at: +-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +-- This will allow to generate bit files and not release the source code, +-- as long as it attaches to an ADI device. +-- +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity dma_fifo is + generic ( + RAM_ADDR_WIDTH : integer := 3; + FIFO_DWIDTH : integer := 32 + ); + port ( + clk : in std_logic; + resetn : in std_logic; + fifo_reset : in std_logic; + + -- Write port + in_stb : in std_logic; + in_ack : out std_logic; + in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0); + + -- Read port + out_stb : out std_logic; + out_ack : in std_logic; + out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0) + ); +end; + +architecture imp of dma_fifo is + + constant FIFO_MAX : natural := 2**RAM_ADDR_WIDTH -1; + type MEM is array (0 to FIFO_MAX) of std_logic_vector(FIFO_DWIDTH - 1 downto 0); + signal data_fifo : MEM; + signal wr_addr : natural range 0 to FIFO_MAX; + signal rd_addr : natural range 0 to FIFO_MAX; + signal not_full, not_empty : Boolean; + +begin + in_ack <= '1' when not_full else '0'; + + out_stb <= '1' when not_empty else '0'; + out_data <= data_fifo(rd_addr); + + fifo_data: process (clk) is + begin + if rising_edge(clk) then + if not_full then + data_fifo(wr_addr) <= in_data; + end if; + end if; + end process; + + fifo_ctrl: process (clk) is + variable free_cnt : integer range 0 to FIFO_MAX + 1; + begin + if rising_edge(clk) then + if (resetn = '0') or (fifo_reset = '1') then + wr_addr <= 0; + rd_addr <= 0; + free_cnt := FIFO_MAX + 1; + not_empty <= False; + not_full <= True; + else + if in_stb = '1' and not_full then + wr_addr <= (wr_addr + 1) mod (FIFO_MAX + 1); + free_cnt := free_cnt - 1; + end if; + + if out_ack = '1' and not_empty then + rd_addr <= (rd_addr + 1) mod (FIFO_MAX + 1); + free_cnt := free_cnt + 1; + end if; + + not_full <= not (free_cnt = 0); + not_empty <= not (free_cnt = FIFO_MAX + 1); + end if; + end if; + end process; +end; diff --git a/adi_library/common/pl330_dma_fifo.vhd b/adi_library/common/pl330_dma_fifo.vhd new file mode 100644 index 00000000..5a4f8ea9 --- /dev/null +++ b/adi_library/common/pl330_dma_fifo.vhd @@ -0,0 +1,175 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +-- +-- In this HDL repository, there are many different and unique modules, consisting +-- of various HDL (Verilog or VHDL) components. The individual modules are +-- developed independently, and may be accompanied by separate and unique license +-- terms. +-- +-- The user should read each of these license terms, and understand the +-- freedoms and responsibilities that he or she has by using this source/core. +-- +-- This core is distributed in the hope that it will be useful, but WITHOUT ANY +-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +-- A PARTICULAR PURPOSE. +-- +-- Redistribution and use of source or resulting binaries, with or without modification +-- of this file, are permitted under one of the following two license terms: +-- +-- 1. The GNU General Public License version 2 as published by the +-- Free Software Foundation, which can be found in the top level directory +-- of this repository (LICENSE_GPL2), and also online at: +-- +-- +-- OR +-- +-- 2. An ADI specific BSD license, which can be found in the top level directory +-- of this repository (LICENSE_ADIBSD), and also on-line at: +-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +-- This will allow to generate bit files and not release the source code, +-- as long as it attaches to an ADI device. +-- +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; + +library work; +use work.dma_fifo; + +entity pl330_dma_fifo is + generic ( + RAM_ADDR_WIDTH : integer := 3; + FIFO_DWIDTH : integer := 32; + FIFO_DIRECTION : integer := 0 -- 0 = write FIFO, 1 = read FIFO + ); + port ( + clk : in std_logic; + resetn : in std_logic; + fifo_reset : in std_logic; + + -- Enable DMA interface + enable : in Boolean; + + -- Write port + in_stb : in std_logic; + in_ack : out std_logic; + in_data : in std_logic_vector(FIFO_DWIDTH-1 downto 0); + + -- Read port + out_stb : out std_logic; + out_ack : in std_logic; + out_data : out std_logic_vector(FIFO_DWIDTH-1 downto 0); + + -- PL330 DMA interface + dclk : in std_logic; + dresetn : in std_logic; + davalid : in std_logic; + daready : out std_logic; + datype : in std_logic_vector(1 downto 0); + drvalid : out std_logic; + drready : in std_logic; + drtype : out std_logic_vector(1 downto 0); + drlast : out std_logic; + + DBG : out std_logic_vector(7 downto 0) + ); +end; + +architecture imp of pl330_dma_fifo is + signal request_data : Boolean; + + type state_type is (IDLE, REQUEST, WAITING, FLUSH); + signal state : state_type; + signal i_in_ack : std_logic; + signal i_out_stb : std_logic; +begin + + in_ack <= i_in_ack; + out_stb <= i_out_stb; + + fifo: entity dma_fifo + generic map ( + RAM_ADDR_WIDTH => RAM_ADDR_WIDTH, + FIFO_DWIDTH => FIFO_DWIDTH + ) + port map ( + clk => clk, + resetn => resetn, + fifo_reset => fifo_reset, + in_stb => in_stb, + in_ack => i_in_ack, + in_data => in_data, + out_stb => i_out_stb, + out_ack => out_ack, + out_data => out_data + ); + + request_data <= i_in_ack = '1' when FIFO_DIRECTION = 0 else i_out_stb = '1'; + + drlast <= '0'; + daready <= '1'; + + drvalid <= '1' when (state = REQUEST) or (state = FLUSH) else '0'; + drtype <= "00" when state = REQUEST else "10"; + + DBG(0) <= davalid; + DBG(2 downto 1) <= datype; + DBG(3) <= '1' when request_data else '0'; + + process (state) + begin + case state is + when IDLE => DBG(5 downto 4) <= "00"; + when REQUEST => DBG(5 downto 4) <= "01"; + when WAITING => DBG(5 downto 4) <= "10"; + when FLUSH => DBG(5 downto 4) <= "11"; + end case; + end process; + + pl330_req_fsm: process (dclk) is + begin + if rising_edge(dclk) then + if dresetn = '0' then + state <= IDLE; + else + -- The controller may send a FLUSH request at any time and it won't + -- respond to any of our requests until we've ack the FLUSH request. + -- The FLUSH request is also supposed to reset our state machine, so + -- go back to idle after having acked the FLUSH. + if davalid = '1' and datype = "10" then + state <= FLUSH; + else + case state is + -- Nothing to do, wait for the fifo to run empty + when IDLE => + if request_data and enable then + state <= REQUEST; + end if; + -- Send out a request to the PL330 + when REQUEST => + if drready = '1' then + state <= WAITING; + end if; + -- Wait for a ACK from the PL330 that it did transfer the data + when WAITING => + if fifo_reset = '1' then + state <= IDLE; + elsif davalid = '1' then + if datype = "00" then + state <= IDLE; + end if; + end if; + -- Send out an ACK for the flush + when FLUSH => + if drready = '1' then + state <= IDLE; + end if; + end case; + end if; + end if; + end if; + end process; +end; diff --git a/adi_library/common/tb/ad_mux_tb b/adi_library/common/tb/ad_mux_tb new file mode 100755 index 00000000..e707994b --- /dev/null +++ b/adi_library/common/tb/ad_mux_tb @@ -0,0 +1,8 @@ +#!/bin/bash + +SOURCE="ad_mux_tb.v" +SOURCE+=" ../ad_mux.v" +SOURCE+=" ../ad_mux_core.v" + +cd `dirname $0` +source run_tb.sh diff --git a/adi_library/common/tb/ad_mux_tb.v b/adi_library/common/tb/ad_mux_tb.v new file mode 100644 index 00000000..08e13158 --- /dev/null +++ b/adi_library/common/tb/ad_mux_tb.v @@ -0,0 +1,105 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_mux_tb; + parameter VCD_FILE = "ad_mux_tb.vcd"; + + parameter CH_W = 16; // Width of input channel + parameter CH_CNT = 64; // Number of input channels + parameter REQ_MUX_SZ = 8; // Size of mux which acts as a building block + parameter EN_REG = 1; // Enable register at output of each mux + + localparam MUX_SZ = CH_CNT < REQ_MUX_SZ ? CH_CNT : REQ_MUX_SZ; + localparam NUM_STAGES = $clog2(CH_CNT) / $clog2(MUX_SZ) + |($clog2(CH_CNT) % $clog2(MUX_SZ)); + localparam DW = CH_W*CH_CNT; + + `include "tb_base.v" + + reg [CH_W*CH_CNT-1:0] data_in = 'h0; + reg [$clog2(CH_CNT)-1:0] ch_sel = 'h0; + wire [CH_W-1:0] data_out; + + ad_mux #( + .CH_W(CH_W), + .CH_CNT(CH_CNT), + .REQ_MUX_SZ(REQ_MUX_SZ), + .EN_REG(EN_REG) + ) DUT ( + .clk(clk), + .data_in(data_in), + .ch_sel(ch_sel), + .data_out(data_out)); + + wire [CH_W-1:0] ref_data; + generate + if (EN_REG) begin + integer ii; + reg [CH_W*CH_CNT-1:0] mux_pln [1:NUM_STAGES]; + always @(posedge clk) begin + mux_pln[1] <= data_in >> ch_sel*CH_W; + for (ii=2; ii<=NUM_STAGES; ii=ii+1) begin + mux_pln[ii] <= mux_pln[ii-1]; + end + end + assign ref_data = mux_pln[NUM_STAGES]; + end else begin + assign ref_data = data_in >> ch_sel*CH_W; + end + endgenerate + + integer i; + initial begin + for (i=0; i +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_pack_tb; + parameter VCD_FILE = "ad_pack_tb.vcd"; + + parameter I_W = 4; // Width of input channel + parameter O_W = 6; // Width of output channel + parameter UNIT_W = 8; + parameter VECT_W = 1024*8; // Multiple of 8 + + `include "tb_base.v" + + reg [I_W*UNIT_W-1 : 0] idata; + wire [O_W*UNIT_W-1 : 0] odata; + reg ivalid = 'b0; + reg [VECT_W-1:0] input_vector; + reg [VECT_W-1:0] output_vector; + + integer i=0; + integer j=0; + + ad_pack #( + .I_W(I_W), + .O_W(O_W), + .UNIT_W(UNIT_W) + ) DUT ( + .clk(clk), + .reset(reset), + .idata(idata), + .ivalid(ivalid), + .odata(odata), + .ovalid(ovalid)); + + task test(input random_n); + begin + @(posedge clk); + i = 0; + j = 0; + while (i < (VECT_W/(I_W*UNIT_W) + (VECT_W%(I_W*UNIT_W)>0))) begin + @(posedge clk); + if ($urandom % 2 == 0 | random_n) begin + idata <= input_vector[i*(I_W*UNIT_W) +: (I_W*UNIT_W)]; + ivalid <= 1'b1; + i = i + 1; + end else begin + idata <= 'bx; + ivalid <= 1'b0; + end + end + @(posedge clk); + idata <= 'bx; + ivalid <= 1'b0; + + // Check output vector + repeat (20) @(posedge clk); + for (i=0; i<(VECT_W/(O_W*UNIT_W))*(O_W*UNIT_W)/8; i=i+1) begin + if (input_vector[i*8+:8] !== output_vector[i*8+:8]) begin + failed <= 1'b1; + $display("i=%d Expected=%x Found=%x",i,input_vector[i*8+:8],output_vector[i*8+:8]); + end + end + // Clear output vector + for (i=0; i +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_upack_tb; + parameter VCD_FILE = "ad_upack_tb.vcd"; + + parameter I_W = 6; // Width of input channel + parameter O_W = 4; // Width of output channel + parameter UNIT_W = 8; + parameter VECT_W = 1024*8; // Multiple of 8 + + `include "tb_base.v" + + reg [I_W*UNIT_W-1 : 0] idata; + wire [O_W*UNIT_W-1 : 0] odata; + reg ivalid = 'b0; + reg [VECT_W-1:0] input_vector; + reg [VECT_W-1:0] output_vector; + + integer i=0; + integer j=0; + + ad_upack #( + .I_W(I_W), + .O_W(O_W), + .UNIT_W(UNIT_W) + ) DUT ( + .clk(clk), + .reset(reset), + .idata(idata), + .iready(iready), + .ivalid(ivalid), + .odata(odata), + .ovalid(ovalid)); + + task test(input no_random); + begin + @(posedge clk); + i = 0; + j = 0; + while (i < VECT_W/(I_W*UNIT_W)) begin + @(posedge clk); + if (iready & (($urandom % 2 == 0) | no_random)) begin + idata <= input_vector[i*(I_W*UNIT_W) +: (I_W*UNIT_W)]; + ivalid <= 1'b1; + i = i + 1; + end else begin + idata <= 'bx; + ivalid <= 1'b0; + end + end + @(posedge clk); + idata <= 'bx; + ivalid <= 1'b0; + + // Check output vector + repeat (20) @(posedge clk); + for (i=0; i<(((VECT_W/(I_W*UNIT_W))*(I_W*UNIT_W))/(O_W*UNIT_W))*(O_W*UNIT_W)/8; i=i+1) begin + if (input_vector[i*8+:8] !== output_vector[i*8+:8]) begin + failed <= 1'b1; + $display("i=%d Expected=%x Found=%x",i,input_vector[i*8+:8],output_vector[i*8+:8]); + end + end + end + endtask + + initial begin + + @(negedge reset); + + // Test with incremental data + for (i=0; i" > $xmlFile +echo -e "" >> $xmlFile +echo -e "\t" >> $xmlFile +if [[ "$ERRS" ]]; then + #replace < with < and > with > in ERRS to not broke created xml + ERRS=$(echo $ERRS | sed 's//>/g') + echo -e "\t\t\n\"$ERRS\"\n\t\t" >> $xmlFile +elif [[ "$SUCCESS" ]]; then + echo -e "\t\t" >> $xmlFile +else #There is no error or 'SUCCESS' keyword in log file - set result to 'Skipped' + echo -e "" >> $xmlFile + echo -e "\tThe log file does not contain any errors or 'SUCCESS' keyword." >> $xmlFile + echo -e "\tLog file was not created properly or the testbench is not automated" >> $xmlFile + echo -e "" >> $xmlFile +fi +echo -e "\t" >> $xmlFile +echo "" >> $xmlFile diff --git a/adi_library/common/tb/run_tb.sh b/adi_library/common/tb/run_tb.sh new file mode 100644 index 00000000..9812dd1d --- /dev/null +++ b/adi_library/common/tb/run_tb.sh @@ -0,0 +1,49 @@ +############################################################################## +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: BSD-1-Clause +############################################################################## + +export NAME=`basename $0` + +# MODE not defined or defined to something else than 'batch' +if [[ -z ${MODE+x} ]] || [[ ! "$MODE" =~ "batch" ]]; then MODE="gui";fi +MODE="-"${MODE##*-} #remove any eventual extra dashes + +case "$SIMULATOR" in + modelsim) + # ModelSim flow + vlib work + vlog ${SOURCE} || exit 1 + vsim ${NAME} -do "add log /* -r; run -a" $MODE -logfile ${NAME}_modelsim.log || exit 1 + ;; + + xsim) + # XSim flow + xvlog -log ${NAME}_xvlog.log --sourcelibdir . ${SOURCE} || exit 1 + xelab -log ${NAME}_xelab.log -debug all ${NAME} || exit 1 + if [[ "$MODE" == "-gui" ]]; then + echo "log_wave -r *" > xsim_gui_cmd.tcl + echo "run all" >> xsim_gui_cmd.tcl + xsim work.${NAME} -gui -tclbatch xsim_gui_cmd.tcl -log ${NAME}_xsim.log + else + xsim work.${NAME} -R -log ${NAME}_xsim.log + fi + ;; + + xcelium) + # Xcelium flow + xmvlog -NOWARN NONPRT ${SOURCE} || exit 1 + xmelab -access +rc ${NAME} + xmsim ${NAME} -gui || exit 1 + ;; + + *) + #Icarus flow is the default + mkdir -p run + mkdir -p vcd + iverilog -o run/run_${NAME} -I.. ${SOURCE} $1 || exit 1 + cd vcd + ../run/run_${NAME} + ;; +esac + diff --git a/adi_library/common/tb/tb_base.v b/adi_library/common/tb/tb_base.v new file mode 100644 index 00000000..18ff6693 --- /dev/null +++ b/adi_library/common/tb/tb_base.v @@ -0,0 +1,75 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + + reg clk = 1'b0; + reg [3:0] reset_shift = 4'b1111; + reg trigger_reset = 1'b0; + wire reset; + + reg failed = 1'b0; + + initial + begin + $dumpfile (VCD_FILE); + $dumpvars; +`ifdef TIMEOUT + #`TIMEOUT +`else + #100000 +`endif + if (failed == 1'b0) + $display("SUCCESS"); + else + $display("FAILED"); + $finish; + end + + always @(*) #10 clk <= ~clk; + always @(posedge clk) begin + if (trigger_reset == 1'b1) begin + reset_shift <= 3'b111; + end else begin + reset_shift <= {reset_shift[2:0],1'b0}; + end + end + + assign reset = reset_shift[3]; + + task do_trigger_reset; + begin + @(posedge clk) trigger_reset <= 1'b1; + @(posedge clk) trigger_reset <= 1'b0; + end + endtask diff --git a/adi_library/common/up_adc_channel.v b/adi_library/common/up_adc_channel.v new file mode 100644 index 00000000..f38c6045 --- /dev/null +++ b/adi_library/common/up_adc_channel.v @@ -0,0 +1,532 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module up_adc_channel #( + + // parameters + + parameter COMMON_ID = 6'h01, + parameter CHANNEL_ID = 4'h0, + parameter USERPORTS_DISABLE = 0, + parameter DATAFORMAT_DISABLE = 0, + parameter DCFILTER_DISABLE = 0, + parameter IQCORRECTION_DISABLE = 0 +) ( + + // adc interface + + input adc_clk, + input adc_rst, + output adc_enable, + output adc_iqcor_enb, + output adc_dcfilt_enb, + output adc_dfmt_se, + output adc_dfmt_type, + output adc_dfmt_enable, + output [15:0] adc_dcfilt_offset, + output [15:0] adc_dcfilt_coeff, + output [15:0] adc_iqcor_coeff_1, + output [15:0] adc_iqcor_coeff_2, + output [ 3:0] adc_pnseq_sel, + output [ 3:0] adc_data_sel, + input adc_pn_err, + input adc_pn_oos, + input adc_or, + input [31:0] adc_read_data, + input [ 7:0] adc_status_header, + input adc_crc_err, + output [ 2:0] adc_softspan, + output up_adc_crc_err, + output up_adc_pn_err, + output up_adc_pn_oos, + output up_adc_or, + + // user controls + + output up_usr_datatype_be, + output up_usr_datatype_signed, + output [ 7:0] up_usr_datatype_shift, + output [ 7:0] up_usr_datatype_total_bits, + output [ 7:0] up_usr_datatype_bits, + output [15:0] up_usr_decimation_m, + output [15:0] up_usr_decimation_n, + input adc_usr_datatype_be, + input adc_usr_datatype_signed, + input [ 7:0] adc_usr_datatype_shift, + input [ 7:0] adc_usr_datatype_total_bits, + input [ 7:0] adc_usr_datatype_bits, + input [15:0] adc_usr_decimation_m, + input [15:0] adc_usr_decimation_n, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // internal registers + + reg up_wack_int = 'd0; + reg up_adc_lb_enb = 'd0; + reg up_adc_pn_sel = 'd0; + reg up_adc_iqcor_enb = 'd0; + reg up_adc_dcfilt_enb = 'd0; + reg up_adc_dfmt_se = 'd0; + reg up_adc_dfmt_type = 'd0; + reg up_adc_dfmt_enable = 'd0; + reg up_adc_pn_type = 'd0; + reg up_adc_enable = 'd0; + reg up_adc_crc_err_int = 'd0; + reg up_adc_pn_err_int = 'd0; + reg up_adc_pn_oos_int = 'd0; + reg up_adc_or_int = 'd0; + reg [15:0] up_adc_dcfilt_offset = 'd0; + reg [15:0] up_adc_dcfilt_coeff = 'd0; + reg [15:0] up_adc_iqcor_coeff_1 = 'd0; + reg [15:0] up_adc_iqcor_coeff_2 = 'd0; + reg [ 3:0] up_adc_pnseq_sel = 'd0; + reg [ 3:0] up_adc_data_sel = 'd0; + reg up_usr_datatype_be_int = 'd0; + reg up_usr_datatype_signed_int = 'd0; + reg [ 7:0] up_usr_datatype_shift_int = 'd0; + reg [ 7:0] up_usr_datatype_total_bits_int = 'd0; + reg [ 7:0] up_usr_datatype_bits_int = 'd0; + reg [15:0] up_usr_decimation_m_int = 'd0; + reg [15:0] up_usr_decimation_n_int = 'd0; + reg up_rack_int = 'd0; + reg [31:0] up_rdata_int = 'd0; + reg [15:0] up_adc_iqcor_coeff_tc_1 = 'd0; + reg [15:0] up_adc_iqcor_coeff_tc_2 = 'd0; + reg [ 3:0] up_adc_pnseq_sel_m = 'd0; + reg [ 3:0] up_adc_data_sel_m = 'd0; + reg [ 2:0] up_adc_softspan_int = 3'h7; + + // internal signals + + wire up_wreq_s; + wire up_rreq_s; + wire up_adc_crc_err_s; + wire up_adc_pn_err_s; + wire up_adc_pn_oos_s; + wire up_adc_or_s; + wire [31:0] up_adc_read_data_s; + wire [ 7:0] up_adc_status_header_s; + wire [ 2:0] up_adc_softspan_s; + + // 2's complement function + + function [15:0] sm2tc; + input [15:0] din; + reg [15:0] dp; + reg [15:0] dn; + reg [15:0] dout; + begin + dp = {1'b0, din[14:0]}; + dn = ~dp + 1'b1; + dout = (din[15] == 1'b1) ? dn : dp; + sm2tc = dout; + end + endfunction + + // up control/status + assign up_adc_crc_err = up_adc_crc_err_int; + assign up_adc_pn_err = up_adc_pn_err_int; + assign up_adc_pn_oos = up_adc_pn_oos_int; + assign up_adc_or = up_adc_or_int; + assign up_usr_datatype_be = up_usr_datatype_be_int; + assign up_usr_datatype_signed = up_usr_datatype_signed_int; + assign up_usr_datatype_shift = up_usr_datatype_shift_int; + assign up_usr_datatype_total_bits = up_usr_datatype_total_bits_int; + assign up_usr_datatype_bits = up_usr_datatype_bits_int; + assign up_usr_decimation_m = up_usr_decimation_m_int; + assign up_usr_decimation_n = up_usr_decimation_n_int; + assign up_adc_softspan_s = up_adc_softspan_int; + + // decode block select + + assign up_wreq_s = ((up_waddr[13:8] == COMMON_ID) && (up_waddr[7:4] == CHANNEL_ID)) ? up_wreq : 1'b0; + assign up_rreq_s = ((up_raddr[13:8] == COMMON_ID) && (up_raddr[7:4] == CHANNEL_ID)) ? up_rreq : 1'b0; + + // processor write interface + + assign up_wack = up_wack_int; + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_wack_int <= 'd0; + up_adc_lb_enb <= 'd0; + up_adc_pn_sel <= 'd0; + end else begin + up_wack_int <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin + up_adc_lb_enb <= up_wdata[11]; + up_adc_pn_sel <= up_wdata[10]; + end + end + end + + generate + if (IQCORRECTION_DISABLE == 1) begin + always @(posedge up_clk) begin + up_adc_iqcor_enb <= 'd0; + end + end else begin + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_iqcor_enb <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin + up_adc_iqcor_enb <= up_wdata[9]; + end + end + end + end + endgenerate + + generate + if (DCFILTER_DISABLE == 1) begin + always @(posedge up_clk) begin + up_adc_dcfilt_enb <= 'd0; + end + end else begin + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_dcfilt_enb <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin + up_adc_dcfilt_enb <= up_wdata[8]; + end + end + end + end + endgenerate + + generate + if (DATAFORMAT_DISABLE == 1) begin + always @(posedge up_clk) begin + up_adc_dfmt_se <= 'd0; + up_adc_dfmt_type <= 'd0; + up_adc_dfmt_enable <= 'd0; + end + end else begin + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_dfmt_se <= 'd0; + up_adc_dfmt_type <= 'd0; + up_adc_dfmt_enable <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin + up_adc_dfmt_se <= up_wdata[6]; + up_adc_dfmt_type <= up_wdata[5]; + up_adc_dfmt_enable <= up_wdata[4]; + end + end + end + end + endgenerate + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_pn_type <= 'd0; + up_adc_enable <= 'd0; + up_adc_crc_err_int <= 'd0; + up_adc_pn_err_int <= 'd0; + up_adc_pn_oos_int <= 'd0; + up_adc_or_int <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin + up_adc_pn_type <= up_wdata[1]; + up_adc_enable <= up_wdata[0]; + end + if (up_adc_crc_err_s == 1'b1) begin + up_adc_crc_err_int <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin + up_adc_crc_err_int <= up_adc_crc_err_int & ~up_wdata[12]; + end + if (up_adc_pn_err_s == 1'b1) begin + up_adc_pn_err_int <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin + up_adc_pn_err_int <= up_adc_pn_err_int & ~up_wdata[2]; + end + if (up_adc_pn_oos_s == 1'b1) begin + up_adc_pn_oos_int <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin + up_adc_pn_oos_int <= up_adc_pn_oos_int & ~up_wdata[1]; + end + if (up_adc_or_s == 1'b1) begin + up_adc_or_int <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin + up_adc_or_int <= up_adc_or_int & ~up_wdata[0]; + end + end + end + + generate + if (DCFILTER_DISABLE == 1) begin + always @(posedge up_clk) begin + up_adc_dcfilt_offset <= 'd0; + up_adc_dcfilt_coeff <= 'd0; + end + end else begin + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_dcfilt_offset <= 'd0; + up_adc_dcfilt_coeff <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h4)) begin + up_adc_dcfilt_offset <= up_wdata[31:16]; + up_adc_dcfilt_coeff <= up_wdata[15:0]; + end + end + end + end + endgenerate + + generate + if (IQCORRECTION_DISABLE == 1) begin + always @(posedge up_clk) begin + up_adc_iqcor_coeff_1 <= 'd0; + up_adc_iqcor_coeff_2 <= 'd0; + end + end else begin + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_iqcor_coeff_1 <= 'd0; + up_adc_iqcor_coeff_2 <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h5)) begin + up_adc_iqcor_coeff_1 <= up_wdata[31:16]; + up_adc_iqcor_coeff_2 <= up_wdata[15:0]; + end + end + end + end + endgenerate + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_pnseq_sel <= 'd0; + up_adc_data_sel <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h6)) begin + up_adc_pnseq_sel <= up_wdata[19:16]; + up_adc_data_sel <= up_wdata[3:0]; + end + end + end + + generate + if (USERPORTS_DISABLE == 1) begin + always @(posedge up_clk) begin + up_usr_datatype_be_int <= 'd0; + up_usr_datatype_signed_int <= 'd0; + up_usr_datatype_shift_int <= 'd0; + up_usr_datatype_total_bits_int <= 'd0; + up_usr_datatype_bits_int <= 'd0; + up_usr_decimation_m_int <= 'd0; + up_usr_decimation_n_int <= 'd0; + end + end else begin + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_usr_datatype_be_int <= 'd0; + up_usr_datatype_signed_int <= 'd0; + up_usr_datatype_shift_int <= 'd0; + up_usr_datatype_total_bits_int <= 'd0; + up_usr_datatype_bits_int <= 'd0; + up_usr_decimation_m_int <= 'd0; + up_usr_decimation_n_int <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h8)) begin + up_usr_datatype_be_int <= up_wdata[25]; + up_usr_datatype_signed_int <= up_wdata[24]; + up_usr_datatype_shift_int <= up_wdata[23:16]; + up_usr_datatype_total_bits_int <= up_wdata[15:8]; + up_usr_datatype_bits_int <= up_wdata[7:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h9)) begin + up_usr_decimation_m_int <= up_wdata[31:16]; + up_usr_decimation_n_int <= up_wdata[15:0]; + end + end + end + end + endgenerate + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_softspan_int <= 3'd7; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'hA)) begin + up_adc_softspan_int <= up_wdata[2:0]; + end + end + end + + // processor read interface + + assign up_rack = up_rack_int; + assign up_rdata = up_rdata_int; + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_rack_int <= 'd0; + up_rdata_int <= 'd0; + end else begin + up_rack_int <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[3:0]) + 4'h0: up_rdata_int <= { 20'd0, up_adc_lb_enb, up_adc_pn_sel, + up_adc_iqcor_enb, up_adc_dcfilt_enb, + 1'd0, up_adc_dfmt_se, up_adc_dfmt_type, up_adc_dfmt_enable, + 2'd0, up_adc_pn_type, up_adc_enable}; + 4'h1: up_rdata_int <= { 19'd0, up_adc_crc_err_int, up_adc_status_header_s, 1'd0, up_adc_pn_err_int, up_adc_pn_oos_int, up_adc_or_int}; + 4'h2: up_rdata_int <= { up_adc_read_data_s}; + 4'h4: up_rdata_int <= { up_adc_dcfilt_offset, up_adc_dcfilt_coeff}; + 4'h5: up_rdata_int <= { up_adc_iqcor_coeff_1, up_adc_iqcor_coeff_2}; + 4'h6: up_rdata_int <= { 12'd0, up_adc_pnseq_sel, 12'd0, up_adc_data_sel}; + 4'h8: up_rdata_int <= { 6'd0, adc_usr_datatype_be, adc_usr_datatype_signed, + adc_usr_datatype_shift, adc_usr_datatype_total_bits, + adc_usr_datatype_bits}; + 4'h9: up_rdata_int <= { adc_usr_decimation_m, adc_usr_decimation_n}; + 4'hA: up_rdata_int <= { 29'd0, up_adc_softspan_int}; + default: up_rdata_int <= 0; + endcase + end else begin + up_rdata_int <= 32'd0; + end + end + end + + // change coefficients to 2's complements + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_iqcor_coeff_tc_1 <= 16'd0; + up_adc_iqcor_coeff_tc_2 <= 16'd0; + end else begin + up_adc_iqcor_coeff_tc_1 <= sm2tc(up_adc_iqcor_coeff_1); + up_adc_iqcor_coeff_tc_2 <= sm2tc(up_adc_iqcor_coeff_2); + end + end + + // data/pn sources + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_pnseq_sel_m <= 4'd0; + up_adc_data_sel_m <= 4'd0; + end else begin + case ({up_adc_pn_type, up_adc_pn_sel}) + 2'b10: up_adc_pnseq_sel_m <= 4'h1; + 2'b01: up_adc_pnseq_sel_m <= 4'h9; + default: up_adc_pnseq_sel_m <= up_adc_pnseq_sel; + endcase + if (up_adc_lb_enb == 1'b1) begin + up_adc_data_sel_m <= 4'h1; + end else begin + up_adc_data_sel_m <= up_adc_data_sel; + end + end + end + + // adc control & status + + up_xfer_cntrl #( + .DATA_WIDTH(81) + ) i_xfer_cntrl ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_cntrl ({ up_adc_iqcor_enb, + up_adc_dcfilt_enb, + up_adc_dfmt_se, + up_adc_dfmt_type, + up_adc_dfmt_enable, + up_adc_enable, + up_adc_dcfilt_offset, + up_adc_dcfilt_coeff, + up_adc_iqcor_coeff_tc_1, + up_adc_iqcor_coeff_tc_2, + up_adc_pnseq_sel_m, + up_adc_data_sel_m, + up_adc_softspan_s}), + .up_xfer_done (), + .d_rst (adc_rst), + .d_clk (adc_clk), + .d_data_cntrl ({ adc_iqcor_enb, + adc_dcfilt_enb, + adc_dfmt_se, + adc_dfmt_type, + adc_dfmt_enable, + adc_enable, + adc_dcfilt_offset, + adc_dcfilt_coeff, + adc_iqcor_coeff_1, + adc_iqcor_coeff_2, + adc_pnseq_sel, + adc_data_sel, + adc_softspan})); + + up_xfer_status #( + .DATA_WIDTH(44) + ) i_xfer_status ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_status ({up_adc_status_header_s, + up_adc_crc_err_s, + up_adc_pn_err_s, + up_adc_pn_oos_s, + up_adc_or_s, + up_adc_read_data_s}), + .d_rst (adc_rst), + .d_clk (adc_clk), + .d_data_status ({ adc_status_header, + adc_crc_err, + adc_pn_err, + adc_pn_oos, + adc_or, + adc_read_data})); + +endmodule diff --git a/adi_library/common/up_adc_common.v b/adi_library/common/up_adc_common.v new file mode 100644 index 00000000..7479f2b7 --- /dev/null +++ b/adi_library/common/up_adc_common.v @@ -0,0 +1,607 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module up_adc_common #( + + // parameters + + parameter ID = 0, + parameter [ 7:0] FPGA_TECHNOLOGY = 0, + parameter [ 7:0] FPGA_FAMILY = 0, + parameter [ 7:0] SPEED_GRADE = 0, + parameter [ 7:0] DEV_PACKAGE = 0, + parameter CONFIG = 0, + parameter COMMON_ID = 6'h00, + parameter DRP_DISABLE = 0, + parameter USERPORTS_DISABLE = 0, + parameter GPIO_DISABLE = 0, + parameter START_CODE_DISABLE = 0 +) ( + + // clock reset + + output mmcm_rst, + + // adc interface + + input adc_clk, + output adc_rst, + output adc_r1_mode, + output adc_ddr_edgesel, + output adc_pin_mode, + input adc_status, + input adc_sync_status, + input adc_status_ovf, + input [31:0] adc_clk_ratio, + output [31:0] adc_start_code, + output adc_sref_sync, + output adc_sync, + output adc_ext_sync_arm, + output adc_ext_sync_disarm, + output adc_ext_sync_manual_req, + output [4:0] adc_num_lanes, + output [7:0] adc_custom_control, + output adc_crc_enable, + output adc_sdr_ddr_n, + output adc_symb_op, + output adc_symb_8_16b, + input [31:0] up_pps_rcounter, + input up_pps_status, + output reg up_pps_irq_mask, + output reg up_adc_r1_mode = 'd0, + + // channel interface + + output up_adc_ce, + input up_status_pn_err, + input up_status_pn_oos, + input up_status_or, + + // drp interface + + output up_drp_sel, + output up_drp_wr, + output [11:0] up_drp_addr, + output [31:0] up_drp_wdata, + input [31:0] up_drp_rdata, + input up_drp_ready, + input up_drp_locked, + + // ADC custom read/write interface + + output [31:0] adc_config_wr, + output [31:0] adc_config_ctrl, + input [31:0] adc_config_rd, + input adc_ctrl_status, + + // user channel control + + output [ 7:0] up_usr_chanmax_out, + input [ 7:0] up_usr_chanmax_in, + input [31:0] up_adc_gpio_in, + output [31:0] up_adc_gpio_out, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // parameters + + localparam VERSION = 32'h000a0300; + + // internal registers + + reg up_adc_clk_enb_int = 'd1; + reg up_core_preset = 'd1; + reg up_mmcm_preset = 'd1; + reg up_wack_int = 'd0; + reg [31:0] up_scratch = 'd0; + reg up_adc_clk_enb = 'd0; + reg up_mmcm_resetn = 'd0; + reg up_resetn = 'd0; + reg up_adc_sync = 'd0; + reg up_adc_ext_sync_arm = 'd0; + reg up_adc_ext_sync_disarm = 'd0; + reg up_adc_ext_sync_manual_req = 'd0; + reg up_adc_sref_sync = 'd0; + reg [4:0] up_adc_num_lanes = 'd0; + reg up_adc_sdr_ddr_n = 'd0; + reg up_adc_symb_op = 'd0; + reg up_adc_symb_8_16b = 'd0; + reg up_adc_ddr_edgesel = 'd0; + reg up_adc_pin_mode = 'd0; + reg up_status_ovf = 'd0; + reg [ 7:0] up_usr_chanmax_int = 'd0; + reg [31:0] up_adc_start_code = 'd0; + reg [31:0] up_adc_gpio_out_int = 'd0; + reg [31:0] up_timer = 'd0; + reg up_rack_int = 'd0; + reg [31:0] up_rdata_int = 'd0; + reg [ 7:0] up_adc_custom_control = 'd0; + reg up_adc_crc_enable = 'd0; + reg [31:0] up_adc_config_wr = 'd0; + reg [31:0] up_adc_config_ctrl = 'd0; + + // internal signals + + wire up_wreq_s; + wire up_rreq_s; + wire up_rack_s; + wire up_write_req; + wire up_read_req; + wire up_status_s; + wire up_sync_status_s; + wire up_status_ovf_s; + wire up_cntrl_xfer_done_s; + wire [31:0] up_adc_clk_count_s; + wire up_drp_status_s; + wire up_drp_rwn_s; + wire [31:0] up_drp_rdata_hold_s; + wire [31:0] up_adc_config_rd; + wire up_adc_ctrl_status; + + wire adc_rst_n; + wire adc_rst_s; + + // decode block select + + assign up_wreq_s = (up_waddr[13:7] == {COMMON_ID,1'b0}) ? up_wreq : 1'b0; + assign up_rreq_s = (up_raddr[13:7] == {COMMON_ID,1'b0}) ? up_rreq : 1'b0; + + // processor write interface + + assign up_wack = up_wack_int; + assign up_adc_ce = up_adc_clk_enb_int; + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_clk_enb_int <= 1'd1; + up_core_preset <= 1'd1; + up_mmcm_preset <= 1'd1; + up_wack_int <= 'd0; + up_scratch <= 'd0; + up_adc_clk_enb <= 'd0; + up_mmcm_resetn <= 'd0; + up_resetn <= 'd0; + up_adc_sync <= 'd0; + up_adc_ext_sync_arm <= 'd0; + up_adc_ext_sync_disarm <= 'd0; + up_adc_ext_sync_manual_req <= 'd0; + up_adc_sref_sync <= 'd0; + up_adc_num_lanes <= 'd0; + up_adc_sdr_ddr_n <= 'd0; + up_adc_symb_op <= 'd0; + up_adc_symb_8_16b <= 'd0; + up_adc_r1_mode <= 'd0; + up_adc_ddr_edgesel <= 'd0; + up_adc_pin_mode <= 'd0; + up_pps_irq_mask <= 1'b1; + up_adc_custom_control <= 'd0; + up_adc_crc_enable <= 'd0; + end else begin + up_adc_clk_enb_int <= ~up_adc_clk_enb; + up_core_preset <= ~up_resetn; + up_mmcm_preset <= ~up_mmcm_resetn; + up_wack_int <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h02)) begin + up_scratch <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h04)) begin + up_pps_irq_mask <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h10)) begin + up_adc_clk_enb <= up_wdata[2]; + up_mmcm_resetn <= up_wdata[1]; + up_resetn <= up_wdata[0]; + end + if (up_adc_sync == 1'b1) begin + if (up_cntrl_xfer_done_s == 1'b1) begin + up_adc_sync <= 1'b0; + end + end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h11)) begin + up_adc_sync <= up_wdata[3]; + end + if (up_adc_ext_sync_arm == 1'b1) begin + if (up_cntrl_xfer_done_s == 1'b1) begin + up_adc_ext_sync_arm <= 1'b0; + end + end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h12)) begin + up_adc_ext_sync_arm <= up_wdata[1]; + end + if (up_adc_ext_sync_disarm == 1'b1) begin + if (up_cntrl_xfer_done_s == 1'b1) begin + up_adc_ext_sync_disarm <= 1'b0; + end + end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h12)) begin + up_adc_ext_sync_disarm <= up_wdata[2]; + end + if (up_adc_ext_sync_manual_req == 1'b1) begin + if (up_cntrl_xfer_done_s == 1'b1) begin + up_adc_ext_sync_manual_req <= 1'b0; + end + end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h12)) begin + up_adc_ext_sync_manual_req <= up_wdata[8]; + end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h13)) begin + up_adc_crc_enable <= up_wdata[8]; + up_adc_custom_control <= up_wdata[7:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h11)) begin + up_adc_sdr_ddr_n <= up_wdata[16]; + up_adc_symb_op <= up_wdata[15]; + up_adc_symb_8_16b <= up_wdata[14]; + up_adc_num_lanes <= up_wdata[12:8]; + up_adc_sref_sync <= up_wdata[4]; + up_adc_r1_mode <= up_wdata[2]; + up_adc_ddr_edgesel <= up_wdata[1]; + up_adc_pin_mode <= up_wdata[0]; + end + end + end + + generate + if (DRP_DISABLE == 1) begin + + assign up_drp_sel = 'd0; + assign up_drp_wr = 'd0; + assign up_drp_status_s = 'd0; + assign up_drp_rwn_s = 'd0; + assign up_drp_addr = 'd0; + assign up_drp_wdata = 'd0; + assign up_drp_rdata_hold_s = 'd0; + + end else begin + + reg up_drp_sel_int = 'd0; + reg up_drp_wr_int = 'd0; + reg up_drp_status_int = 'd0; + reg up_drp_rwn_int = 'd0; + reg [11:0] up_drp_addr_int = 'd0; + reg [31:0] up_drp_wdata_int = 'd0; + reg [31:0] up_drp_rdata_hold_int = 'd0; + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_drp_sel_int <= 'd0; + up_drp_wr_int <= 'd0; + up_drp_status_int <= 'd0; + up_drp_rwn_int <= 'd0; + up_drp_addr_int <= 'd0; + up_drp_wdata_int <= 'd0; + up_drp_rdata_hold_int <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h1c)) begin + up_drp_sel_int <= 1'b1; + up_drp_wr_int <= ~up_wdata[28]; + end else begin + up_drp_sel_int <= 1'b0; + up_drp_wr_int <= 1'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h1c)) begin + up_drp_status_int <= 1'b1; + end else if (up_drp_ready == 1'b1) begin + up_drp_status_int <= 1'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h1c)) begin + up_drp_rwn_int <= up_wdata[28]; + up_drp_addr_int <= up_wdata[27:16]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h1e)) begin + up_drp_wdata_int <= up_wdata; + end + if (up_drp_ready == 1'b1) begin + up_drp_rdata_hold_int <= up_drp_rdata; + end + end + end + + assign up_drp_sel = up_drp_sel_int; + assign up_drp_wr = up_drp_wr_int; + assign up_drp_status_s = up_drp_status_int; + assign up_drp_rwn_s = up_drp_rwn_int; + assign up_drp_addr = up_drp_addr_int; + assign up_drp_wdata = up_drp_wdata_int; + assign up_drp_rdata_hold_s = up_drp_rdata_hold_int; + + end + endgenerate + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_config_wr <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h20)) begin + up_adc_config_wr <= up_wdata; + end + end + end + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_config_ctrl <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h23)) begin + up_adc_config_ctrl <= up_wdata; + end + end + end + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_status_ovf <= 'd0; + end else begin + if (up_status_ovf_s == 1'b1) begin + up_status_ovf <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h22)) begin + up_status_ovf <= up_status_ovf & ~up_wdata[2]; + end + end + end + + assign up_usr_chanmax_out = up_usr_chanmax_int; + + generate + if (USERPORTS_DISABLE == 1) begin + always @(posedge up_clk) begin + up_usr_chanmax_int <= 'd0; + end + end else begin + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_usr_chanmax_int <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h28)) begin + up_usr_chanmax_int <= up_wdata[7:0]; + end + end + end + end + endgenerate + + assign up_adc_gpio_out = up_adc_gpio_out_int; + + generate + if (GPIO_DISABLE == 1) begin + always @(posedge up_clk) begin + up_adc_gpio_out_int <= 'd0; + end + end else begin + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_gpio_out_int <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h2f)) begin + up_adc_gpio_out_int <= up_wdata; + end + end + end + end + endgenerate + + generate + if (START_CODE_DISABLE == 1) begin + always @(posedge up_clk) begin + up_adc_start_code <= 'd0; + end + end else begin + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_adc_start_code <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h29)) begin + up_adc_start_code <= up_wdata[31:0]; + end + end + end + end + endgenerate + + // timer with premature termination + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_timer <= 32'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h40)) begin + up_timer <= up_wdata; + end else if (up_timer > 0) begin + up_timer <= up_timer - 1'b1; + end + end + end + + // processor read interface + + assign up_rack = up_rack_int; + assign up_rdata = up_rdata_int; + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_rack_int <= 'd0; + up_rdata_int <= 'd0; + end else begin + up_rack_int <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[6:0]) + 7'h00: up_rdata_int <= VERSION; + 7'h01: up_rdata_int <= ID; + 7'h02: up_rdata_int <= up_scratch; + 7'h03: up_rdata_int <= CONFIG; + 7'h04: up_rdata_int <= {31'b0, up_pps_irq_mask}; + 7'h07: up_rdata_int <= {FPGA_TECHNOLOGY,FPGA_FAMILY,SPEED_GRADE,DEV_PACKAGE}; // [8,8,8,8] + 7'h10: up_rdata_int <= {29'd0, up_adc_clk_enb, up_mmcm_resetn, up_resetn}; + 7'h11: up_rdata_int <= {15'd0, up_adc_sdr_ddr_n, + up_adc_symb_op, up_adc_symb_8_16b, + 1'd0, up_adc_num_lanes, + 3'd0, up_adc_sref_sync, + up_adc_sync, up_adc_r1_mode, up_adc_ddr_edgesel, up_adc_pin_mode}; + 7'h12: up_rdata_int <= {20'd0, + 3'b0, up_adc_ext_sync_manual_req, + 4'b0, + 1'b0, up_adc_ext_sync_disarm, up_adc_ext_sync_arm, 1'b0}; + 7'h13: up_rdata_int <= {23'd0, up_adc_crc_enable, up_adc_custom_control}; + 7'h15: up_rdata_int <= up_adc_clk_count_s; + 7'h16: up_rdata_int <= adc_clk_ratio; + 7'h17: up_rdata_int <= {27'd0, up_adc_ctrl_status, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s}; + 7'h1a: up_rdata_int <= {31'd0, up_sync_status_s}; + 7'h1c: up_rdata_int <= {3'd0, up_drp_rwn_s, up_drp_addr, 16'b0}; + 7'h1d: up_rdata_int <= {14'd0, up_drp_locked, up_drp_status_s, 16'b0}; + 7'h1e: up_rdata_int <= up_drp_wdata; + 7'h1f: up_rdata_int <= up_drp_rdata_hold_s; + 7'h20: up_rdata_int <= up_adc_config_wr; + 7'h21: up_rdata_int <= up_adc_config_rd; + 7'h22: up_rdata_int <= {29'd0, up_status_ovf, 2'b0}; + 7'h23: up_rdata_int <= up_adc_config_ctrl; + 7'h28: up_rdata_int <= {24'd0, up_usr_chanmax_in}; + 7'h29: up_rdata_int <= up_adc_start_code; + 7'h2e: up_rdata_int <= up_adc_gpio_in; + 7'h2f: up_rdata_int <= up_adc_gpio_out_int; + 7'h30: up_rdata_int <= up_pps_rcounter; + 7'h31: up_rdata_int <= {31'b0, up_pps_status}; + 7'h40: up_rdata_int <= up_timer; + default: up_rdata_int <= 0; + endcase + end else begin + up_rdata_int <= 32'd0; + end + end + end + + // resets + + ad_rst i_mmcm_rst_reg ( + .rst_async(up_mmcm_preset), + .clk(up_clk), + .rstn(), + .rst(mmcm_rst)); + + ad_rst i_core_rst_reg ( + .rst_async(up_core_preset), + .clk(adc_clk), + .rstn(), + .rst(adc_rst_s)); + + // adc control & status + + up_xfer_cntrl #( + .DATA_WIDTH(122) + ) i_xfer_cntrl ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_cntrl ({ up_adc_sdr_ddr_n, + up_adc_symb_op, + up_adc_symb_8_16b, + up_adc_num_lanes, + up_adc_custom_control, + up_adc_crc_enable, + up_adc_sref_sync, + up_adc_ext_sync_arm, + up_adc_ext_sync_disarm, + up_adc_ext_sync_manual_req, + up_adc_sync, + up_adc_config_ctrl, + up_adc_config_wr, + up_adc_start_code, + up_adc_r1_mode, + up_adc_ddr_edgesel, + up_adc_pin_mode, + up_resetn}), + .up_xfer_done (up_cntrl_xfer_done_s), + .d_rst (adc_rst_s), + .d_clk (adc_clk), + .d_data_cntrl ({ adc_sdr_ddr_n, + adc_symb_op, + adc_symb_8_16b, + adc_num_lanes, + adc_custom_control, + adc_crc_enable, + adc_sref_sync, + adc_ext_sync_arm, + adc_ext_sync_disarm, + adc_ext_sync_manual_req, + adc_sync, + adc_config_ctrl, + adc_config_wr, + adc_start_code, + adc_r1_mode, + adc_ddr_edgesel, + adc_pin_mode, + adc_rst_n})); + + // De-assert adc_rst together with an updated control set. + // This allows writing the control registers before releasing the reset. + // This is important at start-up when stable set of controls is required. + + assign adc_rst = ~adc_rst_n; + + up_xfer_status #( + .DATA_WIDTH(36) + ) i_xfer_status ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_status ({up_sync_status_s, + up_status_s, + up_status_ovf_s, + up_adc_config_rd, + up_adc_ctrl_status}), + .d_rst (adc_rst_s), + .d_clk (adc_clk), + .d_data_status ({ adc_sync_status, + adc_status, + adc_status_ovf, + adc_config_rd, + adc_ctrl_status})); + + // adc clock monitor + + up_clock_mon i_clock_mon ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_d_count (up_adc_clk_count_s), + .d_rst (adc_rst_s), + .d_clk (adc_clk)); + +endmodule diff --git a/adi_library/common/up_axi.v b/adi_library/common/up_axi.v new file mode 100644 index 00000000..6b071f42 --- /dev/null +++ b/adi_library/common/up_axi.v @@ -0,0 +1,238 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module up_axi #( + + parameter AXI_ADDRESS_WIDTH = 16 +) ( + + // reset and clocks + + input up_rstn, + input up_clk, + + // axi4 interface + + input up_axi_awvalid, + input [(AXI_ADDRESS_WIDTH-1):0] up_axi_awaddr, + output up_axi_awready, + input up_axi_wvalid, + input [31:0] up_axi_wdata, + input [ 3:0] up_axi_wstrb, + output up_axi_wready, + output up_axi_bvalid, + output [ 1:0] up_axi_bresp, + input up_axi_bready, + input up_axi_arvalid, + input [(AXI_ADDRESS_WIDTH-1):0] up_axi_araddr, + output up_axi_arready, + output up_axi_rvalid, + output [ 1:0] up_axi_rresp, + output [31:0] up_axi_rdata, + input up_axi_rready, + + // pcore interface + + output up_wreq, + output [(AXI_ADDRESS_WIDTH-3):0] up_waddr, + output [31:0] up_wdata, + input up_wack, + output up_rreq, + output [(AXI_ADDRESS_WIDTH-3):0] up_raddr, + input [31:0] up_rdata, + input up_rack +); + + // internal registers + + reg up_axi_awready_int = 'd0; + reg up_axi_wready_int = 'd0; + reg up_axi_bvalid_int = 'd0; + reg up_wack_d = 'd0; + reg up_wsel = 'd0; + reg up_wreq_int = 'd0; + reg [(AXI_ADDRESS_WIDTH-3):0] up_waddr_int = 'd0; + reg [31:0] up_wdata_int = 'd0; + reg [ 4:0] up_wcount = 'd0; + reg up_axi_arready_int = 'd0; + reg up_axi_rvalid_int = 'd0; + reg [31:0] up_axi_rdata_int = 'd0; + reg up_rack_d = 'd0; + reg [31:0] up_rdata_d = 'd0; + reg up_rsel = 'd0; + reg up_rreq_int = 'd0; + reg [(AXI_ADDRESS_WIDTH-3):0] up_raddr_int = 'd0; + reg [ 4:0] up_rcount = 'd0; + + // internal signals + + wire up_wack_s; + wire up_rack_s; + wire [31:0] up_rdata_s; + + // write channel interface + + assign up_axi_awready = up_axi_awready_int; + assign up_axi_wready = up_axi_wready_int; + assign up_axi_bvalid = up_axi_bvalid_int; + assign up_axi_bresp = 2'd0; + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_axi_awready_int <= 'd0; + up_axi_wready_int <= 'd0; + up_axi_bvalid_int <= 'd0; + end else begin + if (up_axi_awready_int == 1'b1) begin + up_axi_awready_int <= 1'b0; + end else if (up_wack_s == 1'b1) begin + up_axi_awready_int <= 1'b1; + end + if (up_axi_wready_int == 1'b1) begin + up_axi_wready_int <= 1'b0; + end else if (up_wack_s == 1'b1) begin + up_axi_wready_int <= 1'b1; + end + if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin + up_axi_bvalid_int <= 1'b0; + end else if (up_wack_d == 1'b1) begin + up_axi_bvalid_int <= 1'b1; + end + end + end + + assign up_wreq = up_wreq_int; + assign up_waddr = up_waddr_int; + assign up_wdata = up_wdata_int; + assign up_wack_s = (up_wcount == 5'h1f) ? 1'b1 : (up_wcount[4] & up_wack); + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_wack_d <= 'd0; + up_wsel <= 'd0; + up_wreq_int <= 'd0; + up_waddr_int <= 'd0; + up_wdata_int <= 'd0; + up_wcount <= 'd0; + end else begin + up_wack_d <= up_wack_s; + if (up_wsel == 1'b1) begin + if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin + up_wsel <= 1'b0; + end + up_wreq_int <= 1'b0; + end else begin + up_wsel <= up_axi_awvalid & up_axi_wvalid; + up_wreq_int <= up_axi_awvalid & up_axi_wvalid; + up_waddr_int <= up_axi_awaddr[(AXI_ADDRESS_WIDTH-1):2]; + up_wdata_int <= up_axi_wdata; + end + if (up_wack_s == 1'b1) begin + up_wcount <= 5'h00; + end else if (up_wcount[4] == 1'b1) begin + up_wcount <= up_wcount + 1'b1; + end else if (up_wreq_int == 1'b1) begin + up_wcount <= 5'h10; + end + end + end + + // read channel interface + + assign up_axi_arready = up_axi_arready_int; + assign up_axi_rvalid = up_axi_rvalid_int; + assign up_axi_rdata = up_axi_rdata_int; + assign up_axi_rresp = 2'd0; + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_axi_arready_int <= 'd0; + up_axi_rvalid_int <= 'd0; + up_axi_rdata_int <= 'd0; + end else begin + if (up_axi_arready_int == 1'b1) begin + up_axi_arready_int <= 1'b0; + end else if (up_rack_s == 1'b1) begin + up_axi_arready_int <= 1'b1; + end + if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin + up_axi_rvalid_int <= 1'b0; + up_axi_rdata_int <= 32'd0; + end else if (up_rack_d == 1'b1) begin + up_axi_rvalid_int <= 1'b1; + up_axi_rdata_int <= up_rdata_d; + end + end + end + + assign up_rreq = up_rreq_int; + assign up_raddr = up_raddr_int; + assign up_rack_s = (up_rcount == 5'h1f) ? 1'b1 : (up_rcount[4] & up_rack); + assign up_rdata_s = (up_rcount == 5'h1f) ? {2{16'hdead}} : up_rdata; + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_rack_d <= 'd0; + up_rdata_d <= 'd0; + up_rsel <= 'd0; + up_rreq_int <= 'd0; + up_raddr_int <= 'd0; + up_rcount <= 'd0; + end else begin + up_rack_d <= up_rack_s; + up_rdata_d <= up_rdata_s; + if (up_rsel == 1'b1) begin + if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin + up_rsel <= 1'b0; + end + up_rreq_int <= 1'b0; + end else begin + up_rsel <= up_axi_arvalid; + up_rreq_int <= up_axi_arvalid; + up_raddr_int <= up_axi_araddr[(AXI_ADDRESS_WIDTH-1):2]; + end + if (up_rack_s == 1'b1) begin + up_rcount <= 5'h00; + end else if (up_rcount[4] == 1'b1) begin + up_rcount <= up_rcount + 1'b1; + end else if (up_rreq_int == 1'b1) begin + up_rcount <= 5'h10; + end + end + end + +endmodule diff --git a/adi_library/common/up_clkgen.v b/adi_library/common/up_clkgen.v new file mode 100644 index 00000000..f3f3bfbb --- /dev/null +++ b/adi_library/common/up_clkgen.v @@ -0,0 +1,194 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module up_clkgen #( + + parameter ID = 0, + parameter [ 7:0] FPGA_TECHNOLOGY = 0, + parameter [ 7:0] FPGA_FAMILY = 0, + parameter [ 7:0] SPEED_GRADE = 0, + parameter [ 7:0] DEV_PACKAGE = 0, + parameter [15:0] FPGA_VOLTAGE = 0 +) ( + + // mmcm reset + + output mmcm_rst, + + // clock selection + + output clk_sel, + + // drp interface + + output reg up_drp_sel, + output reg up_drp_wr, + output reg [11:0] up_drp_addr, + output reg [15:0] up_drp_wdata, + input [15:0] up_drp_rdata, + input up_drp_ready, + input up_drp_locked, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack +); + + localparam PCORE_VERSION = 32'h00050063; + + // internal registers + + reg up_mmcm_preset = 'd0; + reg [31:0] up_scratch = 'd0; + reg up_mmcm_resetn = 'd0; + reg up_resetn = 'd0; + reg up_drp_status = 'd0; + reg up_drp_rwn = 'd0; + reg [15:0] up_drp_rdata_hold = 'd0; + reg up_clk_sel = 'd0; + + // internal signals + + wire up_wreq_s; + wire up_rreq_s; + + // decode block select + + assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0; + assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0; + + assign clk_sel = ~up_clk_sel; + + // processor write interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_mmcm_preset <= 1'd1; + up_wack <= 'd0; + up_scratch <= 'd0; + up_mmcm_resetn <= 'd0; + up_resetn <= 'd0; + up_drp_sel <= 'd0; + up_drp_wr <= 'd0; + up_drp_status <= 'd0; + up_drp_rwn <= 'd0; + up_drp_addr <= 'd0; + up_drp_wdata <= 'd0; + up_drp_rdata_hold <= 'd0; + up_clk_sel <= 'd0; + end else begin + up_mmcm_preset <= ~up_mmcm_resetn; + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin + up_scratch <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin + up_mmcm_resetn <= up_wdata[1]; + up_resetn <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin + up_clk_sel <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin + up_drp_sel <= 1'b1; + up_drp_wr <= ~up_wdata[28]; + end else begin + up_drp_sel <= 1'b0; + up_drp_wr <= 1'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin + up_drp_status <= 1'b1; + end else if (up_drp_ready == 1'b1) begin + up_drp_status <= 1'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin + up_drp_rwn <= up_wdata[28]; + up_drp_addr <= up_wdata[27:16]; + up_drp_wdata <= up_wdata[15:0]; + end + if (up_drp_ready == 1'b1) begin + up_drp_rdata_hold <= up_drp_rdata; + end + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[7:0]) + 8'h00: up_rdata <= PCORE_VERSION; + 8'h01: up_rdata <= ID; + 8'h02: up_rdata <= up_scratch; + 8'h07: up_rdata <= {FPGA_TECHNOLOGY,FPGA_FAMILY,SPEED_GRADE,DEV_PACKAGE}; // [8,8,8,8] + 8'h10: up_rdata <= {30'd0, up_mmcm_resetn, up_resetn}; + 8'h11: up_rdata <= {31'd0, up_clk_sel}; + 8'h17: up_rdata <= {31'd0, up_drp_locked}; + 8'h1c: up_rdata <= {3'd0, up_drp_rwn, up_drp_addr, up_drp_wdata}; + 8'h1d: up_rdata <= {14'd0, up_drp_locked, up_drp_status, up_drp_rdata_hold}; + 8'h50: up_rdata <= {16'd0, FPGA_VOLTAGE}; // mV + default: up_rdata <= 0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + // resets + + ad_rst i_mmcm_rst_reg ( + .rst_async(up_mmcm_preset), + .clk(up_clk), + .rstn(), + .rst(mmcm_rst)); + +endmodule diff --git a/adi_library/common/up_clock_mon.v b/adi_library/common/up_clock_mon.v new file mode 100644 index 00000000..5c4c2107 --- /dev/null +++ b/adi_library/common/up_clock_mon.v @@ -0,0 +1,144 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module up_clock_mon #( + parameter TOTAL_WIDTH = 32 +) ( + + // processor interface + + input up_rstn, + input up_clk, + output reg [TOTAL_WIDTH-1:0] up_d_count, + + // device interface + + input d_rst, + input d_clk +); + + // internal registers + + reg [15:0] up_count = 'd1; + reg up_count_run = 'd0; + reg up_count_running_m1 = 'd0; + reg up_count_running_m2 = 'd0; + reg up_count_running_m3 = 'd0; + reg d_count_run_m1 = 'd0; + reg d_count_run_m2 = 'd0; + reg d_count_run_m3 = 'd0; + reg [TOTAL_WIDTH:0] d_count = 'd0; + + // internal signals + + wire up_count_capture_s; + wire d_count_reset_s; + + // processor reference + + // Capture on the falling edge of running + assign up_count_capture_s = up_count_running_m3 == 1'b1 && up_count_running_m2 == 1'b0; + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_count_running_m1 <= 1'b0; + up_count_running_m2 <= 1'b0; + up_count_running_m3 <= 1'b0; + end else begin + up_count_running_m1 <= d_count_run_m3; + up_count_running_m2 <= up_count_running_m1; + up_count_running_m3 <= up_count_running_m2; + end + end + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_d_count <= 'd0; + up_count_run <= 1'b0; + end else begin + if (up_count_running_m3 == 1'b0) begin + up_count_run <= 1'b1; + end else if (up_count == 'h00) begin + up_count_run <= 1'b0; + end + + if (up_count_capture_s == 1'b1) begin + up_d_count <= d_count[TOTAL_WIDTH-1:0]; + end else if (up_count == 'h00 && up_count_run != up_count_running_m3) begin + up_d_count <= 'h00; + end + end + end + + always @(posedge up_clk) begin + if (up_count_run == 1'b0 && up_count_running_m3 == 1'b0) begin + up_count <= 'h01; + end else begin + up_count <= up_count + 1'b1; + end + end + + // device free running + + // Reset on the rising edge of run + assign d_count_reset_s = d_count_run_m3 == 1'b0 && d_count_run_m2 == 1'b1; + + always @(posedge d_clk or posedge d_rst) begin + if (d_rst == 1'b1) begin + d_count_run_m1 <= 1'b0; + d_count_run_m2 <= 1'b0; + d_count_run_m3 <= 1'b0; + end else begin + d_count_run_m1 <= up_count_run; + d_count_run_m2 <= d_count_run_m1; + d_count_run_m3 <= d_count_run_m2; + end + end + + always @(posedge d_clk) begin + if (d_count_reset_s == 1'b1) begin + d_count <= 'h00; + end else if (d_count_run_m3 == 1'b1) begin + if (d_count[TOTAL_WIDTH] == 1'b0) begin + d_count <= d_count + 1'b1; + end else begin + d_count <= {TOTAL_WIDTH+1{1'b1}}; + end + end + end + +endmodule diff --git a/adi_library/common/up_dac_channel.v b/adi_library/common/up_dac_channel.v new file mode 100644 index 00000000..dc02e673 --- /dev/null +++ b/adi_library/common/up_dac_channel.v @@ -0,0 +1,501 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module up_dac_channel #( + + // parameters + + parameter COMMON_ID = 6'h11, + parameter CHANNEL_ID = 4'h0, + parameter CHANNEL_NUMBER = 8'b0, + parameter DDS_DISABLE = 0, + parameter DDS_PHASE_DW = 16, + parameter USERPORTS_DISABLE = 0, + parameter IQCORRECTION_DISABLE = 0, + parameter XBAR_ENABLE = 0 +) ( + + // dac interface + + input dac_clk, + input dac_rst, + output [15:0] dac_dds_scale_1, + output [15:0] dac_dds_scale_2, + output [DDS_PHASE_DW-1:0] dac_dds_init_1, + output [DDS_PHASE_DW-1:0] dac_dds_incr_1, + output [DDS_PHASE_DW-1:0] dac_dds_init_2, + output [DDS_PHASE_DW-1:0] dac_dds_incr_2, + output [15:0] dac_pat_data_1, + output [15:0] dac_pat_data_2, + output [ 3:0] dac_data_sel, + output dac_mask_enable, + output [ 1:0] dac_iq_mode, + output dac_iqcor_enb, + output [15:0] dac_iqcor_coeff_1, + output [15:0] dac_iqcor_coeff_2, + output [7:0] dac_src_chan_sel, + + // user controls + + output up_usr_datatype_be, + output up_usr_datatype_signed, + output [ 7:0] up_usr_datatype_shift, + output [ 7:0] up_usr_datatype_total_bits, + output [ 7:0] up_usr_datatype_bits, + output [15:0] up_usr_interpolation_m, + output [15:0] up_usr_interpolation_n, + input dac_usr_datatype_be, + input dac_usr_datatype_signed, + input [ 7:0] dac_usr_datatype_shift, + input [ 7:0] dac_usr_datatype_total_bits, + input [ 7:0] dac_usr_datatype_bits, + input [15:0] dac_usr_interpolation_m, + input [15:0] dac_usr_interpolation_n, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // internal registers + + reg up_wack_int = 'd0; + reg [15:0] up_dac_dds_scale_1 = 'd0; + reg [15:0] up_dac_dds_init_1 = 'd0; + reg [15:0] up_dac_dds_incr_1 = 'd0; + reg [15:0] up_dac_dds_scale_2 = 'd0; + reg [15:0] up_dac_dds_init_2 = 'd0; + reg [15:0] up_dac_dds_incr_2 = 'd0; + reg [15:0] up_dac_dds_init_1_extend = 'd0; + reg [15:0] up_dac_dds_incr_1_extend = 'd0; + reg [15:0] up_dac_dds_init_2_extend = 'd0; + reg [15:0] up_dac_dds_incr_2_extend = 'd0; + reg [15:0] up_dac_pat_data_2 = 'd0; + reg [15:0] up_dac_pat_data_1 = 'd0; + reg up_dac_iqcor_enb = 'd0; + reg up_dac_lb_enb = 'd0; + reg up_dac_pn_enb = 'd0; + reg [ 3:0] up_dac_data_sel = 'd0; + reg [15:0] up_dac_iqcor_coeff_1 = 'd0; + reg [15:0] up_dac_iqcor_coeff_2 = 'd0; + reg up_usr_datatype_be_int = 'd0; + reg up_usr_datatype_signed_int = 'd0; + reg [ 7:0] up_usr_datatype_shift_int = 'd0; + reg [ 7:0] up_usr_datatype_total_bits_int = 'd0; + reg [ 7:0] up_usr_datatype_bits_int = 'd0; + reg [15:0] up_usr_interpolation_m_int = 'd0; + reg [15:0] up_usr_interpolation_n_int = 'd0; + reg [ 1:0] up_dac_iq_mode = 'd0; + reg up_rack_int = 'd0; + reg [31:0] up_rdata_int = 'd0; + reg [15:0] up_dac_dds_scale_tc_1 = 'd0; + reg [15:0] up_dac_dds_scale_tc_2 = 'd0; + reg [15:0] up_dac_iqcor_coeff_tc_1 = 'd0; + reg [15:0] up_dac_iqcor_coeff_tc_2 = 'd0; + reg [ 3:0] up_dac_data_sel_m = 'd0; + reg [ 7:0] up_dac_src_chan_sel = XBAR_ENABLE ? CHANNEL_NUMBER[7:0] : 8'h0; + reg up_dac_mask_enable = 1'b0; + + // internal signals + + wire up_wreq_s; + wire up_rreq_s; + wire [ 5:0] dds_phase_w = DDS_PHASE_DW[5:0]; + + wire [15:0] dac_dds_init_1_s; + wire [15:0] dac_dds_incr_1_s; + wire [15:0] dac_dds_init_2_s; + wire [15:0] dac_dds_incr_2_s; + wire [15:0] dac_dds_init_1_extend; + wire [15:0] dac_dds_incr_1_extend; + wire [15:0] dac_dds_init_2_extend; + wire [15:0] dac_dds_incr_2_extend; + + // 2's complement function + + function [15:0] sm2tc; + input [15:0] din; + reg [15:0] dp; + reg [15:0] dn; + reg [15:0] dout; + begin + dp = {1'b0, din[14:0]}; + dn = ~dp + 1'b1; + dout = (din[15] == 1'b1) ? dn : dp; + sm2tc = dout; + end + endfunction + + // decode block select + + assign up_wreq_s = ((up_waddr[13:8] == COMMON_ID) && (up_waddr[7:4] == CHANNEL_ID)) ? up_wreq : 1'b0; + assign up_rreq_s = ((up_raddr[13:8] == COMMON_ID) && (up_raddr[7:4] == CHANNEL_ID)) ? up_rreq : 1'b0; + + // processor write interface + + assign up_wack = up_wack_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack_int <= 'd0; + end else begin + up_wack_int <= up_wreq_s; + end + end + + generate + if (DDS_DISABLE == 1) begin + always @(posedge up_clk) begin + up_dac_dds_scale_1 <= 'd0; + up_dac_dds_init_1 <= 'd0; + up_dac_dds_incr_1 <= 'd0; + up_dac_dds_scale_2 <= 'd0; + up_dac_dds_init_2 <= 'd0; + up_dac_dds_incr_2 <= 'd0; + up_dac_dds_init_1_extend <= 'd0; + up_dac_dds_incr_1_extend <= 'd0; + up_dac_dds_init_2_extend <= 'd0; + up_dac_dds_incr_2_extend <= 'd0; + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_dac_dds_scale_1 <= 'd0; + up_dac_dds_init_1 <= 'd0; + up_dac_dds_incr_1 <= 'd0; + up_dac_dds_scale_2 <= 'd0; + up_dac_dds_init_2 <= 'd0; + up_dac_dds_incr_2 <= 'd0; + up_dac_dds_init_1_extend <= 'd0; + up_dac_dds_incr_1_extend <= 'd0; + up_dac_dds_init_2_extend <= 'd0; + up_dac_dds_incr_2_extend <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin + up_dac_dds_scale_1 <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h1)) begin + up_dac_dds_init_1 <= up_wdata[31:16]; + up_dac_dds_incr_1 <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h2)) begin + up_dac_dds_scale_2 <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h3)) begin + up_dac_dds_init_2 <= up_wdata[31:16]; + up_dac_dds_incr_2 <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'hb)) begin + up_dac_dds_init_1_extend <= up_wdata[31:16]; + up_dac_dds_incr_1_extend <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'hc)) begin + up_dac_dds_init_2_extend <= up_wdata[31:16]; + up_dac_dds_incr_2_extend <= up_wdata[15:0]; + end + end + end + end + endgenerate + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_dac_pat_data_2 <= 'd0; + up_dac_pat_data_1 <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h4)) begin + up_dac_pat_data_2 <= up_wdata[31:16]; + up_dac_pat_data_1 <= up_wdata[15:0]; + end + end + end + + generate + if (IQCORRECTION_DISABLE == 1) begin + always @(posedge up_clk) begin + up_dac_iqcor_enb <= 'd0; + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_dac_iqcor_enb <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h5)) begin + up_dac_iqcor_enb <= up_wdata[2]; + end + end + end + end + endgenerate + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_dac_lb_enb <= 'd0; + up_dac_pn_enb <= 'd0; + up_dac_data_sel <= 'd0; + up_dac_src_chan_sel <= XBAR_ENABLE ? CHANNEL_NUMBER[7:0] : 8'h0; + up_dac_mask_enable <= 1'b0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h5)) begin + up_dac_lb_enb <= up_wdata[1]; + up_dac_pn_enb <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h6)) begin + up_dac_data_sel <= up_wdata[3:0]; + up_dac_mask_enable <= XBAR_ENABLE ? up_wdata[16] : 1'b0; + up_dac_src_chan_sel <= XBAR_ENABLE ? up_wdata[15:8] : 8'h0; + end + end + end + + generate + if (IQCORRECTION_DISABLE == 1) begin + always @(posedge up_clk) begin + up_dac_iqcor_coeff_1 <= 'd0; + up_dac_iqcor_coeff_2 <= 'd0; + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_dac_iqcor_coeff_1 <= 'd0; + up_dac_iqcor_coeff_2 <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h7)) begin + up_dac_iqcor_coeff_1 <= up_wdata[31:16]; + up_dac_iqcor_coeff_2 <= up_wdata[15:0]; + end + end + end + end + endgenerate + + assign up_usr_datatype_be = up_usr_datatype_be_int; + assign up_usr_datatype_signed = up_usr_datatype_signed_int; + assign up_usr_datatype_shift = up_usr_datatype_shift_int; + assign up_usr_datatype_total_bits = up_usr_datatype_total_bits_int; + assign up_usr_datatype_bits = up_usr_datatype_bits_int; + assign up_usr_interpolation_m = up_usr_interpolation_m_int; + assign up_usr_interpolation_n = up_usr_interpolation_n_int; + + generate + if (USERPORTS_DISABLE == 1) begin + always @(posedge up_clk) begin + up_usr_datatype_be_int <= 'd0; + up_usr_datatype_signed_int <= 'd0; + up_usr_datatype_shift_int <= 'd0; + up_usr_datatype_total_bits_int <= 'd0; + up_usr_datatype_bits_int <= 'd0; + up_usr_interpolation_m_int <= 'd0; + up_usr_interpolation_n_int <= 'd0; + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_usr_datatype_be_int <= 'd0; + up_usr_datatype_signed_int <= 'd0; + up_usr_datatype_shift_int <= 'd0; + up_usr_datatype_total_bits_int <= 'd0; + up_usr_datatype_bits_int <= 'd0; + up_usr_interpolation_m_int <= 'd0; + up_usr_interpolation_n_int <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h8)) begin + up_usr_datatype_be_int <= up_wdata[25]; + up_usr_datatype_signed_int <= up_wdata[24]; + up_usr_datatype_shift_int <= up_wdata[23:16]; + up_usr_datatype_total_bits_int <= up_wdata[15:8]; + up_usr_datatype_bits_int <= up_wdata[7:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h9)) begin + up_usr_interpolation_m_int <= up_wdata[31:16]; + up_usr_interpolation_n_int <= up_wdata[15:0]; + end + end + end + end + endgenerate + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_dac_iq_mode <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'ha)) begin + up_dac_iq_mode <= up_wdata[1:0]; + end + end + end + + // processor read interface + + assign up_rack = up_rack_int; + assign up_rdata = up_rdata_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack_int <= 'd0; + up_rdata_int <= 'd0; + end else begin + up_rack_int <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[3:0]) + 4'h0: up_rdata_int <= { 10'd0, dds_phase_w, up_dac_dds_scale_1}; + 4'h1: up_rdata_int <= { up_dac_dds_init_1, up_dac_dds_incr_1}; + 4'h2: up_rdata_int <= { 16'd0, up_dac_dds_scale_2}; + 4'h3: up_rdata_int <= { up_dac_dds_init_2, up_dac_dds_incr_2}; + 4'h4: up_rdata_int <= { up_dac_pat_data_2, up_dac_pat_data_1}; + 4'h5: up_rdata_int <= { 29'd0, up_dac_iqcor_enb, up_dac_lb_enb, up_dac_pn_enb}; + 4'h6: up_rdata_int <= { 15'b0, up_dac_mask_enable, up_dac_src_chan_sel, 4'b0, up_dac_data_sel_m}; + 4'h7: up_rdata_int <= { up_dac_iqcor_coeff_1, up_dac_iqcor_coeff_2}; + 4'h8: up_rdata_int <= { 6'd0, dac_usr_datatype_be, dac_usr_datatype_signed, + dac_usr_datatype_shift, dac_usr_datatype_total_bits, + dac_usr_datatype_bits}; + 4'h9: up_rdata_int <= { dac_usr_interpolation_m, dac_usr_interpolation_n}; + 4'ha: up_rdata_int <= { 30'd0, up_dac_iq_mode}; + 4'hb: up_rdata_int <= { up_dac_dds_init_1_extend, up_dac_dds_incr_1_extend}; + 4'hc: up_rdata_int <= { up_dac_dds_init_2_extend, up_dac_dds_incr_2_extend}; + default: up_rdata_int <= 0; + endcase + end else begin + up_rdata_int <= 32'd0; + end + end + end + + // change coefficients to 2's complements + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_dac_dds_scale_tc_1 <= 16'd0; + up_dac_dds_scale_tc_2 <= 16'd0; + up_dac_iqcor_coeff_tc_1 <= 16'd0; + up_dac_iqcor_coeff_tc_2 <= 16'd0; + end else begin + up_dac_dds_scale_tc_1 <= sm2tc(up_dac_dds_scale_1); + up_dac_dds_scale_tc_2 <= sm2tc(up_dac_dds_scale_2); + up_dac_iqcor_coeff_tc_1 <= sm2tc(up_dac_iqcor_coeff_1); + up_dac_iqcor_coeff_tc_2 <= sm2tc(up_dac_iqcor_coeff_2); + end + end + + // backward compatibility + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_dac_data_sel_m <= 4'd0; + end else begin + case ({up_dac_lb_enb, up_dac_pn_enb}) + 2'b10: up_dac_data_sel_m <= 4'h8; + 2'b01: up_dac_data_sel_m <= 4'h9; + default: up_dac_data_sel_m <= up_dac_data_sel; + endcase + end + end + + // dac control & status + + up_xfer_cntrl #( + .DATA_WIDTH(240) + ) i_xfer_cntrl ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_cntrl ({ up_dac_iq_mode, // 2 + up_dac_iqcor_enb, // 1 + up_dac_iqcor_coeff_tc_1, // 16 + up_dac_iqcor_coeff_tc_2, // 16 + up_dac_dds_scale_tc_1, // 16 + up_dac_dds_init_1, // 16 + up_dac_dds_incr_1, // 16 + up_dac_dds_scale_tc_2, // 16 + up_dac_dds_init_2, // 16 + up_dac_dds_incr_2, // 16 + up_dac_dds_init_1_extend, // 16 + up_dac_dds_incr_1_extend, // 16 + up_dac_dds_init_2_extend, // 16 + up_dac_dds_incr_2_extend, // 16 + up_dac_pat_data_1, // 16 + up_dac_pat_data_2, // 16 + up_dac_data_sel_m, // 4 + up_dac_mask_enable, // 1 + up_dac_src_chan_sel}), // 8 + .up_xfer_done (), + .d_rst (dac_rst), + .d_clk (dac_clk), + .d_data_cntrl ({ dac_iq_mode, + dac_iqcor_enb, + dac_iqcor_coeff_1, + dac_iqcor_coeff_2, + dac_dds_scale_1, + dac_dds_init_1_s, + dac_dds_incr_1_s, + dac_dds_scale_2, + dac_dds_init_2_s, + dac_dds_incr_2_s, + dac_dds_init_1_extend, + dac_dds_incr_1_extend, + dac_dds_init_2_extend, + dac_dds_incr_2_extend, + dac_pat_data_1, + dac_pat_data_2, + dac_data_sel, + dac_mask_enable, + dac_src_chan_sel})); + + generate + if (DDS_PHASE_DW > 16) begin + localparam DDS_EXT_DW = DDS_PHASE_DW - 16 - 1; + assign dac_dds_init_1 = {dac_dds_init_1_extend[DDS_EXT_DW:0], dac_dds_init_1_s}; + assign dac_dds_incr_1 = {dac_dds_incr_1_extend[DDS_EXT_DW:0], dac_dds_incr_1_s}; + assign dac_dds_init_2 = {dac_dds_init_2_extend[DDS_EXT_DW:0], dac_dds_init_2_s}; + assign dac_dds_incr_2 = {dac_dds_incr_2_extend[DDS_EXT_DW:0], dac_dds_incr_2_s}; + end else begin + assign dac_dds_init_1 = dac_dds_init_1_s[DDS_PHASE_DW-1:0]; + assign dac_dds_incr_1 = dac_dds_incr_1_s[DDS_PHASE_DW-1:0]; + assign dac_dds_init_2 = dac_dds_init_2_s[DDS_PHASE_DW-1:0]; + assign dac_dds_incr_2 = dac_dds_incr_2_s[DDS_PHASE_DW-1:0]; + end + endgenerate + +endmodule diff --git a/adi_library/common/up_dac_common.v b/adi_library/common/up_dac_common.v new file mode 100644 index 00000000..8053b9ac --- /dev/null +++ b/adi_library/common/up_dac_common.v @@ -0,0 +1,611 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module up_dac_common #( + + // parameters + + parameter ID = 0, + parameter [ 7:0] FPGA_TECHNOLOGY = 0, + parameter [ 7:0] FPGA_FAMILY = 0, + parameter [ 7:0] SPEED_GRADE = 0, + parameter [ 7:0] DEV_PACKAGE = 0, + parameter CONFIG = 0, + parameter [ 0:0] CLK_EDGE_SEL = 1'b0, + parameter COMMON_ID = 6'h10, + parameter DRP_DISABLE = 0, + parameter USERPORTS_DISABLE = 0, + parameter GPIO_DISABLE = 0 +) ( + + // mmcm reset + + output mmcm_rst, + + // dac interface + + input dac_clk, + output dac_rst, + output [4:0] dac_num_lanes, + output dac_sdr_ddr_n, + output dac_symb_op, + output dac_symb_8_16b, + output dac_sync, + output dac_ext_sync_arm, + output dac_ext_sync_disarm, + output dac_ext_sync_manual_req, + output dac_frame, + output dac_clksel, + output dac_par_type, + output dac_par_enb, + output dac_r1_mode, + output dac_datafmt, + output [15:0] dac_datarate, + input dac_status, + input dac_sync_in_status, + input dac_status_unf, + input [31:0] dac_clk_ratio, + output up_dac_ce, + input [31:0] up_pps_rcounter, + input up_pps_status, + output reg up_pps_irq_mask, + output reg up_dac_r1_mode = 'd0, + + // drp interface + + output up_drp_sel, + output up_drp_wr, + output [11:0] up_drp_addr, + output [31:0] up_drp_wdata, + input [31:0] up_drp_rdata, + input up_drp_ready, + input up_drp_locked, + + // DAC custom read/write interface + + output [31:0] dac_custom_wr, + output [31:0] dac_custom_control, + input [31:0] dac_custom_rd, + input dac_status_if_busy, + + // user channel control + + output [ 7:0] up_usr_chanmax, + input [ 7:0] dac_usr_chanmax, + input [31:0] up_dac_gpio_in, + output [31:0] up_dac_gpio_out, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // parameters + + localparam VERSION = 32'h00090262; + + // internal registers + + reg up_core_preset = 'd1; + reg up_mmcm_preset = 'd1; + reg up_wack_int = 'd0; + reg [31:0] up_scratch = 'd0; + reg up_dac_clk_enb_int = 'd0; + reg up_dac_clk_enb = 'd0; + reg up_mmcm_resetn = 'd0; + reg up_resetn = 'd0; + reg up_dac_sync = 'd0; + reg up_dac_ext_sync_arm = 'd0; + reg up_dac_ext_sync_disarm = 'd0; + reg up_dac_ext_sync_manual_req = 'd0; + reg [4:0] up_dac_num_lanes = 'd0; + reg up_dac_sdr_ddr_n = 'd0; + reg up_dac_symb_op = 'd0; + reg up_dac_symb_8_16b = 'd0; + reg up_dac_par_type = 'd0; + reg up_dac_par_enb = 'd0; + reg up_dac_datafmt = 'd0; + reg [15:0] up_dac_datarate = 'd0; + reg up_dac_frame = 'd0; + reg up_dac_clksel = CLK_EDGE_SEL; + reg [31:0] up_dac_custom_wr = 'd0; + reg [31:0] up_dac_custom_control = 'd0; + reg up_status_unf = 'd0; + reg [ 7:0] up_usr_chanmax_int = 'd0; + reg [31:0] up_dac_gpio_out_int = 'd0; + reg [31:0] up_timer = 'd0; + reg up_rack_int = 'd0; + reg [31:0] up_rdata_int = 'd0; + reg dac_sync_d = 'd0; + reg dac_sync_2d = 'd0; + reg [ 5:0] dac_sync_count = 'd0; + reg dac_sync_int = 'd0; + reg dac_frame_d = 'd0; + reg dac_frame_2d = 'd0; + reg dac_frame_int = 'd0; + + // internal signals + + wire up_wreq_s; + wire up_rreq_s; + wire up_xfer_done_s; + wire up_status_s; + wire [31:0] up_dac_custom_rd; + wire up_status_if_busy; + wire up_sync_in_status; + wire up_status_unf_s; + wire dac_sync_s; + wire dac_frame_s; + wire [31:0] up_dac_clk_count_s; + wire up_drp_status_s; + wire up_drp_rwn_s; + wire [31:0] up_drp_rdata_hold_s; + + wire dac_rst_n; + wire dac_rst_s; + + // decode block select + + assign up_wreq_s = (up_waddr[13:7] == {COMMON_ID,1'b0}) ? up_wreq : 1'b0; + assign up_rreq_s = (up_raddr[13:7] == {COMMON_ID,1'b0}) ? up_rreq : 1'b0; + + assign up_dac_ce = up_dac_clk_enb_int; + + // processor write interface + + assign up_wack = up_wack_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_core_preset <= 1'd1; + up_mmcm_preset <= 1'd1; + up_wack_int <= 'd0; + up_scratch <= 'd0; + up_dac_clk_enb_int <= 'd1; + up_dac_clk_enb <= 'd0; + up_mmcm_resetn <= 'd0; + up_resetn <= 'd0; + up_dac_sync <= 'd0; + up_dac_ext_sync_arm <= 'd0; + up_dac_ext_sync_disarm <= 'd0; + up_dac_ext_sync_manual_req <= 'd0; + up_dac_num_lanes <= 'd0; + up_dac_sdr_ddr_n <= 'd0; + up_dac_symb_op <= 'd0; + up_dac_symb_8_16b <= 'd0; + up_dac_par_type <= 'd0; + up_dac_par_enb <= 'd0; + up_dac_r1_mode <= 'd0; + up_dac_datafmt <= 'd0; + up_dac_datarate <= 'd0; + up_dac_frame <= 'd0; + up_dac_clksel <= CLK_EDGE_SEL; + up_dac_custom_control <= 'd0; + up_pps_irq_mask <= 1'b1; + end else begin + up_dac_clk_enb_int <= ~up_dac_clk_enb; + up_core_preset <= ~up_resetn; + up_mmcm_preset <= ~up_mmcm_resetn; + up_wack_int <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h02)) begin + up_scratch <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h04)) begin + up_pps_irq_mask <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h10)) begin + up_dac_clk_enb <= up_wdata[2]; + up_mmcm_resetn <= up_wdata[1]; + up_resetn <= up_wdata[0]; + end + if (up_dac_sync == 1'b1) begin + if (up_xfer_done_s == 1'b1) begin + up_dac_sync <= 1'b0; + end + end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h11)) begin + up_dac_sync <= up_wdata[0]; + end + if (up_dac_ext_sync_arm == 1'b1) begin + if (up_xfer_done_s == 1'b1) begin + up_dac_ext_sync_arm <= 1'b0; + end + end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h11)) begin + up_dac_ext_sync_arm <= up_wdata[1]; + end + if (up_dac_ext_sync_disarm == 1'b1) begin + if (up_xfer_done_s == 1'b1) begin + up_dac_ext_sync_disarm <= 1'b0; + end + end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h11)) begin + up_dac_ext_sync_disarm <= up_wdata[2]; + end + if (up_dac_ext_sync_manual_req == 1'b1) begin + if (up_xfer_done_s == 1'b1) begin + up_dac_ext_sync_manual_req <= 1'b0; + end + end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h11)) begin + up_dac_ext_sync_manual_req <= up_wdata[8]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h12)) begin + up_dac_sdr_ddr_n <= up_wdata[16]; + up_dac_symb_op <= up_wdata[15]; + up_dac_symb_8_16b <= up_wdata[14]; + up_dac_num_lanes <= up_wdata[12:8]; + up_dac_par_type <= up_wdata[7]; + up_dac_par_enb <= up_wdata[6]; + up_dac_r1_mode <= up_wdata[5]; + up_dac_datafmt <= up_wdata[4]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h13)) begin + up_dac_datarate <= up_wdata[15:0]; + end + if (up_dac_frame == 1'b1) begin + if (up_xfer_done_s == 1'b1) begin + up_dac_frame <= 1'b0; + end + end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h14)) begin + up_dac_frame <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h18)) begin + up_dac_clksel <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h23)) begin + up_dac_custom_control <= up_wdata; + end + end + end + + generate + if (DRP_DISABLE == 1) begin + + assign up_drp_sel = 'd0; + assign up_drp_wr = 'd0; + assign up_drp_status_s = 'd0; + assign up_drp_rwn_s = 'd0; + assign up_drp_addr = 'd0; + assign up_drp_wdata = 'd0; + assign up_drp_rdata_hold_s = 'd0; + + end else begin + + reg up_drp_sel_int = 'd0; + reg up_drp_wr_int = 'd0; + reg up_drp_status_int = 'd0; + reg up_drp_rwn_int = 'd0; + reg [11:0] up_drp_addr_int = 'd0; + reg [31:0] up_drp_wdata_int = 'd0; + reg [31:0] up_drp_rdata_hold_int = 'd0; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_drp_sel_int <= 'd0; + up_drp_wr_int <= 'd0; + up_drp_status_int <= 'd0; + up_drp_rwn_int <= 'd0; + up_drp_addr_int <= 'd0; + up_drp_wdata_int <= 'd0; + up_drp_rdata_hold_int <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h1c)) begin + up_drp_sel_int <= 1'b1; + up_drp_wr_int <= ~up_wdata[28]; + end else begin + up_drp_sel_int <= 1'b0; + up_drp_wr_int <= 1'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h1c)) begin + up_drp_status_int <= 1'b1; + end else if (up_drp_ready == 1'b1) begin + up_drp_status_int <= 1'b0; + end + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h1c)) begin + up_drp_rwn_int <= up_wdata[28]; + up_drp_addr_int <= up_wdata[27:16]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h1e)) begin + up_drp_wdata_int <= up_wdata; + end + if (up_drp_ready == 1'b1) begin + up_drp_rdata_hold_int <= up_drp_rdata; + end + end + end + + assign up_drp_sel = up_drp_sel_int; + assign up_drp_wr = up_drp_wr_int; + assign up_drp_status_s = up_drp_status_int; + assign up_drp_rwn_s = up_drp_rwn_int; + assign up_drp_addr = up_drp_addr_int; + assign up_drp_wdata = up_drp_wdata_int; + assign up_drp_rdata_hold_s = up_drp_rdata_hold_int; + + end + endgenerate + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_dac_custom_wr <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h21)) begin + up_dac_custom_wr <= up_wdata; + end + end + end + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_status_unf <= 'd0; + end else begin + if (up_status_unf_s == 1'b1) begin + up_status_unf <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h22)) begin + up_status_unf <= up_status_unf & ~up_wdata[0]; + end + end + end + + assign up_usr_chanmax = up_usr_chanmax_int; + + generate + if (USERPORTS_DISABLE == 1) begin + always @(posedge up_clk) begin + up_usr_chanmax_int <= 'd0; + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_usr_chanmax_int <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h28)) begin + up_usr_chanmax_int <= up_wdata[7:0]; + end + end + end + end + endgenerate + + assign up_dac_gpio_out = up_dac_gpio_out_int; + + generate + if (GPIO_DISABLE == 1) begin + always @(posedge up_clk) begin + up_dac_gpio_out_int <= 'd0; + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_dac_gpio_out_int <= 'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h2f)) begin + up_dac_gpio_out_int <= up_wdata; + end + end + end + end + endgenerate + + // timer with premature termination + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_timer <= 32'd0; + end else begin + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h40)) begin + up_timer <= up_wdata; + end else if (up_timer > 0) begin + up_timer <= up_timer - 1'b1; + end + end + end + + // processor read interface + + assign up_rack = up_rack_int; + assign up_rdata = up_rdata_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack_int <= 'd0; + up_rdata_int <= 'd0; + end else begin + up_rack_int <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[6:0]) + 7'h00: up_rdata_int <= VERSION; + 7'h01: up_rdata_int <= ID; + 7'h02: up_rdata_int <= up_scratch; + 7'h03: up_rdata_int <= CONFIG; + 7'h07: up_rdata_int <= {FPGA_TECHNOLOGY,FPGA_FAMILY,SPEED_GRADE,DEV_PACKAGE}; // [8,8,8,8] + 7'h10: up_rdata_int <= {29'd0, up_dac_clk_enb, up_mmcm_resetn, up_resetn}; + 7'h11: up_rdata_int <= {20'd0, + 3'b0, up_dac_ext_sync_manual_req, + 4'b0, + 1'b0, up_dac_ext_sync_disarm, up_dac_ext_sync_arm, up_dac_sync}; + 7'h12: up_rdata_int <= {15'd0, up_dac_sdr_ddr_n, up_dac_symb_op, up_dac_symb_8_16b, 1'd0, + up_dac_num_lanes, up_dac_par_type, up_dac_par_enb, up_dac_r1_mode, + up_dac_datafmt, 4'd0}; + 7'h13: up_rdata_int <= {16'd0, up_dac_datarate}; + 7'h14: up_rdata_int <= {31'd0, up_dac_frame}; + 7'h15: up_rdata_int <= up_dac_clk_count_s; + 7'h16: up_rdata_int <= dac_clk_ratio; + 7'h17: up_rdata_int <= {31'd0, up_status_s}; + 7'h18: up_rdata_int <= {31'd0, up_dac_clksel}; + 7'h1a: up_rdata_int <= {31'd0, up_sync_in_status}; + 7'h1c: up_rdata_int <= {3'd0, up_drp_rwn_s, up_drp_addr, 16'b0}; + 7'h1d: up_rdata_int <= {14'd0, up_drp_locked, up_drp_status_s, 16'b0}; + 7'h1e: up_rdata_int <= up_drp_wdata; + 7'h1f: up_rdata_int <= up_drp_rdata_hold_s; + 7'h20: up_rdata_int <= up_dac_custom_rd; + 7'h21: up_rdata_int <= up_dac_custom_wr; + 7'h22: up_rdata_int <= {27'd0, up_status_if_busy, 3'd0, up_status_unf}; + 7'h23: up_rdata_int <= up_dac_custom_control; + 7'h28: up_rdata_int <= {24'd0, dac_usr_chanmax}; + 7'h2e: up_rdata_int <= up_dac_gpio_in; + 7'h2f: up_rdata_int <= up_dac_gpio_out_int; + 7'h30: up_rdata_int <= up_pps_rcounter; + 7'h31: up_rdata_int <= {31'd0,up_pps_status}; + 7'h40: up_rdata_int <= up_timer; + default: up_rdata_int <= 0; + endcase + end else begin + up_rdata_int <= 32'd0; + end + end + end + + // resets + + ad_rst i_mmcm_rst_reg ( + .rst_async(up_mmcm_preset), + .clk(up_clk), + .rstn(), + .rst(mmcm_rst)); + + ad_rst i_core_rst_reg ( + .rst_async(up_core_preset), + .clk(dac_clk), + .rstn(), + .rst(dac_rst_s)); + + // dac control & status + + up_xfer_cntrl #( + .DATA_WIDTH(99) + ) i_xfer_cntrl ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_cntrl ({ up_dac_sdr_ddr_n, + up_dac_symb_op, + up_dac_symb_8_16b, + up_dac_num_lanes, + up_dac_ext_sync_arm, + up_dac_ext_sync_disarm, + up_dac_ext_sync_manual_req, + up_dac_sync, + up_dac_clksel, + up_dac_custom_wr, + up_dac_custom_control, + up_dac_frame, + up_dac_par_type, + up_dac_par_enb, + up_dac_r1_mode, + up_dac_datafmt, + up_dac_datarate, + up_resetn}), + .up_xfer_done (up_xfer_done_s), + .d_rst (dac_rst_s), + .d_clk (dac_clk), + .d_data_cntrl ({ dac_sdr_ddr_n, + dac_symb_op, + dac_symb_8_16b, + dac_num_lanes, + dac_ext_sync_arm, + dac_ext_sync_disarm, + dac_ext_sync_manual_req, + dac_sync_s, + dac_clksel, + dac_custom_wr, + dac_custom_control, + dac_frame_s, + dac_par_type, + dac_par_enb, + dac_r1_mode, + dac_datafmt, + dac_datarate, + dac_rst_n})); + + // De-assert dac_rst together with an updated control set. + // This allows writing the control registers before releasing the reset. + // This is important at start-up when stable set of controls is required. + assign dac_rst = ~dac_rst_n; + + up_xfer_status #( + .DATA_WIDTH(36) + ) i_xfer_status ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_status ({up_sync_in_status, + up_status_s, + up_status_unf_s, + up_status_if_busy, + up_dac_custom_rd}), + .d_rst (dac_rst_s), + .d_clk (dac_clk), + .d_data_status ({ dac_sync_in_status, + dac_status, + dac_status_unf, + dac_status_if_busy, + dac_custom_rd})); + + // generate frame and enable + + assign dac_sync = dac_sync_int; + assign dac_frame = dac_frame_int; + + always @(posedge dac_clk) begin + dac_sync_d <= dac_sync_s; + dac_sync_2d <= dac_sync_d; + if (dac_sync_count[5] == 1'b1) begin + dac_sync_count <= dac_sync_count + 1'b1; + end else if ((dac_sync_d == 1'b1) && (dac_sync_2d == 1'b0)) begin + dac_sync_count <= 6'h20; + end + dac_sync_int <= dac_sync_count[5]; + dac_frame_d <= dac_frame_s; + dac_frame_2d <= dac_frame_d; + dac_frame_int <= dac_frame_d & ~dac_frame_2d; + end + + // dac clock monitor + + up_clock_mon i_clock_mon ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_d_count (up_dac_clk_count_s), + .d_rst (dac_rst_s), + .d_clk (dac_clk)); + +endmodule diff --git a/adi_library/common/up_delay_cntrl.v b/adi_library/common/up_delay_cntrl.v new file mode 100644 index 00000000..f50be757 --- /dev/null +++ b/adi_library/common/up_delay_cntrl.v @@ -0,0 +1,207 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module up_delay_cntrl #( + + // parameters + + parameter DISABLE = 0, + parameter INIT_DELAY = 0, + parameter DATA_WIDTH = 8, + parameter DRP_WIDTH = 5, + parameter BASE_ADDRESS = 6'h02 +) ( + + // delay interface + + input delay_clk, + output delay_rst, + input delay_locked, + + // io interface + + output [(DATA_WIDTH-1):0] up_dld, + output [((DATA_WIDTH*DRP_WIDTH)-1):0] up_dwdata, + input [((DATA_WIDTH*DRP_WIDTH)-1):0] up_drdata, + + // processor interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + generate + if (DISABLE == 1) begin + assign up_wack = 1'd0; + assign up_rack = 1'd0; + assign up_rdata = 32'd0; + + assign up_dld = 'd0; + assign up_dwdata = 'd0; + + assign delay_rst = 1'd0; + + end else begin + // internal registers + + reg up_preset = 'd0; + reg up_wack_int = 'd0; + reg up_rack_int = 'd0; + reg [31:0] up_rdata_int = 'd0; + reg up_dlocked_m1 = 'd0; + reg up_dlocked_m2 = 'd0; + reg up_dlocked_m3 = 'd0; + reg up_dlocked = 'd0; + reg [(DATA_WIDTH-1):0] up_dld_int = 'd0; + reg [((DATA_WIDTH*DRP_WIDTH)-1):0] up_dwdata_int = 'd0; + + // internal signals + + wire up_wreq_s; + wire up_rreq_s; + wire [ DRP_WIDTH-1:0] up_rdata_s; + wire [(DATA_WIDTH-1):0] up_drdata4_s; + wire [(DATA_WIDTH-1):0] up_drdata3_s; + wire [(DATA_WIDTH-1):0] up_drdata2_s; + wire [(DATA_WIDTH-1):0] up_drdata1_s; + wire [(DATA_WIDTH-1):0] up_drdata0_s; + wire [(DATA_WIDTH-1):0] up_dld_s; + wire [((DATA_WIDTH*DRP_WIDTH)-1):0] up_dwdata_s; + wire [(DATA_WIDTH-1):0] up_dinit_s; + wire [((DATA_WIDTH*DRP_WIDTH)-1):0] up_dinitdata_s; + wire delay_rst_s; + + // variables + + genvar n; + + // decode block select + + assign up_wreq_s = (up_waddr[13:8] == BASE_ADDRESS) ? up_wreq : 1'b0; + assign up_rreq_s = (up_raddr[13:8] == BASE_ADDRESS) ? up_rreq : 1'b0; + + assign up_rdata_s = up_drdata >> (DRP_WIDTH*up_raddr[7:0]); + + // processor interface + + assign up_wack = up_wack_int; + assign up_rack = up_rack_int; + assign up_rdata = up_rdata_int; + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_preset <= 1'd1; + up_wack_int <= 'd0; + up_rack_int <= 'd0; + up_rdata_int <= 'd0; + up_dlocked_m1 <= 'd0; + up_dlocked_m2 <= 'd0; + up_dlocked_m3 <= 'd0; + up_dlocked <= 'd0; + end else begin + up_preset <= 1'd0; + up_wack_int <= up_wreq_s; + up_rack_int <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + if (up_dlocked == 1'b0) begin + up_rdata_int <= 32'hffffffff; + end else begin + up_rdata_int <= {{32-DRP_WIDTH{1'b0}}, up_rdata_s}; + end + end else begin + up_rdata_int <= 32'd0; + end + up_dlocked_m1 <= delay_locked; + up_dlocked_m2 <= up_dlocked_m1; + up_dlocked_m3 <= up_dlocked_m2; + up_dlocked <= up_dlocked_m3; + end + end + + // init delay values (after delay locked) + + for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dinit + assign up_dinit_s[n] = up_dlocked_m2 & ~up_dlocked_m3; + assign up_dinitdata_s[(n*DRP_WIDTH) +: DRP_WIDTH] = INIT_DELAY; + end + + // write does not hold- read back what goes into effect. + + for (n = 0; n < DATA_WIDTH; n = n + 1) begin: g_dwr + assign up_dld_s[n] = (up_waddr[7:0] == n) ? up_wreq_s : 1'b0; + assign up_dwdata_s[(n*DRP_WIDTH) +: DRP_WIDTH] = (up_waddr[7:0] == n) ? + up_wdata[DRP_WIDTH-1:0] : up_dwdata_int[(n*DRP_WIDTH) +: DRP_WIDTH]; + end + + assign up_dld = up_dld_int; + assign up_dwdata = up_dwdata_int; + + always @(posedge up_clk) begin + if (up_rstn == 0) begin + up_dld_int <= 'd0; + up_dwdata_int <= 'd0; + end else begin + up_dld_int <= up_dld_s | up_dinit_s; + if ((up_dlocked_m2 == 1'b1) && (up_dlocked_m3 == 1'b0)) begin + up_dwdata_int <= up_dinitdata_s; + end else if (up_wreq_s == 1'b1) begin + up_dwdata_int <= up_dwdata_s; + end + end + end + + // resets + + assign delay_rst = delay_rst_s; + + ad_rst i_delay_rst_reg ( + .rst_async (up_preset), + .clk (delay_clk), + .rstn (), + .rst (delay_rst_s)); + end + endgenerate + +endmodule diff --git a/adi_library/common/up_hdmi_rx.v b/adi_library/common/up_hdmi_rx.v new file mode 100644 index 00000000..48017956 --- /dev/null +++ b/adi_library/common/up_hdmi_rx.v @@ -0,0 +1,289 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module up_hdmi_rx #( + + parameter ID = 0 +) ( + + // hdmi interface + + input hdmi_clk, + output hdmi_rst, + output hdmi_edge_sel, + output hdmi_bgr, + output hdmi_packed, + output hdmi_csc_bypass, + output [15:0] hdmi_vs_count, + output [15:0] hdmi_hs_count, + input hdmi_dma_ovf, + input hdmi_dma_unf, + input hdmi_tpm_oos, + input hdmi_vs_oos, + input hdmi_hs_oos, + input hdmi_vs_mismatch, + input hdmi_hs_mismatch, + input [15:0] hdmi_vs, + input [15:0] hdmi_hs, + input [31:0] hdmi_clk_ratio, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack +); + + localparam PCORE_VERSION = 32'h00040063; + + // internal registers + + reg up_core_preset = 'd0; + reg up_resetn = 'd0; + reg [31:0] up_scratch = 'd0; + reg up_edge_sel = 'd0; + reg up_bgr = 'd0; + reg up_packed = 'd0; + reg up_csc_bypass = 'd0; + reg up_dma_ovf = 'd0; + reg up_dma_unf = 'd0; + reg up_tpm_oos = 'd0; + reg up_vs_oos = 'd0; + reg up_hs_oos = 'd0; + reg up_vs_mismatch = 'd0; + reg up_hs_mismatch = 'd0; + reg [15:0] up_vs_count = 'd0; + reg [15:0] up_hs_count = 'd0; + + // internal signals + + wire up_wreq_s; + wire up_rreq_s; + wire up_dma_ovf_s; + wire up_dma_unf_s; + wire up_vs_oos_s; + wire up_hs_oos_s; + wire up_vs_mismatch_s; + wire up_hs_mismatch_s; + wire [15:0] up_vs_s; + wire [15:0] up_hs_s; + wire [31:0] up_clk_count_s; + + // decode block select + + assign up_wreq_s = (up_waddr[13:12] == 2'd0) ? up_wreq : 1'b0; + assign up_rreq_s = (up_raddr[13:12] == 2'd0) ? up_rreq : 1'b0; + + // processor write interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_core_preset <= 1'd1; + up_resetn <= 'd0; + up_wack <= 'd0; + up_scratch <= 'd0; + up_edge_sel <= 'd0; + up_bgr <= 'd0; + up_packed <= 'd0; + up_csc_bypass <= 'd0; + up_dma_ovf <= 'd0; + up_dma_unf <= 'd0; + up_tpm_oos <= 'd0; + up_vs_oos <= 'd0; + up_hs_oos <= 'd0; + up_vs_mismatch <= 'd0; + up_hs_mismatch <= 'd0; + up_vs_count <= 'd0; + up_hs_count <= 'd0; + end else begin + up_wack <= up_wreq_s; + up_core_preset <= ~up_resetn; + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h002)) begin + up_scratch <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h010)) begin + up_resetn <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin + up_edge_sel <= up_wdata[3]; + up_bgr <= up_wdata[2]; + up_packed <= up_wdata[1]; + up_csc_bypass <= up_wdata[0]; + end + if (up_dma_ovf_s == 1'b1) begin + up_dma_ovf <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h018)) begin + up_dma_ovf <= up_dma_ovf & ~up_wdata[1]; + end + if (up_dma_unf_s == 1'b1) begin + up_dma_unf <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h018)) begin + up_dma_unf <= up_dma_unf & ~up_wdata[0]; + end + if (up_tpm_oos_s == 1'b1) begin + up_tpm_oos <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h019)) begin + up_tpm_oos <= up_tpm_oos & ~up_wdata[1]; + end + if (up_vs_oos_s == 1'b1) begin + up_vs_oos <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h020)) begin + up_vs_oos <= up_vs_oos & ~up_wdata[3]; + end + if (up_hs_oos_s == 1'b1) begin + up_hs_oos <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h020)) begin + up_hs_oos <= up_hs_oos & ~up_wdata[2]; + end + if (up_vs_mismatch_s == 1'b1) begin + up_vs_mismatch <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h020)) begin + up_vs_mismatch <= up_vs_mismatch & ~up_wdata[1]; + end + if (up_hs_mismatch_s == 1'b1) begin + up_hs_mismatch <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h020)) begin + up_hs_mismatch <= up_hs_mismatch & ~up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h100)) begin + up_vs_count <= up_wdata[31:16]; + up_hs_count <= up_wdata[15:0]; + end + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq_s; + if(up_rreq_s == 1'b1) begin + case (up_raddr[11:0]) + 12'h000: up_rdata <= PCORE_VERSION; + 12'h001: up_rdata <= ID; + 12'h002: up_rdata <= up_scratch; + 12'h010: up_rdata <= {31'h0, up_resetn}; + 12'h011: up_rdata <= {28'h0, up_edge_sel, up_bgr, up_packed, up_csc_bypass}; + 12'h015: up_rdata <= up_clk_count_s; + 12'h016: up_rdata <= hdmi_clk_ratio; + 12'h018: up_rdata <= {30'h0, up_dma_ovf, up_dma_unf}; + 12'h019: up_rdata <= {30'h0, up_tpm_oos, 1'b0}; + 12'h020: up_rdata <= {28'h0, up_vs_oos, up_hs_oos, + up_vs_mismatch, up_hs_mismatch}; + 12'h100: up_rdata <= {up_vs_count, up_hs_count}; + 12'h101: up_rdata <= {up_vs_s, up_hs_s}; + default: up_rdata <= 0; + endcase + end + end + end + + // resets + + ad_rst i_hdmi_rst_reg ( + .rst_async (up_core_preset), + .clk (hdmi_clk), + .rstn (), + .rst (hdmi_rst)); + + // hdmi control & status + + up_xfer_cntrl #( + .DATA_WIDTH(36) + ) i_hdmi_xfer_cntrl ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_cntrl ({ up_edge_sel, + up_bgr, + up_packed, + up_csc_bypass, + up_vs_count, + up_hs_count}), + .up_xfer_done (), + .d_rst (hdmi_rst), + .d_clk (hdmi_clk), + .d_data_cntrl ({ hdmi_edge_sel, + hdmi_bgr, + hdmi_packed, + hdmi_csc_bypass, + hdmi_vs_count, + hdmi_hs_count})); + + up_xfer_status #( + .DATA_WIDTH(39) + ) i_hdmi_xfer_status ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_status ({ up_dma_ovf_s, + up_dma_unf_s, + up_tpm_oos_s, + up_vs_oos_s, + up_hs_oos_s, + up_vs_mismatch_s, + up_hs_mismatch_s, + up_vs_s, + up_hs_s}), + .d_rst (hdmi_rst), + .d_clk (hdmi_clk), + .d_data_status ({ hdmi_dma_ovf, + hdmi_dma_unf, + hdmi_tpm_oos, + hdmi_vs_oos, + hdmi_hs_oos, + hdmi_vs_mismatch, + hdmi_hs_mismatch, + hdmi_vs, + hdmi_hs})); + + up_clock_mon i_hdmi_clock_mon ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_d_count (up_clk_count_s), + .d_rst (hdmi_rst), + .d_clk (hdmi_clk)); + +endmodule diff --git a/adi_library/common/up_hdmi_tx.v b/adi_library/common/up_hdmi_tx.v new file mode 100644 index 00000000..009330da --- /dev/null +++ b/adi_library/common/up_hdmi_tx.v @@ -0,0 +1,364 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module up_hdmi_tx #( + + parameter ID = 0 +) ( + + // hdmi interface + + input hdmi_clk, + output hdmi_rst, + output hdmi_csc_bypass, + output hdmi_ss_bypass, + output [ 1:0] hdmi_srcsel, + output [23:0] hdmi_const_rgb, + output [15:0] hdmi_hl_active, + output [15:0] hdmi_hl_width, + output [15:0] hdmi_hs_width, + output [15:0] hdmi_he_max, + output [15:0] hdmi_he_min, + output [15:0] hdmi_vf_active, + output [15:0] hdmi_vf_width, + output [15:0] hdmi_vs_width, + output [15:0] hdmi_ve_max, + output [15:0] hdmi_ve_min, + output [23:0] hdmi_clip_max, + output [23:0] hdmi_clip_min, + input hdmi_status, + input hdmi_tpm_oos, + input [31:0] hdmi_clk_ratio, + + // vdma interface + + input vdma_clk, + output vdma_rst, + input vdma_ovf, + input vdma_unf, + input vdma_tpm_oos, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack +); + + localparam PCORE_VERSION = 32'h00040063; + + // internal registers + + reg up_core_preset; + reg [31:0] up_scratch = 'd0; + reg up_resetn = 'd0; + reg up_csc_bypass = 'd0; + reg up_ss_bypass = 'd0; + reg [ 1:0] up_srcsel = 'd1; + reg [23:0] up_const_rgb = 'd0; + reg up_vdma_ovf = 'd0; + reg up_vdma_unf = 'd0; + reg up_hdmi_tpm_oos = 'd0; + reg up_vdma_tpm_oos = 'd0; + reg [15:0] up_hl_active = 'd0; + reg [15:0] up_hl_width = 'd0; + reg [15:0] up_hs_width = 'd0; + reg [15:0] up_he_max = 'd0; + reg [15:0] up_he_min = 'd0; + reg [15:0] up_vf_active = 'd0; + reg [15:0] up_vf_width = 'd0; + reg [15:0] up_vs_width = 'd0; + reg [15:0] up_ve_max = 'd0; + reg [15:0] up_ve_min = 'd0; + reg [23:0] up_clip_max; + reg [23:0] up_clip_min; + + // internal signals + + wire up_wreq_s; + wire up_rreq_s; + wire up_hdmi_status_s; + wire up_hdmi_tpm_oos_s; + wire [31:0] up_hdmi_clk_count_s; + wire up_vdma_ovf_s; + wire up_vdma_unf_s; + wire up_vdma_tpm_oos_s; + + // decode block select + + assign up_wreq_s = (up_waddr[13:12] == 2'd0) ? up_wreq : 1'b0; + assign up_rreq_s = (up_raddr[13:12] == 2'd0) ? up_rreq : 1'b0; + + // processor write interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_core_preset <= 1'd1; + up_wack <= 'd0; + up_scratch <= 'd0; + up_resetn <= 'd0; + up_csc_bypass <= 'd0; + up_ss_bypass <= 'd0; + up_srcsel <= 'd1; + up_const_rgb <= 'd0; + up_vdma_ovf <= 'd0; + up_vdma_unf <= 'd0; + up_hdmi_tpm_oos <= 'd0; + up_vdma_tpm_oos <= 'd0; + up_hl_active <= 'd0; + up_hl_width <= 'd0; + up_hs_width <= 'd0; + up_he_max <= 'd0; + up_he_min <= 'd0; + up_vf_active <= 'd0; + up_vf_width <= 'd0; + up_vs_width <= 'd0; + up_ve_max <= 'd0; + up_ve_min <= 'd0; + up_clip_max <= 24'hf0ebf0; + up_clip_min <= 24'h101010; + end else begin + up_core_preset <= ~up_resetn; + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h002)) begin + up_scratch <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h010)) begin + up_resetn <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin + up_ss_bypass <= up_wdata[2]; + up_csc_bypass <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h012)) begin + up_srcsel <= up_wdata[1:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h013)) begin + up_const_rgb <= up_wdata[23:0]; + end + if (up_vdma_ovf_s == 1'b1) begin + up_vdma_ovf <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h018)) begin + up_vdma_ovf <= up_vdma_ovf & ~up_wdata[1]; + end + if (up_vdma_unf_s == 1'b1) begin + up_vdma_unf <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h018)) begin + up_vdma_unf <= up_vdma_unf & ~up_wdata[0]; + end + if (up_hdmi_tpm_oos_s == 1'b1) begin + up_hdmi_tpm_oos <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h019)) begin + up_hdmi_tpm_oos <= up_hdmi_tpm_oos & ~up_wdata[1]; + end + if (up_vdma_tpm_oos_s == 1'b1) begin + up_vdma_tpm_oos <= 1'b1; + end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h019)) begin + up_vdma_tpm_oos <= up_vdma_tpm_oos & ~up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01a)) begin + up_clip_max <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01b)) begin + up_clip_min <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h100)) begin + up_hl_active <= up_wdata[31:16]; + up_hl_width <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h101)) begin + up_hs_width <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h102)) begin + up_he_max <= up_wdata[31:16]; + up_he_min <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h110)) begin + up_vf_active <= up_wdata[31:16]; + up_vf_width <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h111)) begin + up_vs_width <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h112)) begin + up_ve_max <= up_wdata[31:16]; + up_ve_min <= up_wdata[15:0]; + end + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[11:0]) + 12'h000: up_rdata <= PCORE_VERSION; + 12'h001: up_rdata <= ID; + 12'h002: up_rdata <= up_scratch; + 12'h010: up_rdata <= {31'd0, up_resetn}; + 12'h011: up_rdata <= {29'd0, up_ss_bypass, 1'b0, up_csc_bypass}; + 12'h012: up_rdata <= {30'd0, up_srcsel}; + 12'h013: up_rdata <= {8'd0, up_const_rgb}; + 12'h015: up_rdata <= up_hdmi_clk_count_s; + 12'h016: up_rdata <= hdmi_clk_ratio; + 12'h017: up_rdata <= {31'd0, up_hdmi_status_s}; + 12'h018: up_rdata <= {30'd0, up_vdma_ovf, up_vdma_unf}; + 12'h019: up_rdata <= {30'd0, up_hdmi_tpm_oos, up_vdma_tpm_oos}; + 12'h01a: up_rdata <= {8'd0, up_clip_max}; + 12'h01b: up_rdata <= {8'd0, up_clip_min}; + + 12'h100: up_rdata <= {up_hl_active, up_hl_width}; + 12'h101: up_rdata <= {16'd0, up_hs_width}; + 12'h102: up_rdata <= {up_he_max, up_he_min}; + 12'h110: up_rdata <= {up_vf_active, up_vf_width}; + 12'h111: up_rdata <= {16'd0, up_vs_width}; + 12'h112: up_rdata <= {up_ve_max, up_ve_min}; + default: up_rdata <= 0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + // resets + + ad_rst i_core_rst_reg ( + .rst_async(up_core_preset), + .clk(hdmi_clk), + .rstn(), + .rst(hdmi_rst)); + + ad_rst i_vdma_rst_reg ( + .rst_async(up_core_preset), + .clk(vdma_clk), + .rstn(), + .rst(vdma_rst)); + + // hdmi control & status + + up_xfer_cntrl #( + .DATA_WIDTH(236) + ) i_xfer_cntrl ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_cntrl ({ up_ss_bypass, + up_csc_bypass, + up_srcsel, + up_const_rgb, + up_hl_active, + up_hl_width, + up_hs_width, + up_he_max, + up_he_min, + up_vf_active, + up_vf_width, + up_vs_width, + up_ve_max, + up_ve_min, + up_clip_max, + up_clip_min}), + .up_xfer_done (), + .d_rst (hdmi_rst), + .d_clk (hdmi_clk), + .d_data_cntrl ({ hdmi_ss_bypass, + hdmi_csc_bypass, + hdmi_srcsel, + hdmi_const_rgb, + hdmi_hl_active, + hdmi_hl_width, + hdmi_hs_width, + hdmi_he_max, + hdmi_he_min, + hdmi_vf_active, + hdmi_vf_width, + hdmi_vs_width, + hdmi_ve_max, + hdmi_ve_min, + hdmi_clip_max, + hdmi_clip_min})); + + up_xfer_status #( + .DATA_WIDTH(2) + ) i_xfer_status ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_status ({up_hdmi_status_s, + up_hdmi_tpm_oos_s}), + .d_rst (hdmi_rst), + .d_clk (hdmi_clk), + .d_data_status ({ hdmi_status, + hdmi_tpm_oos})); + + // hdmi clock monitor + + up_clock_mon i_clock_mon ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_d_count (up_hdmi_clk_count_s), + .d_rst (hdmi_rst), + .d_clk (hdmi_clk)); + + // vdma control & status + + up_xfer_status #( + .DATA_WIDTH(3) + ) i_vdma_xfer_status ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_status ({up_vdma_ovf_s, + up_vdma_unf_s, + up_vdma_tpm_oos_s}), + .d_rst (vdma_rst), + .d_clk (vdma_clk), + .d_data_status ({ vdma_ovf, + vdma_unf, + vdma_tpm_oos})); + +endmodule diff --git a/adi_library/common/up_pmod.v b/adi_library/common/up_pmod.v new file mode 100644 index 00000000..278200e0 --- /dev/null +++ b/adi_library/common/up_pmod.v @@ -0,0 +1,140 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module up_pmod #( + + parameter ID = 0 +) ( + input pmod_clk, + output pmod_rst, + input [31:0] pmod_signal_freq, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack +); + + localparam PCORE_VERSION = 32'h00010001; + + // internal registers + + reg [31:0] up_scratch = 'd0; + reg up_resetn = 'd0; + + // internal signals + + wire [31:0] up_pmod_signal_freq_s; + wire up_wreq_s; + wire up_rreq_s; + + // decode block select + + assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0; + assign up_rreq_s = (up_raddr[13:8] == 6'h00) ? up_rreq : 1'b0; + assign up_preset_s = ~up_resetn; + + // processor write interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_scratch <= 'd0; + up_resetn <= 'd0; + end else begin + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin + up_scratch <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin + up_resetn <= up_wdata[0]; + end + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[7:0]) + 8'h00: up_rdata <= PCORE_VERSION; + 8'h01: up_rdata <= ID; + 8'h02: up_rdata <= up_scratch; + 8'h03: up_rdata <= up_pmod_signal_freq_s; + 8'h10: up_rdata <= up_resetn; + default: up_rdata <= 0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + // resets + + ad_rst i_adc_rst_reg ( + .rst_async(up_preset_s), + .clk(pmod_clk), + .rstn(), + .rst(pmod_rst)); + + // adc control & status + + up_xfer_status #( + .DATA_WIDTH(32) + ) i_pmod_xfer_status ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_status (up_pmod_signal_freq_s), + .d_rst (pmod_rst), + .d_clk (pmod_clk), + .d_data_status (pmod_signal_freq)); + +endmodule diff --git a/adi_library/common/up_tdd_cntrl.v b/adi_library/common/up_tdd_cntrl.v new file mode 100644 index 00000000..bd05c386 --- /dev/null +++ b/adi_library/common/up_tdd_cntrl.v @@ -0,0 +1,484 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +`timescale 1ns/100ps + +module up_tdd_cntrl #( + + parameter ID = 0, + parameter BASE_ADDRESS = 6'h20 +) ( + input clk, + input rst, + + //rf tdd interface control + + output tdd_enable, + output tdd_secondary, + output tdd_rx_only, + output tdd_tx_only, + output tdd_gated_rx_dmapath, + output tdd_gated_tx_dmapath, + output [ 7:0] tdd_burst_count, + output [23:0] tdd_counter_init, + output [23:0] tdd_frame_length, + output tdd_terminal_type, + output [23:0] tdd_vco_rx_on_1, + output [23:0] tdd_vco_rx_off_1, + output [23:0] tdd_vco_tx_on_1, + output [23:0] tdd_vco_tx_off_1, + output [23:0] tdd_rx_on_1, + output [23:0] tdd_rx_off_1, + output [23:0] tdd_rx_dp_on_1, + output [23:0] tdd_rx_dp_off_1, + output [23:0] tdd_tx_on_1, + output [23:0] tdd_tx_off_1, + output [23:0] tdd_tx_dp_on_1, + output [23:0] tdd_tx_dp_off_1, + output [23:0] tdd_vco_rx_on_2, + output [23:0] tdd_vco_rx_off_2, + output [23:0] tdd_vco_tx_on_2, + output [23:0] tdd_vco_tx_off_2, + output [23:0] tdd_rx_on_2, + output [23:0] tdd_rx_off_2, + output [23:0] tdd_rx_dp_on_2, + output [23:0] tdd_rx_dp_off_2, + output [23:0] tdd_tx_on_2, + output [23:0] tdd_tx_off_2, + output [23:0] tdd_tx_dp_on_2, + output [23:0] tdd_tx_dp_off_2, + + input [ 7:0] tdd_status, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output reg up_wack, + input up_rreq, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + output reg up_rack +); + + localparam PCORE_VERSION = 32'h00010061; + localparam PCORE_MAGIC = 32'h54444443; // "TDDC", big endian + + // internal registers + + reg [31:0] up_scratch = 32'h0; + + reg up_tdd_enable = 1'h0; + reg up_tdd_secondary = 1'h0; + reg up_tdd_rx_only = 1'h0; + reg up_tdd_tx_only = 1'h0; + reg up_tdd_gated_tx_dmapath = 1'h0; + reg up_tdd_gated_rx_dmapath = 1'h0; + reg up_tdd_terminal_type = 1'h0; + + reg [ 7:0] up_tdd_burst_count = 8'h0; + reg [23:0] up_tdd_counter_init = 24'h0; + reg [23:0] up_tdd_frame_length = 24'h0; + + reg [23:0] up_tdd_vco_rx_on_1 = 24'h0; + reg [23:0] up_tdd_vco_rx_off_1 = 24'h0; + reg [23:0] up_tdd_vco_tx_on_1 = 24'h0; + reg [23:0] up_tdd_vco_tx_off_1 = 24'h0; + reg [23:0] up_tdd_rx_on_1 = 24'h0; + reg [23:0] up_tdd_rx_off_1 = 24'h0; + reg [23:0] up_tdd_rx_dp_on_1 = 24'h0; + reg [23:0] up_tdd_rx_dp_off_1 = 24'h0; + reg [23:0] up_tdd_tx_on_1 = 24'h0; + reg [23:0] up_tdd_tx_off_1 = 24'h0; + reg [23:0] up_tdd_tx_dp_on_1 = 24'h0; + reg [23:0] up_tdd_tx_dp_off_1 = 24'h0; + reg [23:0] up_tdd_vco_rx_on_2 = 24'h0; + reg [23:0] up_tdd_vco_rx_off_2 = 24'h0; + reg [23:0] up_tdd_vco_tx_on_2 = 24'h0; + reg [23:0] up_tdd_vco_tx_off_2 = 24'h0; + reg [23:0] up_tdd_rx_on_2 = 24'h0; + reg [23:0] up_tdd_rx_off_2 = 24'h0; + reg [23:0] up_tdd_rx_dp_on_2 = 24'h0; + reg [23:0] up_tdd_rx_dp_off_2 = 24'h0; + reg [23:0] up_tdd_tx_on_2 = 24'h0; + reg [23:0] up_tdd_tx_off_2 = 24'h0; + reg [23:0] up_tdd_tx_dp_on_2 = 24'h0; + reg [23:0] up_tdd_tx_dp_off_2 = 24'h0; + + // internal signals + + wire up_wreq_s; + wire up_rreq_s; + + wire [ 7:0] up_tdd_status_s; + + // decode block select + + assign up_wreq_s = (up_waddr[13:8] == BASE_ADDRESS[5:0]) ? up_wreq : 1'b0; + assign up_rreq_s = (up_raddr[13:8] == BASE_ADDRESS[5:0]) ? up_rreq : 1'b0; + + // processor write interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 1'h0; + up_scratch <= 32'h0; + up_tdd_enable <= 1'h0; + up_tdd_secondary <= 1'h0; + up_tdd_rx_only <= 1'h0; + up_tdd_tx_only <= 1'h0; + up_tdd_gated_tx_dmapath <= 1'h0; + up_tdd_gated_rx_dmapath <= 1'h0; + up_tdd_terminal_type <= 1'h0; + up_tdd_counter_init <= 24'h0; + up_tdd_frame_length <= 24'h0; + up_tdd_burst_count <= 8'h0; + up_tdd_vco_rx_on_1 <= 24'h0; + up_tdd_vco_rx_off_1 <= 24'h0; + up_tdd_vco_tx_on_1 <= 24'h0; + up_tdd_vco_tx_off_1 <= 24'h0; + up_tdd_rx_on_1 <= 24'h0; + up_tdd_rx_off_1 <= 24'h0; + up_tdd_rx_dp_on_1 <= 24'h0; + up_tdd_rx_dp_off_1 <= 24'h0; + up_tdd_tx_on_1 <= 24'h0; + up_tdd_tx_off_1 <= 24'h0; + up_tdd_tx_dp_on_1 <= 24'h0; + up_tdd_tx_dp_off_1 <= 24'h0; + up_tdd_vco_rx_on_2 <= 24'h0; + up_tdd_vco_rx_off_2 <= 24'h0; + up_tdd_vco_tx_on_2 <= 24'h0; + up_tdd_vco_tx_off_2 <= 24'h0; + up_tdd_rx_on_2 <= 24'h0; + up_tdd_rx_off_2 <= 24'h0; + up_tdd_rx_dp_on_2 <= 24'h0; + up_tdd_rx_dp_off_2 <= 24'h0; + up_tdd_tx_on_2 <= 24'h0; + up_tdd_tx_off_2 <= 24'h0; + up_tdd_tx_dp_on_2 <= 24'h0; + up_tdd_tx_dp_off_2 <= 24'h0; + end else begin + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin + up_scratch <= up_wdata; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin + up_tdd_enable <= up_wdata[0]; + up_tdd_secondary <= up_wdata[1]; + up_tdd_rx_only <= up_wdata[2]; + up_tdd_tx_only <= up_wdata[3]; + up_tdd_gated_rx_dmapath <= up_wdata[4]; + up_tdd_gated_tx_dmapath <= up_wdata[5]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin + up_tdd_burst_count <= up_wdata[7:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin + up_tdd_counter_init <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin + up_tdd_frame_length <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin + up_tdd_terminal_type <= up_wdata[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin + up_tdd_vco_rx_on_1 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin + up_tdd_vco_rx_off_1 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin + up_tdd_vco_tx_on_1 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h23)) begin + up_tdd_vco_tx_off_1 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h24)) begin + up_tdd_rx_on_1 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h25)) begin + up_tdd_rx_off_1 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h26)) begin + up_tdd_tx_on_1 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h27)) begin + up_tdd_tx_off_1 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin + up_tdd_rx_dp_on_1 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin + up_tdd_rx_dp_off_1 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2a)) begin + up_tdd_tx_dp_on_1 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2b)) begin + up_tdd_tx_dp_off_1 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h30)) begin + up_tdd_vco_rx_on_2 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h31)) begin + up_tdd_vco_rx_off_2 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h32)) begin + up_tdd_vco_tx_on_2 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h33)) begin + up_tdd_vco_tx_off_2 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h34)) begin + up_tdd_rx_on_2 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h35)) begin + up_tdd_rx_off_2 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h36)) begin + up_tdd_tx_on_2 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h37)) begin + up_tdd_tx_off_2 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h38)) begin + up_tdd_rx_dp_on_2 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h39)) begin + up_tdd_rx_dp_off_2 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h3a)) begin + up_tdd_tx_dp_on_2 <= up_wdata[23:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h3b)) begin + up_tdd_tx_dp_off_2 <= up_wdata[23:0]; + end + end + end + + // processor read interface + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 1'b0; + up_rdata <= 1'b0; + end else begin + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[7:0]) + 8'h00: up_rdata <= PCORE_VERSION; + 8'h01: up_rdata <= ID; + 8'h02: up_rdata <= up_scratch; + 8'h03: up_rdata <= PCORE_MAGIC; + 8'h10: up_rdata <= {28'h0, up_tdd_gated_tx_dmapath, + up_tdd_gated_rx_dmapath, + up_tdd_tx_only, + up_tdd_rx_only, + up_tdd_secondary, + up_tdd_enable}; + 8'h11: up_rdata <= {24'h0, up_tdd_burst_count}; + 8'h12: up_rdata <= { 8'h0, up_tdd_counter_init}; + 8'h13: up_rdata <= { 8'h0, up_tdd_frame_length}; + 8'h14: up_rdata <= {31'h0, up_tdd_terminal_type}; + 8'h18: up_rdata <= {24'h0, up_tdd_status_s}; + 8'h20: up_rdata <= { 8'h0, up_tdd_vco_rx_on_1}; + 8'h21: up_rdata <= { 8'h0, up_tdd_vco_rx_off_1}; + 8'h22: up_rdata <= { 8'h0, up_tdd_vco_tx_on_1}; + 8'h23: up_rdata <= { 8'h0, up_tdd_vco_tx_off_1}; + 8'h24: up_rdata <= { 8'h0, up_tdd_rx_on_1}; + 8'h25: up_rdata <= { 8'h0, up_tdd_rx_off_1}; + 8'h26: up_rdata <= { 8'h0, up_tdd_tx_on_1}; + 8'h27: up_rdata <= { 8'h0, up_tdd_tx_off_1}; + 8'h28: up_rdata <= { 8'h0, up_tdd_rx_dp_on_1}; + 8'h29: up_rdata <= { 8'h0, up_tdd_rx_dp_off_1}; + 8'h2a: up_rdata <= { 8'h0, up_tdd_tx_dp_on_1}; + 8'h2b: up_rdata <= { 8'h0, up_tdd_tx_dp_off_1}; + 8'h30: up_rdata <= { 8'h0, up_tdd_vco_rx_on_2}; + 8'h31: up_rdata <= { 8'h0, up_tdd_vco_rx_off_2}; + 8'h32: up_rdata <= { 8'h0, up_tdd_vco_tx_on_2}; + 8'h33: up_rdata <= { 8'h0, up_tdd_vco_tx_off_2}; + 8'h34: up_rdata <= { 8'h0, up_tdd_rx_on_2}; + 8'h35: up_rdata <= { 8'h0, up_tdd_rx_off_2}; + 8'h36: up_rdata <= { 8'h0, up_tdd_tx_on_2}; + 8'h37: up_rdata <= { 8'h0, up_tdd_tx_off_2}; + 8'h38: up_rdata <= { 8'h0, up_tdd_rx_dp_on_2}; + 8'h39: up_rdata <= { 8'h0, up_tdd_rx_dp_off_2}; + 8'h3a: up_rdata <= { 8'h0, up_tdd_tx_dp_on_2}; + 8'h3b: up_rdata <= { 8'h0, up_tdd_tx_dp_off_2}; + default: up_rdata <= 32'h0; + endcase + end else begin + up_rdata <= 32'h0; + end + end + end + + // rf tdd control signal CDC + + up_xfer_cntrl #( + .DATA_WIDTH(63) + ) i_xfer_tdd_control ( + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_data_cntrl({up_tdd_counter_init, + up_tdd_frame_length, + up_tdd_enable, + up_tdd_secondary, + up_tdd_rx_only, + up_tdd_tx_only, + up_tdd_gated_rx_dmapath, + up_tdd_gated_tx_dmapath, + up_tdd_burst_count, + up_tdd_terminal_type}), + .up_xfer_done(), + .d_rst(rst), + .d_clk(clk), + .d_data_cntrl({tdd_counter_init, + tdd_frame_length, + tdd_enable, + tdd_secondary, + tdd_rx_only, + tdd_tx_only, + tdd_gated_rx_dmapath, + tdd_gated_tx_dmapath, + tdd_burst_count, + tdd_terminal_type})); + + up_xfer_cntrl #( + .DATA_WIDTH(144) + ) i_xfer_tdd_counter_values_rx_1 ( + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_data_cntrl({ + up_tdd_vco_rx_on_1, + up_tdd_vco_rx_off_1, + up_tdd_rx_on_1, + up_tdd_rx_off_1, + up_tdd_rx_dp_on_1, + up_tdd_rx_dp_off_1}), + .up_xfer_done(), + .d_rst(rst), + .d_clk(clk), + .d_data_cntrl({ + tdd_vco_rx_on_1, + tdd_vco_rx_off_1, + tdd_rx_on_1, + tdd_rx_off_1, + tdd_rx_dp_on_1, + tdd_rx_dp_off_1})); + + up_xfer_cntrl #( + .DATA_WIDTH(144) + ) i_xfer_tdd_counter_values_tx_1 ( + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_data_cntrl({ + up_tdd_vco_tx_on_1, + up_tdd_vco_tx_off_1, + up_tdd_tx_on_1, + up_tdd_tx_off_1, + up_tdd_tx_dp_on_1, + up_tdd_tx_dp_off_1}), + .up_xfer_done(), + .d_rst(rst), + .d_clk(clk), + .d_data_cntrl({ + tdd_vco_tx_on_1, + tdd_vco_tx_off_1, + tdd_tx_on_1, + tdd_tx_off_1, + tdd_tx_dp_on_1, + tdd_tx_dp_off_1})); + + up_xfer_cntrl #( + .DATA_WIDTH(144) + ) i_xfer_tdd_counter_values_rx_2 ( + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_data_cntrl({ + up_tdd_vco_rx_on_2, + up_tdd_vco_rx_off_2, + up_tdd_rx_on_2, + up_tdd_rx_off_2, + up_tdd_rx_dp_on_2, + up_tdd_rx_dp_off_2}), + .up_xfer_done(), + .d_rst(rst), + .d_clk(clk), + .d_data_cntrl({ + tdd_vco_rx_on_2, + tdd_vco_rx_off_2, + tdd_rx_on_2, + tdd_rx_off_2, + tdd_rx_dp_on_2, + tdd_rx_dp_off_2})); + + up_xfer_cntrl #( + .DATA_WIDTH(144) + ) i_xfer_tdd_counter_values_tx_2 ( + .up_rstn(up_rstn), + .up_clk(up_clk), + .up_data_cntrl({ + up_tdd_vco_tx_on_2, + up_tdd_vco_tx_off_2, + up_tdd_tx_on_2, + up_tdd_tx_off_2, + up_tdd_tx_dp_on_2, + up_tdd_tx_dp_off_2}), + .up_xfer_done(), + .d_rst(rst), + .d_clk(clk), + .d_data_cntrl({ + tdd_vco_tx_on_2, + tdd_vco_tx_off_2, + tdd_tx_on_2, + tdd_tx_off_2, + tdd_tx_dp_on_2, + tdd_tx_dp_off_2})); + + up_xfer_status #( + .DATA_WIDTH(8) + ) i_xfer_tdd_status ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_status (up_tdd_status_s), + .d_rst (rst), + .d_clk (clk), + .d_data_status (tdd_status)); + +endmodule diff --git a/adi_library/common/up_xfer_cntrl.v b/adi_library/common/up_xfer_cntrl.v new file mode 100644 index 00000000..3700157c --- /dev/null +++ b/adi_library/common/up_xfer_cntrl.v @@ -0,0 +1,125 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module up_xfer_cntrl #( + + parameter DATA_WIDTH = 8 +) ( + + // up interface + + input up_rstn, + input up_clk, + input [(DATA_WIDTH-1):0] up_data_cntrl, + output up_xfer_done, + + // device interface + + input d_rst, + input d_clk, + output [(DATA_WIDTH-1):0] d_data_cntrl +); + + // internal registers + + reg up_xfer_state_m1 = 'd0; + reg up_xfer_state_m2 = 'd0; + reg up_xfer_state = 'd0; + reg [ 5:0] up_xfer_count = 'd0; + reg up_xfer_done_int = 'd0; + reg up_xfer_toggle = 'd0; + reg [(DATA_WIDTH-1):0] up_xfer_data = 'd0; + reg d_xfer_toggle_m1 = 'd0; + reg d_xfer_toggle_m2 = 'd0; + reg d_xfer_toggle_m3 = 'd0; + reg d_xfer_toggle = 'd0; + reg [(DATA_WIDTH-1):0] d_data_cntrl_int = 'd0; + + // internal signals + + wire up_xfer_enable_s; + wire d_xfer_toggle_s; + + // device control transfer + + assign up_xfer_done = up_xfer_done_int; + assign up_xfer_enable_s = up_xfer_state ^ up_xfer_toggle; + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_xfer_state_m1 <= 'd0; + up_xfer_state_m2 <= 'd0; + up_xfer_state <= 'd0; + up_xfer_count <= 'd0; + up_xfer_done_int <= 'd0; + up_xfer_toggle <= 'd0; + up_xfer_data <= 'd0; + end else begin + up_xfer_state_m1 <= d_xfer_toggle; + up_xfer_state_m2 <= up_xfer_state_m1; + up_xfer_state <= up_xfer_state_m2; + up_xfer_count <= up_xfer_count + 1'd1; + up_xfer_done_int <= (up_xfer_count == 6'd0) ? ~up_xfer_enable_s : 1'b0; + if ((up_xfer_count == 6'd1) && (up_xfer_enable_s == 1'b0)) begin + up_xfer_toggle <= ~up_xfer_toggle; + up_xfer_data <= up_data_cntrl; + end + end + end + + assign d_data_cntrl = d_data_cntrl_int; + assign d_xfer_toggle_s = d_xfer_toggle_m3 ^ d_xfer_toggle_m2; + + always @(posedge d_clk or posedge d_rst) begin + if (d_rst == 1'b1) begin + d_xfer_toggle_m1 <= 'd0; + d_xfer_toggle_m2 <= 'd0; + d_xfer_toggle_m3 <= 'd0; + d_xfer_toggle <= 'd0; + d_data_cntrl_int <= 'd0; + end else begin + d_xfer_toggle_m1 <= up_xfer_toggle; + d_xfer_toggle_m2 <= d_xfer_toggle_m1; + d_xfer_toggle_m3 <= d_xfer_toggle_m2; + d_xfer_toggle <= d_xfer_toggle_m3; + if (d_xfer_toggle_s == 1'b1) begin + d_data_cntrl_int <= up_xfer_data; + end + end + end + +endmodule diff --git a/adi_library/common/up_xfer_status.v b/adi_library/common/up_xfer_status.v new file mode 100644 index 00000000..715082a1 --- /dev/null +++ b/adi_library/common/up_xfer_status.v @@ -0,0 +1,127 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module up_xfer_status #( + + parameter DATA_WIDTH = 8 +) ( + + // up interface + + input up_rstn, + input up_clk, + output [(DATA_WIDTH-1):0] up_data_status, + + // device interface + + input d_rst, + input d_clk, + input [(DATA_WIDTH-1):0] d_data_status +); + + // internal registers + + reg d_xfer_state_m1 = 'd0; + reg d_xfer_state_m2 = 'd0; + reg d_xfer_state = 'd0; + reg [ 5:0] d_xfer_count = 'd0; + reg d_xfer_toggle = 'd0; + reg [(DATA_WIDTH-1):0] d_xfer_data = 'd0; + reg [(DATA_WIDTH-1):0] d_acc_data = 'd0; + reg up_xfer_toggle_m1 = 'd0; + reg up_xfer_toggle_m2 = 'd0; + reg up_xfer_toggle_m3 = 'd0; + reg up_xfer_toggle = 'd0; + reg [(DATA_WIDTH-1):0] up_data_status_int = 'd0; + + // internal signals + + wire d_xfer_enable_s; + wire up_xfer_toggle_s; + + // device status transfer + + assign d_xfer_enable_s = d_xfer_state ^ d_xfer_toggle; + + always @(posedge d_clk or posedge d_rst) begin + if (d_rst == 1'b1) begin + d_xfer_state_m1 <= 'd0; + d_xfer_state_m2 <= 'd0; + d_xfer_state <= 'd0; + d_xfer_count <= 'd0; + d_xfer_toggle <= 'd0; + d_xfer_data <= 'd0; + d_acc_data <= 'd0; + end else begin + d_xfer_state_m1 <= up_xfer_toggle; + d_xfer_state_m2 <= d_xfer_state_m1; + d_xfer_state <= d_xfer_state_m2; + d_xfer_count <= d_xfer_count + 1'd1; + if ((d_xfer_count == 6'd1) && (d_xfer_enable_s == 1'b0)) begin + d_xfer_toggle <= ~d_xfer_toggle; + d_xfer_data <= d_acc_data; + end + if ((d_xfer_count == 6'd1) && (d_xfer_enable_s == 1'b0)) begin + d_acc_data <= d_data_status; + end else begin + d_acc_data <= d_acc_data | d_data_status; + end + end + end + + assign up_data_status = up_data_status_int; + assign up_xfer_toggle_s = up_xfer_toggle_m3 ^ up_xfer_toggle_m2; + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_xfer_toggle_m1 <= 'd0; + up_xfer_toggle_m2 <= 'd0; + up_xfer_toggle_m3 <= 'd0; + up_xfer_toggle <= 'd0; + up_data_status_int <= 'd0; + end else begin + up_xfer_toggle_m1 <= d_xfer_toggle; + up_xfer_toggle_m2 <= up_xfer_toggle_m1; + up_xfer_toggle_m3 <= up_xfer_toggle_m2; + up_xfer_toggle <= up_xfer_toggle_m3; + if (up_xfer_toggle_s == 1'b1) begin + up_data_status_int <= d_xfer_data; + end + end + end + +endmodule diff --git a/adi_library/common/util_axis_upscale.v b/adi_library/common/util_axis_upscale.v new file mode 100644 index 00000000..499d1f86 --- /dev/null +++ b/adi_library/common/util_axis_upscale.v @@ -0,0 +1,98 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// + A simple AXI stream data upscale module, which can be used with devices +// with resolution which can not be aligned to a WORD (32 bits). Eg. 24 bits +// + It has the same control interface as the ad_datafmt module, which controls +// the data format inside a generic AXI converter core. +// + Supports multiple channels. Contains a single register stage. + +`timescale 1ns/100ps + +module util_axis_upscale #( + + parameter NUM_OF_CHANNELS = 4, + parameter DATA_WIDTH = 24, + parameter UDATA_WIDTH = 32 +) ( + input clk, + input resetn, + + input s_axis_valid, + output reg s_axis_ready, + input [(NUM_OF_CHANNELS*DATA_WIDTH)-1:0] s_axis_data, + + output reg m_axis_valid, + input m_axis_ready, + output reg [(NUM_OF_CHANNELS*UDATA_WIDTH)-1:0] m_axis_data, + + input dfmt_enable, + input dfmt_type, + input dfmt_se +); + + wire type_s; + wire signext_s; + wire [(NUM_OF_CHANNELS*UDATA_WIDTH)-1:0] data_out_s; + + localparam MSB_WIDTH = UDATA_WIDTH - DATA_WIDTH; + + assign type_s = dfmt_enable & dfmt_type; + assign signext_s = dfmt_enable & dfmt_se; + + genvar i; + generate + for (i=1; i <= NUM_OF_CHANNELS; i=i+1) begin : signext_data + wire sign_s; + + assign sign_s = signext_s & (type_s ^ s_axis_data[(i*DATA_WIDTH-1)]); + assign data_out_s[(i*UDATA_WIDTH-1):(i*UDATA_WIDTH-MSB_WIDTH)] = {(MSB_WIDTH){sign_s}}; + assign data_out_s[((i-1)*UDATA_WIDTH+DATA_WIDTH-1)] = type_s ^ s_axis_data[(i*DATA_WIDTH-1)]; + assign data_out_s[((i-1)*UDATA_WIDTH+DATA_WIDTH-2):((i-1)*UDATA_WIDTH)] = s_axis_data[(i*DATA_WIDTH-2):((i-1)*DATA_WIDTH)]; + end + endgenerate + + always @(posedge clk) begin + if (resetn == 1'b0) begin + m_axis_valid <= 1'b0; + s_axis_ready <= 1'b0; + m_axis_data <= {(NUM_OF_CHANNELS*UDATA_WIDTH){1'b0}}; + end else begin + m_axis_valid <= s_axis_valid; + s_axis_ready <= m_axis_ready; + m_axis_data <= data_out_s; + end + end + +endmodule diff --git a/adi_library/common/util_dec256sinc24b.v b/adi_library/common/util_dec256sinc24b.v new file mode 100644 index 00000000..5754da24 --- /dev/null +++ b/adi_library/common/util_dec256sinc24b.v @@ -0,0 +1,205 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_dec256sinc24b ( + + input clk, /* used to clk filter */ + input reset, /* used to reset filter */ + input data_in, /* input data to be filtered */ + output reg [15:0] data_out, /* filtered output */ + output reg data_en, + input [15:0] dec_rate +); + + /* Data is read on positive clk edge */ + + reg [36:0] data_int = 37'h0; + reg [36:0] acc1 = 37'h0; + reg [36:0] acc2 = 37'h0; + reg [36:0] acc3 = 37'h0; + reg [36:0] acc3_d = 37'h0; + reg [36:0] diff1_d = 37'h0; + reg [36:0] diff2_d = 37'h0; + reg [15:0] word_count = 16'h0; + reg word_en = 1'b0; + reg enable = 1'b0; + + wire [36:0] acc1_s; + wire [36:0] acc2_s; + wire [36:0] acc3_s; + wire [36:0] diff1_s; + wire [36:0] diff2_s; + wire [36:0] diff3_s; + + /* Perform the Sinc action */ + + always @(data_in) begin + if (data_in==0) + data_int <= 37'd0; + else /* change 0 to a -1 for twos complement */ + data_int <= 37'd1; + end + + /* Accumulator (Integrator) Perform the accumulation (IIR) at the speed of + * the modulator. Z = one sample delay MCLKOUT = modulators conversion + * bit rate */ + + always @(negedge clk) begin + if (reset == 1'b1) begin + /* initialize acc registers on reset */ + acc1 <= 37'd0; + acc2 <= 37'd0; + acc3 <= 37'd0; + end else begin + /* perform accumulation process */ + acc1 <= acc1_s; + acc2 <= acc2_s; + acc3 <= acc3_s; + end + end + assign acc1_s = acc1 + data_int; + assign acc2_s = acc2 + acc1; + assign acc3_s = acc3 + acc2; + + /* decimation stage (MCLKOUT/WORD_CLK) */ + + always @(posedge clk) begin + if (reset == 1'b1) begin + word_count <= 16'd0; + end else begin + if (word_count == (dec_rate - 1)) + word_count <= 16'd0; + else + word_count <= word_count + 16'b1; + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + word_en <= 1'b0; + end else begin + if (word_count == (dec_rate/2 - 1)) + word_en <= 1'b1; + else + word_en <= 1'b0; + end + end + + /* Differentiator (including decimation stage) + * Perform the differentiation stage (FIR) at a lower speed. + * Z = one sample delay WORD_EN = output word rate */ + + always @(posedge clk) begin + if (reset == 1'b1) begin + diff1_d <= 37'd0; + diff2_d <= 37'd0; + acc3_d <= 37'b0; + end else if (word_en == 1'b1) begin + acc3_d <= acc3; + diff1_d <= diff1_s; + diff2_d <= diff2_s; + end + end + assign diff1_s = acc3_s - acc3; + assign diff2_s = diff1_s - diff1_d; + assign diff3_s = diff2_s - diff2_d; + + /* Clock the Sinc output into an output register + * WORD_EN = output word rate */ + + always @(posedge clk) begin + if (word_en == 1'b1) begin + case (dec_rate) + + 16'd32: begin + data_out <= (diff3_s[15:0] == 16'h8000) ? 16'hFFFF : {diff3_s[14:0], 1'b0}; + end + + 16'd64: begin + data_out <= (diff3_s[18:2] == 17'h10000) ? 16'hFFFF : diff3_s[17:2]; + end + + 16'd128: begin + data_out <= (diff3_s[21:5] == 17'h10000) ? 16'hFFFF : diff3_s[20:5]; + end + + 16'd256: begin + data_out <= (diff3_s[24:8] == 17'h10000) ? 16'hFFFF : diff3_s[23:8]; + end + + 16'd512: begin + data_out <= (diff3_s[27:11] == 17'h10000) ? 16'hFFFF : diff3_s[26:11]; + end + + 16'd1024: begin + data_out <= (diff3_s[30:14] == 17'h10000) ? 16'hFFFF : diff3_s[29:14]; + end + + 16'd2048: begin + data_out <= (diff3_s[33:17] == 17'h10000) ? 16'hFFFF : diff3_s[32:17]; + end + + 16'd4096: begin + data_out <= (diff3_s[36:20] == 17'h10000) ? 16'hFFFF : diff3_s[35:20]; + end + + default:begin + data_out <= (diff3_s[24:8] == 17'h10000) ? 16'hFFFF : diff3_s[23:8]; + end + endcase + end + end + + /* Synchronize Data Output */ + + always @(posedge clk) begin + if (reset == 1'b1) begin + data_en <= 1'b0; + enable <= 1'b1; + end else begin + if ((word_count == (dec_rate/2 - 1)) && (enable == 1'b1)) begin + data_en <= 1'b1; + enable <= 1'b0; + end else if ((word_count == (dec_rate - 1)) && (enable == 1'b0)) begin + data_en <= 1'b0; + enable <= 1'b1; + end else + data_en <= 1'b0; + end + end + +endmodule diff --git a/adi_library/common/util_delay.v b/adi_library/common/util_delay.v new file mode 100644 index 00000000..874049b6 --- /dev/null +++ b/adi_library/common/util_delay.v @@ -0,0 +1,75 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_delay #( + + parameter DATA_WIDTH = 1, + // the minimum valid value for DELAY_CYCLES is 1 + parameter DELAY_CYCLES = 1 +) ( + input clk, + input reset, + input din, + output [DATA_WIDTH-1:0] dout +); + + reg [DATA_WIDTH-1:0] dbuf[0:(DELAY_CYCLES-1)]; + + always @(posedge clk) begin + if (reset) begin + dbuf[0] <= 0; + end else begin + dbuf[0] <= din; + end + end + + generate + genvar i; + for (i = 1; i < DELAY_CYCLES; i=i+1) begin:register_pipe + always @(posedge clk) begin + if (reset) begin + dbuf[i] <= 0; + end else begin + dbuf[i] <= dbuf[i-1]; + end + end + end + endgenerate + + assign dout = dbuf[(DELAY_CYCLES-1)]; + +endmodule diff --git a/adi_library/common/util_ext_sync.v b/adi_library/common/util_ext_sync.v new file mode 100644 index 00000000..8c299bac --- /dev/null +++ b/adi_library/common/util_ext_sync.v @@ -0,0 +1,75 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_ext_sync #( + parameter ENABLED = 1 +) ( + input clk, + + input ext_sync_arm, + input ext_sync_disarm, + + input sync_in, + + output reg sync_armed = 1'b0 +); + + reg sync_in_d1 = 1'b0; + reg sync_in_d2 = 1'b0; + reg ext_sync_arm_d1 = 1'b0; + reg ext_sync_disarm_d1 = 1'b0; + + // External sync + always @(posedge clk) begin + ext_sync_arm_d1 <= ext_sync_arm; + ext_sync_disarm_d1 <= ext_sync_disarm; + + sync_in_d1 <= sync_in ; + sync_in_d2 <= sync_in_d1; + + if (ENABLED == 1'b0) begin + sync_armed <= 1'b0; + end else if (~ext_sync_disarm_d1 & ext_sync_disarm) begin + sync_armed <= 1'b0; + end else if (~ext_sync_arm_d1 & ext_sync_arm) begin + sync_armed <= 1'b1; + end else if (~sync_in_d2 & sync_in_d1) begin + sync_armed <= 1'b0; + end + end + +endmodule diff --git a/adi_library/common/util_pulse_gen.v b/adi_library/common/util_pulse_gen.v new file mode 100644 index 00000000..d323cec6 --- /dev/null +++ b/adi_library/common/util_pulse_gen.v @@ -0,0 +1,114 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +`timescale 1ns/1ps + +module util_pulse_gen #( + + parameter PULSE_WIDTH = 7, + parameter PULSE_PERIOD = 100000000 // t_period * clk_freq +) ( + input clk, + input rstn, + + input [31:0] pulse_width, + input [31:0] pulse_period, + input load_config, + + output reg pulse, + output [31:0] pulse_counter +); + + // internal registers + + reg [31:0] pulse_period_cnt = 32'h0; + reg [31:0] pulse_period_read = 32'b0; + reg [31:0] pulse_width_read = 32'b0; + reg [31:0] pulse_period_d = 32'b0; + reg [31:0] pulse_width_d = 32'b0; + + // flop the desired period + + always @(posedge clk) begin + if (rstn == 1'b0) begin + if (PULSE_PERIOD == 'd0) begin + pulse_period_d <= 32'h1; + pulse_period_read <= 32'h1; + end else begin + pulse_period_d <= PULSE_PERIOD; + pulse_period_read <= PULSE_PERIOD; + end + pulse_width_d <= PULSE_WIDTH; + pulse_width_read <= PULSE_WIDTH; + end else begin + // latch the input period/width values + if (load_config) begin + if (pulse_period == 'd0) begin + pulse_period_read <= 32'h1; + end else begin + pulse_period_read <= pulse_period; + end + pulse_width_read <= pulse_width; + end + // update the current period/width at the end of the period + if (pulse_period_cnt == 32'h1) begin + pulse_period_d <= pulse_period_read; + pulse_width_d <= pulse_width_read; + end + end + end + + // a free running counter + + always @(posedge clk) begin + if (pulse_period_cnt == 'b0) begin + pulse_period_cnt <= pulse_period_d; + end else begin + pulse_period_cnt <= pulse_period_cnt - 32'b1; + end + end + + // generate pulse with a specified width + + always @ (posedge clk) begin + if ((pulse_period_cnt == 'h0) || (rstn == 1'b0)) begin + pulse <= 1'b0; + end else if (pulse_period_cnt == pulse_width_d) begin + pulse <= 1'b1; + end + end + + assign pulse_counter = pulse_period_cnt; + +endmodule diff --git a/adi_library/cordic_demod/Makefile b/adi_library/cordic_demod/Makefile new file mode 100644 index 00000000..95a5ae05 --- /dev/null +++ b/adi_library/cordic_demod/Makefile @@ -0,0 +1,13 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := cordic_demod + +GENERIC_DEPS += cordic_demod.v + +XILINX_DEPS += cordic_demod_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/cordic_demod/component.xml b/adi_library/cordic_demod/component.xml new file mode 100644 index 00000000..0f767537 --- /dev/null +++ b/adi_library/cordic_demod/component.xml @@ -0,0 +1,370 @@ + + + analog.com + user + cordic_demod + 1.0 + + + S_AXIS + + + + + + + TVALID + + + s_axis_valid + + + + + TREADY + + + s_axis_ready + + + + + TDATA + + + s_axis_data + + + + + + M_AXIS + + + + + + + TVALID + + + m_axis_valid + + + + + TREADY + + + m_axis_ready + + + + + TDATA + + + m_axis_data + + + + + + S_AXIS_M_AXIS_signal_clock + S_AXIS_M_AXIS_signal_clock + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_BUSIF + S_AXIS:M_AXIS + + + ASSOCIATED_RESET + resetn + + + + + S_AXIS_M_AXIS_signal_reset + S_AXIS_M_AXIS_signal_reset + + + + + + + RST + + + resetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + cordic_demod + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + e206c42f + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + cordic_demod + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + e206c42f + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f92e9879 + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + resetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_data + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_data + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + xilinx_anylanguagesynthesis_view_fileset + + cordic_demod.v + verilogSource + CHECKSUM_e206c42f + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + cordic_demod.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/cordic_demod_v1_0.tcl + tclSource + CHECKSUM_f92e9879 + XGUI_VERSION_2 + + + + cordic_demod_v1_0 + + + Component_Name + cordic_demod_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + cordic_demod_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:49:54Z + + + 2023.2.1 + + + + + + diff --git a/adi_library/cordic_demod/cordic_demod.v b/adi_library/cordic_demod/cordic_demod.v new file mode 100644 index 00000000..809cabc8 --- /dev/null +++ b/adi_library/cordic_demod/cordic_demod.v @@ -0,0 +1,205 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module cordic_demod ( + input clk, + input resetn, + + input s_axis_valid, + output s_axis_ready, + input [63:0] s_axis_data, + + output m_axis_valid, + input m_axis_ready, + output [63:0] m_axis_data +); + + reg [4:0] step_counter; + reg [4:0] shift_counter; + reg [30:0] phase; + reg [2:0] state; + + reg [32:0] i; + reg [32:0] q; + reg [32:0] i_shift; + reg [32:0] q_shift; + + assign s_axis_ready = state == STATE_IDLE; + assign m_axis_data = {q[32:1],i[32:1]}; + assign m_axis_valid = state == STATE_DONE; + + localparam STATE_IDLE = 0; + localparam STATE_SHIFT_LOAD = 1; + localparam STATE_SHIFT = 2; + localparam STATE_ADD = 3; + localparam STATE_DONE = 4; + + reg [31:0] angle[0:30]; + + initial begin + angle[0] = 32'h20000000; + angle[1] = 32'h12e4051e; + angle[2] = 32'h09fb385b; + angle[3] = 32'h051111d4; + angle[4] = 32'h028b0d43; + angle[5] = 32'h0145d7e1; + angle[6] = 32'h00a2f61e; + angle[7] = 32'h00517c55; + angle[8] = 32'h0028be53; + angle[9] = 32'h00145f2f; + angle[10] = 32'h000a2f98; + angle[11] = 32'h000517cc; + angle[12] = 32'h00028be6; + angle[13] = 32'h000145f3; + angle[14] = 32'h0000a2fa; + angle[15] = 32'h0000517d; + angle[16] = 32'h000028be; + angle[17] = 32'h0000145f; + angle[18] = 32'h00000a30; + angle[19] = 32'h00000518; + angle[20] = 32'h0000028c; + angle[21] = 32'h00000146; + angle[22] = 32'h000000a3; + angle[23] = 32'h00000051; + angle[24] = 32'h00000029; + angle[25] = 32'h00000014; + angle[26] = 32'h0000000a; + angle[27] = 32'h00000005; + angle[28] = 32'h00000003; + angle[29] = 32'h00000001; + angle[30] = 32'h00000001; + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + state <= STATE_IDLE; + end else begin + case (state) + STATE_IDLE: begin + if (s_axis_valid == 1'b1) begin + state <= STATE_SHIFT_LOAD; + end + end + STATE_SHIFT_LOAD: begin + if (step_counter == 'h00) begin + state <= STATE_ADD; + end else begin + state <= STATE_SHIFT; + end + end + STATE_SHIFT: begin + if (shift_counter == 'h01) begin + state <= STATE_ADD; + end + end + STATE_ADD: begin + if (step_counter == 'd30) begin + state <= STATE_DONE; + end else begin + state <= STATE_SHIFT_LOAD; + end + end + STATE_DONE: begin + if (m_axis_ready == 1'b1) + state <= STATE_IDLE; + end + endcase + end + end + + always @(posedge clk) begin + case(state) + STATE_SHIFT_LOAD: begin + shift_counter <= step_counter; + end + STATE_SHIFT: begin + shift_counter <= shift_counter - 1'b1; + end + endcase + end + + always @(posedge clk) + begin + case(state) + STATE_IDLE: + if (s_axis_valid == 1'b1) begin + step_counter <= 'h00; + phase <= {1'b0,s_axis_data[61:32]}; + step_counter <= 'h00; + case (s_axis_data[63:62]) + 2'b00: begin + i <= {s_axis_data[31],s_axis_data[31:0]}; + q <= 'h00; + end + 2'b01: begin + i <= 'h00; + q <= ~{s_axis_data[31],s_axis_data[31:0]}; + end + 2'b10: begin + i <= ~{s_axis_data[31],s_axis_data[31:0]}; + q <= 'h00; + end + 2'b11: begin + i <= 'h00; + q <= {s_axis_data[31],s_axis_data[31:0]}; + end + endcase + end + STATE_SHIFT_LOAD: begin + i_shift <= i; + q_shift <= q; + end + STATE_SHIFT: begin + i_shift <= {i_shift[32],i_shift[32:1]}; + q_shift <= {q_shift[32],q_shift[32:1]}; + end + STATE_ADD: begin + if (phase[30] == 1'b0) begin + i <= i + q_shift; + q <= q - i_shift; + phase <= phase - angle[step_counter]; + end else begin + i <= i - q_shift; + q <= q + i_shift; + phase <= phase + angle[step_counter]; + end + step_counter <= step_counter + 1'b1; + end + endcase + end + +endmodule diff --git a/adi_library/cordic_demod/cordic_demod.xpr b/adi_library/cordic_demod/cordic_demod.xpr new file mode 100644 index 00000000..1556724f --- /dev/null +++ b/adi_library/cordic_demod/cordic_demod.xpr @@ -0,0 +1,399 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/cordic_demod/cordic_demod_ip.tcl b/adi_library/cordic_demod/cordic_demod_ip.tcl new file mode 100644 index 00000000..552bf9c4 --- /dev/null +++ b/adi_library/cordic_demod/cordic_demod_ip.tcl @@ -0,0 +1,36 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create cordic_demod +adi_ip_files cordic_demod [list \ + "cordic_demod.v" \ +] + +adi_ip_properties_lite cordic_demod + +adi_add_bus "S_AXIS" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"s_axis_valid" "TVALID"} \ + {"s_axis_ready" "TREADY"} \ + {"s_axis_data" "TDATA"} \ + } + +adi_add_bus "M_AXIS" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"m_axis_valid" "TVALID"} \ + {"m_axis_ready" "TREADY"} \ + {"m_axis_data" "TDATA"} \ + } + +adi_add_bus_clock "clk" "S_AXIS:M_AXIS" "resetn" + +ipx::save_core [ipx::current_core] diff --git a/adi_library/cordic_demod/xgui/cordic_demod_v1_0.tcl b/adi_library/cordic_demod/xgui/cordic_demod_v1_0.tcl new file mode 100644 index 00000000..0db18e9a --- /dev/null +++ b/adi_library/cordic_demod/xgui/cordic_demod_v1_0.tcl @@ -0,0 +1,10 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + + diff --git a/adi_library/data_offload/Makefile b/adi_library/data_offload/Makefile new file mode 100644 index 00000000..a51ee2be --- /dev/null +++ b/adi_library/data_offload/Makefile @@ -0,0 +1,27 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := data_offload + +GENERIC_DEPS += ../common/ad_axis_inf_rx.v +GENERIC_DEPS += ../common/ad_mem_asym.v +GENERIC_DEPS += ../common/up_axi.v +GENERIC_DEPS += data_offload.v +GENERIC_DEPS += data_offload_fsm.v +GENERIC_DEPS += data_offload_regmap.v + +XILINX_DEPS += data_offload_ip.tcl +XILINX_DEPS += data_offload_sv.ttcl + +XILINX_DEPS += ../interfaces/if_do_ctrl.xml +XILINX_DEPS += ../interfaces/if_do_ctrl_rtl.xml + +XILINX_LIB_DEPS += util_axis_fifo_asym +XILINX_LIB_DEPS += util_cdc + +XILINX_INTERFACE_DEPS += interfaces + +include ../scripts/library.mk diff --git a/adi_library/data_offload/README.md b/adi_library/data_offload/README.md new file mode 100644 index 00000000..1e7e77d4 --- /dev/null +++ b/adi_library/data_offload/README.md @@ -0,0 +1,392 @@ + +# Data offload IP core + +## Description, general use cases + +Data offload module for high-speed converters: + +**NOTE**: This IP will always have a storage unit (internal or external to the FPGA) and is +designed to handle high data rates. If your data paths will run in a lower data +rate, and your intention is just to transfer the data to another clock domain or +to adjust the bus width of the data path, you may want to check out the util_axis_fifo or +util_axis_fifo_asym IPs. + +The initialization and data transfer looks as follows: + + * in case of DAC, the DMA initialize the storage unit, after that the controller +will push the data to the DAC interface in one-shot or cyclic way + + * in case of ADC, the DMA request a transfer, the controller will save the data into +the storage unit, after that will push it to the DMA + + * BYPASS mode: simple streaming FIFO in case of clock rate or data width differences +between source and sink interfaces (data rate MUST match in order to work); the BYPASS +mode is used when an initially high rate path is downgraded to lower rates. + +## Table of content + + * [Block diagrams](README.md#block-diagram) + * [Parameters](README.md#parameters) + * [Interfaces](README.md#interfaces) + * [Register map](README.md#register-map) + * [Clock tree](README.md#clock-tree) + * [Data path](README.md#data-path) + * [Control path](README.md#control-path-offload-fsm) + +## Generic arhitecture + +The main role of our data paths, is to stream data from point A to point B +in a particular system. There are always a SOURCE and a DESTINATION +point, which can be a device (ADC or DAC), a DMA (for system memory) or any other +data processing IP. + +In the context of Data Offload IP, we don't need to know who is the source and +who is the destination. Both interface is a AXI4 Stream interface, which can be +supported in both Xilinx's an Intel's architecture, and can be connected to any device +core or DMA. + +The storage unit is connected to the Data Offload controller via two FIFO interface. +This way the same controller can be used for various storage solutions. (BRAM, +URAM, external memory etc.) + +## Block diagram + +![Generic Block Diagram](./docs/generic_bd.svg) + +## Parameters + +| NAME | TYPE | DEFAULT | DESCRIPTION | +|----------------------|:-----------:|:----------:|:---------------------------:| +|ID | integer | 0 | Instance ID number | +|MEM_TYPE | [ 0:0] | 0 | Define the used storage type: FPGA RAM - 0; external DDR - 1 | +|MEM_SIZE_LOG2 | integer | 10 | Log2 value of storage size, defines the width of transfer length control signals. | +|TX_OR_RXN_PATH | [ 0:0] | 1 | If set TX path enabled, otherwise RX | +|SRC_DATA_WIDTH | integer | 64 | The data width of the source interface | +|DST_DATA_WIDTH | integer | 124 | The data width of the destination interface | +|DST_CYCLIC_EN | [ 0:0] | 0 | Enables CYCLIC mode for destinations like DAC | +|AUTO_BRINGUP | [ 0:0] | 1 | If enabled the IP runs automatically after bootup | +|SYNC_EXT_ADD_INTERNAL_CDC | [ 0:0] | 1 | If enabled the external sync pin is synchronized to the internal clock domain with a CDC. | +|HAS_BYPASS | [ 0:0] | 1 | If set to zero the bypass FIFO is not implemented. | + +## Interfaces + +### AXI4 Lite Memory Mapped Slave (S_AXI4_LITE) + +This interface is used to access the register map. + +```verilog +// interface clock -- system clock -- 100 MHz +input s_axi_aclk +// interface resetn -- synchronous reset active low +input s_axi_aresetn + +/* write address channel */ + +// validates the address on the bus +input s_axi_awvalid +// write address +input [15:0] s_axi_awaddr +// protection type -- not used in the core +input [ 2:0] s_axi_awprot +// write ready, indicates that the slave can accept the address +output s_axi_awready + +/* write data channel */ + +// validate the data on the bus +input s_axi_wvalid +// write data +input [31:0] s_axi_wdata +// write strobe, indicates which byte lanes to update +input [ 3:0] s_axi_wstrb +// write ready, indicates that the slave can accept the data +output s_axi_wready + +/* write response channel */ + +// validates the write response of the slave +output s_axi_bvalid +// write response, indicate the status of the transfer +output [ 1:0] s_axi_bresp +// response ready, indicates that the master can accept the data +input s_axi_bready + +/* read address channel */ + +// validates the address on the bus +input s_axi_arvalid +// read address +input [15:0] s_axi_araddr +// protection type -- not used in the core +input [ 2:0] s_axi_arprot +// read ready, indicates that the slave can accept the address +output s_axi_arready + +/* read data channel */ + +// validate the data on the bus +output s_axi_rvalid +// read response, indicate the status of the transfer +output [ 1:0] s_axi_rresp +// read data drivers by the slave +output [31:0] s_axi_rdata +// read ready, indicates that the master can accept the data +input s_axi_rready +``` + +### Supported data interfaces + +**NOTE**: To simplify the design both the source and destination data interface is +an AXI4 streaming interface. A FIFO write (ADC) interface can be treated as AXI4 +stream where only the master controls the data rate (s_axis_ready is always asserted), +and a FIFO read (DAC) interface can be treated as an AXI4 stream where only the slave +controls the data rate. (m_axis_valid is always asserted). + +#### AXI4 Stream interface (S_AXIS | M_AXIS) + +* The AXI Stream Slave (S_AXIS) interface is used to receive AXI stream from +the transmit DMA or ADC device. + +* The AXI Stream Master (M_AXIS) interface is used to transmit AXI stream +to receive DMA or DAC device + +```verilog +// NOTE: this reference is a master interface + +// interface clock -- can be device/core clock or DMA clock +input m_axis_aclk +// interface resetn -- synchronous reset with the system clock +input m_axis_resetn +// indicates that the slave can accept a transfer in the current cycle (in case of an ADC core, this will control the stream) +input m_axis_ready +// indicates that the master is driving a valid transfer +output m_axis_valid +// primary payload +output [DATA_WIDTH-1:0] m_axis_data +// indicates the boundary of a packet +output m_axis_last +// byte qualifier, we need this so we can have different DMA and device data widths +output [(DATA_WIDTH/8)-1:0] m_axis_tkeep +``` + +**NOTE**: A packet will always be a full buffer. All the data beats going to be +full beats (all the bytes of the bus are valid), except the last one. **axis_last** +and **axis_tkeep** will be used to indicate a partial last beat. This information +should be transferred from the source domain to the sink domain, so we can read +back the data from memory correctly. + +#### AXIS source and destination interface to the storage unit + +This is blocking (back-pressure) interface for the storage unit, +with similar behavior of main AXIS data interfaces. + +### Initialization request interface + +Define a simple request interface to initialize the memory: + + * The request will comes from the system and will put the data offload FSM +into a standby/ready state. + + +#### Synchronization modes + + * **AUTOMATIC** + * ADC: The IP will start to fill up the buffer with samples as soon as possible. + * DAC: As the DMA will send a valid last, the FSM will start to send the +stored data to the device. + + * **HARDWARE** + * ADC and DAC: An external signal will trigger the write or read into or from +the memory. + * **NOTE**: In case of DAC, if the DMA does not sent all the data into the +buffer, before a hardware sync event, the unsent data will be ignored. It's the +user/software responsibility to sync up these events accordingly. + + * **SOFTWARE** + * The software write a RW1C register which will trigger the reads or writes +into or from the memory. + +## Register Map + +| WORD | BYTE | BITS | NAME | TYPE | CLOCK DOMAIN | DESCRIPTION | +|-------:|:--------:|:--------:|:---------------------:|:-----:|:------------:|:-----------------------:| +| 0x0000 | 0x0000 | | `VERSION` | RO | SYS | Version number | +| | | [31:16] | `MAJOR` | | | | +| | | [15: 8] | `MINOR` | | | | +| | | [ 7: 0] | `PATCH` | | | | +| 0x0001 | 0x0004 | | `PERIPHERAL_ID` | RO | SYS | Value of the IP configuration parameter | +| 0x0002 | 0x0008 | | `SCRATCH` | RW | SYS | Scratch register | +| 0x0003 | 0x000C | | `IDENTIFICATION` | RO | SYS | Peripheral identification. Default value: 0x44414F46 - ('D','A','O','F') | +| 0x0004 | 0x0010 | | `SYNTHESIS_CONFIG` | RO | SYS | Core configuration registers | +| | | [13: 8] | `MEM_SIZE_LOG2` | | | Log2 of memory size in bytes | +| | | [ 2: 2] | `HAS_BYPASS` | | | If not set the bypass logic is not implemented. | +| | | [ 1: 1] | `TX_OR_RXN_PATH` | | | RX Path => 0, TX => 1 | +| | | [ 0: 0] | `MEMORY_TYPE` | | | The used storage type (embedded => 0 or external => 1) | +| 0x0007 | 0x001C | | `TRANSFER_LENGTH` | RW | SRC | Transfer length | +| 0x0020 | 0x0080 | | `MEM_PHY_STATE` | RO | DDR | Status bits of the memory controller IP | +| | | [ 5: 5] | `UNDERFLOW` | RW1C | | Indicates that storage could not handle data rate during play. Available when core is in TX mode.| +| | | [ 4: 4] | `OVERFLOW` | RW1C | | Indicates that storage could not handle data rate during capture. Available when core is in RX mode. | +| | | [ 0: 0] | `CALIB_COMPLETE` | | | Indicates that the memory initialization and calibration have completed successfully | +| 0x0021 | 0x0084 | | `RESETN_OFFLOAD` | RW | DST/SRC | Reset all the internal address registers and state machines | +| | | [ 0: 0] | `RESETN` | | | | +| 0x0022 | 0x0088 | | `CONTROL` | RW | DST | A global control register | +| | | [ 1: 1] | `ONESHOT_EN` | | | By default the TX path runs on CYCLIC mode, set this bit to switch it to ONE-SHOT mode | +| | | [ 0: 0] | `OFFLOAD_BYPASS` | | | Bypass the offload storage, the data path consist just of a CDC FIFO | +| 0x0040 | 0x0100 | | `SYNC_TRIGGER` | RW1C | SRC | Synchronization setup for RX and TX path | +| | | [ 0: 0] | `SYNC_TRIGGER` | | | Trigger the data capture | +| 0x0041 | 0x0104 | | `SYNC_CONFIG` | RW | SRC | Synchronization setup | +| | | [ 1: 0] | `SYNC_CONFIG` | | | Auto - '0'; hardware - '1'; software - '2' | +| 0x0080 | 0x0200 | | `FSM_DBG` | RO | | Debug register for the offload FSM | +| | | [11: 8] | `FSM_STATE_READ` | | SRC | The current state of the read-offload state machine | +| | | [ 4: 0] | `FSM_STATE_WRITE` | | DST | The current state of the write-offload state machine | + +## Clock tree + +In general there are at least two different clock in the data offload module: + + * DMA or system clock : on this clock will run all the front end interfaces + * Memory Controller user clock : user interface clock of the DDRx controller (**optional**) + * Device clock : the digital interface clock of the converter + +![Clocks](./docs/clocks.svg) + +A general frequency relationship of the above clocks are: + +``` + CLKdma <= CLKddr <= CLKconverter +``` + +The clock domain crossing should be handled by the [util_axis_fifo](https://github.com/analogdevicesinc/hdl/tree/master/library/util_axis_fifo) module. + * **TODO** : Make sure that we support both AXIS and FIFO + * **TODO** : Add support for asymmetric aspect ratio. + +All the back end paths (device side) are time critical. The module must read or +write from or into the storage at the speed of the device. + +``` + DDR data rate >= Device data rate + DDR data rate >= ADC data rate + DAC data rate +``` + +## Data path + +![Data path](./docs/datapath.svg) + + * The data path should be designed to support any kind of difference between +the source, memory and sink data width. + + * The data width adjustments will be made by the CDC_FIFO. + + * In both path (ADC and DAC) the data stream at the front-end side is packatized, +meaning there is a valid TLAS/TKEEP in the stream. While in the back-end side +the stream is continuous. (no TLAST/TKEEP) + * The DAC path have to have a depacketizer to get rid of the last partial beat +from the stream. + * Because the ADC path already arrive in a packed form, and we always will +fill up the whole storage, we don't need to treat special use-cases. + +### Used storage elements + +| | ZC706 | ZCU102 | A10SOC | +|:----------------------|:------------------:|:-----------------:|:----------------:| +| FPGA | XC7Z045 FFG900 – 2 | XCZU9EG-2FFVB1156 | 10AS066N3F40E2SG | +| External Memory Type | DDR3 SODIMM | DDR4 | DDR4 HILO | +| External Memory Size | 1 GB | 512 MB | 2 GB | +| Embedded Memory Type | BRAM | BRAM | M20K | +| Embedded Memory Size | 19.1 Mb | 32.1 Mb | 41 Mb | + +### Data width manipulation + +* data width differences should be treated by the CDC FIFO + +* the smallest granularity should be 8 bits. This constraints mainly will generate +additional logic just in the TX path, taking the fact that the data from the ADC +will come packed. + +* the gearbox main role is to improve the DDR's bandwidth, strips the padding bits +of each samples, so the raw data could be stored into the memory. + +### Xilinx's MIG vs. Intel's EMIF + +* Incrementing burst support for 1 to 256 beats, the length of the burst should +be defined by the internal controller + +* Concurrent read/write access, the external memory to be shared between an ADC +and DAC +* Dynamic burst length tuning: an FSM reads and writes dummy data until both +ADC's overflow and DAC's underflow lines are de-asserted. Pre-requisites : both +device's interface should be up and running. + +* **TODO**: prefetch the next transfer if it's possible, by driving the address channels ahead (e.g. Overlapping read burst in case of AXI4) + +* Optional gearbox to congest the samples in order to increase the maximum data rate. +* In general we packing all samples into 16 bits. This can add a significant +overhand to the maximum real data rate on the memory interface. The gearbox main +role is to pack and unpack the device's samples into the required data width. (in general 512 or 1024 bit) + +Boards with FPGA side DDR3/4 SODIMMs/HILO: ZC706, ZCU102, A10SOC + +| | ZC706 | ZCU102 | A10SOC | +|------------------------------|:---------:|:----------:|:----------:| +| Max data throughputs (MT/s) | 1600 | 2400 | 2133 | +| DDRx reference clocks | 200 MHz | 300 MHz | 133 MHz | +| DDRx Data bus width | 64 | 16 | 64 | +| Memory to FPGA clock ratio | 4:1 | 4:1 | 4:1 | +| UI type & burst length | AXI4-256 | AXI4-256 | Avalon Memory Map | +| UI data width | 512 | 128 | 512 | + +### Internal cyclic buffer support for the TX path + +![Data path with external storage](./docs/architecture_DDR.svg) + +* On the front end side if the TX path, a special buffer will handle the data +width up/down conversions and run in cyclic mode if the length of the data set +is smaller than 4/8 AXI/Avalon burst. This way we can avoid to overload the memory +interface with small bursts. + +* On the back end side, because the smallest granularity can be 8 bytes, we need +a dynamic 'depackatizer' or re-aligner, which will filter out the invalid data +bytes from the data stream. (this module will use the tlast and tkeep signal of +the AXI stream interface) + +## Control path - Offload FSM + +### RX control FSM for internal RAM mode + +![RX_control FMS for internal RAM mode](./docs/rx_bram_fsm.svg) + +### TX control FSM for internal RAM mode + +![TX_control FMS for internal RAM mode](./docs/tx_bram_fsm.svg) + +**TODO** FSMs for the external DDR mode + +## References + +### AMBA AXI + * [AMBA specification](http://infocenter.arm.com/help/topic/com.arm.doc.set.amba/index.html#specs) + * [UG761 AXI Reference Guide](https://www.xilinx.com/support/documentation/ip_documentation/ug761_axi_reference_guide.pdf) + +### Avalon + * [Avalon Interface Specification](https://www.altera.com/en_US/pdfs/literature/manual/mnl_avalon_spec.pdf) + +### Xilinx + * [Device Memory Interface Solutions](https://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v4_2/ds176_7Series_MIS.pdf) + * [Device Memory Interface Solutions User Guide](https://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v4_2/ug586_7Series_MIS.pdf) + * [Ultrascale Architecutre-Based FPGAs Memory IP (v1.4)](https://www.xilinx.com/support/documentation/ip_documentation/ultrascale_memory_ip/v1_4/pg150-ultrascale-memory-ip.pdf) + * [Xilinx FIFO Generator](https://www.xilinx.com/products/intellectual-property/fifo_generator.html#documentation) + * [7 Series FPGAs Memory Resources](https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf) + * [Ultrascale Memory Resources](https://www.xilinx.com/support/documentation/user_guides/ug573-ultrascale-memory-resources.pdf) + +### Intel + * [Intel Arria 10 Core Fabric and General Purpose I/Os Handbook](https://www.altera.com/en_US/pdfs/literature/hb/arria-10/a10_handbook.pdf) + * [Intel Arria 10 External Memory Interface IP User Guide](https://www.altera.com/en_US/pdfs/literature/ug/ug-20115.pdf) + * [Intel Arria 10 External Memory Interface IP Design Example](https://www.altera.com/en_US/pdfs/literature/ug/ug-20118.pdf) + * [Intel SCFIFO and DCFIFO](https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_fifo.pdf) + * [Intel Startix 10 High-Performance Design Handbook](https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/stratix-10/s10_hp_hb.pdf) + * [Intel Stratix 10 Embedded Memory User Guide](https://www.altera.com/en_US/pdfs/literature/hb/stratix-10/ug-s10-memory.pdf) + +### Supported FPGA boards + * [ZC706](https://www.xilinx.com/products/boards-and-kits/ek-z7-zc706-g.html) + * [ZCU102](https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html) + * [A10SOC](https://www.altera.com/products/boards_and_kits/dev-kits/altera/arria-10-soc-development-kit.html) diff --git a/adi_library/data_offload/component.xml b/adi_library/data_offload/component.xml new file mode 100644 index 00000000..f6483d19 --- /dev/null +++ b/adi_library/data_offload/component.xml @@ -0,0 +1,1961 @@ + + + analog.com + user + data_offload + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + m_axis + + + + + + + TREADY + + + m_axis_ready + + + + + TVALID + + + m_axis_valid + + + + + TDATA + + + m_axis_data + + + + + TLAST + + + m_axis_last + + + + + TKEEP + + + m_axis_tkeep + + + + + + s_axis + + + + + + + TREADY + + + s_axis_ready + + + + + TVALID + + + s_axis_valid + + + + + TDATA + + + s_axis_data + + + + + TLAST + + + s_axis_last + + + + + TKEEP + + + s_axis_tkeep + + + + + + wr_ctrl + + + + + + + request_enable + + + wr_request_enable + + + + + request_valid + + + wr_request_valid + + + + + request_ready + + + wr_request_ready + + + + + request_length + + + wr_request_length + + + + + response_measured_length + + + wr_response_measured_length + + + + + response_eot + + + wr_response_eot + + + + + status_overflow + + + wr_overflow + + + + + + rd_ctrl + + + + + + + request_enable + + + rd_request_enable + + + + + request_valid + + + rd_request_valid + + + + + request_ready + + + rd_request_ready + + + + + request_length + + + rd_request_length + + + + + response_eot + + + rd_response_eot + + + + + status_underflow + + + rd_underflow + + + + + + s_storage_axis + + + + + + + TREADY + + + s_storage_axis_ready + + + + + TVALID + + + s_storage_axis_valid + + + + + TDATA + + + s_storage_axis_data + + + + + TKEEP + + + s_storage_axis_tkeep + + + + + TLAST + + + s_storage_axis_last + + + + + + m_storage_axis + + + + + + + TREADY + + + m_storage_axis_ready + + + + + TVALID + + + m_storage_axis_valid + + + + + TDATA + + + m_storage_axis_data + + + + + TKEEP + + + m_storage_axis_tkeep + + + + + TLAST + + + m_storage_axis_last + + + + + + s_storage_axis_m_axis_signal_clock + s_storage_axis_m_axis_signal_clock + + + + + + + CLK + + + m_axis_aclk + + + + + + ASSOCIATED_BUSIF + s_storage_axis:m_axis + + + ASSOCIATED_RESET + m_axis_aresetn + + + + + s_storage_axis_m_axis_signal_reset + s_storage_axis_m_axis_signal_reset + + + + + + + RST + + + m_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + m_storage_axis_s_axis_signal_clock + m_storage_axis_s_axis_signal_clock + + + + + + + CLK + + + s_axis_aclk + + + + + + ASSOCIATED_BUSIF + m_storage_axis:s_axis + + + ASSOCIATED_RESET + s_axis_aresetn + + + + + m_storage_axis_s_axis_signal_reset + m_storage_axis_s_axis_signal_reset + + + + + + + RST + + + s_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + data_offload + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_analog_com_user_util_axis_fifo_asym_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + ceadfd38 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + data_offload + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_axis_fifo_asym_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + ceadfd38 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_xpgui_analog_com_user_util_axis_fifo_asym_1_0__ref_view_fileset + + + xilinx_xpgui_view_fileset + + + + viewChecksum + 68aed832 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + 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+ + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + wr_request_length + + out + + 9 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + wr_response_measured_length + + in + + 9 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + wr_response_eot + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + wr_overflow + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + rd_request_enable + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rd_request_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rd_request_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rd_request_length + + out + + 9 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rd_response_eot + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rd_underflow + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + ddr_calib_done + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + + + ID + Id + 0 + + + MEM_TYPE + Mem Type + 0 + + + MEM_SIZE_LOG2 + Mem Size Log2 + 10 + + + TX_OR_RXN_PATH + Tx Or Rxn Path + 0 + + + SRC_DATA_WIDTH + Src Data Width + 64 + + + DST_DATA_WIDTH + Dst Data Width + 128 + + + DST_CYCLIC_EN + Dst Cyclic En + true + + + + false + + + + + + AUTO_BRINGUP + Auto Bringup + 1 + + + SYNC_EXT_ADD_INTERNAL_CDC + Sync Ext Add Internal Cdc + true + + + HAS_BYPASS + Has Bypass + true + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_42f127d3 + 0 + 1 + + + choice_pairs_68d17ab3 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + 21 + 22 + 23 + 24 + 25 + 26 + 27 + 28 + 29 + 30 + 31 + 32 + 33 + 34 + + + choice_pairs_f3e4b7dc + 0 + 1 + + + + + xilinx_anylanguagesynthesis_view_fileset + + data_offload_constr.ttcl + ttcl + + + data_offload_fsm.v + verilogSource + + + data_offload_regmap.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + data_offload.v + verilogSource + CHECKSUM_899431db + + + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_analog_com_user_util_axis_fifo_asym_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + data_offload_sv.ttcl + ttcl + + + data_offload_fsm.v + verilogSource + + + data_offload_regmap.v + verilogSource + + + ../common/up_axi.v + verilogSource + + + data_offload.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_axis_fifo_asym_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/data_offload_v1_0.tcl + tclSource + CHECKSUM_9dc0c6aa + XGUI_VERSION_2 + + + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + xilinx_xpgui_analog_com_user_util_axis_fifo_asym_1_0__ref_view_fileset + + + + + + + + xilinx_utilityxitfiles_view_fileset + + gui/data_offload_v1_0.gtcl + GTCL + + + + ADI Data Offload Controller + + + ID + Core ID + 0 + + + MEM_TYPE + Storage Type + 0 + + + MEM_SIZE_LOG2 + Storage Size + 10 + + + TX_OR_RXN_PATH + Data path type + 0 + + + SRC_DATA_WIDTH + Source Interface data width + 64 + + + DST_DATA_WIDTH + Destination Interface data width + 128 + + + DST_CYCLIC_EN + Destination Cyclic Mode Enabled + true + + + + false + + + + + + AUTO_BRINGUP + Auto Bringup + 1 + + + SYNC_EXT_ADD_INTERNAL_CDC + Generate CDC Circuit for sync_ext + true + + + HAS_BYPASS + Internal Bypass Data Path Enabled + true + + + Component_Name + data_offload_v1_0 + + + + + + virtex7 + + + /Analog_Devices + + ADI Data Offload Controller + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:50:18Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/data_offload/data_offload.v b/adi_library/data_offload/data_offload.v new file mode 100644 index 00000000..1e1aed83 --- /dev/null +++ b/adi_library/data_offload/data_offload.v @@ -0,0 +1,384 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +`timescale 1ns / 1ps + +module data_offload #( + + parameter ID = 0, + parameter MEM_TYPE = 0, // 1'b0 -FPGA RAM; 1'b1 - external memory + parameter MEM_SIZE_LOG2 = 10, // log2 of memory size in bytes + + parameter TX_OR_RXN_PATH = 0, // if set IP is used in TX path, other wise in RX path + + parameter SRC_DATA_WIDTH = 64, + + parameter DST_DATA_WIDTH = 128, + parameter DST_CYCLIC_EN = 1'b0, // 1'b1 - CYCLIC mode enabled; 1'b0 - CYCLIC mode disabled + + parameter AUTO_BRINGUP = 1, + parameter SYNC_EXT_ADD_INTERNAL_CDC = 1, + parameter HAS_BYPASS = 1 +) ( + + // AXI4 Slave for configuration + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + input s_axi_rready, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + + // AXI4 stream slave for source stream (TX_DMA or ADC) -- Source interface + + input s_axis_aclk, + input s_axis_aresetn, + + output s_axis_ready, + input s_axis_valid, + input [SRC_DATA_WIDTH-1:0] s_axis_data, + input s_axis_last, + input [SRC_DATA_WIDTH/8-1:0] s_axis_tkeep, + + // AXI4 stream master for destination stream (RX_DMA or DAC) -- Destination + // interface + + input m_axis_aclk, + input m_axis_aresetn, + + input m_axis_ready, + output m_axis_valid, + output [DST_DATA_WIDTH-1:0] m_axis_data, + output m_axis_last, + output [DST_DATA_WIDTH/8-1:0] m_axis_tkeep, + + // initialization request interface + + input init_req, + + input sync_ext, + + // AXIS - Memory UI to storage + + // AXI stream master for source stream to storage (BRAM/URAM/DDR/HBM) + // runs on s_axis_aclk and s_axis_aresetn + input m_storage_axis_ready, + output m_storage_axis_valid, + output [SRC_DATA_WIDTH-1:0] m_storage_axis_data, + output m_storage_axis_last, + output [SRC_DATA_WIDTH/8-1:0] m_storage_axis_tkeep, + + // AXI stream slave for destination stream from storage (BRAM/URAM/DDR/HBM) + // runs on m_axis_aclk and m_axis_aresetn + output s_storage_axis_ready, + input s_storage_axis_valid, + input [DST_DATA_WIDTH-1:0] s_storage_axis_data, + input s_storage_axis_last, + input [DST_DATA_WIDTH/8-1:0] s_storage_axis_tkeep, + + // Control interface for storage for m_storage_axis interface + output wr_request_enable, + output wr_request_valid, + input wr_request_ready, + output [MEM_SIZE_LOG2-1:0] wr_request_length, + input [MEM_SIZE_LOG2-1:0] wr_response_measured_length, + input wr_response_eot, + input wr_overflow, + + // Control interface for storage for s_storage_axis interface + output rd_request_enable, + output rd_request_valid, + input rd_request_ready, + output reg [MEM_SIZE_LOG2-1:0] rd_request_length, + input rd_response_eot, + input rd_underflow, + + // Status and monitor + + input ddr_calib_done +); + + // local parameters -- to make the code more readable + + localparam SRC_ADDR_WIDTH_BYPASS = (SRC_DATA_WIDTH > DST_DATA_WIDTH) ? 4 : 4 + $clog2(SRC_DATA_WIDTH/DST_DATA_WIDTH); + localparam DST_ADDR_WIDTH_BYPASS = (SRC_DATA_WIDTH <= DST_DATA_WIDTH) ? 4 + $clog2(DST_DATA_WIDTH/SRC_DATA_WIDTH) : 4; + + localparam SRC_BEAT_BYTE = $clog2(SRC_DATA_WIDTH/8); + + // NOTE: Clock domain prefixes + // src_* - AXI4 Stream Slave interface's clock domain + // dst_* - AXI4 Stream Master interface's clock domain + + // internal signals + wire up_clk; + wire up_rstn; + wire up_wreq_s; + wire [13:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire up_rreq_s; + wire [13:0] up_raddr_s; + wire up_wack_s; + wire up_rack_s; + wire [31:0] up_rdata_s; + + wire src_clk; + wire src_rstn; + wire dst_clk; + wire dst_rstn; + + wire src_bypass_s; + wire dst_bypass_s; + wire oneshot_s; + wire [ 1:0] sync_config_s; + wire sync_int_s; + wire valid_bypass_s; + wire [DST_DATA_WIDTH-1:0] data_bypass_s; + wire ready_bypass_s; + wire [ 4:0] src_fsm_status_s; + wire [ 3:0] dst_fsm_status_s; + + wire [MEM_SIZE_LOG2-1:0] src_transfer_length_s; + wire [MEM_SIZE_LOG2-1:0] rd_wr_response_measured_length; + wire rd_ml_valid; + wire rd_ready; + wire rd_ml_ready; + wire wr_ready; + + assign src_clk = s_axis_aclk; + assign dst_clk = m_axis_aclk; + + // internal registers + + // Offload FSM and control + data_offload_fsm #( + .TX_OR_RXN_PATH (TX_OR_RXN_PATH), + .SYNC_EXT_ADD_INTERNAL_CDC (SYNC_EXT_ADD_INTERNAL_CDC) + ) i_data_offload_fsm ( + .up_clk (up_clk), + .wr_clk (src_clk), + .wr_resetn_in (src_rstn), + .wr_request_enable (wr_request_enable), + .wr_request_valid (wr_request_valid), + .wr_request_ready (wr_request_ready), + .wr_response_eot (wr_response_eot), + .wr_ready (wr_ready), + .rd_clk (dst_clk), + .rd_resetn_in (dst_rstn), + .rd_request_enable (rd_request_enable), + .rd_request_valid (rd_request_valid), + .rd_request_ready (rd_request_ready), + .rd_response_eot (rd_response_eot), + .rd_ready (rd_ready), + .rd_valid (s_storage_axis_valid), + .rd_ml_valid (rd_ml_valid), + .rd_ml_ready (rd_ml_ready), + .rd_oneshot (oneshot_s), + .wr_bypass (src_bypass_s), + .init_req (init_req), + .sync_config (sync_config_s), + .sync_external (sync_ext), + .sync_internal (sync_int_s), + .wr_fsm_state_out (src_fsm_status_s), + .rd_fsm_state_out (dst_fsm_status_s)); + + assign m_axis_valid = dst_bypass_s ? valid_bypass_s : (rd_ready & s_storage_axis_valid); + // For DAC paths set zero as IDLE data on the axis bus, avoid repeating last + // sample. + assign m_axis_data = TX_OR_RXN_PATH[0] & ~m_axis_valid ? {DST_DATA_WIDTH{1'b0}} : + (dst_bypass_s) ? data_bypass_s : s_storage_axis_data; + assign m_axis_last = (dst_bypass_s) ? 1'b0 : s_storage_axis_last; + assign m_axis_tkeep = (dst_bypass_s) ? {DST_DATA_WIDTH/8{1'b1}} : s_storage_axis_tkeep; + + assign s_axis_ready = src_bypass_s ? ready_bypass_s : (wr_ready & m_storage_axis_ready); + + assign m_storage_axis_valid = s_axis_valid & wr_ready; + assign m_storage_axis_data = s_axis_data; + assign m_storage_axis_last = s_axis_last; + assign m_storage_axis_tkeep = s_axis_tkeep; + + assign s_storage_axis_ready = rd_ready & m_axis_ready; + + // Bypass module instance -- the same FIFO, just a smaller depth + // NOTE: Generating an overflow is making sense just in BYPASS mode, and + // it's supported just with the FIFO interface + util_axis_fifo_asym #( + .S_DATA_WIDTH (SRC_DATA_WIDTH), + .S_ADDRESS_WIDTH (SRC_ADDR_WIDTH_BYPASS), + .M_DATA_WIDTH (DST_DATA_WIDTH), + .ASYNC_CLK (1) + ) i_bypass_fifo ( + .m_axis_aclk (m_axis_aclk), + .m_axis_aresetn (dst_rstn), + .m_axis_ready (m_axis_ready), + .m_axis_valid (valid_bypass_s), + .m_axis_data (data_bypass_s), + .m_axis_tlast (), + .m_axis_empty (), + .m_axis_almost_empty (), + .m_axis_tkeep (), + .m_axis_level (), + .s_axis_aclk (s_axis_aclk), + .s_axis_aresetn (src_rstn), + .s_axis_ready (ready_bypass_s), + .s_axis_valid (s_axis_valid & src_bypass_s), + .s_axis_data (s_axis_data), + .s_axis_tlast (), + .s_axis_full (), + .s_axis_almost_full (), + .s_axis_tkeep (), + .s_axis_room ()); + + // register map + + data_offload_regmap #( + .ID (ID), + .MEM_TYPE (MEM_TYPE), + .MEM_SIZE_LOG2 (MEM_SIZE_LOG2), + .TX_OR_RXN_PATH (TX_OR_RXN_PATH), + .AUTO_BRINGUP (AUTO_BRINGUP), + .HAS_BYPASS (HAS_BYPASS) + ) i_regmap ( + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_rreq (up_rreq_s), + .up_rack (up_rack_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_wreq (up_wreq_s), + .up_wack (up_wack_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .src_clk (s_axis_aclk), + .dst_clk (m_axis_aclk), + .src_sw_resetn (src_rstn), + .dst_sw_resetn (dst_rstn), + .ddr_calib_done (ddr_calib_done), + .src_bypass (src_bypass_s), + .dst_bypass (dst_bypass_s), + .oneshot (oneshot_s), + .sync (sync_int_s), + .sync_config (sync_config_s), + .src_transfer_length (wr_request_length), + .dst_transfer_length (), + .src_fsm_status (src_fsm_status_s), + .dst_fsm_status (dst_fsm_status_s), + .src_overflow (wr_overflow), + .dst_underflow (rd_underflow)); + + // axi interface wrapper + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + up_axi #( + .AXI_ADDRESS_WIDTH (16) + ) i_up_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s), + .up_rack (up_rack_s)); + + // Measured length handshake CDC + util_axis_fifo #( + .DATA_WIDTH(MEM_SIZE_LOG2), + .ADDRESS_WIDTH(0), + .ASYNC_CLK(1) + ) i_measured_length_cdc ( + .s_axis_aclk(s_axis_aclk), + .s_axis_aresetn(s_axis_aresetn), + .s_axis_valid(wr_response_eot), + .s_axis_ready(), + .s_axis_full(), + .s_axis_data(wr_response_measured_length), + .s_axis_room(), + .s_axis_tkeep(), + .s_axis_tlast(), + .s_axis_almost_full(), + + .m_axis_aclk(m_axis_aclk), + .m_axis_aresetn(m_axis_aresetn), + .m_axis_valid(rd_ml_valid), + .m_axis_ready(rd_ml_ready), + .m_axis_data(rd_wr_response_measured_length), + .m_axis_level(), + .m_axis_empty(), + .m_axis_tkeep(), + .m_axis_tlast(), + .m_axis_almost_empty()); + + always @(posedge m_axis_aclk) begin + if (rd_ml_valid & rd_ml_ready) + rd_request_length <= rd_wr_response_measured_length; + end + +endmodule diff --git a/adi_library/data_offload/data_offload.xpr b/adi_library/data_offload/data_offload.xpr new file mode 100644 index 00000000..4e12ca70 --- /dev/null +++ b/adi_library/data_offload/data_offload.xpr @@ -0,0 +1,437 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/data_offload/data_offload_constr.ttcl b/adi_library/data_offload/data_offload_constr.ttcl new file mode 100644 index 00000000..23790f23 --- /dev/null +++ b/adi_library/data_offload/data_offload_constr.ttcl @@ -0,0 +1,171 @@ +############################################################################### +## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName [ttcl_add $ComponentName "_constr"] :> +<: setFileExtension ".xdc" :> +<: setFileProcessingOrder late :> +<: set mem_type [getBooleanValue "MEM_TYPE"] :> +<: set tx_enable [getBooleanValue "TX_OR_RXN_PATH"] :> +<: set internal_cdc [getBooleanValue "SYNC_EXT_ADD_INTERNAL_CDC"] :> +<: set has_bypass [getBooleanValue "HAS_BYPASS"] :> + +## for all synchronization registers from util_cdc modules +set_property ASYNC_REG TRUE \ + [get_cells -hier {*cdc_sync_stage1_reg*}] \ + [get_cells -hier {*cdc_sync_stage2_reg*}] + +## For RX in case of BRAMs +<: if { !$tx_enable } { :> + +<: if { $internal_cdc } { :> + set_false_path \ + -to [get_pins -hierarchical * -filter {NAME=~*/i_sync_wr_sync/cdc_sync_stage1_reg[*]/D}] +<: } :> + +<: } :> + +set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/cdc_hold_reg[*]}] \ + -to [get_cells -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/out_data_reg[*]}] + +set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/in_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/i_sync_out/cdc_sync_stage1_reg[*]/D}] + +set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/out_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*/i_sync_src_transfer_length/i_sync_in/cdc_sync_stage1_reg[*]/D}] + +## For TX in case of BRAMs +<: if { $tx_enable } { :> + +<: if { $internal_cdc } { :> +set_false_path \ + -to [get_pins -hierarchical * -filter {NAME=~*/i_sync_rd_sync/cdc_sync_stage1_reg[*]/D}] +<: } :> + + +<: } :> + +## For external DDRx memory + +<: if { $mem_type } { :> + + set_false_path \ + -to [get_pins -hierarchical * -filter {NAME=~*i_ddr_calib_done_sync/cdc_sync_stage1_reg[0]/D}] + +<: } :> + +## Common constraints + +set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*/i_dst_fsm_status/in_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*/i_dst_fsm_status/i_sync_out/cdc_sync_stage1_reg[*]/D}] + +set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*/i_dst_fsm_status/out_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*/i_dst_fsm_status/i_sync_in/cdc_sync_stage1_reg[*]/D}] + +set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*/i_dst_fsm_status/cdc_hold_reg[*]}] \ + -to [get_cells -hierarchical * -filter {NAME=~*/i_dst_fsm_status/out_data_reg[*]}] + +set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*/i_src_fsm_status/in_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*/i_src_fsm_status/i_sync_out/cdc_sync_stage1_reg[*]/D}] + +set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*/i_src_fsm_status/out_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*/i_src_fsm_status/i_sync_in/cdc_sync_stage1_reg[*]/D}] + +set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*/i_src_fsm_status/cdc_hold_reg[*]}] \ + -to [get_cells -hierarchical * -filter {NAME=~*/i_src_fsm_status/out_data_reg[*]}] + +set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*/i_wr_empty_sync/in_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*/i_wr_empty_sync/i_sync_out/cdc_sync_stage1_reg[*]/D}] + +set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*/i_wr_empty_sync/out_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*/i_wr_empty_sync/i_sync_in/cdc_sync_stage1_reg[*]/D}] + +set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*i_sync_xfer_control/in_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*i_sync_xfer_control/i_sync_out/cdc_sync_stage1_reg[*]/D}] + +set_false_path \ + -from [get_pins -hierarchical * -filter {NAME=~*i_sync_xfer_control/out_toggle_d1_reg/C}] \ + -to [get_pins -hierarchical * -filter {NAME=~*i_sync_xfer_control/i_sync_in/cdc_sync_stage1_reg[*]/D}] + +set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*i_sync_xfer_control/cdc_hold_reg[*]}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_sync_xfer_control/out_data_reg[*]}] + + +<: if { $tx_enable } { :> +set_false_path \ + -to [get_pins -hierarchical * -filter {NAME=~*i_rd_init_req_sync/cdc_sync_stage1_reg[*]/D}] +<: } else { :> +set_false_path \ + -to [get_pins -hierarchical * -filter {NAME=~*i_wr_init_req_sync/cdc_sync_stage1_reg[*]/D}] +<: } :> + +set_false_path \ + -to [get_pins -hierarchical * -filter {NAME=~*i_src_xfer_control/cdc_sync_stage1_reg[*]/D}] + +set_false_path \ + -to [get_pins -hierarchical * -filter {NAME=~*i_dst_xfer_control/cdc_sync_stage1_reg[*]/D}] + +set_false_path \ + -to [get_pins -hierarchical * -filter {NAME=~*i_dst_oneshot_sync/cdc_sync_stage1_reg[0]/D}] + + +# measured transfer length util_axis_fifo +set src_clk [get_clocks -of_objects [get_ports s_axis_aclk]] +set dest_clk [get_clocks -of_objects [get_ports m_axis_aclk]] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_measured_length_cdc/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from $dest_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_measured_length_cdc/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ + -filter {NAME =~ *i_measured_length_cdc* && IS_SEQUENTIAL}] \ + -to $dest_clk \ + [get_property -min PERIOD $dest_clk] + +## Constraints for the bypass module +<: if { $has_bypass } { :> +set_false_path \ + -to [get_pins -hierarchical * -filter {NAME=~*i_waddr_sync_gray/cdc_sync_stage1_reg[*]/D}] + +set_false_path \ + -to [get_pins -hierarchical * -filter {NAME=~*i_raddr_sync_gray/cdc_sync_stage1_reg[*]/D}] +<: } :> + +## Constraints for the overflow/underflow status +<: if { $tx_enable } { :> +set flow_cdc i_rd_underflow_sync +<: } else { :> +set flow_cdc i_wr_overflow_sync +<: } :> +set_false_path \ + -from [get_pins -hierarchical * -filter NAME=~*/$flow_cdc/in_toggle_d1_reg/C] \ + -to [get_pins -hierarchical * -filter NAME=~*/$flow_cdc/i_sync_out/cdc_sync_stage1_reg[*]/D] + +set_false_path \ + -from [get_pins -hierarchical * -filter NAME=~*/$flow_cdc/out_toggle_d1_reg/C] \ + -to [get_pins -hierarchical * -filter NAME=~*/$flow_cdc/i_sync_in/cdc_sync_stage1_reg[*]/D] diff --git a/adi_library/data_offload/data_offload_fsm.v b/adi_library/data_offload/data_offload_fsm.v new file mode 100644 index 00000000..3bccddc9 --- /dev/null +++ b/adi_library/data_offload/data_offload_fsm.v @@ -0,0 +1,321 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +`timescale 1ns/100ps + +/* This module controls the read and write access to the storage unit. It is +* used for both transmit and receive use cases +*/ + +module data_offload_fsm #( + + parameter TX_OR_RXN_PATH = 0, + parameter SYNC_EXT_ADD_INTERNAL_CDC = 1 +) ( + input up_clk, + + // Control interface for storage for m_storage_axis interface + output reg wr_request_enable = 1'b0, + output wr_request_valid, + input wr_request_ready, + input wr_response_eot, + + // Control interface for storage for s_storage_axis interface + output reg rd_request_enable = 1'b0, + output rd_request_valid, + input rd_request_ready, + input rd_response_eot, + + input rd_ml_valid, + output rd_ml_ready, + + // Data path gating + output wr_ready, + output rd_ready, + input rd_valid, + + // write control interface + input wr_clk, + input wr_resetn_in, + input wr_bypass, + + // read control interface + input rd_clk, + input rd_resetn_in, + input rd_oneshot, // 0 - CYCLIC; 1 - ONE_SHOT; + + // Synchronization interface - synchronous to the external DMA clock + input init_req, + input [ 1:0] sync_config, + + input sync_external, + input sync_internal, + + // FSM debug + output [ 4:0] wr_fsm_state_out, + output [ 3:0] rd_fsm_state_out +); + + // FSM states + + localparam WR_STATE_IDLE = 5'b00001; + localparam WR_STATE_PRE_WR = 5'b00010; + localparam WR_STATE_SYNC = 5'b00100; + localparam WR_STATE_WR = 5'b01000; + localparam WR_STATE_WAIT_RD = 5'b10000; + + localparam WR_BIT_IDLE = 0; + localparam WR_BIT_PRE_WR = 1; + localparam WR_BIT_SYNC = 2; + localparam WR_BIT_WR = 3; + + localparam RD_STATE_IDLE = 4'b0001; + localparam RD_STATE_PRE_RD = 4'b0010; + localparam RD_STATE_SYNC = 4'b0100; + localparam RD_STATE_RD = 4'b1000; + + localparam RD_BIT_IDLE = 0; + localparam RD_BIT_PRE_RD = 1; + localparam RD_BIT_SYNC = 2; + localparam RD_BIT_RD = 3; + + // Synchronization options + + localparam AUTOMATIC = 2'b00; + localparam HARDWARE = 2'b01; + localparam SOFTWARE = 2'b10; + + // internal registers + reg rd_cyclic_en = 1'b0; + + // internal signals + wire wr_sync_external_s; + wire wr_init_req_s; + wire wr_rd_response_eot; + wire rd_sync_external_s; + wire rd_last_eot; + wire rd_init_req_s; + + reg [4:0] wr_fsm_state = WR_STATE_IDLE; + reg [4:0] wr_fsm_next_state; + reg [3:0] rd_fsm_state = RD_STATE_IDLE; + reg [3:0] rd_fsm_next_state; + reg [1:0] rd_outstanding = 2'd0; + + assign wr_fsm_state_out = wr_fsm_state; + assign rd_fsm_state_out = rd_fsm_state; + + always @(*) begin + wr_fsm_next_state = wr_fsm_state; + case (wr_fsm_state) + WR_STATE_IDLE: + if (wr_init_req_s & ~wr_bypass) begin + wr_fsm_next_state = WR_STATE_PRE_WR; + end + WR_STATE_PRE_WR: + if (wr_request_ready) begin + wr_fsm_next_state = TX_OR_RXN_PATH ? WR_STATE_WR : WR_STATE_SYNC; + end + WR_STATE_SYNC: + case (sync_config) + AUTOMATIC: + wr_fsm_next_state = WR_STATE_WR; + HARDWARE: + if (wr_sync_external_s) begin + wr_fsm_next_state = WR_STATE_WR; + end + SOFTWARE: + if (sync_internal) begin + wr_fsm_next_state = WR_STATE_WR; + end + default: + wr_fsm_next_state = WR_STATE_WR; + endcase + WR_STATE_WR: + if (wr_response_eot) begin + wr_fsm_next_state = WR_STATE_WAIT_RD; + end + WR_STATE_WAIT_RD: + if (wr_rd_response_eot) begin + wr_fsm_next_state = WR_STATE_IDLE; + end + default: + wr_fsm_next_state = WR_STATE_IDLE; + endcase + end + + always @(posedge wr_clk) begin + if (wr_resetn_in == 1'b0) begin + wr_fsm_state <= WR_STATE_IDLE; + end else begin + wr_fsm_state <= wr_fsm_next_state; + end + end + + always @(*) begin + rd_fsm_next_state = rd_fsm_state; + case (rd_fsm_state) + RD_STATE_IDLE: + if (rd_ml_valid) begin + rd_fsm_next_state = RD_STATE_PRE_RD; + end + RD_STATE_PRE_RD: + if (rd_request_ready) begin + rd_fsm_next_state = TX_OR_RXN_PATH ? RD_STATE_SYNC : RD_STATE_RD; + end + RD_STATE_SYNC: + if (rd_valid) // Wait until storage is valid + case (sync_config) + AUTOMATIC: + rd_fsm_next_state = RD_STATE_RD; + HARDWARE: + if (rd_sync_external_s) begin + rd_fsm_next_state = RD_STATE_RD; + end + SOFTWARE: + if (sync_internal) begin + rd_fsm_next_state = RD_STATE_RD; + end + default: + rd_fsm_next_state = RD_STATE_RD; + endcase + RD_STATE_RD: + if (rd_last_eot) begin + rd_fsm_next_state = (rd_cyclic_en == 1'b0) ? RD_STATE_IDLE : + (TX_OR_RXN_PATH & (sync_config != AUTOMATIC)) ? RD_STATE_SYNC : + RD_STATE_RD; + end + default: + rd_fsm_next_state = RD_STATE_IDLE; + endcase + end + + always @(posedge rd_clk) begin + if (rd_resetn_in == 1'b0) begin + rd_fsm_state <= RD_STATE_IDLE; + end else begin + rd_fsm_state <= rd_fsm_next_state; + end + end + + always @(posedge rd_clk) begin + if (rd_resetn_in == 1'b0) + rd_outstanding <= 2'b0; + else if (rd_request_ready & rd_request_valid & ~rd_response_eot) + rd_outstanding <= rd_outstanding + 2'd1; + else if (~(rd_request_ready & rd_request_valid) & (rd_response_eot & rd_fsm_state[RD_BIT_RD])) + rd_outstanding <= rd_outstanding - 2'd1; + end + assign rd_last_eot = (rd_outstanding == 1) & (rd_response_eot & rd_fsm_state[RD_BIT_RD]) & !(rd_request_ready & rd_request_valid); + + always @(posedge rd_clk) begin + if (rd_init_req_s) begin + rd_cyclic_en <= 1'b0; + end else if (rd_fsm_state[RD_BIT_PRE_RD]) begin + rd_cyclic_en <= ~rd_oneshot; + end + end + + assign rd_ready = rd_fsm_state[RD_BIT_RD]; + assign wr_ready = wr_fsm_state[WR_BIT_WR]; + + assign wr_request_valid = wr_fsm_state[WR_BIT_PRE_WR]; + assign rd_request_valid = rd_fsm_state[RD_BIT_PRE_RD] | rd_cyclic_en; + + always @(posedge rd_clk) begin + if (rd_resetn_in == 1'b0 || (~rd_init_req_s & ~TX_OR_RXN_PATH[0])) + rd_request_enable <= 1'b0; + else + rd_request_enable <= 1'b1; + end + + always @(posedge wr_clk) begin + if (wr_resetn_in == 1'b0) + wr_request_enable <= 1'b0; + else + wr_request_enable <= 1'b1; + end + + assign rd_ml_ready = rd_fsm_state[RD_BIT_IDLE]; + + // CDC circuits + sync_event #( + .NUM_OF_EVENTS (1), + .ASYNC_CLK (1) + ) i_wr_empty_sync ( + .in_clk (rd_clk), + .in_event (rd_last_eot && rd_fsm_state[RD_BIT_RD]), + .out_clk (wr_clk), + .out_event (wr_rd_response_eot)); + + sync_bits #( + .NUM_OF_BITS (1), + .ASYNC_CLK (TX_OR_RXN_PATH[0]) + ) i_rd_init_req_sync ( + .in_bits (init_req), + .out_clk (rd_clk), + .out_resetn (1'b1), + .out_bits (rd_init_req_s)); + + sync_bits #( + .NUM_OF_BITS (1), + .ASYNC_CLK (~TX_OR_RXN_PATH[0]) + ) i_wr_init_req_sync ( + .in_bits (init_req), + .out_clk (wr_clk), + .out_resetn (1'b1), + .out_bits (wr_init_req_s)); + + // When SYNC_EXT_ADD_INTERNAL_CDC is deasserted, one of these signals will end + // up being synchronized to the "wrong" clock domain. This shouldn't matter + // because the incorrectly synchronized signal is guarded by a synthesis constant. + sync_bits #( + .NUM_OF_BITS (1), + .ASYNC_CLK (SYNC_EXT_ADD_INTERNAL_CDC) + ) i_sync_wr_sync ( + .in_bits ({ sync_external }), + .out_clk (wr_clk), + .out_resetn (1'b1), + .out_bits ({wr_sync_external_s})); + + sync_bits #( + .NUM_OF_BITS (1), + .ASYNC_CLK (SYNC_EXT_ADD_INTERNAL_CDC) + ) i_sync_rd_sync ( + .in_bits ({ sync_external }), + .out_clk (rd_clk), + .out_resetn (1'b1), + .out_bits ({ rd_sync_external_s })); + +endmodule diff --git a/adi_library/data_offload/data_offload_ip.tcl b/adi_library/data_offload/data_offload_ip.tcl new file mode 100644 index 00000000..c1373c06 --- /dev/null +++ b/adi_library/data_offload/data_offload_ip.tcl @@ -0,0 +1,284 @@ +############################################################################### +## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create data_offload +adi_ip_files data_offload [list \ + "data_offload_sv.ttcl" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/ad_mem_asym.v" \ + "$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \ + "data_offload_regmap.v" \ + "data_offload_fsm.v" \ + "data_offload.v" ] + +## NOTE: To solve the issue AR# 70646 we need to call the following command +##set_property source_mgmt_mode DisplayOnly [current_project] + +adi_ip_properties data_offload +adi_ip_ttcl data_offload "data_offload_constr.ttcl" +adi_ip_sim_ttcl data_offload "data_offload_sv.ttcl" + +adi_ip_add_core_dependencies [list \ + analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \ + analog.com:$VIVADO_IP_LIBRARY:util_axis_fifo_asym:1.0 \ +] + +set_property display_name "ADI Data Offload Controller" [ipx::current_core] +set_property description "ADI Data Offload Controller" [ipx::current_core] + +## Interface definitions + +## destination interfaces (e.g. RX_DMA or DAC core) + +adi_add_bus "m_axis" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [ list \ + {"m_axis_ready" "TREADY"} \ + {"m_axis_valid" "TVALID"} \ + {"m_axis_data" "TDATA"} \ + {"m_axis_last" "TLAST"} \ + {"m_axis_tkeep" "TKEEP"} ] + +## source interface (e.g. TX_DMA or ADC core) + +adi_add_bus "s_axis" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [ list \ + {"s_axis_ready" "TREADY"} \ + {"s_axis_valid" "TVALID"} \ + {"s_axis_data" "TDATA"} \ + {"s_axis_last" "TLAST"} \ + {"s_axis_tkeep" "TKEEP"} ] + +adi_add_bus "wr_ctrl" "master" \ + "analog.com:interface:if_do_ctrl_rtl:1.0" \ + "analog.com:interface:if_do_ctrl:1.0" \ + [list {"wr_request_enable" "request_enable"} \ + {"wr_request_valid" "request_valid"} \ + {"wr_request_ready" "request_ready"} \ + {"wr_request_length" "request_length"} \ + {"wr_response_measured_length" "response_measured_length"} \ + {"wr_response_eot" "response_eot"} \ + {"wr_overflow" "status_overflow"} \ + ] + +adi_add_bus "rd_ctrl" "master" \ + "analog.com:interface:if_do_ctrl_rtl:1.0" \ + "analog.com:interface:if_do_ctrl:1.0" \ + [list {"rd_request_enable" "request_enable"} \ + {"rd_request_valid" "request_valid"} \ + {"rd_request_ready" "request_ready"} \ + {"rd_request_length" "request_length"} \ + {"rd_response_eot" "response_eot"} \ + {"rd_underflow" "status_underflow"} \ + ] + +adi_add_bus "s_storage_axis" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"s_storage_axis_ready" "TREADY"} \ + {"s_storage_axis_valid" "TVALID"} \ + {"s_storage_axis_data" "TDATA"} \ + {"s_storage_axis_tkeep" "TKEEP"} \ + {"s_storage_axis_last" "TLAST"}] + +adi_add_bus "m_storage_axis" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"m_storage_axis_ready" "TREADY"} \ + {"m_storage_axis_valid" "TVALID"} \ + {"m_storage_axis_data" "TDATA"} \ + {"m_storage_axis_tkeep" "TKEEP"} \ + {"m_storage_axis_last" "TLAST"}] + +adi_add_bus_clock "m_axis_aclk" "s_storage_axis:m_axis" "m_axis_aresetn" +adi_add_bus_clock "s_axis_aclk" "m_storage_axis:s_axis" "s_axis_aresetn" + +set cc [ipx::current_core] + +set_property -dict [list \ + enablement_resolve_type dependent \ + driver_value 0 \ + enablement_dependency {MEM_TYPE == 1} \ + ] \ +[ipx::get_ports ddr_calib_done -of_objects $cc] + +set_property -dict [list \ + driver_value 0 \ + ] \ +[ipx::get_ports wr_overflow -of_objects $cc] + +set_property -dict [list \ + driver_value 0 \ + ] \ +[ipx::get_ports rd_underflow -of_objects $cc] + +## Parameter validations + +## MEM_TPYE +set_property -dict [list \ + "value_format" "long" \ + "value_validation_type" "pairs" \ + "value_validation_pairs" { \ + "Internal memory" "0" \ + "External memory" "1" \ + } \ + ] \ + [ipx::get_user_parameters MEM_TYPE -of_objects $cc] + +set_property -dict [list \ + "value_format" "long" \ + ] \ + [ipx::get_hdl_parameters MEM_TYPE -of_objects $cc] + +set_property -dict [list \ + "value_validation_type" "pairs" \ + "value_validation_pairs" { \ + "RX path" "0" \ + "TX path" "1" \ + } \ + ] \ + [ipx::get_user_parameters TX_OR_RXN_PATH -of_objects $cc] + +set_property -dict [list \ + "value_validation_type" "pairs" \ + "value" "10" \ + "value_validation_pairs" {\ + "1kB" "10" \ + "2kB" "11" \ + "4kB" "12" \ + "8kB" "13" \ + "16kB" "14" \ + "32kB" "15" \ + "64kB" "16" \ + "128kB" "17" \ + "256kB" "18" \ + "512kB" "19" \ + "1MB" "20" \ + "2MB" "21" \ + "4MB" "22" \ + "8MB" "23" \ + "16MB" "24" \ + "32MB" "25" \ + "64MB" "26" \ + "128MB" "27" \ + "256MB" "28" \ + "512MB" "29" \ + "1GB" "30" \ + "2GB" "31" \ + "4GB" "32" \ + "8GB" "33" \ + "16GB" "34" \ + } \ + ] \ + [ipx::get_user_parameters MEM_SIZE_LOG2 -of_objects $cc] + +## Boolean parameters +foreach {k v} { \ + "HAS_BYPASS" "true" \ + "DST_CYCLIC_EN" "true" \ + "SYNC_EXT_ADD_INTERNAL_CDC" "true" \ + } { \ + set_property -dict [list \ + "value_format" "bool" \ + "value_format" "bool" \ + "value" $v \ + ] \ + [ipx::get_user_parameters $k -of_objects $cc] + set_property -dict [list \ + "value_format" "bool" \ + "value_format" "bool" \ + "value" $v \ + ] \ + [ipx::get_hdl_parameters $k -of_objects $cc] +} + +### Customize IP Layout + +## Remove the automatically generated GUI page +ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] +ipx::save_core [ipx::current_core] + +## Create a new GUI page +ipgui::add_page -name {Data Offload} -component [ipx::current_core] -display_name {Data Offload} +set page0 [ipgui::get_pagespec -name "Data Offload" -component $cc] + +## General Configurations +set general_group [ipgui::add_group -name "General Configuration" -component $cc \ + -parent $page0 -display_name "General Configuration" ] + +ipgui::add_param -name "ID" -component $cc -parent $general_group +set_property -dict [list \ + "display_name" "Core ID" \ +] [ipgui::get_guiparamspec -name "ID" -component $cc] + +ipgui::add_param -name "TX_OR_RXN_PATH" -component $cc -parent $general_group +set_property -dict [list \ + "widget" "comboBox" \ + "display_name" "Data path type" \ +] [ipgui::get_guiparamspec -name "TX_OR_RXN_PATH" -component $cc] + +ipgui::add_param -name "MEM_TYPE" -component $cc -parent $general_group +set_property -dict [list \ + "widget" "comboBox" \ + "display_name" "Storage Type" \ +] [ipgui::get_guiparamspec -name "MEM_TYPE" -component $cc] + +ipgui::add_param -name "MEM_SIZE_LOG2" -component $cc -parent $general_group +set_property -dict [list \ + "display_name" "Storage Size" \ + "tooltip" "Log2 value of Storage Size in bytes" \ +] [ipgui::get_guiparamspec -name "MEM_SIZE_LOG2" -component $cc] + +## Transmit and receive endpoints +set source_group [ipgui::add_group -name "Source Endpoint Configuration" -component $cc \ + -parent $page0 -display_name "Source Endpoint Configuration" \ + -layout "horizontal"] +set destination_group [ipgui::add_group -name "Destination Endpoint Configuration" -component $cc \ + -parent $page0 -display_name "Destination Endpoint Configuration" \ + -layout "horizontal"] + +ipgui::add_param -name "SRC_DATA_WIDTH" -component $cc -parent $source_group +set_property -dict [list \ + "display_name" "Source Interface data width" \ +] [ipgui::get_guiparamspec -name "SRC_DATA_WIDTH" -component $cc] + +ipgui::add_param -name "DST_DATA_WIDTH" -component $cc -parent $destination_group +set_property -dict [list \ + "display_name" "Destination Interface data width" \ +] [ipgui::get_guiparamspec -name "DST_DATA_WIDTH" -component $cc] + +## Other features +set features_group [ipgui::add_group -name "Features" -component $cc \ + -parent $page0 -display_name "Features" ] + +ipgui::add_param -name "HAS_BYPASS" -component $cc -parent $features_group +set_property -dict [list \ + "display_name" "Internal Bypass Data Path Enabled" \ +] [ipgui::get_guiparamspec -name "HAS_BYPASS" -component $cc] + +ipgui::add_param -name "DST_CYCLIC_EN" -component $cc -parent $features_group +set_property -dict [list \ + "display_name" "Destination Cyclic Mode Enabled" \ +] [ipgui::get_guiparamspec -name "DST_CYCLIC_EN" -component $cc] +set_property enablement_tcl_expr {$TX_OR_RXN_PATH == 1} [ipx::get_user_parameters DST_CYCLIC_EN -of_objects $cc] + +ipgui::add_param -name "SYNC_EXT_ADD_INTERNAL_CDC" -component $cc -parent $features_group +set_property -dict [list \ + "display_name" "Generate CDC Circuit for sync_ext" \ +] [ipgui::get_guiparamspec -name "SYNC_EXT_ADD_INTERNAL_CDC" -component $cc] + +## Create and save the XGUI file +ipx::create_xgui_files $cc + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/data_offload/data_offload_regmap.v b/adi_library/data_offload/data_offload_regmap.v new file mode 100644 index 00000000..dc3ea177 --- /dev/null +++ b/adi_library/data_offload/data_offload_regmap.v @@ -0,0 +1,408 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +`timescale 1ns/100ps + +module data_offload_regmap #( + + parameter ID = 0, + parameter [ 0:0] MEM_TYPE = 1'b0, + parameter MEM_SIZE_LOG2 = 10, + parameter TX_OR_RXN_PATH = 0, + parameter AUTO_BRINGUP = 0, + parameter HAS_BYPASS = 1 +) ( + + // microprocessor interface + input up_clk, + input up_rstn, + + input up_rreq, + output reg up_rack, + input [13:0] up_raddr, + output reg [31:0] up_rdata, + input up_wreq, + output reg up_wack, + input [13:0] up_waddr, + input [31:0] up_wdata, + + // source clock domain + input src_clk, + + // destination clock domain + input dst_clk, + + // resets for all clock domains + output reg src_sw_resetn, + output reg dst_sw_resetn, + + // status bit from the memory controller + input ddr_calib_done, + + // bypass control + output src_bypass, + output dst_bypass, + output oneshot, + + // synchronization + output sync, + output [ 1:0] sync_config, + + output [MEM_SIZE_LOG2-1:0] src_transfer_length, + output [MEM_SIZE_LOG2-1:0] dst_transfer_length, + + // FSM control and status + input [ 4:0] src_fsm_status, + input [ 3:0] dst_fsm_status, + + input src_overflow, + input dst_underflow +); + + // local parameters + + localparam [31:0] CORE_VERSION = 32'h00010061; // 1.00.a + localparam [31:0] CORE_MAGIC = 32'h44414F46; // DAOF + + localparam [33:0] MEM_SIZE = 1 << MEM_SIZE_LOG2; + + // internal registers + + reg [31:0] up_scratch = 'd0; + reg up_sw_resetn = 'd0; + reg up_bypass = 'd0; + reg up_sync = 'd0; + reg [ 1:0] up_sync_config = 'd0; + reg up_oneshot = 1'b0; + reg [MEM_SIZE_LOG2-1:0] up_transfer_length = 'd0; + reg up_src_overflow = 1'b0; + reg up_dst_underflow = 1'b0; + + //internal signals + + wire up_ddr_calib_done_s; + wire [ 4:0] up_wr_fsm_status_s; + wire [ 3:0] up_rd_fsm_status_s; + wire src_sw_resetn_s; + wire dst_sw_resetn_s; + wire [33:0] src_transfer_length_s; + wire up_src_overflow_set_s; + wire up_dst_underflow_set_s; + + // write interface + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_wack <= up_wreq; + up_scratch <= 'd0; + up_sw_resetn <= AUTO_BRINGUP; + up_oneshot <= ~TX_OR_RXN_PATH; + up_bypass <= 'd0; + up_sync <= 'd0; + up_sync_config <= 'd0; + up_transfer_length <= {MEM_SIZE_LOG2{1'b1}}; + up_src_overflow <= 1'b0; + up_dst_underflow <= 1'b0; + end else begin + up_wack <= up_wreq; + /* Scratch Register */ + if ((up_wreq == 1'b1) && (up_waddr[13:0] == 14'h02)) begin + up_scratch <= up_wdata; + end + /* Transfer Length Register */ + if ((up_wreq == 1'b1) && (up_waddr[13:0] == 14'h07)) begin + up_transfer_length <= {up_wdata[MEM_SIZE_LOG2-7:0], {6{1'b1}}}; + end + /* Memory interface status register */ + if ((up_wreq == 1'b1) && (up_waddr[13:0] == 14'h20) && up_wdata[4]) begin + up_src_overflow <= 1'b0; + end else if (up_src_overflow_set_s) begin + up_src_overflow <= 1'b1; + end + if ((up_wreq == 1'b1) && (up_waddr[13:0] == 14'h20) && up_wdata[5]) begin + up_dst_underflow <= 1'b0; + end else if (up_dst_underflow_set_s) begin + up_dst_underflow <= 1'b1; + end + /* Reset Offload Register */ + if ((up_wreq == 1'b1) && (up_waddr[13:0] == 14'h21)) begin + up_sw_resetn <= up_wdata[0]; + end + /* Control Register */ + if ((up_wreq == 1'b1) && (up_waddr[13:0] == 14'h22)) begin + up_oneshot <= up_wdata[1]; + up_bypass <= up_wdata[0] & HAS_BYPASS; + end + /* SYNC Offload Register - self cleared, one pulse signal */ + if ((up_wreq == 1'b1) && (up_waddr[13:0] == 14'h40)) begin + up_sync <= up_wdata[0]; + end else begin + up_sync <= 1'b0; + end + /* SYNC RX Configuration Register */ + if ((up_wreq == 1'b1) && (up_waddr[13:0] == 14'h41)) begin + up_sync_config <= up_wdata[1:0]; + end + end + end + + //read interface for common registers + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_rack <= 1'b0; + up_rdata <= 32'b0; + end else begin + up_rack <= up_rreq; + case(up_raddr) + + /* Version Register */ + 14'h000: up_rdata <= { + CORE_VERSION[31:16], /* MAJOR */ + CORE_VERSION[15: 8], /* MINOR */ + CORE_VERSION[ 7: 0] /* PATCH */ + }; + /* Peripheral ID Register */ + 14'h001: up_rdata <= ID; + + /* Peripheral ID Register */ + 14'h002: up_rdata <= up_scratch; + + /* Identification Register */ + 14'h003: up_rdata <= CORE_MAGIC; + + /* Configuration Register */ + 14'h004: up_rdata <= { + 29'b0, + /* 2 */ HAS_BYPASS[0], + /* 1 */ TX_OR_RXN_PATH[0], + /* 0 */ MEM_TYPE[0] + }; + /* Configuration Storage Unit Size LSB Register */ + 14'h005: up_rdata <= MEM_SIZE[31:0]; + + /* Configuration Storage Unit Size MSB Register */ + 14'h006: up_rdata <= { + 30'b0, + /* 00-01 */ MEM_SIZE[33:32] + }; + + /* Configuration data transfer length */ + 14'h007: up_rdata <= { + {32-(MEM_SIZE_LOG2-6){1'b0}}, + up_transfer_length[MEM_SIZE_LOG2-1:6] + }; + + /* 0x08-0x1f reserved for future use */ + + /* Memory Physical Interface Status */ + 14'h020: up_rdata <= { + 26'b0, + up_dst_underflow, + up_src_overflow, + 3'b0, + /* 0 */ up_ddr_calib_done_s + }; + /* Reset Offload Register */ + 14'h021: up_rdata <= { + 31'b0, + /* 0 */ up_sw_resetn + }; + /* Control Register */ + 14'h022: up_rdata <= { + 30'b0, + /* 1 */ up_oneshot, + /* 0 */ up_bypass + }; + /* 0x24-0x3f reserved for future use */ + + /* SYNC Offload Register */ + 14'h040: up_rdata <= { + 31'b0, + /* 0 */ up_sync + }; + /* SYNC RX Configuration Register */ + 14'h041: up_rdata <= { + 30'b0, + /* 00-01 */ up_sync_config + }; + /* 0x42-0x7f reserved for future use */ + + /* FMS Debug Register */ + 14'h080: up_rdata <= { + 20'b0, + /* 11-08 */ up_rd_fsm_status_s, + 3'b0, + /* 04-00 */ up_wr_fsm_status_s + }; + + default: up_rdata <= 32'h00000000; + endcase + end + end /* read interface */ + + // Clock Domain Crossing Logic for reset, control and status signals + + sync_data #( + .NUM_OF_BITS (4), + .ASYNC_CLK (1) + ) i_dst_fsm_status ( + .in_clk (dst_clk), + .in_data (dst_fsm_status), + .out_clk (up_clk), + .out_data (up_rd_fsm_status_s)); + + sync_data #( + .NUM_OF_BITS (5), + .ASYNC_CLK (1) + ) i_src_fsm_status ( + .in_clk (src_clk), + .in_data (src_fsm_status), + .out_clk (up_clk), + .out_data (up_wr_fsm_status_s)); + + generate + if (TX_OR_RXN_PATH) begin : sync_tx_path + + sync_data #( + .NUM_OF_BITS (3), + .ASYNC_CLK (1) + ) i_sync_xfer_control ( + .in_clk (up_clk), + .in_data ({up_sync_config, + up_sync}), + .out_clk (dst_clk), + .out_data ({sync_config, + sync})); + + end else begin : sync_rx_path + + sync_data #( + .NUM_OF_BITS (3), + .ASYNC_CLK (1) + ) i_sync_xfer_control ( + .in_clk (up_clk), + .in_data ({up_sync_config, + up_sync}), + .out_clk (src_clk), + .out_data ({sync_config, + sync})); + + end + endgenerate + + sync_bits #( + .NUM_OF_BITS (2), + .ASYNC_CLK (1) + ) i_src_xfer_control ( + .in_bits ({ up_sw_resetn, up_bypass }), + .out_clk (src_clk), + .out_resetn (1'b1), + .out_bits ({ src_sw_resetn_s, src_bypass })); + + sync_bits #( + .NUM_OF_BITS (2), + .ASYNC_CLK (1) + ) i_dst_xfer_control ( + .in_bits ({ up_sw_resetn, up_bypass }), + .out_clk (dst_clk), + .out_resetn (1'b1), + .out_bits ({ dst_sw_resetn_s, dst_bypass })); + + sync_bits #( + .NUM_OF_BITS (1), + .ASYNC_CLK (1) + ) i_ddr_calib_done_sync ( + .in_bits (ddr_calib_done), + .out_clk (up_clk), + .out_resetn (1'b1), + .out_bits (up_ddr_calib_done_s)); + + sync_bits #( + .NUM_OF_BITS (1), + .ASYNC_CLK (1) + ) i_dst_oneshot_sync ( + .in_bits (up_oneshot), + .out_clk (dst_clk), + .out_resetn (1'b1), + .out_bits (oneshot)); + + sync_data #( + .NUM_OF_BITS (MEM_SIZE_LOG2), + .ASYNC_CLK (1) + ) i_sync_src_transfer_length ( + .in_clk (up_clk), + .in_data (up_transfer_length), + .out_clk (src_clk), + .out_data (src_transfer_length)); + + sync_data #( + .NUM_OF_BITS (MEM_SIZE_LOG2), + .ASYNC_CLK (1) + ) i_sync_dst_transfer_length ( + .in_clk (up_clk), + .in_data (up_transfer_length), + .out_clk (dst_clk), + .out_data (dst_transfer_length)); + + always @(posedge src_clk) begin + src_sw_resetn <= src_sw_resetn_s; + end + + always @(posedge dst_clk) begin + dst_sw_resetn <= dst_sw_resetn_s; + end + + generate if (TX_OR_RXN_PATH == 0) begin + sync_event #( + .NUM_OF_EVENTS (1), + .ASYNC_CLK (1) + ) i_wr_overflow_sync ( + .in_clk (src_clk), + .in_event (src_overflow), + .out_clk (up_clk), + .out_event (up_src_overflow_set_s)); + assign up_dst_underflow_set_s = 1'b0; + end else begin + sync_event #( + .NUM_OF_EVENTS (1), + .ASYNC_CLK (1) + ) i_rd_underflow_sync ( + .in_clk (dst_clk), + .in_event (dst_underflow), + .out_clk (up_clk), + .out_event (up_dst_underflow_set_s)); + assign up_src_overflow_set_s = 1'b0; + end + endgenerate + +endmodule diff --git a/adi_library/data_offload/data_offload_sv.ttcl b/adi_library/data_offload/data_offload_sv.ttcl new file mode 100644 index 00000000..6c502c21 --- /dev/null +++ b/adi_library/data_offload/data_offload_sv.ttcl @@ -0,0 +1,46 @@ +############################################################################### +## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +# SPDX short identifier: ADIBSD +############################################################################### + +<: :> +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./sim/" :> +<: setFileName ${ComponentName}_pkg :> +<: setFileExtension ".sv" :> +<: set id [get_property MODELPARAM_VALUE.ID] :> +<: set mem_type [get_property MODELPARAM_VALUE.MEM_TYPE] :> +<: set mem_size_log2 [get_property MODELPARAM_VALUE.MEM_SIZE_LOG2] :> +<: set tx_or_rxn_path [get_property MODELPARAM_VALUE.TX_OR_RXN_PATH] :> +<: set src_data_width [get_property MODELPARAM_VALUE.src_data_width] :> +<: set dst_data_width [get_property MODELPARAM_VALUE.dst_data_width] :> +<: set dst_cyclic_en [get_property MODELPARAM_VALUE.dst_cyclic_en] :> + +// boolean to intiger +<: proc b2i {b} { if {$b==true} {return 1} else {return 0}} :> + +// C hex to verilog hex +<: proc h2vh {a} { return [string replace $a 0 1 "'h"]} :> + +/////////////////////////////////////////////////////////////////////////// +//NOTE: This file has been automatically generated by Vivado. +/////////////////////////////////////////////////////////////////////////// + +package <=: ComponentName :>_pkg; + +/////////////////////////////////////////////////////////////////////////// +// These parameters are named after the component for use in your verification +// environment. +/////////////////////////////////////////////////////////////////////////// + + parameter <=: ComponentName :>_ID = <=: $id :>; + parameter <=: ComponentName :>_MEM_TYPE = <=: $mem_type :>; + parameter <=: ComponentName :>_MEM_SIZE_LOG2 = <=: $mem_size_log2 :>; + parameter <=: ComponentName :>_TX_OR_RXN_PATH = <=: b2i $tx_or_rxn_path :>; + parameter <=: ComponentName :>_SRC_DATA_WIDTH = <=: b2i $src_data_width :>; + parameter <=: ComponentName :>_DST_DATA_WIDTH = <=: b2i $dst_data_width :>; + parameter <=: ComponentName :>_DST_CYCLIC_EN = <=: b2i $dst_cyclic_en :>; + +////////////////////////////////////////////////////////////////////////// + +endpackage : <=: ComponentName :>_pkg diff --git a/adi_library/data_offload/docs/architecture_DDR.svg b/adi_library/data_offload/docs/architecture_DDR.svg new file mode 100755 index 00000000..6bea3e11 --- /dev/null +++ b/adi_library/data_offload/docs/architecture_DDR.svg @@ -0,0 +1,1260 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + AXIS + + TX OFFLOAD FSM + + + ACK + REQ + N*16 + + + CDCFIFO + + + + + + MIG + TRAFFIC + CONTROL + + + FIFO + + AXIS + + RX OFFLOAD FSM + J*16 + + + + ACK + REQ + FIFO + AXIS + AXIS + DDRDW[512] + + CDCFIFO + AXIS + + + AXIS + DDRDW[512] + M*16 + I*16 + + + DMA + DMA + DAC + ADC + + CDCFIFO + + + + + AD_MEM_ASYM + ADDR GENERATORCYCLIC CNTRL + FIFO with cyclic buffer capability + + + + + + + Empty + + UNF + Full + + OVF + + + + + + Packetized stream + Continuous stream + Depacketizer + DDRDW[512] + MEMORY + + diff --git a/adi_library/data_offload/docs/clocks.svg b/adi_library/data_offload/docs/clocks.svg new file mode 100755 index 00000000..547f466a --- /dev/null +++ b/adi_library/data_offload/docs/clocks.svg @@ -0,0 +1,761 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + CDCFIFO + CDCFIFO + AXI REGISTERMAP + MEMORY + GEARBOX + GEARBOX + OFFLOAD FSM + + + CDCFIFO + GEARBOX + + + CDCFIFO + GEARBOX + + + + + + + + + + + + + + + USR_CLK + + + + + + + + + + + SYS_CLK + + DMA_CLK + + DMA_CLK + + DAC_CLK + + ADC_CLK + + diff --git a/adi_library/data_offload/docs/datapath.svg b/adi_library/data_offload/docs/datapath.svg new file mode 100755 index 00000000..3e551742 --- /dev/null +++ b/adi_library/data_offload/docs/datapath.svg @@ -0,0 +1,501 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + CDCFIFO + CDCFIFO + AXI REGISTERMAP + MEMORY + GEARBOX + GEARBOX + OFFLOAD FSM + + + + SOURCE + SINK + + + + SRC_DW + + + + MEM_DW + MEM_DW + MEM_DW + MEM_DW + SINK_DW + + + + + diff --git a/adi_library/data_offload/docs/generic_bd.svg b/adi_library/data_offload/docs/generic_bd.svg new file mode 100755 index 00000000..dc10b53b --- /dev/null +++ b/adi_library/data_offload/docs/generic_bd.svg @@ -0,0 +1,532 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + OFFLOAD FSM + + + + AXI REGISTERMAP + BYPASS + + S_AXIS + + AXI_MM + SOURCE + M_AXIS + + DESTINATION + + + M_STORAGE_AXIS + S_STORAGE_AXIS + + Storage Unit + + diff --git a/adi_library/data_offload/docs/interface.svg b/adi_library/data_offload/docs/interface.svg new file mode 100755 index 00000000..995301a0 --- /dev/null +++ b/adi_library/data_offload/docs/interface.svg @@ -0,0 +1,572 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + AXI REGISTERMAP + MEMORY + CDC FIFO & GEARBOX + + + + + + + + + + + + AXI_MM + CDC FIFO & GEARBOX + CDC FIFO & GEARBOX + CDC FIFO & GEARBOX + DAC + + S_AXIS + + + FIFO_WR + M_AXIS + + + FIFO_RD + ADC + DMA + DMA + + diff --git a/adi_library/data_offload/docs/rx_bram_fsm.svg b/adi_library/data_offload/docs/rx_bram_fsm.svg new file mode 100755 index 00000000..cbd75187 --- /dev/null +++ b/adi_library/data_offload/docs/rx_bram_fsm.svg @@ -0,0 +1,518 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + IDLE + + + + STANDBY + INIT_REQ + + SYNC + + FILL UP MEMORY + + ~FULL + + + + TLAST + READMEMORY + + + PAD ITWITH ZEROS + EMPTY + + + + FULL + + ~EMPTY + + diff --git a/adi_library/data_offload/docs/simple_fifo.svg b/adi_library/data_offload/docs/simple_fifo.svg new file mode 100755 index 00000000..845c7234 --- /dev/null +++ b/adi_library/data_offload/docs/simple_fifo.svg @@ -0,0 +1,225 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + FIFO + + + WREN + WDATA + + + RDEN + RDATA + + diff --git a/adi_library/data_offload/docs/tx_bram_fsm.svg b/adi_library/data_offload/docs/tx_bram_fsm.svg new file mode 100755 index 00000000..eb8d2a04 --- /dev/null +++ b/adi_library/data_offload/docs/tx_bram_fsm.svg @@ -0,0 +1,549 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + IDLE + + + + STANDBY + INIT_REQ + + SYNC + + FILL UP MEMORY + + ~FULL | ~TLAST + + + + INIT_REQ + READMEMORY + ONE-SHOT + + + + FULL | TLAST + + CYCLIC + + diff --git a/adi_library/data_offload/gui/data_offload_v1_0.gtcl b/adi_library/data_offload/gui/data_offload_v1_0.gtcl new file mode 100644 index 00000000..a24d7a68 --- /dev/null +++ b/adi_library/data_offload/gui/data_offload_v1_0.gtcl @@ -0,0 +1,2 @@ +# This file is automatically written. Do not modify. +proc gen_USERPARAMETER_DST_CYCLIC_EN_ENABLEMENT {TX_OR_RXN_PATH } {expr $TX_OR_RXN_PATH == 1} diff --git a/adi_library/data_offload/xgui/data_offload_v1_0.tcl b/adi_library/data_offload/xgui/data_offload_v1_0.tcl new file mode 100644 index 00000000..43f7100b --- /dev/null +++ b/adi_library/data_offload/xgui/data_offload_v1_0.tcl @@ -0,0 +1,185 @@ + +# Loading additional proc with user specified bodies to compute parameter values. +source [file join [file dirname [file dirname [info script]]] gui/data_offload_v1_0.gtcl] + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Data_Offload [ipgui::add_page $IPINST -name "Data Offload"] + #Adding Group + set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${Data_Offload}] + ipgui::add_param $IPINST -name "ID" -parent ${General_Configuration} + ipgui::add_param $IPINST -name "TX_OR_RXN_PATH" -parent ${General_Configuration} -widget comboBox + ipgui::add_param $IPINST -name "MEM_TYPE" -parent ${General_Configuration} -widget comboBox + set MEM_SIZE_LOG2 [ipgui::add_param $IPINST -name "MEM_SIZE_LOG2" -parent ${General_Configuration} -widget comboBox] + set_property tooltip {Log2 value of Storage Size in bytes} ${MEM_SIZE_LOG2} + + #Adding Group + set Source_Endpoint_Configuration [ipgui::add_group $IPINST -name "Source Endpoint Configuration" -parent ${Data_Offload} -layout horizontal] + ipgui::add_param $IPINST -name "SRC_DATA_WIDTH" -parent ${Source_Endpoint_Configuration} + + #Adding Group + set Destination_Endpoint_Configuration [ipgui::add_group $IPINST -name "Destination Endpoint Configuration" -parent ${Data_Offload} -layout horizontal] + ipgui::add_param $IPINST -name "DST_DATA_WIDTH" -parent ${Destination_Endpoint_Configuration} + + #Adding Group + set Features [ipgui::add_group $IPINST -name "Features" -parent ${Data_Offload}] + ipgui::add_param $IPINST -name "HAS_BYPASS" -parent ${Features} + ipgui::add_param $IPINST -name "DST_CYCLIC_EN" -parent ${Features} + ipgui::add_param $IPINST -name "SYNC_EXT_ADD_INTERNAL_CDC" -parent ${Features} + + + +} + +proc update_PARAM_VALUE.DST_CYCLIC_EN { PARAM_VALUE.DST_CYCLIC_EN PARAM_VALUE.TX_OR_RXN_PATH } { + # Procedure called to update DST_CYCLIC_EN when any of the dependent parameters in the arguments change + + set DST_CYCLIC_EN ${PARAM_VALUE.DST_CYCLIC_EN} + set TX_OR_RXN_PATH ${PARAM_VALUE.TX_OR_RXN_PATH} + set values(TX_OR_RXN_PATH) [get_property value $TX_OR_RXN_PATH] + if { [gen_USERPARAMETER_DST_CYCLIC_EN_ENABLEMENT $values(TX_OR_RXN_PATH)] } { + set_property enabled true $DST_CYCLIC_EN + } else { + set_property enabled false $DST_CYCLIC_EN + } +} + +proc validate_PARAM_VALUE.DST_CYCLIC_EN { PARAM_VALUE.DST_CYCLIC_EN } { + # Procedure called to validate DST_CYCLIC_EN + return true +} + +proc update_PARAM_VALUE.AUTO_BRINGUP { PARAM_VALUE.AUTO_BRINGUP } { + # Procedure called to update AUTO_BRINGUP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AUTO_BRINGUP { PARAM_VALUE.AUTO_BRINGUP } { + # Procedure called to validate AUTO_BRINGUP + return true +} + +proc update_PARAM_VALUE.DST_DATA_WIDTH { PARAM_VALUE.DST_DATA_WIDTH } { + # Procedure called to update DST_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DST_DATA_WIDTH { PARAM_VALUE.DST_DATA_WIDTH } { + # Procedure called to validate DST_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.HAS_BYPASS { PARAM_VALUE.HAS_BYPASS } { + # Procedure called to update HAS_BYPASS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.HAS_BYPASS { PARAM_VALUE.HAS_BYPASS } { + # Procedure called to validate HAS_BYPASS + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.MEM_SIZE_LOG2 { PARAM_VALUE.MEM_SIZE_LOG2 } { + # Procedure called to update MEM_SIZE_LOG2 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.MEM_SIZE_LOG2 { PARAM_VALUE.MEM_SIZE_LOG2 } { + # Procedure called to validate MEM_SIZE_LOG2 + return true +} + +proc update_PARAM_VALUE.MEM_TYPE { PARAM_VALUE.MEM_TYPE } { + # Procedure called to update MEM_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.MEM_TYPE { PARAM_VALUE.MEM_TYPE } { + # Procedure called to validate MEM_TYPE + return true +} + +proc update_PARAM_VALUE.SRC_DATA_WIDTH { PARAM_VALUE.SRC_DATA_WIDTH } { + # Procedure called to update SRC_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SRC_DATA_WIDTH { PARAM_VALUE.SRC_DATA_WIDTH } { + # Procedure called to validate SRC_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.SYNC_EXT_ADD_INTERNAL_CDC { PARAM_VALUE.SYNC_EXT_ADD_INTERNAL_CDC } { + # Procedure called to update SYNC_EXT_ADD_INTERNAL_CDC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SYNC_EXT_ADD_INTERNAL_CDC { PARAM_VALUE.SYNC_EXT_ADD_INTERNAL_CDC } { + # Procedure called to validate SYNC_EXT_ADD_INTERNAL_CDC + return true +} + +proc update_PARAM_VALUE.TX_OR_RXN_PATH { PARAM_VALUE.TX_OR_RXN_PATH } { + # Procedure called to update TX_OR_RXN_PATH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TX_OR_RXN_PATH { PARAM_VALUE.TX_OR_RXN_PATH } { + # Procedure called to validate TX_OR_RXN_PATH + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.MEM_TYPE { MODELPARAM_VALUE.MEM_TYPE PARAM_VALUE.MEM_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.MEM_TYPE}] ${MODELPARAM_VALUE.MEM_TYPE} +} + +proc update_MODELPARAM_VALUE.MEM_SIZE_LOG2 { MODELPARAM_VALUE.MEM_SIZE_LOG2 PARAM_VALUE.MEM_SIZE_LOG2 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.MEM_SIZE_LOG2}] ${MODELPARAM_VALUE.MEM_SIZE_LOG2} +} + +proc update_MODELPARAM_VALUE.TX_OR_RXN_PATH { MODELPARAM_VALUE.TX_OR_RXN_PATH PARAM_VALUE.TX_OR_RXN_PATH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TX_OR_RXN_PATH}] ${MODELPARAM_VALUE.TX_OR_RXN_PATH} +} + +proc update_MODELPARAM_VALUE.SRC_DATA_WIDTH { MODELPARAM_VALUE.SRC_DATA_WIDTH PARAM_VALUE.SRC_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SRC_DATA_WIDTH}] ${MODELPARAM_VALUE.SRC_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.DST_DATA_WIDTH { MODELPARAM_VALUE.DST_DATA_WIDTH PARAM_VALUE.DST_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DST_DATA_WIDTH}] ${MODELPARAM_VALUE.DST_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.DST_CYCLIC_EN { MODELPARAM_VALUE.DST_CYCLIC_EN PARAM_VALUE.DST_CYCLIC_EN } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DST_CYCLIC_EN}] ${MODELPARAM_VALUE.DST_CYCLIC_EN} +} + +proc update_MODELPARAM_VALUE.AUTO_BRINGUP { MODELPARAM_VALUE.AUTO_BRINGUP PARAM_VALUE.AUTO_BRINGUP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AUTO_BRINGUP}] ${MODELPARAM_VALUE.AUTO_BRINGUP} +} + +proc update_MODELPARAM_VALUE.SYNC_EXT_ADD_INTERNAL_CDC { MODELPARAM_VALUE.SYNC_EXT_ADD_INTERNAL_CDC PARAM_VALUE.SYNC_EXT_ADD_INTERNAL_CDC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SYNC_EXT_ADD_INTERNAL_CDC}] ${MODELPARAM_VALUE.SYNC_EXT_ADD_INTERNAL_CDC} +} + +proc update_MODELPARAM_VALUE.HAS_BYPASS { MODELPARAM_VALUE.HAS_BYPASS PARAM_VALUE.HAS_BYPASS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.HAS_BYPASS}] ${MODELPARAM_VALUE.HAS_BYPASS} +} + diff --git a/adi_library/intel/adi_jesd204/.timestamp_intel b/adi_library/intel/adi_jesd204/.timestamp_intel new file mode 100644 index 00000000..e69de29b diff --git a/adi_library/intel/adi_jesd204/Makefile b/adi_library/intel/adi_jesd204/Makefile new file mode 100644 index 00000000..91dab071 --- /dev/null +++ b/adi_library/intel/adi_jesd204/Makefile @@ -0,0 +1,18 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := adi_jesd204 + +INTEL_DEPS += adi_jesd204_glue.v +INTEL_DEPS += adi_jesd204_glue_hw.tcl +INTEL_DEPS += adi_jesd204_hw.tcl + +INTEL_LIB_DEPS += intel/axi_adxcvr +INTEL_LIB_DEPS += intel/jesd204_phy +INTEL_LIB_DEPS += jesd204/jesd204_soft_pcs_rx +INTEL_LIB_DEPS += jesd204/jesd204_soft_pcs_tx + +include ../../scripts/library.mk diff --git a/adi_library/intel/adi_jesd204/adi_jesd204_glue.v b/adi_library/intel/adi_jesd204/adi_jesd204_glue.v new file mode 100644 index 00000000..9ebf40ef --- /dev/null +++ b/adi_library/intel/adi_jesd204/adi_jesd204_glue.v @@ -0,0 +1,49 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module adi_jesd204_glue ( + input in_pll_powerdown, + output out_pll_powerdown, + output out_mcgb_rst, + output out_pll_select_gnd +); + + assign out_pll_powerdown = in_pll_powerdown; + assign out_mcgb_rst = in_pll_powerdown; + assign out_pll_select_gnd = 1'b0; + +endmodule diff --git a/adi_library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl b/adi_library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl new file mode 100644 index 00000000..d775f0a4 --- /dev/null +++ b/adi_library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl @@ -0,0 +1,36 @@ +############################################################################### +## Copyright (C) 2016, 2018, 2019, 2020, 2021, 2022 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +package require qsys 14.0 +source ../../../scripts/adi_env.tcl +source ../../scripts/adi_ip_intel.tcl + + +ad_ip_create adi_jesd204_glue {Glue} jesd204_phy_glue_elab +set_module_property INTERNAL true + +# files + +ad_ip_files adi_jesd204_glue [list \ + adi_jesd204_glue.v \ +] + +# parameters + +ad_ip_parameter IN_PLL_POWERDOWN_EN BOOLEAN 1 false + +proc jesd204_phy_glue_elab {} { + add_interface in_pll_powerdown conduit end + add_interface_port in_pll_powerdown in_pll_powerdown pll_powerdown Input 1 + set_interface_property in_pll_powerdown ENABLED [get_parameter IN_PLL_POWERDOWN_EN] + + add_interface out_pll_powerdown conduit end + add_interface_port out_pll_powerdown out_pll_powerdown pll_powerdown Output 1 + add_interface out_mcgb_rst conduit end + add_interface_port out_mcgb_rst out_mcgb_rst mcgb_rst Output 1 + + add_interface out_pll_select_gnd conduit end + add_interface_port out_pll_select_gnd out_pll_select_gnd pll_select Output 1 +} diff --git a/adi_library/intel/adi_jesd204/adi_jesd204_hw.tcl b/adi_library/intel/adi_jesd204/adi_jesd204_hw.tcl new file mode 100644 index 00000000..41487aa7 --- /dev/null +++ b/adi_library/intel/adi_jesd204/adi_jesd204_hw.tcl @@ -0,0 +1,598 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +package require qsys 14.0 +source ../../../scripts/adi_env.tcl +source ../../scripts/adi_ip_intel.tcl + +# +# Wrapper module that instantiates and connects all the components required to +# for a JESD204 link. +# +# The following components are created: +# * Transceiver for each lane +# * Transceiver lane PLL (TX only) +# * Transceiver reset controller +# * Link PLL +# * JESD204 link layer processing +# * JESD204 link layer processing control interface +# * axi_adxcvr link management peripheral +# + +ad_ip_create adi_jesd204 {Analog Devices JESD204} +set_module_property VALIDATION_CALLBACK jesd204_validate +set_module_property COMPOSITION_CALLBACK jesd204_compose + +# parameters + +ad_ip_parameter DEVICE_FAMILY STRING "" false { + VISIBLE true +} + +ad_ip_parameter DEVICE STRING "" false { + SYSTEM_INFO DEVICE + VISIBLE false +} + +ad_ip_parameter TX_OR_RX_N BOOLEAN 0 false { \ + DISPLAY_HINT "radio" \ + DISPLAY_NAME "Data Path" \ + ALLOWED_RANGES { "0:Receive" "1:Transmit" } +} + +ad_ip_parameter ID NATURAL 0 false { \ + DISPLAY_NAME "Core ID" \ +} + +ad_ip_parameter LANE_RATE FLOAT 10000 false { \ + DISPLAY_NAME "Lane Rate" \ + DISPLAY_UNITS "Mbps" \ +} + +ad_ip_parameter SYSCLK_FREQUENCY FLOAT 100.0 false { \ + DISPLAY_NAME "System Clock Frequency" \ + UNITS Megahertz +} + +ad_ip_parameter REFCLK_FREQUENCY FLOAT 500.0 false { \ + DISPLAY_NAME "Reference Clock Frequency" \ + UNITS Megahertz \ +} + +ad_ip_parameter NUM_OF_LANES POSITIVE 4 false { \ + DISPLAY_NAME "Number of Lanes" \ + ALLOWED_RANGES 1:16 +} + +ad_ip_parameter BONDING_CLOCKS_EN BOOLEAN 0 false { \ + DISPLAY_HINT "Clock Network" \ + DISPLAY_NAME "Clock Network" \ + ALLOWED_RANGES { "0:x1/xN (Non-bonded)" "1:x6/xN (Bonded)" } +} + +ad_ip_parameter LANE_MAP STRING "" false { \ + DISPLAY_NAME "Lane Mapping" \ +} + +ad_ip_parameter LANE_INVERT STD_LOGIC_VECTOR 0 false { \ + DISPLAY_NAME "Lane Invert Mask" \ + DISPLAY_HINT "hexadecimal" \ + WIDTH 8 \ +} + +ad_ip_parameter SOFT_PCS BOOLEAN true false { \ + DISPLAY_NAME "Enable Soft PCS" \ +} + +ad_ip_parameter INPUT_PIPELINE_STAGES INTEGER 0 false { \ + DISPLAY_NAME "Enable input pipeline" \ +} + +ad_ip_parameter EXT_DEVICE_CLK_EN BOOLEAN 0 false { \ + DISPLAY_NAME "External Device Clock Enable" \ +} + +ad_ip_parameter TPL_DATA_PATH_WIDTH INTEGER 4 false { \ + DISPLAY_NAME "Transport layer datapath width" \ + DISPLAY_UNITS "octets" \ + ALLOWED_RANGES {4 6 8 12} \ +} + +proc create_phy_reset_control {tx num_of_lanes sysclk_frequency} { + + set device [get_parameter_value DEVICE_FAMILY] + + if {[string equal $device "Arria 10"]} { + + add_instance phy_reset_control altera_xcvr_reset_control + set_instance_property phy_reset_control SUPPRESS_ALL_WARNINGS true + set_instance_parameter_value phy_reset_control {SYNCHRONIZE_RESET} {0} + set_instance_parameter_value phy_reset_control {CHANNELS} $num_of_lanes + set_instance_parameter_value phy_reset_control {SYS_CLK_IN_MHZ} $sysclk_frequency + set_instance_parameter_value phy_reset_control {TX_PLL_ENABLE} $tx + set_instance_parameter_value phy_reset_control {TX_ENABLE} $tx + set_instance_parameter_value phy_reset_control {RX_ENABLE} [expr !$tx] + + add_connection sys_clock.clk phy_reset_control.clock + add_connection link_reset.out_reset phy_reset_control.reset + add_connection sys_clock.clk_reset phy_reset_control.reset + + if {$tx} { + set_instance_parameter_value phy_reset_control {T_PLL_POWERDOWN} {1000} + set_instance_parameter_value phy_reset_control {gui_pll_cal_busy} {1} + set_instance_parameter_value phy_reset_control {T_TX_ANALOGRESET} {70000} + set_instance_parameter_value phy_reset_control {T_TX_DIGITALRESET} {70000} + + add_connection phy_reset_control.tx_ready axi_xcvr.ready + } else { + set_instance_parameter_value phy_reset_control {T_RX_ANALOGRESET} {70000} + set_instance_parameter_value phy_reset_control {T_RX_DIGITALRESET} {4000} + + add_connection phy_reset_control.rx_ready axi_xcvr.ready + } + + } elseif {[string equal $device "Stratix 10"]} { + + add_instance phy_reset_control altera_xcvr_reset_control_s10 + set_instance_parameter_value phy_reset_control {CHANNELS} $num_of_lanes + set_instance_parameter_value phy_reset_control {SYS_CLK_IN_MHZ} $sysclk_frequency + set_instance_parameter_value phy_reset_control {TX_ENABLE} $tx + set_instance_parameter_value phy_reset_control {RX_ENABLE} [expr !$tx] + set_instance_parameter_value phy_reset_control {REDUCED_SIM_TIME} {1} + set_instance_parameter_value phy_reset_control {T_PLL_POWERDOWN} {1000} + set_instance_parameter_value phy_reset_control {T_PLL_LOCK_HYST} {1000} + + add_connection sys_clock.clk phy_reset_control.clock + add_connection link_reset.out_reset phy_reset_control.reset + add_connection sys_clock.clk_reset phy_reset_control.reset + + if {$tx} { + set_instance_parameter_value phy_reset_control {gui_pll_cal_busy} {1} + set_instance_parameter_value phy_reset_control {TX_MANUAL_RESET} {0} + set_instance_parameter_value phy_reset_control {T_TX_ANALOGRESET} {0} + set_instance_parameter_value phy_reset_control {T_TX_DIGITALRESET} {20} + + add_connection phy_reset_control.tx_ready axi_xcvr.ready + } else { + set_instance_parameter_value phy_reset_control {RX_MANUAL_RESET} {0} + set_instance_parameter_value phy_reset_control {T_RX_ANALOGRESET} {40} + set_instance_parameter_value phy_reset_control {T_RX_DIGITALRESET} {5000} + + add_connection phy_reset_control.rx_ready axi_xcvr.ready + } + + } else { + send_message error "Only Arria 10 and Stratix 10 are supported." + } +} + +proc create_lane_pll {id tx_or_rx_n pllclk_frequency refclk_frequency num_lanes bonding_clocks_en} { + + set device_family [get_parameter_value "DEVICE_FAMILY"] + + if {$device_family == "Arria 10"} { + add_instance lane_pll altera_xcvr_atx_pll_a10 + if {$num_lanes > 6} { + set_instance_parameter_value lane_pll enable_mcgb {true} + if {$bonding_clocks_en} { + set_instance_parameter_value lane_pll {enable_bonding_clks} {true} + set_instance_parameter_value lane_pll {mcgb_div} {1} + set_instance_parameter_value lane_pll {set_ref_clk_div} {1} + set_instance_parameter_value lane_pll {pma_width} {40} + } else { + set_instance_parameter_value lane_pll enable_hfreq_clk {true} + } + + add_instance glue adi_jesd204_glue + add_connection phy_reset_control.pll_powerdown glue.in_pll_powerdown + add_connection glue.out_pll_powerdown lane_pll.pll_powerdown + add_connection glue.out_mcgb_rst lane_pll.mcgb_rst + } else { + add_connection phy_reset_control.pll_powerdown lane_pll.pll_powerdown + } + set_instance_parameter_value lane_pll {enable_pll_reconfig} {1} + } elseif {$device_family == "Stratix 10"} { + add_instance lane_pll altera_xcvr_atx_pll_s10_htile + set_instance_parameter_value lane_pll {rcfg_enable} {1} + if {$num_lanes > 6} { + set_instance_parameter_value lane_pll enable_mcgb {true} + if {$bonding_clocks_en} { + set_instance_parameter_value lane_pll {enable_bonding_clks} {true} + set_instance_parameter_value lane_pll {mcgb_div} {1} + set_instance_parameter_value lane_pll {set_ref_clk_div} {1} + set_instance_parameter_value lane_pll {pma_width} {40} + } else { + set_instance_parameter_value lane_pll enable_hfreq_clk {true} + } + } + + ## tie pll_select to GND + add_instance glue adi_jesd204_glue + set_instance_parameter_value glue {IN_PLL_POWERDOWN_EN} {0} + if {$tx_or_rx_n} { + add_connection glue.out_pll_select_gnd phy_reset_control.pll_select + } + + } else { + send_message error "Only Arria 10 and Stratix 10 are supported." + } + + set_instance_parameter_value lane_pll {rcfg_separate_avmm_busy} {1} + set_instance_parameter_value lane_pll {set_capability_reg_enable} {1} + set_instance_parameter_value lane_pll {set_user_identifier} $id + set_instance_parameter_value lane_pll {set_csr_soft_logic_enable} {1} + set_instance_parameter_value lane_pll {set_output_clock_frequency} $pllclk_frequency + set_instance_parameter_value lane_pll {set_auto_reference_clock_frequency} $refclk_frequency + + add_connection lane_pll.pll_locked phy_reset_control.pll_locked + add_connection lane_pll.pll_cal_busy phy_reset_control.pll_cal_busy + add_connection ref_clock.out_clk lane_pll.pll_refclk0 + add_connection sys_clock.clk lane_pll.reconfig_clk0 + add_connection sys_clock.clk_reset lane_pll.reconfig_reset0 + add_interface lane_pll_reconfig avalon slave + set_interface_property lane_pll_reconfig EXPORT_OF lane_pll.reconfig_avmm0 +} + +proc jesd204_get_max_lane_rate {device soft_pcs} { + if {[string range $device 0 2] == "10A"} { + set device_speedgrade [string range $device 13 13] + set pma_speedgrade [string range $device 8 8] + } elseif {[string range $device 0 1] == "1S"} { + set device_speedgrade [string range $device 13 13] + set pma_speedgrade [string range $device 8 8] + } else { + # Assume fastest speed grade + set device_speedgrade 1 + set pma_speedgrade 1 + } + + if {$soft_pcs} { + if {$pma_speedgrade == 1 || $pma_speedgrade == 2} { + return "15000" + } elseif {$pma_speedgrade == 3} { + return "14200" + } else { + return "12500" + } + } else { + if {$device_speedgrade == 1} { + return "12000" + } elseif {$device_speedgrade == 2} { + return "9830" + } else { + return "8936" + } + } +} + +proc jesd204_validate {{quiet false}} { + set soft_pcs [get_parameter_value "SOFT_PCS"] + set input_pipeline [get_parameter_value "INPUT_PIPELINE_STAGES"] + set device_family [get_parameter_value "DEVICE_FAMILY"] + set device [get_parameter_value "DEVICE"] + set lane_rate [get_parameter_value "LANE_RATE"] + set num_of_lanes [get_parameter_value "NUM_OF_LANES"] + set tx_or_rx_n [get_parameter_value "TX_OR_RX_N"] + + if {$device_family != "Arria 10" && $device_family != "Stratix 10"} { + if {!$quiet} { + send_message error "Only Arria 10 and Startix 10 are supported." + } + return false + } + + set max_lane_rate [jesd204_get_max_lane_rate $device $soft_pcs] + + if {$lane_rate < 2000 || $lane_rate > $max_lane_rate} { + if {!$quiet} { + send_message error "Lane rate must be in the range 2000-${max_lane_rate} Mbps." + if {!$soft_pcs} { + send_message error "Consider enabling soft PCS for a higher maximum lane rate." + if {$input_pipeline} { + send_message error "Input pipeline can be active just when soft PCS is used." + } + } + } + return false + } + + set_parameter_property BONDING_CLOCKS_EN VISIBLE [expr ($num_of_lanes > 6) && ($tx_or_rx_n)] + + return true +} + +proc jesd204_compose {} { + + set id [get_parameter_value "ID"] + set lane_rate [get_parameter_value "LANE_RATE"] + set tx_or_rx_n [get_parameter_value "TX_OR_RX_N"] + set num_of_lanes [get_parameter_value "NUM_OF_LANES"] + set sysclk_frequency [get_parameter_value "SYSCLK_FREQUENCY"] + set refclk_frequency [get_parameter_value "REFCLK_FREQUENCY"] + set lane_map [get_parameter_value "LANE_MAP"] + set lane_invert [get_parameter_value "LANE_INVERT"] + set soft_pcs [get_parameter_value "SOFT_PCS"] + set device_family [get_parameter_value "DEVICE_FAMILY"] + set device [get_parameter_value "DEVICE"] + set ext_device_clk_en [get_parameter_value "EXT_DEVICE_CLK_EN"] + set bonding_clocks_en [get_parameter_value "BONDING_CLOCKS_EN"] + set input_pipeline [get_parameter_value "INPUT_PIPELINE_STAGES"] + set tpl_data_path_width [get_parameter_value "TPL_DATA_PATH_WIDTH"] + + set pllclk_frequency [expr $lane_rate / 2] + set linkclk_frequency [expr $lane_rate / 40] + set deviceclk_frequency [expr $linkclk_frequency * 4 / $tpl_data_path_width] + + set dual_clk_mode [expr $tpl_data_path_width > 4] + + if {![jesd204_validate true]} { + return + } + + add_instance sys_clock clock_source + set_instance_parameter_value sys_clock {clockFrequency} [expr $sysclk_frequency*1000000] + set_instance_parameter_value sys_clock {resetSynchronousEdges} {deassert} + add_interface sys_clk clock sink + set_interface_property sys_clk EXPORT_OF sys_clock.clk_in + add_interface sys_resetn reset sink + set_interface_property sys_resetn EXPORT_OF sys_clock.clk_in_reset + + add_instance ref_clock altera_clock_bridge + set_instance_parameter_value ref_clock {EXPLICIT_CLOCK_RATE} [expr $refclk_frequency*1000000] + set_instance_parameter_value ref_clock {NUM_CLOCK_OUTPUTS} 2 + add_interface ref_clk clock sink + set_interface_property ref_clk EXPORT_OF ref_clock.in_clk + + set outclk_name "" + + ## link clock configuration (also known as device clock, which will be used + ## by the upper layers for the data path, it can come from the PCS or external) + + add_instance link_clock altera_clock_bridge + set_instance_parameter_value link_clock {EXPLICIT_CLOCK_RATE} [expr $linkclk_frequency*1000000] + set_instance_parameter_value link_clock {NUM_CLOCK_OUTPUTS} 2 + + add_instance link_reset altera_reset_bridge + set_instance_parameter_value link_reset {NUM_RESET_OUTPUTS} 2 + + if {$dual_clk_mode} { + if {$ext_device_clk_en} { + set link_clock link_clock.out_clk + set device_clock ext_device_clock.out_clk + set device_clock_export ext_device_clock.out_clk_1 + } else { + set link_clock link_clock.out_clk + set device_clock ref_clock.out_clk + set device_clock_export ref_clock.out_clk_1 + } + } else { + if {$ext_device_clk_en} { + set link_clock ext_device_clock.out_clk + set device_clock ext_device_clock.out_clk + set device_clock_export ext_device_clock.out_clk_1 + } else { + set link_clock link_clock.out_clk + set device_clock link_clock.out_clk + set device_clock_export link_clock.out_clk_1 + } + } + + if {$device_family == "Arria 10"} { + + add_instance link_pll altera_xcvr_fpll_a10 + set_instance_parameter_value link_pll {gui_fpll_mode} {0} + set_instance_parameter_value link_pll {gui_reference_clock_frequency} $refclk_frequency + set_instance_parameter_value link_pll {gui_number_of_output_clocks} 2 + set_instance_parameter_value link_pll {gui_enable_phase_alignment} 1 + set_instance_parameter_value link_pll {gui_desired_outclk0_frequency} $linkclk_frequency + set_instance_parameter_value link_pll {enable_pll_reconfig} {1} + set pfdclk_frequency [get_instance_parameter_value link_pll gui_pfd_frequency] + set_instance_parameter_value link_pll {gui_desired_outclk1_frequency} $pfdclk_frequency + + set outclk_name "outclk0" + + add_instance link_pll_reset_control altera_xcvr_reset_control + set_instance_parameter_value link_pll_reset_control {SYNCHRONIZE_RESET} {0} + set_instance_parameter_value link_pll_reset_control {SYS_CLK_IN_MHZ} $sysclk_frequency + set_instance_parameter_value link_pll_reset_control {TX_PLL_ENABLE} {1} + set_instance_parameter_value link_pll_reset_control {T_PLL_POWERDOWN} {1000} + set_instance_parameter_value link_pll_reset_control {TX_ENABLE} {0} + set_instance_parameter_value link_pll_reset_control {RX_ENABLE} {0} + add_connection sys_clock.clk link_pll_reset_control.clock + add_connection link_reset.out_reset link_pll_reset_control.reset + add_connection sys_clock.clk_reset link_pll_reset_control.reset + add_connection link_pll_reset_control.pll_powerdown link_pll.pll_powerdown + + } elseif {$device_family == "Stratix 10"} { + + send_message info "Instantiate a fpll_s10_htile for link_pll." + add_instance link_pll altera_xcvr_fpll_s10_htile + ## Primary Use is Core mode + set_instance_parameter_value link_pll {set_primary_use} 0 + ## Basic Mode + set_instance_parameter_value link_pll {set_prot_mode} 0 + set_instance_parameter_value link_pll {message_level} {error} + set_instance_parameter_value link_pll {set_refclk_cnt} {1} + set_instance_parameter_value link_pll {set_auto_reference_clock_frequency} $refclk_frequency + set_instance_parameter_value link_pll {set_output_clock_frequency} $linkclk_frequency + set_instance_parameter_value link_pll {set_bw_sel} {medium} + set_instance_parameter_value link_pll {rcfg_enable} {1} + set_instance_parameter_value link_pll {set_csr_soft_logic_enable} {1} + set_instance_parameter_value link_pll {set_capability_reg_enable} {1} + + set outclk_name "outclk_div1" + + } else { + ## Unsupported device + send_message error "Only Arria 10 and Stratix 10 are supported." + } + + add_connection link_pll.$outclk_name link_clock.in_clk + add_interface link_clk clock source + + add_connection sys_clock.clk link_reset.clk + add_interface link_reset reset source + set_interface_property link_reset EXPORT_OF link_reset.out_reset_1 + + set_instance_parameter_value link_pll {set_capability_reg_enable} {1} + set_instance_parameter_value link_pll {set_csr_soft_logic_enable} {1} + set_instance_parameter_value link_pll {rcfg_separate_avmm_busy} {1} + add_connection ref_clock.out_clk link_pll.pll_refclk0 + + add_connection sys_clock.clk_reset link_pll.reconfig_reset0 + add_connection sys_clock.clk link_pll.reconfig_clk0 + + add_instance axi_xcvr axi_adxcvr + set_instance_parameter_value axi_xcvr {ID} $id + set_instance_parameter_value axi_xcvr {TX_OR_RX_N} $tx_or_rx_n + set_instance_parameter_value axi_xcvr {NUM_OF_LANES} $num_of_lanes + + add_connection sys_clock.clk axi_xcvr.s_axi_clock + add_connection sys_clock.clk_reset axi_xcvr.s_axi_reset + add_connection axi_xcvr.if_up_rst link_reset.in_reset + add_connection link_pll.pll_locked axi_xcvr.core_pll_locked + + add_interface link_management axi4lite slave + set_interface_property link_management EXPORT_OF axi_xcvr.s_axi + + add_interface link_pll_reconfig avalon slave + set_interface_property link_pll_reconfig EXPORT_OF link_pll.reconfig_avmm0 + set_interface_property link_pll_reconfig associatedClock sys_clk + set_interface_property link_pll_reconfig associatedReset sys_resetn + + + create_phy_reset_control $tx_or_rx_n $num_of_lanes $sysclk_frequency + + add_instance phy jesd204_phy + set_instance_parameter_value phy ID $id + set_instance_parameter_value phy DEVICE $device_family + set_instance_parameter_value phy SOFT_PCS $soft_pcs + set_instance_parameter_value phy TX_OR_RX_N $tx_or_rx_n + set_instance_parameter_value phy LANE_RATE $lane_rate + set_instance_parameter_value phy REFCLK_FREQUENCY $refclk_frequency + set_instance_parameter_value phy NUM_OF_LANES $num_of_lanes + set_instance_parameter_value phy REGISTER_INPUTS $input_pipeline + set_instance_parameter_value phy LANE_INVERT $lane_invert + set_instance_parameter_value phy BONDING_CLOCKS_EN $bonding_clocks_en + + add_connection link_reset.out_reset phy.link_reset + add_connection sys_clock.clk phy.reconfig_clk + add_connection sys_clock.clk_reset phy.reconfig_reset + + ## connect the required device clock + + if {$ext_device_clk_en} { + add_instance ext_device_clock altera_clock_bridge + set_instance_parameter_value ext_device_clock {EXPLICIT_CLOCK_RATE} [expr $deviceclk_frequency*1000000] + set_instance_parameter_value ext_device_clock {NUM_CLOCK_OUTPUTS} 2 + add_interface device_clk clock sink + set_interface_property device_clk EXPORT_OF ext_device_clock.in_clk + } + add_connection $link_clock phy.link_clk + set_interface_property link_clk EXPORT_OF $device_clock_export + + set phy_reset_intfs_s10 {analogreset_stat digitalreset_stat} + + if {$tx_or_rx_n} { + set tx_rx "tx" + set data_direction sink + set jesd204_intfs {config device_config control ilas_config device_event status} + set phy_reset_intfs {analogreset digitalreset cal_busy} + + create_lane_pll $id $tx_or_rx_n $pllclk_frequency $refclk_frequency $num_of_lanes $bonding_clocks_en + if {$num_of_lanes > 6} { + if {$bonding_clocks_en} { + add_connection lane_pll.tx_bonding_clocks phy.bonding_clocks + } else { + add_connection lane_pll.tx_serial_clk phy.serial_clk_x1 + add_connection lane_pll.mcgb_serial_clk phy.serial_clk_xN + } + } else { + add_connection lane_pll.tx_serial_clk phy.serial_clk_x1 + } + } else { + set tx_rx "rx" + set data_direction source + set jesd204_intfs {config device_config ilas_config device_event status} + set phy_reset_intfs {analogreset digitalreset cal_busy is_lockedtodata} + + add_connection ref_clock.out_clk phy.ref_clk + } + + add_instance axi_jesd204_${tx_rx} axi_jesd204_${tx_rx} + set_instance_parameter_value axi_jesd204_${tx_rx} {NUM_LANES} $num_of_lanes + + add_connection sys_clock.clk axi_jesd204_${tx_rx}.s_axi_clock + add_connection sys_clock.clk_reset axi_jesd204_${tx_rx}.s_axi_reset + + add_instance jesd204_${tx_rx} jesd204_${tx_rx} + set_instance_parameter_value jesd204_${tx_rx} {NUM_LANES} $num_of_lanes + set_instance_parameter_value jesd204_${tx_rx} {ASYNC_CLK} $dual_clk_mode + set_instance_parameter_value jesd204_${tx_rx} {TPL_DATA_PATH_WIDTH} $tpl_data_path_width + + add_connection $link_clock axi_jesd204_${tx_rx}.core_clock + add_connection $device_clock axi_jesd204_${tx_rx}.device_clock + add_connection $link_clock jesd204_${tx_rx}.clock + add_connection $device_clock jesd204_${tx_rx}.device_clock + + add_connection link_reset.out_reset axi_jesd204_${tx_rx}.core_reset_ext + add_connection axi_jesd204_${tx_rx}.core_reset jesd204_${tx_rx}.reset + add_connection axi_jesd204_${tx_rx}.device_reset jesd204_${tx_rx}.device_reset + + foreach intf $jesd204_intfs { + add_connection axi_jesd204_${tx_rx}.${intf} jesd204_${tx_rx}.${intf} + } + + foreach intf $phy_reset_intfs { + add_connection phy_reset_control.${tx_rx}_${intf} phy.${intf} + } + + ## connect phy_reset_control interfaces specific to Stratix 10 + if {$device_family == "Stratix 10"} { + foreach intf $phy_reset_intfs_s10 { + add_connection phy_reset_control.${tx_rx}_${intf} phy.${intf} + } + + } + + set lane_map [regexp -all -inline {\S+} $lane_map] + for {set i 0} {$i < $num_of_lanes} {incr i} { + if {$lane_map != {}} { + set j [lindex $lane_map $i] + } else { + set j $i + } + + add_connection jesd204_${tx_rx}.${tx_rx}_phy${j} phy.phy_${i} + } + + for {set i 0} {$i < $num_of_lanes} {incr i} { + add_interface phy_reconfig_${i} avalon slave + set_interface_property phy_reconfig_${i} EXPORT_OF phy.reconfig_avmm_${i} + } + + add_interface interrupt interrupt end + set_interface_property interrupt EXPORT_OF axi_jesd204_${tx_rx}.interrupt + add_interface link_reconfig axi4lite slave + set_interface_property link_reconfig EXPORT_OF axi_jesd204_${tx_rx}.s_axi + + add_interface link_data avalon_streaming $data_direction + set_interface_property link_data EXPORT_OF jesd204_${tx_rx}.${tx_rx}_data + + if {!$tx_or_rx_n} { + add_interface link_sof conduit end + set_interface_property link_sof EXPORT_OF jesd204_rx.rx_sof + } + + add_interface sysref conduit end + set_interface_property sysref EXPORT_OF jesd204_${tx_rx}.sysref + + add_interface sync conduit end + set_interface_property sync EXPORT_OF jesd204_${tx_rx}.sync + + add_interface serial_data conduit end + set_interface_property serial_data EXPORT_OF phy.serial_data + +} diff --git a/adi_library/intel/avl_adxcfg/.timestamp_intel b/adi_library/intel/avl_adxcfg/.timestamp_intel new file mode 100644 index 00000000..e69de29b diff --git a/adi_library/intel/avl_adxcfg/Makefile b/adi_library/intel/avl_adxcfg/Makefile new file mode 100644 index 00000000..b09e72ab --- /dev/null +++ b/adi_library/intel/avl_adxcfg/Makefile @@ -0,0 +1,12 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := avl_adxcfg + +INTEL_DEPS += avl_adxcfg.v +INTEL_DEPS += avl_adxcfg_hw.tcl + +include ../../scripts/library.mk diff --git a/adi_library/intel/avl_adxcfg/avl_adxcfg.v b/adi_library/intel/avl_adxcfg/avl_adxcfg.v new file mode 100644 index 00000000..af903946 --- /dev/null +++ b/adi_library/intel/avl_adxcfg/avl_adxcfg.v @@ -0,0 +1,164 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module avl_adxcfg #( + + parameter ADDRESS_WIDTH = 10 +) ( + + // reconfig sharing + + input rcfg_clk, + input rcfg_reset_n, + + input rcfg_in_read_0, + input rcfg_in_write_0, + input [ADDRESS_WIDTH-1:0] rcfg_in_address_0, + input [31:0] rcfg_in_writedata_0, + output [31:0] rcfg_in_readdata_0, + output rcfg_in_waitrequest_0, + + input rcfg_in_read_1, + input rcfg_in_write_1, + input [ADDRESS_WIDTH-1:0] rcfg_in_address_1, + input [31:0] rcfg_in_writedata_1, + output [31:0] rcfg_in_readdata_1, + output rcfg_in_waitrequest_1, + + output rcfg_out_read_0, + output rcfg_out_write_0, + output [ADDRESS_WIDTH-1:0] rcfg_out_address_0, + output [31:0] rcfg_out_writedata_0, + input [31:0] rcfg_out_readdata_0, + input rcfg_out_waitrequest_0, + + output rcfg_out_read_1, + output rcfg_out_write_1, + output [ADDRESS_WIDTH-1:0] rcfg_out_address_1, + output [31:0] rcfg_out_writedata_1, + input [31:0] rcfg_out_readdata_1, + input rcfg_out_waitrequest_1 +); + + // internal registers + + reg [ 1:0] rcfg_select = 'd0; + reg rcfg_read_int = 'd0; + reg rcfg_write_int = 'd0; + reg [ADDRESS_WIDTH-1:0] rcfg_address_int = 'd0; + reg [31:0] rcfg_writedata_int = 'd0; + reg [31:0] rcfg_readdata_int = 'd0; + reg rcfg_waitrequest_int_0 = 'd1; + reg rcfg_waitrequest_int_1 = 'd1; + + // internal signals + + wire [31:0] rcfg_readdata_s; + wire rcfg_waitrequest_s; + + // xcvr sharing requires same bus (sw must make sure they are mutually exclusive access). + + assign rcfg_out_read_0 = rcfg_read_int; + assign rcfg_out_write_0 = rcfg_write_int; + assign rcfg_out_address_0 = rcfg_address_int; + assign rcfg_out_writedata_0 = rcfg_writedata_int; + assign rcfg_out_read_1 = rcfg_read_int; + assign rcfg_out_write_1 = rcfg_write_int; + assign rcfg_out_address_1 = rcfg_address_int; + assign rcfg_out_writedata_1 = rcfg_writedata_int; + assign rcfg_in_readdata_0 = rcfg_readdata_int; + assign rcfg_in_readdata_1 = rcfg_readdata_int; + assign rcfg_in_waitrequest_0 = rcfg_waitrequest_int_0; + assign rcfg_in_waitrequest_1 = rcfg_waitrequest_int_1; + + assign rcfg_readdata_s = rcfg_out_readdata_1 & rcfg_out_readdata_0; + assign rcfg_waitrequest_s = rcfg_out_waitrequest_1 & rcfg_out_waitrequest_0; + + always @(negedge rcfg_reset_n or posedge rcfg_clk) begin + if (rcfg_reset_n == 0) begin + rcfg_select <= 2'd0; + rcfg_read_int <= 1'd0; + rcfg_write_int <= 1'd0; + rcfg_address_int <= 'd0; + rcfg_writedata_int <= 32'd0; + rcfg_readdata_int <= 32'd0; + rcfg_waitrequest_int_0 <= 1'b1; + rcfg_waitrequest_int_1 <= 1'b1; + end else begin + if (rcfg_select[1] == 1'b1) begin + if (rcfg_waitrequest_s == 1'b0) begin + rcfg_select <= 2'd0; + rcfg_read_int <= 1'b0; + rcfg_write_int <= 1'b0; + rcfg_address_int <= 'd0; + rcfg_writedata_int <= 32'd0; + end + rcfg_readdata_int <= rcfg_readdata_s; + rcfg_waitrequest_int_0 <= rcfg_waitrequest_s | rcfg_select[0]; + rcfg_waitrequest_int_1 <= rcfg_waitrequest_s | ~rcfg_select[0]; + end else if ((rcfg_in_read_0 == 1'b1) || (rcfg_in_write_0 == 1'b1)) begin + rcfg_select <= 2'b10; + rcfg_read_int <= rcfg_in_read_0; + rcfg_write_int <= rcfg_in_write_0; + rcfg_address_int <= rcfg_in_address_0; + rcfg_writedata_int <= rcfg_in_writedata_0; + rcfg_readdata_int <= 32'd0; + rcfg_waitrequest_int_0 <= 1'b1; + rcfg_waitrequest_int_1 <= 1'b1; + end else if ((rcfg_in_read_1 == 1'b1) || (rcfg_in_write_1 == 1'b1)) begin + rcfg_select <= 2'b11; + rcfg_read_int <= rcfg_in_read_1; + rcfg_write_int <= rcfg_in_write_1; + rcfg_address_int <= rcfg_in_address_1; + rcfg_writedata_int <= rcfg_in_writedata_1; + rcfg_readdata_int <= 32'd0; + rcfg_waitrequest_int_0 <= 1'b1; + rcfg_waitrequest_int_1 <= 1'b1; + end else begin + rcfg_select <= 2'd0; + rcfg_read_int <= 1'd0; + rcfg_write_int <= 1'd0; + rcfg_address_int <= 'd0; + rcfg_writedata_int <= 32'd0; + rcfg_readdata_int <= 32'd0; + rcfg_waitrequest_int_0 <= 1'b1; + rcfg_waitrequest_int_1 <= 1'b1; + end + end + end + +endmodule diff --git a/adi_library/intel/avl_adxcfg/avl_adxcfg_hw.tcl b/adi_library/intel/avl_adxcfg/avl_adxcfg_hw.tcl new file mode 100644 index 00000000..40a0da88 --- /dev/null +++ b/adi_library/intel/avl_adxcfg/avl_adxcfg_hw.tcl @@ -0,0 +1,66 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 + +set_module_property NAME avl_adxcfg +set_module_property DESCRIPTION "Avalon ADXCFG Core" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME avl_adxcfg +set_module_property ELABORATION_CALLBACK elaborate + +# files + +add_fileset quartus_synth QUARTUS_SYNTH "" "" +set_fileset_property quartus_synth TOP_LEVEL avl_adxcfg +add_fileset_file avl_adxcfg.v VERILOG PATH avl_adxcfg.v TOP_LEVEL_FILE + +# add exportable hdl parameter + +add_parameter ADDRESS_WIDTH INTEGER 10 +set_parameter_property ADDRESS_WIDTH AFFECTS_GENERATION false +set_parameter_property ADDRESS_WIDTH HDL_PARAMETER true + +# reconfiguration interfaces + +add_interface rcfg_clk clock sink +add_interface_port rcfg_clk rcfg_clk clk Input 1 + +add_interface rcfg_reset_n reset end +set_interface_property rcfg_reset_n associatedClock rcfg_clk +add_interface_port rcfg_reset_n rcfg_reset_n reset_n Input 1 + +proc elaborate {} { + for {set n 0} {$n < 2} {incr n} { + + add_interface rcfg_s${n} avalon slave + add_interface rcfg_m${n} avalon master + + add_interface_port rcfg_s${n} rcfg_in_read_${n} read Input 1 + add_interface_port rcfg_s${n} rcfg_in_write_${n} write Input 1 + add_interface_port rcfg_s${n} rcfg_in_address_${n} address Input [get_parameter_value ADDRESS_WIDTH] + add_interface_port rcfg_s${n} rcfg_in_writedata_${n} writedata Input 32 + add_interface_port rcfg_s${n} rcfg_in_readdata_${n} readdata Output 32 + add_interface_port rcfg_s${n} rcfg_in_waitrequest_${n} waitrequest Output 1 + add_interface_port rcfg_m${n} rcfg_out_read_${n} read Output 1 + add_interface_port rcfg_m${n} rcfg_out_write_${n} write Output 1 + add_interface_port rcfg_m${n} rcfg_out_address_${n} address Output [get_parameter_value ADDRESS_WIDTH] + add_interface_port rcfg_m${n} rcfg_out_writedata_${n} writedata Output 32 + add_interface_port rcfg_m${n} rcfg_out_readdata_${n} readdata Input 32 + add_interface_port rcfg_m${n} rcfg_out_waitrequest_${n} waitrequest Input 1 + + set_interface_property rcfg_s${n} associatedClock rcfg_clk + set_interface_property rcfg_s${n} associatedReset rcfg_reset_n + set_interface_property rcfg_s${n} addressUnits WORDS + set_interface_property rcfg_s${n} burstCountUnits WORDS + set_interface_property rcfg_s${n} explicitAddressSpan 0 + set_interface_property rcfg_m${n} associatedClock rcfg_clk + set_interface_property rcfg_m${n} associatedReset rcfg_reset_n + set_interface_property rcfg_m${n} addressUnits WORDS + set_interface_property rcfg_m${n} burstCountUnits WORDS + } +} + diff --git a/adi_library/intel/avl_adxcvr/.timestamp_intel b/adi_library/intel/avl_adxcvr/.timestamp_intel new file mode 100644 index 00000000..e69de29b diff --git a/adi_library/intel/avl_adxcvr/Makefile b/adi_library/intel/avl_adxcvr/Makefile new file mode 100644 index 00000000..71f5d030 --- /dev/null +++ b/adi_library/intel/avl_adxcvr/Makefile @@ -0,0 +1,14 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := avl_adxcvr + +INTEL_DEPS += avl_adxcvr_hw.tcl + +INTEL_LIB_DEPS += intel/avl_adxcvr_octet_swap +INTEL_LIB_DEPS += intel/avl_adxphy + +include ../../scripts/library.mk diff --git a/adi_library/intel/avl_adxcvr/avl_adxcvr_hw.tcl b/adi_library/intel/avl_adxcvr/avl_adxcvr_hw.tcl new file mode 100644 index 00000000..9b697d78 --- /dev/null +++ b/adi_library/intel/avl_adxcvr/avl_adxcvr_hw.tcl @@ -0,0 +1,359 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +source ../../../scripts/adi_env.tcl +source ../../scripts/adi_ip_intel.tcl + +ad_ip_create avl_adxcvr {Avalon ADXCVR Core} +set_module_property COMPOSITION_CALLBACK p_avl_adxcvr + +# parameters + +ad_ip_parameter DEVICE_FAMILY STRING {Arria 10} +ad_ip_parameter TX_OR_RX_N INTEGER 0 false +ad_ip_parameter ID INTEGER 0 false +ad_ip_parameter PCS_CONFIG STRING "JESD_PCS_CFG2" false +ad_ip_parameter LANE_RATE FLOAT 10000 false +ad_ip_parameter SYSCLK_FREQUENCY FLOAT 100.0 false +ad_ip_parameter REFCLK_FREQUENCY FLOAT 500.0 false +ad_ip_parameter NUM_OF_LANES INTEGER 4 false +ad_ip_parameter NUM_OF_CONVS INTEGER 2 false +ad_ip_parameter FRM_BCNT INTEGER 1 false +ad_ip_parameter FRM_SCNT INTEGER 1 false +ad_ip_parameter MF_FCNT INTEGER 32 false +ad_ip_parameter HD INTEGER 1 false +ad_ip_parameter TX_LANE_MAP STRING "" false + +set_parameter_property LANE_RATE DISPLAY_UNITS "Mbps" +set_parameter_property SYSCLK_FREQUENCY UNITS Megahertz +set_parameter_property REFCLK_FREQUENCY UNITS Megahertz + +proc p_avl_adxcvr {} { + + set m_id [get_parameter_value "ID"] + set m_lane_rate [get_parameter_value "LANE_RATE"] + set m_pcs_config [get_parameter_value "PCS_CONFIG"] + set m_tx_or_rx_n [get_parameter_value "TX_OR_RX_N"] + set m_num_of_lanes [get_parameter_value "NUM_OF_LANES"] + set m_device_family [get_parameter_value "DEVICE_FAMILY"] + set m_sysclk_frequency [get_parameter_value "SYSCLK_FREQUENCY"] + set m_refclk_frequency [get_parameter_value "REFCLK_FREQUENCY"] + set m_num_of_convs [get_parameter_value "NUM_OF_CONVS"] + set m_frm_bcnt [get_parameter_value "FRM_BCNT"] + set m_frm_scnt [get_parameter_value "FRM_SCNT"] + set m_mf_fcnt [get_parameter_value "MF_FCNT"] + set m_hd [get_parameter_value "HD"] + set m_tx_lane_map [get_parameter_value "TX_LANE_MAP"] + + set m_pllclk_frequency [expr $m_lane_rate / 2] + set m_coreclk_frequency [expr $m_lane_rate / 40] + + add_instance sys_clk clock_source + set_instance_parameter_value sys_clk {clockFrequency} [expr $m_sysclk_frequency*1000000] + add_interface sys_clk clock sink + set_interface_property sys_clk EXPORT_OF sys_clk.clk_in + add_interface sys_resetn reset sink + set_interface_property sys_resetn EXPORT_OF sys_clk.clk_in_reset + + add_instance xcvr_rst altera_reset_bridge + add_connection sys_clk.clk xcvr_rst.clk + add_interface rst reset sink + set_interface_property rst EXPORT_OF xcvr_rst.in_reset + + add_instance ref_clk altera_clock_bridge + set_instance_parameter_value ref_clk {EXPLICIT_CLOCK_RATE} [expr $m_refclk_frequency*1000000] + add_interface ref_clk clock sink + set_interface_property ref_clk EXPORT_OF ref_clk.in_clk + + add_instance fpll_rst_control altera_xcvr_reset_control + set_instance_parameter_value fpll_rst_control {SYS_CLK_IN_MHZ} $m_sysclk_frequency + set_instance_parameter_value fpll_rst_control {TX_PLL_ENABLE} {1} + set_instance_parameter_value fpll_rst_control {T_PLL_POWERDOWN} {1000} + set_instance_parameter_value fpll_rst_control {TX_ENABLE} {0} + set_instance_parameter_value fpll_rst_control {RX_ENABLE} {0} + add_connection sys_clk.clk fpll_rst_control.clock + add_connection xcvr_rst.out_reset fpll_rst_control.reset + add_connection sys_clk.clk_reset fpll_rst_control.reset + + add_instance core_pll altera_xcvr_fpll_a10 + set_instance_parameter_value core_pll {gui_fpll_mode} {0} + set_instance_parameter_value core_pll {gui_reference_clock_frequency} $m_refclk_frequency + set_instance_parameter_value core_pll {gui_number_of_output_clocks} 2 + set_instance_parameter_value core_pll {gui_enable_phase_alignment} 1 + set_instance_parameter_value core_pll {gui_desired_outclk0_frequency} $m_coreclk_frequency + set m_pfdclk_frequency [get_instance_parameter_value core_pll gui_pfd_frequency] + set_instance_parameter_value core_pll {gui_desired_outclk1_frequency} $m_pfdclk_frequency + set_instance_parameter_value core_pll {enable_pll_reconfig} {1} + set_instance_parameter_value core_pll {set_capability_reg_enable} {1} + set_instance_parameter_value core_pll {set_csr_soft_logic_enable} {1} + add_connection ref_clk.out_clk core_pll.pll_refclk0 + add_connection fpll_rst_control.pll_powerdown core_pll.pll_powerdown + add_interface core_pll_locked conduit end + set_interface_property core_pll_locked EXPORT_OF core_pll.pll_locked + add_connection sys_clk.clk_reset core_pll.reconfig_reset0 + add_connection sys_clk.clk core_pll.reconfig_clk0 + add_interface core_pll_reconfig avalon slave + set_interface_property core_pll_reconfig EXPORT_OF core_pll.reconfig_avmm0 + + add_instance core_clk altera_clock_bridge + set_instance_parameter_value core_clk {EXPLICIT_CLOCK_RATE} [expr $m_coreclk_frequency*1000000] + add_connection core_pll.outclk0 core_clk.in_clk + add_interface core_clk clock source + set_interface_property core_clk EXPORT_OF core_clk.out_clk + + add_instance octet_swap avl_adxcvr_octet_swap + set_instance_parameter_value octet_swap NUM_OF_LANES $m_num_of_lanes + set_instance_parameter_value octet_swap TX_OR_RX_N m_tx_or_rx_n + add_connection core_pll.outclk0 octet_swap.clock + add_connection sys_clk.clk_reset octet_swap.reset + + if {$m_tx_or_rx_n == 1} { + + add_instance rst_control altera_xcvr_reset_control + set_instance_parameter_value rst_control {CHANNELS} $m_num_of_lanes + set_instance_parameter_value rst_control {SYS_CLK_IN_MHZ} $m_sysclk_frequency + set_instance_parameter_value rst_control {TX_PLL_ENABLE} {1} + set_instance_parameter_value rst_control {T_PLL_POWERDOWN} {1000} + set_instance_parameter_value rst_control {TX_ENABLE} {1} + set_instance_parameter_value rst_control {T_TX_ANALOGRESET} {70000} + set_instance_parameter_value rst_control {T_TX_DIGITALRESET} {70000} + set_instance_parameter_value rst_control {gui_pll_cal_busy} {1} + set_instance_parameter_value rst_control {RX_ENABLE} {0} + add_connection sys_clk.clk rst_control.clock + add_connection xcvr_rst.out_reset rst_control.reset + add_connection sys_clk.clk_reset rst_control.reset + add_interface ready conduit end + set_interface_property ready EXPORT_OF rst_control.tx_ready + + add_instance lane_pll altera_xcvr_atx_pll_a10 + set_instance_parameter_value lane_pll {enable_pll_reconfig} {1} + set_instance_parameter_value lane_pll {rcfg_separate_avmm_busy} {1} + set_instance_parameter_value lane_pll {set_capability_reg_enable} {1} + set_instance_parameter_value lane_pll {set_user_identifier} $m_id + set_instance_parameter_value lane_pll {set_csr_soft_logic_enable} {1} + set_instance_parameter_value lane_pll {set_output_clock_frequency} $m_pllclk_frequency + set_instance_parameter_value lane_pll {set_auto_reference_clock_frequency} $m_refclk_frequency + add_connection rst_control.pll_powerdown lane_pll.pll_powerdown + add_connection lane_pll.pll_locked rst_control.pll_locked + add_connection lane_pll.pll_cal_busy rst_control.pll_cal_busy + add_connection ref_clk.out_clk lane_pll.pll_refclk0 + add_connection sys_clk.clk lane_pll.reconfig_clk0 + add_connection sys_clk.clk_reset lane_pll.reconfig_reset0 + add_interface lane_pll_reconfig avalon slave + set_interface_property lane_pll_reconfig EXPORT_OF lane_pll.reconfig_avmm0 + + add_instance jesd204_ip altera_jesd204 + set_instance_parameter_value jesd204_ip {wrapper_opt} {base} + set_instance_parameter_value jesd204_ip {DATA_PATH} {TX} + set_instance_parameter_value jesd204_ip {lane_rate} $m_lane_rate + set_instance_parameter_value jesd204_ip {L} $m_num_of_lanes + set_instance_parameter_value jesd204_ip {M} $m_num_of_convs + set_instance_parameter_value jesd204_ip {GUI_EN_CFG_F} {1} + set_instance_parameter_value jesd204_ip {GUI_CFG_F} $m_frm_bcnt + set_instance_parameter_value jesd204_ip {N} {16} + set_instance_parameter_value jesd204_ip {N_PRIME} {16} + set_instance_parameter_value jesd204_ip {S} $m_frm_scnt + set_instance_parameter_value jesd204_ip {K} $m_mf_fcnt + set_instance_parameter_value jesd204_ip {SCR} {1} + set_instance_parameter_value jesd204_ip {HD} $m_hd + add_connection core_pll.outclk0 jesd204_ip.txlink_clk + add_connection sys_clk.clk_reset jesd204_ip.txlink_rst_n + + add_connection octet_swap.out jesd204_ip.jesd204_tx_link + add_interface ip_data avalon_streaming sink + set_interface_property ip_data EXPORT_OF octet_swap.in + + add_connection sys_clk.clk jesd204_ip.jesd204_tx_avs_clk + add_connection sys_clk.clk_reset jesd204_ip.jesd204_tx_avs_rst_n + add_interface ip_reconfig avalon slave + set_interface_property ip_reconfig EXPORT_OF jesd204_ip.jesd204_tx_avs + add_interface sysref conduit end + set_interface_property sysref EXPORT_OF jesd204_ip.sysref + add_interface sync conduit end + set_interface_property sync EXPORT_OF jesd204_ip.sync_n + add_connection jesd204_ip.dev_sync_n jesd204_ip.mdev_sync_n + + add_instance avl_xphy avl_adxphy + set_instance_parameter_value avl_xphy {TX_OR_RX_N} {1} + set_instance_parameter_value avl_xphy {NUM_OF_LANES} $m_num_of_lanes + add_connection rst_control.tx_analogreset avl_xphy.tx_core_analogreset + add_connection rst_control.tx_digitalreset avl_xphy.tx_core_digitalreset + add_connection avl_xphy.tx_core_cal_busy rst_control.tx_cal_busy + add_connection avl_xphy.tx_ip_cal_busy jesd204_ip.tx_cal_busy + add_connection avl_xphy.tx_ip_pcfifo_full jesd204_ip.phy_csr_tx_pcfifo_full + add_connection avl_xphy.tx_ip_pcfifo_empty jesd204_ip.phy_csr_tx_pcfifo_empty + add_connection jesd204_ip.jesd204_tx_pcs_data avl_xphy.tx_ip_pcs_data + add_connection jesd204_ip.jesd204_tx_pcs_kchar_data avl_xphy.tx_ip_pcs_kchar_data + add_connection jesd204_ip.phy_tx_elecidle avl_xphy.tx_ip_elecidle + add_connection jesd204_ip.csr_lane_polarity avl_xphy.tx_ip_csr_lane_polarity + add_connection jesd204_ip.csr_lane_powerdown avl_xphy.tx_ip_csr_lane_powerdown + add_connection jesd204_ip.csr_bit_reversal avl_xphy.tx_ip_csr_bit_reversal + add_connection jesd204_ip.csr_byte_reversal avl_xphy.tx_ip_csr_byte_reversal + + set lane_map [regexp -all -inline {\S+} $m_tx_lane_map] + + for {set n 0} {$n < $m_num_of_lanes} {incr n} { + + add_instance phy_${n} altera_jesd204 + set_instance_parameter_value phy_${n} {wrapper_opt} {phy} + set_instance_parameter_value phy_${n} {DATA_PATH} {TX} + set_instance_parameter_value phy_${n} {lane_rate} $m_lane_rate + set_instance_parameter_value phy_${n} {PCS_CONFIG} $m_pcs_config + set_instance_parameter_value phy_${n} {bonded_mode} {non_bonded} + set_instance_parameter_value phy_${n} {pll_reconfig_enable} {1} + set_instance_parameter_value phy_${n} {set_capability_reg_enable} {1} + set_instance_parameter_value phy_${n} {set_user_identifier} $m_id + set_instance_parameter_value phy_${n} {set_csr_soft_logic_enable} {1} + set_instance_parameter_value phy_${n} {L} 1 + add_connection core_pll.outclk0 phy_${n}.txlink_clk + add_connection sys_clk.clk_reset phy_${n}.txlink_rst_n + add_interface tx_data_${n} conduit end + set_interface_property tx_data_${n} EXPORT_OF phy_${n}.tx_serial_data + add_connection avl_xphy.tx_phy${n}_analogreset phy_${n}.tx_analogreset + add_connection avl_xphy.tx_phy${n}_digitalreset phy_${n}.tx_digitalreset + add_connection lane_pll.tx_serial_clk phy_${n}.tx_serial_clk0 + + add_connection sys_clk.clk phy_${n}.reconfig_clk + add_connection sys_clk.clk_reset phy_${n}.reconfig_reset + add_interface phy_reconfig_${n} avalon slave + set_interface_property phy_reconfig_${n} EXPORT_OF phy_${n}.reconfig_avmm + + if {$lane_map != {}} { + set m [lindex $lane_map $n] + } else { + set m $n + } + + add_connection phy_${n}.tx_cal_busy avl_xphy.tx_phy${m}_cal_busy + add_connection phy_${n}.phy_csr_tx_pcfifo_full avl_xphy.tx_phy${m}_pcfifo_full + add_connection phy_${n}.phy_csr_tx_pcfifo_empty avl_xphy.tx_phy${m}_pcfifo_empty + add_connection avl_xphy.tx_phy${m}_pcs_data phy_${n}.jesd204_tx_pcs_data + add_connection avl_xphy.tx_phy${m}_pcs_kchar_data phy_${n}.jesd204_tx_pcs_kchar_data + add_connection avl_xphy.tx_phy${m}_elecidle phy_${n}.phy_tx_elecidle + add_connection avl_xphy.tx_phy${m}_csr_lane_polarity phy_${n}.csr_lane_polarity + add_connection avl_xphy.tx_phy${m}_csr_lane_powerdown phy_${n}.csr_lane_powerdown + add_connection avl_xphy.tx_phy${m}_csr_bit_reversal phy_${n}.csr_bit_reversal + add_connection avl_xphy.tx_phy${m}_csr_byte_reversal phy_${n}.csr_byte_reversal + } + } + + if {$m_tx_or_rx_n == 0} { + + add_instance rst_control altera_xcvr_reset_control + set_instance_parameter_value rst_control {CHANNELS} $m_num_of_lanes + set_instance_parameter_value rst_control {SYS_CLK_IN_MHZ} $m_sysclk_frequency + set_instance_parameter_value rst_control {TX_PLL_ENABLE} {0} + set_instance_parameter_value rst_control {TX_ENABLE} {0} + set_instance_parameter_value rst_control {RX_ENABLE} {1} + set_instance_parameter_value rst_control {T_RX_ANALOGRESET} {70000} + set_instance_parameter_value rst_control {T_RX_DIGITALRESET} {4000} + add_connection sys_clk.clk rst_control.clock + add_connection xcvr_rst.out_reset rst_control.reset + add_connection sys_clk.clk_reset rst_control.reset + add_interface ready conduit end + set_interface_property ready EXPORT_OF rst_control.rx_ready + + add_instance jesd204_ip altera_jesd204 + set_instance_parameter_value jesd204_ip {wrapper_opt} {base} + set_instance_parameter_value jesd204_ip {DATA_PATH} {RX} + set_instance_parameter_value jesd204_ip {lane_rate} $m_lane_rate + set_instance_parameter_value jesd204_ip {L} $m_num_of_lanes + set_instance_parameter_value jesd204_ip {M} $m_num_of_convs + set_instance_parameter_value jesd204_ip {GUI_EN_CFG_F} {1} + set_instance_parameter_value jesd204_ip {GUI_CFG_F} $m_frm_bcnt + set_instance_parameter_value jesd204_ip {N} {16} + set_instance_parameter_value jesd204_ip {N_PRIME} {16} + set_instance_parameter_value jesd204_ip {S} $m_frm_scnt + set_instance_parameter_value jesd204_ip {K} $m_mf_fcnt + set_instance_parameter_value jesd204_ip {SCR} {1} + set_instance_parameter_value jesd204_ip {HD} $m_hd + add_connection core_pll.outclk0 jesd204_ip.rxlink_clk + add_connection sys_clk.clk_reset jesd204_ip.rxlink_rst_n + + add_connection jesd204_ip.sof octet_swap.in_sof + add_interface ip_sof conduit end + set_interface_property ip_sof EXPORT_OF octet_swap.out_sof + + add_connection jesd204_ip.jesd204_rx_link octet_swap.in + add_interface ip_data avalon_streaming source + set_interface_property ip_data EXPORT_OF octet_swap.out + + add_connection sys_clk.clk jesd204_ip.jesd204_rx_avs_clk + add_connection sys_clk.clk_reset jesd204_ip.jesd204_rx_avs_rst_n + add_interface ip_reconfig avalon slave + set_interface_property ip_reconfig EXPORT_OF jesd204_ip.jesd204_rx_avs + add_interface sysref conduit end + set_interface_property sysref EXPORT_OF jesd204_ip.sysref + add_interface sync conduit end + set_interface_property sync EXPORT_OF jesd204_ip.dev_sync_n + add_connection jesd204_ip.dev_lane_aligned jesd204_ip.alldev_lane_aligned + + add_instance avl_xphy avl_adxphy + set_instance_parameter_value avl_xphy {TX_OR_RX_N} {0} + set_instance_parameter_value avl_xphy {NUM_OF_LANES} $m_num_of_lanes + add_connection rst_control.rx_analogreset avl_xphy.rx_core_analogreset + add_connection rst_control.rx_digitalreset avl_xphy.rx_core_digitalreset + add_connection avl_xphy.rx_core_is_lockedtodata rst_control.rx_is_lockedtodata + add_connection avl_xphy.rx_core_cal_busy rst_control.rx_cal_busy + add_connection avl_xphy.rx_ip_is_lockedtodata jesd204_ip.rx_islockedtodata + add_connection avl_xphy.rx_ip_cal_busy jesd204_ip.rx_cal_busy + add_connection avl_xphy.rx_ip_pcs_data_valid jesd204_ip.jesd204_rx_pcs_data_valid + add_connection avl_xphy.rx_ip_pcs_data jesd204_ip.jesd204_rx_pcs_data + add_connection avl_xphy.rx_ip_pcs_disperr jesd204_ip.jesd204_rx_pcs_disperr + add_connection avl_xphy.rx_ip_pcs_errdetect jesd204_ip.jesd204_rx_pcs_errdetect + add_connection avl_xphy.rx_ip_pcs_kchar_data jesd204_ip.jesd204_rx_pcs_kchar_data + add_connection avl_xphy.rx_ip_pcfifo_full jesd204_ip.phy_csr_rx_pcfifo_full + add_connection avl_xphy.rx_ip_pcfifo_empty jesd204_ip.phy_csr_rx_pcfifo_empty + add_connection avl_xphy.rx_ip_patternalign_en jesd204_ip.patternalign_en + add_connection avl_xphy.rx_ip_csr_lane_polarity jesd204_ip.csr_lane_polarity + add_connection avl_xphy.rx_ip_csr_lane_powerdown jesd204_ip.csr_lane_powerdown + add_connection avl_xphy.rx_ip_csr_bit_reversal jesd204_ip.csr_bit_reversal + add_connection avl_xphy.rx_ip_csr_byte_reversal jesd204_ip.csr_byte_reversal + + for {set n 0} {$n < $m_num_of_lanes} {incr n} { + + add_instance phy_${n} altera_jesd204 + set_instance_parameter_value phy_${n} {wrapper_opt} {phy} + set_instance_parameter_value phy_${n} {DATA_PATH} {RX} + set_instance_parameter_value phy_${n} {lane_rate} $m_lane_rate + set_instance_parameter_value phy_${n} {PCS_CONFIG} $m_pcs_config + set_instance_parameter_value phy_${n} {REFCLK_FREQ} $m_refclk_frequency + set_instance_parameter_value phy_${n} {pll_reconfig_enable} {1} + set_instance_parameter_value phy_${n} {set_capability_reg_enable} {1} + set_instance_parameter_value phy_${n} {set_user_identifier} $m_id + set_instance_parameter_value phy_${n} {set_csr_soft_logic_enable} {1} + set_instance_parameter_value phy_${n} {L} 1 + + add_connection sys_clk.clk phy_${n}.reconfig_clk + add_connection sys_clk.clk_reset phy_${n}.reconfig_reset + add_interface phy_reconfig_${n} avalon slave + set_interface_property phy_reconfig_${n} EXPORT_OF phy_${n}.reconfig_avmm + + add_connection ref_clk.out_clk phy_${n}.pll_ref_clk + add_connection core_pll.outclk0 phy_${n}.rxlink_clk + add_connection sys_clk.clk_reset phy_${n}.rxlink_rst_n + add_interface rx_data_${n} conduit end + set_interface_property rx_data_${n} EXPORT_OF phy_${n}.rx_serial_data + add_connection avl_xphy.rx_phy${n}_analogreset phy_${n}.rx_analogreset + add_connection avl_xphy.rx_phy${n}_digitalreset phy_${n}.rx_digitalreset + add_connection phy_${n}.rx_islockedtodata avl_xphy.rx_phy${n}_is_lockedtodata + add_connection phy_${n}.rx_cal_busy avl_xphy.rx_phy${n}_cal_busy + add_connection phy_${n}.jesd204_rx_pcs_data_valid avl_xphy.rx_phy${n}_pcs_data_valid + add_connection phy_${n}.jesd204_rx_pcs_data avl_xphy.rx_phy${n}_pcs_data + add_connection phy_${n}.jesd204_rx_pcs_disperr avl_xphy.rx_phy${n}_pcs_disperr + add_connection phy_${n}.jesd204_rx_pcs_errdetect avl_xphy.rx_phy${n}_pcs_errdetect + add_connection phy_${n}.jesd204_rx_pcs_kchar_data avl_xphy.rx_phy${n}_pcs_kchar_data + add_connection phy_${n}.phy_csr_rx_pcfifo_full avl_xphy.rx_phy${n}_pcfifo_full + add_connection phy_${n}.phy_csr_rx_pcfifo_empty avl_xphy.rx_phy${n}_pcfifo_empty + add_connection avl_xphy.rx_phy${n}_patternalign_en phy_${n}.patternalign_en + add_connection avl_xphy.rx_phy${n}_csr_lane_polarity phy_${n}.csr_lane_polarity + add_connection avl_xphy.rx_phy${n}_csr_lane_powerdown phy_${n}.csr_lane_powerdown + add_connection avl_xphy.rx_phy${n}_csr_bit_reversal phy_${n}.csr_bit_reversal + add_connection avl_xphy.rx_phy${n}_csr_byte_reversal phy_${n}.csr_byte_reversal + } + } +} + diff --git a/adi_library/intel/avl_adxcvr_octet_swap/.timestamp_intel b/adi_library/intel/avl_adxcvr_octet_swap/.timestamp_intel new file mode 100644 index 00000000..e69de29b diff --git a/adi_library/intel/avl_adxcvr_octet_swap/Makefile b/adi_library/intel/avl_adxcvr_octet_swap/Makefile new file mode 100644 index 00000000..6f7b4dd9 --- /dev/null +++ b/adi_library/intel/avl_adxcvr_octet_swap/Makefile @@ -0,0 +1,12 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := avl_adxcvr_octet_swap + +INTEL_DEPS += avl_adxcvr_octet_swap.v +INTEL_DEPS += avl_adxcvr_octet_swap_hw.tcl + +include ../../scripts/library.mk diff --git a/adi_library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap.v b/adi_library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap.v new file mode 100644 index 00000000..0b6030f4 --- /dev/null +++ b/adi_library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap.v @@ -0,0 +1,70 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module avl_adxcvr_octet_swap #( + parameter NUM_OF_LANES = 1 +) ( + input clk, + input reset, + + input in_valid, + output in_ready, + input [NUM_OF_LANES*32-1:0] in_data, + input [3:0] in_sof, + + output out_valid, + input out_ready, + output [NUM_OF_LANES*32-1:0] out_data, + output [3:0] out_sof +); + + assign in_ready = out_ready; + assign out_valid = in_valid; + + generate + genvar i; + genvar j; + + for (j = 0; j < 4; j = j + 1) begin: gen_octet + for (i = 0; i < NUM_OF_LANES; i = i + 1) begin: gen_lane + assign out_data[i*32+j*8+7:i*32+j*8] = in_data[i*32+(3-j)*8+7:i*32+(3-j)*8]; + end + assign out_sof[j] = in_sof[3-j]; + end + endgenerate + +endmodule diff --git a/adi_library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap_hw.tcl b/adi_library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap_hw.tcl new file mode 100644 index 00000000..307ee3f2 --- /dev/null +++ b/adi_library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap_hw.tcl @@ -0,0 +1,67 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl + +ad_ip_create avl_adxcvr_octet_swap "avl_adxcvvr_octet_swap helper" avl_adxcvr_octet_swap_elaboration +set_module_property HIDE_FROM_SOPC true +set_module_property HIDE_FROM_QSYS true +set_module_property HIDE_FROM_QUARTUS true + +# files + +ad_ip_files avl_adxcvr_octet_swap { \ + avl_adxcvr_octet_swap.v +} + +# parameters + +ad_ip_parameter NUM_OF_LANES INTEGER 4 true +ad_ip_parameter TX_OR_RX_N INTEGER 0 false + +# interfaces + +add_interface clock clock end +add_interface_port clock clk clk Input 1 + +add_interface reset reset end +add_interface_port reset reset reset Input 1 +set_interface_property reset associatedClock clock + +add_interface in_sof conduit end +add_interface_port in_sof in_sof export Input 4 + +add_interface out_sof conduit end +add_interface_port out_sof out_sof export Output 4 + +proc avl_adxcvr_octet_swap_elaboration {} { + set num_lanes [get_parameter_value NUM_OF_LANES] + set tx [get_parameter_value TX_OR_RX_N] + + add_interface in avalon_streaming sink + set_interface_property in associatedClock clock + set_interface_property in associatedReset reset + add_interface_port in in_data data input [expr 32*$num_lanes] + add_interface_port in in_valid valid input 1 + add_interface_port in in_ready ready output 1 + set_interface_property in dataBitsPerSymbol [expr 32*$num_lanes] + + add_interface out avalon_streaming source + set_interface_property out associatedClock clock + set_interface_property out associatedReset reset + add_interface_port out out_data data output [expr 32*$num_lanes] + add_interface_port out out_valid valid output 1 + add_interface_port out out_ready ready input 1 + set_interface_property out dataBitsPerSymbol [expr 32*$num_lanes] + + if {$tx} { + set_port_property in_sof TERMINATION true + set_port_property in_sof TERMINATION_VALUE 0 + set_port_property out_sof TERMINATION true + } +} diff --git a/adi_library/intel/avl_adxphy/.timestamp_intel b/adi_library/intel/avl_adxphy/.timestamp_intel new file mode 100644 index 00000000..e69de29b diff --git a/adi_library/intel/avl_adxphy/Makefile b/adi_library/intel/avl_adxphy/Makefile new file mode 100644 index 00000000..3fb20063 --- /dev/null +++ b/adi_library/intel/avl_adxphy/Makefile @@ -0,0 +1,12 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := avl_adxphy + +INTEL_DEPS += avl_adxphy.v +INTEL_DEPS += avl_adxphy_hw.tcl + +include ../../scripts/library.mk diff --git a/adi_library/intel/avl_adxphy/avl_adxphy.v b/adi_library/intel/avl_adxphy/avl_adxphy.v new file mode 100644 index 00000000..dc371c98 --- /dev/null +++ b/adi_library/intel/avl_adxphy/avl_adxphy.v @@ -0,0 +1,922 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// AUTO GENERATED BY avl_adxphy.pl, DO NOT MODIFY! + +`timescale 1ns/1ps + +module avl_adxphy #( + + // parameters + + parameter integer NUM_OF_LANES = 4 +) ( + + // rx-ip interface + + output [((NUM_OF_LANES* 1)-1):0] rx_ip_locked, + output [((NUM_OF_LANES* 1)-1):0] rx_ip_cal_busy, + output [((NUM_OF_LANES* 1)-1):0] rx_ip_valid, + output [((NUM_OF_LANES*32)-1):0] rx_ip_data, + output [((NUM_OF_LANES* 4)-1):0] rx_ip_disperr, + output [((NUM_OF_LANES* 4)-1):0] rx_ip_deterr, + output [((NUM_OF_LANES* 4)-1):0] rx_ip_kchar, + output [((NUM_OF_LANES* 1)-1):0] rx_ip_full, + output [((NUM_OF_LANES* 1)-1):0] rx_ip_empty, + input [((NUM_OF_LANES* 1)-1):0] rx_ip_align_en, + input [((NUM_OF_LANES* 1)-1):0] rx_ip_lane_polarity, + input [((NUM_OF_LANES* 1)-1):0] rx_ip_lane_powerdown, + input rx_ip_bit_reversal, + input rx_ip_byte_reversal, + + // rx-phy interface(s) + + input rx_phy_locked_0, + input rx_phy_cal_busy_0, + input rx_phy_valid_0, + input [31:0] rx_phy_data_0, + input [ 3:0] rx_phy_disperr_0, + input [ 3:0] rx_phy_deterr_0, + input [ 3:0] rx_phy_kchar_0, + input rx_phy_full_0, + input rx_phy_empty_0, + output rx_phy_align_en_0, + output rx_phy_lane_polarity_0, + output rx_phy_lane_powerdown_0, + output rx_phy_bit_reversal_0, + output rx_phy_byte_reversal_0, + output rx_phy_analogreset_0, + output rx_phy_digitalreset_0, + + input rx_phy_locked_1, + input rx_phy_cal_busy_1, + input rx_phy_valid_1, + input [31:0] rx_phy_data_1, + input [ 3:0] rx_phy_disperr_1, + input [ 3:0] rx_phy_deterr_1, + input [ 3:0] rx_phy_kchar_1, + input rx_phy_full_1, + input rx_phy_empty_1, + output rx_phy_align_en_1, + output rx_phy_lane_polarity_1, + output rx_phy_lane_powerdown_1, + output rx_phy_bit_reversal_1, + output rx_phy_byte_reversal_1, + output rx_phy_analogreset_1, + output rx_phy_digitalreset_1, + + input rx_phy_locked_2, + input rx_phy_cal_busy_2, + input rx_phy_valid_2, + input [31:0] rx_phy_data_2, + input [ 3:0] rx_phy_disperr_2, + input [ 3:0] rx_phy_deterr_2, + input [ 3:0] rx_phy_kchar_2, + input rx_phy_full_2, + input rx_phy_empty_2, + output rx_phy_align_en_2, + output rx_phy_lane_polarity_2, + output rx_phy_lane_powerdown_2, + output rx_phy_bit_reversal_2, + output rx_phy_byte_reversal_2, + output rx_phy_analogreset_2, + output rx_phy_digitalreset_2, + + input rx_phy_locked_3, + input rx_phy_cal_busy_3, + input rx_phy_valid_3, + input [31:0] rx_phy_data_3, + input [ 3:0] rx_phy_disperr_3, + input [ 3:0] rx_phy_deterr_3, + input [ 3:0] rx_phy_kchar_3, + input rx_phy_full_3, + input rx_phy_empty_3, + output rx_phy_align_en_3, + output rx_phy_lane_polarity_3, + output rx_phy_lane_powerdown_3, + output rx_phy_bit_reversal_3, + output rx_phy_byte_reversal_3, + output rx_phy_analogreset_3, + output rx_phy_digitalreset_3, + + input rx_phy_locked_4, + input rx_phy_cal_busy_4, + input rx_phy_valid_4, + input [31:0] rx_phy_data_4, + input [ 3:0] rx_phy_disperr_4, + input [ 3:0] rx_phy_deterr_4, + input [ 3:0] rx_phy_kchar_4, + input rx_phy_full_4, + input rx_phy_empty_4, + output rx_phy_align_en_4, + output rx_phy_lane_polarity_4, + output rx_phy_lane_powerdown_4, + output rx_phy_bit_reversal_4, + output rx_phy_byte_reversal_4, + output rx_phy_analogreset_4, + output rx_phy_digitalreset_4, + + input rx_phy_locked_5, + input rx_phy_cal_busy_5, + input rx_phy_valid_5, + input [31:0] rx_phy_data_5, + input [ 3:0] rx_phy_disperr_5, + input [ 3:0] rx_phy_deterr_5, + input [ 3:0] rx_phy_kchar_5, + input rx_phy_full_5, + input rx_phy_empty_5, + output rx_phy_align_en_5, + output rx_phy_lane_polarity_5, + output rx_phy_lane_powerdown_5, + output rx_phy_bit_reversal_5, + output rx_phy_byte_reversal_5, + output rx_phy_analogreset_5, + output rx_phy_digitalreset_5, + + input rx_phy_locked_6, + input rx_phy_cal_busy_6, + input rx_phy_valid_6, + input [31:0] rx_phy_data_6, + input [ 3:0] rx_phy_disperr_6, + input [ 3:0] rx_phy_deterr_6, + input [ 3:0] rx_phy_kchar_6, + input rx_phy_full_6, + input rx_phy_empty_6, + output rx_phy_align_en_6, + output rx_phy_lane_polarity_6, + output rx_phy_lane_powerdown_6, + output rx_phy_bit_reversal_6, + output rx_phy_byte_reversal_6, + output rx_phy_analogreset_6, + output rx_phy_digitalreset_6, + + input rx_phy_locked_7, + input rx_phy_cal_busy_7, + input rx_phy_valid_7, + input [31:0] rx_phy_data_7, + input [ 3:0] rx_phy_disperr_7, + input [ 3:0] rx_phy_deterr_7, + input [ 3:0] rx_phy_kchar_7, + input rx_phy_full_7, + input rx_phy_empty_7, + output rx_phy_align_en_7, + output rx_phy_lane_polarity_7, + output rx_phy_lane_powerdown_7, + output rx_phy_bit_reversal_7, + output rx_phy_byte_reversal_7, + output rx_phy_analogreset_7, + output rx_phy_digitalreset_7, + + // rx-core interface + + input [((NUM_OF_LANES* 1)-1):0] rx_core_analogreset, + input [((NUM_OF_LANES* 1)-1):0] rx_core_digitalreset, + output [((NUM_OF_LANES* 1)-1):0] rx_core_locked, + output [((NUM_OF_LANES* 1)-1):0] rx_core_cal_busy, + + // tx-ip interface + + output [((NUM_OF_LANES* 1)-1):0] tx_ip_cal_busy, + output [((NUM_OF_LANES* 1)-1):0] tx_ip_full, + output [((NUM_OF_LANES* 1)-1):0] tx_ip_empty, + input [((NUM_OF_LANES*32)-1):0] tx_ip_data, + input [((NUM_OF_LANES* 4)-1):0] tx_ip_kchar, + input [((NUM_OF_LANES* 1)-1):0] tx_ip_elecidle, + input [((NUM_OF_LANES* 1)-1):0] tx_ip_lane_polarity, + input [((NUM_OF_LANES* 1)-1):0] tx_ip_lane_powerdown, + input tx_ip_bit_reversal, + input tx_ip_byte_reversal, + + // tx-phy interface + + input tx_phy_cal_busy_0, + input tx_phy_full_0, + input tx_phy_empty_0, + output [31:0] tx_phy_data_0, + output [ 3:0] tx_phy_kchar_0, + output tx_phy_elecidle_0, + output tx_phy_lane_polarity_0, + output tx_phy_lane_powerdown_0, + output tx_phy_bit_reversal_0, + output tx_phy_byte_reversal_0, + output tx_phy_analogreset_0, + output tx_phy_digitalreset_0, + + input tx_phy_cal_busy_1, + input tx_phy_full_1, + input tx_phy_empty_1, + output [31:0] tx_phy_data_1, + output [ 3:0] tx_phy_kchar_1, + output tx_phy_elecidle_1, + output tx_phy_lane_polarity_1, + output tx_phy_lane_powerdown_1, + output tx_phy_bit_reversal_1, + output tx_phy_byte_reversal_1, + output tx_phy_analogreset_1, + output tx_phy_digitalreset_1, + + input tx_phy_cal_busy_2, + input tx_phy_full_2, + input tx_phy_empty_2, + output [31:0] tx_phy_data_2, + output [ 3:0] tx_phy_kchar_2, + output tx_phy_elecidle_2, + output tx_phy_lane_polarity_2, + output tx_phy_lane_powerdown_2, + output tx_phy_bit_reversal_2, + output tx_phy_byte_reversal_2, + output tx_phy_analogreset_2, + output tx_phy_digitalreset_2, + + input tx_phy_cal_busy_3, + input tx_phy_full_3, + input tx_phy_empty_3, + output [31:0] tx_phy_data_3, + output [ 3:0] tx_phy_kchar_3, + output tx_phy_elecidle_3, + output tx_phy_lane_polarity_3, + output tx_phy_lane_powerdown_3, + output tx_phy_bit_reversal_3, + output tx_phy_byte_reversal_3, + output tx_phy_analogreset_3, + output tx_phy_digitalreset_3, + + input tx_phy_cal_busy_4, + input tx_phy_full_4, + input tx_phy_empty_4, + output [31:0] tx_phy_data_4, + output [ 3:0] tx_phy_kchar_4, + output tx_phy_elecidle_4, + output tx_phy_lane_polarity_4, + output tx_phy_lane_powerdown_4, + output tx_phy_bit_reversal_4, + output tx_phy_byte_reversal_4, + output tx_phy_analogreset_4, + output tx_phy_digitalreset_4, + + input tx_phy_cal_busy_5, + input tx_phy_full_5, + input tx_phy_empty_5, + output [31:0] tx_phy_data_5, + output [ 3:0] tx_phy_kchar_5, + output tx_phy_elecidle_5, + output tx_phy_lane_polarity_5, + output tx_phy_lane_powerdown_5, + output tx_phy_bit_reversal_5, + output tx_phy_byte_reversal_5, + output tx_phy_analogreset_5, + output tx_phy_digitalreset_5, + + input tx_phy_cal_busy_6, + input tx_phy_full_6, + input tx_phy_empty_6, + output [31:0] tx_phy_data_6, + output [ 3:0] tx_phy_kchar_6, + output tx_phy_elecidle_6, + output tx_phy_lane_polarity_6, + output tx_phy_lane_powerdown_6, + output tx_phy_bit_reversal_6, + output tx_phy_byte_reversal_6, + output tx_phy_analogreset_6, + output tx_phy_digitalreset_6, + + input tx_phy_cal_busy_7, + input tx_phy_full_7, + input tx_phy_empty_7, + output [31:0] tx_phy_data_7, + output [ 3:0] tx_phy_kchar_7, + output tx_phy_elecidle_7, + output tx_phy_lane_polarity_7, + output tx_phy_lane_powerdown_7, + output tx_phy_bit_reversal_7, + output tx_phy_byte_reversal_7, + output tx_phy_analogreset_7, + output tx_phy_digitalreset_7, + + // tx-core interface + + input [((NUM_OF_LANES* 1)-1):0] tx_core_analogreset, + input [((NUM_OF_LANES* 1)-1):0] tx_core_digitalreset, + output [((NUM_OF_LANES* 1)-1):0] tx_core_cal_busy +); + + // rx assignments + + generate + if (NUM_OF_LANES > 0) begin + assign rx_core_locked[0] = rx_phy_locked_0; + assign rx_core_cal_busy[0] = rx_phy_cal_busy_0; + assign rx_ip_locked[0] = rx_phy_locked_0; + assign rx_ip_cal_busy[0] = rx_phy_cal_busy_0; + assign rx_ip_valid[0] = rx_phy_valid_0; + assign rx_ip_data[((32*1)-1):(32*0)] = rx_phy_data_0; + assign rx_ip_disperr[((4*1)-1):(4*0)] = rx_phy_disperr_0; + assign rx_ip_deterr[((4*1)-1):(4*0)] = rx_phy_deterr_0; + assign rx_ip_kchar[((4*1)-1):(4*0)] = rx_phy_kchar_0; + assign rx_ip_full[0] = rx_phy_full_0; + assign rx_ip_empty[0] = rx_phy_empty_0; + end + endgenerate + + generate + if (NUM_OF_LANES > 0) begin + assign rx_phy_align_en_0 = rx_ip_align_en[0]; + assign rx_phy_lane_polarity_0 = rx_ip_lane_polarity[0]; + assign rx_phy_lane_powerdown_0 = rx_ip_lane_powerdown[0]; + assign rx_phy_analogreset_0 = rx_core_analogreset[0]; + assign rx_phy_digitalreset_0 = rx_core_digitalreset[0]; + end else begin + assign rx_phy_align_en_0 = 1'd0; + assign rx_phy_lane_polarity_0 = 1'd0; + assign rx_phy_lane_powerdown_0 = 1'd0; + assign rx_phy_analogreset_0 = 1'd1; + assign rx_phy_digitalreset_0 = 1'd1; + end + endgenerate + + assign rx_phy_bit_reversal_0 = rx_ip_bit_reversal; + assign rx_phy_byte_reversal_0 = rx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 1) begin + assign rx_core_locked[1] = rx_phy_locked_1; + assign rx_core_cal_busy[1] = rx_phy_cal_busy_1; + assign rx_ip_locked[1] = rx_phy_locked_1; + assign rx_ip_cal_busy[1] = rx_phy_cal_busy_1; + assign rx_ip_valid[1] = rx_phy_valid_1; + assign rx_ip_data[((32*2)-1):(32*1)] = rx_phy_data_1; + assign rx_ip_disperr[((4*2)-1):(4*1)] = rx_phy_disperr_1; + assign rx_ip_deterr[((4*2)-1):(4*1)] = rx_phy_deterr_1; + assign rx_ip_kchar[((4*2)-1):(4*1)] = rx_phy_kchar_1; + assign rx_ip_full[1] = rx_phy_full_1; + assign rx_ip_empty[1] = rx_phy_empty_1; + end + endgenerate + + generate + if (NUM_OF_LANES > 1) begin + assign rx_phy_align_en_1 = rx_ip_align_en[1]; + assign rx_phy_lane_polarity_1 = rx_ip_lane_polarity[1]; + assign rx_phy_lane_powerdown_1 = rx_ip_lane_powerdown[1]; + assign rx_phy_analogreset_1 = rx_core_analogreset[1]; + assign rx_phy_digitalreset_1 = rx_core_digitalreset[1]; + end else begin + assign rx_phy_align_en_1 = 1'd0; + assign rx_phy_lane_polarity_1 = 1'd0; + assign rx_phy_lane_powerdown_1 = 1'd0; + assign rx_phy_analogreset_1 = 1'd1; + assign rx_phy_digitalreset_1 = 1'd1; + end + endgenerate + + assign rx_phy_bit_reversal_1 = rx_ip_bit_reversal; + assign rx_phy_byte_reversal_1 = rx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 2) begin + assign rx_core_locked[2] = rx_phy_locked_2; + assign rx_core_cal_busy[2] = rx_phy_cal_busy_2; + assign rx_ip_locked[2] = rx_phy_locked_2; + assign rx_ip_cal_busy[2] = rx_phy_cal_busy_2; + assign rx_ip_valid[2] = rx_phy_valid_2; + assign rx_ip_data[((32*3)-1):(32*2)] = rx_phy_data_2; + assign rx_ip_disperr[((4*3)-1):(4*2)] = rx_phy_disperr_2; + assign rx_ip_deterr[((4*3)-1):(4*2)] = rx_phy_deterr_2; + assign rx_ip_kchar[((4*3)-1):(4*2)] = rx_phy_kchar_2; + assign rx_ip_full[2] = rx_phy_full_2; + assign rx_ip_empty[2] = rx_phy_empty_2; + end + endgenerate + + generate + if (NUM_OF_LANES > 2) begin + assign rx_phy_align_en_2 = rx_ip_align_en[2]; + assign rx_phy_lane_polarity_2 = rx_ip_lane_polarity[2]; + assign rx_phy_lane_powerdown_2 = rx_ip_lane_powerdown[2]; + assign rx_phy_analogreset_2 = rx_core_analogreset[2]; + assign rx_phy_digitalreset_2 = rx_core_digitalreset[2]; + end else begin + assign rx_phy_align_en_2 = 1'd0; + assign rx_phy_lane_polarity_2 = 1'd0; + assign rx_phy_lane_powerdown_2 = 1'd0; + assign rx_phy_analogreset_2 = 1'd1; + assign rx_phy_digitalreset_2 = 1'd1; + end + endgenerate + + assign rx_phy_bit_reversal_2 = rx_ip_bit_reversal; + assign rx_phy_byte_reversal_2 = rx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 3) begin + assign rx_core_locked[3] = rx_phy_locked_3; + assign rx_core_cal_busy[3] = rx_phy_cal_busy_3; + assign rx_ip_locked[3] = rx_phy_locked_3; + assign rx_ip_cal_busy[3] = rx_phy_cal_busy_3; + assign rx_ip_valid[3] = rx_phy_valid_3; + assign rx_ip_data[((32*4)-1):(32*3)] = rx_phy_data_3; + assign rx_ip_disperr[((4*4)-1):(4*3)] = rx_phy_disperr_3; + assign rx_ip_deterr[((4*4)-1):(4*3)] = rx_phy_deterr_3; + assign rx_ip_kchar[((4*4)-1):(4*3)] = rx_phy_kchar_3; + assign rx_ip_full[3] = rx_phy_full_3; + assign rx_ip_empty[3] = rx_phy_empty_3; + end + endgenerate + + generate + if (NUM_OF_LANES > 3) begin + assign rx_phy_align_en_3 = rx_ip_align_en[3]; + assign rx_phy_lane_polarity_3 = rx_ip_lane_polarity[3]; + assign rx_phy_lane_powerdown_3 = rx_ip_lane_powerdown[3]; + assign rx_phy_analogreset_3 = rx_core_analogreset[3]; + assign rx_phy_digitalreset_3 = rx_core_digitalreset[3]; + end else begin + assign rx_phy_align_en_3 = 1'd0; + assign rx_phy_lane_polarity_3 = 1'd0; + assign rx_phy_lane_powerdown_3 = 1'd0; + assign rx_phy_analogreset_3 = 1'd1; + assign rx_phy_digitalreset_3 = 1'd1; + end + endgenerate + + assign rx_phy_bit_reversal_3 = rx_ip_bit_reversal; + assign rx_phy_byte_reversal_3 = rx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 4) begin + assign rx_core_locked[4] = rx_phy_locked_4; + assign rx_core_cal_busy[4] = rx_phy_cal_busy_4; + assign rx_ip_locked[4] = rx_phy_locked_4; + assign rx_ip_cal_busy[4] = rx_phy_cal_busy_4; + assign rx_ip_valid[4] = rx_phy_valid_4; + assign rx_ip_data[((32*5)-1):(32*4)] = rx_phy_data_4; + assign rx_ip_disperr[((4*5)-1):(4*4)] = rx_phy_disperr_4; + assign rx_ip_deterr[((4*5)-1):(4*4)] = rx_phy_deterr_4; + assign rx_ip_kchar[((4*5)-1):(4*4)] = rx_phy_kchar_4; + assign rx_ip_full[4] = rx_phy_full_4; + assign rx_ip_empty[4] = rx_phy_empty_4; + end + endgenerate + + generate + if (NUM_OF_LANES > 4) begin + assign rx_phy_align_en_4 = rx_ip_align_en[4]; + assign rx_phy_lane_polarity_4 = rx_ip_lane_polarity[4]; + assign rx_phy_lane_powerdown_4 = rx_ip_lane_powerdown[4]; + assign rx_phy_analogreset_4 = rx_core_analogreset[4]; + assign rx_phy_digitalreset_4 = rx_core_digitalreset[4]; + end else begin + assign rx_phy_align_en_4 = 1'd0; + assign rx_phy_lane_polarity_4 = 1'd0; + assign rx_phy_lane_powerdown_4 = 1'd0; + assign rx_phy_analogreset_4 = 1'd1; + assign rx_phy_digitalreset_4 = 1'd1; + end + endgenerate + + assign rx_phy_bit_reversal_4 = rx_ip_bit_reversal; + assign rx_phy_byte_reversal_4 = rx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 5) begin + assign rx_core_locked[5] = rx_phy_locked_5; + assign rx_core_cal_busy[5] = rx_phy_cal_busy_5; + assign rx_ip_locked[5] = rx_phy_locked_5; + assign rx_ip_cal_busy[5] = rx_phy_cal_busy_5; + assign rx_ip_valid[5] = rx_phy_valid_5; + assign rx_ip_data[((32*6)-1):(32*5)] = rx_phy_data_5; + assign rx_ip_disperr[((4*6)-1):(4*5)] = rx_phy_disperr_5; + assign rx_ip_deterr[((4*6)-1):(4*5)] = rx_phy_deterr_5; + assign rx_ip_kchar[((4*6)-1):(4*5)] = rx_phy_kchar_5; + assign rx_ip_full[5] = rx_phy_full_5; + assign rx_ip_empty[5] = rx_phy_empty_5; + end + endgenerate + + generate + if (NUM_OF_LANES > 5) begin + assign rx_phy_align_en_5 = rx_ip_align_en[5]; + assign rx_phy_lane_polarity_5 = rx_ip_lane_polarity[5]; + assign rx_phy_lane_powerdown_5 = rx_ip_lane_powerdown[5]; + assign rx_phy_analogreset_5 = rx_core_analogreset[5]; + assign rx_phy_digitalreset_5 = rx_core_digitalreset[5]; + end else begin + assign rx_phy_align_en_5 = 1'd0; + assign rx_phy_lane_polarity_5 = 1'd0; + assign rx_phy_lane_powerdown_5 = 1'd0; + assign rx_phy_analogreset_5 = 1'd1; + assign rx_phy_digitalreset_5 = 1'd1; + end + endgenerate + + assign rx_phy_bit_reversal_5 = rx_ip_bit_reversal; + assign rx_phy_byte_reversal_5 = rx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 6) begin + assign rx_core_locked[6] = rx_phy_locked_6; + assign rx_core_cal_busy[6] = rx_phy_cal_busy_6; + assign rx_ip_locked[6] = rx_phy_locked_6; + assign rx_ip_cal_busy[6] = rx_phy_cal_busy_6; + assign rx_ip_valid[6] = rx_phy_valid_6; + assign rx_ip_data[((32*7)-1):(32*6)] = rx_phy_data_6; + assign rx_ip_disperr[((4*7)-1):(4*6)] = rx_phy_disperr_6; + assign rx_ip_deterr[((4*7)-1):(4*6)] = rx_phy_deterr_6; + assign rx_ip_kchar[((4*7)-1):(4*6)] = rx_phy_kchar_6; + assign rx_ip_full[6] = rx_phy_full_6; + assign rx_ip_empty[6] = rx_phy_empty_6; + end + endgenerate + + generate + if (NUM_OF_LANES > 6) begin + assign rx_phy_align_en_6 = rx_ip_align_en[6]; + assign rx_phy_lane_polarity_6 = rx_ip_lane_polarity[6]; + assign rx_phy_lane_powerdown_6 = rx_ip_lane_powerdown[6]; + assign rx_phy_analogreset_6 = rx_core_analogreset[6]; + assign rx_phy_digitalreset_6 = rx_core_digitalreset[6]; + end else begin + assign rx_phy_align_en_6 = 1'd0; + assign rx_phy_lane_polarity_6 = 1'd0; + assign rx_phy_lane_powerdown_6 = 1'd0; + assign rx_phy_analogreset_6 = 1'd1; + assign rx_phy_digitalreset_6 = 1'd1; + end + endgenerate + + assign rx_phy_bit_reversal_6 = rx_ip_bit_reversal; + assign rx_phy_byte_reversal_6 = rx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 7) begin + assign rx_core_locked[7] = rx_phy_locked_7; + assign rx_core_cal_busy[7] = rx_phy_cal_busy_7; + assign rx_ip_locked[7] = rx_phy_locked_7; + assign rx_ip_cal_busy[7] = rx_phy_cal_busy_7; + assign rx_ip_valid[7] = rx_phy_valid_7; + assign rx_ip_data[((32*8)-1):(32*7)] = rx_phy_data_7; + assign rx_ip_disperr[((4*8)-1):(4*7)] = rx_phy_disperr_7; + assign rx_ip_deterr[((4*8)-1):(4*7)] = rx_phy_deterr_7; + assign rx_ip_kchar[((4*8)-1):(4*7)] = rx_phy_kchar_7; + assign rx_ip_full[7] = rx_phy_full_7; + assign rx_ip_empty[7] = rx_phy_empty_7; + end + endgenerate + + generate + if (NUM_OF_LANES > 7) begin + assign rx_phy_align_en_7 = rx_ip_align_en[7]; + assign rx_phy_lane_polarity_7 = rx_ip_lane_polarity[7]; + assign rx_phy_lane_powerdown_7 = rx_ip_lane_powerdown[7]; + assign rx_phy_analogreset_7 = rx_core_analogreset[7]; + assign rx_phy_digitalreset_7 = rx_core_digitalreset[7]; + end else begin + assign rx_phy_align_en_7 = 1'd0; + assign rx_phy_lane_polarity_7 = 1'd0; + assign rx_phy_lane_powerdown_7 = 1'd0; + assign rx_phy_analogreset_7 = 1'd1; + assign rx_phy_digitalreset_7 = 1'd1; + end + endgenerate + + assign rx_phy_bit_reversal_7 = rx_ip_bit_reversal; + assign rx_phy_byte_reversal_7 = rx_ip_byte_reversal; + + // tx assignments + + generate + if (NUM_OF_LANES > 0) begin + assign tx_core_cal_busy[0] = tx_phy_cal_busy_0; + assign tx_ip_cal_busy[0] = tx_phy_cal_busy_0; + assign tx_ip_full[0] = tx_phy_full_0; + assign tx_ip_empty[0] = tx_phy_empty_0; + end + endgenerate + + generate + if (NUM_OF_LANES > 0) begin + assign tx_phy_data_0 = tx_ip_data[((32*1)-1):(32*0)]; + assign tx_phy_kchar_0 = tx_ip_kchar[((4*1)-1):(4*0)]; + assign tx_phy_elecidle_0 = tx_ip_elecidle[0]; + assign tx_phy_lane_polarity_0 = tx_ip_lane_polarity[0]; + assign tx_phy_lane_powerdown_0 = tx_ip_lane_powerdown[0]; + end else begin + assign tx_phy_data_0 = 32'd0; + assign tx_phy_kchar_0 = 4'd0; + assign tx_phy_elecidle_0 = 1'd0; + assign tx_phy_lane_polarity_0 = 1'd0; + assign tx_phy_lane_powerdown_0 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES > 0) begin + assign tx_phy_analogreset_0 = tx_core_analogreset[0]; + assign tx_phy_digitalreset_0 = tx_core_digitalreset[0]; + end else begin + assign tx_phy_analogreset_0 = 1'd1; + assign tx_phy_digitalreset_0 = 1'd1; + end + endgenerate + + assign tx_phy_bit_reversal_0 = tx_ip_bit_reversal; + assign tx_phy_byte_reversal_0 = tx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 1) begin + assign tx_core_cal_busy[1] = tx_phy_cal_busy_1; + assign tx_ip_cal_busy[1] = tx_phy_cal_busy_1; + assign tx_ip_full[1] = tx_phy_full_1; + assign tx_ip_empty[1] = tx_phy_empty_1; + end + endgenerate + + generate + if (NUM_OF_LANES > 1) begin + assign tx_phy_data_1 = tx_ip_data[((32*2)-1):(32*1)]; + assign tx_phy_kchar_1 = tx_ip_kchar[((4*2)-1):(4*1)]; + assign tx_phy_elecidle_1 = tx_ip_elecidle[1]; + assign tx_phy_lane_polarity_1 = tx_ip_lane_polarity[1]; + assign tx_phy_lane_powerdown_1 = tx_ip_lane_powerdown[1]; + end else begin + assign tx_phy_data_1 = 32'd0; + assign tx_phy_kchar_1 = 4'd0; + assign tx_phy_elecidle_1 = 1'd0; + assign tx_phy_lane_polarity_1 = 1'd0; + assign tx_phy_lane_powerdown_1 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES > 1) begin + assign tx_phy_analogreset_1 = tx_core_analogreset[1]; + assign tx_phy_digitalreset_1 = tx_core_digitalreset[1]; + end else begin + assign tx_phy_analogreset_1 = 1'd1; + assign tx_phy_digitalreset_1 = 1'd1; + end + endgenerate + + assign tx_phy_bit_reversal_1 = tx_ip_bit_reversal; + assign tx_phy_byte_reversal_1 = tx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 2) begin + assign tx_core_cal_busy[2] = tx_phy_cal_busy_2; + assign tx_ip_cal_busy[2] = tx_phy_cal_busy_2; + assign tx_ip_full[2] = tx_phy_full_2; + assign tx_ip_empty[2] = tx_phy_empty_2; + end + endgenerate + + generate + if (NUM_OF_LANES > 2) begin + assign tx_phy_data_2 = tx_ip_data[((32*3)-1):(32*2)]; + assign tx_phy_kchar_2 = tx_ip_kchar[((4*3)-1):(4*2)]; + assign tx_phy_elecidle_2 = tx_ip_elecidle[2]; + assign tx_phy_lane_polarity_2 = tx_ip_lane_polarity[2]; + assign tx_phy_lane_powerdown_2 = tx_ip_lane_powerdown[2]; + end else begin + assign tx_phy_data_2 = 32'd0; + assign tx_phy_kchar_2 = 4'd0; + assign tx_phy_elecidle_2 = 1'd0; + assign tx_phy_lane_polarity_2 = 1'd0; + assign tx_phy_lane_powerdown_2 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES > 2) begin + assign tx_phy_analogreset_2 = tx_core_analogreset[2]; + assign tx_phy_digitalreset_2 = tx_core_digitalreset[2]; + end else begin + assign tx_phy_analogreset_2 = 1'd1; + assign tx_phy_digitalreset_2 = 1'd1; + end + endgenerate + + assign tx_phy_bit_reversal_2 = tx_ip_bit_reversal; + assign tx_phy_byte_reversal_2 = tx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 3) begin + assign tx_core_cal_busy[3] = tx_phy_cal_busy_3; + assign tx_ip_cal_busy[3] = tx_phy_cal_busy_3; + assign tx_ip_full[3] = tx_phy_full_3; + assign tx_ip_empty[3] = tx_phy_empty_3; + end + endgenerate + + generate + if (NUM_OF_LANES > 3) begin + assign tx_phy_data_3 = tx_ip_data[((32*4)-1):(32*3)]; + assign tx_phy_kchar_3 = tx_ip_kchar[((4*4)-1):(4*3)]; + assign tx_phy_elecidle_3 = tx_ip_elecidle[3]; + assign tx_phy_lane_polarity_3 = tx_ip_lane_polarity[3]; + assign tx_phy_lane_powerdown_3 = tx_ip_lane_powerdown[3]; + end else begin + assign tx_phy_data_3 = 32'd0; + assign tx_phy_kchar_3 = 4'd0; + assign tx_phy_elecidle_3 = 1'd0; + assign tx_phy_lane_polarity_3 = 1'd0; + assign tx_phy_lane_powerdown_3 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES > 3) begin + assign tx_phy_analogreset_3 = tx_core_analogreset[3]; + assign tx_phy_digitalreset_3 = tx_core_digitalreset[3]; + end else begin + assign tx_phy_analogreset_3 = 1'd1; + assign tx_phy_digitalreset_3 = 1'd1; + end + endgenerate + + assign tx_phy_bit_reversal_3 = tx_ip_bit_reversal; + assign tx_phy_byte_reversal_3 = tx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 4) begin + assign tx_core_cal_busy[4] = tx_phy_cal_busy_4; + assign tx_ip_cal_busy[4] = tx_phy_cal_busy_4; + assign tx_ip_full[4] = tx_phy_full_4; + assign tx_ip_empty[4] = tx_phy_empty_4; + end + endgenerate + + generate + if (NUM_OF_LANES > 4) begin + assign tx_phy_data_4 = tx_ip_data[((32*5)-1):(32*4)]; + assign tx_phy_kchar_4 = tx_ip_kchar[((4*5)-1):(4*4)]; + assign tx_phy_elecidle_4 = tx_ip_elecidle[4]; + assign tx_phy_lane_polarity_4 = tx_ip_lane_polarity[4]; + assign tx_phy_lane_powerdown_4 = tx_ip_lane_powerdown[4]; + end else begin + assign tx_phy_data_4 = 32'd0; + assign tx_phy_kchar_4 = 4'd0; + assign tx_phy_elecidle_4 = 1'd0; + assign tx_phy_lane_polarity_4 = 1'd0; + assign tx_phy_lane_powerdown_4 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES > 4) begin + assign tx_phy_analogreset_4 = tx_core_analogreset[4]; + assign tx_phy_digitalreset_4 = tx_core_digitalreset[4]; + end else begin + assign tx_phy_analogreset_4 = 1'd1; + assign tx_phy_digitalreset_4 = 1'd1; + end + endgenerate + + assign tx_phy_bit_reversal_4 = tx_ip_bit_reversal; + assign tx_phy_byte_reversal_4 = tx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 5) begin + assign tx_core_cal_busy[5] = tx_phy_cal_busy_5; + assign tx_ip_cal_busy[5] = tx_phy_cal_busy_5; + assign tx_ip_full[5] = tx_phy_full_5; + assign tx_ip_empty[5] = tx_phy_empty_5; + end + endgenerate + + generate + if (NUM_OF_LANES > 5) begin + assign tx_phy_data_5 = tx_ip_data[((32*6)-1):(32*5)]; + assign tx_phy_kchar_5 = tx_ip_kchar[((4*6)-1):(4*5)]; + assign tx_phy_elecidle_5 = tx_ip_elecidle[5]; + assign tx_phy_lane_polarity_5 = tx_ip_lane_polarity[5]; + assign tx_phy_lane_powerdown_5 = tx_ip_lane_powerdown[5]; + end else begin + assign tx_phy_data_5 = 32'd0; + assign tx_phy_kchar_5 = 4'd0; + assign tx_phy_elecidle_5 = 1'd0; + assign tx_phy_lane_polarity_5 = 1'd0; + assign tx_phy_lane_powerdown_5 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES > 5) begin + assign tx_phy_analogreset_5 = tx_core_analogreset[5]; + assign tx_phy_digitalreset_5 = tx_core_digitalreset[5]; + end else begin + assign tx_phy_analogreset_5 = 1'd1; + assign tx_phy_digitalreset_5 = 1'd1; + end + endgenerate + + assign tx_phy_bit_reversal_5 = tx_ip_bit_reversal; + assign tx_phy_byte_reversal_5 = tx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 6) begin + assign tx_core_cal_busy[6] = tx_phy_cal_busy_6; + assign tx_ip_cal_busy[6] = tx_phy_cal_busy_6; + assign tx_ip_full[6] = tx_phy_full_6; + assign tx_ip_empty[6] = tx_phy_empty_6; + end + endgenerate + + generate + if (NUM_OF_LANES > 6) begin + assign tx_phy_data_6 = tx_ip_data[((32*7)-1):(32*6)]; + assign tx_phy_kchar_6 = tx_ip_kchar[((4*7)-1):(4*6)]; + assign tx_phy_elecidle_6 = tx_ip_elecidle[6]; + assign tx_phy_lane_polarity_6 = tx_ip_lane_polarity[6]; + assign tx_phy_lane_powerdown_6 = tx_ip_lane_powerdown[6]; + end else begin + assign tx_phy_data_6 = 32'd0; + assign tx_phy_kchar_6 = 4'd0; + assign tx_phy_elecidle_6 = 1'd0; + assign tx_phy_lane_polarity_6 = 1'd0; + assign tx_phy_lane_powerdown_6 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES > 6) begin + assign tx_phy_analogreset_6 = tx_core_analogreset[6]; + assign tx_phy_digitalreset_6 = tx_core_digitalreset[6]; + end else begin + assign tx_phy_analogreset_6 = 1'd1; + assign tx_phy_digitalreset_6 = 1'd1; + end + endgenerate + + assign tx_phy_bit_reversal_6 = tx_ip_bit_reversal; + assign tx_phy_byte_reversal_6 = tx_ip_byte_reversal; + + generate + if (NUM_OF_LANES > 7) begin + assign tx_core_cal_busy[7] = tx_phy_cal_busy_7; + assign tx_ip_cal_busy[7] = tx_phy_cal_busy_7; + assign tx_ip_full[7] = tx_phy_full_7; + assign tx_ip_empty[7] = tx_phy_empty_7; + end + endgenerate + + generate + if (NUM_OF_LANES > 7) begin + assign tx_phy_data_7 = tx_ip_data[((32*8)-1):(32*7)]; + assign tx_phy_kchar_7 = tx_ip_kchar[((4*8)-1):(4*7)]; + assign tx_phy_elecidle_7 = tx_ip_elecidle[7]; + assign tx_phy_lane_polarity_7 = tx_ip_lane_polarity[7]; + assign tx_phy_lane_powerdown_7 = tx_ip_lane_powerdown[7]; + end else begin + assign tx_phy_data_7 = 32'd0; + assign tx_phy_kchar_7 = 4'd0; + assign tx_phy_elecidle_7 = 1'd0; + assign tx_phy_lane_polarity_7 = 1'd0; + assign tx_phy_lane_powerdown_7 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES > 7) begin + assign tx_phy_analogreset_7 = tx_core_analogreset[7]; + assign tx_phy_digitalreset_7 = tx_core_digitalreset[7]; + end else begin + assign tx_phy_analogreset_7 = 1'd1; + assign tx_phy_digitalreset_7 = 1'd1; + end + endgenerate + + assign tx_phy_bit_reversal_7 = tx_ip_bit_reversal; + assign tx_phy_byte_reversal_7 = tx_ip_byte_reversal; + +endmodule diff --git a/adi_library/intel/avl_adxphy/avl_adxphy_hw.tcl b/adi_library/intel/avl_adxphy/avl_adxphy_hw.tcl new file mode 100644 index 00000000..ccd05cab --- /dev/null +++ b/adi_library/intel/avl_adxphy/avl_adxphy_hw.tcl @@ -0,0 +1,119 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl + +set_module_property NAME avl_adxphy +set_module_property DESCRIPTION "Avalon ADXPHY Core" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME avl_adxphy +set_module_property ELABORATION_CALLBACK p_avl_adxphy + +# files + +add_fileset quartus_synth QUARTUS_SYNTH "" "" +set_fileset_property quartus_synth TOP_LEVEL avl_adxphy +add_fileset_file avl_adxphy.v VERILOG PATH avl_adxphy.v TOP_LEVEL_FILE + +# parameters + +add_parameter TX_OR_RX_N INTEGER 0 +set_parameter_property TX_OR_RX_N DISPLAY_NAME TX_OR_RX_N +set_parameter_property TX_OR_RX_N UNITS None +set_parameter_property TX_OR_RX_N HDL_PARAMETER false + +add_parameter NUM_OF_LANES INTEGER 4 +set_parameter_property NUM_OF_LANES DISPLAY_NAME NUM_OF_LANES +set_parameter_property NUM_OF_LANES UNITS None +set_parameter_property NUM_OF_LANES HDL_PARAMETER true + +proc p_avl_adxphy {} { + + set m_tx_or_rx_n [get_parameter_value TX_OR_RX_N] + set m_num_of_lanes [get_parameter_value NUM_OF_LANES] + + if {$m_tx_or_rx_n == 1} { + + ad_conduit tx_core_analogreset tx_analogreset tx_core_analogreset input $m_num_of_lanes + ad_conduit tx_core_digitalreset tx_digitalreset tx_core_digitalreset input $m_num_of_lanes + ad_conduit tx_core_cal_busy tx_cal_busy tx_core_cal_busy output $m_num_of_lanes + + ad_conduit tx_ip_cal_busy tx_cal_busy tx_ip_cal_busy output $m_num_of_lanes + ad_conduit tx_ip_pcfifo_full export tx_ip_full output $m_num_of_lanes + ad_conduit tx_ip_pcfifo_empty export tx_ip_empty output $m_num_of_lanes + ad_conduit tx_ip_pcs_data export tx_ip_data input 32*$m_num_of_lanes + ad_conduit tx_ip_pcs_kchar_data export tx_ip_kchar input 4*$m_num_of_lanes + ad_conduit tx_ip_elecidle export tx_ip_elecidle input $m_num_of_lanes + ad_conduit tx_ip_csr_lane_polarity export tx_ip_lane_polarity input $m_num_of_lanes + ad_conduit tx_ip_csr_lane_powerdown export tx_ip_lane_powerdown input $m_num_of_lanes + ad_conduit tx_ip_csr_bit_reversal export rx_ip_bit_reversal input 1 + ad_conduit tx_ip_csr_byte_reversal export rx_ip_byte_reversal input 1 + + for {set n 0} {$n < $m_num_of_lanes} {incr n} { + + ad_conduit tx_phy${n}_cal_busy tx_cal_busy tx_phy_cal_busy_${n} input 1 + ad_conduit tx_phy${n}_pcfifo_full export tx_phy_full_${n} input 1 + ad_conduit tx_phy${n}_pcfifo_empty export tx_phy_empty_${n} input 1 + ad_conduit tx_phy${n}_pcs_data export tx_phy_data_${n} output 32 + ad_conduit tx_phy${n}_pcs_kchar_data export tx_phy_kchar_${n} output 4 + ad_conduit tx_phy${n}_elecidle export tx_phy_elecidle_${n} output 1 + ad_conduit tx_phy${n}_csr_lane_polarity export tx_phy_lane_polarity_${n} output 1 + ad_conduit tx_phy${n}_csr_lane_powerdown export tx_phy_lane_powerdown_${n} output 1 + ad_conduit tx_phy${n}_csr_bit_reversal export tx_phy_bit_reversal_${n} output 1 + ad_conduit tx_phy${n}_csr_byte_reversal export tx_phy_byte_reversal_${n} output 1 + ad_conduit tx_phy${n}_analogreset tx_analogreset tx_phy_analogreset_${n} output 1 + ad_conduit tx_phy${n}_digitalreset tx_digitalreset tx_phy_digitalreset_${n} output 1 + } + } + + if {$m_tx_or_rx_n == 0} { + + ad_conduit rx_core_analogreset rx_analogreset rx_core_analogreset input $m_num_of_lanes + ad_conduit rx_core_digitalreset rx_digitalreset rx_core_digitalreset input $m_num_of_lanes + ad_conduit rx_core_is_lockedtodata rx_is_lockedtodata rx_core_locked output $m_num_of_lanes + ad_conduit rx_core_cal_busy rx_cal_busy rx_core_cal_busy output $m_num_of_lanes + + ad_conduit rx_ip_is_lockedtodata rx_is_lockedtodata rx_ip_locked output $m_num_of_lanes + ad_conduit rx_ip_cal_busy rx_cal_busy rx_ip_cal_busy output $m_num_of_lanes + ad_conduit rx_ip_pcs_data_valid export rx_ip_valid output $m_num_of_lanes + ad_conduit rx_ip_pcs_data export rx_ip_data output 32*$m_num_of_lanes + ad_conduit rx_ip_pcs_disperr export rx_ip_disperr output 4*$m_num_of_lanes + ad_conduit rx_ip_pcs_errdetect export rx_ip_deterr output 4*$m_num_of_lanes + ad_conduit rx_ip_pcs_kchar_data export rx_ip_kchar output 4*$m_num_of_lanes + ad_conduit rx_ip_pcfifo_full export rx_ip_full output $m_num_of_lanes + ad_conduit rx_ip_pcfifo_empty export rx_ip_empty output $m_num_of_lanes + ad_conduit rx_ip_patternalign_en export rx_ip_align_en input $m_num_of_lanes + ad_conduit rx_ip_csr_lane_polarity export rx_ip_lane_polarity input $m_num_of_lanes + ad_conduit rx_ip_csr_lane_powerdown export rx_ip_lane_powerdown input $m_num_of_lanes + ad_conduit rx_ip_csr_bit_reversal export rx_ip_bit_reversal input 1 + ad_conduit rx_ip_csr_byte_reversal export rx_ip_byte_reversal input 1 + + for {set n 0} {$n < $m_num_of_lanes} {incr n} { + + ad_conduit rx_phy${n}_is_lockedtodata rx_is_lockedtodata rx_phy_locked_${n} input 1 + ad_conduit rx_phy${n}_cal_busy rx_cal_busy rx_phy_cal_busy_${n} input 1 + ad_conduit rx_phy${n}_pcs_data_valid export rx_phy_valid_${n} input 1 + ad_conduit rx_phy${n}_pcs_data export rx_phy_data_${n} input 32 + ad_conduit rx_phy${n}_pcs_disperr export rx_phy_disperr_${n} input 4 + ad_conduit rx_phy${n}_pcs_errdetect export rx_phy_deterr_${n} input 4 + ad_conduit rx_phy${n}_pcs_kchar_data export rx_phy_kchar_${n} input 4 + ad_conduit rx_phy${n}_pcfifo_full export rx_phy_full_${n} input 1 + ad_conduit rx_phy${n}_pcfifo_empty export rx_phy_empty_${n} input 1 + ad_conduit rx_phy${n}_patternalign_en export rx_phy_align_en_${n} output 1 + ad_conduit rx_phy${n}_csr_lane_polarity export rx_phy_lane_polarity_${n} output 1 + ad_conduit rx_phy${n}_csr_lane_powerdown export rx_phy_lane_powerdown_${n} output 1 + ad_conduit rx_phy${n}_csr_bit_reversal export rx_phy_bit_reversal_${n} output 1 + ad_conduit rx_phy${n}_csr_byte_reversal export rx_phy_byte_reversal_${n} output 1 + ad_conduit rx_phy${n}_analogreset rx_analogreset rx_phy_analogreset_${n} output 1 + ad_conduit rx_phy${n}_digitalreset rx_digitalreset rx_phy_digitalreset_${n} output 1 + } + } +} + + diff --git a/adi_library/intel/avl_dacfifo/.timestamp_intel b/adi_library/intel/avl_dacfifo/.timestamp_intel new file mode 100644 index 00000000..e69de29b diff --git a/adi_library/intel/avl_dacfifo/Makefile b/adi_library/intel/avl_dacfifo/Makefile new file mode 100644 index 00000000..99400d4a --- /dev/null +++ b/adi_library/intel/avl_dacfifo/Makefile @@ -0,0 +1,20 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := avl_dacfifo + +INTEL_DEPS += ../../common/ad_b2g.v +INTEL_DEPS += ../../common/ad_g2b.v +INTEL_DEPS += ../../common/ad_mem.v +INTEL_DEPS += ../../common/util_delay.v +INTEL_DEPS += avl_dacfifo.v +INTEL_DEPS += avl_dacfifo_constr.sdc +INTEL_DEPS += avl_dacfifo_hw.tcl +INTEL_DEPS += avl_dacfifo_rd.v +INTEL_DEPS += avl_dacfifo_wr.v +INTEL_DEPS += util_dacfifo_bypass.v + +include ../../scripts/library.mk diff --git a/adi_library/intel/avl_dacfifo/avl_dacfifo.v b/adi_library/intel/avl_dacfifo/avl_dacfifo.v new file mode 100644 index 00000000..258ae14f --- /dev/null +++ b/adi_library/intel/avl_dacfifo/avl_dacfifo.v @@ -0,0 +1,261 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module avl_dacfifo #( + + parameter DAC_DATA_WIDTH = 64, + parameter DAC_MEM_ADDRESS_WIDTH = 8, + parameter DMA_DATA_WIDTH = 64, + parameter DMA_MEM_ADDRESS_WIDTH = 10, + parameter AVL_DATA_WIDTH = 512, + parameter AVL_ADDRESS_WIDTH = 25, + parameter AVL_BURST_LENGTH = 127, + parameter AVL_BASE_ADDRESS = 32'h00000000, + parameter AVL_ADDRESS_LIMIT = 32'h1fffffff +) ( + + // dma interface + + input dma_clk, + input dma_rst, + input dma_valid, + input [(DMA_DATA_WIDTH-1):0] dma_data, + output reg dma_ready, + input dma_xfer_req, + input dma_xfer_last, + + // dac interface + + input dac_clk, + input dac_rst, + input dac_valid, + output reg [(DAC_DATA_WIDTH-1):0] dac_data, + output reg dac_dunf, + output reg dac_xfer_out, + + input bypass, + + // avalon interface + + input avl_clk, + input avl_reset, + + output reg [(AVL_ADDRESS_WIDTH-1):0] avl_address, + output reg [ 6:0] avl_burstcount, + output reg [ 63:0] avl_byteenable, + output avl_read, + input [(AVL_DATA_WIDTH-1):0] avl_readdata, + input avl_readdata_valid, + input avl_ready, + output avl_write, + output [(AVL_DATA_WIDTH-1):0] avl_writedata +); + + localparam FIFO_BYPASS = (DAC_DATA_WIDTH == DMA_DATA_WIDTH) ? 1 : 0; + + // internal register + + reg dma_bypass_m1 = 1'b0; + reg dma_bypass = 1'b0; + reg dac_bypass_m1 = 1'b0; + reg dac_bypass = 1'b0; + reg dac_xfer_out_m1 = 1'b0; + reg dac_xfer_out_bypass = 1'b0; + + // internal signals + + wire dma_ready_wr_s; + wire dma_ready_bypass_s; + wire avl_read_s; + wire avl_write_s; + wire [ 24:0] avl_wr_address_s; + wire [ 24:0] avl_rd_address_s; + wire [ 24:0] avl_last_address_s; + wire [ 6:0] avl_last_burstcount_s; + wire [ 7:0] dma_last_beats_s; + wire [ 6:0] avl_wr_burstcount_s; + wire [ 6:0] avl_rd_burstcount_s; + wire [ 63:0] avl_wr_byteenable_s; + wire [ 63:0] avl_rd_byteenable_s; + wire avl_xfer_wren_s; + wire avl_xfer_out_s; + wire avl_xfer_in_s; + wire [(DAC_DATA_WIDTH-1):0] dac_data_fifo_s; + wire [(DAC_DATA_WIDTH-1):0] dac_data_bypass_s; + wire dac_xfer_fifo_out_s; + wire dac_dunf_fifo_s; + wire dac_dunf_bypass_s; + + avl_dacfifo_wr #( + .AVL_DATA_WIDTH (AVL_DATA_WIDTH), + .DMA_DATA_WIDTH (DMA_DATA_WIDTH), + .AVL_DDR_BASE_ADDRESS (AVL_BASE_ADDRESS), + .DMA_MEM_ADDRESS_WIDTH(DMA_MEM_ADDRESS_WIDTH), + .AVL_BURST_LENGTH (AVL_BURST_LENGTH) + ) i_wr ( + .dma_clk (dma_clk), + .dma_data (dma_data), + .dma_ready (dma_ready), + .dma_ready_out (dma_ready_wr_s), + .dma_valid (dma_valid), + .dma_xfer_req (dma_xfer_req), + .dma_xfer_last (dma_xfer_last), + .dma_last_beats (dma_last_beats_s), + .avl_last_address (avl_last_address_s), + .avl_last_burstcount (avl_last_burstcount_s), + .avl_clk (avl_clk), + .avl_reset (avl_reset), + .avl_address (avl_wr_address_s), + .avl_burstcount (avl_wr_burstcount_s), + .avl_byteenable (avl_wr_byteenable_s), + .avl_waitrequest (~avl_ready), + .avl_write (avl_write), + .avl_data (avl_writedata), + .avl_xfer_req_out (avl_xfer_out_s), + .avl_xfer_req_in (avl_xfer_in_s)); + + avl_dacfifo_rd #( + .AVL_DATA_WIDTH(AVL_DATA_WIDTH), + .DAC_DATA_WIDTH(DAC_DATA_WIDTH), + .AVL_DDR_BASE_ADDRESS(AVL_BASE_ADDRESS), + .AVL_DDR_ADDRESS_LIMIT(AVL_ADDRESS_LIMIT), + .DAC_MEM_ADDRESS_WIDTH(DAC_MEM_ADDRESS_WIDTH), + .AVL_BURST_LENGTH (AVL_BURST_LENGTH) + ) i_rd ( + .dac_clk(dac_clk), + .dac_reset(dac_rst), + .dac_valid(dac_valid), + .dac_data(dac_data_fifo_s), + .dac_xfer_req(dac_xfer_fifo_out_s), + .dac_dunf(dac_dunf_fifo_s), + .avl_clk(avl_clk), + .avl_reset(avl_reset), + .avl_address(avl_rd_address_s), + .avl_burstcount(avl_rd_burstcount_s), + .avl_byteenable(avl_rd_byteenable_s), + .avl_waitrequest(~avl_ready), + .avl_readdatavalid(avl_readdata_valid), + .avl_read(avl_read), + .avl_data(avl_readdata), + .avl_last_address(avl_last_address_s), + .avl_last_burstcount(avl_last_burstcount_s), + .dma_last_beats(dma_last_beats_s), + .avl_xfer_req_in(avl_xfer_out_s), + .avl_xfer_req_out(avl_xfer_in_s)); + + // avalon address multiplexer and output registers + + assign avl_xfer_wren_s = ~avl_xfer_in_s; + + always @(posedge avl_clk) begin + if (avl_reset == 1'b1) begin + avl_address <= 0; + avl_burstcount <= 0; + avl_byteenable <= 0; + end else if (avl_ready) begin + avl_address <= (avl_xfer_wren_s == 1'b1) ? avl_wr_address_s : avl_rd_address_s; + avl_burstcount <= (avl_xfer_wren_s == 1'b1) ? avl_wr_burstcount_s : avl_rd_burstcount_s; + avl_byteenable <= (avl_xfer_wren_s == 1'b1) ? avl_wr_byteenable_s : avl_rd_byteenable_s; + end + end + + // bypass logic -- supported if DAC_DATA_WIDTH == DMA_DATA_WIDTH + + generate + if (FIFO_BYPASS) begin + + util_dacfifo_bypass #( + .DAC_DATA_WIDTH (DAC_DATA_WIDTH), + .DMA_DATA_WIDTH (DMA_DATA_WIDTH) + ) i_dacfifo_bypass ( + .dma_clk(dma_clk), + .dma_data(dma_data), + .dma_ready(dma_ready), + .dma_ready_out(dma_ready_bypass_s), + .dma_valid(dma_valid), + .dma_xfer_req(dma_xfer_req), + .dac_clk(dac_clk), + .dac_rst(dac_rst), + .dac_valid(dac_valid), + .dac_data(dac_data_bypass_s), + .dac_dunf(dac_dunf_bypass_s)); + + always @(posedge dma_clk) begin + dma_bypass_m1 <= bypass; + dma_bypass <= dma_bypass_m1; + end + + always @(posedge dac_clk) begin + dac_bypass_m1 <= bypass; + dac_bypass <= dac_bypass_m1; + dac_xfer_out_m1 <= dma_xfer_req; + dac_xfer_out_bypass <= dac_xfer_out_m1; + end + + // mux for the dma_ready + + always @(posedge dma_clk) begin + dma_ready <= (dma_bypass) ? dma_ready_bypass_s : dma_ready_wr_s; + end + + // mux for dac data + + always @(posedge dac_clk) begin + if (dac_valid) begin + dac_data <= (dac_bypass) ? dac_data_bypass_s : dac_data_fifo_s; + end + dac_xfer_out <= (dac_bypass) ? dac_xfer_out_bypass : dac_xfer_fifo_out_s; + dac_dunf <= (dac_bypass) ? dac_dunf_bypass_s : dac_dunf_fifo_s; + end + + end else begin /* if (~FIFO_BYPASS) */ + + always @(posedge dma_clk) begin + dma_ready <= dma_ready_wr_s; + end + always @(posedge dac_clk) begin + if (dac_valid) begin + dac_data <= dac_data_fifo_s; + end + dac_xfer_out <= dac_xfer_fifo_out_s; + dac_dunf <= dac_dunf_fifo_s; + end + + end + endgenerate + +endmodule diff --git a/adi_library/intel/avl_dacfifo/avl_dacfifo_constr.sdc b/adi_library/intel/avl_dacfifo/avl_dacfifo_constr.sdc new file mode 100644 index 00000000..9b835f54 --- /dev/null +++ b/adi_library/intel/avl_dacfifo/avl_dacfifo_constr.sdc @@ -0,0 +1,44 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# CDC paths + +set_false_path -from [get_registers *avl_dacfifo_rd:i_rd|dac_mem_raddr_g*] \ + -to [get_registers *avl_dacfifo_rd:i_rd|avl_mem_raddr_m1*] +set_false_path -from [get_registers *avl_dacfifo_rd:i_rd|avl_mem_waddr_g*] \ + -to [get_registers *avl_dacfifo_rd:i_rd|dac_mem_waddr_m1*] +set_false_path -from [get_registers *avl_dacfifo_rd:i_rd|avl_xfer_req_out*] \ + -to [get_registers *avl_dacfifo_rd:i_rd|dac_avl_xfer_req_m1*] +set_false_path -from [get_registers *avl_dacfifo_rd:i_rd|avl_mem_laddr_toggle*] \ + -to [get_registers *avl_dacfifo_rd:i_rd|dac_mem_laddr_toggle_m[0]] +set_false_path -to [get_registers *avl_dacfifo_rd:i_rd|dac_mem_laddr*] +set_false_path -to [get_registers *avl_dacfifo_rd:i_rd|dac_dma_last_beats_m1*] + +set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|avl_xfer_req_lp*] \ + -to [get_registers *avl_dacfifo_wr:i_wr|dma_xfer_req_lp_m1*] +set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|avl_xfer_req_out*] \ + -to [get_registers *avl_dacfifo_wr:i_wr|dma_avl_xfer_req_out_m1*] +set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|avl_mem_raddr_g*] \ + -to [get_registers *avl_dacfifo_wr:i_wr|dma_mem_raddr_m1*] +set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|dma_xfer_req*] \ + -to [get_registers *avl_dacfifo_wr:i_wr|avl_dma_xfer_req_m1*] +set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|dma_mem_waddr_g*] \ + -to [get_registers *avl_dacfifo_wr:i_wr|avl_mem_waddr_m1*] +set_false_path -from [get_registers *avl_dacfifo_wr:i_wr|dma_last_beats*] \ + -to [get_registers *avl_dacfifo_wr:i_wr|avl_dma_last_beats_m1*] + +set_false_path -from [get_registers *util_dacfifo_bypass:i_dacfifo_bypass|dac_mem_raddr_g*] \ + -to [get_registers *util_dacfifo_bypass:i_dacfifo_bypass|dma_mem_raddr_m1*] + +set_false_path -from [get_registers *util_dacfifo_bypass:i_dacfifo_bypass|dma_mem_waddr_g*] \ + -to [get_registers *util_dacfifo_bypass:i_dacfifo_bypass|dac_mem_waddr_m1*] +set_false_path -to [get_registers *util_dacfifo_bypass:i_dacfifo_bypass|dac_xfer_out_m1*] + +set_false_path -to [get_registers *avl_dacfifo:*avl_dma_xfer_req_m1*] +set_false_path -to [get_registers *avl_dacfifo:*dac_xfer_out_m1*] +set_false_path -to [get_registers *avl_dacfifo:*bypass_m1*] + +set_false_path -to [get_registers *util_dacfifo_bypass:i_dacfifo_bypass|dma_rst_m1*] + diff --git a/adi_library/intel/avl_dacfifo/avl_dacfifo_hw.tcl b/adi_library/intel/avl_dacfifo/avl_dacfifo_hw.tcl new file mode 100644 index 00000000..3e80d631 --- /dev/null +++ b/adi_library/intel/avl_dacfifo/avl_dacfifo_hw.tcl @@ -0,0 +1,143 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +source ../../../scripts/adi_env.tcl +source ../../scripts/adi_ip_intel.tcl + +ad_ip_create avl_dacfifo {Avalon DDR DAC Fifo} p_avl_dacfifo_elab +ad_ip_files avl_dacfifo [list\ + $ad_hdl_dir/library/common/util_delay.v \ + $ad_hdl_dir/library/common/ad_b2g.v \ + $ad_hdl_dir/library/common/ad_g2b.v \ + $ad_hdl_dir/library/common/ad_mem.v \ + util_dacfifo_bypass.v \ + avl_dacfifo_wr.v \ + avl_dacfifo_rd.v \ + avl_dacfifo.v \ + avl_dacfifo_constr.sdc] + +# parameters + +ad_ip_parameter DEVICE_FAMILY STRING {Arria 10} +ad_ip_parameter DAC_DATA_WIDTH INTEGER 64 +ad_ip_parameter DAC_MEM_ADDRESS_WIDTH INTEGER 8 +ad_ip_parameter DMA_DATA_WIDTH INTEGER 64 +ad_ip_parameter DMA_MEM_ADDRESS_WIDTH INTEGER 8 +ad_ip_parameter AVL_DATA_WIDTH INTEGER 512 +ad_ip_parameter AVL_ADDRESS_WIDTH INTEGER 25 +ad_ip_parameter AVL_BURST_LENGTH INTEGER 127 +ad_ip_parameter AVL_BASE_ADDRESS INTEGER 0 +ad_ip_parameter AVL_ADDRESS_LIMIT INTEGER 0x800000 + +# interfaces + +ad_interface clock dma_clk input 1 clk +ad_interface reset dma_rst input 1 if_dma_clk +ad_interface signal dma_xfer_req input 1 xfer_req + +add_interface s_axis axi4stream end +set_interface_property s_axis associatedClock if_dma_clk +set_interface_property s_axis associatedReset if_dma_rst +add_interface_port s_axis dma_valid tvalid Input 1 +add_interface_port s_axis dma_xfer_last tlast Input 1 +add_interface_port s_axis dma_ready tready Output 1 +add_interface_port s_axis dma_data tdata Input DMA_DATA_WIDTH + +ad_interface clock dac_clk input 1 clk +ad_interface reset dac_rst input 1 if_dac_clk +ad_interface signal dac_valid input 1 valid +ad_interface signal dac_data output DAC_DATA_WIDTH data +ad_interface signal dac_dunf output 1 unf +ad_interface signal dac_xfer_out output 1 xfer_out + +ad_interface signal bypass input 1 bypass + +add_interface avl_clock clock end +add_interface_port avl_clock avl_clk clk input 1 + +add_interface avl_reset reset end +set_interface_property avl_reset associatedclock avl_clock +add_interface_port avl_reset avl_reset reset input 1 + +add_interface amm_ddr avalon master +add_interface_port amm_ddr avl_address address output 25 +add_interface_port amm_ddr avl_burstcount burstcount output 7 +add_interface_port amm_ddr avl_byteenable byteenable output 64 +add_interface_port amm_ddr avl_read read output 1 +add_interface_port amm_ddr avl_readdata readdata input 512 +add_interface_port amm_ddr avl_readdata_valid readdatavalid input 1 +add_interface_port amm_ddr avl_ready waitrequest_n input 1 +add_interface_port amm_ddr avl_write write output 1 +add_interface_port amm_ddr avl_writedata writedata output 512 + +set_interface_property amm_ddr associatedClock avl_clock +set_interface_property amm_ddr associatedReset avl_reset +set_interface_property amm_ddr addressUnits WORDS + +# elaborate + +proc p_avl_dacfifo_elab {} { + + # read parameters + + set m_device_family [get_parameter_value "DEVICE_FAMILY"] + set m_dma_data_width [get_parameter_value "DMA_DATA_WIDTH"] + set m_dma_mem_addr_width [get_parameter_value "DMA_MEM_ADDRESS_WIDTH"] + set m_avl_data_width [get_parameter_value "AVL_DATA_WIDTH"] + set m_avl_addr_width [get_parameter_value "AVL_ADDRESS_WIDTH"] + set m_dac_data_width [get_parameter_value "DAC_DATA_WIDTH"] + set m_dac_mem_addr_width [get_parameter_value "DAC_MEM_ADDRESS_WIDTH"] + set m_dac_mem_addr_width_bypass 10 + if {$m_dma_data_width > $m_dac_data_width} { + set m_dma_to_dac_ratio [expr $m_dma_data_width/$m_dac_data_width] + if {$m_dma_to_dac_ratio eq 2} { + set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 1] + } elseif {$m_dma_to_dac_ratio eq 4} { + set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 2] + } else { + set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 3] + } + } else { + set m_dma_to_dac_ratio [expr $m_dac_data_width/$m_dma_data_width] + if {$m_dma_to_dac_ratio eq 1} { + set m_dma_mem_addr_width_bypass $m_dac_mem_addr_width_bypass + } elseif {$m_dma_to_dac_ratio eq 2} { + set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 1] + } elseif {$m_dma_to_dac_ratio eq 4} { + set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 2] + } else { + set m_dma_mem_addr_width_bypass [expr $m_dac_mem_addr_width_bypass - 3] + } + } + + # intel memory for WRITE side + + add_hdl_instance ad_mem_asym_wr intel_mem_asym 1.0 + set_instance_parameter_value ad_mem_asym_wr DEVICE_FAMILY $m_device_family + set_instance_parameter_value ad_mem_asym_wr A_ADDRESS_WIDTH $m_dma_mem_addr_width + set_instance_parameter_value ad_mem_asym_wr A_DATA_WIDTH $m_dma_data_width + set_instance_parameter_value ad_mem_asym_wr B_DATA_WIDTH $m_avl_data_width + + # intel memory for READ side + + add_hdl_instance ad_mem_asym_rd intel_mem_asym 1.0 + set_instance_parameter_value ad_mem_asym_rd DEVICE_FAMILY $m_device_family + set_instance_parameter_value ad_mem_asym_rd A_ADDRESS_WIDTH 0 + set_instance_parameter_value ad_mem_asym_rd A_DATA_WIDTH $m_avl_data_width + set_instance_parameter_value ad_mem_asym_rd B_ADDRESS_WIDTH $m_dac_mem_addr_width + set_instance_parameter_value ad_mem_asym_rd B_DATA_WIDTH $m_dac_data_width + + # intel memory for bypass logic + + add_hdl_instance ad_mem_asym_bypass intel_mem_asym 1.0 + set_instance_parameter_value ad_mem_asym_bypass DEVICE_FAMILY $m_device_family + set_instance_parameter_value ad_mem_asym_bypass A_ADDRESS_WIDTH $m_dma_mem_addr_width_bypass + set_instance_parameter_value ad_mem_asym_bypass A_DATA_WIDTH $m_dma_data_width + set_instance_parameter_value ad_mem_asym_bypass B_ADDRESS_WIDTH $m_dac_mem_addr_width_bypass + set_instance_parameter_value ad_mem_asym_bypass B_DATA_WIDTH $m_dac_data_width + +} + diff --git a/adi_library/intel/avl_dacfifo/avl_dacfifo_rd.v b/adi_library/intel/avl_dacfifo/avl_dacfifo_rd.v new file mode 100644 index 00000000..722b98b3 --- /dev/null +++ b/adi_library/intel/avl_dacfifo/avl_dacfifo_rd.v @@ -0,0 +1,540 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module avl_dacfifo_rd #( + + parameter AVL_DATA_WIDTH = 512, + parameter DAC_DATA_WIDTH = 64, + parameter AVL_BURST_LENGTH = 127, + parameter AVL_DDR_BASE_ADDRESS = 0, + parameter AVL_DDR_ADDRESS_LIMIT = 33554432, + parameter DAC_MEM_ADDRESS_WIDTH = 8 +) ( + input dac_clk, + input dac_reset, + input dac_valid, + output reg [(DAC_DATA_WIDTH-1):0] dac_data, + output reg dac_xfer_req, + output reg dac_dunf, + + input avl_clk, + input avl_reset, + output reg [24:0] avl_address, + output reg [ 6:0] avl_burstcount, + output [63:0] avl_byteenable, + input avl_waitrequest, + input avl_readdatavalid, + output reg avl_read, + input [AVL_DATA_WIDTH-1:0] avl_data, + + input [24:0] avl_last_address, + input [ 6:0] avl_last_burstcount, + input [ 7:0] dma_last_beats, + input avl_xfer_req_in, + output reg avl_xfer_req_out +); + + // Max supported MEM_RATIO is 16 + localparam MEM_RATIO = AVL_DATA_WIDTH/DAC_DATA_WIDTH; + localparam AVL_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_MEM_ADDRESS_WIDTH : + (MEM_RATIO == 2) ? (DAC_MEM_ADDRESS_WIDTH - 1) : + (MEM_RATIO == 4) ? (DAC_MEM_ADDRESS_WIDTH - 2) : + (MEM_RATIO == 8) ? (DAC_MEM_ADDRESS_WIDTH - 3) : + (MEM_RATIO == 16) ? (DAC_MEM_ADDRESS_WIDTH - 4) : + (DAC_MEM_ADDRESS_WIDTH - 5); + localparam AVL_MEM_THRESHOLD_LO = AVL_BURST_LENGTH; + localparam AVL_MEM_THRESHOLD_HI = {(AVL_MEM_ADDRESS_WIDTH){1'b1}} - AVL_BURST_LENGTH; + localparam DAC_MEM_THRESHOLD = 2 * (AVL_BURST_LENGTH * MEM_RATIO); + + localparam MEM_WIDTH_DIFF = (MEM_RATIO > 16) ? 5 : + (MEM_RATIO > 8) ? 4 : + (MEM_RATIO > 4) ? 3 : + (MEM_RATIO > 2) ? 2 : + (MEM_RATIO > 1) ? 1 : 1; + + // FSM state definition + + localparam IDLE = 5'b00001; + localparam XFER_STAGING = 5'b00010; + localparam XFER_FULL_BURST = 5'b00100; + localparam XFER_PARTIAL_BURST = 5'b01000; + localparam XFER_END = 5'b10000; + + // internal register + + reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_waddr; + reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_laddr; + reg avl_mem_laddr_toggle; + reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_waddr_g; + reg [DAC_MEM_ADDRESS_WIDTH-1:0] avl_mem_raddr; + reg [DAC_MEM_ADDRESS_WIDTH-1:0] avl_mem_raddr_m1; + reg [DAC_MEM_ADDRESS_WIDTH-1:0] avl_mem_raddr_m2; + reg avl_mem_request_data; + reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_addr_diff; + reg [ 4:0] avl_read_state; + reg [ 7:0] avl_burstcounter; + reg avl_inread; + + reg [AVL_MEM_ADDRESS_WIDTH-1:0] dac_mem_waddr; + reg [AVL_MEM_ADDRESS_WIDTH-1:0] dac_mem_waddr_m1; + reg [AVL_MEM_ADDRESS_WIDTH-1:0] dac_mem_waddr_m2; + reg [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_laddr; + reg [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_raddr; + reg [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_raddr_g; + reg [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_addr_diff; + reg [ 7:0] dac_mem_laddr_waddr; + reg [ 7:0] dac_mem_laddr_raddr; + reg dac_mem_laddr_valid; + + reg dac_avl_xfer_req; + reg dac_avl_xfer_req_m1; + reg dac_avl_xfer_req_m2; + + reg [ 7:0] dac_dma_last_beats_m1; + reg [ 7:0] dac_dma_last_beats_m2; + reg [ 7:0] dac_dma_last_beats; + reg [ 3:0] dac_mem_laddr_toggle_m; + reg [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_laddr_b; + reg dac_mem_renable; + reg dac_mem_valid; + reg dac_xfer_req_d; + + // internal signals + + wire avl_fifo_reset_s; + wire [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_raddr_s; + wire [AVL_MEM_ADDRESS_WIDTH:0] avl_mem_addr_diff_s; + wire [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_waddr_b2g_s; + wire [DAC_MEM_ADDRESS_WIDTH-1:0] avl_mem_raddr_g2b_s; + wire [DAC_MEM_ADDRESS_WIDTH-1:0] avl_mem_laddr_s; + wire avl_read_int_s; + wire avl_end_of_burst_s; + + wire dac_fifo_reset_s; + wire [DAC_MEM_ADDRESS_WIDTH:0] dac_mem_addr_diff_s; + wire [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_waddr_s; + wire [AVL_MEM_ADDRESS_WIDTH-1:0] dac_mem_waddr_g2b_s; + wire [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_raddr_b2g_s; + wire [DAC_DATA_WIDTH-1:0] dac_mem_data_s; + wire dac_mem_laddr_wea_s; + wire dac_mem_laddr_rea_s; + wire dac_mem_laddr_unf_s; + wire [DAC_MEM_ADDRESS_WIDTH-1:0] dac_mem_laddr_s; + wire dac_mem_dunf_s; + + // An asymmetric memory to transfer data from Avalon interface to DAC + // interface + + ad_mem_asym_rd i_mem_asym ( + .mem_i_wrclock_clk (avl_clk), + .mem_i_wren_wren (avl_readdatavalid), + .mem_i_wraddress_wraddress (avl_mem_waddr), + .mem_i_datain_datain (avl_data), + .mem_i_rdclock_clk (dac_clk), + .mem_i_rdaddress_rdaddress (dac_mem_raddr), + .mem_o_dataout_dataout (dac_mem_data_s)); + + // the fifo reset is the dma_xfer_req + + assign avl_fifo_reset_s = avl_reset || ~avl_xfer_req_out; + assign dac_fifo_reset_s = dac_reset || ~dac_avl_xfer_req; + + // loop back the avl_xfer_req to the WRITE module -- this way we can make + // sure, that in case of a new DMA transfer, the last avalon read burst is + // finished, so the upcomming avalon writes will not block the interface + + always @(posedge avl_clk) begin + if (avl_reset == 1'b1) begin + avl_xfer_req_out <= 1'b0; + end else begin + if ((avl_read_state == IDLE) || + (avl_read_state == XFER_STAGING) || + (avl_read_state == XFER_END)) begin + avl_xfer_req_out <= avl_xfer_req_in; + end + end + end + + // FSM to generate the necessary Avalon Write transactions + + always @(posedge avl_clk) begin + if (avl_fifo_reset_s == 1'b1) begin + avl_read_state <= IDLE; + avl_burstcount <= AVL_BURST_LENGTH; + end else begin + case (avl_read_state) + IDLE : begin + if (avl_xfer_req_in == 1'b1) begin + avl_read_state <= XFER_STAGING; + end else begin + avl_read_state <= IDLE; + end + end + XFER_STAGING : begin + if (avl_xfer_req_in == 1'b1) begin + if (avl_mem_request_data == 1'b1) begin + if (avl_address + AVL_BURST_LENGTH <= avl_last_address) begin + avl_read_state <= XFER_FULL_BURST; + avl_burstcount <= AVL_BURST_LENGTH; + end else begin + avl_read_state <= XFER_PARTIAL_BURST; + avl_burstcount <= avl_last_burstcount; + end + end + end else begin + avl_read_state <= IDLE; + end + end + // Avalon transaction with full burst length + XFER_FULL_BURST : begin + if (avl_burstcounter < avl_burstcount) begin + avl_read_state <= XFER_FULL_BURST; + end else begin + avl_read_state <= XFER_STAGING; + end + end + // Avalon transaction with the remaining data, burst length is less than + // the maximum supported burst length + XFER_PARTIAL_BURST : begin + if (avl_burstcounter < avl_burstcount) begin + avl_read_state <= XFER_PARTIAL_BURST; + end else begin + avl_read_state <= XFER_END; + end + end + XFER_END : begin + avl_read_state <= IDLE; + end + default : begin + avl_read_state <= IDLE; + end + endcase + end + end + + // FSM outputs + + assign avl_read_int_s = ((avl_read_state == XFER_FULL_BURST) || + (avl_read_state == XFER_PARTIAL_BURST)) ? 1 : 0; + assign avl_end_of_burst_s = (avl_burstcount == avl_burstcounter) ? 1 : 0; + + // Avalon address generation and read control signaling + + always @(posedge avl_clk) begin + if (avl_fifo_reset_s == 1'b1) begin + avl_address <= AVL_DDR_BASE_ADDRESS; + end else begin + if (avl_end_of_burst_s == 1'b1) begin + avl_address <= (avl_address < avl_last_address) ? avl_address + avl_burstcount : AVL_DDR_BASE_ADDRESS; + end + end + end + + always @(posedge avl_clk) begin + if (avl_reset == 1'b1) begin + avl_read <= 1'b0; + avl_inread <= 1'b0; + end else begin + if (avl_read == 1'b0) begin + if ((avl_waitrequest == 1'b0) && (avl_read_int_s == 1'b1) && (avl_inread == 1'b0)) begin + avl_read <= 1'b1; + avl_inread <= 1'b1; + end + end else if ((avl_read == 1'b1) && (avl_waitrequest == 1'b0)) begin + avl_read <= 1'b0; + end + if (avl_end_of_burst_s == 1'b1) begin + avl_inread <= 1'b0; + end + end + end + + // Avalon burstcounter + + always @(posedge avl_clk) begin + if (avl_fifo_reset_s == 1'b1) begin + avl_burstcounter <= 8'b0; + end else begin + if ((avl_read_int_s == 1'b1) && (avl_readdatavalid == 1'b1)) begin + avl_burstcounter <= (avl_burstcounter < avl_burstcount) ? avl_burstcounter + 1'b1 : 1'b0; + end else if (avl_end_of_burst_s == 1'b1) begin + avl_burstcounter <= 8'b0; + end + end + end + + assign avl_byteenable = {64{1'b1}}; + + // write data from Avalon interface into the async FIFO + + always @(posedge avl_clk) begin + if (avl_fifo_reset_s == 1'b1) begin + avl_mem_waddr <= 'b0; + avl_mem_waddr_g <= 'b0; + avl_mem_laddr <= 'b0; + avl_mem_laddr_toggle <= 1'b0; + end else begin + if (avl_readdatavalid == 1'b1) begin + avl_mem_waddr <= avl_mem_waddr + 1'b1; + end + if (avl_read_state == XFER_END) begin + avl_mem_laddr <= avl_mem_waddr - 1'b1; + avl_mem_laddr_toggle <= ~avl_mem_laddr_toggle; + end + avl_mem_waddr_g <= avl_mem_waddr_b2g_s; + end + end + + ad_b2g #( + .DATA_WIDTH(AVL_MEM_ADDRESS_WIDTH) + ) i_avl_mem_wr_addr_b2g ( + .din (avl_mem_waddr), + .dout (avl_mem_waddr_b2g_s)); + + // control the FIFO to prevent overflow, underflow is monitored + + assign avl_mem_raddr_s = (MEM_RATIO == 1) ? avl_mem_raddr : + (MEM_RATIO == 2) ? avl_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):1] : + (MEM_RATIO == 4) ? avl_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):2] : + (MEM_RATIO == 8) ? avl_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):3] : + (MEM_RATIO == 16) ? avl_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):4] : + avl_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):5]; + + assign avl_mem_laddr_s = (MEM_RATIO == 1) ? avl_mem_laddr : + (MEM_RATIO == 2) ? {avl_mem_laddr, 1'b0} : + (MEM_RATIO == 4) ? {avl_mem_laddr, 2'b0} : + (MEM_RATIO == 8) ? {avl_mem_laddr, 3'b0} : + (MEM_RATIO == 16) ? {avl_mem_laddr, 4'b0} : + {avl_mem_laddr, 5'b0}; + + assign avl_mem_addr_diff_s = {1'b1, avl_mem_waddr} - avl_mem_raddr_s; + + always @(posedge avl_clk) begin + if (avl_fifo_reset_s == 1'b1) begin + avl_mem_addr_diff <= 'd0; + avl_mem_raddr <= 'd0; + avl_mem_raddr_m1 <= 'd0; + avl_mem_raddr_m2 <= 'd0; + avl_mem_request_data <= 'd0; + end else begin + avl_mem_raddr_m1 <= dac_mem_raddr_g; + avl_mem_raddr_m2 <= avl_mem_raddr_m1; + avl_mem_raddr <= avl_mem_raddr_g2b_s; + avl_mem_addr_diff <= avl_mem_addr_diff_s[AVL_MEM_ADDRESS_WIDTH-1:0]; + if (avl_xfer_req_out == 1'b0) begin + avl_mem_request_data <= 1'b0; + end else if (avl_mem_addr_diff >= AVL_MEM_THRESHOLD_HI) begin + avl_mem_request_data <= 1'b0; + end else if (avl_mem_addr_diff <= AVL_MEM_THRESHOLD_LO) begin + avl_mem_request_data <= 1'b1; + end + end + end + + ad_g2b #( + .DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH) + ) i_avl_mem_rd_addr_g2b ( + .din (avl_mem_raddr_m2), + .dout (avl_mem_raddr_g2b_s)); + + // Push data from the async FIFO to the DAC + // Data flow is controlled by the DAC, no back-pressure. If FIFO is not + // ready, data will be dropped + + assign dac_mem_waddr_s = (MEM_RATIO == 1) ? dac_mem_waddr : + (MEM_RATIO == 2) ? {dac_mem_waddr, 1'b0} : + (MEM_RATIO == 4) ? {dac_mem_waddr, 2'b0} : + (MEM_RATIO == 8) ? {dac_mem_waddr, 3'b0} : + (MEM_RATIO == 16) ? {dac_mem_waddr, 4'b0} : + {dac_mem_waddr, 5'b0}; + + assign dac_mem_addr_diff_s = {1'b1, dac_mem_waddr_s} - dac_mem_raddr; + + always @(posedge dac_clk) begin + if (dac_fifo_reset_s == 1'b1) begin + dac_mem_waddr_m2 <= 0; + dac_mem_waddr_m1 <= 0; + dac_mem_waddr <= 0; + dac_mem_laddr <= 0; + dac_mem_laddr_toggle_m <= 4'b0; + end else begin + dac_mem_waddr_m1 <= avl_mem_waddr_g; + dac_mem_waddr_m2 <= dac_mem_waddr_m1; + dac_mem_waddr <= dac_mem_waddr_g2b_s; + dac_mem_laddr_toggle_m <= {dac_mem_laddr_toggle_m[2:0], avl_mem_laddr_toggle}; + dac_mem_laddr <= (dac_mem_laddr_toggle_m[2] ^ dac_mem_laddr_toggle_m[1]) ? + avl_mem_laddr_s : + dac_mem_laddr; + end + end + + // A buffer for storing the dac_mem_laddr (the address of the last avalon + // beat inside the CDC fifo) + // If the stored data sequence is smaller, it can happen that multiple + // dac_mem_laddr values exist in the same time. This buffers stores this + // values and make sure that they are feeded to the read logic in order. + + assign dac_mem_laddr_wea_s = dac_mem_laddr_toggle_m[3] ^ dac_mem_laddr_toggle_m[2]; + assign dac_mem_laddr_rea_s = ((dac_mem_raddr == dac_mem_laddr_b) && + (dac_mem_laddr_unf_s == 1'b0)) ? 1'b1 :1'b0; + + always @(posedge dac_clk) begin + if (dac_fifo_reset_s == 1'b1) begin + dac_mem_laddr_waddr <= 0; + dac_mem_laddr_raddr <= 0; + end else begin + dac_mem_laddr_waddr <= (dac_mem_laddr_wea_s == 1'b1) ? dac_mem_laddr_waddr + 1 : dac_mem_laddr_waddr; + dac_mem_laddr_raddr <= (dac_mem_laddr_rea_s == 1'b1) ? dac_mem_laddr_raddr + 1 : dac_mem_laddr_raddr; + end + end + assign dac_mem_laddr_unf_s = (dac_mem_laddr_waddr == dac_mem_laddr_raddr) ? 1'b1 : 1'b0; + + always @(posedge dac_clk) begin + if (dac_fifo_reset_s == 1'b1) begin + dac_mem_laddr_valid <= 1'b0; + end else begin + if (dac_mem_laddr_wea_s == 1'b1) + dac_mem_laddr_valid <= 1'b1; + end + end + ad_mem #( + .DATA_WIDTH (DAC_MEM_ADDRESS_WIDTH), + .ADDRESS_WIDTH (8) + ) i_mem ( + .clka (dac_clk), + .wea (dac_mem_laddr_wea_s), + .addra (dac_mem_laddr_waddr), + .dina (dac_mem_laddr), + .clkb (dac_clk), + .reb (1'b1), + .addrb (dac_mem_laddr_raddr), + .doutb (dac_mem_laddr_s)); + + ad_g2b #( + .DATA_WIDTH(AVL_MEM_ADDRESS_WIDTH) + ) i_dac_mem_wr_addr_g2b ( + .din (dac_mem_waddr_m2), + .dout (dac_mem_waddr_g2b_s)); + + always @(posedge dac_clk) begin + if (dac_reset == 1'b1) begin + dac_avl_xfer_req_m2 <= 0; + dac_avl_xfer_req_m1 <= 0; + dac_avl_xfer_req <= 0; + end else begin + dac_avl_xfer_req_m1 <= avl_xfer_req_out; + dac_avl_xfer_req_m2 <= dac_avl_xfer_req_m1; + dac_avl_xfer_req <= dac_avl_xfer_req_m2; + end + end + + always @(posedge dac_clk) begin + if (dac_reset == 1'b1) begin + dac_dma_last_beats_m2 <= 0; + dac_dma_last_beats_m1 <= 0; + dac_dma_last_beats <= 0; + end else begin + dac_dma_last_beats_m1 <= dma_last_beats; + dac_dma_last_beats_m2 <= dac_dma_last_beats_m1; + dac_dma_last_beats <= dac_dma_last_beats_m2; + end + end + + always @(posedge dac_clk) begin + if (dac_fifo_reset_s == 1'b1) begin + dac_mem_renable <= 1'b0; + dac_mem_valid <= 1'b0; + end else begin + if (dac_mem_dunf_s == 1'b1) begin + dac_mem_renable <= 1'b0; + end else if (dac_mem_addr_diff >= DAC_MEM_THRESHOLD) begin + dac_mem_renable <= 1'b1; + end + dac_mem_valid <= (dac_mem_renable) ? dac_valid : 1'b0; + end + end + + assign dac_mem_dunf_s = (dac_mem_addr_diff_s[DAC_MEM_ADDRESS_WIDTH-1:0] == {DAC_MEM_ADDRESS_WIDTH{1'b0}}) ? 1'b1 : 1'b0; + always @(posedge dac_clk) begin + if (dac_fifo_reset_s == 1'b1) begin + dac_mem_raddr <= 0; + dac_mem_raddr_g <= 0; + dac_mem_addr_diff <= 0; + dac_mem_laddr_b <= 0; + end else begin + dac_mem_laddr_b <= (!dac_mem_laddr_unf_s) ? dac_mem_laddr_s : dac_mem_laddr_b; + dac_mem_addr_diff <= dac_mem_addr_diff_s[DAC_MEM_ADDRESS_WIDTH-1:0]; + if (dac_mem_valid) begin + if ((dac_dma_last_beats != {MEM_WIDTH_DIFF{1'b1}}) && + (dac_mem_raddr == (dac_mem_laddr_b + dac_dma_last_beats)) && + (dac_mem_laddr_valid == 1'b1)) begin + dac_mem_raddr <= dac_mem_raddr + (MEM_RATIO - dac_dma_last_beats); + end else begin + dac_mem_raddr <= dac_mem_raddr + 1'b1; + end + end + dac_mem_raddr_g <= dac_mem_raddr_b2g_s; + end + end + + ad_b2g #( + .DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH) + ) i_dac_mem_rd_addr_b2g ( + .din (dac_mem_raddr), + .dout (dac_mem_raddr_b2g_s)); + + always @(posedge dac_clk) begin + if (dac_fifo_reset_s == 1'b1) begin + dac_xfer_req <= 1'b0; + dac_xfer_req_d <= 1'b0; + dac_data <= {DAC_DATA_WIDTH{1'b0}}; + end else begin + dac_xfer_req_d <= dac_mem_renable; + dac_xfer_req <= dac_xfer_req_d; + dac_data <= (dac_xfer_req_d == 1'b1) ? dac_mem_data_s : {DAC_DATA_WIDTH{1'b0}}; + end + end + + always @(posedge dac_clk) begin + if (dac_fifo_reset_s == 1'b1) begin + dac_dunf <= 1'b0; + end else begin + dac_dunf <= (dac_mem_addr_diff == 0) ? 1'b1 : 1'b0; + end + end + +endmodule diff --git a/adi_library/intel/avl_dacfifo/avl_dacfifo_wr.v b/adi_library/intel/avl_dacfifo/avl_dacfifo_wr.v new file mode 100644 index 00000000..21ec8c84 --- /dev/null +++ b/adi_library/intel/avl_dacfifo/avl_dacfifo_wr.v @@ -0,0 +1,520 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module avl_dacfifo_wr #( + + parameter AVL_DATA_WIDTH = 512, + parameter DMA_DATA_WIDTH = 64, + parameter AVL_BURST_LENGTH = 128, + parameter AVL_DDR_BASE_ADDRESS = 0, + parameter AVL_DDR_ADDRESS_LIMIT = 33554432, + parameter DMA_MEM_ADDRESS_WIDTH = 10 +) ( + input dma_clk, + input [DMA_DATA_WIDTH-1:0] dma_data, + input dma_ready, + output reg dma_ready_out, + input dma_valid, + input dma_xfer_req, + input dma_xfer_last, + + output reg [ 7:0] dma_last_beats, + + input avl_clk, + input avl_reset, + output reg [24:0] avl_address, + output reg [ 6:0] avl_burstcount, + output [63:0] avl_byteenable, + input avl_waitrequest, + output reg avl_write, + output reg [AVL_DATA_WIDTH-1:0] avl_data, + + output reg [24:0] avl_last_address, + output reg [ 6:0] avl_last_burstcount, + output reg avl_xfer_req_out, + input avl_xfer_req_in +); + + localparam MEM_RATIO = AVL_DATA_WIDTH/DMA_DATA_WIDTH; // Max supported MEM_RATIO is 16 + localparam AVL_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DMA_MEM_ADDRESS_WIDTH : + (MEM_RATIO == 2) ? (DMA_MEM_ADDRESS_WIDTH - 1) : + (MEM_RATIO == 4) ? (DMA_MEM_ADDRESS_WIDTH - 2) : + (MEM_RATIO == 8) ? (DMA_MEM_ADDRESS_WIDTH - 3) : + (MEM_RATIO == 16) ? (DMA_MEM_ADDRESS_WIDTH - 4) : + (DMA_MEM_ADDRESS_WIDTH - 5); + localparam MEM_WIDTH_DIFF = (MEM_RATIO > 16) ? 5 : + (MEM_RATIO > 8) ? 4 : + (MEM_RATIO > 4) ? 3 : + (MEM_RATIO > 2) ? 2 : + (MEM_RATIO > 1) ? 1 : 1; + + localparam DMA_BUF_THRESHOLD_HI = {(DMA_MEM_ADDRESS_WIDTH){1'b1}} - AVL_BURST_LENGTH; + + // FSM state definition + + localparam IDLE = 5'b00001; + localparam XFER_STAGING = 5'b00010; + localparam XFER_FULL_BURST = 5'b00100; + localparam XFER_PARTIAL_BURST = 5'b01000; + localparam XFER_END = 5'b10000; + + wire dma_reset; + wire dma_fifo_reset_s; + wire dma_mem_wea_s; + wire [DMA_MEM_ADDRESS_WIDTH :0] dma_mem_addr_diff_s; + wire [DMA_MEM_ADDRESS_WIDTH-1:0] dma_mem_raddr_s; + wire [DMA_MEM_ADDRESS_WIDTH-1:0] dma_mem_waddr_b2g_s; + wire [AVL_MEM_ADDRESS_WIDTH-1:0] dma_mem_raddr_g2b_s; + + wire avl_fifo_reset_s; + wire avl_write_int_s; + wire [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_raddr_b2g_s; + wire [DMA_MEM_ADDRESS_WIDTH-1:0] avl_mem_waddr_m2_g2b_s; + wire [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_addr_diff_s; + wire [AVL_MEM_ADDRESS_WIDTH:0] avl_mem_waddr_s; + wire [AVL_DATA_WIDTH-1:0] avl_data_s; + wire avl_xfer_req_lp_s; + + reg [DMA_MEM_ADDRESS_WIDTH-1:0] dma_mem_waddr; + reg [DMA_MEM_ADDRESS_WIDTH-1:0] dma_mem_waddr_g; + reg [AVL_MEM_ADDRESS_WIDTH-1:0] dma_mem_raddr_m1; + reg [AVL_MEM_ADDRESS_WIDTH-1:0] dma_mem_raddr_m2; + reg [AVL_MEM_ADDRESS_WIDTH-1:0] dma_mem_raddr; + reg [DMA_MEM_ADDRESS_WIDTH-1:0] dma_mem_addr_diff; + reg dma_xfer_req_d; + reg dma_xfer_req_lp_m1; + reg dma_xfer_req_lp_m2; + reg dma_xfer_req_lp; + reg dma_avl_xfer_req_out_m1; + reg dma_avl_xfer_req_out_m2; + reg dma_avl_xfer_req_out; + + reg [ 4:0] avl_write_state; + reg avl_write_d; + reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_raddr; + reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_raddr_g; + reg [DMA_MEM_ADDRESS_WIDTH-1:0] avl_mem_waddr; + reg [DMA_MEM_ADDRESS_WIDTH-1:0] avl_mem_waddr_m1; + reg [DMA_MEM_ADDRESS_WIDTH-1:0] avl_mem_waddr_m2; + reg [AVL_MEM_ADDRESS_WIDTH-1:0] avl_mem_addr_diff; + reg avl_dma_xfer_req; + reg avl_dma_xfer_req_m1; + reg avl_dma_xfer_req_m2; + reg [ 7:0] avl_dma_last_beats; + reg [ 7:0] avl_dma_last_beats_m1; + reg [ 7:0] avl_dma_last_beats_m2; + reg [ 3:0] avl_xfer_pburst_offset; + reg [ 7:0] avl_burst_counter; + reg avl_last_burst; + reg avl_init_burst; + reg avl_endof_burst; + reg [ 1:0] avl_mem_rvalid; + reg avl_xfer_req_lp; + + // An asymmetric memory to transfer data from DMAC interface to Avalon Memory Map + // interface + + ad_mem_asym_wr i_mem_asym ( + .mem_i_wrclock_clk (dma_clk), + .mem_i_wren_wren (dma_mem_wea_s), + .mem_i_wraddress_wraddress (dma_mem_waddr), + .mem_i_datain_datain (dma_data), + .mem_i_rdclock_clk (avl_clk), + .mem_i_rdaddress_rdaddress (avl_mem_raddr), + .mem_o_dataout_dataout (avl_data_s)); + + // the fifo reset is the dma_xfer_req + + assign dma_reset = ~dma_xfer_req_d & dma_xfer_req; + assign dma_fifo_reset_s = (~dma_xfer_req_lp & dma_xfer_req_lp_m2); + assign avl_fifo_reset_s = (avl_reset == 1'b1) || + (avl_dma_xfer_req_m2 & ~avl_dma_xfer_req); + + always @(posedge dma_clk) begin + dma_xfer_req_d <= dma_xfer_req; + end + + always @(posedge dma_clk) begin + if (dma_reset) begin + dma_xfer_req_lp_m1 <= 1'b0; + dma_xfer_req_lp_m2 <= 1'b0; + dma_xfer_req_lp <= 1'b0; + dma_avl_xfer_req_out_m1 <= 1'b0; + dma_avl_xfer_req_out_m2 <= 1'b0; + dma_avl_xfer_req_out <= 1'b0; + end else begin + dma_xfer_req_lp_m1 <= avl_xfer_req_lp; + dma_xfer_req_lp_m2 <= dma_xfer_req_lp_m1; + dma_xfer_req_lp <= dma_xfer_req_lp_m2; + dma_avl_xfer_req_out_m1 <= avl_xfer_req_out; + dma_avl_xfer_req_out_m2 <= dma_avl_xfer_req_out_m1; + dma_avl_xfer_req_out <= dma_avl_xfer_req_out_m2; + end + end + + // write address generation + + assign dma_mem_wea_s = dma_ready & dma_valid; + + always @(posedge dma_clk) begin + if ((dma_fifo_reset_s == 1'b1) || (dma_avl_xfer_req_out == 1'b1)) begin + dma_mem_waddr <= 0; + dma_mem_waddr_g <= 0; + end else begin + if (dma_mem_wea_s == 1'b1) begin + dma_mem_waddr <= dma_mem_waddr + 1'b1; + end + end + dma_mem_waddr_g <= dma_mem_waddr_b2g_s; + end + + always @(posedge dma_clk) begin + if (dma_fifo_reset_s == 1'b1) begin + dma_last_beats <= 0; + end else begin + if ((dma_xfer_last == 1'b1) && (dma_mem_wea_s == 1'b1)) begin + dma_last_beats <= dma_mem_waddr[MEM_WIDTH_DIFF-1:0]; + end + end + end + + ad_b2g #( + .DATA_WIDTH(DMA_MEM_ADDRESS_WIDTH) + ) i_dma_mem_waddr_b2g ( + .din (dma_mem_waddr), + .dout (dma_mem_waddr_b2g_s)); + + // The memory module request data until reaches the high threshold. + + assign dma_mem_addr_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s; + assign dma_mem_raddr_s = (MEM_RATIO == 1) ? {dma_mem_raddr, {0{1'b0}}} : + (MEM_RATIO == 2) ? {dma_mem_raddr, {1{1'b0}}} : + (MEM_RATIO == 4) ? {dma_mem_raddr, {2{1'b0}}} : + (MEM_RATIO == 8) ? {dma_mem_raddr, {3{1'b0}}} : + (MEM_RATIO == 16) ? {dma_mem_raddr, {4{1'b0}}} : + {dma_mem_raddr, {5{1'b0}}}; + + always @(posedge dma_clk) begin + if (dma_fifo_reset_s == 1'b1) begin + dma_mem_addr_diff <= 'b0; + dma_mem_raddr_m1 <= 'b0; + dma_mem_raddr_m2 <= 'b0; + dma_mem_raddr <= 'b0; + dma_ready_out <= 1'b0; + end else begin + dma_mem_raddr_m1 <= avl_mem_raddr_g; + dma_mem_raddr_m2 <= dma_mem_raddr_m1; + dma_mem_raddr <= dma_mem_raddr_g2b_s; + dma_mem_addr_diff <= dma_mem_addr_diff_s[DMA_MEM_ADDRESS_WIDTH-1:0]; + if (dma_xfer_req_lp == 1'b1) begin + dma_ready_out <= (dma_mem_addr_diff >= DMA_BUF_THRESHOLD_HI) ? 1'b0 : 1'b1; + end else begin + dma_ready_out <= 1'b0; + end + end + end + + ad_g2b #( + .DATA_WIDTH(AVL_MEM_ADDRESS_WIDTH) + ) i_dma_mem_rd_address_g2b ( + .din (dma_mem_raddr_m2), + .dout (dma_mem_raddr_g2b_s)); + + always @(posedge avl_clk) begin + if (avl_reset == 1'b1) begin + avl_dma_xfer_req_m1 <= 'b0; + avl_dma_xfer_req_m2 <= 'b0; + avl_dma_xfer_req <= 'b0; + end else begin + avl_dma_xfer_req_m1 <= dma_xfer_req; + avl_dma_xfer_req_m2 <= avl_dma_xfer_req_m1; + avl_dma_xfer_req <= avl_dma_xfer_req_m2; + end + end + + assign avl_xfer_req_lp_s = avl_dma_xfer_req & ~avl_xfer_req_in; + always @(posedge avl_clk) begin + if (avl_reset == 1'b1) begin + avl_xfer_req_lp <= 1'b0; + end else begin + avl_xfer_req_lp <= avl_xfer_req_lp_s; + end + end + + // FSM to generate the necessary Avalon Write transactions + + always @(posedge avl_clk) begin + if (avl_fifo_reset_s == 1'b1) begin + avl_write_state <= IDLE; + avl_last_burst <= 1'b0; + avl_init_burst <= 1'b0; + avl_endof_burst <= 1'b0; + end else begin + case (avl_write_state) + IDLE : begin + if (avl_dma_xfer_req == 1'b1) begin + avl_write_state <= XFER_STAGING; + end else begin + avl_write_state <= IDLE; + end + end + XFER_STAGING : begin + avl_endof_burst <= 1'b0; + if (avl_xfer_req_lp == 1'b1) begin + // there are enough data for one transaction + if (avl_mem_addr_diff >= AVL_BURST_LENGTH) begin + avl_write_state <= XFER_FULL_BURST; + avl_init_burst <= 1'b1; + end else begin + avl_write_state <= XFER_STAGING; + end + end else if ((avl_dma_xfer_req == 1'b0) && (avl_xfer_pburst_offset == 4'b0)) begin // DMA transfer was finished + if (avl_mem_addr_diff >= AVL_BURST_LENGTH) begin + avl_write_state <= XFER_FULL_BURST; + avl_init_burst <= 1'b1; + end else if ((avl_mem_addr_diff > 0) || + (avl_dma_last_beats[MEM_WIDTH_DIFF-1:0] != {MEM_WIDTH_DIFF{1'b1}})) begin + avl_write_state <= XFER_PARTIAL_BURST; + avl_last_burst <= 1'b1; + end else begin + avl_write_state <= XFER_END; + end + end else begin + avl_write_state <= XFER_STAGING; + end + end + // Avalon transaction with full burst length + XFER_FULL_BURST : begin + avl_init_burst <= 1'b0; + if ((avl_burst_counter < avl_burstcount) || ((avl_waitrequest) || (avl_write))) begin + avl_write_state <= XFER_FULL_BURST; + end else begin + avl_write_state <= XFER_STAGING; + avl_endof_burst <= 1'b1; + end + end + // Avalon transaction with the remaining data, burst length is less than + // the maximum supported burst length + XFER_PARTIAL_BURST : begin + avl_last_burst <= 1'b0; + if ((avl_burst_counter < avl_burstcount) || ((avl_waitrequest) || (avl_write))) begin + avl_write_state <= XFER_PARTIAL_BURST; + end else begin + avl_write_state <= XFER_END; + end + end + XFER_END : begin + avl_write_state <= IDLE; + end + default : begin + avl_write_state <= IDLE; + end + endcase + end + end + + // FSM outputs + + assign avl_write_int_s = ((avl_write_state == XFER_FULL_BURST) || + (avl_write_state == XFER_PARTIAL_BURST)) ? 1'b1 : 1'b0; + + always @(posedge avl_clk) begin + if (avl_fifo_reset_s == 1'b1) begin + avl_mem_waddr_m1 <= 'b0; + avl_mem_waddr_m2 <= 'b0; + avl_mem_waddr <= 'b0; + avl_xfer_pburst_offset <= 4'b1111; + end else begin + avl_mem_waddr_m1 <= dma_mem_waddr_g; + avl_mem_waddr_m2 <= avl_mem_waddr_m1; + avl_mem_waddr <= avl_mem_waddr_m2_g2b_s; + if ((avl_dma_xfer_req == 0) && (avl_xfer_pburst_offset > 0)) begin + avl_xfer_pburst_offset <= avl_xfer_pburst_offset - 4'b1; + end + end + end + + ad_g2b #( + .DATA_WIDTH (DMA_MEM_ADDRESS_WIDTH) + ) i_avl_mem_waddr_g2b ( + .din (avl_mem_waddr_m2), + .dout (avl_mem_waddr_m2_g2b_s)); + + // ASYNC MEM read control + + assign avl_mem_waddr_s = (MEM_RATIO == 1) ? {avl_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):0]} : + (MEM_RATIO == 2) ? {avl_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):1]} : + (MEM_RATIO == 4) ? {avl_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):2]} : + (MEM_RATIO == 8) ? {avl_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):3]} : + {avl_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):4]}; + assign avl_mem_addr_diff_s = {1'b1, avl_mem_waddr_s} - avl_mem_raddr; + + always @(posedge avl_clk) begin + if (avl_fifo_reset_s == 1'b1) begin + avl_mem_addr_diff <= 'b0; + end else begin + avl_mem_addr_diff <= avl_mem_addr_diff_s[(AVL_MEM_ADDRESS_WIDTH-1):0]; + end + end + + always @(posedge avl_clk) begin + if (avl_fifo_reset_s == 1'b1) begin + avl_mem_rvalid <= 2'b0; + avl_mem_raddr <= 'b0; + avl_mem_raddr_g <= 'b0; + end else begin + if (~avl_waitrequest && avl_write) begin + avl_mem_rvalid[0] <= 1'b1; + avl_mem_rvalid[1] <= avl_mem_rvalid[0]; + end else begin + avl_mem_rvalid <= {avl_mem_rvalid[0], 1'b0}; + end + if (~avl_waitrequest && avl_write) begin + avl_mem_raddr <= avl_mem_raddr + 1'b1; + end + if (avl_write_state == XFER_END) begin + avl_mem_raddr <= 'b0; + end + avl_mem_raddr_g <= avl_mem_raddr_b2g_s; + end + end + + ad_b2g #( + .DATA_WIDTH(AVL_MEM_ADDRESS_WIDTH) + ) i_avl_mem_rd_address_b2g ( + .din (avl_mem_raddr), + .dout (avl_mem_raddr_b2g_s)); + + // Avalon write address + + always @(posedge avl_clk) begin + if (avl_fifo_reset_s == 1'b1) begin + avl_address <= AVL_DDR_BASE_ADDRESS; + end else begin + if (avl_endof_burst == 1'b1) begin + avl_address <= (avl_address < AVL_DDR_ADDRESS_LIMIT) ? avl_address + AVL_BURST_LENGTH : AVL_DDR_BASE_ADDRESS; + end + end + end + + // Avalon write + + always @(posedge avl_clk) begin + if ((avl_fifo_reset_s == 1'b1) || (avl_write_state == XFER_END)) begin + avl_write <= 1'b0; + avl_write_d <= 1'b0; + avl_data <= 'b0; + end else begin + if (~avl_waitrequest) begin + avl_write_d <= (avl_init_burst || avl_last_burst) || + (avl_write_int_s & avl_mem_rvalid[1]); + avl_write <= avl_write_d; + avl_data <= avl_data_s; + end + end + end + + // Avalon burstcount & counter + + always @(posedge avl_clk) begin + if (avl_reset) begin + avl_burstcount <= 'b1; + avl_burst_counter <= 'b0; + end else begin + if (avl_last_burst) begin + if (avl_dma_last_beats[MEM_WIDTH_DIFF-1:0] != {MEM_WIDTH_DIFF{1'b1}}) begin + avl_burstcount <= avl_mem_addr_diff + 1; + end else begin + avl_burstcount <= avl_mem_addr_diff; + end + end else if (avl_write_state != XFER_PARTIAL_BURST) begin + avl_burstcount <= AVL_BURST_LENGTH; + end + if (avl_write_state == XFER_STAGING) begin + avl_burst_counter <= 'b0; + end else if (avl_write_d && ~avl_waitrequest) begin + avl_burst_counter <= avl_burst_counter + 1'b1; + end + end + end + + // generate avl_byteenable signal + + always @(posedge avl_clk) begin + if (avl_reset == 1'b1) begin + avl_dma_last_beats_m1 <= 8'b0; + avl_dma_last_beats_m2 <= 8'b0; + avl_dma_last_beats <= 8'b0; + end else begin + avl_dma_last_beats_m1 <= dma_last_beats; + avl_dma_last_beats_m2 <= avl_dma_last_beats_m1; + avl_dma_last_beats <= avl_dma_last_beats_m2; + end + end + + assign avl_byteenable = {64{1'b1}}; + + // save the last address and byteenable + + always @(posedge avl_clk) begin + if (avl_reset == 1'b1) begin + avl_last_address <= 0; + avl_last_burstcount <= 'b0; + end else begin + if (avl_write && ~avl_waitrequest) begin + avl_last_address <= avl_address; + avl_last_burstcount <= avl_burstcount; + end + end + end + + // avl_xfer_req generation for synchronize the access of the external + // memory + + always @(posedge avl_clk) begin + if (avl_reset == 1'b1) begin + avl_xfer_req_out <= 1'b0; + end else begin + if (avl_write_state == XFER_END) begin + avl_xfer_req_out <= 1'b1; + end else if (avl_write_state == XFER_STAGING) begin + avl_xfer_req_out <= 1'b0; + end + end + end + +endmodule diff --git a/adi_library/intel/avl_dacfifo/util_dacfifo_bypass.v b/adi_library/intel/avl_dacfifo/util_dacfifo_bypass.v new file mode 100644 index 00000000..9e01510d --- /dev/null +++ b/adi_library/intel/avl_dacfifo/util_dacfifo_bypass.v @@ -0,0 +1,275 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_dacfifo_bypass #( + + parameter DAC_DATA_WIDTH = 64, + parameter DMA_DATA_WIDTH = 64 +) ( + + // DMA FIFO interface + + input dma_clk, + input [(DMA_DATA_WIDTH-1):0] dma_data, + input dma_ready, + output reg dma_ready_out, + input dma_valid, + + // request and synchronization + + input dma_xfer_req, + + // dac fifo interface + + input dac_clk, + input dac_rst, + input dac_valid, + output reg [(DAC_DATA_WIDTH-1):0] dac_data, + output reg dac_dunf +); + + // supported ratios: 1:1 / 1:2 / 1:4 / 1:8 / 2:1 / 4:1 / 8:1 + + localparam MEM_RATIO = (DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? DMA_DATA_WIDTH/DAC_DATA_WIDTH : + DAC_DATA_WIDTH/DMA_DATA_WIDTH; + localparam DAC_ADDRESS_WIDTH = 10; + localparam DMA_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_ADDRESS_WIDTH : + (MEM_RATIO == 2) ? ((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 1) : (DAC_ADDRESS_WIDTH + 1)) : + (MEM_RATIO == 4) ? ((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 2) : (DAC_ADDRESS_WIDTH + 2)) : + ((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 3) : (DAC_ADDRESS_WIDTH + 3)); + localparam DMA_BUF_THRESHOLD_HI = {(DMA_ADDRESS_WIDTH){1'b1}} - 4; + localparam DAC_BUF_THRESHOLD_LO = 4; + + reg [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr = 'd0; + reg [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr_g = 'd0; + reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr = 'd0; + reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr_g = 'd0; + reg dac_mem_rea = 1'b0; + reg dac_mem_rea_d = 1'b0; + reg dma_rst_m1 = 1'b0; + reg dma_rst = 1'b0; + reg [DMA_ADDRESS_WIDTH-1:0] dma_mem_addr_diff = 1'b0; + reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m1 = 1'b0; + reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2 = 1'b0; + reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr = 1'b0; + reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m1 = 1'b0; + reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2 = 1'b0; + reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr = 1'b0; + reg dac_xfer_out = 1'b0; + reg dac_xfer_out_m1 = 1'b0; + + // internal signals + + wire [(DAC_ADDRESS_WIDTH):0] dac_mem_addr_diff_s; + wire [(DMA_ADDRESS_WIDTH-1):0] dma_mem_raddr_s; + wire [(DAC_ADDRESS_WIDTH-1):0] dac_mem_waddr_s; + wire dma_mem_wea_s; + wire dac_mem_rea_s; + wire [(DAC_DATA_WIDTH-1):0] dac_mem_rdata_s; + wire [DMA_ADDRESS_WIDTH:0] dma_address_diff_s; + wire dac_mem_empty_s; + + wire [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr_b2g_s; + wire [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr_b2g_s; + wire [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2_g2b_s; + wire [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2_g2b_s; + + // An asymmetric memory to transfer data from DMAC interface to DAC interface + + ad_mem_asym_bypass i_mem_asym ( + .mem_i_wrclock_clk (dma_clk), + .mem_i_wren_wren (dma_mem_wea_s), + .mem_i_wraddress_wraddress (dma_mem_waddr), + .mem_i_datain_datain (dma_data), + .mem_i_rdclock_clk (dac_clk), + .mem_i_rdaddress_rdaddress (dac_mem_raddr), + .mem_o_dataout_dataout (dac_mem_rdata_s)); + + // dma reset is brought from dac domain + + always @(posedge dma_clk) begin + dma_rst_m1 <= dac_rst; + dma_rst <= dma_rst_m1; + end + + // Write address generation for the asymmetric memory + + assign dma_mem_wea_s = dma_xfer_req & dma_valid & dma_ready; + + always @(posedge dma_clk) begin + if (dma_rst == 1'b1) begin + dma_mem_waddr <= 'h0; + dma_mem_waddr_g <= 'h0; + end else begin + if (dma_mem_wea_s == 1'b1) begin + dma_mem_waddr <= dma_mem_waddr + 1'b1; + end + dma_mem_waddr_g <= dma_mem_waddr_b2g_s; + end + end + + ad_b2g #( + .DATA_WIDTH (DMA_ADDRESS_WIDTH) + ) i_dma_mem_waddr_b2g ( + .din (dma_mem_waddr), + .dout (dma_mem_waddr_b2g_s)); + + // The memory module request data until reaches the high threshold. + + always @(posedge dma_clk) begin + if (dma_rst == 1'b1) begin + dma_mem_addr_diff <= 'b0; + dma_mem_raddr_m1 <= 'b0; + dma_mem_raddr_m2 <= 'b0; + dma_mem_raddr <= 'b0; + dma_ready_out <= 1'b0; + end else begin + dma_mem_raddr_m1 <= dac_mem_raddr_g; + dma_mem_raddr_m2 <= dma_mem_raddr_m1; + dma_mem_raddr <= dma_mem_raddr_m2_g2b_s; + dma_mem_addr_diff <= dma_address_diff_s[DMA_ADDRESS_WIDTH-1:0]; + if (dma_mem_addr_diff >= DMA_BUF_THRESHOLD_HI) begin + dma_ready_out <= 1'b0; + end else begin + dma_ready_out <= 1'b1; + end + end + end + + ad_g2b #( + .DATA_WIDTH (DAC_ADDRESS_WIDTH) + ) i_dma_mem_raddr_g2b ( + .din (dma_mem_raddr_m2), + .dout (dma_mem_raddr_m2_g2b_s)); + + // relative address offset on dma domain + assign dma_address_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s; + assign dma_mem_raddr_s = (DMA_DATA_WIDTH>DAC_DATA_WIDTH) ? + ((MEM_RATIO == 1) ? (dma_mem_raddr) : + (MEM_RATIO == 2) ? (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):1]) : + (MEM_RATIO == 4) ? (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):2]) : (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):3])) : + ((MEM_RATIO == 1) ? (dma_mem_raddr) : + (MEM_RATIO == 2) ? ({dma_mem_raddr, 1'b0}) : + (MEM_RATIO == 4) ? ({dma_mem_raddr, 2'b0}) : ({dma_mem_raddr, 3'b0})); + + // relative address offset on dac domain + assign dac_address_diff_s = {1'b1, dac_mem_waddr_s} - dac_mem_raddr; + assign dac_mem_waddr_s = (DAC_DATA_WIDTH>DMA_DATA_WIDTH) ? + ((MEM_RATIO == 1) ? (dac_mem_waddr) : + (MEM_RATIO == 2) ? (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):1]) : + (MEM_RATIO == 4) ? (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):2]) : (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):3])) : + ((MEM_RATIO == 1) ? (dac_mem_waddr) : + (MEM_RATIO == 2) ? ({dac_mem_waddr, 1'b0}) : + (MEM_RATIO == 4) ? ({dac_mem_waddr, 2'b0}) : ({dac_mem_waddr, 3'b0})); + + // Read address generation for the asymmetric memory + + assign dac_mem_empty_s = (dac_mem_waddr_s == dac_mem_raddr) ? 1'b1 : 1'b0; + assign dac_mem_rea_s = dac_valid & !dac_mem_empty_s; + + always @(posedge dac_clk) begin + if (dac_rst == 1'b1) begin + dac_mem_raddr <= 'h0; + dac_mem_raddr_g <= 'h0; + end else begin + if (dac_mem_rea_s == 1'b1) begin + dac_mem_raddr <= dac_mem_raddr + 1'b1; + end + dac_mem_raddr_g <= dac_mem_raddr_b2g_s; + end + end + + // compensate the read latency of the memory + always @(posedge dac_clk) begin + dac_mem_rea_d <= dac_mem_rea_s; + dac_mem_rea <= dac_mem_rea_d; + end + + ad_b2g #( + .DATA_WIDTH (DAC_ADDRESS_WIDTH) + ) i_dac_mem_raddr_b2g ( + .din (dac_mem_raddr), + .dout (dac_mem_raddr_b2g_s)); + + // transfer the write address into the DAC's clock domain + + always @(posedge dac_clk) begin + if (dac_rst == 1'b1) begin + dac_mem_waddr_m1 <= 'b0; + dac_mem_waddr_m2 <= 'b0; + dac_mem_waddr <= 'b0; + end else begin + dac_mem_waddr_m1 <= dma_mem_waddr_g; + dac_mem_waddr_m2 <= dac_mem_waddr_m1; + dac_mem_waddr <= dac_mem_waddr_m2_g2b_s; + end + end + + ad_g2b #( + .DATA_WIDTH (DMA_ADDRESS_WIDTH) + ) i_dac_mem_waddr_g2b ( + .din (dac_mem_waddr_m2), + .dout (dac_mem_waddr_m2_g2b_s)); + + // define underflow + + always @(posedge dac_clk) begin + if (dac_rst == 1'b1) begin + dac_xfer_out_m1 <= 1'b0; + dac_xfer_out <= 1'b0; + dac_dunf <= 1'b0; + end else begin + dac_xfer_out_m1 <= dma_xfer_req; + dac_xfer_out <= dac_xfer_out_m1; + if (dac_valid == 1'b1) begin + dac_dunf <= dac_mem_empty_s; + end + end + end + + // DAC data output logic - make sure that the data output is zero between + // transfers + + always @(posedge dac_clk) begin + if (dac_dunf == 1'b1) begin + dac_data <= 0; + end else begin + dac_data <= dac_mem_rdata_s; + end + end + +endmodule diff --git a/adi_library/intel/axi_adxcvr/.timestamp_intel b/adi_library/intel/axi_adxcvr/.timestamp_intel new file mode 100644 index 00000000..e69de29b diff --git a/adi_library/intel/axi_adxcvr/Makefile b/adi_library/intel/axi_adxcvr/Makefile new file mode 100644 index 00000000..358df5a0 --- /dev/null +++ b/adi_library/intel/axi_adxcvr/Makefile @@ -0,0 +1,14 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_adxcvr + +INTEL_DEPS += ../../common/up_axi.v +INTEL_DEPS += axi_adxcvr.v +INTEL_DEPS += axi_adxcvr_hw.tcl +INTEL_DEPS += axi_adxcvr_up.v + +include ../../scripts/library.mk diff --git a/adi_library/intel/axi_adxcvr/axi_adxcvr.v b/adi_library/intel/axi_adxcvr/axi_adxcvr.v new file mode 100644 index 00000000..cb54ffa3 --- /dev/null +++ b/adi_library/intel/axi_adxcvr/axi_adxcvr.v @@ -0,0 +1,158 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module axi_adxcvr #( + + // parameters + + parameter integer ID = 0, + parameter [ 7:0] FPGA_TECHNOLOGY = 0, + parameter [ 7:0] FPGA_FAMILY = 0, + parameter [ 7:0] SPEED_GRADE = 0, + parameter [ 7:0] DEV_PACKAGE = 0, + parameter [15:0] FPGA_VOLTAGE = 0, + parameter integer XCVR_TYPE = 0, + parameter integer TX_OR_RX_N = 0, + parameter integer NUM_OF_LANES = 4 +) ( + + // xcvr, lane-pll and ref-pll are shared + + output up_rst, + input up_pll_locked, + input [(NUM_OF_LANES-1):0] up_ready, + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [11:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [11:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready +); + + // internal signals + + wire up_rstn; + wire up_clk; + wire up_wreq; + wire [ 9:0] up_waddr; + wire [31:0] up_wdata; + wire up_wack; + wire up_rreq; + wire [ 9:0] up_raddr; + wire [31:0] up_rdata; + wire up_rack; + + // clk & rst + + assign up_rstn = s_axi_aresetn; + assign up_clk = s_axi_aclk; + + // instantiations + + axi_adxcvr_up #( + .ID (ID), + .XCVR_TYPE (XCVR_TYPE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .FPGA_VOLTAGE (FPGA_VOLTAGE), + .TX_OR_RX_N (TX_OR_RX_N), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_up ( + .up_rst (up_rst), + .up_pll_locked (up_pll_locked), + .up_ready (up_ready), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + + up_axi #( + .AXI_ADDRESS_WIDTH (12) + ) i_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/intel/axi_adxcvr/axi_adxcvr_hw.tcl b/adi_library/intel/axi_adxcvr/axi_adxcvr_hw.tcl new file mode 100644 index 00000000..64e352a5 --- /dev/null +++ b/adi_library/intel/axi_adxcvr/axi_adxcvr_hw.tcl @@ -0,0 +1,83 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +package require quartus::device + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl + +set_module_property NAME axi_adxcvr +set_module_property DESCRIPTION "AXI ADXCVR Core" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME axi_adxcvr +set_module_property ELABORATION_CALLBACK p_axi_adxcvr +set_module_property VALIDATION_CALLBACK info_param_validate + +# files + +ad_ip_files axi_adxcvr [list \ + $ad_hdl_dir/library/common/up_axi.v \ + axi_adxcvr_up.v \ + axi_adxcvr.v \ +] + +# parameters + +add_parameter ID INTEGER 0 +set_parameter_property ID DISPLAY_NAME ID +set_parameter_property ID UNITS None +set_parameter_property ID HDL_PARAMETER true + +add_parameter TX_OR_RX_N INTEGER 0 +set_parameter_property TX_OR_RX_N DISPLAY_NAME TX_OR_RX_N +set_parameter_property TX_OR_RX_N UNITS None +set_parameter_property TX_OR_RX_N HDL_PARAMETER true + +add_parameter NUM_OF_LANES INTEGER 4 +set_parameter_property NUM_OF_LANES DISPLAY_NAME NUM_OF_LANES +set_parameter_property NUM_OF_LANES UNITS None +set_parameter_property NUM_OF_LANES HDL_PARAMETER true + +adi_add_auto_fpga_spec_params + +adi_add_device_spec_param XCVR_TYPE +adi_add_device_spec_param FPGA_VOLTAGE +set_parameter_property FPGA_VOLTAGE DISPLAY_UNITS mV +set_parameter_property FPGA_VOLTAGE_MANUAL DISPLAY_UNITS mV +adi_add_indep_spec_params_overwrite XCVR_TYPE +adi_add_indep_spec_params_overwrite FPGA_VOLTAGE + +# axi4 slave interface + +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12 + +# xcvr interface + +ad_interface reset up_rst output 1 s_axi_clock +set_interface_property if_up_rst associatedResetSinks s_axi_reset + +add_interface core_pll_locked conduit end +add_interface_port core_pll_locked up_pll_locked pll_locked Input 1 + +# name changes + +proc p_axi_adxcvr {} { + + set m_tx_or_rx_n [get_parameter_value TX_OR_RX_N] + set m_num_of_lanes [get_parameter_value NUM_OF_LANES] + + if {$m_tx_or_rx_n == 1} { + add_interface ready conduit end + add_interface_port ready up_ready tx_ready input $m_num_of_lanes + } + + if {$m_tx_or_rx_n == 0} { + add_interface ready conduit end + add_interface_port ready up_ready rx_ready input $m_num_of_lanes + } +} + diff --git a/adi_library/intel/axi_adxcvr/axi_adxcvr_up.v b/adi_library/intel/axi_adxcvr/axi_adxcvr_up.v new file mode 100644 index 00000000..366e7136 --- /dev/null +++ b/adi_library/intel/axi_adxcvr/axi_adxcvr_up.v @@ -0,0 +1,190 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adxcvr_up #( + + // parameters + + parameter integer ID = 0, + parameter [ 7:0] FPGA_TECHNOLOGY = 0, + parameter [ 7:0] FPGA_FAMILY = 0, + parameter [ 7:0] SPEED_GRADE = 0, + parameter [ 7:0] DEV_PACKAGE = 0, + parameter [15:0] FPGA_VOLTAGE = 0, + parameter integer XCVR_TYPE = 0, + parameter integer TX_OR_RX_N = 0, + parameter integer NUM_OF_LANES = 4 +) ( + + // xcvr, lane-pll and ref-pll are shared + + output up_rst, + input up_pll_locked, + input [(NUM_OF_LANES-1):0] up_ready, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [ 9:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [ 9:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // parameters + + localparam [31:0] VERSION = 32'h00110161; + + // internal registers + + reg up_wreq_d = 'd0; + reg [31:0] up_scratch = 'd0; + reg up_resetn = 'd0; + reg [ 3:0] up_rst_cnt = 'd8; + reg up_status_int = 'd0; + reg up_rreq_d = 'd0; + reg [31:0] up_rdata_d = 'd0; + + // internal signals + + wire up_ready_s; + wire [31:0] up_status_32_s; + wire [31:0] up_rparam_s; + + // defaults + + assign up_wack = up_wreq_d; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wreq_d <= 'd0; + up_scratch <= 'd0; + end else begin + up_wreq_d <= up_wreq; + if ((up_wreq == 1'b1) && (up_waddr == 10'h002)) begin + up_scratch <= up_wdata; + end + end + end + + // reset-controller + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_resetn <= 'd0; + end else begin + if ((up_wreq == 1'b1) && (up_waddr == 10'h004)) begin + up_resetn <= up_wdata[0]; + end + end + end + + assign up_rst = up_rst_cnt[3]; + assign up_ready_s = & up_status_32_s[NUM_OF_LANES:1]; + assign up_status_32_s[31:(NUM_OF_LANES+1)] = 'd0; + assign up_status_32_s[NUM_OF_LANES] = up_pll_locked; + assign up_status_32_s[(NUM_OF_LANES-1):0] = up_ready; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rst_cnt <= 4'h8; + up_status_int <= 1'b0; + end else begin + if (up_resetn == 1'b0) begin + up_rst_cnt <= 4'h8; + end else if (up_rst_cnt[3] == 1'b1) begin + up_rst_cnt <= up_rst_cnt + 1'b1; + end + if (up_resetn == 1'b0) begin + up_status_int <= 1'b0; + end else if (up_ready_s == 1'b1) begin + up_status_int <= 1'b1; + end + end + end + + // Specific to Intel + + assign up_rparam_s[31:28] = 8'd0; + assign up_rparam_s[27:24] = XCVR_TYPE[3:0]; + + // Specific to Xilinx + + assign up_rparam_s[23:16] = 8'd0; + + // generic + + assign up_rparam_s[15: 9] = 7'd0; + assign up_rparam_s[ 8: 8] = (TX_OR_RX_N == 0) ? 1'b0 : 1'b1; + assign up_rparam_s[ 7: 0] = NUM_OF_LANES[7:0]; + + // read interface + + assign up_rack = up_rreq_d; + assign up_rdata = up_rdata_d; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rreq_d <= 'd0; + up_rdata_d <= 'd0; + end else begin + up_rreq_d <= up_rreq; + if (up_rreq == 1'b1) begin + case (up_raddr) + 10'h000: up_rdata_d <= VERSION; + 10'h001: up_rdata_d <= ID; + 10'h002: up_rdata_d <= up_scratch; + 10'h004: up_rdata_d <= {31'd0, up_resetn}; + 10'h005: up_rdata_d <= {31'd0, up_status_int}; + 10'h006: up_rdata_d <= up_status_32_s; + 10'h007: up_rdata_d <= {FPGA_TECHNOLOGY,FPGA_FAMILY,SPEED_GRADE,DEV_PACKAGE}; // [8,8,8,8] + 10'h009: up_rdata_d <= up_rparam_s; + 10'h050: up_rdata_d <= {16'd0, FPGA_VOLTAGE}; // mV + default: up_rdata_d <= 32'd0; + endcase + end else begin + up_rdata_d <= 32'd0; + end + end + end + +endmodule diff --git a/adi_library/intel/common/ad_dcfilter.v b/adi_library/intel/common/ad_dcfilter.v new file mode 100644 index 00000000..c135f35b --- /dev/null +++ b/adi_library/intel/common/ad_dcfilter.v @@ -0,0 +1,84 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// dc filter- y(n) = c*x(n) + (1-c)*y(n-1) +// NOT IMPLEMENTED + +`timescale 1ps/1ps + +module ad_dcfilter #( + + // data path disable + + parameter DISABLE = 0 +) ( + + // data interface + + input clk, + input valid, + input [15:0] data, + output reg valid_out, + output reg [15:0] data_out, + + // control interface + + input dcfilt_enb, + input [15:0] dcfilt_coeff, + input [15:0] dcfilt_offset +); + + // internal registers + + reg valid_d = 'd0; + reg [15:0] data_d = 'd0; + reg valid_2d = 'd0; + reg [15:0] data_2d = 'd0; + + // internal signals + + wire [47:0] dc_offset_s; + + always @(posedge clk) begin + valid_d <= valid; + if (valid == 1'b1) begin + data_d <= data + dcfilt_offset; + end + valid_2d <= valid_d; + data_2d <= data_d; + valid_out <= valid_2d; + data_out <= data_2d; + end + +endmodule diff --git a/adi_library/intel/common/ad_mul.v b/adi_library/intel/common/ad_mul.v new file mode 100644 index 00000000..7359ec90 --- /dev/null +++ b/adi_library/intel/common/ad_mul.v @@ -0,0 +1,88 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ps/1ps + +module ad_mul #( + + parameter A_DATA_WIDTH = 17, + parameter B_DATA_WIDTH = 17, + parameter DELAY_DATA_WIDTH = 16 +) ( + + // data_p = data_a * data_b; + + input clk, + input [ A_DATA_WIDTH-1:0] data_a, + input [ B_DATA_WIDTH-1:0] data_b, + output [A_DATA_WIDTH + B_DATA_WIDTH-1:0] data_p, + + // delay interface + + input [(DELAY_DATA_WIDTH-1):0] ddata_in, + output reg [(DELAY_DATA_WIDTH-1):0] ddata_out +); + + // internal registers + + reg [(DELAY_DATA_WIDTH-1):0] p1_ddata = 'd0; + reg [(DELAY_DATA_WIDTH-1):0] p2_ddata = 'd0; + + // a/b reg, m-reg, p-reg delay match + + always @(posedge clk) begin + p1_ddata <= ddata_in; + p2_ddata <= p1_ddata; + ddata_out <= p2_ddata; + end + + lpm_mult #( + .lpm_type ("lpm_mult"), + .lpm_widtha (A_DATA_WIDTH), + .lpm_widthb (B_DATA_WIDTH), + .lpm_widthp (A_DATA_WIDTH + B_DATA_WIDTH), + .lpm_representation ("SIGNED"), + .lpm_pipeline (3)) + i_lpm_mult ( + .clken (1'b1), + .aclr (1'b0), + .sclr (1'b0), + .sum (1'b0), + .clock (clk), + .dataa (data_a), + .datab (data_b), + .result (data_p)); + +endmodule diff --git a/adi_library/intel/common/intel_mem_asym/.timestamp_intel b/adi_library/intel/common/intel_mem_asym/.timestamp_intel new file mode 100644 index 00000000..e69de29b diff --git a/adi_library/intel/common/intel_mem_asym/Makefile b/adi_library/intel/common/intel_mem_asym/Makefile new file mode 100644 index 00000000..6ff13107 --- /dev/null +++ b/adi_library/intel/common/intel_mem_asym/Makefile @@ -0,0 +1,11 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := intel_mem_asym + +INTEL_DEPS += intel_mem_asym_hw.tcl + +include ../../../scripts/library.mk diff --git a/adi_library/intel/common/intel_mem_asym/intel_mem_asym_hw.tcl b/adi_library/intel/common/intel_mem_asym/intel_mem_asym_hw.tcl new file mode 100644 index 00000000..b9d270fa --- /dev/null +++ b/adi_library/intel/common/intel_mem_asym/intel_mem_asym_hw.tcl @@ -0,0 +1,64 @@ +############################################################################### +## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 + +source ../../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl + +ad_ip_create intel_mem_asym {Intel Asymmetric Memory} +set_module_property COMPOSITION_CALLBACK p_intel_mem_asym + +# parameters + +ad_ip_parameter DEVICE_FAMILY STRING {Arria 10} +ad_ip_parameter A_ADDRESS_WIDTH INTEGER 8 +ad_ip_parameter A_DATA_WIDTH INTEGER 512 +ad_ip_parameter B_ADDRESS_WIDTH INTEGER 8 +ad_ip_parameter B_DATA_WIDTH INTEGER 64 + +# compose + +proc p_intel_mem_asym {} { + + set m_addr_width_a [get_parameter_value "A_ADDRESS_WIDTH"] + set m_data_width_a [get_parameter_value "A_DATA_WIDTH"] + set m_addr_width_b [get_parameter_value "B_ADDRESS_WIDTH"] + set m_data_width_b [get_parameter_value "B_DATA_WIDTH"] + + set m_size [expr ((2**$m_addr_width_a)*$m_data_width_a)] + if {$m_addr_width_a == 0} { + set m_size [expr ((2**$m_addr_width_b)*$m_data_width_b)] + } + + add_instance intel_mem ram_2port + set_instance_parameter_value intel_mem {GUI_MODE} 0 + set_instance_parameter_value intel_mem {GUI_MEM_IN_BITS} 1 + set_instance_parameter_value intel_mem {GUI_MEMSIZE_BITS} $m_size + set_instance_parameter_value intel_mem {GUI_VAR_WIDTH} 1 + set_instance_parameter_value intel_mem {GUI_QA_WIDTH} $m_data_width_a + set_instance_parameter_value intel_mem {GUI_DATAA_WIDTH} $m_data_width_a + set_instance_parameter_value intel_mem {GUI_QB_WIDTH} $m_data_width_b + set_instance_parameter_value intel_mem {GUI_READ_OUTPUT_QB} {false} + set_instance_parameter_value intel_mem {GUI_RAM_BLOCK_TYPE} {M20K} + set_instance_parameter_value intel_mem {GUI_CLOCK_TYPE} 1 + + add_interface mem_i_wrclock clock end + add_interface mem_i_wren conduit end + add_interface mem_i_wraddress conduit end + add_interface mem_i_datain conduit end + add_interface mem_i_rdclock clock end + add_interface mem_i_rdaddress conduit end + add_interface mem_o_dataout conduit end + + set_interface_property mem_i_wrclock EXPORT_OF intel_mem.wrclock + set_interface_property mem_i_wren EXPORT_OF intel_mem.wren + set_interface_property mem_i_wraddress EXPORT_OF intel_mem.wraddress + set_interface_property mem_i_datain EXPORT_OF intel_mem.data + set_interface_property mem_i_rdclock EXPORT_OF intel_mem.rdclock + set_interface_property mem_i_rdaddress EXPORT_OF intel_mem.rdaddress + set_interface_property mem_o_dataout EXPORT_OF intel_mem.q +} + diff --git a/adi_library/intel/common/intel_serdes/.timestamp_intel b/adi_library/intel/common/intel_serdes/.timestamp_intel new file mode 100644 index 00000000..e69de29b diff --git a/adi_library/intel/common/intel_serdes/Makefile b/adi_library/intel/common/intel_serdes/Makefile new file mode 100644 index 00000000..0acde883 --- /dev/null +++ b/adi_library/intel/common/intel_serdes/Makefile @@ -0,0 +1,11 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := intel_serdes + +INTEL_DEPS += intel_serdes_hw.tcl + +include ../../../scripts/library.mk diff --git a/adi_library/intel/common/intel_serdes/intel_serdes_hw.tcl b/adi_library/intel/common/intel_serdes/intel_serdes_hw.tcl new file mode 100644 index 00000000..ab491c14 --- /dev/null +++ b/adi_library/intel/common/intel_serdes/intel_serdes_hw.tcl @@ -0,0 +1,142 @@ +############################################################################### +## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 + +source ../../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl + +ad_ip_create intel_serdes {Intel SERDES} +set_module_property COMPOSITION_CALLBACK p_intel_serdes + +# parameters + +ad_ip_parameter DEVICE_FAMILY STRING {Arria 10} +ad_ip_parameter MODE STRING "CLK" false +ad_ip_parameter DDR_OR_SDR_N INTEGER 1 false +ad_ip_parameter SERDES_FACTOR INTEGER 8 false +ad_ip_parameter CLKIN_FREQUENCY FLOAT 500.0 false + +set_parameter_property MODE ALLOWED_RANGES {"CLK" "IN" "IN_NODPA" "OUT"} +set_parameter_property DDR_OR_SDR_N ALLOWED_RANGES {0 1} +set_parameter_property SERDES_FACTOR ALLOWED_RANGES {4 8} +set_parameter_property CLKIN_FREQUENCY DISPLAY_UNITS "MHz" + +proc p_intel_serdes {} { + + set m_mode [get_parameter_value "MODE"] + set m_ddr_or_sdr_n [get_parameter_value "DDR_OR_SDR_N"] + set m_serdes_factor [get_parameter_value "SERDES_FACTOR"] + set m_clkin_frequency [get_parameter_value "CLKIN_FREQUENCY"] + + set m_hs_data_rate [expr ($m_clkin_frequency * ($m_ddr_or_sdr_n + 1))] + set m_ls_data_rate [expr ($m_hs_data_rate/$m_serdes_factor)] + + set m_ls_phase 22.5 + set m_ld_phase 315.0 + set m_ld_duty_cycle 12.5 + + if {$m_serdes_factor == 4} { + set m_ls_phase 45 + set m_ld_phase 270.0 + set m_ld_duty_cycle 25.0 + } + + ## arria 10 only + + if {$m_mode == "CLK"} { + add_instance intel_serdes_pll altera_iopll 19.1 + set_instance_parameter_value intel_serdes_pll {gui_reference_clock_frequency} $m_clkin_frequency + set_instance_parameter_value intel_serdes_pll {gui_use_locked} {1} + set_instance_parameter_value intel_serdes_pll {gui_operation_mode} {lvds} + set_instance_parameter_value intel_serdes_pll {gui_number_of_clocks} {3} + set_instance_parameter_value intel_serdes_pll {gui_en_lvds_ports} {Enable LVDS_CLK/LOADEN 0} + set_instance_parameter_value intel_serdes_pll {gui_en_phout_ports} {true} + set_instance_parameter_value intel_serdes_pll {gui_output_clock_frequency0} $m_hs_data_rate + set_instance_parameter_value intel_serdes_pll {gui_ps_units0} {degrees} + set_instance_parameter_value intel_serdes_pll {gui_phase_shift_deg0} {180.0} + set_instance_parameter_value intel_serdes_pll {gui_output_clock_frequency1} $m_ls_data_rate + set_instance_parameter_value intel_serdes_pll {gui_ps_units1} {degrees} + set_instance_parameter_value intel_serdes_pll {gui_phase_shift_deg1} $m_ld_phase + set_instance_parameter_value intel_serdes_pll {gui_duty_cycle1} $m_ld_duty_cycle + set_instance_parameter_value intel_serdes_pll {gui_output_clock_frequency2} $m_ls_data_rate + set_instance_parameter_value intel_serdes_pll {gui_phase_shift_deg2} $m_ls_phase + set_instance_parameter_value intel_serdes_pll {gui_ps_units2} {degrees} + add_interface rst reset sink + set_interface_property rst EXPORT_OF intel_serdes_pll.reset + add_interface ref_clk clock sink + set_interface_property ref_clk EXPORT_OF intel_serdes_pll.refclk + add_interface locked conduit end + set_interface_property locked EXPORT_OF intel_serdes_pll.locked + add_interface hs_phase conduit end + set_interface_property hs_phase EXPORT_OF intel_serdes_pll.phout + add_interface hs_clk conduit end + set_interface_property hs_clk EXPORT_OF intel_serdes_pll.lvds_clk + add_interface loaden conduit end + set_interface_property loaden EXPORT_OF intel_serdes_pll.loaden + add_interface ls_clk clock source + set_interface_property ls_clk EXPORT_OF intel_serdes_pll.outclk2 + return + } + + if {$m_mode == "IN" || $m_mode == "IN_NODPA"} { + add_instance intel_serdes_in altera_lvds 19.1 + if {$m_mode == "IN"} { + set_instance_parameter_value intel_serdes_in {MODE} {RX_DPA-FIFO} + } else { + set_instance_parameter_value intel_serdes_in {MODE} {RX_Non-DPA} + } + set_instance_parameter_value intel_serdes_in {NUM_CHANNELS} {1} + set_instance_parameter_value intel_serdes_in {DATA_RATE} $m_hs_data_rate + set_instance_parameter_value intel_serdes_in {J_FACTOR} $m_serdes_factor + set_instance_parameter_value intel_serdes_in {USE_EXTERNAL_PLL} {true} + set_instance_parameter_value intel_serdes_in {INCLOCK_FREQUENCY} $m_clkin_frequency + set_instance_parameter_value intel_serdes_in {PLL_USE_RESET} {false} + add_interface data_in conduit end + set_interface_property data_in EXPORT_OF intel_serdes_in.rx_in + add_interface clk conduit end + set_interface_property clk EXPORT_OF intel_serdes_in.ext_fclk + add_interface loaden conduit end + set_interface_property loaden EXPORT_OF intel_serdes_in.ext_loaden + add_interface div_clk conduit end + set_interface_property div_clk EXPORT_OF intel_serdes_in.ext_coreclock + if {$m_mode == "IN"} { + add_interface hs_phase conduit end + set_interface_property hs_phase EXPORT_OF intel_serdes_in.ext_vcoph + add_interface locked conduit end + set_interface_property locked EXPORT_OF intel_serdes_in.ext_pll_locked + add_interface delay_locked conduit end + set_interface_property delay_locked EXPORT_OF intel_serdes_in.rx_dpa_locked + } + add_interface data_s conduit end + set_interface_property data_s EXPORT_OF intel_serdes_in.rx_out + return + } + + if {$m_mode == "OUT"} { + add_instance intel_serdes_out altera_lvds 19.1 + set_instance_parameter_value intel_serdes_out {MODE} {TX} + set_instance_parameter_value intel_serdes_out {NUM_CHANNELS} {1} + set_instance_parameter_value intel_serdes_out {DATA_RATE} $m_hs_data_rate + set_instance_parameter_value intel_serdes_out {J_FACTOR} $m_serdes_factor + set_instance_parameter_value intel_serdes_out {TX_EXPORT_CORECLOCK} {false} + set_instance_parameter_value intel_serdes_out {TX_USE_OUTCLOCK} {false} + set_instance_parameter_value intel_serdes_out {USE_EXTERNAL_PLL} {true} + set_instance_parameter_value intel_serdes_out {INCLOCK_FREQUENCY} $m_clkin_frequency + set_instance_parameter_value intel_serdes_out {PLL_USE_RESET} {false} + add_interface data_out conduit end + set_interface_property data_out EXPORT_OF intel_serdes_out.tx_out + add_interface clk conduit end + set_interface_property clk EXPORT_OF intel_serdes_out.ext_fclk + add_interface loaden conduit end + set_interface_property loaden EXPORT_OF intel_serdes_out.ext_loaden + add_interface div_clk conduit end + set_interface_property div_clk EXPORT_OF intel_serdes_out.ext_coreclock + add_interface data_s conduit end + set_interface_property data_s EXPORT_OF intel_serdes_out.tx_in + return + } +} + diff --git a/adi_library/intel/common/up_clock_mon_constr.sdc b/adi_library/intel/common/up_clock_mon_constr.sdc new file mode 100644 index 00000000..2b566667 --- /dev/null +++ b/adi_library/intel/common/up_clock_mon_constr.sdc @@ -0,0 +1,8 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_false_path -from [get_registers *up_clock_mon:*|d_count_run_m3*] -to [get_registers *up_clock_mon:*|up_count_running_m1*] +set_false_path -from [get_registers *up_clock_mon:*|up_count_run*] -to [get_registers *up_clock_mon:*|d_count_run_m1*] +set_false_path -from [get_registers *up_clock_mon:*|d_count*] -to [get_registers *up_clock_mon:*|up_d_count*] diff --git a/adi_library/intel/common/up_rst_constr.sdc b/adi_library/intel/common/up_rst_constr.sdc new file mode 100644 index 00000000..f8102529 --- /dev/null +++ b/adi_library/intel/common/up_rst_constr.sdc @@ -0,0 +1,8 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_false_path -to [get_pins -hierarchical -nocase rst_async_d*|CLRN] +set_false_path -to [get_pins -hierarchical -nocase rst_sync|CLRN] + diff --git a/adi_library/intel/common/up_xfer_cntrl_constr.sdc b/adi_library/intel/common/up_xfer_cntrl_constr.sdc new file mode 100644 index 00000000..af786b0f --- /dev/null +++ b/adi_library/intel/common/up_xfer_cntrl_constr.sdc @@ -0,0 +1,8 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_cntrl|d_xfer_toggle*] -to [get_registers *up_xfer_cntrl:i_xfer_cntrl|up_xfer_state_m1*] +set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_cntrl|up_xfer_toggle*] -to [get_registers *up_xfer_cntrl:i_xfer_cntrl|d_xfer_toggle_m1*] +set_false_path -from [get_registers *up_xfer_cntrl:i_xfer_cntrl|up_xfer_data*] -to [get_registers *up_xfer_cntrl:i_xfer_cntrl|d_data_cntrl*] diff --git a/adi_library/intel/common/up_xfer_status_constr.sdc b/adi_library/intel/common/up_xfer_status_constr.sdc new file mode 100644 index 00000000..b48e615a --- /dev/null +++ b/adi_library/intel/common/up_xfer_status_constr.sdc @@ -0,0 +1,8 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_false_path -from [get_registers *up_xfer_status:i_xfer_status|up_xfer_toggle*] -to [get_registers *up_xfer_status:i_xfer_status|d_xfer_state_m1*] +set_false_path -from [get_registers *up_xfer_status:i_xfer_status|d_xfer_toggle*] -to [get_registers *up_xfer_status:i_xfer_status|up_xfer_toggle_m1*] +set_false_path -from [get_registers *up_xfer_status:i_xfer_status|d_xfer_data*] -to [get_registers *up_xfer_status:i_xfer_status|up_data_status*] diff --git a/adi_library/intel/jesd204_phy/.timestamp_intel b/adi_library/intel/jesd204_phy/.timestamp_intel new file mode 100644 index 00000000..e69de29b diff --git a/adi_library/intel/jesd204_phy/Makefile b/adi_library/intel/jesd204_phy/Makefile new file mode 100644 index 00000000..6e0ea83c --- /dev/null +++ b/adi_library/intel/jesd204_phy/Makefile @@ -0,0 +1,16 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := jesd204_phy + +INTEL_DEPS += jesd204_phy_glue.v +INTEL_DEPS += jesd204_phy_glue_hw.tcl +INTEL_DEPS += jesd204_phy_hw.tcl + +INTEL_LIB_DEPS += jesd204/jesd204_soft_pcs_rx +INTEL_LIB_DEPS += jesd204/jesd204_soft_pcs_tx + +include ../../scripts/library.mk diff --git a/adi_library/intel/jesd204_phy/jesd204_phy_glue.v b/adi_library/intel/jesd204_phy/jesd204_phy_glue.v new file mode 100644 index 00000000..28e2244b --- /dev/null +++ b/adi_library/intel/jesd204_phy/jesd204_phy_glue.v @@ -0,0 +1,56 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_phy_glue #( + parameter WIDTH = 20, + parameter CONST_WIDTH = 1, + parameter NUM_OF_LANES = 1, + parameter LANE_INVERT = 0 +) ( + input [WIDTH-1:0] in, + output [WIDTH-1:0] out, + output [CONST_WIDTH-1:0] const_out, + output [NUM_OF_LANES-1:0] polinv +); + +/* There really should be a standard component in Qsys that allows to do this */ + + assign out = in; + assign const_out = {CONST_WIDTH{1'b0}}; + assign polinv = LANE_INVERT[NUM_OF_LANES-1:0]; + +endmodule diff --git a/adi_library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl b/adi_library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl new file mode 100644 index 00000000..268a2630 --- /dev/null +++ b/adi_library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl @@ -0,0 +1,306 @@ +############################################################################### +## Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +package require qsys 14.0 +source ../../../scripts/adi_env.tcl +source ../../scripts/adi_ip_intel.tcl + +# +# For whatever strange reason all the interface of the native PHY become +# conduits when it is instantiated in a compose callback. This glue logic module +# converts the interfaces to their proper type. +# + +ad_ip_create jesd204_phy_glue {Native PHY to JESD204 glue logic} \ + jesd204_phy_glue_elab +set_module_property INTERNAL true + +# files + +ad_ip_files jesd204_phy_glue [list \ + jesd204_phy_glue.v \ +] + +# parameters + +ad_ip_parameter DEVICE STRING "" false +ad_ip_parameter TX_OR_RX_N BOOLEAN false false +ad_ip_parameter SOFT_PCS BOOLEAN false false +ad_ip_parameter BONDING_CLOCKS_EN BOOLEAN false false +ad_ip_parameter NUM_OF_LANES POSITIVE 4 true +ad_ip_parameter LANE_INVERT INTEGER 0 true +ad_ip_parameter WIDTH NATURAL 20 true { \ + DERIVED true \ +} +ad_ip_parameter CONST_WIDTH NATURAL 1 true { \ + DERIVED true \ +} + +proc glue_add_if {num name type dir {bcast false}} { + if {$bcast} { + add_interface ${name} $type $dir + } else { + for {set i 0} {$i < $num} {incr i} { + add_interface ${name}_${i} $type $dir + } + } + add_interface phy_${name} conduit end +} + +proc glue_add_if_port {num ifname port role dir width {bcast false}} { + variable sig_offset + + set phy_width [expr $num * $width] + if {$dir == "Input"} { + set sig "in" + set phy_dir "Output" + set phy_sig "out" + } else { + set sig "out" + set phy_dir "Input" + set phy_sig "in" + } + + if {$bcast} { + add_interface_port ${ifname} ${port} $role $dir $width + set_port_property ${port} fragment_list \ + [format "%s(%d:%d)" $sig [expr $sig_offset + $width - 1] $sig_offset] + } else { + for {set i 0} {$i < $num} {incr i} { + set base [expr $sig_offset + $width * $i] + + add_interface_port ${ifname}_${i} ${port}_${i} $role $dir $width + set_port_property ${port}_${i} fragment_list \ + [format "%s(%d:%d)" $sig [expr $base + $width - 1] $base] + } + } + + add_interface_port phy_${ifname} phy_${port} $role $phy_dir $phy_width + + if {$bcast} { + set _frag [format "%s(%d:%d)" $phy_sig [expr $sig_offset + $width - 1] $sig_offset] + set sig_offset [expr $sig_offset + $width] + set frag "${_frag}" + for {set i 1} {$i < $num} {incr i} { + set frag [concat ${frag} ${_frag}] + } + } else { + set frag [format "%s(%d:%d)" $phy_sig [expr $sig_offset + $phy_width - 1] $sig_offset] + set sig_offset [expr $sig_offset + $phy_width] + } + + set_port_property phy_${port} fragment_list $frag +} + +proc glue_add_tx_serial_clk {num_of_lanes} { + variable sig_offset + + # The serial clock is special. The first 6 transceivers use the x1 connection + # since they are in the same bank as the PLL. The others have to use the xN + # connection through the CGB. + + if {$num_of_lanes > 6} { + set clk0_width 6 + set clk1_width [expr $num_of_lanes - 6] + + } else { + set clk0_width $num_of_lanes + set clk1_width 0 + } + + add_interface tx_serial_clk_x1 hssi_serial_clock sink + add_interface_port tx_serial_clk_x1 tx_serial_clk_x1 clk Input 1 + set_port_property tx_serial_clk_x1 fragment_list \ + [format "in(%d:%d)" $sig_offset $sig_offset] + + add_interface phy_tx_serial_clk0 conduit end + add_interface_port phy_tx_serial_clk0 phy_tx_serial_clk0 clk Output $num_of_lanes + + set _frag [format "out(%d:%d)" $sig_offset $sig_offset] + set sig_offset [expr $sig_offset + 1] + set frag "${_frag}" + for {set i 1} {$i < $clk0_width} {incr i} { + set frag [concat ${_frag} ${frag}] + } + + if {$num_of_lanes > 6} { + add_interface tx_serial_clk_xN hssi_serial_clock sink + add_interface_port tx_serial_clk_xN tx_serial_clk_xN clk Input 1 + set_port_property tx_serial_clk_xN fragment_list \ + [format "in(%d:%d)" $sig_offset $sig_offset] + + set _frag [format "out(%d:%d)" $sig_offset $sig_offset] + set sig_offset [expr $sig_offset + 1] + for {set i 0} {$i < $clk1_width} {incr i} { + set frag [concat ${_frag} ${frag}] + } + } + + set_port_property phy_tx_serial_clk0 fragment_list $frag +} + +proc glue_add_if_port_conduit {num ifname port phy_port dir width} { + variable sig_offset + + set phy_width [expr $num * $width] + if {$dir == "Input"} { + set sig "in" + set phy_dir "Output" + set phy_sig "out" + } else { + set sig "out" + set phy_dir "Input" + set phy_sig "in" + } + + for {set i 0} {$i < $num} {incr i} { + set base [expr $sig_offset + $width * $i] + + add_interface_port ${ifname}_${i} ${ifname}_${port}_${i} $port $dir $width + set_port_property ${ifname}_${port}_${i} fragment_list \ + [format "%s(%d:%d)" $sig [expr $base + $width - 1] $base] + } + + add_interface phy_${phy_port} conduit end + add_interface_port phy_${phy_port} phy_${phy_port} $phy_port $phy_dir $phy_width + + set_port_property phy_${phy_port} fragment_list \ + [format "%s(%d:%d)" $phy_sig [expr $sig_offset + $phy_width - 1] $sig_offset] + + set sig_offset [expr $sig_offset + $phy_width] +} + +proc glue_add_const_conduit {port width} { + variable const_offset + + set ifname phy_${port} + add_interface $ifname conduit end + add_interface_port $ifname $ifname $port Output $width + set_port_property $ifname fragment_list [format "const_out(%d:%d)" \ + [expr $const_offset + $width - 1] $const_offset] + + set const_offset [expr $const_offset + $width] +} + +proc jesd204_phy_glue_elab {} { + variable sig_offset + variable const_offset + + set device [get_parameter DEVICE] + set soft_pcs [get_parameter SOFT_PCS] + set num_of_lanes [get_parameter NUM_OF_LANES] + set bonding_clocks_en [get_parameter BONDING_CLOCKS_EN] + + set sig_offset 0 + set const_offset 0 + + if {[string equal $device "Arria 10"]} { + set reconfig_avmm_address_width 10 + set unused_width_per_lane 88 + } elseif {[string equal $device "Stratix 10"]} { + set reconfig_avmm_address_width 11 + set unused_width_per_lane 40 + } else { + send_message error "Only Arria 10 and Stratix 10 are supported." + } + + glue_add_if $num_of_lanes reconfig_clk clock sink true + glue_add_if_port $num_of_lanes reconfig_clk reconfig_clk clk Input 1 true + + glue_add_if $num_of_lanes reconfig_reset reset sink true + glue_add_if_port $num_of_lanes reconfig_reset reconfig_reset reset Input 1 true + + glue_add_if $num_of_lanes reconfig_avmm avalon sink + for {set i 0} {$i < $num_of_lanes} {incr i} { + set_interface_property reconfig_avmm_${i} associatedClock reconfig_clk + set_interface_property reconfig_avmm_${i} associatedReset reconfig_reset + } + glue_add_if_port $num_of_lanes reconfig_avmm reconfig_address address Input $reconfig_avmm_address_width + glue_add_if_port $num_of_lanes reconfig_avmm reconfig_read read Input 1 + glue_add_if_port $num_of_lanes reconfig_avmm reconfig_readdata readdata Output 32 + glue_add_if_port $num_of_lanes reconfig_avmm reconfig_waitrequest waitrequest Output 1 + glue_add_if_port $num_of_lanes reconfig_avmm reconfig_write write Input 1 + glue_add_if_port $num_of_lanes reconfig_avmm reconfig_writedata writedata Input 32 + + if {[get_parameter TX_OR_RX_N]} { + glue_add_if $num_of_lanes tx_clkout clock source + glue_add_if_port $num_of_lanes tx_clkout tx_clkout clk Output 1 + + glue_add_if $num_of_lanes tx_coreclkin clock sink true + glue_add_if_port $num_of_lanes tx_coreclkin tx_coreclkin clk Input 1 true + + if {$bonding_clocks_en && $num_of_lanes > 6} { + glue_add_if $num_of_lanes tx_bonding_clocks hssi_bonded_clock sink true + glue_add_if_port $num_of_lanes tx_bonding_clocks tx_bonding_clocks clk Input 6 true + } else { + glue_add_tx_serial_clk $num_of_lanes + } + + if {$soft_pcs} { + set unused_width [expr $num_of_lanes * $unused_width_per_lane] + + glue_add_const_conduit tx_enh_data_valid $num_of_lanes + + for {set i 0} {$i < $num_of_lanes} {incr i} { + add_interface tx_raw_data_${i} conduit start + } + glue_add_if_port_conduit $num_of_lanes tx_raw_data raw_data tx_parallel_data Input 40 + } else { + set unused_width [expr $num_of_lanes * 92] + + for {set i 0} {$i < $num_of_lanes} {incr i} { + add_interface tx_phy_${i} conduit start + } + glue_add_if_port_conduit $num_of_lanes tx_phy char tx_parallel_data Input 32 + glue_add_if_port_conduit $num_of_lanes tx_phy charisk tx_datak Input 4 + } + + glue_add_const_conduit unused_tx_parallel_data $unused_width + + add_interface phy_tx_polinv conduit end + add_interface_port phy_tx_polinv polinv tx_polinv Output $num_of_lanes + set_port_property polinv TERMINATION $soft_pcs + } else { + glue_add_if 1 rx_cdr_refclk0 clock sink true + glue_add_if_port 1 rx_cdr_refclk0 rx_cdr_refclk0 clk Input 1 true + + glue_add_if $num_of_lanes rx_coreclkin clock sink true + glue_add_if_port $num_of_lanes rx_coreclkin rx_coreclkin clk Input 1 true + + glue_add_if $num_of_lanes rx_clkout clock source + glue_add_if_port $num_of_lanes rx_clkout rx_clkout clk Output 1 + + if {$soft_pcs} { + for {set i 0} {$i < $num_of_lanes} {incr i} { + add_interface rx_raw_data_${i} conduit start + } + glue_add_if_port_conduit $num_of_lanes rx_raw_data raw_data rx_parallel_data Output 40 + } else { + for {set i 0} {$i < $num_of_lanes} {incr i} { + add_interface rx_phy_${i} conduit start + } + glue_add_if_port_conduit $num_of_lanes rx_phy char rx_parallel_data Output 32 + glue_add_if_port_conduit $num_of_lanes rx_phy charisk rx_datak Output 4 + glue_add_if_port_conduit $num_of_lanes rx_phy disperr rx_disperr Output 4 + glue_add_if_port_conduit $num_of_lanes rx_phy notintable rx_errdetect Output 4 + glue_add_if_port_conduit $num_of_lanes rx_phy patternalign_en rx_std_wa_patternalign Input 1 + } + + add_interface const_out conduit end + add_interface_port const_out const_out const_out Output 1 + set_port_property const_out TERMINATION true + set const_offset 1 + + add_interface phy_rx_polinv conduit end + add_interface_port phy_rx_polinv polinv rx_polinv Output $num_of_lanes + set_port_property polinv TERMINATION $soft_pcs + } + + set_interface_property reconfig_reset associatedClock reconfig_clk + set_interface_property reconfig_reset synchronousEdges DEASSERT + + set_parameter_value WIDTH $sig_offset + set_parameter_value CONST_WIDTH $const_offset +} diff --git a/adi_library/intel/jesd204_phy/jesd204_phy_hw.tcl b/adi_library/intel/jesd204_phy/jesd204_phy_hw.tcl new file mode 100644 index 00000000..b4c37e6a --- /dev/null +++ b/adi_library/intel/jesd204_phy/jesd204_phy_hw.tcl @@ -0,0 +1,266 @@ +############################################################################### +## Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +package require qsys 14.0 + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl + +# +# Instantiates the Arria 10 native PHY and configures it for JESD204 operation. +# The datapath width is configured for 4 octets per beat. +# +# Optionally a soft-logic PCS is instantiated, this can be used if the lane rate +# is too high for the hard-logic PCS. +# + +ad_ip_create jesd204_phy "ADI JESD204 PHY" +set_module_property COMPOSITION_CALLBACK jesd204_phy_composition_callback +set_module_property INTERNAL false + +# parameters + +ad_ip_parameter DEVICE STRING "Stratix 10" false +ad_ip_parameter ID NATURAL 0 false +ad_ip_parameter SOFT_PCS BOOLEAN false false +ad_ip_parameter TX_OR_RX_N BOOLEAN false false +ad_ip_parameter LANE_RATE FLOAT 10000 false +ad_ip_parameter REFCLK_FREQUENCY FLOAT 500.0 false +ad_ip_parameter NUM_OF_LANES POSITIVE 4 false +ad_ip_parameter REGISTER_INPUTS INTEGER 0 false +ad_ip_parameter LANE_INVERT INTEGER 0 false +ad_ip_parameter BONDING_CLOCKS_EN BOOLEAN false false + +proc jesd204_phy_composition_callback {} { + + set device [get_parameter_value "DEVICE"] + set soft_pcs [get_parameter_value "SOFT_PCS"] + set tx [get_parameter_value "TX_OR_RX_N"] + set lane_rate [get_parameter_value "LANE_RATE"] + set refclk_frequency [get_parameter_value "REFCLK_FREQUENCY"] + set id [get_parameter_value "ID"] + set num_of_lanes [get_parameter_value "NUM_OF_LANES"] + set register_inputs [get_parameter_value "REGISTER_INPUTS"] + set lane_invert [get_parameter_value "LANE_INVERT"] + set bonding_clocks_en [get_parameter_value "BONDING_CLOCKS_EN"] + + set link_clk_frequency [expr $lane_rate / 40] + + if {[string equal $device "Arria 10"]} { + set device_type 1 + } elseif {[string equal $device "Stratix 10"]} { + set device_type 2 + } else { + set device_type 0 + } + + add_instance link_clock clock_source + set_instance_parameter_value link_clock {clockFrequency} [expr $link_clk_frequency*1000000] + add_interface link_clk clock sink + set_interface_property link_clk EXPORT_OF link_clock.clk_in + add_interface link_reset reset sink + set_interface_property link_reset EXPORT_OF link_clock.clk_in_reset + + ## Arria10 + if {$device_type == 1} { + add_instance native_phy altera_xcvr_native_a10 + set_instance_parameter_value native_phy {enh_txfifo_mode} "Phase compensation" + set_instance_parameter_value native_phy {enh_rxfifo_mode} "Phase compensation" + set_instance_property native_phy SUPPRESS_ALL_WARNINGS true + set_instance_property native_phy SUPPRESS_ALL_INFO_MESSAGES true + ## Stratix 10 + } elseif {$device_type == 2} { + add_instance native_phy altera_xcvr_native_s10_htile + set_instance_parameter_value native_phy {tx_fifo_mode} "Phase compensation" + set_instance_parameter_value native_phy {rx_fifo_mode} "Phase compensation" + ## Unsupported device + } else { + send_message error "Only Arria 10 and Stratix 10 are supported." + } + + if {$soft_pcs} { + set_instance_parameter_value native_phy {protocol_mode} "basic_enh" + } else { + set_instance_parameter_value native_phy {protocol_mode} "basic_std" + set_instance_parameter_value native_phy {std_pcs_pma_width} 20 + + if {$tx} { + set_instance_parameter_value native_phy {std_tx_byte_ser_mode} "Serialize x2" + set_instance_parameter_value native_phy {std_tx_8b10b_enable} 1 + set_instance_parameter_value native_phy {std_tx_polinv_enable} 1 + set_instance_parameter_value native_phy {enable_port_tx_polinv} 1 + } else { + set_instance_parameter_value native_phy {std_rx_byte_deser_mode} "Deserialize x2" + set_instance_parameter_value native_phy {std_rx_8b10b_enable} 1 + set_instance_parameter_value native_phy {std_rx_word_aligner_mode} "manual (PLD controlled)" + set_instance_parameter_value native_phy {std_rx_word_aligner_pattern_len} 20 + set_instance_parameter_value native_phy {std_rx_word_aligner_pattern} 0xA0D7C + set_instance_parameter_value native_phy {enable_port_rx_std_wa_patternalign} 1 + set_instance_parameter_value native_phy {std_rx_polinv_enable} 1 + set_instance_parameter_value native_phy {enable_port_rx_polinv} 1 + } + } + + if {$tx} { + set_instance_parameter_value native_phy {duplex_mode} "tx" + if {$bonding_clocks_en && $num_of_lanes > 6} { + set_instance_parameter_value native_phy {bonded_mode} "pma_only" + } else { + set_instance_parameter_value native_phy {bonded_mode} "not_bonded" + } + set_instance_parameter_value native_phy {enable_port_tx_pma_elecidle} 0 + } else { + set_instance_parameter_value native_phy {duplex_mode} "rx" + set_instance_parameter_value native_phy {set_cdr_refclk_freq} $refclk_frequency + set_instance_parameter_value native_phy {enable_port_rx_is_lockedtodata} 1 + set_instance_parameter_value native_phy {enable_port_rx_is_lockedtoref} 0 + set_instance_parameter_value native_phy {enable_ports_rx_manual_cdr_mode} 0 + } + + set_instance_parameter_value native_phy {channels} $num_of_lanes + set_instance_parameter_value native_phy {set_data_rate} $lane_rate + set_instance_parameter_value native_phy {enable_simple_interface} 1 + set_instance_parameter_value native_phy {enh_pcs_pma_width} 40 + set_instance_parameter_value native_phy {enh_pld_pcs_width} 40 + set_instance_parameter_value native_phy {rcfg_enable} 1 + set_instance_parameter_value native_phy {rcfg_shared} 0 + set_instance_parameter_value native_phy {rcfg_jtag_enable} 0 + set_instance_parameter_value native_phy {rcfg_sv_file_enable} 0 + set_instance_parameter_value native_phy {rcfg_h_file_enable} 0 + set_instance_parameter_value native_phy {rcfg_mif_file_enable} 0 + set_instance_parameter_value native_phy {set_user_identifier} $id + set_instance_parameter_value native_phy {set_capability_reg_enable} 1 + set_instance_parameter_value native_phy {set_csr_soft_logic_enable} 1 + set_instance_parameter_value native_phy {set_prbs_soft_logic_enable} 0 + + add_instance phy_glue jesd204_phy_glue + set_instance_parameter_value phy_glue DEVICE $device + set_instance_parameter_value phy_glue TX_OR_RX_N $tx + set_instance_parameter_value phy_glue SOFT_PCS $soft_pcs + set_instance_parameter_value phy_glue NUM_OF_LANES $num_of_lanes + set_instance_parameter_value phy_glue LANE_INVERT $lane_invert + set_instance_parameter_value phy_glue BONDING_CLOCKS_EN $bonding_clocks_en + + add_interface reconfig_clk clock sink + set_interface_property reconfig_clk EXPORT_OF phy_glue.reconfig_clk + + add_interface reconfig_reset reset sink + set_interface_property reconfig_reset EXPORT_OF phy_glue.reconfig_reset + + + if {$tx} { + if {$bonding_clocks_en && $num_of_lanes > 6} { + add_interface bonding_clocks hssi_bonded_clock end + set_interface_property bonding_clocks EXPORT_OF phy_glue.tx_bonding_clocks + add_connection phy_glue.phy_tx_bonding_clocks native_phy.tx_bonding_clocks + } else { + add_interface serial_clk_x1 hssi_serial_clock end + set_interface_property serial_clk_x1 EXPORT_OF phy_glue.tx_serial_clk_x1 + if {$num_of_lanes > 6} { + add_interface serial_clk_xN hssi_serial_clock end + set_interface_property serial_clk_xN EXPORT_OF phy_glue.tx_serial_clk_xN + } + add_connection phy_glue.phy_tx_serial_clk0 native_phy.tx_serial_clk0 + } + + add_connection link_clock.clk phy_glue.tx_coreclkin + + if { $soft_pcs == true && $device_type == 1 } { + add_connection phy_glue.phy_tx_enh_data_valid native_phy.tx_enh_data_valid + } + + foreach x {reconfig_clk reconfig_reset reconfig_avmm tx_coreclkin \ + tx_clkout tx_parallel_data unused_tx_parallel_data} { + add_connection phy_glue.phy_${x} native_phy.${x} + } + + foreach x {serial_data analogreset digitalreset cal_busy} { + add_interface ${x} conduit end + set_interface_property ${x} EXPORT_OF native_phy.tx_${x} + } + + if {$soft_pcs == false} { + add_connection phy_glue.phy_tx_datak native_phy.tx_datak + add_connection phy_glue.phy_tx_polinv native_phy.tx_polinv + } + + ## Startix 10 + if {$device_type == 2} { + foreach x {analogreset_stat digitalreset_stat} { + add_interface ${x} conduit end + set_interface_property ${x} EXPORT_OF native_phy.tx_${x} + } + } + + } else { + + add_interface ref_clk clock sink + set_interface_property ref_clk EXPORT_OF phy_glue.rx_cdr_refclk0 + + add_connection link_clock.clk phy_glue.rx_coreclkin + + foreach x {serial_data analogreset digitalreset cal_busy is_lockedtodata} { + add_interface ${x} conduit end + set_interface_property ${x} EXPORT_OF native_phy.rx_${x} + } + + foreach x {reconfig_clk reconfig_reset reconfig_avmm rx_coreclkin \ + rx_clkout rx_parallel_data rx_cdr_refclk0} { + add_connection phy_glue.phy_${x} native_phy.${x} + } + + if {$soft_pcs == false} { + foreach x {rx_datak rx_disperr rx_errdetect rx_std_wa_patternalign} { + add_connection phy_glue.phy_${x} native_phy.${x} + } + add_connection phy_glue.phy_rx_polinv native_phy.rx_polinv + } + + ## Startix 10 + if {$device_type == 2} { + foreach x {analogreset_stat digitalreset_stat} { + add_interface ${x} conduit end + set_interface_property ${x} EXPORT_OF native_phy.rx_${x} + } + } + + } + + for {set i 0} {$i < $num_of_lanes} {incr i} { + add_interface reconfig_avmm_${i} avalon slave + set_interface_property reconfig_avmm_${i} EXPORT_OF phy_glue.reconfig_avmm_${i} + + add_interface phy_${i} conduit start + + if {$tx} { + if {$soft_pcs} { + add_instance soft_pcs_${i} jesd204_soft_pcs_tx + set_instance_parameter_value soft_pcs_${i} INVERT_OUTPUTS \ + [expr ($lane_invert >> $i) & 1] + add_connection link_clock.clk soft_pcs_${i}.clock + add_connection link_clock.clk_reset soft_pcs_${i}.reset + add_connection soft_pcs_${i}.tx_raw_data phy_glue.tx_raw_data_${i} + + set_interface_property phy_${i} EXPORT_OF soft_pcs_${i}.tx_phy + } else { + set_interface_property phy_${i} EXPORT_OF phy_glue.tx_phy_${i} + } + } else { + if {$soft_pcs} { + add_instance soft_pcs_${i} jesd204_soft_pcs_rx + set_instance_parameter_value soft_pcs_${i} REGISTER_INPUTS $register_inputs + set_instance_parameter_value soft_pcs_${i} INVERT_INPUTS \ + [expr ($lane_invert >> $i) & 1] + add_connection link_clock.clk soft_pcs_${i}.clock + add_connection link_clock.clk_reset soft_pcs_${i}.reset + add_connection phy_glue.rx_raw_data_${i} soft_pcs_${i}.rx_raw_data + + set_interface_property phy_${i} EXPORT_OF soft_pcs_${i}.rx_phy + } else { + set_interface_property phy_${i} EXPORT_OF phy_glue.rx_phy_${i} + } + } + } +} diff --git a/adi_library/intel/util_clkdiv/.timestamp_intel b/adi_library/intel/util_clkdiv/.timestamp_intel new file mode 100644 index 00000000..e69de29b diff --git a/adi_library/intel/util_clkdiv/Makefile b/adi_library/intel/util_clkdiv/Makefile new file mode 100644 index 00000000..68a60ae1 --- /dev/null +++ b/adi_library/intel/util_clkdiv/Makefile @@ -0,0 +1,12 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_clkdiv + +INTEL_DEPS += util_clkdiv.v +INTEL_DEPS += util_clkdiv_hw.tcl + +include ../../scripts/library.mk diff --git a/adi_library/intel/util_clkdiv/util_clkdiv.v b/adi_library/intel/util_clkdiv/util_clkdiv.v new file mode 100644 index 00000000..2c6836a9 --- /dev/null +++ b/adi_library/intel/util_clkdiv/util_clkdiv.v @@ -0,0 +1,79 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +// Divides the input clock to SEL_0_DIV if clk_sel is 0 or SEL_1_DIV if +// clk_sel is 1. Provides a glitch free output clock +// IP uses BUFR/BUFGCE_DIV and BUFGMUX_CTRL primitives + +module util_clkdiv #( + parameter SIM_DEVICE = "CYCLONE5", + parameter CLOCK_TYPE = "Global Clock" +) ( + input clk, + input reset, + output clk_out, + output reset_out +); + + reg enable; + reg reset_d1; + + assign reset_out = reset | reset_d1; + + always @(posedge clk) begin + reset_d1 <= reset; + end + + always @(posedge clk) begin + enable <= ~enable; + end + + generate if (SIM_DEVICE == "CYCLONE5") begin + cyclonev_clkena #( + .clock_type ("Global Clock"), + .ena_register_mode ("falling edge"), + .lpm_type ("cyclonev_clkena") + ) clock_divider_by_2 ( + .ena(enable), + .enaout(), + .inclk(clk), + // .clkselect (2'b0), + .outclk(clk_out)); + + end endgenerate + +endmodule diff --git a/adi_library/intel/util_clkdiv/util_clkdiv_hw.tcl b/adi_library/intel/util_clkdiv/util_clkdiv_hw.tcl new file mode 100644 index 00000000..1db3cf31 --- /dev/null +++ b/adi_library/intel/util_clkdiv/util_clkdiv_hw.tcl @@ -0,0 +1,29 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require -exact qsys 13.0 +source ../../../scripts/adi_env.tcl +source ../../scripts/adi_ip_intel.tcl + + +set_module_property NAME util_clkdiv +set_module_property DESCRIPTION "Clock Division Utility" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME util_clkdiv + +# files + +add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" +set_fileset_property quartus_synth TOP_LEVEL util_clkdiv +add_fileset_file util_clkdiv.v VERILOG PATH util_clkdiv.v TOP_LEVEL_FILE + +# defaults + +ad_interface clock clk input 1 +ad_interface reset reset input 1 if_clk +ad_interface clock clk_out output 1 +ad_interface reset reset_out output 1 if_clk_out + diff --git a/adi_library/interfaces/Makefile b/adi_library/interfaces/Makefile new file mode 100644 index 00000000..7952cae9 --- /dev/null +++ b/adi_library/interfaces/Makefile @@ -0,0 +1,53 @@ +#################################################################################### +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +include ../../quiet.mk + +M_DEPS := interfaces_ip.tcl +M_DEPS += ../../scripts/adi_env.tcl +M_DEPS += ../scripts/adi_ip_xilinx.tcl + +M_VIVADO := vivado -mode batch -source + +M_FLIST := *.log +M_FLIST += *.jou +M_FLIST += if_xcvr_cm.xml +M_FLIST += if_xcvr_cm_rtl.xml +M_FLIST += if_xcvr_ch.xml +M_FLIST += if_xcvr_ch_rtl.xml +M_FLIST += if_gt_qpll.xml +M_FLIST += if_gt_qpll_rtl.xml +M_FLIST += if_gt_pll.xml +M_FLIST += if_gt_pll_rtl.xml +M_FLIST += if_gt_rx.xml +M_FLIST += if_gt_rx_rtl.xml +M_FLIST += if_gt_tx.xml +M_FLIST += if_gt_tx_rtl.xml +M_FLIST += if_gt_rx_ksig.xml +M_FLIST += if_gt_rx_ksig_rtl.xml + + +.PHONY: all xilinx clean clean-all +all: xilinx +xilinx: if_xcvr_cm.xml if_xcvr_cm_rtl.xml if_xcvr_ch.xml if_xcvr_ch_rtl.xml if_gt_qpll.xml if_gt_qpll_rtl.xml if_gt_pll.xml if_gt_pll_rtl.xml if_gt_rx.xml if_gt_rx_rtl.xml if_gt_tx.xml if_gt_tx_rtl.xml if_gt_rx_ksig.xml if_gt_rx_ksig_rtl.xml + +clean:clean-all + +clean-all: + $(call clean, \ + $(M_FLIST), \ + interface definitions) + +%.xml: $(M_DEPS) + $(call build, \ + $(M_VIVADO) interfaces_ip.tcl, \ + interfaces_ip.log, \ + interface definitions) + +#################################################################################### +#################################################################################### diff --git a/adi_library/interfaces/fifo_rd.xml b/adi_library/interfaces/fifo_rd.xml new file mode 100644 index 00000000..66d44bdb --- /dev/null +++ b/adi_library/interfaces/fifo_rd.xml @@ -0,0 +1,13 @@ + + + analog.com + interface + fifo_rd + 1.0 + false + false + + 1 + 1 + FIFO Read Interface + diff --git a/adi_library/interfaces/fifo_rd_rtl.xml b/adi_library/interfaces/fifo_rd_rtl.xml new file mode 100644 index 00000000..ec5505e2 --- /dev/null +++ b/adi_library/interfaces/fifo_rd_rtl.xml @@ -0,0 +1,75 @@ + + + analog.com + interface + fifo_rd_rtl + 1.0 + + + + DATA + FIFO Read Data + + + true + + + required + in + + + required + out + + 0 + + + + EN + FIFO Read Enable + + + required + 1 + out + + + required + 1 + in + + 0 + + + + UNDERFLOW + + + 1 + in + + + 1 + + + + + VALID + + + 1 + in + + + + + XFER_REQ + + + 1 + in + + + + + diff --git a/adi_library/interfaces/fifo_wr.xml b/adi_library/interfaces/fifo_wr.xml new file mode 100644 index 00000000..8e1f4d78 --- /dev/null +++ b/adi_library/interfaces/fifo_wr.xml @@ -0,0 +1,13 @@ + + + analog.com + interface + fifo_wr + 1.0 + false + false + + 1 + 1 + FIFO Write Interface + diff --git a/adi_library/interfaces/fifo_wr_rtl.xml b/adi_library/interfaces/fifo_wr_rtl.xml new file mode 100644 index 00000000..49509dbf --- /dev/null +++ b/adi_library/interfaces/fifo_wr_rtl.xml @@ -0,0 +1,88 @@ + + + analog.com + interface + fifo_wr_rtl + 1.0 + + + + DATA + + + + true + + + required + out + + + required + in + + 0 + + + + EN + + + + required + 1 + out + + + required + 1 + in + + 0 + + + + OVERFLOW + + + + optional + 1 + in + + + optional + 1 + out + + 0 + + + + SYNC + + + + optional + 1 + out + + + optional + 1 + in + + 0 + + + + XFER_REQ + + + 1 + in + + + + + diff --git a/adi_library/interfaces/if_do_ctrl.xml b/adi_library/interfaces/if_do_ctrl.xml new file mode 100644 index 00000000..091b1230 --- /dev/null +++ b/adi_library/interfaces/if_do_ctrl.xml @@ -0,0 +1,11 @@ + + + analog.com + interface + if_do_ctrl + 1.0 + false + false + 1 + 1 + diff --git a/adi_library/interfaces/if_do_ctrl_rtl.xml b/adi_library/interfaces/if_do_ctrl_rtl.xml new file mode 100644 index 00000000..b843264b --- /dev/null +++ b/adi_library/interfaces/if_do_ctrl_rtl.xml @@ -0,0 +1,118 @@ + + + analog.com + interface + if_do_ctrl_rtl + 1.0 + + + + request_enable + + + required + 1 + + + required + 1 + in + + + + + request_valid + + + required + 1 + + + required + 1 + in + + + + + request_ready + + + required + 1 + in + + + required + 1 + + + + + request_length + + + required + + + required + in + + + + + response_measured_length + + + required + + + required + in + + + + + response_eot + + + required + 1 + in + + + required + 1 + + + + + status_underflow + + + required + 1 + in + + + required + 1 + + + + + status_overflow + + + required + 1 + in + + + required + 1 + + + + + diff --git a/adi_library/interfaces/if_do_ctrl_v1_0.sv b/adi_library/interfaces/if_do_ctrl_v1_0.sv new file mode 100644 index 00000000..187dcb0b --- /dev/null +++ b/adi_library/interfaces/if_do_ctrl_v1_0.sv @@ -0,0 +1,96 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +`ifndef if_do_ctrl_v1_0 +`define if_do_ctrl_v1_0 + +package parameter_structs; + + typedef struct packed { + bit portEnabled; + integer portWidth; + }portConfig; + + typedef struct packed { + // = {, } + portConfig request_length; + portConfig response_measured_length; + }if_do_ctrl_v1_0_port_configuration; + + parameter if_do_ctrl_v1_0_port_configuration if_do_ctrl_v1_0_default_port_configuration = '{request_length:'{1, -1}, response_measured_length:'{1, -1}}; + +endpackage + +interface if_do_ctrl_v1_0 #(parameter_structs::if_do_ctrl_v1_0_port_configuration port_configuration)(); + logic request_enable; // + logic request_valid; // + logic request_ready; // + logic [port_configuration.request_length.portWidth-1:0] request_length; // + logic [port_configuration.response_measured_length.portWidth-1:0] response_measured_length; // + logic response_eot; // + logic status_underflow; // + logic status_overflow; // + + modport MASTER ( + input request_ready, response_eot, status_underflow, status_overflow, + output request_enable, request_valid, request_length, response_measured_length + ); + + modport SLAVE ( + input request_enable, request_valid, request_length, response_measured_length, + output request_ready, response_eot, status_underflow, status_overflow + ); + + modport MONITOR ( + input request_enable, request_valid, request_ready, request_length, response_measured_length, response_eot, status_underflow, status_overflow + ); + +endinterface // if_do_ctrl_v1_0 + +`endif \ No newline at end of file diff --git a/adi_library/interfaces/if_gt_pll.xml b/adi_library/interfaces/if_gt_pll.xml new file mode 100644 index 00000000..06aa6099 --- /dev/null +++ b/adi_library/interfaces/if_gt_pll.xml @@ -0,0 +1,11 @@ + + + analog.com + interface + if_gt_pll + 1.0 + false + false + 1 + 1 + diff --git a/adi_library/interfaces/if_gt_pll_rtl.xml b/adi_library/interfaces/if_gt_pll_rtl.xml new file mode 100644 index 00000000..5b9bf106 --- /dev/null +++ b/adi_library/interfaces/if_gt_pll_rtl.xml @@ -0,0 +1,44 @@ + + + analog.com + interface + if_gt_pll_rtl + 1.0 + + + + cpll_rst_m + + + true + + + required + 1 + + + required + 1 + in + + + + + cpll_ref_clk_in + + + true + + + required + 1 + + + required + 1 + in + + + + + diff --git a/adi_library/interfaces/if_gt_pll_v1_0.sv b/adi_library/interfaces/if_gt_pll_v1_0.sv new file mode 100644 index 00000000..cf636ccb --- /dev/null +++ b/adi_library/interfaces/if_gt_pll_v1_0.sv @@ -0,0 +1,71 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +`ifndef if_gt_pll_v1_0 +`define if_gt_pll_v1_0 + +interface if_gt_pll_v1_0(); + logic cpll_rst_m; // + logic cpll_ref_clk_in; // + + modport MASTER ( + output cpll_rst_m, cpll_ref_clk_in + ); + + modport SLAVE ( + input cpll_rst_m, cpll_ref_clk_in + ); + + modport MONITOR ( + input cpll_rst_m, cpll_ref_clk_in + ); + +endinterface // if_gt_pll_v1_0 + +`endif \ No newline at end of file diff --git a/adi_library/interfaces/if_gt_qpll.xml b/adi_library/interfaces/if_gt_qpll.xml new file mode 100644 index 00000000..21d61c1e --- /dev/null +++ b/adi_library/interfaces/if_gt_qpll.xml @@ -0,0 +1,11 @@ + + + analog.com + interface + if_gt_qpll + 1.0 + false + false + 1 + 1 + diff --git a/adi_library/interfaces/if_gt_qpll_rtl.xml b/adi_library/interfaces/if_gt_qpll_rtl.xml new file mode 100644 index 00000000..aa7bfcc7 --- /dev/null +++ b/adi_library/interfaces/if_gt_qpll_rtl.xml @@ -0,0 +1,44 @@ + + + analog.com + interface + if_gt_qpll_rtl + 1.0 + + + + qpll_rst + + + true + + + required + 1 + + + required + 1 + in + + + + + qpll_ref_clk + + + true + + + required + 1 + + + required + 1 + in + + + + + diff --git a/adi_library/interfaces/if_gt_qpll_v1_0.sv b/adi_library/interfaces/if_gt_qpll_v1_0.sv new file mode 100644 index 00000000..a88a7b7c --- /dev/null +++ b/adi_library/interfaces/if_gt_qpll_v1_0.sv @@ -0,0 +1,71 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +`ifndef if_gt_qpll_v1_0 +`define if_gt_qpll_v1_0 + +interface if_gt_qpll_v1_0(); + logic qpll_rst; // + logic qpll_ref_clk; // + + modport MASTER ( + output qpll_rst, qpll_ref_clk + ); + + modport SLAVE ( + input qpll_rst, qpll_ref_clk + ); + + modport MONITOR ( + input qpll_rst, qpll_ref_clk + ); + +endinterface // if_gt_qpll_v1_0 + +`endif \ No newline at end of file diff --git a/adi_library/interfaces/if_gt_rx.xml b/adi_library/interfaces/if_gt_rx.xml new file mode 100644 index 00000000..a4691108 --- /dev/null +++ b/adi_library/interfaces/if_gt_rx.xml @@ -0,0 +1,11 @@ + + + analog.com + interface + if_gt_rx + 1.0 + false + false + 1 + 1 + diff --git a/adi_library/interfaces/if_gt_rx_ksig.xml b/adi_library/interfaces/if_gt_rx_ksig.xml new file mode 100644 index 00000000..90114ad2 --- /dev/null +++ b/adi_library/interfaces/if_gt_rx_ksig.xml @@ -0,0 +1,11 @@ + + + analog.com + interface + if_gt_rx_ksig + 1.0 + false + false + 1 + 1 + diff --git a/adi_library/interfaces/if_gt_rx_ksig_rtl.xml b/adi_library/interfaces/if_gt_rx_ksig_rtl.xml new file mode 100644 index 00000000..ea927e0c --- /dev/null +++ b/adi_library/interfaces/if_gt_rx_ksig_rtl.xml @@ -0,0 +1,80 @@ + + + analog.com + interface + if_gt_rx_ksig_rtl + 1.0 + + + + rx_gt_ilas_f + + + required + 4 + + + required + 4 + in + + + + + rx_gt_ilas_q + + + required + 4 + + + required + 4 + in + + + + + rx_gt_ilas_a + + + required + 4 + + + required + 4 + in + + + + + rx_gt_ilas_r + + + required + 4 + + + required + 4 + in + + + + + rx_gt_cgs_k + + + required + 4 + + + required + 4 + in + + + + + diff --git a/adi_library/interfaces/if_gt_rx_ksig_v1_0.sv b/adi_library/interfaces/if_gt_rx_ksig_v1_0.sv new file mode 100644 index 00000000..e7699434 --- /dev/null +++ b/adi_library/interfaces/if_gt_rx_ksig_v1_0.sv @@ -0,0 +1,74 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +`ifndef if_gt_rx_ksig_v1_0 +`define if_gt_rx_ksig_v1_0 + +interface if_gt_rx_ksig_v1_0(); + logic [3:0] rx_gt_ilas_f; // + logic [3:0] rx_gt_ilas_q; // + logic [3:0] rx_gt_ilas_a; // + logic [3:0] rx_gt_ilas_r; // + logic [3:0] rx_gt_cgs_k; // + + modport MASTER ( + output rx_gt_ilas_f, rx_gt_ilas_q, rx_gt_ilas_a, rx_gt_ilas_r, rx_gt_cgs_k + ); + + modport SLAVE ( + input rx_gt_ilas_f, rx_gt_ilas_q, rx_gt_ilas_a, rx_gt_ilas_r, rx_gt_cgs_k + ); + + modport MONITOR ( + input rx_gt_ilas_f, rx_gt_ilas_q, rx_gt_ilas_a, rx_gt_ilas_r, rx_gt_cgs_k + ); + +endinterface // if_gt_rx_ksig_v1_0 + +`endif \ No newline at end of file diff --git a/adi_library/interfaces/if_gt_rx_rtl.xml b/adi_library/interfaces/if_gt_rx_rtl.xml new file mode 100644 index 00000000..af1729d8 --- /dev/null +++ b/adi_library/interfaces/if_gt_rx_rtl.xml @@ -0,0 +1,384 @@ + + + analog.com + interface + if_gt_rx_rtl + 1.0 + + + + rx_p + + + required + 1 + + + required + 1 + in + + + + + rx_n + + + required + 1 + + + required + 1 + in + + + + + rx_rst + + + true + + + required + 1 + in + + + required + 1 + + + + + rx_rst_m + + + true + + + required + 1 + + + required + 1 + in + + + + + rx_pll_rst + + + true + + + required + 1 + in + + + required + 1 + + + + + rx_gt_rst + + + true + + + required + 1 + in + + + required + 1 + + + + + rx_gt_rst_m + + + true + + + required + 1 + + + required + 1 + in + + + + + rx_pll_locked + + + required + 1 + in + + + required + 1 + + + + + rx_pll_locked_m + + + required + 1 + + + required + 1 + in + + + + + rx_user_ready + + + required + 1 + in + + + required + 1 + + + + + rx_user_ready_m + + + required + 1 + + + required + 1 + in + + + + + rx_rst_done + + + required + 1 + in + + + required + 1 + + + + + rx_rst_done_m + + + required + 1 + + + required + 1 + in + + + + + rx_out_clk + + + true + + + required + 1 + in + + + required + 1 + + + + + rx_clk + + + true + + + required + 1 + + + required + 1 + in + + + + + rx_sysref + + + required + 1 + + + required + 1 + in + + + + + rx_sync + + + required + 1 + in + + + required + 1 + + + + + rx_sof + + + required + 1 + in + + + required + 1 + + + + + rx_data + + + required + 32 + in + + + required + 32 + + + + + rx_ip_rst + + + true + + + required + 1 + in + + + required + 1 + + + + + rx_ip_sof + + + required + 4 + + + required + 4 + in + + + + + rx_ip_data + + + required + 32 + + + required + 32 + in + + + + + rx_ip_sysref + + + required + 1 + in + + + required + 1 + + + + + rx_ip_sync + + + required + 1 + + + required + 1 + in + + + + + rx_ip_rst_done + + + required + 1 + in + + + required + 1 + + + + + diff --git a/adi_library/interfaces/if_gt_rx_v1_0.sv b/adi_library/interfaces/if_gt_rx_v1_0.sv new file mode 100644 index 00000000..540f2bab --- /dev/null +++ b/adi_library/interfaces/if_gt_rx_v1_0.sv @@ -0,0 +1,96 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +`ifndef if_gt_rx_v1_0 +`define if_gt_rx_v1_0 + +interface if_gt_rx_v1_0(); + logic rx_p; // + logic rx_n; // + logic rx_rst; // + logic rx_rst_m; // + logic rx_pll_rst; // + logic rx_gt_rst; // + logic rx_gt_rst_m; // + logic rx_pll_locked; // + logic rx_pll_locked_m; // + logic rx_user_ready; // + logic rx_user_ready_m; // + logic rx_rst_done; // + logic rx_rst_done_m; // + logic rx_out_clk; // + logic rx_clk; // + logic rx_sysref; // + logic rx_sync; // + logic rx_sof; // + logic [31:0] rx_data; // + logic rx_ip_rst; // + logic [3:0] rx_ip_sof; // + logic [31:0] rx_ip_data; // + logic rx_ip_sysref; // + logic rx_ip_sync; // + logic rx_ip_rst_done; // + + modport MASTER ( + input rx_rst, rx_pll_rst, rx_gt_rst, rx_pll_locked, rx_user_ready, rx_rst_done, rx_out_clk, rx_sync, rx_sof, rx_data, rx_ip_rst, rx_ip_sysref, rx_ip_rst_done, + output rx_p, rx_n, rx_rst_m, rx_gt_rst_m, rx_pll_locked_m, rx_user_ready_m, rx_rst_done_m, rx_clk, rx_sysref, rx_ip_sof, rx_ip_data, rx_ip_sync + ); + + modport SLAVE ( + input rx_p, rx_n, rx_rst_m, rx_gt_rst_m, rx_pll_locked_m, rx_user_ready_m, rx_rst_done_m, rx_clk, rx_sysref, rx_ip_sof, rx_ip_data, rx_ip_sync, + output rx_rst, rx_pll_rst, rx_gt_rst, rx_pll_locked, rx_user_ready, rx_rst_done, rx_out_clk, rx_sync, rx_sof, rx_data, rx_ip_rst, rx_ip_sysref, rx_ip_rst_done + ); + + modport MONITOR ( + input rx_p, rx_n, rx_rst, rx_rst_m, rx_pll_rst, rx_gt_rst, rx_gt_rst_m, rx_pll_locked, rx_pll_locked_m, rx_user_ready, rx_user_ready_m, rx_rst_done, rx_rst_done_m, rx_out_clk, rx_clk, rx_sysref, rx_sync, rx_sof, rx_data, rx_ip_rst, rx_ip_sof, rx_ip_data, rx_ip_sysref, rx_ip_sync, rx_ip_rst_done + ); + +endinterface // if_gt_rx_v1_0 + +`endif \ No newline at end of file diff --git a/adi_library/interfaces/if_gt_tx.xml b/adi_library/interfaces/if_gt_tx.xml new file mode 100644 index 00000000..a8c20fab --- /dev/null +++ b/adi_library/interfaces/if_gt_tx.xml @@ -0,0 +1,11 @@ + + + analog.com + interface + if_gt_tx + 1.0 + false + false + 1 + 1 + diff --git a/adi_library/interfaces/if_gt_tx_rtl.xml b/adi_library/interfaces/if_gt_tx_rtl.xml new file mode 100644 index 00000000..0ac409f3 --- /dev/null +++ b/adi_library/interfaces/if_gt_tx_rtl.xml @@ -0,0 +1,356 @@ + + + analog.com + interface + if_gt_tx_rtl + 1.0 + + + + tx_p + + + required + 1 + in + + + required + 1 + + + + + tx_n + + + required + 1 + in + + + required + 1 + + + + + tx_rst + + + true + + + required + 1 + in + + + required + 1 + + + + + tx_rst_m + + + true + + + required + 1 + + + required + 1 + in + + + + + tx_pll_rst + + + true + + + required + 1 + in + + + required + 1 + + + + + tx_gt_rst + + + true + + + required + 1 + in + + + required + 1 + + + + + tx_gt_rst_m + + + true + + + required + 1 + + + required + 1 + in + + + + + tx_pll_locked + + + required + 1 + in + + + required + 1 + + + + + tx_pll_locked_m + + + required + 1 + + + required + 1 + in + + + + + tx_user_ready + + + required + 1 + in + + + required + 1 + + + + + tx_user_ready_m + + + required + 1 + + + required + 1 + in + + + + + tx_rst_done + + + required + 1 + in + + + required + 1 + + + + + tx_rst_done_m + + + required + 1 + + + required + 1 + in + + + + + tx_out_clk + + + true + + + required + 1 + in + + + required + 1 + + + + + tx_clk + + + true + + + required + 1 + + + required + 1 + in + + + + + tx_sysref + + + required + 1 + + + required + 1 + in + + + + + tx_sync + + + required + 1 + + + required + 1 + in + + + + + tx_data + + + required + 32 + + + required + 32 + in + + + + + tx_ip_rst + + + true + + + required + 1 + in + + + required + 1 + + + + + tx_ip_data + + + required + 32 + in + + + required + 32 + + + + + tx_ip_sysref + + + required + 1 + in + + + required + 1 + + + + + tx_ip_sync + + + required + 1 + in + + + required + 1 + + + + + tx_ip_rst_done + + + required + 1 + in + + + required + 1 + + + + + diff --git a/adi_library/interfaces/if_gt_tx_v1_0.sv b/adi_library/interfaces/if_gt_tx_v1_0.sv new file mode 100644 index 00000000..8a77db8d --- /dev/null +++ b/adi_library/interfaces/if_gt_tx_v1_0.sv @@ -0,0 +1,94 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +`ifndef if_gt_tx_v1_0 +`define if_gt_tx_v1_0 + +interface if_gt_tx_v1_0(); + logic tx_p; // + logic tx_n; // + logic tx_rst; // + logic tx_rst_m; // + logic tx_pll_rst; // + logic tx_gt_rst; // + logic tx_gt_rst_m; // + logic tx_pll_locked; // + logic tx_pll_locked_m; // + logic tx_user_ready; // + logic tx_user_ready_m; // + logic tx_rst_done; // + logic tx_rst_done_m; // + logic tx_out_clk; // + logic tx_clk; // + logic tx_sysref; // + logic tx_sync; // + logic [31:0] tx_data; // + logic tx_ip_rst; // + logic [31:0] tx_ip_data; // + logic tx_ip_sysref; // + logic tx_ip_sync; // + logic tx_ip_rst_done; // + + modport MASTER ( + input tx_p, tx_n, tx_rst, tx_pll_rst, tx_gt_rst, tx_pll_locked, tx_user_ready, tx_rst_done, tx_out_clk, tx_ip_rst, tx_ip_data, tx_ip_sysref, tx_ip_sync, tx_ip_rst_done, + output tx_rst_m, tx_gt_rst_m, tx_pll_locked_m, tx_user_ready_m, tx_rst_done_m, tx_clk, tx_sysref, tx_sync, tx_data + ); + + modport SLAVE ( + input tx_rst_m, tx_gt_rst_m, tx_pll_locked_m, tx_user_ready_m, tx_rst_done_m, tx_clk, tx_sysref, tx_sync, tx_data, + output tx_p, tx_n, tx_rst, tx_pll_rst, tx_gt_rst, tx_pll_locked, tx_user_ready, tx_rst_done, tx_out_clk, tx_ip_rst, tx_ip_data, tx_ip_sysref, tx_ip_sync, tx_ip_rst_done + ); + + modport MONITOR ( + input tx_p, tx_n, tx_rst, tx_rst_m, tx_pll_rst, tx_gt_rst, tx_gt_rst_m, tx_pll_locked, tx_pll_locked_m, tx_user_ready, tx_user_ready_m, tx_rst_done, tx_rst_done_m, tx_out_clk, tx_clk, tx_sysref, tx_sync, tx_data, tx_ip_rst, tx_ip_data, tx_ip_sysref, tx_ip_sync, tx_ip_rst_done + ); + +endinterface // if_gt_tx_v1_0 + +`endif \ No newline at end of file diff --git a/adi_library/interfaces/if_xcvr_ch.xml b/adi_library/interfaces/if_xcvr_ch.xml new file mode 100644 index 00000000..0e502edc --- /dev/null +++ b/adi_library/interfaces/if_xcvr_ch.xml @@ -0,0 +1,11 @@ + + + analog.com + interface + if_xcvr_ch + 1.0 + false + false + 1 + 1 + diff --git a/adi_library/interfaces/if_xcvr_ch_rtl.xml b/adi_library/interfaces/if_xcvr_ch_rtl.xml new file mode 100644 index 00000000..0c004d39 --- /dev/null +++ b/adi_library/interfaces/if_xcvr_ch_rtl.xml @@ -0,0 +1,346 @@ + + + analog.com + interface + if_xcvr_ch_rtl + 1.0 + + + + pll_locked + + + required + 1 + in + + + required + 1 + + + + + rst + + + required + 1 + + + required + 1 + in + + + + + user_ready + + + required + 1 + + + required + 1 + in + + + + + rst_done + + + required + 1 + in + + + required + 1 + + + + + prbssel + + + required + 4 + + + required + 4 + in + + + + + prbsforceerr + + + required + 1 + + + required + 1 + in + + + + + prbscntreset + + + required + 1 + + + required + 1 + in + + + + + prbserr + + + required + 1 + in + + + required + 1 + + + + + prbslocked + + + required + 1 + in + + + required + 1 + + + + + lpm_dfe_n + + + required + 1 + + + required + 1 + in + + + + + rate + + + required + 3 + + + required + 3 + in + + + + + sys_clk_sel + + + required + 2 + + + required + 2 + in + + + + + out_clk_sel + + + required + 3 + + + required + 3 + in + + + + + tx_diffctrl + + + required + 4 + + + required + 4 + in + + + + + tx_postcursor + + + required + 5 + + + required + 5 + in + + + + + tx_precursor + + + required + 5 + + + required + 5 + in + + + + + enb + + + required + 1 + + + required + 1 + in + + + + + addr + + + required + 12 + + + required + 12 + in + + + + + wr + + + required + 1 + + + required + 1 + in + + + + + wdata + + + required + 16 + + + required + 16 + in + + + + + rdata + + + required + 16 + in + + + required + 16 + + + + + ready + + + required + 1 + in + + + required + 1 + + + + + bufstatus + + + required + 2 + + + required + 2 + in + + + + + bufstatus_rst + + + required + 1 + + + required + 1 + in + + + + + diff --git a/adi_library/interfaces/if_xcvr_ch_v1_0.sv b/adi_library/interfaces/if_xcvr_ch_v1_0.sv new file mode 100644 index 00000000..c5075566 --- /dev/null +++ b/adi_library/interfaces/if_xcvr_ch_v1_0.sv @@ -0,0 +1,95 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +`ifndef if_xcvr_ch_v1_0 +`define if_xcvr_ch_v1_0 + +interface if_xcvr_ch_v1_0(); + logic pll_locked; // + logic rst; // + logic user_ready; // + logic rst_done; // + logic [3:0] prbssel; // + logic prbsforceerr; // + logic prbscntreset; // + logic prbserr; // + logic prbslocked; // + logic lpm_dfe_n; // + logic [2:0] rate; // + logic [1:0] sys_clk_sel; // + logic [2:0] out_clk_sel; // + logic [3:0] tx_diffctrl; // + logic [4:0] tx_postcursor; // + logic [4:0] tx_precursor; // + logic enb; // + logic [11:0] addr; // + logic wr; // + logic [15:0] wdata; // + logic [15:0] rdata; // + logic ready; // + logic [1:0] bufstatus; // + logic bufstatus_rst; // + + modport MASTER ( + input pll_locked, rst_done, prbserr, prbslocked, rdata, ready, + output rst, user_ready, prbssel, prbsforceerr, prbscntreset, lpm_dfe_n, rate, sys_clk_sel, out_clk_sel, tx_diffctrl, tx_postcursor, tx_precursor, enb, addr, wr, wdata, bufstatus, bufstatus_rst + ); + + modport SLAVE ( + input rst, user_ready, prbssel, prbsforceerr, prbscntreset, lpm_dfe_n, rate, sys_clk_sel, out_clk_sel, tx_diffctrl, tx_postcursor, tx_precursor, enb, addr, wr, wdata, bufstatus, bufstatus_rst, + output pll_locked, rst_done, prbserr, prbslocked, rdata, ready + ); + + modport MONITOR ( + input pll_locked, rst, user_ready, rst_done, prbssel, prbsforceerr, prbscntreset, prbserr, prbslocked, lpm_dfe_n, rate, sys_clk_sel, out_clk_sel, tx_diffctrl, tx_postcursor, tx_precursor, enb, addr, wr, wdata, rdata, ready, bufstatus, bufstatus_rst + ); + +endinterface // if_xcvr_ch_v1_0 + +`endif \ No newline at end of file diff --git a/adi_library/interfaces/if_xcvr_cm.xml b/adi_library/interfaces/if_xcvr_cm.xml new file mode 100644 index 00000000..3599e1bb --- /dev/null +++ b/adi_library/interfaces/if_xcvr_cm.xml @@ -0,0 +1,11 @@ + + + analog.com + interface + if_xcvr_cm + 1.0 + false + false + 1 + 1 + diff --git a/adi_library/interfaces/if_xcvr_cm_rtl.xml b/adi_library/interfaces/if_xcvr_cm_rtl.xml new file mode 100644 index 00000000..25586dde --- /dev/null +++ b/adi_library/interfaces/if_xcvr_cm_rtl.xml @@ -0,0 +1,94 @@ + + + analog.com + interface + if_xcvr_cm_rtl + 1.0 + + + + enb + + + required + 1 + + + required + 1 + in + + + + + addr + + + required + 12 + + + required + 12 + in + + + + + wr + + + required + 1 + + + required + 1 + in + + + + + wdata + + + required + 16 + + + required + 16 + in + + + + + rdata + + + required + 16 + in + + + required + 16 + + + + + ready + + + required + 1 + in + + + required + 1 + + + + + diff --git a/adi_library/interfaces/if_xcvr_cm_v1_0.sv b/adi_library/interfaces/if_xcvr_cm_v1_0.sv new file mode 100644 index 00000000..160717eb --- /dev/null +++ b/adi_library/interfaces/if_xcvr_cm_v1_0.sv @@ -0,0 +1,77 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +`ifndef if_xcvr_cm_v1_0 +`define if_xcvr_cm_v1_0 + +interface if_xcvr_cm_v1_0(); + logic enb; // + logic [11:0] addr; // + logic wr; // + logic [15:0] wdata; // + logic [15:0] rdata; // + logic ready; // + + modport MASTER ( + input rdata, ready, + output enb, addr, wr, wdata + ); + + modport SLAVE ( + input enb, addr, wr, wdata, + output rdata, ready + ); + + modport MONITOR ( + input enb, addr, wr, wdata, rdata, ready + ); + +endinterface // if_xcvr_cm_v1_0 + +`endif \ No newline at end of file diff --git a/adi_library/interfaces/interfaces_ip.tcl b/adi_library/interfaces/interfaces_ip.tcl new file mode 100644 index 00000000..b978d159 --- /dev/null +++ b/adi_library/interfaces/interfaces_ip.tcl @@ -0,0 +1,119 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_if_define if_xcvr_cm +adi_if_ports output 1 enb +adi_if_ports output 12 addr +adi_if_ports output 1 wr +adi_if_ports output 16 wdata +adi_if_ports input 16 rdata +adi_if_ports input 1 ready + +adi_if_define if_xcvr_ch +adi_if_ports input 1 pll_locked +adi_if_ports output 1 rst +adi_if_ports output 1 user_ready +adi_if_ports input 1 rst_done +adi_if_ports output 4 prbssel +adi_if_ports output 1 prbsforceerr +adi_if_ports output 1 prbscntreset +adi_if_ports input 1 prbserr +adi_if_ports input 1 prbslocked +adi_if_ports output 1 lpm_dfe_n +adi_if_ports output 3 rate +adi_if_ports output 2 sys_clk_sel +adi_if_ports output 3 out_clk_sel +adi_if_ports output 4 tx_diffctrl +adi_if_ports output 5 tx_postcursor +adi_if_ports output 5 tx_precursor +adi_if_ports output 1 enb +adi_if_ports output 12 addr +adi_if_ports output 1 wr +adi_if_ports output 16 wdata +adi_if_ports input 16 rdata +adi_if_ports input 1 ready +adi_if_ports output 2 bufstatus +adi_if_ports output 1 bufstatus_rst + +adi_if_define if_gt_qpll +adi_if_ports output 1 qpll_rst reset +adi_if_ports output 1 qpll_ref_clk clock + +adi_if_define if_gt_pll +adi_if_ports output 1 cpll_rst_m reset +adi_if_ports output 1 cpll_ref_clk_in clock + +adi_if_define if_gt_rx +adi_if_ports output 1 rx_p +adi_if_ports output 1 rx_n +adi_if_ports input 1 rx_rst reset +adi_if_ports output 1 rx_rst_m reset +adi_if_ports input 1 rx_pll_rst reset +adi_if_ports input 1 rx_gt_rst reset +adi_if_ports output 1 rx_gt_rst_m reset +adi_if_ports input 1 rx_pll_locked +adi_if_ports output 1 rx_pll_locked_m +adi_if_ports input 1 rx_user_ready +adi_if_ports output 1 rx_user_ready_m +adi_if_ports input 1 rx_rst_done +adi_if_ports output 1 rx_rst_done_m +adi_if_ports input 1 rx_out_clk clock +adi_if_ports output 1 rx_clk clock +adi_if_ports output 1 rx_sysref +adi_if_ports input 1 rx_sync +adi_if_ports input 1 rx_sof +adi_if_ports input 32 rx_data +adi_if_ports input 1 rx_ip_rst reset +adi_if_ports output 4 rx_ip_sof +adi_if_ports output 32 rx_ip_data +adi_if_ports input 1 rx_ip_sysref +adi_if_ports output 1 rx_ip_sync +adi_if_ports input 1 rx_ip_rst_done + +adi_if_define if_gt_tx +adi_if_ports input 1 tx_p +adi_if_ports input 1 tx_n +adi_if_ports input 1 tx_rst reset +adi_if_ports output 1 tx_rst_m reset +adi_if_ports input 1 tx_pll_rst reset +adi_if_ports input 1 tx_gt_rst reset +adi_if_ports output 1 tx_gt_rst_m reset +adi_if_ports input 1 tx_pll_locked +adi_if_ports output 1 tx_pll_locked_m +adi_if_ports input 1 tx_user_ready +adi_if_ports output 1 tx_user_ready_m +adi_if_ports input 1 tx_rst_done +adi_if_ports output 1 tx_rst_done_m +adi_if_ports input 1 tx_out_clk clock +adi_if_ports output 1 tx_clk clock +adi_if_ports output 1 tx_sysref +adi_if_ports output 1 tx_sync +adi_if_ports output 32 tx_data +adi_if_ports input 1 tx_ip_rst reset +adi_if_ports input 32 tx_ip_data +adi_if_ports input 1 tx_ip_sysref +adi_if_ports input 1 tx_ip_sync +adi_if_ports input 1 tx_ip_rst_done + +adi_if_define if_gt_rx_ksig +adi_if_ports output 4 rx_gt_ilas_f +adi_if_ports output 4 rx_gt_ilas_q +adi_if_ports output 4 rx_gt_ilas_a +adi_if_ports output 4 rx_gt_ilas_r +adi_if_ports output 4 rx_gt_cgs_k + +adi_if_define if_do_ctrl +adi_if_ports output 1 request_enable +adi_if_ports output 1 request_valid +adi_if_ports input 1 request_ready +adi_if_ports output -1 request_length +adi_if_ports output -1 response_measured_length +adi_if_ports input 1 response_eot +adi_if_ports input 1 status_underflow +adi_if_ports input 1 status_overflow diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/.lock b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/.lock new file mode 100644 index 00000000..e69de29b diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/.timestamp_intel b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/.timestamp_intel new file mode 100644 index 00000000..e69de29b diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/Makefile b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/Makefile new file mode 100644 index 00000000..cd9246ba --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/Makefile @@ -0,0 +1,42 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := ad_ip_jesd204_tpl_adc + +GENERIC_DEPS += ../../common/ad_datafmt.v +GENERIC_DEPS += ../../common/ad_perfect_shuffle.v +GENERIC_DEPS += ../../common/ad_pnmon.v +GENERIC_DEPS += ../../common/ad_rst.v +GENERIC_DEPS += ../../common/ad_xcvr_rx_if.v +GENERIC_DEPS += ../../common/up_adc_channel.v +GENERIC_DEPS += ../../common/up_adc_common.v +GENERIC_DEPS += ../../common/up_axi.v +GENERIC_DEPS += ../../common/up_clock_mon.v +GENERIC_DEPS += ../../common/up_xfer_cntrl.v +GENERIC_DEPS += ../../common/up_xfer_status.v +GENERIC_DEPS += ../../common/util_ext_sync.v +GENERIC_DEPS += ad_ip_jesd204_tpl_adc.v +GENERIC_DEPS += ad_ip_jesd204_tpl_adc_channel.v +GENERIC_DEPS += ad_ip_jesd204_tpl_adc_core.v +GENERIC_DEPS += ad_ip_jesd204_tpl_adc_deframer.v +GENERIC_DEPS += ad_ip_jesd204_tpl_adc_pnmon.v +GENERIC_DEPS += ad_ip_jesd204_tpl_adc_regmap.v + +XILINX_DEPS += ../../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += ../ad_ip_jesd204_tpl_common/up_tpl_common.v +XILINX_DEPS += ad_ip_jesd204_tpl_adc_ip.tcl + +INTEL_DEPS += ../../intel/common/up_clock_mon_constr.sdc +INTEL_DEPS += ../../intel/common/up_rst_constr.sdc +INTEL_DEPS += ../../intel/common/up_xfer_cntrl_constr.sdc +INTEL_DEPS += ../../intel/common/up_xfer_status_constr.sdc +INTEL_DEPS += ../../jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v +INTEL_DEPS += ad_ip_jesd204_tpl_adc_hw.tcl + +include ../../scripts/library.mk diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v new file mode 100644 index 00000000..bd2bac0c --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v @@ -0,0 +1,240 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_ip_jesd204_tpl_adc #( + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter NUM_LANES = 1, + parameter NUM_CHANNELS = 4, + parameter SAMPLES_PER_FRAME = 1, + parameter CONVERTER_RESOLUTION = 14, + parameter BITS_PER_SAMPLE = 16, + parameter DMA_BITS_PER_SAMPLE = 16, + parameter OCTETS_PER_BEAT = 4, + parameter EN_FRAME_ALIGN = 1, + parameter TWOS_COMPLEMENT = 1, + parameter EXT_SYNC = 0, + parameter PN7_ENABLE = 1, + parameter PN15_ENABLE = 1 +) ( + + // jesd interface + // link_clk is (line-rate/40) + input link_clk, + + input [OCTETS_PER_BEAT-1:0] link_sof, + input link_valid, + input [NUM_LANES*8*OCTETS_PER_BEAT-1:0] link_data, + output link_ready, + + // dma interface + + output [NUM_CHANNELS-1:0] enable, + + output [NUM_CHANNELS-1:0] adc_valid, + output [DMA_BITS_PER_SAMPLE * OCTETS_PER_BEAT * 8 * NUM_LANES / BITS_PER_SAMPLE-1:0] adc_data, + input adc_dovf, + + input adc_sync_in, + output adc_sync_manual_req_out, + input adc_sync_manual_req_in, + + output adc_rst, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + + input s_axi_awvalid, + output s_axi_awready, + input [12:0] s_axi_awaddr, + input [2:0] s_axi_awprot, + + input s_axi_wvalid, + output s_axi_wready, + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + + output s_axi_bvalid, + input s_axi_bready, + output [1:0] s_axi_bresp, + + input s_axi_arvalid, + output s_axi_arready, + input [12:0] s_axi_araddr, + input [2:0] s_axi_arprot, + + output s_axi_rvalid, + input s_axi_rready, + output [1:0] s_axi_rresp, + output [31:0] s_axi_rdata +); + + // Number of samples per channel that are processed in parallel. + localparam DATA_PATH_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES / NUM_CHANNELS / BITS_PER_SAMPLE; + localparam LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8; + localparam DMA_DATA_WIDTH = DMA_BITS_PER_SAMPLE * DATA_PATH_WIDTH * NUM_CHANNELS; + + localparam BYTES_PER_FRAME = (NUM_CHANNELS * BITS_PER_SAMPLE * SAMPLES_PER_FRAME) / ( 8 * NUM_LANES); + + wire [NUM_CHANNELS-1:0] dfmt_enable_s; + wire [NUM_CHANNELS-1:0] dfmt_sign_extend_s; + wire [NUM_CHANNELS-1:0] dfmt_type_s; + + wire [NUM_CHANNELS*4-1:0] pn_seq_sel_s; + wire [NUM_CHANNELS-1:0] pn_err_s; + wire [NUM_CHANNELS-1:0] pn_oos_s; + + wire adc_rst_sync_s; + wire adc_rst_s; + wire adc_sync; + wire adc_sync_status; + + assign adc_rst = adc_rst_s | adc_rst_sync_s; + + // regmap + ad_ip_jesd204_tpl_adc_regmap #( + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .NUM_CHANNELS (NUM_CHANNELS), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .NUM_PROFILES(1), + .EXT_SYNC (EXT_SYNC) + ) i_regmap ( + .s_axi_aclk (s_axi_aclk), + .s_axi_aresetn (s_axi_aresetn), + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awprot (s_axi_awprot), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready (s_axi_wready), + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bresp (s_axi_bresp), + .s_axi_bready (s_axi_bready), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), + .s_axi_araddr (s_axi_araddr), + .s_axi_arprot (s_axi_arprot), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rready (s_axi_rready), + .s_axi_rresp (s_axi_rresp), + .s_axi_rdata (s_axi_rdata), + + .link_clk (link_clk), + + .dfmt_enable (dfmt_enable_s), + .dfmt_sign_extend (dfmt_sign_extend_s), + .dfmt_type (dfmt_type_s), + + .pn_seq_sel (pn_seq_sel_s), + .pn_err (pn_err_s), + .pn_oos (pn_oos_s), + + .enable (enable), + + .adc_sync (adc_sync), + .adc_sync_status (adc_sync_status), + .adc_ext_sync_arm (adc_ext_sync_arm), + .adc_ext_sync_disarm (adc_ext_sync_disarm), + .adc_ext_sync_manual_req (adc_sync_manual_req_out), + + .adc_rst (adc_rst_s), + + .adc_dovf (adc_dovf), + + .jesd_m (NUM_CHANNELS), + .jesd_l (NUM_LANES), + .jesd_s (SAMPLES_PER_FRAME), + .jesd_f (BYTES_PER_FRAME), + .jesd_n (CONVERTER_RESOLUTION), + .jesd_np (BITS_PER_SAMPLE), + .up_profile_sel ()); + + ad_ip_jesd204_tpl_adc_core #( + .NUM_LANES (NUM_LANES), + .NUM_CHANNELS (NUM_CHANNELS), + .BITS_PER_SAMPLE (BITS_PER_SAMPLE), + .CONVERTER_RESOLUTION (CONVERTER_RESOLUTION), + .SAMPLES_PER_FRAME (SAMPLES_PER_FRAME), + .EN_FRAME_ALIGN (EN_FRAME_ALIGN), + .OCTETS_PER_BEAT (OCTETS_PER_BEAT), + .LINK_DATA_WIDTH (LINK_DATA_WIDTH), + .DMA_DATA_WIDTH (DMA_DATA_WIDTH), + .TWOS_COMPLEMENT (TWOS_COMPLEMENT), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .DMA_BITS_PER_SAMPLE (DMA_BITS_PER_SAMPLE), + .EXT_SYNC (EXT_SYNC), + .PN7_ENABLE (PN7_ENABLE), + .PN15_ENABLE(PN15_ENABLE) + ) i_core ( + .clk (link_clk), + + .dfmt_enable (dfmt_enable_s), + .dfmt_sign_extend (dfmt_sign_extend_s), + .dfmt_type (dfmt_type_s), + + .pn_seq_sel (pn_seq_sel_s), + .pn_err (pn_err_s), + .pn_oos (pn_oos_s), + + .link_valid (link_valid), + .link_ready (link_ready), + .link_sof (link_sof), + .link_data (link_data), + + .adc_sync (adc_sync), + .adc_sync_status (adc_sync_status), + .adc_sync_in (adc_sync_in), + .adc_ext_sync_arm (adc_ext_sync_arm), + .adc_ext_sync_disarm (adc_ext_sync_disarm), + .adc_sync_manual_req (adc_sync_manual_req_in), + .adc_rst_sync (adc_rst_sync_s), + + .adc_valid (adc_valid), + .adc_data (adc_data)); + +endmodule diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.xpr b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.xpr new file mode 100644 index 00000000..d0f5430c --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.xpr @@ -0,0 +1,556 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v new file mode 100644 index 00000000..4a4b8a8a --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v @@ -0,0 +1,98 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_ip_jesd204_tpl_adc_channel #( + parameter CONVERTER_RESOLUTION = 14, + parameter DATA_PATH_WIDTH = 2, + parameter TWOS_COMPLEMENT = 1, + parameter BITS_PER_SAMPLE = 16, + parameter PN7_ENABLE = 1, + parameter PN15_ENABLE = 1 +) ( + input clk, + + input [CONVERTER_RESOLUTION*DATA_PATH_WIDTH-1:0] raw_data, + + output [BITS_PER_SAMPLE*DATA_PATH_WIDTH-1:0] fmt_data, + + // Configuration and status + input dfmt_enable, + input dfmt_type, + input dfmt_sign_extend, + + input [3:0] pn_seq_sel, + output pn_oos, + output pn_err +); + + // instantiations + + ad_ip_jesd204_tpl_adc_pnmon #( + .CONVERTER_RESOLUTION (CONVERTER_RESOLUTION), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .TWOS_COMPLEMENT (TWOS_COMPLEMENT), + .PN7_ENABLE (PN7_ENABLE), + .PN15_ENABLE(PN15_ENABLE) + ) i_pnmon ( + .clk (clk), + .data (raw_data), + + .pn_seq_sel (pn_seq_sel), + .pn_oos (pn_oos), + .pn_err (pn_err)); + + generate + genvar n; + for (n = 0; n < DATA_PATH_WIDTH; n = n + 1) begin: g_datafmt + ad_datafmt #( + .DATA_WIDTH (CONVERTER_RESOLUTION), + .BITS_PER_SAMPLE (BITS_PER_SAMPLE) + ) i_ad_datafmt ( + .clk (clk), + + .valid (1'b1), + .data (raw_data[n*CONVERTER_RESOLUTION+:CONVERTER_RESOLUTION]), + .valid_out (), + .data_out (fmt_data[n*BITS_PER_SAMPLE+:BITS_PER_SAMPLE]), + + .dfmt_enable (dfmt_enable), + .dfmt_type (dfmt_type), + .dfmt_se (dfmt_sign_extend)); + end + endgenerate + +endmodule diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v new file mode 100644 index 00000000..c5e6aa2b --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v @@ -0,0 +1,155 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_ip_jesd204_tpl_adc_core #( + parameter NUM_LANES = 1, + parameter NUM_CHANNELS = 1, + parameter SAMPLES_PER_FRAME = 1, + parameter CONVERTER_RESOLUTION = 14, + parameter BITS_PER_SAMPLE = 16, + parameter DMA_BITS_PER_SAMPLE = 16, + parameter OCTETS_PER_BEAT = 4, + parameter EN_FRAME_ALIGN = 0, + parameter DATA_PATH_WIDTH = 1, + parameter LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8, + parameter DMA_DATA_WIDTH = DATA_PATH_WIDTH * DMA_BITS_PER_SAMPLE * NUM_CHANNELS, + parameter TWOS_COMPLEMENT = 1, + parameter EXT_SYNC = 0, + parameter PN7_ENABLE = 1, + parameter PN15_ENABLE = 1 +) ( + input clk, + + input [NUM_CHANNELS-1:0] dfmt_enable, + input [NUM_CHANNELS-1:0] dfmt_sign_extend, + input [NUM_CHANNELS-1:0] dfmt_type, + + input [NUM_CHANNELS*4-1:0] pn_seq_sel, + output [NUM_CHANNELS-1:0] pn_err, + output [NUM_CHANNELS-1:0] pn_oos, + + output [NUM_CHANNELS-1:0] adc_valid, + output [DMA_DATA_WIDTH-1:0] adc_data, + + input adc_sync, + output adc_sync_status, + input adc_ext_sync_arm, + input adc_ext_sync_disarm, + input adc_sync_in, + input adc_sync_manual_req, + output adc_rst_sync, + + input link_valid, + output link_ready, + input [OCTETS_PER_BEAT-1:0] link_sof, + input [LINK_DATA_WIDTH-1:0] link_data +); + // Raw and formatted channel data widths + localparam CDW_RAW = CONVERTER_RESOLUTION * DATA_PATH_WIDTH; + localparam ADC_DATA_WIDTH = CDW_RAW * NUM_CHANNELS; + localparam CDW_FMT = DMA_BITS_PER_SAMPLE * DATA_PATH_WIDTH; + + wire [ADC_DATA_WIDTH-1:0] raw_data_s; + wire link_valid_tmp; + + reg link_valid_d = 1'b0; + reg link_valid_dd = 1'b0; + + assign link_ready = 1'b1; + assign link_valid_tmp = EN_FRAME_ALIGN ? link_valid_dd : link_valid_d; + assign adc_valid = {NUM_CHANNELS{link_valid_tmp & ~adc_sync_armed}}; + assign adc_sync_status = adc_sync_armed; + assign adc_rst_sync = adc_sync_armed; + + always @(posedge clk) begin + link_valid_d <= link_valid; + link_valid_dd <= link_valid_d; + end + + // synchronization logic + util_ext_sync #( + .ENABLED (EXT_SYNC) + ) i_util_ext_sync ( + .clk (clk), + .ext_sync_arm (adc_ext_sync_arm), + .ext_sync_disarm (adc_ext_sync_disarm), + .sync_in (adc_sync_in | adc_sync_manual_req), + .sync_armed (adc_sync_armed)); + + ad_ip_jesd204_tpl_adc_deframer #( + .NUM_LANES (NUM_LANES), + .NUM_CHANNELS (NUM_CHANNELS), + .BITS_PER_SAMPLE (BITS_PER_SAMPLE), + .CONVERTER_RESOLUTION (CONVERTER_RESOLUTION), + .SAMPLES_PER_FRAME (SAMPLES_PER_FRAME), + .OCTETS_PER_BEAT (OCTETS_PER_BEAT), + .EN_FRAME_ALIGN (EN_FRAME_ALIGN), + .LINK_DATA_WIDTH (LINK_DATA_WIDTH), + .ADC_DATA_WIDTH (ADC_DATA_WIDTH) + ) i_deframer ( + .clk (clk), + .link_sof (link_sof), + .link_data (link_data), + .adc_data (raw_data_s)); + + generate + genvar i; + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel + ad_ip_jesd204_tpl_adc_channel #( + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CONVERTER_RESOLUTION (CONVERTER_RESOLUTION), + .TWOS_COMPLEMENT (TWOS_COMPLEMENT), + .BITS_PER_SAMPLE (DMA_BITS_PER_SAMPLE), + .PN7_ENABLE (PN7_ENABLE), + .PN15_ENABLE(PN15_ENABLE) + ) i_channel ( + .clk (clk), + + .raw_data (raw_data_s[CDW_RAW*i+:CDW_RAW]), + .fmt_data (adc_data[CDW_FMT*i+:CDW_FMT]), + + .dfmt_enable (dfmt_enable[i]), + .dfmt_sign_extend (dfmt_sign_extend[i]), + .dfmt_type (dfmt_type[i]), + + .pn_seq_sel (pn_seq_sel[i*4+:4]), + .pn_err (pn_err[i]), + .pn_oos (pn_oos[i])); + end + endgenerate + +endmodule diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v new file mode 100644 index 00000000..c477aa17 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v @@ -0,0 +1,133 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_ip_jesd204_tpl_adc_deframer #( + parameter NUM_LANES = 1, + parameter NUM_CHANNELS = 4, + parameter BITS_PER_SAMPLE = 16, + parameter CONVERTER_RESOLUTION = 14, + parameter SAMPLES_PER_FRAME = 1, + parameter OCTETS_PER_BEAT = 8, + parameter EN_FRAME_ALIGN = 0, + parameter LINK_DATA_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES, + parameter ADC_DATA_WIDTH = LINK_DATA_WIDTH * CONVERTER_RESOLUTION / BITS_PER_SAMPLE +) ( + + // jesd interface + // clk is (line-rate/40) + + input clk, + input [OCTETS_PER_BEAT-1:0] link_sof, + input [LINK_DATA_WIDTH-1:0] link_data, + + // adc data output + + output [ADC_DATA_WIDTH-1:0] adc_data +); + + localparam SAMPLES_PER_BEAT = ADC_DATA_WIDTH / CONVERTER_RESOLUTION; + localparam BITS_PER_CHANNEL_PER_FRAME = BITS_PER_SAMPLE * SAMPLES_PER_FRAME; + localparam BITS_PER_LANE_PER_FRAME = BITS_PER_CHANNEL_PER_FRAME * + NUM_CHANNELS / NUM_LANES; + localparam FRAMES_PER_BEAT = OCTETS_PER_BEAT * 8 / BITS_PER_LANE_PER_FRAME; + + wire [LINK_DATA_WIDTH-1:0] link_data_s; + wire [LINK_DATA_WIDTH-1:0] link_data_msb_s; + wire [LINK_DATA_WIDTH-1:0] frame_data_s; + wire [LINK_DATA_WIDTH-1:0] adc_data_msb; + + // data multiplex + + genvar i; + genvar j; + generate + /* Reorder octets MSB first */ + for (i = 0; i < LINK_DATA_WIDTH; i = i + 8) begin: g_adc_data + assign link_data_msb_s[i+:8] = link_data_s[LINK_DATA_WIDTH-1-i-:8]; + end + + /* Slice lanes into frames */ + ad_perfect_shuffle #( + .NUM_GROUPS (NUM_LANES), + .WORDS_PER_GROUP (FRAMES_PER_BEAT), + .WORD_WIDTH (BITS_PER_LANE_PER_FRAME) + ) i_lanes_to_frames ( + .data_in (link_data_msb_s), + .data_out (frame_data_s)); + + /* Slice frames into channels */ + ad_perfect_shuffle #( + .NUM_GROUPS (FRAMES_PER_BEAT), + .WORDS_PER_GROUP (NUM_CHANNELS), + .WORD_WIDTH (BITS_PER_CHANNEL_PER_FRAME) + ) i_frames_to_channels ( + .data_in (frame_data_s), + .data_out (adc_data_msb)); + + /* Reorder samples LSB first and remove tail bits */ + for (i = 0; i < SAMPLES_PER_BEAT; i = i + 1) begin: g_dac_data_msb + localparam src_w = BITS_PER_SAMPLE; + localparam dst_w = CONVERTER_RESOLUTION; + localparam src_msb = LINK_DATA_WIDTH - 1 - i * src_w ; + localparam dst_lsb = i * dst_w; + + assign adc_data[dst_lsb+:dst_w] = adc_data_msb[src_msb-:dst_w]; + end + endgenerate + + // frame-alignment + + generate + genvar n; + if (EN_FRAME_ALIGN) begin + for (n = 0; n < NUM_LANES; n = n + 1) begin: g_xcvr_if + localparam DW = OCTETS_PER_BEAT * 8; + ad_xcvr_rx_if #( + .OCTETS_PER_BEAT (OCTETS_PER_BEAT) + ) i_xcvr_if ( + .rx_clk (clk), + .rx_ip_sof (link_sof), + .rx_ip_data (link_data[n*DW+:DW]), + .rx_sof (), + .rx_data (link_data_s[n*DW+:DW])); + end + end else begin + assign link_data_s = link_data; + end + endgenerate + +endmodule diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl new file mode 100644 index 00000000..6a4a84ba --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl @@ -0,0 +1,279 @@ +############################################################################### +## Copyright (C) 2018-2022 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +package require qsys 14.0 +source ../../../scripts/adi_env.tcl +source ../../scripts/adi_ip_intel.tcl + +ad_ip_create ad_ip_jesd204_tpl_adc "JESD204 Transport Layer for ADCs" p_ad_ip_jesd204_tpl_adc_elab +set_module_property VALIDATION_CALLBACK p_ad_ip_jesd204_tpl_adc_validate +ad_ip_files ad_ip_jesd204_tpl_adc [list \ + $ad_hdl_dir/library/common/ad_rst.v \ + $ad_hdl_dir/library/common/ad_perfect_shuffle.v \ + $ad_hdl_dir/library/common/ad_pnmon.v \ + $ad_hdl_dir/library/common/ad_datafmt.v \ + $ad_hdl_dir/library/common/up_axi.v \ + $ad_hdl_dir/library/common/up_xfer_cntrl.v \ + $ad_hdl_dir/library/common/up_xfer_status.v \ + $ad_hdl_dir/library/common/up_clock_mon.v \ + $ad_hdl_dir/library/common/up_adc_common.v \ + $ad_hdl_dir/library/common/up_adc_channel.v \ + $ad_hdl_dir/library/common/util_ext_sync.v \ + $ad_hdl_dir/library/common/ad_xcvr_rx_if.v \ + $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v \ + $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v \ + $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v \ + $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_channel.v \ + $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v \ + $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_deframer.v \ + $ad_hdl_dir/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc.v \ + $ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_rst_constr.sdc] + +# parameters + +set group "General Configuration" + +ad_ip_parameter ID INTEGER 0 true [list \ + DISPLAY_NAME "Core ID" \ + GROUP $group \ +] + +ad_ip_parameter OCTETS_PER_BEAT INTEGER 4 true [list \ + DISPLAY_NAME "Datapath width" \ + DISPLAY_UNITS "octets" \ + ALLOWED_RANGES {4 6 8 12} \ + GROUP $group \ +] + +set group "JESD204 Deframer Configuration" + +ad_ip_parameter NUM_LANES INTEGER 1 true [list \ + DISPLAY_NAME "Number of Lanes (L)" \ + DISPLAY_UNITS "lanes" \ + ALLOWED_RANGES {1 2 3 4 8 16 24 32} \ + GROUP $group \ +] + +ad_ip_parameter NUM_CHANNELS INTEGER 1 true [list \ + DISPLAY_NAME "Number of Converters (M)" \ + DISPLAY_UNITS "converters" \ + ALLOWED_RANGES {1 2 4 6 8 16 32 64} \ + GROUP $group \ +] + +ad_ip_parameter BITS_PER_SAMPLE INTEGER 16 true [list \ + DISPLAY_NAME "Bits per Sample (N')" \ + ALLOWED_RANGES {8 12 16} \ + UNITS bits \ + GROUP $group \ +] + +ad_ip_parameter DMA_BITS_PER_SAMPLE INTEGER 16 true [list \ + DISPLAY_NAME "DMA Bits per Sample" \ + ALLOWED_RANGES {8 16} \ + UNITS bits \ + GROUP $group \ +] + +ad_ip_parameter CONVERTER_RESOLUTION INTEGER 16 true [list \ + DISPLAY_NAME "Converter Resolution (N)" \ + ALLOWED_RANGES {8 11 12 14 16} \ + UNITS bits \ + GROUP $group \ +] + +ad_ip_parameter ENABLE_SAMPLES_PER_FRAME_MANUAL BOOLEAN 0 false [list \ + DISPLAY_NAME "Manual Samples per Frame" \ + GROUP $group \ +] + +ad_ip_parameter SAMPLES_PER_FRAME INTEGER 1 true [list \ + DISPLAY_NAME "Samples per Frame (S)" \ + DISPLAY_UNITS "samples" \ + ALLOWED_RANGES {1 2 3 4 6 8 12 16} \ + DERIVED true \ + GROUP $group \ +] + +ad_ip_parameter SAMPLES_PER_FRAME_MANUAL INTEGER 1 false [list \ + DISPLAY_NAME "Samples per Frame (S)" \ + DISPLAY_UNITS "samples" \ + ALLOWED_RANGES {1 2 3 4 6 8 12 16} \ + VISIBLE false \ + GROUP $group \ +] + +ad_ip_parameter OCTETS_PER_FRAME INTEGER 1 false [list \ + DISPLAY_NAME "Octets per Frame (F)" \ + DISPLAY_UNITS "octets" \ + ALLOWED_RANGES {1 2 3 4 6 8 12 16} \ + DERIVED true \ + GROUP $group \ +] + +set group "Deframer Output Information" + +# Parameters in this group are informative only and can be read back after the +# core has been configured to find out the expected layout of the input data. +# E.g. +# set NUM_OF_CHANNELS [get_instance_parameter_value jesd204_transport NUM_CHANNELS] +# set CHANNEL_DATA_WIDTH [get_instance_parameter_value jesd204_transport CHANNEL_DATA_WIDTH] +# +# add_instance util_adc_cpack util_cpack +# set_instance_parameter_values util_adc_cpack [list \ +# CHANNEL_DATA_WIDTH $CHANNEL_DATA_WIDTH \ +# NUM_OF_CHANNELS $NUM_OF_CHANNELS \ +# ] + +ad_ip_parameter SAMPLES_PER_CHANNEL INTEGER 1 false [list \ + DISPLAY_NAME "Samples per Channel per Beat" \ + DERIVED true \ + GROUP $group \ +] + +ad_ip_parameter CHANNEL_DATA_WIDTH INTEGER 1 false [list \ + DISPLAY_NAME "Channel Data Width" \ + UNITS bits \ + DERIVED true \ + GROUP $group \ +] + +set group "Datapath Configuration" + +ad_ip_parameter TWOS_COMPLEMENT boolean 1 true [list \ + DISPLAY_NAME "Twos Complement" \ + GROUP $group \ +] +ad_ip_parameter PN7_ENABLE boolean 1 true [list \ + DISPLAY_NAME "Enable PN7" \ + GROUP $group \ +] +ad_ip_parameter PN15_ENABLE boolean 1 true [list \ + DISPLAY_NAME "Enable PN15" \ + GROUP $group \ +] + +# axi4 slave + +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12 + +# core clock and start of frame + +add_interface link_clk clock end +add_interface_port link_clk link_clk clk Input 1 +ad_interface signal link_sof input 4 export + +# We don't expect too large values for a and b, trivial implementation will do +proc gcd {a b} { + if {$a == $b} { + return $b + } elseif {$a > $b} { + return [gcd [expr $a - $b] $b] + } else { + return [gcd $a [expr $b - $a]] + } +} + +# validate + +proc p_ad_ip_jesd204_tpl_adc_validate {} { + set L [get_parameter_value "NUM_LANES"] + set M [get_parameter_value "NUM_CHANNELS"] + set NP [get_parameter_value "BITS_PER_SAMPLE"] + set N [get_parameter_value "CONVERTER_RESOLUTION"] + set S_manual [get_parameter_value "SAMPLES_PER_FRAME_MANUAL"] + set enable_S_manual [get_parameter_value "ENABLE_SAMPLES_PER_FRAME_MANUAL"] + + # With fixed values for M, L and N' all valid values for S and F have a + # constant ratio of S / F. Choose a ratio so that S and F are co-prime. + # Choosing values for F and S that have a common factor has higher latency + # and no added benefits. + # + # Since converters often support those higher latency modes still allow a + # manual override of the S parameter in case somebody wants to use those modes + # anyway. + # + # To be able to set samples per frame manually ENABLE_SAMPLES_PER_FRAME_MANUAL + # needs to be set to true and SAMPLES_PER_FRAME_MANUAL to the desired value. + # + # When manual sample per frame selection is enabled still verify that the + # selected value is valid. + + set S_min [expr $L * 8] + set F_min [expr $M * $NP] + set common_factor [gcd $S_min $F_min] + set S_min [expr $S_min / $common_factor] + set F_min [expr $F_min / $common_factor] + + if {$enable_S_manual} { + if {$S_manual % $S_min != 0} { + send_message ERROR "For framer configuration (L=$L, M=$M, NP=$NP) samples per frame (S) must be an integer multiple of $S_min" + set S $S_min + set F $F_min + } else { + set S $S_manual + set F [expr $S_manual * $M * $NP / $L / 8] + } + } else { + set S $S_min + set F $F_min + } + + set_parameter_value OCTETS_PER_FRAME $F + set_parameter_value SAMPLES_PER_FRAME $S + + set_parameter_property SAMPLES_PER_FRAME VISIBLE [expr !$enable_S_manual] + set_parameter_property SAMPLES_PER_FRAME_MANUAL VISIBLE $enable_S_manual + + set_parameter_value SAMPLES_PER_CHANNEL [expr 4 * $S / $F] + set_parameter_value CHANNEL_DATA_WIDTH [expr 16 * (4 * $S / $F)] + +} + +# elaborate + +proc p_ad_ip_jesd204_tpl_adc_elab {} { + + # read core parameters + + set L [get_parameter_value "NUM_LANES"] + set M [get_parameter_value "NUM_CHANNELS"] + set NP [get_parameter_value "BITS_PER_SAMPLE"] + set OPB [get_parameter_value "OCTETS_PER_BEAT"] + set DMA_BPS [get_parameter_value "DMA_BITS_PER_SAMPLE"] + + # The DMA interface is rounded to nearest power of two bytes per sample, + # e.g NP=12 is padded into 16 bits + set samples_per_beat_per_channel [expr ($OPB * 8 * $L / ($M * $NP))] + set channel_bus_width [expr $samples_per_beat_per_channel*$DMA_BPS] + + # link layer interface + + add_interface link_data avalon_streaming sink + add_interface_port link_data link_data data input [expr $OPB*8*$L] + add_interface_port link_data link_valid valid input 1 + add_interface_port link_data link_ready ready output 1 + set_interface_property link_data associatedClock link_clk + set_interface_property link_data dataBitsPerSymbol [expr $OPB*8*$L] + + # dma interface + + for {set i 0} {$i < $M} {incr i} { + add_interface adc_ch_$i conduit end + add_interface_port adc_ch_$i adc_enable_$i enable output 1 + set_port_property adc_enable_$i fragment_list [format "enable(%d:%d)" $i $i] + add_interface_port adc_ch_$i adc_valid_$i valid output 1 + set_port_property adc_valid_$i fragment_list [format "adc_valid(%d:%d)" $i $i] + add_interface_port adc_ch_$i adc_data_$i data output $channel_bus_width + set_port_property adc_data_$i fragment_list \ + [format "adc_data(%d:%d)" [expr $channel_bus_width*$i+$channel_bus_width-1] [expr $channel_bus_width*$i]] + set_interface_property adc_ch_$i associatedClock link_clk + } + + ad_interface signal adc_dovf input 1 ovf +} diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl new file mode 100644 index 00000000..cb407b48 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.tcl @@ -0,0 +1,135 @@ +############################################################################### +## Copyright (C) 2018-2022 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create ad_ip_jesd204_tpl_adc + +adi_ip_files ad_ip_jesd204_tpl_adc [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/ad_perfect_shuffle.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ + "$ad_hdl_dir/library/common/ad_datafmt.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_adc_common.v" \ + "$ad_hdl_dir/library/common/up_adc_channel.v" \ + "$ad_hdl_dir/library/common/util_ext_sync.v" \ + "$ad_hdl_dir/library/common/ad_xcvr_rx_if.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "../ad_ip_jesd204_tpl_common/up_tpl_common.v" \ + "ad_ip_jesd204_tpl_adc_core.v" \ + "ad_ip_jesd204_tpl_adc_channel.v" \ + "ad_ip_jesd204_tpl_adc_deframer.v" \ + "ad_ip_jesd204_tpl_adc_pnmon.v" \ + "ad_ip_jesd204_tpl_adc_regmap.v" \ + "ad_ip_jesd204_tpl_adc.v" \ + ] + +adi_ip_properties ad_ip_jesd204_tpl_adc + +adi_init_bd_tcl +adi_ip_bd ad_ip_jesd204_tpl_adc "bd/bd.tcl" + +set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/jesd204/jesd204_tpl_adc} [ipx::current_core] + +set cc [ipx::current_core] + +set_property display_name "JESD204 Transport Layer for ADCs" $cc +set_property description "JESD204 Transport Layer for ADCs" $cc + +adi_add_bus "link" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list \ + {"link_ready" "TREADY"} \ + {"link_valid" "TVALID"} \ + {"link_data" "TDATA"} \ + ] +adi_add_bus_clock "link_clk" "link" + +adi_set_ports_dependency "adc_sync_in" "EXT_SYNC == 1" +adi_set_ports_dependency "adc_sync_manual_req_out" "EXT_SYNC == 1" +adi_set_ports_dependency "adc_sync_manual_req_in" "EXT_SYNC == 1" + +foreach {p v} { + "NUM_LANES" "1 2 3 4 6 8 12 16 24 32" \ + "NUM_CHANNELS" "1 2 4 6 8 16 32 64" \ + "BITS_PER_SAMPLE" "8 12 16" \ + "DMA_BITS_PER_SAMPLE" "8 12 16" \ + "CONVERTER_RESOLUTION" "8 11 12 14 16" \ + "SAMPLES_PER_FRAME" "1 2 3 4 6 8 12 16" \ + "OCTETS_PER_BEAT" "4 6 8 12 16 32 64" \ +} { \ + set_property -dict [list \ + "value_validation_type" "list" \ + "value_validation_list" $v \ + ] [ipx::get_user_parameters $p -of_objects $cc] +} + +set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] + +set general_group [ipgui::add_group -name "General Configuration" -component $cc \ + -parent $page0 -display_name "General Configuration"] + +set p [ipgui::get_guiparamspec -name "ID" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $general_group +set_property -dict [list \ + "display_name" "Core ID" \ +] $p + +set framer_group [ipgui::add_group -name "JESD204 Deframer Configuration" -component $cc \ + -parent $page0 -display_name "JESD204 Deframer Cofiguration"] + +set i 0 + +foreach {k v} { \ + "NUM_LANES" "Number of Lanes (L)" \ + "NUM_CHANNELS" "Number of Conveters (M)" \ + "BITS_PER_SAMPLE" "Bits per Sample (N')" \ + "DMA_BITS_PER_SAMPLE" "DMA Bits per Sample" \ + "CONVERTER_RESOLUTION" "Converter Resolution (N)" \ + "SAMPLES_PER_FRAME" "Samples per Frame (S)" \ + "OCTETS_PER_BEAT" "Octets per Beat" \ + } { \ + set p [ipgui::get_guiparamspec -name $k -component $cc] + ipgui::move_param -component $cc -order $i $p -parent $framer_group + set_property -dict [list \ + WIDGET "comboBox" \ + DISPLAY_NAME $v \ + ] $p + incr i +} + +set datapath_group [ipgui::add_group -name "Datapath Configuration" -component $cc \ + -parent $page0 -display_name "Datapath Cofiguration"] + +set i 0 + +foreach {k v w} { + "TWOS_COMPLEMENT" "Use twos complement" "checkBox" \ + "EXT_SYNC" "Enable external sync" "checkBox" \ + "PN7_ENABLE" "Enable PN7" "checkBox" \ + "PN15_ENABLE" "Enable PN15" "checkBox" \ + } { \ + set p [ipgui::get_guiparamspec -name $k -component $cc] + ipgui::move_param -component $cc -order $i $p -parent $datapath_group + set_property -dict [list \ + WIDGET $w \ + DISPLAY_NAME $v \ + ] $p + incr i +} + +adi_add_auto_fpga_spec_params + +ipx::create_xgui_files [ipx::current_core] +ipx::save_core [ipx::current_core] diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v new file mode 100644 index 00000000..88ae6b36 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_pnmon.v @@ -0,0 +1,162 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_ip_jesd204_tpl_adc_pnmon #( + parameter CONVERTER_RESOLUTION = 16, + parameter DATA_PATH_WIDTH = 1, + parameter TWOS_COMPLEMENT = 1, + parameter PN7_ENABLE = 1, + parameter PN15_ENABLE = 1 +) ( + input clk, + + // data interface + input [CONVERTER_RESOLUTION*DATA_PATH_WIDTH-1:0] data, + + // pn out of sync and error + output pn_oos, + output pn_err, + + // processor interface PN9 (0x0), PN23 (0x1), PN7 (0x4), PN15 (0x5) + input [3:0] pn_seq_sel +); + + localparam DW = DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1; + + // Max width of largest PN and data width + localparam PN_W = DW > 22 ? DW : 22; + + // internal registers + reg [PN_W:0] pn_data_pn = 'd0; + + // internal signals + wire [PN_W:0] pn_data_pn_s; + wire [DW:0] pn_data_in_s; + wire [PN_W:0] pn_data_init; + + wire [DW:0] pn23; + wire [DW+23:0] full_state_pn23; + wire [DW:0] pn9; + wire [DW+9:0] full_state_pn9; + wire [DW:0] pn7; + wire [DW+7:0] full_state_pn7; + wire [DW:0] pn15; + wire [DW+15:0] full_state_pn15; + + // pn sequence select + generate if (PN_W > DW) begin + reg [PN_W-DW-1:0] pn_data_in_d = 'd0; + always @(posedge clk) begin + pn_data_in_d <= pn_data_in_s[PN_W-DW-1:0]; + end + assign pn_data_init = {pn_data_in_d, pn_data_in_s}; + end else begin + assign pn_data_init = pn_data_in_s; + end + endgenerate + + assign pn_data_pn_s = (pn_oos == 1'b1) ? pn_data_init : pn_data_pn; + + wire tc = TWOS_COMPLEMENT ? 1'b1 : 1'b0; + + generate + genvar i; + for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: g_pn_swizzle + localparam src_lsb = i * CONVERTER_RESOLUTION; + localparam src_msb = src_lsb + CONVERTER_RESOLUTION - 1; + localparam dst_lsb = (DATA_PATH_WIDTH - i - 1) * CONVERTER_RESOLUTION; + localparam dst_msb = dst_lsb + CONVERTER_RESOLUTION - 1; + + assign pn_data_in_s[dst_msb] = (~tc) ^ data[src_msb]; + assign pn_data_in_s[dst_msb-1:dst_lsb] = data[src_msb-1:src_lsb]; + end + endgenerate + + // PN23 x^23 + x^18 + 1 + assign pn23 = full_state_pn23[23+:DW+1] ^ full_state_pn23[18+:DW+1]; + assign full_state_pn23 = {pn_data_pn_s[22:0],pn23}; + + // PN9 x^9 + x^5 + 1 + assign pn9 = full_state_pn9[9+:DW+1] ^ full_state_pn9[5+:DW+1]; + assign full_state_pn9 = {pn_data_pn_s[8:0],pn9}; + + always @(posedge clk) begin + if (pn_seq_sel == 4'd0) begin + pn_data_pn <= PN_W > DW ? {pn_data_pn[PN_W-DW-1:0],pn9} : pn9; + end else if (pn_seq_sel == 4'd1) begin + pn_data_pn <= PN_W > DW ? {pn_data_pn[PN_W-DW-1:0],pn23} : pn23; + end else if (pn_seq_sel == 4'd4) begin + pn_data_pn <= PN_W > DW ? {pn_data_pn[PN_W-DW-1:0],pn7} : pn7; + end else if (pn_seq_sel == 4'd5) begin + pn_data_pn <= PN_W > DW ? {pn_data_pn[PN_W-DW-1:0],pn15} : pn15; + end + end + + // specific PN sequences + + generate + if(PN7_ENABLE == 'b1) begin + // PN7 x^7 + x^6 + 1 + assign pn7 = full_state_pn7[7+:DW+1] ^ full_state_pn7[6+:DW+1]; + assign full_state_pn7 = {pn_data_pn_s[6:0],pn7}; + end else begin + assign pn7 = 'd0; + assign full_state_pn7 = 'd0; + end + if(PN15_ENABLE == 'b1) begin + // PN15 x^15 + x^14 + 1 + assign pn15 = full_state_pn15[15+:DW+1] ^ full_state_pn15[14+:DW+1]; + assign full_state_pn15 = {pn_data_pn_s[14:0],pn15}; + end else begin + assign pn15 = 'd0; + assign full_state_pn15 = 'd0; + end + endgenerate + + // pn oos & pn err + + ad_pnmon #( + .DATA_WIDTH (DW+1) + ) i_pnmon ( + .adc_clk (clk), + .adc_valid_in (1'b1), + .adc_data_in (pn_data_in_s), + .adc_data_pn (pn_data_pn[DW:0]), + .adc_pn_oos (pn_oos), + .adc_pn_err (pn_err)); + +endmodule diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v new file mode 100644 index 00000000..1b878c8e --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_regmap.v @@ -0,0 +1,366 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_ip_jesd204_tpl_adc_regmap #( + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter NUM_CHANNELS = 1, + parameter DATA_PATH_WIDTH = 1, + parameter NUM_PROFILES = 1, // Number of supported JESD profiles + parameter EXT_SYNC = 0 +) ( + + // axi interface + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [12:0] s_axi_awaddr, + input [2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [12:0] s_axi_araddr, + input [2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + + // control interface + input link_clk, + + // Data format conversion configuration + output [NUM_CHANNELS-1:0] dfmt_enable, + output [NUM_CHANNELS-1:0] dfmt_sign_extend, + output [NUM_CHANNELS-1:0] dfmt_type, + + // PN sequence monitor + output [NUM_CHANNELS*4-1:0] pn_seq_sel, + input [NUM_CHANNELS-1:0] pn_err, + input [NUM_CHANNELS-1:0] pn_oos, + + output [NUM_CHANNELS-1:0] enable, + + input adc_sync_status, + output adc_sync, + output adc_ext_sync_arm, + output adc_ext_sync_disarm, + output adc_ext_sync_manual_req, + output adc_rst, + + // Underflow + input adc_dovf, + + // Deframer interface + input [NUM_PROFILES*8-1: 0] jesd_m, + input [NUM_PROFILES*8-1: 0] jesd_l, + input [NUM_PROFILES*8-1: 0] jesd_s, + input [NUM_PROFILES*8-1: 0] jesd_f, + input [NUM_PROFILES*8-1: 0] jesd_n, + input [NUM_PROFILES*8-1: 0] jesd_np, + + output [$clog2(NUM_PROFILES):0] up_profile_sel +); + + localparam [31:0] CLK_RATIO = DATA_PATH_WIDTH; + + reg up_rack = 1'b0; + reg up_wack = 1'b0; + reg [31:0] up_rdata = 32'h00; + reg [31:0] up_rdata_all; + + reg up_status_pn_err = 1'b0; + reg up_status_pn_oos = 1'b0; + + reg adc_status = 1'b0; + + // internal clocks & resets + wire up_clk; + wire up_rstn; + + wire up_wreq_s; + wire [10:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire [NUM_CHANNELS+1:0] up_wack_s; + wire up_rreq_s; + wire [10:0] up_raddr_s; + wire [31:0] up_rdata_s[0:NUM_CHANNELS+1]; + wire [NUM_CHANNELS+1:0] up_rack_s; + + wire [NUM_CHANNELS-1:0] up_adc_pn_err_s; + wire [NUM_CHANNELS-1:0] up_adc_pn_oos_s; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // status + + always @(posedge link_clk) begin + if (adc_rst == 1'b1) begin + adc_status <= 1'b0; + end else begin + adc_status <= 1'b1; + end + end + + // up bus interface + + up_axi #( + .AXI_ADDRESS_WIDTH (13) + ) i_up_axi ( + .up_clk (up_clk), + .up_rstn (up_rstn), + + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr ({3'b0,s_axi_awaddr}), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr ({3'b0,s_axi_araddr}), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + + integer n; + + always @(*) begin + up_rdata_all = 'h00; + for (n = 0; n <= NUM_CHANNELS+1; n = n + 1) begin + up_rdata_all = up_rdata_all | up_rdata_s[n]; + end + end + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_status_pn_err <= 'd0; + up_status_pn_oos <= 'd0; + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_status_pn_err <= |up_adc_pn_err_s; + up_status_pn_oos <= |up_adc_pn_oos_s; + + up_rdata <= up_rdata_all; + up_rack <= |up_rack_s; + up_wack <= |up_wack_s; + end + end + + // common processor control + // + localparam CONFIG = (EXT_SYNC << 12); + + up_adc_common #( + .COMMON_ID (6'h0), + .ID (ID), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .DRP_DISABLE (1), + .USERPORTS_DISABLE (1), + .GPIO_DISABLE (1), + .START_CODE_DISABLE (1), + .CONFIG (CONFIG) + ) i_up_adc_common ( + .mmcm_rst (), + .adc_clk (link_clk), + .adc_rst (adc_rst), + .adc_r1_mode (), + .adc_ddr_edgesel (), + .adc_pin_mode (), + .adc_status (adc_status), + .adc_sync_status (adc_sync_status), + .adc_status_ovf (adc_dovf), + .adc_clk_ratio (CLK_RATIO), + .adc_start_code (), + .adc_sref_sync (), + .adc_sync (adc_sync), + .adc_ext_sync_arm (adc_ext_sync_arm), + .adc_ext_sync_disarm (adc_ext_sync_disarm), + .adc_ext_sync_manual_req (adc_ext_sync_manual_req), + + .up_status_pn_err (up_status_pn_err), + .up_status_pn_oos (up_status_pn_oos), + .up_status_or (1'b0), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .adc_config_wr (), + .adc_config_ctrl (), + .adc_config_rd ('d0), + .adc_ctrl_status ('d0), + .up_usr_chanmax_out (), + .up_usr_chanmax_in (NUM_CHANNELS), + .up_adc_gpio_in (32'd0), + .up_adc_gpio_out (), + .up_adc_ce (), + .up_pps_rcounter (32'd0), + .up_pps_status (1'b0), + .up_pps_irq_mask (), + + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_wreq (up_wreq_s), + .up_waddr ({3'b0,up_waddr_s}), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq_s), + .up_raddr ({3'b0,up_raddr_s}), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + generate + genvar i; + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel + up_adc_channel #( + .COMMON_ID (6'h1 + i/16), + .CHANNEL_ID (i % 16), + .USERPORTS_DISABLE (1), + .DCFILTER_DISABLE (1), + .IQCORRECTION_DISABLE (1) + ) i_up_adc_channel ( + .adc_clk (link_clk), + .adc_rst (adc_rst), + .adc_enable (enable[i]), + .adc_iqcor_enb (), + .adc_dcfilt_enb (), + .adc_dfmt_enable (dfmt_enable[i]), + .adc_dfmt_se (dfmt_sign_extend[i]), + .adc_dfmt_type (dfmt_type[i]), + .adc_dcfilt_offset (), + .adc_dcfilt_coeff (), + .adc_iqcor_coeff_1 (), + .adc_iqcor_coeff_2 (), + .adc_pnseq_sel (pn_seq_sel[i*4+:4]), + .adc_data_sel (), + .adc_pn_err (pn_err[i]), + .adc_pn_oos (pn_oos[i]), + .adc_or (1'b0), + .adc_usr_datatype_be (1'b0), + .adc_usr_datatype_signed (1'b1), + .adc_usr_datatype_shift (8'd0), + .adc_usr_datatype_total_bits (8'd16), + .adc_usr_datatype_bits (8'd16), + .adc_usr_decimation_m (16'd1), + .adc_usr_decimation_n (16'd1), + + .up_adc_pn_err (up_adc_pn_err_s[i]), + .up_adc_pn_oos (up_adc_pn_oos_s[i]), + .up_adc_or (), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_decimation_m (), + .up_usr_decimation_n (), + + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_wreq (up_wreq_s), + .up_waddr ({3'b0,up_waddr_s}), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[i+1]), + .up_rreq (up_rreq_s), + .up_raddr ({3'b0,up_raddr_s}), + .up_rdata (up_rdata_s[i+1]), + .up_rack (up_rack_s[i+1])); + end + endgenerate + + up_tpl_common #( + .COMMON_ID(2'h0), // Offset of regmap + .NUM_PROFILES(NUM_PROFILES) // Number of JESD profiles + ) i_up_tpl_adc ( + .jesd_m (jesd_m), + .jesd_l (jesd_l), + .jesd_s (jesd_s), + .jesd_f (jesd_f), + .jesd_n (jesd_n), + .jesd_np (jesd_np), + + .up_profile_sel (up_profile_sel), + + // bus interface + .up_clk (up_clk), + .up_rstn (up_rstn), + + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[NUM_CHANNELS+1]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[NUM_CHANNELS+1]), + .up_rack (up_rack_s[NUM_CHANNELS+1])); + +endmodule diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/bd/bd.tcl b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/bd/bd.tcl new file mode 100644 index 00000000..dceb9498 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/bd/bd.tcl @@ -0,0 +1,47 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + DEV_PACKAGE \ + SPEED_GRADE \ + FPGA_FAMILY \ + FPGA_TECHNOLOGY" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/component.xml b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/component.xml new file mode 100644 index 00000000..67232740 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/component.xml @@ -0,0 +1,1450 @@ + + + analog.com + user + ad_ip_jesd204_tpl_adc + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + link + + + + + + + TREADY + + + link_ready + + + + + TVALID + + + link_valid + + + + + TDATA + + + link_data + + + + + + link_signal_clock + link_signal_clock + + + + + + + CLK + + + link_clk + + + + + + ASSOCIATED_BUSIF + link + + + + + + + s_axi + + axi_lite + 0 + 8192 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + ad_ip_jesd204_tpl_adc + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + caecda58 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + ad_ip_jesd204_tpl_adc + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 649450b5 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + b0ef293d + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + + + link_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + link_sof + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + link_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + link_data + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + link_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + enable + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_valid + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_data + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_dovf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_sync_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + adc_sync_manual_req_out + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + adc_sync_manual_req_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + adc_rst + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 12 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_araddr + + in + + 12 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + NUM_LANES + Num Lanes + 1 + + + NUM_CHANNELS + Num Channels + 4 + + + SAMPLES_PER_FRAME + Samples Per Frame + 1 + + + CONVERTER_RESOLUTION + Converter Resolution + 14 + + + BITS_PER_SAMPLE + Bits Per Sample + 16 + + + DMA_BITS_PER_SAMPLE + Dma Bits Per Sample + 16 + + + OCTETS_PER_BEAT + Octets Per Beat + 4 + + + EN_FRAME_ALIGN + En Frame Align + 1 + + + TWOS_COMPLEMENT + Twos Complement + 1 + + + EXT_SYNC + Ext Sync + 0 + + + PN7_ENABLE + Pn7 Enable + 1 + + + PN15_ENABLE + Pn15 Enable + 1 + + + + + + choice_list_6e77d344 + 1 + 2 + 4 + 6 + 8 + 16 + 32 + 64 + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_list_7540484d + 8 + 12 + 16 + + + choice_list_8be817d0 + 4 + 6 + 8 + 12 + 16 + 32 + 64 + + + choice_list_8da0cefa + 8 + 11 + 12 + 14 + 16 + + + choice_list_9840f1e7 + 1 + 2 + 3 + 4 + 6 + 8 + 12 + 16 + 24 + 32 + + + choice_list_eace76f4 + 1 + 2 + 3 + 4 + 6 + 8 + 12 + 16 + + + choice_pairs_00ecfe9a + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + + + choice_pairs_19f99f31 + 0 + 10 + 11 + 12 + 13 + 14 + 20 + 21 + 22 + 23 + 24 + 25 + 30 + + + choice_pairs_28f798a2 + 0 + 1 + 2 + 3 + 4 + + + choice_pairs_fc01a186 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../../xilinx/common/ad_rst_constr.xdc + xdc + + + ../../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../../xilinx/common/up_clock_mon_constr.xdc + xdc + + + ../../common/ad_datafmt.v + verilogSource + + + ad_ip_jesd204_tpl_adc_channel.v + verilogSource + + + ad_ip_jesd204_tpl_adc_core.v + verilogSource + + + ad_ip_jesd204_tpl_adc_deframer.v + verilogSource + + + ad_ip_jesd204_tpl_adc_pnmon.v + verilogSource + + + ad_ip_jesd204_tpl_adc_regmap.v + verilogSource + + + ../../common/ad_perfect_shuffle.v + verilogSource + + + ../../common/ad_pnmon.v + verilogSource + + + ../../common/ad_rst.v + verilogSource + + + ../../common/ad_xcvr_rx_if.v + verilogSource + + + ../../common/up_adc_channel.v + verilogSource + + + ../../common/up_adc_common.v + verilogSource + + + ../../common/up_axi.v + verilogSource + + + ../../common/up_clock_mon.v + verilogSource + + + ../ad_ip_jesd204_tpl_common/up_tpl_common.v + verilogSource + + + ../../common/up_xfer_cntrl.v + verilogSource + + + ../../common/up_xfer_status.v + verilogSource + + + ../../common/util_ext_sync.v + verilogSource + + + ad_ip_jesd204_tpl_adc.v + verilogSource + CHECKSUM_cd763ccf + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../common/ad_datafmt.v + verilogSource + + + ad_ip_jesd204_tpl_adc_channel.v + verilogSource + + + ad_ip_jesd204_tpl_adc_core.v + verilogSource + + + ad_ip_jesd204_tpl_adc_deframer.v + verilogSource + + + ad_ip_jesd204_tpl_adc_pnmon.v + verilogSource + + + ad_ip_jesd204_tpl_adc_regmap.v + verilogSource + + + ../../common/ad_perfect_shuffle.v + verilogSource + + + ../../common/ad_pnmon.v + verilogSource + + + ../../common/ad_rst.v + verilogSource + + + ../../common/ad_xcvr_rx_if.v + verilogSource + + + ../../common/up_adc_channel.v + verilogSource + + + ../../common/up_adc_common.v + verilogSource + + + ../../common/up_axi.v + verilogSource + + + ../../common/up_clock_mon.v + verilogSource + + + ../ad_ip_jesd204_tpl_common/up_tpl_common.v + verilogSource + + + ../../common/up_xfer_cntrl.v + verilogSource + + + ../../common/up_xfer_status.v + verilogSource + + + ../../common/util_ext_sync.v + verilogSource + + + ad_ip_jesd204_tpl_adc.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/ad_ip_jesd204_tpl_adc_v1_0.tcl + tclSource + CHECKSUM_9757f3c3 + XGUI_VERSION_2 + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + JESD204 Transport Layer for ADCs + + + ID + Core ID + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + NUM_LANES + Number of Lanes (L) + 1 + + + NUM_CHANNELS + Number of Conveters (M) + 4 + + + SAMPLES_PER_FRAME + Samples per Frame (S) + 1 + + + CONVERTER_RESOLUTION + Converter Resolution (N) + 14 + + + BITS_PER_SAMPLE + Bits per Sample (N') + 16 + + + DMA_BITS_PER_SAMPLE + DMA Bits per Sample + 16 + + + OCTETS_PER_BEAT + Octets per Beat + 4 + + + EN_FRAME_ALIGN + En Frame Align + 1 + + + TWOS_COMPLEMENT + Use twos complement + 1 + + + EXT_SYNC + Enable external sync + 0 + + + PN7_ENABLE + Enable PN7 + 1 + + + PN15_ENABLE + Enable PN15 + 1 + + + Component_Name + ad_ip_jesd204_tpl_adc_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + JESD204 Transport Layer for ADCs + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/peripherals/jesd204/jesd204_tpl_adc + 1 + 2024-01-14T03:40:08Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/temporary_case_dependencies.mk b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_adc/xgui/ad_ip_jesd204_tpl_adc_v1_0.tcl b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/xgui/ad_ip_jesd204_tpl_adc_v1_0.tcl new file mode 100644 index 00000000..3c75c79f --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_adc/xgui/ad_ip_jesd204_tpl_adc_v1_0.tcl @@ -0,0 +1,277 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "EN_FRAME_ALIGN" -parent ${Page_0} + #Adding Group + set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${Page_0}] + ipgui::add_param $IPINST -name "ID" -parent ${General_Configuration} + + #Adding Group + set JESD204_Deframer_Configuration [ipgui::add_group $IPINST -name "JESD204 Deframer Configuration" -parent ${Page_0} -display_name {JESD204 Deframer Cofiguration}] + ipgui::add_param $IPINST -name "NUM_LANES" -parent ${JESD204_Deframer_Configuration} -widget comboBox + ipgui::add_param $IPINST -name "NUM_CHANNELS" -parent ${JESD204_Deframer_Configuration} -widget comboBox + ipgui::add_param $IPINST -name "BITS_PER_SAMPLE" -parent ${JESD204_Deframer_Configuration} -widget comboBox + ipgui::add_param $IPINST -name "DMA_BITS_PER_SAMPLE" -parent ${JESD204_Deframer_Configuration} -widget comboBox + ipgui::add_param $IPINST -name "CONVERTER_RESOLUTION" -parent ${JESD204_Deframer_Configuration} -widget comboBox + ipgui::add_param $IPINST -name "SAMPLES_PER_FRAME" -parent ${JESD204_Deframer_Configuration} -widget comboBox + ipgui::add_param $IPINST -name "OCTETS_PER_BEAT" -parent ${JESD204_Deframer_Configuration} -widget comboBox + + #Adding Group + set Datapath_Configuration [ipgui::add_group $IPINST -name "Datapath Configuration" -parent ${Page_0} -display_name {Datapath Cofiguration}] + ipgui::add_param $IPINST -name "TWOS_COMPLEMENT" -parent ${Datapath_Configuration} -widget checkBox + ipgui::add_param $IPINST -name "EXT_SYNC" -parent ${Datapath_Configuration} -widget checkBox + ipgui::add_param $IPINST -name "PN7_ENABLE" -parent ${Datapath_Configuration} -widget checkBox + ipgui::add_param $IPINST -name "PN15_ENABLE" -parent ${Datapath_Configuration} -widget checkBox + + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.BITS_PER_SAMPLE { PARAM_VALUE.BITS_PER_SAMPLE } { + # Procedure called to update BITS_PER_SAMPLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BITS_PER_SAMPLE { PARAM_VALUE.BITS_PER_SAMPLE } { + # Procedure called to validate BITS_PER_SAMPLE + return true +} + +proc update_PARAM_VALUE.CONVERTER_RESOLUTION { PARAM_VALUE.CONVERTER_RESOLUTION } { + # Procedure called to update CONVERTER_RESOLUTION when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CONVERTER_RESOLUTION { PARAM_VALUE.CONVERTER_RESOLUTION } { + # Procedure called to validate CONVERTER_RESOLUTION + return true +} + +proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to validate DEV_PACKAGE + return true +} + +proc update_PARAM_VALUE.DMA_BITS_PER_SAMPLE { PARAM_VALUE.DMA_BITS_PER_SAMPLE } { + # Procedure called to update DMA_BITS_PER_SAMPLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_BITS_PER_SAMPLE { PARAM_VALUE.DMA_BITS_PER_SAMPLE } { + # Procedure called to validate DMA_BITS_PER_SAMPLE + return true +} + +proc update_PARAM_VALUE.EN_FRAME_ALIGN { PARAM_VALUE.EN_FRAME_ALIGN } { + # Procedure called to update EN_FRAME_ALIGN when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.EN_FRAME_ALIGN { PARAM_VALUE.EN_FRAME_ALIGN } { + # Procedure called to validate EN_FRAME_ALIGN + return true +} + +proc update_PARAM_VALUE.EXT_SYNC { PARAM_VALUE.EXT_SYNC } { + # Procedure called to update EXT_SYNC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.EXT_SYNC { PARAM_VALUE.EXT_SYNC } { + # Procedure called to validate EXT_SYNC + return true +} + +proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to validate FPGA_FAMILY + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.NUM_CHANNELS { PARAM_VALUE.NUM_CHANNELS } { + # Procedure called to update NUM_CHANNELS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_CHANNELS { PARAM_VALUE.NUM_CHANNELS } { + # Procedure called to validate NUM_CHANNELS + return true +} + +proc update_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } { + # Procedure called to update NUM_LANES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } { + # Procedure called to validate NUM_LANES + return true +} + +proc update_PARAM_VALUE.OCTETS_PER_BEAT { PARAM_VALUE.OCTETS_PER_BEAT } { + # Procedure called to update OCTETS_PER_BEAT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OCTETS_PER_BEAT { PARAM_VALUE.OCTETS_PER_BEAT } { + # Procedure called to validate OCTETS_PER_BEAT + return true +} + +proc update_PARAM_VALUE.PN15_ENABLE { PARAM_VALUE.PN15_ENABLE } { + # Procedure called to update PN15_ENABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PN15_ENABLE { PARAM_VALUE.PN15_ENABLE } { + # Procedure called to validate PN15_ENABLE + return true +} + +proc update_PARAM_VALUE.PN7_ENABLE { PARAM_VALUE.PN7_ENABLE } { + # Procedure called to update PN7_ENABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PN7_ENABLE { PARAM_VALUE.PN7_ENABLE } { + # Procedure called to validate PN7_ENABLE + return true +} + +proc update_PARAM_VALUE.SAMPLES_PER_FRAME { PARAM_VALUE.SAMPLES_PER_FRAME } { + # Procedure called to update SAMPLES_PER_FRAME when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SAMPLES_PER_FRAME { PARAM_VALUE.SAMPLES_PER_FRAME } { + # Procedure called to validate SAMPLES_PER_FRAME + return true +} + +proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to validate SPEED_GRADE + return true +} + +proc update_PARAM_VALUE.TWOS_COMPLEMENT { PARAM_VALUE.TWOS_COMPLEMENT } { + # Procedure called to update TWOS_COMPLEMENT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TWOS_COMPLEMENT { PARAM_VALUE.TWOS_COMPLEMENT } { + # Procedure called to validate TWOS_COMPLEMENT + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY} +} + +proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE} +} + +proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE} +} + +proc update_MODELPARAM_VALUE.NUM_LANES { MODELPARAM_VALUE.NUM_LANES PARAM_VALUE.NUM_LANES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_LANES}] ${MODELPARAM_VALUE.NUM_LANES} +} + +proc update_MODELPARAM_VALUE.NUM_CHANNELS { MODELPARAM_VALUE.NUM_CHANNELS PARAM_VALUE.NUM_CHANNELS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_CHANNELS}] ${MODELPARAM_VALUE.NUM_CHANNELS} +} + +proc update_MODELPARAM_VALUE.SAMPLES_PER_FRAME { MODELPARAM_VALUE.SAMPLES_PER_FRAME PARAM_VALUE.SAMPLES_PER_FRAME } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SAMPLES_PER_FRAME}] ${MODELPARAM_VALUE.SAMPLES_PER_FRAME} +} + +proc update_MODELPARAM_VALUE.CONVERTER_RESOLUTION { MODELPARAM_VALUE.CONVERTER_RESOLUTION PARAM_VALUE.CONVERTER_RESOLUTION } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CONVERTER_RESOLUTION}] ${MODELPARAM_VALUE.CONVERTER_RESOLUTION} +} + +proc update_MODELPARAM_VALUE.BITS_PER_SAMPLE { MODELPARAM_VALUE.BITS_PER_SAMPLE PARAM_VALUE.BITS_PER_SAMPLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BITS_PER_SAMPLE}] ${MODELPARAM_VALUE.BITS_PER_SAMPLE} +} + +proc update_MODELPARAM_VALUE.DMA_BITS_PER_SAMPLE { MODELPARAM_VALUE.DMA_BITS_PER_SAMPLE PARAM_VALUE.DMA_BITS_PER_SAMPLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_BITS_PER_SAMPLE}] ${MODELPARAM_VALUE.DMA_BITS_PER_SAMPLE} +} + +proc update_MODELPARAM_VALUE.OCTETS_PER_BEAT { MODELPARAM_VALUE.OCTETS_PER_BEAT PARAM_VALUE.OCTETS_PER_BEAT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OCTETS_PER_BEAT}] ${MODELPARAM_VALUE.OCTETS_PER_BEAT} +} + +proc update_MODELPARAM_VALUE.EN_FRAME_ALIGN { MODELPARAM_VALUE.EN_FRAME_ALIGN PARAM_VALUE.EN_FRAME_ALIGN } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.EN_FRAME_ALIGN}] ${MODELPARAM_VALUE.EN_FRAME_ALIGN} +} + +proc update_MODELPARAM_VALUE.TWOS_COMPLEMENT { MODELPARAM_VALUE.TWOS_COMPLEMENT PARAM_VALUE.TWOS_COMPLEMENT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TWOS_COMPLEMENT}] ${MODELPARAM_VALUE.TWOS_COMPLEMENT} +} + +proc update_MODELPARAM_VALUE.EXT_SYNC { MODELPARAM_VALUE.EXT_SYNC PARAM_VALUE.EXT_SYNC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.EXT_SYNC}] ${MODELPARAM_VALUE.EXT_SYNC} +} + +proc update_MODELPARAM_VALUE.PN7_ENABLE { MODELPARAM_VALUE.PN7_ENABLE PARAM_VALUE.PN7_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PN7_ENABLE}] ${MODELPARAM_VALUE.PN7_ENABLE} +} + +proc update_MODELPARAM_VALUE.PN15_ENABLE { MODELPARAM_VALUE.PN15_ENABLE PARAM_VALUE.PN15_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PN15_ENABLE}] ${MODELPARAM_VALUE.PN15_ENABLE} +} + diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v b/adi_library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v new file mode 100644 index 00000000..f0d8de0d --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v @@ -0,0 +1,137 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module up_tpl_common #( + + // parameters + parameter COMMON_ID = 2'h0, // Offset of regmap + parameter NUM_PROFILES = 1 // Number of JESD profiles +) ( + input [NUM_PROFILES*8-1: 0] jesd_m, + input [NUM_PROFILES*8-1: 0] jesd_l, + input [NUM_PROFILES*8-1: 0] jesd_s, + input [NUM_PROFILES*8-1: 0] jesd_f, + input [NUM_PROFILES*8-1: 0] jesd_n, + input [NUM_PROFILES*8-1: 0] jesd_np, + + output reg [$clog2(NUM_PROFILES):0] up_profile_sel = 'h0, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [10:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [10:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // internal registers + reg up_rack_int = 'd0; + reg up_wack_int = 'd0; + reg [31:0] up_rdata_int = 'd0; + + // internal signals + wire up_wreq_s; + wire up_rreq_s; + reg [31:0] up_rdata_jesd_params; + + // decode block select + + assign up_wreq_s = (up_waddr[10:7] == {COMMON_ID,1'b1}) ? up_wreq : 1'b0; + assign up_rreq_s = (up_raddr[10:7] == {COMMON_ID,1'b1}) ? up_rreq : 1'b0; + + // processor write interface + + assign up_wack = up_wack_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack_int <= 'd0; + up_profile_sel <= 'd0; + end else begin + up_wack_int <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h00)) begin + up_profile_sel <= up_wdata[$clog2(NUM_PROFILES):0]; + end + end + end + + // processor read interface + + assign up_rack = up_rack_int; + assign up_rdata = up_rdata_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack_int <= 'd0; + up_rdata_int <= 'd0; + end else begin + up_rack_int <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr[6:0]) + 7'h00: up_rdata_int <= up_profile_sel; + 7'h01: up_rdata_int <= NUM_PROFILES; + default: up_rdata_int <= up_rdata_jesd_params; + endcase + end else begin + up_rdata_int <= 32'd0; + end + end + end + + integer i; + always @(*) begin + for (i=0; i + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9136.qprs b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9136.qprs new file mode 100644 index 00000000..28504256 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9136.qprs @@ -0,0 +1,57 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9144.qprs b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9144.qprs new file mode 100644 index 00000000..79f9572c --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9144.qprs @@ -0,0 +1,93 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9152.qprs b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9152.qprs new file mode 100644 index 00000000..a2c811e1 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9152.qprs @@ -0,0 +1,57 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9154.qprs b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9154.qprs new file mode 100644 index 00000000..c90664f5 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9154.qprs @@ -0,0 +1,93 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9161.qprs b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9161.qprs new file mode 100644 index 00000000..7b0695b3 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9161.qprs @@ -0,0 +1,57 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9162.qprs b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9162.qprs new file mode 100644 index 00000000..e3c051a0 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9162.qprs @@ -0,0 +1,57 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9163.qprs b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9163.qprs new file mode 100644 index 00000000..81f5d2c2 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9163.qprs @@ -0,0 +1,57 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9164.qprs b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9164.qprs new file mode 100644 index 00000000..ea51138a --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9164.qprs @@ -0,0 +1,57 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9171.qprs b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9171.qprs new file mode 100644 index 00000000..78599ecc --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9171.qprs @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9172.qprs b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9172.qprs new file mode 100644 index 00000000..18b45c9e --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9172.qprs @@ -0,0 +1,156 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9173.qprs b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9173.qprs new file mode 100644 index 00000000..e652b1a4 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/AD9173.qprs @@ -0,0 +1,138 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/Makefile b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/Makefile new file mode 100644 index 00000000..4ae28df1 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/Makefile @@ -0,0 +1,49 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := ad_ip_jesd204_tpl_dac + +GENERIC_DEPS += ../../common/ad_dds.v +GENERIC_DEPS += ../../common/ad_dds_1.v +GENERIC_DEPS += ../../common/ad_dds_2.v +GENERIC_DEPS += ../../common/ad_dds_cordic_pipe.v +GENERIC_DEPS += ../../common/ad_dds_sine.v +GENERIC_DEPS += ../../common/ad_dds_sine_cordic.v +GENERIC_DEPS += ../../common/ad_iqcor.v +GENERIC_DEPS += ../../common/ad_mux.v +GENERIC_DEPS += ../../common/ad_mux_core.v +GENERIC_DEPS += ../../common/ad_perfect_shuffle.v +GENERIC_DEPS += ../../common/ad_rst.v +GENERIC_DEPS += ../../common/up_axi.v +GENERIC_DEPS += ../../common/up_clock_mon.v +GENERIC_DEPS += ../../common/up_dac_channel.v +GENERIC_DEPS += ../../common/up_dac_common.v +GENERIC_DEPS += ../../common/up_xfer_cntrl.v +GENERIC_DEPS += ../../common/up_xfer_status.v +GENERIC_DEPS += ../../common/util_ext_sync.v +GENERIC_DEPS += ../ad_ip_jesd204_tpl_common/up_tpl_common.v +GENERIC_DEPS += ad_ip_jesd204_tpl_dac.v +GENERIC_DEPS += ad_ip_jesd204_tpl_dac_channel.v +GENERIC_DEPS += ad_ip_jesd204_tpl_dac_core.v +GENERIC_DEPS += ad_ip_jesd204_tpl_dac_framer.v +GENERIC_DEPS += ad_ip_jesd204_tpl_dac_pn.v +GENERIC_DEPS += ad_ip_jesd204_tpl_dac_regmap.v + +XILINX_DEPS += ../../xilinx/common/ad_mul.v +XILINX_DEPS += ../../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += ../../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += ../../xilinx/common/up_xfer_cntrl_constr.xdc +XILINX_DEPS += ../../xilinx/common/up_xfer_status_constr.xdc +XILINX_DEPS += ad_ip_jesd204_tpl_dac_ip.tcl + +INTEL_DEPS += ../../intel/common/ad_mul.v +INTEL_DEPS += ../../intel/common/up_clock_mon_constr.sdc +INTEL_DEPS += ../../intel/common/up_rst_constr.sdc +INTEL_DEPS += ../../intel/common/up_xfer_cntrl_constr.sdc +INTEL_DEPS += ../../intel/common/up_xfer_status_constr.sdc +INTEL_DEPS += ad_ip_jesd204_tpl_dac_hw.tcl + +include ../../scripts/library.mk diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v new file mode 100644 index 00000000..da0a973d --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v @@ -0,0 +1,291 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_ip_jesd204_tpl_dac #( + parameter ID = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter NUM_LANES = 4, + parameter NUM_CHANNELS = 2, + parameter SAMPLES_PER_FRAME = 1, + parameter CONVERTER_RESOLUTION = 16, // JESD_N + parameter BITS_PER_SAMPLE = 16, // JESD_NP + parameter DMA_BITS_PER_SAMPLE = 16, + parameter PADDING_TO_MSB_LSB_N = 0, + parameter OCTETS_PER_BEAT = 4, + parameter DDS_TYPE = 1, + parameter DDS_CORDIC_DW = 16, + parameter DDS_CORDIC_PHASE_DW = 16, + parameter DDS_PHASE_DW = 16, + parameter DATAPATH_DISABLE = 0, + parameter IQCORRECTION_DISABLE = 1, + parameter EXT_SYNC = 0, + parameter XBAR_ENABLE = 0 +) ( + + // jesd interface + // link_clk is (line-rate/40) + + input link_clk, + output link_valid, + input link_ready, + output [NUM_LANES*8*OCTETS_PER_BEAT-1:0] link_data, + + // dma interface + output [NUM_CHANNELS-1:0] enable, + + output [NUM_CHANNELS-1:0] dac_valid, + input [DMA_BITS_PER_SAMPLE * OCTETS_PER_BEAT * 8 * NUM_LANES / BITS_PER_SAMPLE-1:0] dac_ddata, + input dac_dunf, + + output dac_rst, + + // external sync, should be on the link_clk clock domain + + input dac_sync_in, + output dac_sync_manual_req_out, + input dac_sync_manual_req_in, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + + input s_axi_awvalid, + output s_axi_awready, + input [12:0] s_axi_awaddr, + input [2:0] s_axi_awprot, + + input s_axi_wvalid, + output s_axi_wready, + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + + output s_axi_bvalid, + input s_axi_bready, + output [1:0] s_axi_bresp, + + input s_axi_arvalid, + output s_axi_arready, + input [12:0] s_axi_araddr, + input [2:0] s_axi_arprot, + + output s_axi_rvalid, + input s_axi_rready, + output [31:0] s_axi_rdata, + output [1:0] s_axi_rresp +); + + localparam DATA_PATH_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES / NUM_CHANNELS / BITS_PER_SAMPLE; + localparam LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8; + localparam DMA_DATA_WIDTH = DMA_BITS_PER_SAMPLE * DATA_PATH_WIDTH * NUM_CHANNELS; + + localparam BYTES_PER_FRAME = (NUM_CHANNELS * BITS_PER_SAMPLE * SAMPLES_PER_FRAME) / ( 8 * NUM_LANES); + + // internal signals + + wire dac_sync; + wire dac_ext_sync_arm; + wire dac_sync_in_status; + wire dac_dds_format; + + wire [NUM_CHANNELS*16-1:0] dac_dds_scale_0_s; + wire [NUM_CHANNELS*16-1:0] dac_dds_scale_1_s; + wire [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_init_0_s; + wire [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_incr_0_s; + wire [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_init_1_s; + wire [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_incr_1_s; + wire [NUM_CHANNELS*16-1:0] dac_pat_data_0_s; + wire [NUM_CHANNELS*16-1:0] dac_pat_data_1_s; + wire [NUM_CHANNELS*4-1:0] dac_data_sel_s; + wire [NUM_CHANNELS-1:0] dac_mask_enable_s; + wire [NUM_CHANNELS-1:0] dac_iqcor_enb; + wire [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_1; + wire [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_2; + wire [NUM_CHANNELS*8-1:0] dac_src_chan_sel; + + reg [LINK_DATA_WIDTH-1:0] dac_ddata_cr; + + // regmap + + ad_ip_jesd204_tpl_dac_regmap #( + .ID (ID), + .DATAPATH_DISABLE (DATAPATH_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE), + .XBAR_ENABLE (XBAR_ENABLE), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .NUM_CHANNELS (NUM_CHANNELS), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .PADDING_TO_MSB_LSB_N (PADDING_TO_MSB_LSB_N), + .NUM_PROFILES(1), + .EXT_SYNC (EXT_SYNC), + .DDS_PHASE_DW (DDS_PHASE_DW) + ) i_regmap ( + .s_axi_aclk (s_axi_aclk), + .s_axi_aresetn (s_axi_aresetn), + + .s_axi_awvalid (s_axi_awvalid), + .s_axi_awready (s_axi_awready), + .s_axi_awaddr (s_axi_awaddr), + .s_axi_awprot (s_axi_awprot), + .s_axi_wvalid (s_axi_wvalid), + .s_axi_wready (s_axi_wready), + .s_axi_wdata (s_axi_wdata), + .s_axi_wstrb (s_axi_wstrb), + .s_axi_bvalid (s_axi_bvalid), + .s_axi_bready (s_axi_bready), + .s_axi_bresp (s_axi_bresp), + .s_axi_arvalid (s_axi_arvalid), + .s_axi_arready (s_axi_arready), + .s_axi_araddr (s_axi_araddr), + .s_axi_arprot (s_axi_arprot), + .s_axi_rvalid (s_axi_rvalid), + .s_axi_rresp (s_axi_rresp), + .s_axi_rdata (s_axi_rdata), + .s_axi_rready (s_axi_rready), + + .link_clk (link_clk), + + .dac_dunf (dac_dunf), + + .dac_sync (dac_sync), + .dac_ext_sync_arm (dac_ext_sync_arm), + .dac_ext_sync_disarm (dac_ext_sync_disarm), + .dac_ext_sync_manual_req (dac_sync_manual_req_out), + .dac_sync_in_status (dac_sync_in_status), + .dac_dds_format (dac_dds_format), + + .dac_dds_scale_0 (dac_dds_scale_0_s), + .dac_dds_init_0 (dac_dds_init_0_s), + .dac_dds_incr_0 (dac_dds_incr_0_s), + .dac_dds_scale_1 (dac_dds_scale_1_s), + .dac_dds_init_1 (dac_dds_init_1_s), + .dac_dds_incr_1 (dac_dds_incr_1_s), + .dac_pat_data_0 (dac_pat_data_0_s), + .dac_pat_data_1 (dac_pat_data_1_s), + .dac_data_sel (dac_data_sel_s), + .dac_mask_enable (dac_mask_enable_s), + + .dac_iqcor_enb (dac_iqcor_enb), + .dac_iqcor_coeff_1 (dac_iqcor_coeff_1), + .dac_iqcor_coeff_2 (dac_iqcor_coeff_2), + + .dac_src_chan_sel (dac_src_chan_sel), + + .jesd_m (NUM_CHANNELS), + .jesd_l (NUM_LANES), + .jesd_s (SAMPLES_PER_FRAME), + .jesd_f (BYTES_PER_FRAME), + .jesd_n (CONVERTER_RESOLUTION), + .jesd_np (BITS_PER_SAMPLE), + .up_profile_sel ()); + + // core + + ad_ip_jesd204_tpl_dac_core #( + .DATAPATH_DISABLE (DATAPATH_DISABLE), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE), + .XBAR_ENABLE (XBAR_ENABLE), + .NUM_LANES (NUM_LANES), + .NUM_CHANNELS (NUM_CHANNELS), + .BITS_PER_SAMPLE (BITS_PER_SAMPLE), + .CONVERTER_RESOLUTION (CONVERTER_RESOLUTION), + .SAMPLES_PER_FRAME (SAMPLES_PER_FRAME), + .OCTETS_PER_BEAT (OCTETS_PER_BEAT), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .LINK_DATA_WIDTH (LINK_DATA_WIDTH), + .DDS_TYPE (DDS_TYPE), + .DDS_CORDIC_DW (DDS_CORDIC_DW), + .DDS_CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW), + .DDS_PHASE_DW (DDS_PHASE_DW), + .EXT_SYNC (EXT_SYNC) + ) i_core ( + .clk (link_clk), + + .link_valid (link_valid), + .link_ready (link_ready), + .link_data (link_data), + + .enable (enable), + + .dac_valid (dac_valid), + .dac_ddata (dac_ddata_cr), + .dac_rst (dac_rst), + + .dac_sync (dac_sync), + .dac_ext_sync_arm (dac_ext_sync_arm), + .dac_ext_sync_disarm (dac_ext_sync_disarm), + .dac_sync_in_status (dac_sync_in_status), + .dac_sync_in (dac_sync_in), + .dac_sync_manual_req (dac_sync_manual_req_in), + .dac_dds_format (dac_dds_format), + + .dac_dds_scale_0 (dac_dds_scale_0_s), + .dac_dds_init_0 (dac_dds_init_0_s), + .dac_dds_incr_0 (dac_dds_incr_0_s), + .dac_dds_scale_1 (dac_dds_scale_1_s), + .dac_dds_init_1 (dac_dds_init_1_s), + .dac_dds_incr_1 (dac_dds_incr_1_s), + .dac_pat_data_0 (dac_pat_data_0_s), + .dac_pat_data_1 (dac_pat_data_1_s), + .dac_data_sel (dac_data_sel_s), + .dac_mask_enable (dac_mask_enable_s), + + .dac_iqcor_enb (dac_iqcor_enb), + .dac_iqcor_coeff_1 (dac_iqcor_coeff_1), + .dac_iqcor_coeff_2 (dac_iqcor_coeff_2), + + .dac_src_chan_sel (dac_src_chan_sel)); + + // Drop DMA padding bits from the LSB or MSB based on configuration + integer i; + always @(*) begin + for (i=0;i + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v new file mode 100644 index 00000000..287a973e --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v @@ -0,0 +1,181 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_ip_jesd204_tpl_dac_channel #( + parameter DATAPATH_DISABLE = 0, + parameter IQCORRECTION_DISABLE = 1, + parameter DATA_PATH_WIDTH = 4, + parameter CONVERTER_RESOLUTION = 16, + parameter BITS_PER_SAMPLE = 16, + parameter DDS_TYPE = 1, + parameter DDS_CORDIC_DW = 16, + parameter DDS_CORDIC_PHASE_DW = 16, + parameter DDS_PHASE_DW = 16, + parameter Q_OR_I_N = 0 +) ( + + // dac interface + + input clk, + + input [DATA_PATH_WIDTH*BITS_PER_SAMPLE-1:0] dma_data, + output reg [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] dac_data = 'h00, + + // PN data + + input [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] pn7_data, + input [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] pn15_data, + + // Configuration + + input dac_data_sync, + input dac_dds_format, + + input [3:0] dac_data_sel, + input dac_mask_enable, + + input [15:0] dac_dds_scale_0, + input [15:0] dac_dds_scale_1, + input [DDS_PHASE_DW-1:0] dac_dds_init_0, + input [DDS_PHASE_DW-1:0] dac_dds_incr_0, + input [DDS_PHASE_DW-1:0] dac_dds_init_1, + input [DDS_PHASE_DW-1:0] dac_dds_incr_1, + + input [15:0] dac_pat_data_0, + input [15:0] dac_pat_data_1, + + input dac_iqcor_enb, + input [15:0] dac_iqcor_coeff_1, + input [15:0] dac_iqcor_coeff_2, + + input [DATA_PATH_WIDTH*BITS_PER_SAMPLE-1:0] dac_iqcor_data_in, + + output reg dac_enable = 1'b0 +); + + localparam CR = CONVERTER_RESOLUTION; + localparam CHANNEL_DATA_WIDTH = DATA_PATH_WIDTH * CR; + + // internal signals + + wire [CHANNEL_DATA_WIDTH-1:0] dac_dds_data_s; + wire [CHANNEL_DATA_WIDTH-1:0] dac_dma_data_s; + wire [CHANNEL_DATA_WIDTH-1:0] dac_pat_data_s; + wire [CHANNEL_DATA_WIDTH-1:0] dac_iqcor_data_s; + + generate + if (DATA_PATH_WIDTH > 1) begin + assign dac_pat_data_s = {DATA_PATH_WIDTH/2{dac_pat_data_1[0+:CR],dac_pat_data_0[0+:CR]}}; + end else begin + reg dac_pat_data_sel = 1'b0; + + always @(posedge clk) begin + if (dac_data_sync == 1'b1) begin + dac_pat_data_sel <= 1'b0; + end else begin + dac_pat_data_sel <= ~dac_pat_data_sel; + end + end + + assign dac_pat_data_s = dac_pat_data_sel == 1'b0 ? + dac_pat_data_0[0+:CR] : dac_pat_data_1[0+:CR]; + end + + genvar i; + /* Data is expected to be LSB aligned, drop unused MSBs */ + for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: g_dac_dma_data + assign dac_dma_data_s[CR*i+:CR] = dma_data[BITS_PER_SAMPLE*i+:CR]; + end + endgenerate + + ad_iqcor #( + .Q_OR_I_N (Q_OR_I_N), + .DISABLE (IQCORRECTION_DISABLE), + .CR (CR), + .DPW (DATA_PATH_WIDTH) + ) i_ad_iqcor ( + .clk (clk), + .valid (1'b1), + .data_in (dac_dma_data_s), + .data_iq (dac_iqcor_data_in), + .valid_out (), + .data_out (dac_iqcor_data_s), + .iqcor_enable (dac_iqcor_enb), + .iqcor_coeff_1 (dac_iqcor_coeff_1), + .iqcor_coeff_2 (dac_iqcor_coeff_2)); + + // dac data select + + always @(posedge clk) begin + dac_enable <= dac_mask_enable ? 1'b0 : (dac_data_sel == 4'h2); + casex ({dac_mask_enable,dac_data_sel}) + 5'h07: dac_data <= pn15_data; + 5'h06: dac_data <= pn7_data; + 5'h05: dac_data <= ~pn15_data; + 5'h04: dac_data <= ~pn7_data; + 5'h03: dac_data <= 'h00; + 5'h02: dac_data <= dac_iqcor_data_s; + 5'h01: dac_data <= dac_pat_data_s; + 5'h1x: dac_data <= dac_iqcor_data_s; + default: dac_data <= dac_dds_data_s; + endcase + end + + // dds + + ad_dds #( + .DISABLE (DATAPATH_DISABLE), + .DDS_DW (CONVERTER_RESOLUTION), + .PHASE_DW (DDS_PHASE_DW), + .DDS_TYPE (DDS_TYPE), + .CORDIC_DW (DDS_CORDIC_DW), + .CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW), + .CLK_RATIO (DATA_PATH_WIDTH) + ) i_dds ( + .clk (clk), + .dac_dds_format (dac_dds_format), + .dac_data_sync (dac_data_sync), + .dac_valid (1'b1), + .tone_1_scale (dac_dds_scale_0), + .tone_2_scale (dac_dds_scale_1), + .tone_1_init_offset (dac_dds_init_0), + .tone_2_init_offset (dac_dds_init_1), + .tone_1_freq_word (dac_dds_incr_0), + .tone_2_freq_word (dac_dds_incr_1), + .dac_dds_data (dac_dds_data_s)); + +endmodule diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v new file mode 100644 index 00000000..f5e979f9 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v @@ -0,0 +1,234 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_ip_jesd204_tpl_dac_core #( + parameter DATAPATH_DISABLE = 0, + parameter IQCORRECTION_DISABLE = 1, + parameter XBAR_ENABLE = 1, + parameter NUM_LANES = 1, + parameter NUM_CHANNELS = 1, + parameter BITS_PER_SAMPLE = 16, + parameter CONVERTER_RESOLUTION = 16, + parameter SAMPLES_PER_FRAME = 1, + parameter OCTETS_PER_BEAT = 4, + parameter DATA_PATH_WIDTH = 4, + parameter LINK_DATA_WIDTH = NUM_LANES * OCTETS_PER_BEAT * 8, + parameter DDS_TYPE = 1, + parameter DDS_CORDIC_DW = 16, + parameter DDS_CORDIC_PHASE_DW = 16, + parameter DDS_PHASE_DW = 16, + parameter EXT_SYNC = 0 +) ( + + // dac interface + input clk, + + output link_valid, + input link_ready, + output [LINK_DATA_WIDTH-1:0] link_data, + + // dma interface + output [NUM_CHANNELS-1:0] dac_valid, + input [LINK_DATA_WIDTH-1:0] dac_ddata, + output dac_rst, + + // Configuration interface + + input dac_sync, + input dac_ext_sync_arm, + input dac_ext_sync_disarm, + + input dac_sync_in, + input dac_sync_manual_req, + + output dac_sync_in_status, + + input dac_dds_format, + + input [NUM_CHANNELS*4-1:0] dac_data_sel, + input [NUM_CHANNELS-1:0] dac_mask_enable, + + input [NUM_CHANNELS*16-1:0] dac_dds_scale_0, + input [NUM_CHANNELS*16-1:0] dac_dds_scale_1, + input [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_init_0, + input [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_incr_0, + input [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_init_1, + input [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_incr_1, + + input [NUM_CHANNELS*16-1:0] dac_pat_data_0, + input [NUM_CHANNELS*16-1:0] dac_pat_data_1, + + input [NUM_CHANNELS-1:0] dac_iqcor_enb, + input [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_1, + input [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_2, + + input [NUM_CHANNELS*8-1:0] dac_src_chan_sel, + + output [NUM_CHANNELS-1:0] enable +); + + localparam DAC_CDW = CONVERTER_RESOLUTION * DATA_PATH_WIDTH; + localparam DAC_DATA_WIDTH = DAC_CDW * NUM_CHANNELS; + + wire [DAC_DATA_WIDTH-1:0] dac_data_s; + wire [DAC_DATA_WIDTH-1:0] dac_ddata_muxed; + + wire [DAC_CDW-1:0] pn7_data; + wire [DAC_CDW-1:0] pn15_data; + + wire [LINK_DATA_WIDTH-1:0] dac_ddata_int; + + assign link_valid = 1'b1; + assign dac_sync_in_status = dac_sync_armed; + + util_ext_sync #( + .ENABLED (EXT_SYNC) + ) i_util_ext_sync ( + .clk (clk), + .ext_sync_arm (dac_ext_sync_arm), + .ext_sync_disarm (dac_ext_sync_disarm), + .sync_in (dac_sync_in | dac_sync_manual_req), + .sync_armed (dac_sync_armed)); + + // Sync either from external or software source + assign dac_sync_int = dac_sync_armed | dac_sync; + + // device interface + + ad_ip_jesd204_tpl_dac_framer #( + .NUM_LANES (NUM_LANES), + .NUM_CHANNELS (NUM_CHANNELS), + .BITS_PER_SAMPLE (BITS_PER_SAMPLE), + .CONVERTER_RESOLUTION (CONVERTER_RESOLUTION), + .SAMPLES_PER_FRAME (SAMPLES_PER_FRAME), + .OCTETS_PER_BEAT (OCTETS_PER_BEAT), + .LINK_DATA_WIDTH (LINK_DATA_WIDTH), + .DAC_DATA_WIDTH (DAC_DATA_WIDTH) + ) i_framer ( + .link_data (link_data), + .dac_data (dac_data_s)); + + // PN generator + ad_ip_jesd204_tpl_dac_pn #( + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CONVERTER_RESOLUTION (CONVERTER_RESOLUTION) + ) i_pn_gen ( + .clk (clk), + .reset (dac_sync_int), + + .pn7_data (pn7_data), + .pn15_data (pn15_data)); + + // dac valid + + assign dac_valid = {NUM_CHANNELS{~dac_sync_armed}}; + assign dac_rst = dac_sync_armed; + + // Gate input data + assign dac_ddata_int = dac_sync_armed ? {LINK_DATA_WIDTH{1'b0}} : dac_ddata; + + generate + genvar i; + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel + + // Find the pair of the current channel for I/Q channels + // Assuming even channels are I, odd channels are Q + // Assuming channel count is even other case do not pair channels + localparam IQ_PAIR_CH_INDEX = (NUM_CHANNELS%2) ? i : + (i%2) ? i-1 : i+1; + + if (XBAR_ENABLE == 1) begin + + // NUM_CHANNELS : 1 mux + ad_mux #( + .CH_W (DAC_CDW), + .CH_CNT (NUM_CHANNELS), + .EN_REG (1) + ) channel_mux ( + .clk (clk), + .data_in (dac_ddata_int), + .ch_sel (dac_src_chan_sel[8*i+:8]), + .data_out (dac_ddata_muxed[DAC_CDW*i+:DAC_CDW])); + + end else begin + assign dac_ddata_muxed[DAC_CDW*i+:DAC_CDW] = dac_ddata_int[DAC_CDW*i+:DAC_CDW]; + end + + ad_ip_jesd204_tpl_dac_channel #( + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CONVERTER_RESOLUTION (CONVERTER_RESOLUTION), + .DATAPATH_DISABLE (DATAPATH_DISABLE), + .BITS_PER_SAMPLE (BITS_PER_SAMPLE), + .DDS_TYPE (DDS_TYPE), + .DDS_CORDIC_DW (DDS_CORDIC_DW), + .DDS_CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW), + .DDS_PHASE_DW (DDS_PHASE_DW), + .IQCORRECTION_DISABLE(IQCORRECTION_DISABLE), + .Q_OR_I_N(i%2) + ) i_channel ( + .clk (clk), + .dac_enable (enable[i]), + .dac_data (dac_data_s[DAC_CDW*i+:DAC_CDW]), + .dma_data (dac_ddata_muxed[DAC_CDW*i+:DAC_CDW]), + + .pn7_data (pn7_data), + .pn15_data (pn15_data), + + .dac_data_sync (dac_sync_int), + .dac_dds_format (dac_dds_format), + + .dac_data_sel (dac_data_sel[4*i+:4]), + .dac_mask_enable (dac_mask_enable[i]), + + .dac_dds_scale_0 (dac_dds_scale_0[16*i+:16]), + .dac_dds_scale_1 (dac_dds_scale_1[16*i+:16]), + .dac_dds_init_0 (dac_dds_init_0[DDS_PHASE_DW*i+:DDS_PHASE_DW]), + .dac_dds_incr_0 (dac_dds_incr_0[DDS_PHASE_DW*i+:DDS_PHASE_DW]), + .dac_dds_init_1 (dac_dds_init_1[DDS_PHASE_DW*i+:DDS_PHASE_DW]), + .dac_dds_incr_1 (dac_dds_incr_1[DDS_PHASE_DW*i+:DDS_PHASE_DW]), + + .dac_pat_data_0 (dac_pat_data_0[16*i+:16]), + .dac_pat_data_1 (dac_pat_data_1[16*i+:16]), + + .dac_iqcor_enb (dac_iqcor_enb[i]), + .dac_iqcor_coeff_1 (dac_iqcor_coeff_1[16*i+:16]), + .dac_iqcor_coeff_2 (dac_iqcor_coeff_2[16*i+:16]), + .dac_iqcor_data_in (dac_ddata_muxed[DAC_CDW*IQ_PAIR_CH_INDEX+:DAC_CDW])); + end + endgenerate + +endmodule diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v new file mode 100644 index 00000000..242c1f4e --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_framer.v @@ -0,0 +1,156 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_ip_jesd204_tpl_dac_framer #( + parameter NUM_LANES = 8, + parameter NUM_CHANNELS = 4, + parameter BITS_PER_SAMPLE = 16, + parameter CONVERTER_RESOLUTION = 16, + parameter SAMPLES_PER_FRAME = 2, + parameter OCTETS_PER_BEAT = 4, + parameter LINK_DATA_WIDTH = OCTETS_PER_BEAT * 8 * NUM_LANES, + parameter DAC_DATA_WIDTH = LINK_DATA_WIDTH * CONVERTER_RESOLUTION / BITS_PER_SAMPLE +) ( + + // jesd interface + + output [LINK_DATA_WIDTH-1:0] link_data, + + // dac interface + + input [DAC_DATA_WIDTH-1:0] dac_data +); + + /* + * The framer module takes sample data and maps it onto the format that the + * JESD204 link expects for the specified framer configuration. + * + * The input sample data in dac_data is expected to be grouped by converter. + * The first sample is in the LSBs. Each sample has CONVERTER_RESOLUTION bits. + * + * Or in other words the data in dac_data is expected to have the following + * layout. + * + * MSB LSB + * [ MmSn, ..., MmS1, MnS0, ..., M1Sn, ... M1S1, M1S0, M0Sn, ... M0S1, M0S0 ] + * + * Where MjSi refers to the i-th sample of the j-th converter. With m being + * the number of converters and n the number of samples per converter per + * beat. + * + * In the default configuration the framer module processes 4 octets per beat. + * This means it can support settings with either 1, 2 or 4 octets per frame + * (F). Depending on the octets per frame the frames per beat will either be + * 4, 2 or 1 respectively. For other settings of OCTETS_PER_BEAT similar + * reasoning applies. + * + * The number of samples per frame (S) and the number of frames processed per + * beat gives the number of samples per converter per beat. This is either + * S * 4 (for F=1), S * 2 (for F=2) or S (for F=1). + * + * The framer module does not have a parameter for the octets per frame (F) + * since it can be derived from all other parameters given the following + * relationship: F = (M * N' * S) / (L * 8) + * + * + * Mapping in performed in two steps. First samples are grouped into frames, + * as there might be more than one frame pert beat. In the second step the + * frames are distributed onto the lanes. + * + * In the JESD204 standard samples and octets are ordered MSB first, this + * means earlier data is in the MSBs. This core on the other hand expects + * samples and octets to be LSB first ordered. This means earlier data is in + * the LSBs. To accommodate this two additional steps are required to order + * data from LSB to MSB before the framing process and back from MSB to LSB + * after it. + * + * The data itself that is contained within the samples and octets is LSB + * ordered in either case. That means lower bits are in the LSBs. + */ + + localparam BITS_PER_CHANNEL_PER_FRAME = BITS_PER_SAMPLE * SAMPLES_PER_FRAME; + localparam BITS_PER_LANE_PER_FRAME = BITS_PER_CHANNEL_PER_FRAME * + NUM_CHANNELS / NUM_LANES; + localparam FRAMES_PER_BEAT = OCTETS_PER_BEAT * 8 / BITS_PER_LANE_PER_FRAME; + localparam SAMPLES_PER_BEAT = DAC_DATA_WIDTH / CONVERTER_RESOLUTION; + localparam TAIL_BITS = BITS_PER_SAMPLE - CONVERTER_RESOLUTION; + + wire [LINK_DATA_WIDTH-1:0] link_data_msb_s; + wire [LINK_DATA_WIDTH-1:0] frame_data_s; + wire [LINK_DATA_WIDTH-1:0] dac_data_msb; + + generate + genvar i; + genvar j; + /* Reorder samples MSB first and insert tail bits */ + for (i = 0; i < SAMPLES_PER_BEAT; i = i + 1) begin: g_dac_data_msb + localparam src_w = CONVERTER_RESOLUTION; + localparam dst_w = BITS_PER_SAMPLE; + localparam src_lsb = i * src_w; + localparam dst_msb = LINK_DATA_WIDTH - 1 - i * dst_w; + + assign dac_data_msb[dst_msb-:src_w] = dac_data[src_lsb+:src_w]; + if (TAIL_BITS > 0) begin + assign dac_data_msb[dst_msb-src_w-:TAIL_BITS] = {TAIL_BITS{1'b0}}; + end + end + + /* Slice channel and pack it into frames */ + ad_perfect_shuffle #( + .NUM_GROUPS (NUM_CHANNELS), + .WORDS_PER_GROUP (FRAMES_PER_BEAT), + .WORD_WIDTH (BITS_PER_CHANNEL_PER_FRAME) + ) i_channels_to_frames ( + .data_in (dac_data_msb), + .data_out (frame_data_s)); + + /* Slice frame and pack it into lanes */ + ad_perfect_shuffle #( + .NUM_GROUPS (FRAMES_PER_BEAT), + .WORDS_PER_GROUP (NUM_LANES), + .WORD_WIDTH (BITS_PER_LANE_PER_FRAME) + ) i_frames_to_lanes ( + .data_in (frame_data_s), + .data_out (link_data_msb_s)); + + /* Reorder octets LSB first */ + for (i = 0; i < LINK_DATA_WIDTH; i = i + 8) begin: g_link_data + assign link_data[i+:8] = link_data_msb_s[LINK_DATA_WIDTH-1-i-:8]; + end + endgenerate + +endmodule diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl new file mode 100644 index 00000000..60e13634 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl @@ -0,0 +1,514 @@ +############################################################################### +## Copyright (C) 2018-2022 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +package require qsys 14.0 +source ../../../scripts/adi_env.tcl +source ../../scripts/adi_ip_intel.tcl + +ad_ip_create ad_ip_jesd204_tpl_dac "JESD204 Transport Layer for DACs" p_ad_ip_jesd204_tpl_dac_elab +set_module_property VALIDATION_CALLBACK p_ad_ip_jesd204_tpl_dac_validate +ad_ip_files ad_ip_jesd204_tpl_dac [list \ + $ad_hdl_dir/library/intel/common/ad_mul.v \ + $ad_hdl_dir/library/common/ad_mux.v \ + $ad_hdl_dir/library/common/ad_mux_core.v \ + $ad_hdl_dir/library/common/ad_dds_sine.v \ + $ad_hdl_dir/library/common/ad_dds_cordic_pipe.v \ + $ad_hdl_dir/library/common/ad_dds_sine_cordic.v \ + $ad_hdl_dir/library/common/ad_dds_2.v \ + $ad_hdl_dir/library/common/ad_dds_1.v \ + $ad_hdl_dir/library/common/ad_dds.v \ + $ad_hdl_dir/library/common/ad_iqcor.v \ + $ad_hdl_dir/library/common/ad_perfect_shuffle.v \ + $ad_hdl_dir/library/common/ad_rst.v \ + $ad_hdl_dir/library/common/up_axi.v \ + $ad_hdl_dir/library/common/up_xfer_cntrl.v \ + $ad_hdl_dir/library/common/up_xfer_status.v \ + $ad_hdl_dir/library/common/up_clock_mon.v \ + $ad_hdl_dir/library/common/up_dac_common.v \ + $ad_hdl_dir/library/common/up_dac_channel.v \ + $ad_hdl_dir/library/common/util_ext_sync.v \ + \ + $ad_hdl_dir/library/intel/common/up_xfer_cntrl_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_xfer_status_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \ + $ad_hdl_dir/library/intel/common/up_rst_constr.sdc \ + \ + ad_ip_jesd204_tpl_dac.v \ + ad_ip_jesd204_tpl_dac_channel.v \ + ad_ip_jesd204_tpl_dac_core.v \ + ad_ip_jesd204_tpl_dac_framer.v \ + ad_ip_jesd204_tpl_dac_pn.v \ + ad_ip_jesd204_tpl_dac_regmap.v \ + ../ad_ip_jesd204_tpl_common/up_tpl_common.v \ +] + +# parameters + +set group "General Configuration" + +ad_ip_parameter ID INTEGER 0 true [list \ + DISPLAY_NAME "Core ID" \ + GROUP $group \ +] + +ad_ip_parameter OCTETS_PER_BEAT INTEGER 4 true [list \ + DISPLAY_NAME "Datapath width" \ + DISPLAY_UNITS "octets" \ + ALLOWED_RANGES {4 6 8 12} \ + GROUP $group \ +] + +set group "JESD204 Framer Configuration" + +ad_ip_parameter PART STRING "Generic" false [list \ + DISPLAY_NAME "Part" \ + ALLOWED_RANGES { \ + "Generic" \ + "AD9135" \ + "AD9136" \ + "AD9144" \ + "AD9152" \ + "AD9154" \ + "AD9161" \ + "AD9162" \ + "AD9163" \ + "AD9164" \ + "AD9171" \ + "AD9172" \ + "AD9173" \ + } \ + GROUP $group \ +] + +ad_ip_parameter NUM_LANES INTEGER 1 true [list \ + DISPLAY_NAME "Number of Lanes (L)" \ + DISPLAY_UNITS "lanes" \ + ALLOWED_RANGES {1 2 3 4 8 16 24 32} \ + GROUP $group \ +] + +ad_ip_parameter NUM_CHANNELS INTEGER 1 true [list \ + DISPLAY_NAME "Number of Converters (M)" \ + DISPLAY_UNITS "converters" \ + ALLOWED_RANGES {1 2 4 6 8 16 32 64} \ + GROUP $group \ +] + +ad_ip_parameter BITS_PER_SAMPLE INTEGER 16 true [list \ + DISPLAY_NAME "Bits per Sample (N')" \ + ALLOWED_RANGES {8 12 16} \ + UNITS bits \ + GROUP $group \ +] + +ad_ip_parameter DMA_BITS_PER_SAMPLE INTEGER 16 true [list \ + DISPLAY_NAME "DMA Bits per Sample" \ + ALLOWED_RANGES {8 16} \ + UNITS bits \ + GROUP $group \ +] + +ad_ip_parameter CONVERTER_RESOLUTION INTEGER 16 true [list \ + DISPLAY_NAME "Converter Resolution (N)" \ + ALLOWED_RANGES {8 11 12 16} \ + UNITS bits \ + GROUP $group \ +] + +ad_ip_parameter ENABLE_SAMPLES_PER_FRAME_MANUAL BOOLEAN 0 false [list \ + DISPLAY_NAME "Manual Samples per Frame" \ + GROUP $group \ +] + +ad_ip_parameter SAMPLES_PER_FRAME INTEGER 1 true [list \ + DISPLAY_NAME "Samples per Frame (S)" \ + DISPLAY_UNITS "samples" \ + ALLOWED_RANGES {1 2 3 4 6 8 12 16} \ + DERIVED true \ + GROUP $group \ +] + +ad_ip_parameter SAMPLES_PER_FRAME_MANUAL INTEGER 1 false [list \ + DISPLAY_NAME "Samples per Frame (S)" \ + DISPLAY_UNITS "samples" \ + ALLOWED_RANGES {1 2 3 4 6 8 12 16} \ + VISIBLE false \ + GROUP $group \ +] + +ad_ip_parameter OCTETS_PER_FRAME INTEGER 1 false [list \ + DISPLAY_NAME "Octets per Frame (F)" \ + DISPLAY_UNITS "octets" \ + ALLOWED_RANGES {1 2 3 4 6 8} \ + DERIVED true \ + GROUP $group \ +] + +set group "Framer Input Information" + +# Parameters in this group are informative only and can be read back after the +# core has been configured to find out the expected layout of the input data. +# E.g. +# set NUM_OF_CHANNELS [get_instance_parameter_value jesd204_transport NUM_CHANNELS] +# set CHANNEL_DATA_WIDTH [get_instance_parameter_value jesd204_transport CHANNEL_DATA_WIDTH] +# +# add_instance util_dac_upack util_upack +# set_instance_parameter_values util_dac_upack [list \ +# CHANNEL_DATA_WIDTH $CHANNEL_DATA_WIDTH \ +# NUM_OF_CHANNELS $NUM_OF_CHANNELS \ +# ] + +ad_ip_parameter SAMPLES_PER_CHANNEL INTEGER 1 false [list \ + DISPLAY_NAME "Samples per Channel per Beat" \ + DERIVED true \ + GROUP $group \ +] + +ad_ip_parameter CHANNEL_DATA_WIDTH INTEGER 1 false [list \ + DISPLAY_NAME "Channel Data Width" \ + UNITS bits \ + DERIVED true \ + GROUP $group \ +] + +set group "Datapath Configuration" + +ad_ip_parameter DATAPATH_DISABLE boolean 0 true [list \ + DISPLAY_NAME "Disable Datapath" \ + GROUP $group \ +] + +ad_ip_parameter DDS_TYPE INTEGER 1 true [list \ + DISPLAY_NAME "DDS Type" \ + ALLOWED_RANGES {"0:Polynominal" "1:CORDIC"} \ + GROUP $group \ +] + +ad_ip_parameter DDS_CORDIC_DW INTEGER 16 true [list \ + DISPLAY_NAME "CORDIC DDS Data Width" \ + ALLOWED_RANGES {8:20} \ + UNITS bits \ + GROUP $group \ +] + +ad_ip_parameter DDS_CORDIC_PHASE_DW INTEGER 16 true [list \ + DISPLAY_NAME "CORDIC DDS Phase Width" \ + ALLOWED_RANGES {8:20} \ + UNITS bits \ + GROUP $group \ +] + +ad_ip_parameter XBAR_ENABLE boolean 0 true [list \ + DISPLAY_NAME "Channel Crossbar Enable" \ + GROUP $group \ +] + +# axi4 slave + +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12 + +# core clock and start of frame + +add_interface link_clk clock end +add_interface_port link_clk link_clk clk Input 1 + +# We don't expect too large values for a and b, trivial implementation will do +proc gcd {a b} { + if {$a == $b} { + return $b + } elseif {$a > $b} { + return [gcd [expr $a - $b] $b] + } else { + return [gcd $a [expr $b - $a]] + } +} + +# M L S F N NP +set ad9136_modes { \ + {1 4 2 1 16 16} \ + {1 2 1 1 16 16} \ + {1 1 1 2 16 16} \ + {2 8 2 1 16 16} \ + {2 4 1 1 16 16} \ + {2 2 1 2 16 16} \ +} + +set ad9144_modes { \ + {4 8 1 1 16 16} \ + {4 8 2 2 16 16} \ + {4 4 1 2 16 16} \ + {4 2 1 4 16 16} \ + {2 4 1 1 16 16} \ + {2 4 2 2 16 16} \ + {2 2 1 2 16 16} \ + {2 1 1 4 16 16} \ + {1 2 1 1 16 16} \ + {1 1 1 2 16 16} \ +} + +set ad9152_modes { \ + {2 4 1 1 16 16} \ + {2 4 2 2 16 16} \ + {2 2 1 2 16 16} \ + {2 1 1 4 16 16} \ + {1 2 1 1 16 16} \ + {1 1 1 2 16 16} \ +} + +set ad9161_modes { \ + {2 1 1 4 16 16} \ + {2 2 1 2 16 16} \ + {2 3 3 4 16 16} \ + {2 4 1 1 16 16} \ + {2 6 3 2 16 16} \ + {1 8 4 1 16 16} \ + {2 8 2 1 16 16} \ +} + +set ad9163_modes { \ + {2 1 1 4 16 16} \ + {2 2 1 2 16 16} \ + {2 3 3 4 16 16} \ + {2 4 1 1 16 16} \ + {2 6 3 2 16 16} \ + {2 8 2 1 16 16} \ +} + +set ad9171_modes { \ + {2 1 1 4 16 16} \ + {2 2 1 2 16 16} \ + {2 1 1 3 12 12} \ +} + +set ad9172_modes { \ + {2 1 1 4 16 16} \ + {4 2 1 4 16 16} \ + {6 3 1 4 16 16} \ + {2 2 1 2 16 16} \ + {4 4 1 2 16 16} \ + {2 1 1 3 12 12} \ + {4 2 1 3 12 12} \ + {4 1 1 8 16 16} \ + {2 4 1 1 16 16} \ + {2 4 2 2 16 16} \ + {2 8 2 1 16 16} \ + {2 8 4 2 16 16} \ + {2 8 8 3 12 12} \ + {1 4 2 1 16 16} \ + {1 4 4 2 16 16} \ + {1 8 4 1 16 16} \ + {1 8 8 2 16 16} \ +} + +set ad9173_modes { \ + {2 1 1 4 16 16} \ + {4 2 1 4 16 16} \ + {6 3 1 4 16 16} \ + {2 2 1 2 16 16} \ + {4 4 1 2 16 16} \ + {2 1 1 3 12 12} \ + {4 2 1 3 12 12} \ + {4 1 1 8 16 16} \ + {2 4 1 1 16 16} \ + {2 4 2 2 16 16} \ + {2 4 1 1 11 16} \ + {2 4 2 2 11 16} \ + {2 8 2 1 11 16} \ + {2 8 4 2 11 16} \ + {2 8 8 3 11 12} \ +} + +# validate + +proc p_ad_ip_jesd204_tpl_dac_validate {} { + set L [get_parameter_value "NUM_LANES"] + set M [get_parameter_value "NUM_CHANNELS"] + set NP [get_parameter_value "BITS_PER_SAMPLE"] + set N [get_parameter_value "CONVERTER_RESOLUTION"] + set S_manual [get_parameter_value "SAMPLES_PER_FRAME_MANUAL"] + set enable_S_manual [get_parameter_value "ENABLE_SAMPLES_PER_FRAME_MANUAL"] + + # With fixed values for M, L and N' all valid values for S and F have a + # constant ratio of S / F. Choose a ratio so that S and F are co-prime. + # Choosing values for F and S that have a common factor has higher latency + # and no added benefits. + # + # Since converters often support those higher latency modes still allow a + # manual override of the S parameter in case somebody wants to use those modes + # anyway. + # + # To be able to set samples per frame manually ENABLE_SAMPLES_PER_FRAME_MANUAL + # needs to be set to true and SAMPLES_PER_FRAME_MANUAL to the desired value. + # + # When manual sample per frame selection is enabled still verify that the + # selected value is valid. + + set S_min [expr $L * 8] + set F_min [expr $M * $NP] + set common_factor [gcd $S_min $F_min] + set S_min [expr $S_min / $common_factor] + set F_min [expr $F_min / $common_factor] + + if {$enable_S_manual} { + if {$S_manual % $S_min != 0} { + send_message ERROR "For framer configuration (L=$L, M=$M, NP=$NP) samples per frame (S) must be an integer multiple of $S_min" + set S $S_min + set F $F_min + } else { + set S $S_manual + set F [expr $S_manual * $M * $NP / $L / 8] + } + } else { + set S $S_min + set F $F_min + } + + set_parameter_value OCTETS_PER_FRAME $F + set_parameter_value SAMPLES_PER_FRAME $S + + set_parameter_property SAMPLES_PER_FRAME VISIBLE [expr !$enable_S_manual] + set_parameter_property SAMPLES_PER_FRAME_MANUAL VISIBLE $enable_S_manual + + set_parameter_value SAMPLES_PER_CHANNEL [expr 4 * $S / $F] + set_parameter_value CHANNEL_DATA_WIDTH [expr 16 * (4 * $S / $F)] + + set data_path_enabled [expr ![get_parameter_value DATAPATH_DISABLE]] + set cordic_enabled [expr $data_path_enabled && [get_parameter_value DDS_TYPE] == 1] + + set_parameter_property DDS_TYPE ENABLED $data_path_enabled + set_parameter_property DDS_CORDIC_DW ENABLED $cordic_enabled + set_parameter_property DDS_CORDIC_PHASE_DW ENABLED $cordic_enabled + + set part [get_parameter_value "PART"] + + if {$part == "AD9135" || $part == "AD9136"} { + global ad9136_modes + set modes $ad9136_modes + } elseif {$part == "AD9144" || $part == "AD9154"} { + global ad9144_modes + set modes $ad9144_modes + } elseif {$part == "AD9152"} { + global ad9152_modes + set modes $ad9152_modes + } elseif {$part == "AD9161" || $part == "AD9162" || $part == "AD9164"} { + global ad9161_modes + set modes $ad9161_modes + } elseif {$part == "AD9163"} { + global ad9163_modes + set modes $ad9163_modes + } elseif {$part == "AD9171"} { + global ad9171_modes + set modes $ad9171_modes + } elseif {$part == "AD9172"} { + global ad9172_modes + set modes $ad9172_modes + } elseif {$part == "AD9173"} { + global ad9173_modes + set modes $ad9173_modes + } else { + set modes {} + } + + if {$modes != {}} { + set allowed_channels {} + set allowed_lanes {} + set allowed_samples_per_frame {} + set allowed_resolution {} + set allowed_bits_per_sample {} + + set valid_mode false + foreach m $modes { + if {$m == [list $M $L $S $F $N $NP]} { + set valid_mode true + } + + lappend allowed_channels [lindex $m 0] + lappend allowed_lanes [lindex $m 1] + lappend allowed_samples_per_frame [lindex $m 2] + lappend allowed_resolution [lindex $m 4] + lappend allowed_bits_per_sample [lindex $m 5] + } + + set allowed_channels [lsort -unique -integer $allowed_channels] + set allowed_lanes [lsort -unique -integer $allowed_lanes] + set allowed_samples_per_frame [lsort -unique -integer $allowed_samples_per_frame] + set allowed_resolution [lsort -unique -integer $allowed_resolution] + set allowed_bits_per_sample [lsort -unique -integer $allowed_bits_per_sample] + + if {!$valid_mode} { + send_message ERROR "Framer configuration (L=$L, M=$M, N=$N, NP=$NP, S=$S, F=$F) not supported by $part" + } + } else { + set allowed_channels {1 2 4 6 8 16 32 64} + set allowed_lanes {1 2 3 4 8 16} + set allowed_samples_per_frame {1 2 3 4 6 8 12 16} + set allowed_resolution {8 11 12 16} + set allowed_bits_per_sample {8 12 16} + } + + set_parameter_property "NUM_CHANNELS" "ALLOWED_RANGES" $allowed_channels + set_parameter_property "NUM_LANES" "ALLOWED_RANGES" $allowed_lanes + set_parameter_property "SAMPLES_PER_FRAME" "ALLOWED_RANGES" $allowed_samples_per_frame + set_parameter_property "CONVERTER_RESOLUTION" "ALLOWED_RANGES" $allowed_resolution + set_parameter_property "BITS_PER_SAMPLE" "ALLOWED_RANGES" $allowed_bits_per_sample + + if {$enable_S_manual} { + set allowed_S {} + foreach i {1 2 4} { + if {$F_min * $i <= 4 && $S_min * $i <= 16} { + set new_S [expr $S_min * $i] + if {[lsearch -integer $allowed_samples_per_frame $new_S] != -1} { + lappend allowed_S $new_S + } + } + } + set_parameter_property SAMPLES_PER_FRAME_MANUAL ALLOWED_RANGES $allowed_S + } else { + set_parameter_property SAMPLES_PER_FRAME_MANUAL ALLOWED_RANGES {1 2 3 4 6 8 12 16} + } +} + +# elaborate + +proc p_ad_ip_jesd204_tpl_dac_elab {} { + + # read core parameters + + set L [get_parameter_value "NUM_LANES"] + set M [get_parameter_value "NUM_CHANNELS"] + set NP [get_parameter_value "BITS_PER_SAMPLE"] + set OPB [get_parameter_value "OCTETS_PER_BEAT"] + set DMA_BPS [get_parameter_value "DMA_BITS_PER_SAMPLE"] + + # The DMA interface is rounded to nearest power of two bytes per sample, + # e.g NP=12 is padded into 16 bits + set samples_per_beat_per_channel [expr ($OPB * 8 * $L / ($M * $NP))] + set channel_bus_width [expr $samples_per_beat_per_channel*$DMA_BPS] + + # link layer interface + + add_interface link_data avalon_streaming source + add_interface_port link_data link_data data output [expr $OPB*8*$L] + add_interface_port link_data link_valid valid output 1 + add_interface_port link_data link_ready ready input 1 + set_interface_property link_data associatedClock link_clk + set_interface_property link_data dataBitsPerSymbol [expr $OPB*8*$L] + + # dma interface + + for {set i 0} {$i < $M} {incr i} { + add_interface dac_ch_$i conduit end + add_interface_port dac_ch_$i dac_enable_$i enable output 1 + set_port_property dac_enable_$i fragment_list [format "enable(%d:%d)" $i $i] + add_interface_port dac_ch_$i dac_valid_$i valid output 1 + set_port_property dac_valid_$i fragment_list [format "dac_valid(%d:%d)" $i $i] + add_interface_port dac_ch_$i dac_data_$i data input $channel_bus_width + set_port_property dac_data_$i fragment_list \ + [format "dac_ddata(%d:%d)" [expr $channel_bus_width*$i+$channel_bus_width-1] [expr $channel_bus_width*$i]] + set_interface_property dac_ch_$i associatedClock link_clk + } + + ad_interface signal dac_dunf input 1 unf +} diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl new file mode 100644 index 00000000..a98820ab --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.tcl @@ -0,0 +1,161 @@ +############################################################################### +## Copyright (C) 2018-2022 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create ad_ip_jesd204_tpl_dac +adi_ip_files ad_ip_jesd204_tpl_dac [list \ + "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \ + "$ad_hdl_dir/library/common/ad_mux.v" \ + "$ad_hdl_dir/library/common/ad_mux_core.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine.v" \ + "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \ + "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \ + "$ad_hdl_dir/library/common/ad_dds_2.v" \ + "$ad_hdl_dir/library/common/ad_dds_1.v" \ + "$ad_hdl_dir/library/common/ad_dds.v" \ + "$ad_hdl_dir/library/common/ad_iqcor.v" \ + "$ad_hdl_dir/library/common/ad_perfect_shuffle.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/up_clock_mon.v" \ + "$ad_hdl_dir/library/common/up_dac_common.v" \ + "$ad_hdl_dir/library/common/up_dac_channel.v" \ + "$ad_hdl_dir/library/common/util_ext_sync.v" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ + "../ad_ip_jesd204_tpl_common/up_tpl_common.v" \ + "ad_ip_jesd204_tpl_dac_channel.v" \ + "ad_ip_jesd204_tpl_dac_core.v" \ + "ad_ip_jesd204_tpl_dac_framer.v" \ + "ad_ip_jesd204_tpl_dac_regmap.v" \ + "ad_ip_jesd204_tpl_dac_pn.v" \ + "ad_ip_jesd204_tpl_dac.v" ] + +adi_ip_properties ad_ip_jesd204_tpl_dac + +adi_init_bd_tcl +adi_ip_bd ad_ip_jesd204_tpl_dac "bd/bd.tcl" + +set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/jesd204/jesd204_tpl_dac} [ipx::current_core] + +set cc [ipx::current_core] + +set_property display_name "JESD204 Transport Layer for DACs" $cc +set_property description "JESD204 Transport Layer for DACs" $cc + +# ADD missing stuff ####################################################### + +adi_add_bus "link" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list \ + {"link_ready" "TREADY"} \ + {"link_valid" "TVALID"} \ + {"link_data" "TDATA"} \ + ] +adi_add_bus_clock "link_clk" "link" + +adi_set_ports_dependency "dac_sync_in" "EXT_SYNC == 1" +adi_set_ports_dependency "dac_sync_manual_req_out" "EXT_SYNC == 1" +adi_set_ports_dependency "dac_sync_manual_req_in" "EXT_SYNC == 1" + +set_property -dict [list \ + "value_validation_type" "pairs" \ + "value_validation_pairs" {"Polynominal" "0" "CORDIC" "1"} \ + "enablement_tcl_expr" "\$DATAPATH_DISABLE == 0" \ +] [ipx::get_user_parameters DDS_TYPE -of_objects $cc] + +foreach p {DDS_CORDIC_DW DDS_CORDIC_PHASE_DW} { + set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" 8 \ + "value_validation_range_maximum" 20 \ + "enablement_tcl_expr" "\$DATAPATH_DISABLE == 0 && \$DDS_TYPE == 1" \ + ] [ipx::get_user_parameters $p -of_objects $cc] +} + +foreach {p v} { + "NUM_LANES" "1 2 3 4 6 8 12 16 24 32" \ + "NUM_CHANNELS" "1 2 4 6 8 16 32 64" \ + "BITS_PER_SAMPLE" "8 12 16" \ + "DMA_BITS_PER_SAMPLE" "8 12 16" \ + "CONVERTER_RESOLUTION" "8 11 12 16" \ + "SAMPLES_PER_FRAME" "1 2 3 4 6 8 12 16" \ + "OCTETS_PER_BEAT" "4 6 8 12 16 32 64" \ +} { \ + set_property -dict [list \ + "value_validation_type" "list" \ + "value_validation_list" $v \ + ] [ipx::get_user_parameters $p -of_objects $cc] +} + +set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] + +set general_group [ipgui::add_group -name "General Configuration" -component $cc \ + -parent $page0 -display_name "General Configuration"] + +set p [ipgui::get_guiparamspec -name "ID" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $general_group +set_property -dict [list \ + "display_name" "Core ID" \ +] $p + +set framer_group [ipgui::add_group -name "JESD204 Framer Configuration" -component $cc \ + -parent $page0 -display_name "JESD204 Framer Cofiguration"] + +set i 0 + +foreach {k v} { \ + "NUM_LANES" "Number of Lanes (L)" \ + "NUM_CHANNELS" "Number of Conveters (M)" \ + "BITS_PER_SAMPLE" "Bits per Sample (N')" \ + "DMA_BITS_PER_SAMPLE" "DMA Bits per Sample" \ + "CONVERTER_RESOLUTION" "Converter Resolution (N)" \ + "SAMPLES_PER_FRAME" "Samples per Frame (S)" \ + "OCTETS_PER_BEAT" "Octets per Beat" \ + } { \ + set p [ipgui::get_guiparamspec -name $k -component $cc] + ipgui::move_param -component $cc -order $i $p -parent $framer_group + set_property -dict [list \ + WIDGET "comboBox" \ + DISPLAY_NAME $v \ + ] $p + incr i +} + +set datapath_group [ipgui::add_group -name "Datapath Configuration" -component $cc \ + -parent $page0 -display_name "Datapath Cofiguration"] + +set i 0 + +foreach {k v w} { + "DATAPATH_DISABLE" "Disable Datapath" "checkBox" \ + "EXT_SYNC" "Enable external SYNC" "checkBox" \ + "IQCORRECTION_DISABLE" "Disable IQ Correction" "checkBox" \ + "XBAR_ENABLE" "Enable user data XBAR" "checkBox" \ + "DDS_TYPE" "DDS Type" "comboBox" \ + "DDS_PHASE_DW" "DDS Phase Width" "text" \ + "DDS_CORDIC_DW" "CORDIC DDS Data Width" "text" \ + "DDS_CORDIC_PHASE_DW" "CORDIC DDS Phase Width" "text" \ + } { \ + set p [ipgui::get_guiparamspec -name $k -component $cc] + ipgui::move_param -component $cc -order $i $p -parent $datapath_group + set_property -dict [list \ + WIDGET $w \ + DISPLAY_NAME $v \ + ] $p + incr i +} + +adi_add_auto_fpga_spec_params + +ipx::create_xgui_files [ipx::current_core] +ipx::save_core [ipx::current_core] diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_pn.v b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_pn.v new file mode 100644 index 00000000..70c540f6 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_pn.v @@ -0,0 +1,111 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_ip_jesd204_tpl_dac_pn #( + parameter DATA_PATH_WIDTH = 4, + parameter CONVERTER_RESOLUTION = 16 +) ( + input clk, + input reset, + + output [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] pn7_data, + output [DATA_PATH_WIDTH*CONVERTER_RESOLUTION-1:0] pn15_data +); + + localparam CR = CONVERTER_RESOLUTION; + localparam DW = DATA_PATH_WIDTH * CR - 1; + + /* We need at least enough bits to store the PN state */ + localparam PN7_W = DW > 6 ? DW : 6; + localparam PN15_W = DW > 14 ? DW : 14; + + reg [PN7_W:0] pn7_state = {PN7_W+1{1'b1}}; + reg [PN15_W:0] pn15_state = {PN15_W+1{1'b1}}; + + wire [DW:0] pn7; + wire [DW+7:0] pn7_full_state; + wire [PN7_W:0] pn7_reset; + + wire [DW:0] pn15; + wire [DW+15:0] pn15_full_state; + wire [PN15_W:0] pn15_reset; + + /* PN7 x^7 + x^6 + 1 */ + assign pn7 = pn7_full_state[7+:DW+1] ^ pn7_full_state[6+:DW+1]; + assign pn7_full_state = {pn7_state[6:0],pn7}; + + /* PN15 x^15 + x^14 + 1 */ + assign pn15 = pn15_full_state[15+:DW+1] ^ pn15_full_state[14+:DW+1]; + assign pn15_full_state = {pn15_state[14:0],pn15}; + + assign pn7_reset[PN7_W-:7] = {7{1'b1}}; + assign pn15_reset[PN15_W-:15] = {15{1'b1}}; + + generate + if (PN7_W >= 7) begin + assign pn7_reset[PN7_W-7:0] = pn7_reset[PN7_W:7] ^ pn7_reset[PN7_W-1:6]; + end + + if (PN15_W >= 15) begin + assign pn15_reset[PN15_W-15:0] = pn15_reset[PN15_W:15] ^ pn15_reset[PN15_W-1:14]; + end + endgenerate + + always @(posedge clk) begin + if (reset == 1'b1) begin + pn7_state <= pn7_reset; + pn15_state <= pn15_reset; + end else begin + pn7_state <= pn7_full_state[PN7_W:0]; + pn15_state <= pn15_full_state[PN15_W:0]; + end + end + + generate + /* + * The first sample contains the first MSB of the PN sequence, but the first + * sample is also in the LSB of the output data. So extract data at the MSB + * sample of the PN state and put it into the LSB sample of the output data. + */ + genvar i; + for (i = 0; i <= DW; i = i + CR) begin: g_pn_swizzle + assign pn7_data[i+:CR] = pn7_state[PN7_W-i-:CR]; + assign pn15_data[i+:CR] = pn15_state[PN15_W-i-:CR]; + end + endgenerate + +endmodule diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v new file mode 100644 index 00000000..c89d5c20 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v @@ -0,0 +1,358 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_ip_jesd204_tpl_dac_regmap #( + parameter ID = 0, + parameter DATAPATH_DISABLE = 0, + parameter IQCORRECTION_DISABLE = 1, + parameter XBAR_ENABLE = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter NUM_CHANNELS = 2, + parameter DATA_PATH_WIDTH = 16, + parameter PADDING_TO_MSB_LSB_N = 0, + parameter EXT_SYNC = 0, + parameter NUM_PROFILES = 1, // Number of supported JESD profiles + parameter DDS_PHASE_DW = 16 +) ( + input s_axi_aclk, + input s_axi_aresetn, + + input s_axi_awvalid, + output s_axi_awready, + input [12:0] s_axi_awaddr, + input [2:0] s_axi_awprot, + + input s_axi_wvalid, + output s_axi_wready, + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + + input s_axi_arvalid, + output s_axi_arready, + input [12:0] s_axi_araddr, + input [2:0] s_axi_arprot, + + output s_axi_rvalid, + input s_axi_rready, + output [31:0] s_axi_rdata, + output [1:0] s_axi_rresp, + + output s_axi_bvalid, + input s_axi_bready, + output [1:0] s_axi_bresp, + + input link_clk, + + input dac_dunf, + + output dac_sync, + output dac_ext_sync_arm, + output dac_ext_sync_disarm, + output dac_ext_sync_manual_req, + + input dac_sync_in_status, + + output [NUM_CHANNELS*4-1:0] dac_data_sel, + output [NUM_CHANNELS-1:0] dac_mask_enable, + output dac_dds_format, + + output [NUM_CHANNELS*16-1:0] dac_dds_scale_0, + output [NUM_CHANNELS*16-1:0] dac_dds_scale_1, + output [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_init_0, + output [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_incr_0, + output [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_init_1, + output [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_incr_1, + + output [NUM_CHANNELS*16-1:0] dac_pat_data_0, + output [NUM_CHANNELS*16-1:0] dac_pat_data_1, + + output [NUM_CHANNELS-1:0] dac_iqcor_enb, + output [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_1, + output [NUM_CHANNELS*16-1:0] dac_iqcor_coeff_2, + + output [NUM_CHANNELS*8-1:0] dac_src_chan_sel, + + // Framer interface + input [NUM_PROFILES*8-1: 0] jesd_m, + input [NUM_PROFILES*8-1: 0] jesd_l, + input [NUM_PROFILES*8-1: 0] jesd_s, + input [NUM_PROFILES*8-1: 0] jesd_f, + input [NUM_PROFILES*8-1: 0] jesd_n, + input [NUM_PROFILES*8-1: 0] jesd_np, + + output [$clog2(NUM_PROFILES):0] up_profile_sel +); + + // internal registers + reg up_wack = 1'b0; + reg up_rack = 1'b0; + reg [31:0] up_rdata = 32'h00; + reg [31:0] up_rdata_all; + + wire up_wreq_s; + wire [10:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire [NUM_CHANNELS+1:0] up_wack_s; + wire up_rreq_s; + wire [10:0] up_raddr_s; + wire [31:0] up_rdata_s[0:NUM_CHANNELS+1]; + wire [NUM_CHANNELS+1:0] up_rack_s; + + // internal clocks and resets + + wire up_clk; + wire up_rstn; + wire dac_rst; + + // signal name changes + + assign up_clk = s_axi_aclk; + assign up_rstn = s_axi_aresetn; + + // up bus interface + + up_axi #( + .AXI_ADDRESS_WIDTH (13) + ) i_up_axi ( + .up_clk (up_clk), + .up_rstn (up_rstn), + + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + + integer n; + + always @(*) begin + up_rdata_all = 'h00; + for (n = 0; n < NUM_CHANNELS + 2; n = n + 1) begin + up_rdata_all = up_rdata_all | up_rdata_s[n]; + end + end + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_rdata <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; + end else begin + up_rdata <= up_rdata_all; + up_rack <= |up_rack_s; + up_wack <= |up_wack_s; + end + end + + // dac common processor interface + + localparam CONFIG = (EXT_SYNC << 12) | + (PADDING_TO_MSB_LSB_N << 11) | + (XBAR_ENABLE << 10) | + (DATAPATH_DISABLE << 6) | + (IQCORRECTION_DISABLE << 0); + + up_dac_common #( + .COMMON_ID(6'h0), + .ID (ID), + .CONFIG(CONFIG), + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .FPGA_FAMILY (FPGA_FAMILY), + .SPEED_GRADE (SPEED_GRADE), + .DEV_PACKAGE (DEV_PACKAGE), + .DRP_DISABLE (1), + .USERPORTS_DISABLE (1), + .GPIO_DISABLE (1) + ) i_up_dac_common ( + .mmcm_rst (), + .dac_clk (link_clk), + .dac_rst (dac_rst), + .dac_sync (dac_sync), + .dac_ext_sync_arm (dac_ext_sync_arm), + .dac_ext_sync_disarm (dac_ext_sync_disarm), + .dac_ext_sync_manual_req (dac_ext_sync_manual_req), + .dac_sync_in_status (dac_sync_in_status), + .dac_frame (), + .dac_clksel (), + .dac_custom_wr(), + .dac_custom_rd(32'b0), + .dac_custom_control(), + .dac_status_if_busy(1'b0), + .dac_par_type (), + .dac_par_enb (), + .dac_r1_mode (), + .dac_datafmt (dac_dds_format), + .dac_datarate (), + .dac_status (1'b1), + .dac_status_unf (dac_dunf), + .dac_clk_ratio (DATA_PATH_WIDTH), + .up_drp_sel (), + .up_drp_wr (), + .up_drp_addr (), + .up_drp_wdata (), + .up_drp_rdata (32'd0), + .up_drp_ready (1'd0), + .up_drp_locked (1'd1), + .up_usr_chanmax (), + .dac_usr_chanmax (NUM_CHANNELS), + .up_dac_gpio_in (32'd0), + .up_dac_gpio_out (), + .up_dac_ce (), + .up_pps_rcounter ('h00), + .up_pps_status (1'b0), + .up_pps_irq_mask (), + + .up_clk (up_clk), + .up_rstn (up_rstn), + + .up_wreq (up_wreq_s), + .up_waddr ({3'b0,up_waddr_s}), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[0]), + .up_rreq (up_rreq_s), + .up_raddr ({3'b0,up_raddr_s}), + .up_rdata (up_rdata_s[0]), + .up_rack (up_rack_s[0])); + + generate + genvar i; + for (i = 0; i < NUM_CHANNELS; i = i + 1) begin: g_channel + up_dac_channel #( + .COMMON_ID(6'h1 + i/16), + .CHANNEL_ID (i % 16), + .CHANNEL_NUMBER (i), + .DDS_PHASE_DW (DDS_PHASE_DW), + .USERPORTS_DISABLE (1), + .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE), + .XBAR_ENABLE (XBAR_ENABLE) + ) i_up_dac_channel ( + .dac_clk (link_clk), + .dac_rst (dac_rst), + .dac_dds_scale_1 (dac_dds_scale_0[16*i+:16]), + .dac_dds_init_1 (dac_dds_init_0[DDS_PHASE_DW*i+:DDS_PHASE_DW]), + .dac_dds_incr_1 (dac_dds_incr_0[DDS_PHASE_DW*i+:DDS_PHASE_DW]), + .dac_dds_scale_2 (dac_dds_scale_1[16*i+:16]), + .dac_dds_init_2 (dac_dds_init_1[DDS_PHASE_DW*i+:DDS_PHASE_DW]), + .dac_dds_incr_2 (dac_dds_incr_1[DDS_PHASE_DW*i+:DDS_PHASE_DW]), + .dac_pat_data_1 (dac_pat_data_0[16*i+:16]), + .dac_pat_data_2 (dac_pat_data_1[16*i+:16]), + .dac_data_sel (dac_data_sel[4*i+:4]), + .dac_mask_enable (dac_mask_enable[i]), + .dac_iq_mode (), + .dac_iqcor_enb (dac_iqcor_enb[i]), + .dac_iqcor_coeff_1 (dac_iqcor_coeff_1[16*i+:16]), + .dac_iqcor_coeff_2 (dac_iqcor_coeff_2[16*i+:16]), + .dac_src_chan_sel (dac_src_chan_sel[8*i+:8]), + .up_usr_datatype_be (), + .up_usr_datatype_signed (), + .up_usr_datatype_shift (), + .up_usr_datatype_total_bits (), + .up_usr_datatype_bits (), + .up_usr_interpolation_m (), + .up_usr_interpolation_n (), + .dac_usr_datatype_be (1'b0), + .dac_usr_datatype_signed (1'b1), + .dac_usr_datatype_shift (8'd0), + .dac_usr_datatype_total_bits (8'd16), + .dac_usr_datatype_bits (8'd16), + .dac_usr_interpolation_m (16'd1), + .dac_usr_interpolation_n (16'd1), + + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_wreq (up_wreq_s), + .up_waddr ({3'b0,up_waddr_s}), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[i+1]), + .up_rreq (up_rreq_s), + .up_raddr ({3'b0,up_raddr_s}), + .up_rdata (up_rdata_s[i+1]), + .up_rack (up_rack_s[i+1])); + end + endgenerate + + up_tpl_common #( + .COMMON_ID(2'h0), // Offset of regmap + .NUM_PROFILES(NUM_PROFILES) // Number of JESD profiles + ) i_up_tpl_dac ( + .jesd_m (jesd_m), + .jesd_l (jesd_l), + .jesd_s (jesd_s), + .jesd_f (jesd_f), + .jesd_n (jesd_n), + .jesd_np (jesd_np), + + .up_profile_sel (up_profile_sel), + + // bus interface + .up_clk (up_clk), + .up_rstn (up_rstn), + + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack_s[NUM_CHANNELS+1]), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata_s[NUM_CHANNELS+1]), + .up_rack (up_rack_s[NUM_CHANNELS+1])); + +endmodule diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/bd/bd.tcl b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/bd/bd.tcl new file mode 100644 index 00000000..dceb9498 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/bd/bd.tcl @@ -0,0 +1,47 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + DEV_PACKAGE \ + SPEED_GRADE \ + FPGA_FAMILY \ + FPGA_TECHNOLOGY" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/component.xml b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/component.xml new file mode 100644 index 00000000..5bc7f3c4 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/component.xml @@ -0,0 +1,1566 @@ + + + analog.com + user + ad_ip_jesd204_tpl_dac + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + link + + + + + + + TREADY + + + link_ready + + + + + TVALID + + + link_valid + + + + + TDATA + + + link_data + + + + + + link_signal_clock + link_signal_clock + + + + + + + CLK + + + link_clk + + + + + + ASSOCIATED_BUSIF + link + + + + + + + s_axi + + axi_lite + 0 + 8192 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + ad_ip_jesd204_tpl_dac + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 7664e214 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + ad_ip_jesd204_tpl_dac + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + c6d3408b + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + e8886912 + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_view_fileset + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + + + link_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + link_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + link_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + link_data + + out + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + enable + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_valid + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_ddata + + in + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_dunf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_rst + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_sync_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dac_sync_manual_req_out + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dac_sync_manual_req_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awaddr + + in + + 12 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_araddr + + in + + 12 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + ID + Id + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + NUM_LANES + Num Lanes + 4 + + + NUM_CHANNELS + Num Channels + 2 + + + SAMPLES_PER_FRAME + Samples Per Frame + 1 + + + CONVERTER_RESOLUTION + Converter Resolution + 16 + + + BITS_PER_SAMPLE + Bits Per Sample + 16 + + + DMA_BITS_PER_SAMPLE + Dma Bits Per Sample + 16 + + + PADDING_TO_MSB_LSB_N + Padding To Msb Lsb N + 0 + + + OCTETS_PER_BEAT + Octets Per Beat + 4 + + + DDS_TYPE + Dds Type + 1 + + + DDS_CORDIC_DW + Dds Cordic Dw + 16 + + + DDS_CORDIC_PHASE_DW + Dds Cordic Phase Dw + 16 + + + DDS_PHASE_DW + Dds Phase Dw + 16 + + + DATAPATH_DISABLE + Datapath Disable + 0 + + + IQCORRECTION_DISABLE + Iqcorrection Disable + 1 + + + EXT_SYNC + Ext Sync + 0 + + + XBAR_ENABLE + Xbar Enable + 0 + + + + + + choice_list_6e77d344 + 1 + 2 + 4 + 6 + 8 + 16 + 32 + 64 + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_list_7540484d + 8 + 12 + 16 + + + choice_list_8be817d0 + 4 + 6 + 8 + 12 + 16 + 32 + 64 + + + choice_list_9840f1e7 + 1 + 2 + 3 + 4 + 6 + 8 + 12 + 16 + 24 + 32 + + + choice_list_e05731dc + 8 + 11 + 12 + 16 + + + choice_list_eace76f4 + 1 + 2 + 3 + 4 + 6 + 8 + 12 + 16 + + + choice_pairs_00ecfe9a + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + 11 + 12 + 13 + 14 + 15 + 16 + 17 + 18 + 19 + 20 + + + choice_pairs_19f99f31 + 0 + 10 + 11 + 12 + 13 + 14 + 20 + 21 + 22 + 23 + 24 + 25 + 30 + + + choice_pairs_28f798a2 + 0 + 1 + 2 + 3 + 4 + + + choice_pairs_978e9846 + 0 + 1 + + + choice_pairs_fc01a186 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../../xilinx/common/up_xfer_cntrl_constr.xdc + xdc + + + ../../xilinx/common/ad_rst_constr.xdc + xdc + + + ../../xilinx/common/up_xfer_status_constr.xdc + xdc + + + ../../xilinx/common/up_clock_mon_constr.xdc + xdc + + + ../../common/ad_dds.v + verilogSource + + + ../../common/ad_dds_1.v + verilogSource + + + ../../common/ad_dds_2.v + verilogSource + + + ../../common/ad_dds_cordic_pipe.v + verilogSource + + + ../../common/ad_dds_sine.v + verilogSource + + + ../../common/ad_dds_sine_cordic.v + verilogSource + + + ad_ip_jesd204_tpl_dac_channel.v + verilogSource + + + ad_ip_jesd204_tpl_dac_core.v + verilogSource + + + ad_ip_jesd204_tpl_dac_framer.v + verilogSource + + + ad_ip_jesd204_tpl_dac_pn.v + verilogSource + + + ad_ip_jesd204_tpl_dac_regmap.v + verilogSource + + + ../../common/ad_iqcor.v + verilogSource + + + ../../xilinx/common/ad_mul.v + verilogSource + + + ../../common/ad_mux.v + verilogSource + + + ../../common/ad_mux_core.v + verilogSource + + + ../../common/ad_perfect_shuffle.v + verilogSource + + + ../../common/ad_rst.v + verilogSource + + + ../../common/up_axi.v + verilogSource + + + ../../common/up_clock_mon.v + verilogSource + + + ../../common/up_dac_channel.v + verilogSource + + + ../../common/up_dac_common.v + verilogSource + + + ../ad_ip_jesd204_tpl_common/up_tpl_common.v + verilogSource + + + ../../common/up_xfer_cntrl.v + verilogSource + + + ../../common/up_xfer_status.v + verilogSource + + + ../../common/util_ext_sync.v + verilogSource + + + ad_ip_jesd204_tpl_dac.v + verilogSource + CHECKSUM_1106ebc2 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../common/ad_dds.v + verilogSource + + + ../../common/ad_dds_1.v + verilogSource + + + ../../common/ad_dds_2.v + verilogSource + + + ../../common/ad_dds_cordic_pipe.v + verilogSource + + + ../../common/ad_dds_sine.v + verilogSource + + + ../../common/ad_dds_sine_cordic.v + verilogSource + + + ad_ip_jesd204_tpl_dac_channel.v + verilogSource + + + ad_ip_jesd204_tpl_dac_core.v + verilogSource + + + ad_ip_jesd204_tpl_dac_framer.v + verilogSource + + + ad_ip_jesd204_tpl_dac_pn.v + verilogSource + + + ad_ip_jesd204_tpl_dac_regmap.v + verilogSource + + + ../../common/ad_iqcor.v + verilogSource + + + ../../xilinx/common/ad_mul.v + verilogSource + + + ../../common/ad_mux.v + verilogSource + + + ../../common/ad_mux_core.v + verilogSource + + + ../../common/ad_perfect_shuffle.v + verilogSource + + + ../../common/ad_rst.v + verilogSource + + + ../../common/up_axi.v + verilogSource + + + ../../common/up_clock_mon.v + verilogSource + + + ../../common/up_dac_channel.v + verilogSource + + + ../../common/up_dac_common.v + verilogSource + + + ../ad_ip_jesd204_tpl_common/up_tpl_common.v + verilogSource + + + ../../common/up_xfer_cntrl.v + verilogSource + + + ../../common/up_xfer_status.v + verilogSource + + + ../../common/util_ext_sync.v + verilogSource + + + ad_ip_jesd204_tpl_dac.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/ad_ip_jesd204_tpl_dac_v1_0.tcl + tclSource + CHECKSUM_cffb7772 + XGUI_VERSION_2 + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + xilinx_utilityxitfiles_view_fileset + + gui/ad_ip_jesd204_tpl_dac_v1_0.gtcl + GTCL + + + + JESD204 Transport Layer for DACs + + + ID + Core ID + 0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + NUM_LANES + Number of Lanes (L) + 4 + + + NUM_CHANNELS + Number of Conveters (M) + 2 + + + SAMPLES_PER_FRAME + Samples per Frame (S) + 1 + + + CONVERTER_RESOLUTION + Converter Resolution (N) + 16 + + + BITS_PER_SAMPLE + Bits per Sample (N') + 16 + + + DMA_BITS_PER_SAMPLE + DMA Bits per Sample + 16 + + + PADDING_TO_MSB_LSB_N + Padding To Msb Lsb N + 0 + + + OCTETS_PER_BEAT + Octets per Beat + 4 + + + DDS_TYPE + DDS Type + 1 + + + + true + + + + + + DDS_CORDIC_DW + CORDIC DDS Data Width + 16 + + + + true + + + + + + DDS_CORDIC_PHASE_DW + CORDIC DDS Phase Width + 16 + + + + true + + + + + + DDS_PHASE_DW + DDS Phase Width + 16 + + + DATAPATH_DISABLE + Disable Datapath + 0 + + + IQCORRECTION_DISABLE + Disable IQ Correction + 1 + + + EXT_SYNC + Enable external SYNC + 0 + + + XBAR_ENABLE + Enable user data XBAR + 0 + + + Component_Name + ad_ip_jesd204_tpl_dac_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + JESD204 Transport Layer for DACs + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/peripherals/jesd204/jesd204_tpl_dac + 1 + 2024-01-14T03:50:42Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/gui/ad_ip_jesd204_tpl_dac_v1_0.gtcl b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/gui/ad_ip_jesd204_tpl_dac_v1_0.gtcl new file mode 100644 index 00000000..7009ef51 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/gui/ad_ip_jesd204_tpl_dac_v1_0.gtcl @@ -0,0 +1,4 @@ +# This file is automatically written. Do not modify. +proc gen_USERPARAMETER_DDS_TYPE_ENABLEMENT {DATAPATH_DISABLE } {expr $DATAPATH_DISABLE == 0} +proc gen_USERPARAMETER_DDS_CORDIC_DW_ENABLEMENT {DATAPATH_DISABLE DDS_TYPE } {expr $DATAPATH_DISABLE == 0 && $DDS_TYPE == 1} +proc gen_USERPARAMETER_DDS_CORDIC_PHASE_DW_ENABLEMENT {DATAPATH_DISABLE DDS_TYPE } {expr $DATAPATH_DISABLE == 0 && $DDS_TYPE == 1} diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/scripts/generate_presets.py b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/scripts/generate_presets.py new file mode 100755 index 00000000..62ad6017 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/scripts/generate_presets.py @@ -0,0 +1,53 @@ +#!/usr/bin/env python3 + +############################################################################### +## Copyright (C) 2018 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +import math +import os +import sys + +path = os.path.dirname(sys.argv[0]) + +f = open(os.path.join(path, 'modes.txt')) + +conv = {} + +for l in f: + if l[0] == "#": + continue + + x = l.split() + if len(x) == 0: + continue + if len(x) == 1: + name = x[0] + modes = [] + conv[name] = modes + continue + modes.append(list(map(int, x))) + +f.close() + +for name, modes in conv.items(): + f = open(os.path.join(path, '..', '{}.qprs'.format(name)), 'w') + + f.write('\n\n') + for m in modes: + f.write('\t\n'.format(name, m[0], name)) + f.write('\t\t\n'.format(name)) + f.write('\t\t\n'.format(m[1])) + f.write('\t\t\n'.format(m[2])) + if math.gcd(m[4], m[3]) != 1: + f.write('\t\t\n') + else: + f.write('\t\t\n') + f.write('\t\t\n'.format(m[3])) + f.write('\t\t\n'.format(m[6])) + f.write('\t\t\n'.format(m[7])) + f.write('\t\n') + + f.write('\n') + f.close() diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/scripts/modes.txt b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/scripts/modes.txt new file mode 100644 index 00000000..f45d2074 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/scripts/modes.txt @@ -0,0 +1,121 @@ +# Mode M L S F HD N NP +AD9135 +8 1 4 2 1 1 16 16 +9 1 2 1 1 1 16 16 +10 1 1 1 2 0 16 16 +11 2 8 2 1 1 16 16 +12 2 4 1 1 1 16 16 +13 2 2 1 2 0 16 16 + +AD9136 +8 1 4 2 1 1 16 16 +9 1 2 1 1 1 16 16 +10 1 1 1 2 0 16 16 +11 2 8 2 1 1 16 16 +12 2 4 1 1 1 16 16 +13 2 2 1 2 0 16 16 + +AD9144 +0 4 8 1 1 1 16 16 +1 4 8 2 2 0 16 16 +2 4 4 1 2 0 16 16 +3 4 2 1 4 0 16 16 +4 2 4 1 1 1 16 16 +5 2 4 2 2 0 16 16 +6 2 2 1 2 0 16 16 +7 2 1 1 4 0 16 16 +9 1 2 1 1 1 16 16 +10 1 1 1 2 0 16 16 + +AD9152 +4 2 4 1 1 1 16 16 +5 2 4 2 2 0 16 16 +6 2 2 1 2 0 16 16 +7 2 1 1 4 0 16 16 +9 1 2 1 1 1 16 16 +10 1 1 1 2 0 16 16 + +AD9154 +0 4 8 1 1 1 16 16 +1 4 8 2 2 0 16 16 +2 4 4 1 2 0 16 16 +3 4 2 1 4 0 16 16 +4 2 4 1 1 1 16 16 +5 2 4 2 2 0 16 16 +6 2 2 1 2 0 16 16 +7 2 1 1 4 0 16 16 +9 1 2 1 1 1 16 16 +10 1 1 1 2 0 16 16 + +AD9161 +1 2 1 1 4 1 16 16 +2 2 2 2 2 1 16 16 +3 2 3 3 4 1 16 16 +4 2 4 1 1 1 16 16 +6 2 6 3 2 1 16 16 +8 2 8 2 1 1 16 16 + +AD9162 +1 2 1 1 4 1 16 16 +2 2 2 2 2 1 16 16 +3 2 3 3 4 1 16 16 +4 2 4 1 1 1 16 16 +6 2 6 3 2 1 16 16 +8 2 8 2 1 1 16 16 + +AD9163 +1 2 1 1 4 1 16 16 +2 2 2 2 2 1 16 16 +3 2 3 3 4 1 16 16 +4 2 4 1 1 1 16 16 +6 2 6 3 2 1 16 16 +8 2 8 2 1 1 16 16 + +AD9164 +1 2 1 1 4 1 16 16 +2 2 2 2 2 1 16 16 +3 2 3 3 4 1 16 16 +4 2 4 1 1 1 16 16 +6 2 6 3 2 1 16 16 +8 2 8 2 1 1 16 16 + +AD9171 +0 2 1 1 4 1 16 16 +3 2 2 1 2 1 16 16 +5 2 1 1 3 1 12 12 + +AD9172 +0 2 1 1 4 1 16 16 +1 4 2 1 4 1 16 16 +2 6 3 1 4 1 16 16 +3 2 2 1 2 1 16 16 +4 4 4 1 2 1 16 16 +5 2 1 1 3 1 12 12 +6 4 2 1 3 1 12 12 +7 4 1 1 8 1 16 16 +8 2 4 1 1 1 16 16 +9 2 4 2 2 1 16 16 +10 2 8 2 1 1 16 16 +11 2 8 4 2 1 16 16 +12 2 8 8 3 1 12 12 +18 1 4 2 1 1 16 16 +19 1 4 4 2 1 16 16 +20 1 8 4 1 1 16 16 +21 1 8 8 2 1 16 16 + +AD9173 +0 2 1 1 4 1 16 16 +1 4 2 1 4 1 16 16 +2 6 3 1 4 1 16 16 +3 2 2 1 2 1 16 16 +4 4 4 1 2 1 16 16 +5 2 1 1 3 1 12 12 +6 4 2 1 3 1 12 12 +7 4 1 1 8 1 16 16 +8 2 4 1 1 1 16 16 +9 2 4 2 2 1 16 16 +13 2 4 1 1 1 11 16 +14 2 4 2 2 1 11 16 +15 2 8 2 1 1 11 16 +16 2 8 4 2 1 11 16 +17 2 8 8 3 1 11 12 diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/temporary_case_dependencies.mk b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/jesd204/ad_ip_jesd204_tpl_dac/xgui/ad_ip_jesd204_tpl_dac_v1_0.tcl b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/xgui/ad_ip_jesd204_tpl_dac_v1_0.tcl new file mode 100644 index 00000000..706eb668 --- /dev/null +++ b/adi_library/jesd204/ad_ip_jesd204_tpl_dac/xgui/ad_ip_jesd204_tpl_dac_v1_0.tcl @@ -0,0 +1,372 @@ + +# Loading additional proc with user specified bodies to compute parameter values. +source [file join [file dirname [file dirname [info script]]] gui/ad_ip_jesd204_tpl_dac_v1_0.gtcl] + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "PADDING_TO_MSB_LSB_N" -parent ${Page_0} + #Adding Group + set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${Page_0}] + ipgui::add_param $IPINST -name "ID" -parent ${General_Configuration} + + #Adding Group + set JESD204_Framer_Configuration [ipgui::add_group $IPINST -name "JESD204 Framer Configuration" -parent ${Page_0} -display_name {JESD204 Framer Cofiguration}] + ipgui::add_param $IPINST -name "NUM_LANES" -parent ${JESD204_Framer_Configuration} -widget comboBox + ipgui::add_param $IPINST -name "NUM_CHANNELS" -parent ${JESD204_Framer_Configuration} -widget comboBox + ipgui::add_param $IPINST -name "BITS_PER_SAMPLE" -parent ${JESD204_Framer_Configuration} -widget comboBox + ipgui::add_param $IPINST -name "DMA_BITS_PER_SAMPLE" -parent ${JESD204_Framer_Configuration} -widget comboBox + ipgui::add_param $IPINST -name "CONVERTER_RESOLUTION" -parent ${JESD204_Framer_Configuration} -widget comboBox + ipgui::add_param $IPINST -name "SAMPLES_PER_FRAME" -parent ${JESD204_Framer_Configuration} -widget comboBox + ipgui::add_param $IPINST -name "OCTETS_PER_BEAT" -parent ${JESD204_Framer_Configuration} -widget comboBox + + #Adding Group + set Datapath_Configuration [ipgui::add_group $IPINST -name "Datapath Configuration" -parent ${Page_0} -display_name {Datapath Cofiguration}] + ipgui::add_param $IPINST -name "DATAPATH_DISABLE" -parent ${Datapath_Configuration} -widget checkBox + ipgui::add_param $IPINST -name "EXT_SYNC" -parent ${Datapath_Configuration} -widget checkBox + ipgui::add_param $IPINST -name "IQCORRECTION_DISABLE" -parent ${Datapath_Configuration} -widget checkBox + ipgui::add_param $IPINST -name "XBAR_ENABLE" -parent ${Datapath_Configuration} -widget checkBox + ipgui::add_param $IPINST -name "DDS_TYPE" -parent ${Datapath_Configuration} -widget comboBox + ipgui::add_param $IPINST -name "DDS_PHASE_DW" -parent ${Datapath_Configuration} + ipgui::add_param $IPINST -name "DDS_CORDIC_DW" -parent ${Datapath_Configuration} + ipgui::add_param $IPINST -name "DDS_CORDIC_PHASE_DW" -parent ${Datapath_Configuration} + + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.DDS_CORDIC_DW { PARAM_VALUE.DDS_CORDIC_DW PARAM_VALUE.DATAPATH_DISABLE PARAM_VALUE.DDS_TYPE } { + # Procedure called to update DDS_CORDIC_DW when any of the dependent parameters in the arguments change + + set DDS_CORDIC_DW ${PARAM_VALUE.DDS_CORDIC_DW} + set DATAPATH_DISABLE ${PARAM_VALUE.DATAPATH_DISABLE} + set DDS_TYPE ${PARAM_VALUE.DDS_TYPE} + set values(DATAPATH_DISABLE) [get_property value $DATAPATH_DISABLE] + set values(DDS_TYPE) [get_property value $DDS_TYPE] + if { [gen_USERPARAMETER_DDS_CORDIC_DW_ENABLEMENT $values(DATAPATH_DISABLE) $values(DDS_TYPE)] } { + set_property enabled true $DDS_CORDIC_DW + } else { + set_property enabled false $DDS_CORDIC_DW + } +} + +proc validate_PARAM_VALUE.DDS_CORDIC_DW { PARAM_VALUE.DDS_CORDIC_DW } { + # Procedure called to validate DDS_CORDIC_DW + return true +} + +proc update_PARAM_VALUE.DDS_CORDIC_PHASE_DW { PARAM_VALUE.DDS_CORDIC_PHASE_DW PARAM_VALUE.DATAPATH_DISABLE PARAM_VALUE.DDS_TYPE } { + # Procedure called to update DDS_CORDIC_PHASE_DW when any of the dependent parameters in the arguments change + + set DDS_CORDIC_PHASE_DW ${PARAM_VALUE.DDS_CORDIC_PHASE_DW} + set DATAPATH_DISABLE ${PARAM_VALUE.DATAPATH_DISABLE} + set DDS_TYPE ${PARAM_VALUE.DDS_TYPE} + set values(DATAPATH_DISABLE) [get_property value $DATAPATH_DISABLE] + set values(DDS_TYPE) [get_property value $DDS_TYPE] + if { [gen_USERPARAMETER_DDS_CORDIC_PHASE_DW_ENABLEMENT $values(DATAPATH_DISABLE) $values(DDS_TYPE)] } { + set_property enabled true $DDS_CORDIC_PHASE_DW + } else { + set_property enabled false $DDS_CORDIC_PHASE_DW + } +} + +proc validate_PARAM_VALUE.DDS_CORDIC_PHASE_DW { PARAM_VALUE.DDS_CORDIC_PHASE_DW } { + # Procedure called to validate DDS_CORDIC_PHASE_DW + return true +} + +proc update_PARAM_VALUE.DDS_TYPE { PARAM_VALUE.DDS_TYPE PARAM_VALUE.DATAPATH_DISABLE } { + # Procedure called to update DDS_TYPE when any of the dependent parameters in the arguments change + + set DDS_TYPE ${PARAM_VALUE.DDS_TYPE} + set DATAPATH_DISABLE ${PARAM_VALUE.DATAPATH_DISABLE} + set values(DATAPATH_DISABLE) [get_property value $DATAPATH_DISABLE] + if { [gen_USERPARAMETER_DDS_TYPE_ENABLEMENT $values(DATAPATH_DISABLE)] } { + set_property enabled true $DDS_TYPE + } else { + set_property enabled false $DDS_TYPE + } +} + +proc validate_PARAM_VALUE.DDS_TYPE { PARAM_VALUE.DDS_TYPE } { + # Procedure called to validate DDS_TYPE + return true +} + +proc update_PARAM_VALUE.BITS_PER_SAMPLE { PARAM_VALUE.BITS_PER_SAMPLE } { + # Procedure called to update BITS_PER_SAMPLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BITS_PER_SAMPLE { PARAM_VALUE.BITS_PER_SAMPLE } { + # Procedure called to validate BITS_PER_SAMPLE + return true +} + +proc update_PARAM_VALUE.CONVERTER_RESOLUTION { PARAM_VALUE.CONVERTER_RESOLUTION } { + # Procedure called to update CONVERTER_RESOLUTION when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CONVERTER_RESOLUTION { PARAM_VALUE.CONVERTER_RESOLUTION } { + # Procedure called to validate CONVERTER_RESOLUTION + return true +} + +proc update_PARAM_VALUE.DATAPATH_DISABLE { PARAM_VALUE.DATAPATH_DISABLE } { + # Procedure called to update DATAPATH_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATAPATH_DISABLE { PARAM_VALUE.DATAPATH_DISABLE } { + # Procedure called to validate DATAPATH_DISABLE + return true +} + +proc update_PARAM_VALUE.DDS_PHASE_DW { PARAM_VALUE.DDS_PHASE_DW } { + # Procedure called to update DDS_PHASE_DW when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DDS_PHASE_DW { PARAM_VALUE.DDS_PHASE_DW } { + # Procedure called to validate DDS_PHASE_DW + return true +} + +proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to validate DEV_PACKAGE + return true +} + +proc update_PARAM_VALUE.DMA_BITS_PER_SAMPLE { PARAM_VALUE.DMA_BITS_PER_SAMPLE } { + # Procedure called to update DMA_BITS_PER_SAMPLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_BITS_PER_SAMPLE { PARAM_VALUE.DMA_BITS_PER_SAMPLE } { + # Procedure called to validate DMA_BITS_PER_SAMPLE + return true +} + +proc update_PARAM_VALUE.EXT_SYNC { PARAM_VALUE.EXT_SYNC } { + # Procedure called to update EXT_SYNC when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.EXT_SYNC { PARAM_VALUE.EXT_SYNC } { + # Procedure called to validate EXT_SYNC + return true +} + +proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to validate FPGA_FAMILY + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.IQCORRECTION_DISABLE { PARAM_VALUE.IQCORRECTION_DISABLE } { + # Procedure called to update IQCORRECTION_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IQCORRECTION_DISABLE { PARAM_VALUE.IQCORRECTION_DISABLE } { + # Procedure called to validate IQCORRECTION_DISABLE + return true +} + +proc update_PARAM_VALUE.NUM_CHANNELS { PARAM_VALUE.NUM_CHANNELS } { + # Procedure called to update NUM_CHANNELS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_CHANNELS { PARAM_VALUE.NUM_CHANNELS } { + # Procedure called to validate NUM_CHANNELS + return true +} + +proc update_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } { + # Procedure called to update NUM_LANES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } { + # Procedure called to validate NUM_LANES + return true +} + +proc update_PARAM_VALUE.OCTETS_PER_BEAT { PARAM_VALUE.OCTETS_PER_BEAT } { + # Procedure called to update OCTETS_PER_BEAT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OCTETS_PER_BEAT { PARAM_VALUE.OCTETS_PER_BEAT } { + # Procedure called to validate OCTETS_PER_BEAT + return true +} + +proc update_PARAM_VALUE.PADDING_TO_MSB_LSB_N { PARAM_VALUE.PADDING_TO_MSB_LSB_N } { + # Procedure called to update PADDING_TO_MSB_LSB_N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PADDING_TO_MSB_LSB_N { PARAM_VALUE.PADDING_TO_MSB_LSB_N } { + # Procedure called to validate PADDING_TO_MSB_LSB_N + return true +} + +proc update_PARAM_VALUE.SAMPLES_PER_FRAME { PARAM_VALUE.SAMPLES_PER_FRAME } { + # Procedure called to update SAMPLES_PER_FRAME when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SAMPLES_PER_FRAME { PARAM_VALUE.SAMPLES_PER_FRAME } { + # Procedure called to validate SAMPLES_PER_FRAME + return true +} + +proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to validate SPEED_GRADE + return true +} + +proc update_PARAM_VALUE.XBAR_ENABLE { PARAM_VALUE.XBAR_ENABLE } { + # Procedure called to update XBAR_ENABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.XBAR_ENABLE { PARAM_VALUE.XBAR_ENABLE } { + # Procedure called to validate XBAR_ENABLE + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY} +} + +proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE} +} + +proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE} +} + +proc update_MODELPARAM_VALUE.NUM_LANES { MODELPARAM_VALUE.NUM_LANES PARAM_VALUE.NUM_LANES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_LANES}] ${MODELPARAM_VALUE.NUM_LANES} +} + +proc update_MODELPARAM_VALUE.NUM_CHANNELS { MODELPARAM_VALUE.NUM_CHANNELS PARAM_VALUE.NUM_CHANNELS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_CHANNELS}] ${MODELPARAM_VALUE.NUM_CHANNELS} +} + +proc update_MODELPARAM_VALUE.SAMPLES_PER_FRAME { MODELPARAM_VALUE.SAMPLES_PER_FRAME PARAM_VALUE.SAMPLES_PER_FRAME } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SAMPLES_PER_FRAME}] ${MODELPARAM_VALUE.SAMPLES_PER_FRAME} +} + +proc update_MODELPARAM_VALUE.CONVERTER_RESOLUTION { MODELPARAM_VALUE.CONVERTER_RESOLUTION PARAM_VALUE.CONVERTER_RESOLUTION } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CONVERTER_RESOLUTION}] ${MODELPARAM_VALUE.CONVERTER_RESOLUTION} +} + +proc update_MODELPARAM_VALUE.BITS_PER_SAMPLE { MODELPARAM_VALUE.BITS_PER_SAMPLE PARAM_VALUE.BITS_PER_SAMPLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BITS_PER_SAMPLE}] ${MODELPARAM_VALUE.BITS_PER_SAMPLE} +} + +proc update_MODELPARAM_VALUE.DMA_BITS_PER_SAMPLE { MODELPARAM_VALUE.DMA_BITS_PER_SAMPLE PARAM_VALUE.DMA_BITS_PER_SAMPLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_BITS_PER_SAMPLE}] ${MODELPARAM_VALUE.DMA_BITS_PER_SAMPLE} +} + +proc update_MODELPARAM_VALUE.PADDING_TO_MSB_LSB_N { MODELPARAM_VALUE.PADDING_TO_MSB_LSB_N PARAM_VALUE.PADDING_TO_MSB_LSB_N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PADDING_TO_MSB_LSB_N}] ${MODELPARAM_VALUE.PADDING_TO_MSB_LSB_N} +} + +proc update_MODELPARAM_VALUE.OCTETS_PER_BEAT { MODELPARAM_VALUE.OCTETS_PER_BEAT PARAM_VALUE.OCTETS_PER_BEAT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OCTETS_PER_BEAT}] ${MODELPARAM_VALUE.OCTETS_PER_BEAT} +} + +proc update_MODELPARAM_VALUE.DDS_TYPE { MODELPARAM_VALUE.DDS_TYPE PARAM_VALUE.DDS_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DDS_TYPE}] ${MODELPARAM_VALUE.DDS_TYPE} +} + +proc update_MODELPARAM_VALUE.DDS_CORDIC_DW { MODELPARAM_VALUE.DDS_CORDIC_DW PARAM_VALUE.DDS_CORDIC_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DDS_CORDIC_DW}] ${MODELPARAM_VALUE.DDS_CORDIC_DW} +} + +proc update_MODELPARAM_VALUE.DDS_CORDIC_PHASE_DW { MODELPARAM_VALUE.DDS_CORDIC_PHASE_DW PARAM_VALUE.DDS_CORDIC_PHASE_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DDS_CORDIC_PHASE_DW}] ${MODELPARAM_VALUE.DDS_CORDIC_PHASE_DW} +} + +proc update_MODELPARAM_VALUE.DDS_PHASE_DW { MODELPARAM_VALUE.DDS_PHASE_DW PARAM_VALUE.DDS_PHASE_DW } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DDS_PHASE_DW}] ${MODELPARAM_VALUE.DDS_PHASE_DW} +} + +proc update_MODELPARAM_VALUE.DATAPATH_DISABLE { MODELPARAM_VALUE.DATAPATH_DISABLE PARAM_VALUE.DATAPATH_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATAPATH_DISABLE}] ${MODELPARAM_VALUE.DATAPATH_DISABLE} +} + +proc update_MODELPARAM_VALUE.IQCORRECTION_DISABLE { MODELPARAM_VALUE.IQCORRECTION_DISABLE PARAM_VALUE.IQCORRECTION_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IQCORRECTION_DISABLE}] ${MODELPARAM_VALUE.IQCORRECTION_DISABLE} +} + +proc update_MODELPARAM_VALUE.EXT_SYNC { MODELPARAM_VALUE.EXT_SYNC PARAM_VALUE.EXT_SYNC } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.EXT_SYNC}] ${MODELPARAM_VALUE.EXT_SYNC} +} + +proc update_MODELPARAM_VALUE.XBAR_ENABLE { MODELPARAM_VALUE.XBAR_ENABLE PARAM_VALUE.XBAR_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.XBAR_ENABLE}] ${MODELPARAM_VALUE.XBAR_ENABLE} +} + diff --git a/adi_library/jesd204/axi_jesd204_common/Makefile b/adi_library/jesd204/axi_jesd204_common/Makefile new file mode 100644 index 00000000..23f935a4 --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_common/Makefile @@ -0,0 +1,18 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_jesd204_common + +GENERIC_DEPS += jesd204_up_common.v +GENERIC_DEPS += jesd204_up_sysref.v + +XILINX_DEPS += ../../common/up_clock_mon.v +XILINX_DEPS += ../../xilinx/common/up_clock_mon_constr.xdc +XILINX_DEPS += axi_jesd204_common_ip.tcl + +XILINX_LIB_DEPS += util_cdc + +include ../../scripts/library.mk diff --git a/adi_library/jesd204/axi_jesd204_common/axi_jesd204_common.xpr b/adi_library/jesd204/axi_jesd204_common/axi_jesd204_common.xpr new file mode 100644 index 00000000..2479ca22 --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_common/axi_jesd204_common.xpr @@ -0,0 +1,420 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.tcl b/adi_library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.tcl new file mode 100644 index 00000000..3d7d74b6 --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.tcl @@ -0,0 +1,31 @@ +############################################################################### +## Copyright (C) 2016, 2017, 2019, 2022, 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create axi_jesd204_common + +add_files -fileset [get_filesets sources_1] [list \ + "../../xilinx/common/up_clock_mon_constr.xdc" \ + "../../common/up_clock_mon.v" \ + "jesd204_up_common.v" \ + "jesd204_up_sysref.v" \ +] + +set_property source_mgmt_mode DisplayOnly [current_project] + +adi_ip_properties_lite axi_jesd204_common + +adi_ip_add_core_dependencies [list \ + analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \ +] +set_property display_name "ADI AXI JESD204B Common Library" [ipx::current_core] +set_property description "ADI AXI JESD204B Common Library" [ipx::current_core] +set_property hide_in_gui {1} [ipx::current_core] + +ipx::save_core [ipx::current_core] diff --git a/adi_library/jesd204/axi_jesd204_common/component.xml b/adi_library/jesd204/axi_jesd204_common/component.xml new file mode 100644 index 00000000..cf06e5d7 --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_common/component.xml @@ -0,0 +1,388 @@ + + + analog.com + user + axi_jesd204_common + 1.0 + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + jesd204_up_sysref + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + c4c41562 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + jesd204_up_sysref + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + dd8aa7f3 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_xpgui_view_fileset + + + + viewChecksum + f92e9879 + + + + + + + up_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + up_reset + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + up_raddr + + in + + 11 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + up_rdata + + out + + 31 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + up_wreq + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + up_waddr + + in + + 11 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + up_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + up_cfg_is_writeable + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + up_cfg_sysref_oneshot + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + up_cfg_lmfc_offset + + out + + 7 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + up_cfg_sysref_disable + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_event_sysref_alignment_error + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_event_sysref_edge + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../../xilinx/common/up_clock_mon_constr.xdc + xdc + + + ../../common/up_clock_mon.v + verilogSource + + + jesd204_up_common.v + verilogSource + + + jesd204_up_sysref.v + verilogSource + CHECKSUM_682078ff + + + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../common/up_clock_mon.v + verilogSource + + + jesd204_up_common.v + verilogSource + + + jesd204_up_sysref.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/jesd204_up_sysref_v1_0.tcl + tclSource + CHECKSUM_f92e9879 + XGUI_VERSION_2 + + + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + ADI AXI JESD204B Common Library + + + Component_Name + jesd204_up_sysref_v1_0 + + + + + + virtex7 + + + /Analog_Devices + + ADI AXI JESD204B Common Library + true + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:50:49Z + + + 2023.2.1 + + + + + + diff --git a/adi_library/jesd204/axi_jesd204_common/jesd204_up_common.v b/adi_library/jesd204/axi_jesd204_common/jesd204_up_common.v new file mode 100755 index 00000000..fe22bcb7 --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_common/jesd204_up_common.v @@ -0,0 +1,399 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_up_common #( + parameter PCORE_VERSION = 0, + parameter PCORE_MAGIC = 0, + parameter ID = 0, + parameter NUM_LANES = 1, + parameter NUM_LINKS = 1, + parameter DATA_PATH_WIDTH_LOG2 = 2, + parameter NUM_IRQS = 1, + parameter EXTRA_CFG_WIDTH = 1, + parameter DEV_EXTRA_CFG_WIDTH = 1, + parameter ENABLE_LINK_STATS = 0 +) ( + input up_clk, + input ext_resetn, + + output up_reset, + + output up_reset_synchronizer, + + input core_clk, + input core_reset_ext, + output core_reset, + + input device_clk, + output device_reset, + + input [11:0] up_raddr, + output reg [31:0] up_rdata, + + input up_wreq, + input [11:0] up_waddr, + input [31:0] up_wdata, + + input [EXTRA_CFG_WIDTH-1:0] up_extra_cfg, + input [DEV_EXTRA_CFG_WIDTH-1:0] up_dev_extra_cfg, + + input [NUM_IRQS-1:0] up_irq_trigger, + output reg irq, + + output up_cfg_is_writeable, + + output reg [NUM_LANES-1:0] core_cfg_lanes_disable = {NUM_LANES{1'b0}}, + output reg [NUM_LINKS-1:0] core_cfg_links_disable = {NUM_LINKS{1'b0}}, + output reg [9:0] core_cfg_octets_per_multiframe = 'h00, + output reg [7:0] core_cfg_octets_per_frame = 'h00, + output reg core_cfg_disable_scrambler = 'h00, + output reg core_cfg_disable_char_replacement = 'h00, + output reg [EXTRA_CFG_WIDTH-1:0] core_extra_cfg = 'h00, + + output reg [DEV_EXTRA_CFG_WIDTH-1:0] device_extra_cfg = 'h00, + + output reg [9:0] device_cfg_octets_per_multiframe = 'h00, + output reg [7:0] device_cfg_octets_per_frame = 'h00, + output reg [7:0] device_cfg_beats_per_multiframe = 'h00, + + input [31:0] status_synth_params0, + input [31:0] status_synth_params1, + input [31:0] status_synth_params2 +); + + reg [31:0] up_scratch = 32'h00000000; + + reg [7:0] up_cfg_octets_per_frame = 'h00; + reg [9:0] up_cfg_octets_per_multiframe = {DATA_PATH_WIDTH_LOG2{1'b1}}; + reg [7:0] up_cfg_beats_per_multiframe = 'h00; + reg [NUM_LANES-1:0] up_cfg_lanes_disable = {NUM_LANES{1'b0}}; + reg [NUM_LINKS-1:0] up_cfg_links_disable = {NUM_LINKS{1'b0}}; + reg up_cfg_disable_char_replacement = 1'b0; + reg up_cfg_disable_scrambler = 1'b0; + + /* Reset for the register map */ + reg [2:0] up_reset_vector = 3'b111; + assign up_reset = up_reset_vector[0]; + + /* Reset signal generation for the JESD core */ + reg [4:0] core_reset_vector = 5'b11111; + assign core_reset = core_reset_vector[0]; + + reg [4:0] device_reset_vector = 5'b11111; + assign device_reset = device_reset_vector[0]; + + /* Transfer the reset signal back to the up domain, used to keep the + * synchronizers in reset until the core is ready. This is done in order to + * prevent bogus data to propagate to the register map. */ + reg [1:0] up_reset_synchronizer_vector = 2'b11; + assign up_reset_synchronizer = up_reset_synchronizer_vector[0]; + + /* + * Synchronize the external core reset to the register map domain so the status + * can be shown in the register map. This is useful for debugging. + */ + reg [1:0] up_core_reset_ext_synchronizer_vector = 2'b11; + wire up_core_reset_ext; + + assign up_core_reset_ext = up_core_reset_ext_synchronizer_vector[0]; + + /* Transfer two cycles before the core comes out of reset */ + wire core_cfg_transfer_en; + assign core_cfg_transfer_en = core_reset_vector[2] ^ core_reset_vector[1]; + + wire device_cfg_transfer_en; + assign device_cfg_transfer_en = device_reset_vector[2] ^ device_reset_vector[1]; + + reg up_reset_core = 1'b1; + + assign up_cfg_is_writeable = up_reset_core; + + always @(posedge up_clk or negedge ext_resetn) begin + if (ext_resetn == 1'b0) begin + up_reset_vector <= 3'b111; + end else begin + up_reset_vector <= {1'b0,up_reset_vector[2:1]}; + end + end + + wire core_reset_all = up_reset_core | core_reset_ext; + + always @(posedge core_clk or posedge core_reset_all) begin + if (core_reset_all == 1'b1) begin + core_reset_vector <= 5'b11111; + end else begin + core_reset_vector <= {1'b0,core_reset_vector[4:1]}; + end + end + + always @(posedge device_clk or posedge core_reset_all) begin + if (core_reset_all == 1'b1) begin + device_reset_vector <= 5'b11111; + end else begin + device_reset_vector <= {1'b0,device_reset_vector[4:1]}; + end + end + + always @(posedge up_clk or posedge core_reset) begin + if (core_reset == 1'b1) begin + up_reset_synchronizer_vector <= 2'b11; + end else begin + up_reset_synchronizer_vector <= {1'b0,up_reset_synchronizer_vector[1]}; + end + end + + always @(posedge up_clk or posedge core_reset_ext) begin + if (core_reset_ext == 1'b1) begin + up_core_reset_ext_synchronizer_vector <= 2'b11; + end else begin + up_core_reset_ext_synchronizer_vector <= {1'b0,up_core_reset_ext_synchronizer_vector[1]}; + end + end + + always @(posedge core_clk) begin + if (core_cfg_transfer_en == 1'b1) begin + core_cfg_octets_per_multiframe <= up_cfg_octets_per_multiframe; + core_cfg_octets_per_frame <= up_cfg_octets_per_frame; + core_cfg_lanes_disable <= up_cfg_lanes_disable; + core_cfg_links_disable <= up_cfg_links_disable; + core_cfg_disable_scrambler <= up_cfg_disable_scrambler; + core_cfg_disable_char_replacement <= up_cfg_disable_char_replacement; + core_extra_cfg <= up_extra_cfg; + end + end + + always @(posedge device_clk) begin + if (device_cfg_transfer_en == 1'b1) begin + device_cfg_octets_per_multiframe <= up_cfg_octets_per_multiframe; + device_cfg_octets_per_frame <= up_cfg_octets_per_frame; + device_cfg_beats_per_multiframe <= up_cfg_beats_per_multiframe; + device_extra_cfg <= up_dev_extra_cfg; + end + end + + /* Interupt handling */ + reg [NUM_IRQS-1:0] up_irq_enable = {NUM_IRQS{1'b0}}; + reg [NUM_IRQS-1:0] up_irq_source = 'h00; + reg [NUM_IRQS-1:0] up_irq_clear; + wire [NUM_IRQS-1:0] up_irq_pending; + + assign up_irq_pending = up_irq_source & up_irq_enable; + + always @(posedge up_clk) begin + if (up_reset == 1'b1) begin + irq <= 1'b0; + end else begin + irq <= |up_irq_pending; + end + end + + always @(posedge up_clk) begin + if (up_reset == 1'b1) begin + up_irq_source <= 'h00; + end else begin + up_irq_source <= (up_irq_source & ~up_irq_clear) | up_irq_trigger; + end + end + + /* Count link enable */ + wire [8*16-1:0] up_irq_event_cnt_bus; + wire [15:0] up_link_enable_cnt_s; + + genvar i; + generate if (ENABLE_LINK_STATS == 1) begin : g_link_stats + + reg [15:0] up_link_enable_cnt = 'h0; + reg up_reset_core_d1 = 'b1; + + wire up_stat_clear; + + assign up_stat_clear = (up_waddr == 12'h0b0 && up_wreq && up_wdata[0]); + + always @(posedge up_clk) begin + up_reset_core_d1 <= up_reset_core; + if (up_stat_clear) begin + up_link_enable_cnt <= 'h0; + end else begin + if (~up_reset_core & up_reset_core_d1) begin + up_link_enable_cnt <= up_link_enable_cnt + 16'd1; + end + end + end + + assign up_link_enable_cnt_s = up_link_enable_cnt; + + /* Count IRQ events for max 8 interrupt sources */ + + for (i = 0; i < NUM_IRQS; i=i+1) begin : irq_cnt + + reg [15:0] up_irq_event_cnt = 'h0; + + always @(posedge up_clk) begin + if (up_stat_clear) begin + up_irq_event_cnt <= 'h0; + end else if (up_irq_trigger[i]) begin + up_irq_event_cnt <= up_irq_event_cnt + 16'd1; + end + end + + assign up_irq_event_cnt_bus[i*16 +: 16] = up_irq_event_cnt; + + end + end else begin : g_no_link_stats + assign up_irq_event_cnt_bus = 'h0; + assign up_link_enable_cnt_s = 'h0; + end + endgenerate + + wire [20:0] clk_mon_count; + wire [20:0] device_clk_mon_count; + + always @(*) begin + case (up_raddr) + /* Standard registers */ + 12'h000: up_rdata = PCORE_VERSION; + 12'h001: up_rdata = ID; + 12'h002: up_rdata = up_scratch; + 12'h003: up_rdata = PCORE_MAGIC; + + /* Core configuration */ + 12'h004: up_rdata = status_synth_params0; + 12'h005: up_rdata = status_synth_params1; + 12'h006: up_rdata = status_synth_params2; + /* 0x07-0x0f reserved for future use */ + /* 0x10-0x1f reserved for core specific HDL configuration information */ + + /* IRQ block */ + 12'h020: up_rdata = up_irq_enable; + 12'h021: up_rdata = up_irq_pending; + 12'h022: up_rdata = up_irq_source; + /* 0x23-0x30 reserved for future use */ + + /* JESD common control */ + 12'h030: up_rdata = up_reset_core; + 12'h031: up_rdata = {up_core_reset_ext, up_reset_synchronizer}; /* core ready */ + 12'h032: up_rdata = {11'h00, clk_mon_count}; /* Make it 16.16 */ + 12'h033: up_rdata = {11'h00, device_clk_mon_count}; /* Make it 16.16 */ + /* 0x34-0x34 reserver for future use */ + + 12'h080: up_rdata = up_cfg_lanes_disable; + /* 0x82-0x83 reserved for future lane disable bits (max 128 lanes) */ + 12'h084: up_rdata = { + /* 24-31 */ 8'h00, /* Reserved for future extensions of octets_per_frame */ + /* 16-23 */ up_cfg_octets_per_frame, + /* 10-15 */ 6'b000000, /* Reserved for future extensions of beats_per_multiframe */ + /* 00-09 */ up_cfg_octets_per_multiframe + }; + 12'h85: up_rdata = { + /* 02-31 */ 30'h00, /* Reserved for future additions */ + /* 01 */ up_cfg_disable_char_replacement, /* Disable character replacement */ + /* 00 */ up_cfg_disable_scrambler /* Disable scrambler */ + }; + 12'h086: up_rdata = up_cfg_links_disable; + 12'h087: up_rdata = up_cfg_beats_per_multiframe; + /* 0x88-0x8f reserved for future use */ + + /* 0x90-0x9f reserved for core specific configuration options */ + + /* 0xb0 Stat control */ + 12'h0b1: up_rdata = up_link_enable_cnt_s; + /* 0xb4-0xb7 IRQ Stat, max 8 interrupt sources */ + 12'h0b4: up_rdata = up_irq_event_cnt_bus[0*32 +: 32]; + 12'h0b5: up_rdata = up_irq_event_cnt_bus[1*32 +: 32]; + 12'h0b6: up_rdata = up_irq_event_cnt_bus[2*32 +: 32]; + 12'h0b7: up_rdata = up_irq_event_cnt_bus[3*32 +: 32]; + + default: up_rdata = 'h00; + endcase + end + + /* IRQ pending register is write-1-to-clear */ + always @(*) begin + if (up_wreq == 1'b1 && up_waddr == 12'h21) begin + up_irq_clear = up_wdata[NUM_IRQS-1:0]; + end else begin + up_irq_clear = {NUM_IRQS{1'b0}}; + end + end + + always @(posedge up_clk) begin + if (up_reset == 1'b1) begin + up_scratch <= 'h00; + up_irq_enable <= {NUM_IRQS{1'b0}}; + up_reset_core <= 1'b1; + + up_cfg_octets_per_frame <= 'h00; + up_cfg_octets_per_multiframe <= {DATA_PATH_WIDTH_LOG2{1'b1}}; + up_cfg_lanes_disable <= {NUM_LANES{1'b0}}; + up_cfg_links_disable <= {NUM_LINKS{1'b0}}; + up_cfg_beats_per_multiframe <= 'h00; + + up_cfg_disable_char_replacement <= 1'b0; + up_cfg_disable_scrambler <= 1'b0; + end else if (up_wreq == 1'b1) begin + case (up_waddr) + /* Standard registers */ + 12'h002: up_scratch <= up_wdata; + + /* IRQ block */ + 12'h020: up_irq_enable <= up_wdata[NUM_IRQS-1:0]; + + /* JESD common control */ + 12'h030: up_reset_core <= up_wdata[0]; + endcase + + /* + * The configuration needs to be static while the core is + * active. To enforce this writes to configuration registers + * will be ignored while the core is out of reset. + */ + if (up_cfg_is_writeable == 1'b1) begin + case (up_waddr) + 12'h080: begin + up_cfg_lanes_disable <= up_wdata[NUM_LANES-1:0]; + end + 12'h084: begin + up_cfg_octets_per_frame <= up_wdata[23:16]; + up_cfg_octets_per_multiframe <= {up_wdata[9:DATA_PATH_WIDTH_LOG2], + {DATA_PATH_WIDTH_LOG2{1'b1}}}; + end + 12'h085: begin + up_cfg_disable_char_replacement <= up_wdata[1]; + up_cfg_disable_scrambler <= up_wdata[0]; + end + 12'h086: begin + up_cfg_links_disable <= up_wdata[NUM_LINKS-1:0]; + end + 12'h087: begin + up_cfg_beats_per_multiframe <= up_wdata[7:0]; + end + endcase + end + end + end + + up_clock_mon #( + .TOTAL_WIDTH(21) + ) i_clock_mon ( + .up_rstn(~up_reset), + .up_clk(up_clk), + .up_d_count(clk_mon_count), + .d_rst(1'b0), + .d_clk(core_clk)); + + up_clock_mon #( + .TOTAL_WIDTH(21) + ) i_dev_clock_mon ( + .up_rstn(~up_reset), + .up_clk(up_clk), + .up_d_count(device_clk_mon_count), + .d_rst(1'b0), + .d_clk(device_clk)); + +endmodule diff --git a/adi_library/jesd204/axi_jesd204_common/jesd204_up_sysref.v b/adi_library/jesd204/axi_jesd204_common/jesd204_up_sysref.v new file mode 100755 index 00000000..9c624922 --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_common/jesd204_up_sysref.v @@ -0,0 +1,107 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2016-2018, 2020-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_up_sysref ( + input up_clk, + input up_reset, + + input core_clk, + + input device_clk, + + input [11:0] up_raddr, + output reg [31:0] up_rdata, + + input up_wreq, + input [11:0] up_waddr, + input [31:0] up_wdata, + + input up_cfg_is_writeable, + + output reg up_cfg_sysref_oneshot, + output reg [7:0] up_cfg_lmfc_offset, + output reg up_cfg_sysref_disable, + + input device_event_sysref_alignment_error, + input device_event_sysref_edge +); + + reg [1:0] up_sysref_status; + reg [1:0] up_sysref_status_clear; + wire [1:0] up_sysref_event; + + sync_event #( + .NUM_OF_EVENTS(2) + ) i_cdc_sysref_event ( + .in_clk(device_clk), + .in_event({ + device_event_sysref_alignment_error, + device_event_sysref_edge + }), + .out_clk(up_clk), + .out_event(up_sysref_event)); + + always @(posedge up_clk) begin + if (up_reset == 1'b1) begin + up_sysref_status <= 2'b00; + end else begin + up_sysref_status <= (up_sysref_status & ~up_sysref_status_clear) | up_sysref_event; + end + end + + always @(*) begin + case (up_raddr) + /* JESD SYSREF configuraton */ + 12'h040: up_rdata = { + /* 02-31 */ 30'h00, /* Reserved for future use */ + /* 01 */ up_cfg_sysref_oneshot, + /* 00 */ up_cfg_sysref_disable + }; + 12'h041: up_rdata = { + /* 10-31 */ 22'h00, /* Reserved for future use */ + /* 02-09 */ up_cfg_lmfc_offset, + /* 00-01 */ 2'b00 /* data path alignment for cfg_lmfc_offset */ + }; + 12'h042: up_rdata = { + /* 02-31 */ 30'h00, + /* 00-01 */ up_sysref_status + }; + default: up_rdata = 32'h00000000; + endcase + end + + always @(posedge up_clk) begin + if (up_reset == 1'b1) begin + up_cfg_sysref_oneshot <= 1'b0; + up_cfg_lmfc_offset <= 'h00; + up_cfg_sysref_disable <= 1'b0; + end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin + case (up_waddr) + /* JESD SYSREF configuraton */ + 12'h040: begin + up_cfg_sysref_oneshot <= up_wdata[1]; + up_cfg_sysref_disable <= up_wdata[0]; + end + 12'h041: begin + /* Must be aligned to data path width */ + up_cfg_lmfc_offset <= up_wdata; + end + endcase + end + end + + always @(*) begin + if (up_wreq == 1'b1 && up_waddr == 12'h042) begin + up_sysref_status_clear = up_wdata[1:0]; + end else begin + up_sysref_status_clear = 2'b00; + end + end + +endmodule diff --git a/adi_library/jesd204/axi_jesd204_common/xgui/jesd204_up_sysref_v1_0.tcl b/adi_library/jesd204/axi_jesd204_common/xgui/jesd204_up_sysref_v1_0.tcl new file mode 100644 index 00000000..0db18e9a --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_common/xgui/jesd204_up_sysref_v1_0.tcl @@ -0,0 +1,10 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + + diff --git a/adi_library/jesd204/axi_jesd204_rx/Makefile b/adi_library/jesd204/axi_jesd204_rx/Makefile new file mode 100644 index 00000000..a9f9f5dd --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_rx/Makefile @@ -0,0 +1,42 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_jesd204_rx + +GENERIC_DEPS += ../../common/up_axi.v +GENERIC_DEPS += axi_jesd204_rx.v +GENERIC_DEPS += jesd204_up_ilas_mem.v +GENERIC_DEPS += jesd204_up_rx.v +GENERIC_DEPS += jesd204_up_rx_lane.v + +XILINX_DEPS += axi_jesd204_rx_constr.xdc +XILINX_DEPS += axi_jesd204_rx_ip.tcl +XILINX_DEPS += axi_jesd204_rx_ooc.ttcl + +XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg_rtl.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_event.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_event_rtl.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config_rtl.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_status.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_status_rtl.xml + +XILINX_LIB_DEPS += jesd204/axi_jesd204_common + +XILINX_INTERFACE_DEPS += jesd204/interfaces + +INTEL_DEPS += ../../common/up_clock_mon.v +INTEL_DEPS += ../../intel/common/up_clock_mon_constr.sdc +INTEL_DEPS += ../../util_cdc/sync_bits.v +INTEL_DEPS += ../../util_cdc/sync_data.v +INTEL_DEPS += ../../util_cdc/sync_event.v +INTEL_DEPS += ../axi_jesd204_common/jesd204_up_common.v +INTEL_DEPS += ../axi_jesd204_common/jesd204_up_sysref.v +INTEL_DEPS += axi_jesd204_rx_constr.sdc +INTEL_DEPS += axi_jesd204_rx_hw.tcl + +include ../../scripts/library.mk diff --git a/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v b/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v new file mode 100755 index 00000000..33ab3424 --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v @@ -0,0 +1,317 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_jesd204_rx #( + parameter ID = 0, + parameter NUM_LANES = 1, + parameter NUM_LINKS = 1, + parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B + parameter ENABLE_LINK_STATS = 0, + parameter DATA_PATH_WIDTH = LINK_MODE == 2 ? 8 : 4 +) ( + input s_axi_aclk, + input s_axi_aresetn, + + input s_axi_awvalid, + input [13:0] s_axi_awaddr, + output s_axi_awready, + input [2:0] s_axi_awprot, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [13:0] s_axi_araddr, + output s_axi_arready, + input [2:0] s_axi_arprot, + output s_axi_rvalid, + input s_axi_rready, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + + output irq, + + input core_clk, + input core_reset_ext, + output core_reset, + + input device_clk, + output device_reset, + + output [NUM_LANES-1:0] core_cfg_lanes_disable, + output [NUM_LINKS-1:0] core_cfg_links_disable, + output [9:0] core_cfg_octets_per_multiframe, + output [7:0] core_cfg_octets_per_frame, + output core_cfg_disable_scrambler, + output core_cfg_disable_char_replacement, + output [7:0] core_cfg_frame_align_err_threshold, + + output [9:0] device_cfg_octets_per_multiframe, + output [7:0] device_cfg_octets_per_frame, + output [7:0] device_cfg_beats_per_multiframe, + output [7:0] device_cfg_lmfc_offset, + output device_cfg_sysref_oneshot, + output device_cfg_sysref_disable, + output device_cfg_buffer_early_release, + output [7:0] device_cfg_buffer_delay, + + input [NUM_LANES-1:0] core_ilas_config_valid, + input [2*NUM_LANES-1:0] core_ilas_config_addr, + input [NUM_LANES*DATA_PATH_WIDTH*8-1:0] core_ilas_config_data, + + input device_event_sysref_alignment_error, + input device_event_sysref_edge, + input core_event_frame_alignment_error, + input core_event_unexpected_lane_state_error, + + output [6:0] core_ctrl_err_statistics_mask, + output core_ctrl_err_statistics_reset, + + input [32*NUM_LANES-1:0] core_status_err_statistics_cnt, + + input [1:0] core_status_ctrl_state, + input [2*NUM_LANES-1:0] core_status_lane_cgs_state, + input [3*NUM_LANES-1:0] core_status_lane_emb_state, + input [NUM_LANES-1:0] core_status_lane_ifs_ready, + input [14*NUM_LANES-1:0] core_status_lane_latency, + input [8*NUM_LANES-1:0] core_status_lane_frame_align_err_cnt, + + input [31:0] status_synth_params0, + input [31:0] status_synth_params1, + input [31:0] status_synth_params2 +); + + localparam PCORE_VERSION = 32'h00010761; // 1.07.a + localparam PCORE_MAGIC = 32'h32303452; // 204R + + /* Register interface signals */ + reg [31:0] up_rdata = 'h0; + reg up_wack = 1'b0; + reg up_rack = 1'b0; + reg up_rreq_d1 = 1'b0; + wire up_wreq; + wire up_rreq; + wire [31:0] up_wdata; + wire [11:0] up_waddr; + wire [11:0] up_raddr; + wire [31:0] up_rdata_common; + wire [31:0] up_rdata_sysref; + wire [31:0] up_rdata_rx; + + wire [4:0] up_irq_trigger; + + wire up_cfg_is_writeable; + wire up_cfg_sysref_oneshot; + wire up_cfg_sysref_disable; + wire up_cfg_buffer_early_release; + wire [7:0] up_cfg_buffer_delay; + wire [7:0] up_cfg_lmfc_offset; + wire [7:0] up_cfg_frame_align_err_threshold; + + wire up_reset; + wire up_reset_synchronizer; + wire up_event_frame_alignment_error; + wire up_event_unexpected_lane_state_error; + + sync_event #( + .NUM_OF_EVENTS (2) + ) i_sync_frame_align_err ( + .in_clk(core_clk), + .in_event({core_event_unexpected_lane_state_error, + core_event_frame_alignment_error}), + .out_clk(s_axi_aclk), + .out_event({up_event_unexpected_lane_state_error, + up_event_frame_alignment_error})); + + assign up_irq_trigger = {3'b0, + up_event_unexpected_lane_state_error, + up_event_frame_alignment_error} & + {5{~up_cfg_is_writeable}}; + + up_axi #( + .AXI_ADDRESS_WIDTH (14) + ) i_up_axi ( + .up_rstn(~up_reset), + .up_clk(s_axi_aclk), + .up_axi_awvalid(s_axi_awvalid), + .up_axi_awaddr(s_axi_awaddr), + .up_axi_awready(s_axi_awready), + .up_axi_wvalid(s_axi_wvalid), + .up_axi_wdata(s_axi_wdata), + .up_axi_wstrb(s_axi_wstrb), + .up_axi_wready(s_axi_wready), + .up_axi_bvalid(s_axi_bvalid), + .up_axi_bresp(s_axi_bresp), + .up_axi_bready(s_axi_bready), + .up_axi_arvalid(s_axi_arvalid), + .up_axi_araddr(s_axi_araddr), + .up_axi_arready(s_axi_arready), + .up_axi_rvalid(s_axi_rvalid), + .up_axi_rresp(s_axi_rresp), + .up_axi_rdata(s_axi_rdata), + .up_axi_rready(s_axi_rready), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_wack(up_wack), + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata), + .up_rack(up_rack)); + + jesd204_up_common #( + .PCORE_VERSION(PCORE_VERSION), + .PCORE_MAGIC(PCORE_MAGIC), + .ID(ID), + .NUM_LANES(NUM_LANES), + .NUM_LINKS(NUM_LINKS), + .NUM_IRQS(5), + .EXTRA_CFG_WIDTH(8), + .DEV_EXTRA_CFG_WIDTH(19), + .ENABLE_LINK_STATS(ENABLE_LINK_STATS) + ) i_up_common ( + .up_clk(s_axi_aclk), + .ext_resetn(s_axi_aresetn), + + .up_reset(up_reset), + .up_reset_synchronizer(up_reset_synchronizer), + + .core_clk(core_clk), + .core_reset_ext(core_reset_ext), + .core_reset(core_reset), + + .device_clk(device_clk), + .device_reset(device_reset), + + .up_raddr(up_raddr), + .up_rdata(up_rdata_common), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + + .up_cfg_is_writeable(up_cfg_is_writeable), + + .up_irq_trigger(up_irq_trigger), + .irq(irq), + + .core_cfg_octets_per_multiframe(core_cfg_octets_per_multiframe), + .core_cfg_octets_per_frame(core_cfg_octets_per_frame), + .core_cfg_lanes_disable(core_cfg_lanes_disable), + .core_cfg_links_disable(core_cfg_links_disable), + .core_cfg_disable_scrambler(core_cfg_disable_scrambler), + .core_cfg_disable_char_replacement(core_cfg_disable_char_replacement), + + .up_extra_cfg({ + /* 00-07 */ up_cfg_frame_align_err_threshold + }), + .core_extra_cfg({ + /* 00-07 */ core_cfg_frame_align_err_threshold + }), + + .device_cfg_octets_per_multiframe(device_cfg_octets_per_multiframe), + .device_cfg_octets_per_frame(device_cfg_octets_per_frame), + .device_cfg_beats_per_multiframe(device_cfg_beats_per_multiframe), + + .up_dev_extra_cfg({ + /* 18 */ up_cfg_sysref_disable, + /* 17 */ up_cfg_sysref_oneshot, + /* 16 */ up_cfg_buffer_early_release, + /* 15-08 */ up_cfg_buffer_delay, + /* 00-07 */ up_cfg_lmfc_offset + }), + .device_extra_cfg({ + /* 18 */ device_cfg_sysref_disable, + /* 17 */ device_cfg_sysref_oneshot, + /* 16 */ device_cfg_buffer_early_release, + /* 15-08 */ device_cfg_buffer_delay, + /* 00-07 */ device_cfg_lmfc_offset + }), + + .status_synth_params0(status_synth_params0), + .status_synth_params1(status_synth_params1), + .status_synth_params2(status_synth_params2)); + + jesd204_up_sysref i_up_sysref ( + .up_clk(s_axi_aclk), + .up_reset(up_reset), + + .core_clk(core_clk), + .device_clk(device_clk), + .device_event_sysref_edge(device_event_sysref_edge), + .device_event_sysref_alignment_error(device_event_sysref_alignment_error), + + .up_raddr(up_raddr), + .up_rdata(up_rdata_sysref), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + + .up_cfg_is_writeable(up_cfg_is_writeable), + + .up_cfg_lmfc_offset(up_cfg_lmfc_offset), + .up_cfg_sysref_oneshot(up_cfg_sysref_oneshot), + .up_cfg_sysref_disable(up_cfg_sysref_disable)); + + jesd204_up_rx #( + .NUM_LANES(NUM_LANES), + .DATA_PATH_WIDTH(DATA_PATH_WIDTH) + ) i_up_rx ( + .up_clk(s_axi_aclk), + .up_reset(up_reset), + .up_reset_synchronizer(up_reset_synchronizer), + + .core_clk(core_clk), + .core_reset(core_reset), + + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata_rx), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + + .up_cfg_is_writeable(up_cfg_is_writeable), + + .up_cfg_buffer_early_release(up_cfg_buffer_early_release), + .up_cfg_buffer_delay(up_cfg_buffer_delay), + + .up_cfg_frame_align_err_threshold(up_cfg_frame_align_err_threshold), + + .core_ctrl_err_statistics_reset(core_ctrl_err_statistics_reset), + .core_ctrl_err_statistics_mask(core_ctrl_err_statistics_mask), + + .core_status_ctrl_state(core_status_ctrl_state), + .core_status_lane_cgs_state(core_status_lane_cgs_state), + .core_status_lane_emb_state(core_status_lane_emb_state), + .core_status_lane_ifs_ready(core_status_lane_ifs_ready), + .core_status_lane_latency(core_status_lane_latency), + .core_status_lane_frame_align_err_cnt(core_status_lane_frame_align_err_cnt), + + .core_status_err_statistics_cnt(core_status_err_statistics_cnt), + + .core_ilas_config_valid(core_ilas_config_valid), + .core_ilas_config_addr(core_ilas_config_addr), + .core_ilas_config_data(core_ilas_config_data)); + + always @(posedge s_axi_aclk) begin + up_wack <= up_wreq; + + // ILAS memory takes one clock cycle before the data is ready, hence the extra + // delay. + up_rreq_d1 <= up_rreq; + up_rack <= up_rreq_d1; + if (up_rreq_d1 == 1'b1) begin + up_rdata <= up_rdata_common | up_rdata_sysref | up_rdata_rx; + end + end + +endmodule diff --git a/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx.xpr b/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx.xpr new file mode 100644 index 00000000..e4f01124 --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx.xpr @@ -0,0 +1,435 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.sdc b/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.sdc new file mode 100644 index 00000000..0b9c16f9 --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.sdc @@ -0,0 +1,54 @@ +############################################################################### +## Copyright (C) 2016-2018, 2021 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +set script_dir [file dirname [info script]] + +source "$script_dir/util_cdc_constr.tcl" + +util_cdc_sync_data_constr {*|jesd204_up_rx:i_up_rx|sync_data:i_cdc_status} +util_cdc_sync_data_constr {*|jesd204_up_rx:i_up_rx|sync_data:i_cdc_cfg} +util_cdc_sync_event_constr {*|jesd204_up_sysref:i_up_sysref|sync_event:i_cdc_sysref_event} +util_cdc_sync_bits_constr {*|jesd204_up_rx:i_up_rx|jesd204_up_rx_lane:gen_lane[*].i_up_rx_lane|sync_bits:i_cdc_status_ready} + +# set_max_skew? +set_false_path \ + -to [get_registers {*|jesd204_up_rx:i_up_rx|jesd204_up_rx_lane:gen_lane[*].i_up_rx_lane|up_status_latency[*]}] + +util_cdc_sync_bits_constr {*|jesd204_up_rx:i_up_rx|jesd204_up_rx_lane:gen_lane[*].i_up_rx_lane|jesd204_up_ilas_mem:i_ilas_mem|sync_bits:i_cdc_ilas_ready} + +set_false_path \ + -from [get_registers {*|jesd204_up_common:i_up_common|up_reset_core}] \ + -to [get_registers {*|jesd204_up_common:i_up_common|core_reset_vector[*]}] + +set_false_path \ + -from [get_registers {*|jesd204_up_common:i_up_common|up_reset_core}] \ + -to [get_registers {*|jesd204_up_common:i_up_common|device_reset_vector[*]}] + +set_false_path \ + -from [get_registers {*|jesd204_up_common:i_up_common|core_reset_vector[0]}] \ + -to [get_registers {*|jesd204_up_common:i_up_common|up_reset_synchronizer_vector[*]}] + +set_false_path \ + -to [get_pins -compatibility_mode {*|jesd204_up_common:i_up_common|up_core_reset_ext_synchronizer_vector[*]|clrn}] + +set_false_path \ + -from [get_registers {*|jesd204_up_common:i_up_common|up_cfg_*}] \ + -to [get_registers {*|jesd204_up_common:i_up_common|core_cfg_*}] + +set_false_path \ + -from [get_registers {*|jesd204_up_common:i_up_common|up_cfg_*}] \ + -to [get_registers {*|jesd204_up_common:i_up_common|device_cfg_*}] + +set_false_path \ + -from [get_registers {*|jesd204_up_rx:i_up_rx|up_cfg_*}] \ + -to [get_registers {*|jesd204_up_common:i_up_common|core_extra_cfg[*]}] + +set_false_path \ + -from [get_registers {*|jesd204_up_rx:i_up_rx|up_cfg_*}] \ + -to [get_registers {*|jesd204_up_common:i_up_common|device_extra_cfg[*]}] + +set_false_path \ + -from [get_registers {*|jesd204_up_sysref:i_up_sysref|up_cfg_*}] \ + -to [get_registers {*|jesd204_up_common:i_up_common|device_extra_cfg[*]}] diff --git a/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc b/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc new file mode 100755 index 00000000..aa602336 --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc @@ -0,0 +1,129 @@ +############################################################################### +## Copyright (C) 2016-2018, 2020-2021 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +set axi_clk [get_clocks -of_objects [get_ports s_axi_aclk]] +set core_clk [get_clocks -of_objects [get_ports core_clk]] +set device_clk [get_clocks -of_objects [get_ports device_clk]] + +set_property ASYNC_REG TRUE \ + [get_cells -hier {*cdc_sync_stage1_reg*}] \ + [get_cells -hier {*cdc_sync_stage2_reg*}] + +# Used for synchronizing resets with asynchronous de-assert +set_property ASYNC_REG TRUE \ + [get_cells -hier {up_reset_vector_reg*}] \ + [get_cells -hier {core_reset_vector_reg*}] \ + [get_cells -hier {up_reset_synchronizer_vector_reg*}] \ + [get_cells -hier {up_core_reset_ext_synchronizer_vector_reg*}] + +set_false_path \ + -from [get_pins {i_up_rx/i_cdc_status/in_toggle_d1_reg/C}] \ + -to [get_pins {i_up_rx/i_cdc_status/i_sync_out/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -from [get_pins {i_up_rx/i_cdc_status/out_toggle_d1_reg/C}] \ + -to [get_pins {i_up_rx/i_cdc_status/i_sync_in/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -from [get_pins {i_up_rx/i_cdc_cfg/in_toggle_d1_reg/C}] \ + -to [get_pins {i_up_rx/i_cdc_cfg/i_sync_out/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -from [get_pins {i_up_rx/i_cdc_cfg/out_toggle_d1_reg/C}] \ + -to [get_pins {i_up_rx/i_cdc_cfg/i_sync_in/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -from [get_pins {i_up_sysref/i_cdc_sysref_event/in_toggle_d1_reg/C}] \ + -to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_out/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -from [get_pins {i_up_sysref/i_cdc_sysref_event/out_toggle_d1_reg/C}] \ + -to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_in/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -from [get_pins {i_up_sysref/i_cdc_sysref_event/cdc_hold_reg*/C}] \ + -to [get_pins {i_up_sysref/i_cdc_sysref_event/out_event_reg*/D}] + +set_false_path \ + -from [get_pins {i_sync_frame_align_err/in_toggle_d1_reg/C}] \ + -to [get_pins {i_sync_frame_align_err/i_sync_out/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -from [get_pins {i_sync_frame_align_err/out_toggle_d1_reg/C}] \ + -to [get_pins {i_sync_frame_align_err/i_sync_in/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -from [get_pins {i_sync_frame_align_err/cdc_hold_reg*/C}] \ + -to [get_pins {i_sync_frame_align_err/out_event_reg*/D}] + +# Don't place them too far appart +set_max_delay -datapath_only \ + -from [get_pins {i_up_rx/i_cdc_status/cdc_hold_reg[*]/C}] \ + -to [get_pins {i_up_rx/i_cdc_status/out_data_reg[*]/D}] \ + [get_property -min PERIOD $axi_clk] + +set_false_path \ + -from $core_clk \ + -to [get_pins {i_up_rx/*i_up_rx_lane/i_cdc_status_ready/cdc_sync_stage1_reg*/D}] + +set_max_delay -datapath_only \ + -from [get_pins {i_up_rx/i_cdc_cfg/cdc_hold_reg[*]/C}] \ + -to [get_pins {i_up_rx/i_cdc_cfg/out_data_reg[*]/D}] \ + [get_property -min PERIOD $core_clk] + +set_max_delay -datapath_only \ + -from $core_clk \ + -to [get_pins {i_up_rx/*i_up_rx_lane/up_status_latency_reg[*]/D}] \ + [get_property -min PERIOD $axi_clk] + +set_false_path \ + -from $core_clk \ + -to [get_pins {i_up_rx/*i_up_rx_lane/i_ilas_mem/i_cdc_ilas_ready/cdc_sync_stage1_reg[0]/D}] + +# Use -quiet here since the ILAS mem is missing in non 8b10b configuration +set_max_delay -quiet -datapath_only \ + -from [get_pins {i_up_rx/gen_lane[*].i_up_rx_lane/i_ilas_mem/mem_reg*/*/CLK}] \ + -to [get_pins {i_up_rx/gen_lane[*].i_up_rx_lane/i_ilas_mem/dp_*_gen.up_rdata_reg*/D}] \ + [get_property -min PERIOD $axi_clk] + +set_false_path \ + -from [get_pins {i_up_common/up_reset_core_reg/C}] \ + -to [get_pins {i_up_common/core_reset_vector_reg[*]/PRE}] + +set_false_path \ + -from [get_pins {i_up_common/up_reset_core_reg/C}] \ + -to [get_pins {i_up_common/device_reset_vector_reg[*]/PRE}] + +set_false_path \ + -from [get_pins {i_up_common/core_reset_vector_reg[0]/C}] \ + -to [get_pins {i_up_common/up_reset_synchronizer_vector_reg[*]/PRE}] + +set_false_path \ + -to [get_pins {i_up_common/up_core_reset_ext_synchronizer_vector_reg[*]/PRE}] + +set_max_delay -datapath_only \ + -from [get_pins {i_up_common/up_cfg_*_reg*/C}] \ + -to [get_pins {i_up_common/core_cfg_*_reg*/D}] \ + [get_property -min PERIOD $core_clk] + +set_max_delay -datapath_only \ + -from [get_pins {i_up_common/up_cfg_*_reg*/C}] \ + -to [get_pins {i_up_common/device_cfg_*_reg*/D}] \ + [get_property -min PERIOD $device_clk] + +set_max_delay -datapath_only \ + -from [get_pins {i_up_rx/up_cfg_*_reg*/C}] \ + -to [get_pins {i_up_common/core_extra_cfg_reg[*]/D}] \ + [get_property -min PERIOD $core_clk] + +set_max_delay -datapath_only \ + -from [get_pins {i_up_rx/up_cfg_*_reg*/C}] \ + -to [get_pins {i_up_common/device_extra_cfg_reg[*]/D}] \ + [get_property -min PERIOD $device_clk] + +set_max_delay -datapath_only \ + -from [get_pins {i_up_sysref/up_cfg_*_reg*/C}] \ + -to [get_pins {i_up_common/device_extra_cfg_reg[*]/D}] \ + [get_property -min PERIOD $device_clk] diff --git a/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl b/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl new file mode 100755 index 00000000..836d0638 --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl @@ -0,0 +1,156 @@ +############################################################################### +## Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +package require qsys 14.0 + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl + +ad_ip_create axi_jesd204_rx "ADI JESD204 Receive AXI Interface" + +set_module_property INTERNAL true + +# files + +ad_ip_files axi_jesd204_rx [list \ + axi_jesd204_rx.v \ + axi_jesd204_rx_constr.sdc \ + jesd204_up_rx.v \ + jesd204_up_rx_lane.v \ + jesd204_up_ilas_mem.v \ + ../axi_jesd204_common/jesd204_up_common.v \ + ../axi_jesd204_common/jesd204_up_sysref.v \ + $ad_hdl_dir/library/common/up_axi.v \ + $ad_hdl_dir/library/common/up_clock_mon.v \ + $ad_hdl_dir/library/util_cdc/sync_bits.v \ + $ad_hdl_dir/library/util_cdc/sync_data.v \ + $ad_hdl_dir/library/util_cdc/sync_event.v \ + $ad_hdl_dir/library/util_cdc/util_cdc_constr.tcl \ + $ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \ +] + +# parameters + +add_parameter ID NATURAL 0 +set_parameter_property ID DISPLAY_NAME "Peripheral ID" +set_parameter_property ID HDL_PARAMETER true + +add_parameter NUM_LANES INTEGER 1 +set_parameter_property NUM_LANES DISPLAY_NAME "Number of Lanes" +set_parameter_property NUM_LANES ALLOWED_RANGES 1:32 +set_parameter_property NUM_LANES HDL_PARAMETER true + +add_parameter NUM_LINKS INTEGER 1 +set_parameter_property NUM_LINKS DISPLAY_NAME "Number of Links" +set_parameter_property NUM_LINKS ALLOWED_RANGES 1:8 +set_parameter_property NUM_LINKS HDL_PARAMETER true + +# axi4 slave interface + +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 14 + +# interrupt + +add_interface interrupt interrupt end +set_interface_property interrupt associatedClock s_axi_clock +set_interface_property interrupt associatedReset s_axi_reset +#set_interface_property interrupt associatedAddressablePoint s_axi +add_interface_port interrupt irq irq Output 1 + +# core clock + +add_interface core_clock clock end +add_interface_port core_clock core_clk clk Input 1 + +# device clock + +add_interface device_clock clock end +add_interface_port device_clock device_clk clk Input 1 + +# core reset ext + +add_interface core_reset_ext reset end +set_interface_property core_reset_ext associatedClock core_clock +add_interface_port core_reset_ext core_reset_ext reset Input 1 + +# core reset + +add_interface core_reset reset start +set_interface_property core_reset associatedClock core_clock +set_interface_property core_reset associatedResetSinks core_reset_ext +add_interface_port core_reset core_reset reset Output 1 + +# device reset + +add_interface device_reset reset start +set_interface_property device_reset associatedClock device_clock +set_interface_property device_reset associatedResetSinks core_reset_ext +add_interface_port device_reset device_reset reset Output 1 + +# link clock domain config interface + +add_interface config conduit end +set_interface_property config associatedClock core_clock +set_interface_property config associatedReset core_reset + +add_interface_port config core_cfg_lanes_disable lanes_disable Output NUM_LANES +add_interface_port config core_cfg_links_disable links_disable Output NUM_LINKS +add_interface_port config core_cfg_octets_per_multiframe octets_per_multiframe Output 10 +add_interface_port config core_cfg_octets_per_frame octets_per_frame Output 8 +add_interface_port config core_cfg_disable_scrambler disable_scrambler Output 1 +add_interface_port config core_cfg_disable_char_replacement disable_char_replacement Output 1 +add_interface_port config core_cfg_frame_align_err_threshold frame_align_err_threshold Output 8 +add_interface_port config core_ctrl_err_statistics_reset err_statistics_reset Output 1 +add_interface_port config core_ctrl_err_statistics_mask err_statistics_mask Output 3 + +# device clock domain config interface + +add_interface device_config conduit end +set_interface_property device_config associatedClock device_clock +set_interface_property device_config associatedReset device_reset + +add_interface_port device_config device_cfg_octets_per_multiframe octets_per_multiframe Output 10 +add_interface_port device_config device_cfg_octets_per_frame octets_per_frame Output 8 +add_interface_port device_config device_cfg_beats_per_multiframe beats_per_multiframe Output 8 +add_interface_port device_config device_cfg_lmfc_offset lmfc_offset Output 8 +add_interface_port device_config device_cfg_sysref_disable sysref_disable Output 1 +add_interface_port device_config device_cfg_sysref_oneshot sysref_oneshot Output 1 +add_interface_port device_config device_cfg_buffer_delay buffer_delay Output 8 +add_interface_port device_config device_cfg_buffer_early_release buffer_early_release Output 1 + +# status interface + +add_interface status conduit end +set_interface_property status associatedClock core_clock +set_interface_property status associatedReset core_reset + +add_interface_port status core_status_ctrl_state ctrl_state Input 2 +add_interface_port status core_status_lane_cgs_state lane_cgs_state Input 2*NUM_LANES +add_interface_port status core_status_lane_ifs_ready lane_ifs_ready Input NUM_LANES +add_interface_port status core_status_lane_latency lane_latency Input 14*NUM_LANES +add_interface_port status core_status_lane_frame_align_err_cnt lane_frame_align_err_cnt Input 8*NUM_LANES +add_interface_port status core_status_err_statistics_cnt err_statistics_cnt Input 32*NUM_LANES +add_interface_port status status_synth_params0 synth_params0 Input 32 +add_interface_port status status_synth_params1 synth_params1 Input 32 +add_interface_port status status_synth_params2 synth_params2 Input 32 + +# event interface + +add_interface device_event conduit end +set_interface_property device_event associatedClock device_clock +set_interface_property device_event associatedReset device_reset + +add_interface_port device_event device_event_sysref_alignment_error sysref_alignment_error Input 1 +add_interface_port device_event device_event_sysref_edge sysref_edge Input 1 + +# ilas_config + +add_interface ilas_config conduit end +set_interface_property ilas_config associatedClock core_clock +set_interface_property ilas_config associatedReset core_reset + +add_interface_port ilas_config core_ilas_config_addr addr Input 2*NUM_LANES +add_interface_port ilas_config core_ilas_config_data data Input 32*NUM_LANES +add_interface_port ilas_config core_ilas_config_valid valid Input NUM_LANES diff --git a/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl b/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl new file mode 100755 index 00000000..377e6390 --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl @@ -0,0 +1,126 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create axi_jesd204_rx +adi_ip_files axi_jesd204_rx [list \ + "../../common/up_axi.v" \ + "jesd204_up_rx.v" \ + "jesd204_up_rx_lane.v" \ + "jesd204_up_ilas_mem.v" \ + "axi_jesd204_rx_constr.xdc" \ + "axi_jesd204_rx_ooc.ttcl" \ + "axi_jesd204_rx.v" \ +] + +set_property source_mgmt_mode DisplayOnly [current_project] + +adi_ip_properties axi_jesd204_rx + +adi_ip_ttcl axi_jesd204_rx "axi_jesd204_rx_ooc.ttcl" + +set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_rx} [ipx::current_core] + +set_property PROCESSING_ORDER LATE [ipx::get_files axi_jesd204_rx_constr.xdc \ + -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \ + -filter {NAME =~ *synthesis*}]] + +adi_ip_add_core_dependencies [list \ + analog.com:$VIVADO_IP_LIBRARY:axi_jesd204_common:1.0 \ +] + +set_property display_name "ADI JESD204C Receive AXI Interface" [ipx::current_core] +set_property description "ADI JESD204C Receive AXI Interface" [ipx::current_core] + +adi_add_bus "rx_cfg" "master" \ + "analog.com:interface:jesd204_rx_cfg_rtl:1.0" \ + "analog.com:interface:jesd204_rx_cfg:1.0" \ + { \ + { "core_cfg_lanes_disable" "lanes_disable" } \ + { "core_cfg_links_disable" "links_disable" } \ + { "core_cfg_octets_per_multiframe" "octets_per_multiframe" } \ + { "core_cfg_octets_per_frame" "octets_per_frame" } \ + { "core_cfg_disable_char_replacement" "disable_char_replacement" } \ + { "core_cfg_disable_scrambler" "disable_scrambler" } \ + { "core_cfg_frame_align_err_threshold" "frame_align_err_threshold" } \ + { "device_cfg_octets_per_multiframe" "device_octets_per_multiframe" } \ + { "device_cfg_octets_per_frame" "device_octets_per_frame" } \ + { "device_cfg_beats_per_multiframe" "device_beats_per_multiframe" } \ + { "device_cfg_lmfc_offset" "device_lmfc_offset" } \ + { "device_cfg_sysref_oneshot" "device_sysref_oneshot" } \ + { "device_cfg_sysref_disable" "device_sysref_disable" } \ + { "device_cfg_buffer_early_release" "device_buffer_early_release" } \ + { "device_cfg_buffer_delay" "device_buffer_delay" } \ + { "core_ctrl_err_statistics_reset" "err_statistics_reset" } \ + { "core_ctrl_err_statistics_mask" "err_statistics_mask" } \ + } + +adi_add_bus "rx_ilas_config" "slave" \ + "analog.com:interface:jesd204_rx_ilas_config_rtl:1.0" \ + "analog.com:interface:jesd204_rx_ilas_config:1.0" \ + { \ + { "core_ilas_config_valid" "valid" } \ + { "core_ilas_config_addr" "addr" } \ + { "core_ilas_config_data" "data" } \ + } + +adi_add_bus "rx_event" "slave" \ + "analog.com:interface:jesd204_rx_event_rtl:1.0" \ + "analog.com:interface:jesd204_rx_event:1.0" \ + { \ + { "device_event_sysref_alignment_error" "sysref_alignment_error" } \ + { "device_event_sysref_edge" "sysref_edge" } \ + { "core_event_frame_alignment_error" "frame_alignment_error" } \ + { "core_event_unexpected_lane_state_error" "unexpected_lane_state_error" } \ + } + +adi_add_bus "rx_status" "slave" \ + "analog.com:interface:jesd204_rx_status_rtl:1.0" \ + "analog.com:interface:jesd204_rx_status:1.0" \ + { \ + { "core_status_ctrl_state" "ctrl_state" } \ + { "core_status_lane_cgs_state" "lane_cgs_state" } \ + { "core_status_lane_emb_state" "lane_emb_state" } \ + { "core_status_lane_ifs_ready" "lane_ifs_ready" } \ + { "core_status_lane_latency" "lane_latency" } \ + { "core_status_lane_frame_align_err_cnt" "lane_frame_align_err_cnt" } \ + { "core_status_err_statistics_cnt" "err_statistics_cnt" } \ + { "status_synth_params0" "synth_params0" } \ + { "status_synth_params1" "synth_params1" } \ + { "status_synth_params2" "synth_params2" } \ + } + +ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core] + +adi_add_bus_clock "core_clk" "rx_status:rx_event:rx_ilas_config:rx_cfg" \ + "core_reset" "master" + +set_property DRIVER_VALUE "0" [ipx::get_ports "core_reset_ext"] + +adi_set_bus_dependency "rx_ilas_config" "rx_ilas_config" \ + "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" +set cc [ipx::current_core] +set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] + +# Link layer mode +set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $page0 +set_property -dict [list \ + "display_name" "Link Layer mode" \ + "tooltip" "Link Layer mode" \ + "widget" "comboBox" \ +] $p + +set_property -dict [list \ + value_validation_type pairs \ + value_validation_pairs {64B66B 2 8B10B 1} \ +] [ipx::get_user_parameters $p -of_objects $cc] + +ipx::create_xgui_files [ipx::current_core] +ipx::save_core [ipx::current_core] diff --git a/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ooc.ttcl b/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ooc.ttcl new file mode 100644 index 00000000..a6e0680f --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ooc.ttcl @@ -0,0 +1,23 @@ +############################################################################### +## Copyright (C) 2017-2019, 2021 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +<: setFileUsedIn { out_of_context synthesis implementation } :> +<: ;#Component and file information :> +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName $ComponentName :> +<: setFileExtension "_ooc.xdc" :> + +# This XDC is used only for OOC mode of synthesis, implementation. +# These are default values for timing driven synthesis during OOC flow. +# These values will be overwritten during implementation with information +# from top level. + +create_clock -name s_axi_aclk -period 10 [get_ports s_axi_aclk] +create_clock -name core_clk -period 2.5 [get_ports core_clk] +create_clock -name device_clk -period 2.5 [get_ports device_clk] + +################################################################################ + diff --git a/adi_library/jesd204/axi_jesd204_rx/component.xml b/adi_library/jesd204/axi_jesd204_rx/component.xml new file mode 100644 index 00000000..23cd8670 --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_rx/component.xml @@ -0,0 +1,1848 @@ + + + analog.com + user + axi_jesd204_rx + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + rx_cfg + + + + + + + lanes_disable + + + core_cfg_lanes_disable + + + + + links_disable + + + core_cfg_links_disable + + + + + octets_per_multiframe + + + core_cfg_octets_per_multiframe + + + + + octets_per_frame + + + core_cfg_octets_per_frame + + + + + disable_char_replacement + + + core_cfg_disable_char_replacement + + + + + disable_scrambler + + + core_cfg_disable_scrambler + + + + + frame_align_err_threshold + + + core_cfg_frame_align_err_threshold + + + + + device_octets_per_multiframe + + + device_cfg_octets_per_multiframe + + + + + device_octets_per_frame + + + device_cfg_octets_per_frame + + + + + device_beats_per_multiframe + + + device_cfg_beats_per_multiframe + + + + + device_lmfc_offset + + + device_cfg_lmfc_offset + + + + + device_sysref_oneshot + + + device_cfg_sysref_oneshot + + + + + device_sysref_disable + + + device_cfg_sysref_disable + + + + + device_buffer_early_release + + + device_cfg_buffer_early_release + + + + + device_buffer_delay + + + device_cfg_buffer_delay + + + + + err_statistics_reset + + + core_ctrl_err_statistics_reset + + + + + err_statistics_mask + + + core_ctrl_err_statistics_mask + + + + + + rx_ilas_config + + + + + + + valid + + + core_ilas_config_valid + + + + + addr + + + core_ilas_config_addr + + + + + data + + + core_ilas_config_data + + + + + + + true + + + + + + rx_event + + + + + + + sysref_alignment_error + + + device_event_sysref_alignment_error + + + + + sysref_edge + + + device_event_sysref_edge + + + + + frame_alignment_error + + + core_event_frame_alignment_error + + + + + unexpected_lane_state_error + + + core_event_unexpected_lane_state_error + + + + + + rx_status + + + + + + + ctrl_state + + + core_status_ctrl_state + + + + + lane_cgs_state + + + core_status_lane_cgs_state + + + + + lane_emb_state + + + core_status_lane_emb_state + + + + + lane_ifs_ready + + + core_status_lane_ifs_ready + + + + + lane_latency + + + core_status_lane_latency + + + + + lane_frame_align_err_cnt + + + core_status_lane_frame_align_err_cnt + + + + + err_statistics_cnt + + + core_status_err_statistics_cnt + + + + + synth_params0 + + + status_synth_params0 + + + + + synth_params1 + + + status_synth_params1 + + + + + synth_params2 + + + status_synth_params2 + + + + + + irq + + + + + + + INTERRUPT + + + irq + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + rx_status_rx_event_rx_ilas_config_rx_cfg_signal_clock + rx_status_rx_event_rx_ilas_config_rx_cfg_signal_clock + + + + + + + CLK + + + core_clk + + + + + + ASSOCIATED_BUSIF + rx_status:rx_event:rx_ilas_config:rx_cfg + + + ASSOCIATED_RESET + core_reset + + + + + rx_status_rx_event_rx_ilas_config_rx_cfg_signal_reset + rx_status_rx_event_rx_ilas_config_rx_cfg_signal_reset + + + + + + + RST + + + core_reset + + + + + + POLARITY + ACTIVE_HIGH + + + + + + + s_axi + + axi_lite + 0 + 16384 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_jesd204_rx + + xilinx_anylanguagesynthesis_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + ee177bde + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_jesd204_rx + + xilinx_anylanguagebehavioralsimulation_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 5ba02ad7 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset + + + xilinx_xpgui_view_fileset + + + + viewChecksum + 3df09e24 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 13 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 13 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + irq + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_reset_ext + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + core_reset + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_reset + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_cfg_lanes_disable + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_cfg_links_disable + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_cfg_octets_per_multiframe + + out + + 9 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_cfg_octets_per_frame + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_cfg_disable_scrambler + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_cfg_disable_char_replacement + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_cfg_frame_align_err_threshold + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_octets_per_multiframe + + out + + 9 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_octets_per_frame + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_beats_per_multiframe + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_lmfc_offset + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_sysref_oneshot + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_sysref_disable + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_buffer_early_release + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_buffer_delay + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_ilas_config_valid + + in + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_ilas_config_addr + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_ilas_config_data + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + device_event_sysref_alignment_error + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_event_sysref_edge + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_event_frame_alignment_error + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_event_unexpected_lane_state_error + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_ctrl_err_statistics_mask + + out + + 6 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_ctrl_err_statistics_reset + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_status_err_statistics_cnt + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_status_ctrl_state + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_status_lane_cgs_state + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_status_lane_emb_state + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_status_lane_ifs_ready + + in + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_status_lane_latency + + in + + 13 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_status_lane_frame_align_err_cnt + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + status_synth_params0 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + status_synth_params1 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + status_synth_params2 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + ID + Id + 0 + + + NUM_LANES + Num Lanes + 1 + + + NUM_LINKS + Num Links + 1 + + + LINK_MODE + Link Mode + 1 + + + ENABLE_LINK_STATS + Enable Link Stats + 0 + + + DATA_PATH_WIDTH + Data Path Width + 4 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_list_9ca20931 + LEVEL_HIGH + LEVEL_LOW + EDGE_RISING + EDGE_FALLING + + + choice_pairs_1942b210 + 2 + 1 + + + + + xilinx_anylanguagesynthesis_view_fileset + + axi_jesd204_rx_ooc.ttcl + ttcl + + + axi_jesd204_rx_constr.xdc + xdc + + processing_order + late + + + + ../../common/up_axi.v + verilogSource + + + jesd204_up_rx.v + verilogSource + + + jesd204_up_rx_lane.v + verilogSource + + + jesd204_up_ilas_mem.v + verilogSource + + + axi_jesd204_rx.v + verilogSource + CHECKSUM_d579961a + + + + xilinx_anylanguagesynthesis_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../common/up_axi.v + verilogSource + + + jesd204_up_rx.v + verilogSource + + + jesd204_up_rx_lane.v + verilogSource + + + jesd204_up_ilas_mem.v + verilogSource + + + axi_jesd204_rx.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axi_jesd204_rx_v1_0.tcl + tclSource + CHECKSUM_397049c5 + XGUI_VERSION_2 + + + + xilinx_xpgui_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset + + + + + + + + ADI JESD204C Receive AXI Interface + + + ID + Id + 0 + + + NUM_LANES + Num Lanes + 1 + + + NUM_LINKS + Num Links + 1 + + + LINK_MODE + Link Layer mode + 1 + + + ENABLE_LINK_STATS + Enable Link Stats + 0 + + + DATA_PATH_WIDTH + Data Path Width + 4 + + + Component_Name + axi_jesd204_rx_v1_0 + + + + + + virtex7 + + + /Analog_Devices + + ADI JESD204C Receive AXI Interface + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_rx + 1 + 2024-01-14T03:51:05Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v b/adi_library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v new file mode 100755 index 00000000..dd3815d2 --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_rx/jesd204_up_ilas_mem.v @@ -0,0 +1,98 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2016-2019, 2021-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_up_ilas_mem #( + parameter DATA_PATH_WIDTH = 4 +) ( + input up_clk, + + input up_rreq, + input [1:0] up_raddr, + output reg [31:0] up_rdata, + + input core_clk, + input core_reset, + + input core_ilas_config_valid, + input [1:0] core_ilas_config_addr, + input [DATA_PATH_WIDTH*8-1:0] core_ilas_config_data, + + output up_ilas_ready +); + + localparam ILAS_DATA_LENGTH = (DATA_PATH_WIDTH == 4) ? 4 : 2; + + reg [DATA_PATH_WIDTH*8-1:0] mem[0:ILAS_DATA_LENGTH-1]; + reg core_ilas_captured = 1'b0; + + sync_bits i_cdc_ilas_ready ( + .in_bits(core_ilas_captured), + .out_resetn(1'b1), + .out_clk(up_clk), + .out_bits(up_ilas_ready)); + + always @(posedge core_clk) begin + if (core_reset == 1'b1) begin + core_ilas_captured <= 1'b0; + end else begin + if (core_ilas_config_valid == 1'b1 && core_ilas_config_addr == ILAS_DATA_LENGTH-1) begin + core_ilas_captured <= 1'b1; + end + end + end + + generate + if(DATA_PATH_WIDTH == 4) begin : dp_4_gen + always @(posedge up_clk) begin + if (up_rreq == 1'b1) begin + up_rdata <= mem[up_raddr]; + end + end + end else if(DATA_PATH_WIDTH == 8) begin : dp_8_gen + always @(posedge up_clk) begin + if (up_rreq == 1'b1) begin + up_rdata <= mem[up_raddr[1]] >> (up_raddr[0]*32); + end + end + end + endgenerate + + always @(posedge core_clk) begin + if (core_ilas_config_valid == 1'b1) begin + mem[core_ilas_config_addr] <= core_ilas_config_data; + end + end + + /* + * Shift register with variable tap for accessing the stored data. + * + * This has slightly better utilization on Xilinx based platforms than the dual + * port RAM approach, but there is no equivalent primitive on Intel resulting + * in increased utilization since it needs to be implemented used registers and + * muxes. + * + * We might make this a device dependent configuration option at some point. + + reg [3:0] mem[0:31]; + + generate + genvar i; + for (i = 0; i < 32; i = i + 1) begin: gen_ilas_mem + assign up_rdata[i] = mem[i][~up_raddr]; + + always @(posedge core_clk) begin + if (core_ilas_config_valid == 1'b1) begin + mem[i] <= {mem[i][2:0],core_ilas_config_data[i]}; + end + end + end + endgenerate + */ + +endmodule diff --git a/adi_library/jesd204/axi_jesd204_rx/jesd204_up_rx.v b/adi_library/jesd204/axi_jesd204_rx/jesd204_up_rx.v new file mode 100755 index 00000000..29eecfa6 --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_rx/jesd204_up_rx.v @@ -0,0 +1,199 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2016-2018, 2020-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_up_rx #( + parameter NUM_LANES = 1, + parameter DATA_PATH_WIDTH = 4 +) ( + input up_clk, + input up_reset, + input up_reset_synchronizer, + + input up_rreq, + input [11:0] up_raddr, + output reg [31:0] up_rdata, + input up_wreq, + input [11:0] up_waddr, + input [31:0] up_wdata, + + input core_clk, + input core_reset, + + input [NUM_LANES-1:0] core_ilas_config_valid, + input [2*NUM_LANES-1:0] core_ilas_config_addr, + input [NUM_LANES*DATA_PATH_WIDTH*8-1:0] core_ilas_config_data, + + input [1:0] core_status_ctrl_state, + input [2*NUM_LANES-1:0] core_status_lane_cgs_state, + input [3*NUM_LANES-1:0] core_status_lane_emb_state, + input [NUM_LANES-1:0] core_status_lane_ifs_ready, + input [14*NUM_LANES-1:0] core_status_lane_latency, + input [8*NUM_LANES-1:0] core_status_lane_frame_align_err_cnt, + + input [32*NUM_LANES-1:0] core_status_err_statistics_cnt, + output [6:0] core_ctrl_err_statistics_mask, + output core_ctrl_err_statistics_reset, + + input up_cfg_is_writeable, + output reg up_cfg_buffer_early_release, + output reg [7:0] up_cfg_buffer_delay, + + output reg [7:0] up_cfg_frame_align_err_threshold +); + + localparam ELASTIC_BUFFER_SIZE = 256; + + wire [1:0] up_status_ctrl_state; + wire [2*NUM_LANES-1:0] up_status_lane_cgs_state; + wire [8*NUM_LANES-1:0] up_status_lane_frame_align_err_cnt; + wire [3*NUM_LANES-1:0] up_status_lane_emb_state; + wire [31:0] up_lane_rdata[0:NUM_LANES-1]; + wire [32*NUM_LANES-1:0] up_status_err_statistics_cnt; + + reg up_ctrl_err_statistics_reset = 0; + reg [6:0] up_ctrl_err_statistics_mask = 7'h0; + + sync_data #( + .NUM_OF_BITS(2+NUM_LANES*(3+2+32+8)) + ) i_cdc_status ( + .in_clk(core_clk), + .in_data({ + core_status_err_statistics_cnt, + core_status_ctrl_state, + core_status_lane_cgs_state, + core_status_lane_emb_state, + core_status_lane_frame_align_err_cnt + }), + .out_clk(up_clk), + .out_data({ + up_status_err_statistics_cnt, + up_status_ctrl_state, + up_status_lane_cgs_state, + up_status_lane_emb_state, + up_status_lane_frame_align_err_cnt + })); + + sync_data #( + .NUM_OF_BITS(8) + ) i_cdc_cfg ( + .in_clk(up_clk), + .in_data({ + up_ctrl_err_statistics_mask, + up_ctrl_err_statistics_reset + }), + .out_clk(core_clk), + .out_data({ + core_ctrl_err_statistics_mask, + core_ctrl_err_statistics_reset + })); + + localparam LANE_BASE_ADDR = 'h300 / 32; + + always @(*) begin + case (up_raddr) + /* Core configuration */ + 12'h010: up_rdata = ELASTIC_BUFFER_SIZE; /* Elastic buffer size in octets */ + + /* JESD RX configuraton */ + 12'h090: up_rdata = { + /* 17-31 */ 15'h00, /* Reserved for future additions */ + /* 16 */ up_cfg_buffer_early_release, /* Release buffer as soon as all lanes are ready. */ + /* 10-15 */ 6'b0000, /* Reserved for future extensions of buffer_delay */ + /* 02-09 */ up_cfg_buffer_delay, /* Buffer release delay */ + /* 00-01 */ 2'b00 /* Data path width alignment */ + }; + 12'h91: up_rdata = { + /* 15-31 */ 17'h00, /* Reserved for future additions */ + /* 08-14 */ up_ctrl_err_statistics_mask, + /* 01-07 */ 7'h0, + /* 00 */ up_ctrl_err_statistics_reset + }; + 12'h92: up_rdata = { + /* 08-31 */ 24'h0, + /* 00-07 */ up_cfg_frame_align_err_threshold + }; + + /* 0x93-0x9f reserved for future use */ + + /* JESD RX status */ + 12'ha0: up_rdata = { + /* 04-31 */ 28'h00, /* Reserved for future additions */ + /* 02-03 */ 2'b00, /* Reserved for future extensions of ctrl_state */ + /* 00-01 */ up_status_ctrl_state /* State of the internal state machine */ + }; + default: begin + if (up_raddr[11:3] >= LANE_BASE_ADDR && + up_raddr[11:3] < LANE_BASE_ADDR + NUM_LANES) begin + up_rdata = up_lane_rdata[up_raddr[11:3] - LANE_BASE_ADDR]; + end else begin + up_rdata = 'h00; + end + end + endcase + end + + always @(posedge up_clk) begin + if (up_reset == 1'b1) begin + up_cfg_buffer_early_release <= 1'b0; + up_cfg_buffer_delay <= 'h00; + up_ctrl_err_statistics_mask <= 7'h0; + up_ctrl_err_statistics_reset <= 1'b0; + up_cfg_frame_align_err_threshold <= 8'd4; + end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin + case (up_waddr) + /* JESD RX configuraton */ + 12'h090: begin + up_cfg_buffer_early_release <= up_wdata[16]; + up_cfg_buffer_delay <= up_wdata[7:0]; + end + endcase + end else if (up_wreq == 1'b1) begin + case (up_waddr) + 12'h91: begin + up_ctrl_err_statistics_mask <= up_wdata[14:8]; + up_ctrl_err_statistics_reset <= up_wdata[0]; + end + 12'h92: begin + up_cfg_frame_align_err_threshold <= up_wdata[7:0]; + end + endcase + end + end + + genvar i; + generate for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane + jesd204_up_rx_lane #( + .DATA_PATH_WIDTH(DATA_PATH_WIDTH) + ) i_up_rx_lane ( + .up_clk(up_clk), + .up_reset_synchronizer(up_reset_synchronizer), + + .up_rreq(up_rreq), + .up_raddr(up_raddr[2:0]), + .up_rdata(up_lane_rdata[i]), + + .up_status_cgs_state(up_status_lane_cgs_state[2*i+1:2*i]), + .up_status_err_statistics_cnt(up_status_err_statistics_cnt[32*i+31:32*i]), + .up_status_emb_state(up_status_lane_emb_state[3*i+2:3*i]), + .up_status_lane_frame_align_err_cnt(up_status_lane_frame_align_err_cnt[8*i+7:8*i]), + + .core_clk(core_clk), + .core_reset(core_reset), + + .core_ilas_config_valid(core_ilas_config_valid[i]), + .core_ilas_config_addr(core_ilas_config_addr[2*i+1:2*i]), + .core_ilas_config_data(core_ilas_config_data[(DATA_PATH_WIDTH*8*i)+(DATA_PATH_WIDTH*8)-1:DATA_PATH_WIDTH*8*i]), + + .core_status_ifs_ready(core_status_lane_ifs_ready[i]), + .core_status_latency(core_status_lane_latency[14*i+13:14*i])); + end + + endgenerate + +endmodule diff --git a/adi_library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v b/adi_library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v new file mode 100755 index 00000000..649b7547 --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_rx/jesd204_up_rx_lane.v @@ -0,0 +1,117 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_up_rx_lane #( + parameter DATA_PATH_WIDTH = 4 +) ( + input up_clk, + input up_reset_synchronizer, + + input up_rreq, + input [2:0] up_raddr, + output reg [31:0] up_rdata, + + input [1:0] up_status_cgs_state, + input [31:0] up_status_err_statistics_cnt, + input [2:0] up_status_emb_state, + input [7:0] up_status_lane_frame_align_err_cnt, + + input core_clk, + input core_reset, + + input core_ilas_config_valid, + input [1:0] core_ilas_config_addr, + input [DATA_PATH_WIDTH*8-1:0] core_ilas_config_data, + + input core_status_ifs_ready, + input [13:0] core_status_latency +); + + wire [1:0] up_status_ctrl_state; + + wire up_status_ifs_ready; + reg [13:0] up_status_latency = 'h00; + + wire [31:0] up_ilas_rdata; + wire up_ilas_ready; + + sync_bits #( + .NUM_OF_BITS(1) + ) i_cdc_status_ready ( + .in_bits({ + core_status_ifs_ready + }), + .out_clk(up_clk), + .out_resetn(1'b1), + .out_bits({ + up_status_ifs_ready + })); + + always @(posedge up_clk) begin + if (up_reset_synchronizer == 1'b1) begin + up_status_latency <= 'h00; + end else begin + if (up_status_ifs_ready == 1'b1) begin + up_status_latency <= core_status_latency; + end + end + end + + always @(*) begin + if (up_raddr[2] == 1'b1) begin + if (up_ilas_ready == 1'b1) begin + up_rdata = up_ilas_rdata; + end else begin + up_rdata = 'h00; + end + end else begin + case (up_raddr[1:0]) + 2'b00: up_rdata = { + /* 11-31 */ 21'h0, /* Reserved for future use */ + /* 08-10 */ up_status_emb_state, + /* 06-07 */ 2'h00, + /* 05 */ up_ilas_ready, + /* 04 */ up_status_ifs_ready, + /* 02-03 */ 2'b00, /* Reserved for future extensions of cgs_state */ + /* 00-01 */ up_status_cgs_state + }; + 2'b01: up_rdata = { + /* 14-31 */ 18'h00, /* Reserved for future use */ + /* 00-13 */ up_status_latency + }; + 2'b10: up_rdata = { + /* 00-31 */ up_status_err_statistics_cnt + }; + 2'b11: up_rdata = { + /* 08-31 */ 24'h0, /* Reserved for future use */ + /* 00-07 */ up_status_lane_frame_align_err_cnt + }; + default: up_rdata = 'h00; + endcase + end + end + + jesd204_up_ilas_mem #( + .DATA_PATH_WIDTH(DATA_PATH_WIDTH) + ) i_ilas_mem ( + .up_clk(up_clk), + + .up_rreq(up_rreq), + .up_raddr(up_raddr[1:0]), + .up_rdata(up_ilas_rdata), + .up_ilas_ready(up_ilas_ready), + + .core_clk(core_clk), + .core_reset(core_reset), + + .core_ilas_config_valid(core_ilas_config_valid), + .core_ilas_config_addr(core_ilas_config_addr), + .core_ilas_config_data(core_ilas_config_data)); + +endmodule diff --git a/adi_library/jesd204/axi_jesd204_rx/xgui/axi_jesd204_rx_v1_0.tcl b/adi_library/jesd204/axi_jesd204_rx/xgui/axi_jesd204_rx_v1_0.tcl new file mode 100644 index 00000000..6ebad412 --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_rx/xgui/axi_jesd204_rx_v1_0.tcl @@ -0,0 +1,100 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "LINK_MODE" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "DATA_PATH_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "ENABLE_LINK_STATS" -parent ${Page_0} + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_LANES" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_LINKS" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH } { + # Procedure called to update DATA_PATH_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH } { + # Procedure called to validate DATA_PATH_WIDTH + return true +} + +proc update_PARAM_VALUE.ENABLE_LINK_STATS { PARAM_VALUE.ENABLE_LINK_STATS } { + # Procedure called to update ENABLE_LINK_STATS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ENABLE_LINK_STATS { PARAM_VALUE.ENABLE_LINK_STATS } { + # Procedure called to validate ENABLE_LINK_STATS + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } { + # Procedure called to update LINK_MODE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } { + # Procedure called to validate LINK_MODE + return true +} + +proc update_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } { + # Procedure called to update NUM_LANES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } { + # Procedure called to validate NUM_LANES + return true +} + +proc update_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } { + # Procedure called to update NUM_LINKS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } { + # Procedure called to validate NUM_LINKS + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.NUM_LANES { MODELPARAM_VALUE.NUM_LANES PARAM_VALUE.NUM_LANES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_LANES}] ${MODELPARAM_VALUE.NUM_LANES} +} + +proc update_MODELPARAM_VALUE.NUM_LINKS { MODELPARAM_VALUE.NUM_LINKS PARAM_VALUE.NUM_LINKS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_LINKS}] ${MODELPARAM_VALUE.NUM_LINKS} +} + +proc update_MODELPARAM_VALUE.LINK_MODE { MODELPARAM_VALUE.LINK_MODE PARAM_VALUE.LINK_MODE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LINK_MODE}] ${MODELPARAM_VALUE.LINK_MODE} +} + +proc update_MODELPARAM_VALUE.ENABLE_LINK_STATS { MODELPARAM_VALUE.ENABLE_LINK_STATS PARAM_VALUE.ENABLE_LINK_STATS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ENABLE_LINK_STATS}] ${MODELPARAM_VALUE.ENABLE_LINK_STATS} +} + +proc update_MODELPARAM_VALUE.DATA_PATH_WIDTH { MODELPARAM_VALUE.DATA_PATH_WIDTH PARAM_VALUE.DATA_PATH_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_PATH_WIDTH}] ${MODELPARAM_VALUE.DATA_PATH_WIDTH} +} + diff --git a/adi_library/jesd204/axi_jesd204_tx/Makefile b/adi_library/jesd204/axi_jesd204_tx/Makefile new file mode 100644 index 00000000..fde19573 --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_tx/Makefile @@ -0,0 +1,42 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_jesd204_tx + +GENERIC_DEPS += ../../common/up_axi.v +GENERIC_DEPS += axi_jesd204_tx.v +GENERIC_DEPS += jesd204_up_tx.v + +XILINX_DEPS += axi_jesd204_tx_constr.xdc +XILINX_DEPS += axi_jesd204_tx_ip.tcl +XILINX_DEPS += axi_jesd204_tx_ooc.ttcl + +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg_rtl.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl_rtl.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_event.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_event_rtl.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config_rtl.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_status.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_status_rtl.xml + +XILINX_LIB_DEPS += jesd204/axi_jesd204_common + +XILINX_INTERFACE_DEPS += jesd204/interfaces + +INTEL_DEPS += ../../common/up_clock_mon.v +INTEL_DEPS += ../../intel/common/up_clock_mon_constr.sdc +INTEL_DEPS += ../../util_cdc/sync_bits.v +INTEL_DEPS += ../../util_cdc/sync_data.v +INTEL_DEPS += ../../util_cdc/sync_event.v +INTEL_DEPS += ../axi_jesd204_common/jesd204_up_common.v +INTEL_DEPS += ../axi_jesd204_common/jesd204_up_sysref.v +INTEL_DEPS += axi_jesd204_tx_constr.sdc +INTEL_DEPS += axi_jesd204_tx_hw.tcl + +include ../../scripts/library.mk diff --git a/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v b/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v new file mode 100755 index 00000000..fd201f10 --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v @@ -0,0 +1,284 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2016-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_jesd204_tx #( + parameter ID = 0, + parameter NUM_LANES = 1, + parameter NUM_LINKS = 1, + parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B + parameter ENABLE_LINK_STATS = 0, + parameter DATA_PATH_WIDTH = LINK_MODE == 2 ? 8 : 4 +) ( + input s_axi_aclk, + input s_axi_aresetn, + + input s_axi_awvalid, + input [13:0] s_axi_awaddr, + output s_axi_awready, + input [2:0] s_axi_awprot, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [13:0] s_axi_araddr, + output s_axi_arready, + input [2:0] s_axi_arprot, + output s_axi_rvalid, + input s_axi_rready, + output [1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + + output irq, + + input core_clk, + input core_reset_ext, + output core_reset, + + input device_clk, + output device_reset, + + output [NUM_LANES-1:0] core_cfg_lanes_disable, + output [NUM_LINKS-1:0] core_cfg_links_disable, + output [9:0] core_cfg_octets_per_multiframe, + output [7:0] core_cfg_octets_per_frame, + output core_cfg_continuous_cgs, + output core_cfg_continuous_ilas, + output core_cfg_skip_ilas, + output [7:0] core_cfg_mframes_per_ilas, + output core_cfg_disable_char_replacement, + output core_cfg_disable_scrambler, + + output [9:0] device_cfg_octets_per_multiframe, + output [7:0] device_cfg_octets_per_frame, + output [7:0] device_cfg_beats_per_multiframe, + output [7:0] device_cfg_lmfc_offset, + output device_cfg_sysref_oneshot, + output device_cfg_sysref_disable, + + input core_ilas_config_rd, + input [1:0] core_ilas_config_addr, + output [DATA_PATH_WIDTH*8*NUM_LANES-1:0] core_ilas_config_data, + + input device_event_sysref_alignment_error, + input device_event_sysref_edge, + + output core_ctrl_manual_sync_request, + + input [1:0] core_status_state, + input [NUM_LINKS-1:0] core_status_sync, + + input [31:0] status_synth_params0, + input [31:0] status_synth_params1, + input [31:0] status_synth_params2 +); + + localparam PCORE_VERSION = 32'h00010661; // 1.06.a + localparam PCORE_MAGIC = 32'h32303454; // 204T + + wire up_reset; + + /* Register interface signals */ + reg [31:0] up_rdata = 'd0; + reg up_wack = 1'b0; + reg up_rack = 1'b0; + wire up_wreq; + wire up_rreq; + wire [31:0] up_wdata; + wire [11:0] up_waddr; + wire [11:0] up_raddr; + wire [31:0] up_rdata_common; + wire [31:0] up_rdata_sysref; + wire [31:0] up_rdata_tx; + + wire up_cfg_skip_ilas; + wire up_cfg_continuous_ilas; + wire up_cfg_continuous_cgs; + wire [7:0] up_cfg_mframes_per_ilas; + wire [7:0] up_cfg_lmfc_offset; + wire up_cfg_sysref_oneshot; + wire up_cfg_sysref_disable; + wire up_cfg_is_writeable; + + wire [4:0] up_irq_trigger; + + assign up_irq_trigger[4:0] = 5'b00000; + + up_axi #( + .AXI_ADDRESS_WIDTH (14) + ) i_up_axi ( + .up_rstn(~up_reset), + .up_clk(s_axi_aclk), + .up_axi_awvalid(s_axi_awvalid), + .up_axi_awaddr(s_axi_awaddr), + .up_axi_awready(s_axi_awready), + .up_axi_wvalid(s_axi_wvalid), + .up_axi_wdata(s_axi_wdata), + .up_axi_wstrb(s_axi_wstrb), + .up_axi_wready(s_axi_wready), + .up_axi_bvalid(s_axi_bvalid), + .up_axi_bresp(s_axi_bresp), + .up_axi_bready(s_axi_bready), + .up_axi_arvalid(s_axi_arvalid), + .up_axi_araddr(s_axi_araddr), + .up_axi_arready(s_axi_arready), + .up_axi_rvalid(s_axi_rvalid), + .up_axi_rresp(s_axi_rresp), + .up_axi_rdata(s_axi_rdata), + .up_axi_rready(s_axi_rready), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + .up_wack(up_wack), + .up_rreq(up_rreq), + .up_raddr(up_raddr), + .up_rdata(up_rdata), + .up_rack(up_rack)); + + jesd204_up_common #( + .PCORE_VERSION(PCORE_VERSION), + .PCORE_MAGIC(PCORE_MAGIC), + .ID(ID), + .NUM_LANES(NUM_LANES), + .NUM_LINKS(NUM_LINKS), + .NUM_IRQS(5), + .EXTRA_CFG_WIDTH(11), + .DEV_EXTRA_CFG_WIDTH(10), + .ENABLE_LINK_STATS(ENABLE_LINK_STATS) + ) i_up_common ( + .up_clk(s_axi_aclk), + .ext_resetn(s_axi_aresetn), + + .up_reset(up_reset), + + .up_reset_synchronizer(), + + .core_clk(core_clk), + .core_reset_ext(core_reset_ext), + .core_reset(core_reset), + + .device_clk(device_clk), + .device_reset(device_reset), + + .up_raddr(up_raddr), + .up_rdata(up_rdata_common), + + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + + .up_cfg_is_writeable(up_cfg_is_writeable), + + .up_irq_trigger(up_irq_trigger), + .irq(irq), + + .core_cfg_octets_per_multiframe(core_cfg_octets_per_multiframe), + .core_cfg_octets_per_frame(core_cfg_octets_per_frame), + .core_cfg_lanes_disable(core_cfg_lanes_disable), + .core_cfg_links_disable(core_cfg_links_disable), + .core_cfg_disable_scrambler(core_cfg_disable_scrambler), + .core_cfg_disable_char_replacement(core_cfg_disable_char_replacement), + + .up_extra_cfg({ + /* 10 */ up_cfg_continuous_cgs, + /* 09 */ up_cfg_continuous_ilas, + /* 08 */ up_cfg_skip_ilas, + /* 00-07 */ up_cfg_mframes_per_ilas + }), + .core_extra_cfg({ + /* 10 */ core_cfg_continuous_cgs, + /* 09 */ core_cfg_continuous_ilas, + /* 08 */ core_cfg_skip_ilas, + /* 00-07 */ core_cfg_mframes_per_ilas + }), + + .device_cfg_octets_per_multiframe(device_cfg_octets_per_multiframe), + .device_cfg_octets_per_frame(device_cfg_octets_per_frame), + .device_cfg_beats_per_multiframe(device_cfg_beats_per_multiframe), + + .up_dev_extra_cfg({ + /* 09 */ up_cfg_sysref_disable, + /* 08 */ up_cfg_sysref_oneshot, + /* 00-07 */ up_cfg_lmfc_offset + }), + .device_extra_cfg({ + /* 09 */ device_cfg_sysref_disable, + /* 08 */ device_cfg_sysref_oneshot, + /* 00-07 */ device_cfg_lmfc_offset + }), + + .status_synth_params0(status_synth_params0), + .status_synth_params1(status_synth_params1), + .status_synth_params2(status_synth_params2)); + + jesd204_up_sysref i_up_sysref ( + .up_clk(s_axi_aclk), + .up_reset(up_reset), + + .core_clk(core_clk), + .device_clk(device_clk), + .device_event_sysref_alignment_error(device_event_sysref_alignment_error), + .device_event_sysref_edge(device_event_sysref_edge), + + .up_cfg_lmfc_offset(up_cfg_lmfc_offset), + .up_cfg_sysref_oneshot(up_cfg_sysref_oneshot), + .up_cfg_sysref_disable(up_cfg_sysref_disable), + + .up_raddr(up_raddr), + .up_rdata(up_rdata_sysref), + + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + + .up_cfg_is_writeable(up_cfg_is_writeable)); + + jesd204_up_tx #( + .NUM_LANES(NUM_LANES), + .NUM_LINKS(NUM_LINKS), + .DATA_PATH_WIDTH(DATA_PATH_WIDTH) + ) i_up_tx ( + .up_clk(s_axi_aclk), + .up_reset(up_reset), + + .core_clk(core_clk), + .core_ilas_config_rd(core_ilas_config_rd), + .core_ilas_config_addr(core_ilas_config_addr), + .core_ilas_config_data(core_ilas_config_data), + + .core_ctrl_manual_sync_request(core_ctrl_manual_sync_request), + + .core_status_state(core_status_state), + .core_status_sync(core_status_sync), + + .up_raddr(up_raddr), + .up_rdata(up_rdata_tx), + .up_wreq(up_wreq), + .up_waddr(up_waddr), + .up_wdata(up_wdata), + + .up_cfg_is_writeable(up_cfg_is_writeable), + + .up_cfg_continuous_cgs(up_cfg_continuous_cgs), + .up_cfg_continuous_ilas(up_cfg_continuous_ilas), + .up_cfg_skip_ilas(up_cfg_skip_ilas), + .up_cfg_mframes_per_ilas(up_cfg_mframes_per_ilas)); + + always @(posedge s_axi_aclk) begin + up_wack <= up_wreq; + up_rack <= up_rreq; + if (up_rreq == 1'b1) begin + up_rdata <= up_rdata_common | up_rdata_sysref | up_rdata_tx; + end + end + +endmodule diff --git a/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx.xpr b/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx.xpr new file mode 100644 index 00000000..376f8fd7 --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx.xpr @@ -0,0 +1,421 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.sdc b/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.sdc new file mode 100644 index 00000000..3e51e1ee --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.sdc @@ -0,0 +1,52 @@ +############################################################################### +## Copyright (C) 2016-2018, 2021 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +set script_dir [file dirname [info script]] + +source "$script_dir/util_cdc_constr.tcl" + +util_cdc_sync_event_constr {*|jesd204_up_sysref:i_up_sysref|sync_event:i_cdc_sysref_event} +util_cdc_sync_event_constr {*|jesd204_up_tx:i_up_tx|sync_event:i_cdc_manual_sync_request} +util_cdc_sync_data_constr {*|jesd204_up_tx:i_up_tx|sync_data:i_cdc_status} +util_cdc_sync_bits_constr {*|jesd204_up_tx:i_up_tx|sync_bits:i_cdc_sync} + +set_false_path \ + -from [get_registers {*|jesd204_up_common:i_up_common|up_reset_core}] \ + -to [get_registers {*|jesd204_up_common:i_up_common|core_reset_vector[*]}] + +set_false_path \ + -from [get_registers {*|jesd204_up_common:i_up_common|up_reset_core}] \ + -to [get_registers {*|jesd204_up_common:i_up_common|device_reset_vector[*]}] + +set_false_path \ + -from [get_registers {*|jesd204_up_common:i_up_common|core_reset_vector[0]}] \ + -to [get_registers {*|jesd204_up_common:i_up_common|up_reset_synchronizer_vector[*]}] + +set_false_path \ + -to [get_pins -compatibility_mode {*|jesd204_up_common:i_up_common|up_core_reset_ext_synchronizer_vector[*]|clrn}] + +set_false_path \ + -from [get_registers {*|jesd204_up_common:i_up_common|up_cfg_*}] \ + -to [get_registers {*|jesd204_up_common:i_up_common|core_cfg_*}] + +set_false_path \ + -from [get_registers {*|jesd204_up_common:i_up_common|up_cfg_*}] \ + -to [get_registers {*|jesd204_up_common:i_up_common|device_cfg_*}] + +set_false_path \ + -from [get_registers {*|jesd204_up_tx:i_up_tx|up_cfg_ilas_data_*}] \ + -to [get_registers {*|jesd204_up_tx:i_up_tx|core_ilas_config_data[*]}] + +set_false_path \ + -from [get_registers {*|jesd204_up_tx:i_up_tx|up_cfg_*}] \ + -to [get_registers {*|jesd204_up_common:i_up_common|core_extra_cfg[*]}] + +set_false_path \ + -from [get_registers {*|jesd204_up_tx:i_up_tx|up_cfg_*}] \ + -to [get_registers {*|jesd204_up_common:i_up_common|device_extra_cfg[*]}] + +set_false_path \ + -from [get_registers {*|jesd204_up_sysref:i_up_sysref|up_cfg_*}] \ + -to [get_registers {*|jesd204_up_common:i_up_common|device_extra_cfg[*]}] diff --git a/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc b/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc new file mode 100644 index 00000000..9d51f20c --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc @@ -0,0 +1,102 @@ +############################################################################### +## Copyright (C) 2017, 2018, 2021 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +set axi_clk [get_clocks -of_objects [get_ports s_axi_aclk]] +set core_clk [get_clocks -of_objects [get_ports core_clk]] +set device_clk [get_clocks -of_objects [get_ports device_clk]] + +set_property ASYNC_REG TRUE \ + [get_cells -hier {*cdc_sync_stage1_reg*}] \ + [get_cells -hier {*cdc_sync_stage2_reg*}] + +# Used for synchronizing resets with asynchronous de-assert +set_property ASYNC_REG TRUE \ + [get_cells -hier {up_reset_vector_reg*}] \ + [get_cells -hier {core_reset_vector_reg*}] \ + [get_cells -hier {up_reset_synchronizer_vector_reg*}] \ + [get_cells -hier {up_core_reset_ext_synchronizer_vector_reg*}] + +set_false_path \ + -from [get_pins {i_up_tx/i_cdc_status/out_toggle_d1_reg/C}] \ + -to [get_pins {i_up_tx/i_cdc_status/i_sync_in/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -from [get_pins {i_up_tx/i_cdc_status/in_toggle_d1_reg/C}] \ + -to [get_pins {i_up_tx/i_cdc_status/i_sync_out/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -from [get_pins {i_up_sysref/i_cdc_sysref_event/in_toggle_d1_reg/C}] \ + -to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_out/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -from [get_pins {i_up_sysref/i_cdc_sysref_event/out_toggle_d1_reg/C}] \ + -to [get_pins {i_up_sysref/i_cdc_sysref_event/i_sync_in/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -from [get_pins {i_up_sysref/i_cdc_sysref_event/cdc_hold_reg*/C}] \ + -to [get_pins {i_up_sysref/i_cdc_sysref_event/out_event_reg*/D}] + +# Don't place them too far appart +set_max_delay -datapath_only \ + -from [get_pins {i_up_tx/i_cdc_status/cdc_hold_reg[*]/C}] \ + -to [get_pins {i_up_tx/i_cdc_status/out_data_reg[*]/D}] \ + [get_property -min PERIOD $axi_clk] + +set_false_path \ + -from $core_clk \ + -to [get_pins {i_up_tx/i_cdc_sync/cdc_sync_stage1_reg[*]/D}] + +set_false_path \ + -from [get_pins {i_up_common/up_reset_core_reg/C}] \ + -to [get_pins {i_up_common/core_reset_vector_reg[*]/PRE}] + +set_false_path \ + -from [get_pins {i_up_common/up_reset_core_reg/C}] \ + -to [get_pins {i_up_common/device_reset_vector_reg[*]/PRE}] + +set_false_path \ + -from [get_pins {i_up_common/core_reset_vector_reg[0]/C}] \ + -to [get_pins {i_up_common/up_reset_synchronizer_vector_reg[*]/PRE}] + +set_false_path \ + -to [get_pins {i_up_common/up_core_reset_ext_synchronizer_vector_reg[*]/PRE}] + +set_max_delay -datapath_only \ + -from [get_pins {i_up_common/up_cfg_*_reg*/C}] \ + -to [get_pins {i_up_common/core_cfg_*_reg*/D}] \ + [get_property -min PERIOD $core_clk] + +set_max_delay -datapath_only \ + -from [get_pins {i_up_common/up_cfg_*_reg*/C}] \ + -to [get_pins {i_up_common/device_cfg_*_reg*/D}] \ + [get_property -min PERIOD $device_clk] + +set_max_delay -datapath_only \ + -from [get_pins {i_up_tx/up_cfg_ilas_data_*_reg*/C}] \ + -to [get_cells {i_up_tx/*core_ilas_config_data_reg*}] \ + [get_property -min PERIOD $core_clk] + +set_max_delay -datapath_only \ + -from [get_pins {i_up_tx/up_cfg_*_reg*/C}] \ + -to [get_pins {i_up_common/core_extra_cfg_reg[*]/D}] \ + [get_property -min PERIOD $core_clk] + +set_max_delay -datapath_only \ + -from [get_pins {i_up_tx/up_cfg_*_reg*/C}] \ + -to [get_pins {i_up_common/device_extra_cfg_reg[*]/D}] \ + [get_property -min PERIOD $device_clk] + +set_max_delay -datapath_only \ + -from [get_pins {i_up_sysref/up_cfg_*_reg*/C}] \ + -to [get_pins {i_up_common/device_extra_cfg_reg[*]/D}] \ + [get_property -min PERIOD $device_clk] + +set_false_path \ + -from [get_pins {i_up_tx/i_cdc_manual_sync_request/out_toggle_d1_reg/C}] \ + -to [get_pins {i_up_tx/i_cdc_manual_sync_request/i_sync_in/cdc_sync_stage1_reg[0]/D}] + +set_false_path \ + -from [get_pins {i_up_tx/i_cdc_manual_sync_request/in_toggle_d1_reg/C}] \ + -to [get_pins {i_up_tx/i_cdc_manual_sync_request/i_sync_out/cdc_sync_stage1_reg[0]/D}] diff --git a/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl b/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl new file mode 100644 index 00000000..50ad24af --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl @@ -0,0 +1,157 @@ +############################################################################### +## Copyright (C) 2016-2019, 2021-2022 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +package require qsys 14.0 + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl + +ad_ip_create axi_jesd204_tx "ADI JESD204 Transmit AXI Interface" + +set_module_property INTERNAL true + +# files + +ad_ip_files axi_jesd204_tx [list \ + axi_jesd204_tx.v \ + axi_jesd204_tx_constr.sdc \ + jesd204_up_tx.v \ + ../axi_jesd204_common/jesd204_up_common.v \ + ../axi_jesd204_common/jesd204_up_sysref.v \ + $ad_hdl_dir/library/common/up_axi.v \ + $ad_hdl_dir/library/common/up_clock_mon.v \ + $ad_hdl_dir/library/util_cdc/sync_bits.v \ + $ad_hdl_dir/library/util_cdc/sync_data.v \ + $ad_hdl_dir/library/util_cdc/sync_event.v \ + $ad_hdl_dir/library/util_cdc/util_cdc_constr.tcl \ + $ad_hdl_dir/library/intel/common/up_clock_mon_constr.sdc \ +] + +# parameters + +add_parameter ID NATURAL 0 +set_parameter_property ID DISPLAY_NAME "Peripheral ID" +set_parameter_property ID HDL_PARAMETER true + +add_parameter NUM_LANES INTEGER 1 +set_parameter_property NUM_LANES DISPLAY_NAME "Number of Lanes" +set_parameter_property NUM_LANES ALLOWED_RANGES 1:32 +set_parameter_property NUM_LANES HDL_PARAMETER true + +add_parameter NUM_LINKS INTEGER 1 +set_parameter_property NUM_LINKS DISPLAY_NAME "Number of Links" +set_parameter_property NUM_LINKS ALLOWED_RANGES 1:8 +set_parameter_property NUM_LINKS HDL_PARAMETER true + +# axi4 slave interface + +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 14 + +# interrupt + +add_interface interrupt interrupt end +set_interface_property interrupt associatedClock s_axi_clock +set_interface_property interrupt associatedReset s_axi_reset +#set_interface_property interrupt associatedAddressablePoint s_axi +add_interface_port interrupt irq irq Output 1 + +# core clock + +add_interface core_clock clock end +add_interface_port core_clock core_clk clk Input 1 + +# device clock + +add_interface device_clock clock end +add_interface_port device_clock device_clk clk Input 1 + +# core reset ext + +add_interface core_reset_ext reset end +set_interface_property core_reset_ext associatedClock core_clock +add_interface_port core_reset_ext core_reset_ext reset Input 1 + +# core reset + +add_interface core_reset reset start +set_interface_property core_reset associatedClock core_clock +set_interface_property core_reset associatedResetSinks core_reset_ext +add_interface_port core_reset core_reset reset Output 1 + +# device reset + +add_interface device_reset reset start +set_interface_property device_reset associatedClock device_clock +set_interface_property device_reset associatedResetSinks core_reset_ext +add_interface_port device_reset device_reset reset Output 1 + +# config interface +# +add_interface config conduit end +set_interface_property config associatedClock core_clock +set_interface_property config associatedReset core_reset + +add_interface_port config core_cfg_octets_per_multiframe octets_per_multiframe Output 10 +add_interface_port config core_cfg_continuous_cgs continuous_cgs Output 1 +add_interface_port config core_cfg_continuous_ilas continuous_ilas Output 1 +add_interface_port config core_cfg_disable_char_replacement disable_char_replacement Output 1 +add_interface_port config core_cfg_disable_scrambler disable_scrambler Output 1 +add_interface_port config core_cfg_lanes_disable lanes_disable Output NUM_LANES +add_interface_port config core_cfg_links_disable links_disable Output NUM_LINKS +add_interface_port config core_cfg_mframes_per_ilas mframes_per_ilas Output 8 +add_interface_port config core_cfg_octets_per_frame octets_per_frame Output 8 +add_interface_port config core_cfg_skip_ilas skip_ilas Output 1 + +# device clock domain config interface + +add_interface device_config conduit end +set_interface_property device_config associatedClock device_clock +set_interface_property device_config associatedReset device_reset + +add_interface_port device_config device_cfg_octets_per_multiframe octets_per_multiframe Output 10 +add_interface_port device_config device_cfg_octets_per_frame octets_per_frame Output 8 +add_interface_port device_config device_cfg_beats_per_multiframe beats_per_multiframe Output 8 +add_interface_port device_config device_cfg_lmfc_offset lmfc_offset Output 8 +add_interface_port device_config device_cfg_sysref_disable sysref_disable Output 1 +add_interface_port device_config device_cfg_sysref_oneshot sysref_oneshot Output 1 + +# control interface + +add_interface control conduit end +set_interface_property control associatedClock core_clock +set_interface_property control associatedReset core_reset + +add_interface_port control core_ctrl_manual_sync_request manual_sync_request Output 1 + +# ilas config interface + +add_interface ilas_config conduit end +set_interface_property ilas_config associatedClock core_clock +set_interface_property ilas_config associatedReset core_reset + +add_interface_port ilas_config core_ilas_config_addr addr Input 2 +add_interface_port ilas_config core_ilas_config_data data Output 32*NUM_LANES +add_interface_port ilas_config core_ilas_config_rd rd Input 1 + +# event interface + +add_interface device_event conduit end +set_interface_property device_event associatedClock device_clock +set_interface_property device_event associatedReset device_reset + +add_interface_port device_event device_event_sysref_alignment_error sysref_alignment_error Input 1 +add_interface_port device_event device_event_sysref_edge sysref_edge Input 1 + +# status interface + +add_interface status conduit end +set_interface_property status associatedClock core_clock +set_interface_property status associatedReset core_reset + +add_interface_port status core_status_state state Input 2 +add_interface_port status core_status_sync sync Input 1 +add_interface_port status status_synth_params0 synth_params0 Input 32 +add_interface_port status status_synth_params1 synth_params1 Input 32 +add_interface_port status status_synth_params2 synth_params2 Input 32 diff --git a/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl b/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl new file mode 100644 index 00000000..0675d48d --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl @@ -0,0 +1,127 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create axi_jesd204_tx +adi_ip_files axi_jesd204_tx [list \ + "../../common/up_axi.v" \ + "axi_jesd204_tx_constr.xdc" \ + "axi_jesd204_tx_ooc.ttcl" \ + "jesd204_up_tx.v" \ + "axi_jesd204_tx.v" \ +] + +set_property source_mgmt_mode DisplayOnly [current_project] + +adi_ip_properties axi_jesd204_tx + +adi_ip_ttcl axi_jesd204_tx "axi_jesd204_tx_ooc.ttcl" + +set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_tx} [ipx::current_core] + +set_property PROCESSING_ORDER LATE [ipx::get_files axi_jesd204_tx_constr.xdc \ + -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \ + -filter {NAME =~ *synthesis*}]] + +adi_ip_add_core_dependencies [list \ + analog.com:$VIVADO_IP_LIBRARY:axi_jesd204_common:1.0 \ +] + +set_property display_name "ADI JESD204C Transmit AXI Interface" [ipx::current_core] +set_property description "ADI JESD204B Transmit AXI Interface" [ipx::current_core] + +adi_add_bus "tx_cfg" "master" \ + "analog.com:interface:jesd204_tx_cfg_rtl:1.0" \ + "analog.com:interface:jesd204_tx_cfg:1.0" \ + { \ + { "core_cfg_lanes_disable" "lanes_disable" } \ + { "core_cfg_links_disable" "links_disable" } \ + { "core_cfg_octets_per_multiframe" "octets_per_multiframe" } \ + { "core_cfg_octets_per_frame" "octets_per_frame" } \ + { "core_cfg_continuous_cgs" "continuous_cgs" } \ + { "core_cfg_continuous_ilas" "continuous_ilas" } \ + { "core_cfg_skip_ilas" "skip_ilas" } \ + { "core_cfg_mframes_per_ilas" "mframes_per_ilas" } \ + { "core_cfg_disable_char_replacement" "disable_char_replacement" } \ + { "core_cfg_disable_scrambler" "disable_scrambler" } \ + { "device_cfg_octets_per_multiframe" "device_octets_per_multiframe" } \ + { "device_cfg_octets_per_frame" "device_octets_per_frame" } \ + { "device_cfg_beats_per_multiframe" "device_beats_per_multiframe" } \ + { "device_cfg_lmfc_offset" "device_lmfc_offset" } \ + { "device_cfg_sysref_oneshot" "device_sysref_oneshot" } \ + { "device_cfg_sysref_disable" "device_sysref_disable" } \ + } + +adi_add_bus "tx_ilas_config" "slave" \ + "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" \ + "analog.com:interface:jesd204_tx_ilas_config:1.0" \ + { \ + { "core_ilas_config_rd" "rd" } \ + { "core_ilas_config_addr" "addr" } \ + { "core_ilas_config_data" "data" } \ + } + +adi_add_bus "tx_event" "slave" \ + "analog.com:interface:jesd204_tx_event_rtl:1.0" \ + "analog.com:interface:jesd204_tx_event:1.0" \ + { \ + { "device_event_sysref_alignment_error" "sysref_alignment_error" } \ + { "device_event_sysref_edge" "sysref_edge" } \ + } + +adi_add_bus "tx_status" "slave" \ + "analog.com:interface:jesd204_tx_status_rtl:1.0" \ + "analog.com:interface:jesd204_tx_status:1.0" \ + { \ + { "core_status_state" "state" } \ + { "core_status_sync" "sync" } \ + { "status_synth_params0" "synth_params0" } \ + { "status_synth_params1" "synth_params1" } \ + { "status_synth_params2" "synth_params2" } \ + } + +adi_add_bus "tx_ctrl" "master" \ + "analog.com:interface:jesd204_tx_ctrl_rtl:1.0" \ + "analog.com:interface:jesd204_tx_ctrl:1.0" \ + { \ + { "core_ctrl_manual_sync_request" "manual_sync_request" } \ + } + +ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core] + +adi_add_bus_clock "core_clk" "tx_status:tx_event:tx_ilas_config:tx_cfg:tx_ctrl" \ + "core_reset" "master" + +set_property DRIVER_VALUE "0" [ipx::get_ports "core_reset_ext"] + +adi_set_bus_dependency "tx_ilas_config" "tx_ilas_config" \ + "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" + +adi_set_bus_dependency "tx_ctrl" "tx_ctrl" \ + "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" + +set cc [ipx::current_core] +set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] + +# Link layer mode +set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $page0 +set_property -dict [list \ + "display_name" "Link Layer mode" \ + "tooltip" "Link Layer mode" \ + "widget" "comboBox" \ +] $p + +set_property -dict [list \ + value_validation_type pairs \ + value_validation_pairs {64B66B 2 8B10B 1} \ +] [ipx::get_user_parameters $p -of_objects $cc] + +ipx::create_xgui_files [ipx::current_core] +ipx::save_core [ipx::current_core] diff --git a/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ooc.ttcl b/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ooc.ttcl new file mode 100644 index 00000000..a6e0680f --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ooc.ttcl @@ -0,0 +1,23 @@ +############################################################################### +## Copyright (C) 2017-2019, 2021 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +<: setFileUsedIn { out_of_context synthesis implementation } :> +<: ;#Component and file information :> +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName $ComponentName :> +<: setFileExtension "_ooc.xdc" :> + +# This XDC is used only for OOC mode of synthesis, implementation. +# These are default values for timing driven synthesis during OOC flow. +# These values will be overwritten during implementation with information +# from top level. + +create_clock -name s_axi_aclk -period 10 [get_ports s_axi_aclk] +create_clock -name core_clk -period 2.5 [get_ports core_clk] +create_clock -name device_clk -period 2.5 [get_ports device_clk] + +################################################################################ + diff --git a/adi_library/jesd204/axi_jesd204_tx/component.xml b/adi_library/jesd204/axi_jesd204_tx/component.xml new file mode 100644 index 00000000..95ea2b0d --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_tx/component.xml @@ -0,0 +1,1668 @@ + + + analog.com + user + axi_jesd204_tx + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + tx_cfg + + + + + + + lanes_disable + + + core_cfg_lanes_disable + + + + + links_disable + + + core_cfg_links_disable + + + + + octets_per_multiframe + + + core_cfg_octets_per_multiframe + + + + + octets_per_frame + + + core_cfg_octets_per_frame + + + + + continuous_cgs + + + core_cfg_continuous_cgs + + + + + continuous_ilas + + + core_cfg_continuous_ilas + + + + + skip_ilas + + + core_cfg_skip_ilas + + + + + mframes_per_ilas + + + core_cfg_mframes_per_ilas + + + + + disable_char_replacement + + + core_cfg_disable_char_replacement + + + + + disable_scrambler + + + core_cfg_disable_scrambler + + + + + device_octets_per_multiframe + + + device_cfg_octets_per_multiframe + + + + + device_octets_per_frame + + + device_cfg_octets_per_frame + + + + + device_beats_per_multiframe + + + device_cfg_beats_per_multiframe + + + + + device_lmfc_offset + + + device_cfg_lmfc_offset + + + + + device_sysref_oneshot + + + device_cfg_sysref_oneshot + + + + + device_sysref_disable + + + device_cfg_sysref_disable + + + + + + tx_ilas_config + + + + + + + rd + + + core_ilas_config_rd + + + + + addr + + + core_ilas_config_addr + + + + + data + + + core_ilas_config_data + + + + + + + true + + + + + + tx_event + + + + + + + sysref_alignment_error + + + device_event_sysref_alignment_error + + + + + sysref_edge + + + device_event_sysref_edge + + + + + + tx_status + + + + + + + state + + + core_status_state + + + + + sync + + + core_status_sync + + + + + synth_params0 + + + status_synth_params0 + + + + + synth_params1 + + + status_synth_params1 + + + + + synth_params2 + + + status_synth_params2 + + + + + + tx_ctrl + + + + + + + manual_sync_request + + + core_ctrl_manual_sync_request + + + + + + + true + + + + + + irq + + + + + + + INTERRUPT + + + irq + + + + + + SENSITIVITY + LEVEL_HIGH + + + + + tx_status_tx_event_tx_ilas_config_tx_cfg_tx_ctrl_signal_clock + tx_status_tx_event_tx_ilas_config_tx_cfg_tx_ctrl_signal_clock + + + + + + + CLK + + + core_clk + + + + + + ASSOCIATED_BUSIF + tx_status:tx_event:tx_ilas_config:tx_cfg:tx_ctrl + + + ASSOCIATED_RESET + core_reset + + + + + tx_status_tx_event_tx_ilas_config_tx_cfg_tx_ctrl_signal_reset + tx_status_tx_event_tx_ilas_config_tx_cfg_tx_ctrl_signal_reset + + + + + + + RST + + + core_reset + + + + + + POLARITY + ACTIVE_HIGH + + + + + + + s_axi + + axi_lite + 0 + 16384 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_jesd204_tx + + xilinx_anylanguagesynthesis_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + dc0625d2 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_jesd204_tx + + xilinx_anylanguagebehavioralsimulation_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + eecd3758 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset + + + xilinx_xpgui_view_fileset + + + + viewChecksum + 3df09e24 + + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 13 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 1 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 13 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + irq + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_reset_ext + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + core_reset + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_reset + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_cfg_lanes_disable + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_cfg_links_disable + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_cfg_octets_per_multiframe + + out + + 9 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_cfg_octets_per_frame + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_cfg_continuous_cgs + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_cfg_continuous_ilas + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_cfg_skip_ilas + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_cfg_mframes_per_ilas + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_cfg_disable_char_replacement + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_cfg_disable_scrambler + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_octets_per_multiframe + + out + + 9 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_octets_per_frame + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_beats_per_multiframe + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_lmfc_offset + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_sysref_oneshot + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_sysref_disable + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_ilas_config_rd + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_ilas_config_addr + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_ilas_config_data + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_event_sysref_alignment_error + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_event_sysref_edge + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_ctrl_manual_sync_request + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_status_state + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + core_status_sync + + in + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + status_synth_params0 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + status_synth_params1 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + status_synth_params2 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + ID + Id + 0 + + + NUM_LANES + Num Lanes + 1 + + + NUM_LINKS + Num Links + 1 + + + LINK_MODE + Link Mode + 1 + + + ENABLE_LINK_STATS + Enable Link Stats + 0 + + + DATA_PATH_WIDTH + Data Path Width + 4 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_list_9ca20931 + LEVEL_HIGH + LEVEL_LOW + EDGE_RISING + EDGE_FALLING + + + choice_pairs_1942b210 + 2 + 1 + + + + + xilinx_anylanguagesynthesis_view_fileset + + axi_jesd204_tx_ooc.ttcl + ttcl + + + axi_jesd204_tx_constr.xdc + xdc + + processing_order + late + + + + ../../common/up_axi.v + verilogSource + + + jesd204_up_tx.v + verilogSource + + + axi_jesd204_tx.v + verilogSource + CHECKSUM_949a9562 + + + + xilinx_anylanguagesynthesis_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../common/up_axi.v + verilogSource + + + jesd204_up_tx.v + verilogSource + + + axi_jesd204_tx.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axi_jesd204_tx_v1_0.tcl + tclSource + CHECKSUM_397049c5 + XGUI_VERSION_2 + + + + xilinx_xpgui_analog_com_user_axi_jesd204_common_1_0__ref_view_fileset + + + + + + + + ADI JESD204B Transmit AXI Interface + + + ID + Id + 0 + + + NUM_LANES + Num Lanes + 1 + + + NUM_LINKS + Num Links + 1 + + + LINK_MODE + Link Layer mode + 1 + + + ENABLE_LINK_STATS + Enable Link Stats + 0 + + + DATA_PATH_WIDTH + Data Path Width + 4 + + + Component_Name + axi_jesd204_tx_v1_0 + + + + + + virtex7 + + + /Analog_Devices + + ADI JESD204C Transmit AXI Interface + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/peripherals/jesd204/axi_jesd204_tx + 1 + 2024-01-14T03:51:15Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/jesd204/axi_jesd204_tx/jesd204_up_tx.v b/adi_library/jesd204/axi_jesd204_tx/jesd204_up_tx.v new file mode 100755 index 00000000..699db519 --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_tx/jesd204_up_tx.v @@ -0,0 +1,278 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_up_tx #( + parameter NUM_LANES = 1, + parameter NUM_LINKS = 1, + parameter DATA_PATH_WIDTH = 4 +) ( + input up_clk, + input up_reset, + + input [11:0] up_raddr, + output reg [31:0] up_rdata, + input up_wreq, + input [11:0] up_waddr, + input [31:0] up_wdata, + + input up_cfg_is_writeable, + + output reg up_cfg_skip_ilas, + output reg up_cfg_continuous_ilas, + output reg up_cfg_continuous_cgs, + output reg [7:0] up_cfg_mframes_per_ilas, + + input core_clk, + input core_ilas_config_rd, + input [1:0] core_ilas_config_addr, + output reg [DATA_PATH_WIDTH*8*NUM_LANES-1:0] core_ilas_config_data, + + output core_ctrl_manual_sync_request, + + input [1:0] core_status_state, + input [NUM_LINKS-1:0] core_status_sync +); + + reg [31:0] up_cfg_ilas_data[0:NUM_LANES-1][0:3]; + reg up_ctrl_manual_sync_request = 1'b0; + + wire [1:0] up_status_state; + wire [NUM_LINKS-1:0] up_status_sync; + + sync_bits #( + .NUM_OF_BITS (NUM_LINKS) + ) i_cdc_sync ( + .in_bits(core_status_sync), + .out_clk(up_clk), + .out_resetn(1'b1), + .out_bits(up_status_sync)); + + sync_data #( + .NUM_OF_BITS(2) + ) i_cdc_status ( + .in_clk(core_clk), + .in_data(core_status_state), + .out_clk(up_clk), + .out_data(up_status_state)); + + sync_event #( + .NUM_OF_EVENTS(1), + .ASYNC_CLK(1) + ) i_cdc_manual_sync_request ( + .in_clk(up_clk), + .in_event(up_ctrl_manual_sync_request), + .out_clk(core_clk), + .out_event(core_ctrl_manual_sync_request)); + + integer i; + + always @(*) begin + case (up_raddr) + /* JESD TX configuration */ + 12'h090: up_rdata = { + /* 03-31 */ 29'h00, /* Reserved for future additions */ + /* 02 */ up_cfg_skip_ilas, /* Don't send ILAS, go directly from CGS to DATA */ + /* 01 */ up_cfg_continuous_ilas, /* Continuously send ILAS sequence */ + /* 00 */ up_cfg_continuous_cgs /* Continuously send CGS characters */ + }; + 12'h091: up_rdata = { + /* 08-31 */ 24'h00, /* Reserved for future additions */ + /* 00-07 */ up_cfg_mframes_per_ilas /* Number of multiframes send during the ILAS */ + }; + + /* JESD TX status */ + 12'ha0: up_rdata = { + /* 12-31 */ 20'h00, /* Reserved for future additions */ + /* 04-11 */ up_status_sync, /* Raw value of the SYNC pin */ + /* 02-03 */ 2'b0, /* Reserved fo future extension of the status_state field */ + /* 00-01 */ up_status_state /* State of the internal state machine (0=CGS, 1=ILAS, 2=DATA) */ + }; + default: begin + if (up_raddr[10:3] >= ('h300/32) && + up_raddr[10:3] < (('h300/32) + NUM_LANES) && + up_raddr[2] == 1'b1) begin + up_rdata = up_cfg_ilas_data[up_raddr[5:3]][up_raddr[1:0]]; + end else begin + up_rdata = 32'h00000000; + end + end + endcase + + end + + always @(posedge up_clk) begin + if (up_reset == 1'b1) begin + up_cfg_skip_ilas <= 1'b0; + up_cfg_continuous_ilas <= 1'b0; + up_cfg_continuous_cgs <= 1'b0; + up_cfg_mframes_per_ilas <= 'h3; + end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin + case (up_waddr) + /* JESD TX configuraton */ + 12'h090: begin + up_cfg_skip_ilas <= up_wdata[2]; + up_cfg_continuous_ilas <= up_wdata[1]; + up_cfg_continuous_cgs <= up_wdata[0]; + end + 12'h091: begin + // We'll enable this if we ever have a usecase + // cfg_mframes_per_ilas <= up_wdata[7:0]; + end + endcase + end + end + + always @(posedge up_clk) begin + if (up_reset == 1'b1) begin + up_ctrl_manual_sync_request <= 1'b0; + end else if (up_wreq == 1'b1 && up_waddr == 12'h092) begin + up_ctrl_manual_sync_request <= up_wdata[0]; + end else begin + up_ctrl_manual_sync_request <= 1'b0; + end + end + + /* Shared ILAS data can be access through any lane register map window */ + + /* Shared ILAS data */ + reg [7:0] up_cfg_ilas_data_did = 'h00; + reg [3:0] up_cfg_ilas_data_bid = 'h00; + reg [4:0] up_cfg_ilas_data_l = 'h00; + reg up_cfg_ilas_data_scr = 'h00; + reg [7:0] up_cfg_ilas_data_f = 'h00; + reg [4:0] up_cfg_ilas_data_k = 'h00; + reg [7:0] up_cfg_ilas_data_m = 'h00; + reg [4:0] up_cfg_ilas_data_n = 'h00; + reg [1:0] up_cfg_ilas_data_cs = 'h00; + reg [4:0] up_cfg_ilas_data_np = 'h00; + reg [2:0] up_cfg_ilas_data_subclassv = 'h00; + reg [4:0] up_cfg_ilas_data_s = 'h00; + reg [2:0] up_cfg_ilas_data_jesdv = 'h00; + reg [4:0] up_cfg_ilas_data_cf = 'h00; + reg up_cfg_ilas_data_hd = 'h00; + + /* Per lane ILAS data */ + reg [4:0] up_cfg_ilas_data_lid[0:NUM_LANES-1]; + reg [7:0] up_cfg_ilas_data_fchk[0:NUM_LANES-1]; + + always @(*) begin + for (i = 0; i < NUM_LANES; i = i + 1) begin + up_cfg_ilas_data[i][0] = { + 4'b0000, + up_cfg_ilas_data_bid, + up_cfg_ilas_data_did, + 16'h00 + }; + up_cfg_ilas_data[i][1] = { + 3'b000, + up_cfg_ilas_data_k, + up_cfg_ilas_data_f, + up_cfg_ilas_data_scr, + 2'b00, + up_cfg_ilas_data_l, + 3'b000, + up_cfg_ilas_data_lid[i] + }; + up_cfg_ilas_data[i][2] = { + up_cfg_ilas_data_jesdv, + up_cfg_ilas_data_s, + up_cfg_ilas_data_subclassv, + up_cfg_ilas_data_np, + up_cfg_ilas_data_cs, + 1'b0, + up_cfg_ilas_data_n, + up_cfg_ilas_data_m + }; + up_cfg_ilas_data[i][3] = { + up_cfg_ilas_data_fchk[i], + 16'h0000, + up_cfg_ilas_data_hd, + 2'b00, + up_cfg_ilas_data_cf + }; + end + end + + always @(posedge up_clk) begin + if (up_reset == 1'b1) begin + up_cfg_ilas_data_did <= 'h00; + up_cfg_ilas_data_bid <= 'h00; + up_cfg_ilas_data_scr <= 'h00; + up_cfg_ilas_data_f <= 'h00; + up_cfg_ilas_data_k <= 'h00; + up_cfg_ilas_data_m <= 'h00; + up_cfg_ilas_data_n <= 'h00; + up_cfg_ilas_data_cs <= 'h00; + up_cfg_ilas_data_np <= 'h00; + up_cfg_ilas_data_subclassv <= 'h00; + up_cfg_ilas_data_s <= 'h00; + up_cfg_ilas_data_jesdv <= 'h00; + up_cfg_ilas_data_cf <= 'h00; + up_cfg_ilas_data_hd <= 'h00; + up_cfg_ilas_data_l <= 'h00; + for (i = 0; i < NUM_LANES; i = i + 1) begin + up_cfg_ilas_data_lid[i] <= 'h00; + up_cfg_ilas_data_fchk[i] <= 'h00; + end + end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin + for (i = 0; i < NUM_LANES; i = i + 1) begin + if (up_waddr[10:2] == ('h310 / 16) + i*2) begin + case (up_waddr[1:0]) + 2'h0: begin + up_cfg_ilas_data_bid <= up_wdata[27:24]; + up_cfg_ilas_data_did <= up_wdata[23:16]; + end + 2'h1: begin + up_cfg_ilas_data_k <= up_wdata[28:24]; + up_cfg_ilas_data_f <= up_wdata[23:16]; + up_cfg_ilas_data_scr <= up_wdata[15]; + up_cfg_ilas_data_l <= up_wdata[12:8]; + up_cfg_ilas_data_lid[i] <= up_wdata[4:0]; + end + 2'h2: begin + up_cfg_ilas_data_jesdv <= up_wdata[31:29]; + up_cfg_ilas_data_s <= up_wdata[28:24]; + up_cfg_ilas_data_subclassv <= up_wdata[23:21]; + up_cfg_ilas_data_np <= up_wdata[20:16]; + up_cfg_ilas_data_cs <= up_wdata[15:14]; + up_cfg_ilas_data_n <= up_wdata[12:8]; + up_cfg_ilas_data_m <= up_wdata[7:0]; + end + 2'h3: begin + up_cfg_ilas_data_fchk[i] <= up_wdata[31:24]; + up_cfg_ilas_data_hd <= up_wdata[7]; + up_cfg_ilas_data_cf <= up_wdata[4:0]; + end + endcase + end + end + end + end + + generate + if(DATA_PATH_WIDTH == 4) begin : gen_dp_4 + always @(posedge core_clk) begin + if (core_ilas_config_rd == 1'b1) begin + for (i = 0; i < NUM_LANES; i = i + 1) begin + core_ilas_config_data[i*32+:32] <= up_cfg_ilas_data[i][core_ilas_config_addr]; + end + end + end + end else if(DATA_PATH_WIDTH == 8) begin : gen_dp_8 + always @(posedge core_clk) begin + if (core_ilas_config_rd == 1'b1) begin + for (i = 0; i < NUM_LANES; i = i + 1) begin + core_ilas_config_data[i*64+:64] <= {up_cfg_ilas_data[i][{core_ilas_config_addr[0], 1'b1}],up_cfg_ilas_data[i][{core_ilas_config_addr[0], 1'b0}]}; + end + end + end + end + endgenerate + +endmodule diff --git a/adi_library/jesd204/axi_jesd204_tx/xgui/axi_jesd204_tx_v1_0.tcl b/adi_library/jesd204/axi_jesd204_tx/xgui/axi_jesd204_tx_v1_0.tcl new file mode 100644 index 00000000..6ebad412 --- /dev/null +++ b/adi_library/jesd204/axi_jesd204_tx/xgui/axi_jesd204_tx_v1_0.tcl @@ -0,0 +1,100 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "LINK_MODE" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "DATA_PATH_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "ENABLE_LINK_STATS" -parent ${Page_0} + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_LANES" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_LINKS" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH } { + # Procedure called to update DATA_PATH_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH } { + # Procedure called to validate DATA_PATH_WIDTH + return true +} + +proc update_PARAM_VALUE.ENABLE_LINK_STATS { PARAM_VALUE.ENABLE_LINK_STATS } { + # Procedure called to update ENABLE_LINK_STATS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ENABLE_LINK_STATS { PARAM_VALUE.ENABLE_LINK_STATS } { + # Procedure called to validate ENABLE_LINK_STATS + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } { + # Procedure called to update LINK_MODE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } { + # Procedure called to validate LINK_MODE + return true +} + +proc update_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } { + # Procedure called to update NUM_LANES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } { + # Procedure called to validate NUM_LANES + return true +} + +proc update_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } { + # Procedure called to update NUM_LINKS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } { + # Procedure called to validate NUM_LINKS + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.NUM_LANES { MODELPARAM_VALUE.NUM_LANES PARAM_VALUE.NUM_LANES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_LANES}] ${MODELPARAM_VALUE.NUM_LANES} +} + +proc update_MODELPARAM_VALUE.NUM_LINKS { MODELPARAM_VALUE.NUM_LINKS PARAM_VALUE.NUM_LINKS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_LINKS}] ${MODELPARAM_VALUE.NUM_LINKS} +} + +proc update_MODELPARAM_VALUE.LINK_MODE { MODELPARAM_VALUE.LINK_MODE PARAM_VALUE.LINK_MODE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LINK_MODE}] ${MODELPARAM_VALUE.LINK_MODE} +} + +proc update_MODELPARAM_VALUE.ENABLE_LINK_STATS { MODELPARAM_VALUE.ENABLE_LINK_STATS PARAM_VALUE.ENABLE_LINK_STATS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ENABLE_LINK_STATS}] ${MODELPARAM_VALUE.ENABLE_LINK_STATS} +} + +proc update_MODELPARAM_VALUE.DATA_PATH_WIDTH { MODELPARAM_VALUE.DATA_PATH_WIDTH PARAM_VALUE.DATA_PATH_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_PATH_WIDTH}] ${MODELPARAM_VALUE.DATA_PATH_WIDTH} +} + diff --git a/adi_library/jesd204/docs/JIF_logo.png b/adi_library/jesd204/docs/JIF_logo.png new file mode 100644 index 0000000000000000000000000000000000000000..ccd7baa7c8f1886ba2ff8bb78de73d76981ee377 GIT binary patch literal 86389 zcmYiN1zgkL`#z43kPeY<1qG3AkXEEiK)OfC=o+08k^(9@P(e^>kRC8<6Dg6d5hFx$ zbn}1m`u=_YKF`PF47NS?*m>@p`@XOHx~}tDPe+xUgoy+M0+Fk$DeHqkL{Jb2N0f*F zc%@o76bJZ&@AE|6kO;U!i0tEm=fs|BramB$0LRV1`L;Bd4!p?d`^?1Gz{AlOYU}L) zfe0~9SbVul5*3l~^OK*FqN0Qn9lfGGPfeX3@R8rX zg>UP9bw!R(FTF-$B=~!0Wqh2{cg_!UjB}Ue*QC|CGJ0oyhJ@q)yVNRe%K7o8_Znl? z-5*r0fOam_R!8~2D?@48kZtyp)pBt_)4mo^mMv$duE1={R;j4<;e8YE1Cp!<06Kjk_9eeTQg-#k>m91 zx67$l1zbe9j&EZmb$m3> zP!Y_E8q%6bJ8H|!tx&>8K3Ai&v$J;;H6p)MR?dG59m^3sPd0F`HE>PAza)!) zXH7;VgIqAW5kFv#;fh?gW#HGx>*rL-YPP;FW`#Y_vc=lD?=vsy_)HM+z@Uy;Op1_R`Eb&!^%su+fEX%@Jau(`ym4C5_Ls_L^8=j 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b/adi_library/jesd204/interfaces/Makefile @@ -0,0 +1,52 @@ +#################################################################################### +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### +#################################################################################### + +M_DEPS := interfaces_ip.tcl +M_DEPS += ../../../scripts/adi_env.tcl +M_DEPS += ../../scripts/adi_ip_xilinx.tcl + +M_VIVADO := vivado -mode batch -source + +XML_FLIST := jesd204_tx_cfg.xml +XML_FLIST += jesd204_tx_cfg_rtl.xml +XML_FLIST += jesd204_tx_ilas_config.xml +XML_FLIST += jesd204_tx_ilas_config_rtl.xml +XML_FLIST += jesd204_tx_status.xml +XML_FLIST += jesd204_tx_status_rtl.xml +XML_FLIST += jesd204_tx_event.xml +XML_FLIST += jesd204_tx_event_rtl.xml +XML_FLIST += jesd204_tx_ctrl.xml +XML_FLIST += jesd204_tx_ctrl_rtl.xml +XML_FLIST += jesd204_rx_cfg.xml +XML_FLIST += jesd204_rx_cfg_rtl.xml +XML_FLIST += jesd204_rx_status.xml +XML_FLIST += jesd204_rx_status_rtl.xml +XML_FLIST += jesd204_rx_ilas_config.xml +XML_FLIST += jesd204_rx_ilas_config_rtl.xml +XML_FLIST += jesd204_rx_event.xml +XML_FLIST += jesd204_rx_event_rtl.xml + +M_FLIST := *.log +M_FLIST += *.jou +M_FLIST += $(XML_FLIST) + +.PHONY: all xilinx clean clean-all +all: xilinx + +xilinx: $(XML_FLIST) + +clean:clean-all + +clean-all: + rm -rf $(M_FLIST) + +%.xml: $(M_DEPS) + $(M_VIVADO) interfaces_ip.tcl >> interfaces_ip.log 2>&1 + +#################################################################################### +#################################################################################### diff --git a/adi_library/jesd204/interfaces/interfaces_ip.tcl b/adi_library/jesd204/interfaces/interfaces_ip.tcl new file mode 100755 index 00000000..c8300beb --- /dev/null +++ b/adi_library/jesd204/interfaces/interfaces_ip.tcl @@ -0,0 +1,91 @@ +############################################################################### +## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +# TX interfaces + +adi_if_define "jesd204_tx_cfg" +adi_if_ports output -1 lanes_disable +adi_if_ports output -1 links_disable +adi_if_ports output 10 octets_per_multiframe +adi_if_ports output 8 octets_per_frame +adi_if_ports output 1 continuous_cgs +adi_if_ports output 1 continuous_ilas +adi_if_ports output 1 skip_ilas +adi_if_ports output 8 mframes_per_ilas +adi_if_ports output 1 disable_char_replacement +adi_if_ports output 1 disable_scrambler +adi_if_ports output 10 device_octets_per_multiframe +adi_if_ports output 8 device_octets_per_frame +adi_if_ports output 8 device_beats_per_multiframe +adi_if_ports output 8 device_lmfc_offset +adi_if_ports output 1 device_sysref_oneshot +adi_if_ports output 1 device_sysref_disable + +adi_if_define "jesd204_tx_ilas_config" +adi_if_ports output 1 rd +adi_if_ports output 2 addr +adi_if_ports input 32 data + +adi_if_define "jesd204_tx_status" +adi_if_ports output 1 state +adi_if_ports output 1 sync +adi_if_ports output -1 synth_params0 +adi_if_ports output -1 synth_params1 +adi_if_ports output -1 synth_params2 + +adi_if_define "jesd204_tx_event" +adi_if_ports output 1 sysref_alignment_error +adi_if_ports output 1 sysref_edge + +adi_if_define "jesd204_tx_ctrl" +adi_if_ports output 1 manual_sync_request + +# RX interfaces + +adi_if_define "jesd204_rx_cfg" +adi_if_ports output -1 lanes_disable +adi_if_ports output -1 links_disable +adi_if_ports output 10 octets_per_multiframe +adi_if_ports output 8 octets_per_frame +adi_if_ports output 1 disable_char_replacement +adi_if_ports output 1 disable_scrambler +adi_if_ports output 8 frame_align_err_threshold +adi_if_ports output 10 device_octets_per_multiframe +adi_if_ports output 8 device_octets_per_frame +adi_if_ports output 8 device_beats_per_multiframe +adi_if_ports output 8 device_lmfc_offset +adi_if_ports output 1 device_sysref_oneshot +adi_if_ports output 1 device_sysref_disable +adi_if_ports output 1 device_buffer_early_release +adi_if_ports output 1 device_buffer_delay +adi_if_ports output 1 err_statistics_reset +adi_if_ports output 7 err_statistics_mask + +adi_if_define "jesd204_rx_status" +adi_if_ports output 3 ctrl_state +adi_if_ports output -1 lane_cgs_state +adi_if_ports output -1 lane_emb_state +adi_if_ports output -1 lane_frame_align +adi_if_ports output -1 lane_ifs_ready +adi_if_ports output -1 lane_latency_ready +adi_if_ports output -1 lane_latency +adi_if_ports output -1 err_statistics_cnt +adi_if_ports output -1 synth_params0 +adi_if_ports output -1 synth_params1 +adi_if_ports output -1 synth_params2 + +adi_if_define "jesd204_rx_ilas_config" +adi_if_ports output -1 valid +adi_if_ports output -1 addr +adi_if_ports input -1 data + +adi_if_define "jesd204_rx_event" +adi_if_ports output 1 sysref_alignment_error +adi_if_ports output 1 sysref_edge +adi_if_ports output 1 frame_alignment_error +adi_if_ports output 1 unexpected_lane_state_error diff --git a/adi_library/jesd204/interfaces/jesd204_rx_cfg.xml b/adi_library/jesd204/interfaces/jesd204_rx_cfg.xml new file mode 100644 index 00000000..4af755c1 --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_rx_cfg.xml @@ -0,0 +1,11 @@ + + + analog.com + interface + jesd204_rx_cfg + 1.0 + false + false + 1 + 1 + diff --git a/adi_library/jesd204/interfaces/jesd204_rx_cfg_rtl.xml b/adi_library/jesd204/interfaces/jesd204_rx_cfg_rtl.xml new file mode 100644 index 00000000..fe380130 --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_rx_cfg_rtl.xml @@ -0,0 +1,244 @@ + + + analog.com + interface + jesd204_rx_cfg_rtl + 1.0 + + + + lanes_disable + + + required + + + required + in + + + + + links_disable + + + required + + + required + in + + + + + octets_per_multiframe + + + required + 10 + + + required + 10 + in + + + + + octets_per_frame + + + required + 8 + + + required + 8 + in + + + + + disable_char_replacement + + + required + 1 + + + required + 1 + in + + + + + disable_scrambler + + + required + 1 + + + required + 1 + in + + + + + frame_align_err_threshold + + + required + 8 + + + required + 8 + in + + + + + device_octets_per_multiframe + + + required + 10 + + + required + 10 + in + + + + + device_octets_per_frame + + + required + 8 + + + required + 8 + in + + + + + device_beats_per_multiframe + + + required + 8 + + + required + 8 + in + + + + + device_lmfc_offset + + + required + 8 + + + required + 8 + in + + + + + device_sysref_oneshot + + + required + 1 + + + required + 1 + in + + + + + device_sysref_disable + + + required + 1 + + + required + 1 + in + + + + + device_buffer_early_release + + + required + 1 + + + required + 1 + in + + + + + device_buffer_delay + + + required + 1 + + + required + 1 + in + + + + + err_statistics_reset + + + required + 1 + + + required + 1 + in + + + + + err_statistics_mask + + + required + 7 + + + required + 7 + in + + + + + diff --git a/adi_library/jesd204/interfaces/jesd204_rx_cfg_v1_0.sv b/adi_library/jesd204/interfaces/jesd204_rx_cfg_v1_0.sv new file mode 100644 index 00000000..cdf6c0f4 --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_rx_cfg_v1_0.sv @@ -0,0 +1,103 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +`ifndef jesd204_rx_cfg_v1_0 +`define jesd204_rx_cfg_v1_0 + +package parameter_structs; + + typedef struct packed { + bit portEnabled; + integer portWidth; + }portConfig; + + typedef struct packed { + // = {, } + portConfig lanes_disable; + portConfig links_disable; + }jesd204_rx_cfg_v1_0_port_configuration; + + parameter jesd204_rx_cfg_v1_0_port_configuration jesd204_rx_cfg_v1_0_default_port_configuration = '{lanes_disable:'{1, -1}, links_disable:'{1, -1}}; + +endpackage + +interface jesd204_rx_cfg_v1_0 #(parameter_structs::jesd204_rx_cfg_v1_0_port_configuration port_configuration)(); + logic [port_configuration.lanes_disable.portWidth-1:0] lanes_disable; // + logic [port_configuration.links_disable.portWidth-1:0] links_disable; // + logic [9:0] octets_per_multiframe; // + logic [7:0] octets_per_frame; // + logic disable_char_replacement; // + logic disable_scrambler; // + logic [7:0] frame_align_err_threshold; // + logic [9:0] device_octets_per_multiframe; // + logic [7:0] device_octets_per_frame; // + logic [7:0] device_beats_per_multiframe; // + logic [7:0] device_lmfc_offset; // + logic device_sysref_oneshot; // + logic device_sysref_disable; // + logic device_buffer_early_release; // + logic device_buffer_delay; // + logic err_statistics_reset; // + logic [6:0] err_statistics_mask; // + + modport MASTER ( + output lanes_disable, links_disable, octets_per_multiframe, octets_per_frame, disable_char_replacement, disable_scrambler, frame_align_err_threshold, device_octets_per_multiframe, device_octets_per_frame, device_beats_per_multiframe, device_lmfc_offset, device_sysref_oneshot, device_sysref_disable, device_buffer_early_release, device_buffer_delay, err_statistics_reset, err_statistics_mask + ); + + modport SLAVE ( + input lanes_disable, links_disable, octets_per_multiframe, octets_per_frame, disable_char_replacement, disable_scrambler, frame_align_err_threshold, device_octets_per_multiframe, device_octets_per_frame, device_beats_per_multiframe, device_lmfc_offset, device_sysref_oneshot, device_sysref_disable, device_buffer_early_release, device_buffer_delay, err_statistics_reset, err_statistics_mask + ); + + modport MONITOR ( + input lanes_disable, links_disable, octets_per_multiframe, octets_per_frame, disable_char_replacement, disable_scrambler, frame_align_err_threshold, device_octets_per_multiframe, device_octets_per_frame, device_beats_per_multiframe, device_lmfc_offset, device_sysref_oneshot, device_sysref_disable, device_buffer_early_release, device_buffer_delay, err_statistics_reset, err_statistics_mask + ); + +endinterface // jesd204_rx_cfg_v1_0 + +`endif \ No newline at end of file diff --git a/adi_library/jesd204/interfaces/jesd204_rx_event.xml b/adi_library/jesd204/interfaces/jesd204_rx_event.xml new file mode 100644 index 00000000..e7c016a4 --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_rx_event.xml @@ -0,0 +1,11 @@ + + + analog.com + interface + jesd204_rx_event + 1.0 + false + false + 1 + 1 + diff --git a/adi_library/jesd204/interfaces/jesd204_rx_event_rtl.xml b/adi_library/jesd204/interfaces/jesd204_rx_event_rtl.xml new file mode 100644 index 00000000..bb546bac --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_rx_event_rtl.xml @@ -0,0 +1,66 @@ + + + analog.com + interface + jesd204_rx_event_rtl + 1.0 + + + + sysref_alignment_error + + + required + 1 + + + required + 1 + in + + + + + sysref_edge + + + required + 1 + + + required + 1 + in + + + + + frame_alignment_error + + + required + 1 + + + required + 1 + in + + + + + unexpected_lane_state_error + + + required + 1 + + + required + 1 + in + + + + + diff --git a/adi_library/jesd204/interfaces/jesd204_rx_event_v1_0.sv b/adi_library/jesd204/interfaces/jesd204_rx_event_v1_0.sv new file mode 100644 index 00000000..96ed2dcf --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_rx_event_v1_0.sv @@ -0,0 +1,73 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +`ifndef jesd204_rx_event_v1_0 +`define jesd204_rx_event_v1_0 + +interface jesd204_rx_event_v1_0(); + logic sysref_alignment_error; // + logic sysref_edge; // + logic frame_alignment_error; // + logic unexpected_lane_state_error; // + + modport MASTER ( + output sysref_alignment_error, sysref_edge, frame_alignment_error, unexpected_lane_state_error + ); + + modport SLAVE ( + input sysref_alignment_error, sysref_edge, frame_alignment_error, unexpected_lane_state_error + ); + + modport MONITOR ( + input sysref_alignment_error, sysref_edge, frame_alignment_error, unexpected_lane_state_error + ); + +endinterface // jesd204_rx_event_v1_0 + +`endif \ No newline at end of file diff --git a/adi_library/jesd204/interfaces/jesd204_rx_ilas_config.xml b/adi_library/jesd204/interfaces/jesd204_rx_ilas_config.xml new file mode 100644 index 00000000..c407272f --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_rx_ilas_config.xml @@ -0,0 +1,11 @@ + + + analog.com + interface + jesd204_rx_ilas_config + 1.0 + false + false + 1 + 1 + diff --git a/adi_library/jesd204/interfaces/jesd204_rx_ilas_config_rtl.xml b/adi_library/jesd204/interfaces/jesd204_rx_ilas_config_rtl.xml new file mode 100644 index 00000000..24dc5139 --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_rx_ilas_config_rtl.xml @@ -0,0 +1,46 @@ + + + analog.com + interface + jesd204_rx_ilas_config_rtl + 1.0 + + + + valid + + + required + + + required + in + + + + + addr + + + required + + + required + in + + + + + data + + + required + in + + + required + + + + + diff --git a/adi_library/jesd204/interfaces/jesd204_rx_ilas_config_v1_0.sv b/adi_library/jesd204/interfaces/jesd204_rx_ilas_config_v1_0.sv new file mode 100644 index 00000000..b85bac7e --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_rx_ilas_config_v1_0.sv @@ -0,0 +1,92 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +`ifndef jesd204_rx_ilas_config_v1_0 +`define jesd204_rx_ilas_config_v1_0 + +package parameter_structs; + + typedef struct packed { + bit portEnabled; + integer portWidth; + }portConfig; + + typedef struct packed { + // = {, } + portConfig valid; + portConfig addr; + portConfig data; + }jesd204_rx_ilas_config_v1_0_port_configuration; + + parameter jesd204_rx_ilas_config_v1_0_port_configuration jesd204_rx_ilas_config_v1_0_default_port_configuration = '{valid:'{1, -1}, addr:'{1, -1}, data:'{1, -1}}; + +endpackage + +interface jesd204_rx_ilas_config_v1_0 #(parameter_structs::jesd204_rx_ilas_config_v1_0_port_configuration port_configuration)(); + logic [port_configuration.valid.portWidth-1:0] valid; // + logic [port_configuration.addr.portWidth-1:0] addr; // + logic [port_configuration.data.portWidth-1:0] data; // + + modport MASTER ( + input data, + output valid, addr + ); + + modport SLAVE ( + input valid, addr, + output data + ); + + modport MONITOR ( + input valid, addr, data + ); + +endinterface // jesd204_rx_ilas_config_v1_0 + +`endif \ No newline at end of file diff --git a/adi_library/jesd204/interfaces/jesd204_rx_status.xml b/adi_library/jesd204/interfaces/jesd204_rx_status.xml new file mode 100644 index 00000000..adadbe72 --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_rx_status.xml @@ -0,0 +1,11 @@ + + + analog.com + interface + jesd204_rx_status + 1.0 + false + false + 1 + 1 + diff --git a/adi_library/jesd204/interfaces/jesd204_rx_status_rtl.xml b/adi_library/jesd204/interfaces/jesd204_rx_status_rtl.xml new file mode 100644 index 00000000..1e107373 --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_rx_status_rtl.xml @@ -0,0 +1,144 @@ + + + analog.com + interface + jesd204_rx_status_rtl + 1.0 + + + + ctrl_state + + + required + 3 + + + required + 3 + in + + + + + lane_cgs_state + + + required + + + required + in + + + + + lane_emb_state + + + required + + + required + in + + + + + lane_frame_align + + + required + + + required + in + + + + + lane_ifs_ready + + + required + + + required + in + + + + + lane_latency_ready + + + required + + + required + in + + + + + lane_latency + + + required + + + required + in + + + + + err_statistics_cnt + + + required + + + required + in + + + + + synth_params0 + + + required + + + required + in + + + + + synth_params1 + + + required + + + required + in + + + + + synth_params2 + + + required + + + required + in + + + + + diff --git a/adi_library/jesd204/interfaces/jesd204_rx_status_v1_0.sv b/adi_library/jesd204/interfaces/jesd204_rx_status_v1_0.sv new file mode 100644 index 00000000..e1541733 --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_rx_status_v1_0.sv @@ -0,0 +1,105 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +`ifndef jesd204_rx_status_v1_0 +`define jesd204_rx_status_v1_0 + +package parameter_structs; + + typedef struct packed { + bit portEnabled; + integer portWidth; + }portConfig; + + typedef struct packed { + // = {, } + portConfig lane_cgs_state; + portConfig lane_emb_state; + portConfig lane_frame_align; + portConfig lane_ifs_ready; + portConfig lane_latency_ready; + portConfig lane_latency; + portConfig err_statistics_cnt; + portConfig synth_params0; + portConfig synth_params1; + portConfig synth_params2; + }jesd204_rx_status_v1_0_port_configuration; + + parameter jesd204_rx_status_v1_0_port_configuration jesd204_rx_status_v1_0_default_port_configuration = '{lane_cgs_state:'{1, -1}, lane_emb_state:'{1, -1}, lane_frame_align:'{1, -1}, lane_ifs_ready:'{1, -1}, lane_latency_ready:'{1, -1}, lane_latency:'{1, -1}, err_statistics_cnt:'{1, -1}, synth_params0:'{1, -1}, synth_params1:'{1, -1}, synth_params2:'{1, -1}}; + +endpackage + +interface jesd204_rx_status_v1_0 #(parameter_structs::jesd204_rx_status_v1_0_port_configuration port_configuration)(); + logic [2:0] ctrl_state; // + logic [port_configuration.lane_cgs_state.portWidth-1:0] lane_cgs_state; // + logic [port_configuration.lane_emb_state.portWidth-1:0] lane_emb_state; // + logic [port_configuration.lane_frame_align.portWidth-1:0] lane_frame_align; // + logic [port_configuration.lane_ifs_ready.portWidth-1:0] lane_ifs_ready; // + logic [port_configuration.lane_latency_ready.portWidth-1:0] lane_latency_ready; // + logic [port_configuration.lane_latency.portWidth-1:0] lane_latency; // + logic [port_configuration.err_statistics_cnt.portWidth-1:0] err_statistics_cnt; // + logic [port_configuration.synth_params0.portWidth-1:0] synth_params0; // + logic [port_configuration.synth_params1.portWidth-1:0] synth_params1; // + logic [port_configuration.synth_params2.portWidth-1:0] synth_params2; // + + modport MASTER ( + output ctrl_state, lane_cgs_state, lane_emb_state, lane_frame_align, lane_ifs_ready, lane_latency_ready, lane_latency, err_statistics_cnt, synth_params0, synth_params1, synth_params2 + ); + + modport SLAVE ( + input ctrl_state, lane_cgs_state, lane_emb_state, lane_frame_align, lane_ifs_ready, lane_latency_ready, lane_latency, err_statistics_cnt, synth_params0, synth_params1, synth_params2 + ); + + modport MONITOR ( + input ctrl_state, lane_cgs_state, lane_emb_state, lane_frame_align, lane_ifs_ready, lane_latency_ready, lane_latency, err_statistics_cnt, synth_params0, synth_params1, synth_params2 + ); + +endinterface // jesd204_rx_status_v1_0 + +`endif \ No newline at end of file diff --git a/adi_library/jesd204/interfaces/jesd204_tx_cfg.xml b/adi_library/jesd204/interfaces/jesd204_tx_cfg.xml new file mode 100644 index 00000000..f4e7e4ea --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_tx_cfg.xml @@ -0,0 +1,11 @@ + + + analog.com + interface + jesd204_tx_cfg + 1.0 + false + false + 1 + 1 + diff --git a/adi_library/jesd204/interfaces/jesd204_tx_cfg_rtl.xml b/adi_library/jesd204/interfaces/jesd204_tx_cfg_rtl.xml new file mode 100644 index 00000000..6c425d0f --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_tx_cfg_rtl.xml @@ -0,0 +1,230 @@ + + + analog.com + interface + jesd204_tx_cfg_rtl + 1.0 + + + + lanes_disable + + + required + + + required + in + + + + + links_disable + + + required + + + required + in + + + + + octets_per_multiframe + + + required + 10 + + + required + 10 + in + + + + + octets_per_frame + + + required + 8 + + + required + 8 + in + + + + + continuous_cgs + + + required + 1 + + + required + 1 + in + + + + + continuous_ilas + + + required + 1 + + + required + 1 + in + + + + + skip_ilas + + + required + 1 + + + required + 1 + in + + + + + mframes_per_ilas + + + required + 8 + + + required + 8 + in + + + + + disable_char_replacement + + + required + 1 + + + required + 1 + in + + + + + disable_scrambler + + + required + 1 + + + required + 1 + in + + + + + device_octets_per_multiframe + + + required + 10 + + + required + 10 + in + + + + + device_octets_per_frame + + + required + 8 + + + required + 8 + in + + + + + device_beats_per_multiframe + + + required + 8 + + + required + 8 + in + + + + + device_lmfc_offset + + + required + 8 + + + required + 8 + in + + + + + device_sysref_oneshot + + + required + 1 + + + required + 1 + in + + + + + device_sysref_disable + + + required + 1 + + + required + 1 + in + + + + + diff --git a/adi_library/jesd204/interfaces/jesd204_tx_cfg_v1_0.sv b/adi_library/jesd204/interfaces/jesd204_tx_cfg_v1_0.sv new file mode 100644 index 00000000..0fd1c255 --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_tx_cfg_v1_0.sv @@ -0,0 +1,102 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +`ifndef jesd204_tx_cfg_v1_0 +`define jesd204_tx_cfg_v1_0 + +package parameter_structs; + + typedef struct packed { + bit portEnabled; + integer portWidth; + }portConfig; + + typedef struct packed { + // = {, } + portConfig lanes_disable; + portConfig links_disable; + }jesd204_tx_cfg_v1_0_port_configuration; + + parameter jesd204_tx_cfg_v1_0_port_configuration jesd204_tx_cfg_v1_0_default_port_configuration = '{lanes_disable:'{1, -1}, links_disable:'{1, -1}}; + +endpackage + +interface jesd204_tx_cfg_v1_0 #(parameter_structs::jesd204_tx_cfg_v1_0_port_configuration port_configuration)(); + logic [port_configuration.lanes_disable.portWidth-1:0] lanes_disable; // + logic [port_configuration.links_disable.portWidth-1:0] links_disable; // + logic [9:0] octets_per_multiframe; // + logic [7:0] octets_per_frame; // + logic continuous_cgs; // + logic continuous_ilas; // + logic skip_ilas; // + logic [7:0] mframes_per_ilas; // + logic disable_char_replacement; // + logic disable_scrambler; // + logic [9:0] device_octets_per_multiframe; // + logic [7:0] device_octets_per_frame; // + logic [7:0] device_beats_per_multiframe; // + logic [7:0] device_lmfc_offset; // + logic device_sysref_oneshot; // + logic device_sysref_disable; // + + modport MASTER ( + output lanes_disable, links_disable, octets_per_multiframe, octets_per_frame, continuous_cgs, continuous_ilas, skip_ilas, mframes_per_ilas, disable_char_replacement, disable_scrambler, device_octets_per_multiframe, device_octets_per_frame, device_beats_per_multiframe, device_lmfc_offset, device_sysref_oneshot, device_sysref_disable + ); + + modport SLAVE ( + input lanes_disable, links_disable, octets_per_multiframe, octets_per_frame, continuous_cgs, continuous_ilas, skip_ilas, mframes_per_ilas, disable_char_replacement, disable_scrambler, device_octets_per_multiframe, device_octets_per_frame, device_beats_per_multiframe, device_lmfc_offset, device_sysref_oneshot, device_sysref_disable + ); + + modport MONITOR ( + input lanes_disable, links_disable, octets_per_multiframe, octets_per_frame, continuous_cgs, continuous_ilas, skip_ilas, mframes_per_ilas, disable_char_replacement, disable_scrambler, device_octets_per_multiframe, device_octets_per_frame, device_beats_per_multiframe, device_lmfc_offset, device_sysref_oneshot, device_sysref_disable + ); + +endinterface // jesd204_tx_cfg_v1_0 + +`endif \ No newline at end of file diff --git a/adi_library/jesd204/interfaces/jesd204_tx_ctrl.xml b/adi_library/jesd204/interfaces/jesd204_tx_ctrl.xml new file mode 100644 index 00000000..55c3ad88 --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_tx_ctrl.xml @@ -0,0 +1,11 @@ + + + analog.com + interface + jesd204_tx_ctrl + 1.0 + false + false + 1 + 1 + diff --git a/adi_library/jesd204/interfaces/jesd204_tx_ctrl_rtl.xml b/adi_library/jesd204/interfaces/jesd204_tx_ctrl_rtl.xml new file mode 100644 index 00000000..938ab0da --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_tx_ctrl_rtl.xml @@ -0,0 +1,24 @@ + + + analog.com + interface + jesd204_tx_ctrl_rtl + 1.0 + + + + manual_sync_request + + + required + 1 + + + required + 1 + in + + + + + diff --git a/adi_library/jesd204/interfaces/jesd204_tx_ctrl_v1_0.sv b/adi_library/jesd204/interfaces/jesd204_tx_ctrl_v1_0.sv new file mode 100644 index 00000000..82652fa9 --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_tx_ctrl_v1_0.sv @@ -0,0 +1,70 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +`ifndef jesd204_tx_ctrl_v1_0 +`define jesd204_tx_ctrl_v1_0 + +interface jesd204_tx_ctrl_v1_0(); + logic manual_sync_request; // + + modport MASTER ( + output manual_sync_request + ); + + modport SLAVE ( + input manual_sync_request + ); + + modport MONITOR ( + input manual_sync_request + ); + +endinterface // jesd204_tx_ctrl_v1_0 + +`endif \ No newline at end of file diff --git a/adi_library/jesd204/interfaces/jesd204_tx_event.xml b/adi_library/jesd204/interfaces/jesd204_tx_event.xml new file mode 100644 index 00000000..8d209a97 --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_tx_event.xml @@ -0,0 +1,11 @@ + + + analog.com + interface + jesd204_tx_event + 1.0 + false + false + 1 + 1 + diff --git a/adi_library/jesd204/interfaces/jesd204_tx_event_rtl.xml b/adi_library/jesd204/interfaces/jesd204_tx_event_rtl.xml new file mode 100644 index 00000000..1ea6e2f6 --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_tx_event_rtl.xml @@ -0,0 +1,38 @@ + + + analog.com + interface + jesd204_tx_event_rtl + 1.0 + + + + sysref_alignment_error + + + required + 1 + + + required + 1 + in + + + + + sysref_edge + + + required + 1 + + + required + 1 + in + + + + + diff --git a/adi_library/jesd204/interfaces/jesd204_tx_event_v1_0.sv b/adi_library/jesd204/interfaces/jesd204_tx_event_v1_0.sv new file mode 100644 index 00000000..7c59d459 --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_tx_event_v1_0.sv @@ -0,0 +1,71 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +`ifndef jesd204_tx_event_v1_0 +`define jesd204_tx_event_v1_0 + +interface jesd204_tx_event_v1_0(); + logic sysref_alignment_error; // + logic sysref_edge; // + + modport MASTER ( + output sysref_alignment_error, sysref_edge + ); + + modport SLAVE ( + input sysref_alignment_error, sysref_edge + ); + + modport MONITOR ( + input sysref_alignment_error, sysref_edge + ); + +endinterface // jesd204_tx_event_v1_0 + +`endif \ No newline at end of file diff --git a/adi_library/jesd204/interfaces/jesd204_tx_ilas_config.xml b/adi_library/jesd204/interfaces/jesd204_tx_ilas_config.xml new file mode 100644 index 00000000..b46e7e73 --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_tx_ilas_config.xml @@ -0,0 +1,11 @@ + + + analog.com + interface + jesd204_tx_ilas_config + 1.0 + false + false + 1 + 1 + diff --git a/adi_library/jesd204/interfaces/jesd204_tx_ilas_config_rtl.xml b/adi_library/jesd204/interfaces/jesd204_tx_ilas_config_rtl.xml new file mode 100644 index 00000000..941c9d57 --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_tx_ilas_config_rtl.xml @@ -0,0 +1,52 @@ + + + analog.com + interface + jesd204_tx_ilas_config_rtl + 1.0 + + + + rd + + + required + 1 + + + required + 1 + in + + + + + addr + + + required + 2 + + + required + 2 + in + + + + + data + + + required + 32 + in + + + required + 32 + + + + + diff --git a/adi_library/jesd204/interfaces/jesd204_tx_ilas_config_v1_0.sv b/adi_library/jesd204/interfaces/jesd204_tx_ilas_config_v1_0.sv new file mode 100644 index 00000000..e1a0c6c4 --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_tx_ilas_config_v1_0.sv @@ -0,0 +1,74 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +`ifndef jesd204_tx_ilas_config_v1_0 +`define jesd204_tx_ilas_config_v1_0 + +interface jesd204_tx_ilas_config_v1_0(); + logic rd; // + logic [1:0] addr; // + logic [31:0] data; // + + modport MASTER ( + input data, + output rd, addr + ); + + modport SLAVE ( + input rd, addr, + output data + ); + + modport MONITOR ( + input rd, addr, data + ); + +endinterface // jesd204_tx_ilas_config_v1_0 + +`endif \ No newline at end of file diff --git a/adi_library/jesd204/interfaces/jesd204_tx_status.xml b/adi_library/jesd204/interfaces/jesd204_tx_status.xml new file mode 100644 index 00000000..6e5c46bb --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_tx_status.xml @@ -0,0 +1,11 @@ + + + analog.com + interface + jesd204_tx_status + 1.0 + false + false + 1 + 1 + diff --git a/adi_library/jesd204/interfaces/jesd204_tx_status_rtl.xml b/adi_library/jesd204/interfaces/jesd204_tx_status_rtl.xml new file mode 100644 index 00000000..ffc499c8 --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_tx_status_rtl.xml @@ -0,0 +1,74 @@ + + + analog.com + interface + jesd204_tx_status_rtl + 1.0 + + + + state + + + required + 1 + + + required + 1 + in + + + + + sync + + + required + 1 + + + required + 1 + in + + + + + synth_params0 + + + required + + + required + in + + + + + synth_params1 + + + required + + + required + in + + + + + synth_params2 + + + required + + + required + in + + + + + diff --git a/adi_library/jesd204/interfaces/jesd204_tx_status_v1_0.sv b/adi_library/jesd204/interfaces/jesd204_tx_status_v1_0.sv new file mode 100644 index 00000000..60b0bfc1 --- /dev/null +++ b/adi_library/jesd204/interfaces/jesd204_tx_status_v1_0.sv @@ -0,0 +1,92 @@ +// (c) Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +// (c) Copyright 2022-2024 Advanced Micro Devices, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of AMD and is protected under U.S. and international copyright +// and other intellectual property laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// AMD, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) AMD shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or AMD had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// AMD products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of AMD products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// DO NOT MODIFY THIS FILE. + + +`ifndef jesd204_tx_status_v1_0 +`define jesd204_tx_status_v1_0 + +package parameter_structs; + + typedef struct packed { + bit portEnabled; + integer portWidth; + }portConfig; + + typedef struct packed { + // = {, } + portConfig synth_params0; + portConfig synth_params1; + portConfig synth_params2; + }jesd204_tx_status_v1_0_port_configuration; + + parameter jesd204_tx_status_v1_0_port_configuration jesd204_tx_status_v1_0_default_port_configuration = '{synth_params0:'{1, -1}, synth_params1:'{1, -1}, synth_params2:'{1, -1}}; + +endpackage + +interface jesd204_tx_status_v1_0 #(parameter_structs::jesd204_tx_status_v1_0_port_configuration port_configuration)(); + logic state; // + logic sync; // + logic [port_configuration.synth_params0.portWidth-1:0] synth_params0; // + logic [port_configuration.synth_params1.portWidth-1:0] synth_params1; // + logic [port_configuration.synth_params2.portWidth-1:0] synth_params2; // + + modport MASTER ( + output state, sync, synth_params0, synth_params1, synth_params2 + ); + + modport SLAVE ( + input state, sync, synth_params0, synth_params1, synth_params2 + ); + + modport MONITOR ( + input state, sync, synth_params0, synth_params1, synth_params2 + ); + +endinterface // jesd204_tx_status_v1_0 + +`endif \ No newline at end of file diff --git a/adi_library/jesd204/jesd204_common/Makefile b/adi_library/jesd204/jesd204_common/Makefile new file mode 100644 index 00000000..5d0a3c42 --- /dev/null +++ b/adi_library/jesd204/jesd204_common/Makefile @@ -0,0 +1,20 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := jesd204_common + +GENERIC_DEPS += jesd204_crc12.v +GENERIC_DEPS += jesd204_eof_generator.v +GENERIC_DEPS += jesd204_frame_align_replace.v +GENERIC_DEPS += jesd204_frame_mark.v +GENERIC_DEPS += jesd204_lmfc.v +GENERIC_DEPS += jesd204_scrambler.v +GENERIC_DEPS += jesd204_scrambler_64b.v +GENERIC_DEPS += pipeline_stage.v + +XILINX_DEPS += jesd204_common_ip.tcl + +include ../../scripts/library.mk diff --git a/adi_library/jesd204/jesd204_common/component.xml b/adi_library/jesd204/jesd204_common/component.xml new file mode 100644 index 00000000..75592bd1 --- /dev/null +++ b/adi_library/jesd204/jesd204_common/component.xml @@ -0,0 +1,266 @@ + + + analog.com + user + jesd204_common + 1.0 + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + pipeline_stage + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 392e3498 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + pipeline_stage + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 392e3498 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + fa2aa10a + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + in + + in + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + out + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + REGISTERED + Registered + 1 + + + WIDTH + Width + 1 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + jesd204_lmfc.v + verilogSource + + + jesd204_scrambler.v + verilogSource + + + jesd204_scrambler_64b.v + verilogSource + + + jesd204_crc12.v + verilogSource + + + jesd204_eof_generator.v + verilogSource + + + jesd204_frame_mark.v + verilogSource + + + jesd204_frame_align_replace.v + verilogSource + + + pipeline_stage.v + verilogSource + CHECKSUM_b063a4fc + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + jesd204_lmfc.v + verilogSource + + + jesd204_scrambler.v + verilogSource + + + jesd204_scrambler_64b.v + verilogSource + + + jesd204_crc12.v + verilogSource + + + jesd204_eof_generator.v + verilogSource + + + jesd204_frame_mark.v + verilogSource + + + jesd204_frame_align_replace.v + verilogSource + + + pipeline_stage.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/pipeline_stage_v1_0.tcl + tclSource + CHECKSUM_fa2aa10a + XGUI_VERSION_2 + + + + ADI JESD204C Common Library + + + REGISTERED + Registered + 1 + + + WIDTH + Width + 1 + + + Component_Name + pipeline_stage_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + ADI JESD204C Common Library + true + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:51:22Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/jesd204/jesd204_common/jesd204_common.xpr b/adi_library/jesd204/jesd204_common/jesd204_common.xpr new file mode 100644 index 00000000..deb33a81 --- /dev/null +++ b/adi_library/jesd204/jesd204_common/jesd204_common.xpr @@ -0,0 +1,449 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/jesd204/jesd204_common/jesd204_common_ip.tcl b/adi_library/jesd204/jesd204_common/jesd204_common_ip.tcl new file mode 100755 index 00000000..afd58a7d --- /dev/null +++ b/adi_library/jesd204/jesd204_common/jesd204_common_ip.tcl @@ -0,0 +1,30 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create jesd204_common + +add_files -fileset [get_filesets sources_1] [list \ + "jesd204_lmfc.v" \ + "jesd204_scrambler.v" \ + "jesd204_scrambler_64b.v" \ + "jesd204_crc12.v" \ + "jesd204_eof_generator.v" \ + "jesd204_frame_mark.v" \ + "jesd204_frame_align_replace.v" \ + "pipeline_stage.v" \ +] + +set_property source_mgmt_mode DisplayOnly [current_project] + +adi_ip_properties_lite jesd204_common + +set_property display_name "ADI JESD204C Common Library" [ipx::current_core] +set_property description "ADI JESD204C Common Library" [ipx::current_core] +set_property hide_in_gui {1} [ipx::current_core] + +ipx::save_core [ipx::current_core] diff --git a/adi_library/jesd204/jesd204_common/jesd204_crc12.v b/adi_library/jesd204/jesd204_common/jesd204_crc12.v new file mode 100644 index 00000000..85a9d4ec --- /dev/null +++ b/adi_library/jesd204/jesd204_common/jesd204_crc12.v @@ -0,0 +1,51 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_crc12 #( + parameter WIDTH = 64 +) ( + input clk, + input reset, + + input init, + + input [WIDTH-1:0] data_in, + output [11:0] crc12 +); + + reg [11:0] state = 12'b0; + + wire [WIDTH-1:0] feedback; + wire [WIDTH-1+12:0] full_state; + + assign full_state = {init ? 12'h0 : state, feedback}; + assign feedback = full_state[WIDTH-1+12:12] ^ + full_state[WIDTH-1:11] ^ + full_state[WIDTH-1:10] ^ + full_state[WIDTH-1:9] ^ + full_state[WIDTH-1:4] ^ + full_state[WIDTH-1:3] ^ + data_in; + + always @(posedge clk) begin + if (reset == 1'b1) begin + state <= 12'b0; + end else begin + state <= full_state[11:0] ^ + {full_state[10:0],1'b0} ^ + {full_state[9:0],2'b0} ^ + {full_state[8:0],3'b0} ^ + {full_state[3:0],8'b0} ^ + {full_state[2:0],9'b0}; + end + end + + assign crc12 = state; + +endmodule diff --git a/adi_library/jesd204/jesd204_common/jesd204_eof_generator.v b/adi_library/jesd204/jesd204_common/jesd204_eof_generator.v new file mode 100644 index 00000000..03cb7c21 --- /dev/null +++ b/adi_library/jesd204/jesd204_common/jesd204_eof_generator.v @@ -0,0 +1,117 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_eof_generator #( + parameter DATA_PATH_WIDTH = 4, + parameter MAX_OCTETS_PER_FRAME = 256 +) ( + input clk, + input reset, + + input lmfc_edge, + + input [7:0] cfg_octets_per_frame, + input cfg_generate_eomf, + + output reg [DATA_PATH_WIDTH-1:0] sof, + output reg [DATA_PATH_WIDTH-1:0] eof, + output reg eomf +); + + localparam CW = MAX_OCTETS_PER_FRAME > 128 ? 8 : + MAX_OCTETS_PER_FRAME > 64 ? 7 : + MAX_OCTETS_PER_FRAME > 32 ? 6 : + MAX_OCTETS_PER_FRAME > 16 ? 5 : + MAX_OCTETS_PER_FRAME > 8 ? 4 : + MAX_OCTETS_PER_FRAME > 4 ? 3 : + MAX_OCTETS_PER_FRAME > 2 ? 2 : 1; + localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : + DATA_PATH_WIDTH == 4 ? 2 : 1; + + reg lmfc_edge_d1 = 1'b0; + + wire beat_counter_sof; + wire beat_counter_eof; + wire small_octets_per_frame; + + always @(posedge clk) begin + if (cfg_generate_eomf == 1'b1) begin + lmfc_edge_d1 <= lmfc_edge; + end else begin + lmfc_edge_d1 <= 1'b0; + end + eomf <= lmfc_edge_d1; + end + + generate + if (CW > DPW_LOG2) begin + reg [CW-DPW_LOG2-1:0] beat_counter = 'h00; + wire [CW-DPW_LOG2-1:0] cfg_beats_per_frame = cfg_octets_per_frame[CW-1:DPW_LOG2]; + + assign beat_counter_sof = beat_counter == 'h00; + assign beat_counter_eof = beat_counter == cfg_beats_per_frame; + assign small_octets_per_frame = cfg_beats_per_frame == 'h00; + + always @(posedge clk) begin + if (reset == 1'b1) begin + beat_counter <= 'h00; + end else if (beat_counter_eof == 1'b1) begin + beat_counter <= 'h00; + end else begin + beat_counter <= beat_counter + 1'b1; + end + end + + end else begin + assign beat_counter_sof = 1'b1; + assign beat_counter_eof = 1'b1; + assign small_octets_per_frame = 1'b1; + end + endgenerate + + function [1:0] ffs; + input [2:0] x; + begin + case (x) + 1: ffs = 0; + 2: ffs = 1; + 3: ffs = 0; + 4: ffs = 2; + 5: ffs = 0; + 6: ffs = 1; + 7: ffs = 0; + default: ffs = 0; + endcase + end + endfunction + + integer i; + + /* Only 1, 2 and multiples of 4 are supported atm */ + always @(posedge clk) begin + if (reset == 1'b1) begin + sof <= {DATA_PATH_WIDTH{1'b0}}; + eof <= {DATA_PATH_WIDTH{1'b0}}; + end else begin + sof <= {{DATA_PATH_WIDTH-1{1'b0}},beat_counter_sof}; + eof <= {beat_counter_eof,{DATA_PATH_WIDTH-1{1'b0}}}; + + if (small_octets_per_frame == 1'b1) begin + for (i = 1; i < DATA_PATH_WIDTH; i = i + 1) begin + if (cfg_octets_per_frame[ffs(i)] != 1'b1) begin + sof[i] <= 1'b1; + eof[DATA_PATH_WIDTH-1-i] <= 1'b1; + end + end + end else begin + end + end + end + +endmodule diff --git a/adi_library/jesd204/jesd204_common/jesd204_frame_align_replace.v b/adi_library/jesd204/jesd204_common/jesd204_frame_align_replace.v new file mode 100755 index 00000000..41e1a653 --- /dev/null +++ b/adi_library/jesd204/jesd204_common/jesd204_frame_align_replace.v @@ -0,0 +1,209 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2021, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +// Limitations: +// DATA_PATH_WIDTH = 4, 8 +// F=1,2,3,4,6, and multiples of DATA_PATH_WIDTH + +`timescale 1ns/100ps + +module jesd204_frame_align_replace #( + parameter DATA_PATH_WIDTH = 4, + parameter IS_RX = 1'b1, + parameter ENABLED = 1'b1 +) ( + input clk, + input reset, + + input [7:0] cfg_octets_per_frame, + input cfg_disable_char_replacement, + input cfg_disable_scrambler, + + input [DATA_PATH_WIDTH*8-1:0] data, + input [DATA_PATH_WIDTH-1:0] eof, + input [DATA_PATH_WIDTH-1:0] rx_char_is_a, + input [DATA_PATH_WIDTH-1:0] rx_char_is_f, + input [DATA_PATH_WIDTH-1:0] tx_eomf, + + output [DATA_PATH_WIDTH*8-1:0] data_out, + output [DATA_PATH_WIDTH-1:0] charisk_out +); + + localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1; + + wire single_eof = cfg_octets_per_frame >= (DATA_PATH_WIDTH-1); + reg [DATA_PATH_WIDTH*8-1:0] data_d1; + reg [DATA_PATH_WIDTH*8-1:0] data_d2; + wire [DATA_PATH_WIDTH-1:0] char_is_align; + reg [DATA_PATH_WIDTH-1:0] char_is_align_d1; + reg [DATA_PATH_WIDTH-1:0] char_is_align_d2; + wire [((DATA_PATH_WIDTH*2)+4)*8-1:0] saved_data; + wire [((DATA_PATH_WIDTH*2)+4)-1:0] saved_char_is_align; + wire [DATA_PATH_WIDTH*8-1:0] data_replaced; + wire [DATA_PATH_WIDTH*8-1:0] data_prev_eof; + wire [DATA_PATH_WIDTH*8-1:0] data_prev_prev_eof; + reg [7:0] data_prev_eof_single; + reg [7:0] data_prev_eof_single_int; + reg char_is_align_prev_single; + + wire [DATA_PATH_WIDTH*8-1:0] prev_data_1; + wire [DATA_PATH_WIDTH*8-1:0] prev_prev_data_1; + wire [DATA_PATH_WIDTH-1:0] prev_char_is_align_1; + wire [DATA_PATH_WIDTH*8-1:0] prev_data_2; + wire [DATA_PATH_WIDTH*8-1:0] prev_prev_data_2; + wire [DATA_PATH_WIDTH-1:0] prev_char_is_align_2; + wire [DATA_PATH_WIDTH*8-1:0] prev_data_3; + wire [DATA_PATH_WIDTH*8-1:0] prev_prev_data_3; + wire [DATA_PATH_WIDTH-1:0] prev_char_is_align_3; + wire [DATA_PATH_WIDTH*8-1:0] prev_data_4; + wire [DATA_PATH_WIDTH*8-1:0] prev_prev_data_4; + wire [DATA_PATH_WIDTH-1:0] prev_char_is_align_4; + wire [DATA_PATH_WIDTH*8-1:0] prev_data_6; + wire [DATA_PATH_WIDTH*8-1:0] prev_prev_data_6; + wire [DATA_PATH_WIDTH-1:0] prev_char_is_align_6; + reg [DATA_PATH_WIDTH*8-1:0] prev_data; + reg [DATA_PATH_WIDTH*8-1:0] prev_prev_data; + reg [DATA_PATH_WIDTH-1:0] prev_char_is_align; + reg [DPW_LOG2:0] jj; + reg [DPW_LOG2:0] ll; + + always @(posedge clk) begin + data_d1 <= data; + data_d2 <= data_d1; + end + + always @(posedge clk) begin + if(reset) begin + char_is_align_d1 <= 'b0; + char_is_align_d2 <= 'b0; + end else begin + char_is_align_d1 <= char_is_align; + char_is_align_d2 <= char_is_align_d1; + end + end + + // Capture single EOF in current cycle + + always @(eof, data) begin + data_prev_eof_single_int = 'b0; + for(ll = 0; ll < DATA_PATH_WIDTH; ll=ll+1) begin + data_prev_eof_single_int = data_prev_eof_single_int | (data[ll*8 +: 8] & {8{eof[ll]}}); + end + end + + always @(posedge clk) begin + if(reset) begin + data_prev_eof_single <= 'b0; + end else begin + if(|eof && (!IS_RX || !(|char_is_align))) begin + data_prev_eof_single <= data_prev_eof_single_int; + end + end + end + + always @(posedge clk) begin + if(reset) begin + char_is_align_prev_single <= 'b0; + end else begin + if(|eof) begin + char_is_align_prev_single <= |char_is_align; + end + end + end + + assign saved_data = {data, data_d1, data_d2[(DATA_PATH_WIDTH*8)-1:(DATA_PATH_WIDTH-4)*8]}; + assign saved_char_is_align = {char_is_align, char_is_align_d1, char_is_align_d2[DATA_PATH_WIDTH-1:DATA_PATH_WIDTH-4]}; + + genvar ii; + generate + for (ii = 0; ii < DATA_PATH_WIDTH; ii = ii + 1) begin: gen_replace_byte + assign prev_data_1[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+3+ii)*8 +: 8]; + assign prev_data_2[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+2+ii)*8 +: 8]; + assign prev_data_3[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+1+ii)*8 +: 8]; + assign prev_prev_data_1[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+2+ii)*8 +: 8]; + assign prev_prev_data_2[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+ii)*8 +: 8]; + assign prev_prev_data_3[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH-2+ii)*8 +: 8]; + assign prev_char_is_align_1[ii] = saved_char_is_align[(DATA_PATH_WIDTH+3+ii)]; + assign prev_char_is_align_2[ii] = saved_char_is_align[(DATA_PATH_WIDTH+2+ii)]; + assign prev_char_is_align_3[ii] = saved_char_is_align[(DATA_PATH_WIDTH+1+ii)]; + + if(DATA_PATH_WIDTH == 8) begin : gen_dp_8 + assign prev_data_4[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH+ii)*8 +: 8]; + assign prev_data_6[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH-2+ii)*8 +: 8]; + assign prev_prev_data_4[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH-4+ii)*8 +: 8]; + assign prev_prev_data_6[ii*8 +:8] = saved_data[(DATA_PATH_WIDTH-8+ii)*8 +: 8]; + assign prev_char_is_align_4[ii] = saved_char_is_align[(DATA_PATH_WIDTH+ii)]; + assign prev_char_is_align_6[ii] = saved_char_is_align[(DATA_PATH_WIDTH-2+ii)]; + end else begin + assign prev_data_4[ii*8 +:8] = 'bX; + assign prev_data_6[ii*8 +:8] = 'bX; + assign prev_prev_data_4[ii*8 +:8] = 'bX; + assign prev_prev_data_6[ii*8 +:8] = 'bX; + assign prev_char_is_align_4[ii] = 'bX; + assign prev_char_is_align_6[ii] = 'bX; + end + + always @(*) begin + case(cfg_octets_per_frame) + 0: + begin + prev_data[ii*8 +:8] = prev_data_1[ii*8 +:8]; + prev_prev_data[ii*8 +:8] = prev_prev_data_1[ii*8 +:8]; + prev_char_is_align[ii] = prev_char_is_align_1[ii]; + end + 1: + begin + prev_data[ii*8 +:8] = prev_data_2[ii*8 +:8]; + prev_prev_data[ii*8 +:8] = prev_prev_data_2[ii*8 +:8]; + prev_char_is_align[ii] = prev_char_is_align_2[ii]; + end + 2: + begin + prev_data[ii*8 +:8] = prev_data_3[ii*8 +:8]; + prev_prev_data[ii*8 +:8] = prev_prev_data_3[ii*8 +:8]; + prev_char_is_align[ii] = prev_char_is_align_3[ii]; + end + 3: + begin + prev_data[ii*8 +:8] = prev_data_4[ii*8 +:8]; + prev_prev_data[ii*8 +:8] = prev_prev_data_4[ii*8 +:8]; + prev_char_is_align[ii] = prev_char_is_align_4[ii]; + end + 5: + begin + prev_data[ii*8 +:8] = prev_data_6[ii*8 +:8]; + prev_prev_data[ii*8 +:8] = prev_prev_data_6[ii*8 +:8]; + prev_char_is_align[ii] = prev_char_is_align_6[ii]; + end + default: + begin + prev_data[ii*8 +:8] = 'bX; + prev_prev_data[ii*8 +:8] = 'bX; + prev_char_is_align[ii] = 1'bX; + end + endcase + end + + if(IS_RX) begin : gen_rx + // RX + assign char_is_align[ii] = !reset && (rx_char_is_a[ii] | rx_char_is_f[ii]); + assign data_replaced[ii*8 +: 8] = char_is_align[ii] ? data_prev_eof[ii*8 +: 8] : data[ii*8 +: 8]; + assign data_prev_eof[ii*8 +: 8] = single_eof ? data_prev_eof_single : prev_char_is_align[ii] ? data_prev_prev_eof[ii*8 +: 8] : prev_data[ii*8 +: 8]; + assign data_prev_prev_eof[ii*8 +: 8] = prev_prev_data[ii*8 +: 8]; + end else begin : gen_tx + // TX + assign data_prev_eof[ii*8 +: 8] = single_eof ? data_prev_eof_single : prev_data[ii*8 +: 8]; + assign char_is_align[ii] = !reset && (tx_eomf[ii] || (eof[ii] && !(single_eof ? char_is_align_prev_single : prev_char_is_align[ii]))) && (data[ii*8 +: 8] == data_prev_eof[ii*8 +: 8]); + assign data_replaced[ii*8 +: 8] = char_is_align[ii] ? (tx_eomf[ii] ? 8'h7c : 8'hfc) : data[ii*8 +: 8]; + end + end + endgenerate + + assign data_out = (cfg_disable_char_replacement || !cfg_disable_scrambler || ENABLED==0) ? data : data_replaced; + assign charisk_out = (IS_RX || !cfg_disable_scrambler || cfg_disable_char_replacement || ENABLED==0) ? 'b0 : char_is_align; + +endmodule diff --git a/adi_library/jesd204/jesd204_common/jesd204_frame_mark.v b/adi_library/jesd204/jesd204_common/jesd204_frame_mark.v new file mode 100755 index 00000000..b6cee5e3 --- /dev/null +++ b/adi_library/jesd204/jesd204_common/jesd204_frame_mark.v @@ -0,0 +1,256 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2020-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +// Limitations: +// for DATA_PATH_WIDTH = 4, 8 +// F*K=4, multiples of DATA_PATH_WIDTH +// F=1,2,3,4,6, and multiples of DATA_PATH_WIDTH +// for DATA_PATH_WIDTH = 6 +// F=3,6 +// for DATA_PATH_WIDTH = 12 +// F=3,6,12 + +`timescale 1ns/100ps + +module jesd204_frame_mark #( + parameter DATA_PATH_WIDTH = 4 +) ( + input clk, + input reset, + input [9:0] cfg_octets_per_multiframe, + input [7:0] cfg_beats_per_multiframe, + input [7:0] cfg_octets_per_frame, + + output reg [DATA_PATH_WIDTH-1:0] sof, + output reg [DATA_PATH_WIDTH-1:0] eof, + output reg [DATA_PATH_WIDTH-1:0] somf, + output reg [DATA_PATH_WIDTH-1:0] eomf +); + + localparam MAX_OCTETS_PER_FRAME = 32; + localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1; + localparam CW = MAX_OCTETS_PER_FRAME > 128 ? 8 : + MAX_OCTETS_PER_FRAME > 64 ? 7 : + MAX_OCTETS_PER_FRAME > 32 ? 6 : + MAX_OCTETS_PER_FRAME > 16 ? 5 : + MAX_OCTETS_PER_FRAME > 8 ? 4 : + MAX_OCTETS_PER_FRAME > 4 ? 3 : + MAX_OCTETS_PER_FRAME > 2 ? 2 : 1; + localparam BEATS_PER_FRAME_WIDTH = CW-DPW_LOG2; + localparam BEATS_PER_MF_WIDTH = 10-DPW_LOG2; + + // For DATA_PATH_WIDTH = 8, special case if F*K%8=4 + wire octets_per_mf_4_mod_8 = (DATA_PATH_WIDTH == 8) && ~cfg_octets_per_multiframe[2]; + reg [BEATS_PER_MF_WIDTH-1:0] cur_beats_per_multiframe; + reg mf_phase; + reg [1:0] beat_cnt_mod_3; + reg [BEATS_PER_FRAME_WIDTH-1:0] beat_cnt_frame; + wire cur_sof; + wire cur_eof; + reg [BEATS_PER_MF_WIDTH-1:0] beat_cnt_mf; + wire cur_somf; + wire cur_eomf; + wire [DATA_PATH_WIDTH-1:0] default_sof; + wire [DATA_PATH_WIDTH-1:0] default_eof; + + wire [BEATS_PER_FRAME_WIDTH-1:0] cfg_beats_per_frame = cfg_octets_per_frame[CW-1:DPW_LOG2]; + reg [DATA_PATH_WIDTH-1:0] sof_f_3[2:0]; + reg [DATA_PATH_WIDTH-1:0] eof_f_3[2:0]; + reg [DATA_PATH_WIDTH-1:0] sof_f_6[2:0]; + reg [DATA_PATH_WIDTH-1:0] eof_f_6[2:0]; + reg [DATA_PATH_WIDTH-1:0] sof_f_12[2:0]; + reg [DATA_PATH_WIDTH-1:0] eof_f_12[2:0]; + + generate + if(DATA_PATH_WIDTH == 4) begin : gen_dp_4 + initial begin + sof_f_3[0] = {4'b1001}; + sof_f_3[1] = {4'b0100}; + sof_f_3[2] = {4'b0010}; + eof_f_3[0] = {4'b0100}; + eof_f_3[1] = {4'b0010}; + eof_f_3[2] = {4'b1001}; + sof_f_6[0] = {4'b0001}; + sof_f_6[1] = {4'b0100}; + sof_f_6[2] = {4'b0000}; + eof_f_6[0] = {4'b0000}; + eof_f_6[1] = {4'b0010}; + eof_f_6[2] = {4'b1000}; + end + end else if(DATA_PATH_WIDTH == 6) begin : gen_dp_6 + initial begin + sof_f_3[0] = {6'b001001}; + sof_f_3[1] = {6'b001001}; + sof_f_3[2] = {6'b001001}; + eof_f_3[0] = {6'b100100}; + eof_f_3[1] = {6'b100100}; + eof_f_3[2] = {6'b100100}; + sof_f_6[0] = {6'b000001}; + sof_f_6[1] = {6'b000001}; + sof_f_6[2] = {6'b000001}; + eof_f_6[0] = {6'b100000}; + eof_f_6[1] = {6'b100000}; + eof_f_6[2] = {6'b100000}; + end + end else if(DATA_PATH_WIDTH == 8) begin : gen_dp_8 + initial begin + sof_f_3[0] = {8'b01001001}; + sof_f_3[1] = {8'b10010010}; + sof_f_3[2] = {8'b00100100}; + eof_f_3[0] = {8'b00100100}; + eof_f_3[1] = {8'b01001001}; + eof_f_3[2] = {8'b10010010}; + sof_f_6[0] = {8'b01000001}; + sof_f_6[1] = {8'b00010000}; + sof_f_6[2] = {8'b00000100}; + eof_f_6[0] = {8'b00100000}; + eof_f_6[1] = {8'b00001000}; + eof_f_6[2] = {8'b10000010}; + sof_f_12[0] = {8'b00000001}; + sof_f_12[1] = {8'b00010000}; + sof_f_12[2] = {8'b00000000}; + eof_f_12[0] = {8'b00000000}; + eof_f_12[1] = {8'b00001000}; + eof_f_12[2] = {8'b10000000}; + end + end + // Beat count % 3, to support F=3, 6, 12 + always @(posedge clk) begin + if(reset) begin + beat_cnt_mod_3 <= 2'd0; + end else begin + if(beat_cnt_mod_3 == 2'd2) begin + beat_cnt_mod_3 <= 2'd0; + end else begin + beat_cnt_mod_3 <= beat_cnt_mod_3 + 1'b1; + end + end + end + + // Beat count per frame + always @(posedge clk) begin + if(reset) begin + beat_cnt_frame <= {BEATS_PER_FRAME_WIDTH{1'b0}}; + end else begin + if(beat_cnt_frame == cfg_beats_per_frame) begin + beat_cnt_frame <= {BEATS_PER_FRAME_WIDTH{1'b0}}; + end else begin + beat_cnt_frame <= beat_cnt_frame + 1'b1; + end + end + end + + assign cur_sof = beat_cnt_frame == 0; + assign cur_eof = beat_cnt_frame == cfg_beats_per_frame; + + assign default_sof = {{DATA_PATH_WIDTH-1{1'b0}}, cur_sof}; + assign default_eof = {cur_eof, {DATA_PATH_WIDTH-1{1'b0}}}; + + // cfg_octets_per_frame must be a multiple of DATA_PATH_WIDTH + // except for the following supported special cases + always @(*) begin + case(cfg_octets_per_frame) + 8'd0: + begin + sof = {DATA_PATH_WIDTH{1'b1}}; + eof = {DATA_PATH_WIDTH{1'b1}}; + end + 8'd1: + begin + sof = {DATA_PATH_WIDTH/2{2'b01}}; + eof = {DATA_PATH_WIDTH/2{2'b10}}; + end + 8'd2: + begin + sof = sof_f_3[beat_cnt_mod_3]; + eof = eof_f_3[beat_cnt_mod_3]; + end + 8'd3: + begin + sof = {DATA_PATH_WIDTH/4{4'b0001}}; + eof = {DATA_PATH_WIDTH/4{4'b1000}}; + end + 8'd5: + begin + sof = sof_f_6[beat_cnt_mod_3]; + eof = eof_f_6[beat_cnt_mod_3]; + end + 8'd11: + begin + sof = (DATA_PATH_WIDTH == 4) ? default_sof : sof_f_12[beat_cnt_mod_3]; + eof = (DATA_PATH_WIDTH == 4) ? default_eof : eof_f_12[beat_cnt_mod_3]; + end + default: + begin + sof = default_sof; + eof = default_eof; + end + endcase + end + + // Beat count per multiframe + // Only support F*K%4=0 + // If DATA_PATH_WIDTH == 4, or if DATA_PATH_WIDTH == 8 and F*K%8=0, + // then multiframes always start/end at the first/last octet in the data bus + // Otherwise, start/end of multiframe have more complicated patterns + always @(posedge clk) begin + if(reset) begin + beat_cnt_mf <= 8'b0; + mf_phase <= 1'b0; + end else begin + if(beat_cnt_mf == cur_beats_per_multiframe) begin + beat_cnt_mf <= 8'b0; + mf_phase <= ~mf_phase; + end else begin + beat_cnt_mf <= beat_cnt_mf + 1'b1; + end + end + end + + assign cur_somf = beat_cnt_mf == 0; + assign cur_eomf = beat_cnt_mf == cur_beats_per_multiframe; + + if(DATA_PATH_WIDTH == 4 || DATA_PATH_WIDTH == 6) begin : gen_mf_dp_4_6 + always @(*) begin + cur_beats_per_multiframe = cfg_beats_per_multiframe; + somf = {{DATA_PATH_WIDTH-1{1'b0}}, cur_somf}; + eomf = {cur_eomf, {DATA_PATH_WIDTH-1{1'b0}}}; + end + end else if(DATA_PATH_WIDTH == 8) begin : gen_mf_dp_8 + always @(*) begin + // cfg_octets_per_multiframe = 4 + if(cfg_octets_per_multiframe[9:2] == 0) begin + cur_beats_per_multiframe = 8'hXX; + somf = 8'h11; + eomf = 8'h88; + end else if(~octets_per_mf_4_mod_8) begin + cur_beats_per_multiframe = cfg_beats_per_multiframe; + somf = {{DATA_PATH_WIDTH-1{1'b0}}, cur_somf}; + eomf = {cur_eomf, {DATA_PATH_WIDTH-1{1'b0}}}; + end else begin + cur_beats_per_multiframe = cfg_beats_per_multiframe - mf_phase; + if((mf_phase == 0) && (beat_cnt_mf == 0)) begin + somf = 8'h01; + end else if((mf_phase == 0) && (beat_cnt_mf == cur_beats_per_multiframe)) begin + somf = 8'h10; + end else begin + somf = 8'b0; + end + + if((mf_phase == 0) && (beat_cnt_mf == cur_beats_per_multiframe)) begin + eomf = 8'h08; + end else if((mf_phase == 1) && (beat_cnt_mf == cur_beats_per_multiframe)) begin + eomf = 8'h80; + end else begin + eomf = 8'b0; + end + end + end + end + endgenerate + +endmodule diff --git a/adi_library/jesd204/jesd204_common/jesd204_lmfc.v b/adi_library/jesd204/jesd204_common/jesd204_lmfc.v new file mode 100755 index 00000000..1a6aee8f --- /dev/null +++ b/adi_library/jesd204/jesd204_common/jesd204_lmfc.v @@ -0,0 +1,202 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_lmfc #( + parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B + parameter DATA_PATH_WIDTH = 4 +) ( + input clk, + input reset, + + input sysref, + + input [9:0] cfg_octets_per_multiframe, + input [7:0] cfg_beats_per_multiframe, + input [7:0] cfg_lmfc_offset, + input cfg_sysref_oneshot, + input cfg_sysref_disable, + + output reg lmfc_edge, + output reg lmfc_clk, + output reg [7:0] lmfc_counter, + + // Local MultiBlock clock edge + output reg lmc_edge, + output reg lmc_quarter_edge, + // End of Extended MultiBlock + output reg eoemb, + + output reg sysref_edge, + output reg sysref_alignment_error +); + + localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1; + localparam BEATS_PER_MF_WIDTH = 10-DPW_LOG2; + + //wire [BEATS_PER_MF_WIDTH-1:0] cfg_beats_per_multiframe = cfg_octets_per_multiframe[9:DPW_LOG2]; + reg [BEATS_PER_MF_WIDTH:0] cfg_whole_beats_per_multiframe; + + reg sysref_r = 1'b0; + reg sysref_d1 = 1'b0; + reg sysref_d2 = 1'b0; + reg sysref_d3 = 1'b0; + + reg sysref_captured; + + /* lmfc_octet_counter = lmfc_counter * (char_clock_rate / device_clock_rate) */ + reg [7:0] lmfc_counter_next = 'h00; + + reg lmfc_clk_p1 = 1'b1; + + reg lmfc_active = 1'b0; + + always @(posedge clk) begin + sysref_r <= sysref; + end + + /* + * Unfortunately setup and hold are often ignored on the sysref signal relative + * to the device clock. The device will often still work fine, just not + * deterministic. Reduce the probability that the meta-stability creeps into the + * reset of the system and causes non-reproducible issues. + */ + always @(posedge clk) begin + sysref_d1 <= sysref_r; + sysref_d2 <= sysref_d1; + sysref_d3 <= sysref_d2; + end + + always @(posedge clk) begin + if (sysref_d3 == 1'b0 && sysref_d2 == 1'b1 && cfg_sysref_disable == 1'b0) begin + sysref_edge <= 1'b1; + end else begin + sysref_edge <= 1'b0; + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + sysref_captured <= 1'b0; + end else if (sysref_edge == 1'b1) begin + sysref_captured <= 1'b1; + end + end + + /* + * The configuration must be static when the core is out of reset. Otherwise + * undefined behaviour might occur. + * E.g. lmfc_counter > beats_per_multiframe + * + * To change the configuration first assert reset, then update the configuration + * setting, finally deassert reset. + */ + + /* + * For DATA_PATH_WIDTH == 8, F*K%8=4, set + * cfg_beats_per_multiframe = cfg_beats_per_multiframe*2 + * LMFC will be twice the actual length + */ + always @(*) begin + if((LINK_MODE == 1) && (DATA_PATH_WIDTH == 8) && ~cfg_octets_per_multiframe[2]) begin + cfg_whole_beats_per_multiframe = cfg_beats_per_multiframe*2; + end else begin + cfg_whole_beats_per_multiframe = cfg_beats_per_multiframe; + end + end + + always @(*) begin + if (lmfc_counter == cfg_whole_beats_per_multiframe) begin + lmfc_counter_next = 'h00; + end else begin + lmfc_counter_next = lmfc_counter + 1'b1; + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + lmfc_counter <= 'h01; + lmfc_active <= cfg_sysref_disable; + end else begin + /* + * In oneshot mode only the first occurence of the + * SYSREF signal is used for alignment. + */ + if (sysref_edge == 1'b1 && + (cfg_sysref_oneshot == 1'b0 || sysref_captured == 1'b0)) begin + lmfc_counter <= cfg_lmfc_offset; + lmfc_active <= 1'b1; + end else begin + lmfc_counter <= lmfc_counter_next; + end + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + sysref_alignment_error <= 1'b0; + end else begin + /* + * Alignement error is reported regardless of oneshot mode + * setting. + */ + sysref_alignment_error <= 1'b0; + if (sysref_edge == 1'b1 && lmfc_active == 1'b1 && + lmfc_counter_next != cfg_lmfc_offset) begin + sysref_alignment_error <= 1'b1; + end + end + end + + always @(posedge clk) begin + if (lmfc_counter == 'h00 && lmfc_active == 1'b1) begin + lmfc_edge <= 1'b1; + end else begin + lmfc_edge <= 1'b0; + end + end + + // 1 MultiBlock = 32 blocks + always @(posedge clk) begin + if (lmfc_counter[4:0] == 'h00 && lmfc_active == 1'b1) begin + lmc_edge <= 1'b1; + end else begin + lmc_edge <= 1'b0; + end + end + always @(posedge clk) begin + if (lmfc_counter[2:0] == 'h00 && lmfc_active == 1'b1) begin + lmc_quarter_edge <= 1'b1; + end else begin + lmc_quarter_edge <= 1'b0; + end + end + // End of Extended MultiBlock + always @(posedge clk) begin + if (lmfc_active == 1'b1) begin + eoemb <= lmfc_counter[7:5] == cfg_whole_beats_per_multiframe[7:5]; + end else begin + eoemb <= 1'b0; + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + lmfc_clk_p1 <= 1'b0; + end else if (lmfc_active == 1'b1) begin + if (lmfc_counter == cfg_whole_beats_per_multiframe) begin + lmfc_clk_p1 <= 1'b1; + end else if (lmfc_counter == cfg_whole_beats_per_multiframe[7:1]) begin + lmfc_clk_p1 <= 1'b0; + end + end + + lmfc_clk <= lmfc_clk_p1; + end + +endmodule diff --git a/adi_library/jesd204/jesd204_common/jesd204_scrambler.v b/adi_library/jesd204/jesd204_common/jesd204_scrambler.v new file mode 100644 index 00000000..681dd560 --- /dev/null +++ b/adi_library/jesd204/jesd204_common/jesd204_scrambler.v @@ -0,0 +1,56 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_scrambler #( + parameter WIDTH = 32, + parameter DESCRAMBLE = 0 +) ( + input clk, + input reset, + + input enable, + + input [WIDTH-1:0] data_in, + output [WIDTH-1:0] data_out +); + + reg [14:0] state = 'h7f80; + reg [WIDTH-1:0] swizzle_out; + wire [WIDTH-1:0] swizzle_in; + wire [WIDTH-1:0] feedback; + wire [WIDTH-1+15:0] full_state; + + generate + genvar i; + for (i = 0; i < WIDTH / 8; i = i + 1) begin: gen_swizzle + assign swizzle_in[WIDTH-1-i*8:WIDTH-i*8-8] = data_in[i*8+7:i*8]; + assign data_out[WIDTH-1-i*8:WIDTH-i*8-8] = swizzle_out[i*8+7:i*8]; + end + endgenerate + + assign full_state = {state,DESCRAMBLE ? swizzle_in : feedback}; + assign feedback = full_state[WIDTH-1+15:15] ^ full_state[WIDTH-1+14:14] ^ swizzle_in; + + always @(*) begin + if (enable == 1'b0) begin + swizzle_out = swizzle_in; + end else begin + swizzle_out = feedback; + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + state <= 'h7f80; + end else begin + state <= full_state[14:0]; + end + end + +endmodule diff --git a/adi_library/jesd204/jesd204_common/jesd204_scrambler_64b.v b/adi_library/jesd204/jesd204_common/jesd204_scrambler_64b.v new file mode 100644 index 00000000..7dbc8d49 --- /dev/null +++ b/adi_library/jesd204/jesd204_common/jesd204_scrambler_64b.v @@ -0,0 +1,46 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_scrambler_64b #( + parameter WIDTH = 64, + parameter DESCRAMBLE = 0 +) ( + input clk, + input reset, + + input enable, + + input [WIDTH-1:0] data_in, + output reg [WIDTH-1:0] data_out +); + + reg [57:0] state = {1'b1,57'b0}; + wire [WIDTH-1:0] feedback; + wire [WIDTH-1+58:0] full_state; + + assign full_state = {state,DESCRAMBLE ? data_in : feedback}; + assign feedback = full_state[WIDTH-1+58:58] ^ full_state[WIDTH-1:39] ^ data_in; + + always @(*) begin + if (enable == 1'b0) begin + data_out = data_in; + end else begin + data_out = feedback; + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + state <= {1'b1,57'b0}; + end else begin + state <= full_state[57:0] ^ {full_state[38:0],19'b0}; + end + end + +endmodule diff --git a/adi_library/jesd204/jesd204_common/pipeline_stage.v b/adi_library/jesd204/jesd204_common/pipeline_stage.v new file mode 100644 index 00000000..37108cf4 --- /dev/null +++ b/adi_library/jesd204/jesd204_common/pipeline_stage.v @@ -0,0 +1,27 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module pipeline_stage #( + parameter REGISTERED = 1, + parameter WIDTH = 1 +) ( + input clk, + input [WIDTH-1:0] in, + output [WIDTH-1:0] out +); + + generate if (REGISTERED == 0) begin + assign out = in; + end else begin + (* shreg_extract = "no" *) reg [REGISTERED*WIDTH-1:0] in_dly = {REGISTERED*WIDTH{1'b0}}; + always @(posedge clk) in_dly <= {in_dly,in}; + assign out = in_dly[REGISTERED*WIDTH-1 -: WIDTH]; + end endgenerate + +endmodule diff --git a/adi_library/jesd204/jesd204_common/sync_header_align.v b/adi_library/jesd204/jesd204_common/sync_header_align.v new file mode 100644 index 00000000..546ef4ce --- /dev/null +++ b/adi_library/jesd204/jesd204_common/sync_header_align.v @@ -0,0 +1,97 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module sync_header_align ( + input clk, + input reset, + + input [65:0] i_data, + output i_slip, + input i_slip_done, + + output [63:0] o_data, + output [1:0] o_header, + output o_block_sync +); + + assign {o_header,o_data} = i_data; + + // TODO : Add alignment FSM + localparam STATE_SH_HUNT = 3'b001; + localparam STATE_SH_SLIP = 3'b010; + localparam STATE_SH_LOCK = 3'b100; + + localparam BIT_SH_HUNT = 0; + localparam BIT_SH_SLIP = 1; + localparam BIT_SH_LOCK = 2; + + localparam RX_THRESH_SH_ERR = 16; + localparam LOG2_RX_THRESH_SH_ERR = $clog2(RX_THRESH_SH_ERR); + + reg [2:0] state = STATE_SH_HUNT; + reg [2:0] next_state; + + reg [7:0] header_vcnt = 8'h0; + reg [LOG2_RX_THRESH_SH_ERR:0] header_icnt = 'h0; + + wire valid_header; + assign valid_header = ^o_header; + + always @(posedge clk) begin + if (reset | ~valid_header) begin + header_vcnt <= 'b0; + end else if (state[BIT_SH_HUNT] & ~header_vcnt[7]) begin + header_vcnt <= header_vcnt + 'b1; + end + end + + always @(posedge clk) begin + if (reset | valid_header) begin + header_icnt <= 'b0; + end else if (state[BIT_SH_LOCK] & ~header_icnt[LOG2_RX_THRESH_SH_ERR]) begin + header_icnt <= header_icnt + 'b1; + end + end + + always @(*) begin + next_state = state; + case (state) + STATE_SH_HUNT: + if (valid_header) begin + if (header_vcnt[7]) begin + next_state = STATE_SH_LOCK; + end + end else begin + next_state = STATE_SH_SLIP; + end + STATE_SH_SLIP: + if (i_slip_done) begin + next_state = STATE_SH_HUNT; + end + STATE_SH_LOCK: + if (~valid_header) begin + if (header_icnt[LOG2_RX_THRESH_SH_ERR]) begin + next_state = STATE_SH_HUNT; + end + end + endcase + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + state <= STATE_SH_HUNT; + end else begin + state <= next_state; + end + end + + assign o_block_sync = state[BIT_SH_LOCK]; + assign i_slip = state[BIT_SH_SLIP]; + +endmodule diff --git a/adi_library/jesd204/jesd204_common/xgui/pipeline_stage_v1_0.tcl b/adi_library/jesd204/jesd204_common/xgui/pipeline_stage_v1_0.tcl new file mode 100644 index 00000000..a5103fce --- /dev/null +++ b/adi_library/jesd204/jesd204_common/xgui/pipeline_stage_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "REGISTERED" -parent ${Page_0} + ipgui::add_param $IPINST -name "WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.REGISTERED { PARAM_VALUE.REGISTERED } { + # Procedure called to update REGISTERED when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.REGISTERED { PARAM_VALUE.REGISTERED } { + # Procedure called to validate REGISTERED + return true +} + +proc update_PARAM_VALUE.WIDTH { PARAM_VALUE.WIDTH } { + # Procedure called to update WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.WIDTH { PARAM_VALUE.WIDTH } { + # Procedure called to validate WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.REGISTERED { MODELPARAM_VALUE.REGISTERED PARAM_VALUE.REGISTERED } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.REGISTERED}] ${MODELPARAM_VALUE.REGISTERED} +} + +proc update_MODELPARAM_VALUE.WIDTH { MODELPARAM_VALUE.WIDTH PARAM_VALUE.WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.WIDTH}] ${MODELPARAM_VALUE.WIDTH} +} + diff --git a/adi_library/jesd204/jesd204_rx/Makefile b/adi_library/jesd204/jesd204_rx/Makefile new file mode 100644 index 00000000..584c8e34 --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/Makefile @@ -0,0 +1,56 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := jesd204_rx + +GENERIC_DEPS += ../../common/ad_pack.v +GENERIC_DEPS += ../../common/ad_upack.v +GENERIC_DEPS += align_mux.v +GENERIC_DEPS += elastic_buffer.v +GENERIC_DEPS += jesd204_ilas_monitor.v +GENERIC_DEPS += jesd204_lane_latency_monitor.v +GENERIC_DEPS += jesd204_rx.v +GENERIC_DEPS += jesd204_rx_cgs.v +GENERIC_DEPS += jesd204_rx_ctrl.v +GENERIC_DEPS += jesd204_rx_frame_align.v +GENERIC_DEPS += jesd204_rx_lane.v + +XILINX_DEPS += bd/bd.tcl +XILINX_DEPS += error_monitor.v +XILINX_DEPS += jesd204_rx_constr.ttcl +XILINX_DEPS += jesd204_rx_ctrl_64b.v +XILINX_DEPS += jesd204_rx_header.v +XILINX_DEPS += jesd204_rx_ip.tcl +XILINX_DEPS += jesd204_rx_lane_64b.v +XILINX_DEPS += jesd204_rx_ooc.ttcl + +XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg_rtl.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_event.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_event_rtl.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_ilas_config_rtl.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_status.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_status_rtl.xml + +XILINX_LIB_DEPS += jesd204/jesd204_common +XILINX_LIB_DEPS += util_cdc + +XILINX_INTERFACE_DEPS += jesd204/interfaces + +INTEL_DEPS += ../../util_cdc/sync_bits.v +INTEL_DEPS += ../../util_cdc/sync_data.v +INTEL_DEPS += ../../util_cdc/sync_event.v +INTEL_DEPS += ../jesd204_common/jesd204_eof_generator.v +INTEL_DEPS += ../jesd204_common/jesd204_frame_align_replace.v +INTEL_DEPS += ../jesd204_common/jesd204_frame_mark.v +INTEL_DEPS += ../jesd204_common/jesd204_lmfc.v +INTEL_DEPS += ../jesd204_common/jesd204_scrambler.v +INTEL_DEPS += ../jesd204_common/pipeline_stage.v +INTEL_DEPS += jesd204_rx_constr.sdc +INTEL_DEPS += jesd204_rx_hw.tcl + +include ../../scripts/library.mk diff --git a/adi_library/jesd204/jesd204_rx/align_mux.v b/adi_library/jesd204/jesd204_rx/align_mux.v new file mode 100755 index 00000000..455d7a87 --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/align_mux.v @@ -0,0 +1,42 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module align_mux #( + parameter DATA_PATH_WIDTH = 4 +) ( + input clk, + input [2:0] align, + input [DATA_PATH_WIDTH*8-1:0] in_data, + input [DATA_PATH_WIDTH-1:0] in_charisk, + output [DATA_PATH_WIDTH*8-1:0] out_data, + output [DATA_PATH_WIDTH-1:0] out_charisk +); + + localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1; + + wire [DPW_LOG2-1:0] align_int; + reg [DATA_PATH_WIDTH*8-1:0] in_data_d1; + reg [DATA_PATH_WIDTH-1:0] in_charisk_d1; + wire [(DATA_PATH_WIDTH*8*2)-1:0] data; + wire [(DATA_PATH_WIDTH*2)-1:0] charisk; + + always @(posedge clk) begin + in_data_d1 <= in_data; + in_charisk_d1 <= in_charisk; + end + + assign data = {in_data, in_data_d1}; + assign charisk = {in_charisk, in_charisk_d1}; + + assign align_int = align[DPW_LOG2-1:0]; + + assign out_data = data[align_int*8 +: (DATA_PATH_WIDTH*8)]; + assign out_charisk = charisk[align_int +: DATA_PATH_WIDTH]; + +endmodule diff --git a/adi_library/jesd204/jesd204_rx/bd/bd.tcl b/adi_library/jesd204/jesd204_rx/bd/bd.tcl new file mode 100644 index 00000000..d8d7739a --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/bd/bd.tcl @@ -0,0 +1,49 @@ +############################################################################### +## Copyright (C) 2021 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_override $ip \ + "ASYNC_CLK" + +} + +proc detect_async_clk { cellpath ip param_name clk_a clk_b } { + set param_src [get_property "CONFIG.$param_name.VALUE_SRC" $ip] + if {[string equal $param_src "USER"]} { + return; + } + + set clk_domain_a [get_property CONFIG.CLK_DOMAIN $clk_a] + set clk_domain_b [get_property CONFIG.CLK_DOMAIN $clk_b] + set clk_freq_a [get_property CONFIG.FREQ_HZ $clk_a] + set clk_freq_b [get_property CONFIG.FREQ_HZ $clk_b] + set clk_phase_a [get_property CONFIG.PHASE $clk_a] + set clk_phase_b [get_property CONFIG.PHASE $clk_b] + + # Only mark it as sync if we can make sure that it is sync, if the + # relationship of the clocks is unknown mark it as async + if {$clk_domain_a != {} && $clk_domain_b != {} && \ + $clk_domain_a == $clk_domain_b && $clk_freq_a == $clk_freq_b && \ + $clk_phase_a == $clk_phase_b} { + set clk_async 0 + } else { + set clk_async 1 + } + + set_property "CONFIG.$param_name" $clk_async $ip + +} + +proc propagate {cellpath otherinfo} { + set ip [get_bd_cells $cellpath] + + set link_clk [get_bd_pins "$ip/clk"] + set device_clk [get_bd_pins "$ip/device_clk"] + + detect_async_clk $cellpath $ip "ASYNC_CLK" $link_clk $device_clk +} + diff --git a/adi_library/jesd204/jesd204_rx/component.xml b/adi_library/jesd204/jesd204_rx/component.xml new file mode 100644 index 00000000..95c69426 --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/component.xml @@ -0,0 +1,4589 @@ + + + analog.com + user + jesd204_rx + 1.0 + + + rx_phy0 + + + + + + + rxdata + + + phy_data + + 31 + 0 + + + + + + rxcharisk + + + phy_charisk + + 3 + 0 + + + + + + rxdisperr + + + phy_disperr + + 3 + 0 + + + + + + rxnotintable + + + phy_notintable + + 3 + 0 + + + + + + rxheader + + + phy_header + + 1 + 0 + + + + + + rxblock_sync + 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status_ctrl_state + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + status_lane_cgs_state + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + status_lane_ifs_ready + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + status_lane_latency + + out + + 13 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + status_lane_emb_state + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + status_lane_frame_align_err_cnt + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + status_synth_params0 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + status_synth_params1 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + status_synth_params2 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + NUM_LANES + Num Lanes + 1 + + + NUM_LINKS + Num Links + 1 + + + NUM_INPUT_PIPELINE + Num Input Pipeline + 1 + + + NUM_OUTPUT_PIPELINE + Num Output Pipeline + 1 + + + LINK_MODE + Link Mode + 1 + + + DATA_PATH_WIDTH + Data Path Width + 4 + + + ENABLE_FRAME_ALIGN_CHECK + Enable Frame Align Check + 1 + + + ENABLE_FRAME_ALIGN_ERR_RESET + Enable Frame Align Err Reset + 0 + + + ENABLE_CHAR_REPLACE + Enable Char Replace + 0 + + + ASYNC_CLK + Async Clk + 1 + + + TPL_DATA_PATH_WIDTH + Tpl Data Path Width + 4 + + + + + + choice_pairs_1942b210 + 2 + 1 + + + + + xilinx_anylanguagesynthesis_view_fileset + + jesd204_rx_ooc.ttcl + ttcl + + + jesd204_rx_constr.ttcl + ttcl + + + jesd204_rx_lane.v + verilogSource + + + jesd204_rx_lane_64b.v + verilogSource + + + jesd204_rx_header.v + verilogSource + + + jesd204_rx_cgs.v + verilogSource + + + jesd204_rx_ctrl.v + verilogSource + + + jesd204_rx_ctrl_64b.v + verilogSource + + + elastic_buffer.v + verilogSource + + + error_monitor.v + verilogSource + + + jesd204_ilas_monitor.v + verilogSource + + + align_mux.v + verilogSource + + + jesd204_lane_latency_monitor.v + verilogSource + + + jesd204_rx_frame_align.v + verilogSource + + + jesd204_rx.v + verilogSource + + + ../../common/ad_pack.v + verilogSource + + + bd/bd.tcl + tclSource + + + ../../common/ad_upack.v + verilogSource + CHECKSUM_b9097df1 + + + + xilinx_anylanguagesynthesis_analog_com_user_jesd204_common_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + jesd204_rx_lane.v + verilogSource + + + jesd204_rx_lane_64b.v + verilogSource + + + jesd204_rx_header.v + verilogSource + + + jesd204_rx_cgs.v + verilogSource + + + jesd204_rx_ctrl.v + verilogSource + + + jesd204_rx_ctrl_64b.v + verilogSource + + + elastic_buffer.v + verilogSource + + + error_monitor.v + verilogSource + + + jesd204_ilas_monitor.v + verilogSource + + + align_mux.v + verilogSource + + + jesd204_lane_latency_monitor.v + verilogSource + + + jesd204_rx_frame_align.v + verilogSource + + + jesd204_rx.v + verilogSource + + + ../../common/ad_pack.v + verilogSource + + + bd/bd.tcl + tclSource + + + ../../common/ad_upack.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_jesd204_common_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/jesd204_rx_v1_0.tcl + tclSource + CHECKSUM_8cf9565f + XGUI_VERSION_2 + + + + xilinx_xpgui_analog_com_user_jesd204_common_1_0__ref_view_fileset + + + + + + + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + xilinx_blockdiagram_analog_com_user_jesd204_common_1_0__ref_view_fileset + + + + + + + + xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + xilinx_utilityxitfiles_view_fileset + + gui/jesd204_rx_v1_0.gtcl + GTCL + + + + ADI JESD204 Receive + + + NUM_LANES + Num Lanes + 1 + + + NUM_LINKS + Num Links + 1 + + + NUM_INPUT_PIPELINE + Num Input Pipeline + 1 + + + NUM_OUTPUT_PIPELINE + Num Output Pipeline + 1 + + + LINK_MODE + Link Layer mode + 1 + + + DATA_PATH_WIDTH + Data Path Width + 4 + + + + true + + + + + + ENABLE_FRAME_ALIGN_CHECK + Enable Frame Align Check + 1 + + + ENABLE_FRAME_ALIGN_ERR_RESET + Enable Frame Align Err Reset + 0 + + + ENABLE_CHAR_REPLACE + Enable Char Replace + 0 + + + ASYNC_CLK + Link and Device Clock Asynchronous + 1 + + + TPL_DATA_PATH_WIDTH + Tpl Data Path Width + 4 + + + Component_Name + jesd204_rx_v1_0 + + + SYSREF_IOB + Place SYSREF in IOB + true + + + + + + virtex7 + + + /Analog_Devices + + ADI JESD204 Receive + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:51:40Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/jesd204/jesd204_rx/elastic_buffer.v b/adi_library/jesd204/jesd204_rx/elastic_buffer.v new file mode 100644 index 00000000..87ca4a5c --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/elastic_buffer.v @@ -0,0 +1,142 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module elastic_buffer #( + parameter IWIDTH = 32, + parameter OWIDTH = 48, + parameter SIZE = 256, + parameter ASYNC_CLK = 0 +) ( + input clk, + input reset, + + input device_clk, + input device_reset, + + input [IWIDTH-1:0] wr_data, + + output [OWIDTH-1:0] rd_data, + + input ready_n, + input do_release_n +); + + localparam ADDR_WIDTH = SIZE > 128 ? 7 : + SIZE > 64 ? 6 : + SIZE > 32 ? 5 : + SIZE > 16 ? 4 : + SIZE > 8 ? 3 : + SIZE > 4 ? 2 : + SIZE > 2 ? 1 : 0; + + localparam WIDTH = OWIDTH >= IWIDTH ? OWIDTH : IWIDTH; + + reg [ADDR_WIDTH:0] wr_addr = 'h00; + reg [ADDR_WIDTH:0] rd_addr = 'h00; + (* ram_style = "distributed" *) reg [WIDTH-1:0] mem[0:SIZE - 1]; + reg mem_rd_valid = 'b0; + reg [WIDTH-1:0] mem_rd_data; + + wire mem_wr; + wire [WIDTH-1:0] mem_wr_data; + wire unpacker_ready; + + generate if ((OWIDTH < IWIDTH) && ASYNC_CLK) begin + + assign mem_wr = 1'b1; + + always @(posedge clk) begin + if (ready_n) begin + wr_addr <= 'h00; + end else if (mem_wr) begin + wr_addr <= wr_addr + 1; + end + end + + always @(posedge clk) begin + if (mem_wr) begin + mem[wr_addr] <= wr_data; + end + end + + assign mem_rd_en = ~do_release_n & unpacker_ready; + + always @(posedge device_clk) begin + if (mem_rd_en) begin + mem_rd_data <= mem[rd_addr]; + end + mem_rd_valid <= mem_rd_en; + end + + always @(posedge device_clk) begin + if (do_release_n) begin + rd_addr <= 'b0; + end else if (mem_rd_en) begin + rd_addr <= rd_addr + 1; + end + end + + ad_upack #( + .I_W(IWIDTH/8), + .O_W(OWIDTH/8), + .UNIT_W(8), + .O_REG(0) + ) i_ad_upack ( + .clk(device_clk), + .reset(do_release_n), + .idata(mem_rd_data), + .ivalid(mem_rd_valid), + .iready(unpacker_ready), + + .odata(rd_data), + .ovalid()); + + end else begin + if ((OWIDTH > IWIDTH) && ASYNC_CLK) begin + ad_pack #( + .I_W(IWIDTH/8), + .O_W(OWIDTH/8), + .UNIT_W(8) + ) i_ad_pack ( + .clk(clk), + .reset(ready_n), + .idata(wr_data), + .ivalid(1'b1), + + .odata(mem_wr_data), + .ovalid(mem_wr)); + end else begin + assign mem_wr = 1'b1; + assign mem_wr_data = wr_data; + end + + always @(posedge clk) begin + if (ready_n == 1'b1) begin + wr_addr <= 'h00; + end else if (mem_wr) begin + mem[wr_addr] <= mem_wr_data; + wr_addr <= wr_addr + 1'b1; + end + end + + always @(posedge device_clk) begin + if (do_release_n == 1'b1) begin + rd_addr <= 'h00; + end else begin + rd_addr <= rd_addr + 1'b1; + mem_rd_data <= mem[rd_addr]; + end + end + + assign rd_data = mem_rd_data; + + end + endgenerate + +endmodule diff --git a/adi_library/jesd204/jesd204_rx/error_monitor.v b/adi_library/jesd204/jesd204_rx/error_monitor.v new file mode 100644 index 00000000..421206f4 --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/error_monitor.v @@ -0,0 +1,53 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module error_monitor #( + parameter EVENT_WIDTH = 16, + parameter CNT_WIDTH = 32 +) ( + input clk, + input reset, + input active, + input [EVENT_WIDTH-1:0] error_event, + input [EVENT_WIDTH-1:0] error_event_mask, + output reg [CNT_WIDTH-1:0] status_err_cnt = 'h0 +); + + localparam EVENT_WIDTH_LOG = $clog2(EVENT_WIDTH); + + reg [EVENT_WIDTH-1:0] err; + + function [EVENT_WIDTH_LOG-1:0] num_set_bits; + input [EVENT_WIDTH-1:0] x; + integer j; + begin + num_set_bits = 0; + for (j = 0; j < EVENT_WIDTH; j = j + 1) begin + num_set_bits = num_set_bits + x[j]; + end + end + endfunction + + always @(posedge clk) begin + if (active == 1'b1) begin + err <= (~error_event_mask) & error_event; + end else begin + err <= {EVENT_WIDTH{1'b0}}; + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + status_err_cnt <= 'h0; + end else if (~&status_err_cnt[CNT_WIDTH-1:EVENT_WIDTH_LOG]) begin + status_err_cnt <= status_err_cnt + num_set_bits(err); + end + end + +endmodule diff --git a/adi_library/jesd204/jesd204_rx/gui/jesd204_rx_v1_0.gtcl b/adi_library/jesd204/jesd204_rx/gui/jesd204_rx_v1_0.gtcl new file mode 100644 index 00000000..bb21c296 --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/gui/jesd204_rx_v1_0.gtcl @@ -0,0 +1,3 @@ +# This file is automatically written. Do not modify. +proc gen_USERPARAMETER_DATA_PATH_WIDTH_ENABLEMENT {LINK_MODE } {expr $LINK_MODE==1} +proc gen_USERPARAMETER_DATA_PATH_WIDTH_VALUE {LINK_MODE } {expr $LINK_MODE*4} diff --git a/adi_library/jesd204/jesd204_rx/jesd204_ilas_monitor.v b/adi_library/jesd204/jesd204_rx/jesd204_ilas_monitor.v new file mode 100755 index 00000000..8ecd9588 --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/jesd204_ilas_monitor.v @@ -0,0 +1,123 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_ilas_monitor #( + parameter DATA_PATH_WIDTH = 4 +) ( + input clk, + input reset, + + input [9:0] cfg_octets_per_multiframe, + input [DATA_PATH_WIDTH*8-1:0] data, + input [DATA_PATH_WIDTH-1:0] charisk28, + + output reg ilas_config_valid, + output reg [1:0] ilas_config_addr, + output reg [DATA_PATH_WIDTH*8-1:0] ilas_config_data, + + output data_ready_n +); + + localparam STATE_ILAS = 1'b1; + localparam STATE_DATA = 1'b0; + localparam ILAS_DATA_LENGTH = (DATA_PATH_WIDTH == 4) ? 4 : 2; + + wire octets_per_mf_4_mod_8 = (DATA_PATH_WIDTH == 8) && ~cfg_octets_per_multiframe[2]; + reg state = STATE_ILAS; + reg next_state; + reg prev_was_last = 1'b0; + wire ilas_config_start; + reg ilas_config_valid_i; + reg [1:0] ilas_config_addr_i; + reg [DATA_PATH_WIDTH*8-1:0] ilas_config_data_i; + + assign data_ready_n = next_state; + + always @(*) begin + next_state = state; + if (reset == 1'b0 && prev_was_last == 1'b1) begin + if (charisk28[0] != 1'b1 || data[7:5] != 3'h0) begin + next_state = STATE_DATA; + end + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + state <= STATE_ILAS; + end else begin + state <= next_state; + end + end + + always @(posedge clk) begin + if (reset == 1'b1 || (charisk28[DATA_PATH_WIDTH-1] == 1'b1 && data[(DATA_PATH_WIDTH*8)-1:(DATA_PATH_WIDTH*8)-3] == 3'h3)) begin + prev_was_last <= 1'b1; + end else begin + prev_was_last <= 1'b0; + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + ilas_config_valid_i <= 1'b0; + end else if (state == STATE_ILAS) begin + if (ilas_config_start) begin + ilas_config_valid_i <= 1'b1; + end else if (ilas_config_addr_i == (ILAS_DATA_LENGTH-1)) begin + ilas_config_valid_i <= 1'b0; + end + end + end + + always @(posedge clk) begin + if (ilas_config_valid_i == 1'b0) begin + ilas_config_addr_i <= 1'b0; + end else if (ilas_config_valid_i == 1'b1) begin + ilas_config_addr_i <= ilas_config_addr_i + 1'b1; + end + end + + always @(posedge clk) begin + ilas_config_data_i <= data; + end + + generate + if(DATA_PATH_WIDTH == 4) begin : gen_dp_4 + + assign ilas_config_start = charisk28[1] && (data[15:13] == 3'h4); + + always @(*) begin + ilas_config_valid = ilas_config_valid_i; + ilas_config_addr = ilas_config_addr_i; + ilas_config_data = ilas_config_data_i; + end + + end else begin : gen_dp_8 + + assign ilas_config_start = octets_per_mf_4_mod_8 ? + (charisk28[5] && (data[47:45] == 3'h4)) : + (charisk28[1] && (data[15:13] == 3'h4)); + + always @(posedge clk) begin + if (reset == 1'b1) begin + ilas_config_valid <= 1'b0; + end else begin + ilas_config_valid <= ilas_config_valid_i; + end + end + + always @(posedge clk) begin + ilas_config_addr <= ilas_config_addr_i; + ilas_config_data <= octets_per_mf_4_mod_8 ? {data[31:0], ilas_config_data_i[63:32]} : ilas_config_data_i; + end + end + endgenerate + +endmodule diff --git a/adi_library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v b/adi_library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v new file mode 100755 index 00000000..b7284074 --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v @@ -0,0 +1,59 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_lane_latency_monitor #( + parameter NUM_LANES = 1, + parameter DATA_PATH_WIDTH = 4 +) ( + input clk, + input reset, + + input [NUM_LANES-1:0] lane_ready, + input [NUM_LANES*3-1:0] lane_frame_align, + + output [14*NUM_LANES-1:0] lane_latency, + output [NUM_LANES-1:0] lane_latency_ready +); + + localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1; + localparam BEAT_CNT_WIDTH = 14-DPW_LOG2; + + reg [BEAT_CNT_WIDTH-1:0] beat_counter; + + reg [BEAT_CNT_WIDTH-1:0] lane_latency_mem[0:NUM_LANES-1]; + reg [NUM_LANES-1:0] lane_captured = 'h00; + + always @(posedge clk) begin + if (reset == 1'b1) begin + beat_counter <= 'h0; + end else if (beat_counter != {BEAT_CNT_WIDTH{1'b1}}) begin + beat_counter <= beat_counter + 1'b1; + end + end + + generate + genvar i; + + for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane + always @(posedge clk) begin + if (reset == 1'b1) begin + lane_latency_mem[i] <= 'h00; + lane_captured[i] <= 1'b0; + end else if (lane_ready[i] == 1'b1 && lane_captured[i] == 1'b0) begin + lane_latency_mem[i] <= beat_counter; + lane_captured[i] <= 1'b1; + end + end + + assign lane_latency[i*14+13:i*14] = {lane_latency_mem[i],lane_frame_align[(i*3)+DPW_LOG2-1:i*3]}; + assign lane_latency_ready[i] = lane_captured[i]; + end + endgenerate + +endmodule diff --git a/adi_library/jesd204/jesd204_rx/jesd204_rx.v b/adi_library/jesd204/jesd204_rx/jesd204_rx.v new file mode 100755 index 00000000..00602c5c --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/jesd204_rx.v @@ -0,0 +1,574 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_rx #( + parameter NUM_LANES = 1, + parameter NUM_LINKS = 1, + parameter NUM_INPUT_PIPELINE = 1, + parameter NUM_OUTPUT_PIPELINE = 1, + parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B + /* Only 4 is supported at the moment for 8b/10b and 8 for 64b */ + parameter DATA_PATH_WIDTH = LINK_MODE == 2 ? 8 : 4, + parameter ENABLE_FRAME_ALIGN_CHECK = 1, + parameter ENABLE_FRAME_ALIGN_ERR_RESET = 0, + parameter ENABLE_CHAR_REPLACE = 0, + parameter ASYNC_CLK = 1, + parameter TPL_DATA_PATH_WIDTH = LINK_MODE == 2 ? 8 : 4 +) ( + input clk, // Link clock, lane rate / 40 or lane rate / 20 or lane rate / 66 + input reset, + + input device_clk, // Integer multiple of frame clock + input device_reset, + + input [DATA_PATH_WIDTH*8*NUM_LANES-1:0] phy_data, + input [2*NUM_LANES-1:0] phy_header, + input [DATA_PATH_WIDTH*NUM_LANES-1:0] phy_charisk, + input [DATA_PATH_WIDTH*NUM_LANES-1:0] phy_notintable, + input [DATA_PATH_WIDTH*NUM_LANES-1:0] phy_disperr, + input [NUM_LANES-1:0] phy_block_sync, + + input sysref, + output lmfc_edge, + output lmfc_clk, + + output device_event_sysref_alignment_error, + output device_event_sysref_edge, + output event_frame_alignment_error, + output event_unexpected_lane_state_error, + + output [NUM_LINKS-1:0] sync, + + output phy_en_char_align, + + output [TPL_DATA_PATH_WIDTH*8*NUM_LANES-1:0] rx_data, + output rx_valid, + output [TPL_DATA_PATH_WIDTH-1:0] rx_eof, + output [TPL_DATA_PATH_WIDTH-1:0] rx_sof, + output [TPL_DATA_PATH_WIDTH-1:0] rx_eomf, + output [TPL_DATA_PATH_WIDTH-1:0] rx_somf, + + input [NUM_LANES-1:0] cfg_lanes_disable, + input [NUM_LINKS-1:0] cfg_links_disable, + input [9:0] cfg_octets_per_multiframe, + input [7:0] cfg_octets_per_frame, + input cfg_disable_scrambler, + input cfg_disable_char_replacement, + input [7:0] cfg_frame_align_err_threshold, + + input [9:0] device_cfg_octets_per_multiframe, + input [7:0] device_cfg_octets_per_frame, + input [7:0] device_cfg_beats_per_multiframe, + input [7:0] device_cfg_lmfc_offset, + input device_cfg_sysref_oneshot, + input device_cfg_sysref_disable, + input device_cfg_buffer_early_release, + input [7:0] device_cfg_buffer_delay, + + input ctrl_err_statistics_reset, + input [6:0] ctrl_err_statistics_mask, + + output [32*NUM_LANES-1:0] status_err_statistics_cnt, + + output [NUM_LANES-1:0] ilas_config_valid, + output [NUM_LANES*2-1:0] ilas_config_addr, + output [NUM_LANES*DATA_PATH_WIDTH*8-1:0] ilas_config_data, + + output [1:0] status_ctrl_state, + output [2*NUM_LANES-1:0] status_lane_cgs_state, + output [NUM_LANES-1:0] status_lane_ifs_ready, + output [14*NUM_LANES-1:0] status_lane_latency, + output [3*NUM_LANES-1:0] status_lane_emb_state, + output [8*NUM_LANES-1:0] status_lane_frame_align_err_cnt, + + output [31:0] status_synth_params0, + output [31:0] status_synth_params1, + output [31:0] status_synth_params2 +); + + /* + * Can be used to enable additional pipeline stages to ease timing. Usually not + * necessary. + */ + localparam CHAR_INFO_REGISTERED = 0; + localparam ALIGN_MUX_REGISTERED = 1; + localparam SCRAMBLER_REGISTERED = 0; + + /* + * Maximum number of octets per multiframe for ADI JESD204 DACs is 256 (Adjust + * as necessary). Divide by data path width. + */ + localparam MAX_OCTETS_PER_FRAME = 32; + localparam MAX_OCTETS_PER_MULTIFRAME = + (MAX_OCTETS_PER_FRAME * 32) > 1024 ? 1024 : (MAX_OCTETS_PER_FRAME * 32); + localparam MAX_BEATS_PER_MULTIFRAME = MAX_OCTETS_PER_MULTIFRAME / DATA_PATH_WIDTH; + localparam ELASTIC_BUFFER_SIZE = MAX_BEATS_PER_MULTIFRAME; + localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1; + + localparam LMFC_COUNTER_WIDTH = MAX_BEATS_PER_MULTIFRAME > 256 ? 9 : + MAX_BEATS_PER_MULTIFRAME > 128 ? 8 : + MAX_BEATS_PER_MULTIFRAME > 64 ? 7 : + MAX_BEATS_PER_MULTIFRAME > 32 ? 6 : + MAX_BEATS_PER_MULTIFRAME > 16 ? 5 : + MAX_BEATS_PER_MULTIFRAME > 8 ? 4 : + MAX_BEATS_PER_MULTIFRAME > 4 ? 3 : + MAX_BEATS_PER_MULTIFRAME > 2 ? 2 : 1; + + /* Helper for common expressions */ + localparam DW = 8*DATA_PATH_WIDTH*NUM_LANES; + localparam ODW = 8*TPL_DATA_PATH_WIDTH*NUM_LANES; + localparam CW = DATA_PATH_WIDTH*NUM_LANES; + localparam HW = 2*NUM_LANES; + + wire [7:0] cfg_beats_per_multiframe = cfg_octets_per_multiframe >> DPW_LOG2; + wire [7:0] device_cfg_beats_per_multiframe_s; + + wire [NUM_LANES-1:0] cgs_reset; + wire [NUM_LANES-1:0] cgs_ready; + wire [NUM_LANES-1:0] ifs_reset; + + reg buffer_release_n = 1'b1; + reg buffer_release_d1 = 1'b0; + wire [NUM_LANES-1:0] buffer_ready_n; + wire all_buffer_ready_n; + wire dev_all_buffer_ready_n; + + reg eof_reset = 1'b1; + + wire [DW-1:0] phy_data_r; + wire [HW-1:0] phy_header_r; + wire [CW-1:0] phy_charisk_r; + wire [CW-1:0] phy_notintable_r; + wire [CW-1:0] phy_disperr_r; + wire [NUM_LANES-1:0] phy_block_sync_r; + + wire [ODW-1:0] rx_data_s; + + wire rx_valid_s = buffer_release_d1; + + wire [7:0] lmfc_counter; + wire latency_monitor_reset; + + wire [3*NUM_LANES-1:0] frame_align; + wire [NUM_LANES-1:0] ifs_ready; + + wire event_data_phase; + wire err_statistics_reset; + + wire lmfc_edge_synced; + + reg [NUM_LANES-1:0] frame_align_err_thresh_met = {NUM_LANES{1'b0}}; + reg [NUM_LANES-1:0] event_frame_alignment_error_per_lane = {NUM_LANES{1'b0}}; + + reg buffer_release_opportunity = 1'b0; + + always @(posedge device_clk) begin + if (lmfc_counter == device_cfg_buffer_delay || + device_cfg_buffer_early_release == 1'b1) begin + buffer_release_opportunity <= 1'b1; + end else begin + buffer_release_opportunity <= 1'b0; + end + end + + assign all_buffer_ready_n = |(buffer_ready_n & ~cfg_lanes_disable); + + sync_bits #( + .NUM_OF_BITS (1), + .ASYNC_CLK(ASYNC_CLK) + ) i_all_buffer_ready_cdc ( + .in_bits(all_buffer_ready_n), + .out_clk(device_clk), + .out_resetn(1'b1), + .out_bits(dev_all_buffer_ready_n)); + + always @(posedge device_clk) begin + if (device_reset == 1'b1) begin + buffer_release_n <= 1'b1; + end else begin + if (buffer_release_opportunity == 1'b1) begin + buffer_release_n <= dev_all_buffer_ready_n; + end + end + buffer_release_d1 <= ~buffer_release_n; + eof_reset <= buffer_release_n; + end + + pipeline_stage #( + .WIDTH(NUM_LANES + (3 * CW) + HW + DW), + .REGISTERED(NUM_INPUT_PIPELINE) + ) i_input_pipeline_stage ( + .clk(clk), + .in({ + phy_data, + phy_header, + phy_charisk, + phy_notintable, + phy_disperr, + phy_block_sync + }), + .out({ + phy_data_r, + phy_header_r, + phy_charisk_r, + phy_notintable_r, + phy_disperr_r, + phy_block_sync_r + })); + + pipeline_stage #( + .WIDTH(ODW+2), + .REGISTERED(NUM_OUTPUT_PIPELINE) + ) i_output_pipeline_stage ( + .clk(device_clk), + .in({ + eof_reset, + rx_data_s, + rx_valid_s + }), + .out({ + eof_reset_d, + rx_data, + rx_valid + })); + + // If input and output widths are symmetric keep the calculation for backwards + // compatibility of the software. + assign device_cfg_beats_per_multiframe_s = (TPL_DATA_PATH_WIDTH == DATA_PATH_WIDTH) ? + device_cfg_octets_per_multiframe >> DPW_LOG2 : + device_cfg_beats_per_multiframe; + + jesd204_lmfc #( + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (TPL_DATA_PATH_WIDTH) + ) i_lmfc ( + .clk (device_clk), + .reset (device_reset), + + .cfg_octets_per_multiframe (device_cfg_octets_per_multiframe), + .cfg_beats_per_multiframe (device_cfg_beats_per_multiframe_s), + .cfg_lmfc_offset (device_cfg_lmfc_offset), + .cfg_sysref_oneshot (device_cfg_sysref_oneshot), + .cfg_sysref_disable (device_cfg_sysref_disable), + + .sysref (sysref), + .lmfc_edge (lmfc_edge), + .lmfc_clk (lmfc_clk), + .lmfc_counter (lmfc_counter), + .lmc_edge (), + .lmc_quarter_edge (), + .eoemb (), + + .sysref_edge (device_event_sysref_edge), + .sysref_alignment_error (device_event_sysref_alignment_error)); + + jesd204_frame_mark #( + .DATA_PATH_WIDTH (TPL_DATA_PATH_WIDTH) + ) i_frame_mark ( + .clk (device_clk), + .reset (eof_reset_d), + .cfg_beats_per_multiframe (device_cfg_beats_per_multiframe_s), + .cfg_octets_per_multiframe (device_cfg_octets_per_multiframe), + .cfg_octets_per_frame (device_cfg_octets_per_frame), + .sof (rx_sof), + .eof (rx_eof), + .somf (rx_somf), + .eomf (rx_eomf)); + + generate + genvar i; + + sync_event #( + .NUM_OF_EVENTS (1), + .ASYNC_CLK(ASYNC_CLK) + ) i_sync_lmfc ( + .in_clk(device_clk), + .in_event(lmfc_edge), + .out_clk(clk), + .out_event(lmfc_edge_synced)); + + if (LINK_MODE[0] == 1) begin : mode_8b10b + + wire unexpected_lane_state_error; + reg unexpected_lane_state_error_d = 1'b0; + + jesd204_rx_ctrl #( + .NUM_LANES (NUM_LANES), + .NUM_LINKS (NUM_LINKS), + .ENABLE_FRAME_ALIGN_ERR_RESET (ENABLE_FRAME_ALIGN_ERR_RESET) + ) i_rx_ctrl ( + .clk (clk), + .reset (reset), + + .cfg_lanes_disable (cfg_lanes_disable), + .cfg_links_disable (cfg_links_disable), + + .phy_ready (1'b1), + .phy_en_char_align (phy_en_char_align), + + .lmfc_edge (lmfc_edge_synced), + .frame_align_err_thresh_met (frame_align_err_thresh_met), + .sync (sync), + + .latency_monitor_reset (latency_monitor_reset), + + .cgs_reset (cgs_reset), + .cgs_ready (cgs_ready), + + .ifs_reset (ifs_reset), + + .status_state (status_ctrl_state), + + .event_data_phase (event_data_phase)); + + assign err_statistics_reset = ctrl_err_statistics_reset || + event_data_phase; + + for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane + + localparam D_START = i * DATA_PATH_WIDTH*8; + localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1; + localparam OD_START = i * TPL_DATA_PATH_WIDTH*8; + localparam OD_STOP = OD_START + TPL_DATA_PATH_WIDTH*8-1; + localparam C_START = i * DATA_PATH_WIDTH; + localparam C_STOP = C_START + DATA_PATH_WIDTH-1; + + jesd204_rx_lane #( + .DATA_PATH_WIDTH(DATA_PATH_WIDTH), + .TPL_DATA_PATH_WIDTH(TPL_DATA_PATH_WIDTH), + .CHAR_INFO_REGISTERED(CHAR_INFO_REGISTERED), + .ALIGN_MUX_REGISTERED(ALIGN_MUX_REGISTERED), + .SCRAMBLER_REGISTERED(SCRAMBLER_REGISTERED), + .ELASTIC_BUFFER_SIZE(ELASTIC_BUFFER_SIZE), + .ENABLE_FRAME_ALIGN_CHECK(ENABLE_FRAME_ALIGN_CHECK), + .ENABLE_CHAR_REPLACE(ENABLE_CHAR_REPLACE), + .ASYNC_CLK(ASYNC_CLK) + ) i_lane ( + .clk(clk), + .reset(reset), + + .device_clk(device_clk), + .device_reset(device_reset), + + .phy_data(phy_data_r[D_STOP:D_START]), + .phy_charisk(phy_charisk_r[C_STOP:C_START]), + .phy_notintable(phy_notintable_r[C_STOP:C_START]), + .phy_disperr(phy_disperr_r[C_STOP:C_START]), + + .cgs_reset(cgs_reset[i]), + .cgs_ready(cgs_ready[i]), + + .ifs_reset(ifs_reset[i]), + + .rx_data(rx_data_s[OD_STOP:OD_START]), + + .buffer_release_n(buffer_release_n), + .buffer_ready_n(buffer_ready_n[i]), + + .cfg_octets_per_multiframe(cfg_octets_per_multiframe), + .cfg_octets_per_frame(cfg_octets_per_frame), + .cfg_disable_char_replacement(cfg_disable_char_replacement), + .cfg_disable_scrambler(cfg_disable_scrambler), + + .err_statistics_reset(err_statistics_reset), + .ctrl_err_statistics_mask(ctrl_err_statistics_mask[2:0]), + .status_err_statistics_cnt(status_err_statistics_cnt[32*i+31:32*i]), + + .ilas_config_valid(ilas_config_valid[i]), + .ilas_config_addr(ilas_config_addr[2*i+1:2*i]), + .ilas_config_data(ilas_config_data[D_STOP:D_START]), + + .status_cgs_state(status_lane_cgs_state[2*i+1:2*i]), + .status_ifs_ready(ifs_ready[i]), + .status_frame_align(frame_align[3*i+2:3*i]), + + .status_frame_align_err_cnt(status_lane_frame_align_err_cnt[8*i+7:8*i])); + + if(ENABLE_FRAME_ALIGN_CHECK) begin : gen_frame_align_err_thresh + always @(posedge clk) begin + if (reset) begin + frame_align_err_thresh_met[i] <= 1'b0; + event_frame_alignment_error_per_lane[i] <= 1'b0; + end else begin + if (status_lane_frame_align_err_cnt[8*i+7:8*i] >= cfg_frame_align_err_threshold) begin + frame_align_err_thresh_met[i] <= cgs_ready[i]; + event_frame_alignment_error_per_lane[i] <= ~frame_align_err_thresh_met[i]; + end else begin + frame_align_err_thresh_met[i] <= 1'b0; + event_frame_alignment_error_per_lane[i] <= 1'b0; + end + end + end + end else begin : gen_no_frame_align_err_thresh + always @(*) begin + frame_align_err_thresh_met[i] <= 1'b0; + event_frame_alignment_error_per_lane[i] <= 1'b0; + end + end + end + + assign event_frame_alignment_error = |event_frame_alignment_error_per_lane; + + /* If one of the enabled lanes falls out of DATA phase while the link is in DATA phase + * report an error event */ + assign unexpected_lane_state_error = |(~(cgs_ready|cfg_lanes_disable)) & &status_ctrl_state; + always @(posedge clk) begin + unexpected_lane_state_error_d <= unexpected_lane_state_error; + end + assign event_unexpected_lane_state_error = unexpected_lane_state_error & ~unexpected_lane_state_error_d; + + /* Delay matching based on the number of pipeline stages */ + reg [NUM_LANES-1:0] ifs_ready_d1 = 1'b0; + reg [NUM_LANES-1:0] ifs_ready_d2 = 1'b0; + reg [NUM_LANES-1:0] ifs_ready_mux; + + always @(posedge clk) begin + ifs_ready_d1 <= ifs_ready; + ifs_ready_d2 <= ifs_ready_d1; + end + + always @(*) begin + case (SCRAMBLER_REGISTERED + ALIGN_MUX_REGISTERED) + 1: ifs_ready_mux = ifs_ready_d1; + 2: ifs_ready_mux = ifs_ready_d2; + default: ifs_ready_mux = ifs_ready; + endcase + end + + jesd204_lane_latency_monitor #( + .NUM_LANES(NUM_LANES), + .DATA_PATH_WIDTH(DATA_PATH_WIDTH) + ) i_lane_latency_monitor ( + .clk(clk), + .reset(latency_monitor_reset), + + .lane_ready(ifs_ready_mux), + .lane_frame_align(frame_align), + .lane_latency_ready(status_lane_ifs_ready), + .lane_latency(status_lane_latency)); + + assign status_lane_emb_state = 'b0; + + end + + if (LINK_MODE[1] == 1) begin : mode_64b66b + + wire [NUM_LANES-1:0] emb_lock; + wire link_buffer_release_n; + + sync_bits #( + .NUM_OF_BITS (1), + .ASYNC_CLK(ASYNC_CLK) + ) i_buffer_release_cdc ( + .in_bits(buffer_release_n), + .out_clk(clk), + .out_resetn(1'b1), + .out_bits(link_buffer_release_n)); + + jesd204_rx_ctrl_64b #( + .NUM_LANES(NUM_LANES) + ) i_jesd204_rx_ctrl_64b ( + .clk(clk), + .reset(reset), + + .cfg_lanes_disable(cfg_lanes_disable), + + .phy_block_sync(phy_block_sync_r), + .emb_lock(emb_lock), + + .all_emb_lock(all_emb_lock), + .buffer_release_n(link_buffer_release_n), + + .status_state(status_ctrl_state), + .event_unexpected_lane_state_error(event_unexpected_lane_state_error)); + + for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane + + localparam D_START = i * DATA_PATH_WIDTH*8; + localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1; + localparam TPL_D_START = i * TPL_DATA_PATH_WIDTH*8; + localparam TPL_D_STOP = TPL_D_START + TPL_DATA_PATH_WIDTH*8-1; + localparam H_START = i * 2; + localparam H_STOP = H_START + 2-1; + + wire [7:0] status_lane_skew; + + jesd204_rx_lane_64b #( + .ELASTIC_BUFFER_SIZE(ELASTIC_BUFFER_SIZE), + .TPL_DATA_PATH_WIDTH(TPL_DATA_PATH_WIDTH), + .ASYNC_CLK(ASYNC_CLK) + ) i_lane ( + .clk(clk), + .reset(reset), + + .device_clk(device_clk), + .device_reset(device_reset), + + .phy_data(phy_data_r[D_STOP:D_START]), + .phy_header(phy_header_r[H_STOP:H_START]), + .phy_block_sync(phy_block_sync_r[i]), + + .cfg_disable_scrambler(cfg_disable_scrambler), + .cfg_header_mode(2'b0), + .cfg_rx_thresh_emb_err(5'd8), + .cfg_beats_per_multiframe(cfg_beats_per_multiframe), + + .rx_data(rx_data_s[TPL_D_STOP:TPL_D_START]), + + .buffer_release_n(buffer_release_n), + .buffer_ready_n(buffer_ready_n[i]), + .all_buffer_ready_n(all_buffer_ready_n), + + .lmfc_edge(lmfc_edge_synced), + .emb_lock(emb_lock[i]), + + .ctrl_err_statistics_reset(ctrl_err_statistics_reset), + .ctrl_err_statistics_mask(ctrl_err_statistics_mask[6:3]), + .status_err_statistics_cnt(status_err_statistics_cnt[32*i+31:32*i]), + + .status_lane_emb_state(status_lane_emb_state[3*i+2:3*i]), + .status_lane_skew(status_lane_skew)); + + assign status_lane_latency[14*(i+1)-1:14*i] = {3'b0,status_lane_skew,3'b0}; + + end + + // Assign unused outputs + assign sync = 'b0; + assign phy_en_char_align = 1'b0; + + assign ilas_config_valid ='b0; + assign ilas_config_addr = 'b0; + assign ilas_config_data = 'b0; + assign status_lane_cgs_state = 'b0; + assign status_lane_ifs_ready = {NUM_LANES{1'b1}}; + assign event_frame_alignment_error = 1'b0; + + end + + endgenerate + + // Core static parameters + assign status_synth_params0 = {NUM_LANES}; + assign status_synth_params1 = { + /*31:16 */ 16'b0, + /*15: 8 */ 1'b0,TPL_DATA_PATH_WIDTH[6:0], + /* 7: 0 */ 4'b0,DPW_LOG2[3:0]}; + assign status_synth_params2 = { + /*31:19 */ 13'b0, + /* 18 */ ENABLE_CHAR_REPLACE[0], + /* 17 */ ENABLE_FRAME_ALIGN_ERR_RESET[0], + /* 16 */ ENABLE_FRAME_ALIGN_CHECK[0], + /*15:13 */ 3'b0, + /* 12 */ ASYNC_CLK[0], + /*11:10 */ 2'b0, + /* 9: 8 */ LINK_MODE[1:0], + /* 7: 0 */ NUM_LINKS[7:0]}; + +endmodule diff --git a/adi_library/jesd204/jesd204_rx/jesd204_rx.xpr b/adi_library/jesd204/jesd204_rx/jesd204_rx.xpr new file mode 100644 index 00000000..13c9a2ed --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/jesd204_rx.xpr @@ -0,0 +1,507 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/jesd204/jesd204_rx/jesd204_rx_cgs.v b/adi_library/jesd204/jesd204_rx/jesd204_rx_cgs.v new file mode 100644 index 00000000..ee88ce6c --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/jesd204_rx_cgs.v @@ -0,0 +1,88 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_rx_cgs #( + parameter DATA_PATH_WIDTH = 4 +) ( + input clk, + input reset, + + input [DATA_PATH_WIDTH-1:0] char_is_cgs, + input [DATA_PATH_WIDTH-1:0] char_is_error, + + output ready, + + output [1:0] status_state +); + + localparam CGS_STATE_INIT = 2'b00; + localparam CGS_STATE_CHECK = 2'b01; + localparam CGS_STATE_DATA = 2'b10; + + reg [1:0] state = CGS_STATE_INIT; + reg rdy = 1'b0; + reg [1:0] beat_error_count = 'h00; + + wire beat_is_cgs = &char_is_cgs; + wire beat_has_error = |char_is_error; + wire beat_is_all_error = &char_is_error; + + assign ready = rdy; + assign status_state = state; + + always @(posedge clk) begin + if (state == CGS_STATE_INIT) begin + beat_error_count <= 'h00; + end else begin + if (beat_has_error == 1'b1) begin + beat_error_count <= beat_error_count + 1'b1; + end else begin + beat_error_count <= 'h00; + end + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + state <= CGS_STATE_INIT; + end else begin + case (state) + CGS_STATE_INIT: begin + if (beat_is_cgs == 1'b1) begin + state <= CGS_STATE_CHECK; + end + end + CGS_STATE_CHECK: begin + if (beat_has_error == 1'b1) begin + if (beat_error_count == 'h3 || + beat_is_all_error == 1'b1) begin + state <= CGS_STATE_INIT; + end + end else begin + state <= CGS_STATE_DATA; + end + end + CGS_STATE_DATA: begin + if (beat_has_error == 1'b1) begin + state <= CGS_STATE_CHECK; + end + end + endcase + end + end + + always @(posedge clk) begin + case (state) + CGS_STATE_INIT: rdy <= 1'b0; + CGS_STATE_DATA: rdy <= 1'b1; + default: rdy <= rdy; + endcase + end + +endmodule diff --git a/adi_library/jesd204/jesd204_rx/jesd204_rx_constr.sdc b/adi_library/jesd204/jesd204_rx/jesd204_rx_constr.sdc new file mode 100644 index 00000000..14c4731b --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/jesd204_rx_constr.sdc @@ -0,0 +1,15 @@ +############################################################################### +## Copyright (C) 2017, 2020, 2021 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +set script_dir [file dirname [info script]] + +source "$script_dir/util_cdc_constr.tcl" + +# SYNC~ is a asynchronous interface +set_false_path \ + -from [get_registers *|jesd204_rx_ctrl:i_rx_ctrl|sync_n[0]] + +util_cdc_sync_bits_constr {*|sync_bits:i_all_buffer_ready_cdc} +util_cdc_sync_event_constr {*|sync_event:i_sync_lmfc} diff --git a/adi_library/jesd204/jesd204_rx/jesd204_rx_constr.ttcl b/adi_library/jesd204/jesd204_rx/jesd204_rx_constr.ttcl new file mode 100644 index 00000000..00c39fda --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/jesd204_rx_constr.ttcl @@ -0,0 +1,93 @@ +############################################################################### +## Copyright (C) 2017, 2018, 2021 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName [ttcl_add $ComponentName "_constr"] :> +<: setFileExtension ".xdc" :> +<: setFileProcessingOrder late :> +<: set sysref_iob [get_property PARAM_VALUE.SYSREF_IOB] :> +<: set async_clk [getBooleanValue "ASYNC_CLK"] :> +<: set link_mode [getBooleanValue "LINK_MODE"] :> + +set_property ASYNC_REG TRUE \ + [get_cells {i_lmfc/sysref_d1_reg}] \ + [get_cells {i_lmfc/sysref_d2_reg}] + +# Make sure that the device clock to sysref skew is at least somewhat +# predictable +set_property IOB <=: $sysref_iob :> \ + [get_cells {i_lmfc/sysref_r_reg}] + +<: if {$async_clk} { :> + +set link_clk [get_clocks -of_objects [get_ports -quiet {clk}]] +set device_clk [get_clocks -of_objects [get_ports -quiet {device_clk}]] + +# sync bits +set_false_path \ + -from $link_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_all_buffer_ready_cdc* && IS_SEQUENTIAL}] + +set_property ASYNC_REG TRUE \ + [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_all_buffer_ready_cdc* && IS_SEQUENTIAL}] + +set_property ASYNC_REG TRUE \ + [get_cells -quiet -hier *cdc_sync_stage2_reg* \ + -filter {NAME =~ *i_all_buffer_ready_cdc* && IS_SEQUENTIAL}] + +# sync event i_sync_lmfc +set_false_path -quiet \ + -from $device_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_lmfc/i_sync_out* && IS_SEQUENTIAL}] + +set_property ASYNC_REG TRUE \ + [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_lmfc/i_sync_out* && IS_SEQUENTIAL}] + +set_property ASYNC_REG TRUE \ + [get_cells -quiet -hier *cdc_sync_stage2_reg* \ + -filter {NAME =~ *i_sync_lmfc/i_sync_out* && IS_SEQUENTIAL}] + +set_false_path -quiet \ + -from $link_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_lmfc/i_sync_in* && IS_SEQUENTIAL}] + +set_property ASYNC_REG TRUE \ + [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_lmfc/i_sync_in* && IS_SEQUENTIAL}] + +set_property ASYNC_REG TRUE \ + [get_cells -quiet -hier *cdc_sync_stage2_reg* \ + -filter {NAME =~ *i_sync_lmfc/i_sync_in* && IS_SEQUENTIAL}] + +# elastic buffer distributed RAM +set_false_path -quiet \ + -from $link_clk \ + -to [get_cells -quiet -hier *rd_data_reg* \ + -filter {NAME =~ *i_elastic_buffer* && IS_SEQUENTIAL}] + +<: if {$link_mode == 2} { :> +# sync bits i_buffer_release_cdc 64b66b +set_false_path \ + -from $device_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_buffer_release_cdc* && IS_SEQUENTIAL}] + +set_property ASYNC_REG TRUE \ + [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_buffer_release_cdc* && IS_SEQUENTIAL}] + +set_property ASYNC_REG TRUE \ + [get_cells -quiet -hier *cdc_sync_stage2_reg* \ + -filter {NAME =~ *i_buffer_release_cdc* && IS_SEQUENTIAL}] +<: } :> + +<: } :> + diff --git a/adi_library/jesd204/jesd204_rx/jesd204_rx_ctrl.v b/adi_library/jesd204/jesd204_rx/jesd204_rx_ctrl.v new file mode 100755 index 00000000..a032b92a --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/jesd204_rx_ctrl.v @@ -0,0 +1,149 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_rx_ctrl #( + parameter NUM_LANES = 1, + parameter NUM_LINKS = 1, + parameter ENABLE_FRAME_ALIGN_ERR_RESET = 0 +) ( + input clk, + input reset, + + input [NUM_LANES-1:0] cfg_lanes_disable, + input [NUM_LINKS-1:0] cfg_links_disable, + + input phy_ready, + output phy_en_char_align, + + output [NUM_LANES-1:0] cgs_reset, + input [NUM_LANES-1:0] cgs_ready, + + output [NUM_LANES-1:0] ifs_reset, + + input lmfc_edge, + input [NUM_LANES-1:0] frame_align_err_thresh_met, + + output [NUM_LINKS-1:0] sync, + output reg latency_monitor_reset, + + output [1:0] status_state, + output event_data_phase +); + + localparam STATE_RESET = 0; + localparam STATE_WAIT_FOR_PHY = 1; + localparam STATE_CGS = 2; + localparam STATE_SYNCHRONIZED = 3; + + reg [2:0] state = STATE_RESET; + reg [2:0] next_state = STATE_RESET; + + reg [NUM_LANES-1:0] cgs_rst = {NUM_LANES{1'b1}}; + reg [NUM_LANES-1:0] ifs_rst = {NUM_LANES{1'b1}}; + reg [NUM_LINKS-1:0] sync_n = {NUM_LINKS{1'b1}}; + reg en_align = 1'b0; + reg state_good = 1'b0; + + reg [7:0] good_counter = 'h00; + + wire [7:0] good_cnt_limit_s; + wire good_cnt_limit_reached_s; + wire goto_next_state_s; + + assign cgs_reset = cgs_rst; + assign ifs_reset = ifs_rst; + assign sync = sync_n; + assign phy_en_char_align = en_align; + + assign status_state = state; + + always @(posedge clk) begin + case (state) + STATE_RESET: begin + cgs_rst <= {NUM_LANES{1'b1}}; + ifs_rst <= {NUM_LANES{1'b1}}; + sync_n <= {NUM_LINKS{1'b1}}; + latency_monitor_reset <= 1'b1; + end + STATE_CGS: begin + sync_n <= cfg_links_disable; + cgs_rst <= cfg_lanes_disable; + end + STATE_SYNCHRONIZED: begin + if (lmfc_edge == 1'b1) begin + sync_n <= {NUM_LINKS{1'b1}}; + ifs_rst <= cfg_lanes_disable; + latency_monitor_reset <= 1'b0; + end + end + endcase + end + + always @(*) begin + case (state) + STATE_RESET: state_good = 1'b1; + STATE_WAIT_FOR_PHY: state_good = phy_ready; + STATE_CGS: state_good = &(cgs_ready | cfg_lanes_disable); + STATE_SYNCHRONIZED: state_good = ENABLE_FRAME_ALIGN_ERR_RESET ? + &(~frame_align_err_thresh_met | cfg_lanes_disable) : + 1'b1; + default: state_good = 1'b0; + endcase + end + + assign good_cnt_limit_s = (state == STATE_CGS) ? 'hff : 'h7; + assign good_cnt_limit_reached_s = good_counter == good_cnt_limit_s; + + assign goto_next_state_s = good_cnt_limit_reached_s || (state == STATE_SYNCHRONIZED); + + always @(posedge clk) begin + if (reset) begin + good_counter <= 'h00; + end else if (state_good == 1'b1) begin + if (good_cnt_limit_reached_s) begin + good_counter <= 'h00; + end else begin + good_counter <= good_counter + 1'b1; + end + end else begin + good_counter <= 'h00; + end + end + + always @(posedge clk) begin + case (state) + STATE_CGS: en_align <= 1'b1; + default: en_align <= 1'b0; + endcase + end + + always @(*) begin + case (state) + STATE_RESET: next_state = STATE_WAIT_FOR_PHY; + STATE_WAIT_FOR_PHY: next_state = STATE_CGS; + STATE_CGS: next_state = STATE_SYNCHRONIZED; + default: next_state = state_good ? state : STATE_RESET; + endcase + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + state <= STATE_RESET; + end else begin + if (goto_next_state_s) begin + state <= next_state; + end + end + end + + assign event_data_phase = state == STATE_CGS && + next_state == STATE_SYNCHRONIZED && + good_cnt_limit_reached_s; + +endmodule diff --git a/adi_library/jesd204/jesd204_rx/jesd204_rx_ctrl_64b.v b/adi_library/jesd204/jesd204_rx/jesd204_rx_ctrl_64b.v new file mode 100644 index 00000000..9fa08355 --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/jesd204_rx_ctrl_64b.v @@ -0,0 +1,119 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_rx_ctrl_64b #( + parameter NUM_LANES = 1 +) ( + input clk, + input reset, + + input [NUM_LANES-1:0] cfg_lanes_disable, + + input [NUM_LANES-1:0] phy_block_sync, + + input [NUM_LANES-1:0] emb_lock, + + output all_emb_lock, + input buffer_release_n, + + output [1:0] status_state, + output reg event_unexpected_lane_state_error +); + + localparam STATE_RESET = 2'b00; + localparam STATE_WAIT_BS = 2'b01; + localparam STATE_BLOCK_SYNC = 2'b10; + localparam STATE_DATA = 2'b11; + + reg [1:0] state = STATE_RESET; + reg [1:0] next_state; + reg [5:0] good_cnt; + reg rst_good_cnt; + reg event_unexpected_lane_state_error_nx; + + wire [NUM_LANES-1:0] phy_block_sync_masked; + wire [NUM_LANES-1:0] emb_lock_masked; + wire all_block_sync; + + reg [NUM_LANES-1:0] emb_lock_d = {NUM_LANES{1'b0}}; + reg buffer_release_d_n = 1'b1; + + always @(posedge clk) begin + emb_lock_d <= emb_lock; + buffer_release_d_n <= buffer_release_n; + end + + assign phy_block_sync_masked = phy_block_sync | cfg_lanes_disable; + assign emb_lock_masked = emb_lock_d | cfg_lanes_disable; + + assign all_block_sync = &phy_block_sync_masked; + assign all_emb_lock = &emb_lock_masked; + + always @(*) begin + next_state = state; + rst_good_cnt = 1'b1; + event_unexpected_lane_state_error_nx = 1'b0; + case (state) + STATE_RESET: + next_state = STATE_WAIT_BS; + STATE_WAIT_BS: + if (all_block_sync) begin + rst_good_cnt = 1'b0; + if (&good_cnt) begin + next_state = STATE_BLOCK_SYNC; + end + end + STATE_BLOCK_SYNC: + if (~all_block_sync) begin + next_state = STATE_WAIT_BS; + end else if (all_emb_lock & ~buffer_release_d_n) begin + rst_good_cnt = 1'b0; + if (&good_cnt) begin + next_state = STATE_DATA; + end + end + STATE_DATA: + if (~all_block_sync) begin + next_state = STATE_WAIT_BS; + event_unexpected_lane_state_error_nx = 1'b1; + end else if (~all_emb_lock | buffer_release_d_n) begin + next_state = STATE_BLOCK_SYNC; + event_unexpected_lane_state_error_nx = 1'b1; + end + endcase + end + + // Wait n consecutive valid cycles before jumping into next state + always @(posedge clk) begin + if (reset || rst_good_cnt) begin + good_cnt <= 'h0; + end else begin + good_cnt <= good_cnt + 1; + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + state <= STATE_RESET; + end else begin + state <= next_state; + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + event_unexpected_lane_state_error <= 1'b0; + end else begin + event_unexpected_lane_state_error <= event_unexpected_lane_state_error_nx; + end + end + + assign status_state = state; + +endmodule diff --git a/adi_library/jesd204/jesd204_rx/jesd204_rx_frame_align.v b/adi_library/jesd204/jesd204_rx/jesd204_rx_frame_align.v new file mode 100755 index 00000000..fafd87b4 --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/jesd204_rx_frame_align.v @@ -0,0 +1,162 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2020-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_rx_frame_align #( + parameter DATA_PATH_WIDTH = 4, + parameter ENABLE_CHAR_REPLACE = 0 +) ( + input clk, + input reset, + input [9:0] cfg_octets_per_multiframe, + input [7:0] cfg_octets_per_frame, + input cfg_disable_char_replacement, + input cfg_disable_scrambler, + input [DATA_PATH_WIDTH-1:0] charisk28, + input [DATA_PATH_WIDTH*8-1:0] data, + + output [DATA_PATH_WIDTH*8-1:0] data_replaced, + output reg [7:0] align_err_cnt +); + + // Reset alignment error count on good multiframe alignment, + // or on good frame or multiframe alignment + // If disabled, misalignments could me masked if + // due to cfg_octets_per_multiframe mismatch or due to + // a slip of a multiple of cfg_octets_per_frame octets + localparam RESET_COUNT_ON_MF_ONLY = 1'b1; + + localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : + DATA_PATH_WIDTH == 4 ? 2 : 1; + + function automatic [DPW_LOG2*2:0] count_ones(input [DATA_PATH_WIDTH*2-1:0] val); + reg [DPW_LOG2*2-1:0] ii; + begin + count_ones = 0; + for(ii = 0; ii != (DATA_PATH_WIDTH*2-1); ii=ii+1) begin + count_ones = count_ones + val[ii]; + end + end + endfunction + + reg [DATA_PATH_WIDTH-1:0] char_is_a; + reg [DATA_PATH_WIDTH-1:0] char_is_f; + wire [DATA_PATH_WIDTH-1:0] eof; + wire [DATA_PATH_WIDTH-1:0] eomf; + reg [DATA_PATH_WIDTH-1:0] eof_err; + reg [DATA_PATH_WIDTH-1:0] eof_good; + reg [DATA_PATH_WIDTH-1:0] eomf_err; + reg [DATA_PATH_WIDTH-1:0] eomf_good; + reg align_good; + reg align_err; + reg [DPW_LOG2*2:0] cur_align_err_cnt; + wire [8:0] align_err_cnt_next; + + wire [7:0] cfg_beats_per_multiframe = cfg_octets_per_multiframe>>DPW_LOG2; + + jesd204_frame_mark #( + .DATA_PATH_WIDTH (DATA_PATH_WIDTH) + ) i_frame_mark ( + .clk (clk), + .reset (reset), + .cfg_octets_per_multiframe (cfg_octets_per_multiframe), + .cfg_beats_per_multiframe (cfg_beats_per_multiframe), + .cfg_octets_per_frame (cfg_octets_per_frame), + .sof (), + .eof (eof), + .somf (), + .eomf (eomf)); + + genvar ii; + generate + for (ii = 0; ii < DATA_PATH_WIDTH; ii = ii + 1) begin: gen_k_char + always @(*) begin + char_is_a[ii] = 1'b0; + char_is_f[ii] = 1'b0; + + if(charisk28[ii]) begin + if(data[ii*8+7:ii*8+5] == 3'd3) begin + char_is_a[ii] = 1'b1; + end + if(data[ii*8+7:ii*8+5] == 3'd7) begin + char_is_f[ii] = 1'b1; + end + end + end + + always @(posedge clk) begin + if(reset) begin + eomf_err[ii] <= 1'b0; + eomf_good[ii] <= 1'b0; + eof_err[ii] <= 1'b0; + eof_good[ii] <= 1'b0; + end else begin + eomf_err[ii] <= char_is_a[ii] && !eomf[ii]; + eomf_good[ii] <= char_is_a[ii] && eomf[ii]; + eof_err[ii] <= char_is_f[ii] && !eof[ii]; + eof_good[ii] <= char_is_f[ii] && eof[ii]; + end + end + end + endgenerate + + always @(posedge clk) begin + if(reset) begin + align_good <= 1'b0; + align_err <= 1'b0; + end else begin + if(RESET_COUNT_ON_MF_ONLY) begin + align_good <= |eomf_good; + end else begin + align_good <= |({eomf_good, eof_good}); + end + + align_err <= |({eomf_err, eof_err}); + end + end + + assign align_err_cnt_next = {1'b0, align_err_cnt} + cur_align_err_cnt; + + // Alignment error counter + // Resets upon good alignment + always @(posedge clk) begin + if(reset) begin + align_err_cnt <= 8'd0; + cur_align_err_cnt <= 'd0; + end else begin + cur_align_err_cnt <= count_ones({eomf_err, eof_err}); + + if(align_good && !align_err) begin + align_err_cnt <= 8'd0; + end else if(align_err_cnt_next[8]) begin + align_err_cnt <= 8'hFF; + end else begin + align_err_cnt <= align_err_cnt_next[7:0]; + end + end + end + + jesd204_frame_align_replace #( + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .IS_RX (1'b1), + .ENABLED (ENABLE_CHAR_REPLACE) + ) i_align_replace ( + .clk (clk), + .reset (reset), + .cfg_octets_per_frame (cfg_octets_per_frame), + .cfg_disable_char_replacement (cfg_disable_char_replacement), + .cfg_disable_scrambler (cfg_disable_scrambler), + .data (data), + .eof (eof), + .rx_char_is_a (char_is_a), + .rx_char_is_f (char_is_f), + .tx_eomf ({DATA_PATH_WIDTH{1'b0}}), + .data_out (data_replaced), + .charisk_out ()); + +endmodule diff --git a/adi_library/jesd204/jesd204_rx/jesd204_rx_header.v b/adi_library/jesd204/jesd204_rx/jesd204_rx_header.v new file mode 100644 index 00000000..14e34e32 --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/jesd204_rx_header.v @@ -0,0 +1,166 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2020, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_rx_header ( + input clk, + input reset, + + input sh_lock, + input [1:0] header, + + input [1:0] cfg_header_mode, // 0 - CRC12 ; 1 - CRC3; 2 - FEC; 3 - CMD + input [4:0] cfg_rx_thresh_emb_err, + input [7:0] cfg_beats_per_multiframe, + + output emb_lock, + + output valid_eomb, + output valid_eoemb, + // Received header data qualified by valid_eomb + output [11:0] crc12, + output [2:0] crc3, + output [25:0] fec, + output [18:0] cmd, + output reg [7:0] sh_count = 'h0, + + output [2:0] status_lane_emb_state, + output reg event_invalid_header, + output reg event_unexpected_eomb, + output reg event_unexpected_eoemb +); + + localparam STATE_EMB_INIT = 3'b001; + localparam STATE_EMB_HUNT = 3'b010; + localparam STATE_EMB_LOCK = 3'b100; + + localparam BIT_EMB_INIT = 0; + localparam BIT_EMB_HUNT = 1; + localparam BIT_EMB_LOCK = 2; + + reg [2:0] state = STATE_EMB_INIT; + reg [2:0] next_state; + + reg [31:0] sync_word = 'h0; + + wire header_bit; + wire invalid_sequence; + wire invalid_eoemb; + wire invalid_eomb; + wire [6:0] cmd0; + wire [6:0] cmd1; + wire [18:0] cmd3; + wire eoemb; + wire eomb; + + assign header_bit = header == 2'b01; + + always @(posedge clk) begin + sync_word <= {sync_word[30:0],header_bit}; + end + + assign crc12 = {sync_word[31:29],sync_word[27:25], + sync_word[23:21],sync_word[19:17]}; + assign crc3 = {sync_word[31:29]}; + assign cmd0 = {sync_word[15:13],sync_word[11], + sync_word[7:5]}; + assign cmd1 = {sync_word[27:25], + sync_word[19:17], + sync_word[11]}; + assign cmd3 = {sync_word[31:29],sync_word[27:25], + sync_word[23:21],sync_word[19:17], + sync_word[15:13],sync_word[11], + sync_word[7:5]}; + + assign cmd = cfg_header_mode == 0 ? {12'b0,cmd0} : + cfg_header_mode == 1 ? {12'b0,cmd1} : + cfg_header_mode == 3 ? cmd3 : 'b0; + + assign fec = {sync_word[31:10],sync_word[8:5]}; + + assign eomb = sync_word[4:0] == 5'b00001; + assign eoemb = sync_word[9] & eomb; + + always @(posedge clk) begin + if (next_state[BIT_EMB_INIT] || sh_count == cfg_beats_per_multiframe) begin + sh_count <= 'h0; + end else begin + sh_count <= sh_count + 8'b1; + end + end + + reg [1:0] emb_vcount = 'b0; + always @(posedge clk) begin + if (state[BIT_EMB_INIT]) begin + emb_vcount <= 'b0; + end else if (state[BIT_EMB_HUNT] && (sh_count == 0 && eoemb)) begin + emb_vcount <= emb_vcount + 'b1; + end + end + + reg [4:0] emb_icount = 'b0; + always @(posedge clk) begin + if (state[BIT_EMB_INIT]) begin + emb_icount <= 'b0; + end else if (state[BIT_EMB_LOCK]) begin + if (sh_count == 0 && eoemb) begin + emb_icount <= 'b0; + end else if (invalid_eoemb || invalid_eomb) begin + emb_icount <= emb_icount + 5'b1; + end + end + end + + always @(*) begin + next_state = state; + case (state) + STATE_EMB_INIT: + if (eoemb) begin + next_state = STATE_EMB_HUNT; + end + STATE_EMB_HUNT: + if (invalid_sequence) begin + next_state = STATE_EMB_INIT; + end else if (eoemb && emb_vcount == 2'd3) begin + next_state = STATE_EMB_LOCK; + end + STATE_EMB_LOCK: + if (emb_icount == cfg_rx_thresh_emb_err) begin + next_state = STATE_EMB_INIT; + end + endcase + if (sh_lock == 1'b0) next_state = STATE_EMB_INIT; + end + + assign invalid_eoemb = (sh_count == 0 && ~eoemb); + assign invalid_eomb = (sh_count[4:0] == 0 && ~eomb); + assign valid_eomb = next_state[BIT_EMB_LOCK] && eomb; + assign valid_eoemb = next_state[BIT_EMB_LOCK] && eoemb; + + assign invalid_sequence = (invalid_eoemb || invalid_eomb); + + always @(posedge clk) begin + if (reset == 1'b1) begin + state <= STATE_EMB_INIT; + end else begin + state <= next_state; + end + end + + assign emb_lock = next_state[BIT_EMB_LOCK]; + + // Status & error events + assign status_lane_emb_state = state; + + always @(posedge clk) begin + event_invalid_header <= (~state[BIT_EMB_INIT]) && (header[0] == header[1]); + event_unexpected_eomb <= (~state[BIT_EMB_INIT]) && (sh_count[4:0] != 0 && eomb); + event_unexpected_eoemb <= (~state[BIT_EMB_INIT]) && invalid_eoemb; + end + +endmodule diff --git a/adi_library/jesd204/jesd204_rx/jesd204_rx_hw.tcl b/adi_library/jesd204/jesd204_rx/jesd204_rx_hw.tcl new file mode 100755 index 00000000..4186ddb1 --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/jesd204_rx_hw.tcl @@ -0,0 +1,244 @@ +############################################################################### +## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +package require qsys 14.0 + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl + +ad_ip_create jesd204_rx "ADI JESD204 Receive" jesd204_rx_elaboration_callback + +set_module_property INTERNAL true + +# files + +ad_ip_files jesd204_rx [list \ + jesd204_rx.v \ + align_mux.v \ + elastic_buffer.v \ + jesd204_ilas_monitor.v \ + jesd204_lane_latency_monitor.v \ + jesd204_rx_cgs.v \ + jesd204_rx_ctrl.v \ + jesd204_rx_lane.v \ + jesd204_rx_frame_align.v \ + jesd204_rx_constr.sdc \ + ../jesd204_common/jesd204_eof_generator.v \ + ../jesd204_common/jesd204_frame_mark.v \ + ../jesd204_common/jesd204_frame_align_replace.v \ + ../jesd204_common/jesd204_lmfc.v \ + ../jesd204_common/jesd204_scrambler.v \ + ../jesd204_common/pipeline_stage.v \ + $ad_hdl_dir/library/util_cdc/sync_bits.v \ + $ad_hdl_dir/library/util_cdc/sync_data.v \ + $ad_hdl_dir/library/util_cdc/sync_event.v \ + $ad_hdl_dir/library/util_cdc/util_cdc_constr.tcl \ + ../../common/ad_pack.v \ + ../../common/ad_upack.v \ +] + +# parameters + +add_parameter NUM_LANES INTEGER 1 +set_parameter_property NUM_LANES DISPLAY_NAME "Number of Lanes" +set_parameter_property NUM_LANES ALLOWED_RANGES 1:32 +set_parameter_property NUM_LANES HDL_PARAMETER true + +add_parameter NUM_LINKS INTEGER 1 +set_parameter_property NUM_LINKS DISPLAY_NAME "Number of Links" +set_parameter_property NUM_LINKS ALLOWED_RANGES 1:8 +set_parameter_property NUM_LINKS HDL_PARAMETER true + +add_parameter NUM_INPUT_PIPELINE INTEGER 1 +set_parameter_property NUM_INPUT_PIPELINE DISPLAY_NAME "Number of input pipeline stages" +set_parameter_property NUM_INPUT_PIPELINE ALLOWED_RANGES 1:3 +set_parameter_property NUM_INPUT_PIPELINE HDL_PARAMETER true + +add_parameter ASYNC_CLK BOOLEAN false +set_parameter_property ASYNC_CLK DISPLAY_NAME "Link and device clock asynchronous" +set_parameter_property ASYNC_CLK HDL_PARAMETER true + +ad_ip_parameter TPL_DATA_PATH_WIDTH INTEGER 4 true { \ + DISPLAY_NAME "Transport layer datapath width" \ + DISPLAY_UNITS "octets" \ + ALLOWED_RANGES {4 6 8 12} \ +} + +#ad_ip_parameter PORT_ENABLE_RX_EOF BOOLEAN false false +#ad_ip_parameter PORT_ENABLE_LMFC_CLK BOOLEAN false false +#ad_ip_parameter PORT_ENABLE_LMFC_EDGE BOOLEAN false false + +# link clock + +add_interface clock clock end +add_interface_port clock clk clk Input 1 + +# link clock reset + +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT + +add_interface_port reset reset reset Input 1 + +# device clock + +add_interface device_clock clock end +add_interface_port device_clock device_clk clk Input 1 + +# device clock reset + +add_interface device_reset reset end +set_interface_property device_reset associatedClock device_clock +set_interface_property device_reset synchronousEdges DEASSERT + +add_interface_port device_reset device_reset reset Input 1 + +# SYSREF~ interface + +add_interface sysref conduit end +set_interface_property sysref associatedClock device_clock +set_interface_property sysref associatedReset device_reset +add_interface_port sysref sysref export Input 1 + +# SYNC interface + +add_interface sync conduit end +set_interface_property sync associatedClock clock +set_interface_property sync associatedReset reset +add_interface_port sync sync export Output NUM_LINKS + +# link clock domain config interface + +add_interface config conduit end +set_interface_property config associatedClock clock +set_interface_property config associatedReset reset + +add_interface_port config cfg_lanes_disable lanes_disable Input NUM_LANES +add_interface_port config cfg_links_disable links_disable Input NUM_LINKS +add_interface_port config cfg_octets_per_multiframe octets_per_multiframe Input 10 +add_interface_port config cfg_octets_per_frame octets_per_frame Input 8 +add_interface_port config cfg_disable_scrambler disable_scrambler Input 1 +add_interface_port config cfg_disable_char_replacement disable_char_replacement Input 1 +add_interface_port config cfg_frame_align_err_threshold frame_align_err_threshold Input 8 +add_interface_port config ctrl_err_statistics_reset err_statistics_reset Input 1 +add_interface_port config ctrl_err_statistics_mask err_statistics_mask Input 3 + +# device clock domain config interface + +add_interface device_config conduit end +set_interface_property device_config associatedClock device_clock +set_interface_property device_config associatedReset device_reset + +add_interface_port device_config device_cfg_octets_per_multiframe octets_per_multiframe Input 10 +add_interface_port device_config device_cfg_octets_per_frame octets_per_frame Input 8 +add_interface_port device_config device_cfg_beats_per_multiframe beats_per_multiframe Input 8 +add_interface_port device_config device_cfg_lmfc_offset lmfc_offset Input 8 +add_interface_port device_config device_cfg_sysref_disable sysref_disable Input 1 +add_interface_port device_config device_cfg_sysref_oneshot sysref_oneshot Input 1 +add_interface_port device_config device_cfg_buffer_delay buffer_delay Input 8 +add_interface_port device_config device_cfg_buffer_early_release buffer_early_release Input 1 + +# status interface + +add_interface status conduit end +set_interface_property status associatedClock clock +set_interface_property status associatedReset reset + +add_interface_port status status_ctrl_state ctrl_state Output 2 +add_interface_port status status_lane_cgs_state lane_cgs_state Output 2*NUM_LANES +add_interface_port status status_lane_ifs_ready lane_ifs_ready Output NUM_LANES +add_interface_port status status_lane_latency lane_latency Output 14*NUM_LANES +add_interface_port status status_err_statistics_cnt err_statistics_cnt Output 32*NUM_LANES +add_interface_port status status_lane_frame_align_err_cnt lane_frame_align_err_cnt Output 8*NUM_LANES +add_interface_port status status_synth_params0 synth_params0 Output 32 +add_interface_port status status_synth_params1 synth_params1 Output 32 +add_interface_port status status_synth_params2 synth_params2 Output 32 + +# event interface + +add_interface device_event conduit end +set_interface_property device_event associatedClock device_clock +set_interface_property device_event associatedReset device_reset + +add_interface_port device_event device_event_sysref_alignment_error sysref_alignment_error Output 1 +add_interface_port device_event device_event_sysref_edge sysref_edge Output 1 + +# ilas_config interface + +add_interface ilas_config conduit end +set_interface_property ilas_config associatedClock clock +set_interface_property ilas_config associatedReset reset + +add_interface_port ilas_config ilas_config_addr addr Output NUM_LANES*2 +add_interface_port ilas_config ilas_config_data data Output NUM_LANES*32 +add_interface_port ilas_config ilas_config_valid valid Output NUM_LANES + +# rx_eof interface + +add_interface rx_eof conduit end +#set_interface_property rx_eof associatedClock clock +#set_interface_property rx_eof associatedReset reset +add_interface_port rx_eof rx_eof export Output 4 +set_port_property rx_eof TERMINATION TRUE + +# rx_sof interface + +add_interface rx_sof conduit end +#set_interface_property rx_sof associatedClock clock +#set_interface_property rx_sof associatedReset reset +add_interface_port rx_sof rx_sof export Output 4 + +# lmfc_clk interface + +add_interface lmfc_clk conduit end +#set_interface_property lmfc_clk associatedClock clock +#set_interface_property lmfc_clk associatedReset reset +add_interface_port lmfc_clk lmfc_clk export Output 1 +set_port_property lmfc_clk TERMINATION TRUE + +# lmfc_edge interface + +add_interface lmfc_edge conduit end +#set_interface_property lmfc_edge associatedClock clock +#set_interface_property lmfc_edge associatedReset reset +add_interface_port lmfc_edge lmfc_edge export Output 1 +set_port_property lmfc_edge TERMINATION TRUE + +proc jesd204_rx_elaboration_callback {} { + set num_lanes [get_parameter_value "NUM_LANES"] + set tpl_width [get_parameter_value "TPL_DATA_PATH_WIDTH"] + + # rx_data interface + + add_interface rx_data avalon_streaming source + set_interface_property rx_data associatedClock device_clock + + add_interface_port rx_data rx_data data output [expr 8*$tpl_width*$num_lanes] + add_interface_port rx_data rx_valid valid output 1 + set_interface_property rx_data dataBitsPerSymbol [expr 8*$tpl_width*$num_lanes] + + # phy interfaces + + for {set i 0 } {$i < $num_lanes} {incr i} { + add_interface rx_phy${i} conduit end +# set_interface_property rx_phy${i} associatedClock clock +# set_interface_property rx_phy${i} associatedReset reset + add_interface_port rx_phy${i} rx_phy${i}_data char Input 32 + set_port_property rx_phy${i}_data fragment_list \ + [format "phy_data(%d:%d)" [expr 32*$i+31] [expr 32*$i]] + add_interface_port rx_phy${i} rx_phy${i}_charisk charisk Input 4 + set_port_property rx_phy${i}_charisk fragment_list \ + [format "phy_charisk(%d:%d)" [expr 4*$i+3] [expr 4*$i]] + add_interface_port rx_phy${i} rx_phy${i}_disperr disperr Input 4 + set_port_property rx_phy${i}_disperr fragment_list \ + [format "phy_disperr(%d:%d)" [expr 4*$i+3] [expr 4*$i]] + add_interface_port rx_phy${i} rx_phy${i}_notintable notintable Input 4 + set_port_property rx_phy${i}_notintable fragment_list \ + [format "phy_notintable(%d:%d)" [expr 4*$i+3] [expr 4*$i]] + add_interface_port rx_phy${i} rx_phy${i}_patternalign_en patternalign_en Output 1 + set_port_property rx_phy${i}_patternalign_en fragment_list "phy_en_char_align" + } +} diff --git a/adi_library/jesd204/jesd204_rx/jesd204_rx_ip.tcl b/adi_library/jesd204/jesd204_rx/jesd204_rx_ip.tcl new file mode 100755 index 00000000..023c893b --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/jesd204_rx_ip.tcl @@ -0,0 +1,195 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create jesd204_rx +adi_ip_files jesd204_rx [list \ + "jesd204_rx_lane.v" \ + "jesd204_rx_lane_64b.v" \ + "jesd204_rx_header.v" \ + "jesd204_rx_cgs.v" \ + "jesd204_rx_ctrl.v" \ + "jesd204_rx_ctrl_64b.v" \ + "elastic_buffer.v" \ + "error_monitor.v" \ + "jesd204_ilas_monitor.v" \ + "align_mux.v" \ + "jesd204_lane_latency_monitor.v" \ + "jesd204_rx_frame_align.v" \ + "jesd204_rx_constr.ttcl" \ + "jesd204_rx_ooc.ttcl" \ + "jesd204_rx.v" \ + "../../common/ad_pack.v" \ + "../../common/ad_upack.v" \ + "bd/bd.tcl" +] + +set_property source_mgmt_mode DisplayOnly [current_project] + +adi_ip_properties_lite jesd204_rx +adi_ip_ttcl jesd204_rx "jesd204_rx_constr.ttcl" +adi_ip_ttcl jesd204_rx "jesd204_rx_ooc.ttcl" +adi_ip_bd jesd204_rx "bd/bd.tcl" + +adi_ip_add_core_dependencies [list \ + analog.com:$VIVADO_IP_LIBRARY:jesd204_common:1.0 \ + analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \ +] + +set_property display_name "ADI JESD204 Receive" [ipx::current_core] +set_property description "ADI JESD204 Receive" [ipx::current_core] + +#adi_add_bus "rx_data" "master" \ +# "xilinx.com:interface:axis_rtl:1.0" \ +# "xilinx.com:interface:axis:1.0" \ +# { \ +# { "rx_valid" "TVALID" } \ +# { "rx_data" "TDATA" } \ +# } + +adi_add_multi_bus 32 "rx_phy" "slave" \ + "xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0" \ + "xilinx.com:display_jesd204:jesd204_rx_bus:1.0" \ + [list \ + { "phy_data" "rxdata" 32 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')) * 8)"} \ + { "phy_charisk" "rxcharisk" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \ + { "phy_disperr" "rxdisperr" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \ + { "phy_notintable" "rxnotintable" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \ + { "phy_header" "rxheader" 2} \ + { "phy_block_sync" "rxblock_sync" 1} \ + ] \ + "(spirit:decode(id('MODELPARAM_VALUE.NUM_LANES')) > {i})" + +set_property driver_value 0 [ipx::get_ports phy_charisk -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports phy_disperr -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports phy_notintable -of_objects [ipx::current_core]] + +adi_add_bus "rx_cfg" "slave" \ + "analog.com:interface:jesd204_rx_cfg_rtl:1.0" \ + "analog.com:interface:jesd204_rx_cfg:1.0" \ + { \ + { "cfg_lanes_disable" "lanes_disable" } \ + { "cfg_links_disable" "links_disable" } \ + { "cfg_octets_per_multiframe" "octets_per_multiframe" } \ + { "cfg_octets_per_frame" "octets_per_frame" } \ + { "cfg_disable_scrambler" "disable_scrambler" } \ + { "cfg_disable_char_replacement" "disable_char_replacement" } \ + { "cfg_frame_align_err_threshold" "frame_align_err_threshold" } \ + { "device_cfg_octets_per_multiframe" "device_octets_per_multiframe" } \ + { "device_cfg_octets_per_frame" "device_octets_per_frame" } \ + { "device_cfg_beats_per_multiframe" "device_beats_per_multiframe" } \ + { "device_cfg_lmfc_offset" "device_lmfc_offset" } \ + { "device_cfg_sysref_oneshot" "device_sysref_oneshot" } \ + { "device_cfg_sysref_disable" "device_sysref_disable" } \ + { "device_cfg_buffer_delay" "device_buffer_delay" } \ + { "device_cfg_buffer_early_release" "device_buffer_early_release" } \ + { "ctrl_err_statistics_reset" "err_statistics_reset" } \ + { "ctrl_err_statistics_mask" "err_statistics_mask" } \ + } + +adi_add_bus "rx_status" "master" \ + "analog.com:interface:jesd204_rx_status_rtl:1.0" \ + "analog.com:interface:jesd204_rx_status:1.0" \ + { \ + { "status_ctrl_state" "ctrl_state" } \ + { "status_lane_cgs_state" "lane_cgs_state" } \ + { "status_lane_emb_state" "lane_emb_state" } \ + { "status_err_statistics_cnt" "err_statistics_cnt" } \ + { "status_lane_ifs_ready" "lane_ifs_ready" } \ + { "status_lane_latency" "lane_latency" } \ + { "status_lane_frame_align_err_cnt" "lane_frame_align_err_cnt" } \ + { "status_synth_params0" "synth_params0" } \ + { "status_synth_params1" "synth_params1" } \ + { "status_synth_params2" "synth_params2" } \ + } + +adi_add_bus "rx_ilas_config" "master" \ + "analog.com:interface:jesd204_rx_ilas_config_rtl:1.0" \ + "analog.com:interface:jesd204_rx_ilas_config:1.0" \ + { \ + { "ilas_config_valid" "valid" } \ + { "ilas_config_addr" "addr" } \ + { "ilas_config_data" "data" } \ + } + +adi_add_bus "rx_event" "master" \ + "analog.com:interface:jesd204_rx_event_rtl:1.0" \ + "analog.com:interface:jesd204_rx_event:1.0" \ + { \ + { "device_event_sysref_alignment_error" "sysref_alignment_error" } \ + { "device_event_sysref_edge" "sysref_edge" } \ + { "event_frame_alignment_error" "frame_alignment_error" } \ + { "event_unexpected_lane_state_error" "unexpected_lane_state_error" } \ + } + +adi_add_bus_clock "clk" "rx_cfg:rx_ilas_config:rx_event:rx_status" "reset" +adi_add_bus_clock "device_clk" "rx_data" "device_reset" + +adi_set_bus_dependency "rx_ilas_config" "rx_ilas_config" \ + "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" + +adi_set_ports_dependency "sync" \ + "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" + +adi_set_ports_dependency "phy_en_char_align" \ + "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" + +set cc [ipx::current_core] + +set_property -dict [list \ + driver_value 0 \ +] [ipx::get_ports phy_header -of_objects $cc] + +# Arrange GUI page layout +set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] + +# Link layer mode +set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $page0 +set_property -dict [list \ + "display_name" "Link Layer mode" \ + "tooltip" "Link Layer mode" \ + "widget" "comboBox" \ +] $p + +set_property -dict [list \ + value_validation_type pairs \ + value_validation_pairs {64B66B 2 8B10B 1} \ +] [ipx::get_user_parameters $p -of_objects $cc] + +# Data width selection +set param [ipx::get_user_parameters DATA_PATH_WIDTH -of_objects $cc] +set_property -dict [list \ + enablement_tcl_expr {$LINK_MODE==1} \ + value_tcl_expr {expr $LINK_MODE*4} \ +] $param + + +set param [ipx::add_user_parameter SYSREF_IOB $cc] +set_property -dict {value_resolve_type user value_format bool value true} $param + +set param [ipgui::add_param -name {SYSREF_IOB} -component $cc -parent $page0] +set_property -dict [list \ + display_name {Place SYSREF in IOB} \ + widget {checkBox} \ + show_label true \ +] $param + +set clk_group [ipgui::add_group -name {Clock Domain Configuration} -component $cc \ + -parent $page0 -display_name {Clock Domain Configuration}] + +set p [ipgui::get_guiparamspec -name "ASYNC_CLK" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $clk_group +set_property -dict [list \ + "display_name" "Link and Device Clock Asynchronous" \ + "widget" "checkBox" \ +] $p + +ipx::create_xgui_files [ipx::current_core] +ipx::save_core [ipx::current_core] diff --git a/adi_library/jesd204/jesd204_rx/jesd204_rx_lane.v b/adi_library/jesd204/jesd204_rx/jesd204_rx_lane.v new file mode 100755 index 00000000..277cb648 --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/jesd204_rx_lane.v @@ -0,0 +1,314 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_rx_lane #( + parameter DATA_PATH_WIDTH = 4, + parameter TPL_DATA_PATH_WIDTH = 4, + parameter CHAR_INFO_REGISTERED = 0, + parameter ALIGN_MUX_REGISTERED = 0, + parameter SCRAMBLER_REGISTERED = 0, + parameter ELASTIC_BUFFER_SIZE = 256, + parameter ENABLE_FRAME_ALIGN_CHECK = 0, + parameter ENABLE_CHAR_REPLACE = 0, + parameter ASYNC_CLK = 0 +) ( + input clk, + input reset, + + input device_clk, + input device_reset, + + input [DATA_PATH_WIDTH*8-1:0] phy_data, + input [DATA_PATH_WIDTH-1:0] phy_charisk, + input [DATA_PATH_WIDTH-1:0] phy_notintable, + input [DATA_PATH_WIDTH-1:0] phy_disperr, + + input cgs_reset, + output cgs_ready, + + input ifs_reset, + + output [TPL_DATA_PATH_WIDTH*8-1:0] rx_data, + + output buffer_ready_n, + input buffer_release_n, + + input [9:0] cfg_octets_per_multiframe, + input [7:0] cfg_octets_per_frame, + input cfg_disable_char_replacement, + input cfg_disable_scrambler, + + output ilas_config_valid, + output [1:0] ilas_config_addr, + output [DATA_PATH_WIDTH*8-1:0] ilas_config_data, + + input err_statistics_reset, + input [2:0] ctrl_err_statistics_mask, + output reg [31:0] status_err_statistics_cnt, + + output [1:0] status_cgs_state, + output status_ifs_ready, + output [2:0] status_frame_align, + output [7:0] status_frame_align_err_cnt +); + + localparam MAX_DATA_PATH_WIDTH = 8; + localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1; + + wire [7:0] char[0:DATA_PATH_WIDTH-1]; + wire [DATA_PATH_WIDTH-1:0] char_is_valid; + reg [DATA_PATH_WIDTH-1:0] char_is_cgs = 1'b0; // K28.5 /K/ + + reg [DATA_PATH_WIDTH-1:0] char_is_error = 1'b0; + reg [DATA_PATH_WIDTH-1:0] charisk28 = 4'b0000; + + wire cgs_beat_is_cgs = &char_is_cgs; + wire cgs_beat_has_error = |char_is_error; + + reg ifs_ready = 1'b0; + reg [2:0] frame_align = 'h00; + reg [2:0] frame_align_int; + + wire [DATA_PATH_WIDTH*8-1:0] phy_data_s; + wire [DATA_PATH_WIDTH-1:0] charisk28_aligned_s; + wire [DATA_PATH_WIDTH*8-1:0] data_aligned_s; + wire [DATA_PATH_WIDTH-1:0] charisk28_aligned; + wire [DATA_PATH_WIDTH*8-1:0] data_aligned; + wire [DATA_PATH_WIDTH*8-1:0] data_replaced; + wire [DATA_PATH_WIDTH*8-1:0] data_scrambled_s; + wire [DATA_PATH_WIDTH*8-1:0] data_scrambled; + + reg [DATA_PATH_WIDTH-1:0] unexpected_char; + reg [DATA_PATH_WIDTH-1:0] phy_char_err; + + wire ilas_monitor_reset_s; + wire ilas_monitor_reset; + wire buffer_ready_n_s; + reg [DPW_LOG2:0] jj; + reg align_found; + + assign status_ifs_ready = ifs_ready; + assign status_frame_align = frame_align; + + genvar i; + generate + + for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_char + assign char[i] = phy_data[i*8+7:i*8]; + assign char_is_valid[i] = ~(phy_notintable[i] | phy_disperr[i]); + + always @(*) begin + char_is_error[i] = ~char_is_valid[i]; + + char_is_cgs[i] = 1'b0; + charisk28[i] = 1'b0; + unexpected_char[i] = 1'b0; + + if (phy_charisk[i] == 1'b1 && char_is_valid[i] == 1'b1) begin + if (char[i][4:0] == 'd28) begin + charisk28[i] = 1'b1; + if (char[i][7:5] == 'd5) begin + char_is_cgs[i] = 1'b1; + end + end else begin + unexpected_char[i] = 1'b1; + end + end + end + end + endgenerate + + always @(posedge clk) begin + if (cgs_ready == 1'b1) begin + /* + * Set the bit in phy_char_err if at least one of the monitored error + * conditions has occured. + */ + phy_char_err <= (~{DATA_PATH_WIDTH{ctrl_err_statistics_mask[0]}} & phy_disperr) | + (~{DATA_PATH_WIDTH{ctrl_err_statistics_mask[1]}} & phy_notintable) | + (~{DATA_PATH_WIDTH{ctrl_err_statistics_mask[2]}} & unexpected_char); + end else begin + phy_char_err <= {DATA_PATH_WIDTH{1'b0}}; + end + end + + function [7:0] num_set_bits; + input [DATA_PATH_WIDTH-1:0] x; + integer j; + begin + num_set_bits = 0; + for (j = 0; j < DATA_PATH_WIDTH; j = j + 1) begin + num_set_bits = num_set_bits + x[j]; + end + end + endfunction + + always @(posedge clk) begin + if (reset == 1'b1 || err_statistics_reset == 1'b1) begin + status_err_statistics_cnt <= 32'h0; + end else if (status_err_statistics_cnt[31:5] != 27'h7ffffff) begin + status_err_statistics_cnt <= status_err_statistics_cnt + num_set_bits(phy_char_err); + end + end + + always @(posedge clk) begin + if (ifs_reset == 1'b1) begin + ifs_ready <= 1'b0; + end else if (cgs_beat_is_cgs == 1'b0 && cgs_beat_has_error == 1'b0) begin + ifs_ready <= 1'b1; + end + end + + always @(*) begin + align_found = 1'b0; + frame_align_int = 0; + for(jj = 0; jj < DATA_PATH_WIDTH; jj=jj+1) begin + if (!align_found && (char_is_cgs[jj] == 1'b0)) begin + align_found = 1'b1; + frame_align_int = jj; + end + end + end + + always @(posedge clk) begin + if (ifs_ready == 1'b0) begin + frame_align <= frame_align_int; + end + end + + pipeline_stage #( + .WIDTH(DATA_PATH_WIDTH*8), + .REGISTERED(CHAR_INFO_REGISTERED) + ) i_pipeline_stage0 ( + .clk(clk), + .in(phy_data), + .out(phy_data_s)); + + align_mux #( + .DATA_PATH_WIDTH(DATA_PATH_WIDTH) + ) i_align_mux ( + .clk(clk), + .align(frame_align), + .in_data(phy_data_s), + .out_data(data_aligned_s), + .in_charisk(charisk28), + .out_charisk(charisk28_aligned_s)); + + assign ilas_monitor_reset_s = ~ifs_ready; + + pipeline_stage #( + .WIDTH(1 + DATA_PATH_WIDTH * (8 + 1)), + .REGISTERED(ALIGN_MUX_REGISTERED) + ) i_pipeline_stage1 ( + .clk(clk), + .in({ + ilas_monitor_reset_s, + data_aligned_s, + charisk28_aligned_s + }), + .out({ + ilas_monitor_reset, + data_aligned, + charisk28_aligned + })); + + generate + if (ENABLE_FRAME_ALIGN_CHECK) begin : gen_frame_align + jesd204_rx_frame_align #( + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .ENABLE_CHAR_REPLACE (ENABLE_CHAR_REPLACE) + ) i_frame_align ( + .clk (clk), + .reset (buffer_ready_n_s), + .cfg_octets_per_multiframe (cfg_octets_per_multiframe), + .cfg_octets_per_frame (cfg_octets_per_frame), + .cfg_disable_char_replacement (cfg_disable_char_replacement), + .cfg_disable_scrambler (cfg_disable_scrambler), + .charisk28 (charisk28_aligned), + .data (data_aligned), + .data_replaced (data_replaced), + .align_err_cnt (status_frame_align_err_cnt)); + + end else begin : gen_no_frame_align_monitor + assign status_frame_align_err_cnt = 32'd0; + assign data_replaced = data_aligned; + end + endgenerate + + jesd204_scrambler #( + .WIDTH(DATA_PATH_WIDTH*8), + .DESCRAMBLE(1) + ) i_descrambler ( + .clk(clk), + .reset(buffer_ready_n_s), + .enable(~cfg_disable_scrambler), + .data_in(data_replaced), + .data_out(data_scrambled_s)); + + pipeline_stage #( + .WIDTH(1 + DATA_PATH_WIDTH * 8), + .REGISTERED(SCRAMBLER_REGISTERED) + ) i_pipeline_stage2 ( + .clk(clk), + .in({ + buffer_ready_n_s, + data_scrambled_s + }), + .out({ + buffer_ready_n, + data_scrambled + })); + + elastic_buffer #( + .IWIDTH(DATA_PATH_WIDTH*8), + .OWIDTH(TPL_DATA_PATH_WIDTH*8), + .SIZE(ELASTIC_BUFFER_SIZE), + .ASYNC_CLK(ASYNC_CLK) + ) i_elastic_buffer ( + .clk(clk), + .reset(reset), + + .device_clk(device_clk), + .device_reset(device_reset), + + .wr_data(data_scrambled), + .rd_data(rx_data), + + .ready_n(buffer_ready_n), + .do_release_n(buffer_release_n)); + + jesd204_ilas_monitor #( + .DATA_PATH_WIDTH(DATA_PATH_WIDTH) + ) i_ilas_monitor ( + .clk(clk), + .reset(ilas_monitor_reset), + .cfg_octets_per_multiframe(cfg_octets_per_multiframe), + .data(data_aligned), + .charisk28(charisk28_aligned), + + .data_ready_n(buffer_ready_n_s), + + .ilas_config_valid(ilas_config_valid), + .ilas_config_addr(ilas_config_addr), + .ilas_config_data(ilas_config_data)); + + jesd204_rx_cgs #( + .DATA_PATH_WIDTH(DATA_PATH_WIDTH) + ) i_cgs ( + .clk(clk), + .reset(cgs_reset), + + .char_is_cgs(char_is_cgs), + .char_is_error(char_is_error), + + .ready(cgs_ready), + + .status_state(status_cgs_state)); + +endmodule diff --git a/adi_library/jesd204/jesd204_rx/jesd204_rx_lane_64b.v b/adi_library/jesd204/jesd204_rx/jesd204_rx_lane_64b.v new file mode 100644 index 00000000..fea5aeaa --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/jesd204_rx_lane_64b.v @@ -0,0 +1,215 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2020-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_rx_lane_64b #( + parameter ELASTIC_BUFFER_SIZE = 256, + parameter TPL_DATA_PATH_WIDTH = 8, + parameter ASYNC_CLK = 0 +) ( + input clk, + input reset, + + input device_clk, + input device_reset, + + input [63:0] phy_data, + input [1:0] phy_header, + input phy_block_sync, + + output [TPL_DATA_PATH_WIDTH*8-1:0] rx_data, + + output reg buffer_ready_n = 'b1, + input all_buffer_ready_n, + input buffer_release_n, + + input lmfc_edge, + output emb_lock, + + input cfg_disable_scrambler, + input [1:0] cfg_header_mode, // 0 - CRC12 ; 1 - CRC3; 2 - FEC; 3 - CMD + input [4:0] cfg_rx_thresh_emb_err, + input [7:0] cfg_beats_per_multiframe, + + input ctrl_err_statistics_reset, + input [3:0] ctrl_err_statistics_mask, + output [31:0] status_err_statistics_cnt, + + output [2:0] status_lane_emb_state, + output reg [7:0] status_lane_skew +); + + reg [11:0] crc12_calculated_prev; + + wire [63:0] data_descrambled_s; + wire [63:0] data_descrambled; + wire [63:0] data_descrambled_reordered; + wire [11:0] crc12_received; + wire [11:0] crc12_calculated; + + wire event_invalid_header; + wire event_unexpected_eomb; + wire event_unexpected_eoemb; + wire event_crc12_mismatch; + wire err_cnt_rst; + + wire [63:0] rx_data_msb_s; + + wire eomb; + wire eoemb; + + wire [7:0] sh_count; + + jesd204_rx_header i_rx_header ( + .clk(clk), + .reset(reset), + + .sh_lock(phy_block_sync), + .header(phy_header), + + .cfg_header_mode(cfg_header_mode), + .cfg_rx_thresh_emb_err(cfg_rx_thresh_emb_err), + .cfg_beats_per_multiframe(cfg_beats_per_multiframe), + + .emb_lock(emb_lock), + + .valid_eomb(eomb), + .valid_eoemb(eoemb), + .crc12(crc12_received), + .crc3(), + .fec(), + .cmd(), + .sh_count(sh_count), + + .status_lane_emb_state(status_lane_emb_state), + .event_invalid_header(event_invalid_header), + .event_unexpected_eomb(event_unexpected_eomb), + .event_unexpected_eoemb(event_unexpected_eoemb)); + + jesd204_crc12 i_crc12 ( + .clk(clk), + .reset(1'b0), + .init(eomb), + .data_in(phy_data), + .crc12(crc12_calculated)); + + reg crc12_on = 'b0; + always @(posedge clk) begin + if (reset == 1'b1) begin + crc12_on <= 1'b0; + end else if (eomb) begin + crc12_on <= 1'b1; + end + end + + reg crc12_rdy = 'b0; + always @(posedge clk) begin + if (reset == 1'b1) begin + crc12_rdy <= 1'b0; + end else if (crc12_on && eomb) begin + crc12_rdy <= 1'b1; + end + end + + always @(posedge clk) begin + if (eomb) begin + crc12_calculated_prev <= crc12_calculated; + end + end + + assign event_crc12_mismatch = crc12_rdy && eomb && (crc12_calculated_prev != crc12_received); + + assign err_cnt_rst = reset || ctrl_err_statistics_reset; + + error_monitor #( + .EVENT_WIDTH(4), + .CNT_WIDTH(32) + ) i_error_monitor ( + .clk(clk), + .reset(err_cnt_rst), + .active(1'b1), + .error_event({ + event_invalid_header, + event_unexpected_eomb, + event_unexpected_eoemb, + event_crc12_mismatch + }), + .error_event_mask(ctrl_err_statistics_mask), + .status_err_cnt(status_err_statistics_cnt)); + + jesd204_scrambler_64b #( + .WIDTH(64), + .DESCRAMBLE(1) + ) i_descrambler ( + .clk(clk), + .reset(1'b0), + .enable(~cfg_disable_scrambler), + .data_in(phy_data), + .data_out(data_descrambled_s)); + + pipeline_stage #( + .WIDTH(64), + .REGISTERED(1) + ) i_pipeline_stage2 ( + .clk(clk), + .in({ + data_descrambled_s + }), + .out({ + data_descrambled + })); + + // Control when data is written to the elastic buffer + // Start writing to the buffer when current lane is multiblock locked, but if + // other lanes are not writing in the next half multiblock period stop + // writing. + // This limits the supported lane skew to half of the multiframe + always @(posedge clk) begin + if (reset | ~emb_lock) begin + buffer_ready_n <= 1'b1; + end else if (sh_count == {1'b0,cfg_beats_per_multiframe[7:1]} && all_buffer_ready_n) begin + buffer_ready_n <= 1'b1; + end else if (eoemb) begin + buffer_ready_n <= 1'b0; + end + end + + elastic_buffer #( + .IWIDTH(64), + .OWIDTH(TPL_DATA_PATH_WIDTH*8), + .SIZE(ELASTIC_BUFFER_SIZE), + .ASYNC_CLK(ASYNC_CLK) + ) i_elastic_buffer ( + .clk(clk), + .reset(reset), + + .device_clk(device_clk), + .device_reset(device_reset), + + .wr_data(data_descrambled_reordered), + .rd_data(rx_data), + + .ready_n(buffer_ready_n), + .do_release_n(buffer_release_n)); + + // Measure the delay from the eoemb to the next LMFC edge. + always @(posedge clk) begin + if (lmfc_edge) begin + status_lane_skew <= sh_count; + end + end + + /* Reorder octets LSB first */ + genvar i; + generate + for (i = 0; i < 64; i = i + 8) begin: g_link_data + assign data_descrambled_reordered[i+:8] = data_descrambled[64-1-i-:8]; + end + endgenerate + +endmodule diff --git a/adi_library/jesd204/jesd204_rx/jesd204_rx_ooc.ttcl b/adi_library/jesd204/jesd204_rx/jesd204_rx_ooc.ttcl new file mode 100644 index 00000000..3eba1ddb --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/jesd204_rx_ooc.ttcl @@ -0,0 +1,22 @@ +############################################################################### +## Copyright (C) 2017-2019, 2021 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +<: setFileUsedIn { out_of_context synthesis implementation } :> +<: ;#Component and file information :> +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName $ComponentName :> +<: setFileExtension "_ooc.xdc" :> + +# This XDC is used only for OOC mode of synthesis, implementation. +# These are default values for timing driven synthesis during OOC flow. +# These values will be overwritten during implementation with information +# from top level. + +create_clock -name clk -period 2.5 [get_ports clk] +create_clock -name device_clk -period 2.5 [get_ports device_clk] + +################################################################################ + diff --git a/adi_library/jesd204/jesd204_rx/xgui/jesd204_rx_v1_0.tcl b/adi_library/jesd204/jesd204_rx/xgui/jesd204_rx_v1_0.tcl new file mode 100644 index 00000000..3cacc8c3 --- /dev/null +++ b/adi_library/jesd204/jesd204_rx/xgui/jesd204_rx_v1_0.tcl @@ -0,0 +1,202 @@ + +# Loading additional proc with user specified bodies to compute parameter values. +source [file join [file dirname [file dirname [info script]]] gui/jesd204_rx_v1_0.gtcl] + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "LINK_MODE" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "DATA_PATH_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "ENABLE_CHAR_REPLACE" -parent ${Page_0} + ipgui::add_param $IPINST -name "ENABLE_FRAME_ALIGN_CHECK" -parent ${Page_0} + ipgui::add_param $IPINST -name "ENABLE_FRAME_ALIGN_ERR_RESET" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_INPUT_PIPELINE" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_LANES" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_LINKS" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_OUTPUT_PIPELINE" -parent ${Page_0} + ipgui::add_param $IPINST -name "TPL_DATA_PATH_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "SYSREF_IOB" -parent ${Page_0} + #Adding Group + set Clock_Domain_Configuration [ipgui::add_group $IPINST -name "Clock Domain Configuration" -parent ${Page_0}] + ipgui::add_param $IPINST -name "ASYNC_CLK" -parent ${Clock_Domain_Configuration} -widget checkBox + + + +} + +proc update_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH PARAM_VALUE.LINK_MODE } { + # Procedure called to update DATA_PATH_WIDTH when any of the dependent parameters in the arguments change + + set DATA_PATH_WIDTH ${PARAM_VALUE.DATA_PATH_WIDTH} + set LINK_MODE ${PARAM_VALUE.LINK_MODE} + set values(LINK_MODE) [get_property value $LINK_MODE] + if { [gen_USERPARAMETER_DATA_PATH_WIDTH_ENABLEMENT $values(LINK_MODE)] } { + set_property enabled true $DATA_PATH_WIDTH + } else { + set_property enabled false $DATA_PATH_WIDTH + set_property value [gen_USERPARAMETER_DATA_PATH_WIDTH_VALUE $values(LINK_MODE)] $DATA_PATH_WIDTH + } +} + +proc validate_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH } { + # Procedure called to validate DATA_PATH_WIDTH + return true +} + +proc update_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } { + # Procedure called to update ASYNC_CLK when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } { + # Procedure called to validate ASYNC_CLK + return true +} + +proc update_PARAM_VALUE.ENABLE_CHAR_REPLACE { PARAM_VALUE.ENABLE_CHAR_REPLACE } { + # Procedure called to update ENABLE_CHAR_REPLACE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ENABLE_CHAR_REPLACE { PARAM_VALUE.ENABLE_CHAR_REPLACE } { + # Procedure called to validate ENABLE_CHAR_REPLACE + return true +} + +proc update_PARAM_VALUE.ENABLE_FRAME_ALIGN_CHECK { PARAM_VALUE.ENABLE_FRAME_ALIGN_CHECK } { + # Procedure called to update ENABLE_FRAME_ALIGN_CHECK when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ENABLE_FRAME_ALIGN_CHECK { PARAM_VALUE.ENABLE_FRAME_ALIGN_CHECK } { + # Procedure called to validate ENABLE_FRAME_ALIGN_CHECK + return true +} + +proc update_PARAM_VALUE.ENABLE_FRAME_ALIGN_ERR_RESET { PARAM_VALUE.ENABLE_FRAME_ALIGN_ERR_RESET } { + # Procedure called to update ENABLE_FRAME_ALIGN_ERR_RESET when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ENABLE_FRAME_ALIGN_ERR_RESET { PARAM_VALUE.ENABLE_FRAME_ALIGN_ERR_RESET } { + # Procedure called to validate ENABLE_FRAME_ALIGN_ERR_RESET + return true +} + +proc update_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } { + # Procedure called to update LINK_MODE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } { + # Procedure called to validate LINK_MODE + return true +} + +proc update_PARAM_VALUE.NUM_INPUT_PIPELINE { PARAM_VALUE.NUM_INPUT_PIPELINE } { + # Procedure called to update NUM_INPUT_PIPELINE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_INPUT_PIPELINE { PARAM_VALUE.NUM_INPUT_PIPELINE } { + # Procedure called to validate NUM_INPUT_PIPELINE + return true +} + +proc update_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } { + # Procedure called to update NUM_LANES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } { + # Procedure called to validate NUM_LANES + return true +} + +proc update_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } { + # Procedure called to update NUM_LINKS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } { + # Procedure called to validate NUM_LINKS + return true +} + +proc update_PARAM_VALUE.NUM_OUTPUT_PIPELINE { PARAM_VALUE.NUM_OUTPUT_PIPELINE } { + # Procedure called to update NUM_OUTPUT_PIPELINE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OUTPUT_PIPELINE { PARAM_VALUE.NUM_OUTPUT_PIPELINE } { + # Procedure called to validate NUM_OUTPUT_PIPELINE + return true +} + +proc update_PARAM_VALUE.SYSREF_IOB { PARAM_VALUE.SYSREF_IOB } { + # Procedure called to update SYSREF_IOB when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SYSREF_IOB { PARAM_VALUE.SYSREF_IOB } { + # Procedure called to validate SYSREF_IOB + return true +} + +proc update_PARAM_VALUE.TPL_DATA_PATH_WIDTH { PARAM_VALUE.TPL_DATA_PATH_WIDTH } { + # Procedure called to update TPL_DATA_PATH_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TPL_DATA_PATH_WIDTH { PARAM_VALUE.TPL_DATA_PATH_WIDTH } { + # Procedure called to validate TPL_DATA_PATH_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.NUM_LANES { MODELPARAM_VALUE.NUM_LANES PARAM_VALUE.NUM_LANES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_LANES}] ${MODELPARAM_VALUE.NUM_LANES} +} + +proc update_MODELPARAM_VALUE.NUM_LINKS { MODELPARAM_VALUE.NUM_LINKS PARAM_VALUE.NUM_LINKS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_LINKS}] ${MODELPARAM_VALUE.NUM_LINKS} +} + +proc update_MODELPARAM_VALUE.NUM_INPUT_PIPELINE { MODELPARAM_VALUE.NUM_INPUT_PIPELINE PARAM_VALUE.NUM_INPUT_PIPELINE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_INPUT_PIPELINE}] ${MODELPARAM_VALUE.NUM_INPUT_PIPELINE} +} + +proc update_MODELPARAM_VALUE.NUM_OUTPUT_PIPELINE { MODELPARAM_VALUE.NUM_OUTPUT_PIPELINE PARAM_VALUE.NUM_OUTPUT_PIPELINE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OUTPUT_PIPELINE}] ${MODELPARAM_VALUE.NUM_OUTPUT_PIPELINE} +} + +proc update_MODELPARAM_VALUE.LINK_MODE { MODELPARAM_VALUE.LINK_MODE PARAM_VALUE.LINK_MODE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LINK_MODE}] ${MODELPARAM_VALUE.LINK_MODE} +} + +proc update_MODELPARAM_VALUE.DATA_PATH_WIDTH { MODELPARAM_VALUE.DATA_PATH_WIDTH PARAM_VALUE.DATA_PATH_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_PATH_WIDTH}] ${MODELPARAM_VALUE.DATA_PATH_WIDTH} +} + +proc update_MODELPARAM_VALUE.ENABLE_FRAME_ALIGN_CHECK { MODELPARAM_VALUE.ENABLE_FRAME_ALIGN_CHECK PARAM_VALUE.ENABLE_FRAME_ALIGN_CHECK } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ENABLE_FRAME_ALIGN_CHECK}] ${MODELPARAM_VALUE.ENABLE_FRAME_ALIGN_CHECK} +} + +proc update_MODELPARAM_VALUE.ENABLE_FRAME_ALIGN_ERR_RESET { MODELPARAM_VALUE.ENABLE_FRAME_ALIGN_ERR_RESET PARAM_VALUE.ENABLE_FRAME_ALIGN_ERR_RESET } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ENABLE_FRAME_ALIGN_ERR_RESET}] ${MODELPARAM_VALUE.ENABLE_FRAME_ALIGN_ERR_RESET} +} + +proc update_MODELPARAM_VALUE.ENABLE_CHAR_REPLACE { MODELPARAM_VALUE.ENABLE_CHAR_REPLACE PARAM_VALUE.ENABLE_CHAR_REPLACE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ENABLE_CHAR_REPLACE}] ${MODELPARAM_VALUE.ENABLE_CHAR_REPLACE} +} + +proc update_MODELPARAM_VALUE.ASYNC_CLK { MODELPARAM_VALUE.ASYNC_CLK PARAM_VALUE.ASYNC_CLK } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK}] ${MODELPARAM_VALUE.ASYNC_CLK} +} + +proc update_MODELPARAM_VALUE.TPL_DATA_PATH_WIDTH { MODELPARAM_VALUE.TPL_DATA_PATH_WIDTH PARAM_VALUE.TPL_DATA_PATH_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TPL_DATA_PATH_WIDTH}] ${MODELPARAM_VALUE.TPL_DATA_PATH_WIDTH} +} + diff --git a/adi_library/jesd204/jesd204_rx_static_config/Makefile b/adi_library/jesd204/jesd204_rx_static_config/Makefile new file mode 100644 index 00000000..1830f87a --- /dev/null +++ b/adi_library/jesd204/jesd204_rx_static_config/Makefile @@ -0,0 +1,18 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := jesd204_rx_static_config + +GENERIC_DEPS += jesd204_rx_static_config.v + +XILINX_DEPS += jesd204_rx_static_config_ip.tcl + +XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_rx_cfg_rtl.xml + +XILINX_INTERFACE_DEPS += jesd204/interfaces + +include ../../scripts/library.mk diff --git a/adi_library/jesd204/jesd204_rx_static_config/component.xml b/adi_library/jesd204/jesd204_rx_static_config/component.xml new file mode 100644 index 00000000..1a145800 --- /dev/null +++ b/adi_library/jesd204/jesd204_rx_static_config/component.xml @@ -0,0 +1,653 @@ + + + analog.com + user + jesd204_rx_static_config + 1.0 + + + rx_cfg + + + + + + + lanes_disable + + + cfg_lanes_disable + + + + + links_disable + + + cfg_links_disable + + + + + octets_per_multiframe + + + cfg_octets_per_multiframe + + + + + octets_per_frame + + + cfg_octets_per_frame + + + + + disable_char_replacement + + + cfg_disable_char_replacement + + + + + disable_scrambler + + + cfg_disable_scrambler + + + + + frame_align_err_threshold + + + cfg_frame_align_err_threshold + + + + + device_octets_per_multiframe + + + device_cfg_octets_per_multiframe + + + + + device_octets_per_frame + + + device_cfg_octets_per_frame + + + + + device_beats_per_multiframe + + + device_cfg_beats_per_multiframe + + + + + device_lmfc_offset + + + device_cfg_lmfc_offset + + + + + device_sysref_oneshot + + + device_cfg_sysref_oneshot + + + + + device_sysref_disable + + + device_cfg_sysref_disable + + + + + device_buffer_early_release + + + device_cfg_buffer_early_release + + + + + device_buffer_delay + + + device_cfg_buffer_delay + + + + + + rx_cfg_signal_clock + rx_cfg_signal_clock + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_BUSIF + rx_cfg + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + jesd204_rx_static_config + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 047d5aaf + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + jesd204_rx_static_config + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 047d5aaf + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + c55d0be5 + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_lanes_disable + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_links_disable + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_octets_per_multiframe + + out + + 9 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_octets_per_frame + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_disable_scrambler + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_disable_char_replacement + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_frame_align_err_threshold + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_octets_per_multiframe + + out + + 9 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_octets_per_frame + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_beats_per_multiframe + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_lmfc_offset + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_sysref_oneshot + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_sysref_disable + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_buffer_early_release + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_buffer_delay + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + NUM_LANES + Num Lanes + 1 + + + NUM_LINKS + Num Links + 1 + + + OCTETS_PER_FRAME + Octets Per Frame + 1 + + + FRAMES_PER_MULTIFRAME + Frames Per Multiframe + 32 + + + SCR + Scr + 1 + + + BUFFER_EARLY_RELEASE + Buffer Early Release + 0 + + + LINK_MODE + Link Mode + 1 + + + SYSREF_DISABLE + Sysref Disable + 0 + + + SYSREF_ONE_SHOT + Sysref One Shot + 0 + + + DATA_PATH_WIDTH + Data Path Width + 4 + + + TPL_DATA_PATH_WIDTH + Tpl Data Path Width + 4 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + jesd204_rx_static_config.v + verilogSource + CHECKSUM_047d5aaf + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + jesd204_rx_static_config.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/jesd204_rx_static_config_v1_0.tcl + tclSource + CHECKSUM_c55d0be5 + XGUI_VERSION_2 + + + + jesd204_rx_static_config_v1_0 + + + NUM_LANES + Num Lanes + 1 + + + NUM_LINKS + Num Links + 1 + + + OCTETS_PER_FRAME + Octets Per Frame + 1 + + + FRAMES_PER_MULTIFRAME + Frames Per Multiframe + 32 + + + SCR + Scr + 1 + + + BUFFER_EARLY_RELEASE + Buffer Early Release + 0 + + + LINK_MODE + Link Mode + 1 + + + SYSREF_DISABLE + Sysref Disable + 0 + + + SYSREF_ONE_SHOT + Sysref One Shot + 0 + + + DATA_PATH_WIDTH + Data Path Width + 4 + + + TPL_DATA_PATH_WIDTH + Tpl Data Path Width + 4 + + + Component_Name + jesd204_rx_static_config_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + jesd204_rx_static_config_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:51:47Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.v b/adi_library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.v new file mode 100755 index 00000000..8c721bed --- /dev/null +++ b/adi_library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.v @@ -0,0 +1,61 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_rx_static_config #( + parameter NUM_LANES = 1, + parameter NUM_LINKS = 1, + parameter OCTETS_PER_FRAME = 1, + parameter FRAMES_PER_MULTIFRAME = 32, + parameter SCR = 1, + parameter BUFFER_EARLY_RELEASE = 0, + parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B + parameter SYSREF_DISABLE = 0, + parameter SYSREF_ONE_SHOT = 0, + /* Only 4, 8 are supported at the moment for 8b/10b and 8 for 64b */ + parameter DATA_PATH_WIDTH = LINK_MODE == 2 ? 8 : 4, + parameter TPL_DATA_PATH_WIDTH = LINK_MODE == 2 ? 8 : 4 +) ( + input clk, + + output [NUM_LANES-1:0] cfg_lanes_disable, + output [NUM_LINKS-1:0] cfg_links_disable, + output [9:0] cfg_octets_per_multiframe, + output [7:0] cfg_octets_per_frame, + output cfg_disable_scrambler, + output cfg_disable_char_replacement, + output [7:0] cfg_frame_align_err_threshold, + + output [9:0] device_cfg_octets_per_multiframe, + output [7:0] device_cfg_octets_per_frame, + output [7:0] device_cfg_beats_per_multiframe, + output [7:0] device_cfg_lmfc_offset, + output device_cfg_sysref_oneshot, + output device_cfg_sysref_disable, + output device_cfg_buffer_early_release, + output [7:0] device_cfg_buffer_delay +); + + assign cfg_octets_per_multiframe = (FRAMES_PER_MULTIFRAME * OCTETS_PER_FRAME) - 1; + assign cfg_octets_per_frame = OCTETS_PER_FRAME - 1; + assign device_cfg_octets_per_multiframe = (FRAMES_PER_MULTIFRAME * OCTETS_PER_FRAME) - 1; + assign device_cfg_octets_per_frame = OCTETS_PER_FRAME - 1; + assign device_cfg_beats_per_multiframe = ((FRAMES_PER_MULTIFRAME * OCTETS_PER_FRAME) / + TPL_DATA_PATH_WIDTH) - 1; + assign device_cfg_lmfc_offset = 1; + assign device_cfg_sysref_oneshot = SYSREF_ONE_SHOT; + assign device_cfg_sysref_disable = SYSREF_DISABLE; + assign device_cfg_buffer_delay = 'h0; + assign device_cfg_buffer_early_release = BUFFER_EARLY_RELEASE; + assign cfg_lanes_disable = {NUM_LANES{1'b0}}; + assign cfg_links_disable = {NUM_LINKS{1'b0}}; + assign cfg_disable_scrambler = SCR ? 1'b0 : 1'b1; + assign cfg_disable_char_replacement = 1'b0; + assign cfg_frame_align_err_threshold = 8'd4; + +endmodule diff --git a/adi_library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.xpr b/adi_library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.xpr new file mode 100644 index 00000000..24742546 --- /dev/null +++ b/adi_library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config.xpr @@ -0,0 +1,399 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config_ip.tcl b/adi_library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config_ip.tcl new file mode 100755 index 00000000..a21e8741 --- /dev/null +++ b/adi_library/jesd204/jesd204_rx_static_config/jesd204_rx_static_config_ip.tcl @@ -0,0 +1,38 @@ +############################################################################### +## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create jesd204_rx_static_config +adi_ip_files jesd204_rx_static_config [list \ + "jesd204_rx_static_config.v" \ +] + +adi_ip_properties_lite jesd204_rx_static_config + +adi_add_bus "rx_cfg" "master" \ + "analog.com:interface:jesd204_rx_cfg_rtl:1.0" \ + "analog.com:interface:jesd204_rx_cfg:1.0" \ + { \ + { "cfg_lanes_disable" "lanes_disable" } \ + { "cfg_links_disable" "links_disable" } \ + { "cfg_octets_per_multiframe" "octets_per_multiframe" } \ + { "cfg_octets_per_frame" "octets_per_frame" } \ + { "cfg_disable_char_replacement" "disable_char_replacement" } \ + { "cfg_disable_scrambler" "disable_scrambler" } \ + { "cfg_frame_align_err_threshold" "frame_align_err_threshold" } \ + { "device_cfg_octets_per_multiframe" "device_octets_per_multiframe" } \ + { "device_cfg_octets_per_frame" "device_octets_per_frame" } \ + { "device_cfg_beats_per_multiframe" "device_beats_per_multiframe" } \ + { "device_cfg_lmfc_offset" "device_lmfc_offset" } \ + { "device_cfg_sysref_oneshot" "device_sysref_oneshot" } \ + { "device_cfg_sysref_disable" "device_sysref_disable" } \ + { "device_cfg_buffer_early_release" "device_buffer_early_release" } \ + { "device_cfg_buffer_delay" "device_buffer_delay" } \ + } +adi_add_bus_clock "clk" "rx_cfg" + +ipx::save_core [ipx::current_core] diff --git a/adi_library/jesd204/jesd204_rx_static_config/xgui/jesd204_rx_static_config_v1_0.tcl b/adi_library/jesd204/jesd204_rx_static_config/xgui/jesd204_rx_static_config_v1_0.tcl new file mode 100644 index 00000000..2023f547 --- /dev/null +++ b/adi_library/jesd204/jesd204_rx_static_config/xgui/jesd204_rx_static_config_v1_0.tcl @@ -0,0 +1,175 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "BUFFER_EARLY_RELEASE" -parent ${Page_0} + ipgui::add_param $IPINST -name "DATA_PATH_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "FRAMES_PER_MULTIFRAME" -parent ${Page_0} + ipgui::add_param $IPINST -name "LINK_MODE" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_LANES" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_LINKS" -parent ${Page_0} + ipgui::add_param $IPINST -name "OCTETS_PER_FRAME" -parent ${Page_0} + ipgui::add_param $IPINST -name "SCR" -parent ${Page_0} + ipgui::add_param $IPINST -name "SYSREF_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "SYSREF_ONE_SHOT" -parent ${Page_0} + ipgui::add_param $IPINST -name "TPL_DATA_PATH_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.BUFFER_EARLY_RELEASE { PARAM_VALUE.BUFFER_EARLY_RELEASE } { + # Procedure called to update BUFFER_EARLY_RELEASE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BUFFER_EARLY_RELEASE { PARAM_VALUE.BUFFER_EARLY_RELEASE } { + # Procedure called to validate BUFFER_EARLY_RELEASE + return true +} + +proc update_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH } { + # Procedure called to update DATA_PATH_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH } { + # Procedure called to validate DATA_PATH_WIDTH + return true +} + +proc update_PARAM_VALUE.FRAMES_PER_MULTIFRAME { PARAM_VALUE.FRAMES_PER_MULTIFRAME } { + # Procedure called to update FRAMES_PER_MULTIFRAME when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FRAMES_PER_MULTIFRAME { PARAM_VALUE.FRAMES_PER_MULTIFRAME } { + # Procedure called to validate FRAMES_PER_MULTIFRAME + return true +} + +proc update_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } { + # Procedure called to update LINK_MODE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } { + # Procedure called to validate LINK_MODE + return true +} + +proc update_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } { + # Procedure called to update NUM_LANES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } { + # Procedure called to validate NUM_LANES + return true +} + +proc update_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } { + # Procedure called to update NUM_LINKS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } { + # Procedure called to validate NUM_LINKS + return true +} + +proc update_PARAM_VALUE.OCTETS_PER_FRAME { PARAM_VALUE.OCTETS_PER_FRAME } { + # Procedure called to update OCTETS_PER_FRAME when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OCTETS_PER_FRAME { PARAM_VALUE.OCTETS_PER_FRAME } { + # Procedure called to validate OCTETS_PER_FRAME + return true +} + +proc update_PARAM_VALUE.SCR { PARAM_VALUE.SCR } { + # Procedure called to update SCR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SCR { PARAM_VALUE.SCR } { + # Procedure called to validate SCR + return true +} + +proc update_PARAM_VALUE.SYSREF_DISABLE { PARAM_VALUE.SYSREF_DISABLE } { + # Procedure called to update SYSREF_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SYSREF_DISABLE { PARAM_VALUE.SYSREF_DISABLE } { + # Procedure called to validate SYSREF_DISABLE + return true +} + +proc update_PARAM_VALUE.SYSREF_ONE_SHOT { PARAM_VALUE.SYSREF_ONE_SHOT } { + # Procedure called to update SYSREF_ONE_SHOT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SYSREF_ONE_SHOT { PARAM_VALUE.SYSREF_ONE_SHOT } { + # Procedure called to validate SYSREF_ONE_SHOT + return true +} + +proc update_PARAM_VALUE.TPL_DATA_PATH_WIDTH { PARAM_VALUE.TPL_DATA_PATH_WIDTH } { + # Procedure called to update TPL_DATA_PATH_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TPL_DATA_PATH_WIDTH { PARAM_VALUE.TPL_DATA_PATH_WIDTH } { + # Procedure called to validate TPL_DATA_PATH_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.NUM_LANES { MODELPARAM_VALUE.NUM_LANES PARAM_VALUE.NUM_LANES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_LANES}] ${MODELPARAM_VALUE.NUM_LANES} +} + +proc update_MODELPARAM_VALUE.NUM_LINKS { MODELPARAM_VALUE.NUM_LINKS PARAM_VALUE.NUM_LINKS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_LINKS}] ${MODELPARAM_VALUE.NUM_LINKS} +} + +proc update_MODELPARAM_VALUE.OCTETS_PER_FRAME { MODELPARAM_VALUE.OCTETS_PER_FRAME PARAM_VALUE.OCTETS_PER_FRAME } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OCTETS_PER_FRAME}] ${MODELPARAM_VALUE.OCTETS_PER_FRAME} +} + +proc update_MODELPARAM_VALUE.FRAMES_PER_MULTIFRAME { MODELPARAM_VALUE.FRAMES_PER_MULTIFRAME PARAM_VALUE.FRAMES_PER_MULTIFRAME } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FRAMES_PER_MULTIFRAME}] ${MODELPARAM_VALUE.FRAMES_PER_MULTIFRAME} +} + +proc update_MODELPARAM_VALUE.SCR { MODELPARAM_VALUE.SCR PARAM_VALUE.SCR } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SCR}] ${MODELPARAM_VALUE.SCR} +} + +proc update_MODELPARAM_VALUE.BUFFER_EARLY_RELEASE { MODELPARAM_VALUE.BUFFER_EARLY_RELEASE PARAM_VALUE.BUFFER_EARLY_RELEASE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BUFFER_EARLY_RELEASE}] ${MODELPARAM_VALUE.BUFFER_EARLY_RELEASE} +} + +proc update_MODELPARAM_VALUE.LINK_MODE { MODELPARAM_VALUE.LINK_MODE PARAM_VALUE.LINK_MODE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LINK_MODE}] ${MODELPARAM_VALUE.LINK_MODE} +} + +proc update_MODELPARAM_VALUE.SYSREF_DISABLE { MODELPARAM_VALUE.SYSREF_DISABLE PARAM_VALUE.SYSREF_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SYSREF_DISABLE}] ${MODELPARAM_VALUE.SYSREF_DISABLE} +} + +proc update_MODELPARAM_VALUE.SYSREF_ONE_SHOT { MODELPARAM_VALUE.SYSREF_ONE_SHOT PARAM_VALUE.SYSREF_ONE_SHOT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SYSREF_ONE_SHOT}] ${MODELPARAM_VALUE.SYSREF_ONE_SHOT} +} + +proc update_MODELPARAM_VALUE.DATA_PATH_WIDTH { MODELPARAM_VALUE.DATA_PATH_WIDTH PARAM_VALUE.DATA_PATH_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_PATH_WIDTH}] ${MODELPARAM_VALUE.DATA_PATH_WIDTH} +} + +proc update_MODELPARAM_VALUE.TPL_DATA_PATH_WIDTH { MODELPARAM_VALUE.TPL_DATA_PATH_WIDTH PARAM_VALUE.TPL_DATA_PATH_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TPL_DATA_PATH_WIDTH}] ${MODELPARAM_VALUE.TPL_DATA_PATH_WIDTH} +} + diff --git a/adi_library/jesd204/jesd204_soft_pcs_rx/.timestamp_intel b/adi_library/jesd204/jesd204_soft_pcs_rx/.timestamp_intel new file mode 100644 index 00000000..e69de29b diff --git a/adi_library/jesd204/jesd204_soft_pcs_rx/Makefile b/adi_library/jesd204/jesd204_soft_pcs_rx/Makefile new file mode 100644 index 00000000..0bf0bc46 --- /dev/null +++ b/adi_library/jesd204/jesd204_soft_pcs_rx/Makefile @@ -0,0 +1,15 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := jesd204_soft_pcs_rx + +GENERIC_DEPS += jesd204_8b10b_decoder.v +GENERIC_DEPS += jesd204_pattern_align.v +GENERIC_DEPS += jesd204_soft_pcs_rx.v + +INTEL_DEPS += jesd204_soft_pcs_rx_hw.tcl + +include ../../scripts/library.mk diff --git a/adi_library/jesd204/jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v b/adi_library/jesd204/jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v new file mode 100644 index 00000000..c9cb8c92 --- /dev/null +++ b/adi_library/jesd204/jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v @@ -0,0 +1,379 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_8b10b_decoder ( + input in_disparity, + input [9:0] in_char, + + output [7:0] out_char, + output out_charisk, + output out_notintable, + output reg out_disperr, + output reg out_disparity +); + + /* + * Only supports the subset of 8b10b that is used by JESD204. + * If non-supported control characters are supplied the output is undefined. + */ + + reg [4:0] data5b; + reg notintable5b; + reg [1:0] disparity5b; + reg ignore5b; + reg [2:0] data3b; + reg notintable3b; + reg [1:0] disparity3b; + reg ignore3b; + reg [1:0] total_disparity; + reg notintable_disparity; + + // Only detect K28.X + wire charisk = in_char[5:0] == 6'b000011 || in_char[5:0] == 6'b111100; + + always @(*) begin + notintable5b = 1'b0; + disparity5b = 2'b00; + ignore5b = 1'b0; + + case (in_char[5:0]) + 6'b000011: begin + data5b = 5'd28; + disparity5b = 2'b11; + end + 6'b111100: begin + data5b = 5'd28; + disparity5b = 2'b01; + end + 6'b000110: begin + data5b = 5'd00; + disparity5b = 2'b11; + end + 6'b111001: begin + data5b = 5'd00; + disparity5b = 2'b01; + end + 6'b010001: begin + data5b = 5'd01; + disparity5b = 2'b11; + end + 6'b101110: begin + data5b = 5'd01; + disparity5b = 2'b01; + end + 6'b010010: begin + data5b = 5'd02; + disparity5b = 2'b11; + end + 6'b101101: begin + data5b = 5'd02; + disparity5b = 2'b01; + end + 6'b100011: begin + data5b = 5'd03; + end + 6'b010100: begin + data5b = 5'd04; + disparity5b = 2'b11; + end + 6'b101011: begin + data5b = 5'd04; + disparity5b = 2'b01; + end + 6'b100101: begin + data5b = 5'd05; + end + 6'b100110: begin + data5b = 5'd06; + end + 6'b000111: begin + data5b = 5'd7; + disparity5b = 2'b11; + ignore5b = 1'b1; + end + 6'b111000: begin + data5b = 5'd7; + disparity5b = 2'b01; + ignore5b = 1'b1; + end + 6'b011000: begin + data5b = 5'd8; + disparity5b = 2'b11; + end + 6'b100111: begin + data5b = 5'd8; + disparity5b = 2'b01; + end + 6'b101001: begin + data5b = 5'd9; + end + 6'b101010: begin + data5b = 5'd10; + end + 6'b001011: begin + data5b = 5'd11; + end + 6'b101100: begin + data5b = 5'd12; + end + 6'b001101: begin + data5b = 5'd13; + end + 6'b001110: begin + data5b = 5'd14; + end + 6'b000101: begin + data5b = 5'd15; + disparity5b = 2'b11; + end + 6'b111010: begin + data5b = 5'd15; + disparity5b = 2'b01; + end + 6'b001001: begin + data5b = 5'd16; + disparity5b = 2'b11; + end + 6'b110110: begin + data5b = 5'd16; + disparity5b = 2'b01; + end + 6'b110001: begin + data5b = 5'd17; + end + 6'b110010: begin + data5b = 5'd18; + end + 6'b010011: begin + data5b = 5'd19; + end + 6'b110100: begin + data5b = 5'd20; + end + 6'b010101: begin + data5b = 5'd21; + end + 6'b010110: begin + data5b = 5'd22; + end + 6'b101000: begin + data5b = 5'd23; + disparity5b = 2'b11; + end + 6'b010111: begin + data5b = 5'd23; + disparity5b = 2'b01; + end + 6'b001100: begin + data5b = 5'd24; + disparity5b = 2'b11; + end + 6'b110011: begin + data5b = 5'd24; + disparity5b = 2'b01; + end + 6'b011001: begin + data5b = 5'd25; + end + 6'b011010: begin + data5b = 5'd26; + end + 6'b100100: begin + data5b = 5'd27; + disparity5b = 2'b11; + end + 6'b011011: begin + data5b = 5'd27; + disparity5b = 2'b01; + end + 6'b011100: begin + data5b = 5'd28; + end + 6'b100010: begin + data5b = 5'd29; + disparity5b = 2'b11; + end + 6'b011101: begin + data5b = 5'd29; + disparity5b = 2'b01; + end + 6'b100001: begin + data5b = 5'd30; + disparity5b = 2'b11; + end + 6'b011110: begin + data5b = 5'd30; + disparity5b = 2'b01; + end + 6'b001010: begin + data5b = 5'd31; + disparity5b = 2'b11; + end + 6'b110101: begin + data5b = 5'd31; + disparity5b = 2'b01; + end + default: begin + data5b = 5'd00; + notintable5b = 1'b1; + end + endcase + end + + always @(*) begin + ignore3b = 1'b0; + + case (in_char[9:6]) + 4'b0010: begin + disparity3b = 2'b11; + end + 4'b1101: begin + disparity3b = 2'b01; + end + 4'b1100: begin + disparity3b = 2'b11; + ignore3b = 1'b1; + end + 4'b0011: begin + disparity3b = 2'b01; + ignore3b = 1'b1; + end + 4'b0100: begin + disparity3b = 2'b11; + end + 4'b1011: begin + disparity3b = 2'b01; + end + 4'b1000: begin + disparity3b = 2'b11; + end + 4'b0111: begin + disparity3b = 2'b01; + end + 4'b0001: begin + disparity3b = 2'b11; + end + 4'b1110: begin + disparity3b = 2'b01; + end + default: begin + disparity3b = 2'b00; + end + endcase + end + + always @(*) begin + notintable3b = 1'b0; + + if (charisk == 1'b1) begin + case (in_char[9:6] ^ {4{in_char[5]}}) + 4'b1101: begin + data3b = 3'd0; + end + 4'b0011: begin + data3b = 3'd3; + end + 4'b1011: begin + data3b = 3'd4; + end + 4'b1010: begin + data3b = 3'd5; + end + 4'b1110: begin + data3b = 3'd7; + end + default: begin + data3b = 3'd0; + notintable3b = 1'b1; + end + endcase + end else begin + case (in_char[9:6]) + 4'b0010: begin + data3b = 3'd0; + end + 4'b1101: begin + data3b = 3'd0; + end + 4'b1001: begin + data3b = 3'd1; + end + 4'b1010: begin + data3b = 3'd2; + end + 4'b1100: begin + data3b = 3'd3; + end + 4'b0011: begin + data3b = 3'd3; + end + 4'b0100: begin + data3b = 3'd4; + end + 4'b1011: begin + data3b = 3'd4; + end + 4'b0101: begin + data3b = 3'd5; + end + 4'b0110: begin + data3b = 3'd6; + end + 4'b1000: begin + data3b = 3'd7; + notintable3b = in_char[5:4] == 2'b00; + end + 4'b0111: begin + data3b = 3'd7; + notintable3b = in_char[5:4] == 2'b11; + end + 4'b0001: begin + data3b = 3'd7; + notintable3b = in_char[5:4] != 2'b00; + end + 4'b1110: begin + data3b = 3'd7; + notintable3b = in_char[5:4] != 2'b11; + end + default: begin + data3b = 3'd0; + notintable3b = 1'b1; + end + endcase + end + end + + always @(*) begin + if (disparity3b == disparity5b && disparity3b != 2'b00) begin + notintable_disparity = 1'b1; + end else begin + notintable_disparity = 1'b0; + end + end + + always @(*) begin + total_disparity = (ignore3b ? 2'b00 : disparity3b) ^ (ignore5b ? 2'b00 : disparity5b); + + if (total_disparity[0] == 1'b0 || out_notintable == 1'b1) begin + out_disparity = in_disparity; + out_disperr = 1'b0; + end else if (total_disparity[1] == 1'b1) begin + out_disparity = 1'b0; + out_disperr = ~in_disparity; + end else begin + out_disparity = 1'b1; + out_disperr = in_disparity; + end + end + + assign out_char = {data3b,data5b}; + assign out_charisk = charisk; + assign out_notintable = notintable5b | notintable3b | notintable_disparity; + +endmodule diff --git a/adi_library/jesd204/jesd204_soft_pcs_rx/jesd204_pattern_align.v b/adi_library/jesd204/jesd204_soft_pcs_rx/jesd204_pattern_align.v new file mode 100644 index 00000000..0ccfd1ce --- /dev/null +++ b/adi_library/jesd204/jesd204_soft_pcs_rx/jesd204_pattern_align.v @@ -0,0 +1,118 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_pattern_align #( + parameter DATA_PATH_WIDTH = 4 +) ( + input clk, + input reset, + + input patternalign_en, + + input [DATA_PATH_WIDTH*10-1:0] in_data, + output [DATA_PATH_WIDTH*10-1:0] out_data +); + + localparam [9:0] PATTERN_P = 10'b1010000011; + localparam [9:0] PATTERN_N = 10'b0101111100; + + reg [1:0] match_counter = 2'h0; + reg pattern_sync = 1'b0; + reg pattern_match = 1'b0; + + reg [3:0] align = 4'h0; + reg [1:0] cooldown = 2'h3; + + reg [8:0] data_d1 = 9'h00; + reg [DATA_PATH_WIDTH*10+2:0] aligned_data_stage1; + reg [DATA_PATH_WIDTH*10-1:0] aligned_data_stage2; + wire [(DATA_PATH_WIDTH+1)*10-2:0] full_data; + + assign full_data = {in_data,data_d1}; + assign out_data = aligned_data_stage2; + + /* 2-stage cascade of 3:1 and 4:1 muxes */ + + integer i; + + always @(*) begin + for (i = 0; i < DATA_PATH_WIDTH*10+3; i = i + 1) begin + if (i < DATA_PATH_WIDTH*10+1) begin + case (align[3:2]) + 2'b00: aligned_data_stage1[i] = full_data[i]; + 2'b01: aligned_data_stage1[i] = full_data[i+4]; + 2'b10: aligned_data_stage1[i] = full_data[i+8]; + default: aligned_data_stage1[i] = 1'b0; + endcase + end else begin + case (align[2]) + 1'b0: aligned_data_stage1[i] = full_data[i]; + default: aligned_data_stage1[i] = full_data[i+4]; + endcase + end + end + + aligned_data_stage2 = aligned_data_stage1[align[1:0]+:DATA_PATH_WIDTH*10]; + end + + always @(posedge clk) begin + data_d1 <= in_data[DATA_PATH_WIDTH*10-9+:9]; + end + + always @(posedge clk) begin + if (out_data[9:0] == PATTERN_P || out_data[9:0] == PATTERN_N) begin + pattern_match <= 1'b1; + end else begin + pattern_match <= 1'b0; + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + cooldown <= 2'h3; + align <= 4'h0; + end else begin + if (cooldown != 2'h0) begin + cooldown <= cooldown - 1'b1; + end else if (patternalign_en == 1'b1 && pattern_sync == 1'b0 && + pattern_match == 1'b0) begin + cooldown <= 2'h3; + if (align == 'h9) begin + align <= 4'h0; + end else begin + align <= align + 1'b1; + end + end + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + pattern_sync <= 1'b0; + match_counter <= 2'h0; + end else begin + if (match_counter == 2'h0) begin + pattern_sync <= 1'b0; + end else if (match_counter == 2'h3) begin + pattern_sync <= 1'b1; + end + + if (pattern_match == 1'b1) begin + if (match_counter != 2'h3) begin + match_counter <= match_counter + 1'b1; + end + end else begin + if (match_counter != 2'h0) begin + match_counter <= match_counter - 1'b1; + end + end + end + end + +endmodule diff --git a/adi_library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v b/adi_library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v new file mode 100644 index 00000000..2da67b43 --- /dev/null +++ b/adi_library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v @@ -0,0 +1,118 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_soft_pcs_rx #( + parameter NUM_LANES = 1, + parameter DATA_PATH_WIDTH = 4, + parameter REGISTER_INPUTS = 0, + parameter INVERT_INPUTS = 0 +) ( + input clk, + input reset, + + input patternalign_en, + + input [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data, + + output reg [NUM_LANES*DATA_PATH_WIDTH*8-1:0] char, + output reg [NUM_LANES*DATA_PATH_WIDTH-1:0] charisk, + output reg [NUM_LANES*DATA_PATH_WIDTH-1:0] notintable, + output reg [NUM_LANES*DATA_PATH_WIDTH-1:0] disperr +); + + localparam LANE_DATA_WIDTH = DATA_PATH_WIDTH * 10; + + wire [NUM_LANES*LANE_DATA_WIDTH-1:0] data_aligned; + + wire [NUM_LANES*DATA_PATH_WIDTH*8-1:0] char_s; + wire [NUM_LANES*DATA_PATH_WIDTH-1:0] charisk_s; + wire [NUM_LANES*DATA_PATH_WIDTH-1:0] notintable_s; + wire [NUM_LANES*DATA_PATH_WIDTH-1:0] disperr_s; + + reg [NUM_LANES-1:0] disparity = {NUM_LANES{1'b0}}; + wire [DATA_PATH_WIDTH:0] disparity_chain[0:NUM_LANES-1]; + + wire [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data_s; + wire patternalign_en_s; + + always @(posedge clk) begin + char <= char_s; + charisk <= charisk_s; + notintable <= notintable_s; + disperr <= disperr_s; + end + + generate + genvar lane; + genvar i; + if (REGISTER_INPUTS > 0) begin + reg patternalign_en_r; + reg [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data_r; + always @(posedge clk) begin + patternalign_en_r <= patternalign_en; + data_r <= data; + end + assign patternalign_en_s = patternalign_en_r; + assign data_s = data_r; + end else begin + assign patternalign_en_s = patternalign_en; + assign data_s = data; + end + + for (lane = 0; lane < NUM_LANES; lane = lane + 1) begin: gen_lane + + jesd204_pattern_align #( + .DATA_PATH_WIDTH(DATA_PATH_WIDTH) + ) i_pattern_align ( + .clk(clk), + .reset(reset), + + .patternalign_en(patternalign_en_s), + .in_data(data_s[LANE_DATA_WIDTH*lane+:LANE_DATA_WIDTH]), + .out_data(data_aligned[LANE_DATA_WIDTH*lane+:LANE_DATA_WIDTH])); + + assign disparity_chain[lane][0] = disparity[lane]; + + always @(posedge clk) begin + if (reset == 1'b1) begin + disparity[lane] <= 1'b0; + end else begin + disparity[lane] <= disparity_chain[lane][DATA_PATH_WIDTH]; + end + end + + for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_dpw + localparam j = DATA_PATH_WIDTH * lane + i; + wire [9:0] in_char; + if (REGISTER_INPUTS > 1) begin + reg [9:0] in_char_r = 10'b0; + always @(posedge clk) begin + in_char_r <= INVERT_INPUTS ? ~data_aligned[j*10+:10] : + data_aligned[j*10+:10]; + end + assign in_char = in_char_r; + end else begin + assign in_char = INVERT_INPUTS ? ~data_aligned[j*10+:10] : + data_aligned[j*10+:10]; + end + + jesd204_8b10b_decoder i_dec ( + .in_char(in_char), + .out_char(char_s[j*8+:8]), + .out_charisk(charisk_s[j]), + .out_notintable(notintable_s[j]), + .out_disperr(disperr_s[j]), + + .in_disparity(disparity_chain[lane][i]), + .out_disparity(disparity_chain[lane][i+1])); + end + end + endgenerate + +endmodule diff --git a/adi_library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl b/adi_library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl new file mode 100644 index 00000000..2995ba2e --- /dev/null +++ b/adi_library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl @@ -0,0 +1,53 @@ +############################################################################### +## Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +package require qsys 14.0 + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl + +ad_ip_create jesd204_soft_pcs_rx "ADI JESD204 Transmit Soft PCS" + +ad_ip_parameter REGISTER_INPUTS INTEGER 0 +ad_ip_parameter INVERT_INPUTS INTEGER 0 + +set_module_property INTERNAL true + +# files + +ad_ip_files jesd204_soft_pcs_rx [list \ + jesd204_soft_pcs_rx.v \ + jesd204_pattern_align.v \ + jesd204_8b10b_decoder.v \ +] + +# clock + +add_interface clock clock end +add_interface_port clock clk clk Input 1 + +# reset + +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT + +add_interface_port reset reset reset Input 1 + +# interfaces + +add_interface rx_phy conduit start +#set_interface_property rx_phy associatedClock clock +#set_interface_property rx_phy associatedReset reset +add_interface_port rx_phy char char Output 32 +add_interface_port rx_phy charisk charisk Output 4 +add_interface_port rx_phy disperr disperr Output 4 +add_interface_port rx_phy notintable notintable Output 4 +add_interface_port rx_phy patternalign_en patternalign_en Input 1 + +add_interface rx_raw_data conduit end +#set_interface_property rx_raw_data associatedClock clock +#set_interface_property rx_raw_data associatedReset reset +add_interface_port rx_raw_data data raw_data Input 40 diff --git a/adi_library/jesd204/jesd204_soft_pcs_tx/.timestamp_intel b/adi_library/jesd204/jesd204_soft_pcs_tx/.timestamp_intel new file mode 100644 index 00000000..e69de29b diff --git a/adi_library/jesd204/jesd204_soft_pcs_tx/Makefile b/adi_library/jesd204/jesd204_soft_pcs_tx/Makefile new file mode 100644 index 00000000..accf3aa6 --- /dev/null +++ b/adi_library/jesd204/jesd204_soft_pcs_tx/Makefile @@ -0,0 +1,14 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := jesd204_soft_pcs_tx + +GENERIC_DEPS += jesd204_8b10b_encoder.v +GENERIC_DEPS += jesd204_soft_pcs_tx.v + +INTEL_DEPS += jesd204_soft_pcs_tx_hw.tcl + +include ../../scripts/library.mk diff --git a/adi_library/jesd204/jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v b/adi_library/jesd204/jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v new file mode 100644 index 00000000..4c12c8ad --- /dev/null +++ b/adi_library/jesd204/jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v @@ -0,0 +1,293 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_8b10b_encoder ( + input in_disparity, + input [7:0] in_char, + input in_charisk, + + output [9:0] out_char, + output out_disparity +); + + /* + * Only supports the subset of 8b10b that is used by JESD204. + * If non-supported control characters are supplied the output is undefined. + */ + + reg [5:0] data6b; + reg [5:0] out6b; + reg may_invert6b; + reg disparity6b; + reg [3:0] data4b; + reg [3:0] out4b; + reg may_invert4b; + reg disparity4b; + wire disparity4b_in; + reg alt7; + + always @(*) begin + if (in_charisk == 1'b1) begin + // Assume K28.x + data6b = 6'b000011; + may_invert6b = 1'b1; + disparity6b = 1'b1; + end else begin + case (in_char[4:0]) + 5'd00: begin + data6b = 6'b000110; + may_invert6b = 1'b1; + disparity6b = 1'b1; + end + 5'd01: begin + data6b = 6'b010001; + may_invert6b = 1'b1; + disparity6b = 1'b1; + end + 5'd02: begin + data6b = 6'b010010; + may_invert6b = 1'b1; + disparity6b = 1'b1; + end + 5'd03: begin + data6b = 6'b100011; + may_invert6b = 1'b0; + disparity6b = 1'b0; + end + 5'd04: begin + data6b = 6'b010100; + may_invert6b = 1'b1; + disparity6b = 1'b1; + end + 5'd05: begin + data6b = 6'b100101; + may_invert6b = 1'b0; + disparity6b = 1'b0; + end + 5'd06: begin + data6b = 6'b100110; + may_invert6b = 1'b0; + disparity6b = 1'b0; + end + 5'd07: begin + data6b = 6'b111000; + may_invert6b = 1'b1; + disparity6b = 1'b0; + end + 5'd08: begin + data6b = 6'b011000; + may_invert6b = 1'b1; + disparity6b = 1'b1; + end + 5'd09: begin + data6b = 6'b101001; + may_invert6b = 1'b0; + disparity6b = 1'b0; + end + 5'd10: begin + data6b = 6'b101010; + may_invert6b = 1'b0; + disparity6b = 1'b0; + end + 5'd11: begin + data6b = 6'b001011; + may_invert6b = 1'b0; + disparity6b = 1'b0; + end + 5'd12: begin + data6b = 6'b101100; + may_invert6b = 1'b0; + disparity6b = 1'b0; + end + 5'd13: begin + data6b = 6'b001101; + may_invert6b = 1'b0; + disparity6b = 1'b0; + end + 5'd14: begin + data6b = 6'b001110; + may_invert6b = 1'b0; + disparity6b = 1'b0; + end + 5'd15: begin + data6b = 6'b000101; + may_invert6b = 1'b1; + disparity6b = 1'b1; + end + 5'd16: begin + data6b = 6'b001001; + may_invert6b = 1'b1; + disparity6b = 1'b1; + end + 5'd17: begin + data6b = 6'b110001; + may_invert6b = 1'b0; + disparity6b = 1'b0; + end + 5'd18: begin + data6b = 6'b110010; + may_invert6b = 1'b0; + disparity6b = 1'b0; + end + 5'd19: begin + data6b = 6'b010011; + may_invert6b = 1'b0; + disparity6b = 1'b0; + end + 5'd20: begin + data6b = 6'b110100; + may_invert6b = 1'b0; + disparity6b = 1'b0; + end + 5'd21: begin + data6b = 6'b010101; + may_invert6b = 1'b0; + disparity6b = 1'b0; + end + 5'd22: begin + data6b = 6'b010110; + may_invert6b = 1'b0; + disparity6b = 1'b0; + end + 5'd23: begin + data6b = 6'b101000; + may_invert6b = 1'b1; + disparity6b = 1'b1; + end + 5'd24: begin + data6b = 6'b001100; + may_invert6b = 1'b1; + disparity6b = 1'b1; + end + 5'd25: begin + data6b = 6'b011001; + may_invert6b = 1'b0; + disparity6b = 1'b0; + end + 5'd26: begin + data6b = 6'b011010; + may_invert6b = 1'b0; + disparity6b = 1'b0; + end + 5'd27: begin + data6b = 6'b100100; + may_invert6b = 1'b1; + disparity6b = 1'b1; + end + 5'd28: begin + data6b = 6'b011100; + may_invert6b = 1'b0; + disparity6b = 1'b0; + end + 5'd29: begin + data6b = 6'b100010; + may_invert6b = 1'b1; + disparity6b = 1'b1; + end + 5'd30: begin + data6b = 6'b100001; + may_invert6b = 1'b1; + disparity6b = 1'b1; + end + default: begin + data6b = 6'b001010; + may_invert6b = 1'b1; + disparity6b = 1'b1; + end + endcase + end + end + + always @(*) begin + if (in_charisk == 1'b1) begin + alt7 = 1'b1; + end else begin + // case (in_char[4:0]) + // 5'd11, 5'd13, 5'd14: alt7 = in_disparity; + // 5'd17, 5'd18, 5'd20: alt7 = ~in_disparity; + // default: alt7 = 1'b0; + // endcase + + // Slightly better packing + case ({may_invert6b,data6b[5:4]}) + 3'b000: alt7 = in_disparity; + 3'b011: alt7 = ~in_disparity; + default: alt7 = 1'b0; + endcase + end + end + + always @(*) begin + case (in_char[7:5]) + 3'd0: begin + data4b = 4'b0010; + may_invert4b = 1'b1; + disparity4b = 1'b1; + end + 3'd1: begin + data4b = 4'b1001; + may_invert4b = in_charisk; + disparity4b = 1'b0; + end + 3'd2: begin + data4b = 4'b1010; + may_invert4b = in_charisk; + disparity4b = 1'b0; + end + 3'd3: begin + data4b = 4'b1100; + may_invert4b = 1'b1; + disparity4b = 1'b0; + end + 3'd4: begin + data4b = 4'b0100; + may_invert4b = 1'b1; + disparity4b = 1'b1; + end + 3'd5: begin + data4b = 4'b0101; + may_invert4b = in_charisk; + disparity4b = 1'b0; + end + 3'd6: begin + data4b = 4'b0110; + may_invert4b = in_charisk; + disparity4b = 1'b0; + end + default: begin + if (alt7 == 1'b1) begin + data4b = 4'b0001; + end else begin + data4b = 4'b1000; + end + may_invert4b = 1'b1; + disparity4b = 1'b1; + end + endcase + end + + assign disparity4b_in = in_disparity ^ disparity6b; + assign out_disparity = disparity4b_in ^ disparity4b; + + always @(*) begin + if (in_disparity == 1'b0 && may_invert6b == 1'b1) begin + out6b = ~data6b; + end else begin + out6b = data6b; + end + if (disparity4b_in == 1'b0 && may_invert4b == 1'b1) begin + out4b = ~data4b; + end else begin + out4b = data4b; + end + end + + assign out_char = {out4b,out6b}; + +endmodule diff --git a/adi_library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v b/adi_library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v new file mode 100644 index 00000000..870054b6 --- /dev/null +++ b/adi_library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v @@ -0,0 +1,61 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_soft_pcs_tx #( + parameter NUM_LANES = 1, + parameter DATA_PATH_WIDTH = 4, + parameter INVERT_OUTPUTS = 0 +) ( + input clk, + input reset, + + input [NUM_LANES*DATA_PATH_WIDTH*8-1:0] char, + input [NUM_LANES*DATA_PATH_WIDTH-1:0] charisk, + + output reg [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data +); + + reg [NUM_LANES-1:0] disparity = 'h00; + + wire [DATA_PATH_WIDTH:0] disparity_chain[0:NUM_LANES-1]; + wire [NUM_LANES*DATA_PATH_WIDTH*10-1:0] data_s; + + always @(posedge clk) begin + data <= INVERT_OUTPUTS ? ~data_s : data_s; + end + + generate + genvar lane; + genvar i; + for (lane = 0; lane < NUM_LANES; lane = lane + 1) begin: gen_lane + assign disparity_chain[lane][0] = disparity[lane]; + + always @(posedge clk) begin + if (reset == 1'b1) begin + disparity[lane] <= 1'b0; + end else begin + disparity[lane] <= disparity_chain[lane][DATA_PATH_WIDTH]; + end + end + + for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_dpw + localparam j = DATA_PATH_WIDTH * lane + i; + + jesd204_8b10b_encoder i_enc ( + .in_char(char[j*8+:8]), + .in_charisk(charisk[j]), + .out_char(data_s[j*10+:10]), + + .in_disparity(disparity_chain[lane][i]), + .out_disparity(disparity_chain[lane][i+1])); + end + end + endgenerate + +endmodule diff --git a/adi_library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl b/adi_library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl new file mode 100644 index 00000000..8e84d44a --- /dev/null +++ b/adi_library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl @@ -0,0 +1,48 @@ +############################################################################### +## Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +package require qsys 14.0 + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl + +ad_ip_create jesd204_soft_pcs_tx "ADI JESD204 Transmit Soft PCS" + +set_module_property INTERNAL true + +ad_ip_parameter INVERT_OUTPUTS INTEGER 0 + +# files + +ad_ip_files jesd204_soft_pcs_tx [list \ + jesd204_soft_pcs_tx.v \ + jesd204_8b10b_encoder.v \ +] + +# clock + +add_interface clock clock end +add_interface_port clock clk clk Input 1 + +# reset + +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT + +add_interface_port reset reset reset Input 1 + +# interfaces + +add_interface tx_phy conduit start +#set_interface_property tx_phy associatedClock clock +#set_interface_property tx_phy associatedReset reset +add_interface_port tx_phy char char Input 32 +add_interface_port tx_phy charisk charisk Input 4 + +add_interface tx_raw_data conduit end +#set_interface_property data associatedClock clock +#set_interface_property data associatedReset reset +add_interface_port tx_raw_data data raw_data Output 40 diff --git a/adi_library/jesd204/jesd204_tx/Makefile b/adi_library/jesd204/jesd204_tx/Makefile new file mode 100644 index 00000000..6048caf1 --- /dev/null +++ b/adi_library/jesd204/jesd204_tx/Makefile @@ -0,0 +1,50 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := jesd204_tx + +GENERIC_DEPS += ../../common/ad_pack.v +GENERIC_DEPS += ../../common/ad_upack.v +GENERIC_DEPS += jesd204_tx.v +GENERIC_DEPS += jesd204_tx_ctrl.v +GENERIC_DEPS += jesd204_tx_gearbox.v +GENERIC_DEPS += jesd204_tx_lane.v + +XILINX_DEPS += bd/bd.tcl +XILINX_DEPS += jesd204_tx_constr.ttcl +XILINX_DEPS += jesd204_tx_header.v +XILINX_DEPS += jesd204_tx_ip.tcl +XILINX_DEPS += jesd204_tx_lane_64b.v +XILINX_DEPS += jesd204_tx_ooc.ttcl + +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg_rtl.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl_rtl.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_event.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_event_rtl.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config_rtl.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_status.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_status_rtl.xml + +XILINX_LIB_DEPS += jesd204/jesd204_common +XILINX_LIB_DEPS += util_cdc + +XILINX_INTERFACE_DEPS += jesd204/interfaces + +INTEL_DEPS += ../../util_cdc/sync_bits.v +INTEL_DEPS += ../../util_cdc/sync_event.v +INTEL_DEPS += ../jesd204_common/jesd204_eof_generator.v +INTEL_DEPS += ../jesd204_common/jesd204_frame_align_replace.v +INTEL_DEPS += ../jesd204_common/jesd204_frame_mark.v +INTEL_DEPS += ../jesd204_common/jesd204_lmfc.v +INTEL_DEPS += ../jesd204_common/jesd204_scrambler.v +INTEL_DEPS += ../jesd204_common/pipeline_stage.v +INTEL_DEPS += jesd204_tx_constr.sdc +INTEL_DEPS += jesd204_tx_hw.tcl + +include ../../scripts/library.mk diff --git a/adi_library/jesd204/jesd204_tx/bd/bd.tcl b/adi_library/jesd204/jesd204_tx/bd/bd.tcl new file mode 100644 index 00000000..d8d7739a --- /dev/null +++ b/adi_library/jesd204/jesd204_tx/bd/bd.tcl @@ -0,0 +1,49 @@ +############################################################################### +## Copyright (C) 2021 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_override $ip \ + "ASYNC_CLK" + +} + +proc detect_async_clk { cellpath ip param_name clk_a clk_b } { + set param_src [get_property "CONFIG.$param_name.VALUE_SRC" $ip] + if {[string equal $param_src "USER"]} { + return; + } + + set clk_domain_a [get_property CONFIG.CLK_DOMAIN $clk_a] + set clk_domain_b [get_property CONFIG.CLK_DOMAIN $clk_b] + set clk_freq_a [get_property CONFIG.FREQ_HZ $clk_a] + set clk_freq_b [get_property CONFIG.FREQ_HZ $clk_b] + set clk_phase_a [get_property CONFIG.PHASE $clk_a] + set clk_phase_b [get_property CONFIG.PHASE $clk_b] + + # Only mark it as sync if we can make sure that it is sync, if the + # relationship of the clocks is unknown mark it as async + if {$clk_domain_a != {} && $clk_domain_b != {} && \ + $clk_domain_a == $clk_domain_b && $clk_freq_a == $clk_freq_b && \ + $clk_phase_a == $clk_phase_b} { + set clk_async 0 + } else { + set clk_async 1 + } + + set_property "CONFIG.$param_name" $clk_async $ip + +} + +proc propagate {cellpath otherinfo} { + set ip [get_bd_cells $cellpath] + + set link_clk [get_bd_pins "$ip/clk"] + set device_clk [get_bd_pins "$ip/device_clk"] + + detect_async_clk $cellpath $ip "ASYNC_CLK" $link_clk $device_clk +} + diff --git a/adi_library/jesd204/jesd204_tx/component.xml b/adi_library/jesd204/jesd204_tx/component.xml new file mode 100644 index 00000000..db54efb5 --- /dev/null +++ b/adi_library/jesd204/jesd204_tx/component.xml @@ -0,0 +1,3152 @@ + + + analog.com + user + jesd204_tx + 1.0 + + + tx_data + + + + + + + TVALID + + + tx_valid + + + + + TREADY + + + tx_ready + + + + + TDATA + + + tx_data + + + + + + tx_phy0 + + + + + + + txdata + + + phy_data + + 31 + 0 + + + + + + txcharisk + + + phy_charisk + + 3 + 0 + + + + + + txheader + + + phy_header + + 1 + 0 + + + + + + + + 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tx_cfg_tx_ilas_config_tx_event_tx_status_tx_ctrl_signal_reset + tx_cfg_tx_ilas_config_tx_event_tx_status_tx_ctrl_signal_reset + + + + + + + RST + + + reset + + + + + + POLARITY + ACTIVE_HIGH + + + + + tx_data_signal_clock + tx_data_signal_clock + + + + + + + CLK + + + device_clk + + + + + + ASSOCIATED_BUSIF + tx_data + + + ASSOCIATED_RESET + device_reset + + + + + tx_data_signal_reset + tx_data_signal_reset + + + + + + + RST + + + device_reset + + + + + + POLARITY + ACTIVE_HIGH + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + jesd204_tx + + xilinx_anylanguagesynthesis_analog_com_user_jesd204_common_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + df6c408b + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + jesd204_tx + + xilinx_anylanguagebehavioralsimulation_analog_com_user_jesd204_common_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + df6c408b + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_analog_com_user_jesd204_common_1_0__ref_view_fileset + + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_xpgui_view_fileset + + + + viewChecksum + e83e8551 + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_analog_com_user_jesd204_common_1_0__ref_view_fileset + + + xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_blockdiagram_view_fileset + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + reset + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_reset + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + phy_data + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + phy_charisk + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + phy_header + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sysref + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + lmfc_edge + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + lmfc_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sync + + in + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + tx_data + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + tx_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + tx_eof + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + tx_sof + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + tx_somf + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + tx_eomf + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + tx_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_lanes_disable + + in + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_links_disable + + in + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_octets_per_multiframe + + in + + 9 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_octets_per_frame + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_continuous_cgs + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_continuous_ilas + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_skip_ilas + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_mframes_per_ilas + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_disable_char_replacement + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_disable_scrambler + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_octets_per_multiframe + + in + + 9 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_octets_per_frame + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_beats_per_multiframe + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_lmfc_offset + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_sysref_oneshot + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_sysref_disable + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ilas_config_rd + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ilas_config_addr + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ilas_config_data + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + ctrl_manual_sync_request + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + device_event_sysref_edge + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_event_sysref_alignment_error + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + status_sync + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + status_state + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + status_synth_params0 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + status_synth_params1 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + status_synth_params2 + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + NUM_LANES + Num Lanes + 1 + + + NUM_LINKS + Num Links + 1 + + + NUM_OUTPUT_PIPELINE + Num Output Pipeline + 0 + + + LINK_MODE + Link Mode + 1 + + + DATA_PATH_WIDTH + Data Path Width + 4 + + + TPL_DATA_PATH_WIDTH + Tpl Data Path Width + 4 + + + ENABLE_CHAR_REPLACE + Enable Char Replace + "0" + + + ASYNC_CLK + Async Clk + 1 + + + + + + choice_pairs_1942b210 + 2 + 1 + + + + + xilinx_anylanguagesynthesis_view_fileset + + jesd204_tx_ooc.ttcl + ttcl + + + jesd204_tx_constr.ttcl + ttcl + + + jesd204_tx_lane.v + verilogSource + + + jesd204_tx_lane_64b.v + verilogSource + + + jesd204_tx_header.v + verilogSource + + + jesd204_tx_gearbox.v + verilogSource + + + jesd204_tx_ctrl.v + verilogSource + + + ../../common/ad_pack.v + verilogSource + + + ../../common/ad_upack.v + verilogSource + + + bd/bd.tcl + tclSource + + + jesd204_tx.v + verilogSource + CHECKSUM_b8083ac0 + + + + xilinx_anylanguagesynthesis_analog_com_user_jesd204_common_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + jesd204_tx_lane.v + verilogSource + + + jesd204_tx_lane_64b.v + verilogSource + + + jesd204_tx_header.v + verilogSource + + + jesd204_tx_gearbox.v + verilogSource + + + jesd204_tx_ctrl.v + verilogSource + + + ../../common/ad_pack.v + verilogSource + + + ../../common/ad_upack.v + verilogSource + + + bd/bd.tcl + tclSource + + + jesd204_tx.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_jesd204_common_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/jesd204_tx_v1_0.tcl + tclSource + CHECKSUM_62c3c738 + XGUI_VERSION_2 + + + + xilinx_xpgui_analog_com_user_jesd204_common_1_0__ref_view_fileset + + + + + + + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + xilinx_blockdiagram_analog_com_user_jesd204_common_1_0__ref_view_fileset + + + + + + + + xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + xilinx_utilityxitfiles_view_fileset + + gui/jesd204_tx_v1_0.gtcl + GTCL + + + + ADI JESD204 Transmit + + + NUM_LANES + Num Lanes + 1 + + + NUM_LINKS + Num Links + 1 + + + NUM_OUTPUT_PIPELINE + Num Output Pipeline + 0 + + + LINK_MODE + Link Layer mode + 1 + + + DATA_PATH_WIDTH + Data Path Width + 4 + + + + true + + + + + + TPL_DATA_PATH_WIDTH + Tpl Data Path Width + 4 + + + ENABLE_CHAR_REPLACE + Enable Char Replace + "0" + + + ASYNC_CLK + Link and Device Clock Asynchronous + 1 + + + Component_Name + jesd204_tx_v1_0 + + + SYSREF_IOB + Place SYSREF in IOB + true + + + + + + virtex7 + + + /Analog_Devices + + ADI JESD204 Transmit + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:52:01Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/jesd204/jesd204_tx/gui/jesd204_tx_v1_0.gtcl b/adi_library/jesd204/jesd204_tx/gui/jesd204_tx_v1_0.gtcl new file mode 100644 index 00000000..bb21c296 --- /dev/null +++ b/adi_library/jesd204/jesd204_tx/gui/jesd204_tx_v1_0.gtcl @@ -0,0 +1,3 @@ +# This file is automatically written. Do not modify. +proc gen_USERPARAMETER_DATA_PATH_WIDTH_ENABLEMENT {LINK_MODE } {expr $LINK_MODE==1} +proc gen_USERPARAMETER_DATA_PATH_WIDTH_VALUE {LINK_MODE } {expr $LINK_MODE*4} diff --git a/adi_library/jesd204/jesd204_tx/jesd204_tx.v b/adi_library/jesd204/jesd204_tx/jesd204_tx.v new file mode 100755 index 00000000..a0bf699e --- /dev/null +++ b/adi_library/jesd204/jesd204_tx/jesd204_tx.v @@ -0,0 +1,497 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_tx #( + parameter NUM_LANES = 1, + parameter NUM_LINKS = 1, + parameter NUM_OUTPUT_PIPELINE = 0, + parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B + /* Only 4 is supported at the moment for 8b/10b and 8 for 64b */ + parameter DATA_PATH_WIDTH = LINK_MODE[1] ? 8 : 4, + parameter TPL_DATA_PATH_WIDTH = LINK_MODE[1] ? 8 : 4, + parameter ENABLE_CHAR_REPLACE = 1'b0, + parameter ASYNC_CLK = 1 +) ( + input clk, + input reset, + + input device_clk, + input device_reset, + + output [DATA_PATH_WIDTH*8*NUM_LANES-1:0] phy_data, + output [DATA_PATH_WIDTH*NUM_LANES-1:0] phy_charisk, + output [2*NUM_LANES-1:0] phy_header, + + input sysref, + output lmfc_edge, + output lmfc_clk, + + input [NUM_LINKS-1:0] sync, + + input [TPL_DATA_PATH_WIDTH*8*NUM_LANES-1:0] tx_data, + output tx_ready, + output [TPL_DATA_PATH_WIDTH-1:0] tx_eof, + output [TPL_DATA_PATH_WIDTH-1:0] tx_sof, + output [TPL_DATA_PATH_WIDTH-1:0] tx_somf, + output [TPL_DATA_PATH_WIDTH-1:0] tx_eomf, + input tx_valid, + + input [NUM_LANES-1:0] cfg_lanes_disable, + input [NUM_LINKS-1:0] cfg_links_disable, + input [9:0] cfg_octets_per_multiframe, + input [7:0] cfg_octets_per_frame, + input cfg_continuous_cgs, + input cfg_continuous_ilas, + input cfg_skip_ilas, + input [7:0] cfg_mframes_per_ilas, + input cfg_disable_char_replacement, + input cfg_disable_scrambler, + + input [9:0] device_cfg_octets_per_multiframe, + input [7:0] device_cfg_octets_per_frame, + input [7:0] device_cfg_beats_per_multiframe, + input [7:0] device_cfg_lmfc_offset, + input device_cfg_sysref_oneshot, + input device_cfg_sysref_disable, + + output ilas_config_rd, + output [1:0] ilas_config_addr, + input [NUM_LANES*DATA_PATH_WIDTH*8-1:0] ilas_config_data, + + input ctrl_manual_sync_request, + + output device_event_sysref_edge, + output device_event_sysref_alignment_error, + + output [NUM_LINKS-1:0] status_sync, + output [1:0] status_state, + + output [31:0] status_synth_params0, + output [31:0] status_synth_params1, + output [31:0] status_synth_params2 +); + + localparam MAX_OCTETS_PER_FRAME = 32; + localparam MAX_OCTETS_PER_MULTIFRAME = + (MAX_OCTETS_PER_FRAME * 32) > 1024 ? 1024 : (MAX_OCTETS_PER_FRAME * 32); + localparam MAX_BEATS_PER_MULTIFRAME = MAX_OCTETS_PER_MULTIFRAME / DATA_PATH_WIDTH; + + localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1; + + localparam LMFC_COUNTER_WIDTH = MAX_BEATS_PER_MULTIFRAME > 256 ? 9 : + MAX_BEATS_PER_MULTIFRAME > 128 ? 8 : + MAX_BEATS_PER_MULTIFRAME > 64 ? 7 : + MAX_BEATS_PER_MULTIFRAME > 32 ? 6 : + MAX_BEATS_PER_MULTIFRAME > 16 ? 5 : + MAX_BEATS_PER_MULTIFRAME > 8 ? 4 : + MAX_BEATS_PER_MULTIFRAME > 4 ? 3 : + MAX_BEATS_PER_MULTIFRAME > 2 ? 2 : 1; + + localparam DW = DATA_PATH_WIDTH * 8 * NUM_LANES; + localparam CW = DATA_PATH_WIDTH * NUM_LANES; + localparam HW = 2 * NUM_LANES; + + wire [DW-1:0] phy_data_r; + wire [CW-1:0] phy_charisk_r; + wire [HW-1:0] phy_header_r; + + wire eof_gen_reset; + wire tx_ready_64b_next; + reg tx_ready_64b = 1'b0; + wire frame_mark_reset; + wire [DATA_PATH_WIDTH-1:0] tx_sof_fm; + wire [DATA_PATH_WIDTH-1:0] tx_eof_fm; + wire [DATA_PATH_WIDTH-1:0] tx_somf_fm; + wire [DATA_PATH_WIDTH-1:0] tx_eomf_fm; + reg [DATA_PATH_WIDTH-1:0] tx_sof_fm_d1; + reg [DATA_PATH_WIDTH-1:0] tx_eof_fm_d1; + reg [DATA_PATH_WIDTH-1:0] tx_somf_fm_d1; + reg [DATA_PATH_WIDTH-1:0] tx_eomf_fm_d1; + reg [DATA_PATH_WIDTH-1:0] tx_sof_fm_d2; + reg [DATA_PATH_WIDTH-1:0] tx_eof_fm_d2; + reg [DATA_PATH_WIDTH-1:0] tx_somf_fm_d2; + reg [DATA_PATH_WIDTH-1:0] tx_eomf_fm_d2; + wire lmfc_edge_synced; + wire lmc_edge; + wire lmc_quarter_edge; + wire eoemb; + wire [DATA_PATH_WIDTH*8*NUM_LANES-1:0] gearbox_data; + wire tx_ready_nx; + wire link_lmfc_edge; + wire link_lmfc_clk; + wire device_lmfc_edge; + wire device_lmfc_clk; + wire device_lmc_edge; + wire device_lmc_quarter_edge; + wire device_eoemb; + wire tx_next_mf_ready; + wire link_tx_ready; + + wire [7:0] cfg_beats_per_multiframe = cfg_octets_per_multiframe >> DPW_LOG2; + wire [7:0] device_cfg_beats_per_multiframe_s; + + // If input and output widths are symmetric keep the calculation for backwards + // compatibility of the software. + assign device_cfg_beats_per_multiframe_s = (TPL_DATA_PATH_WIDTH == DATA_PATH_WIDTH) ? + device_cfg_octets_per_multiframe >> DPW_LOG2 : + device_cfg_beats_per_multiframe; + + jesd204_lmfc #( + .LINK_MODE(LINK_MODE), + .DATA_PATH_WIDTH(TPL_DATA_PATH_WIDTH) + ) i_lmfc ( + .clk(device_clk), + .reset(device_reset), + + .cfg_octets_per_multiframe(device_cfg_octets_per_multiframe), + .cfg_lmfc_offset(device_cfg_lmfc_offset), + .cfg_beats_per_multiframe(device_cfg_beats_per_multiframe_s), + .cfg_sysref_oneshot(device_cfg_sysref_oneshot), + .cfg_sysref_disable(device_cfg_sysref_disable), + + .sysref(sysref), + + .sysref_edge(device_event_sysref_edge), + .sysref_alignment_error(device_event_sysref_alignment_error), + + .lmfc_edge(device_lmfc_edge), + .lmfc_clk(device_lmfc_clk), + .lmfc_counter(), + .lmc_edge(device_lmc_edge), + .lmc_quarter_edge(device_lmc_quarter_edge), + .eoemb(device_eoemb)); + + generate + if (ASYNC_CLK) begin : dual_lmfc_mode + + reg link_lmfc_reset = 1'b1; + reg device_tx_ready = 1'b0; + + jesd204_lmfc #( + .LINK_MODE(LINK_MODE), + .DATA_PATH_WIDTH(DATA_PATH_WIDTH) + ) i_link_lmfc ( + .clk(clk), + .reset(link_lmfc_reset), + + .cfg_octets_per_multiframe(cfg_octets_per_multiframe), + .cfg_lmfc_offset('h0), + .cfg_beats_per_multiframe(cfg_beats_per_multiframe), + .cfg_sysref_oneshot(1'b0), + .cfg_sysref_disable(1'b1), + + .sysref(sysref), + + .sysref_edge(), + .sysref_alignment_error(), + + .lmfc_edge(link_lmfc_edge), + .lmfc_clk(link_lmfc_clk), + .lmfc_counter(), + .lmc_edge(lmc_edge), + .lmc_quarter_edge(lmc_quarter_edge), + .eoemb(eoemb)); + + sync_bits #( + .NUM_OF_BITS (1), + .ASYNC_CLK(ASYNC_CLK) + ) i_link_reset_done_cdc ( + .in_bits(~reset), + .out_clk(device_clk), + .out_resetn(~device_reset), + .out_bits(link_reset_n)); + + sync_event #( + .NUM_OF_EVENTS (1) + ) i_sync_lmfc ( + .in_clk(device_clk), + .in_event(device_lmfc_edge & link_reset_n), + .out_clk(clk), + .out_event(lmfc_edge_synced)); + + always @(posedge clk) begin + if (reset) begin + link_lmfc_reset <= 1'b1; + end else if (lmfc_edge_synced) begin + link_lmfc_reset <= 1'b0; + end + end + + jesd204_tx_gearbox #( + .IN_DATA_PATH_WIDTH(TPL_DATA_PATH_WIDTH), + .OUT_DATA_PATH_WIDTH(DATA_PATH_WIDTH), + .NUM_LANES(NUM_LANES), + .DEPTH(8) + ) i_tx_gearbox ( + .link_clk(clk), + .reset(reset), + .device_clk(device_clk), + .device_reset(device_reset), + .device_data(tx_data), + .device_lmfc_edge(device_lmfc_edge), + .link_data(gearbox_data), + .output_ready(tx_ready_nx)); + + sync_bits #( + .NUM_OF_BITS (1), + .ASYNC_CLK(ASYNC_CLK) + ) i_next_mf_ready_cdc ( + .in_bits(tx_next_mf_ready), + .out_clk(device_clk), + .out_resetn(1'b1), + .out_bits(device_tx_next_mf_ready)); + + always @(posedge device_clk) begin + if (device_reset) begin + device_tx_ready <= 1'b0; + end else if (device_lmfc_edge & device_tx_next_mf_ready) begin + device_tx_ready <= 1'b1; + end + end + + jesd204_frame_mark #( + .DATA_PATH_WIDTH(TPL_DATA_PATH_WIDTH) + ) i_device_frame_mark ( + .clk(device_clk), + .reset(~device_tx_ready), + .cfg_octets_per_multiframe(device_cfg_octets_per_multiframe), + .cfg_beats_per_multiframe(device_cfg_beats_per_multiframe_s), + .cfg_octets_per_frame(device_cfg_octets_per_frame), + .sof(tx_sof), + .eof(tx_eof), + .somf(tx_somf), + .eomf(tx_eomf)); + + assign tx_ready = device_tx_ready; + + end else begin + assign link_lmfc_edge = device_lmfc_edge; + assign link_lmfc_clk = device_lmfc_clk; + assign lmc_edge = device_lmc_edge; + assign lmc_quarter_edge = device_lmc_quarter_edge; + assign eoemb = device_eoemb; + assign gearbox_data = tx_data; + + assign tx_sof = (LINK_MODE == 1) ? tx_sof_fm_d2 : tx_sof_fm; + assign tx_eof = (LINK_MODE == 1) ? tx_eof_fm_d2 : tx_eof_fm; + assign tx_somf = (LINK_MODE == 1) ? tx_somf_fm_d2 : tx_somf_fm; + assign tx_eomf = (LINK_MODE == 1) ? tx_eomf_fm_d2 : tx_eomf_fm; + assign tx_ready = link_tx_ready; + + end + endgenerate + + assign lmfc_edge = device_lmfc_edge; + assign lmfc_clk = device_lmfc_clk; + + assign frame_mark_reset = (LINK_MODE == 1) ? eof_gen_reset : ~tx_ready_64b_next; + + jesd204_frame_mark #( + .DATA_PATH_WIDTH (DATA_PATH_WIDTH) + ) i_frame_mark ( + .clk (clk), + .reset (frame_mark_reset), + .cfg_octets_per_multiframe (cfg_octets_per_multiframe), + .cfg_beats_per_multiframe (cfg_beats_per_multiframe), + .cfg_octets_per_frame (cfg_octets_per_frame), + .sof (tx_sof_fm), + .eof (tx_eof_fm), + .somf (tx_somf_fm), + .eomf (tx_eomf_fm)); + + always @(posedge clk) begin + tx_sof_fm_d1 <= tx_sof_fm; + tx_eof_fm_d1 <= tx_eof_fm; + tx_somf_fm_d1 <= tx_somf_fm; + tx_eomf_fm_d1 <= tx_eomf_fm; + tx_sof_fm_d2 <= tx_sof_fm_d1; + tx_eof_fm_d2 <= tx_eof_fm_d1; + tx_somf_fm_d2 <= tx_somf_fm_d1; + tx_eomf_fm_d2 <= tx_eomf_fm_d1; + end + + generate + genvar i; + + if (LINK_MODE[0] == 1) begin : mode_8b10b + + reg [DATA_PATH_WIDTH-1:0] tx_eof_fm_d3; + reg [DATA_PATH_WIDTH-1:0] tx_eomf_fm_d3; + wire [NUM_LANES-1:0] lane_cgs_enable; + wire [DW-1:0] ilas_data; + wire [DATA_PATH_WIDTH*NUM_LANES-1:0] ilas_charisk; + + wire cfg_generate_eomf = 1'b1; + + always @(posedge clk) begin + tx_eof_fm_d3 <= tx_eof_fm_d2; + tx_eomf_fm_d3 <= tx_eomf_fm_d2; + end + + jesd204_tx_ctrl #( + .NUM_LANES(NUM_LANES), + .NUM_LINKS(NUM_LINKS), + .DATA_PATH_WIDTH(DATA_PATH_WIDTH) + ) i_tx_ctrl ( + .clk(clk), + .reset(reset), + + .sync(sync), + .lmfc_edge(link_lmfc_edge), + .somf(tx_somf_fm_d2), + .somf_early2(tx_somf_fm), + .eomf(tx_eomf_fm_d2), + + .lane_cgs_enable(lane_cgs_enable), + .eof_reset(eof_gen_reset), + + .tx_ready(link_tx_ready), + .tx_ready_nx(tx_ready_nx), + .tx_next_mf_ready(tx_next_mf_ready), + + .ilas_data(ilas_data), + .ilas_charisk(ilas_charisk), + + .ilas_config_addr(ilas_config_addr), + .ilas_config_rd(ilas_config_rd), + .ilas_config_data(ilas_config_data), + + .cfg_lanes_disable(cfg_lanes_disable), + .cfg_links_disable(cfg_links_disable), + .cfg_continuous_cgs(cfg_continuous_cgs), + .cfg_continuous_ilas(cfg_continuous_ilas), + .cfg_skip_ilas(cfg_skip_ilas), + .cfg_mframes_per_ilas(cfg_mframes_per_ilas), + .cfg_octets_per_multiframe(cfg_octets_per_multiframe), + .ctrl_manual_sync_request(ctrl_manual_sync_request), + + .status_sync(status_sync), + .status_state(status_state)); + + for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane + + localparam D_START = i * DATA_PATH_WIDTH*8; + localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1; + localparam C_START = i * DATA_PATH_WIDTH; + localparam C_STOP = C_START + DATA_PATH_WIDTH-1; + + jesd204_tx_lane #( + .DATA_PATH_WIDTH(DATA_PATH_WIDTH), + .ENABLE_CHAR_REPLACE(ENABLE_CHAR_REPLACE) + ) i_lane ( + .clk(clk), + + .eof(tx_eof_fm_d3), + .eomf(tx_eomf_fm_d3), + + .cgs_enable(lane_cgs_enable[i]), + + .ilas_data(ilas_data[D_STOP:D_START]), + .ilas_charisk(ilas_charisk[C_STOP:C_START]), + + .tx_data(gearbox_data[D_STOP:D_START]), + .tx_ready(link_tx_ready), + + .phy_data(phy_data_r[D_STOP:D_START]), + .phy_charisk(phy_charisk_r[C_STOP:C_START]), + + .cfg_octets_per_frame(cfg_octets_per_frame), + .cfg_disable_char_replacement(cfg_disable_char_replacement), + .cfg_disable_scrambler(cfg_disable_scrambler)); + end + + assign phy_header_r = 'h0; + + end + + if (LINK_MODE[1] == 1) begin : mode_64b66b + + for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane + localparam D_START = i * DATA_PATH_WIDTH*8; + localparam D_STOP = D_START + DATA_PATH_WIDTH*8-1; + localparam H_START = i * 2; + localparam H_STOP = H_START + 2 -1; + jesd204_tx_lane_64b i_lane( + .clk(clk), + .reset(reset), + + .tx_data(gearbox_data[D_STOP:D_START]), + .tx_ready(tx_ready_64b), + + .phy_data(phy_data_r[D_STOP:D_START]), + .phy_header(phy_header_r[H_STOP:H_START]), + + .lmc_edge(lmc_edge), + .lmc_quarter_edge(lmc_quarter_edge), + .eoemb(eoemb), + + .cfg_disable_scrambler(cfg_disable_scrambler), + .cfg_header_mode(2'b0), + .cfg_lane_disable(cfg_lanes_disable[i])); + end + + assign tx_ready_64b_next = reset ? 1'b0 : (link_lmfc_edge || tx_ready_64b); + + always @(posedge clk) begin + if (reset) begin + tx_ready_64b <= 1'b0; + end else begin + tx_ready_64b <= tx_ready_64b_next; + end + end + + assign tx_ready_nx = tx_ready_64b_next; + assign tx_next_mf_ready = 1'b1; + + assign link_tx_ready = tx_ready_64b; + // Link considered in DATA phase when SYSREF received and LEMC clock started + // running + assign status_state = {2{tx_ready_64b}}; + + assign phy_charisk_r = 'h0; + assign ilas_config_rd = 'h0; + assign ilas_config_addr = 'h0; + assign status_sync = 'h0; + + end + + endgenerate + + pipeline_stage #( + .WIDTH(CW + DW + HW), + .REGISTERED(NUM_OUTPUT_PIPELINE) + ) i_output_pipeline_stage ( + .clk(clk), + .in({ + phy_data_r, + phy_charisk_r, + phy_header_r + }), + .out({ + phy_data, + phy_charisk, + phy_header + })); + + // Core static parameters + assign status_synth_params0 = {NUM_LANES}; + assign status_synth_params1 = { + /*31:16 */ 16'b0, + /*15: 8 */ 1'b0,TPL_DATA_PATH_WIDTH[6:0], + /* 7: 0 */ 4'b0,DPW_LOG2[3:0]}; + assign status_synth_params2 = { + /*31:19 */ 13'b0, + /* 18 */ ENABLE_CHAR_REPLACE[0], + /*17:13 */ 5'b0, + /* 12 */ ASYNC_CLK[0], + /*11:10 */ 2'b0, + /* 9: 8 */ LINK_MODE[1:0], + /* 7: 0 */ NUM_LINKS[7:0]}; + +endmodule diff --git a/adi_library/jesd204/jesd204_tx/jesd204_tx.xpr b/adi_library/jesd204/jesd204_tx/jesd204_tx.xpr new file mode 100644 index 00000000..aae1ef5c --- /dev/null +++ b/adi_library/jesd204/jesd204_tx/jesd204_tx.xpr @@ -0,0 +1,458 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/jesd204/jesd204_tx/jesd204_tx_constr.sdc b/adi_library/jesd204/jesd204_tx/jesd204_tx_constr.sdc new file mode 100644 index 00000000..bb3ab5c2 --- /dev/null +++ b/adi_library/jesd204/jesd204_tx/jesd204_tx_constr.sdc @@ -0,0 +1,21 @@ +############################################################################### +## Copyright (C) 2017, 2021 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +set script_dir [file dirname [info script]] + +source "$script_dir/util_cdc_constr.tcl" + +# SYNC~ is a asynchronous interface +util_cdc_sync_bits_constr {*|jesd204_tx_ctrl:i_tx_ctrl|sync_bits:i_cdc_sync} + +util_cdc_sync_event_constr {*|sync_event:dual_lmfc_mode.i_sync_lmfc} +util_cdc_sync_bits_constr {*|sync_bits:dual_lmfc_mode.i_next_mf_ready_cdc} +util_cdc_sync_bits_constr {*|sync_bits:dual_lmfc_mode.i_link_reset_done_cdc} +util_cdc_sync_bits_constr {*|sync_bits:i_sync_ready} + +set_false_path -to *|dual_lmfc_mode.i_link_reset_done_cdc|cdc_sync_stage1[0]~RTM + +## gearbox on distributed RAM +#set_false_path -from *|dual_lmfc_mode.i_tx_gearbox|mem* -to *|dual_lmfc_mode.i_tx_gearbox|mem_rd_data* diff --git a/adi_library/jesd204/jesd204_tx/jesd204_tx_constr.ttcl b/adi_library/jesd204/jesd204_tx/jesd204_tx_constr.ttcl new file mode 100644 index 00000000..53f68963 --- /dev/null +++ b/adi_library/jesd204/jesd204_tx/jesd204_tx_constr.ttcl @@ -0,0 +1,63 @@ +############################################################################### +## Copyright (C) 2017, 2018, 2021 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName [ttcl_add $ComponentName "_constr"] :> +<: setFileExtension ".xdc" :> +<: setFileProcessingOrder late :> +<: set sysref_iob [get_property PARAM_VALUE.SYSREF_IOB] :> +<: set async_clk [getBooleanValue "ASYNC_CLK"] :> + +set_property ASYNC_REG TRUE \ + [get_cells {i_lmfc/sysref_d1_reg}] \ + [get_cells {i_lmfc/sysref_d2_reg}] + +# Make sure that the device clock to sysref skew is at least somewhat +# predictable +set_property IOB <=: $sysref_iob :> \ + [get_cells {i_lmfc/sysref_r_reg}] + +<: if {$async_clk} { :> + +set link_clk [get_clocks -of_objects [get_ports -quiet {clk}]] +set device_clk [get_clocks -of_objects [get_ports -quiet {device_clk}]] + +# sync event i_sync_lmfc +set_false_path -quiet \ + -from $device_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_lmfc/i_sync_out* && IS_SEQUENTIAL}] + +set_false_path -quiet \ + -from $link_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_lmfc/i_sync_in* && IS_SEQUENTIAL}] + +# sync bits i_next_mf_ready_cdc +set_false_path \ + -from $link_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_next_mf_ready_cdc* && IS_SEQUENTIAL}] + +# sync bits i_link_reset_done_cdc +set_false_path \ + -from $link_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_link_reset_done_cdc* && IS_SEQUENTIAL}] + +# sync bits gearbox/i_sync_ready +set_false_path \ + -from $link_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_ready* && IS_SEQUENTIAL}] + +# gearbox distributed RAM +set_false_path -quiet \ + -from $device_clk \ + -to [get_cells -quiet -hier *mem_rd_data_reg* \ + -filter {NAME =~ *i_tx_gearbox* && IS_SEQUENTIAL}] + +<: } :> diff --git a/adi_library/jesd204/jesd204_tx/jesd204_tx_ctrl.v b/adi_library/jesd204/jesd204_tx/jesd204_tx_ctrl.v new file mode 100755 index 00000000..94e06a0b --- /dev/null +++ b/adi_library/jesd204/jesd204_tx/jesd204_tx_ctrl.v @@ -0,0 +1,340 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_tx_ctrl #( + parameter NUM_LANES = 1, + parameter NUM_LINKS = 1, + parameter DATA_PATH_WIDTH = 4 +) ( + input clk, + input reset, + + input [NUM_LINKS-1:0] sync, + input lmfc_edge, + input [DATA_PATH_WIDTH-1:0] somf, + input [DATA_PATH_WIDTH-1:0] somf_early2, + input [DATA_PATH_WIDTH-1:0] eomf, + + output reg [NUM_LANES-1:0] lane_cgs_enable, + output reg eof_reset, + + output reg tx_ready, + output tx_ready_nx, + output tx_next_mf_ready, + + output reg [DATA_PATH_WIDTH*8*NUM_LANES-1:0] ilas_data, + output reg [DATA_PATH_WIDTH*NUM_LANES-1:0] ilas_charisk, + + output reg [1:0] ilas_config_addr, + output reg ilas_config_rd, + input [DATA_PATH_WIDTH*8*NUM_LANES-1:0] ilas_config_data, + + input [NUM_LANES-1:0] cfg_lanes_disable, + input [NUM_LINKS-1:0] cfg_links_disable, + input cfg_continuous_cgs, + input cfg_continuous_ilas, + input cfg_skip_ilas, + input [7:0] cfg_mframes_per_ilas, + input [9:0] cfg_octets_per_multiframe, + input ctrl_manual_sync_request, + + output [NUM_LINKS-1:0] status_sync, + output reg [1:0] status_state +); + + localparam ILAS_DATA_LENGTH = (DATA_PATH_WIDTH == 4) ? 4 : 2; + localparam ILAS_COUNTER_WIDTH = (DATA_PATH_WIDTH == 4) ? 6 : 5; + localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1; + localparam BEATS_PER_MF_WIDTH = 10-DPW_LOG2; + + // For DATA_PATH_WIDTH = 8, special case if F*K%8=4 + // Multiframe boundaries can occur in the middle of a beat + // jesd204_lmfc will assert lmfc_edge once per two LMFC periods + // cfg_mframes_per_ilas must be even + wire [BEATS_PER_MF_WIDTH-1:0] cfg_beats_per_multiframe = cfg_octets_per_multiframe[9:DPW_LOG2]; + wire octets_per_mf_4_mod_8 = (DATA_PATH_WIDTH == 8) && ~cfg_octets_per_multiframe[2]; + wire [7:0] cfg_lmfc_per_ilas = octets_per_mf_4_mod_8 ? cfg_mframes_per_ilas/2 : cfg_mframes_per_ilas; + reg lmfc_edge_d1 = 1'b0; + reg lmfc_edge_d2 = 1'b0; + reg eof_reset_d; + reg ilas_reset = 1'b1; + reg ilas_data_reset = 1'b1; + reg sync_request = 1'b0; + reg sync_request_received = 1'b0; + reg last_ilas_mframe = 1'b0; + reg [7:0] mframe_counter = 'h00; + reg [ILAS_COUNTER_WIDTH-1:0] ilas_counter = 'h00; + wire ilas_config_rd_start; + reg ilas_config_rd_d1 = 1'b1; + reg cgs_enable = 1'b1; + wire [DATA_PATH_WIDTH*8-1:0] ilas_default_data; + + wire [NUM_LINKS-1:0] status_sync_masked; + + genvar ii; + genvar jj; + + sync_bits #( + .NUM_OF_BITS (NUM_LINKS) + ) i_cdc_sync ( + .in_bits(sync), + .out_clk(clk), + .out_resetn(1'b1), + .out_bits(status_sync)); + + assign status_sync_masked = status_sync | cfg_links_disable; + + always @(posedge clk) begin + if (reset == 1'b1) begin + sync_request <= {NUM_LINKS{1'b0}}; + end else begin + /* TODO: SYNC must be asserted at least 4 frames before interpreted as a + * sync request and the /K28.5/ symbol generation has lasted for at + * least 1 frame + 9 octets */ + if (cfg_continuous_cgs == 1'b1) begin + sync_request <= 1'b1; + end else begin + sync_request <= ~(&status_sync_masked) | ctrl_manual_sync_request; + end + end + end + + always @(posedge clk) begin + if (sync_request == 1'b0 && sync_request_received == 1'b1) begin + lmfc_edge_d1 <= lmfc_edge; + lmfc_edge_d2 <= lmfc_edge_d1; + end else begin + lmfc_edge_d1 <= 1'b0; + lmfc_edge_d2 <= 1'b0; + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + sync_request_received <= 1'b0; + end else if (sync_request == 1'b1) begin + sync_request_received <= 1'b1; + end + end + + always @(posedge clk) begin + if (cfg_skip_ilas == 1'b1 || + mframe_counter == cfg_lmfc_per_ilas) begin + last_ilas_mframe <= 1'b1; + end else begin + last_ilas_mframe <= 1'b0; + end + end + + always @(*) begin + if (sync_request == 1'b1 || reset == 1'b1) begin + eof_reset = 1'b1; + end else if (lmfc_edge == 1'b1 && sync_request_received == 1'b1) begin + eof_reset = 1'b0; + end else begin + eof_reset = eof_reset_d; + end + end + + always @(posedge clk) begin + eof_reset_d <= eof_reset; + end + + localparam STATE_WAIT = 2'b00; + localparam STATE_CGS = 2'b01; + localparam STATE_ILAS = 2'b10; + localparam STATE_DATA = 2'b11; + + /* Timeline + * + * #1 lmfc_edge == 1, ilas_reset update + * #3 {lane_,}cgs_enable, tx_ready update + * + * One multi-frame should at least be 3 clock cycles (TBD 64-bit data path) + */ + + always @(posedge clk) begin + if (sync_request == 1'b1 || reset == 1'b1) begin + cgs_enable <= 1'b1; + lane_cgs_enable <= {NUM_LANES{1'b1}}; + tx_ready <= 1'b0; + ilas_reset <= 1'b1; + ilas_data_reset <= 1'b1; + + if (sync_request_received == 1'b0) begin + status_state <= STATE_WAIT; + end else begin + status_state <= STATE_CGS; + end + end else if (sync_request_received == 1'b1) begin + if (lmfc_edge == 1'b1 && last_ilas_mframe == 1'b1) begin + ilas_reset <= 1'b1; + status_state <= STATE_DATA; + end else if (lmfc_edge_d1 == 1'b1 && (cfg_continuous_ilas == 1'b1 || + cgs_enable == 1'b1)) begin + ilas_reset <= 1'b0; + status_state <= STATE_ILAS; + end + + if (lmfc_edge_d1 == 1'b1) begin + if (last_ilas_mframe == 1'b1 && cfg_continuous_ilas == 1'b0) begin + ilas_data_reset <= 1'b1; + end else if (cgs_enable == 1'b1) begin + ilas_data_reset <= 1'b0; + end + end + + if (lmfc_edge_d2 == 1'b1) begin + lane_cgs_enable <= cfg_lanes_disable; + cgs_enable <= 1'b0; + if (last_ilas_mframe == 1'b1 && cfg_continuous_ilas == 1'b0) begin + tx_ready <= 1'b1; + end + end + end + end + + assign tx_next_mf_ready = sync_request_received & last_ilas_mframe & ~cfg_continuous_ilas; + assign tx_ready_nx = tx_ready | (tx_next_mf_ready & lmfc_edge_d2); + + always @(posedge clk) begin + if (ilas_reset == 1'b1) begin + mframe_counter <= 'h00; + end else if (lmfc_edge_d1 == 1'b1) begin + mframe_counter <= mframe_counter + 1'b1; + end + end + + always @(posedge clk) begin + if (ilas_reset == 1'b1) begin + ilas_config_rd <= 1'b0; + end else if (ilas_config_rd_start == 1'b1) begin + ilas_config_rd <= 1'b1; + end else if (ilas_config_addr == (ILAS_DATA_LENGTH-1)) begin + ilas_config_rd <= 1'b0; + end + ilas_config_rd_d1 <= ilas_config_rd; + end + + always @(posedge clk) begin + if (ilas_config_rd == 1'b0) begin + ilas_config_addr <= 'h00; + end else begin + ilas_config_addr <= ilas_config_addr + 1'b1; + end + end + + always @(posedge clk) begin + if (ilas_reset == 1'b1) begin + ilas_counter <= 'h00; + end else begin + ilas_counter <= ilas_counter + 1'b1; + end + end + + generate + for(ii = 0; ii < DATA_PATH_WIDTH; ii=ii+1) begin : gen_default_data + wire [(8-ILAS_COUNTER_WIDTH)-1:0] ii_sig = ii; + assign ilas_default_data[(ii*8)+7:ii*8] = {ilas_counter, ii_sig}; + end + endgenerate + + generate + if(DATA_PATH_WIDTH == 4) begin : gen_dp4 + + assign ilas_config_rd_start = mframe_counter == 'h00 && somf_early2[0]; + + always @(posedge clk) begin + if (ilas_data_reset == 1'b1) begin + ilas_data <= {NUM_LANES{32'h00}}; + ilas_charisk <= {NUM_LANES{4'b0000}}; + end else begin + if (ilas_config_rd_d1 == 1'b1) begin + case (ilas_config_addr) + 2'h1: begin + ilas_data <= (ilas_config_data & {NUM_LANES{32'hffff0000}}) | + {NUM_LANES{16'h00,8'h9c,8'h1c}}; // /Q/ /R/ + ilas_charisk <= {NUM_LANES{4'b0011}}; + end + default: begin + ilas_data <= ilas_config_data; + ilas_charisk <= {NUM_LANES{4'b0000}}; + end + endcase + end else if (lmfc_edge_d2 == 1'b1) begin + ilas_data <= {NUM_LANES{ilas_default_data[31:8],8'h1c}}; // /R/ + ilas_charisk <= {NUM_LANES{4'b0001}}; + end else if (lmfc_edge_d1 == 1'b1) begin + ilas_data <= {NUM_LANES{8'h7c,ilas_default_data[23:0]}}; // /A/ + ilas_charisk <= {NUM_LANES{4'b1000}}; + end else begin + ilas_data <= {NUM_LANES{ilas_default_data}}; + ilas_charisk <= {NUM_LANES{4'b0000}}; + end + end + end + + end else if(DATA_PATH_WIDTH == 8) begin : gen_dp8 + + reg [63:0] ilas_config_data_d[NUM_LANES-1:0]; + reg ilas_config_rd_d2 = 1'b0; + + always @(posedge clk) begin + ilas_config_rd_d2 <= ilas_config_rd_d1; + end + + for(jj = 0; jj < NUM_LANES; jj = jj + 1) begin : gen_dp8_lane + + assign ilas_config_rd_start = (mframe_counter == 'h00) && (octets_per_mf_4_mod_8 ? somf_early2[4] : somf_early2[0]); + + always @(posedge clk) begin + ilas_config_data_d[jj] <= {32'b0, ilas_config_data[(jj*64)+32+:32]}; + end + + for(ii = 0; ii < DATA_PATH_WIDTH; ii=ii+1) begin : gen_ilas_data + + always @(posedge clk) begin + if (ilas_data_reset) begin + ilas_data[(jj*64)+(ii*8)+:8] <= 8'h00; + ilas_charisk[(jj*8)+ii] <= 1'b0; + end else begin + if(somf[ii]) begin + ilas_data[(jj*64)+(ii*8)+:8] <= 8'h1c; // /R/ + ilas_charisk[(jj*8)+ii] <= 1'b1; + end else if(eomf[ii]) begin + ilas_data[(jj*64)+(ii*8)+:8] <= 8'h7c; // /A/ + ilas_charisk[(jj*8)+ii] <= 1'b1; + end else if (ilas_config_rd_d1 && + (ilas_config_addr == 2'h1) && + ((octets_per_mf_4_mod_8 && (ii == 5)) || + (!octets_per_mf_4_mod_8 && (ii == 1)))) begin + ilas_data[(jj*64)+(ii*8)+:8] <= 8'h9c; // /Q/ + ilas_charisk[(jj*8)+ii] <= 1'b1; + end else if (octets_per_mf_4_mod_8 && ilas_config_rd_d2 && (ii < 4)) begin + ilas_data[(jj*64)+(ii*8)+:8] <= ilas_config_data_d[jj][ii*8+:8]; + ilas_charisk[(jj*8)+ii] <= 1'b0; + end else if (octets_per_mf_4_mod_8 && ilas_config_rd_d1 && (ii >= 4)) begin + ilas_data[(jj*64)+(ii*8)+:8] <= ilas_config_data[(jj*64)+((ii-4)*8)+:8]; + ilas_charisk[(jj*8)+ii] <= 1'b0; + end else if (!octets_per_mf_4_mod_8 && ilas_config_rd_d1) begin + ilas_data[(jj*64)+(ii*8)+:8] <= ilas_config_data[(jj*64)+(ii*8)+:8]; + ilas_charisk[(jj*8)+ii] <= 1'b0; + end else begin + ilas_data[(jj*64)+(ii*8)+:8] <= ilas_default_data[ii*8+:8]; + ilas_charisk[(jj*8)+ii] <= 1'b0; + end + end + end + + end + end + end + endgenerate + +endmodule diff --git a/adi_library/jesd204/jesd204_tx/jesd204_tx_gearbox.v b/adi_library/jesd204/jesd204_tx/jesd204_tx_gearbox.v new file mode 100644 index 00000000..9956c0c0 --- /dev/null +++ b/adi_library/jesd204/jesd204_tx/jesd204_tx_gearbox.v @@ -0,0 +1,159 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +// Constraints: +// - IN_DATA_PATH_WIDTH >= OUT_DATA_PATH_WIDTH +// + +module jesd204_tx_gearbox #( + parameter IN_DATA_PATH_WIDTH = 6, + parameter OUT_DATA_PATH_WIDTH = 4, + parameter NUM_LANES = 1, + parameter DEPTH = 16 +) ( + input link_clk, + input reset, + input device_clk, + input device_reset, + input [NUM_LANES*IN_DATA_PATH_WIDTH*8-1:0] device_data, + input device_lmfc_edge, + output [NUM_LANES*OUT_DATA_PATH_WIDTH*8-1:0] link_data, + input output_ready +); + + localparam MEM_W = (OUT_DATA_PATH_WIDTH <= IN_DATA_PATH_WIDTH) ? + IN_DATA_PATH_WIDTH*8*NUM_LANES : + OUT_DATA_PATH_WIDTH*8*NUM_LANES; + localparam D_LOG2 = $clog2(DEPTH); + + reg [MEM_W-1:0] mem [0:DEPTH-1]; + reg [D_LOG2-1:0] in_addr ='h00; + reg [D_LOG2-1:0] out_addr = 'b0; + reg mem_rd_valid = 'b0; + reg [MEM_W-1:0] mem_rd_data = 'b0; + + wire mem_rd_en; + wire mem_wr_en; + wire [D_LOG2-1:0] in_out_addr; + wire [D_LOG2-1:0] out_in_addr; + wire [MEM_W-1:0] mem_wr_data; + wire [NUM_LANES-1:0] data_ready; + wire output_ready_sync; + wire addr_reset; + wire packer_reset; + + sync_bits i_sync_ready ( + .in_bits(output_ready), + .out_resetn(~device_reset), + .out_clk(device_clk), + .out_bits(output_ready_sync)); + + assign addr_reset = device_lmfc_edge & ~output_ready_sync; + assign packer_reset = device_reset | addr_reset; + + genvar i; + generate if (OUT_DATA_PATH_WIDTH < IN_DATA_PATH_WIDTH) begin + + assign mem_wr_en = 1'b1; + + always @(posedge device_clk) begin + if (addr_reset) begin + in_addr <= 'h00; + end else if (mem_wr_en) begin + in_addr <= in_addr + 1; + end + end + + always @(posedge device_clk) begin + if (mem_wr_en) begin + mem[in_addr] <= device_data; + end + end + + assign mem_rd_en = output_ready&data_ready[0]; + + always @(posedge link_clk) begin + if (mem_rd_en) begin + mem_rd_data <= mem[out_addr]; + end + mem_rd_valid <= mem_rd_en; + end + + always @(posedge link_clk) begin + if (reset) begin + out_addr <= 'b0; + end else if (mem_rd_en) begin + out_addr <= out_addr + 1; + end + end + + for (i = 0; i < NUM_LANES; i=i+1) begin: unpacker + ad_upack #( + .I_W(IN_DATA_PATH_WIDTH), + .O_W(OUT_DATA_PATH_WIDTH), + .UNIT_W(8), + .O_REG(0) + ) i_ad_upack ( + .clk(link_clk), + .reset(reset), + .idata(mem_rd_data[i*IN_DATA_PATH_WIDTH*8+:IN_DATA_PATH_WIDTH*8]), + .ivalid(mem_rd_valid), + .iready(data_ready[i]), + + .odata(link_data[i*OUT_DATA_PATH_WIDTH*8+:OUT_DATA_PATH_WIDTH*8]), + .ovalid()); + end + + end else begin + if (OUT_DATA_PATH_WIDTH > IN_DATA_PATH_WIDTH) begin + for (i = 0; i < NUM_LANES; i=i+1) begin: packer + ad_pack #( + .I_W(IN_DATA_PATH_WIDTH), + .O_W(OUT_DATA_PATH_WIDTH), + .UNIT_W(8), + .O_REG(0) + ) i_ad_pack ( + .clk(device_clk), + .reset(packer_reset), + .idata(device_data[i*IN_DATA_PATH_WIDTH*8+:IN_DATA_PATH_WIDTH*8]), + .ivalid(1'b1), + + .odata(mem_wr_data[i*OUT_DATA_PATH_WIDTH*8+:OUT_DATA_PATH_WIDTH*8]), + .ovalid(data_ready[i])); + end + assign mem_wr_en = data_ready[0]; + end else begin + assign mem_wr_en = 1'b1; + assign mem_wr_data = device_data; + end + + always @(posedge device_clk) begin + if (addr_reset) begin + in_addr <= 'h00; + end else if (mem_wr_en) begin + mem[in_addr] <= mem_wr_data; + in_addr <= in_addr + 1'b1; + end + end + + always @(posedge link_clk) begin + if (output_ready == 1'b0) begin + out_addr <= 'h00; + end else begin + out_addr <= out_addr + 1'b1; + mem_rd_data <= mem[out_addr]; + end + end + + assign link_data = mem_rd_data; + + end + endgenerate + +endmodule diff --git a/adi_library/jesd204/jesd204_tx/jesd204_tx_header.v b/adi_library/jesd204/jesd204_tx/jesd204_tx_header.v new file mode 100644 index 00000000..a4269b35 --- /dev/null +++ b/adi_library/jesd204/jesd204_tx/jesd204_tx_header.v @@ -0,0 +1,69 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_tx_header ( + input clk, + input reset, + + input [1:0] cfg_header_mode, + + input lmc_edge, + input lmc_quarter_edge, + + // Header content to be sent must be valid during lmc_edge + input eoemb, + input [2:0] crc3, + input [11:0] crc12, + input [25:0] fec, + input [18:0] cmd, + + output [1:0] header +); + + reg header_bit; + reg [31:0] sync_word = 'h0; + + always @(posedge clk) begin + if (reset) begin + sync_word <= 'h0; + end else if (lmc_edge) begin + case (cfg_header_mode) + // CRC-12 + 2'b00 : sync_word <= {crc12[11:9],1'b1,crc12[8:6],1'b1, + crc12[5:3],1'b1,crc12[2:0],1'b1, + cmd[6:4],1'b1,cmd[3],1'b1,eoemb,1'b1, + cmd[2:0],5'b00001}; + // CRC-3 + 2'b01 : sync_word <= { crc3[2:0],1'b1,cmd[6:4],1'b1, + 3'b000,1'b1,cmd[3:1],1'b1, + 3'b000,1'b1,cmd[0],1'b1,eoemb,1'b1, + 3'b000,5'b00001}; + // FEC + 2'b10 : sync_word <= { fec[25:18], + fec[17:10], + fec[9:4],eoemb,fec[3], + fec[2:0],5'b00001}; + // Stand alone command + 2'b11 : sync_word <= { cmd[18:16],1'b1,cmd[15:13],1'b1, + cmd[12:10],1'b1,cmd[9:7],1'b1, + cmd[6:4],1'b1,cmd[3],1'b1,eoemb,1'b1, + cmd[2:0],5'b00001}; + endcase + end else begin + if (lmc_quarter_edge && cfg_header_mode == 2'b01) begin + sync_word <= {crc3[2],crc3[1],crc3[0],sync_word[27:0],1'b0}; + end else begin + sync_word <= {sync_word[30:0],1'b0}; + end + end + end + + assign header = {~sync_word[31],sync_word[31]}; + +endmodule diff --git a/adi_library/jesd204/jesd204_tx/jesd204_tx_hw.tcl b/adi_library/jesd204/jesd204_tx/jesd204_tx_hw.tcl new file mode 100644 index 00000000..b852dceb --- /dev/null +++ b/adi_library/jesd204/jesd204_tx/jesd204_tx_hw.tcl @@ -0,0 +1,214 @@ +############################################################################### +## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +package require qsys 14.0 + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl + +ad_ip_create jesd204_tx "ADI JESD204 Transmit" jesd204_tx_elaboration_callback + +set_module_property INTERNAL true + +# files + +ad_ip_files jesd204_tx [list \ + jesd204_tx.v \ + jesd204_tx_ctrl.v \ + jesd204_tx_lane.v \ + jesd204_tx_gearbox.v \ + jesd204_tx_constr.sdc \ + ../jesd204_common/jesd204_eof_generator.v \ + ../jesd204_common/jesd204_frame_align_replace.v \ + ../jesd204_common/jesd204_frame_mark.v \ + ../jesd204_common/jesd204_lmfc.v \ + ../jesd204_common/jesd204_scrambler.v \ + ../jesd204_common/pipeline_stage.v \ + $ad_hdl_dir/library/util_cdc/sync_bits.v \ + $ad_hdl_dir/library/util_cdc/sync_event.v \ + $ad_hdl_dir/library/util_cdc/util_cdc_constr.tcl \ + $ad_hdl_dir/library/common/ad_pack.v \ + $ad_hdl_dir/library/common/ad_upack.v \ +] + +# parameters + +add_parameter NUM_LANES INTEGER 1 +set_parameter_property NUM_LANES DISPLAY_NAME "Number of Lanes" +set_parameter_property NUM_LANES ALLOWED_RANGES 1:32 +set_parameter_property NUM_LANES HDL_PARAMETER true + +add_parameter NUM_LINKS INTEGER 1 +set_parameter_property NUM_LINKS DISPLAY_NAME "Number of Links" +set_parameter_property NUM_LINKS ALLOWED_RANGES 1:8 +set_parameter_property NUM_LINKS HDL_PARAMETER true + +add_parameter NUM_OUTPUT_PIPELINE INTEGER 0 +set_parameter_property NUM_OUTPUT_PIPELINE DISPLAY_NAME "Number of output pipeline stages" +set_parameter_property NUM_OUTPUT_PIPELINE ALLOWED_RANGES 0:3 +set_parameter_property NUM_OUTPUT_PIPELINE HDL_PARAMETER true + +add_parameter ASYNC_CLK BOOLEAN false +set_parameter_property ASYNC_CLK DISPLAY_NAME "Link and device clock asynchronous" +set_parameter_property ASYNC_CLK HDL_PARAMETER true + +ad_ip_parameter TPL_DATA_PATH_WIDTH INTEGER 4 true { \ + DISPLAY_NAME "Transport layer datapath width" \ + DISPLAY_UNITS "octets" \ + ALLOWED_RANGES {4 6 8 12} \ +} + +# link clock + +add_interface clock clock end +add_interface_port clock clk clk Input 1 + +# link clock reset + +add_interface reset reset end +set_interface_property reset associatedClock clock +set_interface_property reset synchronousEdges DEASSERT +add_interface_port reset reset reset Input 1 + +# device clock + +add_interface device_clock clock end +add_interface_port device_clock device_clk clk Input 1 + +# device clock reset + +add_interface device_reset reset end +set_interface_property device_reset associatedClock device_clock +set_interface_property device_reset synchronousEdges DEASSERT + +add_interface_port device_reset device_reset reset Input 1 + +# SYSREF~ interface + +add_interface sysref conduit end +set_interface_property sysref associatedClock device_clock +set_interface_property sysref associatedReset device_reset +add_interface_port sysref sysref export Input 1 + +# SYNC interface + +add_interface sync conduit end +set_interface_property sync associatedClock clock +set_interface_property sync associatedReset reset +add_interface_port sync sync export Input 1 + +# ilas_config interface + +add_interface ilas_config conduit end +set_interface_property ilas_config associatedClock clock +set_interface_property ilas_config associatedReset reset + +add_interface_port ilas_config ilas_config_addr addr Output 2 +add_interface_port ilas_config ilas_config_data data Input 32*NUM_LANES +add_interface_port ilas_config ilas_config_rd rd Output 1 + +# event interface + +add_interface device_event conduit end +set_interface_property device_event associatedClock device_clock +set_interface_property device_event associatedReset device_reset + +add_interface_port device_event device_event_sysref_alignment_error sysref_alignment_error Output 1 +add_interface_port device_event device_event_sysref_edge sysref_edge Output 1 + +# control interface + +add_interface control conduit end +set_interface_property control associatedClock clock +set_interface_property control associatedReset reset + +add_interface_port control ctrl_manual_sync_request manual_sync_request Input 1 + +# config interface + +add_interface config conduit end +set_interface_property config associatedClock clock +set_interface_property config associatedReset reset + +add_interface_port config cfg_octets_per_multiframe octets_per_multiframe Input 10 +add_interface_port config cfg_continuous_cgs continuous_cgs Input 1 +add_interface_port config cfg_continuous_ilas continuous_ilas Input 1 +add_interface_port config cfg_disable_char_replacement disable_char_replacement Input 1 +add_interface_port config cfg_disable_scrambler disable_scrambler Input 1 +add_interface_port config cfg_lanes_disable lanes_disable Input NUM_LANES +add_interface_port config cfg_links_disable links_disable Input NUM_LINKS +add_interface_port config cfg_mframes_per_ilas mframes_per_ilas Input 8 +add_interface_port config cfg_octets_per_frame octets_per_frame Input 8 +add_interface_port config cfg_skip_ilas skip_ilas Input 1 + +# device clock domain config interface + +add_interface device_config conduit end +set_interface_property device_config associatedClock device_clock +set_interface_property device_config associatedReset device_reset + +add_interface_port device_config device_cfg_octets_per_multiframe octets_per_multiframe Input 10 +add_interface_port device_config device_cfg_octets_per_frame octets_per_frame Input 8 +add_interface_port device_config device_cfg_beats_per_multiframe beats_per_multiframe Input 8 +add_interface_port device_config device_cfg_lmfc_offset lmfc_offset Input 8 +add_interface_port device_config device_cfg_sysref_disable sysref_disable Input 1 +add_interface_port device_config device_cfg_sysref_oneshot sysref_oneshot Input 1 + +# status interface + +add_interface status conduit end +set_interface_property status associatedClock clock +set_interface_property status associatedReset reset + +add_interface_port status status_state state Output 2 +add_interface_port status status_sync sync Output 1 +add_interface_port status status_synth_params0 synth_params0 Output 32 +add_interface_port status status_synth_params1 synth_params1 Output 32 +add_interface_port status status_synth_params2 synth_params2 Output 32 + +# lmfc_clk interface + +add_interface lmfc_clk conduit end +#set_interface_property lmfc_clk associatedClock clock +#set_interface_property lmfc_clk associatedReset reset +add_interface_port lmfc_clk lmfc_clk export Output 1 +set_port_property lmfc_clk TERMINATION TRUE + +# lmfc_edge interface + +add_interface lmfc_edge conduit end +#set_interface_property lmfc_edge associatedClock clock +#set_interface_property lmfc_edge associatedReset reset +add_interface_port lmfc_edge lmfc_edge export Output 1 +set_port_property lmfc_edge TERMINATION TRUE + +proc jesd204_tx_elaboration_callback {} { + set num_lanes [get_parameter_value "NUM_LANES"] + set tpl_width [get_parameter_value "TPL_DATA_PATH_WIDTH"] + + # tx_data interface + + add_interface tx_data avalon_streaming sink + set_interface_property tx_data associatedClock device_clock + + add_interface_port tx_data tx_data data input [expr 8*$tpl_width*$num_lanes] + add_interface_port tx_data tx_ready ready output 1 + add_interface_port tx_data tx_valid valid input 1 + set_interface_property tx_data dataBitsPerSymbol [expr 8*$tpl_width*$num_lanes] + + # phy interfaces + + for {set i 0 } {$i < $num_lanes} {incr i} { + add_interface tx_phy${i} conduit start +# set_interface_property tx_phy${i} associatedClock clock +# set_interface_property tx_phy${i} associatedReset reset + add_interface_port tx_phy${i} tx_phy${i}_data char Output 32 + set_port_property tx_phy${i}_data fragment_list \ + [format "phy_data(%d:%d)" [expr 32*$i+31] [expr 32*$i]] + add_interface_port tx_phy${i} tx_phy${i}_charisk charisk Output 4 + set_port_property tx_phy${i}_charisk fragment_list \ + [format "phy_charisk(%d:%d)" [expr 4*$i+3] [expr 4*$i]] + } +} diff --git a/adi_library/jesd204/jesd204_tx/jesd204_tx_ip.tcl b/adi_library/jesd204/jesd204_tx/jesd204_tx_ip.tcl new file mode 100644 index 00000000..ab491bc9 --- /dev/null +++ b/adi_library/jesd204/jesd204_tx/jesd204_tx_ip.tcl @@ -0,0 +1,180 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create jesd204_tx +adi_ip_files jesd204_tx [list \ + "jesd204_tx_lane.v" \ + "jesd204_tx_lane_64b.v" \ + "jesd204_tx_header.v" \ + "jesd204_tx_gearbox.v" \ + "jesd204_tx_ctrl.v" \ + "jesd204_tx_constr.ttcl" \ + "jesd204_tx_ooc.ttcl" \ + "../../common/ad_pack.v" \ + "../../common/ad_upack.v" \ + "jesd204_tx.v" \ + "bd/bd.tcl" +] + +set_property source_mgmt_mode DisplayOnly [current_project] + +adi_ip_properties_lite jesd204_tx +adi_ip_ttcl jesd204_tx "jesd204_tx_constr.ttcl" +adi_ip_ttcl jesd204_tx "jesd204_tx_ooc.ttcl" +adi_ip_bd jesd204_tx "bd/bd.tcl" + +adi_ip_add_core_dependencies [list \ + analog.com:$VIVADO_IP_LIBRARY:jesd204_common:1.0 \ + analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \ +] + +set_property display_name "ADI JESD204 Transmit" [ipx::current_core] +set_property description "ADI JESD204 Transmit" [ipx::current_core] + +adi_add_bus "tx_data" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { \ + { "tx_valid" "TVALID" } \ + { "tx_ready" "TREADY" } \ + { "tx_data" "TDATA" } \ + } + +adi_add_multi_bus 32 "tx_phy" "master" \ + "xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0" \ + "xilinx.com:display_jesd204:jesd204_tx_bus:1.0" \ + [list \ + { "phy_data" "txdata" 32 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')) * 8)"} \ + { "phy_charisk" "txcharisk" 4 "(spirit:decode(id('MODELPARAM_VALUE.DATA_PATH_WIDTH')))"} \ + { "phy_header" "txheader" 2} \ + ] \ + "(spirit:decode(id('MODELPARAM_VALUE.NUM_LANES')) > {i})" + +adi_add_bus "tx_cfg" "slave" \ + "analog.com:interface:jesd204_tx_cfg_rtl:1.0" \ + "analog.com:interface:jesd204_tx_cfg:1.0" \ + { \ + { "cfg_lanes_disable" "lanes_disable" } \ + { "cfg_links_disable" "links_disable" } \ + { "cfg_octets_per_multiframe" "octets_per_multiframe" } \ + { "cfg_octets_per_frame" "octets_per_frame" } \ + { "cfg_continuous_cgs" "continuous_cgs" } \ + { "cfg_continuous_ilas" "continuous_ilas" } \ + { "cfg_skip_ilas" "skip_ilas" } \ + { "cfg_mframes_per_ilas" "mframes_per_ilas" } \ + { "cfg_disable_char_replacement" "disable_char_replacement" } \ + { "cfg_disable_scrambler" "disable_scrambler" } \ + { "device_cfg_octets_per_multiframe" "device_octets_per_multiframe" } \ + { "device_cfg_octets_per_frame" "device_octets_per_frame" } \ + { "device_cfg_beats_per_multiframe" "device_beats_per_multiframe" } \ + { "device_cfg_lmfc_offset" "device_lmfc_offset" } \ + { "device_cfg_sysref_oneshot" "device_sysref_oneshot" } \ + { "device_cfg_sysref_disable" "device_sysref_disable" } \ + } + +adi_add_bus "tx_ilas_config" "master" \ + "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" \ + "analog.com:interface:jesd204_tx_ilas_config:1.0" \ + { \ + { "ilas_config_rd" "rd" } \ + { "ilas_config_addr" "addr" } \ + { "ilas_config_data" "data" } \ + } + +adi_add_bus "tx_event" "master" \ + "analog.com:interface:jesd204_tx_event_rtl:1.0" \ + "analog.com:interface:jesd204_tx_event:1.0" \ + { \ + { "device_event_sysref_alignment_error" "sysref_alignment_error" } \ + { "device_event_sysref_edge" "sysref_edge" } \ + } + +adi_add_bus "tx_status" "master" \ + "analog.com:interface:jesd204_tx_status_rtl:1.0" \ + "analog.com:interface:jesd204_tx_status:1.0" \ + { \ + { "status_state" "state" } \ + { "status_sync" "sync" } \ + { "status_synth_params0" "synth_params0" } \ + { "status_synth_params1" "synth_params1" } \ + { "status_synth_params2" "synth_params2" } \ + } + +adi_add_bus "tx_ctrl" "slave" \ + "analog.com:interface:jesd204_tx_ctrl_rtl:1.0" \ + "analog.com:interface:jesd204_tx_ctrl:1.0" \ + { \ + { "ctrl_manual_sync_request" "manual_sync_request" } \ + } + +adi_add_bus_clock "clk" "tx_cfg:tx_ilas_config:tx_event:tx_status:tx_ctrl" "reset" + +adi_add_bus_clock "device_clk" "tx_data" "device_reset" + +adi_set_bus_dependency "tx_ilas_config" "tx_ilas_config" \ + "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" + +adi_set_bus_dependency "tx_ctrl" "tx_ctrl" \ + "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" + +adi_set_ports_dependency "sync" \ + "(spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 1)" + + +set cc [ipx::current_core] +set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] + +# Link layer mode +set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $page0 +set_property -dict [list \ + "display_name" "Link Layer mode" \ + "tooltip" "Link Layer mode" \ + "widget" "comboBox" \ +] $p + +set_property -dict [list \ + value_validation_type pairs \ + value_validation_pairs {64B66B 2 8B10B 1} \ +] [ipx::get_user_parameters $p -of_objects $cc] + + +# Data width selection +set param [ipx::get_user_parameters DATA_PATH_WIDTH -of_objects $cc] +set_property -dict [list \ + enablement_tcl_expr {$LINK_MODE==1} \ + value_tcl_expr {expr $LINK_MODE*4} \ +] $param + + +# SYSREF IOB placement +set param [ipx::add_user_parameter SYSREF_IOB $cc] +set_property -dict {value_resolve_type user value_format bool value true} $param + +set param [ipgui::add_param -name {SYSREF_IOB} -component $cc -parent $page0] +set_property -dict [list \ + display_name {Place SYSREF in IOB} \ + widget {checkBox} \ + show_label true \ +] $param + + +set clk_group [ipgui::add_group -name {Clock Domain Configuration} -component $cc \ + -parent $page0 -display_name {Clock Domain Configuration}] + +set p [ipgui::get_guiparamspec -name "ASYNC_CLK" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $clk_group +set_property -dict [list \ + "display_name" "Link and Device Clock Asynchronous" \ + "widget" "checkBox" \ +] $p + +ipx::create_xgui_files [ipx::current_core] +ipx::save_core [ipx::current_core] diff --git a/adi_library/jesd204/jesd204_tx/jesd204_tx_lane.v b/adi_library/jesd204/jesd204_tx/jesd204_tx_lane.v new file mode 100755 index 00000000..8fb6bf27 --- /dev/null +++ b/adi_library/jesd204/jesd204_tx/jesd204_tx_lane.v @@ -0,0 +1,143 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_tx_lane #( + parameter DATA_PATH_WIDTH = 4, + parameter ENABLE_CHAR_REPLACE = 1'b0 +) ( + input clk, + + input [DATA_PATH_WIDTH-1:0] eof, + input [DATA_PATH_WIDTH-1:0] eomf, + + input cgs_enable, + + input [DATA_PATH_WIDTH*8-1:0] ilas_data, + input [DATA_PATH_WIDTH-1:0] ilas_charisk, + + input [DATA_PATH_WIDTH*8-1:0] tx_data, + input tx_ready, + + output reg [DATA_PATH_WIDTH*8-1:0] phy_data, + output reg [DATA_PATH_WIDTH-1:0] phy_charisk, + + input [7:0] cfg_octets_per_frame, + input cfg_disable_char_replacement, + input cfg_disable_scrambler +); + + wire [DATA_PATH_WIDTH*8-1:0] scrambled_data; + wire [DATA_PATH_WIDTH*8-1:0] scrambled_data_d; + wire cgs_enable_d; + wire tx_ready_d; + wire [DATA_PATH_WIDTH-1:0] eof_d; + wire [DATA_PATH_WIDTH-1:0] eomf_d; + wire [DATA_PATH_WIDTH*8-1:0] ilas_data_d; + wire [DATA_PATH_WIDTH-1:0] ilas_charisk_d; + wire [DATA_PATH_WIDTH*8-1:0] data_replaced; + wire [DATA_PATH_WIDTH-1:0] charisk_replaced; + wire [7:0] scrambled_char[0:DATA_PATH_WIDTH-1]; + reg [7:0] char_align[0:DATA_PATH_WIDTH-1]; + + jesd204_scrambler #( + .WIDTH (DATA_PATH_WIDTH*8), + .DESCRAMBLE (0) + ) i_scrambler ( + .clk (clk), + .reset (~tx_ready), + .enable (~cfg_disable_scrambler), + .data_in (tx_data), + .data_out (scrambled_data)); + + pipeline_stage #( + .WIDTH ((DATA_PATH_WIDTH*19) + 2), + .REGISTERED (1) + ) i_lane_pipeline_stage ( + .clk(clk), + .in({ + cgs_enable, + tx_ready, + eof, + eomf, + scrambled_data, + ilas_data, + ilas_charisk + }), + .out({ + cgs_enable_d, + tx_ready_d, + eof_d, + eomf_d, + scrambled_data_d, + ilas_data_d, + ilas_charisk_d + })); + + jesd204_frame_align_replace #( + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .IS_RX (1'b0), + .ENABLED (ENABLE_CHAR_REPLACE) + ) i_align_replace ( + .clk (clk), + .reset (~tx_ready_d), + .cfg_octets_per_frame (cfg_octets_per_frame), + .cfg_disable_char_replacement (cfg_disable_char_replacement), + .cfg_disable_scrambler (cfg_disable_scrambler), + .data (scrambled_data_d), + .eof (eof_d), + .rx_char_is_a ({DATA_PATH_WIDTH{1'b0}}), + .rx_char_is_f ({DATA_PATH_WIDTH{1'b0}}), + .tx_eomf (eomf_d), + .data_out (data_replaced), + .charisk_out (charisk_replaced)); + + generate + genvar i; + + for (i = 0; i < DATA_PATH_WIDTH; i = i + 1) begin: gen_char + assign scrambled_char[i] = scrambled_data_d[i*8+7:i*8]; + + always @(*) begin + if (eomf_d[i]) begin + char_align[i] = 8'h7c; // /A/ + end else begin + char_align[i] = 8'hfc; // /F/ + end + end + + always @(posedge clk) begin + if (cgs_enable_d) begin + phy_charisk[i] <= 1'b1; + end else if (tx_ready_d) begin + if(!cfg_disable_scrambler) begin + phy_charisk[i] <= eof_d[i] && (scrambled_char[i] == char_align[i]); + end else begin + phy_charisk[i] <= charisk_replaced[i]; + end + end else begin + phy_charisk[i] <= ilas_charisk_d[i]; + end + end + end + + endgenerate + + always @(posedge clk) begin + if (cgs_enable_d) begin + phy_data <= {DATA_PATH_WIDTH{8'hbc}}; + end else begin + if(tx_ready_d) begin + phy_data <= data_replaced; + end else begin + phy_data <= ilas_data_d; + end + end + end + +endmodule diff --git a/adi_library/jesd204/jesd204_tx/jesd204_tx_lane_64b.v b/adi_library/jesd204/jesd204_tx/jesd204_tx_lane_64b.v new file mode 100644 index 00000000..eb2e293f --- /dev/null +++ b/adi_library/jesd204/jesd204_tx/jesd204_tx_lane_64b.v @@ -0,0 +1,100 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_tx_lane_64b ( + input clk, + input reset, + + input [63:0] tx_data, + input tx_ready, + + output reg [63:0] phy_data, + output [1:0] phy_header, + + input lmc_edge, + input lmc_quarter_edge, + input eoemb, + + // Scrambling mandatory in 64bxxb, keep this for debugging purposes + input cfg_disable_scrambler, + input [1:0] cfg_header_mode, + input cfg_lane_disable +); + + reg [63:0] scrambled_data; + reg lmc_edge_d1 = 'b0; + reg lmc_edge_d2 = 'b0; + reg lmc_quarter_edge_d1 = 'b0; + reg lmc_quarter_edge_d2 = 'b0; + reg tx_ready_d1 = 'b0; + + wire [63:0] tx_data_msb_s; + wire [63:0] scrambled_data_r; + wire [11:0] crc12; + + /* Reorder octets MSB first */ + genvar i; + generate + for (i = 0; i < 64; i = i + 8) begin: g_link_data + assign tx_data_msb_s[i+:8] = tx_data[64-1-i-:8]; + end + endgenerate + + jesd204_scrambler_64b #( + .WIDTH(64), + .DESCRAMBLE(0) + ) i_scrambler ( + .clk(clk), + .reset(1'b0), + .enable(~cfg_disable_scrambler), + .data_in(tx_data_msb_s), + .data_out(scrambled_data_r)); + + always @(posedge clk) begin + lmc_edge_d1 <= lmc_edge; + lmc_edge_d2 <= lmc_edge_d1; + lmc_quarter_edge_d1 <= lmc_quarter_edge; + lmc_quarter_edge_d2 <= lmc_quarter_edge_d1; + end + + always @(posedge clk) begin + scrambled_data <= scrambled_data_r; + phy_data <= scrambled_data; + end + + always @(posedge clk) begin + tx_ready_d1 <= tx_ready; + end + + jesd204_crc12 i_crc12 ( + .clk(clk), + .reset(~tx_ready_d1), + .init(lmc_edge_d2), + .data_in(scrambled_data), + .crc12(crc12)); + + jesd204_tx_header i_header_gen ( + .clk(clk), + .reset(~tx_ready | cfg_lane_disable), + + .cfg_header_mode(cfg_header_mode), + + .lmc_edge(lmc_edge_d2), + .lmc_quarter_edge(lmc_quarter_edge_d2), + + // Header content to be sent must be valid during lmc_edge + .eoemb(eoemb), + .crc3(3'b0), + .crc12(crc12), + .fec(26'b0), + .cmd(19'b0), + + .header(phy_header)); + +endmodule diff --git a/adi_library/jesd204/jesd204_tx/jesd204_tx_ooc.ttcl b/adi_library/jesd204/jesd204_tx/jesd204_tx_ooc.ttcl new file mode 100644 index 00000000..3eba1ddb --- /dev/null +++ b/adi_library/jesd204/jesd204_tx/jesd204_tx_ooc.ttcl @@ -0,0 +1,22 @@ +############################################################################### +## Copyright (C) 2017-2019, 2021 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +<: setFileUsedIn { out_of_context synthesis implementation } :> +<: ;#Component and file information :> +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName $ComponentName :> +<: setFileExtension "_ooc.xdc" :> + +# This XDC is used only for OOC mode of synthesis, implementation. +# These are default values for timing driven synthesis during OOC flow. +# These values will be overwritten during implementation with information +# from top level. + +create_clock -name clk -period 2.5 [get_ports clk] +create_clock -name device_clk -period 2.5 [get_ports device_clk] + +################################################################################ + diff --git a/adi_library/jesd204/jesd204_tx/xgui/jesd204_tx_v1_0.tcl b/adi_library/jesd204/jesd204_tx/xgui/jesd204_tx_v1_0.tcl new file mode 100644 index 00000000..41e3ebdd --- /dev/null +++ b/adi_library/jesd204/jesd204_tx/xgui/jesd204_tx_v1_0.tcl @@ -0,0 +1,157 @@ + +# Loading additional proc with user specified bodies to compute parameter values. +source [file join [file dirname [file dirname [info script]]] gui/jesd204_tx_v1_0.gtcl] + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "LINK_MODE" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "DATA_PATH_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "ENABLE_CHAR_REPLACE" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_LANES" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_LINKS" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_OUTPUT_PIPELINE" -parent ${Page_0} + ipgui::add_param $IPINST -name "TPL_DATA_PATH_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "SYSREF_IOB" -parent ${Page_0} + #Adding Group + set Clock_Domain_Configuration [ipgui::add_group $IPINST -name "Clock Domain Configuration" -parent ${Page_0}] + ipgui::add_param $IPINST -name "ASYNC_CLK" -parent ${Clock_Domain_Configuration} -widget checkBox + + + +} + +proc update_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH PARAM_VALUE.LINK_MODE } { + # Procedure called to update DATA_PATH_WIDTH when any of the dependent parameters in the arguments change + + set DATA_PATH_WIDTH ${PARAM_VALUE.DATA_PATH_WIDTH} + set LINK_MODE ${PARAM_VALUE.LINK_MODE} + set values(LINK_MODE) [get_property value $LINK_MODE] + if { [gen_USERPARAMETER_DATA_PATH_WIDTH_ENABLEMENT $values(LINK_MODE)] } { + set_property enabled true $DATA_PATH_WIDTH + } else { + set_property enabled false $DATA_PATH_WIDTH + set_property value [gen_USERPARAMETER_DATA_PATH_WIDTH_VALUE $values(LINK_MODE)] $DATA_PATH_WIDTH + } +} + +proc validate_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH } { + # Procedure called to validate DATA_PATH_WIDTH + return true +} + +proc update_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } { + # Procedure called to update ASYNC_CLK when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } { + # Procedure called to validate ASYNC_CLK + return true +} + +proc update_PARAM_VALUE.ENABLE_CHAR_REPLACE { PARAM_VALUE.ENABLE_CHAR_REPLACE } { + # Procedure called to update ENABLE_CHAR_REPLACE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ENABLE_CHAR_REPLACE { PARAM_VALUE.ENABLE_CHAR_REPLACE } { + # Procedure called to validate ENABLE_CHAR_REPLACE + return true +} + +proc update_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } { + # Procedure called to update LINK_MODE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } { + # Procedure called to validate LINK_MODE + return true +} + +proc update_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } { + # Procedure called to update NUM_LANES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } { + # Procedure called to validate NUM_LANES + return true +} + +proc update_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } { + # Procedure called to update NUM_LINKS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } { + # Procedure called to validate NUM_LINKS + return true +} + +proc update_PARAM_VALUE.NUM_OUTPUT_PIPELINE { PARAM_VALUE.NUM_OUTPUT_PIPELINE } { + # Procedure called to update NUM_OUTPUT_PIPELINE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OUTPUT_PIPELINE { PARAM_VALUE.NUM_OUTPUT_PIPELINE } { + # Procedure called to validate NUM_OUTPUT_PIPELINE + return true +} + +proc update_PARAM_VALUE.SYSREF_IOB { PARAM_VALUE.SYSREF_IOB } { + # Procedure called to update SYSREF_IOB when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SYSREF_IOB { PARAM_VALUE.SYSREF_IOB } { + # Procedure called to validate SYSREF_IOB + return true +} + +proc update_PARAM_VALUE.TPL_DATA_PATH_WIDTH { PARAM_VALUE.TPL_DATA_PATH_WIDTH } { + # Procedure called to update TPL_DATA_PATH_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TPL_DATA_PATH_WIDTH { PARAM_VALUE.TPL_DATA_PATH_WIDTH } { + # Procedure called to validate TPL_DATA_PATH_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.NUM_LANES { MODELPARAM_VALUE.NUM_LANES PARAM_VALUE.NUM_LANES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_LANES}] ${MODELPARAM_VALUE.NUM_LANES} +} + +proc update_MODELPARAM_VALUE.NUM_LINKS { MODELPARAM_VALUE.NUM_LINKS PARAM_VALUE.NUM_LINKS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_LINKS}] ${MODELPARAM_VALUE.NUM_LINKS} +} + +proc update_MODELPARAM_VALUE.NUM_OUTPUT_PIPELINE { MODELPARAM_VALUE.NUM_OUTPUT_PIPELINE PARAM_VALUE.NUM_OUTPUT_PIPELINE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OUTPUT_PIPELINE}] ${MODELPARAM_VALUE.NUM_OUTPUT_PIPELINE} +} + +proc update_MODELPARAM_VALUE.LINK_MODE { MODELPARAM_VALUE.LINK_MODE PARAM_VALUE.LINK_MODE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LINK_MODE}] ${MODELPARAM_VALUE.LINK_MODE} +} + +proc update_MODELPARAM_VALUE.DATA_PATH_WIDTH { MODELPARAM_VALUE.DATA_PATH_WIDTH PARAM_VALUE.DATA_PATH_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_PATH_WIDTH}] ${MODELPARAM_VALUE.DATA_PATH_WIDTH} +} + +proc update_MODELPARAM_VALUE.TPL_DATA_PATH_WIDTH { MODELPARAM_VALUE.TPL_DATA_PATH_WIDTH PARAM_VALUE.TPL_DATA_PATH_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TPL_DATA_PATH_WIDTH}] ${MODELPARAM_VALUE.TPL_DATA_PATH_WIDTH} +} + +proc update_MODELPARAM_VALUE.ENABLE_CHAR_REPLACE { MODELPARAM_VALUE.ENABLE_CHAR_REPLACE PARAM_VALUE.ENABLE_CHAR_REPLACE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ENABLE_CHAR_REPLACE}] ${MODELPARAM_VALUE.ENABLE_CHAR_REPLACE} +} + +proc update_MODELPARAM_VALUE.ASYNC_CLK { MODELPARAM_VALUE.ASYNC_CLK PARAM_VALUE.ASYNC_CLK } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK}] ${MODELPARAM_VALUE.ASYNC_CLK} +} + diff --git a/adi_library/jesd204/jesd204_tx_static_config/Makefile b/adi_library/jesd204/jesd204_tx_static_config/Makefile new file mode 100644 index 00000000..1ee79a2b --- /dev/null +++ b/adi_library/jesd204/jesd204_tx_static_config/Makefile @@ -0,0 +1,21 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := jesd204_tx_static_config + +GENERIC_DEPS += jesd204_ilas_cfg_static.v +GENERIC_DEPS += jesd204_tx_static_config.v + +XILINX_DEPS += jesd204_tx_static_config_ip.tcl + +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg_rtl.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config.xml +XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config_rtl.xml + +XILINX_INTERFACE_DEPS += jesd204/interfaces + +include ../../scripts/library.mk diff --git a/adi_library/jesd204/jesd204_tx_static_config/component.xml b/adi_library/jesd204/jesd204_tx_static_config/component.xml new file mode 100644 index 00000000..953c233a --- /dev/null +++ b/adi_library/jesd204/jesd204_tx_static_config/component.xml @@ -0,0 +1,787 @@ + + + analog.com + user + jesd204_tx_static_config + 1.0 + + + tx_cfg + + + + + + + lanes_disable + + + cfg_lanes_disable + + + + + links_disable + + + cfg_links_disable + + + + + octets_per_multiframe + + + cfg_octets_per_multiframe + + + + + octets_per_frame + + + cfg_octets_per_frame + + + + + continuous_cgs + + + cfg_continuous_cgs + + + + + continuous_ilas + + + cfg_continuous_ilas + + + + + skip_ilas + + + cfg_skip_ilas + + + + + mframes_per_ilas + + + cfg_mframes_per_ilas + + + + + disable_char_replacement + + + cfg_disable_char_replacement + + + + + disable_scrambler + + + cfg_disable_scrambler + + + + + device_octets_per_multiframe + + + device_cfg_octets_per_multiframe + + + + + device_octets_per_frame + + + device_cfg_octets_per_frame + + + + + device_beats_per_multiframe + + + device_cfg_beats_per_multiframe + + + + + device_lmfc_offset + + + device_cfg_lmfc_offset + + + + + device_sysref_oneshot + + + device_cfg_sysref_oneshot + + + + + device_sysref_disable + + + device_cfg_sysref_disable + + + + + + tx_ilas_config + + + + + + + rd + + + ilas_config_rd + + + + + addr + + + ilas_config_addr + + + + + data + + + ilas_config_data + + + + + + tx_cfg_tx_ilas_config_signal_clock + tx_cfg_tx_ilas_config_signal_clock + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_BUSIF + tx_cfg:tx_ilas_config + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + jesd204_tx_static_config + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + f2d29d60 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + jesd204_tx_static_config + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + f2d29d60 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 5557730d + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_lanes_disable + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_links_disable + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_octets_per_multiframe + + out + + 9 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_octets_per_frame + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_continuous_cgs + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_continuous_ilas + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_skip_ilas + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_mframes_per_ilas + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_disable_char_replacement + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cfg_disable_scrambler + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_octets_per_multiframe + + out + + 9 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_octets_per_frame + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_beats_per_multiframe + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_lmfc_offset + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_sysref_oneshot + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + device_cfg_sysref_disable + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ilas_config_rd + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ilas_config_addr + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ilas_config_data + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + NUM_LANES + Num Lanes + 1 + + + NUM_LINKS + Num Links + 1 + + + OCTETS_PER_FRAME + Octets Per Frame + 1 + + + FRAMES_PER_MULTIFRAME + Frames Per Multiframe + 32 + + + NUM_CONVERTERS + Num Converters + 1 + + + N + N + 16 + + + NP + Np + 16 + + + HIGH_DENSITY + High Density + 1 + + + SCR + Scr + 1 + + + LINK_MODE + Link Mode + 1 + + + SYSREF_DISABLE + Sysref Disable + 0 + + + SYSREF_ONE_SHOT + Sysref One Shot + 0 + + + DATA_PATH_WIDTH + Data Path Width + 4 + + + TPL_DATA_PATH_WIDTH + Tpl Data Path Width + 4 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + jesd204_ilas_cfg_static.v + verilogSource + + + jesd204_tx_static_config.v + verilogSource + CHECKSUM_c8a1b22f + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + jesd204_ilas_cfg_static.v + verilogSource + + + jesd204_tx_static_config.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/jesd204_tx_static_config_v1_0.tcl + tclSource + CHECKSUM_5557730d + XGUI_VERSION_2 + + + + jesd204_tx_static_config_v1_0 + + + NUM_LANES + Num Lanes + 1 + + + NUM_LINKS + Num Links + 1 + + + OCTETS_PER_FRAME + Octets Per Frame + 1 + + + FRAMES_PER_MULTIFRAME + Frames Per Multiframe + 32 + + + NUM_CONVERTERS + Num Converters + 1 + + + N + N + 16 + + + NP + Np + 16 + + + HIGH_DENSITY + High Density + 1 + + + SCR + Scr + 1 + + + LINK_MODE + Link Mode + 1 + + + SYSREF_DISABLE + Sysref Disable + 0 + + + SYSREF_ONE_SHOT + Sysref One Shot + 0 + + + DATA_PATH_WIDTH + Data Path Width + 4 + + + TPL_DATA_PATH_WIDTH + Tpl Data Path Width + 4 + + + Component_Name + jesd204_tx_static_config_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + jesd204_tx_static_config_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:52:09Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v b/adi_library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v new file mode 100755 index 00000000..7335b6c9 --- /dev/null +++ b/adi_library/jesd204/jesd204_tx_static_config/jesd204_ilas_cfg_static.v @@ -0,0 +1,99 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_ilas_cfg_static #( + parameter DID = 8'h00, + parameter BID = 4'h0, + parameter L = 5'h3, + parameter SCR = 1'b1, + parameter F = 8'h01, + parameter K = 5'h1f, + parameter M = 8'h3, + parameter N = 5'h0f, + parameter CS = 2'h0, + parameter NP = 5'h0f, + parameter SUBCLASSV = 3'h1, + parameter S = 5'h00, + parameter JESDV = 3'h1, + parameter CF = 5'h00, + parameter HD = 1'b1, + parameter NUM_LANES = 1, + parameter DATA_PATH_WIDTH = 4 +) ( + input clk, + + input [1:0] ilas_config_addr, + input ilas_config_rd, + output reg [NUM_LANES*DATA_PATH_WIDTH*8-1:0] ilas_config_data +); + + wire [31:0] ilas_mem[0:3]; + reg [31:0] ilas_lane_mem[0:NUM_LANES-1][0:3]; + + assign ilas_mem[0][15:0] = 8'h00; + assign ilas_mem[0][23:16] = DID; // DID + assign ilas_mem[0][27:24] = BID; // BID + assign ilas_mem[0][31:28] = 4'h0; // ADJCNT + assign ilas_mem[1][4:0] = 5'h00; // LID + assign ilas_mem[1][5] = 1'b0; // PHADJ + assign ilas_mem[1][6] = 1'b0; // ADJDIR + assign ilas_mem[1][7] = 1'b0; // X + assign ilas_mem[1][12:8] = L; // L + assign ilas_mem[1][14:13] = 2'b00; // X + assign ilas_mem[1][15] = SCR; // SCR + assign ilas_mem[1][23:16] = F; // F + assign ilas_mem[1][28:24] = K; // K + assign ilas_mem[1][31:29] = 3'b000; // X + assign ilas_mem[2][7:0] = M; // M + assign ilas_mem[2][12:8] = N; // N + assign ilas_mem[2][13] = 1'b0; // X + assign ilas_mem[2][15:14] = CS; // CS + assign ilas_mem[2][20:16] = NP; // N' + assign ilas_mem[2][23:21] = SUBCLASSV; // SUBCLASSV + assign ilas_mem[2][28:24] = S; // S + assign ilas_mem[2][31:29] = JESDV; // JESDV + assign ilas_mem[3][4:0] = CF; // CF + assign ilas_mem[3][6:5] = 2'b00; // X + assign ilas_mem[3][7] = HD; // HD + assign ilas_mem[3][23:8] = 16'h0000; // X + assign ilas_mem[3][31:24] = ilas_mem[0][23:16] + ilas_mem[0][31:24] + + ilas_mem[1][4:0] + ilas_mem[1][5] + ilas_mem[1][6] + ilas_mem[1][12:8] + + ilas_mem[1][15] + ilas_mem[1][23:16] + ilas_mem[1][28:24] + + ilas_mem[2][7:0] + ilas_mem[2][12:8] + ilas_mem[2][15:14] + + ilas_mem[2][20:16] + ilas_mem[2][23:21] + ilas_mem[2][28:24] + + ilas_mem[2][31:29] + ilas_mem[3][4:0] + ilas_mem[3][7]; + + generate + genvar i; + genvar j; + + for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane + for(j = 0; j < 4; j = j + 1) begin : gen_word + always @(*) begin + ilas_lane_mem[i][j] = ilas_mem[j]; + case(j) + 1: ilas_lane_mem[i][j][4:0] = i; + 3: ilas_lane_mem[i][j][31:24] = ilas_mem[3][31:24] + i; + endcase + end + end + + always @(posedge clk) begin + if (ilas_config_rd == 1'b1) begin + if(DATA_PATH_WIDTH == 4) begin + ilas_config_data[i*32+31:i*32] <= ilas_lane_mem[i][ilas_config_addr]; + end else begin + ilas_config_data[i*64+63:i*64] <= {ilas_lane_mem[i][{ilas_config_addr[0], 1'b1}], ilas_lane_mem[i][{ilas_config_addr[0], 1'b0}]}; + end + end + end + end + endgenerate + +endmodule diff --git a/adi_library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v b/adi_library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v new file mode 100755 index 00000000..fd7add3f --- /dev/null +++ b/adi_library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.v @@ -0,0 +1,94 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_tx_static_config #( + parameter NUM_LANES = 1, + parameter NUM_LINKS = 1, + parameter OCTETS_PER_FRAME = 1, + parameter FRAMES_PER_MULTIFRAME = 32, + parameter NUM_CONVERTERS = 1, + parameter N = 16, + parameter NP = 16, + parameter HIGH_DENSITY = 1, + parameter SCR = 1, + parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B + parameter SYSREF_DISABLE = 0, + parameter SYSREF_ONE_SHOT = 0, + /* Only 4, 8 are supported at the moment for 8b/10b and 8 for 64b */ + parameter DATA_PATH_WIDTH = LINK_MODE == 2 ? 8 : 4, + parameter TPL_DATA_PATH_WIDTH = LINK_MODE == 2 ? 8 : 4 +) ( + input clk, + + output [NUM_LANES-1:0] cfg_lanes_disable, + output [NUM_LINKS-1:0] cfg_links_disable, + output [9:0] cfg_octets_per_multiframe, + output [7:0] cfg_octets_per_frame, + output cfg_continuous_cgs, + output cfg_continuous_ilas, + output cfg_skip_ilas, + output [7:0] cfg_mframes_per_ilas, + output cfg_disable_char_replacement, + output cfg_disable_scrambler, + + output [9:0] device_cfg_octets_per_multiframe, + output [7:0] device_cfg_octets_per_frame, + output [7:0] device_cfg_beats_per_multiframe, + output [7:0] device_cfg_lmfc_offset, + output device_cfg_sysref_oneshot, + output device_cfg_sysref_disable, + + input ilas_config_rd, + input [1:0] ilas_config_addr, + output [NUM_LANES*DATA_PATH_WIDTH*8-1:0] ilas_config_data +); + + assign cfg_lanes_disable = {NUM_LANES{1'b0}}; + assign cfg_links_disable = {NUM_LINKS{1'b0}}; + assign cfg_octets_per_multiframe = (FRAMES_PER_MULTIFRAME * OCTETS_PER_FRAME) - 1; + assign cfg_octets_per_frame = OCTETS_PER_FRAME - 1; + assign cfg_continuous_cgs = 1'b0; + assign cfg_continuous_ilas = 1'b0; + assign cfg_skip_ilas = 1'b0; + assign cfg_mframes_per_ilas = 3; + assign cfg_disable_char_replacement = 1'b0; + assign cfg_disable_scrambler = SCR ? 1'b0 : 1'b1; + + assign device_cfg_octets_per_multiframe = (FRAMES_PER_MULTIFRAME * OCTETS_PER_FRAME) - 1; + assign device_cfg_octets_per_frame = OCTETS_PER_FRAME - 1; + assign device_cfg_beats_per_multiframe = ((FRAMES_PER_MULTIFRAME * OCTETS_PER_FRAME) / + TPL_DATA_PATH_WIDTH) - 1; + assign device_cfg_lmfc_offset = 1; + assign device_cfg_sysref_oneshot = SYSREF_ONE_SHOT; + assign device_cfg_sysref_disable = SYSREF_DISABLE; + + jesd204_ilas_cfg_static #( + .DID(8'h00), + .BID(5'h00), + .L(NUM_LANES - 1), + .SCR(SCR), + .F(OCTETS_PER_FRAME - 1), + .K(FRAMES_PER_MULTIFRAME - 1), + .M(NUM_CONVERTERS - 1), + .N(N), + .NP(NP), + .SUBCLASSV(3'h1), + .S(5'h00), + .JESDV(3'h1), + .CF(5'h00), + .HD(HIGH_DENSITY), + .NUM_LANES(NUM_LANES), + .DATA_PATH_WIDTH(DATA_PATH_WIDTH) + ) i_ilas_config ( + .clk(clk), + .ilas_config_addr(ilas_config_addr), + .ilas_config_rd(ilas_config_rd), + .ilas_config_data(ilas_config_data)); + +endmodule diff --git a/adi_library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.xpr b/adi_library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.xpr new file mode 100644 index 00000000..3fa4c024 --- /dev/null +++ b/adi_library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config.xpr @@ -0,0 +1,406 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config_ip.tcl b/adi_library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config_ip.tcl new file mode 100644 index 00000000..89106acf --- /dev/null +++ b/adi_library/jesd204/jesd204_tx_static_config/jesd204_tx_static_config_ip.tcl @@ -0,0 +1,50 @@ +############################################################################### +## Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create jesd204_tx_static_config +adi_ip_files jesd204_tx_static_config [list \ + "jesd204_tx_static_config.v" \ + "jesd204_ilas_cfg_static.v" \ +] + +adi_ip_properties_lite jesd204_tx_static_config + +adi_add_bus "tx_cfg" "master" \ + "analog.com:interface:jesd204_tx_cfg_rtl:1.0" \ + "analog.com:interface:jesd204_tx_cfg:1.0" \ + { \ + { "cfg_lanes_disable" "lanes_disable" } \ + { "cfg_links_disable" "links_disable" } \ + { "cfg_octets_per_multiframe" "octets_per_multiframe" } \ + { "cfg_octets_per_frame" "octets_per_frame" } \ + { "cfg_continuous_cgs" "continuous_cgs" } \ + { "cfg_continuous_ilas" "continuous_ilas" } \ + { "cfg_skip_ilas" "skip_ilas" } \ + { "cfg_mframes_per_ilas" "mframes_per_ilas" } \ + { "cfg_disable_char_replacement" "disable_char_replacement" } \ + { "cfg_disable_scrambler" "disable_scrambler" } \ + { "device_cfg_octets_per_multiframe" "device_octets_per_multiframe" } \ + { "device_cfg_octets_per_frame" "device_octets_per_frame" } \ + { "device_cfg_beats_per_multiframe" "device_beats_per_multiframe" } \ + { "device_cfg_lmfc_offset" "device_lmfc_offset" } \ + { "device_cfg_sysref_oneshot" "device_sysref_oneshot" } \ + { "device_cfg_sysref_disable" "device_sysref_disable" } \ + } + +adi_add_bus "tx_ilas_config" "slave" \ + "analog.com:interface:jesd204_tx_ilas_config_rtl:1.0" \ + "analog.com:interface:jesd204_tx_ilas_config:1.0" \ + { \ + { "ilas_config_rd" "rd" } \ + { "ilas_config_addr" "addr" } \ + { "ilas_config_data" "data" } \ + } + +adi_add_bus_clock "clk" "tx_cfg:tx_ilas_config" + +ipx::save_core [ipx::current_core] diff --git a/adi_library/jesd204/jesd204_tx_static_config/xgui/jesd204_tx_static_config_v1_0.tcl b/adi_library/jesd204/jesd204_tx_static_config/xgui/jesd204_tx_static_config_v1_0.tcl new file mode 100644 index 00000000..e651d167 --- /dev/null +++ b/adi_library/jesd204/jesd204_tx_static_config/xgui/jesd204_tx_static_config_v1_0.tcl @@ -0,0 +1,220 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DATA_PATH_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "FRAMES_PER_MULTIFRAME" -parent ${Page_0} + ipgui::add_param $IPINST -name "HIGH_DENSITY" -parent ${Page_0} + ipgui::add_param $IPINST -name "LINK_MODE" -parent ${Page_0} + ipgui::add_param $IPINST -name "N" -parent ${Page_0} + ipgui::add_param $IPINST -name "NP" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_CONVERTERS" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_LANES" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_LINKS" -parent ${Page_0} + ipgui::add_param $IPINST -name "OCTETS_PER_FRAME" -parent ${Page_0} + ipgui::add_param $IPINST -name "SCR" -parent ${Page_0} + ipgui::add_param $IPINST -name "SYSREF_DISABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "SYSREF_ONE_SHOT" -parent ${Page_0} + ipgui::add_param $IPINST -name "TPL_DATA_PATH_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH } { + # Procedure called to update DATA_PATH_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH } { + # Procedure called to validate DATA_PATH_WIDTH + return true +} + +proc update_PARAM_VALUE.FRAMES_PER_MULTIFRAME { PARAM_VALUE.FRAMES_PER_MULTIFRAME } { + # Procedure called to update FRAMES_PER_MULTIFRAME when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FRAMES_PER_MULTIFRAME { PARAM_VALUE.FRAMES_PER_MULTIFRAME } { + # Procedure called to validate FRAMES_PER_MULTIFRAME + return true +} + +proc update_PARAM_VALUE.HIGH_DENSITY { PARAM_VALUE.HIGH_DENSITY } { + # Procedure called to update HIGH_DENSITY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.HIGH_DENSITY { PARAM_VALUE.HIGH_DENSITY } { + # Procedure called to validate HIGH_DENSITY + return true +} + +proc update_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } { + # Procedure called to update LINK_MODE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } { + # Procedure called to validate LINK_MODE + return true +} + +proc update_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to update N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.N { PARAM_VALUE.N } { + # Procedure called to validate N + return true +} + +proc update_PARAM_VALUE.NP { PARAM_VALUE.NP } { + # Procedure called to update NP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NP { PARAM_VALUE.NP } { + # Procedure called to validate NP + return true +} + +proc update_PARAM_VALUE.NUM_CONVERTERS { PARAM_VALUE.NUM_CONVERTERS } { + # Procedure called to update NUM_CONVERTERS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_CONVERTERS { PARAM_VALUE.NUM_CONVERTERS } { + # Procedure called to validate NUM_CONVERTERS + return true +} + +proc update_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } { + # Procedure called to update NUM_LANES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_LANES { PARAM_VALUE.NUM_LANES } { + # Procedure called to validate NUM_LANES + return true +} + +proc update_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } { + # Procedure called to update NUM_LINKS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_LINKS { PARAM_VALUE.NUM_LINKS } { + # Procedure called to validate NUM_LINKS + return true +} + +proc update_PARAM_VALUE.OCTETS_PER_FRAME { PARAM_VALUE.OCTETS_PER_FRAME } { + # Procedure called to update OCTETS_PER_FRAME when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OCTETS_PER_FRAME { PARAM_VALUE.OCTETS_PER_FRAME } { + # Procedure called to validate OCTETS_PER_FRAME + return true +} + +proc update_PARAM_VALUE.SCR { PARAM_VALUE.SCR } { + # Procedure called to update SCR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SCR { PARAM_VALUE.SCR } { + # Procedure called to validate SCR + return true +} + +proc update_PARAM_VALUE.SYSREF_DISABLE { PARAM_VALUE.SYSREF_DISABLE } { + # Procedure called to update SYSREF_DISABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SYSREF_DISABLE { PARAM_VALUE.SYSREF_DISABLE } { + # Procedure called to validate SYSREF_DISABLE + return true +} + +proc update_PARAM_VALUE.SYSREF_ONE_SHOT { PARAM_VALUE.SYSREF_ONE_SHOT } { + # Procedure called to update SYSREF_ONE_SHOT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SYSREF_ONE_SHOT { PARAM_VALUE.SYSREF_ONE_SHOT } { + # Procedure called to validate SYSREF_ONE_SHOT + return true +} + +proc update_PARAM_VALUE.TPL_DATA_PATH_WIDTH { PARAM_VALUE.TPL_DATA_PATH_WIDTH } { + # Procedure called to update TPL_DATA_PATH_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TPL_DATA_PATH_WIDTH { PARAM_VALUE.TPL_DATA_PATH_WIDTH } { + # Procedure called to validate TPL_DATA_PATH_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.NUM_LANES { MODELPARAM_VALUE.NUM_LANES PARAM_VALUE.NUM_LANES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_LANES}] ${MODELPARAM_VALUE.NUM_LANES} +} + +proc update_MODELPARAM_VALUE.NUM_LINKS { MODELPARAM_VALUE.NUM_LINKS PARAM_VALUE.NUM_LINKS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_LINKS}] ${MODELPARAM_VALUE.NUM_LINKS} +} + +proc update_MODELPARAM_VALUE.OCTETS_PER_FRAME { MODELPARAM_VALUE.OCTETS_PER_FRAME PARAM_VALUE.OCTETS_PER_FRAME } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OCTETS_PER_FRAME}] ${MODELPARAM_VALUE.OCTETS_PER_FRAME} +} + +proc update_MODELPARAM_VALUE.FRAMES_PER_MULTIFRAME { MODELPARAM_VALUE.FRAMES_PER_MULTIFRAME PARAM_VALUE.FRAMES_PER_MULTIFRAME } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FRAMES_PER_MULTIFRAME}] ${MODELPARAM_VALUE.FRAMES_PER_MULTIFRAME} +} + +proc update_MODELPARAM_VALUE.NUM_CONVERTERS { MODELPARAM_VALUE.NUM_CONVERTERS PARAM_VALUE.NUM_CONVERTERS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_CONVERTERS}] ${MODELPARAM_VALUE.NUM_CONVERTERS} +} + +proc update_MODELPARAM_VALUE.N { MODELPARAM_VALUE.N PARAM_VALUE.N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.N}] ${MODELPARAM_VALUE.N} +} + +proc update_MODELPARAM_VALUE.NP { MODELPARAM_VALUE.NP PARAM_VALUE.NP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NP}] ${MODELPARAM_VALUE.NP} +} + +proc update_MODELPARAM_VALUE.HIGH_DENSITY { MODELPARAM_VALUE.HIGH_DENSITY PARAM_VALUE.HIGH_DENSITY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.HIGH_DENSITY}] ${MODELPARAM_VALUE.HIGH_DENSITY} +} + +proc update_MODELPARAM_VALUE.SCR { MODELPARAM_VALUE.SCR PARAM_VALUE.SCR } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SCR}] ${MODELPARAM_VALUE.SCR} +} + +proc update_MODELPARAM_VALUE.LINK_MODE { MODELPARAM_VALUE.LINK_MODE PARAM_VALUE.LINK_MODE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LINK_MODE}] ${MODELPARAM_VALUE.LINK_MODE} +} + +proc update_MODELPARAM_VALUE.SYSREF_DISABLE { MODELPARAM_VALUE.SYSREF_DISABLE PARAM_VALUE.SYSREF_DISABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SYSREF_DISABLE}] ${MODELPARAM_VALUE.SYSREF_DISABLE} +} + +proc update_MODELPARAM_VALUE.SYSREF_ONE_SHOT { MODELPARAM_VALUE.SYSREF_ONE_SHOT PARAM_VALUE.SYSREF_ONE_SHOT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SYSREF_ONE_SHOT}] ${MODELPARAM_VALUE.SYSREF_ONE_SHOT} +} + +proc update_MODELPARAM_VALUE.DATA_PATH_WIDTH { MODELPARAM_VALUE.DATA_PATH_WIDTH PARAM_VALUE.DATA_PATH_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_PATH_WIDTH}] ${MODELPARAM_VALUE.DATA_PATH_WIDTH} +} + +proc update_MODELPARAM_VALUE.TPL_DATA_PATH_WIDTH { MODELPARAM_VALUE.TPL_DATA_PATH_WIDTH PARAM_VALUE.TPL_DATA_PATH_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TPL_DATA_PATH_WIDTH}] ${MODELPARAM_VALUE.TPL_DATA_PATH_WIDTH} +} + diff --git a/adi_library/jesd204/jesd204_versal_gt_adapter_rx/Makefile b/adi_library/jesd204/jesd204_versal_gt_adapter_rx/Makefile new file mode 100644 index 00000000..9450aa62 --- /dev/null +++ b/adi_library/jesd204/jesd204_versal_gt_adapter_rx/Makefile @@ -0,0 +1,14 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := jesd204_versal_gt_adapter_rx + +GENERIC_DEPS += jesd204_versal_gt_adapter_rx.v + +XILINX_DEPS += ../jesd204_common/sync_header_align.v +XILINX_DEPS += jesd204_versal_gt_adapter_rx_ip.tcl + +include ../../scripts/library.mk diff --git a/adi_library/jesd204/jesd204_versal_gt_adapter_rx/component.xml b/adi_library/jesd204/jesd204_versal_gt_adapter_rx/component.xml new file mode 100644 index 00000000..3ffbd94b --- /dev/null +++ b/adi_library/jesd204/jesd204_versal_gt_adapter_rx/component.xml @@ -0,0 +1,345 @@ + + + analog.com + user + jesd204_versal_gt_adapter_rx + 1.0 + + + RX + + + + + + + rxdata + + + rx_data + + + + + rxheader + + + rx_header + + + + + rxblock_sync + + + rx_block_sync + + + + + + RX_GT_IP_Interface + + + + + + + ch_rxdata + + + rxdata + + + + + ch_rxheader + + + rxheader + + + + + ch_rxheadervalid + + + rxheadervalid + + + + + ch_rxgearboxslip + + + rxgearboxslip + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + jesd204_versal_gt_adapter_rx + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 1ff4f3cf + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + jesd204_versal_gt_adapter_rx + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 1ff4f3cf + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f92e9879 + + + + + + + rxdata + + in + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rxheader + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rxgearboxslip + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rxheadervalid + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_data + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_header + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rx_block_sync + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + usr_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../jesd204_common/sync_header_align.v + verilogSource + + + jesd204_versal_gt_adapter_rx.v + verilogSource + CHECKSUM_3e482be2 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../jesd204_common/sync_header_align.v + verilogSource + + + jesd204_versal_gt_adapter_rx.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/jesd204_versal_gt_adapter_rx_v1_0.tcl + tclSource + CHECKSUM_f92e9879 + XGUI_VERSION_2 + + + + ADI JESD204 Versal Transceiver Rx Lane Adapter + + + Component_Name + jesd204_versal_gt_adapter_rx_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + ADI JESD204 Versal Transceiver Rx Lane Adapter + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:52:17Z + + + 2023.2.1 + + + + + + diff --git a/adi_library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v b/adi_library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v new file mode 100644 index 00000000..0b630405 --- /dev/null +++ b/adi_library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v @@ -0,0 +1,59 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_versal_gt_adapter_rx ( + input [127 : 0] rxdata, + input [5 : 0] rxheader, + output rxgearboxslip, + input [1 : 0] rxheadervalid, + + // Interface to Link layer core + output [63:0] rx_data, + output [1:0] rx_header, + output rx_block_sync, + + input usr_clk +); + + // Sync header alignment + wire rx_bitslip_req_s; + reg [4:0] rx_bitslip_done_cnt = 'h0; + always @(posedge usr_clk) begin + if (rx_bitslip_done_cnt[4]) begin + rx_bitslip_done_cnt <= 'b0; + end else if (rx_bitslip_req_s & ~rx_bitslip_done_cnt[4]) begin + rx_bitslip_done_cnt <= rx_bitslip_done_cnt + 1; + end + end + + reg rx_bitslip_req_s_d = 1'b0; + always @(posedge usr_clk) begin + rx_bitslip_req_s_d <= rx_bitslip_req_s; + end + assign rxgearboxslip = rx_bitslip_req_s & ~rx_bitslip_req_s_d; + + wire [63:0] rxdata_flip; + genvar i; + for (i = 0; i < 64; i=i+1) begin + assign rxdata_flip[63-i] = rxdata[i]; + end + + // Sync header alignment + sync_header_align i_sync_header_align ( + .clk(usr_clk), + .reset(~rxheadervalid[0]), + // Flip header bits and data + .i_data({rxheader[0],rxheader[1],rxdata_flip[63:0]}), + .i_slip(rx_bitslip_req_s), + .i_slip_done(rx_bitslip_done_cnt[4]), + .o_data(rx_data), + .o_header(rx_header), + .o_block_sync(rx_block_sync)); + +endmodule diff --git a/adi_library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.xpr b/adi_library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.xpr new file mode 100644 index 00000000..6b87fce0 --- /dev/null +++ b/adi_library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.xpr @@ -0,0 +1,406 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl b/adi_library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl new file mode 100644 index 00000000..b2f37d86 --- /dev/null +++ b/adi_library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl @@ -0,0 +1,39 @@ +############################################################################### +## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create jesd204_versal_gt_adapter_rx +adi_ip_files jesd204_versal_gt_adapter_rx [list \ + jesd204_versal_gt_adapter_rx.v \ + ../jesd204_common/sync_header_align.v \ + ] + +adi_ip_properties_lite jesd204_versal_gt_adapter_rx + +set_property display_name "ADI JESD204 Versal Transceiver Rx Lane Adapter" [ipx::current_core] +set_property description "ADI JESD204 Versal Transceiver Rx Lane Adapter" [ipx::current_core] + +adi_add_bus "RX" "master" \ + "xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0" \ + "xilinx.com:display_jesd204:jesd204_rx_bus:1.0" \ + { \ + { "rx_data" "rxdata" } \ + { "rx_header" "rxheader" } \ + { "rx_block_sync" "rxblock_sync" } \ + } + +adi_add_bus "RX_GT_IP_Interface" "master" \ + "xilinx.com:interface:gt_rx_interface_rtl:1.0" \ + "xilinx.com:interface:gt_rx_interface:1.0" \ + { \ + { "rxdata" "ch_rxdata" } \ + { "rxheader" "ch_rxheader" } \ + { "rxheadervalid" "ch_rxheadervalid" } \ + { "rxgearboxslip" "ch_rxgearboxslip" } \ + } + +ipx::save_core [ipx::current_core] diff --git a/adi_library/jesd204/jesd204_versal_gt_adapter_rx/xgui/jesd204_versal_gt_adapter_rx_v1_0.tcl b/adi_library/jesd204/jesd204_versal_gt_adapter_rx/xgui/jesd204_versal_gt_adapter_rx_v1_0.tcl new file mode 100644 index 00000000..0db18e9a --- /dev/null +++ b/adi_library/jesd204/jesd204_versal_gt_adapter_rx/xgui/jesd204_versal_gt_adapter_rx_v1_0.tcl @@ -0,0 +1,10 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + + diff --git a/adi_library/jesd204/jesd204_versal_gt_adapter_tx/Makefile b/adi_library/jesd204/jesd204_versal_gt_adapter_tx/Makefile new file mode 100644 index 00000000..1fabb191 --- /dev/null +++ b/adi_library/jesd204/jesd204_versal_gt_adapter_tx/Makefile @@ -0,0 +1,13 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := jesd204_versal_gt_adapter_tx + +GENERIC_DEPS += jesd204_versal_gt_adapter_tx.v + +XILINX_DEPS += jesd204_versal_gt_adapter_tx_ip.tcl + +include ../../scripts/library.mk diff --git a/adi_library/jesd204/jesd204_versal_gt_adapter_tx/component.xml b/adi_library/jesd204/jesd204_versal_gt_adapter_tx/component.xml new file mode 100644 index 00000000..397df5bd --- /dev/null +++ b/adi_library/jesd204/jesd204_versal_gt_adapter_tx/component.xml @@ -0,0 +1,273 @@ + + + analog.com + user + jesd204_versal_gt_adapter_tx + 1.0 + + + TX_GT_IP_Interface + + + + + + + ch_txdata + + + txdata + + + + + ch_txheader + + + txheader + + + + + + TX + + + + + + + txdata + + + tx_data + + + + + txheader + + + tx_header + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + jesd204_versal_gt_adapter_tx + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 8858e8f7 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + jesd204_versal_gt_adapter_tx + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 8858e8f7 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f92e9879 + + + + + + + txdata + + out + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + txheader + + out + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + tx_data + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + tx_header + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + usr_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + xilinx_anylanguagesynthesis_view_fileset + + jesd204_versal_gt_adapter_tx.v + verilogSource + CHECKSUM_8858e8f7 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + jesd204_versal_gt_adapter_tx.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/jesd204_versal_gt_adapter_tx_v1_0.tcl + tclSource + CHECKSUM_f92e9879 + XGUI_VERSION_2 + + + + ADI JESD204 Versal Transceiver Tx Lane Adapter + + + Component_Name + jesd204_versal_gt_adapter_tx_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + ADI JESD204 Versal Transceiver Tx Lane Adapter + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:52:25Z + + + 2023.2.1 + + + + + + diff --git a/adi_library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v b/adi_library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v new file mode 100644 index 00000000..21a53145 --- /dev/null +++ b/adi_library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v @@ -0,0 +1,31 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2019, 2021 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_versal_gt_adapter_tx ( + output [127 : 0] txdata, + output [5 : 0] txheader, + + // Interface to Link layer core + input [63:0] tx_data, + input [1:0] tx_header, + + input usr_clk +); + + wire [63:0] tx_data_flip; + genvar i; + for (i = 0; i < 64; i=i+1) begin + assign tx_data_flip[63-i] = tx_data[i]; + end + + assign txdata = {64'b0,tx_data_flip}; + // Flip header bits and data + assign txheader = {4'b0,tx_header[0],tx_header[1]}; + +endmodule diff --git a/adi_library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.xpr b/adi_library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.xpr new file mode 100644 index 00000000..9513ddde --- /dev/null +++ b/adi_library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.xpr @@ -0,0 +1,399 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl b/adi_library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl new file mode 100644 index 00000000..04fbb584 --- /dev/null +++ b/adi_library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl @@ -0,0 +1,35 @@ +############################################################################### +## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create jesd204_versal_gt_adapter_tx +adi_ip_files jesd204_versal_gt_adapter_tx [list \ + jesd204_versal_gt_adapter_tx.v + ] + +adi_ip_properties_lite jesd204_versal_gt_adapter_tx + +set_property display_name "ADI JESD204 Versal Transceiver Tx Lane Adapter" [ipx::current_core] +set_property description "ADI JESD204 Versal Transceiver Tx Lane Adapter" [ipx::current_core] + +adi_add_bus "TX_GT_IP_Interface" "master" \ + "xilinx.com:interface:gt_tx_interface_rtl:1.0" \ + "xilinx.com:interface:gt_tx_interface:1.0" \ + { \ + { "txdata" "ch_txdata" } \ + { "txheader" "ch_txheader" } \ + } + +adi_add_bus "TX" "slave" \ + "xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0" \ + "xilinx.com:display_jesd204:jesd204_tx_bus:1.0" \ + { \ + { "tx_data" "txdata" } \ + { "tx_header" "txheader" } \ + } + +ipx::save_core [ipx::current_core] diff --git a/adi_library/jesd204/jesd204_versal_gt_adapter_tx/xgui/jesd204_versal_gt_adapter_tx_v1_0.tcl b/adi_library/jesd204/jesd204_versal_gt_adapter_tx/xgui/jesd204_versal_gt_adapter_tx_v1_0.tcl new file mode 100644 index 00000000..0db18e9a --- /dev/null +++ b/adi_library/jesd204/jesd204_versal_gt_adapter_tx/xgui/jesd204_versal_gt_adapter_tx_v1_0.tcl @@ -0,0 +1,10 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + + diff --git a/adi_library/jesd204/scripts/jesd204.tcl b/adi_library/jesd204/scripts/jesd204.tcl new file mode 100644 index 00000000..d2a3e664 --- /dev/null +++ b/adi_library/jesd204/scripts/jesd204.tcl @@ -0,0 +1,453 @@ +############################################################################### +## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIJESD204 +############################################################################### + +proc adi_axi_jesd204_tx_create {ip_name num_lanes {num_links 1} {link_mode 1}} { + + if {$num_lanes < 1 || $num_lanes > 32} { + return -code 1 "ERROR: Invalid number of JESD204B lanes. (Supported range 1-32)" + } + + if {$num_links < 1 || $num_links > 8} { + return -code 1 "ERROR: Invalid number of JESD204B links. (Supported range 1-8)" + } + + startgroup + + set result [catch { + + create_bd_cell -type hier $ip_name + + ad_ip_instance axi_jesd204_tx "${ip_name}/tx_axi" + ad_ip_instance jesd204_tx "${ip_name}/tx" + + ad_ip_parameter "${ip_name}/tx_axi" CONFIG.NUM_LANES $num_lanes + ad_ip_parameter "${ip_name}/tx_axi" CONFIG.NUM_LINKS $num_links + ad_ip_parameter "${ip_name}/tx_axi" CONFIG.LINK_MODE $link_mode + ad_ip_parameter "${ip_name}/tx" CONFIG.NUM_LANES $num_lanes + ad_ip_parameter "${ip_name}/tx" CONFIG.NUM_LINKS $num_links + ad_ip_parameter "${ip_name}/tx" CONFIG.LINK_MODE $link_mode + + ad_connect "${ip_name}/tx_axi/core_reset" "${ip_name}/tx/reset" + ad_connect "${ip_name}/tx_axi/device_reset" "${ip_name}/tx/device_reset" + if {$link_mode == 1} {ad_connect "${ip_name}/tx_axi/tx_ctrl" "${ip_name}/tx/tx_ctrl"} + ad_connect "${ip_name}/tx_axi/tx_cfg" "${ip_name}/tx/tx_cfg" + ad_connect "${ip_name}/tx/tx_event" "${ip_name}/tx_axi/tx_event" + ad_connect "${ip_name}/tx/tx_status" "${ip_name}/tx_axi/tx_status" + if {$link_mode == 1} {ad_connect "${ip_name}/tx/tx_ilas_config" "${ip_name}/tx_axi/tx_ilas_config"} + + # Control interface + create_bd_pin -dir I -type clk "${ip_name}/s_axi_aclk" + create_bd_pin -dir I -type rst "${ip_name}/s_axi_aresetn" + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "${ip_name}/s_axi" + create_bd_pin -dir O -type intr "${ip_name}/irq" + + ad_connect "${ip_name}/s_axi_aclk" "${ip_name}/tx_axi/s_axi_aclk" + ad_connect "${ip_name}/s_axi_aresetn" "${ip_name}/tx_axi/s_axi_aresetn" + ad_connect "${ip_name}/s_axi" "${ip_name}/tx_axi/s_axi" + ad_connect "${ip_name}/tx_axi/irq" "${ip_name}/irq" + + # JESD204 processing + create_bd_pin -dir I -type clk "${ip_name}/link_clk" + create_bd_pin -dir I -type clk "${ip_name}/device_clk" + if {$link_mode == 1} {create_bd_pin -dir I -from [expr $num_links - 1] -to 0 "${ip_name}/sync"} + create_bd_pin -dir I "${ip_name}/sysref" + + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 "${ip_name}/tx_data" + + ad_connect "${ip_name}/link_clk" "${ip_name}/tx_axi/core_clk" + ad_connect "${ip_name}/link_clk" "${ip_name}/tx/clk" + ad_connect "${ip_name}/device_clk" "${ip_name}/tx_axi/device_clk" + ad_connect "${ip_name}/device_clk" "${ip_name}/tx/device_clk" + if {$link_mode == 1} {ad_connect "${ip_name}/sync" "${ip_name}/tx/sync"} + ad_connect "${ip_name}/sysref" "${ip_name}/tx/sysref" + ad_connect "${ip_name}/tx_data" "${ip_name}/tx/tx_data" + + for {set i 0} {$i < $num_lanes} {incr i} { + create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 "${ip_name}/tx_phy${i}" + ad_connect "${ip_name}/tx/tx_phy${i}" "${ip_name}/tx_phy${i}" + } + } resulttext resultoptions] + + dict unset resultoptions -level + + endgroup + + if {$result != 0} { + undo -quiet + } + + return -options $resultoptions $resulttext +} + +proc adi_axi_jesd204_rx_create {ip_name num_lanes {num_links 1} {link_mode 1}} { + + if {$num_lanes < 1 || $num_lanes > 32} { + return -code 1 "ERROR: Invalid number of JESD204B lanes. (Supported range 1-32)" + } + + if {$num_links < 1 || $num_links > 8} { + return -code 1 "ERROR: Invalid number of JESD204B links. (Supported range 1-8)" + } + + startgroup + + set result [catch { + + create_bd_cell -type hier $ip_name + + ad_ip_instance axi_jesd204_rx "${ip_name}/rx_axi" + ad_ip_instance jesd204_rx "${ip_name}/rx" + + ad_ip_parameter "${ip_name}/rx_axi" CONFIG.NUM_LANES $num_lanes + ad_ip_parameter "${ip_name}/rx_axi" CONFIG.NUM_LINKS $num_links + ad_ip_parameter "${ip_name}/rx_axi" CONFIG.LINK_MODE $link_mode + ad_ip_parameter "${ip_name}/rx" CONFIG.NUM_LANES $num_lanes + ad_ip_parameter "${ip_name}/rx" CONFIG.NUM_LINKS $num_links + ad_ip_parameter "${ip_name}/rx" CONFIG.LINK_MODE $link_mode + + ad_connect "${ip_name}/rx_axi/core_reset" "${ip_name}/rx/reset" + ad_connect "${ip_name}/rx_axi/device_reset" "${ip_name}/rx/device_reset" + ad_connect "${ip_name}/rx_axi/rx_cfg" "${ip_name}/rx/rx_cfg" + ad_connect "${ip_name}/rx/rx_event" "${ip_name}/rx_axi/rx_event" + ad_connect "${ip_name}/rx/rx_status" "${ip_name}/rx_axi/rx_status" + if {$link_mode == 1} {ad_connect "${ip_name}/rx/rx_ilas_config" "${ip_name}/rx_axi/rx_ilas_config"} + + # Control interface + create_bd_pin -dir I -type clk "${ip_name}/s_axi_aclk" + create_bd_pin -dir I -type rst "${ip_name}/s_axi_aresetn" + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "${ip_name}/s_axi" + create_bd_pin -dir O -type intr "${ip_name}/irq" + + ad_connect "${ip_name}/s_axi_aclk" "${ip_name}/rx_axi/s_axi_aclk" + ad_connect "${ip_name}/s_axi_aresetn" "${ip_name}/rx_axi/s_axi_aresetn" + ad_connect "${ip_name}/s_axi" "${ip_name}/rx_axi/s_axi" + ad_connect "${ip_name}/rx_axi/irq" "${ip_name}/irq" + + # JESD204 processing + create_bd_pin -dir I -type clk "${ip_name}/link_clk" + create_bd_pin -dir I -type clk "${ip_name}/device_clk" + if {$link_mode == 1} {create_bd_pin -dir O -from [expr $num_links - 1] -to 0 "${ip_name}/sync"} + create_bd_pin -dir I "${ip_name}/sysref" + if {$link_mode == 1} {create_bd_pin -dir O "${ip_name}/phy_en_char_align"} +# create_bd_pin -dir I "${ip_name}/phy_ready" + create_bd_pin -dir O -from 3 -to 0 "${ip_name}/rx_eof" + create_bd_pin -dir O -from 3 -to 0 "${ip_name}/rx_sof" + +# create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 "${ip_name}/rx_data" + create_bd_pin -dir O "${ip_name}/rx_data_tvalid" + create_bd_pin -dir O -from [expr $num_lanes * 32 - 1] -to 0 "${ip_name}/rx_data_tdata" + + ad_connect "${ip_name}/link_clk" "${ip_name}/rx_axi/core_clk" + ad_connect "${ip_name}/link_clk" "${ip_name}/rx/clk" + ad_connect "${ip_name}/device_clk" "${ip_name}/rx_axi/device_clk" + ad_connect "${ip_name}/device_clk" "${ip_name}/rx/device_clk" + if {$link_mode == 1} {ad_connect "${ip_name}/rx/sync" "${ip_name}/sync"} + ad_connect "${ip_name}/sysref" "${ip_name}/rx/sysref" +# ad_connect "${ip_name}/phy_ready" "${ip_name}/rx/phy_ready" + if {$link_mode == 1} {ad_connect "${ip_name}/rx/phy_en_char_align" "${ip_name}/phy_en_char_align"} + ad_connect "${ip_name}/rx/rx_data" "${ip_name}/rx_data_tdata" + ad_connect "${ip_name}/rx/rx_valid" "${ip_name}/rx_data_tvalid" + ad_connect "${ip_name}/rx/rx_eof" "${ip_name}/rx_eof" + ad_connect "${ip_name}/rx/rx_sof" "${ip_name}/rx_sof" + + for {set i 0} {$i < $num_lanes} {incr i} { + create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 "${ip_name}/rx_phy${i}" + ad_connect "${ip_name}/rx/rx_phy${i}" "${ip_name}/rx_phy${i}" + } + } resulttext resultoptions] + + dict unset resultoptions -level + + endgroup + + if {$result != 0} { + undo -quiet + } + + return -options $resultoptions $resulttext +} + + + + +# L M S N & NP +proc adi_tpl_jesd204_tx_create {ip_name num_of_lanes num_of_converters samples_per_frame sample_width {link_layer_bytes_per_beat 4} {dma_sample_width 16}} { + + + if {$num_of_lanes < 1 || $num_of_lanes > 32} { + return -code 1 "ERROR: Invalid number of JESD204B lanes. (Supported range 1-32)" + } + # F = (M * N * S) / (L * 8) + set bytes_per_frame [expr ($num_of_converters * $sample_width * $samples_per_frame) / ($num_of_lanes * 8)]; + # one beat per lane must accommodate at least one frame + set tpl_bytes_per_beat [expr max($bytes_per_frame, $link_layer_bytes_per_beat)] + + # datapath width = L * 8 * TPL_BYTES_PER_BEAT / (M * N) + set samples_per_channel [expr ($num_of_lanes * 8 * $tpl_bytes_per_beat) / ($num_of_converters * $sample_width)]; + + + startgroup + + set result [catch { + + create_bd_cell -type hier $ip_name + + # Control interface + create_bd_pin -dir I -type clk "${ip_name}/s_axi_aclk" + create_bd_pin -dir I -type rst "${ip_name}/s_axi_aresetn" + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "${ip_name}/s_axi" + + # Interface to link layer + create_bd_pin -dir I -type clk "${ip_name}/link_clk" + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 "${ip_name}/link" + + # Interface to application layer + create_bd_pin -dir I "${ip_name}/dac_dunf" + for {set i 0} {$i < $num_of_converters} {incr i} { + create_bd_pin -dir O "${ip_name}/dac_enable_${i}" + create_bd_pin -dir O "${ip_name}/dac_valid_${i}" + create_bd_pin -dir I "${ip_name}/dac_data_${i}" + } + + # Generic TPL core + ad_ip_instance ad_ip_jesd204_tpl_dac "${ip_name}/dac_tpl_core" [list \ + NUM_LANES $num_of_lanes \ + NUM_CHANNELS $num_of_converters \ + SAMPLES_PER_FRAME $samples_per_frame \ + CONVERTER_RESOLUTION $sample_width \ + BITS_PER_SAMPLE $sample_width \ + OCTETS_PER_BEAT $tpl_bytes_per_beat \ + DMA_BITS_PER_SAMPLE $dma_sample_width + ] + + if {$num_of_converters > 1} { + # Concatenation and slicer cores + # xconcat limited to 32 input ports + for {set i 0} {$i < $num_of_converters} {incr i 32} { + ad_ip_instance xlconcat "${ip_name}/data_concat[expr $i/32]" [list \ + NUM_PORTS [expr min(32,$num_of_converters-$i)] \ + ] + } + # main concat + if {$num_of_converters > 32} { + ad_ip_instance xlconcat "${ip_name}/data_concat" [list \ + NUM_PORTS [expr int(ceil(double($num_of_converters)/32))] \ + ] + } + + for {set i 0} {$i < $num_of_converters} {incr i} { + ad_ip_instance xlslice "${ip_name}/enable_slice_${i}" [list \ + DIN_WIDTH $num_of_converters \ + DIN_FROM $i \ + DIN_TO $i \ + ] + ad_ip_instance xlslice "${ip_name}/valid_slice_${i}" [list \ + DIN_WIDTH $num_of_converters \ + DIN_FROM $i \ + DIN_TO $i \ + ] + } + } + # Create connections + # TPL configuration interface + ad_connect "${ip_name}/s_axi_aclk" "${ip_name}/dac_tpl_core/s_axi_aclk" + ad_connect "${ip_name}/s_axi_aresetn" "${ip_name}/dac_tpl_core/s_axi_aresetn" + ad_connect "${ip_name}/s_axi" "${ip_name}/dac_tpl_core/s_axi" + + # TPL - link layer + ad_connect ${ip_name}/dac_tpl_core/link_clk ${ip_name}/link_clk + ad_connect ${ip_name}/dac_tpl_core/link ${ip_name}/link + + # TPL - app layer + if {$num_of_converters > 1} { + for {set i 0} {$i < $num_of_converters} {incr i} { + ad_connect ${ip_name}/dac_tpl_core/enable ${ip_name}/enable_slice_$i/Din + ad_connect ${ip_name}/dac_tpl_core/dac_valid ${ip_name}/valid_slice_$i/Din + + ad_connect ${ip_name}/enable_slice_$i/Dout ${ip_name}/dac_enable_$i + ad_connect ${ip_name}/valid_slice_$i/Dout ${ip_name}/dac_valid_$i + ad_connect ${ip_name}/dac_data_$i ${ip_name}/data_concat[expr $i/32]/In[expr $i%32] + + } + if {$num_of_converters > 32} { + # wire all concatenators together + for {set i 0} {$i < $num_of_converters} {incr i 32} { + ad_connect ${ip_name}/data_concat[expr $i/32]/dout ${ip_name}/data_concat/In[expr $i/32] + } + ad_connect ${ip_name}/data_concat/dout ${ip_name}/dac_tpl_core/dac_ddata + } else { + ad_connect ${ip_name}/data_concat0/dout ${ip_name}/dac_tpl_core/dac_ddata + } + } else { + ad_connect ${ip_name}/dac_data_0 ${ip_name}/dac_tpl_core/dac_ddata + ad_connect ${ip_name}/dac_tpl_core/enable ${ip_name}/dac_enable_0 + ad_connect ${ip_name}/dac_tpl_core/dac_valid ${ip_name}/dac_valid_0 + } + ad_connect ${ip_name}/dac_dunf ${ip_name}/dac_tpl_core/dac_dunf + + } resulttext resultoptions] + + dict unset resultoptions -level + + endgroup + + if {$result != 0} { + undo -quiet + } + + return -options $resultoptions $resulttext +} + + +# L M S N & NP +proc adi_tpl_jesd204_rx_create {ip_name num_of_lanes num_of_converters samples_per_frame sample_width {link_layer_bytes_per_beat 4} {dma_sample_width 16}} { + + + if {$num_of_lanes < 1 || $num_of_lanes > 32} { + return -code 1 "ERROR: Invalid number of JESD204B lanes. (Supported range 1-32)" + } + # F = (M * N * S) / (L * 8) + set bytes_per_frame [expr ($num_of_converters * $sample_width * $samples_per_frame) / ($num_of_lanes * 8)]; + # one beat per lane must accommodate at least one frame + set tpl_bytes_per_beat [expr max($bytes_per_frame, $link_layer_bytes_per_beat)] + + # datapath width = L * 8 * TPL_BYTES_PER_BEAT / (M * N) + set samples_per_channel [expr ($num_of_lanes * 8 * $tpl_bytes_per_beat) / ($num_of_converters * $sample_width)]; + + + startgroup + + set result [catch { + + create_bd_cell -type hier $ip_name + + # Control interface + create_bd_pin -dir I -type clk "${ip_name}/s_axi_aclk" + create_bd_pin -dir I -type rst "${ip_name}/s_axi_aresetn" + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 "${ip_name}/s_axi" + + # Interface to link layer + create_bd_pin -dir I -type clk "${ip_name}/link_clk" + #create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 "${ip_name}/link" + create_bd_pin -dir I "${ip_name}/link_sof" + create_bd_pin -dir I "${ip_name}/link_valid" + create_bd_pin -dir I "${ip_name}/link_data" + + # Interface to application layer + create_bd_pin -dir I "${ip_name}/adc_dovf" + for {set i 0} {$i < $num_of_converters} {incr i} { + create_bd_pin -dir O "${ip_name}/adc_enable_${i}" + create_bd_pin -dir O "${ip_name}/adc_valid_${i}" + create_bd_pin -dir O "${ip_name}/adc_data_${i}" + } + + # Generic TPL core + ad_ip_instance ad_ip_jesd204_tpl_adc "${ip_name}/adc_tpl_core" [list \ + NUM_LANES $num_of_lanes \ + NUM_CHANNELS $num_of_converters \ + SAMPLES_PER_FRAME $samples_per_frame \ + CONVERTER_RESOLUTION $sample_width \ + BITS_PER_SAMPLE $sample_width \ + OCTETS_PER_BEAT $tpl_bytes_per_beat \ + DMA_BITS_PER_SAMPLE $dma_sample_width + ] + + if {$num_of_converters > 1} { + # Slicer cores + for {set i 0} {$i < $num_of_converters} {incr i} { + ad_ip_instance xlslice ${ip_name}/data_slice_$i [list \ + DIN_WIDTH [expr $dma_sample_width*$samples_per_channel*$num_of_converters] \ + DIN_FROM [expr $dma_sample_width*$samples_per_channel*($i+1)-1] \ + DIN_TO [expr $dma_sample_width*$samples_per_channel*$i] \ + ] + + ad_ip_instance xlslice "${ip_name}/enable_slice_${i}" [list \ + DIN_WIDTH $num_of_converters \ + DIN_FROM $i \ + DIN_TO $i \ + ] + ad_ip_instance xlslice "${ip_name}/valid_slice_${i}" [list \ + DIN_WIDTH $num_of_converters \ + DIN_FROM $i \ + DIN_TO $i \ + ] + } + } + + # Create connections + # TPL configuration interface + ad_connect "${ip_name}/s_axi_aclk" "${ip_name}/adc_tpl_core/s_axi_aclk" + ad_connect "${ip_name}/s_axi_aresetn" "${ip_name}/adc_tpl_core/s_axi_aresetn" + ad_connect "${ip_name}/s_axi" "${ip_name}/adc_tpl_core/s_axi" + + # TPL - link layer + ad_connect ${ip_name}/adc_tpl_core/link_clk ${ip_name}/link_clk + #ad_connect ${ip_name}/adc_tpl_core/link ${ip_name}/link + ad_connect ${ip_name}/adc_tpl_core/link_sof ${ip_name}/link_sof + ad_connect ${ip_name}/adc_tpl_core/link_data ${ip_name}/link_data + ad_connect ${ip_name}/adc_tpl_core/link_valid ${ip_name}/link_valid + + # TPL - app layer + if {$num_of_converters > 1} { + for {set i 0} {$i < $num_of_converters} {incr i} { + ad_connect ${ip_name}/adc_tpl_core/adc_data ${ip_name}/data_slice_$i/Din + ad_connect ${ip_name}/adc_tpl_core/enable ${ip_name}/enable_slice_$i/Din + ad_connect ${ip_name}/adc_tpl_core/adc_valid ${ip_name}/valid_slice_$i/Din + + ad_connect ${ip_name}/data_slice_$i/Dout ${ip_name}/adc_data_$i + ad_connect ${ip_name}/enable_slice_$i/Dout ${ip_name}/adc_enable_$i + ad_connect ${ip_name}/valid_slice_$i/Dout ${ip_name}/adc_valid_$i + + } + } else { + ad_connect ${ip_name}/adc_tpl_core/adc_data ${ip_name}/adc_data_0 + ad_connect ${ip_name}/adc_tpl_core/enable ${ip_name}/adc_enable_0 + ad_connect ${ip_name}/adc_tpl_core/adc_valid ${ip_name}/adc_valid_0 + } + ad_connect ${ip_name}/adc_dovf ${ip_name}/adc_tpl_core/adc_dovf + + } resulttext resultoptions] + + dict unset resultoptions -level + + endgroup + + if {$result != 0} { + undo -quiet + } + + return -options $resultoptions $resulttext +} + +# Calculate Link Layer interface width towards Transport Layer +# TPL width must be set to an integer multiple of F +proc adi_jesd204_calc_tpl_width {link_datapath_width jesd_l jesd_m jesd_s jesd_np {tpl_datapath_width {}}} { + + set jesd_f [expr ($jesd_m*$jesd_s*$jesd_np)/(8*$jesd_l)] + + if {$tpl_datapath_width != ""} { + set tpl_div [expr $tpl_datapath_width / $jesd_f] + set tpl_mod [expr $tpl_datapath_width % $jesd_f] + + if {$tpl_div < 1 || $tpl_mod != 0 || (($tpl_div > 1) && ([expr $tpl_div % 2] != 0))} { + return -code 1 "ERROR: Invalid custom TPL width. Must be a power of 2 multiple of F" + } else { + return $tpl_datapath_width + } + + # For F=3,6,12 get first pow 2 multiple of F greater than link_datapath_width + } elseif {$jesd_f % 3 == 0} { + set np12_datapath_width $jesd_f + while {$np12_datapath_width < $link_datapath_width} { + set np12_datapath_width [expr 2*$np12_datapath_width] + } + return $np12_datapath_width + } else { + return [expr max($jesd_f,$link_datapath_width)] + } + +} + + diff --git a/adi_library/jesd204/tb/.gitignore b/adi_library/jesd204/tb/.gitignore new file mode 100644 index 00000000..804d96e7 --- /dev/null +++ b/adi_library/jesd204/tb/.gitignore @@ -0,0 +1,2 @@ +run/ +vcd/ diff --git a/adi_library/jesd204/tb/axi_jesd204_rx_regmap_tb b/adi_library/jesd204/tb/axi_jesd204_rx_regmap_tb new file mode 100755 index 00000000..0944842a --- /dev/null +++ b/adi_library/jesd204/tb/axi_jesd204_rx_regmap_tb @@ -0,0 +1,17 @@ +#!/bin/bash + +SOURCE="axi_jesd204_rx_regmap_tb.v" +SOURCE+=" ../axi_jesd204_rx/axi_jesd204_rx.v" +SOURCE+=" ../axi_jesd204_rx/jesd204_up_rx.v" +SOURCE+=" ../axi_jesd204_rx/jesd204_up_rx_lane.v" +SOURCE+=" ../axi_jesd204_rx/jesd204_up_ilas_mem.v" +SOURCE+=" ../axi_jesd204_common/jesd204_up_common.v" +SOURCE+=" ../axi_jesd204_common/jesd204_up_sysref.v" +SOURCE+=" ../../common/up_clock_mon.v" +SOURCE+=" ../../common/up_axi.v" +SOURCE+=" ../../util_cdc/sync_bits.v" +SOURCE+=" ../../util_cdc/sync_data.v" +SOURCE+=" ../../util_cdc/sync_event.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/jesd204/tb/axi_jesd204_rx_regmap_tb.v b/adi_library/jesd204/tb/axi_jesd204_rx_regmap_tb.v new file mode 100644 index 00000000..9ac30bdd --- /dev/null +++ b/adi_library/jesd204/tb/axi_jesd204_rx_regmap_tb.v @@ -0,0 +1,346 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_jesd204_rx_regmap_tb; + parameter VCD_FILE = "axi_jesd204_rx_regmap_tb.vcd"; + parameter NUM_LANES = 2; + parameter NUM_LINKS = 1; + + `define TIMEOUT 1000000 + `include "tb_base.v" + + reg core_clk = 1'b0; + always @(*) #4 core_clk <= ~core_clk; + + wire s_axi_aclk = clk; + wire s_axi_aresetn = ~reset; + + reg s_axi_awvalid = 1'b0; + reg s_axi_wvalid = 1'b0; + reg [13:0] s_axi_awaddr = 'h00; + reg [31:0] s_axi_wdata = 'h00; + wire [1:0] s_axi_bresp; + wire s_axi_awready; + wire s_axi_wready; + wire s_axi_bready = 1'b1; + wire [3:0] s_axi_wstrb = 4'b1111; + wire [2:0] s_axi_awprot = 3'b000; + wire [2:0] s_axi_arprot = 3'b000; + wire [1:0] s_axi_rresp; + wire [31:0] s_axi_rdata; + + wire [NUM_LANES*32-1:0] core_status_err_statistics_cnt; + + reg [31:0] expected_reg_mem[0:1023]; + + task write_reg; + input [31:0] addr; + input [31:0] value; + begin + @(posedge s_axi_aclk) + s_axi_awvalid <= 1'b1; + s_axi_wvalid <= 1'b1; + s_axi_awaddr <= addr; + s_axi_wdata <= value; + @(posedge s_axi_aclk) + while (s_axi_awvalid || s_axi_wvalid) begin + @(posedge s_axi_aclk) + if (s_axi_awready) + s_axi_awvalid <= 1'b0; + if (s_axi_wready) + s_axi_wvalid <= 1'b0; + end + end + endtask + + reg [13:0] s_axi_araddr = 'h0; + reg s_axi_arvalid = 'h0; + reg s_axi_rready = 'h0; + wire s_axi_arready; + wire s_axi_rvalid; + + task read_reg; + input [31:0] addr; + output [31:0] value; + begin + s_axi_arvalid <= 1'b1; + s_axi_araddr <= addr; + s_axi_rready <= 1'b1; + @(posedge s_axi_aclk) #0; + while (s_axi_arvalid) begin + if (s_axi_arready == 1'b1) begin + s_axi_arvalid <= 1'b0; + end + @(posedge s_axi_aclk) #0; + end + + while (s_axi_rready) begin + if (s_axi_rvalid == 1'b1) begin + value <= s_axi_rdata; + s_axi_rready <= 1'b0; + end + @(posedge s_axi_aclk) #0; + end + end + endtask + + task read_reg_check; + input [31:0] addr; + output match; + reg [31:0] value; + reg [31:0] expected; + begin + read_reg(addr, value); + expected = expected_reg_mem[addr[13:2]]; + match <= value === expected; + if (value !== expected) begin + $display("Address %h, Expected %h, Found %h", addr, expected, value); + end + end + endtask + + reg read_match = 1'b1; + + always @(posedge clk) begin + if (read_match == 1'b0) begin + failed <= 1'b1; + end + end + + task set_reset_reg_value; + input [31:0] addr; + input [31:0] value; + begin + expected_reg_mem[addr[13:2]] <= value; + end + endtask + + task initialize_expected_reg_mem; + integer i; + begin + for (i = 0; i < 1024; i = i + 1) + expected_reg_mem[i] <= 'h00; + /* Non zero power-on-reset values */ + set_reset_reg_value('h00, 32'h00010761); /* PCORE version register */ + set_reset_reg_value('h0c, 32'h32303452); /* PCORE magic register */ + set_reset_reg_value('h10, NUM_LANES); /* Number of lanes */ + set_reset_reg_value('h18, NUM_LINKS); /* Number of links */ + set_reset_reg_value('h40, 32'h00000100); /* Elastic buffer size */ + set_reset_reg_value('h14, 'h2); /* Datapath width */ + set_reset_reg_value('hc0, 'h1); /* Core reset */ + set_reset_reg_value('hc4, 'h1); /* Core state */ +// set_reset_reg_value('hc8, 'h28000); /* clock monitor */ + set_reset_reg_value('h210, 'h3); /* OCTETS_PER_MULTIFRAME */ + set_reset_reg_value('h248, 'h4); /* FRAME_ALIGN_ERR_THRESHOLD */ + + /* Lane error statistics */ + for (i = 0; i < NUM_LANES; i = i + 1) begin + set_reset_reg_value('h308 + i*'h20, core_status_err_statistics_cnt[32*i+:32]); + end + end + endtask + + task check_all_registers; + integer i; + begin + for (i = 0; i < 'h400; i = i + 4) begin + read_reg_check(i, read_match); + end + end + endtask + + task write_reg_and_update; + input [31:0] addr; + input [31:0] value; + integer i; + begin + write_reg(addr, value); + expected_reg_mem[addr[13:2]] <= value; + + if (addr == 'hc0) begin + expected_reg_mem['hc4/4][0] <= value[0]; + end + end + endtask + + task invert_register; + input [31:0] addr; + reg [31:0] value; + begin + read_reg(addr, value); + write_reg(addr, ~value); + end + endtask + + task invert_all_registers; + integer i; + begin + for (i = 0; i < 'h400; i = i + 4) begin + invert_register(i); + end + end + endtask + + /* ILAS memory */ + + reg core_ilas_config_valid = 1'b0; + reg [1:0] core_ilas_config_addr = 2'b00; + wire [NUM_LANES*32-1:0] core_ilas_config_data; + + generate + genvar l; + for (l = 0; l < NUM_LANES; l = l + 1) begin + localparam [3:0] l2 = l; + assign core_ilas_config_data[32*l+31:32*l] = { + l2,core_ilas_config_addr,2'h3, + l2,core_ilas_config_addr,2'h2, + l2,core_ilas_config_addr,2'h1, + l2,core_ilas_config_addr,2'h0 + }; + + assign core_status_err_statistics_cnt[32*l+:32] = {28'hffaa550,l2}; + end + endgenerate + + task set_ilas_registers; + integer i; + reg [3:0] lane; + begin + for (i = 0; i < 4; i = i + 1) begin + @(posedge core_clk) + core_ilas_config_valid <= 1'b1; + core_ilas_config_addr <= i; + end + @(posedge core_clk) + core_ilas_config_valid <= 1'b0; + core_ilas_config_addr <= 0; + @(posedge core_clk) #0; + + /* Update the expected values */ + for (i = 0; i < NUM_LANES * 'h20; i = i + 'h20) begin + lane = i / 20; + set_reset_reg_value('h300 + i, 'h20); + set_reset_reg_value('h310 + i, 'h03020100 | {4{lane,4'h0}}); + set_reset_reg_value('h314 + i, 'h07060504 | {4{lane,4'h0}}); + set_reset_reg_value('h318 + i, 'h0b0a0908 | {4{lane,4'h0}}); + set_reset_reg_value('h31c + i, 'h0f0e0d0c | {4{lane,4'h0}}); + end + end + endtask + + integer i; + initial begin + #1; + initialize_expected_reg_mem(); + @(posedge s_axi_aresetn) + check_all_registers(); + + /* Check scratch */ + write_reg_and_update('h08, 32'h12345678); + check_all_registers(); + + /* Check IRQ mask */ + write_reg_and_update('h80, 32'h0); + check_all_registers(); + + /* Check lanes enable */ + write_reg_and_update('h200, {NUM_LANES{1'b1}}); + check_all_registers(); + + /* Check JESD common config */ + write_reg_and_update('h210, 32'hff03ff); + check_all_registers(); + write_reg_and_update('h214, 32'h03); + check_all_registers(); + + /* Check links enable */ + write_reg_and_update('h218, {NUM_LINKS{1'b1}}); + check_all_registers(); + + /* Check JESD RX configuration */ + write_reg_and_update('h240, 32'h103fc); + check_all_registers(); + + /* Reset core */ + write_reg_and_update('hc0, 32'h0); + check_all_registers(); + + /* Should be read-only when core is out of reset */ + invert_register('h200); /* lanes enable */ + invert_register('h210); /* octets per frame, octets per multiframe */ + invert_register('h218); /* links enable */ + invert_register('h240); /* char replacement, scrambler */ + + check_all_registers(); + + /* Check ILAS */ + set_ilas_registers(); + check_all_registers(); + + /* Check that reset works for all registers */ + do_trigger_reset(); + initialize_expected_reg_mem(); + check_all_registers(); + invert_all_registers(); + do_trigger_reset(); + check_all_registers(); + end + + axi_jesd204_rx #( + .NUM_LANES(NUM_LANES), + .NUM_LINKS(NUM_LINKS) + ) i_axi ( + .s_axi_aclk(s_axi_aclk), + .s_axi_aresetn(s_axi_aresetn), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awready(s_axi_awready), + .s_axi_awprot(s_axi_awprot), + .s_axi_wvalid(s_axi_wvalid), + .s_axi_wdata(s_axi_wdata), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wready(s_axi_wready), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_bresp(s_axi_bresp), + .s_axi_bready(s_axi_bready), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_araddr(s_axi_araddr), + .s_axi_arready(s_axi_arready), + .s_axi_arprot(s_axi_arprot), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_rready(s_axi_rready), + .s_axi_rresp(s_axi_rresp), + .s_axi_rdata(s_axi_rdata), + + .core_clk(core_clk), + .core_reset_ext(1'b0), + + .core_ilas_config_valid({NUM_LANES{core_ilas_config_valid}}), + .core_ilas_config_addr({NUM_LANES{core_ilas_config_addr}}), + .core_ilas_config_data(core_ilas_config_data), + + .device_event_sysref_alignment_error(1'b0), + .device_event_sysref_edge(1'b0), + + .core_status_err_statistics_cnt(core_status_err_statistics_cnt), + .core_ctrl_err_statistics_mask(), + .core_ctrl_err_statistics_reset(), + + .core_status_ctrl_state(2'b00), + .core_status_lane_cgs_state({NUM_LANES{2'b0}}), + .core_status_lane_emb_state({NUM_LANES{3'b0}}), + .core_status_lane_ifs_ready({NUM_LANES{1'b0}}), + .core_status_lane_latency({NUM_LANES{14'h00}}), + .core_status_lane_frame_align_err_cnt({NUM_LANES{8'b0}}), + + .status_synth_params0(NUM_LANES), + .status_synth_params1(2), + .status_synth_params2(NUM_LINKS)); + +endmodule diff --git a/adi_library/jesd204/tb/axi_jesd204_tx_regmap_tb b/adi_library/jesd204/tb/axi_jesd204_tx_regmap_tb new file mode 100755 index 00000000..604fd263 --- /dev/null +++ b/adi_library/jesd204/tb/axi_jesd204_tx_regmap_tb @@ -0,0 +1,15 @@ +#!/bin/bash + +SOURCE="axi_jesd204_tx_regmap_tb.v" +SOURCE+=" ../axi_jesd204_tx/axi_jesd204_tx.v" +SOURCE+=" ../axi_jesd204_tx/jesd204_up_tx.v" +SOURCE+=" ../axi_jesd204_common/jesd204_up_common.v" +SOURCE+=" ../axi_jesd204_common/jesd204_up_sysref.v" +SOURCE+=" ../../common/up_axi.v" +SOURCE+=" ../../common/up_clock_mon.v" +SOURCE+=" ../../util_cdc/sync_bits.v" +SOURCE+=" ../../util_cdc/sync_data.v" +SOURCE+=" ../../util_cdc/sync_event.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/jesd204/tb/axi_jesd204_tx_regmap_tb.v b/adi_library/jesd204/tb/axi_jesd204_tx_regmap_tb.v new file mode 100644 index 00000000..49408390 --- /dev/null +++ b/adi_library/jesd204/tb/axi_jesd204_tx_regmap_tb.v @@ -0,0 +1,334 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_jesd204_tx_regmap_tb; + parameter VCD_FILE = "axi_jesd204_tx_regmap_tb.vcd"; + parameter NUM_LANES = 2; + parameter NUM_LINKS = 2; + + `define TIMEOUT 1000000 + `include "tb_base.v" + + reg [1:0] core_status_state = 2'b00; + reg [NUM_LINKS-1:0] core_status_sync = {NUM_LINKS{1'b0}}; + + wire s_axi_aclk = clk; + wire s_axi_aresetn = ~reset; + + reg s_axi_awvalid = 1'b0; + reg s_axi_wvalid = 1'b0; + reg [13:0] s_axi_awaddr = 'h00; + reg [31:0] s_axi_wdata = 'h00; + wire [1:0] s_axi_bresp; + wire s_axi_awready; + wire s_axi_wready; + wire s_axi_bready = 1'b1; + wire [3:0] s_axi_wstrb = 4'b1111; + wire [2:0] s_axi_awprot = 3'b000; + wire [2:0] s_axi_arprot = 3'b000; + wire [1:0] s_axi_rresp; + wire [31:0] s_axi_rdata; + + reg [31:0] expected_reg_mem[0:1023]; + + task write_reg; + input [31:0] addr; + input [31:0] value; + begin + @(posedge s_axi_aclk) + s_axi_awvalid <= 1'b1; + s_axi_wvalid <= 1'b1; + s_axi_awaddr <= addr; + s_axi_wdata <= value; + @(posedge s_axi_aclk) + while (s_axi_awvalid || s_axi_wvalid) begin + @(posedge s_axi_aclk) + if (s_axi_awready) + s_axi_awvalid <= 1'b0; + if (s_axi_wready) + s_axi_wvalid <= 1'b0; + end + end + endtask + + reg [13:0] s_axi_araddr = 'h0; + reg s_axi_arvalid = 'h0; + reg s_axi_rready = 'h0; + wire s_axi_arready; + wire s_axi_rvalid; + + task read_reg; + input [31:0] addr; + output [31:0] value; + begin + s_axi_arvalid <= 1'b1; + s_axi_araddr <= addr; + s_axi_rready <= 1'b1; + @(posedge s_axi_aclk) #0; + while (s_axi_arvalid) begin + if (s_axi_arready == 1'b1) begin + s_axi_arvalid <= 1'b0; + end + @(posedge s_axi_aclk) #0; + end + + while (s_axi_rready) begin + if (s_axi_rvalid == 1'b1) begin + value <= s_axi_rdata; + s_axi_rready <= 1'b0; + end + @(posedge s_axi_aclk) #0; + end + end + endtask + + task read_reg_check; + input [31:0] addr; + output match; + reg [31:0] value; + reg [31:0] expected; + begin + read_reg(addr, value); + expected = expected_reg_mem[addr[13:2]]; + match <= value === expected; + if (value !== expected) begin + $display("Address %h, Expected %h, Found %h", addr, expected, value); + end + end + endtask + + reg read_match = 1'b1; + + always @(posedge clk) begin + if (read_match == 1'b0) begin + failed <= 1'b1; + end + end + + task set_reset_reg_value; + input [31:0] addr; + input [31:0] value; + begin + expected_reg_mem[addr[13:2]] <= value; + end + endtask + + task initialize_expected_reg_mem; + integer i; + begin + for (i = 0; i < 1024; i = i + 1) + expected_reg_mem[i] <= 'h00; + /* Non zero power-on-reset values */ + set_reset_reg_value('h00, 32'h00010661); /* PCORE version register */ + set_reset_reg_value('h0c, 32'h32303454); /* PCORE magic register */ + set_reset_reg_value('h10, NUM_LANES); /* Number of lanes */ + set_reset_reg_value('h14, 'h2); /* Datapath width */ + set_reset_reg_value('h18, NUM_LINKS); /* Number of links */ + set_reset_reg_value('hc0, 'h1); /* Link disable */ + set_reset_reg_value('hc4, 'h1); /* Core state */ +// set_reset_reg_value('hc8, 'h80000); /* clock monitor */ + set_reset_reg_value('h210, 'h3); /* OCTETS_PER_MULTIFRAME */ + + set_reset_reg_value('h244, 'h3); /* MFRAMES_PER_ILAS */ + end + endtask + + task check_all_registers; + integer i; + begin + for (i = 0; i < 'h400; i = i + 4) begin + read_reg_check(i, read_match); + end + end + endtask + + task write_reg_and_update; + input [31:0] addr; + input [31:0] value; + integer i; + begin + write_reg(addr, value); + expected_reg_mem[addr[13:2]] <= value; + + /* Special case for ILAS */ + if (addr >= 'h310 && addr < 'h310 + 32 * NUM_LANES) begin + for (i = 0; i < NUM_LANES; i = i + 1) begin + case (addr[3:2]) + 2'b01: expected_reg_mem['h310/4 + i * 8 + 1][31:5] <= value[31:5]; + 2'b11: expected_reg_mem['h310/4 + i * 8 + 3][23:0] <= value[23:0]; + default: expected_reg_mem['h310/4 + i * 8 + addr[3:2]] <= value; + endcase + end + end + + if (addr == 'hc0) begin + expected_reg_mem['hc4/4][0] <= value[0]; + end + end + endtask + + task invert_register; + input [31:0] addr; + reg [31:0] value; + begin + read_reg(addr, value); + write_reg(addr, ~value); + end + endtask + + task invert_all_registers; + integer i; + begin + for (i = 0; i < 'h400; i = i + 4) begin + invert_register(i); + end + end + endtask + + integer i; + initial begin + initialize_expected_reg_mem(); + @(posedge s_axi_aresetn) + check_all_registers(); + + /* Check scratch */ + write_reg_and_update('h08, 32'h12345678); + check_all_registers(); + + /* Check IRQ mask */ + write_reg_and_update('h80, 32'h0); + check_all_registers(); + + /* Check lanes disable */ + write_reg_and_update('h200, {NUM_LANES{1'b1}}); + check_all_registers(); + + /* Check JESD common config */ + write_reg_and_update('h210, 32'hff03ff); + check_all_registers(); + write_reg_and_update('h214, 32'h03); + check_all_registers(); + + /* Check links disable */ + write_reg_and_update('h218, {NUM_LINKS{1'b1}}); + check_all_registers(); + + /* Check JESD TX configuration */ + write_reg_and_update('h240, 32'h07); + check_all_registers(); + + /* Check mframes per ILAS - RO at the moment */ + write_reg('h244, 32'hff); + check_all_registers(); + + /* Check status register */ + core_status_state = 2'b01; /* CGS */ + set_reset_reg_value('h280, 32'h00000001); + check_all_registers(); + core_status_state = 2'b10; /* ILAS */ + set_reset_reg_value('h280, 32'h00000002); + check_all_registers(); + core_status_state = 2'b11; /* DATA */ + set_reset_reg_value('h280, 32'h00000003); + check_all_registers(); + core_status_state = 2'b00; /* WAIT */ + set_reset_reg_value('h280, 32'h00000000); + check_all_registers(); + + core_status_sync = {NUM_LINKS{1'b1}}; /* SYNC deasserted */ + set_reset_reg_value('h280, ({NUM_LINKS{1'b1}} << 4)); + check_all_registers(); + core_status_sync = {NUM_LINKS{1'b0}}; /* SYNC asserted */ + set_reset_reg_value('h280, 32'h00000000); + check_all_registers(); + + /* ILAS register */ + for (i = 0; i < NUM_LANES; i = i + 1) begin + write_reg_and_update('h310 + i * 32, 32'h0fff0000); + write_reg_and_update('h314 + i * 32, 32'h1fff9f1f ^ i); + write_reg_and_update('h318 + i * 32, 32'hffffdfff ^ i); + write_reg_and_update('h31c + i * 32, 32'h0f00009f ^ (2 << 24)); + end + check_all_registers(); + + /* Reset core */ + write_reg_and_update('hc0, 32'h0); + check_all_registers(); + + /* Should be read-only when core is out of reset */ + invert_register('h200); + invert_register('h210); + invert_register('h214); + invert_register('h218); + invert_register('h240); + invert_register('h244); + for (i = 0; i < NUM_LANES; i = i + 1) begin + invert_register('h310 + i * 32); + invert_register('h314 + i * 32); + invert_register('h318 + i * 32); + invert_register('h31c + i * 32); + end + + check_all_registers(); + + /* Check that reset works for all registers */ + do_trigger_reset(); + initialize_expected_reg_mem(); + check_all_registers(); + invert_all_registers(); + do_trigger_reset(); + check_all_registers(); + end + + reg core_clk = 1'b0; + always @(*) #4 core_clk <= ~core_clk; + + axi_jesd204_tx #( + .NUM_LANES(NUM_LANES), + .NUM_LINKS(NUM_LINKS) + ) i_axi ( + .s_axi_aclk(s_axi_aclk), + .s_axi_aresetn(s_axi_aresetn), + .s_axi_awvalid(s_axi_awvalid), + .s_axi_awaddr(s_axi_awaddr), + .s_axi_awready(s_axi_awready), + .s_axi_awprot(s_axi_awprot), + .s_axi_wvalid(s_axi_wvalid), + .s_axi_wdata(s_axi_wdata), + .s_axi_wstrb(s_axi_wstrb), + .s_axi_wready(s_axi_wready), + .s_axi_bvalid(s_axi_bvalid), + .s_axi_bresp(s_axi_bresp), + .s_axi_bready(s_axi_bready), + .s_axi_arvalid(s_axi_arvalid), + .s_axi_araddr(s_axi_araddr), + .s_axi_arready(s_axi_arready), + .s_axi_arprot(s_axi_arprot), + .s_axi_rvalid(s_axi_rvalid), + .s_axi_rready(s_axi_rready), + .s_axi_rresp(s_axi_rresp), + .s_axi_rdata(s_axi_rdata), + + .core_clk(core_clk), + .core_reset_ext(1'b0), + + .core_ilas_config_rd(1'b1), + .core_ilas_config_addr(2'b00), + + .device_event_sysref_alignment_error(1'b0), + .device_event_sysref_edge(1'b0), + + .core_status_state(core_status_state), + .core_status_sync(core_status_sync), + + .status_synth_params0(NUM_LANES), + .status_synth_params1(2), + .status_synth_params2(NUM_LINKS)); + +endmodule diff --git a/adi_library/jesd204/tb/crc12_tb b/adi_library/jesd204/tb/crc12_tb new file mode 100755 index 00000000..9a805bf2 --- /dev/null +++ b/adi_library/jesd204/tb/crc12_tb @@ -0,0 +1,7 @@ +#!/bin/bash + +SOURCE="crc12_tb.v" +SOURCE+=" ../jesd204_common/jesd204_crc12.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/jesd204/tb/crc12_tb.v b/adi_library/jesd204/tb/crc12_tb.v new file mode 100644 index 00000000..74e413f1 --- /dev/null +++ b/adi_library/jesd204/tb/crc12_tb.v @@ -0,0 +1,66 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module crc12_tb; + parameter VCD_FILE = "crc12_tb.vcd"; + + `define TIMEOUT 400 + + `include "tb_base.v" + + reg [63:0] data_in = 'h0; + reg [11:0] ref_crc12 = 'h0; + wire [11:0] crc12; + reg test_en = 1'b1; + reg init = 1'b0; + + jesd204_crc12 DUT ( + .clk (clk), + .reset (1'b0), + .init (init), + .data_in (data_in), + .crc12 (crc12)); + + // Test against dataset from the standard + // - Test contiguous input stream with init phase + initial begin + @(negedge reset); + @(posedge clk); + repeat (3) begin + @(posedge clk) data_in <= 'h80_01_02_03_05_05_04_23; + init <= 1'b1; + @(posedge clk) data_in <= 'h0e_43_80_c2_0b_50_81_cd; + init <= 1'b0; + @(posedge clk) data_in <= 'h04_e7_83_92_5a_3c_aa_51; + @(posedge clk) data_in <= 'h05_4d_87_d9_31_3d_11_51; + end + @(posedge clk); + @(posedge clk); + test_en <= 1'b0; + end + + initial begin + @(negedge reset); + @(posedge clk); + @(posedge clk); + repeat(3) begin + @(posedge clk) ref_crc12 <= 'hd00; + @(posedge clk) ref_crc12 <= 'h11c; + @(posedge clk) ref_crc12 <= 'hfea; + @(posedge clk) ref_crc12 <= 'h5fe; + end + end + + always @(posedge clk) begin + if (ref_crc12 != crc12 && failed == 1'b0 && test_en) begin + failed <= 1'b1; + end + end + +endmodule diff --git a/adi_library/jesd204/tb/frame_align_tb b/adi_library/jesd204/tb/frame_align_tb new file mode 100755 index 00000000..36a854b7 --- /dev/null +++ b/adi_library/jesd204/tb/frame_align_tb @@ -0,0 +1,23 @@ +#!/bin/bash + +SOURCE="frame_align_tb.v" +SOURCE+=" ../jesd204_common/jesd204_lmfc.v ../jesd204_common/jesd204_scrambler.v ../jesd204_common/jesd204_eof_generator.v" +SOURCE+=" ../jesd204_common/pipeline_stage.v ../jesd204_common/jesd204_frame_mark.v ../jesd204_common/jesd204_frame_align_replace.v" +SOURCE+=" ../jesd204_rx/jesd204_rx.v ../jesd204_rx/jesd204_rx_lane.v" +SOURCE+=" ../jesd204_rx/jesd204_ilas_monitor.v ../jesd204_rx/align_mux.v ../jesd204_rx/jesd204_rx_cgs.v" +SOURCE+=" ../jesd204_rx/jesd204_rx_ctrl.v ../jesd204_rx/elastic_buffer.v ../jesd204_rx/jesd204_lane_latency_monitor.v" +SOURCE+=" ../jesd204_rx/jesd204_rx_frame_align.v" +SOURCE+=" ../jesd204_rx_static_config/jesd204_rx_static_config.v" +SOURCE+=" ../jesd204_tx/jesd204_tx.v ../jesd204_tx/jesd204_tx_ctrl.v ../jesd204_tx/jesd204_tx_lane.v" +SOURCE+=" ../jesd204_tx_static_config/jesd204_tx_static_config.v" +SOURCE+=" ../jesd204_tx_static_config/jesd204_ilas_cfg_static.v" +SOURCE+=" ../../util_cdc/sync_bits.v" +SOURCE+=" ../../util_cdc/sync_event.v" +SOURCE+=" ../../common/ad_mem.v" +SOURCE+=" ../../common/ad_mem_asym.v" +SOURCE+=" ../../util_axis_fifo/util_axis_fifo_address_generator.v" +SOURCE+=" ../../util_axis_fifo/util_axis_fifo.v" + + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/jesd204/tb/frame_align_tb.v b/adi_library/jesd204/tb/frame_align_tb.v new file mode 100755 index 00000000..171ba5bc --- /dev/null +++ b/adi_library/jesd204/tb/frame_align_tb.v @@ -0,0 +1,584 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module frame_align_tb; + parameter VCD_FILE = "frame_align_tb.vcd"; + parameter NUM_LANES = 1; + parameter NUM_LINKS = 1; + parameter OCTETS_PER_FRAME = 3; + parameter FRAMES_PER_MULTIFRAME = 8; + parameter NUM_CONVERTERS = 1; + parameter N = 16; + parameter NP = 16; + parameter HIGH_DENSITY = 1'b0; + parameter ENABLE_SCRAMBLER = 0; + parameter BUFFER_EARLY_RELEASE = 1; + parameter SYSREF_DISABLE = 1; + parameter SYSREF_ONE_SHOT = 0; + parameter LANE_DELAY = 1; + parameter DATA_PATH_WIDTH = 8; + parameter DATA_RANDOM = ENABLE_SCRAMBLER ? 0 : 1; + parameter ALIGN_ERROR_PERCENT = 50; + + localparam DPW_LOG2 = DATA_PATH_WIDTH == 8 ? 3 : DATA_PATH_WIDTH == 4 ? 2 : 1; + localparam BEATS_PER_MULTIFRAME = OCTETS_PER_FRAME * FRAMES_PER_MULTIFRAME / 4; + localparam TX_LATENCY = 3; + wire [31:0] RX_LATENCY = 3 + i_rx.CHAR_INFO_REGISTERED + i_rx.ALIGN_MUX_REGISTERED + i_rx.SCRAMBLER_REGISTERED; + wire [31:0] BASE_LATENCY = TX_LATENCY + RX_LATENCY; + localparam SYSREF_HALF_COUNT = OCTETS_PER_FRAME * FRAMES_PER_MULTIFRAME; + + `define TIMEOUT 1000000 + + `include "tb_base.v" + + reg [5:0] tx_counter = 'h00; + reg [5:0] rx_counter = 'h00; + reg [NUM_LANES*DATA_PATH_WIDTH*8-1:0] rx_mask = 64'hffffffffffff0000; + wire tx_ready; + wire rx_valid; + wire [NUM_LANES*DATA_PATH_WIDTH*8-1:0] rx_data; + wire [DATA_PATH_WIDTH-1:0] rx_eof; + wire [DATA_PATH_WIDTH-1:0] rx_sof; + wire cur_data_mismatch; + reg data_mismatch = 1'b1; + reg enable_checker = 1'b0; + wire [NUM_LINKS-1:0] sync; + + always @(posedge clk) begin + if (sync == 1'b0) begin + tx_counter <= 'h00000000; + end else if (tx_ready == 1'b1) begin + tx_counter <= tx_counter + 1'b1; + end + end + + always @(posedge clk) begin + if (sync == 1'b0) begin + rx_counter <= 'h00000000; + if (ENABLE_SCRAMBLER == 1'b1) begin + rx_mask <= {NUM_LANES{64'hffffffffffff0000}}; // First two octets are invalid due to scrambling + end else begin + rx_mask <= {NUM_LANES{64'hffffffffffffffff}}; + end + end else if (rx_valid == 1'b1) begin + rx_counter <= rx_counter + 1'b1; + rx_mask <= {NUM_LANES{64'hffffffffffffffff}}; + end + end + + reg [(DATA_PATH_WIDTH*8)-1:0] tx_random_data; + wire [(DATA_PATH_WIDTH*8)-1:0] tx_data; + wire [(DATA_PATH_WIDTH*8)-1:0] rx_ref_data; + + genvar ii; + generate + for(ii = 0; ii < DATA_PATH_WIDTH; ii=ii+1) begin : data_gen + wire [1:0] ii_sig = ii; + + always @(posedge clk) begin + tx_random_data[ii*8+:8] <= $urandom(); + end + + assign tx_data[ii*8+:8] = DATA_RANDOM ? tx_random_data[ii*8+:8] : {tx_counter, ii_sig}; + assign rx_ref_data[ii*8+:8] = {rx_counter, ii_sig}; + end + endgenerate + + wire [NUM_LANES*DATA_PATH_WIDTH*8-1:0] phy_data_out; + wire [NUM_LANES*DATA_PATH_WIDTH-1:0] phy_charisk_out; + wire [NUM_LANES*DATA_PATH_WIDTH*8-1:0] phy_data_delayed; + wire [NUM_LANES*DATA_PATH_WIDTH-1:0] phy_charisk_delayed; + reg [NUM_LANES*DATA_PATH_WIDTH*8-1:0] phy_data_in; + reg [NUM_LANES*DATA_PATH_WIDTH-1:0] phy_charisk_in; + + reg align_err_mf = 1'b0; + reg align_err_f = 1'b0; + reg cur_err; + + reg [9:0] sysref_counter = 'h00; + reg sysref_rx = 1'b0; + reg sysref_tx = 1'b0; + + always @(posedge clk) begin + if (sysref_counter == (SYSREF_HALF_COUNT-1)) begin + sysref_rx <= ~sysref_rx; + sysref_counter <= 'b0; + end else begin + sysref_counter <= sysref_counter + 1'b1; + end + sysref_tx <= sysref_rx; + end + + localparam MAX_LANE_DELAY = LANE_DELAY + NUM_LANES; + + reg [10:0] phy_delay_fifo_wr; + reg [DATA_PATH_WIDTH*9*NUM_LANES-1:0] phy_delay_fifo[0:MAX_LANE_DELAY-1]; + + always @(posedge clk) begin + phy_delay_fifo[phy_delay_fifo_wr] <= {phy_charisk_out,phy_data_out}; + + if (reset == 1'b1 || phy_delay_fifo_wr == MAX_LANE_DELAY-1) begin + phy_delay_fifo_wr <= 'h00; + end else begin + phy_delay_fifo_wr <= phy_delay_fifo_wr + 1'b1; + end + end + + initial begin + #10000; + enable_checker = 1'b1; + #100000; + align_err_f = 1'b1; + #50000; + align_err_f = 1'b0; + #100000; + + align_err_mf = 1'b1; + #50000; + align_err_mf = 1'b0; + #100000; + + align_err_f = 1'b1; + align_err_mf = 1'b1; + #50000; + align_err_f = 1'b0; + align_err_mf = 1'b0; + #100000; + end + + always @(posedge clk) begin + if(ALIGN_ERROR_PERCENT != 0) begin + cur_err <= $urandom_range(99) < ALIGN_ERROR_PERCENT; + end else begin + cur_err <= 1'b0; + end + end + + genvar i; + generate for (i = 0; i < NUM_LANES; i = i + 1) begin + localparam OFF = MAX_LANE_DELAY - (i + LANE_DELAY); + assign phy_data_delayed[DATA_PATH_WIDTH*8*i+(DATA_PATH_WIDTH*8)-1:DATA_PATH_WIDTH*8*i] = + phy_delay_fifo[(phy_delay_fifo_wr + OFF) % MAX_LANE_DELAY][DATA_PATH_WIDTH*8*i+(DATA_PATH_WIDTH*8)-1:DATA_PATH_WIDTH*8*i]; + assign phy_charisk_delayed[DATA_PATH_WIDTH*i+DATA_PATH_WIDTH-1:DATA_PATH_WIDTH*i]= + phy_delay_fifo[(phy_delay_fifo_wr + OFF) % MAX_LANE_DELAY][DATA_PATH_WIDTH*i+DATA_PATH_WIDTH-1+NUM_LANES*DATA_PATH_WIDTH*8:DATA_PATH_WIDTH*i+DATA_PATH_WIDTH*8*NUM_LANES]; + end endgenerate + + always @(*) begin + phy_data_in = phy_data_delayed; + phy_charisk_in = phy_charisk_delayed; + + if(cur_err) begin + if(align_err_mf) begin + phy_data_in = {NUM_LANES*4{8'h7C}}; + phy_charisk_in = {NUM_LANES*4{1'b1}}; + end else if(align_err_f) begin + phy_data_in = {NUM_LANES*4{8'hFC}}; + phy_charisk_in = {NUM_LANES*4{1'b1}}; + end + end + end + + wire [NUM_LANES-1:0] tx_cfg_lanes_disable; + wire [NUM_LINKS-1:0] tx_cfg_links_disable; + wire [9:0] tx_cfg_octets_per_multiframe; + wire [7:0] tx_cfg_octets_per_frame; + wire [7:0] tx_device_cfg_lmfc_offset; + wire [9:0] tx_device_cfg_octets_per_multiframe; + wire [7:0] tx_device_cfg_octets_per_frame; + wire [7:0] tx_device_cfg_beats_per_multiframe; + wire tx_device_cfg_sysref_disable; + wire tx_device_cfg_sysref_oneshot; + wire tx_cfg_continuous_cgs; + wire tx_cfg_continuous_ilas; + wire tx_cfg_skip_ilas; + wire [7:0] tx_cfg_mframes_per_ilas; + wire tx_cfg_disable_char_replacement; + wire tx_cfg_disable_scrambler; + wire tx_lmfc_edge; + wire tx_lmfc_clk; + wire [DATA_PATH_WIDTH-1:0] tx_eof; + wire [DATA_PATH_WIDTH-1:0] tx_sof; + + wire tx_ilas_config_rd; + wire [1:0] tx_ilas_config_addr; + wire [DATA_PATH_WIDTH*8*NUM_LANES-1:0] tx_ilas_config_data; + wire tx_event_sysref_edge; + wire tx_event_sysref_alignment_error; + wire [NUM_LINKS-1:0] tx_status_sync; + wire [1:0] tx_status_state; + + jesd204_tx_static_config #( + .NUM_LANES(NUM_LANES), + .NUM_LINKS(NUM_LINKS), + .OCTETS_PER_FRAME(OCTETS_PER_FRAME), + .FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME), + .NUM_CONVERTERS(NUM_CONVERTERS), + .N(N), + .NP(NP), + .HIGH_DENSITY(HIGH_DENSITY), + .SCR(ENABLE_SCRAMBLER), + .LINK_MODE(1), + .SYSREF_DISABLE(SYSREF_DISABLE), + .SYSREF_ONE_SHOT(SYSREF_ONE_SHOT), + .DATA_PATH_WIDTH(DATA_PATH_WIDTH), + .TPL_DATA_PATH_WIDTH(DATA_PATH_WIDTH) + ) i_tx_cfg ( + .clk(clk), + + .cfg_lanes_disable(tx_cfg_lanes_disable), + .cfg_links_disable(tx_cfg_links_disable), + .cfg_octets_per_multiframe(tx_cfg_octets_per_multiframe), + .cfg_octets_per_frame(tx_cfg_octets_per_frame), + .cfg_continuous_cgs(tx_cfg_continuous_cgs), + .cfg_continuous_ilas(tx_cfg_continuous_ilas), + .cfg_skip_ilas(tx_cfg_skip_ilas), + .cfg_mframes_per_ilas(tx_cfg_mframes_per_ilas), + .cfg_disable_char_replacement(tx_cfg_disable_char_replacement), + .cfg_disable_scrambler(tx_cfg_disable_scrambler), + + .device_cfg_octets_per_multiframe(tx_device_cfg_octets_per_multiframe), + .device_cfg_octets_per_frame(tx_device_cfg_octets_per_frame), + .device_cfg_beats_per_multiframe(tx_device_cfg_beats_per_multiframe), + .device_cfg_lmfc_offset(tx_device_cfg_lmfc_offset), + .device_cfg_sysref_disable(tx_device_cfg_sysref_disable), + .device_cfg_sysref_oneshot(tx_device_cfg_sysref_oneshot), + + .ilas_config_rd(tx_ilas_config_rd), + .ilas_config_addr(tx_ilas_config_addr), + .ilas_config_data(tx_ilas_config_data)); + + jesd204_tx #( + .NUM_LANES(NUM_LANES), + .NUM_LINKS(NUM_LINKS), + .NUM_OUTPUT_PIPELINE(0), + .LINK_MODE(1), + .DATA_PATH_WIDTH(DATA_PATH_WIDTH), + .TPL_DATA_PATH_WIDTH(DATA_PATH_WIDTH), + .ASYNC_CLK(0), + .ENABLE_CHAR_REPLACE(1) + ) i_tx ( + .clk(clk), + .reset(reset), + + .device_clk(clk), + .device_reset(reset), + + .phy_data(phy_data_out), + .phy_charisk(phy_charisk_out), + .phy_header(), + + .sysref(sysref_tx), + .lmfc_edge(tx_lmfc_edge), + .lmfc_clk(tx_lmfc_clk), + + .sync(sync), + + .tx_data({NUM_LANES{tx_data}}), + .tx_ready(tx_ready), + .tx_eof(tx_eof), + .tx_sof(tx_sof), + .tx_somf(), + .tx_eomf(), + .tx_valid(1'b1), + + .cfg_lanes_disable(tx_cfg_lanes_disable), + .cfg_links_disable(tx_cfg_links_disable), + .cfg_octets_per_multiframe(tx_cfg_octets_per_multiframe), + .cfg_octets_per_frame(tx_cfg_octets_per_frame), + .cfg_continuous_cgs(tx_cfg_continuous_cgs), + .cfg_continuous_ilas(tx_cfg_continuous_ilas), + .cfg_skip_ilas(tx_cfg_skip_ilas), + .cfg_mframes_per_ilas(tx_cfg_mframes_per_ilas), + .cfg_disable_char_replacement(tx_cfg_disable_char_replacement), + .cfg_disable_scrambler(tx_cfg_disable_scrambler), + + .device_cfg_octets_per_multiframe(tx_device_cfg_octets_per_multiframe), + .device_cfg_octets_per_frame(tx_device_cfg_octets_per_frame), + .device_cfg_beats_per_multiframe(tx_device_cfg_beats_per_multiframe), + .device_cfg_lmfc_offset(tx_device_cfg_lmfc_offset), + .device_cfg_sysref_disable(tx_device_cfg_sysref_disable), + .device_cfg_sysref_oneshot(tx_device_cfg_sysref_oneshot), + + .ilas_config_rd(tx_ilas_config_rd), + .ilas_config_addr(tx_ilas_config_addr), + .ilas_config_data(tx_ilas_config_data), + + .ctrl_manual_sync_request(1'b0), + + .device_event_sysref_edge (tx_event_sysref_edge), + .device_event_sysref_alignment_error (tx_event_sysref_alignment_error), + + .status_sync (tx_status_sync), + .status_state (tx_status_state), + + .status_synth_params0(), + .status_synth_params1(), + .status_synth_params2()); + + wire [NUM_LANES-1:0] rx_cfg_lanes_disable; + wire [NUM_LINKS-1:0] rx_cfg_links_disable; + wire [9:0] rx_cfg_octets_per_multiframe; + wire [7:0] rx_cfg_octets_per_frame; + wire [7:0] rx_device_cfg_lmfc_offset; + wire [9:0] rx_device_cfg_octets_per_multiframe; + wire [7:0] rx_device_cfg_octets_per_frame; + wire [7:0] rx_device_cfg_beats_per_multiframe; + wire rx_device_cfg_sysref_disable; + wire rx_device_cfg_sysref_oneshot; + wire rx_device_cfg_buffer_early_release; + wire [7:0] rx_device_cfg_buffer_delay; + wire rx_cfg_disable_scrambler; + wire rx_cfg_disable_char_replacement; + wire [NUM_LANES-1:0] rx_status_lane_ifs_ready; + wire [NUM_LANES*14-1:0] rx_status_lane_latency; + wire [NUM_LANES*8-1:0] rx_status_lane_frame_align_err_cnt; + wire [7:0] rx_cfg_frame_align_err_threshold; + wire [32*NUM_LANES-1:0] rx_status_err_statistics_cnt; + wire rx_lmfc_edge; + wire rx_lmfc_clk; + wire rx_event_sysref_alignment_error; + wire rx_event_sysref_edge; + wire [NUM_LANES-1:0] rx_ilas_config_valid; + wire [NUM_LANES*2-1:0] rx_ilas_config_addr; + wire [NUM_LANES*DATA_PATH_WIDTH*8-1:0] rx_ilas_config_data; + wire [1:0] rx_status_ctrl_state; + wire [2*NUM_LANES-1:0] rx_status_lane_cgs_state; + wire rx_phy_en_char_align; + + jesd204_rx_static_config #( + .NUM_LANES(NUM_LANES), + .NUM_LINKS(NUM_LINKS), + .OCTETS_PER_FRAME(OCTETS_PER_FRAME), + .FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME), + .SCR(ENABLE_SCRAMBLER), + .BUFFER_EARLY_RELEASE(BUFFER_EARLY_RELEASE), + .LINK_MODE(1), + .SYSREF_DISABLE(SYSREF_DISABLE), + .SYSREF_ONE_SHOT(SYSREF_ONE_SHOT), + .DATA_PATH_WIDTH(DATA_PATH_WIDTH), + .TPL_DATA_PATH_WIDTH(DATA_PATH_WIDTH) + ) i_rx_cfg ( + .clk(clk), + + .cfg_lanes_disable(rx_cfg_lanes_disable), + .cfg_links_disable(rx_cfg_links_disable), + .cfg_octets_per_multiframe(rx_cfg_octets_per_multiframe), + .cfg_octets_per_frame(rx_cfg_octets_per_frame), + .cfg_disable_scrambler(rx_cfg_disable_scrambler), + .cfg_disable_char_replacement(rx_cfg_disable_char_replacement), + .cfg_frame_align_err_threshold(rx_cfg_frame_align_err_threshold), + + .device_cfg_octets_per_multiframe(rx_device_cfg_octets_per_multiframe), + .device_cfg_octets_per_frame(rx_device_cfg_octets_per_frame), + .device_cfg_beats_per_multiframe(rx_device_cfg_beats_per_multiframe), + .device_cfg_lmfc_offset(rx_device_cfg_lmfc_offset), + .device_cfg_sysref_disable(rx_device_cfg_sysref_disable), + .device_cfg_sysref_oneshot(rx_device_cfg_sysref_oneshot), + .device_cfg_buffer_early_release(rx_device_cfg_buffer_early_release), + .device_cfg_buffer_delay(rx_device_cfg_buffer_delay)); + + jesd204_rx #( + .NUM_LANES(NUM_LANES), + .NUM_LINKS(NUM_LINKS), + .NUM_INPUT_PIPELINE(1), + .LINK_MODE(1), + .DATA_PATH_WIDTH(DATA_PATH_WIDTH), + .ENABLE_FRAME_ALIGN_CHECK(1), + .ENABLE_FRAME_ALIGN_ERR_RESET(1), + .TPL_DATA_PATH_WIDTH(DATA_PATH_WIDTH), + .ASYNC_CLK(0), + .ENABLE_CHAR_REPLACE(1) + ) i_rx ( + .clk(clk), + .reset(reset), + + .device_clk(clk), + .device_reset(reset), + + .phy_data(phy_data_in), + .phy_header({2*NUM_LANES{1'b0}}), + .phy_charisk(phy_charisk_in), + .phy_notintable({NUM_LANES*DATA_PATH_WIDTH{1'b0}}), + .phy_disperr({NUM_LANES*DATA_PATH_WIDTH{1'b0}}), + .phy_block_sync({NUM_LANES{1'b0}}), + + .sysref(sysref_rx), + .lmfc_edge(rx_lmfc_edge), + .lmfc_clk(rx_lmfc_clk), + + .device_event_sysref_alignment_error(rx_event_sysref_alignment_error), + .device_event_sysref_edge(rx_event_sysref_edge), + .event_frame_alignment_error(), + .event_unexpected_lane_state_error(), + + .sync(sync), + + .phy_en_char_align(rx_phy_en_char_align), + + .rx_data(rx_data), + .rx_valid(rx_valid), + .rx_eof(rx_eof), + .rx_sof(rx_sof), + .rx_eomf(), + .rx_somf(), + + .cfg_lanes_disable(rx_cfg_lanes_disable), + .cfg_links_disable(rx_cfg_links_disable), + .cfg_octets_per_multiframe(rx_cfg_octets_per_multiframe), + .cfg_octets_per_frame(rx_cfg_octets_per_frame), + .cfg_disable_char_replacement(rx_cfg_disable_char_replacement), + .cfg_disable_scrambler(rx_cfg_disable_scrambler), + + .device_cfg_octets_per_multiframe(rx_device_cfg_octets_per_multiframe), + .device_cfg_octets_per_frame(rx_device_cfg_octets_per_frame), + .device_cfg_beats_per_multiframe(rx_device_cfg_beats_per_multiframe), + .device_cfg_lmfc_offset(rx_device_cfg_lmfc_offset), + .device_cfg_sysref_disable(rx_device_cfg_sysref_disable), + .device_cfg_sysref_oneshot(rx_device_cfg_sysref_oneshot), + .device_cfg_buffer_early_release(rx_device_cfg_buffer_early_release), + .device_cfg_buffer_delay(rx_device_cfg_buffer_delay), + + .ctrl_err_statistics_reset(1'b0), + .ctrl_err_statistics_mask(7'b0), + + .cfg_frame_align_err_threshold(rx_cfg_frame_align_err_threshold), + + .status_err_statistics_cnt(rx_status_err_statistics_cnt), + + .ilas_config_valid(rx_ilas_config_valid), + .ilas_config_addr(rx_ilas_config_addr), + .ilas_config_data(rx_ilas_config_data), + + .status_ctrl_state(rx_status_ctrl_state), + .status_lane_cgs_state(rx_status_lane_cgs_state), + + .status_lane_ifs_ready(rx_status_lane_ifs_ready), + .status_lane_latency(rx_status_lane_latency), + .status_lane_emb_state(), + .status_lane_frame_align_err_cnt(rx_status_lane_frame_align_err_cnt), + + .status_synth_params0(), + .status_synth_params1(), + .status_synth_params2()); + + wire m_axis_aresetn; + wire m_axis_ready; + wire m_axis_valid; + wire [DATA_PATH_WIDTH*8-1:0] m_axis_data; + wire [DATA_PATH_WIDTH-1:0] m_axis_tkeep; + wire m_axis_tlast; + wire [DATA_PATH_WIDTH-1:0] m_axis_level; + wire m_axis_empty; + wire m_axis_almost_empty; + + wire s_axis_aresetn; + wire s_axis_ready; + wire s_axis_valid; + wire [DATA_PATH_WIDTH-1:0] s_axis_tkeep; + wire s_axis_tlast; + wire [DATA_PATH_WIDTH-1:0] s_axis_room; + wire s_axis_full; + wire s_axis_almost_full; + wire error_inject = (align_err_f | align_err_mf); + + reg invalid_data = 1'b0; + reg read_flag = 1'b1; + + assign s_axis_aresetn = ~error_inject; + assign m_axis_aresetn = ~error_inject; + assign m_axis_ready = rx_valid; + assign s_axis_valid = tx_ready; + + //util_axis_fifo instance + util_axis_fifo #( + .DATA_WIDTH(DATA_PATH_WIDTH*8), + .ADDRESS_WIDTH(DATA_PATH_WIDTH), + .ASYNC_CLK(0), + .M_AXIS_REGISTERED(0), + .ALMOST_EMPTY_THRESHOLD(16), + .ALMOST_FULL_THRESHOLD(16), + .TLAST_EN(0), + .TKEEP_EN(0), + .REMOVE_NULL_BEAT_EN(0) + ) some_fifo( + //rx is master so rx is "reading" from fifo + .m_axis_aclk(clk), + .m_axis_aresetn(m_axis_aresetn), + .m_axis_ready(m_axis_ready), + .m_axis_valid(m_axis_valid), + .m_axis_data(m_axis_data), + .m_axis_tkeep(m_axis_tkeep), + .m_axis_tlast(m_axis_tlast), + .m_axis_level(m_axis_level), + .m_axis_empty(m_axis_empty), + .m_axis_almost_empty(m_axis_almost_empty), + //tx is slave so tx writes in fifo + .s_axis_aclk(clk), + .s_axis_aresetn(s_axis_aresetn), + .s_axis_ready(s_axis_ready), + .s_axis_valid(s_axis_valid), + .s_axis_data(tx_data), + .s_axis_tkeep(s_axis_tkeep), + .s_axis_tlast(s_axis_tlast), + .s_axis_room(s_axis_room), + .s_axis_full(s_axis_full), + .s_axis_almost_full(s_axis_almost_full)); + + always @ (negedge error_inject) begin + //get fifo out of reset + #5000; //wait for tx_ready to rise up + if ((rx_valid == 0 || tx_ready == 0) && enable_checker == 1) begin + read_flag <= 1'b0; + end + end + + always @(posedge clk) begin + if (rx_valid == 1 && error_inject == 0) begin + //remove from the queue first element and compare to rx_data + //compare the data sent by tx with the data recieved + if(rx_data[DATA_PATH_WIDTH*8-1:0] !== m_axis_data) begin + invalid_data <= 1'b1; + end + end + end + + assign cur_data_mismatch = (rx_data & rx_mask) !== ({NUM_LANES{rx_ref_data}} & rx_mask); + + always @(posedge clk) begin + if (reset == 1'b1) begin + data_mismatch <= 1'b0; + end else if (rx_valid == 1'b1) begin + if (cur_data_mismatch) begin + data_mismatch <= 1'b1; + end + end + end + + reg [NUM_LANES-1:0] lane_latency_match; + + generate for (i = 0; i < NUM_LANES; i = i + 1) begin + wire [31:0] LANE_OFFSET = BASE_LATENCY + LANE_DELAY + BEATS_PER_MULTIFRAME + i; + + always @(posedge clk) begin + if (rx_status_lane_ifs_ready[i] == 1'b1 && + rx_status_lane_latency[i*14+13:i*14+DPW_LOG2] == LANE_OFFSET) begin + lane_latency_match[i] <= 1'b1; + end else begin + lane_latency_match[i] <= 1'b0; + end + end + end endgenerate + + always @(*) begin + if ((rx_valid == 1'b1 && invalid_data == 1'b1) || read_flag == 1'b0) begin + failed <= 1'b1; + end + end + +endmodule diff --git a/adi_library/jesd204/tb/jesd204_frame_align_replace_tb b/adi_library/jesd204/tb/jesd204_frame_align_replace_tb new file mode 100755 index 00000000..896cec77 --- /dev/null +++ b/adi_library/jesd204/tb/jesd204_frame_align_replace_tb @@ -0,0 +1,7 @@ +#!/bin/bash + +SOURCE="jesd204_frame_align_replace_tb.v" +SOURCE+=" ../jesd204_common/jesd204_frame_align_replace.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/jesd204/tb/jesd204_frame_align_replace_tb.v b/adi_library/jesd204/tb/jesd204_frame_align_replace_tb.v new file mode 100755 index 00000000..5ba5e76b --- /dev/null +++ b/adi_library/jesd204/tb/jesd204_frame_align_replace_tb.v @@ -0,0 +1,61 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_frame_align_replace_tb; + + parameter VCD_FILE = "jesd204_frame_align_replace_tb.vcd"; + `define TIMEOUT 1000000 + `include "tb_base.v" + + localparam DATA_PATH_WIDTH = 8; + localparam IS_RX = 1'b1; + + wire [7:0] cfg_octets_per_frame = 5; + wire cfg_disable_char_replacement = 1'b0; + wire cfg_disable_scrambler = 1'b1; + reg [DATA_PATH_WIDTH*8-1:0] data; + reg [DATA_PATH_WIDTH-1:0] eof; + reg [DATA_PATH_WIDTH-1:0] eomf; + reg [DATA_PATH_WIDTH-1:0] char_is_a; + reg [DATA_PATH_WIDTH-1:0] char_is_f; + wire [DATA_PATH_WIDTH*8-1:0] data_out; + wire [DATA_PATH_WIDTH-1:0] charisk_out; + reg [31:00] ii; + + initial begin + forever begin + for(ii = 0; ii < DATA_PATH_WIDTH; ii = ii + 1) begin + eof[ii] = $urandom_range(cfg_octets_per_frame) == 0; + eomf[ii] = $urandom_range(cfg_octets_per_frame*4) == 0; + char_is_a[ii] = $urandom_range(cfg_octets_per_frame*2) == 0; + char_is_f[ii] = $urandom_range(cfg_octets_per_frame*2) == 0; + end + data = {$urandom, $urandom}; + @(negedge clk); + end + end + + jesd204_frame_align_replace #( + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .IS_RX (IS_RX) + ) frame_align_replace ( + .clk (clk), + .reset (reset), + .cfg_octets_per_frame (cfg_octets_per_frame), + .cfg_disable_char_replacement (cfg_disable_char_replacement), + .cfg_disable_scrambler (cfg_disable_scrambler), + .data (data), + .eof (eof), + .rx_char_is_a (char_is_a), + .rx_char_is_f (char_is_f), + .tx_eomf (eomf), + .data_out (data_out), + .charisk_out (charisk_out)); + +endmodule diff --git a/adi_library/jesd204/tb/jesd204_frame_mark_tb b/adi_library/jesd204/tb/jesd204_frame_mark_tb new file mode 100755 index 00000000..63a17f97 --- /dev/null +++ b/adi_library/jesd204/tb/jesd204_frame_mark_tb @@ -0,0 +1,7 @@ +#!/bin/bash + +SOURCE="jesd204_frame_mark_tb.v" +SOURCE+=" ../jesd204_common/jesd204_frame_mark.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/jesd204/tb/jesd204_frame_mark_tb.v b/adi_library/jesd204/tb/jesd204_frame_mark_tb.v new file mode 100755 index 00000000..c1925511 --- /dev/null +++ b/adi_library/jesd204/tb/jesd204_frame_mark_tb.v @@ -0,0 +1,39 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module jesd204_frame_mark_tb; + + parameter VCD_FILE = "jesd204_frame_mark_tb.vcd"; + `define TIMEOUT 1000000 + `include "tb_base.v" + + localparam DATA_PATH_WIDTH = 8; + + wire [9:0] cfg_octets_per_multiframe = 23; + wire [7:0] cfg_beats_per_multiframe = 2; + wire [7:0] cfg_octets_per_frame = 5; + wire [DATA_PATH_WIDTH-1:0] sof; + wire [DATA_PATH_WIDTH-1:0] somf; + wire [DATA_PATH_WIDTH-1:0] eof; + wire [DATA_PATH_WIDTH-1:0] eomf; + + jesd204_frame_mark #( + .DATA_PATH_WIDTH (DATA_PATH_WIDTH) + ) frame_mark ( + .clk (clk), + .reset (reset), + .cfg_octets_per_multiframe (cfg_octets_per_multiframe), + .cfg_beats_per_multiframe (cfg_beats_per_multiframe), + .cfg_octets_per_frame (cfg_octets_per_frame), + .sof (sof), + .eof (eof), + .somf (somf), + .eomf (eomf)); + +endmodule diff --git a/adi_library/jesd204/tb/loopback_64b_tb b/adi_library/jesd204/tb/loopback_64b_tb new file mode 100755 index 00000000..57044ef4 --- /dev/null +++ b/adi_library/jesd204/tb/loopback_64b_tb @@ -0,0 +1,16 @@ +#!/bin/bash + +SOURCE="loopback_64b_tb.v" +SOURCE+=" ../jesd204_common/jesd204_lmfc.v ../jesd204_common/jesd204_scrambler.v ../jesd204_common/jesd204_eof_generator.v" +SOURCE+=" ../jesd204_common/pipeline_stage.v" +SOURCE+=" ../jesd204_common/jesd204_scrambler_64b.v ../jesd204_common/jesd204_crc12.v" +SOURCE+=" ../jesd204_rx/jesd204_rx.v ../jesd204_rx/jesd204_rx_ctrl_64b.v ../jesd204_rx/jesd204_rx_lane_64b.v" +SOURCE+=" ../jesd204_rx/elastic_buffer.v ../jesd204_rx/error_monitor.v ../jesd204_rx/jesd204_rx_header.v" +SOURCE+=" ../jesd204_rx_static_config/jesd204_rx_static_config.v" +SOURCE+=" ../jesd204_tx/jesd204_tx.v ../jesd204_tx/jesd204_tx_lane_64b.v ../jesd204_tx/jesd204_tx_header.v" +SOURCE+=" ../jesd204_tx_static_config/jesd204_tx_static_config.v" +SOURCE+=" ../jesd204_tx_static_config/jesd204_ilas_cfg_static.v" +SOURCE+=" ../../util_cdc/sync_bits.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/jesd204/tb/loopback_64b_tb.v b/adi_library/jesd204/tb/loopback_64b_tb.v new file mode 100644 index 00000000..7c845cfb --- /dev/null +++ b/adi_library/jesd204/tb/loopback_64b_tb.v @@ -0,0 +1,384 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module loopback_64b_tb; + parameter VCD_FILE = "loopback_64b_tb.vcd"; + parameter NUM_LANES = 4; + parameter NUM_LINKS = 1; + parameter OCTETS_PER_FRAME = 8; + parameter FRAMES_PER_MULTIFRAME = 32; + parameter ENABLE_SCRAMBLER = 1; + parameter BUFFER_EARLY_RELEASE = 0; + parameter LANE_DELAY = 1; + parameter DATA_PATH_WIDTH = 8; + + localparam BEATS_PER_MULTIFRAME = OCTETS_PER_FRAME * FRAMES_PER_MULTIFRAME / 8; + localparam TX_LATENCY = 3 + i_tx.NUM_OUTPUT_PIPELINE; + localparam RX_LATENCY = 3; + localparam BASE_LATENCY = TX_LATENCY + RX_LATENCY; + + `include "tb_base.v" + + reg [5:0] tx_counter = 'h00; + reg [5:0] rx_counter = 'h00; + wire tx_ready; + wire rx_valid; + wire [NUM_LANES*64-1:0] rx_data; + reg data_mismatch = 1'b1; + + always @(posedge clk) begin + if (tx_ready == 1'b1) begin + tx_counter <= tx_counter + 1'b1; + end + end + + reg rx_valid_d1 = 1'b0; + + always @(posedge clk) begin + rx_valid_d1 <= rx_valid; + if (rx_valid == 1'b1) begin + if (rx_valid_d1 == 1'b0) begin + // Resynchronize counter to the first received data + rx_counter <= rx_data[7:2] + 1'b1; + end else begin + rx_counter <= rx_counter + 1'b1; + end + end + end + + wire [63:0] tx_data = + {{tx_counter,2'h0,tx_counter,2'h1,tx_counter,2'h2,tx_counter,2'h3}, + {tx_counter,2'h3,tx_counter,2'h2,tx_counter,2'h1,tx_counter,2'h0}}; + wire [63:0] rx_ref_data = + {{rx_counter,2'h0,rx_counter,2'h1,rx_counter,2'h2,rx_counter,2'h3}, + {rx_counter,2'h3,rx_counter,2'h2,rx_counter,2'h1,rx_counter,2'h0}}; + + wire [NUM_LANES*64-1:0] phy_data_out; + wire [NUM_LANES*2-1:0] phy_header_out; + wire [NUM_LANES*64-1:0] phy_data_in; + wire [NUM_LANES*2-1:0] phy_header_in; + + reg [NUM_LANES-1:0] phy_block_sync = {NUM_LANES{1'b1}}; + + reg [5:0] sysref_counter = 'h00; + reg sysref_rx = 1'b0; + reg sysref_tx = 1'b0; + + always @(posedge clk) begin + if (sysref_counter == 'h2f) + sysref_rx <= ~sysref_rx; + sysref_counter <= sysref_counter + 1'b1; + sysref_tx <= sysref_rx; + end + + localparam MAX_LANE_DELAY = LANE_DELAY + NUM_LANES; + + reg [10:0] phy_delay_fifo_wr; + reg [(2+64)*NUM_LANES-1:0] phy_delay_fifo[0:MAX_LANE_DELAY-1]; + + always @(posedge clk) begin + phy_delay_fifo[phy_delay_fifo_wr] <= {phy_header_out,phy_data_out}; + + if (reset == 1'b1 || phy_delay_fifo_wr == MAX_LANE_DELAY-1) begin + phy_delay_fifo_wr <= 'h00; + end else begin + phy_delay_fifo_wr <= phy_delay_fifo_wr + 1'b1; + end + end + + genvar i; + generate for (i = 0; i < NUM_LANES; i = i + 1) begin + localparam OFF = MAX_LANE_DELAY - (i + LANE_DELAY); + + assign phy_data_in[64*i+63:64*i] = + phy_delay_fifo[(phy_delay_fifo_wr + OFF) % MAX_LANE_DELAY][64*i+63:64*i]; + + assign phy_header_in[2*i+1:2*i] = + phy_delay_fifo[(phy_delay_fifo_wr + OFF) % MAX_LANE_DELAY][2*i+1+NUM_LANES*64 : 2*i+64*NUM_LANES]; + + end endgenerate + + wire [NUM_LANES-1:0] tx_cfg_lanes_disable; + wire [NUM_LINKS-1:0] tx_cfg_links_disable; + wire [9:0] tx_cfg_octets_per_multiframe; + wire [7:0] tx_cfg_octets_per_frame; + wire [7:0] tx_device_cfg_lmfc_offset; + wire [9:0] tx_device_cfg_octets_per_multiframe; + wire [7:0] tx_device_cfg_octets_per_frame; + wire [7:0] tx_device_cfg_beats_per_multiframe; + wire tx_device_cfg_sysref_disable; + wire tx_device_cfg_sysref_oneshot; + wire tx_cfg_continuous_cgs; + wire tx_cfg_continuous_ilas; + wire tx_cfg_skip_ilas; + wire [7:0] tx_cfg_mframes_per_ilas; + wire tx_cfg_disable_char_replacement; + wire tx_cfg_disable_scrambler; + + wire tx_ilas_config_rd; + wire [1:0] tx_ilas_config_addr; + wire [DATA_PATH_WIDTH*8*NUM_LANES-1:0] tx_ilas_config_data; + + jesd204_tx_static_config #( + .NUM_LANES(NUM_LANES), + .NUM_LINKS(NUM_LINKS), + .OCTETS_PER_FRAME(OCTETS_PER_FRAME), + .FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME), + .SCR(ENABLE_SCRAMBLER), + .LINK_MODE(2), + .DATA_PATH_WIDTH(DATA_PATH_WIDTH), + .TPL_DATA_PATH_WIDTH(DATA_PATH_WIDTH) + ) i_tx_cfg ( + .clk(clk), + + .cfg_lanes_disable(tx_cfg_lanes_disable), + .cfg_links_disable(tx_cfg_links_disable), + .cfg_octets_per_multiframe(tx_cfg_octets_per_multiframe), + .cfg_octets_per_frame(tx_cfg_octets_per_frame), + .cfg_continuous_cgs(tx_cfg_continuous_cgs), + .cfg_continuous_ilas(tx_cfg_continuous_ilas), + .cfg_skip_ilas(tx_cfg_skip_ilas), + .cfg_mframes_per_ilas(tx_cfg_mframes_per_ilas), + .cfg_disable_char_replacement(tx_cfg_disable_char_replacement), + .cfg_disable_scrambler(tx_cfg_disable_scrambler), + + .device_cfg_octets_per_multiframe(tx_device_cfg_octets_per_multiframe), + .device_cfg_octets_per_frame(tx_device_cfg_octets_per_frame), + .device_cfg_beats_per_multiframe(tx_device_cfg_beats_per_multiframe), + .device_cfg_lmfc_offset(tx_device_cfg_lmfc_offset), + .device_cfg_sysref_disable(tx_device_cfg_sysref_disable), + .device_cfg_sysref_oneshot(tx_device_cfg_sysref_oneshot), + + .ilas_config_rd(tx_ilas_config_rd), + .ilas_config_addr(tx_ilas_config_addr), + .ilas_config_data(tx_ilas_config_data)); + + jesd204_tx #( + .NUM_LANES(NUM_LANES), + .NUM_LINKS(NUM_LINKS), + .LINK_MODE(2), + .DATA_PATH_WIDTH(DATA_PATH_WIDTH), + .TPL_DATA_PATH_WIDTH(DATA_PATH_WIDTH), + .ASYNC_CLK(0), + .ENABLE_CHAR_REPLACE(1) + ) i_tx ( + .clk(clk), + .reset(reset), + + .device_clk(clk), + .device_reset(reset), + + .phy_data(phy_data_out), + .phy_charisk(), + .phy_header(phy_header_out), + + .sysref(sysref_tx), + .lmfc_edge(), + .lmfc_clk(), + + .sync(), + + .tx_data({NUM_LANES{tx_data}}), + .tx_ready(tx_ready), + .tx_eof(), + .tx_sof(), + .tx_somf(), + .tx_eomf(), + .tx_valid(), + + .cfg_lanes_disable(tx_cfg_lanes_disable), + .cfg_links_disable(tx_cfg_links_disable), + .cfg_octets_per_multiframe(tx_cfg_octets_per_multiframe), + .cfg_octets_per_frame(tx_cfg_octets_per_frame), + .cfg_continuous_cgs(tx_cfg_continuous_cgs), + .cfg_continuous_ilas(tx_cfg_continuous_ilas), + .cfg_skip_ilas(tx_cfg_skip_ilas), + .cfg_mframes_per_ilas(tx_cfg_mframes_per_ilas), + .cfg_disable_char_replacement(tx_cfg_disable_char_replacement), + .cfg_disable_scrambler(tx_cfg_disable_scrambler), + + .device_cfg_octets_per_multiframe(tx_device_cfg_octets_per_multiframe), + .device_cfg_octets_per_frame(tx_device_cfg_octets_per_frame), + .device_cfg_beats_per_multiframe(tx_device_cfg_beats_per_multiframe), + .device_cfg_lmfc_offset(tx_device_cfg_lmfc_offset), + .device_cfg_sysref_disable(tx_device_cfg_sysref_disable), + .device_cfg_sysref_oneshot(tx_device_cfg_sysref_oneshot), + + .ilas_config_rd(tx_ilas_config_rd), + .ilas_config_addr(tx_ilas_config_addr), + .ilas_config_data(tx_ilas_config_data), + + .ctrl_manual_sync_request(1'b0), + + .device_event_sysref_edge(), + .device_event_sysref_alignment_error(), + + .status_sync(), + .status_state(), + + .status_synth_params0(), + .status_synth_params1(), + .status_synth_params2()); + + wire [NUM_LANES-1:0] rx_cfg_lanes_disable; + wire [NUM_LINKS-1:0] rx_cfg_links_disable; + wire [9:0] rx_cfg_octets_per_multiframe; + wire [7:0] rx_cfg_octets_per_frame; + wire [7:0] rx_device_cfg_lmfc_offset; + wire [9:0] rx_device_cfg_octets_per_multiframe; + wire [7:0] rx_device_cfg_octets_per_frame; + wire [7:0] rx_device_cfg_beats_per_multiframe; + wire rx_device_cfg_sysref_disable; + wire rx_device_cfg_sysref_oneshot; + wire rx_device_cfg_buffer_early_release; + wire [7:0] rx_device_cfg_buffer_delay; + wire rx_cfg_disable_scrambler; + wire rx_cfg_disable_char_replacement; + wire [NUM_LANES*3-1:0] status_lane_emb_state; + wire [7:0] rx_cfg_frame_align_err_threshold; + + jesd204_rx_static_config #( + .NUM_LANES(NUM_LANES), + .OCTETS_PER_FRAME(OCTETS_PER_FRAME), + .FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME), + .SCR(ENABLE_SCRAMBLER), + .BUFFER_EARLY_RELEASE(BUFFER_EARLY_RELEASE), + .LINK_MODE(2) + ) i_rx_cfg ( + .clk(clk), + + .cfg_lanes_disable(rx_cfg_lanes_disable), + .cfg_links_disable(rx_cfg_links_disable), + .cfg_octets_per_multiframe(rx_cfg_octets_per_multiframe), + .cfg_octets_per_frame(rx_cfg_octets_per_frame), + .cfg_disable_scrambler(rx_cfg_disable_scrambler), + .cfg_disable_char_replacement(rx_cfg_disable_char_replacement), + .cfg_frame_align_err_threshold(rx_cfg_frame_align_err_threshold), + + .device_cfg_octets_per_multiframe(rx_device_cfg_octets_per_multiframe), + .device_cfg_octets_per_frame(rx_device_cfg_octets_per_frame), + .device_cfg_beats_per_multiframe(rx_device_cfg_beats_per_multiframe), + .device_cfg_lmfc_offset(rx_device_cfg_lmfc_offset), + .device_cfg_sysref_disable(rx_device_cfg_sysref_disable), + .device_cfg_sysref_oneshot(rx_device_cfg_sysref_oneshot), + .device_cfg_buffer_early_release(rx_device_cfg_buffer_early_release), + .device_cfg_buffer_delay(rx_device_cfg_buffer_delay)); + + jesd204_rx #( + .NUM_LANES(NUM_LANES), + .LINK_MODE(2), + .DATA_PATH_WIDTH(DATA_PATH_WIDTH), + .TPL_DATA_PATH_WIDTH(DATA_PATH_WIDTH), + .ASYNC_CLK(0) + ) i_rx ( + .clk(clk), + .reset(reset), + + .device_clk(clk), + .device_reset(reset), + + .phy_data(phy_data_in), + .phy_header(phy_header_in), + .phy_charisk({NUM_LANES*DATA_PATH_WIDTH{1'b0}}), + .phy_notintable({NUM_LANES*DATA_PATH_WIDTH{1'b0}}), + .phy_disperr({NUM_LANES*DATA_PATH_WIDTH{1'b0}}), + .phy_block_sync(phy_block_sync), + + .sysref(sysref_rx), + .lmfc_edge(), + .lmfc_clk(), + + .device_event_sysref_alignment_error(), + .device_event_sysref_edge(), + .event_frame_alignment_error(), + .event_unexpected_lane_state_error(), + + .sync(), + + .phy_en_char_align(), + + .rx_data(rx_data), + .rx_valid(rx_valid), + .rx_eof(), + .rx_sof(), + .rx_eomf(), + .rx_somf(), + + .cfg_lanes_disable(rx_cfg_lanes_disable), + .cfg_links_disable(rx_cfg_links_disable), + .cfg_octets_per_multiframe(rx_cfg_octets_per_multiframe), + .cfg_octets_per_frame(rx_cfg_octets_per_frame), + .cfg_disable_char_replacement(rx_cfg_disable_char_replacement), + .cfg_disable_scrambler(rx_cfg_disable_scrambler), + + .device_cfg_octets_per_multiframe(rx_device_cfg_octets_per_multiframe), + .device_cfg_octets_per_frame(rx_device_cfg_octets_per_frame), + .device_cfg_beats_per_multiframe(rx_device_cfg_beats_per_multiframe), + .device_cfg_lmfc_offset(rx_device_cfg_lmfc_offset), + .device_cfg_sysref_disable(rx_device_cfg_sysref_disable), + .device_cfg_sysref_oneshot(rx_device_cfg_sysref_oneshot), + .device_cfg_buffer_early_release(rx_device_cfg_buffer_early_release), + .device_cfg_buffer_delay(rx_device_cfg_buffer_delay), + + .ctrl_err_statistics_reset(1'b0), + .ctrl_err_statistics_mask(7'b0), + + .cfg_frame_align_err_threshold(rx_cfg_frame_align_err_threshold), + + .status_err_statistics_cnt(), + + .ilas_config_valid(), + .ilas_config_addr(), + .ilas_config_data(), + + .status_ctrl_state(), + .status_lane_cgs_state(), + + .status_lane_ifs_ready(), + .status_lane_latency(), + .status_lane_emb_state(status_lane_emb_state), + .status_lane_frame_align_err_cnt(), + + .status_synth_params0(), + .status_synth_params1(), + .status_synth_params2()); + + integer ii; + reg rx_status_mismatch = 1'b0; + initial begin + @(posedge rx_valid); + for (ii=0;ii 'h20) begin + char_is_cgs <= 4'b0000; + end + end + + jesd204_rx_cgs i_rx_cgs ( + .clk(clk), + .reset(reset), + .char_is_cgs(char_is_cgs), + .char_is_error(char_is_error), + + .ready(ready)); + + reg lost_sync = 1'b0; + + always @(posedge clk) begin + ready_prev <= ready; + if (ready_prev == 1'b1 && ready == 1'b0) begin + lost_sync <= 1'b1; + end + failed <= lost_sync | ~ready; + end + +endmodule diff --git a/adi_library/jesd204/tb/rx_ctrl_tb b/adi_library/jesd204/tb/rx_ctrl_tb new file mode 100755 index 00000000..ad96e3ed --- /dev/null +++ b/adi_library/jesd204/tb/rx_ctrl_tb @@ -0,0 +1,7 @@ +#!/bin/bash + +SOURCE="rx_ctrl_tb.v" +SOURCE+=" ../jesd204_rx/jesd204_rx_ctrl.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/jesd204/tb/rx_ctrl_tb.v b/adi_library/jesd204/tb/rx_ctrl_tb.v new file mode 100644 index 00000000..d8546ec3 --- /dev/null +++ b/adi_library/jesd204/tb/rx_ctrl_tb.v @@ -0,0 +1,75 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module rx_ctrl_tb; + parameter VCD_FILE = "rx_ctrl_tb.vcd"; + + `include "tb_base.v" + + integer phy_reset_counter = 'h00; + integer align_counter = 'h00; + integer cgs_counter = 'h00; + + reg phy_ready = 1'b0; + reg aligned = 1'b0; + reg cgs_ready = 1'b0; + + wire en_align; + wire cgs_reset; + + always @(posedge clk) begin + if (reset == 1'b1) begin + phy_reset_counter <= 'h00; + phy_ready <= 1'b0; + end else begin + if (phy_reset_counter == 'h7) begin + phy_ready <= 1'b1; + end else begin + phy_reset_counter <= phy_reset_counter + 1'b1; + end + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + aligned <= 1'b0; + align_counter <= 'h00; + end else if (phy_ready == 1'b1) begin + if (en_align == 1'b1) begin + if (align_counter == 'h20) begin + aligned <= 1'b1; + end else begin + align_counter <= align_counter + 1; + end + end + end + end + + always @(posedge clk or posedge cgs_reset) begin + if (cgs_reset == 1'b1) begin + cgs_counter <= 'h00; + cgs_ready <= 1'b0; + end else begin + if (cgs_counter == 'h20) begin + cgs_ready <= 1'b1; + end else begin + cgs_counter <= cgs_counter + 1; + end + end + end + + jesd204_rx_ctrl i_rx_ctrl ( + .clk(clk), + .reset(reset), + .phy_ready(phy_ready), + .phy_en_char_align(en_align), + .cgs_reset(cgs_reset), + .cgs_ready(cgs_ready)); + +endmodule diff --git a/adi_library/jesd204/tb/rx_lane_tb b/adi_library/jesd204/tb/rx_lane_tb new file mode 100755 index 00000000..bba23062 --- /dev/null +++ b/adi_library/jesd204/tb/rx_lane_tb @@ -0,0 +1,10 @@ +#!/bin/bash + +SOURCE="rx_lane_tb.v " +SOURCE+=" ../jesd204_rx/jesd204_rx_lane.v ../jesd204_rx/jesd204_rx_cgs.v ../jesd204_rx/elastic_buffer.v" +SOURCE+=" ../jesd204_rx/align_mux.v ../jesd204_rx/jesd204_ilas_monitor.v" +SOURCE+=" ../jesd204_common/jesd204_scrambler.v" +SOURCE+=" ../jesd204_common/pipeline_stage.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/jesd204/tb/rx_lane_tb.v b/adi_library/jesd204/tb/rx_lane_tb.v new file mode 100644 index 00000000..e3d5d0c6 --- /dev/null +++ b/adi_library/jesd204/tb/rx_lane_tb.v @@ -0,0 +1,118 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module rx_lane_tb; + parameter VCD_FILE = "rx_lane_tb.vcd"; + + `include "tb_base.v" + + reg [31:0] data = {4{{3'd5,5'd28}}}; + reg [3:0] disperr = 4'b0000; + reg [3:0] notintable = 4'b0000; + reg [3:0] charisk = 4'b1111; + + wire ilas_config_valid; + wire [1:0] ilas_config_addr; + wire [4*8-1:0] ilas_config_data; + wire [31:0] status_err_statistics_cnt; + + wire [4*8-1:0] rx_data; + + wire [1:0] status_cgs_state; + wire status_ifs_ready; + wire [2:0] status_frame_align; + + integer counter = 'h00; + wire [31:0] counter2 = (counter - 'h20) * 4; + + always @(posedge clk) begin + if ($urandom % 400 == 0) + disperr <= 4'b1111; + else if ($urandom % 400 == 1) + disperr <= 4'b0001; + else if ($urandom % 400 == 2) + disperr <= 4'b0011; + else if ($urandom % 400 == 3) + disperr <= 4'b0111; + else + disperr <= 4'b0000; + end + + always @(posedge clk) begin + if ($random % 500 == 0) + notintable <= 4'b1111; + else + notintable <= 4'b0000; + end + + always @(posedge clk) begin + counter <= counter + 1; + if (counter == 'h20) begin + charisk <= 'h0001; + data[31:8] <= {{24'h020100}}; + end else if (counter == 'h21) begin + charisk <= 'h0000; + data[31:0] <= {{32'h06050403}}; + end else if (counter > 'h21) begin + data <= (counter2 + 'h2) << 24 | + (counter2 + 'h1) << 16 | + (counter2 + 'h0) << 8 | + (counter2 - 'h1); + charisk <= 4'b0000; + end + end + + reg buffer_release_n = 1'b0; + wire buffer_ready_n; + + always @(posedge clk) begin + buffer_release_n <= buffer_ready_n; + end + + jesd204_rx_lane i_rx_lane ( + .clk(clk), + .reset(1'b0), + + .device_clk(clk), + .device_reset(1'b0), + + .phy_data(data), + .phy_charisk(charisk), + .phy_disperr(disperr), + .phy_notintable(notintable), + + .cgs_reset(reset), + .cgs_ready(), + + .ifs_reset(1'b0), + + .rx_data(rx_data), + + .buffer_release_n(buffer_release_n), + .buffer_ready_n(buffer_ready_n), + + .cfg_octets_per_multiframe(10'd31), + .cfg_octets_per_frame(8'd3), + .cfg_disable_char_replacement(1'b0), + .cfg_disable_scrambler(1'b0), + + .ilas_config_valid(ilas_config_valid), + .ilas_config_addr(ilas_config_addr), + .ilas_config_data(ilas_config_data), + + .err_statistics_reset(1'b0), + .ctrl_err_statistics_mask(3'h7), + .status_err_statistics_cnt(status_err_statistics_cnt), + + .status_cgs_state(status_cgs_state), + .status_ifs_ready(status_ifs_ready), + .status_frame_align(status_frame_align), + .status_frame_align_err_cnt()); + +endmodule diff --git a/adi_library/jesd204/tb/rx_tb b/adi_library/jesd204/tb/rx_tb new file mode 100755 index 00000000..005a6ba7 --- /dev/null +++ b/adi_library/jesd204/tb/rx_tb @@ -0,0 +1,12 @@ +#!/bin/bash + +SOURCE="rx_tb.v" +SOURCE+=" ../jesd204_common/jesd204_lmfc.v ../jesd204_common/jesd204_scrambler.v ../jesd204_common/jesd204_eof_generator.v" +SOURCE+=" ../jesd204_common/pipeline_stage.v" +SOURCE+=" ../jesd204_rx_static_config/jesd204_rx_static_config.v " +SOURCE+=" ../jesd204_rx/jesd204_rx.v ../jesd204_rx/jesd204_rx_lane.v ../jesd204_rx/jesd204_lane_latency_monitor.v" +SOURCE+=" ../jesd204_rx/jesd204_ilas_monitor.v ../jesd204_rx/align_mux.v ../jesd204_rx/jesd204_rx_cgs.v" +SOURCE+=" ../jesd204_rx/jesd204_rx_ctrl.v ../jesd204_rx/elastic_buffer.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/jesd204/tb/rx_tb.v b/adi_library/jesd204/tb/rx_tb.v new file mode 100644 index 00000000..7dba6cc8 --- /dev/null +++ b/adi_library/jesd204/tb/rx_tb.v @@ -0,0 +1,234 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module rx_tb; + parameter VCD_FILE = "rx_tb.vcd"; + parameter NUM_LANES = 1; + parameter NUM_LINKS = 1; + parameter OCTETS_PER_FRAME = 8; + parameter FRAMES_PER_MULTIFRAME = 32; + + `include "tb_base.v" + + integer phy_reset_counter = 'h00; + integer align_counter = 'h00; + + reg phy_ready = 1'b0; + reg aligned = 1'b0; + + wire en_align; + + always @(posedge clk) begin + if (reset == 1'b1) begin + phy_reset_counter <= 'h00; + phy_ready <= 1'b0; + end else begin + if (phy_reset_counter == 'h40) begin + phy_ready <= 1'b1; + end else begin + phy_reset_counter <= phy_reset_counter + 1'b1; + end + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + aligned <= 1'b0; + align_counter <= 'h00; + end else if (phy_ready == 1'b1) begin + if (en_align == 1'b1) begin + if (align_counter == 'h20) begin + aligned <= 1'b1; + end else begin + align_counter <= align_counter + 1; + end + end + end + end + + localparam KCHAR_ILAS_START = {3'd0,5'd28}; + localparam KCHAR_LANE_ALIGN = {3'd3,5'd28}; + localparam KCHAR_ILAS_CONFIG = {3'd4,5'd28}; + localparam KCHAR_CGS = {3'd5,5'd28}; + localparam KCHAR_FRAME_ALIGN = {3'd7,5'd28}; + + reg [31:0] data = KCHAR_CGS; + reg [3:0] charisk = 4'b1111; + reg [3:0] disperr = 4'b0000; + reg [3:0] notintable = 4'b0000; + wire [NUM_LINKS-1:0] sync; + + integer counter = 'h00; + wire [31:0] counter2 = (counter - 'h10) * 4; + + always @(posedge clk) begin + if ( &sync == 1'b0 ) begin + counter <= 'h00; + charisk <= 4'b1111; + data <= {KCHAR_CGS,KCHAR_CGS,KCHAR_CGS,KCHAR_CGS}; + end else begin + counter <= counter + 1; + if (counter >= 'h8 && counter < 'h28) begin + if (counter % 'h8 == 'h0) begin + if (counter != 'h10) begin + data <= {24'h00,KCHAR_ILAS_START}; + charisk <= 4'b0001; + end else begin + data <= {16'hffaa,KCHAR_ILAS_CONFIG,KCHAR_ILAS_START}; + charisk <= 4'b0011; + end + end else if (counter % 'h8 == 'h7) begin + data <= {KCHAR_LANE_ALIGN,24'h00}; + charisk <= 4'b1000; + end else begin + data <= {32'h00}; + charisk <= 4'b0000; + end + end else if (counter > 'h10) begin + data <= (counter2 + 'h2) << 24 | + (counter2 + 'h1) << 16 | + (counter2 + 'h0) << 8 | + (counter2 - 'h1); + charisk <= 4'b0000; + end + end + end + + wire [NUM_LANES-1:0] cfg_lanes_disable; + wire [NUM_LINKS-1:0] cfg_links_disable; + wire [9:0] cfg_octets_per_multiframe; + wire [7:0] cfg_octets_per_frame; + wire [7:0] device_cfg_lmfc_offset; + wire [9:0] device_cfg_octets_per_multiframe; + wire [7:0] device_cfg_octets_per_frame; + wire [7:0] device_cfg_beats_per_multiframe; + wire device_cfg_sysref_disable; + wire device_cfg_sysref_oneshot; + wire device_cfg_buffer_early_release; + wire [7:0] device_cfg_buffer_delay; + wire cfg_disable_scrambler; + wire cfg_disable_char_replacement; + wire [7:0] cfg_frame_align_err_threshold; + + always @(posedge clk) begin + if ($urandom % 400 == 0) + disperr <= 4'b1111; + else if ($urandom % 400 == 1) + disperr <= 4'b0001; + else if ($urandom % 400 == 2) + disperr <= 4'b0011; + else if ($urandom % 400 == 3) + disperr <= 4'b0111; + else + disperr <= 4'b0000; + end + wire [NUM_LANES*32-1:0] status_err_statistics_cnt; + + jesd204_rx_static_config #( + .NUM_LANES(NUM_LANES), + .NUM_LINKS(NUM_LINKS), + .OCTETS_PER_FRAME(OCTETS_PER_FRAME), + .FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME) + ) i_cfg ( + .clk(clk), + + .cfg_lanes_disable(cfg_lanes_disable), + .cfg_links_disable(cfg_links_disable), + .cfg_octets_per_multiframe(cfg_octets_per_multiframe), + .cfg_octets_per_frame(cfg_octets_per_frame), + .cfg_disable_scrambler(cfg_disable_scrambler), + .cfg_disable_char_replacement(cfg_disable_char_replacement), + .cfg_frame_align_err_threshold(cfg_frame_align_err_threshold), + + .device_cfg_octets_per_multiframe(device_cfg_octets_per_multiframe), + .device_cfg_octets_per_frame(device_cfg_octets_per_frame), + .device_cfg_beats_per_multiframe(device_cfg_beats_per_multiframe), + .device_cfg_lmfc_offset(device_cfg_lmfc_offset), + .device_cfg_sysref_disable(device_cfg_sysref_disable), + .device_cfg_sysref_oneshot(device_cfg_sysref_oneshot), + .device_cfg_buffer_early_release(device_cfg_buffer_early_release), + .device_cfg_buffer_delay(device_cfg_buffer_delay)); + + jesd204_rx #( + .NUM_LANES(NUM_LANES), + .NUM_LINKS(NUM_LINKS) + ) i_rx ( + .clk(clk), + .reset(reset), + + .device_clk(clk), + .device_reset(reset), + + .phy_data({NUM_LANES{data}}), + .phy_header({2*NUM_LANES{1'b0}}), + .phy_charisk({NUM_LANES{charisk}}), + .phy_notintable({NUM_LANES{notintable}}), + .phy_disperr({NUM_LANES{disperr}}), + .phy_block_sync({NUM_LANES{1'b0}}), + + .sysref(sysref), + .lmfc_edge(), + .lmfc_clk(), + + .device_event_sysref_alignment_error(), + .device_event_sysref_edge(), + .event_frame_alignment_error(), + .event_unexpected_lane_state_error(), + + .sync(sync), + + .phy_en_char_align(en_align), + + .rx_data(), + .rx_valid(), + .rx_eof(), + .rx_sof(), + .rx_eomf(), + .rx_somf(), + + .cfg_lanes_disable(cfg_lanes_disable), + .cfg_links_disable(cfg_links_disable), + .cfg_octets_per_multiframe(cfg_octets_per_multiframe), + .cfg_octets_per_frame(cfg_octets_per_frame), + .cfg_disable_char_replacement(cfg_disable_char_replacement), + .cfg_disable_scrambler(cfg_disable_scrambler), + + .device_cfg_octets_per_multiframe(device_cfg_octets_per_multiframe), + .device_cfg_octets_per_frame(device_cfg_octets_per_frame), + .device_cfg_beats_per_multiframe(device_cfg_beats_per_multiframe), + .device_cfg_lmfc_offset(device_cfg_lmfc_offset), + .device_cfg_sysref_disable(device_cfg_sysref_disable), + .device_cfg_sysref_oneshot(device_cfg_sysref_oneshot), + .device_cfg_buffer_early_release(device_cfg_buffer_early_release), + .device_cfg_buffer_delay(device_cfg_buffer_delay), + + .ctrl_err_statistics_reset(1'b0), + .ctrl_err_statistics_mask(7'h7), + + .cfg_frame_align_err_threshold(cfg_frame_align_err_threshold), + + .status_err_statistics_cnt(status_err_statistics_cnt), + + .ilas_config_valid(), + .ilas_config_addr(), + .ilas_config_data(), + + .status_ctrl_state(), + .status_lane_cgs_state(), + + .status_lane_ifs_ready(), + .status_lane_latency(), + .status_lane_emb_state(), + .status_lane_frame_align_err_cnt(), + + .status_synth_params0(), + .status_synth_params1(), + .status_synth_params2()); + +endmodule diff --git a/adi_library/jesd204/tb/scrambler_64b_input.txt b/adi_library/jesd204/tb/scrambler_64b_input.txt new file mode 100644 index 00000000..98ea4dc2 --- /dev/null +++ b/adi_library/jesd204/tb/scrambler_64b_input.txt @@ -0,0 +1,994 @@ +e949a63d63222000 +f44cb1c66f152c3e +fc37ba9a78bb369f +ffd7bf617e9e3d8f +fe9ebf617fd73fff +f8bbba9a7c373d8f +ef15b1c6744c369f +e322a63d69492c3e +d6b699c25cdd2000 +cbb38e3950ea13c1 +c3c8856547440960 +c028809e41610270 +c161809e40280001 +c744856543c80270 +d0ea8e394bb30960 +dcdd99c256b613c1 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+653346384526a865 +ecb14d78c9c07281 +011d471524a8890f +845132665608c185 +2cac39d0e77c1506 diff --git a/adi_library/jesd204/tb/scrambler_64b_tb b/adi_library/jesd204/tb/scrambler_64b_tb new file mode 100755 index 00000000..202e5fae --- /dev/null +++ b/adi_library/jesd204/tb/scrambler_64b_tb @@ -0,0 +1,7 @@ +#!/bin/bash + +SOURCE="scrambler_64b_tb.v" +SOURCE+=" ../jesd204_common/jesd204_scrambler_64b.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/jesd204/tb/scrambler_64b_tb.v b/adi_library/jesd204/tb/scrambler_64b_tb.v new file mode 100644 index 00000000..8310a091 --- /dev/null +++ b/adi_library/jesd204/tb/scrambler_64b_tb.v @@ -0,0 +1,104 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module scrambler_64b_tb; + parameter VCD_FILE = "scrambler_64b_tb.vcd"; + + `include "tb_base.v" + reg failed_t1 = 1'b0; + reg failed_t2 = 1'b0; + + // Test scrambler against descrambler + // + // Descrambled data should match the input of the scrambler. + reg [63:0] data_in = 'h0; + reg [63:0] data_out_expected; + wire [63:0] data_scrambled; + wire [63:0] data_out; + + always @(posedge clk) begin + if (reset == 1'b1) begin + data_in <= 'h0001020304050607; + end else begin + data_in <= data_in + {8{8'h08}}; + end + end + + jesd204_scrambler_64b #( + .DESCRAMBLE(0) + ) i_scrambler ( + .clk(clk), + .reset(reset), + .enable(1'b1), + .data_in(data_in), + .data_out(data_scrambled)); + + jesd204_scrambler_64b #( + .DESCRAMBLE(1) + ) i_descrambler ( + .clk(clk), + .reset(reset), + .enable(1'b1), + .data_in(data_scrambled), + .data_out(data_out)); + + always @(posedge clk) begin + if (data_in != data_out && failed_t1 == 1'b0) begin + failed_t1 <= 1'b1; + end + end + + // Test descrambler against reference data + // + // Check if descrambler can synchronize and a stream captured from + // a scrambler output. The descrambled data stream should match the input of + // the scrambler. + reg [63:0] descrambler_data_in = 'h0; + reg [63:0] data_ref = 'h0; + wire[63:0] descrambler_data_out; + + integer i; + reg [63:0] scrambler_64b_input [0:993]; + reg [63:0] scrambler_64b_output [0:993]; + reg t2_enable = 1'b0; + + initial begin + $readmemh("scrambler_64b_input.txt", scrambler_64b_input); // Input to a scrambler + $readmemh("scrambler_64b_output.txt", scrambler_64b_output); // Output of a scrambler + @(negedge reset); + @(posedge clk); + for (i=0;i<994;i=i+1) begin + @(posedge clk); + descrambler_data_in <= scrambler_64b_output[i]; + data_ref <= scrambler_64b_input[i]; + if (i==1) t2_enable <= 1'b1; + if (i==993) t2_enable <= 1'b0; + end + end + + jesd204_scrambler_64b #( + .DESCRAMBLE(1) + ) i_descrambler2 ( + .clk(clk), + .reset(reset), + .enable(1'b1), + .data_in(descrambler_data_in), + .data_out(descrambler_data_out)); + + always @(posedge clk) begin + if (data_ref != descrambler_data_out && failed_t2 == 1'b0 && t2_enable) begin + failed_t2 <= 1'b1; + end + end + + always @(posedge clk) begin + failed <= failed_t1 || failed_t2; + end + +endmodule diff --git a/adi_library/jesd204/tb/scrambler_tb b/adi_library/jesd204/tb/scrambler_tb new file mode 100755 index 00000000..c9d8be7c --- /dev/null +++ b/adi_library/jesd204/tb/scrambler_tb @@ -0,0 +1,7 @@ +#!/bin/bash + +SOURCE="scrambler_tb.v" +SOURCE+=" ../jesd204_common/jesd204_scrambler.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/jesd204/tb/scrambler_tb.v b/adi_library/jesd204/tb/scrambler_tb.v new file mode 100644 index 00000000..a46bfdb4 --- /dev/null +++ b/adi_library/jesd204/tb/scrambler_tb.v @@ -0,0 +1,52 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module scrambler_tb; + parameter VCD_FILE = "scrambler_tb.vcd"; + + `include "tb_base.v" + + reg [31:0] data_in; + reg [31:0] data_out_expected; + wire [31:0] data_scrambled; + wire [31:0] data_out; + + always @(posedge clk) begin + if (reset == 1'b1) begin + data_in <= 'h03020100; + end else begin + data_in <= data_in + {4{8'h04}}; + end + end + + jesd204_scrambler #( + .DESCRAMBLE(0) + ) i_scrambler ( + .clk(clk), + .reset(reset), + .enable(1'b1), + .data_in(data_in), + .data_out(data_scrambled)); + + jesd204_scrambler #( + .DESCRAMBLE(1) + ) i_descrambler ( + .clk(clk), + .reset(reset), + .enable(1'b1), + .data_in(data_scrambled), + .data_out(data_out)); + + always @(posedge clk) begin + if (data_in != data_out && failed == 1'b0) begin + failed <= 1'b1; + end + end + +endmodule diff --git a/adi_library/jesd204/tb/soft_pcs_8b10b_sequence_tb b/adi_library/jesd204/tb/soft_pcs_8b10b_sequence_tb new file mode 100755 index 00000000..dca05278 --- /dev/null +++ b/adi_library/jesd204/tb/soft_pcs_8b10b_sequence_tb @@ -0,0 +1,8 @@ +#!/bin/bash + +SOURCE="soft_pcs_8b10b_sequence_tb.v" +SOURCE+=" ../jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v" +SOURCE+=" ../jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/jesd204/tb/soft_pcs_8b10b_sequence_tb.v b/adi_library/jesd204/tb/soft_pcs_8b10b_sequence_tb.v new file mode 100644 index 00000000..5a1ade87 --- /dev/null +++ b/adi_library/jesd204/tb/soft_pcs_8b10b_sequence_tb.v @@ -0,0 +1,95 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module soft_pcs_8b10b_sequence_tb; + parameter VCD_FILE = "soft_pcs_8b10b_sequence_tb.vcd"; + + `include "tb_base.v" + + // Send a random sequence of characters to the decoder and make sure the + // decoder produces the same character sequence and no disparity or + // not-in-table errors + + wire [9:0] raw_data; + + reg [7:0] encoder_char = 'h00; + reg encoder_charisk = 1'b0; + + wire [7:0] decoder_char; + wire decoder_charisk; + wire decoder_notintable; + wire decoder_disperr; + + reg encoder_disparity = 1'b0; + wire encoder_disparity_s; + reg decoder_disparity = 1'b0; + wire decoder_disparity_s; + + integer x; + + reg inject_enc_disparity_error = 1'b0; + +/* + always @(posedge clk) begin + if ({$random} % 256 == 0) begin + inject_enc_disparity_error <= 1'b1; + end else begin + inject_enc_disparity_error <= 1'b0; + end + end +*/ + + always @(posedge clk) begin + x = {$random} % (256 + 5); + if (x < 256) begin + encoder_char <= x & 8'hff; + encoder_charisk <= 1'b0; + end else begin + case (x - 256) + 0: encoder_char <= {3'd0,5'd28}; + 1: encoder_char <= {3'd3,5'd28}; + 2: encoder_char <= {3'd4,5'd28}; + 3: encoder_char <= {3'd5,5'd28}; + 4: encoder_char <= {3'd7,5'd28}; + endcase + encoder_charisk <= 1'b1; + end + encoder_disparity <= encoder_disparity_s ^ inject_enc_disparity_error; + decoder_disparity <= decoder_disparity_s; + end + + jesd204_8b10b_encoder i_enc ( + .in_char(encoder_char), + .in_charisk(encoder_charisk), + .out_char(raw_data), + + .in_disparity(encoder_disparity), + .out_disparity(encoder_disparity_s)); + + jesd204_8b10b_decoder i_dec ( + .in_char(raw_data), + .out_char(decoder_char), + .out_notintable(decoder_notintable), + .out_disperr(decoder_disperr), + .out_charisk(decoder_charisk), + + .in_disparity(decoder_disparity), + .out_disparity(decoder_disparity_s)); + + wire char_mismatch = encoder_char != decoder_char; + wire charisk_mismatch = encoder_charisk != decoder_charisk; + + always @(posedge clk) begin + if (char_mismatch == 1'b1 || charisk_mismatch == 1'b1 || + decoder_notintable == 1'b1 || decoder_disperr == 1'b1) begin + failed <= 1'b1; + end + end + +endmodule diff --git a/adi_library/jesd204/tb/soft_pcs_8b10b_table_tb b/adi_library/jesd204/tb/soft_pcs_8b10b_table_tb new file mode 100755 index 00000000..24345756 --- /dev/null +++ b/adi_library/jesd204/tb/soft_pcs_8b10b_table_tb @@ -0,0 +1,8 @@ +#!/bin/bash + +SOURCE="soft_pcs_8b10b_table_tb.v" +SOURCE+=" ../jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v" +SOURCE+=" ../jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/jesd204/tb/soft_pcs_8b10b_table_tb.v b/adi_library/jesd204/tb/soft_pcs_8b10b_table_tb.v new file mode 100644 index 00000000..6a1b1aa8 --- /dev/null +++ b/adi_library/jesd204/tb/soft_pcs_8b10b_table_tb.v @@ -0,0 +1,113 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2019, 2021, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module soft_pcs_8b10b_table_tb; + parameter VCD_FILE = "soft_pcs_8b10b_table_tb.vcd"; + + `include "tb_base.v" + + // Build a table of all valid 8b10b words using the encoder and then check + // for every possible 10-bit value that the decoder correctly reports the + // not-in-table flag + + reg [1023:0] valid_table = 'h00; + + reg [8:0] counter = 10'h00; + + reg [7:0] encoder_char = 8'h00; + reg encoder_charisk = 1'b0; + reg encoder_disparity = 1'b0; + wire [9:0] encoder_raw; + + wire [7:0] decoder_char; + wire decoder_notintable; + wire decoder_charisk; + reg [9:0] decoder_raw = 10'h00; + + reg build_k28 = 1'b0; + reg build_table = 1'b1; + + reg decoder_disparity = 1'b0; + wire decoder_disparity_s; + + always @(posedge clk) begin + counter <= counter + 1'b1; + + if (counter == 'h1ff) begin + build_k28 <= 1'b1; + end else if (counter == 'h9 && build_k28 == 1'b1) begin + build_table <= 1'b0; + end + end + + always @(*) begin + encoder_disparity <= counter[0]; + if (build_k28 == 1'b0) begin + encoder_char <= counter[8:1]; + encoder_charisk <= 1'b0; + end else begin + case (counter[8:1]) + 0: encoder_char <= {3'd0,5'd28}; + 1: encoder_char <= {3'd3,5'd28}; + 2: encoder_char <= {3'd4,5'd28}; + 3: encoder_char <= {3'd5,5'd28}; + 4: encoder_char <= {3'd7,5'd28}; + endcase + encoder_charisk <= 1'b1; + end + end + + jesd204_8b10b_encoder i_enc ( + .in_char(encoder_char), + .in_charisk(encoder_charisk), + .in_disparity(encoder_disparity), + .out_char(encoder_raw), + .out_disparity()); + + always @(posedge clk) begin + if (build_table == 1'b1) begin + valid_table[encoder_raw] <= 1'b1; + end + end + + always @(posedge clk) begin + if (build_table == 1'b0) begin + decoder_disparity <= ~decoder_disparity; + if (decoder_disparity == 1'b1 && decoder_raw != 'h3ff) begin + decoder_raw <= decoder_raw + 1'b1; + end + end + end + + always @(posedge clk) begin + end + + jesd204_8b10b_decoder i_dec ( + .in_char(build_table ? encoder_raw : decoder_raw), + .out_char(decoder_char), + .out_notintable(decoder_notintable), + .out_charisk(decoder_charisk), + + .in_disparity(decoder_disparity), + .out_disparity(decoder_disparity_s), + .out_disperr()); + + wire decoder_should_be_in_table = valid_table[decoder_raw]; + + always @(posedge clk) begin + if (build_table == 1'b0) begin + if (decoder_notintable == decoder_should_be_in_table) begin + $display("%b.%b, %d", decoder_raw[9:6], decoder_raw[5:0], + decoder_should_be_in_table); + failed <= 1'b1; + end + end + end + +endmodule diff --git a/adi_library/jesd204/tb/soft_pcs_loopback_tb b/adi_library/jesd204/tb/soft_pcs_loopback_tb new file mode 100755 index 00000000..567c6453 --- /dev/null +++ b/adi_library/jesd204/tb/soft_pcs_loopback_tb @@ -0,0 +1,9 @@ +#!/bin/bash + +SOURCE="soft_pcs_loopback_tb.v" +SOURCE+=" ../jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v ../jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v" +SOURCE+=" ../jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v ../jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v" +SOURCE+=" ../jesd204_soft_pcs_rx/jesd204_pattern_align.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/jesd204/tb/soft_pcs_loopback_tb.v b/adi_library/jesd204/tb/soft_pcs_loopback_tb.v new file mode 100644 index 00000000..8204bb34 --- /dev/null +++ b/adi_library/jesd204/tb/soft_pcs_loopback_tb.v @@ -0,0 +1,170 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module soft_pcs_loopback_tb; + parameter VCD_FILE = "soft_pcs_loopback_tb.vcd"; + parameter DATA_PATH_WIDTH = 4; + parameter LANE_INVERT = 0; + + `include "tb_base.v" + + reg [7:0] tx_char = {3'd5,5'd28}; + reg tx_charisk = 1'b1; + reg [8*DATA_PATH_WIDTH-1:0] tx_char_pcs = 'h00; + reg [DATA_PATH_WIDTH-1:0] tx_charisk_pcs = 'h00; + + wire [7:0] rx_char; + wire rx_charisk; + wire rx_notintable; + wire rx_disperr; + wire [8*DATA_PATH_WIDTH-1:0] rx_char_pcs; + wire [DATA_PATH_WIDTH-1:0] rx_charisk_pcs; + wire [DATA_PATH_WIDTH-1:0] rx_notintable_pcs; + wire [DATA_PATH_WIDTH-1:0] rx_disperr_pcs; + reg rx_pattern_align_en = 1'b1; + + wire [10*DATA_PATH_WIDTH-1:0] data_aligned; + wire [10*DATA_PATH_WIDTH+9:0] data_aligned_full; + reg [8:0] data_aligned_d1 = 'h00; + reg [10*DATA_PATH_WIDTH-1:0] data_unaligned = 'h00; + reg [3:0] bitshift = 'h00; + + integer clk_div = 0; + wire pcs_clk = clk_div < DATA_PATH_WIDTH / 2 ? 1'b1 : 1'b0; + reg pcs_reset = 1'b1; + + always @(posedge pcs_clk) begin + pcs_reset <= 1'b0; + end + + always @(posedge clk) begin + if (clk_div == DATA_PATH_WIDTH - 1) begin + clk_div <= 0; + end else begin + clk_div <= clk_div + 1; + end + end + + always @(posedge pcs_clk) begin + data_aligned_d1 <= data_aligned[DATA_PATH_WIDTH*10-1:DATA_PATH_WIDTH*10-9]; + end + + assign data_aligned_full = {data_aligned,data_aligned_d1}; + + always @(*) begin + data_unaligned <= data_aligned_full[bitshift+:DATA_PATH_WIDTH*10]; + end + + jesd204_soft_pcs_tx #( + .DATA_PATH_WIDTH(DATA_PATH_WIDTH), + .INVERT_OUTPUTS(LANE_INVERT) + ) i_soft_pcs_tx ( + .clk(pcs_clk), + .reset(pcs_reset), + + .char(tx_char_pcs), + .charisk(tx_charisk_pcs), + + .data(data_aligned)); + + jesd204_soft_pcs_rx #( + .DATA_PATH_WIDTH(DATA_PATH_WIDTH), + .INVERT_INPUTS(LANE_INVERT) + ) i_soft_pcs_rx ( + .clk(pcs_clk), + .reset(pcs_reset), + + .patternalign_en(rx_pattern_align_en), + .data(data_unaligned), + + .char(rx_char_pcs), + .charisk(rx_charisk_pcs), + .notintable(rx_notintable_pcs), + .disperr(rx_disperr_pcs)); + + always @(posedge clk) begin + tx_char_pcs <= {tx_char,tx_char_pcs[DATA_PATH_WIDTH*8-1:8]}; + tx_charisk_pcs <= {tx_charisk,tx_charisk_pcs[DATA_PATH_WIDTH-1:1]}; + end + + integer rx_mux_select = 0; + + always @(posedge clk) begin + if (rx_mux_select == DATA_PATH_WIDTH - 1) begin + rx_mux_select <= 0; + end else begin + rx_mux_select <= rx_mux_select + 1; + end + end + + assign rx_charisk = rx_charisk_pcs[rx_mux_select]; + assign rx_notintable = rx_notintable_pcs[rx_mux_select]; + assign rx_disperr = rx_disperr_pcs[rx_mux_select]; + + generate + genvar i; + for (i = 0; i < 8; i = i + 1) begin + assign rx_char[i] = rx_char_pcs[rx_mux_select*8+i]; + end + endgenerate + + integer counter = 0; + + localparam STATE_SEND_ALIGN = 0; + localparam STATE_SEND_DATA = 1; + reg state = STATE_SEND_ALIGN; + reg [7:0] rx_compare = 'h00; + + always @(posedge clk) begin + case(state) + STATE_SEND_ALIGN: begin + tx_char <= {3'd5,5'd28}; + tx_charisk <= 1'b1; + + // Worst case alignment time is 40 * DATA_PATH_WIDTH + if (counter < DATA_PATH_WIDTH * 60) begin + rx_pattern_align_en <= 1'b1; + end else begin + rx_pattern_align_en <= 1'b0; + end + + if (counter == DATA_PATH_WIDTH * 64) begin + state <= STATE_SEND_DATA; + counter <= 0; + rx_compare <= 'h00; + end else begin + counter <= counter + 1'b1; + end + end + STATE_SEND_DATA: begin + if (tx_charisk == 1'b1) begin + tx_char <= 'h00; + end else begin + tx_char <= tx_char + 1'b1; + end + tx_charisk <= 1'b0; + + if (rx_charisk == 1'b0) begin + rx_compare <= rx_compare + 1'b1; + if (rx_char != rx_compare || rx_disperr == 1'b1 || rx_notintable == 1'b1) begin + failed <= 1'b1; + end + end else begin + rx_compare <= 'h00; + end + + if (rx_char == 'd255) begin + state <= STATE_SEND_ALIGN; + bitshift <= {$random} % 10; + end + end + endcase + end + +endmodule diff --git a/adi_library/jesd204/tb/soft_pcs_pattern_align_tb b/adi_library/jesd204/tb/soft_pcs_pattern_align_tb new file mode 100755 index 00000000..bd63f016 --- /dev/null +++ b/adi_library/jesd204/tb/soft_pcs_pattern_align_tb @@ -0,0 +1,7 @@ +#!/bin/bash + +SOURCE="soft_pcs_pattern_align_tb.v" +SOURCE+=" ../jesd204_soft_pcs_rx/jesd204_pattern_align.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/jesd204/tb/soft_pcs_pattern_align_tb.v b/adi_library/jesd204/tb/soft_pcs_pattern_align_tb.v new file mode 100644 index 00000000..53c0b687 --- /dev/null +++ b/adi_library/jesd204/tb/soft_pcs_pattern_align_tb.v @@ -0,0 +1,79 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module soft_pcs_pattern_align_tb; + parameter VCD_FILE = "soft_pcs_pattern_align_tb.vcd"; + + localparam [9:0] PATTERN_P = 10'b1010000011; + localparam [9:0] PATTERN_N = 10'b0101111100; + + `define TIMEOUT 1000000 + `include "tb_base.v" + + integer counter = 0; + + reg [3:0] bitshift = 4'd0; + reg [9:0] comma_unaligned; + reg comma_sync = 1'b0; + wire [9:0] comma_aligned; + reg [9:0] comma = PATTERN_P; + + wire comma_match = comma == comma_aligned; + + always @(posedge clk) begin + if (counter == 63) begin + if (comma_sync != 1'b1) begin + failed <= 1'b1; + end + + comma_sync <= 1'b0; + counter <= 0; + bitshift <= {$random} % 10; + comma <= {$random} % 2 ? PATTERN_P : PATTERN_N; + end else begin + counter <= counter + 1'b1; + + // Takes two clock cycles for the new value to propagate + if (counter > 1) begin + // Shouldn't loose sync after it gained it + if (comma_match == 1'b1) begin + comma_sync <= 1'b1; + end else if (comma_sync == 1'b1) begin + failed <= 1'b1; + end + end + end + end + + always @(*) begin + case (bitshift) + 4'd0: comma_unaligned <= comma[9:0]; + 4'd1: comma_unaligned <= {comma[0],comma[9:1]}; + 4'd2: comma_unaligned <= {comma[1:0],comma[9:2]}; + 4'd3: comma_unaligned <= {comma[2:0],comma[9:3]}; + 4'd4: comma_unaligned <= {comma[3:0],comma[9:4]}; + 4'd5: comma_unaligned <= {comma[4:0],comma[9:5]}; + 4'd6: comma_unaligned <= {comma[5:0],comma[9:6]}; + 4'd7: comma_unaligned <= {comma[6:0],comma[9:7]}; + 4'd8: comma_unaligned <= {comma[7:0],comma[9:8]}; + default: comma_unaligned <= {comma[8:0],comma[9]}; + endcase + end + + jesd204_pattern_align #( + .DATA_PATH_WIDTH(1) + ) i_pa ( + .clk(clk), + .reset(1'b0), + .patternalign_en(1'b1), + + .in_data(comma_unaligned), + .out_data(comma_aligned)); + +endmodule diff --git a/adi_library/jesd204/tb/tb_base.v b/adi_library/jesd204/tb/tb_base.v new file mode 100755 index 00000000..66086779 --- /dev/null +++ b/adi_library/jesd204/tb/tb_base.v @@ -0,0 +1,55 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2019, 2020, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + + reg clk = 1'b0; + reg [3:0] reset_shift = 4'b1111; + reg trigger_reset = 1'b0; + wire reset; + + reg failed = 1'b0; + + reg sysref = 1'b0; + + initial + begin + $dumpfile (VCD_FILE); + $dumpvars; +`ifdef TIMEOUT + #`TIMEOUT +`else + #100000 +`endif + if (failed == 1'b0) + $display("SUCCESS"); + else + $display("FAILED"); + $finish; + end + + initial forever #10 clk <= ~clk; + always @(posedge clk) begin + if (trigger_reset == 1'b1) begin + reset_shift <= 3'b111; + end else begin + reset_shift <= {reset_shift[2:0],1'b0}; + end + end + + assign reset = reset_shift[3]; + + initial begin + #1000; + @(posedge clk) sysref <= 1'b1; + @(posedge clk) sysref <= 1'b0; + end + + task do_trigger_reset; + begin + @(posedge clk) trigger_reset <= 1'b1; + @(posedge clk) trigger_reset <= 1'b0; + end + endtask diff --git a/adi_library/jesd204/tb/tx_64b_tb b/adi_library/jesd204/tb/tx_64b_tb new file mode 100755 index 00000000..688639aa --- /dev/null +++ b/adi_library/jesd204/tb/tx_64b_tb @@ -0,0 +1,11 @@ +#!/bin/bash + +SOURCE="tx_64b_tb.v" +SOURCE+=" ../jesd204_common/jesd204_lmfc.v ../jesd204_common/jesd204_scrambler_64b.v ../jesd204_common/jesd204_crc12.v" +SOURCE+=" ../jesd204_tx/jesd204_tx.v ../jesd204_tx/jesd204_tx_lane_64b.v ../jesd204_tx/jesd204_tx_header.v" +SOURCE+=" ../jesd204_tx_static_config/jesd204_tx_static_config.v ../jesd204_tx_static_config/jesd204_ilas_cfg_static.v" +SOURCE+=" ../../util_cdc/sync_bits.v" +SOURCE+=" ../jesd204_common/pipeline_stage.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/jesd204/tb/tx_64b_tb.v b/adi_library/jesd204/tb/tx_64b_tb.v new file mode 100644 index 00000000..4a9eb1bc --- /dev/null +++ b/adi_library/jesd204/tb/tx_64b_tb.v @@ -0,0 +1,150 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2020-2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module tx_64b_tb; + parameter VCD_FILE = "tx_tb.vcd"; + parameter NUM_LANES = 1; + parameter NUM_LINKS = 1; + parameter OCTETS_PER_FRAME = 4; + parameter FRAMES_PER_MULTIFRAME = 32; + + localparam SYSREF_HALF_COUNT = OCTETS_PER_FRAME * FRAMES_PER_MULTIFRAME; + + `include "tb_base.v" + + reg [31:0] counter = 'h00; + reg [63:0] tx_data = 'h00000000; + + wire tx_ready; + wire [NUM_LANES-1:0] cfg_lanes_disable; + wire [NUM_LINKS-1:0] cfg_links_disable; + wire [9:0] cfg_octets_per_multiframe; + wire [7:0] cfg_octets_per_frame; + wire [7:0] device_cfg_lmfc_offset; + wire [9:0] device_cfg_octets_per_multiframe; + wire [7:0] device_cfg_octets_per_frame; + wire [7:0] device_cfg_beats_per_multiframe; + wire device_cfg_sysref_disable; + wire device_cfg_sysref_oneshot; + wire cfg_continuous_cgs; + wire cfg_continuous_ilas; + wire cfg_skip_ilas; + wire [7:0] cfg_mframes_per_ilas; + wire cfg_disable_char_replacement; + wire cfg_disable_scrambler; + wire tx_ilas_config_rd; + wire [1:0] tx_ilas_config_addr; + wire [64*NUM_LANES-1:0] tx_ilas_config_data; + + always @(posedge clk) begin + if (reset == 1'b1) begin + tx_data <= 'h00000000; + end else if (tx_ready == 1'b1) begin + tx_data <= tx_data + 1'b1; + end + end + + // DUT with static configuration + + jesd204_tx_static_config #( + .NUM_LANES(NUM_LANES), + .NUM_LINKS(NUM_LINKS), + .OCTETS_PER_FRAME(OCTETS_PER_FRAME), + .FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME), + .LINK_MODE(2) + ) i_cfg ( + .clk(clk), + + .cfg_lanes_disable(cfg_lanes_disable), + .cfg_links_disable(cfg_links_disable), + .cfg_octets_per_multiframe(cfg_octets_per_multiframe), + .cfg_octets_per_frame(cfg_octets_per_frame), + .cfg_continuous_cgs(cfg_continuous_cgs), + .cfg_continuous_ilas(cfg_continuous_ilas), + .cfg_skip_ilas(cfg_skip_ilas), + .cfg_mframes_per_ilas(cfg_mframes_per_ilas), + .cfg_disable_char_replacement(cfg_disable_char_replacement), + .cfg_disable_scrambler(cfg_disable_scrambler), + + .device_cfg_octets_per_multiframe(device_cfg_octets_per_multiframe), + .device_cfg_octets_per_frame(device_cfg_octets_per_frame), + .device_cfg_beats_per_multiframe(device_cfg_beats_per_multiframe), + .device_cfg_lmfc_offset(device_cfg_lmfc_offset), + .device_cfg_sysref_disable(device_cfg_sysref_disable), + .device_cfg_sysref_oneshot(device_cfg_sysref_oneshot), + + .ilas_config_rd(tx_ilas_config_rd), + .ilas_config_addr(tx_ilas_config_addr), + .ilas_config_data(tx_ilas_config_data)); + + jesd204_tx #( + .NUM_LANES(NUM_LANES), + .NUM_LINKS(NUM_LINKS), + .LINK_MODE(2), + .ASYNC_CLK(0) + ) i_tx ( + .clk(clk), + .reset(reset), + + .device_clk(clk), + .device_reset(reset), + + .phy_data(), + .phy_charisk(), + .phy_header(), + + .sysref(sysref), + .lmfc_edge(), + .lmfc_clk(), + + .sync(), + + .tx_data({NUM_LANES{tx_data}}), + .tx_ready(tx_ready), + .tx_eof(), + .tx_sof(), + .tx_somf(), + .tx_eomf(), + .tx_valid(1'b1), + + .cfg_lanes_disable(cfg_lanes_disable), + .cfg_links_disable(cfg_links_disable), + .cfg_octets_per_multiframe(cfg_octets_per_multiframe), + .cfg_octets_per_frame(cfg_octets_per_frame), + .cfg_continuous_cgs(cfg_continuous_cgs), + .cfg_continuous_ilas(cfg_continuous_ilas), + .cfg_skip_ilas(cfg_skip_ilas), + .cfg_mframes_per_ilas(cfg_mframes_per_ilas), + .cfg_disable_char_replacement(cfg_disable_char_replacement), + .cfg_disable_scrambler(cfg_disable_scrambler), + + .device_cfg_octets_per_multiframe(device_cfg_octets_per_multiframe), + .device_cfg_octets_per_frame(device_cfg_octets_per_frame), + .device_cfg_beats_per_multiframe(device_cfg_beats_per_multiframe), + .device_cfg_lmfc_offset(device_cfg_lmfc_offset), + .device_cfg_sysref_disable(device_cfg_sysref_disable), + .device_cfg_sysref_oneshot(device_cfg_sysref_oneshot), + + .ilas_config_rd(tx_ilas_config_rd), + .ilas_config_addr(tx_ilas_config_addr), + .ilas_config_data(tx_ilas_config_data), + + .ctrl_manual_sync_request (1'b0), + + .device_event_sysref_edge (), + .device_event_sysref_alignment_error (), + + .status_sync (), + .status_state (), + + .status_synth_params0(), + .status_synth_params1(), + .status_synth_params2()); + +endmodule diff --git a/adi_library/jesd204/tb/tx_ctrl_phase_tb b/adi_library/jesd204/tb/tx_ctrl_phase_tb new file mode 100755 index 00000000..6a94c89a --- /dev/null +++ b/adi_library/jesd204/tb/tx_ctrl_phase_tb @@ -0,0 +1,8 @@ +#!/bin/bash + +SOURCE="tx_ctrl_phase_tb.v" +SOURCE+=" ../jesd204_tx/jesd204_tx_ctrl.v" +SOURCE+=" ../../util_cdc/sync_bits.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/jesd204/tb/tx_ctrl_phase_tb.v b/adi_library/jesd204/tb/tx_ctrl_phase_tb.v new file mode 100644 index 00000000..f78a7175 --- /dev/null +++ b/adi_library/jesd204/tb/tx_ctrl_phase_tb.v @@ -0,0 +1,198 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +/* + * Regardless of the phase relationship between LMFC and sync the output of the + * ctrl core should be the same as long as the sync signal is in the same lmfc + * cycle. + */ + +`timescale 1ns/100ps + +module tx_ctrl_phase_tb; + parameter VCD_FILE = "tx_ctrl_phase.vcd"; + parameter BEATS_PER_LMFC = 20; + + `include "tb_base.v" + + reg lmfc_edge = 1'b0; + reg a_sync = 1'b0; + reg b_sync = 1'b0; + + wire [31:0] a_ilas_data; + wire [3:0] a_ilas_charisk; + wire [1:0] a_ilas_config_addr; + wire a_ilas_config_rd; + wire a_tx_ready; + wire a_lane_cgs_enable; + + wire [31:0] b_ilas_data; + wire [3:0] b_ilas_charisk; + wire [1:0] b_ilas_config_addr; + wire b_ilas_config_rd; + wire b_tx_ready; + wire b_lane_cgs_enable; + + wire [9:0] cfg_octets_per_multiframe = BEATS_PER_LMFC*4-1; + + reg reset2 = 1'b1; + + integer reset_counter = 0; + integer beat_counter = 0; + integer lmfc_counter = 0; + integer b_offset = 0; + + always @(posedge clk) begin + if (reset2 == 1'b1) begin + if (reset_counter == 7) begin + reset2 <= 1'b0; + reset_counter <= 0; + end else begin + reset_counter <= reset_counter + 1; + end + end + + if (reset2 == 1'b1) begin + beat_counter <= 0; + a_sync <= 1'b0; + b_sync <= 1'b0; + end else begin + beat_counter <= beat_counter + 1'b1; + if (beat_counter == BEATS_PER_LMFC*2) begin + a_sync <= 1'b1; + end + + if (beat_counter == BEATS_PER_LMFC*2 + b_offset) begin + b_sync <= 1'b1; + end + + if (beat_counter == BEATS_PER_LMFC*9) begin + b_offset <= b_offset + 1; + reset2 <= 1'b1; + end + end + + if (reset2 == 1'b1) begin + lmfc_counter <= BEATS_PER_LMFC-3; + end else begin + lmfc_counter <= lmfc_counter + 1; + if (lmfc_counter == BEATS_PER_LMFC-1) begin + lmfc_counter <= 0; + lmfc_edge <= 1'b1; + end else begin + lmfc_edge <= 1'b0; + end + end + end + + jesd204_tx_ctrl i_tx_ctrl_a ( + .clk(clk), + .reset(reset2), + + .sync(a_sync), + .lmfc_edge(lmfc_edge), + .somf(), + .somf_early2({3'b0,lmfc_edge}), + .eomf(), + + .lane_cgs_enable(a_lane_cgs_enable), + .eof_reset(), + + .tx_ready(a_tx_ready), + .tx_ready_nx(), + .tx_next_mf_ready(), + + .ilas_data(a_ilas_data), + .ilas_charisk(a_ilas_charisk), + + .ilas_config_addr(a_ilas_config_addr), + .ilas_config_rd(a_ilas_config_rd), + .ilas_config_data('h00), + + .cfg_lanes_disable(1'b0), + .cfg_links_disable(1'b0), + .cfg_continuous_cgs(1'b0), + .cfg_continuous_ilas(1'b0), + .cfg_skip_ilas(1'b0), + .cfg_mframes_per_ilas(8'h3), + .cfg_octets_per_multiframe(cfg_octets_per_multiframe), + + .ctrl_manual_sync_request(1'b0), + + .status_sync(), + .status_state()); + + jesd204_tx_ctrl i_tx_ctrl_b ( + .clk(clk), + .reset(reset2), + + .sync(b_sync), + .lmfc_edge(lmfc_edge), + .somf(), + .somf_early2({3'b0,lmfc_edge}), + .eomf(), + + .lane_cgs_enable(b_lane_cgs_enable), + .eof_reset(), + + .tx_ready(b_tx_ready), + .tx_ready_nx(), + .tx_next_mf_ready(), + + .ilas_data(b_ilas_data), + .ilas_charisk(b_ilas_charisk), + + .ilas_config_addr(b_ilas_config_addr), + .ilas_config_rd(b_ilas_config_rd), + .ilas_config_data('h00), + + .cfg_lanes_disable(1'b0), + .cfg_links_disable(1'b0), + .cfg_continuous_cgs(1'b0), + .cfg_continuous_ilas(1'b0), + .cfg_skip_ilas(1'b0), + .cfg_mframes_per_ilas(8'h3), + .cfg_octets_per_multiframe(cfg_octets_per_multiframe), + + .ctrl_manual_sync_request(1'b0), + + .status_sync(), + .status_state()); + + reg status = 1'b1; + + always @(*) begin + if (reset2 == 1'b1) begin + status <= 1'b1; + end else if (a_ilas_data != b_ilas_data || + a_ilas_charisk != b_ilas_charisk || + a_ilas_config_addr != b_ilas_config_addr || + a_ilas_config_rd != b_ilas_config_rd || + a_lane_cgs_enable != b_lane_cgs_enable || + a_tx_ready != b_tx_ready) begin + status <= 1'b0; + end + end + + reg message_shown = 1'b0; + + always @(posedge clk) begin + if (status == 1'b0 && message_shown == 1'b0 && b_offset < BEATS_PER_LMFC) begin + $display("FAILED at offset %0d", b_offset); + message_shown <= 1'b1; + end + end + + always @(posedge clk) begin + if (b_offset == BEATS_PER_LMFC+1) begin + if (message_shown == 1'b0) + $display("SUCCESS"); + $finish; + end + end + +endmodule diff --git a/adi_library/jesd204/tb/tx_tb b/adi_library/jesd204/tb/tx_tb new file mode 100755 index 00000000..ee4b010c --- /dev/null +++ b/adi_library/jesd204/tb/tx_tb @@ -0,0 +1,10 @@ +#!/bin/bash + +SOURCE="tx_tb.v" +SOURCE+=" ../jesd204_common/jesd204_lmfc.v ../jesd204_common/jesd204_scrambler.v ../jesd204_common/jesd204_eof_generator.v" +SOURCE+=" ../jesd204_tx/jesd204_tx.v ../jesd204_tx/jesd204_tx_ctrl.v ../jesd204_tx/jesd204_tx_lane.v" +SOURCE+=" ../jesd204_tx_static_config/jesd204_tx_static_config.v ../jesd204_tx_static_config/jesd204_ilas_cfg_static.v" +SOURCE+=" ../../util_cdc/sync_bits.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/jesd204/tb/tx_tb.v b/adi_library/jesd204/tb/tx_tb.v new file mode 100644 index 00000000..cb901f14 --- /dev/null +++ b/adi_library/jesd204/tb/tx_tb.v @@ -0,0 +1,170 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved. +// SPDX short identifier: ADIJESD204 +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module tx_tb; + parameter VCD_FILE = "tx_tb.vcd"; + parameter NUM_LANES = 4; + parameter NUM_LINKS = 2; + parameter OCTETS_PER_FRAME = 4; + parameter FRAMES_PER_MULTIFRAME = 32; + + `include "tb_base.v" + + reg [NUM_LINKS-1:0] sync = {NUM_LINKS{1'b1}}; + reg [31:0] counter = 'h00; + reg [31:0] tx_data = 'h00000000; + + wire tx_ready; + wire tx_valid = 1'b1; + wire [NUM_LANES-1:0] cfg_lanes_disable; + wire [NUM_LINKS-1:0] cfg_links_disable; + wire [9:0] cfg_octets_per_multiframe; + wire [7:0] cfg_octets_per_frame; + wire [7:0] device_cfg_lmfc_offset; + wire [9:0] device_cfg_octets_per_multiframe; + wire [7:0] device_cfg_octets_per_frame; + wire [7:0] device_cfg_beats_per_multiframe; + wire device_cfg_sysref_disable; + wire device_cfg_sysref_oneshot; + wire cfg_continuous_cgs; + wire cfg_continuous_ilas; + wire cfg_skip_ilas; + wire [7:0] cfg_mframes_per_ilas; + wire cfg_disable_char_replacement; + wire cfg_disable_scrambler; + wire tx_ilas_config_rd; + wire [1:0] tx_ilas_config_addr; + wire [32*NUM_LANES-1:0] tx_ilas_config_data; + + always @(posedge clk) begin + if (reset == 1'b1) begin + tx_data <= 'h00000000; + end else if (tx_ready == 1'b1) begin + tx_data <= tx_data + 1'b1; + end + end + + /* Generate independent SYNCs + * + * Each SYNC will be asserted/deasserted at different clock edges. + * The assertion/deassertion order: first SYNC[0], ..., last SYNC[NUM_LINKS-1] + */ + always @(posedge clk) begin + counter <= counter + 1'b1; + end + + genvar i; + generate + for (i=1; i<=NUM_LINKS; i=i+1) begin: SYNC_GENERATOR + always @(posedge clk) begin + if (counter >= (32'h100 | (i << 4)) && counter <= (32'h300 | (i << 4))) begin + sync[i-1] <= 1'b0; + end else begin + sync[i-1] <= 1'b1; + end + end + end + endgenerate + + // DUT with static configuration + + jesd204_tx_static_config #( + .NUM_LANES(NUM_LANES), + .NUM_LINKS(NUM_LINKS), + .OCTETS_PER_FRAME(OCTETS_PER_FRAME), + .FRAMES_PER_MULTIFRAME(FRAMES_PER_MULTIFRAME) + ) i_cfg ( + .clk(clk), + + .cfg_lanes_disable(cfg_lanes_disable), + .cfg_links_disable(cfg_links_disable), + .cfg_octets_per_multiframe(cfg_octets_per_multiframe), + .cfg_octets_per_frame(cfg_octets_per_frame), + .cfg_continuous_cgs(cfg_continuous_cgs), + .cfg_continuous_ilas(cfg_continuous_ilas), + .cfg_skip_ilas(cfg_skip_ilas), + .cfg_mframes_per_ilas(cfg_mframes_per_ilas), + .cfg_disable_char_replacement(cfg_disable_char_replacement), + .cfg_disable_scrambler(cfg_disable_scrambler), + + .device_cfg_octets_per_multiframe(device_cfg_octets_per_multiframe), + .device_cfg_octets_per_frame(device_cfg_octets_per_frame), + .device_cfg_beats_per_multiframe(device_cfg_beats_per_multiframe), + .device_cfg_lmfc_offset(device_cfg_lmfc_offset), + .device_cfg_sysref_disable(device_cfg_sysref_disable), + .device_cfg_sysref_oneshot(device_cfg_sysref_oneshot), + + .ilas_config_rd(tx_ilas_config_rd), + .ilas_config_addr(tx_ilas_config_addr), + .ilas_config_data(tx_ilas_config_data)); + + jesd204_tx #( + .NUM_LANES(NUM_LANES), + .NUM_LINKS(NUM_LINKS), + .ASYNC_CLK(0) + ) i_tx ( + .clk(clk), + .reset(reset), + + .device_clk(clk), + .device_reset(reset), + + .phy_data(), + .phy_charisk(), + .phy_header(), + + .sysref(sysref), + .lmfc_edge(), + .lmfc_clk(), + + .sync(sync), + + .tx_data({NUM_LANES{tx_data}}), + .tx_ready(tx_ready), + .tx_eof(), + .tx_sof(), + .tx_somf(), + .tx_eomf(), + .tx_valid(1'b1), + + .cfg_lanes_disable(cfg_lanes_disable), + .cfg_links_disable(cfg_links_disable), + .cfg_octets_per_multiframe(cfg_octets_per_multiframe), + .cfg_octets_per_frame(cfg_octets_per_frame), + .cfg_continuous_cgs(cfg_continuous_cgs), + .cfg_continuous_ilas(cfg_continuous_ilas), + .cfg_skip_ilas(cfg_skip_ilas), + .cfg_mframes_per_ilas(cfg_mframes_per_ilas), + .cfg_disable_char_replacement(cfg_disable_char_replacement), + .cfg_disable_scrambler(cfg_disable_scrambler), + + .device_cfg_octets_per_multiframe(device_cfg_octets_per_multiframe), + .device_cfg_octets_per_frame(device_cfg_octets_per_frame), + .device_cfg_beats_per_multiframe(device_cfg_beats_per_multiframe), + .device_cfg_lmfc_offset(device_cfg_lmfc_offset), + .device_cfg_sysref_disable(device_cfg_sysref_disable), + .device_cfg_sysref_oneshot(device_cfg_sysref_oneshot), + + .ilas_config_rd(tx_ilas_config_rd), + .ilas_config_addr(tx_ilas_config_addr), + .ilas_config_data(tx_ilas_config_data), + + .ctrl_manual_sync_request (1'b0), + + .device_event_sysref_edge (), + .device_event_sysref_alignment_error (), + + .status_sync (), + .status_state (), + + .status_synth_params0(), + .status_synth_params1(), + .status_synth_params2()); + +endmodule diff --git a/adi_library/scripts/adi_intel_device_info_enc.tcl b/adi_library/scripts/adi_intel_device_info_enc.tcl new file mode 100644 index 00000000..04b26ed4 --- /dev/null +++ b/adi_library/scripts/adi_intel_device_info_enc.tcl @@ -0,0 +1,141 @@ +############################################################################### +## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# adi_intel_device_info_enc.tcl + +# The main rule when adding a new parameter is to have the same names for the parameter +# and it's list (valid range type or supported entity and its encoded value type) + +variable auto_set_param_list +variable fpga_technology_list +variable fpga_technology +variable fpga_family_list +variable fpga_family +variable speed_grade_list +variable speed_grade +variable dev_package_list +variable dev_package +variable xcvr_type_list +variable xcvr_type +variable fpga_voltage_list +variable fpga_voltage + +# Parameter list for automatic assignament(generation) +set auto_gen_param_list { \ + FPGA_TECHNOLOGY \ + FPGA_FAMILY \ + SPEED_GRADE \ + DEV_PACKAGE} + +set auto_set_param_list { \ + FPGA_VOLTAGE \ + XCVR_TYPE} + + +# List for automatically assigned parameter values and encoded values +# The list name must be the parameter name (lowercase), appending "_list" to it +set fpga_technology_list { \ + { Unknown 100 } \ + { "Cyclone V" 101 } \ + { "Cyclone 10" 102 } \ + { "Arria 10" 103 } \ + { "Stratix 10" 104 }} + +set fpga_family_list { \ + { Unknown 0 } \ + { SX 1 } \ + { GX 2 } \ + { GT 3 } \ + { GZ 4 } \ + { "SE Base" 5 }} + + #technology 5 generation + # family Arria SX + +set speed_grade_list { \ + { Unknown 0 } \ + { 1 1 } \ + { 2 2 } \ + { 3 3 } \ + { 4 4 } \ + { 5 5 } \ + { 6 6 } \ + { 7 7 } \ + { 8 8 }} + +set dev_package_list { \ + { Unknown 0 } \ + { BGA 1 } \ + { PGA 2 } \ + { FBGA 3 } \ + { HBGA 4 } \ + { PDIP 5 } \ + { EQFP 6 } \ + { PLCC 7 } \ + { PQFP 8 } \ + { RQFP 9 } \ + { TQFP 10 } \ + { UBGA 11 } \ + { UFBGA 12 } \ + { MBGA 13 }} + +# Ball-Grid Array (BGA) +# Ceramic Pin-Grid Array (PGA) +# FineLine BGA (FBGA) +# Hybrid FineLine BGA (HBGA) +# Plastic Dual In-Line Package (PDIP) +# Plastic Enhanced Quad Flat Pack (EQFP) +# Plastic J-Lead Chip Carrier (PLCC) +# Plastic Quad Flat Pack (PQFP) +# Power Quad Flat Pack (RQFP) +# Thin Quad Flat Pack (TQFP) +# Ultra FineLine BGA (UBGA-UFBGA) + +# transceiver speedgrade +set xcvr_type_list { 0 9 } + +set fpga_voltage_list { 0 5000 } ;# min 0mV max 5V + +################################################################################ + +proc get_part_param {} { + + global fpga_technology + global fpga_family + global speed_grade + global dev_package + global xcvr_type + global fpga_voltage + + set device [get_parameter_value DEVICE] + + # user and system values (sys_val) + if {[catch {set fpga_technology [quartus::device::get_part_info -family $device]} fid]} { + set fpga_technology "Unknown" + } + if {[catch {set fpga_family [quartus::device::get_part_info -family_variant $device]} fid]} { + set fpga_family "Unknown" + } + if {[catch {set speed_grade [quartus::device::get_part_info -speed_grade $device]} fid]} { + set speed_grade "Unknown" + } + if {[catch {set dev_package [quartus::device::get_part_info -package $device]} fid]} { + set dev_package "Unknown" + } + if {[catch {set xcvr_type [quartus::device::get_part_info -hssi_speed_grade $device]} fid]} { + set xcvr_type "Unknown" + } + if {[catch {set fpga_voltage [quartus::device::get_part_info -default_voltage $device]} fid]} { + set fpga_voltage "0" + } + + # user and system values (sys_val) + regsub {V} $fpga_voltage "" fpga_voltage + set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) + +} + +## *************************************************************************** +## *************************************************************************** diff --git a/adi_library/scripts/adi_ip_intel.tcl b/adi_library/scripts/adi_ip_intel.tcl new file mode 100644 index 00000000..a5f31e11 --- /dev/null +++ b/adi_library/scripts/adi_ip_intel.tcl @@ -0,0 +1,448 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +## Define an interface for Platform Designer. +# +# \param[type] - Type of the interface, valid values are : clock, reset, reset-n, +# signal, intr +# \param[name] - The name of the interface +# \param[dir] - The direction of the interface +# \param[width] - The width of the interface +# \param[arg_1] - Optional argument to define the associated clock for a reset +# interface +# \param[arg_2] - Optional argument to define the associated reset sink for a +# reset interface +# +proc ad_interface {type name dir width {arg_1 ""} {arg_2 ""}} { + + if {([string equal -nocase ${type} "clock"]) && ([string equal -nocase ${dir} "input"])} { + add_interface if_${name} clock sink + add_interface_port if_${name} ${name} clk ${dir} ${width} + return + } + + if {([string equal -nocase ${type} "clock"]) && ([string equal -nocase ${dir} "output"])} { + add_interface if_${name} clock source + add_interface_port if_${name} ${name} clk ${dir} ${width} + return + } + + if {([string equal -nocase ${type} "reset"]) && ([string equal -nocase ${dir} "input"])} { + add_interface if_${name} reset sink + add_interface_port if_${name} ${name} reset ${dir} ${width} + set_interface_property if_${name} associatedclock ${arg_1} + return + } + + if {([string equal -nocase ${type} "reset"]) && ([string equal -nocase ${dir} "output"])} { + add_interface if_${name} reset source + add_interface_port if_${name} ${name} reset ${dir} ${width} + set_interface_property if_${name} associatedclock ${arg_1} + set_interface_property if_${name} associatedResetSinks ${arg_2} + return + } + + if {([string equal -nocase ${type} "reset-n"]) && ([string equal -nocase ${dir} "input"])} { + add_interface if_${name} reset sink + add_interface_port if_${name} ${name} reset_n ${dir} ${width} + set_interface_property if_${name} associatedclock ${arg_1} + return + } + + if {([string equal -nocase ${type} "reset-n"]) && ([string equal -nocase ${dir} "output"])} { + add_interface if_${name} reset source + add_interface_port if_${name} ${name} reset_n ${dir} ${width} + set_interface_property if_${name} associatedclock ${arg_1} + set_interface_property if_${name} associatedResetSinks ${arg_2} + return + } + + if {([string equal -nocase ${type} "intr"]) && ([string equal -nocase ${dir} "output"])} { + add_interface if_${name} interrupt source + add_interface_port if_${name} ${name} irq ${dir} ${width} + set_interface_property if_${name} associatedclock ${arg_1} + return + } + + set remap $arg_1 + if {$arg_1 eq ""} { + set remap $name + } + + if {[string equal -nocase ${type} "signal"]} { + add_interface if_${name} conduit end + add_interface_port if_${name} ${name} ${remap} ${dir} ${width} + return + } +} + +## Create a point-to-point conduit interface. +# +# \param[if_name] - the name of the interface +# \param[if_port] - the type of signal for this port, which must be unique +# \param[port] - the name of the port, this name must match the signal name +# in HDL +# \param[dir] - the direction of the signal, expected values: input/output/bidir +# \param[width] - the width of the port, in bits +# +proc ad_conduit {if_name if_port port dir width} { + + add_interface $if_name conduit end + add_interface_port $if_name $port $if_port $dir $width +} + +## Create an IP. +# +# \param[pname] - name of the IP, general equivalent to the top HDL module name +# \param[pdisplay_name] - displayed name +# \param[pelabfunction] - name of the elaboration callback function +# \param[pcomposefunction] - name of the composition callback function +# +proc ad_ip_create {pname pdisplay_name {pelabfunction ""} {pcomposefunction ""}} { + + set_module_property NAME $pname + set_module_property DISPLAY_NAME $pdisplay_name + set_module_property DESCRIPTION $pdisplay_name + set_module_property VERSION 1.0 + set_module_property GROUP "Analog Devices" + + if {$pelabfunction ne ""} { + set_module_property ELABORATION_CALLBACK $pelabfunction + } + + if {$pcomposefunction ne ""} { + set_module_property COMPOSITION_CALLBACK $pcomposefunction + } +} + +## Create an IP parameter. +# +# \param[pname] - name of the IP, general equivalent to the top HDL module name +# \param[ptype] - the data type of the parameter +# \param[pdefault] - the initial value of the parameter +# \param[phdl] - define if the parameter is an HDL parameter or not +# \param[properties] - can define different properties for the parameter, must be +# a list of {key, value} pairs +# +proc ad_ip_parameter {pname ptype pdefault {phdl true} {properties {}}} { + + if {$pname eq "DEVICE_FAMILY"} { + add_parameter DEVICE_FAMILY STRING + set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY} + set_parameter_property DEVICE_FAMILY AFFECTS_GENERATION true + set_parameter_property DEVICE_FAMILY HDL_PARAMETER false + set_parameter_property DEVICE_FAMILY ENABLED true + } else { + add_parameter $pname $ptype $pdefault + set_parameter_property $pname HDL_PARAMETER $phdl + set_parameter_property $pname ENABLED true + } + + foreach {key value} $properties { + set_parameter_property $pname $key $value + } +} + +## Adds the generic ADI spec parameters to the current IP, with the help of +# adi_add_device_spec_param. The spec parameter list is auto_gen_param_list, +# from library/scripts/adi_intel_device_info_enc.tcl. +# +proc adi_add_auto_fpga_spec_params {} { + + global ad_hdl_dir + source $ad_hdl_dir/library/scripts/adi_intel_device_info_enc.tcl + + ad_ip_parameter DEVICE STRING "" false { + SYSTEM_INFO DEVICE + VISIBLE false + } + + foreach p $auto_gen_param_list { + adi_add_device_spec_param $p + } +} + +## Generate validation properties for a parameter, using predefined ranges or +# set of values (the definition of the ranges can be found in +# library/scripts/adi_intel_device_info_enc.tcl). +# +# In Intel callback flow, one cannot directly change a parameter value, the value +# can only be calculated/deduced from the environment. +# Adding a second parameter with the same name followed by "_MANUAL", will add +# in the environment the desired value that is still constrained to a predefined +# set. Having the second parameter is not enough, to activate the manual +# overwriting of a parameter one must call the adi_add_indep_spec_params_overwrite +# process. +# +# \param[param] - Name of the HDL parameter. The list of accepted values for +# the parameter are defined with the same name as the parameter's one(lower case), +# followed by "_list" +# +proc adi_add_device_spec_param {param} { + + global auto_gen_param_list + global auto_set_param_list + global fpga_technology_list + global fpga_family_list + global speed_grade_list + global dev_package_list + global xcvr_type_list + global fpga_voltage_list + + set group "FPGA info" + + set list_pointer [string tolower $param] + set list_pointer [append list_pointer "_list"] + + set enc_list [subst $$list_pointer] + + set ranges "" + + add_parameter $param INTEGER + set_parameter_property $param DISPLAY_NAME $param + set_parameter_property $param GROUP $group + set_parameter_property $param UNITS None + set_parameter_property $param HDL_PARAMETER true + set_parameter_property $param VISIBLE true + set_parameter_property $param DERIVED true + + add_parameter ${param}_MANUAL INTEGER + set_parameter_property ${param}_MANUAL DISPLAY_NAME $param + set_parameter_property ${param}_MANUAL GROUP $group + set_parameter_property ${param}_MANUAL UNITS None + set_parameter_property ${param}_MANUAL HDL_PARAMETER false + set_parameter_property ${param}_MANUAL VISIBLE false + set_parameter_property ${param}_MANUAL DEFAULT_VALUE [lindex $enc_list 0 1] + + foreach i $enc_list { + set value [lindex $i 0] + set encode [lindex $i 1] + append ranges "\"$encode\:$value\" " + } + set_parameter_property $param ALLOWED_RANGES $ranges + set_parameter_property ${param}_MANUAL ALLOWED_RANGES $ranges +} + +## Creates a boolean type parameter that allows this user to manually overwrite +# parameter values. +# +# \param[param] - Name of the HDL parameter. +# +proc adi_add_indep_spec_params_overwrite {param} { + add_parameter ${param}_USER_OVERWRITE BOOLEAN 0 + set_parameter_property ${param}_USER_OVERWRITE DISPLAY_NAME "Manually overwrite $param parameter" + set_parameter_property ${param}_USER_OVERWRITE HDL_PARAMETER false + set_parameter_property ${param}_USER_OVERWRITE GROUP {FPGA info} +} + +## In this process the IP parameters are compared against predefined parameter lists +# in library/scripts/adi_intel_device_info_enc.tcl. For the matching parameters, +# a search is started after a pair *_USER_OVERWRITE(boolean) parameter. If the pair +# *_USER_OVERWRITE parameter is found, and its value is true, the target parameter +# will take the value of the *_MANUAL parameter. The GUI parameter is set as +# writable in the qsys GUI (${parameter_name} is replaced by ${parameter_name}_MANUAL). +# +proc info_param_validate {} { + global ad_hdl_dir + global fpga_technology + global fpga_family + global speed_grade + global dev_package + global xcvr_type + global fpga_voltage + + source $ad_hdl_dir/library/scripts/adi_intel_device_info_enc.tcl + + set device [get_parameter_value DEVICE] + set auto_populate true ;# for future code dev + + set all_ip_param_list [get_parameters] + set validate_list "" + set independent_overwrite_list "" + foreach param $all_ip_param_list { + foreach elem [concat $auto_gen_param_list $auto_set_param_list] { + if { "$elem" == "$param" } { + append validate_list "$param " + } + if { [regexp ${elem}_USER_OVERWRITE $param] } { + append independent_overwrite_list "$elem " + } + } + } + + set indep_overwrite [expr {[llength $independent_overwrite_list] != 0} ? 1 : 0] + + if { $auto_populate == true } { + + get_part_param ;# in adi_intel_device_info_enc.tcl + + # point parameters and assign + foreach param $validate_list { + set ls_param [string tolower $param] + set list_pointer $ls_param + append list_pointer "_list" + set pointer_to_sys_val [subst $$ls_param] ;# e.g., $fpga_technology + set enc_list_pointer [subst $$list_pointer] ;# e.g., $fpga_technology_list + + # get_part_info returns '{'#value'}' + regsub -all "{" $pointer_to_sys_val "" pointer_to_sys_val + regsub -all "}" $pointer_to_sys_val "" pointer_to_sys_val + + # the list defines a range or pairs of values + set get_list_correspondence 1 + if { [llength $enc_list_pointer] != 0 } { + if { [llength $enc_list_pointer] == 2 } { + if { [llength [lindex $enc_list_pointer 0]] == 1 } { + set get_list_correspondence 0 + } + } + } else { + send_message ERROR "No list $list_pointer defined in adi_intel_device_info_enc.tcl for parameter $param" + } + + # auto assign parameter value + if { $get_list_correspondence } { + set matched "" + foreach i $enc_list_pointer { + if { [regexp ^[lindex $i 0] $pointer_to_sys_val] } { + set matched [lindex $i 1] + } + } + if { $matched == "" } { + send_message ERROR "Unknown or undefined(adi_intel_device_info_enc.tcl) $param \"$pointer_to_sys_val\" form \"$device\" device" + } else { + set_parameter_value $param $matched + } + } else { + set_parameter_value $param $pointer_to_sys_val + } + } + } else { + foreach p $validate_list { + set_parameter_value $p [get_parameter_value ${p}_MANUAL] + } + } + + # display manual(writable) or auto(non-writable) parameters + foreach p $validate_list { + set_parameter_property ${p}_MANUAL VISIBLE [expr $auto_populate ? false : true] + set_parameter_property $p VISIBLE $auto_populate + if { $indep_overwrite == 1 } { + foreach p_overwrite $independent_overwrite_list { + if { $p == $p_overwrite } { + set p_over_val [get_parameter_value ${p}_USER_OVERWRITE] + # set the hdl parameter with the independent manual overwritten value + if { $p_over_val } { + set_parameter_value $p [get_parameter_value ${p}_MANUAL] + set_parameter_property ${p}_MANUAL VISIBLE $p_over_val + set_parameter_property $p VISIBLE [expr $p_over_val ? false : true] + } + } + } + } + } +} + +## Add source files to an IP, automatically find the file type using its extension. +# +# \param[pname] - name of the IP, general equivalent to the top HDL module name +# \param[pfile] - name of the file +# +proc ad_ip_addfile {pname pfile} { + + set pmodule [file tail $pfile] + + regsub {\..$} $pmodule {} mname + if {$pname eq $mname} { + add_fileset_file $pmodule VERILOG PATH $pfile TOP_LEVEL_FILE + return + } + + set ptype [file extension $pfile] + if {$ptype eq ".v"} { + add_fileset_file $pmodule VERILOG PATH $pfile + return + } + if {$ptype eq ".sv"} { + add_fileset_file $pmodule SYSTEM_VERILOG PATH $pfile + return + } + if {$ptype eq ".vh"} { + add_fileset_file $pmodule VERILOG_INCLUDE PATH $pfile + return + } + if {$ptype eq ".svh"} { + add_fileset_file $pmodule SYSTEM_VERILOG_INCLUDE PATH $pfile + return + } + if {$ptype eq ".sdc"} { + add_fileset_file $pmodule SDC PATH $pfile + return + } + if {$ptype eq ".tcl"} { + add_fileset_file $pmodule OTHER PATH $pfile + return + } +} + +## Add source files to an IP, automatically find the file type using its extension. +# +# \param[pname] - name of the IP, general equivalent to the top HDL module name +# \param[pfile] - name of the file +# +proc ad_ip_files {pname pfiles {pfunction ""}} { + + add_fileset quartus_synth QUARTUS_SYNTH $pfunction "" + set_fileset_property quartus_synth TOP_LEVEL $pname + foreach pfile $pfiles { + ad_ip_addfile $pname $pfile + } + + add_fileset quartus_sim SIM_VERILOG $pfunction "" + set_fileset_property quartus_sim TOP_LEVEL $pname + foreach pfile $pfiles { + ad_ip_addfile $pname $pfile + } +} + +## Infer an AXI4 Lite memory mapped interface. +# +# \param[aclk] - name of the interface clock +# \param[arstn] - name fo the interface reset +# \param[addr_width] - address width of the read and write channels +# +proc ad_ip_intf_s_axi {aclk arstn {addr_width 16}} { + + add_interface s_axi_clock clock end + add_interface_port s_axi_clock ${aclk} clk Input 1 + + add_interface s_axi_reset reset end + set_interface_property s_axi_reset associatedClock s_axi_clock + add_interface_port s_axi_reset ${arstn} reset_n Input 1 + + add_interface s_axi axi4lite end + set_interface_property s_axi associatedClock s_axi_clock + set_interface_property s_axi associatedReset s_axi_reset + add_interface_port s_axi s_axi_awvalid awvalid Input 1 + add_interface_port s_axi s_axi_awaddr awaddr Input $addr_width + add_interface_port s_axi s_axi_awprot awprot Input 3 + add_interface_port s_axi s_axi_awready awready Output 1 + add_interface_port s_axi s_axi_wvalid wvalid Input 1 + add_interface_port s_axi s_axi_wdata wdata Input 32 + add_interface_port s_axi s_axi_wstrb wstrb Input 4 + add_interface_port s_axi s_axi_wready wready Output 1 + add_interface_port s_axi s_axi_bvalid bvalid Output 1 + add_interface_port s_axi s_axi_bresp bresp Output 2 + add_interface_port s_axi s_axi_bready bready Input 1 + add_interface_port s_axi s_axi_arvalid arvalid Input 1 + add_interface_port s_axi s_axi_araddr araddr Input $addr_width + add_interface_port s_axi s_axi_arprot arprot Input 3 + add_interface_port s_axi s_axi_arready arready Output 1 + add_interface_port s_axi s_axi_rvalid rvalid Output 1 + add_interface_port s_axi s_axi_rresp rresp Output 2 + add_interface_port s_axi s_axi_rdata rdata Output 32 + add_interface_port s_axi s_axi_rready rready Input 1 +} + diff --git a/adi_library/scripts/adi_ip_xilinx.tcl b/adi_library/scripts/adi_ip_xilinx.tcl new file mode 100644 index 00000000..833708d1 --- /dev/null +++ b/adi_library/scripts/adi_ip_xilinx.tcl @@ -0,0 +1,638 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl +if {[info exists ::env(ADI_VIVADO_IP_LIBRARY)]} { + set VIVADO_IP_LIBRARY $::env(ADI_VIVADO_IP_LIBRARY) +} else { + set VIVADO_IP_LIBRARY user +} + +## Add a ttcl file to the project. XDC does not support if statements +# in constraint definitions, this file can be used to add parameter dependent +# constraints to the IP. +# +# \param[ip_name] - IP name +# \param[ip_constr_files] - .ttcl file name (full path) +# +proc adi_ip_ttcl {ip_name ip_constr_files} { + + set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}] + set f [ipx::add_file $ip_constr_files $proj_filegroup] + set_property -dict [list \ + type ttcl \ + ] $f + ipx::reorder_files -front $ip_constr_files $proj_filegroup +} + +## Add ttcl file to generate simulation files for System Verilog environments. +# +# \param[ip_name] - IP name +# \param[ip_constr_files] - .ttcl file name (full path) +# +proc adi_ip_sim_ttcl {ip_name ip_files} { + + set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}] + set f [ipx::add_file $ip_files $proj_filegroup] + set_property -dict [list \ + type ttcl \ + ] $f + ipx::reorder_files -front $ip_files $proj_filegroup +} + +## Add a block design, defined by a tcl source, to the IP. +# +# \param[ip_name] - IP name +# \param[ip_bd_files] - Tcl source file +# +proc adi_ip_bd {ip_name ip_bd_files} { + set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]] + if {$proj_filegroup == {}} { + set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]] + } + + foreach file $ip_bd_files { + set f [ipx::add_file $file $proj_filegroup] + set_property -dict [list \ + type tclSource \ + ] $f + } +} + +## Infers an AXI Streaming interface. Note that the interface has to exist. +# +# \param[ip_name] - IP name +# +proc adi_ip_infer_streaming_interfaces {ip_name} { + + ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core] + +} + +## Infers an AXI Memory Mapped interface. Note that the interface has to exist. +# +# \param[ip_name] - IP name +# +proc adi_ip_infer_mm_interfaces {ip_name} { + + ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] + +} + +## Defines a dependency for a port. +# +# \param[port_prefix] - Port prefix, which defines an interface. All ports of an +# interface must have the same prefix. If it's a single port, the whole name +# shall be defined. +# \param[dependency] - Dependency (e.g "PARAMETER_NAME == 1") ??? {spirit:decode(id('MODELPARAM_VALUE.PARAM_NAME')) == CONST} +# \param[driver_value] - Driver value is optional. It defines the default driver +# value of the port. +# +proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} { + foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] { + set_property ENABLEMENT_DEPENDENCY $dependency $port + if {$driver_value != {}} { + set_property DRIVER_VALUE $driver_value $port + } + } +} + +## Defines a dependency for a bus. +# +# \param[bus] - Name of the bus +# \param[prefix] - Port prefix, in general same as the name of the bus +# \param[dependency] - Dependency (e.g "PARAMETER_NAME == 1") ??? {spirit:decode(id('MODELPARAM_VALUE.PARAM_NAME')) == CONST} +# +proc adi_set_bus_dependency {bus prefix dependency} { + set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]] + adi_set_ports_dependency $prefix $dependency 0 +} + +## Add a new port map definition to a bus interface. +# +# \param[bus] - Name of the bus interface +# \param[phys] - Physical name of the port +# \param[logic] - Logic name of the port (defined by the interface) +# +proc adi_add_port_map {bus phys logic} { + set map [ipx::add_port_map $phys $bus] + set_property "PHYSICAL_NAME" $phys $map + set_property "LOGICAL_NAME" $logic $map +} + +## Infers a new bus interface to an IP. +# +# \param[bus_name] - Bus name +# \param[mode] - Interface mode (master/slave) +# \param[abs_type] - Abstraction type, example: "xilinx.com:interface:axis_rtl:1.0" +# \param[bus_type] - Bus type, example: "xilinx.com:interface:axis:1.0" +# \param[port_maps] - Port map +# +# Port map example:\n +# [list \n +# {"m_axis_ready" "TREADY"}\n +# {"m_axis_valid" "TVALID"}\n +# {"m_axis_data" "TDATA"} ]\n + +proc adi_add_bus {bus_name mode abs_type bus_type port_maps} { + set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] + + set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus + set_property "BUS_TYPE_VLNV" $bus_type $bus + set_property "INTERFACE_MODE" $mode $bus + + foreach port_map $port_maps { + adi_add_port_map $bus {*}$port_map + } +} + +## Add multiple bus interfaces of the same type to an IP. +# +# \param[num] - Number of interfaces +# \param[bus_name_prefix] - Prefix of the name of the interface +# \param[mode] - Interface mode (master/slave) +# \param[abs_type] - Abstraction type, example: "xilinx.com:interface:axis_rtl:1.0" +# \param[bus_type] - Bus type, example: "xilinx.com:interface:axis:1.0" +# \param[port_maps] - Port map, example: [list \n +# {"m_axis_ready" "TREADY"}\n +# {"m_axis_valid" "TVALID"}\n: +# {"m_axis_data" "TDATA"} ]\n +# \param[dependency] - Dependency (e.g "PARAMETER_NAME == 1") ??? {spirit:decode(id('MODELPARAM_VALUE.PARAM_NAME')) == CONST} +# +proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} { + for {set i 0} {$i < $num} {incr i} { + set bus_name [format "%s%d" $bus_name_prefix $i] + set bus [ipx::add_bus_interface $bus_name [ipx::current_core]] + + set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus + set_property "BUS_TYPE_VLNV" $bus_type $bus + set_property "INTERFACE_MODE" $mode $bus + + if {$dependency ne ""} { + set bus_dependency [string map [list "{i}" $i] $dependency] + set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus + } + + foreach port_map $port_maps { + lassign $port_map phys logic width width_dep + set map [ipx::add_port_map $phys $bus] + set_property "PHYSICAL_NAME" $phys $map + set_property "LOGICAL_NAME" $logic $map + set_property "PHYSICAL_RIGHT" [expr $i*$width] $map + set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map + if {$width_dep ne ""} { + set_property "PHYSICAL_RIGHT_RESOLVE_TYPE" "dependent" $map + set_property "PHYSICAL_LEFT_RESOLVE_TYPE" "dependent" $map + set width_dep_r "(($width_dep) * $i)" + set width_dep_l "(($width_dep) * ($i + 1)-1)" + set_property "PHYSICAL_RIGHT_DEPENDENCY" $width_dep_r $map + set_property "PHYSICAL_LEFT_DEPENDENCY" $width_dep_l $map + } + } + } +} + +## Assign clock and reset to an interface bus. +# +# \param[clock_signal_name] - Clock name +# \param[bus_inf_name] - Interface bus name. Note: If multiple interfaces uses +# the same clock, all shall be defined here. (e.g. "s_axis:m_axis") +# \param[reset_signal_name] - Reset signal name +# \param[reset_signal_mode] - Reset mode (master/slave) +# +proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} { + set bus_inf_name_clean [string map {":" "_"} $bus_inf_name] + set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"] + set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]] + set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf + set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf + set_property display_name $clock_inf_name $clock_inf + set clock_map [ipx::add_port_map "CLK" $clock_inf] + set_property physical_name $clock_signal_name $clock_map + + set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf] + set_property value $bus_inf_name $assoc_busif + + if { $reset_signal_name != "" } { + set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf] + set_property value $reset_signal_name $assoc_reset + + set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"] + set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]] + set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf + set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf + set_property display_name $reset_inf_name $reset_inf + set_property interface_mode $reset_signal_mode $reset_inf + set reset_map [ipx::add_port_map "RST" $reset_inf] + set_property physical_name $reset_signal_name $reset_map + + set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf] + if {[string match {*[Nn]} $reset_signal_name] == 1} { + set_property value "ACTIVE_LOW" $reset_polarity + } else { + set_property value "ACTIVE_HIGH" $reset_polarity + } + } +} + +## Defines an IP as the current IP's dependency. +# +# \param[vlnvs] - VLNVs of the instantiated IPs (e.g. "analog.com:user:util_cdc:1.0") +# +proc adi_ip_add_core_dependencies {vlnvs} { + foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] { + foreach vlnv $vlnvs { + ipx::add_subcore $vlnv $file_group + } + } +} + +## Create a project which will be packed as an IP. +# +# \param[ip_name] - IP name +# +proc adi_ip_create {ip_name} { + + global ad_hdl_dir + global ad_ghdl_dir + global required_vivado_version + global IGNORE_VERSION_CHECK + + set VIVADO_VERSION [version -short] + if {$IGNORE_VERSION_CHECK} { + if {[string compare $VIVADO_VERSION $required_vivado_version] != 0} { + puts -nonewline "CRITICAL WARNING: vivado version mismatch; " + puts -nonewline "expected $required_vivado_version, " + puts -nonewline "got $VIVADO_VERSION.\n" + } + } else { + if {[string compare $VIVADO_VERSION $required_vivado_version] != 0} { + puts -nonewline "ERROR: vivado version mismatch; " + puts -nonewline "expected $required_vivado_version, " + puts -nonewline "got $VIVADO_VERSION.\n" + puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n" + exit 2 + } + } + + create_project $ip_name . -force + + ## Load custom message severity definitions + + if {![info exists ::env(ADI_DISABLE_MESSAGE_SUPPRESION)]} { + source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl + } + + set lib_dirs $ad_hdl_dir/library + if {[info exists ::env(ADI_GHDL_DIR)]} { + if {$ad_hdl_dir ne $ad_ghdl_dir} { + lappend lib_dirs $ad_ghdl_dir/library + } + } else { + # puts -nonew-line "INFO: ADI_GHDL_DIR not defined.\n" + } + + set_property ip_repo_paths $lib_dirs [current_fileset] + update_ip_catalog +} + +## Add all source files to the IP's project. +# +# \param[ip_name] - The ip name +# \param[ip_files] - IP files (*.v *.vhd *.xdc) +# +proc adi_ip_files {ip_name ip_files} { + set proj_fileset [get_filesets sources_1] + foreach m_file $ip_files { + if {[file extension $m_file] eq ".xdc"} { + add_files -norecurse -fileset constrs_1 $m_file + } else { + add_files -norecurse -scan_for_includes -fileset $proj_fileset $m_file + } + } + set_property "top" "$ip_name" $proj_fileset +} + +## Pack the IP and set its proprieties. +# +# \param[ip_name] - The ip name +# +proc adi_ip_properties_lite {ip_name} { + + global ad_hdl_dir + global VIVADO_IP_LIBRARY + + ipx::package_project -root_dir . -vendor analog.com -library $VIVADO_IP_LIBRARY -taxonomy /Analog_Devices + + set_property name $ip_name [ipx::current_core] + + set_property vendor_display_name {Analog Devices} [ipx::current_core] + set_property company_url {http://www.analog.com} [ipx::current_core] + + set_property AUTO_FAMILY_SUPPORT_LEVEL level_2 [ipx::current_core] + + ipx::save_core [ipx::current_core] + + ipx::remove_all_bus_interface [ipx::current_core] + set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]] + foreach map $memory_maps { + ipx::remove_memory_map [lindex $map 2] [ipx::current_core] + } + + ipx::update_checksums [ipx::current_core] + ipx::save_core [ipx::current_core] +} + +## Set AXI interface IP proprieties. +# +# \param[ip_name] - The ip name +# +proc adi_ip_properties {ip_name} { + + adi_ip_properties_lite $ip_name + + ipx::infer_bus_interface {\ + s_axi_awvalid \ + s_axi_awaddr \ + s_axi_awprot \ + s_axi_awready \ + s_axi_wvalid \ + s_axi_wdata \ + s_axi_wstrb \ + s_axi_wready \ + s_axi_bvalid \ + s_axi_bresp \ + + s_axi_bready \ + s_axi_arvalid \ + s_axi_araddr \ + s_axi_arprot \ + s_axi_arready \ + s_axi_rvalid \ + s_axi_rdata \ + s_axi_rresp \ + s_axi_rready} \ + xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] + + ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + + set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1] + set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1] + + if {$raddr_width != $waddr_width} { + puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width] + set range 65536 + } else { + if {$raddr_width >= 16} { + set range 65536 + } else { + set range [expr 1 << $raddr_width] + } + } + + ipx::add_memory_map {s_axi} [ipx::current_core] + set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] + ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] + set_property range $range [ipx::get_address_blocks axi_lite \ + -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] + ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core] + ipx::save_core +} + +## Create/overwrite temporary files containing particular build case dependencies. +# +# DO NOT USE FOR: axi_dmac/jesd204/axi_clkgen +# +proc adi_init_bd_tcl {} { + + global auto_set_param_list + global auto_set_param_list_overwritable + set cc [ipx::current_core] + + if { [file exists bd] } { + file delete -force bd + } + file mkdir bd + + set bd_tcl [open "bd/bd.tcl" w] + + puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!" + puts $bd_tcl "proc init {cellpath otherInfo} {" + puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" + puts $bd_tcl "" + set auto_set_param "" + foreach i $auto_set_param_list { + if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { + append auto_set_param " $i \\\n" + } + } + if { $auto_set_param ne "" } { + puts $bd_tcl " bd::mark_propagate_only \$ip \" \\" + regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param + puts $bd_tcl $auto_set_param + } + + set auto_set_overwritable_param "" + foreach i $auto_set_param_list_overwritable { + if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } { + append auto_set_overwritable_param " $i \\\n" + } + } + if { $auto_set_overwritable_param ne "" } { + puts $bd_tcl " bd::mark_propagate_override \$ip \" \\" + regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param + puts $bd_tcl $auto_set_overwritable_param + } + puts $bd_tcl " adi_auto_assign_device_spec \$cellpath" + puts $bd_tcl "}" + puts $bd_tcl "" + puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)" + puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {" + puts $bd_tcl "" + puts $bd_tcl " set ip \[get_bd_cells \$cellpath\]" + puts $bd_tcl " set ip_param_list \[list_property \$ip\]" + puts $bd_tcl " set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]" + puts $bd_tcl "" + puts $bd_tcl " set parent_dir \"../\"" + puts $bd_tcl " for {set x 1} {\$x<=4} {incr x} {" + puts $bd_tcl " set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl" + puts $bd_tcl " if { \[file exists \$linkname\] } {" + puts $bd_tcl " source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl" + puts $bd_tcl " break" + puts $bd_tcl " }" + puts $bd_tcl " append parent_dir \"../\"" + puts $bd_tcl " }" + puts $bd_tcl "" + puts $bd_tcl " # Find predefindes auto assignable parameters" + puts $bd_tcl " foreach i \$auto_set_param_list {" + puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" + puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" + puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" + puts $bd_tcl " }" + puts $bd_tcl " }" + puts $bd_tcl "" + puts $bd_tcl " # Find predefindes auto assignable/overwritable parameters" + puts $bd_tcl " foreach i \$auto_set_param_list_overwritable {" + puts $bd_tcl " if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {" + puts $bd_tcl " set val \[adi_device_spec \$cellpath \$i\]" + puts $bd_tcl " set_property CONFIG.\$i \$val \$ip" + puts $bd_tcl " }" + puts $bd_tcl " }" + puts $bd_tcl "}" + puts $bd_tcl "" + close $bd_tcl + + set proj_fileset [get_filesets sources_1] + add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl" + + set local_mk [open "temporary_case_dependencies.mk" w] + seek $local_mk 0 start + puts $local_mk "CLEAN_TARGET += bd" + puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk" + close $local_mk +} + +## Search after device specific parameters and call the adi_add_device_spec_param +# process with the result. The list of these parameters are defined in +# library/scripts/adi_xilinx_device_info_enc.tcl +# +proc adi_add_auto_fpga_spec_params {} { + + global auto_set_param_list + global auto_set_param_list_overwritable + set cc [ipx::current_core] + + foreach i $auto_set_param_list { + if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { + adi_add_device_spec_param $i + } + } + foreach i $auto_set_param_list_overwritable { + if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} { + adi_add_device_spec_param $i + } + } +} + +## Generate validation properties for a parameter, using predefined ranges or +# set of values (the definition of the ranges can be found in +# library/scripts/adi_xilinx_device_info_enc.tcl). +# +# \param[ip_parameter] - name of the HDL parameter +# +proc adi_add_device_spec_param {ip_param} { + + set cc [ipx::current_core] + + set list_pointer [string tolower $ip_param] + set list_pointer [append list_pointer "_list"] + + global $list_pointer + + # set j 1D list from the original list + foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]} + + # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL) + if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} { + set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \ + "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \ + [ipx::get_user_parameters $ip_param -of_objects $cc] + } else { + set_property -dict [list \ + "value_validation_type" "pairs" \ + "value_validation_pairs" $j ] \ + [ipx::get_user_parameters $ip_param -of_objects $cc] + } + + # FPGA info grup + set info_group_name "FPGA info" + set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet] + if { [string trim $info_group] eq "" } { + set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] + set info_group [ipgui::add_group -name $info_group_name -component $cc \ + -parent $page0 -display_name $info_group_name] + } + + set p [ipgui::get_guiparamspec -name $ip_param -component $cc] + set_property -dict [list "widget" "comboBox" ] $p + ipgui::move_param -component $cc -order 0 $p -parent $info_group +} + +## Define a custom interface bus. +# +# \param[name] - Interface name +# +proc adi_if_define {name} { + + ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0 + ipx::create_bus_definition analog.com interface $name 1.0 + + set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs] + set_property xml_file_name ${name}.xml [ipx::current_busdef] + set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs] + + ipx::save_abstraction_definition [ipx::current_busabs] + ipx::save_bus_definition [ipx::current_busdef] +} + +## Add ports to a custom interface bus. +# +# \param[dir] - Port direction +# \param[width] - Port width +# \param[name] - Port logical name +# \param[type] - Type of the port (default "none") +# +proc adi_if_ports {dir width name {type none}} { + + ipx::add_bus_abstraction_port $name [ipx::current_busabs] + set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]] + set_property master_presence required $m_intf + set_property slave_presence required $m_intf + set_property master_width $width $m_intf + set_property slave_width $width $m_intf + + set m_dir "in" + set s_dir "out" + if {$dir eq "output"} { + set m_dir "out" + set s_dir "in" + } + + set_property master_direction $m_dir $m_intf + set_property slave_direction $s_dir $m_intf + + if {$type ne "none"} { + set_property is_${type} true $m_intf + } + + ipx::save_bus_definition [ipx::current_busdef] + ipx::save_abstraction_definition [ipx::current_busabs] +} + +## Infers a new bus interface to an IP. +# +# \param[if_name] - Interface bus name +# \param[mode] - Type of the interface bus (master/slave) +# \param[name] - Interface bus instance name +# \param[maps] - Mapping of the physical ports +# +proc adi_if_infer_bus {if_name mode name maps} { + + ipx::add_bus_interface $name [ipx::current_core] + set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]] + set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if + set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if + set_property interface_mode $mode $m_bus_if + + foreach map $maps { + set m_maps [regexp -all -inline {\S+} $map] + lassign $m_maps p_name p_map + ipx::add_port_map $p_name $m_bus_if + set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if] + } +} diff --git a/adi_library/scripts/adi_xilinx_device_info_enc.tcl b/adi_library/scripts/adi_xilinx_device_info_enc.tcl new file mode 100644 index 00000000..85035a88 --- /dev/null +++ b/adi_library/scripts/adi_xilinx_device_info_enc.tcl @@ -0,0 +1,176 @@ +############################################################################### +## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# adi_xilinx_device_info_enc.tcl + +variable auto_set_param_list +variable auto_set_param_list_overwritable +variable fpga_series_list +variable fpga_family_list +variable speed_grade_list +variable dev_package_list +variable xcvr_type_list +variable fpga_voltage_list + +# Parameter list for automatic assignament +set auto_set_param_list { \ + DEV_PACKAGE \ + SPEED_GRADE \ + FPGA_FAMILY \ + FPGA_TECHNOLOGY } + +set auto_set_param_list_overwritable { \ + FPGA_VOLTAGE \ + XCVR_TYPE } + +# List for automatically assigned parameter values and encoded values +# The list name must be the parameter name (lowercase), appending "_list" to it +set fpga_technology_list { \ + { Unknown 0 } \ + { 7series 1 } \ + { ultrascale 2 } \ + { ultrascale+ 3 } \ + { versal 4 }} + +set fpga_family_list { \ + { Unknown 0 } \ + { artix 1 } \ + { kintex 2 } \ + { virtex 3 } \ + { zynq 4 } \ + { versalprime 5 } \ + { versalaicore 6 } \ + } + +set speed_grade_list { \ + { Unknown 0 } \ + { -1 10 } \ + { -1L 11 } \ + { -1H 12 } \ + { -1HV 13 } \ + { -1LV 14 } \ + { -2 20 } \ + { -2L 21 } \ + { -2LV 22 } \ + { -2MP 23 } \ + { -2LVC 24 } \ + { -2LVI 25 } \ + { -3 30 }} + +set dev_package_list { \ + { Unknown 0 } \ + { rf 1 } \ + { fl 2 } \ + { ff 3 } \ + { fb 4 } \ + { hc 5 } \ + { fh 6 } \ + { cs 7 } \ + { cp 8 } \ + { ft 9 } \ + { fg 10 } \ + { sb 11 } \ + { rb 12 } \ + { rs 13 } \ + { cl 14 } \ + { sf 15 } \ + { ba 16 } \ + { fa 17 } \ + { fs 18 } \ + { fi 19 } \ + { vs 20 }} + + +set xcvr_type_list { \ + { Unknown 0 } \ + { GTPE2_NOT_SUPPORTED 1 } \ + { GTXE2 2 } \ + { GTHE2_NOT_SUPPORTED 3 } \ + { GTZE2_NOT_SUPPORTED 4 } \ + { GTHE3 5 } \ + { GTYE3_NOT_SUPPORTED 6 } \ + { GTRE4_NOT_SUPPORTED 7 } \ + { GTHE4 8 } \ + { GTYE4 9 } \ + { GTME4_NOT_SUPPORTED 10}} + +set fpga_voltage_list {0 5000} ;# 0 to 5000mV + + +## *************************************************************************** + +proc adi_device_spec {cellpath param} { + + set list_pointer [string tolower $param] + set list_pointer [append list_pointer "_list"] + + upvar 1 $list_pointer $list_pointer + + set ip [get_bd_cells $cellpath] + set part [get_property PART [current_project]] + + switch -regexp -- $param { + FPGA_TECHNOLOGY { + switch -regexp -- $part { + ^xc7 {set series_name 7series} + ^xczu {set series_name ultrascale+} + ^x.zu..?p {set series_name ultrascale+} + ^xck26 {set series_name ultrascale+} + ^xc.u {set series_name ultrascale } + ^xcv[ecmph] {set series_name versal} + default { + puts "Undefined fpga technology for \"$part\"!" + exit -1 + } + } + return "$series_name" + } + FPGA_FAMILY { + set fpga_family [get_property FAMILY $part] + foreach i $fpga_family_list { + regexp ^[lindex $i 0] $fpga_family matched + } + return "$matched" + } + SPEED_GRADE { + set speed_grade [get_property SPEED $part] + return "$speed_grade" + } + DEV_PACKAGE { + set dev_package [get_property PACKAGE $part] + foreach i $dev_package_list { + regexp ^[lindex $i 0] $dev_package matched + } + return "$matched" + } + XCVR_TYPE { + set matched "" + set dev_transcivers "none" + foreach x [list_property $part] { + regexp ^GT..._TRANSCEIVERS $x dev_transcivers + } + foreach i $xcvr_type_list { + regexp ^[lindex $i 0] $dev_transcivers matched + } + if { $matched eq "" } { + puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!" + } + return "$matched" + } + FPGA_VOLTAGE { + set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part] + set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val) + + return "$fpga_voltage" + } + default { + puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!" + } + } +} + + +## *************************************************************************** +## *************************************************************************** diff --git a/adi_library/scripts/library.mk b/adi_library/scripts/library.mk new file mode 100644 index 00000000..ddfc29d5 --- /dev/null +++ b/adi_library/scripts/library.mk @@ -0,0 +1,107 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +## SPDX short identifier: BSD-1-Clause +#################################################################################### + +# Assumes this file is in library/scripts/library.mk +HDL_LIBRARY_PATH := $(subst scripts/library.mk,,$(lastword $(MAKEFILE_LIST))) + +include $(HDL_LIBRARY_PATH)../quiet.mk + +CASE_INCLUDE := $(wildcard temporary_case_dependencies.mk) +ifneq ($(CASE_INCLUDE),) + include temporary_case_dependencies.mk +endif + +VIVADO := vivado -mode batch -source + +CLEAN_TARGET += *.cache +CLEAN_TARGET += *.data +CLEAN_TARGET += *.xpr +CLEAN_TARGET += *.log +CLEAN_TARGET += component.xml +CLEAN_TARGET += *.jou +CLEAN_TARGET += xgui +CLEAN_TARGET += gui +CLEAN_TARGET += *.runs +CLEAN_TARGET += *.gen +CLEAN_TARGET += *.ip_user_files +CLEAN_TARGET += *.srcs +CLEAN_TARGET += *.hw +CLEAN_TARGET += *.sim +CLEAN_TARGET += .Xil +CLEAN_TARGET += .timestamp_intel +CLEAN_TARGET += *.hbs +CLEAN_TARGET += tb/*.log +CLEAN_TARGET += tb/*.xml +CLEAN_TARGET += tb/*.jou +CLEAN_TARGET += tb/*.dir +CLEAN_TARGET += tb/*.pb +CLEAN_TARGET += tb/*.vcd +CLEAN_TARGET += tb/*.wdb +CLEAN_TARGET += tb/dcv. +CLEAN_TARGET += tb/vsim.wlf +CLEAN_TARGET += tb/work +CLEAN_TARGET += tb/vcd +CLEAN_TARGET += tb/run +CLEAN_TARGET += tb/libraries +CLEAN_TARGET += tb/.Xil +CLEAN_TARGET += tb/xsim_gui_cmd.tcl +CLEAN_TARGET += tb/libraries + +GENERIC_DEPS += $(HDL_LIBRARY_PATH)../scripts/adi_env.tcl + +.PHONY: all intel xilinx clean clean-all + +all: intel xilinx + +clean: clean-all + +clean-all: + $(call clean, \ + $(CLEAN_TARGET) .lock, \ + $(HL)$(LIBRARY_NAME)$(NC) library) + +ifneq ($(INTEL_DEPS),) + +INTEL_DEPS += $(GENERIC_DEPS) +INTEL_DEPS += $(HDL_LIBRARY_PATH)scripts/adi_ip_intel.tcl +_INTEL_LIB_DEPS = $(foreach dep,$(INTEL_LIB_DEPS),$(HDL_LIBRARY_PATH)$(dep)/.timestamp_intel) + +intel: .timestamp_intel + +.timestamp_intel: $(INTEL_DEPS) $(_INTEL_LIB_DEPS) + touch $@ + +$(_INTEL_LIB_DEPS): + $(MAKE) -C $(dir $@) intel + +endif + +ifneq ($(XILINX_DEPS),) + +XILINX_DEPS += $(GENERIC_DEPS) +XILINX_DEPS += $(HDL_LIBRARY_PATH)scripts/adi_ip_xilinx.tcl +_XILINX_LIB_DEPS = $(foreach dep,$(XILINX_LIB_DEPS),$(HDL_LIBRARY_PATH)$(dep)/component.xml) +_XILINX_INTF_DEPS = $(foreach dep,$(XILINX_INTERFACE_DEPS),$(HDL_LIBRARY_PATH)$(dep)) + +xilinx: component.xml + +.DELETE_ON_ERROR: + +component.xml: $(XILINX_DEPS) $(_XILINX_INTF_DEPS) $(_XILINX_LIB_DEPS) + -rm -rf $(CLEAN_TARGET) + $(call build, \ + $(VIVADO) $(LIBRARY_NAME)_ip.tcl, \ + $(LIBRARY_NAME)_ip.log, \ + $(HL)$(LIBRARY_NAME)$(NC) library) + +$(_XILINX_INTF_DEPS): + $(MAKE) -C $(dir $@) $(notdir $@) + +$(_XILINX_LIB_DEPS): + flock $(dir $@).lock -c "$(MAKE) -C $(dir $@) xilinx"; exit $$? + +%.xml: + $(MAKE) -C $(dir $@) $(notdir $@) +endif diff --git a/adi_library/spi_engine/axi_spi_engine/Makefile b/adi_library/spi_engine/axi_spi_engine/Makefile new file mode 100644 index 00000000..33588929 --- /dev/null +++ b/adi_library/spi_engine/axi_spi_engine/Makefile @@ -0,0 +1,34 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_spi_engine + +GENERIC_DEPS += ../../common/ad_rst.v +GENERIC_DEPS += ../../common/up_axi.v +GENERIC_DEPS += axi_spi_engine.v + +XILINX_DEPS += ../../xilinx/common/ad_rst_constr.xdc +XILINX_DEPS += axi_spi_engine_constr.ttcl +XILINX_DEPS += axi_spi_engine_ip.tcl + +XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml +XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml +XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl.xml +XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml + +XILINX_LIB_DEPS += util_axis_fifo +XILINX_LIB_DEPS += util_cdc + +INTEL_DEPS += ../../common/ad_mem.v +INTEL_DEPS += ../../intel/common/up_rst_constr.sdc +INTEL_DEPS += ../../util_axis_fifo/util_axis_fifo.v +INTEL_DEPS += ../../util_axis_fifo/util_axis_fifo_address_generator.v +INTEL_DEPS += ../../util_cdc/sync_bits.v +INTEL_DEPS += ../../util_cdc/sync_gray.v +INTEL_DEPS += axi_spi_engine_constr.sdc +INTEL_DEPS += axi_spi_engine_hw.tcl + +include ../../scripts/library.mk diff --git a/adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v b/adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v new file mode 100644 index 00000000..77e3d9b4 --- /dev/null +++ b/adi_library/spi_engine/axi_spi_engine/axi_spi_engine.v @@ -0,0 +1,653 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_spi_engine #( + + parameter CMD_FIFO_ADDRESS_WIDTH = 4, + parameter SYNC_FIFO_ADDRESS_WIDTH = 4, + parameter SDO_FIFO_ADDRESS_WIDTH = 5, + parameter SDI_FIFO_ADDRESS_WIDTH = 5, + parameter MM_IF_TYPE = 0, + parameter ASYNC_SPI_CLK = 0, + parameter NUM_OFFLOAD = 0, + parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = 4, + parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4, + parameter ID = 0, + parameter [15:0] DATA_WIDTH = 8, + parameter [ 7:0] NUM_OF_SDI = 1, + parameter CFG_INFO_0 = 0, + parameter CFG_INFO_1 = 0, + parameter CFG_INFO_2 = 0, + parameter CFG_INFO_3 = 0 +) ( + + // Slave AXI interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + output s_axi_awready, + input [2:0] s_axi_awprot, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + output s_axi_arready, + input [2:0] s_axi_arprot, + output s_axi_rvalid, + input s_axi_rready, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + + // up interface + + input up_clk, + input up_rstn, + input up_wreq, + input [13:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [13:0] up_raddr, + output [31:0] up_rdata, + output up_rack, + + output reg irq, + + // SPI signals + + input spi_clk, + + output spi_resetn, + + input cmd_ready, + output cmd_valid, + output [15:0] cmd_data, + + input sdo_data_ready, + output sdo_data_valid, + output [(DATA_WIDTH-1):0] sdo_data, + + output sdi_data_ready, + input sdi_data_valid, + input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data, + + output sync_ready, + input sync_valid, + input [7:0] sync_data, + + // Offload ctrl signals + + output offload0_cmd_wr_en, + output [15:0] offload0_cmd_wr_data, + + output offload0_sdo_wr_en, + output [(DATA_WIDTH-1):0] offload0_sdo_wr_data, + + output offload0_mem_reset, + output offload0_enable, + input offload0_enabled, + + output offload_sync_ready, + input offload_sync_valid, + input [7:0] offload_sync_data +); + + localparam PCORE_VERSION = 'h010071; + localparam S_AXI = 0; + localparam UP_FIFO = 1; + + wire clk; + wire rstn; + + wire [CMD_FIFO_ADDRESS_WIDTH-1:0] cmd_fifo_room; + wire cmd_fifo_almost_empty; + wire up_cmd_fifo_almost_empty; + + wire [15:0] cmd_fifo_in_data; + wire cmd_fifo_in_ready; + wire cmd_fifo_in_valid; + + wire [SDO_FIFO_ADDRESS_WIDTH-1:0] sdo_fifo_room; + wire sdo_fifo_almost_empty; + wire up_sdo_fifo_almost_empty; + + wire [(DATA_WIDTH-1):0] sdo_fifo_in_data; + wire sdo_fifo_in_ready; + wire sdo_fifo_in_valid; + + wire sdi_fifo_out_data_msb_s; + wire [SDI_FIFO_ADDRESS_WIDTH-1:0] sdi_fifo_level; + wire sdi_fifo_almost_full; + wire up_sdi_fifo_almost_full; + + wire [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_fifo_out_data; + wire sdi_fifo_out_ready; + wire sdi_fifo_out_valid; + + wire [7:0] sync_fifo_data; + wire sync_fifo_valid; + + wire [7:0] offload_sync_fifo_data; + wire offload_sync_fifo_valid; + + reg up_sw_reset = 1'b1; + wire up_sw_resetn = ~up_sw_reset; + + reg [31:0] up_rdata_ff = 'd0; + reg up_wack_ff = 1'b0; + reg up_rack_ff = 1'b0; + wire up_wreq_s; + wire up_rreq_s; + wire [31:0] up_wdata_s; + wire [13:0] up_waddr_s; + wire [13:0] up_raddr_s; + + // Scratch register + reg [31:0] up_scratch = 'h00; + + reg [7:0] sync_id = 'h00; + reg sync_id_pending = 1'b0; + + reg [7:0] offload_sync_id = 'h00; + reg offload_sync_id_pending = 1'b0; + + generate if (MM_IF_TYPE == S_AXI) begin + + // assign clock and reset + + assign clk = s_axi_aclk; + assign rstn = s_axi_aresetn; + + // interface wrapper + + up_axi #( + .AXI_ADDRESS_WIDTH (16) + ) i_up_axi ( + .up_rstn(rstn), + .up_clk(clk), + .up_axi_awvalid(s_axi_awvalid), + .up_axi_awaddr(s_axi_awaddr), + .up_axi_awready(s_axi_awready), + .up_axi_wvalid(s_axi_wvalid), + .up_axi_wdata(s_axi_wdata), + .up_axi_wstrb(s_axi_wstrb), + .up_axi_wready(s_axi_wready), + .up_axi_bvalid(s_axi_bvalid), + .up_axi_bresp(s_axi_bresp), + .up_axi_bready(s_axi_bready), + .up_axi_arvalid(s_axi_arvalid), + .up_axi_araddr(s_axi_araddr), + .up_axi_arready(s_axi_arready), + .up_axi_rvalid(s_axi_rvalid), + .up_axi_rresp(s_axi_rresp), + .up_axi_rdata(s_axi_rdata), + .up_axi_rready(s_axi_rready), + .up_wreq(up_wreq_s), + .up_waddr(up_waddr_s), + .up_wdata(up_wdata_s), + .up_wack(up_wack_ff), + .up_rreq(up_rreq_s), + .up_raddr(up_raddr_s), + .up_rdata(up_rdata_ff), + .up_rack(up_rack_ff)); + + assign up_rdata = 32'b0; + assign up_rack = 1'b0; + assign up_wack = 1'b0; + + end + endgenerate + + generate if (MM_IF_TYPE == UP_FIFO) begin + + // assign clock and reset + + assign clk = up_clk; + assign rstn = up_rstn; + + assign up_wreq_s = up_wreq; + assign up_waddr_s = up_waddr; + assign up_wdata_s = up_wdata; + assign up_wack = up_wack_ff; + assign up_rreq_s = up_rreq; + assign up_raddr_s = up_raddr; + assign up_rdata = up_rdata_ff; + assign up_rack = up_rack_ff; + + end + endgenerate + + // IRQ handling + reg [4:0] up_irq_mask = 5'h0; + wire [4:0] up_irq_source; + wire [4:0] up_irq_pending; + + assign up_irq_source = { + offload_sync_id_pending, + sync_id_pending, + up_sdi_fifo_almost_full, + up_sdo_fifo_almost_empty, + up_cmd_fifo_almost_empty + }; + + assign up_irq_pending = up_irq_mask & up_irq_source; + + always @(posedge clk) begin + if (rstn == 1'b0) + irq <= 1'b0; + else + irq <= |up_irq_pending; + end + + always @(posedge clk) begin + if (rstn == 1'b0) begin + up_wack_ff <= 1'b0; + up_scratch <= 'h00; + up_sw_reset <= 1'b1; + end else begin + up_wack_ff <= up_wreq_s; + if (up_wreq_s) begin + case (up_waddr_s) + 8'h02: up_scratch <= up_wdata_s; + 8'h10: up_sw_reset <= up_wdata_s; + endcase + end + end + end + + reg offload0_enable_reg; + reg offload0_mem_reset_reg; + wire offload0_enabled_s; + + // the software reset should reset all the registers + always @(posedge clk) begin + if (up_sw_resetn == 1'b0) begin + up_irq_mask <= 'h00; + offload0_enable_reg <= 1'b0; + offload0_mem_reset_reg <= 1'b0; + end else begin + if (up_wreq_s) begin + case (up_waddr_s) + 8'h20: up_irq_mask <= up_wdata_s; + 8'h40: offload0_enable_reg <= up_wdata_s[0]; + 8'h42: offload0_mem_reset_reg <= up_wdata_s[0]; + endcase + end + end + end + + always @(posedge clk) begin + if (rstn == 1'b0) begin + up_rack_ff <= 'd0; + end else begin + up_rack_ff <= up_rreq_s; + end + end + + generate + if (NUM_OF_SDI > 1) begin + // Only the first two SDI data can be recovered through AXI regmap + assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data[DATA_WIDTH+:DATA_WIDTH]; + end else begin + assign sdi_fifo_out_data_msb_s = sdi_fifo_out_data; + end + endgenerate + + always @(posedge clk) begin + case (up_raddr_s) + 8'h00: up_rdata_ff <= PCORE_VERSION; + 8'h01: up_rdata_ff <= ID; + 8'h02: up_rdata_ff <= up_scratch; + 8'h03: up_rdata_ff <= {8'b0, NUM_OF_SDI, DATA_WIDTH}; + 8'h10: up_rdata_ff <= up_sw_reset; + 8'h20: up_rdata_ff <= up_irq_mask; + 8'h21: up_rdata_ff <= up_irq_pending; + 8'h22: up_rdata_ff <= up_irq_source; + 8'h30: up_rdata_ff <= sync_id; + 8'h31: up_rdata_ff <= offload_sync_id; + 8'h34: up_rdata_ff <= cmd_fifo_room; + 8'h35: up_rdata_ff <= sdo_fifo_room; + 8'h36: up_rdata_ff <= (sdi_fifo_out_valid == 1) ? sdi_fifo_level + 1 : sdi_fifo_level; /* beacuse of first-word-fall-through */ + 8'h3a: up_rdata_ff <= sdi_fifo_out_data[DATA_WIDTH-1:0]; + 8'h3b: up_rdata_ff <= sdi_fifo_out_data_msb_s; /* store SDI's 32 bits MSB, if exists */ + 8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */ + 8'h40: up_rdata_ff <= {offload0_enable_reg}; + 8'h41: up_rdata_ff <= {offload0_enabled_s}; + 8'h80: up_rdata_ff <= CFG_INFO_0; + 8'h81: up_rdata_ff <= CFG_INFO_1; + 8'h82: up_rdata_ff <= CFG_INFO_2; + 8'h83: up_rdata_ff <= CFG_INFO_3; + default: up_rdata_ff <= 'h00; + endcase + end + + always @(posedge clk) begin + if (up_sw_resetn == 1'b0) begin + sync_id <= 'h00; + sync_id_pending <= 1'b0; + end else begin + if (sync_fifo_valid == 1'b1) begin + sync_id <= sync_fifo_data; + sync_id_pending <= 1'b1; + end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[3] == 1'b1) begin + sync_id_pending <= 1'b0; + end + end + end + + always @(posedge clk) begin + if (up_sw_resetn == 1'b0) begin + offload_sync_id <= 'h00; + offload_sync_id_pending <= 1'b0; + end else begin + if (offload_sync_fifo_valid == 1'b1) begin + offload_sync_id <= offload_sync_fifo_data; + offload_sync_id_pending <= 1'b1; + end else if (up_wreq_s == 1'b1 && up_waddr_s == 8'h21 && up_wdata_s[4] == 1'b1) begin + offload_sync_id_pending <= 1'b0; + end + end + end + + generate if (ASYNC_SPI_CLK) begin + + wire spi_reset; + ad_rst i_spi_resetn ( + .rst_async(up_sw_reset), + .clk(spi_clk), + .rst(spi_reset), + .rstn()); + assign spi_resetn = ~spi_reset; + end else begin + assign spi_resetn = ~up_sw_reset; + end + endgenerate + + assign cmd_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h38; + assign cmd_fifo_in_data = up_wdata_s[15:0]; + + util_axis_fifo #( + .DATA_WIDTH(16), + .ADDRESS_WIDTH(CMD_FIFO_ADDRESS_WIDTH), + .ASYNC_CLK(ASYNC_SPI_CLK), + .M_AXIS_REGISTERED(0), + .ALMOST_EMPTY_THRESHOLD(1), + .ALMOST_FULL_THRESHOLD(1) + ) i_cmd_fifo ( + .s_axis_aclk(clk), + .s_axis_aresetn(up_sw_resetn), + .s_axis_ready(cmd_fifo_in_ready), + .s_axis_valid(cmd_fifo_in_valid), + .s_axis_data(cmd_fifo_in_data), + .s_axis_room(cmd_fifo_room), + .s_axis_tlast(1'b0), + .s_axis_full(), + .s_axis_almost_full(), + .m_axis_aclk(spi_clk), + .m_axis_aresetn(spi_resetn), + .m_axis_ready(cmd_ready), + .m_axis_valid(cmd_valid), + .m_axis_data(cmd_data), + .m_axis_tlast(), + .m_axis_empty(), + .m_axis_almost_empty(cmd_fifo_almost_empty), + .m_axis_level()); + + assign sdo_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h39; + assign sdo_fifo_in_data = up_wdata_s[(DATA_WIDTH-1):0]; + + util_axis_fifo #( + .DATA_WIDTH(DATA_WIDTH), + .ASYNC_CLK(ASYNC_SPI_CLK), + .ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH), + .M_AXIS_REGISTERED(0), + .ALMOST_EMPTY_THRESHOLD(1), + .ALMOST_FULL_THRESHOLD(1) + ) i_sdo_fifo ( + .s_axis_aclk(clk), + .s_axis_aresetn(up_sw_resetn), + .s_axis_ready(sdo_fifo_in_ready), + .s_axis_valid(sdo_fifo_in_valid), + .s_axis_data(sdo_fifo_in_data), + .s_axis_room(sdo_fifo_room), + .s_axis_tlast(1'b0), + .s_axis_full(), + .s_axis_almost_full(), + .m_axis_aclk(spi_clk), + .m_axis_aresetn(spi_resetn), + .m_axis_ready(sdo_data_ready), + .m_axis_valid(sdo_data_valid), + .m_axis_data(sdo_data), + .m_axis_tlast(), + .m_axis_level(), + .m_axis_empty(), + .m_axis_almost_empty(sdo_fifo_almost_empty)); + + assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a; + + util_axis_fifo #( + .DATA_WIDTH(NUM_OF_SDI * DATA_WIDTH), + .ASYNC_CLK(ASYNC_SPI_CLK), + .ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH), + .M_AXIS_REGISTERED(0), + .ALMOST_EMPTY_THRESHOLD(1), + .ALMOST_FULL_THRESHOLD(31) + ) i_sdi_fifo ( + .s_axis_aclk(spi_clk), + .s_axis_aresetn(spi_resetn), + .s_axis_ready(sdi_data_ready), + .s_axis_valid(sdi_data_valid), + .s_axis_data(sdi_data), + .s_axis_room(), + .s_axis_tlast(), + .s_axis_full(), + .s_axis_almost_full(sdi_fifo_almost_full), + .m_axis_aclk(clk), + .m_axis_aresetn(up_sw_resetn), + .m_axis_ready(sdi_fifo_out_ready), + .m_axis_valid(sdi_fifo_out_valid), + .m_axis_data(sdi_fifo_out_data), + .m_axis_tlast(), + .m_axis_level(sdi_fifo_level), + .m_axis_empty(), + .m_axis_almost_empty()); + + generate if (ASYNC_SPI_CLK) begin + + // synchronization FIFO for the SYNC interface + util_axis_fifo #( + .DATA_WIDTH(8), + .ASYNC_CLK(ASYNC_SPI_CLK), + .ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH), + .M_AXIS_REGISTERED(0) + ) i_sync_fifo ( + .s_axis_aclk(spi_clk), + .s_axis_aresetn(spi_resetn), + .s_axis_ready(sync_ready), + .s_axis_valid(sync_valid), + .s_axis_data(sync_data), + .s_axis_room(), + .s_axis_full(), + .m_axis_aclk(clk), + .m_axis_aresetn(up_sw_resetn), + .m_axis_ready(1'b1), + .m_axis_valid(sync_fifo_valid), + .m_axis_data(sync_fifo_data), + .m_axis_level(), + .m_axis_empty()); + + // synchronization FIFO for the offload command interface + wire up_offload0_cmd_wr_en_s; + wire [15:0] up_offload0_cmd_wr_data_s; + + util_axis_fifo #( + .DATA_WIDTH(16), + .ASYNC_CLK(ASYNC_SPI_CLK), + .ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH), + .M_AXIS_REGISTERED(0) + ) i_offload_cmd_fifo ( + .s_axis_aclk(clk), + .s_axis_aresetn(up_sw_resetn), + .s_axis_ready(), + .s_axis_valid(up_offload0_cmd_wr_en_s), + .s_axis_data(up_offload0_cmd_wr_data_s), + .s_axis_room(), + .s_axis_full(), + .m_axis_aclk(spi_clk), + .m_axis_aresetn(spi_resetn), + .m_axis_ready(1'b1), + .m_axis_valid(offload0_cmd_wr_en), + .m_axis_data(offload0_cmd_wr_data), + .m_axis_level(), + .m_axis_empty()); + + assign up_offload0_cmd_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h44; + assign up_offload0_cmd_wr_data_s = up_wdata_s[15:0]; + + // synchronization FIFO for the offload SDO interface + wire up_offload0_sdo_wr_en_s; + wire [DATA_WIDTH-1:0] up_offload0_sdo_wr_data_s; + + util_axis_fifo #( + .DATA_WIDTH(DATA_WIDTH), + .ASYNC_CLK(ASYNC_SPI_CLK), + .ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH), + .M_AXIS_REGISTERED(0) + ) i_offload_sdo_fifo ( + .s_axis_aclk(clk), + .s_axis_aresetn(up_sw_resetn), + .s_axis_ready(), + .s_axis_valid(up_offload0_sdo_wr_en_s), + .s_axis_data(up_offload0_sdo_wr_data_s), + .s_axis_room(), + .s_axis_full(), + .m_axis_aclk(spi_clk), + .m_axis_aresetn(spi_resetn), + .m_axis_ready(1'b1), + .m_axis_valid(offload0_sdo_wr_en), + .m_axis_data(offload0_sdo_wr_data), + .m_axis_level(), + .m_axis_empty()); + + assign up_offload0_sdo_wr_en_s = up_wreq_s == 1'b1 && up_waddr_s == 8'h45; + assign up_offload0_sdo_wr_data_s = up_wdata_s[DATA_WIDTH-1:0]; + + // synchronization FIFO for the Offload SYNC interface + util_axis_fifo #( + .DATA_WIDTH(8), + .ASYNC_CLK(ASYNC_SPI_CLK), + .ADDRESS_WIDTH(SYNC_FIFO_ADDRESS_WIDTH), + .M_AXIS_REGISTERED(0) + ) i_offload_sync_fifo ( + .s_axis_aclk(spi_clk), + .s_axis_aresetn(spi_resetn), + .s_axis_ready(offload_sync_ready), + .s_axis_valid(offload_sync_valid), + .s_axis_data(offload_sync_data), + .s_axis_room(), + .s_axis_full(), + .m_axis_aclk(clk), + .m_axis_aresetn(up_sw_resetn), + .m_axis_ready(1'b1), + .m_axis_valid(offload_sync_fifo_valid), + .m_axis_data(offload_sync_fifo_data), + .m_axis_level(), + .m_axis_empty()); + + end else begin /* ASYNC_SPI_CLK == 0 */ + + assign sync_fifo_valid = sync_valid; + assign sync_fifo_data = sync_data; + assign sync_ready = 1'b1; + + assign offload0_cmd_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h44; + assign offload0_cmd_wr_data = up_wdata_s[15:0]; + + assign offload0_sdo_wr_en = up_wreq_s == 1'b1 && up_waddr_s == 8'h45; + assign offload0_sdo_wr_data = up_wdata_s[DATA_WIDTH-1:0]; + + assign offload_sync_fifo_valid = offload_sync_valid; + assign offload_sync_fifo_data = offload_sync_data; + assign offload_sync_ready = 1'b1; + + end + endgenerate + + sync_bits #( + .NUM_OF_BITS (1), + .ASYNC_CLK (ASYNC_SPI_CLK) + ) i_offload_enable_sync ( + .in_bits (offload0_enable_reg), + .out_resetn (spi_resetn), + .out_clk (spi_clk), + .out_bits (offload0_enable)); + + sync_bits #( + .NUM_OF_BITS (1), + .ASYNC_CLK (ASYNC_SPI_CLK) + ) i_offload_enabled_sync ( + .in_bits (offload0_enabled), + .out_resetn (up_sw_resetn), + .out_clk (clk), + .out_bits (offload0_enabled_s)); + + sync_bits #( + .NUM_OF_BITS (1), + .ASYNC_CLK (ASYNC_SPI_CLK) + ) i_offload_mem_reset_sync ( + .in_bits (offload0_mem_reset_reg), + .out_resetn (spi_resetn), + .out_clk (spi_clk), + .out_bits (offload0_mem_reset)); + + sync_bits #( + .NUM_OF_BITS (3), + .ASYNC_CLK (ASYNC_SPI_CLK) + ) i_fifo_status ( + .in_bits ({cmd_fifo_almost_empty, sdi_fifo_almost_full, sdo_fifo_almost_empty}), + .out_resetn (up_sw_resetn), + .out_clk (clk), + .out_bits ({up_cmd_fifo_almost_empty, up_sdi_fifo_almost_full, up_sdo_fifo_almost_empty})); + +endmodule diff --git a/adi_library/spi_engine/axi_spi_engine/axi_spi_engine.xpr b/adi_library/spi_engine/axi_spi_engine/axi_spi_engine.xpr new file mode 100644 index 00000000..6a23ed21 --- /dev/null +++ b/adi_library/spi_engine/axi_spi_engine/axi_spi_engine.xpr @@ -0,0 +1,420 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/spi_engine/axi_spi_engine/axi_spi_engine_constr.sdc b/adi_library/spi_engine/axi_spi_engine/axi_spi_engine_constr.sdc new file mode 100644 index 00000000..a8fc8c6a --- /dev/null +++ b/adi_library/spi_engine/axi_spi_engine/axi_spi_engine_constr.sdc @@ -0,0 +1,8 @@ +############################################################################### +## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_false_path \ + -to [get_registers *cdc_sync_stage1*] + diff --git a/adi_library/spi_engine/axi_spi_engine/axi_spi_engine_constr.ttcl b/adi_library/spi_engine/axi_spi_engine/axi_spi_engine_constr.ttcl new file mode 100644 index 00000000..31703234 --- /dev/null +++ b/adi_library/spi_engine/axi_spi_engine/axi_spi_engine_constr.ttcl @@ -0,0 +1,35 @@ +############################################################################### +## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +# SPDX short identifier: ADIBSD +############################################################################### + +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName [ttcl_add $ComponentName "_constr"] :> +<: setFileExtension ".xdc" :> +<: setFileProcessingOrder late :> +<: set async_spi_clk [getBooleanValue "ASYNC_SPI_CLK"] :> + +<: if { $async_spi_clk } { :> + +set_property ASYNC_REG TRUE \ + [get_cells -quiet -hierarchical *cdc_sync_stage1_reg*] \ + [get_cells -quiet -hierarchical *cdc_sync_stage2_reg*] + +set_false_path -quiet \ + -from [get_cells -quiet -hierarchical -filter {NAME =~ *i_address_gray/*cdc_sync_stage0_reg* && IS_SEQUENTIAL}] \ + -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_address_gray/*cdc_sync_stage1_reg* && IS_SEQUENTIAL}] + +set_false_path -quiet \ + -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_enable_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}] + +set_false_path -quiet \ + -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_enabled_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}] + +set_false_path -quiet \ + -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_mem_reset_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}] + +set_false_path -quiet \ + -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_fifo_status/cdc_sync_stage1_reg* && IS_SEQUENTIAL}] + +<: } :> diff --git a/adi_library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl b/adi_library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl new file mode 100644 index 00000000..329cc3dc --- /dev/null +++ b/adi_library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl @@ -0,0 +1,188 @@ +############################################################################### +## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +source ../../../scripts/adi_env.tcl +source ../../scripts/adi_ip_intel.tcl + +ad_ip_create axi_spi_engine {AXI SPI Engine} p_elaboration +ad_ip_files axi_spi_engine [list\ + $ad_hdl_dir/library/util_axis_fifo/util_axis_fifo.v \ + $ad_hdl_dir/library/util_axis_fifo/util_axis_fifo_address_generator.v \ + $ad_hdl_dir/library/util_cdc/sync_bits.v \ + $ad_hdl_dir/library/util_cdc/sync_gray.v \ + $ad_hdl_dir/library/common/ad_mem.v \ + $ad_hdl_dir/library/common/up_axi.v \ + $ad_hdl_dir/library/common/ad_rst.v \ + $ad_hdl_dir/library/intel/common/up_rst_constr.sdc \ + axi_spi_engine_constr.sdc \ + axi_spi_engine.v] + +# parameters + +ad_ip_parameter CMD_FIFO_ADDRESS_WIDTH INTEGER 4 +ad_ip_parameter SYNC_FIFO_ADDRESS_WIDTH INTEGER 4 +ad_ip_parameter SDO_FIFO_ADDRESS_WIDTH INTEGER 5 +ad_ip_parameter SDI_FIFO_ADDRESS_WIDTH INTEGER 5 +ad_ip_parameter MM_IF_TYPE INTEGER 1 +ad_ip_parameter ASYNC_SPI_CLK INTEGER 0 +ad_ip_parameter NUM_OFFLOAD INTEGER 1 +ad_ip_parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH INTEGER 4 +ad_ip_parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH INTEGER 4 +ad_ip_parameter ID INTEGER 0 +ad_ip_parameter DATA_WIDTH INTEGER 8 +ad_ip_parameter NUM_OF_SDI INTEGER 1 + +proc p_elaboration {} { + + # read parameters + + set mm_if_type [get_parameter_value "MM_IF_TYPE"] + + set num_of_sdi [get_parameter_value NUM_OF_SDI] + set data_width [get_parameter_value DATA_WIDTH] + + # interrupt + + add_interface interrupt_sender interrupt end + add_interface_port interrupt_sender irq irq Output 1 + + # Microprocessor interface + + ad_interface clock up_clk input 1 + ad_interface reset up_rstn input 1 if_up_clk + ad_interface signal up_wreq input 1 + ad_interface signal up_wack output 1 + ad_interface signal up_waddr input 14 + ad_interface signal up_wdata input 32 + ad_interface signal up_rreq input 1 + ad_interface signal up_rack output 1 + ad_interface signal up_raddr output 14 + ad_interface signal up_rdata output 32 + + # AXI Memory Mapped interface + + ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 16 + + set disabled_intfs {} + if {$mm_if_type} { + + # uProcessor interface active for regmap, deactivate S_AXI + lappend disabled_intfs s_axi + + set_port_property s_axi_aclk termination true + set_port_property s_axi_aresetn termination true + set_port_property s_axi_aresetn termination_value 1 + set_port_property s_axi_awvalid termination true + set_port_property s_axi_awaddr termination true + set_port_property s_axi_awprot termination true + set_port_property s_axi_wvalid termination true + set_port_property s_axi_wdata termination true + set_port_property s_axi_wstrb termination true + set_port_property s_axi_bready termination true + set_port_property s_axi_arvalid termination true + set_port_property s_axi_araddr termination true + set_port_property s_axi_arprot termination true + set_port_property s_axi_rready termination true + + } else { + + set_interface_property interrupt_sender associatedAddressablePoint s_axi + set_interface_property interrupt_sender associatedClock s_axi_clock + set_interface_property interrupt_sender associatedReset s_axi_reset + set_interface_property interrupt_sender ENABLED true + + # AXI4 Slave is active for regmap, deactivate uP + lappend disabled_intfs if_up_clk if_up_rstn if_up_wreq if_up_wack if_up_waddr \ + if_up_wdata if_up_rreq if_up_rack if_up_raddr if_up_rdata + + set_port_property up_clk termination true + set_port_property up_rstn termination true + set_port_property up_rstn termination_value 1 + set_port_property up_wreq termination true + set_port_property up_waddr termination true + set_port_property up_wdata termination true + set_port_property up_rreq termination true + set_port_property up_raddr termination true + + } + + ad_interface signal pulse_gen_period output 32 + ad_interface signal pulse_gen_width output 32 + ad_interface signal pulse_gen_load output 1 + + lappend disabled_intfs if_pulse_gen_period if_pulse_gen_width if_pulse_gen_load + + foreach interface $disabled_intfs { + set_interface_property $interface ENABLED false + } + + # SPI Engine interfaces + + ad_interface clock spi_clk input 1 + ad_interface reset spi_resetn output 1 if_spi_clk + + add_interface cmd axi4stream start + add_interface_port cmd cmd_ready tready input 1 + add_interface_port cmd cmd_valid tvalid output 1 + add_interface_port cmd cmd_data tdata output 16 + + set_interface_property cmd associatedClock if_spi_clk + set_interface_property cmd associatedReset if_spi_resetn + + add_interface sdo_data axi4stream start + add_interface_port sdo_data sdo_data_ready tready input 1 + add_interface_port sdo_data sdo_data_valid tvalid output 1 + add_interface_port sdo_data sdo_data tdata output $data_width + + set_interface_property sdo_data associatedClock if_spi_clk + set_interface_property sdo_data associatedReset if_spi_resetn + + add_interface sdi_data axi4stream end + add_interface_port sdi_data sdi_data_ready tready output 1 + add_interface_port sdi_data sdi_data_valid tvalid input 1 + add_interface_port sdi_data sdi_data tdata input [expr $num_of_sdi * $data_width] + + set_interface_property sdi_data associatedClock if_spi_clk + set_interface_property sdi_data associatedReset if_spi_resetn + + add_interface sync axi4stream end + add_interface_port sync sync_valid tvalid input 1 + add_interface_port sync sync_ready tready output 1 + add_interface_port sync sync_data tdata input 8 + + set_interface_property sync associatedClock if_spi_clk + set_interface_property sync associatedReset if_spi_resetn + + # Offload interfaces + + add_interface offload0_cmd conduit end + add_interface_port offload0_cmd offload0_cmd_wr_en wre output 1 + add_interface_port offload0_cmd offload0_cmd_wr_data data output 16 + + set_interface_property offload0_cmd associatedClock if_spi_clk + set_interface_property offload0_cmd associatedReset none + + add_interface offload0_sdo conduit end + add_interface_port offload0_sdo offload0_sdo_wr_en wre output 1 + add_interface_port offload0_sdo offload0_sdo_wr_data data output $data_width + + set_interface_property offload0_sdo associatedClock if_spi_clk + set_interface_property offload0_sdo associatedReset none + + ad_interface signal offload0_mem_reset output 1 reset + ad_interface signal offload0_enable output 1 enable + ad_interface signal offload0_enabled input 1 enabled + + add_interface offload_sync axi4stream end + add_interface_port offload_sync offload_sync_valid tvalid input 1 + add_interface_port offload_sync offload_sync_ready tready output 1 + add_interface_port offload_sync offload_sync_data tdata input 8 + + set_interface_property offload_sync associatedClock if_spi_clk + set_interface_property offload_sync associatedReset if_spi_resetn + +} + diff --git a/adi_library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl b/adi_library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl new file mode 100644 index 00000000..496a99fc --- /dev/null +++ b/adi_library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl @@ -0,0 +1,304 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create axi_spi_engine +adi_ip_files axi_spi_engine [list \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \ + "axi_spi_engine_constr.ttcl" \ + "axi_spi_engine.v" \ +] + +adi_ip_properties axi_spi_engine +adi_ip_ttcl axi_spi_engine "axi_spi_engine_constr.ttcl" + +adi_ip_add_core_dependencies [list \ + analog.com:$VIVADO_IP_LIBRARY:util_axis_fifo:1.0 \ + analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \ +] + +set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/spi_engine/axi} [ipx::current_core] + +## Interface definitions + +adi_add_bus "spi_engine_ctrl" "master" \ + "analog.com:interface:spi_engine_ctrl_rtl:1.0" \ + "analog.com:interface:spi_engine_ctrl:1.0" \ + { + {"cmd_ready" "CMD_READY"} \ + {"cmd_valid" "CMD_VALID"} \ + {"cmd_data" "CMD_DATA"} \ + {"sdo_data_ready" "SDO_READY"} \ + {"sdo_data_valid" "SDO_VALID"} \ + {"sdo_data" "SDO_DATA"} \ + {"sdi_data_ready" "SDI_READY"} \ + {"sdi_data_valid" "SDI_VALID"} \ + {"sdi_data" "SDI_DATA"} \ + {"sync_ready" "SYNC_READY"} \ + {"sync_valid" "SYNC_VALID"} \ + {"sync_data" "SYNC_DATA"} \ + } +adi_add_bus_clock "spi_clk" "spi_engine_ctrl" "spi_resetn" "master" + +adi_add_bus "spi_engine_offload_ctrl0" "master" \ + "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \ + "analog.com:interface:spi_engine_offload_ctrl:1.0" \ + { \ + { "offload0_cmd_wr_en" "CMD_WR_EN"} \ + { "offload0_cmd_wr_data" "CMD_WR_DATA"} \ + { "offload0_sdo_wr_en" "SDO_WR_EN"} \ + { "offload0_sdo_wr_data" "SDO_WR_DATA"} \ + { "offload0_enable" "ENABLE"} \ + { "offload0_enabled" "ENABLED"} \ + { "offload0_mem_reset" "MEM_RESET"} \ + { "offload_sync_ready" "SYNC_READY"} \ + { "offload_sync_valid" "SYNC_VALID"} \ + { "offload_sync_data" "SYNC_DATA"} \ + } + +adi_add_bus_clock "s_axi_aclk" "spi_engine_offload_ctrl0:s_axi" "s_axi_aresetn" + +foreach port {"up_clk" "up_rstn" "up_wreq" "up_waddr" "up_wdata" "up_rreq" "up_raddr"} { + set_property DRIVER_VALUE "0" [ipx::get_ports $port] +} +adi_set_bus_dependency "spi_engine_offload_ctrl0" "spi_engine_offload_ctrl0" \ + "(spirit:decode(id('MODELPARAM_VALUE.NUM_OFFLOAD')) > 0)" + +adi_set_bus_dependency "s_axi" "s_axi" \ + "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 0)" + +adi_set_ports_dependency "up_clk" \ + "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" +adi_set_ports_dependency "up_rstn" \ + "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" +adi_set_ports_dependency "up_wreq" \ + "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" +adi_set_ports_dependency "up_waddr" \ + "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" +adi_set_ports_dependency "up_wdata" \ + "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" +adi_set_ports_dependency "up_rreq" \ + "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" +adi_set_ports_dependency "up_raddr" \ + "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" +adi_set_ports_dependency "up_wack" \ + "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" +adi_set_ports_dependency "up_rdata" \ + "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" +adi_set_ports_dependency "up_rack" \ + "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 1)" + +## Parameter validations + +set cc [ipx::current_core] + +## ID +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "0" \ + "value_validation_range_maximum" "255" \ + ] \ + [ipx::get_user_parameters ID -of_objects $cc] + +## CMD_FIFO_ADDRESS_WIDTH +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "1" \ + "value_validation_range_maximum" "16" \ + ] \ + [ipx::get_user_parameters CMD_FIFO_ADDRESS_WIDTH -of_objects $cc] + +## SYNC_FIFO_ADDRESS_WIDTH +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "1" \ + "value_validation_range_maximum" "16" \ + ] \ + [ipx::get_user_parameters SYNC_FIFO_ADDRESS_WIDTH -of_objects $cc] + +## SDO_FIFO_ADDRESS_WIDTH +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "1" \ + "value_validation_range_maximum" "16" \ + ] \ + [ipx::get_user_parameters SDO_FIFO_ADDRESS_WIDTH -of_objects $cc] + +## SDI_FIFO_ADDRESS_WIDTH +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "1" \ + "value_validation_range_maximum" "16" \ + ] \ + [ipx::get_user_parameters SDI_FIFO_ADDRESS_WIDTH -of_objects $cc] + +## MM_IF_TYPE +set_property -dict [list \ + "value_validation_type" "pairs" \ + "value_validation_pairs" { \ + "AXI4 Memory Mapped" "0" \ + "ADI uP FIFO" "1" \ + } \ + ] \ + [ipx::get_user_parameters MM_IF_TYPE -of_objects $cc] + +## ASYNC_SPI_CLK +set_property -dict [list \ + "value_format" "bool" \ + "value" "false" \ + ] \ + [ipx::get_user_parameters ASYNC_SPI_CLK -of_objects $cc] +set_property -dict [list \ + "value_format" "bool" \ + "value" "false" \ + ] \ + [ipx::get_hdl_parameters ASYNC_SPI_CLK -of_objects $cc] + +## NUM_OFFLOAD +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "0" \ + "value_validation_range_maximum" "8" \ + ] \ + [ipx::get_user_parameters NUM_OFFLOAD -of_objects $cc] + +## OFFLOAD0_CMD_MEM_ADDRESS_WIDTH +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "1" \ + "value_validation_range_maximum" "16" \ + ] \ + [ipx::get_user_parameters OFFLOAD0_CMD_MEM_ADDRESS_WIDTH -of_objects $cc] + +## OFFLOAD0_SDO_MEM_ADDRESS_WIDTH +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "1" \ + "value_validation_range_maximum" "16" \ + ] \ + [ipx::get_user_parameters OFFLOAD0_SDO_MEM_ADDRESS_WIDTH -of_objects $cc] + +## DATA_WIDTH +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "8" \ + "value_validation_range_maximum" "256" \ + ] \ + [ipx::get_user_parameters DATA_WIDTH -of_objects $cc] + +## NUM_OF_SDI +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "1" \ + "value_validation_range_maximum" "8" \ + ] \ + [ipx::get_user_parameters NUM_OF_SDI -of_objects $cc] + +## Customize IP Layout + +## Remove the automatically generated GUI page +ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] +ipx::save_core [ipx::current_core] + +## Create general configuration page +ipgui::add_page -name {AXI SPI Engine soft-controller} -component [ipx::current_core] -display_name {AXI SPI Engine soft-controller} +set page0 [ipgui::get_pagespec -name "AXI SPI Engine soft-controller" -component $cc] + +set general_group [ipgui::add_group -name "General Configuration" -component $cc \ + -parent $page0 -display_name "General Configuration" ] + +ipgui::add_param -name "ID" -component $cc -parent $general_group +set_property -dict [list \ + "display_name" "Core ID" \ + "tooltip" "\[ID\] Core instance ID" \ +] [ipgui::get_guiparamspec -name "ID" -component $cc] + +ipgui::add_param -name "DATA_WIDTH" -component $cc -parent $general_group +set_property -dict [list \ + "display_name" "Parallel data width" \ + "tooltip" "\[DATA_WIDTH\] Define the data interface width" +] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc] + +ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group +set_property -dict [list \ + "display_name" "Number of MISO lines" \ + "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \ +] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc] + +ipgui::add_param -name "MM_IF_TYPE" -component $cc -parent $general_group +set_property -dict [list \ + "display_name" "Memory Mapped Interface Type" \ + "tooltip" "\[MM_IF_TYPE\] Define the memory mapped interface type" \ +] [ipgui::get_guiparamspec -name "MM_IF_TYPE" -component $cc] + +ipgui::add_param -name "ASYNC_SPI_CLK" -component $cc -parent $general_group +set_property -dict [list \ + "display_name" "Asynchronous core clock" \ + "tooltip" "\[ASYNC_SPI_CLK\] Define the relationship between the core clock and the memory mapped interface clock" \ +] [ipgui::get_guiparamspec -name "ASYNC_SPI_CLK" -component $cc] + +## Command stream FIFO depth configuration +set cmd_stream_fifo_group [ipgui::add_group -name "Command stream FIFO configuration" -component $cc \ + -parent $page0 -display_name "Command stream FIFO configuration" ] + +ipgui::add_param -name "CMD_FIFO_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group +set_property -dict [list \ + "display_name" "Command FIFO address width" \ + "tooltip" "\[CMD_FIFO_ADDRESS_WIDTH\] Define the depth of the FIFO" \ +] [ipgui::get_guiparamspec -name "CMD_FIFO_ADDRESS_WIDTH" -component $cc] + +ipgui::add_param -name "SYNC_FIFO_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group +set_property -dict [list \ + "display_name" "SYNC FIFO address width" \ + "tooltip" "\[SYNC_FIFO_ADDRESS_WIDTH\] Define the depth of the FIFO" \ +] [ipgui::get_guiparamspec -name "SYNC_FIFO_ADDRESS_WIDTH" -component $cc] + +ipgui::add_param -name "SDO_FIFO_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group +set_property -dict [list \ + "display_name" "MOSI FIFO address width" \ + "tooltip" "\[SDO_FIFO_ADDRESS_WIDTH\] Define the depth of the FIFO" \ +] [ipgui::get_guiparamspec -name "SDO_FIFO_ADDRESS_WIDTH" -component $cc] + +ipgui::add_param -name "SDI_FIFO_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group +set_property -dict [list \ + "display_name" "MISO FIFO address width" \ + "tooltip" "\[SDI_FIFO_ADDRESS_WIDTH\] Define the depth of the FIFO" \ +] [ipgui::get_guiparamspec -name "SDI_FIFO_ADDRESS_WIDTH" -component $cc] + +## Offload module(s) configuration +set offload_group [ipgui::add_group -name "Offload module configuration" -component $cc \ + -parent $page0 -display_name "Offload module configuration" ] + +ipgui::add_param -name "NUM_OFFLOAD" -component $cc -parent $offload_group +set_property -dict [list \ + "display_name" "Number of offloads" \ + "tooltip" "\[NUM_OFFLOAD\] Number of offloads" \ +] [ipgui::get_guiparamspec -name "NUM_OFFLOAD" -component $cc] + +ipgui::add_param -name "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH" -component $cc -parent $offload_group +set_property -dict [list \ + "display_name" "Offload command FIFO address width" \ + "tooltip" "\[OFFLOAD0_CMD_MEM_ADDRESS_WIDTH\] Define the depth of the FIFO" \ +] [ipgui::get_guiparamspec -name "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH" -component $cc] +set_property enablement_tcl_expr {$NUM_OFFLOAD > 0} [ipx::get_user_parameters OFFLOAD0_CMD_MEM_ADDRESS_WIDTH -of_objects $cc] + +ipgui::add_param -name "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH" -component $cc -parent $offload_group +set_property -dict [list \ + "display_name" "Offload MOSI FIFO address width" \ + "tooltip" "\[OFFLOAD0_SDO_MEM_ADDRESS_WIDTH\] Define the depth of the FIFO" \ +] [ipgui::get_guiparamspec -name "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH" -component $cc] +set_property enablement_tcl_expr {$NUM_OFFLOAD > 0} [ipx::get_user_parameters OFFLOAD0_SDO_MEM_ADDRESS_WIDTH -of_objects $cc] + +## Create and save the XGUI file +ipx::create_xgui_files $cc + +ipx::save_core [ipx::current_core] diff --git a/adi_library/spi_engine/axi_spi_engine/component.xml b/adi_library/spi_engine/axi_spi_engine/component.xml new file mode 100644 index 00000000..e0fef590 --- /dev/null +++ b/adi_library/spi_engine/axi_spi_engine/component.xml @@ -0,0 +1,2087 @@ + + + analog.com + user + axi_spi_engine + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + + true + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + spi_engine_ctrl + + + + + + + CMD_READY + + + cmd_ready + + + + + CMD_VALID + + + cmd_valid + + + + + CMD_DATA + + + cmd_data + + + + + SDO_READY + + + sdo_data_ready + + + + + SDO_VALID + + + sdo_data_valid + + + + + SDO_DATA + + + sdo_data + + + + + SDI_READY + + + sdi_data_ready + + + + + SDI_VALID + + + sdi_data_valid + + + + + SDI_DATA + + + sdi_data + + + + + SYNC_READY + + + sync_ready + + + + + SYNC_VALID + + + sync_valid + + + + + SYNC_DATA + + + sync_data + + + + + + spi_engine_ctrl_signal_clock + spi_engine_ctrl_signal_clock + + + + + + + CLK + + + spi_clk + + + + + + ASSOCIATED_BUSIF + spi_engine_ctrl + + + ASSOCIATED_RESET + spi_resetn + + + + + spi_engine_ctrl_signal_reset + spi_engine_ctrl_signal_reset + + + + + + + RST + + + spi_resetn + + + + + + POLARITY + ACTIVE_LOW + + + + + spi_engine_offload_ctrl0 + + + + + + + CMD_WR_EN + + + offload0_cmd_wr_en + + + + + CMD_WR_DATA + + + offload0_cmd_wr_data + + + + + SDO_WR_EN + + + offload0_sdo_wr_en + + + + + SDO_WR_DATA + + + offload0_sdo_wr_data + + + + + ENABLE + + + offload0_enable + + + + + ENABLED + + + offload0_enabled + + + + + MEM_RESET + + + offload0_mem_reset + + + + + SYNC_READY + + + offload_sync_ready + + + + + SYNC_VALID + + + offload_sync_valid + + + + + SYNC_DATA + + + offload_sync_data + + + + + + + false + + + + + + spi_engine_offload_ctrl0_s_axi_signal_clock + spi_engine_offload_ctrl0_s_axi_signal_clock + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + spi_engine_offload_ctrl0:s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + spi_engine_offload_ctrl0_s_axi_signal_reset + spi_engine_offload_ctrl0_s_axi_signal_reset + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + axi_lite + 0 + 65536 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_spi_engine + + xilinx_anylanguagesynthesis_analog_com_user_util_axis_fifo_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 1fd5eec0 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_spi_engine + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_axis_fifo_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 089a1d05 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_analog_com_user_util_axis_fifo_1_0__ref_view_fileset + + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_xpgui_view_fileset + + + + viewChecksum + ce0bf8b0 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + 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std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + up_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + up_rstn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + up_wreq + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + up_waddr + + in + + 13 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + up_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + up_wack + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false 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xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cmd_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cmd_data + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sdo_data_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + sdo_data_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sdo_data + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sdi_data_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sdi_data_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + sdi_data + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + sync_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sync_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sync_data + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + offload0_cmd_wr_en + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + offload0_cmd_wr_data + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + offload0_sdo_wr_en + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + offload0_sdo_wr_data + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + offload0_mem_reset + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + offload0_enable + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + offload0_enabled + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + offload_sync_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + offload_sync_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + offload_sync_data + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + CMD_FIFO_ADDRESS_WIDTH + Cmd Fifo Address Width + 4 + + + SYNC_FIFO_ADDRESS_WIDTH + Sync Fifo Address Width + 4 + + + SDO_FIFO_ADDRESS_WIDTH + Sdo Fifo Address Width + 5 + + + SDI_FIFO_ADDRESS_WIDTH + Sdi Fifo Address Width + 5 + + + MM_IF_TYPE + Mm If Type + 0 + + + ASYNC_SPI_CLK + Async Spi Clk + false + + + NUM_OFFLOAD + Num Offload + 0 + + + OFFLOAD0_CMD_MEM_ADDRESS_WIDTH + Offload0 Cmd Mem Address Width + 4 + + + + false + + + + + + OFFLOAD0_SDO_MEM_ADDRESS_WIDTH + Offload0 Sdo Mem Address Width + 4 + + + + false + + + + + + ID + Id + 0 + + + DATA_WIDTH + Data Width + 8 + + + NUM_OF_SDI + Num Of Sdi + 1 + + + CFG_INFO_0 + Cfg Info 0 + 0 + + + CFG_INFO_1 + Cfg Info 1 + 0 + + + CFG_INFO_2 + Cfg Info 2 + 0 + + + CFG_INFO_3 + Cfg Info 3 + 0 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_a1d277e1 + 0 + 1 + + + + + xilinx_anylanguagesynthesis_view_fileset + + axi_spi_engine_constr.ttcl + ttcl + + + ../../xilinx/common/ad_rst_constr.xdc + xdc + + + ../../common/ad_rst.v + verilogSource + + + ../../common/up_axi.v + verilogSource + + + axi_spi_engine.v + verilogSource + CHECKSUM_6b9f989c + + + + xilinx_anylanguagesynthesis_analog_com_user_util_axis_fifo_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../common/ad_rst.v + verilogSource + + + ../../common/up_axi.v + verilogSource + + + axi_spi_engine.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_axis_fifo_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axi_spi_engine_v1_0.tcl + tclSource + CHECKSUM_c80cbb85 + XGUI_VERSION_2 + + + + xilinx_xpgui_analog_com_user_util_axis_fifo_1_0__ref_view_fileset + + + + + + + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + xilinx_utilityxitfiles_view_fileset + + gui/axi_spi_engine_v1_0.gtcl + GTCL + + + + axi_spi_engine_v1_0 + + + CMD_FIFO_ADDRESS_WIDTH + Command FIFO address width + 4 + + + SYNC_FIFO_ADDRESS_WIDTH + SYNC FIFO address width + 4 + + + SDO_FIFO_ADDRESS_WIDTH + MOSI FIFO address width + 5 + + + SDI_FIFO_ADDRESS_WIDTH + MISO FIFO address width + 5 + + + MM_IF_TYPE + Memory Mapped Interface Type + 0 + + + ASYNC_SPI_CLK + Asynchronous core clock + false + + + NUM_OFFLOAD + Number of offloads + 0 + + + OFFLOAD0_CMD_MEM_ADDRESS_WIDTH + Offload command FIFO address width + 4 + + + + false + + + + + + OFFLOAD0_SDO_MEM_ADDRESS_WIDTH + Offload MOSI FIFO address width + 4 + + + + false + + + + + + ID + Core ID + 0 + + + DATA_WIDTH + Parallel data width + 8 + + + NUM_OF_SDI + Number of MISO lines + 1 + + + CFG_INFO_0 + Cfg Info 0 + 0 + + + CFG_INFO_1 + Cfg Info 1 + 0 + + + CFG_INFO_2 + Cfg Info 2 + 0 + + + CFG_INFO_3 + Cfg Info 3 + 0 + + + Component_Name + axi_spi_engine_v1_0 + + + + + + virtex7 + + + /Analog_Devices + + axi_spi_engine_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/peripherals/spi_engine/axi + 1 + 2024-01-14T03:52:34Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/spi_engine/axi_spi_engine/gui/axi_spi_engine_v1_0.gtcl b/adi_library/spi_engine/axi_spi_engine/gui/axi_spi_engine_v1_0.gtcl new file mode 100644 index 00000000..3d15eb4e --- /dev/null +++ b/adi_library/spi_engine/axi_spi_engine/gui/axi_spi_engine_v1_0.gtcl @@ -0,0 +1,3 @@ +# This file is automatically written. Do not modify. +proc gen_USERPARAMETER_OFFLOAD0_CMD_MEM_ADDRESS_WIDTH_ENABLEMENT {NUM_OFFLOAD } {expr $NUM_OFFLOAD > 0} +proc gen_USERPARAMETER_OFFLOAD0_SDO_MEM_ADDRESS_WIDTH_ENABLEMENT {NUM_OFFLOAD } {expr $NUM_OFFLOAD > 0} diff --git a/adi_library/spi_engine/axi_spi_engine/xgui/axi_spi_engine_v1_0.tcl b/adi_library/spi_engine/axi_spi_engine/xgui/axi_spi_engine_v1_0.tcl new file mode 100644 index 00000000..9d4ce069 --- /dev/null +++ b/adi_library/spi_engine/axi_spi_engine/xgui/axi_spi_engine_v1_0.tcl @@ -0,0 +1,289 @@ + +# Loading additional proc with user specified bodies to compute parameter values. +source [file join [file dirname [file dirname [info script]]] gui/axi_spi_engine_v1_0.gtcl] + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set AXI_SPI_Engine_soft-controller [ipgui::add_page $IPINST -name "AXI SPI Engine soft-controller"] + #Adding Group + set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${AXI_SPI_Engine_soft-controller}] + set ID [ipgui::add_param $IPINST -name "ID" -parent ${General_Configuration}] + set_property tooltip {[ID] Core instance ID} ${ID} + set DATA_WIDTH [ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${General_Configuration}] + set_property tooltip {[DATA_WIDTH] Define the data interface width} ${DATA_WIDTH} + set NUM_OF_SDI [ipgui::add_param $IPINST -name "NUM_OF_SDI" -parent ${General_Configuration}] + set_property tooltip {[NUM_OF_SDI] Define the number of MISO lines} ${NUM_OF_SDI} + set MM_IF_TYPE [ipgui::add_param $IPINST -name "MM_IF_TYPE" -parent ${General_Configuration}] + set_property tooltip {[MM_IF_TYPE] Define the memory mapped interface type} ${MM_IF_TYPE} + set ASYNC_SPI_CLK [ipgui::add_param $IPINST -name "ASYNC_SPI_CLK" -parent ${General_Configuration}] + set_property tooltip {[ASYNC_SPI_CLK] Define the relationship between the core clock and the memory mapped interface clock} ${ASYNC_SPI_CLK} + + #Adding Group + set Command_stream_FIFO_configuration [ipgui::add_group $IPINST -name "Command stream FIFO configuration" -parent ${AXI_SPI_Engine_soft-controller}] + set CMD_FIFO_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "CMD_FIFO_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}] + set_property tooltip {[CMD_FIFO_ADDRESS_WIDTH] Define the depth of the FIFO} ${CMD_FIFO_ADDRESS_WIDTH} + set SYNC_FIFO_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "SYNC_FIFO_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}] + set_property tooltip {[SYNC_FIFO_ADDRESS_WIDTH] Define the depth of the FIFO} ${SYNC_FIFO_ADDRESS_WIDTH} + set SDO_FIFO_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "SDO_FIFO_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}] + set_property tooltip {[SDO_FIFO_ADDRESS_WIDTH] Define the depth of the FIFO} ${SDO_FIFO_ADDRESS_WIDTH} + set SDI_FIFO_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "SDI_FIFO_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}] + set_property tooltip {[SDI_FIFO_ADDRESS_WIDTH] Define the depth of the FIFO} ${SDI_FIFO_ADDRESS_WIDTH} + + #Adding Group + set Offload_module_configuration [ipgui::add_group $IPINST -name "Offload module configuration" -parent ${AXI_SPI_Engine_soft-controller}] + set NUM_OFFLOAD [ipgui::add_param $IPINST -name "NUM_OFFLOAD" -parent ${Offload_module_configuration}] + set_property tooltip {[NUM_OFFLOAD] Number of offloads} ${NUM_OFFLOAD} + set OFFLOAD0_CMD_MEM_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH" -parent ${Offload_module_configuration}] + set_property tooltip {[OFFLOAD0_CMD_MEM_ADDRESS_WIDTH] Define the depth of the FIFO} ${OFFLOAD0_CMD_MEM_ADDRESS_WIDTH} + set OFFLOAD0_SDO_MEM_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH" -parent ${Offload_module_configuration}] + set_property tooltip {[OFFLOAD0_SDO_MEM_ADDRESS_WIDTH] Define the depth of the FIFO} ${OFFLOAD0_SDO_MEM_ADDRESS_WIDTH} + + + +} + +proc update_PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH PARAM_VALUE.NUM_OFFLOAD } { + # Procedure called to update OFFLOAD0_CMD_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change + + set OFFLOAD0_CMD_MEM_ADDRESS_WIDTH ${PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH} + set NUM_OFFLOAD ${PARAM_VALUE.NUM_OFFLOAD} + set values(NUM_OFFLOAD) [get_property value $NUM_OFFLOAD] + if { [gen_USERPARAMETER_OFFLOAD0_CMD_MEM_ADDRESS_WIDTH_ENABLEMENT $values(NUM_OFFLOAD)] } { + set_property enabled true $OFFLOAD0_CMD_MEM_ADDRESS_WIDTH + } else { + set_property enabled false $OFFLOAD0_CMD_MEM_ADDRESS_WIDTH + } +} + +proc validate_PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH } { + # Procedure called to validate OFFLOAD0_CMD_MEM_ADDRESS_WIDTH + return true +} + +proc update_PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH PARAM_VALUE.NUM_OFFLOAD } { + # Procedure called to update OFFLOAD0_SDO_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change + + set OFFLOAD0_SDO_MEM_ADDRESS_WIDTH ${PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH} + set NUM_OFFLOAD ${PARAM_VALUE.NUM_OFFLOAD} + set values(NUM_OFFLOAD) [get_property value $NUM_OFFLOAD] + if { [gen_USERPARAMETER_OFFLOAD0_SDO_MEM_ADDRESS_WIDTH_ENABLEMENT $values(NUM_OFFLOAD)] } { + set_property enabled true $OFFLOAD0_SDO_MEM_ADDRESS_WIDTH + } else { + set_property enabled false $OFFLOAD0_SDO_MEM_ADDRESS_WIDTH + } +} + +proc validate_PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH } { + # Procedure called to validate OFFLOAD0_SDO_MEM_ADDRESS_WIDTH + return true +} + +proc update_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } { + # Procedure called to update ASYNC_SPI_CLK when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } { + # Procedure called to validate ASYNC_SPI_CLK + return true +} + +proc update_PARAM_VALUE.CFG_INFO_0 { PARAM_VALUE.CFG_INFO_0 } { + # Procedure called to update CFG_INFO_0 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CFG_INFO_0 { PARAM_VALUE.CFG_INFO_0 } { + # Procedure called to validate CFG_INFO_0 + return true +} + +proc update_PARAM_VALUE.CFG_INFO_1 { PARAM_VALUE.CFG_INFO_1 } { + # Procedure called to update CFG_INFO_1 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CFG_INFO_1 { PARAM_VALUE.CFG_INFO_1 } { + # Procedure called to validate CFG_INFO_1 + return true +} + +proc update_PARAM_VALUE.CFG_INFO_2 { PARAM_VALUE.CFG_INFO_2 } { + # Procedure called to update CFG_INFO_2 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CFG_INFO_2 { PARAM_VALUE.CFG_INFO_2 } { + # Procedure called to validate CFG_INFO_2 + return true +} + +proc update_PARAM_VALUE.CFG_INFO_3 { PARAM_VALUE.CFG_INFO_3 } { + # Procedure called to update CFG_INFO_3 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CFG_INFO_3 { PARAM_VALUE.CFG_INFO_3 } { + # Procedure called to validate CFG_INFO_3 + return true +} + +proc update_PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH { PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH } { + # Procedure called to update CMD_FIFO_ADDRESS_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH { PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH } { + # Procedure called to validate CMD_FIFO_ADDRESS_WIDTH + return true +} + +proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to validate DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.MM_IF_TYPE { PARAM_VALUE.MM_IF_TYPE } { + # Procedure called to update MM_IF_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.MM_IF_TYPE { PARAM_VALUE.MM_IF_TYPE } { + # Procedure called to validate MM_IF_TYPE + return true +} + +proc update_PARAM_VALUE.NUM_OFFLOAD { PARAM_VALUE.NUM_OFFLOAD } { + # Procedure called to update NUM_OFFLOAD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OFFLOAD { PARAM_VALUE.NUM_OFFLOAD } { + # Procedure called to validate NUM_OFFLOAD + return true +} + +proc update_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } { + # Procedure called to update NUM_OF_SDI when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } { + # Procedure called to validate NUM_OF_SDI + return true +} + +proc update_PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH } { + # Procedure called to update SDI_FIFO_ADDRESS_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH } { + # Procedure called to validate SDI_FIFO_ADDRESS_WIDTH + return true +} + +proc update_PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH } { + # Procedure called to update SDO_FIFO_ADDRESS_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH } { + # Procedure called to validate SDO_FIFO_ADDRESS_WIDTH + return true +} + +proc update_PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH } { + # Procedure called to update SYNC_FIFO_ADDRESS_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH { PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH } { + # Procedure called to validate SYNC_FIFO_ADDRESS_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH { MODELPARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.CMD_FIFO_ADDRESS_WIDTH} +} + +proc update_MODELPARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH { MODELPARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.SYNC_FIFO_ADDRESS_WIDTH} +} + +proc update_MODELPARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH { MODELPARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.SDO_FIFO_ADDRESS_WIDTH} +} + +proc update_MODELPARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH { MODELPARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.SDI_FIFO_ADDRESS_WIDTH} +} + +proc update_MODELPARAM_VALUE.MM_IF_TYPE { MODELPARAM_VALUE.MM_IF_TYPE PARAM_VALUE.MM_IF_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.MM_IF_TYPE}] ${MODELPARAM_VALUE.MM_IF_TYPE} +} + +proc update_MODELPARAM_VALUE.ASYNC_SPI_CLK { MODELPARAM_VALUE.ASYNC_SPI_CLK PARAM_VALUE.ASYNC_SPI_CLK } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASYNC_SPI_CLK}] ${MODELPARAM_VALUE.ASYNC_SPI_CLK} +} + +proc update_MODELPARAM_VALUE.NUM_OFFLOAD { MODELPARAM_VALUE.NUM_OFFLOAD PARAM_VALUE.NUM_OFFLOAD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OFFLOAD}] ${MODELPARAM_VALUE.NUM_OFFLOAD} +} + +proc update_MODELPARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH} +} + +proc update_MODELPARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.OFFLOAD0_SDO_MEM_ADDRESS_WIDTH} +} + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.NUM_OF_SDI { MODELPARAM_VALUE.NUM_OF_SDI PARAM_VALUE.NUM_OF_SDI } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_SDI}] ${MODELPARAM_VALUE.NUM_OF_SDI} +} + +proc update_MODELPARAM_VALUE.CFG_INFO_0 { MODELPARAM_VALUE.CFG_INFO_0 PARAM_VALUE.CFG_INFO_0 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CFG_INFO_0}] ${MODELPARAM_VALUE.CFG_INFO_0} +} + +proc update_MODELPARAM_VALUE.CFG_INFO_1 { MODELPARAM_VALUE.CFG_INFO_1 PARAM_VALUE.CFG_INFO_1 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CFG_INFO_1}] ${MODELPARAM_VALUE.CFG_INFO_1} +} + +proc update_MODELPARAM_VALUE.CFG_INFO_2 { MODELPARAM_VALUE.CFG_INFO_2 PARAM_VALUE.CFG_INFO_2 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CFG_INFO_2}] ${MODELPARAM_VALUE.CFG_INFO_2} +} + +proc update_MODELPARAM_VALUE.CFG_INFO_3 { MODELPARAM_VALUE.CFG_INFO_3 PARAM_VALUE.CFG_INFO_3 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CFG_INFO_3}] ${MODELPARAM_VALUE.CFG_INFO_3} +} + diff --git a/adi_library/spi_engine/interfaces/spi_engine_ctrl.xml b/adi_library/spi_engine/interfaces/spi_engine_ctrl.xml new file mode 100644 index 00000000..0ccbf8de --- /dev/null +++ b/adi_library/spi_engine/interfaces/spi_engine_ctrl.xml @@ -0,0 +1,13 @@ + + + analog.com + interface + spi_engine_ctrl + 1.0 + false + false + 1 + 1 + diff --git a/adi_library/spi_engine/interfaces/spi_engine_ctrl_rtl.xml b/adi_library/spi_engine/interfaces/spi_engine_ctrl_rtl.xml new file mode 100644 index 00000000..2ba4f27f --- /dev/null +++ b/adi_library/spi_engine/interfaces/spi_engine_ctrl_rtl.xml @@ -0,0 +1,189 @@ + + + analog.com + interface + spi_engine_ctrl_rtl + 1.0 + + + + CMD_READY + + + required + 1 + in + + + required + 1 + + + + + CMD_VALID + + + required + 1 + + + required + 1 + in + + + + + CMD_DATA + + + required + 16 + + + required + 16 + in + + + + + SDO_READY + + + required + 1 + in + + + required + 1 + + + + + SDO_VALID + + + required + 1 + + + required + 1 + in + + + + + SDO_DATA + + + required + 8 + + + required + 8 + in + + + + + SDI_READY + + + required + 1 + out + + + required + 1 + in + + + + + SDI_VALID + + + required + 1 + in + + + required + 1 + out + + + + + SDI_DATA + + + required + 8 + in + + + required + 8 + out + + + + + SYNC_READY + + + required + 1 + out + + + required + 1 + in + + + + + SYNC_VALID + + + required + 1 + in + + + required + 1 + out + + + + + SYNC_DATA + + + required + 8 + in + + + required + 8 + out + + + + + diff --git a/adi_library/spi_engine/interfaces/spi_engine_offload_ctrl.xml b/adi_library/spi_engine/interfaces/spi_engine_offload_ctrl.xml new file mode 100644 index 00000000..5a8a05ea --- /dev/null +++ b/adi_library/spi_engine/interfaces/spi_engine_offload_ctrl.xml @@ -0,0 +1,13 @@ + + + analog.com + interface + spi_engine_offload_ctrl + 1.0 + false + false + 1 + 1 + diff --git a/adi_library/spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml b/adi_library/spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml new file mode 100644 index 00000000..82013432 --- /dev/null +++ b/adi_library/spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml @@ -0,0 +1,158 @@ + + + analog.com + interface + spi_engine_offload_ctrl_rtl + 1.0 + + + + CMD_WR_EN + + + required + 1 + + + required + 1 + in + + + + + CMD_WR_DATA + + + required + 16 + + + required + 16 + in + + + + + SDO_WR_EN + + + optional + 1 + + + optional + 1 + in + + + + + SDO_WR_DATA + + + optional + 8 + + + optional + 8 + in + + + + + ENABLE + + + required + 1 + + + required + 1 + in + + + + + MEM_RESET + + + required + 1 + + + required + 1 + in + + + + + ENABLED + + + required + 1 + in + + + required + 1 + + + + + SYNC_READY + + + required + 1 + out + + + required + 1 + in + + + + + SYNC_VALID + + + required + 1 + in + + + required + 1 + out + + + + + SYNC_DATA + + + required + 8 + in + + + required + 8 + out + + + + + diff --git a/adi_library/spi_engine/interfaces/spi_master.xml b/adi_library/spi_engine/interfaces/spi_master.xml new file mode 100644 index 00000000..b03644e6 --- /dev/null +++ b/adi_library/spi_engine/interfaces/spi_master.xml @@ -0,0 +1,14 @@ + + + analog.com + interface + spi_master + 1.0 + false + false + 1 + 1 + SPI Engine physical interface + diff --git a/adi_library/spi_engine/interfaces/spi_master_rtl.xml b/adi_library/spi_engine/interfaces/spi_master_rtl.xml new file mode 100644 index 00000000..3c406305 --- /dev/null +++ b/adi_library/spi_engine/interfaces/spi_master_rtl.xml @@ -0,0 +1,112 @@ + + + analog.com + interface + spi_master_rtl + 1.0 + + + + SCLK + SPI clock + + + required + 1 + out + + + required + 1 + in + + + + + SDI + Serial data in + + + optional + in + + + optional + out + + 0 + + + + SDO + Serial data out + + + optional + 1 + out + + + optional + 1 + in + + 0 + + + + SDO_T + Serial data out three state controle line + + + optional + 1 + out + + + optional + 1 + in + + 0 + + + + THREE_WIRE + Three wire mode + + + optional + 1 + out + + + optional + 1 + in + + 0 + + + + CS + Chip select + + + required + out + + + required + in + + 0 + + + + diff --git a/adi_library/spi_engine/scripts/spi_engine.tcl b/adi_library/spi_engine/scripts/spi_engine.tcl new file mode 100644 index 00000000..f59a7db1 --- /dev/null +++ b/adi_library/spi_engine/scripts/spi_engine.tcl @@ -0,0 +1,90 @@ +############################################################################### +## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {num_cs 1} {num_sdi 1} {num_sdo 1} {sdi_delay 0} {echo_sclk 0}} { + puts "echo_sclk: $echo_sclk" + + create_bd_cell -type hier $name + current_bd_instance /$name + + if {$async_spi_clk == 1} { + create_bd_pin -dir I -type clk spi_clk + } + if {$echo_sclk == 1} { + create_bd_pin -dir I -type clk echo_sclk + } + create_bd_pin -dir I -type clk clk + create_bd_pin -dir I -type rst resetn + create_bd_pin -dir I trigger + create_bd_pin -dir O irq + create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_sample + + set execution "${name}_execution" + set axi_regmap "${name}_axi_regmap" + set offload "${name}_offload" + set interconnect "${name}_interconnect" + + ad_ip_instance spi_engine_execution $execution + ad_ip_parameter $execution CONFIG.DATA_WIDTH $data_width + ad_ip_parameter $execution CONFIG.NUM_OF_CS $num_cs + ad_ip_parameter $execution CONFIG.NUM_OF_SDI $num_sdi + ad_ip_parameter $execution CONFIG.SDO_DEFAULT 1 + ad_ip_parameter $execution CONFIG.SDI_DELAY $sdi_delay + ad_ip_parameter $execution CONFIG.ECHO_SCLK $echo_sclk + + ad_ip_instance axi_spi_engine $axi_regmap + ad_ip_parameter $axi_regmap CONFIG.DATA_WIDTH $data_width + ad_ip_parameter $axi_regmap CONFIG.NUM_OFFLOAD 1 + ad_ip_parameter $axi_regmap CONFIG.NUM_OF_SDI $num_sdi + ad_ip_parameter $axi_regmap CONFIG.ASYNC_SPI_CLK $async_spi_clk + + ad_ip_instance spi_engine_offload $offload + ad_ip_parameter $offload CONFIG.DATA_WIDTH $data_width + ad_ip_parameter $offload CONFIG.ASYNC_SPI_CLK $async_spi_clk + ad_ip_parameter $offload CONFIG.NUM_OF_SDI $num_sdi + + ad_ip_instance spi_engine_interconnect $interconnect + ad_ip_parameter $interconnect CONFIG.DATA_WIDTH $data_width + ad_ip_parameter $interconnect CONFIG.NUM_OF_SDI $num_sdi + + ad_connect $axi_regmap/spi_engine_offload_ctrl0 $offload/spi_engine_offload_ctrl + ad_connect $offload/spi_engine_ctrl $interconnect/s0_ctrl + ad_connect $axi_regmap/spi_engine_ctrl $interconnect/s1_ctrl + ad_connect $interconnect/m_ctrl $execution/ctrl + ad_connect $offload/offload_sdi m_axis_sample + ad_connect $offload/trigger trigger + + ad_connect $execution/spi m_spi + + ad_connect clk $axi_regmap/s_axi_aclk + + if {$async_spi_clk == 1} { + ad_connect spi_clk $offload/spi_clk + ad_connect spi_clk $offload/ctrl_clk + ad_connect spi_clk $execution/clk + ad_connect spi_clk $axi_regmap/spi_clk + ad_connect spi_clk $interconnect/clk + } else { + ad_connect clk $offload/spi_clk + ad_connect clk $offload/ctrl_clk + ad_connect clk $execution/clk + ad_connect clk $axi_regmap/spi_clk + ad_connect clk $interconnect/clk + } + + if {$echo_sclk == 1} { + ad_connect echo_sclk $execution/echo_sclk + } + + ad_connect $axi_regmap/spi_resetn $offload/spi_resetn + ad_connect $axi_regmap/spi_resetn $execution/resetn + ad_connect $axi_regmap/spi_resetn $interconnect/resetn + + ad_connect resetn $axi_regmap/s_axi_aresetn + ad_connect irq $axi_regmap/irq + + current_bd_instance / +} diff --git a/adi_library/spi_engine/spi_axis_reorder/Makefile b/adi_library/spi_engine/spi_axis_reorder/Makefile new file mode 100644 index 00000000..af8fe5be --- /dev/null +++ b/adi_library/spi_engine/spi_axis_reorder/Makefile @@ -0,0 +1,13 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := spi_axis_reorder + +GENERIC_DEPS += spi_axis_reorder.v + +XILINX_DEPS += spi_axis_reorder_ip.tcl + +include ../../scripts/library.mk diff --git a/adi_library/spi_engine/spi_axis_reorder/component.xml b/adi_library/spi_engine/spi_axis_reorder/component.xml new file mode 100644 index 00000000..b928aa2b --- /dev/null +++ b/adi_library/spi_engine/spi_axis_reorder/component.xml @@ -0,0 +1,383 @@ + + + analog.com + user + spi_axis_reorder + 1.0 + + + s_axis + + + + + + + TREADY + + + s_axis_ready + + + + + TVALID + + + s_axis_valid + + + + + TDATA + + + s_axis_data + + + + + + m_axis + + + + + + + TREADY + + + m_axis_ready + + + + + TVALID + + + m_axis_valid + + + + + TDATA + + + m_axis_data + + + + + + s_axis_m_axis_signal_clock + s_axis_m_axis_signal_clock + + + + + + + CLK + + + axis_aclk + + + + + + ASSOCIATED_BUSIF + s_axis:m_axis + + + ASSOCIATED_RESET + axis_aresetn + + + + + s_axis_m_axis_signal_reset + s_axis_m_axis_signal_reset + + + + + + + RST + + + axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + spi_axis_reorder + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 6f89b3dc + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + spi_axis_reorder + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 6f89b3dc + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 130431ad + + + + + + + axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_data + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_data + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + NUM_OF_LANES + Num Of Lanes + 2 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + spi_axis_reorder.v + verilogSource + CHECKSUM_6f89b3dc + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + spi_axis_reorder.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/spi_axis_reorder_v1_0.tcl + tclSource + CHECKSUM_130431ad + XGUI_VERSION_2 + + + + spi_axis_reorder_v1_0 + + + NUM_OF_LANES + Num Of Lanes + 2 + + + Component_Name + spi_axis_reorder_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + spi_axis_reorder_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:52:42Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/spi_engine/spi_axis_reorder/spi_axis_reorder.v b/adi_library/spi_engine/spi_axis_reorder/spi_axis_reorder.v new file mode 100644 index 00000000..04a3356d --- /dev/null +++ b/adi_library/spi_engine/spi_axis_reorder/spi_axis_reorder.v @@ -0,0 +1,140 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +// Re-ordering module for Flexi-SPI +// +module spi_axis_reorder #( + + parameter [3:0] NUM_OF_LANES = 2 +) ( + input axis_aclk, + input axis_aresetn, + + input s_axis_valid, + output s_axis_ready, + input [(NUM_OF_LANES * 32)-1:0] s_axis_data, + + output m_axis_valid, + input m_axis_ready, + output [63:0] m_axis_data +); + + // re-packager is always ready + assign s_axis_ready = 1'b1; + + genvar i, j; + generate + if (NUM_OF_LANES == 1) begin : g_reorder_1_lane_interleaved + + reg wr_addr = 0; + reg [63:0] axis_data_int; + reg mem_is_full; + + // address control + // NOTE: ready is ignored, taking the fact that the module is always ready + always @(posedge axis_aclk) begin + if (axis_aresetn == 1'b0) begin + wr_addr <= 1'b0; + axis_data_int <= 64'b0; + end else begin + if ((s_axis_valid == 1'b1) && (s_axis_ready == 1'b1)) begin + wr_addr <= wr_addr + 1'b1; + axis_data_int <= (wr_addr) ? {s_axis_data, axis_data_int[31:0]} : + {axis_data_int[63:32], s_axis_data}; + end + end + end + + // latch the state of the memory + always @(posedge axis_aclk) begin + if (axis_aresetn == 1'b0) begin + mem_is_full <= 1'b0; + end else begin + if ((wr_addr == 1'b1) && (s_axis_valid == 1'b1)) begin + mem_is_full <= 1'b1; + end else begin + mem_is_full <= 1'b0; + end + end + end + + // reorder the interleaved data + assign m_axis_valid = mem_is_full; + for (i=0; i<32; i=i+1) begin + assign m_axis_data[ i] = axis_data_int[2*i+1]; + assign m_axis_data[32+i] = axis_data_int[2*i]; + end + + end else if (NUM_OF_LANES == 2) begin : g_reorder_2_lanes + + assign m_axis_valid = s_axis_valid; + assign m_axis_data = s_axis_data; + + end else if (NUM_OF_LANES == 4) begin : g_reorder_4_lanes + + assign m_axis_valid = s_axis_valid; + for (i=0; i<16; i=i+1) begin + // first channel + assign m_axis_data[2*i ] = s_axis_data[32+i]; + assign m_axis_data[2*i+1] = s_axis_data[ i]; + // second channel + assign m_axis_data[2*i+32] = s_axis_data[96+i]; + assign m_axis_data[2*i+33] = s_axis_data[64+i]; + end + + end else if (NUM_OF_LANES == 8) begin : g_reorder_8_lanes + + assign m_axis_valid = s_axis_valid; + for (i=0; i<8; i=i+1) begin + // first channel + assign m_axis_data[4*i ] = s_axis_data[96+i]; + assign m_axis_data[4*i+1] = s_axis_data[64+i]; + assign m_axis_data[4*i+2] = s_axis_data[32+i]; + assign m_axis_data[4*i+3] = s_axis_data[ i]; + // second channel + assign m_axis_data[4*i+32] = s_axis_data[224+i]; + assign m_axis_data[4*i+33] = s_axis_data[192+i]; + assign m_axis_data[4*i+34] = s_axis_data[160+i]; + assign m_axis_data[4*i+35] = s_axis_data[128+i]; + end + + end else begin + // WARNING: Invalid configuration, leave everybody in the air + end + endgenerate + +endmodule diff --git a/adi_library/spi_engine/spi_axis_reorder/spi_axis_reorder.xpr b/adi_library/spi_engine/spi_axis_reorder/spi_axis_reorder.xpr new file mode 100644 index 00000000..c951eaf2 --- /dev/null +++ b/adi_library/spi_engine/spi_axis_reorder/spi_axis_reorder.xpr @@ -0,0 +1,399 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/spi_engine/spi_axis_reorder/spi_axis_reorder_ip.tcl b/adi_library/spi_engine/spi_axis_reorder/spi_axis_reorder_ip.tcl new file mode 100644 index 00000000..9aa8c7bb --- /dev/null +++ b/adi_library/spi_engine/spi_axis_reorder/spi_axis_reorder_ip.tcl @@ -0,0 +1,37 @@ +############################################################################### +## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create spi_axis_reorder +adi_ip_files spi_axis_reorder [list \ + "spi_axis_reorder.v" \ +] + +adi_ip_properties_lite spi_axis_reorder +# Remove all inferred interfaces +ipx::remove_all_bus_interface [ipx::current_core] + +# Interface definitions + +adi_add_bus "s_axis" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"s_axis_ready" "TREADY"} \ + {"s_axis_valid" "TVALID"} \ + {"s_axis_data" "TDATA"}] + +adi_add_bus "m_axis" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"m_axis_ready" "TREADY"} \ + {"m_axis_valid" "TVALID"} \ + {"m_axis_data" "TDATA"}] + +adi_add_bus_clock "axis_aclk" "s_axis:m_axis" "axis_aresetn" + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/spi_engine/spi_axis_reorder/xgui/spi_axis_reorder_v1_0.tcl b/adi_library/spi_engine/spi_axis_reorder/xgui/spi_axis_reorder_v1_0.tcl new file mode 100644 index 00000000..e2363a6c --- /dev/null +++ b/adi_library/spi_engine/spi_axis_reorder/xgui/spi_axis_reorder_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "NUM_OF_LANES" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.NUM_OF_LANES { PARAM_VALUE.NUM_OF_LANES } { + # Procedure called to update NUM_OF_LANES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_LANES { PARAM_VALUE.NUM_OF_LANES } { + # Procedure called to validate NUM_OF_LANES + return true +} + + +proc update_MODELPARAM_VALUE.NUM_OF_LANES { MODELPARAM_VALUE.NUM_OF_LANES PARAM_VALUE.NUM_OF_LANES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_LANES}] ${MODELPARAM_VALUE.NUM_OF_LANES} +} + diff --git a/adi_library/spi_engine/spi_engine_execution/Makefile b/adi_library/spi_engine/spi_engine_execution/Makefile new file mode 100644 index 00000000..0bd32b44 --- /dev/null +++ b/adi_library/spi_engine/spi_engine_execution/Makefile @@ -0,0 +1,21 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := spi_engine_execution + +GENERIC_DEPS += spi_engine_execution.v + +XILINX_DEPS += spi_engine_execution_constr.ttcl +XILINX_DEPS += spi_engine_execution_ip.tcl + +XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml +XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml +XILINX_DEPS += ../../spi_engine/interfaces/spi_master.xml +XILINX_DEPS += ../../spi_engine/interfaces/spi_master_rtl.xml + +INTEL_DEPS += spi_engine_execution_hw.tcl + +include ../../scripts/library.mk diff --git a/adi_library/spi_engine/spi_engine_execution/component.xml b/adi_library/spi_engine/spi_engine_execution/component.xml new file mode 100644 index 00000000..311ff360 --- /dev/null +++ b/adi_library/spi_engine/spi_engine_execution/component.xml @@ -0,0 +1,810 @@ + + + analog.com + user + spi_engine_execution + 1.0 + + + ctrl + + + + + + + CMD_READY + + + cmd_ready + + + + + CMD_VALID + + + cmd_valid + + + + + CMD_DATA + + + cmd + + + + + SDO_READY + + + sdo_data_ready + + + + + SDO_VALID + + + sdo_data_valid + + + + + SDO_DATA + + + sdo_data + + + + + SDI_READY + + + sdi_data_ready + + + + + SDI_VALID + + + sdi_data_valid + + + + + SDI_DATA + + + sdi_data + + + + + SYNC_READY + + + sync_ready + + + + + SYNC_VALID + + + sync_valid + + + + + SYNC_DATA + + + sync + + + + + + ctrl_signal_clock + ctrl_signal_clock + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_BUSIF + ctrl + + + ASSOCIATED_RESET + resetn + + + + + ctrl_signal_reset + ctrl_signal_reset + + + + + + + RST + + + resetn + + + + + + POLARITY + ACTIVE_LOW + + + + + spi + + + + + + + SCLK + + + sclk + + + + + SDI + + + sdi + + + + + SDO + + + sdo + + + + + SDO_T + + + sdo_t + + + + + THREE_WIRE + + + three_wire + + + + + CS + + + cs + + + + + + spi_signal_clock + spi_signal_clock + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_BUSIF + spi + + + ASSOCIATED_RESET + resetn + + + + + spi_signal_reset + spi_signal_reset + + + + + + + RST + + + resetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + spi_engine_execution + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 4f3438ce + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + spi_engine_execution + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 4f3438ce + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 3d941b35 + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + resetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + active + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cmd_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cmd_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cmd + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sdo_data_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + sdo_data_ready + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sdo_data + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + sdi_data_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + sdi_data_valid + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sdi_data + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sync_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sync_valid + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sync + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + echo_sclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + sclk + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sdo + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sdo_t + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sdi + + in + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + cs + + out + + 0 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + three_wire + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + NUM_OF_CS + Num Of Cs + 1 + + + DEFAULT_SPI_CFG + Default Spi Cfg + 0 + + + DEFAULT_CLK_DIV + Default Clk Div + 0 + + + DATA_WIDTH + Data Width + 8 + + + NUM_OF_SDI + Num Of Sdi + 1 + + + SDO_DEFAULT + Sdo Default + "0" + + + ECHO_SCLK + Echo Sclk + false + + + SDI_DELAY + Sdi Delay + false + + + + + + choice_list_b71134be + "0" + "1" + + + choice_list_dd9ee503 + 0 + 1 + 2 + 3 + + + + + xilinx_anylanguagesynthesis_view_fileset + + spi_engine_execution_constr.ttcl + ttcl + + + spi_engine_execution.v + verilogSource + CHECKSUM_4f3438ce + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + spi_engine_execution.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/spi_engine_execution_v1_0.tcl + tclSource + CHECKSUM_b2ce64e5 + XGUI_VERSION_2 + + + + spi_engine_execution_v1_0 + + + NUM_OF_CS + Number of CSN lines + 1 + + + DEFAULT_SPI_CFG + Default SPI mode + 0 + + + DEFAULT_CLK_DIV + Default SCLK divider + 0 + + + DATA_WIDTH + Parallel data width + 8 + + + NUM_OF_SDI + Number of MISO + 1 + + + SDO_DEFAULT + MOSI default level + "0" + + + ECHO_SCLK + Echoed SCLK + false + + + SDI_DELAY + Delay MISO latching + false + + + Component_Name + spi_engine_execution_v1_0 + + + + + + virtex7 + + + /Analog_Devices + + spi_engine_execution_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/peripherals/spi_engine/engine + 1 + 2024-01-14T03:52:49Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v b/adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v new file mode 100644 index 00000000..418d2f01 --- /dev/null +++ b/adi_library/spi_engine/spi_engine_execution/spi_engine_execution.v @@ -0,0 +1,614 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module spi_engine_execution #( + + parameter NUM_OF_CS = 1, + parameter DEFAULT_SPI_CFG = 0, + parameter DEFAULT_CLK_DIV = 0, + parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32 + parameter NUM_OF_SDI = 1, + parameter [0:0] SDO_DEFAULT = 1'b0, + parameter ECHO_SCLK = 0, + parameter [1:0] SDI_DELAY = 2'b00 +) ( + input clk, + input resetn, + + output reg active, + + output cmd_ready, + input cmd_valid, + input [15:0] cmd, + + input sdo_data_valid, + output reg sdo_data_ready, + input [(DATA_WIDTH-1):0] sdo_data, + + input sdi_data_ready, + output reg sdi_data_valid, + output [(NUM_OF_SDI * DATA_WIDTH)-1:0] sdi_data, + + input sync_ready, + output reg sync_valid, + output [7:0] sync, + + input echo_sclk, + output reg sclk, + output reg sdo, + output reg sdo_t, + input [NUM_OF_SDI-1:0] sdi, + output reg [NUM_OF_CS-1:0] cs, + output reg three_wire +); + + localparam CMD_TRANSFER = 2'b00; + localparam CMD_CHIPSELECT = 2'b01; + localparam CMD_WRITE = 2'b10; + localparam CMD_MISC = 2'b11; + + localparam MISC_SYNC = 1'b0; + localparam MISC_SLEEP = 1'b1; + + localparam REG_CLK_DIV = 2'b00; + localparam REG_CONFIG = 2'b01; + localparam REG_WORD_LENGTH = 2'b10; + + localparam BIT_COUNTER_WIDTH = DATA_WIDTH > 16 ? 5 : + DATA_WIDTH > 8 ? 4 : 3; + + localparam BIT_COUNTER_CARRY = 2** (BIT_COUNTER_WIDTH + 1); + localparam BIT_COUNTER_CLEAR = {{8{1'b1}}, {BIT_COUNTER_WIDTH{1'b0}}, 1'b1}; + + reg sclk_int = 1'b0; + wire sdo_int_s; + reg sdo_t_int = 1'b0; + + reg idle; + + reg [7:0] clk_div_counter = 'h00; + reg [7:0] clk_div_counter_next = 'h00; + reg clk_div_last; + + reg [(BIT_COUNTER_WIDTH+8):0] counter = 'h00; + + wire [7:0] sleep_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)]; + wire [1:0] cs_sleep_counter = counter[(BIT_COUNTER_WIDTH+2):(BIT_COUNTER_WIDTH+1)]; + wire [(BIT_COUNTER_WIDTH-1):0] bit_counter = counter[BIT_COUNTER_WIDTH:1]; + wire [7:0] transfer_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)]; + wire ntx_rx = counter[0]; + + reg trigger = 1'b0; + reg trigger_next = 1'b0; + reg wait_for_io = 1'b0; + reg transfer_active = 1'b0; + + wire last_bit; + wire first_bit; + reg last_transfer; + reg [7:0] word_length = DATA_WIDTH; + reg [7:0] left_aligned = 8'b0; + wire end_of_word; + + reg [7:0] sdi_counter = 8'b0; + + assign first_bit = ((bit_counter == 'h0) || (bit_counter == word_length)); + + reg [15:0] cmd_d1; + + reg cpha = DEFAULT_SPI_CFG[0]; + reg cpol = DEFAULT_SPI_CFG[1]; + reg [7:0] clk_div = DEFAULT_CLK_DIV; + + reg sdo_enabled = 1'b0; + reg sdi_enabled = 1'b0; + + reg [(DATA_WIDTH-1):0] data_sdo_shift = 'h0; + + reg [SDI_DELAY+1:0] trigger_rx_d = {(SDI_DELAY+2){1'b0}}; + + wire [1:0] inst = cmd[13:12]; + wire [1:0] inst_d1 = cmd_d1[13:12]; + + wire exec_cmd = cmd_ready && cmd_valid; + wire exec_transfer_cmd = exec_cmd && inst == CMD_TRANSFER; + + wire exec_write_cmd = exec_cmd && inst == CMD_WRITE; + wire exec_chipselect_cmd = exec_cmd && inst == CMD_CHIPSELECT; + wire exec_misc_cmd = exec_cmd && inst == CMD_MISC; + wire exec_sync_cmd = exec_misc_cmd && cmd[8] == MISC_SYNC; + + wire trigger_tx; + wire trigger_rx; + + wire sleep_counter_compare; + wire cs_sleep_counter_compare; + wire cs_sleep_early_exit; + reg cs_sleep_repeat; + + wire io_ready1; + wire io_ready2; + wire trigger_rx_s; + + wire last_sdi_bit; + wire end_of_sdi_latch; + + (* direct_enable = "yes" *) wire cs_gen; + + assign cs_gen = inst_d1 == CMD_CHIPSELECT + && ((cs_sleep_counter_compare == 1'b1) || cs_sleep_early_exit) + && (cs_sleep_repeat == 1'b0) + && (idle == 1'b0); + assign cmd_ready = idle; + + always @(posedge clk) begin + if (exec_transfer_cmd) begin + sdo_enabled <= cmd[8]; + sdi_enabled <= cmd[9]; + end + end + + always @(posedge clk) begin + if (cmd_ready & cmd_valid) + cmd_d1 <= cmd; + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + active <= 1'b0; + end else begin + if (exec_cmd == 1'b1) + active <= 1'b1; + else if (sync_ready == 1'b1 && sync_valid == 1'b1) + active <= 1'b0; + end + end + + // Load the interface configurations from the 'Configuration Write' + // instruction + always @(posedge clk) begin + if (resetn == 1'b0) begin + cpha <= DEFAULT_SPI_CFG[0]; + cpol <= DEFAULT_SPI_CFG[1]; + three_wire <= DEFAULT_SPI_CFG[2]; + clk_div <= DEFAULT_CLK_DIV; + word_length <= DATA_WIDTH; + left_aligned <= 8'b0; + end else if (exec_write_cmd == 1'b1) begin + if (cmd[9:8] == REG_CONFIG) begin + cpha <= cmd[0]; + cpol <= cmd[1]; + three_wire <= cmd[2]; + end else if (cmd[9:8] == REG_CLK_DIV) begin + clk_div <= cmd[7:0]; + end else if (cmd[9:8] == REG_WORD_LENGTH) begin + // the max value of this reg must be DATA_WIDTH + word_length <= cmd[7:0]; + left_aligned <= DATA_WIDTH - cmd[7:0]; + end + end + end + + always @(posedge clk) begin + if ((clk_div_last == 1'b0 && idle == 1'b0 && wait_for_io == 1'b0 && + clk_div_counter == 'h01) || clk_div == 'h00) + clk_div_last <= 1'b1; + else + clk_div_last <= 1'b0; + end + + always @(posedge clk) begin + if (clk_div_last == 1'b1 || idle == 1'b1 || wait_for_io == 1'b1) begin + clk_div_counter <= clk_div; + trigger <= 1'b1; + end else begin + clk_div_counter <= clk_div_counter - 1'b1; + trigger <= 1'b0; + end + end + + assign trigger_tx = trigger == 1'b1 && ntx_rx == 1'b0; + assign trigger_rx = trigger == 1'b1 && ntx_rx == 1'b1; + + assign sleep_counter_compare = sleep_counter == cmd_d1[7:0]; + assign cs_sleep_counter_compare = cs_sleep_counter == cmd_d1[9:8]; + assign cs_sleep_early_exit = (cmd_d1[9:8] == 2'b00); + + always @(posedge clk) begin + if (resetn == 1'b0) begin + cs_sleep_repeat <= 1'b0; + end else begin + if (idle) begin + cs_sleep_repeat <= 1'b0; + end else if (cs_sleep_counter_compare && (inst_d1 == CMD_CHIPSELECT)) begin + cs_sleep_repeat <= !cs_sleep_repeat; + end + end + end + + always @(posedge clk) begin + if (idle == 1'b1 || (cs_sleep_counter_compare && !cs_sleep_repeat && inst_d1 == CMD_CHIPSELECT)) begin + counter <= 'h00; + end else if (clk_div_last == 1'b1 && wait_for_io == 1'b0) begin + if (bit_counter == word_length) begin + counter <= (counter & BIT_COUNTER_CLEAR) + (transfer_active ? 'h1 : (2**BIT_COUNTER_WIDTH)) + BIT_COUNTER_CARRY; + end else begin + counter <= counter + (transfer_active ? 'h1 : (2**BIT_COUNTER_WIDTH)); + end + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + idle <= 1'b1; + end else begin + if (exec_transfer_cmd || exec_chipselect_cmd || exec_misc_cmd) begin + idle <= 1'b0; + end else begin + case (inst_d1) + CMD_TRANSFER: begin + if (transfer_active == 1'b0 && wait_for_io == 1'b0 && end_of_sdi_latch == 1'b1) + idle <= 1'b1; + end + CMD_CHIPSELECT: begin + if ((cs_sleep_counter_compare && cs_sleep_repeat) || cs_sleep_early_exit) + idle <= 1'b1; + end + CMD_MISC: begin + case (cmd_d1[8]) + MISC_SLEEP: begin + if (sleep_counter_compare) + idle <= 1'b1; + end + MISC_SYNC: begin + if (sync_ready) + idle <= 1'b1; + end + endcase + end + endcase + end + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + cs <= 'hff; + end else if (cs_gen) begin + cs <= cmd_d1[NUM_OF_CS-1:0]; + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + sync_valid <= 1'b0; + end else begin + if (exec_sync_cmd == 1'b1) begin + sync_valid <= 1'b1; + end else if (sync_ready == 1'b1) begin + sync_valid <= 1'b0; + end + end + end + + assign sync = cmd_d1[7:0]; + + always @(posedge clk) begin + if (resetn == 1'b0) + sdo_data_ready <= 1'b0; + else if (sdo_enabled == 1'b1 && first_bit == 1'b1 && trigger_tx == 1'b1 && transfer_active == 1'b1) + sdo_data_ready <= 1'b1; + else if (sdo_data_valid == 1'b1) + sdo_data_ready <= 1'b0; + end + + assign io_ready1 = (sdi_data_valid == 1'b0 || sdi_data_ready == 1'b1) && + (sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1); + assign io_ready2 = (sdi_enabled == 1'b0 || sdi_data_ready == 1'b1) && + (sdo_enabled == 1'b0 || last_transfer == 1'b1 || sdo_data_valid == 1'b1); + + always @(posedge clk) begin + if (idle == 1'b1) begin + last_transfer <= 1'b0; + end else if (trigger_tx == 1'b1 && transfer_active == 1'b1) begin + if (transfer_counter == cmd_d1[7:0]) + last_transfer <= 1'b1; + else + last_transfer <= 1'b0; + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + transfer_active <= 1'b0; + wait_for_io <= 1'b0; + end else begin + if (exec_transfer_cmd == 1'b1) begin + wait_for_io <= 1'b1; + transfer_active <= 1'b0; + end else if (wait_for_io == 1'b1 && io_ready1 == 1'b1) begin + wait_for_io <= 1'b0; + if (last_transfer == 1'b0) + transfer_active <= 1'b1; + else + transfer_active <= 1'b0; + end else if (transfer_active == 1'b1 && end_of_word == 1'b1) begin + if (last_transfer == 1'b1 || io_ready2 == 1'b0) + transfer_active <= 1'b0; + if (io_ready2 == 1'b0) + wait_for_io <= 1'b1; + end + end + end + + always @(posedge clk) begin + if (transfer_active == 1'b1 || wait_for_io == 1'b1) + begin + sdo_t_int <= ~sdo_enabled; + end else begin + sdo_t_int <= 1'b1; + end + end + + // Load the SDO parallel data into the SDO shift register. In case of a custom + // data width, additional bit shifting must done at load. + always @(posedge clk) begin + if ((inst_d1 == CMD_TRANSFER) && (!sdo_enabled)) begin + data_sdo_shift <= {DATA_WIDTH{SDO_DEFAULT}}; + end else if (transfer_active == 1'b1 && trigger_tx == 1'b1) begin + if (first_bit == 1'b1) + data_sdo_shift <= sdo_data << left_aligned; + else + data_sdo_shift <= {data_sdo_shift[(DATA_WIDTH-2):0], 1'b0}; + end + end + + assign sdo_int_s = data_sdo_shift[DATA_WIDTH-1]; + + // In case of an interface with high clock rate (SCLK > 50MHz), the latch of + // the SDI line can be delayed with 1, 2 or 3 SPI core clock cycle. + // Taking the fact that in high SCLK frequencies the pre-scaler most likely will + // be set to 0, to reduce the core clock's speed, this delay will mean that SDI will + // be latched at one of the next consecutive SCLK edge. + + always @(posedge clk) begin + trigger_rx_d <= {trigger_rx_d, trigger_rx}; + end + + assign trigger_rx_s = trigger_rx_d[SDI_DELAY+1]; + + // Load the serial data into SDI shift register(s), then link it to the output + // register of the module + // NOTE: ECHO_SCLK mode can be used when the SCLK line is looped back to the FPGA + // through an other level shifter, in order to remove the round-trip timing delays + // introduced by the level shifters. This can improve the timing significantly + // on higher SCLK rates. Devices like ad4630 have an echod SCLK, which can be + // used to latch the MISO lines, improving the overall timing margin of the + // interface. + + wire cs_active_s = (inst_d1 == CMD_CHIPSELECT) & ~(&cmd_d1[NUM_OF_CS-1:0]); + genvar i; + + // NOTE: SPI configuration (CPOL/PHA) is only hardware configurable at this point + generate + if (ECHO_SCLK == 1) begin : g_echo_sclk_miso_latch + + reg [7:0] sdi_counter_d = 8'b0; + reg [7:0] sdi_transfer_counter = 8'b0; + reg [7:0] num_of_transfers = 8'b0; + reg [(NUM_OF_SDI * DATA_WIDTH)-1:0] sdi_data_latch = {(NUM_OF_SDI * DATA_WIDTH){1'b0}}; + + if ((DEFAULT_SPI_CFG[1:0] == 2'b01) || (DEFAULT_SPI_CFG[1:0] == 2'b10)) begin : g_echo_miso_nshift_reg + + // MISO shift register runs on negative echo_sclk + for (i=0; i + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/spi_engine/spi_engine_execution/spi_engine_execution_constr.ttcl b/adi_library/spi_engine/spi_engine_execution/spi_engine_execution_constr.ttcl new file mode 100644 index 00000000..c9cdf9b5 --- /dev/null +++ b/adi_library/spi_engine/spi_engine_execution/spi_engine_execution_constr.ttcl @@ -0,0 +1,35 @@ +############################################################################### +## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName [ttcl_add $ComponentName "_constr"] :> +<: setFileExtension ".xdc" :> +<: setFileProcessingOrder late :> +<: set echo_sclk [getBooleanValue "ECHO_SCLK"] :> + +# Relax the timing between the SDI shift register and DMA. The shift register +# runs at negative edge of echoSCLK and the DMA runs at spi_clk. Registers +# will have valid data at worst case (fastest rate) in every 8 echoSCLK cycle. + +set_multicycle_path -setup -from [get_pins -hier -filter {name=~*data_sdi_shift_reg[*]/C}] 8 +set_multicycle_path -hold -from [get_pins -hier -filter {name=~*data_sdi_shift_reg[*]/C}] 7 + +# word_length is updated before transfer, never changes during transfer, therefor +# it's safe to define a false path between word_length and sdi_counter +set_false_path -from [get_cells -hierarchical -filter {NAME=~*word_length_reg[*]}] -to [get_cells -hierarchical -filter {NAME=~*sdi_counter_reg[*]}] + +<: if { $echo_sclk } { :> + +## SDI counter runs on echo_SCLK but sdi_data_valid is generated with spi_clk which +# is synchronous to SCLK. The last_sdi_bit should be transferred into spi_clk domain. +set_property ASYNC_REG true [get_cells -hier {*last_sdi_bit_m_reg[0]}] +set_property ASYNC_REG true [get_cells -hier {*last_sdi_bit_m_reg[1]}] +set_false_path -to [get_cells -hier -filter {name =~ *last_sdi_bit_m_reg[0]* && IS_SEQUENTIAL}] + +# SDI shift registers are reset asynchronously after a negative edge of CSN - define the reset line as a false path +set_false_path -to [get_pins -hierarchical -filter {NAME=~*g_echo_sclk_miso_latch.*.data_sdi_shift_reg[*]/CLR}] + +<: } :> diff --git a/adi_library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl b/adi_library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl new file mode 100644 index 00000000..2dd42d85 --- /dev/null +++ b/adi_library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl @@ -0,0 +1,90 @@ +############################################################################### +## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +source ../../../scripts/adi_env.tcl +source ../../scripts/adi_ip_intel.tcl + +ad_ip_create spi_engine_execution {SPI Engine Execution} +set_module_property ELABORATION_CALLBACK p_elaboration +ad_ip_files spi_engine_execution [list\ + spi_engine_execution.v] + +# parameters + +ad_ip_parameter NUM_OF_CS INTEGER 1 +ad_ip_parameter DEFAULT_SPI_CFG INTEGER 0 +ad_ip_parameter DEFAULT_CLK_DIV INTEGER 0 +ad_ip_parameter DATA_WIDTH INTEGER 8 +ad_ip_parameter NUM_OF_SDI INTEGER 1 +ad_ip_parameter SDI_DELAY INTEGER 0 +ad_ip_parameter SDO_DEFAULT INTEGER 0 + +proc p_elaboration {} { + + set data_width [get_parameter_value DATA_WIDTH] + set num_of_sdi [get_parameter_value NUM_OF_SDI] + set num_of_cs [get_parameter_value NUM_OF_CS] + + # clock and reset interface + + ad_interface clock clk input 1 + ad_interface reset resetn input 1 if_clk + + ad_interface signal active output 1 + + # command interface + + add_interface cmd axi4stream end + add_interface_port cmd cmd_ready tready output 1 + add_interface_port cmd cmd_valid tvalid input 1 + add_interface_port cmd cmd tdata input 16 + + set_interface_property cmd associatedClock if_clk + set_interface_property cmd associatedReset if_resetn + + # SDO data interface + + add_interface sdo_data axi4stream end + add_interface_port sdo_data sdo_data_ready tready output 1 + add_interface_port sdo_data sdo_data_valid tvalid input 1 + add_interface_port sdo_data sdo_data tdata input $data_width + + set_interface_property sdo_data associatedClock if_clk + set_interface_property sdo_data associatedReset if_resetn + + # SDI data interface + + add_interface sdi_data axi4stream start + add_interface_port sdi_data sdi_data_ready tready input 1 + add_interface_port sdi_data sdi_data_valid tvalid output 1 + add_interface_port sdi_data sdi_data tdata output [expr $num_of_sdi * $data_width] + + set_interface_property sdi_data associatedClock if_clk + set_interface_property sdi_data associatedReset if_resetn + + # SYNC data interface + + add_interface sync axi4stream start + add_interface_port sync sync_valid tvalid output 1 + add_interface_port sync sync_ready tready input 1 + add_interface_port sync sync tdata output 8 + + set_interface_property sync associatedClock if_clk + set_interface_property sync associatedReset if_resetn + + # physical SPI interface + + ad_interface clock sclk output 1 + + ad_interface signal sdo output 1 + ad_interface signal sdo_t output 1 + ad_interface signal sdi input $num_of_sdi + + ad_interface signal cs output 1 + ad_interface signal three_wire output 1 + +} + diff --git a/adi_library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl b/adi_library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl new file mode 100644 index 00000000..84c16d7c --- /dev/null +++ b/adi_library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl @@ -0,0 +1,215 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create spi_engine_execution +adi_ip_files spi_engine_execution [list \ + "spi_engine_execution_constr.ttcl" \ + "spi_engine_execution.v" \ +] + +adi_ip_properties_lite spi_engine_execution +adi_ip_ttcl spi_engine_execution "spi_engine_execution_constr.ttcl" + +set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/spi_engine/engine} [ipx::current_core] + +# Remove all inferred interfaces +ipx::remove_all_bus_interface [ipx::current_core] + +## Interface definitions + +adi_add_bus "ctrl" "slave" \ + "analog.com:interface:spi_engine_ctrl_rtl:1.0" \ + "analog.com:interface:spi_engine_ctrl:1.0" \ + { + {"cmd_ready" "CMD_READY"} \ + {"cmd_valid" "CMD_VALID"} \ + {"cmd" "CMD_DATA"} \ + {"sdo_data_ready" "SDO_READY"} \ + {"sdo_data_valid" "SDO_VALID"} \ + {"sdo_data" "SDO_DATA"} \ + {"sdi_data_ready" "SDI_READY"} \ + {"sdi_data_valid" "SDI_VALID"} \ + {"sdi_data" "SDI_DATA"} \ + {"sync_ready" "SYNC_READY"} \ + {"sync_valid" "SYNC_VALID"} \ + {"sync" "SYNC_DATA"} \ + } +adi_add_bus_clock "clk" "ctrl" "resetn" + +adi_add_bus "spi" "master" \ + "analog.com:interface:spi_master_rtl:1.0" \ + "analog.com:interface:spi_master:1.0" \ + { + {"sclk" "SCLK"} \ + {"sdi" "SDI"} \ + {"sdo" "SDO"} \ + {"sdo_t" "SDO_T"} \ + {"three_wire" "THREE_WIRE"} \ + {"cs" "CS"} \ + } +adi_add_bus_clock "clk" "spi" "resetn" + +## Parameter validations + +set cc [ipx::current_core] + +## DATA_WIDTH +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "8" \ + "value_validation_range_maximum" "32" \ + ] \ + [ipx::get_user_parameters DATA_WIDTH -of_objects $cc] + +## NUM_OF_CS +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "1" \ + "value_validation_range_maximum" "8" \ + ] \ + [ipx::get_user_parameters NUM_OF_CS -of_objects $cc] + +## NUM_OF_SDI +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "1" \ + "value_validation_range_maximum" "8" \ + ] \ + [ipx::get_user_parameters NUM_OF_SDI -of_objects $cc] + +## DEFAULT_SPI_CFG +set_property -dict [list \ + "value_validation_type" "list" \ + "value_validation_list" "0 1 2 3" \ + ] \ + [ipx::get_user_parameters DEFAULT_SPI_CFG -of_objects $cc] + +## DEFAULT_CLK_DIV +set_property -dict [list \ + "value_validation_type" "list" \ + "value_validation_range_minimum" "0" \ + "value_validation_range_maximum" "255" \ + ] \ + [ipx::get_user_parameters DEFAULT_CLK_DIV -of_objects $cc] + +## SDO_DEFAULT +set_property -dict [list \ + "value_validation_type" "list" \ + "value_validation_list" "0 1" \ + ] \ + [ipx::get_user_parameters SDO_DEFAULT -of_objects $cc] + +## SDI_DELAY +set_property -dict [list \ + "value_format" "bool" \ + "value" "false" \ + ] \ + [ipx::get_user_parameters SDI_DELAY -of_objects $cc] +set_property -dict [list \ + "value_format" "bool" \ + "value" "false" \ + ] \ + [ipx::get_hdl_parameters SDI_DELAY -of_objects $cc] + +## ECHO SCLK +set_property -dict [list \ + "value_format" "bool" \ + "value" "false" \ + ] \ + [ipx::get_user_parameters ECHO_SCLK -of_objects $cc] +set_property -dict [list \ + "value_format" "bool" \ + "value" "false" \ + ] \ + [ipx::get_hdl_parameters ECHO_SCLK -of_objects $cc] + +## echo_sclk should be active only when ECHO_SCLK is set +adi_set_ports_dependency echo_sclk ECHO_SCLK 0 + +## Customize IP Layout + +## Remove the automatically generated GUI page +ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] +ipx::save_core [ipx::current_core] + +## Create general configuration page +ipgui::add_page -name {SPI Engine execution} -component [ipx::current_core] -display_name {AXI SPI Engine execution} +set page0 [ipgui::get_pagespec -name "SPI Engine execution" -component $cc] + +set general_group [ipgui::add_group -name "General Configuration" -component $cc \ + -parent $page0 -display_name "General Configuration" ] + +ipgui::add_param -name "DATA_WIDTH" -component $cc -parent $general_group +set_property -dict [list \ + "display_name" "Parallel data width" \ + "tooltip" "\[DATA_WIDTH\] Define the data interface width" +] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc] + +ipgui::add_param -name "NUM_OF_CS" -component $cc -parent $general_group +set_property -dict [list \ + "display_name" "Number of CSN lines" \ + "tooltip" "\[NUM_OF_CS\] Define the number of chip select lines" \ +] [ipgui::get_guiparamspec -name "NUM_OF_CS" -component $cc] + +ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group +set_property -dict [list \ + "display_name" "Number of MISO lines" \ + "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \ +] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc] + +set spi_config_group [ipgui::add_group -name "SPI Configuration" -component $cc \ + -parent $page0 -display_name "SPI Configuration" ] + +ipgui::add_param -name "DEFAULT_SPI_CFG" -component $cc -parent $spi_config_group +set_property -dict [list \ + "widget" "comboBox" \ + "display_name" "Default SPI mode" \ + "tooltip" "\[DEFAULT_SPI_CFG\] Define the default SPI configuration, bit 1 defines CPOL, bit 0 defines CPHA" +] [ipgui::get_guiparamspec -name "DEFAULT_SPI_CFG" -component $cc] + +ipgui::add_param -name "DEFAULT_CLK_DIV" -component $cc -parent $spi_config_group +set_property -dict [list \ + "display_name" "Default SCLK divider" \ + "tooltip" "\[DEFAULT_CLK_DIV\] Define the default SCLK divider, fSCLK = fCoreClk / DEFAULT_CLK_DIV + 1" +] [ipgui::get_guiparamspec -name "DEFAULT_CLK_DIV" -component $cc] + +set mosi_miso_config_group [ipgui::add_group -name "MOSI/MISO Configuration" -component $cc \ + -parent $page0 -display_name "MOSI/MISO Configuration" ] + +ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $mosi_miso_config_group +set_property -dict [list \ + "display_name" "Number of MISO" \ + "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" +] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc] + +ipgui::add_param -name "SDI_DELAY" -component $cc -parent $mosi_miso_config_group +set_property -dict [list \ + "display_name" "Delay MISO latching" \ + "tooltip" "\[SDI_DELAY\] Delay the MISO latching to the next consecutive SCLK edge" +] [ipgui::get_guiparamspec -name "SDI_DELAY" -component $cc] + +ipgui::add_param -name "SDO_DEFAULT" -component $cc -parent $mosi_miso_config_group +set_property -dict [list \ + "widget" "comboBox" \ + "display_name" "MOSI default level" \ + "tooltip" "\[SDO_DEFAULT\] Define the default voltage level on MOSI" +] [ipgui::get_guiparamspec -name "SDO_DEFAULT" -component $cc] + +set custom_clocking_group [ipgui::add_group -name "Custom clocking options" -component $cc \ + -parent $page0 -display_name "Custom clocking options" ] + +ipgui::add_param -name "ECHO_SCLK" -component $cc -parent $custom_clocking_group +set_property -dict [list \ + "display_name" "Echoed SCLK" \ + "tooltip" "\[ECHO_SCLK\] Activate echo SCLK option (hardware support required)" +] [ipgui::get_guiparamspec -name "ECHO_SCLK" -component $cc] + +## Create and save the XGUI file +ipx::create_xgui_files $cc + +ipx::save_core [ipx::current_core] diff --git a/adi_library/spi_engine/spi_engine_execution/xgui/spi_engine_execution_v1_0.tcl b/adi_library/spi_engine/spi_engine_execution/xgui/spi_engine_execution_v1_0.tcl new file mode 100644 index 00000000..4ba62355 --- /dev/null +++ b/adi_library/spi_engine/spi_engine_execution/xgui/spi_engine_execution_v1_0.tcl @@ -0,0 +1,150 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set SPI_Engine_execution [ipgui::add_page $IPINST -name "SPI Engine execution" -display_name {AXI SPI Engine execution}] + #Adding Group + set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${SPI_Engine_execution}] + set DATA_WIDTH [ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${General_Configuration}] + set_property tooltip {[DATA_WIDTH] Define the data interface width} ${DATA_WIDTH} + set NUM_OF_CS [ipgui::add_param $IPINST -name "NUM_OF_CS" -parent ${General_Configuration}] + set_property tooltip {[NUM_OF_CS] Define the number of chip select lines} ${NUM_OF_CS} + set NUM_OF_SDI [ipgui::add_param $IPINST -name "NUM_OF_SDI" -parent ${General_Configuration}] + set_property tooltip {[NUM_OF_SDI] Define the number of MISO lines} ${NUM_OF_SDI} + + #Adding Group + set SPI_Configuration [ipgui::add_group $IPINST -name "SPI Configuration" -parent ${SPI_Engine_execution}] + set DEFAULT_SPI_CFG [ipgui::add_param $IPINST -name "DEFAULT_SPI_CFG" -parent ${SPI_Configuration} -widget comboBox] + set_property tooltip {[DEFAULT_SPI_CFG] Define the default SPI configuration, bit 1 defines CPOL, bit 0 defines CPHA} ${DEFAULT_SPI_CFG} + set DEFAULT_CLK_DIV [ipgui::add_param $IPINST -name "DEFAULT_CLK_DIV" -parent ${SPI_Configuration}] + set_property tooltip {[DEFAULT_CLK_DIV] Define the default SCLK divider, fSCLK = fCoreClk / DEFAULT_CLK_DIV + 1} ${DEFAULT_CLK_DIV} + + #Adding Group + set MOSI/MISO_Configuration [ipgui::add_group $IPINST -name "MOSI/MISO Configuration" -parent ${SPI_Engine_execution}] + set SDI_DELAY [ipgui::add_param $IPINST -name "SDI_DELAY" -parent ${MOSI/MISO_Configuration}] + set_property tooltip {[SDI_DELAY] Delay the MISO latching to the next consecutive SCLK edge} ${SDI_DELAY} + set SDO_DEFAULT [ipgui::add_param $IPINST -name "SDO_DEFAULT" -parent ${MOSI/MISO_Configuration} -widget comboBox] + set_property tooltip {[SDO_DEFAULT] Define the default voltage level on MOSI} ${SDO_DEFAULT} + + #Adding Group + set Custom_clocking_options [ipgui::add_group $IPINST -name "Custom clocking options" -parent ${SPI_Engine_execution}] + set ECHO_SCLK [ipgui::add_param $IPINST -name "ECHO_SCLK" -parent ${Custom_clocking_options}] + set_property tooltip {[ECHO_SCLK] Activate echo SCLK option (hardware support required)} ${ECHO_SCLK} + + + +} + +proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to validate DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.DEFAULT_CLK_DIV { PARAM_VALUE.DEFAULT_CLK_DIV } { + # Procedure called to update DEFAULT_CLK_DIV when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEFAULT_CLK_DIV { PARAM_VALUE.DEFAULT_CLK_DIV } { + # Procedure called to validate DEFAULT_CLK_DIV + return true +} + +proc update_PARAM_VALUE.DEFAULT_SPI_CFG { PARAM_VALUE.DEFAULT_SPI_CFG } { + # Procedure called to update DEFAULT_SPI_CFG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEFAULT_SPI_CFG { PARAM_VALUE.DEFAULT_SPI_CFG } { + # Procedure called to validate DEFAULT_SPI_CFG + return true +} + +proc update_PARAM_VALUE.ECHO_SCLK { PARAM_VALUE.ECHO_SCLK } { + # Procedure called to update ECHO_SCLK when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ECHO_SCLK { PARAM_VALUE.ECHO_SCLK } { + # Procedure called to validate ECHO_SCLK + return true +} + +proc update_PARAM_VALUE.NUM_OF_CS { PARAM_VALUE.NUM_OF_CS } { + # Procedure called to update NUM_OF_CS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_CS { PARAM_VALUE.NUM_OF_CS } { + # Procedure called to validate NUM_OF_CS + return true +} + +proc update_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } { + # Procedure called to update NUM_OF_SDI when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } { + # Procedure called to validate NUM_OF_SDI + return true +} + +proc update_PARAM_VALUE.SDI_DELAY { PARAM_VALUE.SDI_DELAY } { + # Procedure called to update SDI_DELAY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SDI_DELAY { PARAM_VALUE.SDI_DELAY } { + # Procedure called to validate SDI_DELAY + return true +} + +proc update_PARAM_VALUE.SDO_DEFAULT { PARAM_VALUE.SDO_DEFAULT } { + # Procedure called to update SDO_DEFAULT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SDO_DEFAULT { PARAM_VALUE.SDO_DEFAULT } { + # Procedure called to validate SDO_DEFAULT + return true +} + + +proc update_MODELPARAM_VALUE.NUM_OF_CS { MODELPARAM_VALUE.NUM_OF_CS PARAM_VALUE.NUM_OF_CS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_CS}] ${MODELPARAM_VALUE.NUM_OF_CS} +} + +proc update_MODELPARAM_VALUE.DEFAULT_SPI_CFG { MODELPARAM_VALUE.DEFAULT_SPI_CFG PARAM_VALUE.DEFAULT_SPI_CFG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEFAULT_SPI_CFG}] ${MODELPARAM_VALUE.DEFAULT_SPI_CFG} +} + +proc update_MODELPARAM_VALUE.DEFAULT_CLK_DIV { MODELPARAM_VALUE.DEFAULT_CLK_DIV PARAM_VALUE.DEFAULT_CLK_DIV } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEFAULT_CLK_DIV}] ${MODELPARAM_VALUE.DEFAULT_CLK_DIV} +} + +proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.NUM_OF_SDI { MODELPARAM_VALUE.NUM_OF_SDI PARAM_VALUE.NUM_OF_SDI } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_SDI}] ${MODELPARAM_VALUE.NUM_OF_SDI} +} + +proc update_MODELPARAM_VALUE.SDO_DEFAULT { MODELPARAM_VALUE.SDO_DEFAULT PARAM_VALUE.SDO_DEFAULT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SDO_DEFAULT}] ${MODELPARAM_VALUE.SDO_DEFAULT} +} + +proc update_MODELPARAM_VALUE.ECHO_SCLK { MODELPARAM_VALUE.ECHO_SCLK PARAM_VALUE.ECHO_SCLK } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ECHO_SCLK}] ${MODELPARAM_VALUE.ECHO_SCLK} +} + +proc update_MODELPARAM_VALUE.SDI_DELAY { MODELPARAM_VALUE.SDI_DELAY PARAM_VALUE.SDI_DELAY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SDI_DELAY}] ${MODELPARAM_VALUE.SDI_DELAY} +} + diff --git a/adi_library/spi_engine/spi_engine_interconnect/Makefile b/adi_library/spi_engine/spi_engine_interconnect/Makefile new file mode 100644 index 00000000..6624efa0 --- /dev/null +++ b/adi_library/spi_engine/spi_engine_interconnect/Makefile @@ -0,0 +1,18 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := spi_engine_interconnect + +GENERIC_DEPS += spi_engine_interconnect.v + +XILINX_DEPS += spi_engine_interconnect_ip.tcl + +XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml +XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml + +INTEL_DEPS += spi_engine_interconnect_hw.tcl + +include ../../scripts/library.mk diff --git a/adi_library/spi_engine/spi_engine_interconnect/component.xml b/adi_library/spi_engine/spi_engine_interconnect/component.xml new file mode 100644 index 00000000..9c927203 --- /dev/null +++ b/adi_library/spi_engine/spi_engine_interconnect/component.xml @@ -0,0 +1,1195 @@ + + + analog.com + user + spi_engine_interconnect + 1.0 + + + m_ctrl + + + + + + + CMD_READY + + + m_cmd_ready + + + + + CMD_VALID + + + m_cmd_valid + + + + + CMD_DATA + + + m_cmd_data + + + + + SDO_READY + + + m_sdo_ready + + + + + SDO_VALID + + + m_sdo_valid + + + + + SDO_DATA + + + m_sdo_data + + + + + SDI_READY + + + m_sdi_ready + + + + + SDI_VALID + + + m_sdi_valid + + + + + SDI_DATA + + + m_sdi_data + + + + + SYNC_READY + + + m_sync_ready + + + + + SYNC_VALID + + + m_sync_valid + + + + + SYNC_DATA + + + m_sync + + + + + + m_ctrl_signal_clock + m_ctrl_signal_clock + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_BUSIF + m_ctrl + + + ASSOCIATED_RESET + resetn + + + + + m_ctrl_signal_reset + m_ctrl_signal_reset + + + + + + + RST + + + resetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s0_ctrl + + + + + + + CMD_READY + + + s0_cmd_ready + + + + + CMD_VALID + + + s0_cmd_valid + + + + + CMD_DATA + + + s0_cmd_data + + + + + SDO_READY + + + s0_sdo_ready + + + + + SDO_VALID + + + s0_sdo_valid + + + + + SDO_DATA + + + s0_sdo_data + + + + + SDI_READY + + + s0_sdi_ready + + + + + SDI_VALID + + + s0_sdi_valid + + + + + SDI_DATA + + + s0_sdi_data + + + + + SYNC_READY + + + s0_sync_ready + + + + + SYNC_VALID + + + s0_sync_valid + + + + + SYNC_DATA + + + s0_sync + + + + + + s0_ctrl_signal_clock + s0_ctrl_signal_clock + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_BUSIF + s0_ctrl + + + ASSOCIATED_RESET + resetn + + + + + s0_ctrl_signal_reset + s0_ctrl_signal_reset + + + + + + + RST + + + resetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s1_ctrl + + + + + + + CMD_READY + + + s1_cmd_ready + + + + + CMD_VALID + + + s1_cmd_valid + + + + + CMD_DATA + + + s1_cmd_data + + + + + SDO_READY + + + s1_sdo_ready + + + + + SDO_VALID + + + s1_sdo_valid + + + + + SDO_DATA + + + s1_sdo_data + + + + + SDI_READY + + + s1_sdi_ready + + + + + SDI_VALID + + + s1_sdi_valid + + + + + SDI_DATA + + + s1_sdi_data + + + + + SYNC_READY + + + s1_sync_ready + + + + + SYNC_VALID + + + s1_sync_valid + + + + + SYNC_DATA + + + s1_sync + + + + + + s1_ctrl_signal_clock + s1_ctrl_signal_clock + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_BUSIF + s1_ctrl + + + ASSOCIATED_RESET + resetn + + + + + s1_ctrl_signal_reset + s1_ctrl_signal_reset + + + + + + + RST + + + resetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + spi_engine_interconnect + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + d4ae3839 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + spi_engine_interconnect + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + d4ae3839 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + e4fdc10e + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + resetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_cmd_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_cmd_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_cmd_data + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_sdo_valid + + out + + + std_logic + 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s0_sdi_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_sdi_data + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_sync_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s0_sync_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s0_sync + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_cmd_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_cmd_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_cmd_data + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s1_sdo_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_sdo_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_sdo_data + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s1_sdi_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_sdi_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_sdi_data + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_sync_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s1_sync_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s1_sync + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + DATA_WIDTH + Data Width + 8 + + + NUM_OF_SDI + Num Of Sdi + 1 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + spi_engine_interconnect.v + verilogSource + CHECKSUM_d4ae3839 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + spi_engine_interconnect.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/spi_engine_interconnect_v1_0.tcl + tclSource + CHECKSUM_d9e58594 + XGUI_VERSION_2 + + + + spi_engine_interconnect_v1_0 + + + DATA_WIDTH + Parallel data width + 8 + + + NUM_OF_SDI + Number of MISO lines + 1 + + + Component_Name + spi_engine_interconnect_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + spi_engine_interconnect_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/peripherals/spi_engine/interconnect + 1 + 2024-01-14T03:52:56Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v b/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v new file mode 100644 index 00000000..85d1d1d4 --- /dev/null +++ b/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v @@ -0,0 +1,144 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module spi_engine_interconnect #( + + parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32 + parameter NUM_OF_SDI = 1 +) ( + input clk, + input resetn, + + output m_cmd_valid, + input m_cmd_ready, + output [15:0] m_cmd_data, + + output m_sdo_valid, + input m_sdo_ready, + output [(DATA_WIDTH-1):0] m_sdo_data, + + input m_sdi_valid, + output m_sdi_ready, + input [(NUM_OF_SDI * DATA_WIDTH-1):0] m_sdi_data, + + input m_sync_valid, + output m_sync_ready, + input [7:0] m_sync, + + input s0_cmd_valid, + output s0_cmd_ready, + input [15:0] s0_cmd_data, + + input s0_sdo_valid, + output s0_sdo_ready, + input [(DATA_WIDTH-1):0] s0_sdo_data, + + output s0_sdi_valid, + input s0_sdi_ready, + output [(NUM_OF_SDI * DATA_WIDTH-1):0] s0_sdi_data, + + output s0_sync_valid, + input s0_sync_ready, + output [7:0] s0_sync, + + input s1_cmd_valid, + output s1_cmd_ready, + input [15:0] s1_cmd_data, + + input s1_sdo_valid, + output s1_sdo_ready, + input [(DATA_WIDTH-1):0] s1_sdo_data, + + output s1_sdi_valid, + input s1_sdi_ready, + output [(NUM_OF_SDI * DATA_WIDTH-1):0] s1_sdi_data, + + output s1_sync_valid, + input s1_sync_ready, + output [7:0] s1_sync +); + + reg s_active = 1'b0; + + reg idle = 1'b1; + + `define spi_engine_interconnect_mux(s0, s1) (idle == 1'b1 ? 1'b0 : (s_active == 1'b0 ? s0 : s1)) + + assign m_cmd_data = s_active == 1'b0 ? s0_cmd_data : s1_cmd_data; + assign m_cmd_valid = `spi_engine_interconnect_mux(s0_cmd_valid, s1_cmd_valid); + assign s0_cmd_ready = `spi_engine_interconnect_mux(m_cmd_ready, 1'b0); + assign s1_cmd_ready = `spi_engine_interconnect_mux(1'b0, m_cmd_ready); + + assign m_sdo_data = s_active == 1'b0 ? s0_sdo_data : s1_sdo_data; + assign m_sdo_valid = `spi_engine_interconnect_mux(s0_sdo_valid, s1_sdo_valid); + assign s0_sdo_ready = `spi_engine_interconnect_mux(m_sdo_ready, 1'b0); + assign s1_sdo_ready = `spi_engine_interconnect_mux(1'b0, m_sdo_ready); + + assign s0_sdi_data = m_sdi_data; + assign s1_sdi_data = m_sdi_data; + assign m_sdi_ready = `spi_engine_interconnect_mux(s0_sdi_ready, s1_sdi_ready); + assign s0_sdi_valid = `spi_engine_interconnect_mux(m_sdi_valid, 1'b0); + assign s1_sdi_valid = `spi_engine_interconnect_mux(1'b0, m_sdi_valid); + + assign s0_sync = m_sync; + assign s1_sync = m_sync; + assign m_sync_ready = `spi_engine_interconnect_mux(s0_sync_ready, s1_sync_ready); + assign s0_sync_valid = `spi_engine_interconnect_mux(m_sync_valid, 1'b0); + assign s1_sync_valid = `spi_engine_interconnect_mux(1'b0, m_sync_valid); + + always @(posedge clk) begin + if (idle == 1'b1) begin + if (s0_cmd_valid) + s_active <= 1'b0; + else if (s1_cmd_valid) + s_active <= 1'b1; + end + end + + always @(posedge clk) begin + if (resetn == 1'b0) begin + idle <= 1'b1; + end else begin + if (m_sync_valid == 1'b1 && m_sync_ready == 1'b1) begin + idle <= 1'b1; + end else if (s0_cmd_valid == 1'b1 || s1_cmd_valid == 1'b1) begin + idle <= 1'b0; + end + end + end + +endmodule diff --git a/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr b/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr new file mode 100644 index 00000000..a29644b1 --- /dev/null +++ b/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.xpr @@ -0,0 +1,399 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_hw.tcl b/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_hw.tcl new file mode 100644 index 00000000..0dda130a --- /dev/null +++ b/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_hw.tcl @@ -0,0 +1,150 @@ +############################################################################### +## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +source ../../../scripts/adi_env.tcl +source ../../scripts/adi_ip_intel.tcl + +ad_ip_create spi_engine_interconnect {SPI Engine Interconnect} p_elaboration +ad_ip_files spi_engine_interconnect [list\ + spi_engine_interconnect.v] + +# parameters + +ad_ip_parameter DATA_WIDTH INTEGER 8 +ad_ip_parameter NUM_OF_SDI INTEGER 1 + +proc p_elaboration {} { + + set data_width [get_parameter_value DATA_WIDTH] + set num_of_sdi [get_parameter_value NUM_OF_SDI] + + # clock and reset interface + + ad_interface clock clk input 1 + ad_interface reset resetn input 1 if_clk + + # command master interface + + add_interface m_cmd axi4stream start + add_interface_port m_cmd m_cmd_ready tready input 1 + add_interface_port m_cmd m_cmd_valid tvalid output 1 + add_interface_port m_cmd m_cmd_data tdata output 16 + + set_interface_property m_cmd associatedClock if_clk + set_interface_property m_cmd associatedReset if_resetn + + # SDO data master interface + + add_interface m_sdo axi4stream start + add_interface_port m_sdo m_sdo_ready tready input 1 + add_interface_port m_sdo m_sdo_valid tvalid output 1 + add_interface_port m_sdo m_sdo_data tdata output $data_width + + set_interface_property m_sdo associatedClock if_clk + set_interface_property m_sdo associatedReset if_resetn + + # SDI data master interface + + add_interface m_sdi axi4stream end + add_interface_port m_sdi m_sdi_ready tready output 1 + add_interface_port m_sdi m_sdi_valid tvalid input 1 + add_interface_port m_sdi m_sdi_data tdata input [expr $num_of_sdi * $data_width] + + set_interface_property m_sdi associatedClock if_clk + set_interface_property m_sdi associatedReset if_resetn + + # SYNC master interface + + add_interface m_sync axi4stream end + add_interface_port m_sync m_sync_valid tvalid input 1 + add_interface_port m_sync m_sync_ready tready output 1 + add_interface_port m_sync m_sync tdata input 8 + + set_interface_property m_sync associatedClock if_clk + set_interface_property m_sync associatedReset if_resetn + + # command slave0 interface + + add_interface s0_cmd axi4stream end + add_interface_port s0_cmd s0_cmd_ready tready output 1 + add_interface_port s0_cmd s0_cmd_valid tvalid input 1 + add_interface_port s0_cmd s0_cmd_data tdata input 16 + + set_interface_property s0_cmd associatedClock if_clk + set_interface_property s0_cmd associatedReset if_resetn + + # SDO data slave0 interface + + add_interface s0_sdo axi4stream end + add_interface_port s0_sdo s0_sdo_ready tready output 1 + add_interface_port s0_sdo s0_sdo_valid tvalid input 1 + add_interface_port s0_sdo s0_sdo_data tdata input $data_width + + set_interface_property s0_sdo associatedClock if_clk + set_interface_property s0_sdo associatedReset if_resetn + + # SDI data slave0 interface + + add_interface s0_sdi axi4stream start + add_interface_port s0_sdi s0_sdi_ready tready input 1 + add_interface_port s0_sdi s0_sdi_valid tvalid output 1 + add_interface_port s0_sdi s0_sdi_data tdata output [expr $num_of_sdi * $data_width] + + set_interface_property s0_sdi associatedClock if_clk + set_interface_property s0_sdi associatedReset if_resetn + + # SYNC slave0 interface + + add_interface s0_sync axi4stream start + add_interface_port s0_sync s0_sync_valid tvalid output 1 + add_interface_port s0_sync s0_sync_ready tready input 1 + add_interface_port s0_sync s0_sync tdata output 8 + + set_interface_property s0_sync associatedClock if_clk + set_interface_property s0_sync associatedReset if_resetn + + # command slave1 interface + + add_interface s1_cmd axi4stream end + add_interface_port s1_cmd s1_cmd_ready tready output 1 + add_interface_port s1_cmd s1_cmd_valid tvalid input 1 + add_interface_port s1_cmd s1_cmd_data tdata input 16 + + set_interface_property s1_cmd associatedClock if_clk + set_interface_property s1_cmd associatedReset if_resetn + + # SDO data slave1 interface + + add_interface s1_sdo axi4stream end + add_interface_port s1_sdo s1_sdo_ready tready output 1 + add_interface_port s1_sdo s1_sdo_valid tvalid input 1 + add_interface_port s1_sdo s1_sdo_data tdata input $data_width + + set_interface_property s1_sdo associatedClock if_clk + set_interface_property s1_sdo associatedReset if_resetn + + # SDI data slave1 interface + + add_interface s1_sdi axi4stream start + add_interface_port s1_sdi s1_sdi_ready tready input 1 + add_interface_port s1_sdi s1_sdi_valid tvalid output 1 + add_interface_port s1_sdi s1_sdi_data tdata output [expr $num_of_sdi * $data_width] + + set_interface_property s1_sdi associatedClock if_clk + set_interface_property s1_sdi associatedReset if_resetn + + # SYNC slave1 interface + + add_interface s1_sync axi4stream start + add_interface_port s1_sync s1_sync_valid tvalid output 1 + add_interface_port s1_sync s1_sync_ready tready input 1 + add_interface_port s1_sync s1_sync tdata output 8 + + set_interface_property s1_sync associatedClock if_clk + set_interface_property s1_sync associatedReset if_resetn + +} + diff --git a/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.tcl b/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.tcl new file mode 100644 index 00000000..49e19b6e --- /dev/null +++ b/adi_library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_ip.tcl @@ -0,0 +1,111 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create spi_engine_interconnect +adi_ip_files spi_engine_interconnect [list \ + "spi_engine_interconnect.v" \ +] + +adi_ip_properties_lite spi_engine_interconnect + +set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/spi_engine/interconnect} [ipx::current_core] + +# Remove all inferred interfaces +ipx::remove_all_bus_interface [ipx::current_core] + +## Interface definitions + +adi_add_bus "m_ctrl" "master" \ + "analog.com:interface:spi_engine_ctrl_rtl:1.0" \ + "analog.com:interface:spi_engine_ctrl:1.0" \ + { \ + {"m_cmd_ready" "CMD_READY"} \ + {"m_cmd_valid" "CMD_VALID"} \ + {"m_cmd_data" "CMD_DATA"} \ + {"m_sdo_ready" "SDO_READY"} \ + {"m_sdo_valid" "SDO_VALID"} \ + {"m_sdo_data" "SDO_DATA"} \ + {"m_sdi_ready" "SDI_READY"} \ + {"m_sdi_valid" "SDI_VALID"} \ + {"m_sdi_data" "SDI_DATA"} \ + {"m_sync_ready" "SYNC_READY"} \ + {"m_sync_valid" "SYNC_VALID"} \ + {"m_sync" "SYNC_DATA"} \ + } +adi_add_bus_clock "clk" "m_ctrl" "resetn" + +foreach prefix [list "s0" "s1"] { + adi_add_bus [format "%s_ctrl" $prefix] "slave" \ + "analog.com:interface:spi_engine_ctrl_rtl:1.0" \ + "analog.com:interface:spi_engine_ctrl:1.0" \ + [list \ + [list [format "%s_cmd_ready" $prefix] "CMD_READY"] \ + [list [format "%s_cmd_valid" $prefix] "CMD_VALID"] \ + [list [format "%s_cmd_data" $prefix] "CMD_DATA"] \ + [list [format "%s_sdo_ready" $prefix] "SDO_READY"] \ + [list [format "%s_sdo_valid" $prefix] "SDO_VALID"] \ + [list [format "%s_sdo_data" $prefix] "SDO_DATA"] \ + [list [format "%s_sdi_ready" $prefix] "SDI_READY"] \ + [list [format "%s_sdi_valid" $prefix] "SDI_VALID"] \ + [list [format "%s_sdi_data" $prefix] "SDI_DATA"] \ + [list [format "%s_sync_ready" $prefix] "SYNC_READY"] \ + [list [format "%s_sync_valid" $prefix] "SYNC_VALID"] \ + [list [format "%s_sync" $prefix] "SYNC_DATA"] \ + ] + adi_add_bus_clock "clk" [format "%s_ctrl" $prefix] "resetn" +} + +## Parameter validations + +set cc [ipx::current_core] + +## DATA_WIDTH +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "8" \ + "value_validation_range_maximum" "256" \ + ] \ + [ipx::get_user_parameters DATA_WIDTH -of_objects $cc] + +## NUM_OF_SDI +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "1" \ + "value_validation_range_maximum" "8" \ + ] \ + [ipx::get_user_parameters NUM_OF_SDI -of_objects $cc] + +## Customize IP Layout + +## Remove the automatically generated GUI page +ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] +ipx::save_core [ipx::current_core] + +## Create general configuration page +ipgui::add_page -name {SPI Engine interconnect} -component [ipx::current_core] -display_name {SPI Engine interconnect} +set page0 [ipgui::get_pagespec -name "SPI Engine interconnect" -component $cc] + +set general_group [ipgui::add_group -name "General Configuration" -component $cc \ + -parent $page0 -display_name "General Configuration" ] + +ipgui::add_param -name "DATA_WIDTH" -component $cc -parent $general_group +set_property -dict [list \ + "display_name" "Parallel data width" \ + "tooltip" "\[DATA_WIDTH\] Define the data interface width" +] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc] + +ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group +set_property -dict [list \ + "display_name" "Number of MISO lines" \ + "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \ +] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc] + +## Create and save the XGUI file +ipx::create_xgui_files $cc + +ipx::save_core [ipx::current_core] diff --git a/adi_library/spi_engine/spi_engine_interconnect/xgui/spi_engine_interconnect_v1_0.tcl b/adi_library/spi_engine/spi_engine_interconnect/xgui/spi_engine_interconnect_v1_0.tcl new file mode 100644 index 00000000..f9cae07b --- /dev/null +++ b/adi_library/spi_engine/spi_engine_interconnect/xgui/spi_engine_interconnect_v1_0.tcl @@ -0,0 +1,45 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set SPI_Engine_interconnect [ipgui::add_page $IPINST -name "SPI Engine interconnect"] + #Adding Group + set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${SPI_Engine_interconnect}] + set DATA_WIDTH [ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${General_Configuration}] + set_property tooltip {[DATA_WIDTH] Define the data interface width} ${DATA_WIDTH} + set NUM_OF_SDI [ipgui::add_param $IPINST -name "NUM_OF_SDI" -parent ${General_Configuration}] + set_property tooltip {[NUM_OF_SDI] Define the number of MISO lines} ${NUM_OF_SDI} + + + +} + +proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to validate DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } { + # Procedure called to update NUM_OF_SDI when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } { + # Procedure called to validate NUM_OF_SDI + return true +} + + +proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.NUM_OF_SDI { MODELPARAM_VALUE.NUM_OF_SDI PARAM_VALUE.NUM_OF_SDI } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_SDI}] ${MODELPARAM_VALUE.NUM_OF_SDI} +} + diff --git a/adi_library/spi_engine/spi_engine_offload/Makefile b/adi_library/spi_engine/spi_engine_offload/Makefile new file mode 100644 index 00000000..0a7e97da --- /dev/null +++ b/adi_library/spi_engine/spi_engine_offload/Makefile @@ -0,0 +1,24 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := spi_engine_offload + +GENERIC_DEPS += spi_engine_offload.v + +XILINX_DEPS += spi_engine_offload_constr.ttcl +XILINX_DEPS += spi_engine_offload_ip.tcl + +XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml +XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml +XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl.xml +XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml + +XILINX_LIB_DEPS += util_cdc + +INTEL_DEPS += ../../util_cdc/sync_bits.v +INTEL_DEPS += spi_engine_offload_hw.tcl + +include ../../scripts/library.mk diff --git a/adi_library/spi_engine/spi_engine_offload/component.xml b/adi_library/spi_engine/spi_engine_offload/component.xml new file mode 100644 index 00000000..9266627e --- /dev/null +++ b/adi_library/spi_engine/spi_engine_offload/component.xml @@ -0,0 +1,954 @@ + + + analog.com + user + spi_engine_offload + 1.0 + + + spi_engine_ctrl + + + + + + + CMD_READY + + + cmd_ready + + + + + CMD_VALID + + + cmd_valid + + + + + CMD_DATA + + + cmd + + + + + SDO_READY + + + sdo_data_ready + + + + + SDO_VALID + + + sdo_data_valid + + + + + SDO_DATA + + + sdo_data + + + + + SDI_READY + + + sdi_data_ready + + + + + SDI_VALID + + + sdi_data_valid + + + + + SDI_DATA + + + sdi_data + + + + + SYNC_READY + + + sync_ready + + + + + SYNC_VALID + + + sync_valid + + + + + SYNC_DATA + + + sync_data + + + + + + spi_engine_offload_ctrl + + + + + + + CMD_WR_EN + + + ctrl_cmd_wr_en + + + + + CMD_WR_DATA + + + ctrl_cmd_wr_data + + + + + SDO_WR_EN + + + ctrl_sdo_wr_en + + + + + SDO_WR_DATA + + + ctrl_sdo_wr_data + + + + + ENABLE + + + ctrl_enable + + + + + ENABLED + + + ctrl_enabled + + + + + MEM_RESET + + + ctrl_mem_reset + + + + + SYNC_READY + + + status_sync_ready + + + + + SYNC_VALID + + + status_sync_valid + + + + + SYNC_DATA + + + status_sync_data + + + + + + offload_sdi + + + + + + + TVALID + + + offload_sdi_valid + + + + + TREADY + + + offload_sdi_ready + + + + + TDATA + + + offload_sdi_data + + + + + + spi_engine_ctrl_offload_sdi_signal_clock + spi_engine_ctrl_offload_sdi_signal_clock + + + + + + + CLK + + + spi_clk + + + + + + ASSOCIATED_BUSIF + spi_engine_ctrl:offload_sdi + + + ASSOCIATED_RESET + spi_resetn + + + + + spi_engine_ctrl_offload_sdi_signal_reset + spi_engine_ctrl_offload_sdi_signal_reset + + + + + + + RST + + + spi_resetn + + + + + + POLARITY + ACTIVE_LOW + + + + + spi_engine_offload_ctrl_signal_clock + spi_engine_offload_ctrl_signal_clock + + + + + + + CLK + + + ctrl_clk + + + + + + ASSOCIATED_BUSIF + spi_engine_offload_ctrl + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + spi_engine_offload + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 54da56d5 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + spi_engine_offload + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 54da56d5 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_xpgui_view_fileset + + + + viewChecksum + 9caa5391 + + + + + + + ctrl_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ctrl_cmd_wr_en + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + ctrl_cmd_wr_data + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + ctrl_sdo_wr_en + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + ctrl_sdo_wr_data + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + ctrl_enable + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ctrl_enabled + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ctrl_mem_reset + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + status_sync_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + status_sync_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + status_sync_data + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + spi_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + spi_resetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + trigger + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cmd_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cmd_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + cmd + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sdo_data_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sdo_data_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + sdo_data + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sdi_data_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + sdi_data_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sdi_data + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + sync_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sync_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sync_data + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + offload_sdi_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + offload_sdi_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + offload_sdi_data + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + ASYNC_SPI_CLK + Async Spi Clk + false + + + ASYNC_TRIG + Async Trig + false + + + CMD_MEM_ADDRESS_WIDTH + Cmd Mem Address Width + 4 + + + SDO_MEM_ADDRESS_WIDTH + Sdo Mem Address Width + 4 + + + DATA_WIDTH + Data Width + 8 + + + NUM_OF_SDI + Num Of Sdi + 1 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + spi_engine_offload_constr.ttcl + ttcl + + + spi_engine_offload.v + verilogSource + CHECKSUM_54da56d5 + + + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + spi_engine_offload.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/spi_engine_offload_v1_0.tcl + tclSource + CHECKSUM_1ce3c7e4 + XGUI_VERSION_2 + + + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + spi_engine_offload_v1_0 + + + ASYNC_SPI_CLK + Asynchronous core clock + false + + + ASYNC_TRIG + Asynchronous trigger + false + + + CMD_MEM_ADDRESS_WIDTH + Command FIFO address width + 4 + + + SDO_MEM_ADDRESS_WIDTH + MOSI FIFO address width + 4 + + + DATA_WIDTH + Shift register's data width + 8 + + + NUM_OF_SDI + Number of MISO lines + 1 + + + Component_Name + spi_engine_offload_v1_0 + + + + + + virtex7 + + + /Analog_Devices + + spi_engine_offload_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/peripherals/spi_engine/offload + 1 + 2024-01-14T03:53:04Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v b/adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v new file mode 100644 index 00000000..a15dfc18 --- /dev/null +++ b/adi_library/spi_engine/spi_engine_offload/spi_engine_offload.v @@ -0,0 +1,304 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module spi_engine_offload #( + + parameter ASYNC_SPI_CLK = 0, + parameter ASYNC_TRIG = 0, + parameter CMD_MEM_ADDRESS_WIDTH = 4, + parameter SDO_MEM_ADDRESS_WIDTH = 4, + parameter DATA_WIDTH = 8, // Valid data widths values are 8/16/24/32 + parameter NUM_OF_SDI = 1 +) ( + input ctrl_clk, + + input ctrl_cmd_wr_en, + input [15:0] ctrl_cmd_wr_data, + + input ctrl_sdo_wr_en, + input [(DATA_WIDTH-1):0] ctrl_sdo_wr_data, + + input ctrl_enable, + output ctrl_enabled, + input ctrl_mem_reset, + + output status_sync_valid, + input status_sync_ready, + output [7:0] status_sync_data, + + input spi_clk, + input spi_resetn, + + input trigger, + + output cmd_valid, + input cmd_ready, + output [15:0] cmd, + + output sdo_data_valid, + input sdo_data_ready, + output [(DATA_WIDTH-1):0] sdo_data, + + input sdi_data_valid, + output sdi_data_ready, + input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data, + + input sync_valid, + output sync_ready, + input [7:0] sync_data, + + output offload_sdi_valid, + input offload_sdi_ready, + output [(NUM_OF_SDI * DATA_WIDTH-1):0] offload_sdi_data +); + + reg spi_active = 1'b0; + + reg [CMD_MEM_ADDRESS_WIDTH-1:0] ctrl_cmd_wr_addr = 'h00; + reg [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr = 'h00; + reg [SDO_MEM_ADDRESS_WIDTH-1:0] ctrl_sdo_wr_addr = 'h00; + reg [SDO_MEM_ADDRESS_WIDTH-1:0] spi_sdo_rd_addr = 'h00; + + reg [15:0] cmd_mem[0:2**CMD_MEM_ADDRESS_WIDTH-1]; + reg [(DATA_WIDTH-1):0] sdo_mem[0:2**SDO_MEM_ADDRESS_WIDTH-1]; + + wire [15:0] cmd_int_s; + wire [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr_next; + wire spi_enable; + + assign cmd_valid = spi_active; + assign sdo_data_valid = spi_active; + + assign offload_sdi_valid = sdi_data_valid; + + // we don't want to block the SDI interface after disabling the module + // so just assert the SDI_READY if the sink module (DMA) is disabled + assign sdi_data_ready = (spi_enable) ? offload_sdi_ready : 1'b1; + + assign offload_sdi_data = sdi_data; + + assign cmd_int_s = cmd_mem[spi_cmd_rd_addr]; + assign sdo_data = sdo_mem[spi_sdo_rd_addr]; + + /* SYNC ID counter. The offload module increments the sync_id on each + * transaction. The initial value of the sync_id is the value of the last + * sync_id command loaded into the command buffer. + */ + + reg [ 7:0] ctrl_sync_id_init = 8'b0; + reg ctrl_sync_id_load = 1'b0; + reg [ 7:0] spi_sync_id_counter = 8'b0; + + wire [ 7:0] spi_sync_id_init_s; + + always @(posedge ctrl_clk) begin + if (ctrl_mem_reset == 1'b1) begin + ctrl_sync_id_init <= 8'b0; + ctrl_sync_id_load <= 1'b0; + end else begin + if (ctrl_cmd_wr_en && (ctrl_cmd_wr_data[15:8] == 8'h30)) begin + ctrl_sync_id_init <= ctrl_cmd_wr_data; + ctrl_sync_id_load <= 1'b1; + end else begin + ctrl_sync_id_load <= 1'b0; + end + end + end + + wire spi_sync_id_load_s; + + sync_event #( + .NUM_OF_EVENTS(1), + .ASYNC_CLK(1) + ) i_sync_sync_id_load ( + .in_clk (ctrl_clk), + .in_event(ctrl_sync_id_load), + .out_clk(spi_clk), + .out_event(spi_sync_id_load_s)); + + sync_bits #( + .NUM_OF_BITS(8), + .ASYNC_CLK(1) + ) i_sync_sync_id ( + .in_bits(ctrl_sync_id_init), + .out_clk(spi_clk), + .out_resetn(1'b1), + .out_bits(spi_sync_id_init_s)); + + always @(posedge spi_clk) begin + if (spi_resetn == 1'b0) begin + spi_sync_id_counter <= 8'b0; + end else begin + if (spi_sync_id_load_s) begin + spi_sync_id_counter <= spi_sync_id_init_s; + end else if(cmd_valid && cmd_ready && (cmd[15:8] == 8'h30)) begin + spi_sync_id_counter <= spi_sync_id_counter + 1'b1; + end + end + end + + assign cmd = (cmd_int_s[15:8] == 8'h30) ? {cmd_int_s[15:8], spi_sync_id_counter} : cmd_int_s; + + /* + * Forwarded SYNC interface, this can be used to monitor the state of the + * offload command sequence through SPI Engine regmap + */ + + assign status_sync_data = sync_data; + assign status_sync_valid = sync_valid; + assign sync_ready = status_sync_ready; + + generate if (ASYNC_SPI_CLK) begin + + /* + * The synchronization circuit takes care that there are no glitches on the + * ctrl_enabled signal. ctrl_do_enable is asserted whenever ctrl_enable is + * asserted, but only deasserted once the signal has been synchronized back from + * the SPI domain. This makes sure that we can't end up in a state where the + * enable signal in the SPI domain is asserted, but neither enable nor enabled + * is asserted in the control domain. + */ + + reg ctrl_do_enable = 1'b0; + wire ctrl_is_enabled; + reg spi_enabled = 1'b0; + + always @(posedge ctrl_clk) begin + if (ctrl_enable == 1'b1) begin + ctrl_do_enable <= 1'b1; + end else if (ctrl_is_enabled == 1'b1) begin + ctrl_do_enable <= 1'b0; + end + end + + assign ctrl_enabled = ctrl_is_enabled | ctrl_do_enable; + + always @(posedge spi_clk) begin + spi_enabled <= spi_enable | spi_active; + end + + sync_bits #( + .NUM_OF_BITS(1), + .ASYNC_CLK(1) + ) i_sync_enable ( + .in_bits(ctrl_do_enable), + .out_clk(spi_clk), + .out_resetn(1'b1), + .out_bits(spi_enable)); + + sync_bits #( + .NUM_OF_BITS(1), + .ASYNC_CLK(1) + ) i_sync_enabled ( + .in_bits(spi_enabled), + .out_clk(ctrl_clk), + .out_resetn(1'b1), + .out_bits(ctrl_is_enabled)); + + end else begin + assign spi_enable = ctrl_enable; + assign ctrl_enabled = spi_enable | spi_active; + end endgenerate + + assign spi_cmd_rd_addr_next = spi_cmd_rd_addr + 1; + + wire trigger_s; + sync_bits #( + .NUM_OF_BITS(1), + .ASYNC_CLK(ASYNC_TRIG) + ) i_sync_trigger ( + .in_bits(trigger), + .out_clk(spi_clk), + .out_resetn(1'b1), + .out_bits(trigger_s)); + + always @(posedge spi_clk) begin + if (spi_resetn == 1'b0) begin + spi_active <= 1'b0; + end else begin + if (spi_active == 1'b0) begin + // start offload when we have a valid trigger, offload is enabled and + // the DMA is enabled + if (trigger_s == 1'b1 && spi_enable == 1'b1 && offload_sdi_ready == 1'b1) + spi_active <= 1'b1; + end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin + spi_active <= 1'b0; + end + end + end + + always @(posedge spi_clk) begin + if (cmd_valid == 1'b0) begin + spi_cmd_rd_addr <= 'h00; + end else if (cmd_ready == 1'b1) begin + spi_cmd_rd_addr <= spi_cmd_rd_addr_next; + end + end + + always @(posedge spi_clk) begin + if (spi_active == 1'b0) begin + spi_sdo_rd_addr <= 'h00; + end else if (sdo_data_ready == 1'b1) begin + spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1; + end + end + + always @(posedge ctrl_clk) begin + if (ctrl_mem_reset == 1'b1) + ctrl_cmd_wr_addr <= 'h00; + else if (ctrl_cmd_wr_en == 1'b1) + ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1'b1; + end + + always @(posedge ctrl_clk) begin + if (ctrl_cmd_wr_en == 1'b1) + cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data; + end + + always @(posedge ctrl_clk) begin + if (ctrl_mem_reset == 1'b1) + ctrl_sdo_wr_addr <= 'h00; + else if (ctrl_sdo_wr_en == 1'b1) + ctrl_sdo_wr_addr <= ctrl_sdo_wr_addr + 1'b1; + end + + always @(posedge ctrl_clk) begin + if (ctrl_sdo_wr_en == 1'b1) + sdo_mem[ctrl_sdo_wr_addr] <= ctrl_sdo_wr_data; + end + +endmodule diff --git a/adi_library/spi_engine/spi_engine_offload/spi_engine_offload.xpr b/adi_library/spi_engine/spi_engine_offload/spi_engine_offload.xpr new file mode 100644 index 00000000..19013a72 --- /dev/null +++ b/adi_library/spi_engine/spi_engine_offload/spi_engine_offload.xpr @@ -0,0 +1,400 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/spi_engine/spi_engine_offload/spi_engine_offload_constr.ttcl b/adi_library/spi_engine/spi_engine_offload/spi_engine_offload_constr.ttcl new file mode 100644 index 00000000..60cc7859 --- /dev/null +++ b/adi_library/spi_engine/spi_engine_offload/spi_engine_offload_constr.ttcl @@ -0,0 +1,36 @@ +############################################################################### +## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName [ttcl_add $ComponentName "_constr"] :> +<: setFileExtension ".xdc" :> +<: setFileProcessingOrder late :> +<: set async_spi_clk [getBooleanValue "ASYNC_SPI_CLK"] :> + +<: if { $async_spi_clk } { :> + +set_property ASYNC_REG TRUE \ + [get_cells -quiet -hierarchical *cdc_sync_stage1_reg*] \ + [get_cells -quiet -hierarchical *cdc_sync_stage2_reg*] + +set_false_path -quiet \ + -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_sync_id_load/i_sync_out/cdc_sync_stage1_reg* && IS_SEQUENTIAL}] +set_false_path -quiet \ + -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_sync_id_load/i_sync_in/cdc_sync_stage1_reg* && IS_SEQUENTIAL}] + +set_false_path -quiet \ + -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_sync_id/cdc_sync_stage1_reg* && IS_SEQUENTIAL}] + +set_false_path -quiet \ + -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_enable/cdc_sync_stage1_reg* && IS_SEQUENTIAL}] + +set_false_path -quiet \ + -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_enabled/cdc_sync_stage1_reg* && IS_SEQUENTIAL}] + +set_false_path -quiet \ + -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_sync_trigger/cdc_sync_stage1_reg* && IS_SEQUENTIAL}] + +<: } :> diff --git a/adi_library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl b/adi_library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl new file mode 100644 index 00000000..77887f61 --- /dev/null +++ b/adi_library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl @@ -0,0 +1,117 @@ +############################################################################### +## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +source ../../../scripts/adi_env.tcl +source ../../scripts/adi_ip_intel.tcl + +ad_ip_create spi_engine_offload {SPI Engine Offload} p_elaboration +ad_ip_files spi_engine_offload [list\ + $ad_hdl_dir/library/util_cdc/sync_bits.v \ + spi_engine_offload.v] + +# parameters + +ad_ip_parameter ASYNC_SPI_CLK INTEGER 0 +ad_ip_parameter ASYNC_TRIG INTEGER 0 +ad_ip_parameter CMD_MEM_ADDRESS_WIDTH INTEGER 4 +ad_ip_parameter SDO_MEM_ADDRESS_WIDTH INTEGER 4 +ad_ip_parameter DATA_WIDTH INTEGER 8 +ad_ip_parameter NUM_OF_SDI INTEGER 1 + +proc p_elaboration {} { + + set data_width [get_parameter_value DATA_WIDTH] + set num_of_sdi [get_parameter_value NUM_OF_SDI] + + # control interface + + ad_interface clock ctrl_clk input 1 + ad_interface reset spi_resetn input 1 if_spi_clk + + add_interface ctrl_cmd_wr conduit end + add_interface_port ctrl_cmd_wr ctrl_cmd_wr_en wre input 1 + add_interface_port ctrl_cmd_wr ctrl_cmd_wr_data data input 16 + + set_interface_property ctrl_cmd_wr associatedClock if_ctrl_clk + set_interface_property ctrl_cmd_wr associatedReset none + + add_interface ctrl_sdo_wr conduit end + add_interface_port ctrl_sdo_wr ctrl_sdo_wr_en wre input 1 + add_interface_port ctrl_sdo_wr ctrl_sdo_wr_data data input $data_width + + set_interface_property ctrl_sdo_wr associatedClock if_ctrl_clk + set_interface_property ctrl_sdo_wr associatedReset none + + ad_interface signal ctrl_enable input 1 enable + ad_interface signal ctrl_enabled output 1 enabled + ad_interface signal ctrl_mem_reset input 1 reset + + add_interface status_sync axi4stream start + add_interface_port status_sync status_sync_valid tvalid output 1 + add_interface_port status_sync status_sync_ready tready input 1 + add_interface_port status_sync status_sync_data tdata output 8 + + set_interface_property status_sync associatedClock if_spi_clk + set_interface_property status_sync associatedReset if_spi_resetn + + # SPI Engine interfaces + + ad_interface clock spi_clk input 1 + ad_interface resetn spi_resetn input 1 if_spi_clk + + ad_interface signal trigger input 1 if_pwm + + ## command interface + + add_interface cmd axi4stream start + add_interface_port cmd cmd_valid tvalid output 1 + add_interface_port cmd cmd_ready tready input 1 + add_interface_port cmd cmd tdata output 16 + + set_interface_property cmd associatedClock if_spi_clk + set_interface_property cmd associatedReset if_spi_resetn + + ## SDO data interface + + add_interface sdo_data axi4stream start + add_interface_port sdo_data sdo_data_valid tvalid output 1 + add_interface_port sdo_data sdo_data_ready tready input 1 + add_interface_port sdo_data sdo_data tdata output $data_width + + set_interface_property sdo_data associatedClock if_spi_clk + set_interface_property sdo_data associatedReset if_spi_resetn + + ## SDI data interface + + add_interface sdi_data axi4stream end + add_interface_port sdi_data sdi_data_valid tvalid input 1 + add_interface_port sdi_data sdi_data_ready tready output 1 + add_interface_port sdi_data sdi_data tdata input [expr $num_of_sdi * $data_width] + + set_interface_property sdi_data associatedClock if_spi_clk + set_interface_property sdi_data associatedReset if_spi_resetn + + ## SYNC data interface + + add_interface sync axi4stream end + add_interface_port sync sync_valid tvalid input 1 + add_interface_port sync sync_ready tready output 1 + add_interface_port sync sync_data tdata input 8 + + set_interface_property sync associatedClock if_spi_clk + set_interface_property sync associatedReset if_spi_resetn + + ## Offload SDI data interface + + add_interface offload_sdi axi4stream start + add_interface_port offload_sdi offload_sdi_valid tvalid output 1 + add_interface_port offload_sdi offload_sdi_ready tready input 1 + add_interface_port offload_sdi offload_sdi_data tdata output [expr $num_of_sdi * $data_width] + + set_interface_property offload_sdi associatedClock if_spi_clk + set_interface_property offload_sdi associatedReset if_spi_resetn + +} diff --git a/adi_library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl b/adi_library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl new file mode 100644 index 00000000..4f230890 --- /dev/null +++ b/adi_library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl @@ -0,0 +1,193 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create spi_engine_offload +adi_ip_files spi_engine_offload [list \ + "spi_engine_offload_constr.ttcl" \ + "spi_engine_offload.v" \ +] + +adi_ip_properties_lite spi_engine_offload +adi_ip_ttcl axi_spi_engine "spi_engine_offload_constr.ttcl" + +set_property company_url {https://wiki.analog.com/resources/fpga/peripherals/spi_engine/offload} [ipx::current_core] + +# Remove all inferred interfaces +ipx::remove_all_bus_interface [ipx::current_core] + +adi_ip_add_core_dependencies [list \ + analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \ +] + +## Interface definitions + +adi_add_bus "spi_engine_ctrl" "master" \ + "analog.com:interface:spi_engine_ctrl_rtl:1.0" \ + "analog.com:interface:spi_engine_ctrl:1.0" \ + { + {"cmd_ready" "CMD_READY"} \ + {"cmd_valid" "CMD_VALID"} \ + {"cmd" "CMD_DATA"} \ + {"sdo_data_ready" "SDO_READY"} \ + {"sdo_data_valid" "SDO_VALID"} \ + {"sdo_data" "SDO_DATA"} \ + {"sdi_data_ready" "SDI_READY"} \ + {"sdi_data_valid" "SDI_VALID"} \ + {"sdi_data" "SDI_DATA"} \ + {"sync_ready" "SYNC_READY"} \ + {"sync_valid" "SYNC_VALID"} \ + {"sync_data" "SYNC_DATA"} \ + } + +adi_add_bus "spi_engine_offload_ctrl" "slave" \ + "analog.com:interface:spi_engine_offload_ctrl_rtl:1.0" \ + "analog.com:interface:spi_engine_offload_ctrl:1.0" \ + { \ + { "ctrl_cmd_wr_en" "CMD_WR_EN"} \ + { "ctrl_cmd_wr_data" "CMD_WR_DATA"} \ + { "ctrl_sdo_wr_en" "SDO_WR_EN"} \ + { "ctrl_sdo_wr_data" "SDO_WR_DATA"} \ + { "ctrl_enable" "ENABLE"} \ + { "ctrl_enabled" "ENABLED"} \ + { "ctrl_mem_reset" "MEM_RESET"} \ + { "status_sync_ready" "SYNC_READY"} \ + { "status_sync_valid" "SYNC_VALID"} \ + { "status_sync_data" "SYNC_DATA"} \ + } + +adi_add_bus "offload_sdi" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { \ + {"offload_sdi_valid" "TVALID"} \ + {"offload_sdi_ready" "TREADY"} \ + {"offload_sdi_data" "TDATA"} \ + } + +adi_add_bus_clock "spi_clk" "spi_engine_ctrl:offload_sdi" "spi_resetn" +adi_add_bus_clock "ctrl_clk" "spi_engine_offload_ctrl" + +## Parameter validations + +set cc [ipx::current_core] + +## ASYNC_SPI_CLK +set_property -dict [list \ + "value_format" "bool" \ + "value" "false" \ + ] \ + [ipx::get_user_parameters ASYNC_SPI_CLK -of_objects $cc] +set_property -dict [list \ + "value_format" "bool" \ + "value" "false" \ + ] \ + [ipx::get_hdl_parameters ASYNC_SPI_CLK -of_objects $cc] + +## ASYNC_TRIG +set_property -dict [list \ + "value_format" "bool" \ + "value" "false" \ + ] \ + [ipx::get_user_parameters ASYNC_TRIG -of_objects $cc] +set_property -dict [list \ + "value_format" "bool" \ + "value" "false" \ + ] \ + [ipx::get_hdl_parameters ASYNC_TRIG -of_objects $cc] + +## NUM_OF_SDI +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "1" \ + "value_validation_range_maximum" "8" \ + ] \ + [ipx::get_user_parameters NUM_OF_SDI -of_objects $cc] + +## DATA_WIDTH +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "8" \ + "value_validation_range_maximum" "256" \ + ] \ + [ipx::get_user_parameters DATA_WIDTH -of_objects $cc] + +## CMD_MEM_ADDRESS_WIDTH +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "1" \ + "value_validation_range_maximum" "16" \ + ] \ + [ipx::get_user_parameters CMD_MEM_ADDRESS_WIDTH -of_objects $cc] + +## SDO_MEM_ADDRESS_WIDTH +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "1" \ + "value_validation_range_maximum" "16" \ + ] \ + [ipx::get_user_parameters SDO_MEM_ADDRESS_WIDTH -of_objects $cc] + +## Customize IP Layout + +## Remove the automatically generated GUI page +ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] +ipx::save_core [ipx::current_core] + +## Create general configuration page +ipgui::add_page -name {SPI Engine RX offload} -component [ipx::current_core] -display_name {SPI Engine RX offload} +set page0 [ipgui::get_pagespec -name "SPI Engine RX offload" -component $cc] + +set general_group [ipgui::add_group -name "General Configuration" -component $cc \ + -parent $page0 -display_name "General Configuration" ] + +ipgui::add_param -name "DATA_WIDTH" -component $cc -parent $general_group +set_property -dict [list \ + "display_name" "Shift register's data width" \ + "tooltip" "\[DATA_WIDTH\] Define the data interface width" +] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component $cc] + +ipgui::add_param -name "NUM_OF_SDI" -component $cc -parent $general_group +set_property -dict [list \ + "display_name" "Number of MISO lines" \ + "tooltip" "\[NUM_OF_SDI\] Define the number of MISO lines" \ +] [ipgui::get_guiparamspec -name "NUM_OF_SDI" -component $cc] + +ipgui::add_param -name "ASYNC_SPI_CLK" -component $cc -parent $general_group +set_property -dict [list \ + "display_name" "Asynchronous core clock" \ + "tooltip" "\[ASYNC_SPI_CLK\] Define the relationship between the core clock and the memory mapped interface clock" \ +] [ipgui::get_guiparamspec -name "ASYNC_SPI_CLK" -component $cc] + +ipgui::add_param -name "ASYNC_TRIG" -component $cc -parent $general_group +set_property -dict [list \ + "display_name" "Asynchronous trigger" \ + "tooltip" "\[ASYNC_TRIG\] Set if the external trigger is asynchronous to the core clk" \ +] [ipgui::get_guiparamspec -name "ASYNC_TRIG" -component $cc] + +## Command stream FIFO depth configuration +set cmd_stream_fifo_group [ipgui::add_group -name "Command stream FIFO configuration" -component $cc \ + -parent $page0 -display_name "Command stream FIFO configuration" ] + +ipgui::add_param -name "CMD_MEM_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group +set_property -dict [list \ + "display_name" "Command FIFO address width" \ + "tooltip" "\[CMD_MEM_ADDRESS_WIDTH\] Define the depth of the FIFO" \ +] [ipgui::get_guiparamspec -name "CMD_MEM_ADDRESS_WIDTH" -component $cc] + +ipgui::add_param -name "SDO_MEM_ADDRESS_WIDTH" -component $cc -parent $cmd_stream_fifo_group +set_property -dict [list \ + "display_name" "MOSI FIFO address width" \ + "tooltip" "\[SDO_MEM_ADDRESS_WIDTH\] Define the depth of the FIFO" \ +] [ipgui::get_guiparamspec -name "SDO_MEM_ADDRESS_WIDTH" -component $cc] + +## Create and save the XGUI file +ipx::create_xgui_files $cc + +ipx::save_core [ipx::current_core] diff --git a/adi_library/spi_engine/spi_engine_offload/xgui/spi_engine_offload_v1_0.tcl b/adi_library/spi_engine/spi_engine_offload/xgui/spi_engine_offload_v1_0.tcl new file mode 100644 index 00000000..5a4c48bf --- /dev/null +++ b/adi_library/spi_engine/spi_engine_offload/xgui/spi_engine_offload_v1_0.tcl @@ -0,0 +1,112 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set SPI_Engine_RX_offload [ipgui::add_page $IPINST -name "SPI Engine RX offload"] + #Adding Group + set General_Configuration [ipgui::add_group $IPINST -name "General Configuration" -parent ${SPI_Engine_RX_offload}] + set DATA_WIDTH [ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${General_Configuration}] + set_property tooltip {[DATA_WIDTH] Define the data interface width} ${DATA_WIDTH} + set NUM_OF_SDI [ipgui::add_param $IPINST -name "NUM_OF_SDI" -parent ${General_Configuration}] + set_property tooltip {[NUM_OF_SDI] Define the number of MISO lines} ${NUM_OF_SDI} + set ASYNC_SPI_CLK [ipgui::add_param $IPINST -name "ASYNC_SPI_CLK" -parent ${General_Configuration}] + set_property tooltip {[ASYNC_SPI_CLK] Define the relationship between the core clock and the memory mapped interface clock} ${ASYNC_SPI_CLK} + set ASYNC_TRIG [ipgui::add_param $IPINST -name "ASYNC_TRIG" -parent ${General_Configuration}] + set_property tooltip {[ASYNC_TRIG] Set if the external trigger is asynchronous to the core clk} ${ASYNC_TRIG} + + #Adding Group + set Command_stream_FIFO_configuration [ipgui::add_group $IPINST -name "Command stream FIFO configuration" -parent ${SPI_Engine_RX_offload}] + set CMD_MEM_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "CMD_MEM_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}] + set_property tooltip {[CMD_MEM_ADDRESS_WIDTH] Define the depth of the FIFO} ${CMD_MEM_ADDRESS_WIDTH} + set SDO_MEM_ADDRESS_WIDTH [ipgui::add_param $IPINST -name "SDO_MEM_ADDRESS_WIDTH" -parent ${Command_stream_FIFO_configuration}] + set_property tooltip {[SDO_MEM_ADDRESS_WIDTH] Define the depth of the FIFO} ${SDO_MEM_ADDRESS_WIDTH} + + + +} + +proc update_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } { + # Procedure called to update ASYNC_SPI_CLK when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASYNC_SPI_CLK { PARAM_VALUE.ASYNC_SPI_CLK } { + # Procedure called to validate ASYNC_SPI_CLK + return true +} + +proc update_PARAM_VALUE.ASYNC_TRIG { PARAM_VALUE.ASYNC_TRIG } { + # Procedure called to update ASYNC_TRIG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASYNC_TRIG { PARAM_VALUE.ASYNC_TRIG } { + # Procedure called to validate ASYNC_TRIG + return true +} + +proc update_PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } { + # Procedure called to update CMD_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } { + # Procedure called to validate CMD_MEM_ADDRESS_WIDTH + return true +} + +proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to validate DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } { + # Procedure called to update NUM_OF_SDI when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_SDI { PARAM_VALUE.NUM_OF_SDI } { + # Procedure called to validate NUM_OF_SDI + return true +} + +proc update_PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } { + # Procedure called to update SDO_MEM_ADDRESS_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } { + # Procedure called to validate SDO_MEM_ADDRESS_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.ASYNC_SPI_CLK { MODELPARAM_VALUE.ASYNC_SPI_CLK PARAM_VALUE.ASYNC_SPI_CLK } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASYNC_SPI_CLK}] ${MODELPARAM_VALUE.ASYNC_SPI_CLK} +} + +proc update_MODELPARAM_VALUE.ASYNC_TRIG { MODELPARAM_VALUE.ASYNC_TRIG PARAM_VALUE.ASYNC_TRIG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASYNC_TRIG}] ${MODELPARAM_VALUE.ASYNC_TRIG} +} + +proc update_MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CMD_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.CMD_MEM_ADDRESS_WIDTH} +} + +proc update_MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH { MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SDO_MEM_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.SDO_MEM_ADDRESS_WIDTH} +} + +proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.NUM_OF_SDI { MODELPARAM_VALUE.NUM_OF_SDI PARAM_VALUE.NUM_OF_SDI } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_SDI}] ${MODELPARAM_VALUE.NUM_OF_SDI} +} + diff --git a/adi_library/sysid_rom/Makefile b/adi_library/sysid_rom/Makefile new file mode 100755 index 00000000..fc42c1d6 --- /dev/null +++ b/adi_library/sysid_rom/Makefile @@ -0,0 +1,15 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := sysid_rom + +GENERIC_DEPS += sysid_rom.v + +XILINX_DEPS += sysid_rom_ip.tcl + +INTEL_DEPS += sysid_rom_hw.tcl + +include ../scripts/library.mk diff --git a/adi_library/sysid_rom/component.xml b/adi_library/sysid_rom/component.xml new file mode 100644 index 00000000..85649ddf --- /dev/null +++ b/adi_library/sysid_rom/component.xml @@ -0,0 +1,237 @@ + + + analog.com + user + sysid_rom + 1.0 + + + clk + + + + + + + CLK + + + clk + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + sysid_rom + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + c025daf5 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + sysid_rom + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + c025daf5 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 8f178b19 + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rom_addr + + in + + 5 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rom_data + + out + + 31 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + ROM_WIDTH + Rom Width + 32 + + + ROM_ADDR_BITS + Rom Addr Bits + 6 + + + PATH_TO_FILE + Path To File + path_to_mem_init_file + + + + + + xilinx_anylanguagesynthesis_view_fileset + + sysid_rom.v + verilogSource + CHECKSUM_c025daf5 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + sysid_rom.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/sysid_rom_v1_0.tcl + tclSource + CHECKSUM_8f178b19 + XGUI_VERSION_2 + + + + sysid_rom_v1_0 + + + ROM_WIDTH + Rom Width + 32 + + + ROM_ADDR_BITS + Rom Addr Bits + 6 + + + PATH_TO_FILE + Path To File + path_to_mem_init_file + + + Component_Name + sysid_rom_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + sysid_rom_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:53:11Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/sysid_rom/sysid_rom.v b/adi_library/sysid_rom/sysid_rom.v new file mode 100755 index 00000000..fd15e993 --- /dev/null +++ b/adi_library/sysid_rom/sysid_rom.v @@ -0,0 +1,57 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** + +`timescale 1ns / 1ps + +module sysid_rom #( + parameter ROM_WIDTH = 32, + parameter ROM_ADDR_BITS = 6, + parameter PATH_TO_FILE = "path_to_mem_init_file" +) ( + input clk, + input [ROM_ADDR_BITS-1:0] rom_addr, + output reg [ROM_WIDTH-1:0] rom_data +); + + reg [ROM_WIDTH-1:0] lut_rom [(2**ROM_ADDR_BITS)-1:0]; + + initial begin + $readmemh(PATH_TO_FILE, lut_rom, 0, (2**ROM_ADDR_BITS)-1); + end + + always @(posedge clk) begin + rom_data = lut_rom[rom_addr]; + end + +endmodule diff --git a/adi_library/sysid_rom/sysid_rom.xpr b/adi_library/sysid_rom/sysid_rom.xpr new file mode 100644 index 00000000..6a9800f5 --- /dev/null +++ b/adi_library/sysid_rom/sysid_rom.xpr @@ -0,0 +1,399 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/sysid_rom/sysid_rom_hw.tcl b/adi_library/sysid_rom/sysid_rom_hw.tcl new file mode 100644 index 00000000..1562f077 --- /dev/null +++ b/adi_library/sysid_rom/sysid_rom_hw.tcl @@ -0,0 +1,42 @@ +############################################################################### +## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +source ../../scripts/adi_env.tcl +source ../scripts/adi_ip_intel.tcl + +set_module_property NAME sysid_rom +set_module_property DESCRIPTION "System ID ROM" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME sysid_rom + +# source files + +ad_ip_files sysid_rom [list \ + "sysid_rom.v"] + +# IP parameters + +add_parameter ROM_WIDTH INTEGER 32 +set_parameter_property ROM_WIDTH DEFAULT_VALUE 32 +set_parameter_property ROM_WIDTH DISPLAY_NAME "ROM width" +set_parameter_property ROM_WIDTH UNITS None +set_parameter_property ROM_WIDTH HDL_PARAMETER true + +add_parameter ROM_ADDR_BITS INTEGER 6 +set_parameter_property ROM_ADDR_BITS DEFAULT_VALUE 6 +set_parameter_property ROM_ADDR_BITS DISPLAY_NAME "ROM address bits" +set_parameter_property ROM_ADDR_BITS HDL_PARAMETER true + +add_parameter PATH_TO_FILE STRING "path_to_mem_init_file" +set_parameter_property PATH_TO_FILE DISPLAY_NAME "Path to file" +set_parameter_property PATH_TO_FILE HDL_PARAMETER true + +# external clock and control/status ports + +ad_interface clock clk input 1 +ad_interface signal rom_data output ROM_WIDTH rom_data +ad_interface signal rom_addr input ROM_ADDR_BITS diff --git a/adi_library/sysid_rom/sysid_rom_ip.tcl b/adi_library/sysid_rom/sysid_rom_ip.tcl new file mode 100755 index 00000000..19f59f8c --- /dev/null +++ b/adi_library/sysid_rom/sysid_rom_ip.tcl @@ -0,0 +1,19 @@ +############################################################################### +## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create sysid_rom +adi_ip_files sysid_rom [list \ + "sysid_rom.v"] + +adi_ip_properties_lite sysid_rom +set cc [ipx::current_core] + +ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + +ipx::save_core $cc diff --git a/adi_library/sysid_rom/xgui/sysid_rom_v1_0.tcl b/adi_library/sysid_rom/xgui/sysid_rom_v1_0.tcl new file mode 100644 index 00000000..aa08a4d3 --- /dev/null +++ b/adi_library/sysid_rom/xgui/sysid_rom_v1_0.tcl @@ -0,0 +1,55 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "PATH_TO_FILE" -parent ${Page_0} + ipgui::add_param $IPINST -name "ROM_ADDR_BITS" -parent ${Page_0} + ipgui::add_param $IPINST -name "ROM_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.PATH_TO_FILE { PARAM_VALUE.PATH_TO_FILE } { + # Procedure called to update PATH_TO_FILE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PATH_TO_FILE { PARAM_VALUE.PATH_TO_FILE } { + # Procedure called to validate PATH_TO_FILE + return true +} + +proc update_PARAM_VALUE.ROM_ADDR_BITS { PARAM_VALUE.ROM_ADDR_BITS } { + # Procedure called to update ROM_ADDR_BITS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ROM_ADDR_BITS { PARAM_VALUE.ROM_ADDR_BITS } { + # Procedure called to validate ROM_ADDR_BITS + return true +} + +proc update_PARAM_VALUE.ROM_WIDTH { PARAM_VALUE.ROM_WIDTH } { + # Procedure called to update ROM_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ROM_WIDTH { PARAM_VALUE.ROM_WIDTH } { + # Procedure called to validate ROM_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.ROM_WIDTH { MODELPARAM_VALUE.ROM_WIDTH PARAM_VALUE.ROM_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ROM_WIDTH}] ${MODELPARAM_VALUE.ROM_WIDTH} +} + +proc update_MODELPARAM_VALUE.ROM_ADDR_BITS { MODELPARAM_VALUE.ROM_ADDR_BITS PARAM_VALUE.ROM_ADDR_BITS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ROM_ADDR_BITS}] ${MODELPARAM_VALUE.ROM_ADDR_BITS} +} + +proc update_MODELPARAM_VALUE.PATH_TO_FILE { MODELPARAM_VALUE.PATH_TO_FILE PARAM_VALUE.PATH_TO_FILE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PATH_TO_FILE}] ${MODELPARAM_VALUE.PATH_TO_FILE} +} + diff --git a/adi_library/util_adcfifo/Makefile b/adi_library/util_adcfifo/Makefile new file mode 100644 index 00000000..50bc11a1 --- /dev/null +++ b/adi_library/util_adcfifo/Makefile @@ -0,0 +1,23 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_adcfifo + +GENERIC_DEPS += ../common/ad_axis_inf_rx.v +GENERIC_DEPS += ../common/ad_rst.v +GENERIC_DEPS += util_adcfifo.v + +XILINX_DEPS += ../common/ad_mem_asym.v +XILINX_DEPS += util_adcfifo_constr.xdc +XILINX_DEPS += util_adcfifo_ip.tcl + +XILINX_LIB_DEPS += util_cdc + +INTEL_DEPS += ../util_cdc/sync_gray.v +INTEL_DEPS += util_adcfifo_constr.sdc +INTEL_DEPS += util_adcfifo_hw.tcl + +include ../scripts/library.mk diff --git a/adi_library/util_adcfifo/component.xml b/adi_library/util_adcfifo/component.xml new file mode 100644 index 00000000..1ccd34a3 --- /dev/null +++ b/adi_library/util_adcfifo/component.xml @@ -0,0 +1,468 @@ + + + analog.com + user + util_adcfifo + 1.0 + + + adc_clk + + + + + + + CLK + + + adc_clk + + + + + + ASSOCIATED_RESET + adc_rst + + + + + adc_rst + + + + + + + RST + + + adc_rst + + + + + + dma_clk + + + + + + + CLK + + + dma_clk + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_adcfifo + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 2eb31c0a + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_adcfifo + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + f2ab08a6 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_xpgui_view_fileset + + + + viewChecksum + 26128cef + + + + + + + adc_rst + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_wr + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_wdata + + in + + 255 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_wovf + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_wr + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_wdata + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_wready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_xfer_req + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_xfer_status + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + ADC_DATA_WIDTH + Adc Data Width + 256 + + + DMA_DATA_WIDTH + Dma Data Width + 64 + + + DMA_READY_ENABLE + Dma Ready Enable + 1 + + + DMA_ADDRESS_WIDTH + Dma Address Width + 10 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + util_adcfifo_constr.xdc + xdc + + + ../common/ad_axis_inf_rx.v + verilogSource + + + ../common/ad_mem_asym.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + util_adcfifo.v + verilogSource + CHECKSUM_4808813e + + + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_axis_inf_rx.v + verilogSource + + + ../common/ad_mem_asym.v + verilogSource + + + ../common/ad_rst.v + verilogSource + + + util_adcfifo.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/util_adcfifo_v1_0.tcl + tclSource + CHECKSUM_26128cef + XGUI_VERSION_2 + + + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + util_adcfifo_v1_0 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + ADC_DATA_WIDTH + Adc Data Width + 256 + + + DMA_DATA_WIDTH + Dma Data Width + 64 + + + DMA_READY_ENABLE + Dma Ready Enable + 1 + + + DMA_ADDRESS_WIDTH + Dma Address Width + 10 + + + Component_Name + util_adcfifo_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + util_adcfifo_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:53:21Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_adcfifo/util_adcfifo.v b/adi_library/util_adcfifo/util_adcfifo.v new file mode 100644 index 00000000..f0396d4b --- /dev/null +++ b/adi_library/util_adcfifo/util_adcfifo.v @@ -0,0 +1,253 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_adcfifo #( + + parameter FPGA_TECHNOLOGY = 0, + parameter ADC_DATA_WIDTH = 256, + parameter DMA_DATA_WIDTH = 64, + parameter DMA_READY_ENABLE = 1, + parameter DMA_ADDRESS_WIDTH = 10 +) ( + + // fifo interface + + input adc_rst, + input adc_clk, + input adc_wr, + input [ADC_DATA_WIDTH-1:0] adc_wdata, + output adc_wovf, + + // dma interface + + input dma_clk, + output dma_wr, + output [DMA_DATA_WIDTH-1:0] dma_wdata, + input dma_wready, + input dma_xfer_req, + output [ 3:0] dma_xfer_status +); + + localparam DMA_MEM_RATIO = ADC_DATA_WIDTH/DMA_DATA_WIDTH; + localparam ADDRESS_PADDING_WIDTH = (DMA_MEM_RATIO == 1) ? 0 : + (DMA_MEM_RATIO == 2) ? 1 : + (DMA_MEM_RATIO == 4) ? 2 : 3; + localparam ADC_ADDRESS_WIDTH = DMA_ADDRESS_WIDTH - ADDRESS_PADDING_WIDTH; + localparam ADC_ADDR_LIMIT = (2**ADC_ADDRESS_WIDTH)-1; + localparam DMA_ADDR_LIMIT = (2**DMA_ADDRESS_WIDTH)-1; + + // internal registers + + reg [ 2:0] adc_xfer_req_m = 'd0; + reg adc_xfer_init = 'd0; + reg adc_xfer_enable = 'd0; + reg adc_wr_int = 'd0; + reg [ADC_DATA_WIDTH-1:0] adc_wdata_int = 'd0; + reg [ADC_ADDRESS_WIDTH-1:0] adc_waddr_int = 'd0; + reg adc_capture_arm = 1'b0; + reg dma_rd = 'd0; + reg dma_rd_d = 'd0; + reg [DMA_DATA_WIDTH-1:0] dma_rdata_d = 'd0; + reg [DMA_ADDRESS_WIDTH:0] dma_raddr = 'd0; + reg [DMA_ADDRESS_WIDTH-1:0] dma_waddr_int = 'd0; + reg dma_endof_read = 'd0; + + // internal signals + + wire adc_rst_s; + wire dma_wready_s; + wire [DMA_DATA_WIDTH-1:0] dma_rdata_s; + wire dma_read_rst_s; + wire dma_wr_int_s; + wire [ADC_ADDRESS_WIDTH-1:0] dma_waddr_int_s; + wire adc_end_of_capture_s; + wire [ADC_ADDRESS_WIDTH-1:0] adc_waddr_int_s; + + // write interface + + assign adc_wovf = 1'd0; + + // synchronize the adc_rst to the adc_clk clock domain + ad_rst i_adc_rst_sync ( + .rst_async (adc_rst), + .clk (adc_clk), + .rstn (), + .rst (adc_rst_s)); + + // optional capture synchronization + + always @(posedge adc_clk) begin + if (adc_rst_s == 1'b1) begin + adc_xfer_req_m <= 'd0; + end else begin + adc_xfer_req_m <= {adc_xfer_req_m[1:0], dma_xfer_req}; + end + end + + always @(posedge adc_clk) begin + if (adc_rst_s == 1'b1) begin + adc_xfer_init <= 'd0; + end else begin + adc_xfer_init <= adc_xfer_req_m[1] & ~adc_xfer_req_m[2]; + end + end + + // a de-asserted xfer_req will reset the FIFO + assign dma_wr = dma_wr_int_s & dma_xfer_req; + + assign adc_end_of_capture_s = ((adc_waddr_int_s == ADC_ADDR_LIMIT) || (adc_xfer_req_m[2] == 1'b0)) && + (adc_wr_int == 1'b1); + always @(posedge adc_clk) begin + if (adc_rst_s == 1'b1) begin + adc_xfer_enable <= 'd0; + end else begin + if (adc_xfer_init == 1'b1) begin + adc_xfer_enable <= 1'b1; + end else if (adc_end_of_capture_s == 1'b1) begin + adc_xfer_enable <= 1'b0; + end + end + end + + assign adc_waddr_int_s = (adc_waddr_int == ADC_ADDR_LIMIT) ? adc_waddr_int : adc_waddr_int + 1'b1; + always @(posedge adc_clk) begin + if (adc_xfer_req_m[2] == 1'b0) begin + adc_wr_int <= 'd0; + adc_wdata_int <= 'd0; + adc_waddr_int <= 'd0; + end else begin + adc_wr_int <= adc_wr & adc_xfer_enable; + adc_wdata_int <= adc_wdata; + if (adc_wr_int == 1'b1) begin + adc_waddr_int <= adc_waddr_int_s; + end + end + end + + // read interface + + assign dma_xfer_status = 4'd0; + + // write address synchronization + + sync_gray #( + .DATA_WIDTH (ADC_ADDRESS_WIDTH), + .ASYNC_CLK (1) + ) i_dma_waddr_sync ( + .in_clk (adc_clk), + .in_resetn (1'b1), + .in_count (adc_waddr_int), + .out_resetn (1'b1), + .out_clk (dma_clk), + .out_count (dma_waddr_int_s)); + + always @(posedge dma_clk) begin + if (dma_read_rst_s == 1'b1) begin + dma_waddr_int <= 'd0; + end else begin + dma_waddr_int <= {dma_waddr_int_s,{ADDRESS_PADDING_WIDTH{1'b0}}}; + end + end + + assign dma_read_rst_s = ~dma_xfer_req; + + assign dma_wready_s = (DMA_READY_ENABLE == 0) ? 1'b1 : dma_wready; + assign dma_rd_s = ((dma_raddr < {1'b0, dma_waddr_int}) || &dma_waddr_int) & dma_wready_s; + + always @(posedge dma_clk) begin + if (dma_read_rst_s == 1'b1) begin + dma_rd <= 'd0; + dma_rd_d <= 'd0; + dma_rdata_d <= 'd0; + dma_raddr <= 'd0; + dma_endof_read <= 'd0; + end else begin + if (dma_waddr_int != 'd0) begin + dma_rd <= dma_rd_s; + if (dma_rd_s == 1'b1) begin + dma_raddr <= dma_raddr + 1'b1; + end + end + dma_rd_d <= dma_rd; + dma_rdata_d <= dma_rdata_s; + end + end + + // instantiations + + generate + if (FPGA_TECHNOLOGY == 1) begin + mem_asym i_mem_asym ( + .mem_i_wrclock_clk (adc_clk), + .mem_i_wren_wren (adc_wr_int), + .mem_i_wraddress_wraddress (adc_waddr_int), + .mem_i_datain_datain (adc_wdata_int), + .mem_i_rdclock_clk (dma_clk), + .mem_i_rdaddress_rdaddress (dma_raddr[DMA_ADDRESS_WIDTH-1:0]), + .mem_o_dataout_dataout (dma_rdata_s)); + end else begin + ad_mem_asym #( + .A_ADDRESS_WIDTH (ADC_ADDRESS_WIDTH), + .A_DATA_WIDTH (ADC_DATA_WIDTH), + .B_ADDRESS_WIDTH (DMA_ADDRESS_WIDTH), + .B_DATA_WIDTH (DMA_DATA_WIDTH) + ) i_mem_asym ( + .clka (adc_clk), + .wea (adc_wr_int), + .addra (adc_waddr_int), + .dina (adc_wdata_int), + .clkb (dma_clk), + .reb (1'b1), + .addrb (dma_raddr[DMA_ADDRESS_WIDTH-1:0]), + .doutb (dma_rdata_s)); + end + endgenerate + + ad_axis_inf_rx #( + .DATA_WIDTH(DMA_DATA_WIDTH) + ) i_axis_inf ( + .clk (dma_clk), + .rst (dma_read_rst_s), + .valid (dma_rd_d), + .last (1'd0), + .data (dma_rdata_d), + .inf_valid (dma_wr_int_s), + .inf_last (), + .inf_data (dma_wdata), + .inf_ready (dma_wready)); + +endmodule diff --git a/adi_library/util_adcfifo/util_adcfifo.xpr b/adi_library/util_adcfifo/util_adcfifo.xpr new file mode 100644 index 00000000..1548eb2d --- /dev/null +++ b/adi_library/util_adcfifo/util_adcfifo.xpr @@ -0,0 +1,426 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_adcfifo/util_adcfifo_constr.sdc b/adi_library/util_adcfifo/util_adcfifo_constr.sdc new file mode 100644 index 00000000..ff222303 --- /dev/null +++ b/adi_library/util_adcfifo/util_adcfifo_constr.sdc @@ -0,0 +1,9 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_false_path -to [get_registers *adc_xfer_req_m_reg[0]*] +set_false_path -to [get_registers *adc_xfer_req_m[0]*] +set_false_path -to [get_registers *cdc_sync_stage1*] + diff --git a/adi_library/util_adcfifo/util_adcfifo_constr.xdc b/adi_library/util_adcfifo/util_adcfifo_constr.xdc new file mode 100644 index 00000000..c144dbd4 --- /dev/null +++ b/adi_library/util_adcfifo/util_adcfifo_constr.xdc @@ -0,0 +1,15 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property ASYNC_REG TRUE \ + [get_cells -hier -filter {name =~ *adc_xfer_req_m*}] \ + [get_cells -hier {*cdc_sync_stage1_reg*}] \ + [get_cells -hier {*cdc_sync_stage2_reg*}] + +set_false_path \ + -to [get_cells -hier -filter {name =~ *adc_xfer_req_m_reg[0]* && IS_SEQUENTIAL}] + +set_false_path \ + -to [get_pins -hierarchical * -filter {NAME=~*i_dma_waddr_sync/cdc_sync_stage1_reg[*]/D}] diff --git a/adi_library/util_adcfifo/util_adcfifo_hw.tcl b/adi_library/util_adcfifo/util_adcfifo_hw.tcl new file mode 100644 index 00000000..548438e5 --- /dev/null +++ b/adi_library/util_adcfifo/util_adcfifo_hw.tcl @@ -0,0 +1,71 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +source ../../scripts/adi_env.tcl +source ../scripts/adi_ip_intel.tcl + +ad_ip_create util_adcfifo {UTIL ADC FIFO IP core} +set_module_property ELABORATION_CALLBACK p_util_adcfifo + +# files + +ad_ip_files util_adcfifo [list\ + $ad_hdl_dir/library/common/ad_rst.v \ + $ad_hdl_dir/library/common/ad_axis_inf_rx.v \ + $ad_hdl_dir/library/util_cdc/sync_gray.v \ + util_adcfifo.v \ + util_adcfifo_constr.sdc] + +# parameters + +ad_ip_parameter DEVICE_FAMILY STRING {Arria 10} +ad_ip_parameter FPGA_TECHNOLOGY INTEGER 1 +ad_ip_parameter ADC_DATA_WIDTH INTEGER 256 +ad_ip_parameter DMA_DATA_WIDTH INTEGER 64 +ad_ip_parameter DMA_READY_ENABLE INTEGER 1 +ad_ip_parameter DMA_ADDRESS_WIDTH INTEGER 10 + +# elaborate + +proc p_util_adcfifo {} { + + # read parameters + + set m_device_family [get_parameter_value "DEVICE_FAMILY"] + set m_adc_data_width [get_parameter_value "ADC_DATA_WIDTH"] + set m_dma_addr_width [get_parameter_value "DMA_ADDRESS_WIDTH"] + set m_dma_data_width [get_parameter_value "DMA_DATA_WIDTH"] + + # intel memory + + add_hdl_instance mem_asym intel_mem_asym 1.0 + set_instance_parameter_value mem_asym DEVICE_FAMILY $m_device_family + set_instance_parameter_value mem_asym A_ADDRESS_WIDTH 0 + set_instance_parameter_value mem_asym A_DATA_WIDTH $m_adc_data_width + set_instance_parameter_value mem_asym B_ADDRESS_WIDTH $m_dma_addr_width + set_instance_parameter_value mem_asym B_DATA_WIDTH $m_dma_data_width + + # interfaces + + ad_interface clock adc_clk input 1 + ad_interface reset adc_rst input 1 if_adc_clk + ad_interface signal adc_wr input 1 valid + ad_interface signal adc_wdata input ADC_DATA_WIDTH data + ad_interface signal adc_wovf output 1 ovf + + ad_interface clock dma_clk input 1 clk + ad_interface signal dma_xfer_req input 1 xfer_req + ad_interface signal dma_xfer_status output 4 xfer_status + + add_interface m_axis axi4stream start + set_interface_property m_axis associatedClock if_dma_clk + set_interface_property m_axis associatedReset if_adc_rst + add_interface_port m_axis dma_wr tvalid Output 1 + add_interface_port m_axis dma_wready tready Input 1 + add_interface_port m_axis dma_wdata tdata Output DMA_DATA_WIDTH + +} + diff --git a/adi_library/util_adcfifo/util_adcfifo_ip.tcl b/adi_library/util_adcfifo/util_adcfifo_ip.tcl new file mode 100644 index 00000000..fa86232f --- /dev/null +++ b/adi_library/util_adcfifo/util_adcfifo_ip.tcl @@ -0,0 +1,31 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create util_adcfifo +adi_ip_files util_adcfifo [list \ + "$ad_hdl_dir/library/common/ad_rst.v" \ + "$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \ + "$ad_hdl_dir/library/common/ad_mem_asym.v" \ + "util_adcfifo.v" \ + "util_adcfifo_constr.xdc" ] + +adi_ip_properties_lite util_adcfifo + +adi_ip_add_core_dependencies [list \ + analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \ +] + +ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] diff --git a/adi_library/util_adcfifo/xgui/util_adcfifo_v1_0.tcl b/adi_library/util_adcfifo/xgui/util_adcfifo_v1_0.tcl new file mode 100644 index 00000000..1f5b1f66 --- /dev/null +++ b/adi_library/util_adcfifo/xgui/util_adcfifo_v1_0.tcl @@ -0,0 +1,85 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ADC_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "DMA_ADDRESS_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "DMA_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "DMA_READY_ENABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.ADC_DATA_WIDTH { PARAM_VALUE.ADC_DATA_WIDTH } { + # Procedure called to update ADC_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADC_DATA_WIDTH { PARAM_VALUE.ADC_DATA_WIDTH } { + # Procedure called to validate ADC_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.DMA_ADDRESS_WIDTH { PARAM_VALUE.DMA_ADDRESS_WIDTH } { + # Procedure called to update DMA_ADDRESS_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_ADDRESS_WIDTH { PARAM_VALUE.DMA_ADDRESS_WIDTH } { + # Procedure called to validate DMA_ADDRESS_WIDTH + return true +} + +proc update_PARAM_VALUE.DMA_DATA_WIDTH { PARAM_VALUE.DMA_DATA_WIDTH } { + # Procedure called to update DMA_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_DATA_WIDTH { PARAM_VALUE.DMA_DATA_WIDTH } { + # Procedure called to validate DMA_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.DMA_READY_ENABLE { PARAM_VALUE.DMA_READY_ENABLE } { + # Procedure called to update DMA_READY_ENABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_READY_ENABLE { PARAM_VALUE.DMA_READY_ENABLE } { + # Procedure called to validate DMA_READY_ENABLE + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.ADC_DATA_WIDTH { MODELPARAM_VALUE.ADC_DATA_WIDTH PARAM_VALUE.ADC_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADC_DATA_WIDTH}] ${MODELPARAM_VALUE.ADC_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.DMA_DATA_WIDTH { MODELPARAM_VALUE.DMA_DATA_WIDTH PARAM_VALUE.DMA_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_DATA_WIDTH}] ${MODELPARAM_VALUE.DMA_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.DMA_READY_ENABLE { MODELPARAM_VALUE.DMA_READY_ENABLE PARAM_VALUE.DMA_READY_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_READY_ENABLE}] ${MODELPARAM_VALUE.DMA_READY_ENABLE} +} + +proc update_MODELPARAM_VALUE.DMA_ADDRESS_WIDTH { MODELPARAM_VALUE.DMA_ADDRESS_WIDTH PARAM_VALUE.DMA_ADDRESS_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.DMA_ADDRESS_WIDTH} +} + diff --git a/adi_library/util_axis_fifo/.lock b/adi_library/util_axis_fifo/.lock new file mode 100644 index 00000000..e69de29b diff --git a/adi_library/util_axis_fifo/Makefile b/adi_library/util_axis_fifo/Makefile new file mode 100644 index 00000000..162718fb --- /dev/null +++ b/adi_library/util_axis_fifo/Makefile @@ -0,0 +1,18 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_axis_fifo + +GENERIC_DEPS += ../common/ad_mem.v +GENERIC_DEPS += ../common/ad_mem_asym.v +GENERIC_DEPS += util_axis_fifo.v +GENERIC_DEPS += util_axis_fifo_address_generator.v + +XILINX_DEPS += util_axis_fifo_ip.tcl + +XILINX_LIB_DEPS += util_cdc + +include ../scripts/library.mk diff --git a/adi_library/util_axis_fifo/component.xml b/adi_library/util_axis_fifo/component.xml new file mode 100644 index 00000000..1c56f68b --- /dev/null +++ b/adi_library/util_axis_fifo/component.xml @@ -0,0 +1,840 @@ + + + analog.com + user + util_axis_fifo + 1.0 + + + s_axis + + + + + + + TVALID + + + s_axis_valid + + + + + TREADY + + + s_axis_ready + + + + + TDATA + + + s_axis_data + + + + + TLAST + + + s_axis_tlast + + + + + TKEEP + + + s_axis_tkeep + + + + + + m_axis + + + + + + + TVALID + + + m_axis_valid + + + + + TREADY + + + m_axis_ready + + + + + TDATA + + + m_axis_data + + + + + TLAST + + + m_axis_tlast + + + + + TKEEP + + + m_axis_tkeep + + + + + + m_axis_signal_clock + m_axis_signal_clock + + + + + + + CLK + + + m_axis_aclk + + + + + + ASSOCIATED_BUSIF + m_axis + + + ASSOCIATED_RESET + m_axis_aresetn + + + + + m_axis_signal_reset + m_axis_signal_reset + + + + + + + RST + + + m_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s_axis_signal_clock + s_axis_signal_clock + + + + + + + CLK + + + s_axis_aclk + + + + + + ASSOCIATED_BUSIF + s_axis + + + ASSOCIATED_RESET + s_axis_aresetn + + + + + s_axis_signal_reset + s_axis_signal_reset + + + + + + + RST + + + s_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_axis_fifo + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 4837ce55 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_axis_fifo + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 4837ce55 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_xpgui_view_fileset + + + + viewChecksum + fa323617 + + + + + xilinx_utilityxitfiles + Utility XIT/TTCL + :vivado.xilinx.com:xit.util + + xilinx_utilityxitfiles_view_fileset + + + + + + m_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_data + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tkeep + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + m_axis_tlast + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + m_axis_level + + out + + 4 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_empty + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_almost_empty + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_data + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axis_tkeep + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + s_axis_tlast + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + s_axis_room + + out + + 4 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_full + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_almost_full + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + DATA_WIDTH + Data Width + 64 + + + ADDRESS_WIDTH + Address Width + 5 + + + ASYNC_CLK + Async Clk + 1 + + + M_AXIS_REGISTERED + M Axis Registered + true + + + ALMOST_EMPTY_THRESHOLD + Almost Empty Threshold + 16 + + + ALMOST_FULL_THRESHOLD + Almost Full Threshold + 16 + + + TLAST_EN + Tlast En + false + + + TKEEP_EN + Tkeep En + true + + + REMOVE_NULL_BEAT_EN + Remove Null Beat En + false + + + + + + choice_list_a900bd4b + 8 + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + + + choice_pairs_b09a2f00 + 0 + 1 + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../common/ad_mem.v + verilogSource + + + util_axis_fifo_address_generator.v + verilogSource + + + util_axis_fifo.v + verilogSource + CHECKSUM_56c88183 + + + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_mem.v + verilogSource + + + util_axis_fifo_address_generator.v + verilogSource + + + util_axis_fifo.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/util_axis_fifo_v1_0.tcl + tclSource + CHECKSUM_d562f032 + XGUI_VERSION_2 + + + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + xilinx_utilityxitfiles_view_fileset + + gui/util_axis_fifo_v1_0.gtcl + GTCL + + + + ADI AXI Stream FIFO + + + DATA_WIDTH + Data width + 64 + + + ADDRESS_WIDTH + Address width + 5 + + + ASYNC_CLK + Clocking mode + 1 + + + M_AXIS_REGISTERED + Master AXIS Registered output + true + + + ALMOST_EMPTY_THRESHOLD + Almost empty threshold + 16 + + + ALMOST_FULL_THRESHOLD + Almost full threshold + 16 + + + TLAST_EN + TLAST Enable + false + + + TKEEP_EN + TKEEP Enable + true + + + REMOVE_NULL_BEAT_EN + REMOVE_NULL_BEAT_EN Enable + false + + + + true + + + + + + Component_Name + util_axis_fifo_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + ADI AXI Stream FIFO + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/util_axis_fifo + 1 + 2024-01-14T03:45:42Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_axis_fifo/gui/util_axis_fifo_v1_0.gtcl b/adi_library/util_axis_fifo/gui/util_axis_fifo_v1_0.gtcl new file mode 100644 index 00000000..e5d57aca --- /dev/null +++ b/adi_library/util_axis_fifo/gui/util_axis_fifo_v1_0.gtcl @@ -0,0 +1,2 @@ +# This file is automatically written. Do not modify. +proc gen_USERPARAMETER_REMOVE_NULL_BEAT_EN_ENABLEMENT {TKEEP_EN } {expr $TKEEP_EN == "true"} diff --git a/adi_library/util_axis_fifo/util_axis_fifo.v b/adi_library/util_axis_fifo/util_axis_fifo.v new file mode 100644 index 00000000..20cccf99 --- /dev/null +++ b/adi_library/util_axis_fifo/util_axis_fifo.v @@ -0,0 +1,358 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +`timescale 1ns/1ps + +module util_axis_fifo #( + parameter DATA_WIDTH = 64, + parameter ADDRESS_WIDTH = 5, + parameter ASYNC_CLK = 1, + parameter M_AXIS_REGISTERED = 1, + parameter [ADDRESS_WIDTH-1:0] ALMOST_EMPTY_THRESHOLD = 16, + parameter [ADDRESS_WIDTH-1:0] ALMOST_FULL_THRESHOLD = 16, + parameter TLAST_EN = 0, + parameter TKEEP_EN = 0, + parameter REMOVE_NULL_BEAT_EN = 0 +) ( + input m_axis_aclk, + input m_axis_aresetn, + input m_axis_ready, + output m_axis_valid, + output [DATA_WIDTH-1:0] m_axis_data, + output [DATA_WIDTH/8-1:0] m_axis_tkeep, + output m_axis_tlast, + output [ADDRESS_WIDTH-1:0] m_axis_level, + output m_axis_empty, + output m_axis_almost_empty, + + input s_axis_aclk, + input s_axis_aresetn, + output s_axis_ready, + input s_axis_valid, + input [DATA_WIDTH-1:0] s_axis_data, + input [DATA_WIDTH/8-1:0] s_axis_tkeep, + input s_axis_tlast, + output [ADDRESS_WIDTH-1:0] s_axis_room, + output s_axis_full, + output s_axis_almost_full +); + + localparam MEM_WORD = (TKEEP_EN & TLAST_EN) ? (DATA_WIDTH+DATA_WIDTH/8+1) : + (TKEEP_EN) ? (DATA_WIDTH+DATA_WIDTH/8) : + (TLAST_EN) ? (DATA_WIDTH+1) : + (DATA_WIDTH); + + wire [MEM_WORD-1:0] s_axis_data_int_s; + wire [MEM_WORD-1:0] m_axis_data_int_s; + + generate if (ADDRESS_WIDTH == 0) begin : zerodeep /* it's not a real FIFO, just a 1 stage pipeline */ + + if (ASYNC_CLK) begin + + (* KEEP = "yes" *) reg [DATA_WIDTH-1:0] cdc_sync_fifo_ram; + reg s_axis_waddr = 1'b0; + reg m_axis_raddr = 1'b0; + + wire m_axis_waddr; + wire s_axis_raddr; + + sync_bits #( + .NUM_OF_BITS(1), + .ASYNC_CLK(ASYNC_CLK) + ) i_waddr_sync ( + .out_clk(m_axis_aclk), + .out_resetn(m_axis_aresetn), + .in_bits(s_axis_waddr), + .out_bits(m_axis_waddr)); + + sync_bits #( + .NUM_OF_BITS(1), + .ASYNC_CLK(ASYNC_CLK) + ) i_raddr_sync ( + .out_clk(s_axis_aclk), + .out_resetn(s_axis_aresetn), + .in_bits(m_axis_raddr), + .out_bits(s_axis_raddr)); + + assign m_axis_valid = m_axis_raddr != m_axis_waddr; + assign m_axis_level = ~m_axis_ready; + assign m_axis_empty = 0; + assign m_axis_almost_empty = 0; + assign s_axis_ready = s_axis_raddr == s_axis_waddr; + assign s_axis_full = 0; + assign s_axis_almost_full = 0; + assign s_axis_room = s_axis_ready; + + always @(posedge s_axis_aclk) begin + if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1) + cdc_sync_fifo_ram <= s_axis_data; + end + + always @(posedge s_axis_aclk) begin + if (s_axis_aresetn == 1'b0) begin + s_axis_waddr <= 1'b0; + end else if (s_axis_ready & s_axis_valid) begin + s_axis_waddr <= s_axis_waddr + 1'b1; + end + end + + always @(posedge m_axis_aclk) begin + if (m_axis_aresetn == 1'b0) begin + m_axis_raddr <= 1'b0; + end else begin + if (m_axis_valid & m_axis_ready) + m_axis_raddr <= m_axis_raddr + 1'b1; + end + end + + assign m_axis_data = cdc_sync_fifo_ram; + + // TLAST support + if (TLAST_EN) begin + + reg axis_tlast_d; + + always @(posedge s_axis_aclk) begin + if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1) + axis_tlast_d <= s_axis_tlast; + end + assign m_axis_tlast = axis_tlast_d; + + end + + // TKEEP support + if (TKEEP_EN) begin + + reg axis_tkeep_d; + + always @(posedge s_axis_aclk) begin + if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1) + axis_tkeep_d <= s_axis_tkeep; + end + assign m_axis_tkeep = axis_tkeep_d; + + end + + end /* zerodeep */ + else + begin /* !ASYNC_CLK */ + + // Note: In this mode, the write and read interface must have a symmetric + // aspect ratio + reg [DATA_WIDTH-1:0] axis_data_d; + reg axis_valid_d; + + always @(posedge s_axis_aclk) begin + if (!s_axis_aresetn) begin + axis_data_d <= {DATA_WIDTH{1'b0}}; + axis_valid_d <= 1'b0; + end else if (s_axis_ready) begin + axis_data_d <= s_axis_data; + axis_valid_d <= s_axis_valid; + end + end + + assign m_axis_data = axis_data_d; + assign m_axis_valid = axis_valid_d; + assign s_axis_ready = m_axis_ready | ~m_axis_valid; + assign m_axis_empty = 1'b0; + assign m_axis_almost_empty = 1'b0; + assign m_axis_level = 1'b0; + assign s_axis_full = 1'b0; + assign s_axis_almost_full = 1'b0; + assign s_axis_room = 1'b0; + + // TLAST support + if (TLAST_EN) begin + reg axis_tlast_d; + + always @(posedge s_axis_aclk) begin + if (!s_axis_aresetn) begin + axis_tlast_d <= 1'b0; + end else if (s_axis_ready) begin + axis_tlast_d <= s_axis_tlast; + end + end + assign m_axis_tlast = axis_tlast_d; + end + + // TKEEP support + if (TKEEP_EN) begin + reg axis_tkeep_d; + + always @(posedge s_axis_aclk) begin + if (!s_axis_aresetn) begin + axis_tkeep_d <= 1'b0; + end else if (s_axis_ready) begin + axis_tkeep_d <= s_axis_tkeep; + end + end + assign m_axis_tkeep = axis_tkeep_d; + + end + + end /* !ASYNC_CLK */ + + end else begin : fifo /* ADDRESS_WIDTH != 0 - this is a real FIFO implementation */ + + wire [ADDRESS_WIDTH-1:0] s_axis_waddr; + wire [ADDRESS_WIDTH-1:0] m_axis_raddr; + wire _m_axis_ready; + wire _m_axis_valid; + + wire s_mem_write; + wire m_mem_read; + + reg valid = 1'b0; + + /* Control for first falls through */ + always @(posedge m_axis_aclk) begin + if (m_axis_aresetn == 1'b0) begin + valid <= 1'b0; + end else begin + if (_m_axis_valid) + valid <= 1'b1; + else if (m_axis_ready) + valid <= 1'b0; + end + end + + if (REMOVE_NULL_BEAT_EN) begin + // remove NULL bytes from the stream - NOTE: TKEEP is all-LOW or all-HIGH + assign s_mem_write = s_axis_ready & s_axis_valid & (&s_axis_tkeep); + end else begin + assign s_mem_write = s_axis_ready & s_axis_valid; + end + assign m_mem_read = (~valid || m_axis_ready) && _m_axis_valid; + + util_axis_fifo_address_generator #( + .ASYNC_CLK(ASYNC_CLK), + .ADDRESS_WIDTH(ADDRESS_WIDTH), + .ALMOST_EMPTY_THRESHOLD (ALMOST_EMPTY_THRESHOLD), + .ALMOST_FULL_THRESHOLD (ALMOST_FULL_THRESHOLD) + ) i_address_gray ( + .m_axis_aclk(m_axis_aclk), + .m_axis_aresetn(m_axis_aresetn), + .m_axis_ready(_m_axis_ready), + .m_axis_valid(_m_axis_valid), + .m_axis_raddr(m_axis_raddr), + .m_axis_level(m_axis_level), + .m_axis_empty(m_axis_empty), + .m_axis_almost_empty(m_axis_almost_empty), + .s_axis_aclk(s_axis_aclk), + .s_axis_aresetn(s_axis_aresetn), + .s_axis_ready(s_axis_ready), + .s_axis_valid(s_axis_valid), + .s_axis_full(s_axis_full), + .s_axis_almost_full(s_axis_almost_full), + .s_axis_waddr(s_axis_waddr), + .s_axis_room(s_axis_room)); + + // TLAST and TKEEP support + if (TLAST_EN & TKEEP_EN) begin + assign s_axis_data_int_s = {s_axis_tkeep, s_axis_tlast, s_axis_data}; + assign m_axis_tkeep = m_axis_data_int_s[MEM_WORD-1-:DATA_WIDTH/8]; + assign m_axis_tlast = m_axis_data_int_s[DATA_WIDTH]; + assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0]; + end else if (TKEEP_EN) begin + assign s_axis_data_int_s = {s_axis_tkeep, s_axis_data}; + assign m_axis_tkeep = m_axis_data_int_s[MEM_WORD-1-:DATA_WIDTH/8]; + assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0]; + end else if (TLAST_EN) begin + assign s_axis_data_int_s = {s_axis_tlast, s_axis_data}; + assign m_axis_tlast = m_axis_data_int_s[DATA_WIDTH]; + assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0]; + end else begin + assign s_axis_data_int_s = {s_axis_data}; + assign m_axis_data = m_axis_data_int_s[DATA_WIDTH-1:0]; + end + + if (ASYNC_CLK == 1) begin : async_clocks /* Asynchronous WRITE/READ clocks */ + + // The assumption is that in this mode the M_AXIS_REGISTERED is 1 + // When the clocks are asynchronous instantiate a block RAM + // regardless of the requested size to make sure we threat the + // clock crossing correctly + ad_mem #( + .DATA_WIDTH (MEM_WORD), + .ADDRESS_WIDTH (ADDRESS_WIDTH) + ) i_mem ( + .clka(s_axis_aclk), + .wea(s_mem_write), + .addra(s_axis_waddr), + .dina(s_axis_data_int_s), + .clkb(m_axis_aclk), + .reb(m_mem_read), + .addrb(m_axis_raddr), + .doutb(m_axis_data_int_s)); + + assign _m_axis_ready = ~valid || m_axis_ready; + assign m_axis_valid = valid; + + end else begin : sync_clocks /* Synchronous WRITE/READ clocks */ + + reg [MEM_WORD-1:0] ram[0:2**ADDRESS_WIDTH-1]; + + // When the clocks are synchronous use behavioral modeling for the SDP RAM + // Let the synthesizer decide what to infer (distributed or block RAM) + always @(posedge s_axis_aclk) begin + if (s_mem_write) + ram[s_axis_waddr] <= s_axis_data_int_s; + end + + if (M_AXIS_REGISTERED == 1) begin + + reg [MEM_WORD-1:0] data; + + always @(posedge m_axis_aclk) begin + if (m_mem_read) + data <= ram[m_axis_raddr]; + end + + assign _m_axis_ready = ~valid || m_axis_ready; + assign m_axis_data_int_s = data; + assign m_axis_valid = valid; + + end else begin + + assign _m_axis_ready = m_axis_ready; + assign m_axis_valid = _m_axis_valid; + assign m_axis_data_int_s = ram[m_axis_raddr]; + + end + end + end /* fifo */ + endgenerate + +endmodule diff --git a/adi_library/util_axis_fifo/util_axis_fifo.xpr b/adi_library/util_axis_fifo/util_axis_fifo.xpr new file mode 100644 index 00000000..ce9c3591 --- /dev/null +++ b/adi_library/util_axis_fifo/util_axis_fifo.xpr @@ -0,0 +1,421 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_axis_fifo/util_axis_fifo_address_generator.v b/adi_library/util_axis_fifo/util_axis_fifo_address_generator.v new file mode 100644 index 00000000..4e354617 --- /dev/null +++ b/adi_library/util_axis_fifo/util_axis_fifo_address_generator.v @@ -0,0 +1,172 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module util_axis_fifo_address_generator #( + parameter ASYNC_CLK = 0, // single or double clocked FIFO + parameter ADDRESS_WIDTH = 4, // address width, effective FIFO depth + parameter [ADDRESS_WIDTH-1:0] ALMOST_EMPTY_THRESHOLD = 16, + parameter [ADDRESS_WIDTH-1:0] ALMOST_FULL_THRESHOLD = 16 +) ( + + // Read interface - Sink side + + input m_axis_aclk, + input m_axis_aresetn, + input m_axis_ready, + output m_axis_valid, + output m_axis_empty, + output m_axis_almost_empty, + output [ADDRESS_WIDTH-1:0] m_axis_raddr, + output [ADDRESS_WIDTH-1:0] m_axis_level, + + // Write interface - Source side + + input s_axis_aclk, + input s_axis_aresetn, + output s_axis_ready, + input s_axis_valid, + output s_axis_full, + output s_axis_almost_full, + output [ADDRESS_WIDTH-1:0] s_axis_waddr, + output [ADDRESS_WIDTH-1:0] s_axis_room +); + + localparam FIFO_DEPTH = {ADDRESS_WIDTH{1'b1}}; + + // Definition of address counters + // All the counters are wider with one bit to indicate wraparounds + reg [ADDRESS_WIDTH:0] s_axis_waddr_reg = 'h0; + reg [ADDRESS_WIDTH:0] m_axis_raddr_reg = 'h0; + + wire [ADDRESS_WIDTH:0] s_axis_raddr_reg; + wire [ADDRESS_WIDTH:0] m_axis_waddr_reg; + + wire s_axis_write_s; + wire s_axis_ready_s; + + wire m_axis_read_s; + wire m_axis_valid_s; + wire [ADDRESS_WIDTH-1:0] m_axis_level_s; + + // Write address counter + + assign s_axis_write_s = s_axis_ready && s_axis_valid && ~s_axis_full; + always @(posedge s_axis_aclk) + begin + if (!s_axis_aresetn) + s_axis_waddr_reg <= 'h0; + else + if (s_axis_write_s) + s_axis_waddr_reg <= s_axis_waddr_reg + 1'b1; + end + + // Read address counter + + assign m_axis_read_s = m_axis_ready && m_axis_valid && ~m_axis_empty; + always @(posedge m_axis_aclk) + begin + if (!m_axis_aresetn) + m_axis_raddr_reg <= 'h0; + else + if (m_axis_read_s) + m_axis_raddr_reg <= m_axis_raddr_reg + 1'b1; + end + + // Output assignments + + assign s_axis_waddr = s_axis_waddr_reg[ADDRESS_WIDTH-1:0]; + assign m_axis_raddr = m_axis_raddr_reg[ADDRESS_WIDTH-1:0]; + + // CDC circuits for double clock configuration + + generate if (ASYNC_CLK == 1) begin : g_async_clock + // CDC transfer of the write pointer to the read clock domain + sync_gray #( + .DATA_WIDTH(ADDRESS_WIDTH + 1) + ) i_waddr_sync_gray ( + .in_clk(s_axis_aclk), + .in_resetn(s_axis_aresetn), + .out_clk(m_axis_aclk), + .out_resetn(m_axis_aresetn), + .in_count(s_axis_waddr_reg), + .out_count(m_axis_waddr_reg)); + + // CDC transfer of the read pointer to the write clock domain + sync_gray #( + .DATA_WIDTH(ADDRESS_WIDTH + 1) + ) i_raddr_sync_gray ( + .in_clk(m_axis_aclk), + .in_resetn(m_axis_aresetn), + .out_clk(s_axis_aclk), + .out_resetn(s_axis_aresetn), + .in_count(m_axis_raddr_reg), + .out_count(s_axis_raddr_reg)); + end else begin + assign m_axis_waddr_reg = s_axis_waddr_reg; + assign s_axis_raddr_reg = m_axis_raddr_reg; + end + endgenerate + + //------------------------------------------------------------------------------ + // FIFO write logic - upstream + // + // s_axis_full - FIFO is full if next write pointer equal to read pointer + // s_axis_ready - FIFO is always ready, unless it's full + // + //------------------------------------------------------------------------------ + + wire [ADDRESS_WIDTH:0] s_axis_fifo_fill = s_axis_waddr_reg - s_axis_raddr_reg; + assign s_axis_full = (s_axis_fifo_fill == {ADDRESS_WIDTH{1'b1}}); + assign s_axis_almost_full = s_axis_fifo_fill > {1'b0, ~ALMOST_FULL_THRESHOLD}; + assign s_axis_ready = ~s_axis_full; + assign s_axis_room = ~s_axis_fifo_fill; + + //------------------------------------------------------------------------------ + // FIFO read logic - downstream + // + // m_axis_empty - FIFO is empty if read pointer equal to write pointer + // m_axis_valid - FIFO has a valid output data, if it's not empty + // + //------------------------------------------------------------------------------ + + wire [ADDRESS_WIDTH:0] m_axis_fifo_fill = m_axis_waddr_reg - m_axis_raddr_reg; + assign m_axis_empty = m_axis_fifo_fill == 0; + assign m_axis_almost_empty = (m_axis_fifo_fill < ALMOST_EMPTY_THRESHOLD); + assign m_axis_valid = ~m_axis_empty; + assign m_axis_level = m_axis_fifo_fill; + +endmodule diff --git a/adi_library/util_axis_fifo/util_axis_fifo_ip.tcl b/adi_library/util_axis_fifo/util_axis_fifo_ip.tcl new file mode 100644 index 00000000..561cef56 --- /dev/null +++ b/adi_library/util_axis_fifo/util_axis_fifo_ip.tcl @@ -0,0 +1,198 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create util_axis_fifo +adi_ip_files util_axis_fifo [list \ + "util_axis_fifo_address_generator.v" \ + "../common/ad_mem.v" \ + "../common/ad_mem_asym.v" \ + "util_axis_fifo.v" \ +] + +adi_ip_properties_lite util_axis_fifo + +adi_ip_add_core_dependencies [list \ + analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \ +] + +set_property display_name "ADI AXI Stream FIFO" [ipx::current_core] +set_property description "ADI AXI Stream FIFO" [ipx::current_core] +set_property company_url {https://wiki.analog.com/resources/fpga/docs/util_axis_fifo} [ipx::current_core] + +## Interface definitions + +adi_add_bus "s_axis" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"s_axis_valid" "TVALID"} \ + {"s_axis_ready" "TREADY"} \ + {"s_axis_data" "TDATA"} \ + {"s_axis_tlast" "TLAST"} \ + {"s_axis_tkeep" "TKEEP"} \ + } + +adi_set_ports_dependency "s_axis_tlast" \ + "(spirit:decode(id('MODELPARAM_VALUE.TLAST_EN')) = 1)" +adi_set_ports_dependency "s_axis_tkeep" \ + "(spirit:decode(id('MODELPARAM_VALUE.TKEEP_EN')) = 1)" + +adi_add_bus "m_axis" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"m_axis_valid" "TVALID"} \ + {"m_axis_ready" "TREADY"} \ + {"m_axis_data" "TDATA"} \ + {"m_axis_tlast" "TLAST"} \ + {"m_axis_tkeep" "TKEEP"} \ + } + +adi_set_ports_dependency "m_axis_tlast" \ + "(spirit:decode(id('MODELPARAM_VALUE.TLAST_EN')) = 1)" +adi_set_ports_dependency "m_axis_tkeep" \ + "(spirit:decode(id('MODELPARAM_VALUE.TKEEP_EN')) = 1)" + +adi_add_bus_clock "m_axis_aclk" "m_axis" "m_axis_aresetn" +adi_add_bus_clock "s_axis_aclk" "s_axis" "s_axis_aresetn" + +## Parameter validation + +set_property -dict [list \ + "value_validation_type" "list" \ + "value_validation_list" "8 16 32 64 128 256 512 1024 2048 4096" \ + ] \ +[ipx::get_user_parameters DATA_WIDTH -of_objects [ipx::current_core]] + +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "0" \ + "value_validation_range_maximum" "4096" \ + ] \ +[ipx::get_user_parameters ADDRESS_WIDTH -of_objects [ipx::current_core]] + +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "0" \ + ] \ +[ipx::get_user_parameters ALMOST_FULL_THRESHOLD -of_objects [ipx::current_core]] + +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "0" \ + ] \ +[ipx::get_user_parameters ALMOST_EMPTY_THRESHOLD -of_objects [ipx::current_core]] + +set_property -dict [list \ + "value_validation_type" "pairs" \ + "value_validation_pairs" { \ + "Synchronous" "0" \ + "Asynchronous" "1" \ + } \ +] \ +[ipx::get_user_parameters ASYNC_CLK -of_objects [ipx::current_core]] + +foreach {k v} { \ + "M_AXIS_REGISTERED" "true" \ + "TLAST_EN" "false" \ + "TKEEP_EN" "true" \ + "REMOVE_NULL_BEAT_EN" "false" \ +} { \ + set_property -dict [list \ + "value_format" "bool" \ + "value" $v \ + ] \ + [ipx::get_user_parameters $k -of_objects [ipx::current_core]] + set_property -dict [list \ + "value_format" "bool" \ + "value" $v \ + ] \ + [ipx::get_hdl_parameters $k -of_objects [ipx::current_core]] +} + +## Customize IP layout + +## Remove the automatically generated GUI page +ipgui::remove_page -component [ipx::current_core] [ipgui::get_pagespec -name "Page 0" -component [ipx::current_core]] +ipx::save_core [ipx::current_core] + +## Create a new GUI page +ipgui::add_page -name {AXI Stream FIFO} -component [ipx::current_core] -display_name {AXI Stream FIFO} +set page0 [ipgui::get_pagespec -name "AXI Stream FIFO" -component [ipx::current_core]] + +set clock_group [ipgui::add_group -name "Clock Configuration" -component [ipx::current_core] \ + -parent $page0 -display_name "Clock Configuration" ] + +ipgui::add_param -name "ASYNC_CLK" -component [ipx::current_core] -parent $clock_group +set_property -dict [list \ + "widget" "comboBox" \ + "display_name" "Clocking mode" \ + "tooltip" "\[ASYNC_CLK\] If enabled the readn and write interface of the FIFO is asynchronous (its clocks are from different clock domain)." + ] [ipgui::get_guiparamspec -name "ASYNC_CLK" -component [ipx::current_core]] + +set interface_group [ipgui::add_group -name "Interface Configuration" -component [ipx::current_core] \ + -parent $page0 -display_name "Interface Configuration" ] + +ipgui::add_param -name "DATA_WIDTH" -component [ipx::current_core] -parent $interface_group +set_property -dict [list \ + "display_name" "Data width" \ + "tooltip" "\[DATA_WIDTH\] Data width of the AXI stream interfaces." \ + ] [ipgui::get_guiparamspec -name "DATA_WIDTH" -component [ipx::current_core]] + +ipgui::add_param -name "ADDRESS_WIDTH" -component [ipx::current_core] -parent $interface_group +set_property -dict [list \ + "display_name" "Address width" \ + "tooltip" "\[ADDRESS_WIDTH\] Address width of the read and write address pointers. It defines the depth of the FIFO : DATA_WIDTH/8 * (2 ^ ADDRESS_WIDTH)" \ + ] [ipgui::get_guiparamspec -name "ADDRESS_WIDTH" -component [ipx::current_core]] + +ipgui::add_param -name "ALMOST_FULL_THRESHOLD" -component [ipx::current_core] -parent $interface_group +set_property -dict [list \ + "display_name" "Almost full threshold" \ + "tooltip" "\[ALMOST_FULL_THRESHOLD\] The offset between the almost full assertion and full assertion in number of FIFO words." \ + ] [ipgui::get_guiparamspec -name "ALMOST_FULL_THRESHOLD" -component [ipx::current_core]] + +ipgui::add_param -name "ALMOST_EMPTY_THRESHOLD" -component [ipx::current_core] -parent $interface_group +set_property -dict [list \ + "display_name" "Almost empty threshold" \ + "tooltip" "\[ALMOST_EMPTY_THRESHOLD\] The offset between the almost empty assertion and empty assertion in number of FIFO words." \ + ] [ipgui::get_guiparamspec -name "ALMOST_EMPTY_THRESHOLD" -component [ipx::current_core]] + +ipgui::add_param -name "TLAST_EN" -component [ipx::current_core] -parent $interface_group +set_property -dict [list \ + "display_name" "TLAST Enable" \ + "tooltip" "\[TLAST_EN\] Enable the TLAST for the AXI stream interface, signaling packet boundaries." \ + ] [ipgui::get_guiparamspec -name "TLAST_EN" -component [ipx::current_core]] + +ipgui::add_param -name "TKEEP_EN" -component [ipx::current_core] -parent $interface_group +set_property -dict [list \ + "display_name" "TKEEP Enable" \ + "tooltip" "\[TKEEP_EN\] Enable the TKEEP for the AXI stream interface, for data byte qualification for each AXIS beat." \ + ] [ipgui::get_guiparamspec -name "TKEEP_EN" -component [ipx::current_core]] + +set other_group [ipgui::add_group -name "Other Features" -component [ipx::current_core] \ + -parent $page0 -display_name "Other Features" ] + +ipgui::add_param -name "M_AXIS_REGISTERED" -component [ipx::current_core] -parent $other_group +set_property -dict [list \ + "display_name" "Master AXIS Registered output" \ + "tooltip" "\[M_AXIS_REGISTERED\] Add an additional register stage to the master AXI stream data output." \ + ] [ipgui::get_guiparamspec -name "M_AXIS_REGISTERED" -component [ipx::current_core]] + +ipgui::add_param -name "REMOVE_NULL_BEAT_EN" -component [ipx::current_core] -parent $other_group +set_property -dict [list \ + "display_name" "REMOVE_NULL_BEAT_EN Enable" \ + "tooltip" "\[REMOVE_NULL_BEAT_EN\] Filteres out all the beats with a null TKEEP qualifier." \ + ] [ipgui::get_guiparamspec -name "REMOVE_NULL_BEAT_EN" -component [ipx::current_core]] +set_property enablement_tcl_expr {$TKEEP_EN == "true"} [ipx::get_user_parameters REMOVE_NULL_BEAT_EN -of_objects [ipx::current_core]] + +## Create and save the XGUI file +ipx::create_xgui_files [ipx::current_core] + +ipx::save_core [ipx::current_core] diff --git a/adi_library/util_axis_fifo/xgui/util_axis_fifo_v1_0.tcl b/adi_library/util_axis_fifo/xgui/util_axis_fifo_v1_0.tcl new file mode 100644 index 00000000..918aaa33 --- /dev/null +++ b/adi_library/util_axis_fifo/xgui/util_axis_fifo_v1_0.tcl @@ -0,0 +1,176 @@ + +# Loading additional proc with user specified bodies to compute parameter values. +source [file join [file dirname [file dirname [info script]]] gui/util_axis_fifo_v1_0.gtcl] + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set AXI_Stream_FIFO [ipgui::add_page $IPINST -name "AXI Stream FIFO"] + #Adding Group + set Clock_Configuration [ipgui::add_group $IPINST -name "Clock Configuration" -parent ${AXI_Stream_FIFO}] + set ASYNC_CLK [ipgui::add_param $IPINST -name "ASYNC_CLK" -parent ${Clock_Configuration} -widget comboBox] + set_property tooltip {[ASYNC_CLK] If enabled the readn and write interface of the FIFO is asynchronous (its clocks are from different clock domain).} ${ASYNC_CLK} + + #Adding Group + set Interface_Configuration [ipgui::add_group $IPINST -name "Interface Configuration" -parent ${AXI_Stream_FIFO}] + set DATA_WIDTH [ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Interface_Configuration} -widget comboBox] + set_property tooltip {[DATA_WIDTH] Data width of the AXI stream interfaces.} ${DATA_WIDTH} + set ADDRESS_WIDTH [ipgui::add_param $IPINST -name "ADDRESS_WIDTH" -parent ${Interface_Configuration}] + set_property tooltip {[ADDRESS_WIDTH] Address width of the read and write address pointers. It defines the depth of the FIFO : DATA_WIDTH/8 * (2 ^ ADDRESS_WIDTH)} ${ADDRESS_WIDTH} + set ALMOST_FULL_THRESHOLD [ipgui::add_param $IPINST -name "ALMOST_FULL_THRESHOLD" -parent ${Interface_Configuration}] + set_property tooltip {[ALMOST_FULL_THRESHOLD] The offset between the almost full assertion and full assertion in number of FIFO words.} ${ALMOST_FULL_THRESHOLD} + set ALMOST_EMPTY_THRESHOLD [ipgui::add_param $IPINST -name "ALMOST_EMPTY_THRESHOLD" -parent ${Interface_Configuration}] + set_property tooltip {[ALMOST_EMPTY_THRESHOLD] The offset between the almost empty assertion and empty assertion in number of FIFO words.} ${ALMOST_EMPTY_THRESHOLD} + set TLAST_EN [ipgui::add_param $IPINST -name "TLAST_EN" -parent ${Interface_Configuration}] + set_property tooltip {[TLAST_EN] Enable the TLAST for the AXI stream interface, signaling packet boundaries.} ${TLAST_EN} + set TKEEP_EN [ipgui::add_param $IPINST -name "TKEEP_EN" -parent ${Interface_Configuration}] + set_property tooltip {[TKEEP_EN] Enable the TKEEP for the AXI stream interface, for data byte qualification for each AXIS beat.} ${TKEEP_EN} + + #Adding Group + set Other_Features [ipgui::add_group $IPINST -name "Other Features" -parent ${AXI_Stream_FIFO}] + set M_AXIS_REGISTERED [ipgui::add_param $IPINST -name "M_AXIS_REGISTERED" -parent ${Other_Features}] + set_property tooltip {[M_AXIS_REGISTERED] Add an additional register stage to the master AXI stream data output.} ${M_AXIS_REGISTERED} + set REMOVE_NULL_BEAT_EN [ipgui::add_param $IPINST -name "REMOVE_NULL_BEAT_EN" -parent ${Other_Features}] + set_property tooltip {[REMOVE_NULL_BEAT_EN] Filteres out all the beats with a null TKEEP qualifier.} ${REMOVE_NULL_BEAT_EN} + + + +} + +proc update_PARAM_VALUE.REMOVE_NULL_BEAT_EN { PARAM_VALUE.REMOVE_NULL_BEAT_EN PARAM_VALUE.TKEEP_EN } { + # Procedure called to update REMOVE_NULL_BEAT_EN when any of the dependent parameters in the arguments change + + set REMOVE_NULL_BEAT_EN ${PARAM_VALUE.REMOVE_NULL_BEAT_EN} + set TKEEP_EN ${PARAM_VALUE.TKEEP_EN} + set values(TKEEP_EN) [get_property value $TKEEP_EN] + if { [gen_USERPARAMETER_REMOVE_NULL_BEAT_EN_ENABLEMENT $values(TKEEP_EN)] } { + set_property enabled true $REMOVE_NULL_BEAT_EN + } else { + set_property enabled false $REMOVE_NULL_BEAT_EN + } +} + +proc validate_PARAM_VALUE.REMOVE_NULL_BEAT_EN { PARAM_VALUE.REMOVE_NULL_BEAT_EN } { + # Procedure called to validate REMOVE_NULL_BEAT_EN + return true +} + +proc update_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } { + # Procedure called to update ADDRESS_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } { + # Procedure called to validate ADDRESS_WIDTH + return true +} + +proc update_PARAM_VALUE.ALMOST_EMPTY_THRESHOLD { PARAM_VALUE.ALMOST_EMPTY_THRESHOLD } { + # Procedure called to update ALMOST_EMPTY_THRESHOLD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ALMOST_EMPTY_THRESHOLD { PARAM_VALUE.ALMOST_EMPTY_THRESHOLD } { + # Procedure called to validate ALMOST_EMPTY_THRESHOLD + return true +} + +proc update_PARAM_VALUE.ALMOST_FULL_THRESHOLD { PARAM_VALUE.ALMOST_FULL_THRESHOLD } { + # Procedure called to update ALMOST_FULL_THRESHOLD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ALMOST_FULL_THRESHOLD { PARAM_VALUE.ALMOST_FULL_THRESHOLD } { + # Procedure called to validate ALMOST_FULL_THRESHOLD + return true +} + +proc update_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } { + # Procedure called to update ASYNC_CLK when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } { + # Procedure called to validate ASYNC_CLK + return true +} + +proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to validate DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.M_AXIS_REGISTERED { PARAM_VALUE.M_AXIS_REGISTERED } { + # Procedure called to update M_AXIS_REGISTERED when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.M_AXIS_REGISTERED { PARAM_VALUE.M_AXIS_REGISTERED } { + # Procedure called to validate M_AXIS_REGISTERED + return true +} + +proc update_PARAM_VALUE.TKEEP_EN { PARAM_VALUE.TKEEP_EN } { + # Procedure called to update TKEEP_EN when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TKEEP_EN { PARAM_VALUE.TKEEP_EN } { + # Procedure called to validate TKEEP_EN + return true +} + +proc update_PARAM_VALUE.TLAST_EN { PARAM_VALUE.TLAST_EN } { + # Procedure called to update TLAST_EN when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TLAST_EN { PARAM_VALUE.TLAST_EN } { + # Procedure called to validate TLAST_EN + return true +} + + +proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.ADDRESS_WIDTH { MODELPARAM_VALUE.ADDRESS_WIDTH PARAM_VALUE.ADDRESS_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADDRESS_WIDTH}] ${MODELPARAM_VALUE.ADDRESS_WIDTH} +} + +proc update_MODELPARAM_VALUE.ASYNC_CLK { MODELPARAM_VALUE.ASYNC_CLK PARAM_VALUE.ASYNC_CLK } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK}] ${MODELPARAM_VALUE.ASYNC_CLK} +} + +proc update_MODELPARAM_VALUE.M_AXIS_REGISTERED { MODELPARAM_VALUE.M_AXIS_REGISTERED PARAM_VALUE.M_AXIS_REGISTERED } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.M_AXIS_REGISTERED}] ${MODELPARAM_VALUE.M_AXIS_REGISTERED} +} + +proc update_MODELPARAM_VALUE.ALMOST_EMPTY_THRESHOLD { MODELPARAM_VALUE.ALMOST_EMPTY_THRESHOLD PARAM_VALUE.ALMOST_EMPTY_THRESHOLD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ALMOST_EMPTY_THRESHOLD}] ${MODELPARAM_VALUE.ALMOST_EMPTY_THRESHOLD} +} + +proc update_MODELPARAM_VALUE.ALMOST_FULL_THRESHOLD { MODELPARAM_VALUE.ALMOST_FULL_THRESHOLD PARAM_VALUE.ALMOST_FULL_THRESHOLD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ALMOST_FULL_THRESHOLD}] ${MODELPARAM_VALUE.ALMOST_FULL_THRESHOLD} +} + +proc update_MODELPARAM_VALUE.TLAST_EN { MODELPARAM_VALUE.TLAST_EN PARAM_VALUE.TLAST_EN } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TLAST_EN}] ${MODELPARAM_VALUE.TLAST_EN} +} + +proc update_MODELPARAM_VALUE.TKEEP_EN { MODELPARAM_VALUE.TKEEP_EN PARAM_VALUE.TKEEP_EN } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TKEEP_EN}] ${MODELPARAM_VALUE.TKEEP_EN} +} + +proc update_MODELPARAM_VALUE.REMOVE_NULL_BEAT_EN { MODELPARAM_VALUE.REMOVE_NULL_BEAT_EN PARAM_VALUE.REMOVE_NULL_BEAT_EN } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.REMOVE_NULL_BEAT_EN}] ${MODELPARAM_VALUE.REMOVE_NULL_BEAT_EN} +} + diff --git a/adi_library/util_axis_fifo_asym/.lock b/adi_library/util_axis_fifo_asym/.lock new file mode 100644 index 00000000..e69de29b diff --git a/adi_library/util_axis_fifo_asym/Makefile b/adi_library/util_axis_fifo_asym/Makefile new file mode 100644 index 00000000..f16b73df --- /dev/null +++ b/adi_library/util_axis_fifo_asym/Makefile @@ -0,0 +1,16 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_axis_fifo_asym + +GENERIC_DEPS += util_axis_fifo_asym.v + +XILINX_DEPS += util_axis_fifo_asym_ip.tcl + +XILINX_LIB_DEPS += util_axis_fifo +XILINX_LIB_DEPS += util_cdc + +include ../scripts/library.mk diff --git a/adi_library/util_axis_fifo_asym/component.xml b/adi_library/util_axis_fifo_asym/component.xml new file mode 100644 index 00000000..5ba4b79b --- /dev/null +++ b/adi_library/util_axis_fifo_asym/component.xml @@ -0,0 +1,775 @@ + + + analog.com + user + util_axis_fifo_asym + 1.0 + + + s_axis + + + + + + + TVALID + + + s_axis_valid + + + + + TREADY + + + s_axis_ready + + + + + TDATA + + + s_axis_data + + + + + TLAST + + + s_axis_tlast + + + + + + m_axis + + + + + + + TVALID + + + m_axis_valid + + + + + TREADY + + + m_axis_ready + + + + + TDATA + + + m_axis_data + + + + + TLAST + + + m_axis_tlast + + + + + + m_axis_signal_clock + m_axis_signal_clock + + + + + + + CLK + + + m_axis_aclk + + + + + + ASSOCIATED_BUSIF + m_axis + + + ASSOCIATED_RESET + m_axis_aresetn + + + + + m_axis_signal_reset + m_axis_signal_reset + + + + + + + RST + + + m_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + s_axis_signal_clock + s_axis_signal_clock + + + + + + + CLK + + + s_axis_aclk + + + + + + ASSOCIATED_BUSIF + s_axis + + + ASSOCIATED_RESET + s_axis_aresetn + + + + + s_axis_signal_reset + s_axis_signal_reset + + + + + + + RST + + + s_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_axis_fifo_asym + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_analog_com_user_util_axis_fifo_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 94187aef + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_axis_fifo_asym + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_axis_fifo_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 94187aef + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_xpgui_analog_com_user_util_axis_fifo_1_0__ref_view_fileset + + + xilinx_xpgui_view_fileset + + + + viewChecksum + 02216b5c + + + + + + + m_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_data + + out + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tkeep + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_tlast + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_empty + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_almost_empty + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_level + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_data + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axis_tkeep + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_tlast + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_full + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_almost_full + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_room + + out + + 4 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + ASYNC_CLK + Async Clk + 1 + + + S_DATA_WIDTH + S Data Width + 64 + + + S_ADDRESS_WIDTH + S Address Width + 5 + + + M_DATA_WIDTH + M Data Width + 128 + + + M_AXIS_REGISTERED + M Axis Registered + 1 + + + ALMOST_EMPTY_THRESHOLD + Almost Empty Threshold + 4 + + + ALMOST_FULL_THRESHOLD + Almost Full Threshold + 4 + + + TLAST_EN + Tlast En + 0 + + + TKEEP_EN + Tkeep En + 0 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + util_axis_fifo_asym.v + verilogSource + CHECKSUM_94187aef + + + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_analog_com_user_util_axis_fifo_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + util_axis_fifo_asym.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_axis_fifo_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/util_axis_fifo_asym_v1_0.tcl + tclSource + CHECKSUM_02216b5c + XGUI_VERSION_2 + + + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + xilinx_xpgui_analog_com_user_util_axis_fifo_1_0__ref_view_fileset + + + + + + + + util_axis_fifo_asym_v1_0 + + + ASYNC_CLK + Async Clk + 1 + + + S_DATA_WIDTH + S Data Width + 64 + + + S_ADDRESS_WIDTH + S Address Width + 5 + + + M_DATA_WIDTH + M Data Width + 128 + + + M_AXIS_REGISTERED + M Axis Registered + 1 + + + ALMOST_EMPTY_THRESHOLD + Almost Empty Threshold + 4 + + + ALMOST_FULL_THRESHOLD + Almost Full Threshold + 4 + + + TLAST_EN + Tlast En + 0 + + + TKEEP_EN + Tkeep En + 0 + + + Component_Name + util_axis_fifo_asym_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + util_axis_fifo_asym_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/util_axis_fifo_asym + 1 + 2024-01-14T03:50:07Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_axis_fifo_asym/util_axis_fifo_asym.v b/adi_library/util_axis_fifo_asym/util_axis_fifo_asym.v new file mode 100644 index 00000000..888f87de --- /dev/null +++ b/adi_library/util_axis_fifo_asym/util_axis_fifo_asym.v @@ -0,0 +1,307 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +`timescale 1ns/1ps + +module util_axis_fifo_asym #( + parameter ASYNC_CLK = 1, + parameter S_DATA_WIDTH = 64, + parameter S_ADDRESS_WIDTH = 5, + parameter M_DATA_WIDTH = 128, + parameter M_AXIS_REGISTERED = 1, + parameter ALMOST_EMPTY_THRESHOLD = 4, + parameter ALMOST_FULL_THRESHOLD = 4, + parameter TLAST_EN = 0, + parameter TKEEP_EN = 0 +) ( + input m_axis_aclk, + input m_axis_aresetn, + input m_axis_ready, + output m_axis_valid, + output [M_DATA_WIDTH-1:0] m_axis_data, + output [M_DATA_WIDTH/8-1:0] m_axis_tkeep, + output m_axis_tlast, + output m_axis_empty, + output m_axis_almost_empty, + output [31:0] m_axis_level, + + input s_axis_aclk, + input s_axis_aresetn, + output s_axis_ready, + input s_axis_valid, + input [S_DATA_WIDTH-1:0] s_axis_data, + input [S_DATA_WIDTH/8-1:0] s_axis_tkeep, + input s_axis_tlast, + output s_axis_full, + output s_axis_almost_full, + output [S_ADDRESS_WIDTH-1:0] s_axis_room +); + + // define which interface has a wider bus + localparam RATIO_TYPE = (S_DATA_WIDTH >= M_DATA_WIDTH) ? 1 : 0; + + // bus width ratio + localparam RATIO = (RATIO_TYPE) ? S_DATA_WIDTH/M_DATA_WIDTH : M_DATA_WIDTH/S_DATA_WIDTH; + + // atomic parameters - NOTE: depth is always defined by the slave attributes + localparam A_WIDTH = (RATIO_TYPE) ? M_DATA_WIDTH : S_DATA_WIDTH; + localparam A_ADDRESS = (RATIO_TYPE) ? S_ADDRESS_WIDTH : (S_ADDRESS_WIDTH-$clog2(RATIO)); + localparam A_ALMOST_FULL_THRESHOLD = (RATIO_TYPE) ? ALMOST_FULL_THRESHOLD : (ALMOST_FULL_THRESHOLD/RATIO); + localparam A_ALMOST_EMPTY_THRESHOLD = (RATIO_TYPE) ? (ALMOST_EMPTY_THRESHOLD/RATIO) : ALMOST_EMPTY_THRESHOLD; + + // slave and master sequencers + reg [$clog2(RATIO)-1:0] s_axis_counter; + reg [$clog2(RATIO)-1:0] m_axis_counter; + + wire [RATIO-1:0] m_axis_ready_int_s; + wire [RATIO-1:0] m_axis_valid_int_s; + wire [RATIO*A_WIDTH-1:0] m_axis_data_int_s; + wire [RATIO*A_WIDTH/8-1:0] m_axis_tkeep_int_s; + wire [RATIO-1:0] m_axis_tlast_int_s; + wire [RATIO-1:0] m_axis_empty_int_s; + wire [RATIO-1:0] m_axis_almost_empty_int_s; + wire [RATIO*A_ADDRESS-1:0] m_axis_level_int_s; + + wire [RATIO-1:0] s_axis_ready_int_s; + wire [RATIO-1:0] s_axis_valid_int_s; + wire [RATIO*A_WIDTH-1:0] s_axis_data_int_s; + wire [RATIO*A_WIDTH/8-1:0] s_axis_tkeep_int_s; + wire [RATIO-1:0] s_axis_tlast_int_s; + wire [RATIO-1:0] s_axis_full_int_s; + wire [RATIO-1:0] s_axis_almost_full_int_s; + wire [RATIO*A_ADDRESS-1:0] s_axis_room_int_s; + + // instantiate the FIFOs + genvar i; + generate + for (i=0; i> s_axis_counter; + assign s_axis_almost_full = s_axis_almost_full_int_s >> s_axis_counter; + + // the FIFO has the same room as the last atomic instance + // (NOTE: this is not the real room value, rather the value will be updated + // after every RATIO number of writes) + assign s_axis_full = s_axis_full_int_s[RATIO-1]; + assign s_axis_room = {s_axis_room_int_s[A_ADDRESS*(RATIO-1)+:A_ADDRESS], {$clog2(RATIO){1'b1}}}; + + end + + endgenerate + + // read or slave logic + generate + if (RATIO_TYPE) begin : small_master + + for (i=0; i> (m_axis_counter*A_WIDTH) ; + assign m_axis_tkeep = m_axis_tkeep_int_s >> (m_axis_counter*A_WIDTH/8) ; + + // VALID/EMPTY/ALMOST_EMPTY is driven by the current atomic instance + assign m_axis_valid = m_axis_valid_int_s >> m_axis_counter; + + // the FIFO has the same level as the last atomic instance + // (NOTE: this is not the real level value, rather the value will be updated + // after every RATIO number of reads) + assign m_axis_level = {m_axis_level_int_s[A_ADDRESS-1:0], {$clog2(RATIO){1'b0}}}; + assign m_axis_almost_empty = m_axis_almost_empty_int_s[RATIO-1]; + assign m_axis_empty = m_axis_empty_int_s[RATIO-1]; + + end else begin : big_master + + for (i=0; i 1) begin + if (RATIO_TYPE) begin + always @(posedge s_axis_aclk) begin + if (!s_axis_aresetn) begin + s_axis_counter <= 0; + end else begin + if (s_axis_ready && s_axis_valid) begin + s_axis_counter <= s_axis_counter + 1'b1; + end + end + end + end else begin + // in case of a small slave, after an active TLAST reset the counter + always @(posedge s_axis_aclk) begin + if (!s_axis_aresetn || s_axis_tlast_d) begin + s_axis_counter <= 0; + end else begin + if (s_axis_ready && s_axis_valid) begin + s_axis_counter <= s_axis_counter + 1'b1; + end + end + end + end + end + endgenerate + + // master handshake sequencer + + generate + if (RATIO == 1) begin + initial begin + m_axis_counter = 1'b0; + end + end else if (RATIO > 1) begin + always @(posedge m_axis_aclk) begin + if (!m_axis_aresetn) begin + m_axis_counter <= 0; + end else begin + if (m_axis_ready && m_axis_valid) begin + m_axis_counter <= m_axis_counter + 1'b1; + end + end + end + end + endgenerate + +endmodule diff --git a/adi_library/util_axis_fifo_asym/util_axis_fifo_asym.xpr b/adi_library/util_axis_fifo_asym/util_axis_fifo_asym.xpr new file mode 100644 index 00000000..f3bd772c --- /dev/null +++ b/adi_library/util_axis_fifo_asym/util_axis_fifo_asym.xpr @@ -0,0 +1,399 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_axis_fifo_asym/util_axis_fifo_asym_ip.tcl b/adi_library/util_axis_fifo_asym/util_axis_fifo_asym_ip.tcl new file mode 100644 index 00000000..5fe4ad90 --- /dev/null +++ b/adi_library/util_axis_fifo_asym/util_axis_fifo_asym_ip.tcl @@ -0,0 +1,50 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create util_axis_fifo_asym +adi_ip_files util_axis_fifo_asym [list \ + "util_axis_fifo_asym.v" \ +] + +adi_ip_properties_lite util_axis_fifo_asym + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/util_axis_fifo_asym} [ipx::current_core] + +adi_ip_add_core_dependencies [list \ + analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \ + analog.com:$VIVADO_IP_LIBRARY:util_axis_fifo:1.0 \ +] + +adi_add_bus "s_axis" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"s_axis_valid" "TVALID"} \ + {"s_axis_ready" "TREADY"} \ + {"s_axis_data" "TDATA"} \ + {"s_axis_tlast" "TLAST"} \ + } + +adi_add_bus "m_axis" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"m_axis_valid" "TVALID"} \ + {"m_axis_ready" "TREADY"} \ + {"m_axis_data" "TDATA"} \ + {"m_axis_tlast" "TLAST"} \ + } + +adi_add_bus_clock "m_axis_aclk" "m_axis" "m_axis_aresetn" +adi_add_bus_clock "s_axis_aclk" "s_axis" "s_axis_aresetn" + +## TODO: Validate RD_ADDRESS_WIDTH + +ipx::save_core [ipx::current_core] diff --git a/adi_library/util_axis_fifo_asym/xgui/util_axis_fifo_asym_v1_0.tcl b/adi_library/util_axis_fifo_asym/xgui/util_axis_fifo_asym_v1_0.tcl new file mode 100644 index 00000000..d6d29caa --- /dev/null +++ b/adi_library/util_axis_fifo_asym/xgui/util_axis_fifo_asym_v1_0.tcl @@ -0,0 +1,145 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ALMOST_EMPTY_THRESHOLD" -parent ${Page_0} + ipgui::add_param $IPINST -name "ALMOST_FULL_THRESHOLD" -parent ${Page_0} + ipgui::add_param $IPINST -name "ASYNC_CLK" -parent ${Page_0} + ipgui::add_param $IPINST -name "M_AXIS_REGISTERED" -parent ${Page_0} + ipgui::add_param $IPINST -name "M_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "S_ADDRESS_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "S_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "TKEEP_EN" -parent ${Page_0} + ipgui::add_param $IPINST -name "TLAST_EN" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.ALMOST_EMPTY_THRESHOLD { PARAM_VALUE.ALMOST_EMPTY_THRESHOLD } { + # Procedure called to update ALMOST_EMPTY_THRESHOLD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ALMOST_EMPTY_THRESHOLD { PARAM_VALUE.ALMOST_EMPTY_THRESHOLD } { + # Procedure called to validate ALMOST_EMPTY_THRESHOLD + return true +} + +proc update_PARAM_VALUE.ALMOST_FULL_THRESHOLD { PARAM_VALUE.ALMOST_FULL_THRESHOLD } { + # Procedure called to update ALMOST_FULL_THRESHOLD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ALMOST_FULL_THRESHOLD { PARAM_VALUE.ALMOST_FULL_THRESHOLD } { + # Procedure called to validate ALMOST_FULL_THRESHOLD + return true +} + +proc update_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } { + # Procedure called to update ASYNC_CLK when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } { + # Procedure called to validate ASYNC_CLK + return true +} + +proc update_PARAM_VALUE.M_AXIS_REGISTERED { PARAM_VALUE.M_AXIS_REGISTERED } { + # Procedure called to update M_AXIS_REGISTERED when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.M_AXIS_REGISTERED { PARAM_VALUE.M_AXIS_REGISTERED } { + # Procedure called to validate M_AXIS_REGISTERED + return true +} + +proc update_PARAM_VALUE.M_DATA_WIDTH { PARAM_VALUE.M_DATA_WIDTH } { + # Procedure called to update M_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.M_DATA_WIDTH { PARAM_VALUE.M_DATA_WIDTH } { + # Procedure called to validate M_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.S_ADDRESS_WIDTH { PARAM_VALUE.S_ADDRESS_WIDTH } { + # Procedure called to update S_ADDRESS_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.S_ADDRESS_WIDTH { PARAM_VALUE.S_ADDRESS_WIDTH } { + # Procedure called to validate S_ADDRESS_WIDTH + return true +} + +proc update_PARAM_VALUE.S_DATA_WIDTH { PARAM_VALUE.S_DATA_WIDTH } { + # Procedure called to update S_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.S_DATA_WIDTH { PARAM_VALUE.S_DATA_WIDTH } { + # Procedure called to validate S_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.TKEEP_EN { PARAM_VALUE.TKEEP_EN } { + # Procedure called to update TKEEP_EN when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TKEEP_EN { PARAM_VALUE.TKEEP_EN } { + # Procedure called to validate TKEEP_EN + return true +} + +proc update_PARAM_VALUE.TLAST_EN { PARAM_VALUE.TLAST_EN } { + # Procedure called to update TLAST_EN when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TLAST_EN { PARAM_VALUE.TLAST_EN } { + # Procedure called to validate TLAST_EN + return true +} + + +proc update_MODELPARAM_VALUE.ASYNC_CLK { MODELPARAM_VALUE.ASYNC_CLK PARAM_VALUE.ASYNC_CLK } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK}] ${MODELPARAM_VALUE.ASYNC_CLK} +} + +proc update_MODELPARAM_VALUE.S_DATA_WIDTH { MODELPARAM_VALUE.S_DATA_WIDTH PARAM_VALUE.S_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.S_DATA_WIDTH}] ${MODELPARAM_VALUE.S_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.S_ADDRESS_WIDTH { MODELPARAM_VALUE.S_ADDRESS_WIDTH PARAM_VALUE.S_ADDRESS_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.S_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.S_ADDRESS_WIDTH} +} + +proc update_MODELPARAM_VALUE.M_DATA_WIDTH { MODELPARAM_VALUE.M_DATA_WIDTH PARAM_VALUE.M_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.M_DATA_WIDTH}] ${MODELPARAM_VALUE.M_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.M_AXIS_REGISTERED { MODELPARAM_VALUE.M_AXIS_REGISTERED PARAM_VALUE.M_AXIS_REGISTERED } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.M_AXIS_REGISTERED}] ${MODELPARAM_VALUE.M_AXIS_REGISTERED} +} + +proc update_MODELPARAM_VALUE.ALMOST_EMPTY_THRESHOLD { MODELPARAM_VALUE.ALMOST_EMPTY_THRESHOLD PARAM_VALUE.ALMOST_EMPTY_THRESHOLD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ALMOST_EMPTY_THRESHOLD}] ${MODELPARAM_VALUE.ALMOST_EMPTY_THRESHOLD} +} + +proc update_MODELPARAM_VALUE.ALMOST_FULL_THRESHOLD { MODELPARAM_VALUE.ALMOST_FULL_THRESHOLD PARAM_VALUE.ALMOST_FULL_THRESHOLD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ALMOST_FULL_THRESHOLD}] ${MODELPARAM_VALUE.ALMOST_FULL_THRESHOLD} +} + +proc update_MODELPARAM_VALUE.TLAST_EN { MODELPARAM_VALUE.TLAST_EN PARAM_VALUE.TLAST_EN } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TLAST_EN}] ${MODELPARAM_VALUE.TLAST_EN} +} + +proc update_MODELPARAM_VALUE.TKEEP_EN { MODELPARAM_VALUE.TKEEP_EN PARAM_VALUE.TKEEP_EN } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TKEEP_EN}] ${MODELPARAM_VALUE.TKEEP_EN} +} + diff --git a/adi_library/util_axis_resize/Makefile b/adi_library/util_axis_resize/Makefile new file mode 100644 index 00000000..b9acd41c --- /dev/null +++ b/adi_library/util_axis_resize/Makefile @@ -0,0 +1,13 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_axis_resize + +GENERIC_DEPS += util_axis_resize.v + +XILINX_DEPS += util_axis_resize_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/util_axis_resize/component.xml b/adi_library/util_axis_resize/component.xml new file mode 100644 index 00000000..41b2d0f6 --- /dev/null +++ b/adi_library/util_axis_resize/component.xml @@ -0,0 +1,403 @@ + + + analog.com + user + util_axis_resize + 1.0 + + + s_axis + + + + + + + TVALID + + + s_valid + + + + + TREADY + + + s_ready + + + + + TDATA + + + s_data + + + + + + m_axis + + + + + + + TVALID + + + m_valid + + + + + TREADY + + + m_ready + + + + + TDATA + + + m_data + + + + + + s_axis_m_axis_signal_clock + s_axis_m_axis_signal_clock + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_BUSIF + s_axis:m_axis + + + ASSOCIATED_RESET + resetn + + + + + s_axis_m_axis_signal_reset + s_axis_m_axis_signal_reset + + + + + + + RST + + + resetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_axis_resize + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + a67c1595 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_axis_resize + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + a67c1595 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 9664bffc + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + resetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_data + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_data + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + MASTER_DATA_WIDTH + Master Data Width + 64 + + + SLAVE_DATA_WIDTH + Slave Data Width + 64 + + + BIG_ENDIAN + Big Endian + 0 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + util_axis_resize.v + verilogSource + CHECKSUM_a67c1595 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + util_axis_resize.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/util_axis_resize_v1_0.tcl + tclSource + CHECKSUM_9664bffc + XGUI_VERSION_2 + + + + util_axis_resize_v1_0 + + + MASTER_DATA_WIDTH + Master Data Width + 64 + + + SLAVE_DATA_WIDTH + Slave Data Width + 64 + + + BIG_ENDIAN + Big Endian + 0 + + + Component_Name + util_axis_resize_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + util_axis_resize_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:53:28Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_axis_resize/util_axis_resize.v b/adi_library/util_axis_resize/util_axis_resize.v new file mode 100644 index 00000000..0a5b1042 --- /dev/null +++ b/adi_library/util_axis_resize/util_axis_resize.v @@ -0,0 +1,163 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_axis_resize #( + + parameter MASTER_DATA_WIDTH = 64, + parameter SLAVE_DATA_WIDTH = 64, + parameter BIG_ENDIAN = 0 +) ( + input clk, + input resetn, + + input s_valid, + output s_ready, + input [SLAVE_DATA_WIDTH-1:0] s_data, + + output m_valid, + input m_ready, + output [MASTER_DATA_WIDTH-1:0] m_data +); + + localparam RATIO = (SLAVE_DATA_WIDTH < MASTER_DATA_WIDTH) ? + MASTER_DATA_WIDTH / SLAVE_DATA_WIDTH : + SLAVE_DATA_WIDTH / MASTER_DATA_WIDTH; + + function integer clog2; + input integer value; + begin + value = value-1; + for (clog2=0; value>0; clog2=clog2+1) + value = value>>1; + end + endfunction + + generate if (SLAVE_DATA_WIDTH == MASTER_DATA_WIDTH) begin + + assign m_valid = s_valid; + assign s_ready = m_ready; + assign m_data = s_data; + + end else if (SLAVE_DATA_WIDTH < MASTER_DATA_WIDTH) begin + + reg [MASTER_DATA_WIDTH-1:0] data; + reg [clog2(RATIO)-1:0] count; + reg valid; + + always @(posedge clk) + begin + if (resetn == 1'b0) begin + count <= RATIO - 1; + valid <= 1'b0; + end else begin + if (count == 'h00 && s_ready == 1'b1 && s_valid == 1'b1) + valid <= 1'b1; + else if (m_ready == 1'b1) + valid <= 1'b0; + + if (s_ready == 1'b1 && s_valid == 1'b1) begin + if (count == 'h00) + count <= RATIO - 1; + else + count <= count - 1'b1; + end + end + end + + always @(posedge clk) + begin + if (s_ready == 1'b1 && s_valid == 1'b1) + if (BIG_ENDIAN == 1) begin + data <= {data[MASTER_DATA_WIDTH-SLAVE_DATA_WIDTH-1:0], s_data}; + end else begin + data <= {s_data, data[MASTER_DATA_WIDTH-1:SLAVE_DATA_WIDTH]}; + end + end + + assign s_ready = ~valid || m_ready; + assign m_valid = valid; + assign m_data = data; + + end else begin + + reg [SLAVE_DATA_WIDTH-1:0] data; + reg [clog2(RATIO)-1:0] count; + reg valid; + + always @(posedge clk) + begin + if (resetn == 1'b0) begin + count <= RATIO - 1; + valid <= 1'b0; + end else begin + if (s_valid == 1'b1 && s_ready == 1'b1) + valid <= 1'b1; + else if (count == 'h0 && m_ready == 1'b1 && m_valid == 1'b1) + valid <= 1'b0; + + if (m_ready == 1'b1 && m_valid == 1'b1) begin + if (count == 'h00) + count <= RATIO - 1; + else + count <= count - 1'b1; + end + end + end + + always @(posedge clk) + begin + if (s_ready == 1'b1 && s_valid == 1'b1) begin + data <= s_data; + end else if (m_ready == 1'b1 && m_valid == 1'b1) begin + if (BIG_ENDIAN == 1) begin + data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH] <= data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0]; + end else begin + data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0] <= data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH]; + end + end + end + + assign s_ready = ~valid || (m_ready && count == 'h0); + assign m_valid = valid; + assign m_data = BIG_ENDIAN == 1 ? + data[SLAVE_DATA_WIDTH-1:SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH] : + data[MASTER_DATA_WIDTH-1:0]; + + end + endgenerate + +endmodule diff --git a/adi_library/util_axis_resize/util_axis_resize.xpr b/adi_library/util_axis_resize/util_axis_resize.xpr new file mode 100644 index 00000000..e678208a --- /dev/null +++ b/adi_library/util_axis_resize/util_axis_resize.xpr @@ -0,0 +1,399 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_axis_resize/util_axis_resize_ip.tcl b/adi_library/util_axis_resize/util_axis_resize_ip.tcl new file mode 100644 index 00000000..afe58448 --- /dev/null +++ b/adi_library/util_axis_resize/util_axis_resize_ip.tcl @@ -0,0 +1,35 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_axis_resize +adi_ip_files util_axis_resize [list \ + "util_axis_resize.v" ] + +adi_ip_properties_lite util_axis_resize + +adi_add_bus "s_axis" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"s_valid" "TVALID"} \ + {"s_ready" "TREADY"} \ + {"s_data" "TDATA"} \ + } + +adi_add_bus "m_axis" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"m_valid" "TVALID"} \ + {"m_ready" "TREADY"} \ + {"m_data" "TDATA"} \ + } + +adi_add_bus_clock "clk" "s_axis:m_axis" "resetn" + +ipx::save_core [ipx::current_core] diff --git a/adi_library/util_axis_resize/xgui/util_axis_resize_v1_0.tcl b/adi_library/util_axis_resize/xgui/util_axis_resize_v1_0.tcl new file mode 100644 index 00000000..5d2fe72d --- /dev/null +++ b/adi_library/util_axis_resize/xgui/util_axis_resize_v1_0.tcl @@ -0,0 +1,55 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "BIG_ENDIAN" -parent ${Page_0} + ipgui::add_param $IPINST -name "MASTER_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "SLAVE_DATA_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.BIG_ENDIAN { PARAM_VALUE.BIG_ENDIAN } { + # Procedure called to update BIG_ENDIAN when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.BIG_ENDIAN { PARAM_VALUE.BIG_ENDIAN } { + # Procedure called to validate BIG_ENDIAN + return true +} + +proc update_PARAM_VALUE.MASTER_DATA_WIDTH { PARAM_VALUE.MASTER_DATA_WIDTH } { + # Procedure called to update MASTER_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.MASTER_DATA_WIDTH { PARAM_VALUE.MASTER_DATA_WIDTH } { + # Procedure called to validate MASTER_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.SLAVE_DATA_WIDTH { PARAM_VALUE.SLAVE_DATA_WIDTH } { + # Procedure called to update SLAVE_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SLAVE_DATA_WIDTH { PARAM_VALUE.SLAVE_DATA_WIDTH } { + # Procedure called to validate SLAVE_DATA_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.MASTER_DATA_WIDTH { MODELPARAM_VALUE.MASTER_DATA_WIDTH PARAM_VALUE.MASTER_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.MASTER_DATA_WIDTH}] ${MODELPARAM_VALUE.MASTER_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.SLAVE_DATA_WIDTH { MODELPARAM_VALUE.SLAVE_DATA_WIDTH PARAM_VALUE.SLAVE_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SLAVE_DATA_WIDTH}] ${MODELPARAM_VALUE.SLAVE_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.BIG_ENDIAN { MODELPARAM_VALUE.BIG_ENDIAN PARAM_VALUE.BIG_ENDIAN } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.BIG_ENDIAN}] ${MODELPARAM_VALUE.BIG_ENDIAN} +} + diff --git a/adi_library/util_axis_upscale/Makefile b/adi_library/util_axis_upscale/Makefile new file mode 100644 index 00000000..fca516b7 --- /dev/null +++ b/adi_library/util_axis_upscale/Makefile @@ -0,0 +1,13 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_axis_upscale + +GENERIC_DEPS += ../common/util_axis_upscale.v + +XILINX_DEPS += util_axis_upscale_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/util_axis_upscale/component.xml b/adi_library/util_axis_upscale/component.xml new file mode 100644 index 00000000..ab3b4647 --- /dev/null +++ b/adi_library/util_axis_upscale/component.xml @@ -0,0 +1,442 @@ + + + analog.com + user + util_axis_upscale + 1.0 + + + s_axis + + + + + + + TVALID + + + s_axis_valid + + + + + TREADY + + + s_axis_ready + + + + + TDATA + + + s_axis_data + + + + + + s_axis_signal_clock + s_axis_signal_clock + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_BUSIF + s_axis:m_axis + + + ASSOCIATED_RESET + resetn + + + + + s_axis_signal_reset + s_axis_signal_reset + + + + + + + RST + + + resetn + + + + + + POLARITY + ACTIVE_LOW + + + + + m_axis + + + + + + + TVALID + + + m_axis_valid + + + + + TREADY + + + m_axis_ready + + + + + TDATA + + + m_axis_data + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_axis_upscale + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 81d2643b + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_axis_upscale + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 81d2643b + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 690ac9cf + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + resetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_ready + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_data + + in + + 95 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_axis_valid + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_data + + out + + 127 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dfmt_enable + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dfmt_type + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dfmt_se + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + NUM_OF_CHANNELS + Num Of Channels + 4 + + + DATA_WIDTH + Data Width + 24 + + + UDATA_WIDTH + Udata Width + 32 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../common/util_axis_upscale.v + verilogSource + CHECKSUM_81d2643b + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/util_axis_upscale.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/util_axis_upscale_v1_0.tcl + tclSource + CHECKSUM_690ac9cf + XGUI_VERSION_2 + + + + util_axis_upscale_v1_0 + + + NUM_OF_CHANNELS + Num Of Channels + 4 + + + DATA_WIDTH + Data Width + 24 + + + UDATA_WIDTH + Udata Width + 32 + + + Component_Name + util_axis_upscale_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + util_axis_upscale_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:53:35Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_axis_upscale/util_axis_upscale.xpr b/adi_library/util_axis_upscale/util_axis_upscale.xpr new file mode 100644 index 00000000..ccc8b210 --- /dev/null +++ b/adi_library/util_axis_upscale/util_axis_upscale.xpr @@ -0,0 +1,399 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_axis_upscale/util_axis_upscale_ip.tcl b/adi_library/util_axis_upscale/util_axis_upscale_ip.tcl new file mode 100644 index 00000000..711b446e --- /dev/null +++ b/adi_library/util_axis_upscale/util_axis_upscale_ip.tcl @@ -0,0 +1,36 @@ +############################################################################### +## Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_axis_upscale +adi_ip_files util_axis_upscale [list \ + "$ad_hdl_dir/library/common/util_axis_upscale.v"] + +adi_ip_properties_lite util_axis_upscale + +adi_add_bus "s_axis" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"s_axis_valid" "TVALID"} \ + {"s_axis_ready" "TREADY"} \ + {"s_axis_data" "TDATA"} \ + } +adi_add_bus_clock "clk" "s_axis" "resetn" + +adi_add_bus "m_axis" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + { + {"m_axis_valid" "TVALID"} \ + {"m_axis_ready" "TREADY"} \ + {"m_axis_data" "TDATA"} \ + } +ipx::associate_bus_interfaces -busif m_axis -clock s_axis_signal_clock [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/util_axis_upscale/xgui/util_axis_upscale_v1_0.tcl b/adi_library/util_axis_upscale/xgui/util_axis_upscale_v1_0.tcl new file mode 100644 index 00000000..912821e2 --- /dev/null +++ b/adi_library/util_axis_upscale/xgui/util_axis_upscale_v1_0.tcl @@ -0,0 +1,55 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_OF_CHANNELS" -parent ${Page_0} + ipgui::add_param $IPINST -name "UDATA_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to validate DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to update NUM_OF_CHANNELS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to validate NUM_OF_CHANNELS + return true +} + +proc update_PARAM_VALUE.UDATA_WIDTH { PARAM_VALUE.UDATA_WIDTH } { + # Procedure called to update UDATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.UDATA_WIDTH { PARAM_VALUE.UDATA_WIDTH } { + # Procedure called to validate UDATA_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.NUM_OF_CHANNELS { MODELPARAM_VALUE.NUM_OF_CHANNELS PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_CHANNELS}] ${MODELPARAM_VALUE.NUM_OF_CHANNELS} +} + +proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.UDATA_WIDTH { MODELPARAM_VALUE.UDATA_WIDTH PARAM_VALUE.UDATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.UDATA_WIDTH}] ${MODELPARAM_VALUE.UDATA_WIDTH} +} + diff --git a/adi_library/util_bsplit/Makefile b/adi_library/util_bsplit/Makefile new file mode 100644 index 00000000..43a6267b --- /dev/null +++ b/adi_library/util_bsplit/Makefile @@ -0,0 +1,15 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_bsplit + +GENERIC_DEPS += util_bsplit.v + +XILINX_DEPS += util_bsplit_ip.tcl + +INTEL_DEPS += util_bsplit_hw.tcl + +include ../scripts/library.mk diff --git a/adi_library/util_bsplit/component.xml b/adi_library/util_bsplit/component.xml new file mode 100644 index 00000000..25880222 --- /dev/null +++ b/adi_library/util_bsplit/component.xml @@ -0,0 +1,385 @@ + + + analog.com + user + util_bsplit + 1.0 + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_bsplit + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + ada098d6 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_bsplit + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + ada098d6 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 9b1f267c + + + + + + + data + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + split_data_0 + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + split_data_1 + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + split_data_2 + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + split_data_3 + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + split_data_4 + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + split_data_5 + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + split_data_6 + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + split_data_7 + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + + + CHANNEL_DATA_WIDTH + Channel Data Width + 1 + + + NUM_OF_CHANNELS + Num Of Channels + 8 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + util_bsplit.v + verilogSource + CHECKSUM_ada098d6 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + util_bsplit.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/util_bsplit_v1_0.tcl + tclSource + CHECKSUM_9b1f267c + XGUI_VERSION_2 + + + + util_bsplit_v1_0 + + + CHANNEL_DATA_WIDTH + Channel Data Width + 1 + + + NUM_OF_CHANNELS + Num Of Channels + 8 + + + Component_Name + util_bsplit_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + util_bsplit_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:53:43Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_bsplit/util_bsplit.v b/adi_library/util_bsplit/util_bsplit.v new file mode 100644 index 00000000..4371e2c1 --- /dev/null +++ b/adi_library/util_bsplit/util_bsplit.v @@ -0,0 +1,76 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// too bad- we have to do this! + +`timescale 1ns/100ps + +module util_bsplit #( + + parameter CHANNEL_DATA_WIDTH = 1, + parameter NUM_OF_CHANNELS = 8 +) ( + input [((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] data, + + output [(CHANNEL_DATA_WIDTH-1):0] split_data_0, + output [(CHANNEL_DATA_WIDTH-1):0] split_data_1, + output [(CHANNEL_DATA_WIDTH-1):0] split_data_2, + output [(CHANNEL_DATA_WIDTH-1):0] split_data_3, + output [(CHANNEL_DATA_WIDTH-1):0] split_data_4, + output [(CHANNEL_DATA_WIDTH-1):0] split_data_5, + output [(CHANNEL_DATA_WIDTH-1):0] split_data_6, + output [(CHANNEL_DATA_WIDTH-1):0] split_data_7 +); + + localparam NUM_OF_CHANNELS_M = 9; + + // internal signals + + wire [((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):0] data_s; + + // extend and split + + assign data_s[((NUM_OF_CHANNELS_M*CHANNEL_DATA_WIDTH)-1):(NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)] = 'd0; + assign data_s[((NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH)-1):0] = data; + + assign split_data_0 = data_s[((CHANNEL_DATA_WIDTH*1)-1):(CHANNEL_DATA_WIDTH*0)]; + assign split_data_1 = data_s[((CHANNEL_DATA_WIDTH*2)-1):(CHANNEL_DATA_WIDTH*1)]; + assign split_data_2 = data_s[((CHANNEL_DATA_WIDTH*3)-1):(CHANNEL_DATA_WIDTH*2)]; + assign split_data_3 = data_s[((CHANNEL_DATA_WIDTH*4)-1):(CHANNEL_DATA_WIDTH*3)]; + assign split_data_4 = data_s[((CHANNEL_DATA_WIDTH*5)-1):(CHANNEL_DATA_WIDTH*4)]; + assign split_data_5 = data_s[((CHANNEL_DATA_WIDTH*6)-1):(CHANNEL_DATA_WIDTH*5)]; + assign split_data_6 = data_s[((CHANNEL_DATA_WIDTH*7)-1):(CHANNEL_DATA_WIDTH*6)]; + assign split_data_7 = data_s[((CHANNEL_DATA_WIDTH*8)-1):(CHANNEL_DATA_WIDTH*7)]; + +endmodule diff --git a/adi_library/util_bsplit/util_bsplit.xpr b/adi_library/util_bsplit/util_bsplit.xpr new file mode 100644 index 00000000..64c3d463 --- /dev/null +++ b/adi_library/util_bsplit/util_bsplit.xpr @@ -0,0 +1,399 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_bsplit/util_bsplit_hw.tcl b/adi_library/util_bsplit/util_bsplit_hw.tcl new file mode 100644 index 00000000..98283dff --- /dev/null +++ b/adi_library/util_bsplit/util_bsplit_hw.tcl @@ -0,0 +1,70 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +source ../../scripts/adi_env.tcl +source ../scripts/adi_ip_intel.tcl + + +set_module_property NAME util_bsplit +set_module_property DESCRIPTION "Channel Split Utility" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME util_bsplit +set_module_property ELABORATION_CALLBACK p_util_bsplit + +# files + +add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis" +set_fileset_property quartus_synth TOP_LEVEL util_bsplit +add_fileset_file util_bsplit.v VERILOG PATH util_bsplit.v TOP_LEVEL_FILE + +# parameters + +add_parameter CHANNEL_DATA_WIDTH INTEGER 0 +set_parameter_property CHANNEL_DATA_WIDTH DEFAULT_VALUE 32 +set_parameter_property CHANNEL_DATA_WIDTH DISPLAY_NAME CHANNEL_DATA_WIDTH +set_parameter_property CHANNEL_DATA_WIDTH UNITS None +set_parameter_property CHANNEL_DATA_WIDTH HDL_PARAMETER true + +add_parameter NUM_OF_CHANNELS INTEGER 0 +set_parameter_property NUM_OF_CHANNELS DEFAULT_VALUE 8 +set_parameter_property NUM_OF_CHANNELS DISPLAY_NAME NUM_OF_CHANNELS +set_parameter_property NUM_OF_CHANNELS UNITS None +set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true + +# avalon streaming + +ad_interface signal data input NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH +ad_interface signal split_data_0 output CHANNEL_DATA_WIDTH data + +proc p_util_bsplit {} { + + set p_ch_cnt [get_parameter_value "NUM_OF_CHANNELS"] + set p_ch_dw [get_parameter_value "CHANNEL_DATA_WIDTH"] + + if {[get_parameter_value NUM_OF_CHANNELS] > 1} { + ad_interface signal split_data_1 output CHANNEL_DATA_WIDTH data + } + if {[get_parameter_value NUM_OF_CHANNELS] > 2} { + ad_interface signal split_data_2 output CHANNEL_DATA_WIDTH data + } + if {[get_parameter_value NUM_OF_CHANNELS] > 3} { + ad_interface signal split_data_3 output CHANNEL_DATA_WIDTH data + } + if {[get_parameter_value NUM_OF_CHANNELS] > 4} { + ad_interface signal split_data_4 output CHANNEL_DATA_WIDTH data + } + if {[get_parameter_value NUM_OF_CHANNELS] > 5} { + ad_interface signal split_data_5 output CHANNEL_DATA_WIDTH data + } + if {[get_parameter_value NUM_OF_CHANNELS] > 6} { + ad_interface signal split_data_6 output CHANNEL_DATA_WIDTH data + } + if {[get_parameter_value NUM_OF_CHANNELS] > 7} { + ad_interface signal split_data_7 output CHANNEL_DATA_WIDTH data + } +} + diff --git a/adi_library/util_bsplit/util_bsplit_ip.tcl b/adi_library/util_bsplit/util_bsplit_ip.tcl new file mode 100644 index 00000000..ca0fcd04 --- /dev/null +++ b/adi_library/util_bsplit/util_bsplit_ip.tcl @@ -0,0 +1,46 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_bsplit +adi_ip_files util_bsplit [list \ + "util_bsplit.v" ] + +adi_ip_properties_lite util_bsplit + +set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1}} \ + [ipx::get_ports *_1* -of_objects [ipx::current_core]] \ + + +set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2}} \ + [ipx::get_ports *_2* -of_objects [ipx::current_core]] \ + + +set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3}} \ + [ipx::get_ports *_3* -of_objects [ipx::current_core]] \ + + +set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4}} \ + [ipx::get_ports *_4* -of_objects [ipx::current_core]] \ + + +set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5}} \ + [ipx::get_ports *_5* -of_objects [ipx::current_core]] \ + + +set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6}} \ + [ipx::get_ports *_6* -of_objects [ipx::current_core]] \ + + +set_property -dict {driver_value {0} enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7}} \ + [ipx::get_ports *_7* -of_objects [ipx::current_core]] \ + + +ipx::save_core [ipx::current_core] + + diff --git a/adi_library/util_bsplit/xgui/util_bsplit_v1_0.tcl b/adi_library/util_bsplit/xgui/util_bsplit_v1_0.tcl new file mode 100644 index 00000000..ba9f451a --- /dev/null +++ b/adi_library/util_bsplit/xgui/util_bsplit_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "CHANNEL_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_OF_CHANNELS" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.CHANNEL_DATA_WIDTH { PARAM_VALUE.CHANNEL_DATA_WIDTH } { + # Procedure called to update CHANNEL_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CHANNEL_DATA_WIDTH { PARAM_VALUE.CHANNEL_DATA_WIDTH } { + # Procedure called to validate CHANNEL_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to update NUM_OF_CHANNELS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to validate NUM_OF_CHANNELS + return true +} + + +proc update_MODELPARAM_VALUE.CHANNEL_DATA_WIDTH { MODELPARAM_VALUE.CHANNEL_DATA_WIDTH PARAM_VALUE.CHANNEL_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CHANNEL_DATA_WIDTH}] ${MODELPARAM_VALUE.CHANNEL_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.NUM_OF_CHANNELS { MODELPARAM_VALUE.NUM_OF_CHANNELS PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_CHANNELS}] ${MODELPARAM_VALUE.NUM_OF_CHANNELS} +} + diff --git a/adi_library/util_cdc/.lock b/adi_library/util_cdc/.lock new file mode 100644 index 00000000..e69de29b diff --git a/adi_library/util_cdc/Makefile b/adi_library/util_cdc/Makefile new file mode 100644 index 00000000..0154cc7d --- /dev/null +++ b/adi_library/util_cdc/Makefile @@ -0,0 +1,16 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_cdc + +GENERIC_DEPS += sync_bits.v +GENERIC_DEPS += sync_data.v +GENERIC_DEPS += sync_event.v +GENERIC_DEPS += sync_gray.v + +XILINX_DEPS += util_cdc_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/util_cdc/component.xml b/adi_library/util_cdc/component.xml new file mode 100644 index 00000000..48a8d6b9 --- /dev/null +++ b/adi_library/util_cdc/component.xml @@ -0,0 +1,247 @@ + + + analog.com + user + util_cdc + 1.0 + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + sync_event + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + b5f3c2f0 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + sync_event + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + b5f3c2f0 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 3416f698 + + + + + + + in_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + in_event + + in + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + out_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + out_event + + out + + 0 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + NUM_OF_EVENTS + Num Of Events + 1 + + + ASYNC_CLK + Async Clk + 1 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + sync_gray.v + verilogSource + + + sync_bits.v + verilogSource + + + sync_data.v + verilogSource + + + sync_event.v + verilogSource + CHECKSUM_afcd7b7e + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + sync_gray.v + verilogSource + + + sync_bits.v + verilogSource + + + sync_data.v + verilogSource + + + sync_event.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/sync_event_v1_0.tcl + tclSource + CHECKSUM_3416f698 + XGUI_VERSION_2 + + + + ADI Clock-Domain-Crossing Utils + + + NUM_OF_EVENTS + Num Of Events + 1 + + + ASYNC_CLK + Async Clk + 1 + + + Component_Name + sync_event_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + ADI Clock-Domain-Crossing Utils + true + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:38:18Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_cdc/sync_bits.v b/adi_library/util_cdc/sync_bits.v new file mode 100644 index 00000000..d6bd616c --- /dev/null +++ b/adi_library/util_cdc/sync_bits.v @@ -0,0 +1,80 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +/* + * Helper module for synchronizing bit signals from one clock domain to another. + * It uses the standard approach of 2 FF in series. + * Note, that while the module allows to synchronize multiple bits at once it is + * only able to synchronize multi-bit signals where at max one bit changes per + * clock cycle (e.g. a gray counter). + */ + +`timescale 1ns/100ps + +module sync_bits #( + + // Number of bits to synchronize + parameter NUM_OF_BITS = 1, + // Whether input and output clocks are asynchronous, if 0 the synchronizer will + // be bypassed and the output signal equals the input signal. + parameter ASYNC_CLK = 1 +) ( + input [NUM_OF_BITS-1:0] in_bits, + input out_resetn, + input out_clk, + output [NUM_OF_BITS-1:0] out_bits +); + + generate if (ASYNC_CLK == 1) begin + reg [NUM_OF_BITS-1:0] cdc_sync_stage1 = 'h0; + reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0; + + always @(posedge out_clk) + begin + if (out_resetn == 1'b0) begin + cdc_sync_stage1 <= 'b0; + cdc_sync_stage2 <= 'b0; + end else begin + cdc_sync_stage1 <= in_bits; + cdc_sync_stage2 <= cdc_sync_stage1; + end + end + + assign out_bits = cdc_sync_stage2; + end else begin + assign out_bits = in_bits; + end endgenerate + +endmodule diff --git a/adi_library/util_cdc/sync_data.v b/adi_library/util_cdc/sync_data.v new file mode 100644 index 00000000..a9f7c1db --- /dev/null +++ b/adi_library/util_cdc/sync_data.v @@ -0,0 +1,95 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module sync_data #( + parameter NUM_OF_BITS = 1, + parameter ASYNC_CLK = 1 +) ( + input in_clk, + input [NUM_OF_BITS-1:0] in_data, + input out_clk, + output reg [NUM_OF_BITS-1:0] out_data +); + + generate + if (ASYNC_CLK == 1) begin + + wire out_toggle; + wire in_toggle; + + reg out_toggle_d1 = 1'b0; + reg in_toggle_d1 = 1'b0; + + reg [NUM_OF_BITS-1:0] cdc_hold; + + sync_bits i_sync_out ( + .in_bits(in_toggle_d1), + .out_clk(out_clk), + .out_resetn(1'b1), + .out_bits(out_toggle)); + + sync_bits i_sync_in ( + .in_bits(out_toggle_d1), + .out_clk(in_clk), + .out_resetn(1'b1), + .out_bits(in_toggle)); + + wire in_load = in_toggle == in_toggle_d1; + wire out_load = out_toggle ^ out_toggle_d1; + + always @(posedge in_clk) begin + if (in_load == 1'b1) begin + cdc_hold <= in_data; + in_toggle_d1 <= ~in_toggle_d1; + end + end + + always @(posedge out_clk) begin + if (out_load == 1'b1) begin + out_data <= cdc_hold; + end + out_toggle_d1 <= out_toggle; + end + + end else begin + always @(*) begin + out_data <= in_data; + end + end + endgenerate + +endmodule diff --git a/adi_library/util_cdc/sync_event.v b/adi_library/util_cdc/sync_event.v new file mode 100644 index 00000000..8c93fe5a --- /dev/null +++ b/adi_library/util_cdc/sync_event.v @@ -0,0 +1,118 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module sync_event #( + parameter NUM_OF_EVENTS = 1, + parameter ASYNC_CLK = 1 +) ( + input in_clk, + input [NUM_OF_EVENTS-1:0] in_event, + input out_clk, + output reg [NUM_OF_EVENTS-1:0] out_event +); + + generate + if (ASYNC_CLK == 1) begin + + wire out_toggle; + wire in_toggle; + + reg out_toggle_d1 = 1'b0; + reg in_toggle_d1 = 1'b0; + + sync_bits i_sync_out ( + .in_bits(in_toggle_d1), + .out_clk(out_clk), + .out_resetn(1'b1), + .out_bits(out_toggle)); + + sync_bits i_sync_in ( + .in_bits(out_toggle_d1), + .out_clk(in_clk), + .out_resetn(1'b1), + .out_bits(in_toggle)); + + wire in_ready = in_toggle == in_toggle_d1; + wire load_out = out_toggle ^ out_toggle_d1; + + reg [NUM_OF_EVENTS-1:0] in_event_sticky = 'h00; + wire [NUM_OF_EVENTS-1:0] pending_events = in_event_sticky | in_event; + wire [NUM_OF_EVENTS-1:0] out_event_s; + + always @(posedge in_clk) begin + if (in_ready == 1'b1) begin + in_event_sticky <= {NUM_OF_EVENTS{1'b0}}; + if (|pending_events == 1'b1) begin + in_toggle_d1 <= ~in_toggle_d1; + end + end else begin + in_event_sticky <= pending_events; + end + end + + if (NUM_OF_EVENTS > 1) begin + reg [NUM_OF_EVENTS-1:0] cdc_hold = 'h00; + + always @(posedge in_clk) begin + if (in_ready == 1'b1) begin + cdc_hold <= pending_events; + end + end + + assign out_event_s = cdc_hold; + end else begin + // When there is only one event, we know that it is set. + assign out_event_s = 1'b1; + end + + always @(posedge out_clk) begin + if (load_out == 1'b1) begin + out_event <= out_event_s; + end else begin + out_event <= {NUM_OF_EVENTS{1'b0}}; + end + out_toggle_d1 <= out_toggle; + end + + end else begin + always @(*) begin + out_event <= in_event; + end + end + endgenerate + +endmodule diff --git a/adi_library/util_cdc/sync_gray.v b/adi_library/util_cdc/sync_gray.v new file mode 100644 index 00000000..a60e8559 --- /dev/null +++ b/adi_library/util_cdc/sync_gray.v @@ -0,0 +1,116 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +/* + * Helper module for synchronizing a counter from one clock domain to another + * using gray code. To work correctly the counter must not change its value by + * more than one in one clock cycle in the source domain. I.e. the value may + * change by either -1, 0 or +1. + */ + +`timescale 1ns/100ps + +module sync_gray #( + + // Bit-width of the counter + parameter DATA_WIDTH = 1, + // Whether the input and output clock are asynchronous, if set to 0 the + // synchronizer will be bypassed and out_count will be in_count. + parameter ASYNC_CLK = 1 +) ( + input in_clk, + input in_resetn, + input [DATA_WIDTH-1:0] in_count, + input out_resetn, + input out_clk, + output [DATA_WIDTH-1:0] out_count +); + + generate if (ASYNC_CLK == 1) begin + reg [DATA_WIDTH-1:0] cdc_sync_stage0 = 'h0; + reg [DATA_WIDTH-1:0] cdc_sync_stage1 = 'h0; + reg [DATA_WIDTH-1:0] cdc_sync_stage2 = 'h0; + reg [DATA_WIDTH-1:0] out_count_m = 'h0; + + function [DATA_WIDTH-1:0] g2b; + input [DATA_WIDTH-1:0] g; + reg [DATA_WIDTH-1:0] b; + integer i; + begin + b[DATA_WIDTH-1] = g[DATA_WIDTH-1]; + for (i = DATA_WIDTH - 2; i >= 0; i = i - 1) + b[i] = b[i + 1] ^ g[i]; + g2b = b; + end + endfunction + + function [DATA_WIDTH-1:0] b2g; + input [DATA_WIDTH-1:0] b; + reg [DATA_WIDTH-1:0] g; + integer i; + begin + g[DATA_WIDTH-1] = b[DATA_WIDTH-1]; + for (i = DATA_WIDTH - 2; i >= 0; i = i -1) + g[i] = b[i + 1] ^ b[i]; + b2g = g; + end + endfunction + + always @(posedge in_clk) begin + if (in_resetn == 1'b0) begin + cdc_sync_stage0 <= 'h00; + end else begin + cdc_sync_stage0 <= b2g(in_count); + end + end + + always @(posedge out_clk) begin + if (out_resetn == 1'b0) begin + cdc_sync_stage1 <= 'h00; + cdc_sync_stage2 <= 'h00; + out_count_m <= 'h00; + end else begin + cdc_sync_stage1 <= cdc_sync_stage0; + cdc_sync_stage2 <= cdc_sync_stage1; + out_count_m <= g2b(cdc_sync_stage2); + end + end + + assign out_count = out_count_m; + end else begin + assign out_count = in_count; + end endgenerate + +endmodule diff --git a/adi_library/util_cdc/util_cdc.xpr b/adi_library/util_cdc/util_cdc.xpr new file mode 100644 index 00000000..e50672a4 --- /dev/null +++ b/adi_library/util_cdc/util_cdc.xpr @@ -0,0 +1,421 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_cdc/util_cdc_constr.tcl b/adi_library/util_cdc/util_cdc_constr.tcl new file mode 100644 index 00000000..4d8afbd8 --- /dev/null +++ b/adi_library/util_cdc/util_cdc_constr.tcl @@ -0,0 +1,40 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +proc util_cdc_sync_bits_constr {inst {from {}}} { + if {$from != {}} { + set_false_path \ + -from [get_registers $from] \ + -to [get_registers [format "%s%s" ${inst} {|cdc_sync_stage1[0]}]] + } else { + set_false_path \ + -to [get_registers [format "%s%s" ${inst} {|cdc_sync_stage1[0]}]] + } +} + +proc util_cdc_sync_data_constr {inst} { + util_cdc_sync_bits_constr ${inst}|sync_bits:i_sync_out ${inst}|in_toggle_d1 + util_cdc_sync_bits_constr ${inst}|sync_bits:i_sync_in ${inst}|out_toggle_d1 + + # set_max_skew + set_false_path \ + -from [get_registers [format "%s%s" ${inst} {|cdc_hold[*]}]] \ + -to [get_registers [format "%s%s" ${inst} {|out_data[*]}]] +} + +proc util_cdc_sync_event_constr {inst} { + util_cdc_sync_bits_constr ${inst}|sync_bits:i_sync_out ${inst}|in_toggle_d1 + util_cdc_sync_bits_constr ${inst}|sync_bits:i_sync_in ${inst}|out_toggle_d1 + + set cdc_hold_reg [get_registers -nowarn [format "%s%s" ${inst} {|cdc_hold[*]}]] + + # For a event synchronizer with one event there is no hold register + if {[get_collection_size ${cdc_hold_reg}] != 0} { + # set_max_skew + set_false_path \ + -from ${cdc_hold_reg} \ + -to [get_registers [format "%s%s" ${inst} {|out_event[*]}]] + } +} diff --git a/adi_library/util_cdc/util_cdc_ip.tcl b/adi_library/util_cdc/util_cdc_ip.tcl new file mode 100644 index 00000000..97363a8b --- /dev/null +++ b/adi_library/util_cdc/util_cdc_ip.tcl @@ -0,0 +1,27 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_cdc + +add_files -fileset [get_filesets sources_1] [list \ + "sync_gray.v" \ + "sync_bits.v" \ + "sync_data.v" \ + "sync_event.v" \ +] + +set_property source_mgmt_mode DisplayOnly [current_project] + +adi_ip_properties_lite util_cdc + +set_property name "util_cdc" [ipx::current_core] +set_property display_name "ADI Clock-Domain-Crossing Utils" [ipx::current_core] +set_property description "ADI Clock-Domain-Crossing Utils" [ipx::current_core] +set_property hide_in_gui {1} [ipx::current_core] + +ipx::save_core [ipx::current_core] diff --git a/adi_library/util_cdc/xgui/sync_event_v1_0.tcl b/adi_library/util_cdc/xgui/sync_event_v1_0.tcl new file mode 100644 index 00000000..c05ab22f --- /dev/null +++ b/adi_library/util_cdc/xgui/sync_event_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ASYNC_CLK" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_OF_EVENTS" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } { + # Procedure called to update ASYNC_CLK when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ASYNC_CLK { PARAM_VALUE.ASYNC_CLK } { + # Procedure called to validate ASYNC_CLK + return true +} + +proc update_PARAM_VALUE.NUM_OF_EVENTS { PARAM_VALUE.NUM_OF_EVENTS } { + # Procedure called to update NUM_OF_EVENTS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_EVENTS { PARAM_VALUE.NUM_OF_EVENTS } { + # Procedure called to validate NUM_OF_EVENTS + return true +} + + +proc update_MODELPARAM_VALUE.NUM_OF_EVENTS { MODELPARAM_VALUE.NUM_OF_EVENTS PARAM_VALUE.NUM_OF_EVENTS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_EVENTS}] ${MODELPARAM_VALUE.NUM_OF_EVENTS} +} + +proc update_MODELPARAM_VALUE.ASYNC_CLK { MODELPARAM_VALUE.ASYNC_CLK PARAM_VALUE.ASYNC_CLK } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ASYNC_CLK}] ${MODELPARAM_VALUE.ASYNC_CLK} +} + diff --git a/adi_library/util_cic/.lock b/adi_library/util_cic/.lock new file mode 100644 index 00000000..e69de29b diff --git a/adi_library/util_cic/Makefile b/adi_library/util_cic/Makefile new file mode 100644 index 00000000..401b8e7e --- /dev/null +++ b/adi_library/util_cic/Makefile @@ -0,0 +1,14 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_cic + +GENERIC_DEPS += cic_comb.v +GENERIC_DEPS += cic_int.v + +XILINX_DEPS += util_cic_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/util_cic/cic_comb.v b/adi_library/util_cic/cic_comb.v new file mode 100644 index 00000000..de176ceb --- /dev/null +++ b/adi_library/util_cic/cic_comb.v @@ -0,0 +1,131 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module cic_comb #( + parameter DATA_WIDTH = 32, + parameter SEQ = 1, + parameter STAGE_WIDTH = 1, + parameter NUM_STAGES = 1 +) ( + input clk, + input ce, + input [NUM_STAGES-1:0] enable, + input [DATA_WIDTH-1:0] data_in, + output [DATA_WIDTH-1:0] data_out +); + + reg [SEQ-1:0] storage[0:DATA_WIDTH-1]; + reg [DATA_WIDTH-1:0] state = 'h00; + + reg [2:0] counter = 'h00; + reg active = 1'b0; + + integer x; + + initial begin + for (x = 0; x < DATA_WIDTH; x = x + 1) begin + storage[x] = 'h00; + end + end + + generate if (SEQ != 1) begin + + always @(posedge clk) begin + if (ce == 1'b1) begin + counter <= SEQ-1; + active <= 1'b1; + end else if (active == 1'b1) begin + counter <= counter - 1'b1; + if (counter == 'h1) begin + active <= 1'b0; + end + end + end + + end + endgenerate + + wire [DATA_WIDTH-1:0] mask; + reg [DATA_WIDTH-1:0] data_in_seq; + wire [DATA_WIDTH-1:0] storage_out; + wire [DATA_WIDTH-1:0] diff = (data_in_seq | ~mask) - (storage_out & mask); + + always @(*) begin + if (ce == 1'b1) begin + data_in_seq <= data_in; + end else begin + data_in_seq <= SEQ != 1 ? state : 'h00; + end + end + + generate + genvar i, j; + + for (j = 0; j < NUM_STAGES; j = j + 1) begin + localparam k = NUM_STAGES - j - 1; + localparam H = DATA_WIDTH - STAGE_WIDTH * j - 1; + localparam L = k == 0 ? 0 : DATA_WIDTH - STAGE_WIDTH * (j+1); + + assign mask[H:L] = {{H-L{1'b1}},k != 0 ? enable[k] : 1'b1}; + + for (i = L; i <= H; i = i + 1) begin: shift_r + always @(posedge clk) begin + if (enable[k] == 1'b1 && (ce == 1'b1 || active == 1'b1)) begin + if (SEQ > 1) begin + storage[i] <= {storage[i][SEQ-2:0],data_in_seq[i]}; + end else begin + storage[i] <= data_in_seq[i]; + end + end + end + + assign storage_out[i] = storage[i][SEQ-1]; + + end + + always @(posedge clk) begin + if (enable[k] == 1'b1 && (ce == 1'b1 || active == 1'b1)) begin + state[H:L] <= diff[H:L]; + end + end + end + + endgenerate + + assign data_out = state; + +endmodule diff --git a/adi_library/util_cic/cic_int.v b/adi_library/util_cic/cic_int.v new file mode 100644 index 00000000..06fbd8fd --- /dev/null +++ b/adi_library/util_cic/cic_int.v @@ -0,0 +1,74 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module cic_int #( + parameter DATA_WIDTH = 12, + parameter STAGE_WIDTH = 1, + parameter NUM_STAGES = 1 +) ( + input clk, + input [NUM_STAGES-1:0] ce, + input [DATA_WIDTH-1:0] data_in, + output [DATA_WIDTH-1:0] data_out +); + + reg [DATA_WIDTH-1:0] state = 'h00; + wire [DATA_WIDTH-1:0] sum; + wire [DATA_WIDTH-1:0] mask; + + assign data_out = state; + assign sum = (data_in & mask) + (state & mask); + generate + genvar i; + + for (i = 0; i < NUM_STAGES; i = i + 1) begin + localparam j = NUM_STAGES - i - 1; + localparam H = DATA_WIDTH - STAGE_WIDTH * i - 1; + localparam L = j == 0 ? 0 : DATA_WIDTH - STAGE_WIDTH * (i+1); + + assign mask[H:L] = {{H-L{1'b1}},j != 0 ? ce[j] : 1'b1}; + + always @(posedge clk) begin + if (ce[j] == 1'b1) begin + state[H:L] <= sum[H:L]; + end + end + end + + endgenerate + +endmodule diff --git a/adi_library/util_cic/component.xml b/adi_library/util_cic/component.xml new file mode 100644 index 00000000..6a3bb58c --- /dev/null +++ b/adi_library/util_cic/component.xml @@ -0,0 +1,268 @@ + + + analog.com + user + util_cic + 1.0 + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + cic_comb + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 55312928 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + cic_comb + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 55312928 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + fe1ab863 + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ce + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + enable + + in + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_in + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_out + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + DATA_WIDTH + Data Width + 32 + + + SEQ + Seq + 1 + + + STAGE_WIDTH + Stage Width + 1 + + + NUM_STAGES + Num Stages + 1 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + cic_int.v + verilogSource + + + cic_comb.v + verilogSource + CHECKSUM_17b13b1f + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + cic_int.v + verilogSource + + + cic_comb.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/cic_comb_v1_0.tcl + tclSource + CHECKSUM_fe1ab863 + XGUI_VERSION_2 + + + + CIC building blocks + + + DATA_WIDTH + Data Width + 32 + + + SEQ + Seq + 1 + + + STAGE_WIDTH + Stage Width + 1 + + + NUM_STAGES + Num Stages + 1 + + + Component_Name + cic_comb_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + CIC building blocks + true + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:44:04Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_cic/util_cic.xpr b/adi_library/util_cic/util_cic.xpr new file mode 100644 index 00000000..05d3d7bf --- /dev/null +++ b/adi_library/util_cic/util_cic.xpr @@ -0,0 +1,407 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_cic/util_cic_ip.tcl b/adi_library/util_cic/util_cic_ip.tcl new file mode 100644 index 00000000..0d6bc8e4 --- /dev/null +++ b/adi_library/util_cic/util_cic_ip.tcl @@ -0,0 +1,25 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_cic + +add_files -fileset [get_filesets sources_1] [list \ + "cic_int.v" \ + "cic_comb.v" \ +] + +set_property source_mgmt_mode DisplayOnly [current_project] + +adi_ip_properties_lite util_cic + +set_property name "util_cic" [ipx::current_core] +set_property display_name "CIC building blocks" [ipx::current_core] +set_property description "CIC building blocks" [ipx::current_core] +set_property hide_in_gui {1} [ipx::current_core] + +ipx::save_core [ipx::current_core] diff --git a/adi_library/util_cic/xgui/cic_comb_v1_0.tcl b/adi_library/util_cic/xgui/cic_comb_v1_0.tcl new file mode 100644 index 00000000..09c4a98a --- /dev/null +++ b/adi_library/util_cic/xgui/cic_comb_v1_0.tcl @@ -0,0 +1,70 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_STAGES" -parent ${Page_0} + ipgui::add_param $IPINST -name "SEQ" -parent ${Page_0} + ipgui::add_param $IPINST -name "STAGE_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to validate DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.NUM_STAGES { PARAM_VALUE.NUM_STAGES } { + # Procedure called to update NUM_STAGES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_STAGES { PARAM_VALUE.NUM_STAGES } { + # Procedure called to validate NUM_STAGES + return true +} + +proc update_PARAM_VALUE.SEQ { PARAM_VALUE.SEQ } { + # Procedure called to update SEQ when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SEQ { PARAM_VALUE.SEQ } { + # Procedure called to validate SEQ + return true +} + +proc update_PARAM_VALUE.STAGE_WIDTH { PARAM_VALUE.STAGE_WIDTH } { + # Procedure called to update STAGE_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.STAGE_WIDTH { PARAM_VALUE.STAGE_WIDTH } { + # Procedure called to validate STAGE_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.SEQ { MODELPARAM_VALUE.SEQ PARAM_VALUE.SEQ } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SEQ}] ${MODELPARAM_VALUE.SEQ} +} + +proc update_MODELPARAM_VALUE.STAGE_WIDTH { MODELPARAM_VALUE.STAGE_WIDTH PARAM_VALUE.STAGE_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.STAGE_WIDTH}] ${MODELPARAM_VALUE.STAGE_WIDTH} +} + +proc update_MODELPARAM_VALUE.NUM_STAGES { MODELPARAM_VALUE.NUM_STAGES PARAM_VALUE.NUM_STAGES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_STAGES}] ${MODELPARAM_VALUE.NUM_STAGES} +} + diff --git a/adi_library/util_dacfifo/Makefile b/adi_library/util_dacfifo/Makefile new file mode 100644 index 00000000..3f866fe8 --- /dev/null +++ b/adi_library/util_dacfifo/Makefile @@ -0,0 +1,23 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_dacfifo + +GENERIC_DEPS += ../common/ad_b2g.v +GENERIC_DEPS += ../common/ad_g2b.v +GENERIC_DEPS += ../common/ad_mem.v +GENERIC_DEPS += ../common/ad_mem_asym.v +GENERIC_DEPS += util_dacfifo.v +GENERIC_DEPS += util_dacfifo_bypass.v + +XILINX_DEPS += util_dacfifo_constr.xdc +XILINX_DEPS += util_dacfifo_ip.tcl +XILINX_DEPS += util_dacfifo_ooc.ttcl + +INTEL_DEPS += util_dacfifo_constr.sdc +INTEL_DEPS += util_dacfifo_hw.tcl + +include ../scripts/library.mk diff --git a/adi_library/util_dacfifo/component.xml b/adi_library/util_dacfifo/component.xml new file mode 100644 index 00000000..d5e0791f --- /dev/null +++ b/adi_library/util_dacfifo/component.xml @@ -0,0 +1,457 @@ + + + analog.com + user + util_dacfifo + 1.0 + + + dma_clk + + + + + + + CLK + + + dma_clk + + + + + + ASSOCIATED_RESET + dma_rst + + + + + dma_rst + + + + + + + RST + + + dma_rst + + + + + + dac_clk + + + + + + + CLK + + + dac_clk + + + + + + ASSOCIATED_RESET + dac_rst + + + + + dac_rst + + + + + + + RST + + + dac_rst + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_dacfifo + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 71800a14 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_dacfifo + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + fb2fd7ae + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 7dfe8a5d + + + + + + + dma_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_rst + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_data + + in + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + dma_ready + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_xfer_req + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_xfer_last + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_rst + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_data + + out + + 127 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_dunf + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_xfer_out + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + bypass + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + ADDRESS_WIDTH + Address Width + 6 + + + DATA_WIDTH + Data Width + 128 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + util_dacfifo_ooc.ttcl + ttcl + + + util_dacfifo_constr.xdc + xdc + + + ../common/ad_b2g.v + verilogSource + + + ../common/ad_g2b.v + verilogSource + + + ../common/ad_mem.v + verilogSource + + + ../common/ad_mem_asym.v + verilogSource + + + util_dacfifo_bypass.v + verilogSource + + + util_dacfifo.v + verilogSource + CHECKSUM_3ff18447 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_b2g.v + verilogSource + + + ../common/ad_g2b.v + verilogSource + + + ../common/ad_mem.v + verilogSource + + + ../common/ad_mem_asym.v + verilogSource + + + util_dacfifo_bypass.v + verilogSource + + + util_dacfifo.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/util_dacfifo_v1_0.tcl + tclSource + CHECKSUM_7dfe8a5d + XGUI_VERSION_2 + + + + util_dacfifo_v1_0 + + + ADDRESS_WIDTH + Address Width + 6 + + + DATA_WIDTH + Data Width + 128 + + + Component_Name + util_dacfifo_v1_0 + + + + + + virtex7 + + + /Analog_Devices + + util_dacfifo_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:53:57Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_dacfifo/util_dacfifo.v b/adi_library/util_dacfifo/util_dacfifo.v new file mode 100644 index 00000000..e17f9469 --- /dev/null +++ b/adi_library/util_dacfifo/util_dacfifo.v @@ -0,0 +1,334 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_dacfifo #( + + parameter ADDRESS_WIDTH = 6, + parameter DATA_WIDTH = 128 +) ( + + // DMA interface + + input dma_clk, + input dma_rst, + input dma_valid, + input [(DATA_WIDTH-1):0] dma_data, + output reg dma_ready, + input dma_xfer_req, + input dma_xfer_last, + + // DAC interface + + input dac_clk, + input dac_rst, + input dac_valid, + output reg [(DATA_WIDTH-1):0] dac_data, + output reg dac_dunf, + output reg dac_xfer_out, + + input bypass +); + + localparam FIFO_THRESHOLD_HI = {(ADDRESS_WIDTH){1'b1}} - 4; + + // internal registers + + reg dma_init = 1'b0; + reg [(ADDRESS_WIDTH-1):0] dma_waddr = 'b0; + reg [(ADDRESS_WIDTH-1):0] dma_waddr_g = 'b0; + reg [(ADDRESS_WIDTH-1):0] dma_lastaddr_g = 'b0; + reg dma_bypass = 1'b0; + reg dma_bypass_m1 = 1'b0; + reg dma_xfer_req_d1 = 1'b0; + reg dma_xfer_req_d2 = 1'b0; + reg dma_xfer_out_fifo = 1'b0; + + reg [(ADDRESS_WIDTH-1):0] dac_raddr = 'b0; + reg [(ADDRESS_WIDTH-1):0] dac_waddr = 'b0; + reg [(ADDRESS_WIDTH-1):0] dac_waddr_m1 = 'b0; + reg [(ADDRESS_WIDTH-1):0] dac_waddr_m2 = 'b0; + reg [(ADDRESS_WIDTH-1):0] dac_addr_diff = 'b0; + reg [(ADDRESS_WIDTH-1):0] dac_lastaddr_m1 = 'b0; + reg [(ADDRESS_WIDTH-1):0] dac_lastaddr_m2 = 'b0; + reg [(ADDRESS_WIDTH-1):0] dac_lastaddr = 'b0; + reg dac_mem_ready = 1'b0; + reg dac_xfer_req_m1 = 1'b0; + reg dac_xfer_req = 1'b0; + reg dac_xfer_req_d = 1'b0; + reg dac_xfer_out_fifo = 1'b0; + reg dac_xfer_out_fifo_m1 = 1'b0; + reg dac_xfer_out_fifo_d = 1'b0; + reg dac_bypass = 1'b0; + reg dac_bypass_m1 = 1'b0; + + // internal wires + + wire dma_rst_int_s; + wire dma_wren_s; + wire dma_xfer_posedge_s; + wire dma_ready_bypass_s; + wire [(DATA_WIDTH-1):0] dac_data_fifo_s; + wire [(DATA_WIDTH-1):0] dac_data_bypass_s; + wire [ADDRESS_WIDTH:0] dac_addr_diff_s; + wire [(ADDRESS_WIDTH-1):0] dma_waddr_b2g_s; + wire [(ADDRESS_WIDTH-1):0] dac_waddr_g2b_s; + wire [(ADDRESS_WIDTH-1):0] dac_lastaddr_g2b_s; + wire dac_mem_ren_s; + wire dac_xfer_posedge_s; + wire dac_rst_int_s; + + // internal reset generation + + always @(posedge dma_clk) begin + dma_xfer_req_d1 <= dma_xfer_req; + dma_xfer_req_d2 <= dma_xfer_req_d1; + end + assign dma_xfer_posedge_s = ~dma_xfer_req_d2 & dma_xfer_req_d1; + + // status register indicating that the module is in initialization phase + + always @(posedge dma_clk) begin + if ((dma_rst == 1'b1) || (dma_xfer_last == 1'b1)) begin + dma_init <= 1'b0; + end else begin + if (dma_xfer_posedge_s == 1'b1) begin + dma_init <= 1'b1; + end + end + end + + // if the module is not in initialization phase, it should go + // into reset at a positive edge of dma_xfer_req + + assign dma_rst_int_s = dma_rst | (dma_xfer_posedge_s & ~dma_init); + + // DMA / Write interface + + // write address generation + + assign dma_wren_s = dma_valid & dma_ready; + + always @(posedge dma_clk) begin + if(dma_rst_int_s == 1'b1) begin + dma_waddr <= 'b0; + dma_waddr_g <= 'b0; + dma_xfer_out_fifo <= 1'b0; + end else begin + if (dma_wren_s == 1'b1) begin + dma_waddr <= dma_waddr + 1'b1; + end + if (dma_xfer_last == 1'b1) begin + dma_waddr <= 'b0; + dma_xfer_out_fifo <= 1'b1; + end + dma_waddr_g <= dma_waddr_b2g_s; + end + end + + ad_b2g #( + .DATA_WIDTH (ADDRESS_WIDTH) + ) i_dma_waddr_b2g ( + .din (dma_waddr), + .dout (dma_waddr_b2g_s)); + + // save the last write address + + always @(posedge dma_clk) begin + if (dma_rst_int_s == 1'b1) begin + dma_lastaddr_g <= 'b0; + end else begin + if (dma_bypass == 1'b0) begin + dma_lastaddr_g <= (dma_xfer_last == 1'b1)? dma_waddr_b2g_s : dma_lastaddr_g; + end + end + end + + // DAC / Read interface + + always @(posedge dac_clk) begin + dac_xfer_req_m1 <= dma_xfer_req; + dac_xfer_req <= dac_xfer_req_m1; + dac_xfer_req_d <= dac_xfer_req; + end + assign dac_xfer_posedge_s = ~dac_xfer_req_d & dac_xfer_req; + + // we can reset the DAC side at each positive edge of xfer_req, even if + // sometimes the reset is redundant + assign dac_rst_int_s = dac_xfer_req | dac_rst; + + assign dac_addr_diff_s = {1'b1, dac_waddr} - dac_raddr; + + // The memory module is ready if it's not empty + always @(posedge dac_clk) begin + if (dac_rst_int_s == 1'b1) begin + dac_addr_diff <= 'b0; + dac_waddr_m1 <= 'b0; + dac_waddr_m2 <= 'b0; + dac_waddr <= 'b0; + dac_mem_ready <= 1'b0; + end else begin + dac_waddr_m1 <= dma_waddr_g; + dac_waddr_m2 <= dac_waddr_m1; + dac_waddr <= dac_waddr_g2b_s; + dac_addr_diff <= dac_addr_diff_s[ADDRESS_WIDTH-1:0]; + if (dac_addr_diff > 0) begin + dac_mem_ready <= 1'b1; + end else begin + dac_mem_ready <= 1'b0; + end + end + end + + ad_g2b #( + .DATA_WIDTH (ADDRESS_WIDTH) + ) i_dac_waddr_g2b ( + .din (dac_waddr_m2), + .dout (dac_waddr_g2b_s)); + + // sync lastaddr to dac clock domain + + always @(posedge dac_clk) begin + if (dac_rst_int_s == 1'b1) begin + dac_lastaddr_m1 <= 1'b0; + dac_lastaddr_m2 <= 1'b0; + dac_xfer_out_fifo_m1 <= 1'b0; + dac_xfer_out_fifo <= 1'b0; + dac_xfer_out_fifo_d <= 1'b0; + end else begin + dac_lastaddr_m1 <= dma_lastaddr_g; + dac_lastaddr_m2 <= dac_lastaddr_m1; + dac_lastaddr <= dac_lastaddr_g2b_s; + dac_xfer_out_fifo_m1 <= dma_xfer_out_fifo; + dac_xfer_out_fifo <= dac_xfer_out_fifo_m1; + if (dac_valid) + dac_xfer_out_fifo_d <= dac_xfer_out_fifo; + end + end + + ad_g2b #( + .DATA_WIDTH (ADDRESS_WIDTH) + ) i_dac_lastaddr_g2b ( + .din (dac_lastaddr_m2), + .dout (dac_lastaddr_g2b_s)); + + // generate dac read address + + assign dac_mem_ren_s = (dac_bypass == 1'b1) ? (dac_valid & dac_mem_ready) : + (dac_valid & dac_xfer_out_fifo); + + always @(posedge dac_clk) begin + if (dac_rst_int_s == 1'b1) begin + dac_raddr <= 'b0; + end else begin + if (dac_mem_ren_s == 1'b1) begin + if (dac_lastaddr == 'b0 || dac_raddr != dac_lastaddr) begin + dac_raddr <= dac_raddr + 1'b1; + end else begin + dac_raddr <= 'b0; + end + end + end + end + + // memory instantiation + + ad_mem #( + .ADDRESS_WIDTH (ADDRESS_WIDTH), + .DATA_WIDTH (DATA_WIDTH) + ) i_mem_fifo ( + .clka (dma_clk), + .wea (dma_wren_s), + .addra (dma_waddr), + .dina (dma_data), + .clkb (dac_clk), + .reb (1'b1), + .addrb (dac_raddr), + .doutb (dac_data_fifo_s)); + + // define underflow + // underflow make sense just if bypass is enabled + + always @(posedge dac_clk) begin + if (dac_rst_int_s == 1'b1) begin + dac_dunf <= 1'b0; + end else begin + dac_dunf <= (dac_bypass == 1'b1) ? (dac_valid & dac_xfer_req & ~dac_mem_ren_s) : 1'b0; + end + end + + // bypass logic + + util_dacfifo_bypass #( + .DAC_DATA_WIDTH (DATA_WIDTH), + .DMA_DATA_WIDTH (DATA_WIDTH) + ) i_dacfifo_bypass ( + .dma_clk(dma_clk), + .dma_data(dma_data), + .dma_ready(dma_ready), + .dma_ready_out(dma_ready_bypass_s), + .dma_valid(dma_valid), + .dma_xfer_req(dma_xfer_req), + .dac_clk(dac_clk), + .dac_rst(dac_rst), + .dac_valid(dac_valid), + .dac_data(dac_data_bypass_s), + .dac_dunf(dac_dunf_bypass_s)); + + always @(posedge dma_clk) begin + dma_bypass_m1 <= bypass; + dma_bypass <= dma_bypass_m1; + end + + always @(posedge dac_clk) begin + dac_bypass_m1 <= bypass; + dac_bypass <= dac_bypass_m1; + end + + // the util_dacfifo is always ready for the DMA + always @(posedge dma_clk) begin + dma_ready <= (dma_bypass == 1'b1) ? dma_ready_bypass_s : 1'b1; + end + + always @(posedge dac_clk) begin + if (dac_valid) begin + dac_data <= (dac_bypass == 1'b1) ? dac_data_bypass_s : dac_data_fifo_s; + end + // this signal along with the dac_valid validate the data coming out from the buffer + dac_xfer_out <= (dac_bypass == 1'b1) ? dac_xfer_req : dac_xfer_out_fifo_d; + end + +endmodule diff --git a/adi_library/util_dacfifo/util_dacfifo.xpr b/adi_library/util_dacfifo/util_dacfifo.xpr new file mode 100644 index 00000000..ef9182b4 --- /dev/null +++ b/adi_library/util_dacfifo/util_dacfifo.xpr @@ -0,0 +1,441 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_dacfifo/util_dacfifo_bypass.v b/adi_library/util_dacfifo/util_dacfifo_bypass.v new file mode 100644 index 00000000..eb5e2459 --- /dev/null +++ b/adi_library/util_dacfifo/util_dacfifo_bypass.v @@ -0,0 +1,269 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_dacfifo_bypass #( + + parameter DAC_DATA_WIDTH = 64, + parameter DMA_DATA_WIDTH = 64 +) ( + + // DMA FIFO interface + + input dma_clk, + input [(DMA_DATA_WIDTH-1):0] dma_data, + input dma_ready, + output reg dma_ready_out, + input dma_valid, + + // request and synchronization + + input dma_xfer_req, + + // DAC FIFO interface + + input dac_clk, + input dac_rst, + input dac_valid, + output reg [(DAC_DATA_WIDTH-1):0] dac_data, + output reg dac_dunf +); + + // supported ratios: 1:1 / 1:2 / 1:4 / 1:8 / 2:1 / 4:1 / 8:1 + + localparam MEM_RATIO = (DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? DMA_DATA_WIDTH/DAC_DATA_WIDTH : + DAC_DATA_WIDTH/DMA_DATA_WIDTH; + localparam DAC_ADDRESS_WIDTH = 4; + localparam DMA_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_ADDRESS_WIDTH : + (MEM_RATIO == 2) ? ((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 1) : (DAC_ADDRESS_WIDTH + 1)) : + (MEM_RATIO == 4) ? ((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 2) : (DAC_ADDRESS_WIDTH + 2)) : + ((DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? (DAC_ADDRESS_WIDTH - 3) : (DAC_ADDRESS_WIDTH + 3)); + localparam DMA_BUF_THRESHOLD_HI = {(DMA_ADDRESS_WIDTH){1'b1}} - 4; + localparam DAC_BUF_THRESHOLD_LO = 4; + + reg [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr = 'd0; + reg [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr_g = 'd0; + reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr = 'd0; + reg [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr_g = 'd0; + reg dac_mem_rea = 1'b0; + reg dma_rst_m1 = 1'b0; + reg dma_rst = 1'b0; + reg [DMA_ADDRESS_WIDTH-1:0] dma_mem_addr_diff = 'd0; + reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m1 = 'd0; + reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2 = 'd0; + reg [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr = 'd0; + reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m1 = 'd0; + reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2 = 'd0; + reg [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr = 'd0; + + // internal signals + + wire [(DMA_ADDRESS_WIDTH-1):0] dma_mem_raddr_s; + wire [(DAC_ADDRESS_WIDTH-1):0] dac_mem_waddr_s; + wire dma_mem_wea_s; + wire dac_mem_rea_s; + wire [(DAC_DATA_WIDTH-1):0] dac_mem_rdata_s; + wire [DMA_ADDRESS_WIDTH:0] dma_address_diff_s; + wire dac_mem_empty_s; + + wire [(DMA_ADDRESS_WIDTH-1):0] dma_mem_waddr_b2g_s; + wire [(DAC_ADDRESS_WIDTH-1):0] dac_mem_raddr_b2g_s; + wire [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2_g2b_s; + wire [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2_g2b_s; + + // an asymmetric memory, storage element of the FIFO + + ad_mem_asym #( + .A_ADDRESS_WIDTH (DMA_ADDRESS_WIDTH), + .A_DATA_WIDTH (DMA_DATA_WIDTH), + .B_ADDRESS_WIDTH (DAC_ADDRESS_WIDTH), + .B_DATA_WIDTH (DAC_DATA_WIDTH) + ) i_mem_asym ( + .clka (dma_clk), + .wea (dma_mem_wea_s), + .addra (dma_mem_waddr), + .dina (dma_data), + .clkb (dac_clk), + .reb (1'b1), + .addrb (dac_mem_raddr), + .doutb (dac_mem_rdata_s)); + + // DMA reset is brought from dac domain + + always @(posedge dma_clk) begin + dma_rst_m1 <= dac_rst; + dma_rst <= dma_rst_m1; + end + + // write address generation for the asymmetric FIFO + + assign dma_mem_wea_s = dma_valid & dma_ready; + + always @(posedge dma_clk) begin + if (dma_rst == 1'b1) begin + dma_mem_waddr <= 'h0; + dma_mem_waddr_g <= 'h0; + end else begin + if (dma_mem_wea_s == 1'b1) begin + dma_mem_waddr <= dma_mem_waddr + 1'b1; + end + dma_mem_waddr_g <= dma_mem_waddr_b2g_s; + end + end + + ad_b2g #( + .DATA_WIDTH (DMA_ADDRESS_WIDTH) + ) i_dma_mem_waddr_b2g ( + .din (dma_mem_waddr), + .dout (dma_mem_waddr_b2g_s)); + + // FIFO request data until reaches the high threshold. + + always @(posedge dma_clk) begin + if (dma_rst == 1'b1) begin + dma_mem_addr_diff <= 'b0; + dma_mem_raddr_m1 <= 'b0; + dma_mem_raddr_m2 <= 'b0; + dma_mem_raddr <= 'b0; + dma_ready_out <= 1'b0; + end else begin + dma_mem_raddr_m1 <= dac_mem_raddr_g; + dma_mem_raddr_m2 <= dma_mem_raddr_m1; + dma_mem_raddr <= dma_mem_raddr_m2_g2b_s; + dma_mem_addr_diff <= dma_address_diff_s[DMA_ADDRESS_WIDTH-1:0]; + if (dma_mem_addr_diff >= DMA_BUF_THRESHOLD_HI) begin + dma_ready_out <= 1'b0; + end else begin + dma_ready_out <= 1'b1; + end + end + end + + ad_g2b #( + .DATA_WIDTH (DAC_ADDRESS_WIDTH) + ) i_dma_mem_raddr_g2b ( + .din (dma_mem_raddr_m2), + .dout (dma_mem_raddr_m2_g2b_s)); + + // relative address offset on DMA domain + assign dma_address_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s; + assign dma_mem_raddr_s = (DMA_DATA_WIDTH>DAC_DATA_WIDTH) ? + ((MEM_RATIO == 1) ? (dma_mem_raddr) : + (MEM_RATIO == 2) ? (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):1]) : + (MEM_RATIO == 4) ? (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):2]) : (dma_mem_raddr[(DAC_ADDRESS_WIDTH-1):3])) : + ((MEM_RATIO == 1) ? (dma_mem_raddr) : + (MEM_RATIO == 2) ? ({dma_mem_raddr, 1'b0}) : + (MEM_RATIO == 4) ? ({dma_mem_raddr, 2'b0}) : ({dma_mem_raddr, 3'b0})); + + // relative address offset on DAC domain + assign dac_mem_waddr_s = (DAC_DATA_WIDTH>DMA_DATA_WIDTH) ? + ((MEM_RATIO == 1) ? (dac_mem_waddr) : + (MEM_RATIO == 2) ? (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):1]) : + (MEM_RATIO == 4) ? (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):2]) : (dac_mem_waddr[(DMA_ADDRESS_WIDTH-1):3])) : + ((MEM_RATIO == 1) ? (dac_mem_waddr) : + (MEM_RATIO == 2) ? ({dac_mem_waddr, 1'b0}) : + (MEM_RATIO == 4) ? ({dac_mem_waddr, 2'b0}) : ({dac_mem_waddr, 3'b0})); + + assign dac_mem_empty_s = (dac_mem_waddr_s == dac_mem_raddr) ? 1'b1 : 1'b0; + assign dac_mem_rea_s = dac_valid & !dac_mem_empty_s; + + always @(posedge dac_clk) begin + if (dac_rst == 1'b1) begin + dac_mem_raddr <= 'h0; + dac_mem_raddr_g <= 'h0; + end else begin + if (dac_mem_rea_s == 1'b1) begin + dac_mem_raddr <= dac_mem_raddr + 1'b1; + end + dac_mem_raddr_g <= dac_mem_raddr_b2g_s; + end + end + + // compensate the read latency of the memory + always @(posedge dac_clk) begin + dac_mem_rea <= dac_mem_rea_s; + end + + ad_b2g #( + .DATA_WIDTH (DAC_ADDRESS_WIDTH) + ) i_dac_mem_raddr_b2g ( + .din (dac_mem_raddr), + .dout (dac_mem_raddr_b2g_s)); + + // transfer the write address into the DAC's clock domain + + always @(posedge dac_clk) begin + if (dac_rst == 1'b1) begin + dac_mem_waddr_m1 <= 'b0; + dac_mem_waddr_m2 <= 'b0; + dac_mem_waddr <= 'b0; + end else begin + dac_mem_waddr_m1 <= dma_mem_waddr_g; + dac_mem_waddr_m2 <= dac_mem_waddr_m1; + dac_mem_waddr <= dac_mem_waddr_m2_g2b_s; + end + end + + ad_g2b #( + .DATA_WIDTH (DMA_ADDRESS_WIDTH) + ) i_dac_mem_waddr_g2b ( + .din (dac_mem_waddr_m2), + .dout (dac_mem_waddr_m2_g2b_s)); + + // define underflow + + always @(posedge dac_clk) begin + if (dac_rst == 1'b1) begin + dac_dunf <= 1'b0; + end else begin + if (dac_valid == 1'b1) begin + dac_dunf <= dac_mem_empty_s; + end + end + end + + // DAC data output logic - make sure that the data output is zero between + // transfers + + always @(posedge dac_clk) begin + if (dac_dunf == 1'b1) begin + dac_data <= 0; + end else begin + dac_data <= dac_mem_rdata_s; + end + end + +endmodule diff --git a/adi_library/util_dacfifo/util_dacfifo_constr.sdc b/adi_library/util_dacfifo/util_dacfifo_constr.sdc new file mode 100644 index 00000000..e0c34f42 --- /dev/null +++ b/adi_library/util_dacfifo/util_dacfifo_constr.sdc @@ -0,0 +1,19 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_false_path -to [get_registers *dac_bypass_m1*] +set_false_path -to [get_registers *dma_bypass_m1*] + +set_false_path -from [get_registers *dac_raddr_g*] -to [get_registers *dma_raddr_m1*] +set_false_path -from [get_registers *dma_waddr_g*] -to [get_registers *dac_waddr_m1*] +set_false_path -from [get_registers *dma_lastaddr_g*] -to [get_registers *dac_lastaddr_m1*] +set_false_path -from [get_registers *dma_xfer_out_fifo*] -to [get_registers *dac_xfer_out_fifo_m1*] + +set_false_path -from [get_registers *dma_mem_waddr_g*] -to [get_registers *dac_mem_waddr_m1*] +set_false_path -from [get_registers *dac_mem_raddr_g*] -to [get_registers *dma_mem_raddr_m1*] +set_false_path -to [get_registers *dma_rst_m1*] +set_false_path -to [get_registers *dac_xfer_req_m1*] + + diff --git a/adi_library/util_dacfifo/util_dacfifo_constr.xdc b/adi_library/util_dacfifo/util_dacfifo_constr.xdc new file mode 100644 index 00000000..8634b10a --- /dev/null +++ b/adi_library/util_dacfifo/util_dacfifo_constr.xdc @@ -0,0 +1,36 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property ASYNC_REG TRUE [get_cells -hierarchical -filter {name =~ *dac_waddr_m*}] \ + [get_cells -hierarchical -filter {name =~ *dac_lastaddr_m*}] \ + [get_cells -hierarchical -filter {name =~ *dac_xfer_out_*}] \ + [get_cells -hierarchical -filter {name =~ *dma_bypass*}] \ + [get_cells -hierarchical -filter {name =~ *dac_bypass*}] \ + [get_cells -hierarchical -filter {name =~ *dac_xfer_req_m*}] + +set_false_path -from [get_cells -hierarchical -filter {name =~ *dma_waddr_g* && IS_SEQUENTIAL}] \ + -to [get_cells -hierarchical -filter {name =~ *dac_waddr_m1* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hierarchical -filter {name =~ *dma_lastaddr_g* && IS_SEQUENTIAL}] \ + -to [get_cells -hierarchical -filter {name =~ *dac_lastaddr_m1* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hierarchical -filter {name =~ *dma_xfer_out_fifo* && IS_SEQUENTIAL}] \ + -to [get_cells -hierarchical -filter {name =~ *dac_xfer_out_fifo_m1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hierarchical -filter {name =~ *dac_bypass_m1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hierarchical -filter {name =~ *dma_bypass_m1* && IS_SEQUENTIAL}] + +# util_dacfifo_bypass CDC false-paths + +set_property ASYNC_REG TRUE [get_cells -hierarchical -filter {name =~ *dac_mem_*_m*}] \ + [get_cells -hierarchical -filter {name =~ *dma_mem_*_m*}] \ + [get_cells -hierarchical -filter {name =~ *dma_rst_m1*}] \ + +set_false_path -from [get_cells -hierarchical -filter {name =~ */dma_mem_waddr_g* && IS_SEQUENTIAL}] \ + -to [get_cells -hierarchical -filter {name =~ */dac_mem_waddr_m1* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hierarchical -filter {name =~ */dac_mem_raddr_g* && IS_SEQUENTIAL}] \ + -to [get_cells -hierarchical -filter {name =~ */dma_mem_raddr_m1* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hierarchical -filter {name =~ */dma_rst_m1_reg && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hierarchical -filter {name =~ */dac_xfer_req_m1_reg && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hierarchical -filter {name =~ */dma_xfer_req* && IS_SEQUENTIAL}] \ + -to [get_cells -hierarchical -filter {name =~ */dac_mem_waddr_m1* && IS_SEQUENTIAL}] + diff --git a/adi_library/util_dacfifo/util_dacfifo_hw.tcl b/adi_library/util_dacfifo/util_dacfifo_hw.tcl new file mode 100644 index 00000000..bb338219 --- /dev/null +++ b/adi_library/util_dacfifo/util_dacfifo_hw.tcl @@ -0,0 +1,48 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +source ../../scripts/adi_env.tcl +source ../scripts/adi_ip_intel.tcl + +ad_ip_create util_dacfifo {UTIL DAC FIFO Interface} +ad_ip_files util_dacfifo [list\ + $ad_hdl_dir/library/common/ad_mem.v \ + $ad_hdl_dir/library/common/ad_mem_asym.v \ + $ad_hdl_dir/library/common/ad_b2g.v \ + $ad_hdl_dir/library/common/ad_g2b.v \ + util_dacfifo.v \ + util_dacfifo_bypass.v \ + util_dacfifo_constr.sdc] + +# parameters + +ad_ip_parameter DEVICE_FAMILY STRING {Arria 10} +ad_ip_parameter ADDRESS_WIDTH INTEGER 6 +ad_ip_parameter DATA_WIDTH INTEGER 128 + +# interfaces + +ad_interface clock dma_clk input 1 clk +ad_interface reset dma_rst input 1 if_dma_clk +ad_interface signal dma_xfer_req input 1 xfer_req + +add_interface s_axis axi4stream end +set_interface_property s_axis associatedClock if_dma_clk +set_interface_property s_axis associatedReset if_dma_rst +add_interface_port s_axis dma_valid tvalid Input 1 +add_interface_port s_axis dma_xfer_last tlast Input 1 +add_interface_port s_axis dma_ready tready Output 1 +add_interface_port s_axis dma_data tdata Input DATA_WIDTH + +ad_interface clock dac_clk input 1 +ad_interface reset dac_rst input 1 if_dac_clk +ad_interface signal dac_valid input 1 valid +ad_interface signal dac_data output DATA_WIDTH data +ad_interface signal dac_xfer_out output 1 xfer_req +ad_interface signal dac_dunf output 1 unf + +ad_interface signal bypass input 1 bypass + diff --git a/adi_library/util_dacfifo/util_dacfifo_ip.tcl b/adi_library/util_dacfifo/util_dacfifo_ip.tcl new file mode 100644 index 00000000..84441756 --- /dev/null +++ b/adi_library/util_dacfifo/util_dacfifo_ip.tcl @@ -0,0 +1,32 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_dacfifo +adi_ip_files util_dacfifo [list \ + "$ad_hdl_dir/library/common/ad_mem.v" \ + "$ad_hdl_dir/library/common/ad_mem_asym.v" \ + "$ad_hdl_dir/library/common/ad_b2g.v" \ + "$ad_hdl_dir/library/common/ad_g2b.v" \ + "util_dacfifo.v" \ + "util_dacfifo_bypass.v" \ + "util_dacfifo_ooc.ttcl" \ + "util_dacfifo_constr.xdc"] + + +adi_ip_properties_lite util_dacfifo + +adi_ip_ttcl util_dacfifo "util_dacfifo_ooc.ttcl" + +ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface dma_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/util_dacfifo/util_dacfifo_ooc.ttcl b/adi_library/util_dacfifo/util_dacfifo_ooc.ttcl new file mode 100644 index 00000000..1baad712 --- /dev/null +++ b/adi_library/util_dacfifo/util_dacfifo_ooc.ttcl @@ -0,0 +1,21 @@ +############################################################################### +## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +<: setFileUsedIn { out_of_context synthesis implementation } :> +<: ;#Component and file information :> +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName $ComponentName :> +<: setFileExtension "_ooc.xdc" :> + +# This XDC is used only for OOC mode of synthesis, implementation. +# These are default values for timing driven synthesis during OOC flow. +# These values will be overwritten during implementation with information +# from top level. + +create_clock -name dma_clk -period 8 [get_ports dma_clk] +create_clock -name dac_clk -period 3.2 [get_ports dac_clk] + +################################################################################ diff --git a/adi_library/util_dacfifo/xgui/util_dacfifo_v1_0.tcl b/adi_library/util_dacfifo/xgui/util_dacfifo_v1_0.tcl new file mode 100644 index 00000000..e0467965 --- /dev/null +++ b/adi_library/util_dacfifo/xgui/util_dacfifo_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ADDRESS_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } { + # Procedure called to update ADDRESS_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } { + # Procedure called to validate ADDRESS_WIDTH + return true +} + +proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to validate DATA_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.ADDRESS_WIDTH { MODELPARAM_VALUE.ADDRESS_WIDTH PARAM_VALUE.ADDRESS_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADDRESS_WIDTH}] ${MODELPARAM_VALUE.ADDRESS_WIDTH} +} + +proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} +} + diff --git a/adi_library/util_dec256sinc24b/Makefile b/adi_library/util_dec256sinc24b/Makefile new file mode 100644 index 00000000..7eeb00a8 --- /dev/null +++ b/adi_library/util_dec256sinc24b/Makefile @@ -0,0 +1,13 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_dec256sinc24b + +GENERIC_DEPS += ../common/util_dec256sinc24b.v + +XILINX_DEPS += util_dec256sinc24b_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/util_dec256sinc24b/component.xml b/adi_library/util_dec256sinc24b/component.xml new file mode 100644 index 00000000..327f845c --- /dev/null +++ b/adi_library/util_dec256sinc24b/component.xml @@ -0,0 +1,265 @@ + + + analog.com + user + util_dec256sinc24b + 1.0 + + + clk + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_RESET + reset + + + + + reset + + + + + + + RST + + + reset + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_dec256sinc24b + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 82712b89 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_dec256sinc24b + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 82712b89 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f92e9879 + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + reset + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_out + + out + + 15 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_en + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dec_rate + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../common/util_dec256sinc24b.v + verilogSource + CHECKSUM_82712b89 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/util_dec256sinc24b.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/util_dec256sinc24b_v1_0.tcl + tclSource + CHECKSUM_f92e9879 + XGUI_VERSION_2 + + + + util_dec256sinc24b_v1_0 + + + Component_Name + util_dec256sinc24b_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + util_dec256sinc24b_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:54:12Z + + + 2023.2.1 + + + + + + diff --git a/adi_library/util_dec256sinc24b/util_dec256sinc24b.xpr b/adi_library/util_dec256sinc24b/util_dec256sinc24b.xpr new file mode 100644 index 00000000..c1026e09 --- /dev/null +++ b/adi_library/util_dec256sinc24b/util_dec256sinc24b.xpr @@ -0,0 +1,399 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_dec256sinc24b/util_dec256sinc24b_ip.tcl b/adi_library/util_dec256sinc24b/util_dec256sinc24b_ip.tcl new file mode 100644 index 00000000..cbdb869f --- /dev/null +++ b/adi_library/util_dec256sinc24b/util_dec256sinc24b_ip.tcl @@ -0,0 +1,20 @@ +############################################################################### +## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_dec256sinc24b +adi_ip_files util_dec256sinc24b [list \ + "$ad_hdl_dir/library/common/util_dec256sinc24b.v"] + +adi_ip_properties_lite util_dec256sinc24b +ipx::remove_all_bus_interface [ipx::current_core] + +ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/util_dec256sinc24b/xgui/util_dec256sinc24b_v1_0.tcl b/adi_library/util_dec256sinc24b/xgui/util_dec256sinc24b_v1_0.tcl new file mode 100644 index 00000000..0db18e9a --- /dev/null +++ b/adi_library/util_dec256sinc24b/xgui/util_dec256sinc24b_v1_0.tcl @@ -0,0 +1,10 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + + diff --git a/adi_library/util_delay/Makefile b/adi_library/util_delay/Makefile new file mode 100644 index 00000000..dfe733f0 --- /dev/null +++ b/adi_library/util_delay/Makefile @@ -0,0 +1,13 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_delay + +GENERIC_DEPS += ../common/util_delay.v + +XILINX_DEPS += util_delay_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/util_delay/component.xml b/adi_library/util_delay/component.xml new file mode 100644 index 00000000..cda22d21 --- /dev/null +++ b/adi_library/util_delay/component.xml @@ -0,0 +1,258 @@ + + + analog.com + user + util_delay + 1.0 + + + clk + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_RESET + reset + + + + + reset + + + + + + + RST + + + reset + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_delay + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 18c36dfa + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_delay + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 18c36dfa + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + b1d00148 + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + reset + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + din + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dout + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + DATA_WIDTH + Data Width + 1 + + + DELAY_CYCLES + Delay Cycles + 1 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../common/util_delay.v + verilogSource + CHECKSUM_18c36dfa + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/util_delay.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/util_delay_v1_0.tcl + tclSource + CHECKSUM_b1d00148 + XGUI_VERSION_2 + + + + util_delay_v1_0 + + + DATA_WIDTH + Data Width + 1 + + + DELAY_CYCLES + Delay Cycles + 1 + + + Component_Name + util_delay_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + util_delay_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:54:23Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_delay/util_delay.xpr b/adi_library/util_delay/util_delay.xpr new file mode 100644 index 00000000..6895d2ff --- /dev/null +++ b/adi_library/util_delay/util_delay.xpr @@ -0,0 +1,399 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_delay/util_delay_ip.tcl b/adi_library/util_delay/util_delay_ip.tcl new file mode 100644 index 00000000..17100bc7 --- /dev/null +++ b/adi_library/util_delay/util_delay_ip.tcl @@ -0,0 +1,21 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_delay +adi_ip_files util_delay [list \ + "$ad_hdl_dir/library/common/util_delay.v"] + +adi_ip_properties_lite util_delay +ipx::remove_all_bus_interface [ipx::current_core] + +ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +set_property value_validation_range_minimum 1 [ipx::get_user_parameters DELAY_CYCLES -of_objects [ipx::current_core]] + +ipx::save_core [ipx::current_core] diff --git a/adi_library/util_delay/xgui/util_delay_v1_0.tcl b/adi_library/util_delay/xgui/util_delay_v1_0.tcl new file mode 100644 index 00000000..bf62b732 --- /dev/null +++ b/adi_library/util_delay/xgui/util_delay_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "DELAY_CYCLES" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to validate DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.DELAY_CYCLES { PARAM_VALUE.DELAY_CYCLES } { + # Procedure called to update DELAY_CYCLES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DELAY_CYCLES { PARAM_VALUE.DELAY_CYCLES } { + # Procedure called to validate DELAY_CYCLES + return true +} + + +proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.DELAY_CYCLES { MODELPARAM_VALUE.DELAY_CYCLES PARAM_VALUE.DELAY_CYCLES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DELAY_CYCLES}] ${MODELPARAM_VALUE.DELAY_CYCLES} +} + diff --git a/adi_library/util_do_ram/Makefile b/adi_library/util_do_ram/Makefile new file mode 100644 index 00000000..ccfb6b49 --- /dev/null +++ b/adi_library/util_do_ram/Makefile @@ -0,0 +1,21 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_do_ram + +GENERIC_DEPS += ../common/ad_mem_asym.v +GENERIC_DEPS += util_do_ram.v + +XILINX_DEPS += util_do_ram_constr.xdc +XILINX_DEPS += util_do_ram_ip.tcl +XILINX_DEPS += util_do_ram_ooc.ttcl + +XILINX_DEPS += ../interfaces/if_do_ctrl.xml +XILINX_DEPS += ../interfaces/if_do_ctrl_rtl.xml + +XILINX_INTERFACE_DEPS += interfaces + +include ../scripts/library.mk diff --git a/adi_library/util_do_ram/component.xml b/adi_library/util_do_ram/component.xml new file mode 100644 index 00000000..4b7590b1 --- /dev/null +++ b/adi_library/util_do_ram/component.xml @@ -0,0 +1,1012 @@ + + + analog.com + user + util_do_ram + 1.0 + + + s_axis + + + + + + + TREADY + + + s_axis_ready + + + + + TVALID + + + s_axis_valid + + + + + TDATA + + + s_axis_data + + + + + TSTRB + + + s_axis_strb + + + + + TKEEP + + + s_axis_keep + + + + + TUSER + + + s_axis_user + + + + + TLAST + + + s_axis_last + + + + + + m_axis + + + + + + + TREADY + + + m_axis_ready + + + + + TVALID + + + m_axis_valid + + + + + TDATA + + + m_axis_data + + + + + TSTRB + + + m_axis_strb + + + + + TKEEP + + + m_axis_keep + + + + + TUSER + + + m_axis_user + + + + + TLAST + + + m_axis_last + + + + + + wr_ctrl + + + + + + + request_enable + + + wr_request_enable + + + + + request_valid + + + wr_request_valid + + + + + request_ready + + + wr_request_ready + + + + + request_length + + + wr_request_length + + + + + response_measured_length + + + wr_response_measured_length + + + + + response_eot + + + wr_response_eot + + + + + + rd_ctrl + + + + + + + request_enable + + + rd_request_enable + + + + + request_valid + + + rd_request_valid + + + + + request_ready + + + rd_request_ready + + + + + request_length + + + rd_request_length + + + + + response_eot + + + rd_response_eot + + + + + + s_axis_wr_ctrl_signal_clock + s_axis_wr_ctrl_signal_clock + + + + + + + CLK + + + s_axis_aclk + + + + + + ASSOCIATED_BUSIF + s_axis:wr_ctrl + + + ASSOCIATED_RESET + s_axis_aresetn + + + + + s_axis_wr_ctrl_signal_reset + s_axis_wr_ctrl_signal_reset + + + + + + + RST + + + s_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + m_axis_rd_ctrl_signal_clock + m_axis_rd_ctrl_signal_clock + + + + + + + CLK + + + m_axis_aclk + + + + + + ASSOCIATED_BUSIF + m_axis:rd_ctrl + + + ASSOCIATED_RESET + m_axis_aresetn + + + + + m_axis_rd_ctrl_signal_reset + m_axis_rd_ctrl_signal_reset + + + + + + + RST + + + m_axis_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_do_ram + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_analog_com_user_util_axis_fifo_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + f913396f + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_do_ram + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_axis_fifo_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + f913396f + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_xpgui_analog_com_user_util_axis_fifo_1_0__ref_view_fileset + + + xilinx_xpgui_view_fileset + + + + viewChecksum + 770a1483 + + + + + + + wr_request_enable + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + wr_request_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + wr_request_ready + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + wr_request_length + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + wr_response_measured_length + + out + + 15 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x00000000 + + + + + wr_response_eot + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + rd_request_enable + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rd_request_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rd_request_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rd_request_length + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rd_response_eot + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_ready + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0x0 + + + + + s_axis_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_data + + in + + 511 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axis_strb + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_keep + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_user + + in + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_last + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_ready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_data + + out + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_strb + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_keep + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_user + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_axis_last + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + SRC_DATA_WIDTH + Src Data Width + 512 + + + DST_DATA_WIDTH + Dst Data Width + 128 + + + LENGTH_WIDTH + Length Width + 16 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + util_do_ram_ooc.ttcl + ttcl + + + util_do_ram_constr.xdc + xdc + + processing_order + late + + + + ../common/ad_mem_asym.v + verilogSource + + + util_do_ram.v + verilogSource + CHECKSUM_94f67d2d + + + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_analog_com_user_util_axis_fifo_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_mem_asym.v + verilogSource + + + util_do_ram.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_axis_fifo_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/util_do_ram_v1_0.tcl + tclSource + CHECKSUM_770a1483 + XGUI_VERSION_2 + + + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + xilinx_xpgui_analog_com_user_util_axis_fifo_1_0__ref_view_fileset + + + + + + + + Serves as storage for the Data Offload core, using Block RAM or URAM + + + SRC_DATA_WIDTH + Src Data Width + 512 + + + DST_DATA_WIDTH + Dst Data Width + 128 + + + LENGTH_WIDTH + Length Width + 16 + + + Component_Name + util_do_ram_v1_0 + + + + + + virtex7 + + + /Analog_Devices + + ADI Data Offload RAM Storage + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:54:37Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_do_ram/util_do_ram.v b/adi_library/util_do_ram/util_do_ram.v new file mode 100644 index 00000000..6e91233b --- /dev/null +++ b/adi_library/util_do_ram/util_do_ram.v @@ -0,0 +1,284 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +// Constraints: + +`timescale 1ns/100ps + +module util_do_ram #( + parameter SRC_DATA_WIDTH = 512, + parameter DST_DATA_WIDTH = 128, + + parameter LENGTH_WIDTH = 16 +) ( + input wr_request_enable, + input wr_request_valid, + output reg wr_request_ready = 1'b0, + input [LENGTH_WIDTH-1:0] wr_request_length, + output reg [LENGTH_WIDTH-1:0] wr_response_measured_length = 'h0, + output reg wr_response_eot = 1'b0, + + input rd_request_enable, + input rd_request_valid, + output rd_request_ready, + input [LENGTH_WIDTH-1:0] rd_request_length, + output rd_response_eot, + + // Slave streaming AXI interface + input s_axis_aclk, + input s_axis_aresetn, + output reg s_axis_ready = 1'b0, + input s_axis_valid, + input [SRC_DATA_WIDTH-1:0] s_axis_data, + input [SRC_DATA_WIDTH/8-1:0] s_axis_strb, + input [SRC_DATA_WIDTH/8-1:0] s_axis_keep, + input [0:0] s_axis_user, + input s_axis_last, + + // Master streaming AXI interface + input m_axis_aclk, + input m_axis_aresetn, + input m_axis_ready, + output m_axis_valid, + output [DST_DATA_WIDTH-1:0] m_axis_data, + output [DST_DATA_WIDTH/8-1:0] m_axis_strb, + output [DST_DATA_WIDTH/8-1:0] m_axis_keep, + output [0:0] m_axis_user, + output m_axis_last +); + + // src = s_axis_* = wr + // dst = m_axis_* = rd + // + + localparam RAM_LATENCY = 2; + + localparam SRC_ADDR_ALIGN = $clog2(SRC_DATA_WIDTH/8); + localparam DST_ADDR_ALIGN = $clog2(DST_DATA_WIDTH/8); + + localparam SRC_ADDRESS_WIDTH = LENGTH_WIDTH - SRC_ADDR_ALIGN; + localparam DST_ADDRESS_WIDTH = LENGTH_WIDTH - DST_ADDR_ALIGN; + + wire wr_enable; + wire [DST_DATA_WIDTH-1:0] rd_data; + wire [1:0] rd_fifo_room; + wire rd_enable; + wire rd_last_beat; + wire rd_fifo_s_ready; + wire rd_fifo_s_valid; + + reg [SRC_ADDRESS_WIDTH-1:0] wr_length = 'h0; + reg [SRC_ADDRESS_WIDTH-1:0] wr_addr = 'h0; + reg [DST_DATA_WIDTH-1:0] rd_data_l2 = 'h0; + reg [DST_ADDRESS_WIDTH-1:0] rd_length = 'h0; + reg [DST_ADDRESS_WIDTH-1:0] rd_addr = 'h0; + reg rd_pending = 1'b0; + + always @(posedge s_axis_aclk) begin + if (~s_axis_aresetn) + wr_request_ready <= 1'b1; + else if (wr_request_valid) + wr_request_ready <= 1'b0; + else if (wr_response_eot) + wr_request_ready <= 1'b1; + end + + always @(posedge s_axis_aclk) begin + if (wr_request_valid & wr_request_ready) + wr_length <= wr_request_length[LENGTH_WIDTH-1:SRC_ADDR_ALIGN]; + end + + wire wr_last_beat; + assign wr_last_beat = s_axis_valid & s_axis_ready & ((wr_addr == wr_length) | s_axis_last); + + always @(posedge s_axis_aclk) begin + if (~wr_request_enable) + s_axis_ready <= 1'b0; + else if (wr_request_valid & wr_request_ready) + s_axis_ready <= 1'b1; + else if (wr_last_beat) begin + s_axis_ready <= 1'b0; + end + end + + always @(posedge s_axis_aclk) begin + if (s_axis_valid & s_axis_ready) + wr_response_eot <= s_axis_last | (wr_addr == wr_length); + else + wr_response_eot <= 1'b0; + end + + always @(posedge s_axis_aclk) begin + if (wr_last_beat) + wr_response_measured_length <= {wr_addr, {SRC_ADDR_ALIGN{1'b1}}}; + end + + reg wr_full = 1'b0; + // Protect against larger transfers than storage + always @(posedge s_axis_aclk) begin + if (wr_request_valid & wr_request_ready) + wr_full <= 1'b0; + else if (&wr_addr & (s_axis_valid & s_axis_ready)) + wr_full <= 1'b1; + end + + // Do not roll over write address + always @(posedge s_axis_aclk) begin + if (~wr_request_enable | wr_last_beat) + wr_addr <= 'h0; + else if (s_axis_valid & s_axis_ready & (~(&wr_addr))) + wr_addr <= wr_addr + 1; + end + assign wr_enable = s_axis_valid & s_axis_ready & ~wr_full; + + ad_mem_asym #( + .A_ADDRESS_WIDTH (SRC_ADDRESS_WIDTH), + .A_DATA_WIDTH (SRC_DATA_WIDTH), + .B_ADDRESS_WIDTH (DST_ADDRESS_WIDTH), + .B_DATA_WIDTH (DST_DATA_WIDTH) + ) i_mem ( + .clka (s_axis_aclk), + .wea (wr_enable), + .addra (wr_addr), + .dina (s_axis_data), + + .clkb (m_axis_aclk), + .reb (1'b1), + .addrb (rd_addr), + .doutb (rd_data)); + + reg rd_active = 1'b0; + reg [1:0] rd_req_cnt = 2'b0; + always @(posedge m_axis_aclk) begin + if (~rd_request_enable) + rd_req_cnt <= 2'b0; + else if (rd_request_valid & rd_request_ready) + rd_req_cnt <= rd_req_cnt + 2'b1; + else if (rd_response_eot) + rd_req_cnt <= rd_req_cnt - 2'b1; + end + + assign rd_request_ready = ~rd_req_cnt[1]; + + always @(posedge m_axis_aclk) begin + if (rd_request_valid & rd_request_ready) + rd_length <= rd_request_length[LENGTH_WIDTH-1:DST_ADDR_ALIGN]; + end + + wire rd_early_finish; + + assign rd_early_finish = rd_active & ~rd_request_enable; + assign rd_last_beat = (rd_addr == rd_length) & rd_enable; + assign rd_response_eot = (m_axis_last & m_axis_valid & m_axis_ready) || rd_early_finish; + + // Read logic + always @(posedge m_axis_aclk) begin + if (~rd_request_enable) + rd_active <= 1'b0; + else if (rd_request_valid & rd_request_ready) + rd_active <= 1'b1; + else if (rd_last_beat) + rd_active <= rd_req_cnt == 2; + end + + assign rd_enable = rd_fifo_s_ready & rd_active & + (rd_fifo_room >= (m_axis_valid&m_axis_ready ? 1 : RAM_LATENCY)); + + always @(posedge m_axis_aclk) begin + if (~rd_request_enable | rd_last_beat) + rd_addr <= 'h0; + else if (rd_enable) + rd_addr <= rd_addr + 1; + end + + // Delay read enable with latency cycles + // make this depend on parameter + reg rd_valid_l1 = 1'b0; + reg rd_valid_l2 = 1'b0; + reg rd_last_l1 = 1'b0; + reg rd_last_l2 = 1'b0; + always @(posedge m_axis_aclk) begin + rd_valid_l1 <= rd_enable; + rd_last_l1 <= rd_last_beat; + end + + // Extra pipeline to be sucked in by the BRAM/URAM output stage + always @(posedge m_axis_aclk) begin + if (rd_valid_l1) + rd_data_l2 <= rd_data; + end + + always @(posedge m_axis_aclk) begin + if (rd_valid_l1) + rd_valid_l2 <= 1'b1; + else if (rd_fifo_s_ready) + rd_valid_l2 <= 1'b0; + + if (rd_valid_l1) + rd_last_l2 <= rd_last_l1; + end + + assign rd_fifo_s_valid = rd_valid_l2; + + // Read datapath to AXIS logic + util_axis_fifo #( + .DATA_WIDTH(DST_DATA_WIDTH+1), + .ADDRESS_WIDTH(2), + .ASYNC_CLK(0), + .M_AXIS_REGISTERED(0) + ) i_rd_fifo ( + .s_axis_aclk(m_axis_aclk), + .s_axis_aresetn(m_axis_aresetn & rd_request_enable), + .s_axis_valid(rd_fifo_s_valid), + .s_axis_ready(rd_fifo_s_ready), + .s_axis_full(), + .s_axis_data({rd_last_l2,rd_data_l2}), + .s_axis_room(rd_fifo_room), + .s_axis_tkeep(), + .s_axis_tlast(), + .s_axis_almost_full(), + + .m_axis_aclk(m_axis_aclk), + .m_axis_aresetn(m_axis_aresetn & rd_request_enable), + .m_axis_valid(m_axis_valid), + .m_axis_ready(m_axis_ready), + .m_axis_data({m_axis_last,m_axis_data}), + .m_axis_level(), + .m_axis_empty(), + .m_axis_tkeep(), + .m_axis_tlast(), + .m_axis_almost_empty()); + +endmodule diff --git a/adi_library/util_do_ram/util_do_ram.xpr b/adi_library/util_do_ram/util_do_ram.xpr new file mode 100644 index 00000000..7fd3c91d --- /dev/null +++ b/adi_library/util_do_ram/util_do_ram.xpr @@ -0,0 +1,413 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_do_ram/util_do_ram_constr.xdc b/adi_library/util_do_ram/util_do_ram_constr.xdc new file mode 100644 index 00000000..e69de29b diff --git a/adi_library/util_do_ram/util_do_ram_ip.tcl b/adi_library/util_do_ram/util_do_ram_ip.tcl new file mode 100644 index 00000000..2522a5b0 --- /dev/null +++ b/adi_library/util_do_ram/util_do_ram_ip.tcl @@ -0,0 +1,81 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_do_ram +adi_ip_files util_do_ram [list \ + "../common/ad_mem_asym.v" \ + "util_do_ram_constr.xdc" \ + "util_do_ram_ooc.ttcl" \ + "util_do_ram.v" \ +] + +adi_ip_properties_lite util_do_ram +adi_ip_ttcl util_dacfifo "util_do_ram_ooc.ttcl" + +set_property PROCESSING_ORDER LATE [ipx::get_files util_do_ram_constr.xdc \ + -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \ + -filter {NAME =~ *synthesis*}]] + +adi_ip_add_core_dependencies { \ + analog.com:user:util_cdc:1.0 \ + analog.com:user:util_axis_fifo:1.0 \ +} + +set_property display_name "ADI Data Offload RAM Storage" [ipx::current_core] +set_property description "Serves as storage for the Data Offload core, using Block RAM or URAM" [ipx::current_core] + +set cc [ipx::current_core] + +adi_add_bus "s_axis" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"s_axis_ready" "TREADY"} \ + {"s_axis_valid" "TVALID"} \ + {"s_axis_data" "TDATA"} \ + {"s_axis_strb" "TSTRB"} \ + {"s_axis_keep" "TKEEP"} \ + {"s_axis_user" "TUSER"} \ + {"s_axis_last" "TLAST"}] + +adi_add_bus "m_axis" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"m_axis_ready" "TREADY"} \ + {"m_axis_valid" "TVALID"} \ + {"m_axis_data" "TDATA"} \ + {"m_axis_strb" "TSTRB"} \ + {"m_axis_keep" "TKEEP"} \ + {"m_axis_user" "TUSER"} \ + {"m_axis_last" "TLAST"}] + +adi_add_bus "wr_ctrl" "slave" \ + "analog.com:interface:if_do_ctrl_rtl:1.0" \ + "analog.com:interface:if_do_ctrl:1.0" \ + [list {"wr_request_enable" "request_enable"} \ + {"wr_request_valid" "request_valid"} \ + {"wr_request_ready" "request_ready"} \ + {"wr_request_length" "request_length"} \ + {"wr_response_measured_length" "response_measured_length"} \ + {"wr_response_eot" "response_eot"} \ + ] + +adi_add_bus "rd_ctrl" "slave" \ + "analog.com:interface:if_do_ctrl_rtl:1.0" \ + "analog.com:interface:if_do_ctrl:1.0" \ + [list {"rd_request_enable" "request_enable"} \ + {"rd_request_valid" "request_valid"} \ + {"rd_request_ready" "request_ready"} \ + {"rd_request_length" "request_length"} \ + {"rd_response_eot" "response_eot"} \ + ] + +adi_add_bus_clock "s_axis_aclk" "s_axis:wr_ctrl" "s_axis_aresetn" +adi_add_bus_clock "m_axis_aclk" "m_axis:rd_ctrl" "m_axis_aresetn" + +ipx::create_xgui_files [ipx::current_core] +ipx::save_core [ipx::current_core] diff --git a/adi_library/util_do_ram/util_do_ram_ooc.ttcl b/adi_library/util_do_ram/util_do_ram_ooc.ttcl new file mode 100644 index 00000000..b4034dff --- /dev/null +++ b/adi_library/util_do_ram/util_do_ram_ooc.ttcl @@ -0,0 +1,19 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +<: setFileUsedIn { out_of_context synthesis implementation } :> +<: ;#Component and file information :> +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName $ComponentName :> +<: setFileExtension "_ooc.xdc" :> + +# This XDC is used only for OOC mode of synthesis, implementation. +# These are default values for timing driven synthesis during OOC flow. +# These values will be overwritten during implementation with information +# from top level. + +create_clock -name s_axis_aclk -period 2.5 [get_ports s_axis_aclk] +create_clock -name m_axis_aclk -period 2.5 [get_ports m_axis_aclk] diff --git a/adi_library/util_do_ram/xgui/util_do_ram_v1_0.tcl b/adi_library/util_do_ram/xgui/util_do_ram_v1_0.tcl new file mode 100644 index 00000000..4c829777 --- /dev/null +++ b/adi_library/util_do_ram/xgui/util_do_ram_v1_0.tcl @@ -0,0 +1,55 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DST_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "LENGTH_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "SRC_DATA_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DST_DATA_WIDTH { PARAM_VALUE.DST_DATA_WIDTH } { + # Procedure called to update DST_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DST_DATA_WIDTH { PARAM_VALUE.DST_DATA_WIDTH } { + # Procedure called to validate DST_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.LENGTH_WIDTH { PARAM_VALUE.LENGTH_WIDTH } { + # Procedure called to update LENGTH_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.LENGTH_WIDTH { PARAM_VALUE.LENGTH_WIDTH } { + # Procedure called to validate LENGTH_WIDTH + return true +} + +proc update_PARAM_VALUE.SRC_DATA_WIDTH { PARAM_VALUE.SRC_DATA_WIDTH } { + # Procedure called to update SRC_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SRC_DATA_WIDTH { PARAM_VALUE.SRC_DATA_WIDTH } { + # Procedure called to validate SRC_DATA_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.SRC_DATA_WIDTH { MODELPARAM_VALUE.SRC_DATA_WIDTH PARAM_VALUE.SRC_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SRC_DATA_WIDTH}] ${MODELPARAM_VALUE.SRC_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.DST_DATA_WIDTH { MODELPARAM_VALUE.DST_DATA_WIDTH PARAM_VALUE.DST_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DST_DATA_WIDTH}] ${MODELPARAM_VALUE.DST_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.LENGTH_WIDTH { MODELPARAM_VALUE.LENGTH_WIDTH PARAM_VALUE.LENGTH_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LENGTH_WIDTH}] ${MODELPARAM_VALUE.LENGTH_WIDTH} +} + diff --git a/adi_library/util_extract/Makefile b/adi_library/util_extract/Makefile new file mode 100644 index 00000000..a66d3072 --- /dev/null +++ b/adi_library/util_extract/Makefile @@ -0,0 +1,13 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_extract + +GENERIC_DEPS += util_extract.v + +XILINX_DEPS += util_extract_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/util_extract/component.xml b/adi_library/util_extract/component.xml new file mode 100644 index 00000000..a8ba3899 --- /dev/null +++ b/adi_library/util_extract/component.xml @@ -0,0 +1,283 @@ + + + analog.com + user + util_extract + 1.0 + + + clk + + + + + + + CLK + + + clk + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_extract + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 797a4514 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_extract + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 797a4514 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + cdd73d0a + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_in + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_in_trigger + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_out + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + valid_out + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + trigger_out + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + NUM_OF_CHANNELS + Num Of Channels + 2 + + + DATA_WIDTH + Data Width + 32 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + util_extract.v + verilogSource + CHECKSUM_797a4514 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + util_extract.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/util_extract_v1_0.tcl + tclSource + CHECKSUM_cdd73d0a + XGUI_VERSION_2 + + + + util_extract_v1_0 + + + NUM_OF_CHANNELS + Num Of Channels + 2 + + + DATA_WIDTH + Data Width + 32 + + + Component_Name + util_extract_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + util_extract_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/util_extract + 1 + 2024-01-14T03:54:45Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_extract/util_extract.v b/adi_library/util_extract/util_extract.v new file mode 100644 index 00000000..1058e62b --- /dev/null +++ b/adi_library/util_extract/util_extract.v @@ -0,0 +1,81 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_extract #( + + parameter NUM_OF_CHANNELS = 2, + parameter DATA_WIDTH = NUM_OF_CHANNELS * 16 +) ( + input clk, + + input [DATA_WIDTH-1:0] data_in, + input [DATA_WIDTH-1:0] data_in_trigger, + input data_valid, + + output [DATA_WIDTH-1:0] data_out, + output reg valid_out, + output reg trigger_out +); + + // loop variables + + genvar n; + + reg trigger_d1; + + wire [15:0] trigger; // 16 maximum channels + + generate + for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_data_out + assign data_out[(n+1)*16-1:n*16] = {data_in[(n*16)+14],data_in[(n*16)+14:n*16]}; + assign trigger[n] = data_in_trigger[(16*n)+15]; + end + for (n = NUM_OF_CHANNELS; n < 16; n = n + 1) begin: g_trigger_out + assign trigger[n] = 1'b0; + end + endgenerate + + // compensate delay in the FIFO + always @(posedge clk) begin + valid_out <= data_valid; + if (data_valid == 1'b1) begin + trigger_d1 <= |trigger; + trigger_out <= trigger_d1; + end + end + +endmodule diff --git a/adi_library/util_extract/util_extract.xpr b/adi_library/util_extract/util_extract.xpr new file mode 100644 index 00000000..bb6c6e8b --- /dev/null +++ b/adi_library/util_extract/util_extract.xpr @@ -0,0 +1,399 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_extract/util_extract_ip.tcl b/adi_library/util_extract/util_extract_ip.tcl new file mode 100644 index 00000000..d38b81a8 --- /dev/null +++ b/adi_library/util_extract/util_extract_ip.tcl @@ -0,0 +1,22 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_extract +adi_ip_files util_extract [list \ + "util_extract.v" ] + +adi_ip_properties_lite util_extract + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/util_extract} [ipx::current_core] + +ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] + + diff --git a/adi_library/util_extract/xgui/util_extract_v1_0.tcl b/adi_library/util_extract/xgui/util_extract_v1_0.tcl new file mode 100644 index 00000000..5d56f0bd --- /dev/null +++ b/adi_library/util_extract/xgui/util_extract_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_OF_CHANNELS" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to validate DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to update NUM_OF_CHANNELS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to validate NUM_OF_CHANNELS + return true +} + + +proc update_MODELPARAM_VALUE.NUM_OF_CHANNELS { MODELPARAM_VALUE.NUM_OF_CHANNELS PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_CHANNELS}] ${MODELPARAM_VALUE.NUM_OF_CHANNELS} +} + +proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} +} + diff --git a/adi_library/util_fir_dec/Makefile b/adi_library/util_fir_dec/Makefile new file mode 100644 index 00000000..d0ff9592 --- /dev/null +++ b/adi_library/util_fir_dec/Makefile @@ -0,0 +1,13 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_fir_dec + +GENERIC_DEPS += util_fir_dec.v + +XILINX_DEPS += util_fir_dec_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/util_fir_dec/coefile_dec.coe b/adi_library/util_fir_dec/coefile_dec.coe new file mode 100644 index 00000000..06a60396 --- /dev/null +++ b/adi_library/util_fir_dec/coefile_dec.coe @@ -0,0 +1,134 @@ +; XILINX CORE Generator(tm)Distributed Arithmetic FIR filter coefficient (.COE) File +; Generated by MATLAB(R) 9.0 and the DSP System Toolbox 9.2. +; Generated on: 24-Oct-2016 14:07:18 +Radix = 10; +Coefficient_Width = 16; +CoefData = 0, + -1, + -2, + -4, + -6, + -8, + -8, + -5, + 0, + 8, + 18, + 29, + 37, + 41, + 37, + 23, + 0, + -31, + -67, + -100, + -124, + -130, + -113, + -69, + 0, + 87, + 181, + 263, + 318, + 326, + 277, + 166, + 0, + -202, + -410, + -589, + -700, + -709, + -594, + -352, + 0, + 420, + 848, + 1211, + 1432, + 1446, + 1210, + 717, + 0, + -863, +-1756, +-2535, +-3043, +-3133, +-2690, +-1646, + 0, + 2180, + 4757, + 7534, +10278, +12743, +14697, +15951, +16384, +15951, +14697, +12743, +10278, + 7534, + 4757, + 2180, + 0, +-1646, +-2690, +-3133, +-3043, +-2535, +-1756, + -863, + 0, + 717, + 1210, + 1446, + 1432, + 1211, + 848, + 420, + 0, + -352, + -594, + -709, + -700, + -589, + -410, + -202, + 0, + 166, + 277, + 326, + 318, + 263, + 181, + 87, + 0, + -69, + -113, + -130, + -124, + -100, + -67, + -31, + 0, + 23, + 37, + 41, + 37, + 29, + 18, + 8, + 0, + -5, + -8, + -8, + -6, + -4, + -2, + -1, + 0; diff --git a/adi_library/util_fir_dec/component.xml b/adi_library/util_fir_dec/component.xml new file mode 100644 index 00000000..13371ecb --- /dev/null +++ b/adi_library/util_fir_dec/component.xml @@ -0,0 +1,278 @@ + + + analog.com + user + util_fir_dec + 1.0 + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_fir_dec + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + df87a941 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_fir_dec + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + df87a941 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f92e9879 + + + + + + + aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_data_tvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axis_data_tready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + channel_0 + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + channel_1 + + in + + 15 + 0 + + + + std_logic_vector + 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"boundary": { + "ports": { + "aclk": [ { "direction": "in" } ], + "s_axis_data_tvalid": [ { "direction": "in", "driver_value": "0x0" } ], + "s_axis_data_tready": [ { "direction": "out", "driver_value": "0x1" } ], + "s_axis_data_tdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ], + "m_axis_data_tvalid": [ { "direction": "out", "driver_value": "0x0" } ], + "m_axis_data_tdata": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ] + }, + "interfaces": { + "event_s_data_tlast_missing_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_s_data_tlast_unexpected_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_s_data_chanid_incorrect_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_s_config_tlast_missing_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_s_config_tlast_unexpected_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_s_reload_tlast_missing_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_s_reload_tlast_unexpected_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "aclk_intf": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD", "value_src": "constant", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ], + "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "aclk" } ] + } + }, + "aresetn_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "aclken_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "S_AXIS_DATA": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "slave", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "s_axis_data_tdata" } ], + "TREADY": [ { "physical_name": "s_axis_data_tready" } ], + "TVALID": [ { "physical_name": "s_axis_data_tvalid" } ] + } + }, + "M_AXIS_DATA": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "master", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "m_axis_data_tdata" } ], + "TVALID": [ { "physical_name": "m_axis_data_tvalid" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/adi_library/util_fir_dec/util_fir_dec.v b/adi_library/util_fir_dec/util_fir_dec.v new file mode 100644 index 00000000..04a68ce2 --- /dev/null +++ b/adi_library/util_fir_dec/util_fir_dec.v @@ -0,0 +1,67 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_fir_dec ( + input aclk, + input s_axis_data_tvalid, + output s_axis_data_tready, + input [15:0] channel_0, + input [15:0] channel_1, + input decimate, + output m_axis_data_tvalid, + output [31:0] m_axis_data_tdata +); + + wire [31:0] s_axis_data_tdata; + + wire m_axis_data_tvalid_s; + wire [31:0] m_axis_data_tdata_s; + + assign s_axis_data_tdata = {channel_1, channel_0}; + + assign m_axis_data_tvalid = (decimate == 1'b1) ? m_axis_data_tvalid_s : s_axis_data_tvalid; + assign m_axis_data_tdata = (decimate == 1'b1) ? {m_axis_data_tdata_s[30:16], 1'b0, m_axis_data_tdata_s[14:0], 1'b0} : {channel_1, channel_0}; + + fir_decim decimator ( + .aclk(aclk), + .s_axis_data_tvalid(s_axis_data_tvalid), + .s_axis_data_tready(s_axis_data_tready), + .s_axis_data_tdata(s_axis_data_tdata), + .m_axis_data_tvalid(m_axis_data_tvalid_s), + .m_axis_data_tdata(m_axis_data_tdata_s)); + +endmodule diff --git a/adi_library/util_fir_dec/util_fir_dec.xpr b/adi_library/util_fir_dec/util_fir_dec.xpr new file mode 100644 index 00000000..96ef415b --- /dev/null +++ b/adi_library/util_fir_dec/util_fir_dec.xpr @@ -0,0 +1,412 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_fir_dec/util_fir_dec_ip.tcl b/adi_library/util_fir_dec/util_fir_dec_ip.tcl new file mode 100644 index 00000000..f7945934 --- /dev/null +++ b/adi_library/util_fir_dec/util_fir_dec_ip.tcl @@ -0,0 +1,45 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_fir_dec + +set fir_decim [create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_decim] + set_property -dict [ list \ +CONFIG.Clock_Frequency {61.44} \ +CONFIG.CoefficientSource {COE_File} \ +CONFIG.Coefficient_File {../../../../coefile_dec.coe} \ +CONFIG.Coefficient_Fractional_Bits {0} \ +CONFIG.Data_Fractional_Bits {15} \ +CONFIG.Coefficient_Sets {1} \ +CONFIG.Coefficient_Sign {Signed} \ +CONFIG.Coefficient_Structure {Inferred} \ +CONFIG.Coefficient_Width {16} \ +CONFIG.ColumnConfig {5} \ +CONFIG.Decimation_Rate {8} \ +CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ +CONFIG.Filter_Type {Decimation} \ +CONFIG.Interpolation_Rate {1} \ +CONFIG.Number_Channels {1} \ +CONFIG.Number_Paths {2} \ +CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \ +CONFIG.Output_Width {16} \ +CONFIG.Quantization {Integer_Coefficients} \ +CONFIG.RateSpecification {Frequency_Specification} \ +CONFIG.Sample_Frequency {61.44} \ +CONFIG.Zero_Pack_Factor {1} \ + ] [get_ips fir_decim] + +generate_target {all} [get_files util_fir_dec.srcs/sources_1/ip/fir_decim/fir_decim.xci] + + +adi_ip_files util_fir_dec [list \ +"util_fir_dec.v" ] + +adi_ip_properties_lite util_fir_dec + +ipx::save_core [ipx::current_core] diff --git a/adi_library/util_fir_dec/xgui/util_fir_dec_v1_0.tcl b/adi_library/util_fir_dec/xgui/util_fir_dec_v1_0.tcl new file mode 100644 index 00000000..0db18e9a --- /dev/null +++ b/adi_library/util_fir_dec/xgui/util_fir_dec_v1_0.tcl @@ -0,0 +1,10 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + + diff --git a/adi_library/util_fir_int/Makefile b/adi_library/util_fir_int/Makefile new file mode 100644 index 00000000..98fd44c3 --- /dev/null +++ b/adi_library/util_fir_int/Makefile @@ -0,0 +1,13 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_fir_int + +GENERIC_DEPS += util_fir_int.v + +XILINX_DEPS += util_fir_int_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/util_fir_int/coefile_int.coe b/adi_library/util_fir_int/coefile_int.coe new file mode 100644 index 00000000..d7aee256 --- /dev/null +++ b/adi_library/util_fir_int/coefile_int.coe @@ -0,0 +1,134 @@ +; XILINX CORE Generator(tm)Distributed Arithmetic FIR filter coefficient (.COE) File +; Generated by MATLAB(R) 9.0 and the DSP System Toolbox 9.2. +; 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a/adi_library/util_fir_int/component.xml b/adi_library/util_fir_int/component.xml new file mode 100644 index 00000000..d7a6b09f --- /dev/null +++ b/adi_library/util_fir_int/component.xml @@ -0,0 +1,294 @@ + + + analog.com + user + util_fir_int + 1.0 + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_fir_int + + xilinx_anylanguagesynthesis_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 20812f76 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_fir_int + + xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_fir_compiler_7_2__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 20812f76 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + f92e9879 + + + + + + + aclk + + in + + + std_logic + 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"m_axis_data_tvalid": [ { "direction": "out", "driver_value": "0x0" } ], + "m_axis_data_tdata": [ { "direction": "out", "size_left": "31", "size_right": "0", "driver_value": "0" } ] + }, + "interfaces": { + "event_s_data_tlast_missing_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_s_data_tlast_unexpected_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_s_data_chanid_incorrect_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_s_config_tlast_missing_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_s_config_tlast_unexpected_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_s_reload_tlast_missing_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "event_s_reload_tlast_unexpected_intf": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ], + "PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "aclk_intf": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA:S_AXIS_RELOAD", "value_src": "constant", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ], + "ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "aclk" } ] + } + }, + "aresetn_intf": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "aclken_intf": { + "vlnv": "xilinx.com:signal:clockenable:1.0", + "abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ] + } + }, + "S_AXIS_DATA": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "slave", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TREADY": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "s_axis_data_tdata" } ], + "TREADY": [ { "physical_name": "s_axis_data_tready" } ], + "TVALID": [ { "physical_name": "s_axis_data_tvalid" } ] + } + }, + "M_AXIS_DATA": { + "vlnv": "xilinx.com:interface:axis:1.0", + "abstraction_type": "xilinx.com:interface:axis_rtl:1.0", + "mode": "master", + "parameters": { + "TDATA_NUM_BYTES": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "TDATA": [ { "physical_name": "m_axis_data_tdata" } ], + "TVALID": [ { "physical_name": "m_axis_data_tvalid" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/adi_library/util_fir_int/util_fir_int.v b/adi_library/util_fir_int/util_fir_int.v new file mode 100644 index 00000000..9ad4ab20 --- /dev/null +++ b/adi_library/util_fir_int/util_fir_int.v @@ -0,0 +1,79 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_fir_int ( + input aclk, + input s_axis_data_tvalid, + output s_axis_data_tready, + input [31:0] s_axis_data_tdata, + output [15:0] channel_0, + output [15:0] channel_1, + output m_axis_data_tvalid, + input interpolate, + input dac_read +); + + wire [31:0] m_axis_data_tdata_s; + wire s_axis_data_tvalid_s; + + reg s_axis_data_tready_r; + reg s_axis_data_tvalid_r; + reg [2:0] ready_counter; + + always @(posedge aclk) begin + ready_counter <= ready_counter + 1; + s_axis_data_tready_r <= s_axis_data_tvalid_r; + if (ready_counter == 0) begin + s_axis_data_tvalid_r <= 1'b1; + end else begin + s_axis_data_tvalid_r <= 1'b0; + end + end + + assign {channel_1, channel_0} = (interpolate == 1'b1) ? {m_axis_data_tdata_s[30:16],1'b0,m_axis_data_tdata_s[14:0], 1'b0} : s_axis_data_tdata; + assign s_axis_data_tready = (interpolate == 1'b1) ? s_axis_data_tready_r : dac_read; + assign s_axis_data_tvalid_s = (interpolate == 1'b1) ? s_axis_data_tvalid_r : s_axis_data_tvalid; + + fir_interp interpolator ( + .aclk(aclk), + .s_axis_data_tvalid(s_axis_data_tvalid_s), + .s_axis_data_tready(), + .s_axis_data_tdata(s_axis_data_tdata), + .m_axis_data_tvalid(m_axis_data_tvalid), + .m_axis_data_tdata(m_axis_data_tdata_s)); + +endmodule diff --git a/adi_library/util_fir_int/util_fir_int.xpr b/adi_library/util_fir_int/util_fir_int.xpr new file mode 100644 index 00000000..24322152 --- /dev/null +++ b/adi_library/util_fir_int/util_fir_int.xpr @@ -0,0 +1,412 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_fir_int/util_fir_int_ip.tcl b/adi_library/util_fir_int/util_fir_int_ip.tcl new file mode 100644 index 00000000..c03538bc --- /dev/null +++ b/adi_library/util_fir_int/util_fir_int_ip.tcl @@ -0,0 +1,47 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_fir_int + +set fir_interp [create_ip -name fir_compiler -vendor xilinx.com -library ip -version 7.2 -module_name fir_interp] + set_property -dict [ list \ +CONFIG.Clock_Frequency {61.44} \ +CONFIG.CoefficientSource {COE_File} \ +CONFIG.Coefficient_File {../../../../coefile_int.coe} \ +CONFIG.Coefficient_Fractional_Bits {0} \ +CONFIG.Data_Fractional_Bits {15} \ +CONFIG.Coefficient_Sets {1} \ +CONFIG.Coefficient_Sign {Signed} \ +CONFIG.S_DATA_Has_FIFO {true} \ +CONFIG.Coefficient_Structure {Inferred} \ +CONFIG.Coefficient_Width {16} \ +CONFIG.ColumnConfig {5} \ +CONFIG.Decimation_Rate {1} \ +CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \ +CONFIG.Filter_Type {Interpolation} \ +CONFIG.Interpolation_Rate {8} \ +CONFIG.M_DATA_Has_TREADY {false} \ +CONFIG.Number_Channels {1} \ +CONFIG.Number_Paths {2} \ +CONFIG.Output_Rounding_Mode {Truncate_LSBs} \ +CONFIG.Output_Width {16} \ +CONFIG.Quantization {Integer_Coefficients} \ +CONFIG.RateSpecification {Frequency_Specification} \ +CONFIG.Sample_Frequency {7.68} \ +CONFIG.Zero_Pack_Factor {1} \ + ] [get_ips fir_interp] + +generate_target {all} [get_files util_fir_int.srcs/sources_1/ip/fir_interp/fir_interp.xci] + + +adi_ip_files util_fir_int [list \ +"util_fir_int.v" ] + +adi_ip_properties_lite util_fir_int + +ipx::save_core [ipx::current_core] diff --git a/adi_library/util_fir_int/xgui/util_fir_int_v1_0.tcl b/adi_library/util_fir_int/xgui/util_fir_int_v1_0.tcl new file mode 100644 index 00000000..0db18e9a --- /dev/null +++ b/adi_library/util_fir_int/xgui/util_fir_int_v1_0.tcl @@ -0,0 +1,10 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + ipgui::add_page $IPINST -name "Page 0" + + +} + + diff --git a/adi_library/util_gmii_to_rgmii/Makefile b/adi_library/util_gmii_to_rgmii/Makefile new file mode 100644 index 00000000..3a9ac086 --- /dev/null +++ b/adi_library/util_gmii_to_rgmii/Makefile @@ -0,0 +1,15 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_gmii_to_rgmii + +GENERIC_DEPS += mdc_mdio.v +GENERIC_DEPS += util_gmii_to_rgmii.v + +XILINX_DEPS += util_gmii_to_rgmii_constr.xdc +XILINX_DEPS += util_gmii_to_rgmii_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/util_gmii_to_rgmii/component.xml b/adi_library/util_gmii_to_rgmii/component.xml new file mode 100644 index 00000000..31000c14 --- /dev/null +++ b/adi_library/util_gmii_to_rgmii/component.xml @@ -0,0 +1,783 @@ + + + analog.com + user + util_gmii_to_rgmii + 1.0 + + + gmii + + + + + + + TXD + + + gmii_txd + + + + + TX_EN + + + gmii_tx_en + + + + + TX_ER + + + gmii_tx_er + + + + + RXD + + + gmii_rxd + + + + + RX_DV + + + gmii_rx_dv + + + + + RX_ER + + + gmii_rx_er + + + + + CRS + + + gmii_crs + + + + + COL + + + gmii_col + + + + + TX_CLK + + + gmii_tx_clk + + + + + RX_CLK + + + gmii_rx_clk + + + + + + rgmii + + + + + + + TD + + + rgmii_td + + + + + TX_CTL + + + rgmii_tx_ctl + + + + + TXC + + + rgmii_txc + + + + + RD + + + rgmii_rd + + + + + RX_CTL + + + rgmii_rx_ctl + + + + + RXC + + + rgmii_rxc + + + + + + clk_20m + + + + + + + CLK + + + clk_20m + + + + + + clk_25m + + + + + + + CLK + + + clk_25m + + + + + + clk_125m + + + + + + + CLK + + + clk_125m + + + + + + idelayctrl_clk + + + + + + + CLK + + + idelayctrl_clk + + + + + + reset + + + + + + + RST + + + reset + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_gmii_to_rgmii + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 4fe18eb9 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_gmii_to_rgmii + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + a61fc92b + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + d6c4c122 + + + + + + + clk_20m + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + clk_25m + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + clk_125m + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + idelayctrl_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + reset + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rgmii_td + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rgmii_tx_ctl + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rgmii_txc + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rgmii_rd + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + rgmii_rx_ctl + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + rgmii_rxc + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + mdio_mdc + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + mdio_in_w + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + mdio_in_r + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + gmii_txd + + in + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + gmii_tx_en + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + gmii_tx_er + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + gmii_tx_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + gmii_crs + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + gmii_col + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + gmii_rxd + + out + + 7 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + gmii_rx_dv + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + gmii_rx_er + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + gmii_rx_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + PHY_AD + Phy Ad + "10000" + + + IODELAY_CTRL + Iodelay Ctrl + "0" + + + IDELAY_VALUE + Idelay Value + 18 + + + IODELAY_GROUP + Iodelay Group + if_delay_group + + + REFCLK_FREQUENCY + Refclk Frequency + 200 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + util_gmii_to_rgmii_constr.xdc + xdc + + + mdc_mdio.v + verilogSource + + + util_gmii_to_rgmii.v + verilogSource + CHECKSUM_1fb997f7 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + mdc_mdio.v + verilogSource + + + util_gmii_to_rgmii.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/util_gmii_to_rgmii_v1_0.tcl + tclSource + CHECKSUM_d6c4c122 + XGUI_VERSION_2 + + + + util_gmii_to_rgmii_v1_0 + + + PHY_AD + Phy Ad + "10000" + + + IODELAY_CTRL + Iodelay Ctrl + "0" + + + IDELAY_VALUE + Idelay Value + 18 + + + IODELAY_GROUP + Iodelay Group + if_delay_group + + + REFCLK_FREQUENCY + Refclk Frequency + 200 + + + Component_Name + util_gmii_to_rgmii_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + util_gmii_to_rgmii_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:55:11Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_gmii_to_rgmii/mdc_mdio.v b/adi_library/util_gmii_to_rgmii/mdc_mdio.v new file mode 100644 index 00000000..32099d96 --- /dev/null +++ b/adi_library/util_gmii_to_rgmii/mdc_mdio.v @@ -0,0 +1,104 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module mdc_mdio #( + parameter PHY_AD = 5'b10000 +) ( + input mdio_mdc, + input mdio_in_w, + input mdio_in_r, + + output reg [ 1:0] speed_select, + output reg duplex_mode +); + + localparam IDLE = 2'b01; + localparam ACQUIRE = 2'b10; + + wire preamble; + + reg [ 1:0] current_state = IDLE; + reg [ 1:0] next_state = IDLE; + reg [31:0] data_in = 32'h0; + reg [31:0] data_in_r = 32'h0; + reg [ 5:0] data_counter = 6'h0; + + assign preamble = &data_in; + + always @(posedge mdio_mdc) begin + current_state <= next_state; + data_in <= {data_in[30:0], mdio_in_w}; + if (current_state == ACQUIRE) begin + data_counter <= data_counter + 1; + end else begin + data_counter <= 0; + end + if (data_counter == 6'h1f) begin + if (data_in[31] == 1'b0 && data_in[29:28]==2'b10 && data_in[27:23] == PHY_AD && data_in[22:18] == 5'h11) begin + speed_select <= data_in_r[16:15] ; + duplex_mode <= data_in_r[14]; + end + end + end + + always @(negedge mdio_mdc) begin + data_in_r <= {data_in_r[30:0], mdio_in_r}; + end + + always @(*) begin + case (current_state) + IDLE: begin + if (preamble == 1 && mdio_in_w == 0) begin + next_state <= ACQUIRE; + end else begin + next_state <= IDLE; + end + end + ACQUIRE: begin + if (data_counter == 6'h1f) begin + next_state <= IDLE; + end else begin + next_state <= ACQUIRE; + end + end + default: begin + next_state <= IDLE; + end + endcase + end + +endmodule diff --git a/adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v b/adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v new file mode 100644 index 00000000..8c542b92 --- /dev/null +++ b/adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.v @@ -0,0 +1,333 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// based on XILINX xapp692 +// specific for MOTCON2 ADI board +// works correctly if the PHY is set with Autonegotiation on + +`timescale 1ns/100ps + +module util_gmii_to_rgmii #( + + parameter PHY_AD = 5'b10000, + parameter IODELAY_CTRL = 1'b0, + parameter IDELAY_VALUE = 18, + parameter IODELAY_GROUP = "if_delay_group", + parameter REFCLK_FREQUENCY = 200 +) ( + input clk_20m, + input clk_25m, + input clk_125m, + input idelayctrl_clk, + + input reset, + + output [ 3:0] rgmii_td, + output rgmii_tx_ctl, + output rgmii_txc, + input [ 3:0] rgmii_rd, + input rgmii_rx_ctl, + input rgmii_rxc, + + input mdio_mdc, + input mdio_in_w, + input mdio_in_r, + + input [ 7:0] gmii_txd, + input gmii_tx_en, + input gmii_tx_er, + output gmii_tx_clk, + output reg gmii_crs, + output reg gmii_col, + output reg [ 7:0] gmii_rxd, + output reg gmii_rx_dv, + output reg gmii_rx_er, + output gmii_rx_clk +); + + // wires + wire clk_2_5m; + wire clk_100msps; + wire [ 3:0] rgmii_rd_delay; + wire [ 7:0] gmii_rxd_s; + wire rgmii_rx_ctl_delay; + wire rgmii_rx_ctl_s; + + wire [ 1:0] speed_selection; // 1x gigabit, 01 100Mbps, 00 10mbps + wire duplex_mode; // 1 full, 0 half + + // registers + reg tx_reset_d1; + reg tx_reset_sync; + reg rx_reset_d1; + reg [ 7:0] gmii_txd_r; + reg gmii_tx_en_r; + reg gmii_tx_er_r; + reg [ 7:0] gmii_txd_r_d1; + reg gmii_tx_en_r_d1; + reg gmii_tx_er_r_d1; + + reg rgmii_tx_ctl_r; + reg [ 3:0] gmii_txd_low; + + reg idelayctrl_reset; + reg [ 3:0] idelay_reset_cnt; + + assign gigabit = speed_selection [1]; + assign gmii_tx_clk = gmii_tx_clk_s; + + always @(posedge gmii_rx_clk) + begin + gmii_rxd = gmii_rxd_s; + gmii_rx_dv = gmii_rx_dv_s; + gmii_rx_er = gmii_rx_dv_s ^ rgmii_rx_ctl_s; + end + + always @(posedge gmii_tx_clk_s) begin + tx_reset_d1 <= reset; + tx_reset_sync <= tx_reset_d1; + end + + always @(posedge gmii_tx_clk_s) + begin + rgmii_tx_ctl_r = gmii_tx_en_r ^ gmii_tx_er_r; + gmii_txd_low = gigabit ? gmii_txd_r[7:4] : gmii_txd_r[3:0]; + gmii_col = duplex_mode ? 1'b0 : (gmii_tx_en_r| gmii_tx_er_r) & ( gmii_rx_dv | gmii_rx_er) ; + gmii_crs = duplex_mode ? 1'b0 : (gmii_tx_en_r| gmii_tx_er_r| gmii_rx_dv | gmii_rx_er); + end + + always @(posedge gmii_tx_clk_s) begin + if (tx_reset_sync == 1'b1) begin + gmii_txd_r <= 8'h0; + gmii_tx_en_r <= 1'b0; + gmii_tx_er_r <= 1'b0; + end + else + begin + gmii_txd_r <= gmii_txd; + gmii_tx_en_r <= gmii_tx_en; + gmii_tx_er_r <= gmii_tx_er; + gmii_txd_r_d1 <= gmii_txd_r; + gmii_tx_en_r_d1 <= gmii_tx_en_r; + gmii_tx_er_r_d1 <= gmii_tx_er_r; + end + end + + BUFR #( + .BUFR_DIVIDE("8"), + .SIM_DEVICE("7SERIES") + ) clk_2_5_divide ( + .I(clk_20m), + .CE(1), + .CLR(0), + .O(clk_2_5m)); + + BUFGMUX #( + .CLK_SEL_TYPE ("SYNC") + ) clk_tx_mux0 ( + .S(speed_selection[0]), + .I0(clk_2_5m), + .I1(clk_25m), + .O(clk_100msps)); + + BUFGMUX #( + .CLK_SEL_TYPE ("SYNC") + ) clk_tx_mux1 ( + .S(speed_selection[1]), + .I0(clk_100msps), + .I1(clk_125m), + .O(gmii_tx_clk_s)); + + ODDR #( + .DDR_CLK_EDGE("SAME_EDGE") + ) rgmii_txc_out ( + .Q (rgmii_txc), + .C (gmii_tx_clk_s), + .CE(1), + .D1(1), + .D2(0), + .R(tx_reset_sync), + .S(0)); + + generate + genvar i; + for (i = 0; i < 4; i = i + 1) begin : gen_tx_data + ODDR #( + .DDR_CLK_EDGE("SAME_EDGE") + ) rgmii_td_out ( + .Q (rgmii_td[i]), + .C (gmii_tx_clk_s), + .CE(1), + .D1(gmii_txd_r_d1[i]), + .D2(gmii_txd_low[i]), + .R(tx_reset_sync), + .S(0)); + end + endgenerate + + ODDR #( + .DDR_CLK_EDGE("SAME_EDGE") + ) rgmii_tx_ctl_out ( + .Q (rgmii_tx_ctl), + .C (gmii_tx_clk_s), + .CE(1), + .D1(gmii_tx_en_r_d1), + .D2(rgmii_tx_ctl_r), + .R(tx_reset_sync), + .S(0)); + + BUFG bufmr_rgmii_rxc( + .I(rgmii_rxc), + .O(gmii_rx_clk)); + + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYE2 #( + .IDELAY_TYPE("FIXED"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .REFCLK_FREQUENCY(REFCLK_FREQUENCY), + .SIGNAL_PATTERN("DATA"), + .IDELAY_VALUE (IDELAY_VALUE), + .DELAY_SRC("IDATAIN") + ) delay_rgmii_rx_ctl ( + .IDATAIN(rgmii_rx_ctl), + .DATAOUT(rgmii_rx_ctl_delay), + .DATAIN(0), + .C(0), + .CE(0), + .INC(0), + .CINVCTRL(0), + .CNTVALUEOUT(), + .LD(0), + .LDPIPEEN(0), + .CNTVALUEIN(0), + .REGRST(0)); + + generate + for (i = 0; i < 4; i = i + 1) begin + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYE2 #( + .IDELAY_TYPE("FIXED"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .REFCLK_FREQUENCY(REFCLK_FREQUENCY), + .SIGNAL_PATTERN("DATA"), + .IDELAY_VALUE (IDELAY_VALUE), + .DELAY_SRC("IDATAIN") + ) delay_rgmii_rd ( + .IDATAIN(rgmii_rd[i]), + .DATAOUT(rgmii_rd_delay[i]), + .DATAIN(0), + .C(0), + .CE(0), + .INC(0), + .CINVCTRL(0), + .CNTVALUEOUT(), + .LD(0), + .LDPIPEEN(0), + .CNTVALUEIN(0), + .REGRST(0)); + + IDDR #( + .DDR_CLK_EDGE("SAME_EDGE_PIPELINED") + ) rgmii_rx_iddr ( + .Q1(gmii_rxd_s[i]), + .Q2(gmii_rxd_s[i+4]), + .C(gmii_rx_clk), + .CE(1), + .D(rgmii_rd_delay[i]), + .R(0), + .S(0)); + end + endgenerate + + IDDR #( + .DDR_CLK_EDGE("SAME_EDGE_PIPELINED") + ) rgmii_rx_ctl_iddr ( + .Q1(gmii_rx_dv_s), + .Q2(rgmii_rx_ctl_s), + .C(gmii_rx_clk), + .CE(1), + .D(rgmii_rx_ctl_delay), + .R(0), + .S(0)); + + mdc_mdio #( + .PHY_AD(PHY_AD) + ) mdc_mdio_in( + .mdio_mdc(mdio_mdc), + .mdio_in_w(mdio_in_w), + .mdio_in_r(mdio_in_r), + .speed_select(speed_selection), + .duplex_mode(duplex_mode)); + + // DELAY CONTROLLER + generate + if (IODELAY_CTRL == 1'b1) begin + always @(posedge idelayctrl_clk) begin + if (reset == 1'b1) begin + idelay_reset_cnt <= 4'h0; + idelayctrl_reset <= 1'b1; + end else begin + idelayctrl_reset <= 1'b1; + case (idelay_reset_cnt) + 4'h0: idelay_reset_cnt <= 4'h1; + 4'h1: idelay_reset_cnt <= 4'h2; + 4'h2: idelay_reset_cnt <= 4'h3; + 4'h3: idelay_reset_cnt <= 4'h4; + 4'h4: idelay_reset_cnt <= 4'h5; + 4'h5: idelay_reset_cnt <= 4'h6; + 4'h6: idelay_reset_cnt <= 4'h7; + 4'h7: idelay_reset_cnt <= 4'h8; + 4'h8: idelay_reset_cnt <= 4'h9; + 4'h9: idelay_reset_cnt <= 4'ha; + 4'ha: idelay_reset_cnt <= 4'hb; + 4'hb: idelay_reset_cnt <= 4'hc; + 4'hc: idelay_reset_cnt <= 4'hd; + 4'hd: idelay_reset_cnt <= 4'he; + default: begin + idelay_reset_cnt <= 4'he; + idelayctrl_reset <= 1'b0; + end + endcase + end + end + + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYCTRL dlyctrl ( + .RDY(), + .REFCLK(idelayctrl_clk), + .RST(idelayctrl_reset)); + end + endgenerate + +endmodule diff --git a/adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.xpr b/adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.xpr new file mode 100644 index 00000000..b4076c45 --- /dev/null +++ b/adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii.xpr @@ -0,0 +1,412 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii_constr.xdc b/adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii_constr.xdc new file mode 100644 index 00000000..78dfd6c2 --- /dev/null +++ b/adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii_constr.xdc @@ -0,0 +1,12 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property ASYNC_REG TRUE \ + [get_cells -hier *tx_reset_d1_reg*] \ + [get_cells -hier *tx_reset_sync*] + +set_false_path \ + -to [get_cells -hier tx_reset_d1_reg* -filter {primitive_subgroup == flop}] + diff --git a/adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl b/adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl new file mode 100644 index 00000000..5dea2287 --- /dev/null +++ b/adi_library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl @@ -0,0 +1,30 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_gmii_to_rgmii +adi_ip_files util_gmii_to_rgmii [list \ + "mdc_mdio.v" \ + "util_gmii_to_rgmii_constr.xdc" \ + "util_gmii_to_rgmii.v" ] + +adi_ip_properties_lite util_gmii_to_rgmii + +ipx::infer_bus_interface {gmii_tx_clk gmii_txd gmii_tx_en gmii_tx_er gmii_crs gmii_col gmii_rx_clk gmii_rxd gmii_rx_dv gmii_rx_er} xilinx.com:interface:gmii_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface {rgmii_td rgmii_tx_ctl rgmii_txc rgmii_rd rgmii_rx_ctl rgmii_rxc} xilinx.com:interface:rgmii_rtl:1.0 [ipx::current_core] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.IODELAY_CTRL')) = 1} \ + [ipx::get_ports idelayctrl_clk -of_objects [ipx::current_core]] + +ipx::infer_bus_interface clk_20m xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface clk_25m xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface clk_125m xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface idelayctrl_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface reset xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] diff --git a/adi_library/util_gmii_to_rgmii/xgui/util_gmii_to_rgmii_v1_0.tcl b/adi_library/util_gmii_to_rgmii/xgui/util_gmii_to_rgmii_v1_0.tcl new file mode 100644 index 00000000..3ed379e4 --- /dev/null +++ b/adi_library/util_gmii_to_rgmii/xgui/util_gmii_to_rgmii_v1_0.tcl @@ -0,0 +1,85 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "IDELAY_VALUE" -parent ${Page_0} + ipgui::add_param $IPINST -name "IODELAY_CTRL" -parent ${Page_0} + ipgui::add_param $IPINST -name "IODELAY_GROUP" -parent ${Page_0} + ipgui::add_param $IPINST -name "PHY_AD" -parent ${Page_0} + ipgui::add_param $IPINST -name "REFCLK_FREQUENCY" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.IDELAY_VALUE { PARAM_VALUE.IDELAY_VALUE } { + # Procedure called to update IDELAY_VALUE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IDELAY_VALUE { PARAM_VALUE.IDELAY_VALUE } { + # Procedure called to validate IDELAY_VALUE + return true +} + +proc update_PARAM_VALUE.IODELAY_CTRL { PARAM_VALUE.IODELAY_CTRL } { + # Procedure called to update IODELAY_CTRL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IODELAY_CTRL { PARAM_VALUE.IODELAY_CTRL } { + # Procedure called to validate IODELAY_CTRL + return true +} + +proc update_PARAM_VALUE.IODELAY_GROUP { PARAM_VALUE.IODELAY_GROUP } { + # Procedure called to update IODELAY_GROUP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IODELAY_GROUP { PARAM_VALUE.IODELAY_GROUP } { + # Procedure called to validate IODELAY_GROUP + return true +} + +proc update_PARAM_VALUE.PHY_AD { PARAM_VALUE.PHY_AD } { + # Procedure called to update PHY_AD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PHY_AD { PARAM_VALUE.PHY_AD } { + # Procedure called to validate PHY_AD + return true +} + +proc update_PARAM_VALUE.REFCLK_FREQUENCY { PARAM_VALUE.REFCLK_FREQUENCY } { + # Procedure called to update REFCLK_FREQUENCY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.REFCLK_FREQUENCY { PARAM_VALUE.REFCLK_FREQUENCY } { + # Procedure called to validate REFCLK_FREQUENCY + return true +} + + +proc update_MODELPARAM_VALUE.PHY_AD { MODELPARAM_VALUE.PHY_AD PARAM_VALUE.PHY_AD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PHY_AD}] ${MODELPARAM_VALUE.PHY_AD} +} + +proc update_MODELPARAM_VALUE.IODELAY_CTRL { MODELPARAM_VALUE.IODELAY_CTRL PARAM_VALUE.IODELAY_CTRL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IODELAY_CTRL}] ${MODELPARAM_VALUE.IODELAY_CTRL} +} + +proc update_MODELPARAM_VALUE.IDELAY_VALUE { MODELPARAM_VALUE.IDELAY_VALUE PARAM_VALUE.IDELAY_VALUE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IDELAY_VALUE}] ${MODELPARAM_VALUE.IDELAY_VALUE} +} + +proc update_MODELPARAM_VALUE.IODELAY_GROUP { MODELPARAM_VALUE.IODELAY_GROUP PARAM_VALUE.IODELAY_GROUP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IODELAY_GROUP}] ${MODELPARAM_VALUE.IODELAY_GROUP} +} + +proc update_MODELPARAM_VALUE.REFCLK_FREQUENCY { MODELPARAM_VALUE.REFCLK_FREQUENCY PARAM_VALUE.REFCLK_FREQUENCY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.REFCLK_FREQUENCY}] ${MODELPARAM_VALUE.REFCLK_FREQUENCY} +} + diff --git a/adi_library/util_hbm/Makefile b/adi_library/util_hbm/Makefile new file mode 100644 index 00000000..382c6bb3 --- /dev/null +++ b/adi_library/util_hbm/Makefile @@ -0,0 +1,21 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_hbm + +GENERIC_DEPS += util_hbm.v + +XILINX_DEPS += bd/bd.tcl +XILINX_DEPS += util_hbm_constr.xdc +XILINX_DEPS += util_hbm_ip.tcl +XILINX_DEPS += util_hbm_ooc.ttcl + +XILINX_DEPS += ../interfaces/if_do_ctrl.xml +XILINX_DEPS += ../interfaces/if_do_ctrl_rtl.xml + +XILINX_INTERFACE_DEPS += interfaces + +include ../scripts/library.mk diff --git a/adi_library/util_hbm/bd/bd.tcl b/adi_library/util_hbm/bd/bd.tcl new file mode 100644 index 00000000..c70fe8e1 --- /dev/null +++ b/adi_library/util_hbm/bd/bd.tcl @@ -0,0 +1,91 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip \ + "AXI_ADDR_WIDTH" +} + +# Executed when you close the config window +proc post_config_ip {cellpath otherinfo} { + set ip [get_bd_cells $cellpath] + + # Update AXI interface properties according to configuration + set axi_protocol [get_property "CONFIG.AXI_PROTOCOL" $ip] + set data_width [get_property "CONFIG.AXI_DATA_WIDTH" $ip] + + set src_fifo_size [get_property "CONFIG.SRC_FIFO_SIZE" $ip] + set dst_fifo_size [get_property "CONFIG.DST_FIFO_SIZE" $ip] + + if {$axi_protocol == 0} { + set axi_protocol_str "AXI4" + set max_beats_per_burst 256 + } else { + set axi_protocol_str "AXI3" + set max_beats_per_burst 16 + } + + set num_m [get_property "CONFIG.NUM_M" $ip] + for {set idx 0} {$idx < $num_m} {incr idx} { + + set intf [get_bd_intf_pins [format "%s/MAXI_%d" $cellpath $idx]] + + set_property CONFIG.PROTOCOL $axi_protocol_str $intf + set_property CONFIG.MAX_BURST_LENGTH $max_beats_per_burst $intf + + set_property CONFIG.NUM_WRITE_OUTSTANDING $src_fifo_size $intf + set_property CONFIG.NUM_READ_OUTSTANDING $dst_fifo_size $intf + + } + + # For multi master configurations (e.g.HBM) the AXIS data widths must match + if { $num_m > 1} { + set src_width [get_property "CONFIG.SRC_DATA_WIDTH" $ip] + set dst_width [get_property "CONFIG.DST_DATA_WIDTH" $ip] + if {$src_width != $dst_width} { + bd::send_msg -of $cellpath -type ERROR -msg_id 1 -text ": For multi AXI master configuration the Source AXIS interface width ($src_width) must match the Destination AXIS interface width ($dst_width) ." + } else { + # AXIS Data widths divided by number of masters must be >= 8 and power of 2 + set bits_per_master [expr $src_width/$num_m] + if {$bits_per_master < 8} { + bd::send_msg -of $cellpath -type ERROR -msg_id 2 -text ": Number of AXI masters ($num_m) too high. AXIS data widths divided by number of masters ($src_width / $num_m = $bits_per_master) must be >= 8 ." + } + } + } + +} + +proc log2 {x} { + return [tcl::mathfunc::int [tcl::mathfunc::ceil [expr [tcl::mathfunc::log $x] / [tcl::mathfunc::log 2]]]] +} + +# Executed when the block design is validated +proc propagate {cellpath otherinfo} { + set ip [get_bd_cells $cellpath] + +} + +proc post_propagate {cellpath otherinfo} { + set ip [get_bd_cells $cellpath] + + #Check address space + set length_width [get_property "CONFIG.LENGTH_WIDTH" $ip] + set axi_addr_width [get_property "CONFIG.AXI_ADDR_WIDTH" $ip] + set ddr_base_adddress [get_property "CONFIG.DDR_BASE_ADDDRESS" $ip] + set hbm_segment_index [get_property "CONFIG.HBM_SEGMENT_INDEX" $ip] + set mem_type [get_property "CONFIG.MEM_TYPE" $ip] + if {$mem_type == 1} { + set addr_width [log2 [expr $ddr_base_adddress + 2 ** $length_width - 1]] + } else { + # assumption: 1 segmetn is 256MB + set addr_width [log2 [expr $hbm_segment_index * 256 * 1024 * 1024 + 2 ** $length_width - 1]] + } + + set_property "CONFIG.AXI_ADDR_WIDTH" $addr_width $ip + bd::send_msg -of $cellpath -type INFO -msg_id 2 -text ": AXI Address Width set to $addr_width" + +} diff --git a/adi_library/util_hbm/component.xml b/adi_library/util_hbm/component.xml new file mode 100644 index 00000000..fa05ed63 --- /dev/null +++ b/adi_library/util_hbm/component.xml @@ -0,0 +1,7053 @@ + + + analog.com + user + util_hbm + 1.0 + + + s_axis + + + + + + + TREADY + + + s_axis_ready + + + + + TVALID + + + s_axis_valid + + + + + TDATA + + + s_axis_data + + + + + TSTRB + + + s_axis_strb + + + + + TKEEP + + + s_axis_keep + + + + + TUSER + + + s_axis_user + + + + + TLAST + + + s_axis_last + + + + + + m_axis + + + + + + + TREADY + + + m_axis_ready + + + + + TVALID + + + m_axis_valid + + + + + TDATA + + + m_axis_data + + + + + TSTRB + + + m_axis_strb + + + + + TKEEP + + + m_axis_keep + + + + + TUSER + + + m_axis_user + + + + + TLAST + + + m_axis_last + + + + + + MAXI_0 + + + + + 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xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + e53075f6 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_hbm + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_axi_dmac_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 9b7d6e4d + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_xpgui_analog_com_user_axi_dmac_1_0__ref_view_fileset + + + xilinx_xpgui_view_fileset + + + + viewChecksum + b924abcc + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_blockdiagram_analog_com_user_axi_dmac_1_0__ref_view_fileset + + + xilinx_blockdiagram_view_fileset + + + + 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LENGTH_WIDTH + Length Width + 32 + + + AXI_PROTOCOL + Axi Protocol + 0 + + + AXI_DATA_WIDTH + Axi Data Width + 256 + + + AXI_ADDR_WIDTH + Axi Addr Width + 32 + + + MEM_TYPE + Mem Type + 2 + + + HBM_SEGMENTS_PER_MASTER + Hbm Segments Per Master + + + + HBM_SEGMENT_INDEX + Hbm Segment Index + 0 + + + DDR_BASE_ADDDRESS + Ddr Base Adddress + 0 + + + + false + + + + + + NUM_M + Num M + 2 + + + SRC_FIFO_SIZE + Src Fifo Size + 8 + + + DST_FIFO_SIZE + Dst Fifo Size + 8 + + + + + + choice_list_2fc640b2 + 16 + 32 + 64 + 128 + 256 + 512 + 1024 + 2048 + 4096 + + + choice_list_90ee0cc7 + 32 + 64 + 128 + 256 + 512 + 1024 + + + choice_list_9a3ef62d + 2 + 4 + 8 + 16 + 32 + + + choice_list_f4d5364e + 1 + 2 + 4 + 8 + 16 + + + choice_pairs_453b9fa5 + 1 + 0 + + + choice_pairs_4b4b5176 + 2 + 1 + + + choice_pairs_8bd59fa5 + 1 + 0 + + + choice_pairs_cebf9777 + 28 + 29 + 30 + 31 + 32 + 33 + 34 + + + + + xilinx_anylanguagesynthesis_view_fileset + + util_hbm_ooc.ttcl + ttcl + + + util_hbm_constr.xdc + xdc + + processing_order + late + + + + bd/bd.tcl + tclSource + + + util_hbm.v + verilogSource + CHECKSUM_a4a1e134 + + + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagesynthesis_analog_com_user_axi_dmac_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + bd/bd.tcl + tclSource + + + util_hbm.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_axi_dmac_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/util_hbm_v1_0.tcl + tclSource + CHECKSUM_c86c89ca + XGUI_VERSION_2 + + + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + xilinx_xpgui_analog_com_user_axi_dmac_1_0__ref_view_fileset + + + + + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + xilinx_blockdiagram_analog_com_user_axi_dmac_1_0__ref_view_fileset + + + + + + + + xilinx_utilityxitfiles_view_fileset + + gui/util_hbm_v1_0.gtcl + GTCL + + + + Bridge between a AXI Stream master/slave interface and an AXI Memory Mapped interface + + + TX_RX_N + Datapath type + 1 + + + SRC_DATA_WIDTH + Source AXIS Bus Width + 512 + + + DST_DATA_WIDTH + Destination AXIS Bus Width + 512 + + + LENGTH_WIDTH + Storage size + 24 + + + AXI_PROTOCOL + AXI Protocol + 0 + + + AXI_DATA_WIDTH + AXI Data Bus Width + 256 + + + AXI_ADDR_WIDTH + Axi Addr Width + 32 + + + MEM_TYPE + External Storage Type + 2 + + + HBM_SEGMENTS_PER_MASTER + HBM sections per master + + + + + false + + + + + + HBM_SEGMENT_INDEX + First HBM section index + 0 + + + + true + + + + + + DDR_BASE_ADDDRESS + DDR base address + 0 + + + + false + + + + + + NUM_M + Number of AXI Masters + 2 + + + SRC_FIFO_SIZE + Write Buffer Size + 8 + + + DST_FIFO_SIZE + Read Buffer Size + 8 + + + Component_Name + util_hbm_v1_0 + + + + + + virtex7 + + + /Analog_Devices + + ADI AXIS to HBM/DDR AXI bridge + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:55:19Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_hbm/gui/util_hbm_v1_0.gtcl b/adi_library/util_hbm/gui/util_hbm_v1_0.gtcl new file mode 100644 index 00000000..87f28807 --- /dev/null +++ b/adi_library/util_hbm/gui/util_hbm_v1_0.gtcl @@ -0,0 +1,4 @@ +# This file is automatically written. Do not modify. +proc gen_USERPARAMETER_HBM_SEGMENTS_PER_MASTER_VALUE {LENGTH_WIDTH NUM_M } {expr int(ceil(2**($LENGTH_WIDTH-28) / ${NUM_M}.0)) } +proc gen_USERPARAMETER_HBM_SEGMENT_INDEX_ENABLEMENT {MEM_TYPE } {expr $MEM_TYPE == 2} +proc gen_USERPARAMETER_DDR_BASE_ADDDRESS_ENABLEMENT {MEM_TYPE } {expr $MEM_TYPE == 1} diff --git a/adi_library/util_hbm/scripts/adi_util_hbm.tcl b/adi_library/util_hbm/scripts/adi_util_hbm.tcl new file mode 100644 index 00000000..45ddb3a0 --- /dev/null +++ b/adi_library/util_hbm/scripts/adi_util_hbm.tcl @@ -0,0 +1,122 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# density 4GB,8GB +proc ad_create_hbm {ip_name {density "4GB"}} { + global hbm_sim; + if { [info exists hbm_sim] == 0} { + set hbm_sim 0 + } + + if {$hbm_sim == 0} { + ad_ip_instance hbm $ip_name + ad_ip_parameter $ip_name CONFIG.USER_HBM_DENSITY $density + ad_ip_parameter $ip_name CONFIG.USER_APB_EN {false} + + set i_hbm_ip [get_bd_cells $ip_name] + set num_stacks [get_property CONFIG.USER_HBM_STACK $i_hbm_ip] + # 16 pseudo channels / sections / segments per stack + set num_segments [expr $num_stacks*16] + for {set i 1} {$i < $num_segments} {incr i} { + set i_formatted [format "%02d" $i] + ad_ip_parameter $ip_name CONFIG.USER_SAXI_${i_formatted} {false} + } + + } else { + # Create data storage HMB controller model (AXI slave) + ad_ip_instance axi_vip $ip_name [list \ + INTERFACE_MODE {SLAVE} \ + ] + adi_sim_add_define "HBM_AXI=$ip_name" + } +} + +proc ad_create_util_hbm {name rx_tx_n src_width dst_width mem_size {axi_data_width 256} {mem_type 2}} { + + if {$mem_type == 2} { + # HBM + # split converter side bus into multiple AXI masters + set number_of_masters [expr int(ceil((${rx_tx_n} == 1 ? ${dst_width}.0 : ${src_width}.0) / ${axi_data_width}.0))] + } else { + # DDR we have always one master + set number_of_masters 1 + } + + ad_ip_instance util_hbm $name [list \ + LENGTH_WIDTH [log2 $mem_size] \ + SRC_DATA_WIDTH $src_width \ + DST_DATA_WIDTH $dst_width \ + AXI_DATA_WIDTH $axi_data_width \ + TX_RX_N $rx_tx_n \ + NUM_M $number_of_masters \ + MEM_TYPE $mem_type \ + ] +} + +proc ad_connect_hbm {i_hbm i_util_hbm axi_clk axi_aresetn {first_slave_index 0}} { + global hbm_sim; + if { [info exists hbm_sim] == 0} { + set hbm_sim 0 + } + + set i_util_hbm_ip [get_bd_cells $i_util_hbm] + set segments_per_master [get_property CONFIG.HBM_SEGMENTS_PER_MASTER $i_util_hbm_ip] + set num_m [get_property CONFIG.NUM_M $i_util_hbm_ip] + + if {$hbm_sim == 0} { + + set i_hbm_ip [get_bd_cells $i_hbm] + set num_stacks [get_property CONFIG.USER_HBM_STACK $i_hbm_ip] + + # 16 pseudo channels / sections / segments per stack + set num_segments [expr $num_stacks*16] + + set totat_used_segments [expr $num_m * $segments_per_master] + + for {set i 0} {$i < $totat_used_segments} {incr i} { + + set idx_hbm_slv [format "%02d" [expr $i+$first_slave_index]] + + if {$i % $segments_per_master == 0} { + ad_ip_parameter $i_hbm CONFIG.USER_SAXI_${idx_hbm_slv} {true} + ad_connect $i_util_hbm/MAXI_[expr $i/$segments_per_master] $i_hbm/SAXI_${idx_hbm_slv} + ad_connect $i_hbm/AXI_${idx_hbm_slv}_ACLK $axi_clk + ad_connect $i_hbm/AXI_${idx_hbm_slv}_ARESET_N $axi_aresetn + } + } + + ad_ip_parameter $i_util_hbm CONFIG.HBM_SEGMENT_INDEX $first_slave_index + + } else { + + # Create smart connect + ad_ip_instance smartconnect axi_hbm_interconnect [list \ + NUM_MI 1 \ + NUM_SI $num_m \ + ] + # connect it to hbm vip + ad_connect axi_hbm_interconnect/M00_AXI $i_hbm/S_AXI + # connect smart connect to util_hbm + for {set i 0} {$i < $num_m} {incr i} { + set i_formatted [format "%02d" $i] + ad_connect $i_util_hbm/MAXI_$i axi_hbm_interconnect/S${i_formatted}_AXI + } + ad_connect axi_hbm_interconnect/aclk $axi_clk + ad_connect axi_hbm_interconnect/aresetn $axi_aresetn + + ad_connect $i_hbm/aclk $axi_clk + ad_connect $i_hbm/aresetn $axi_aresetn + } + ad_connect $axi_clk $i_util_hbm/m_axi_aclk + ad_connect $axi_aresetn $i_util_hbm/m_axi_aresetn + + for {set i 0} {$i < $num_m} {incr i} { + assign_bd_address -target_address_space $i_util_hbm/MAXI_${i} + } +} + +proc log2 {x} { + return [tcl::mathfunc::int [tcl::mathfunc::ceil [expr [tcl::mathfunc::log $x] / [tcl::mathfunc::log 2]]]] +} diff --git a/adi_library/util_hbm/util_hbm.v b/adi_library/util_hbm/util_hbm.v new file mode 100644 index 00000000..d5396d57 --- /dev/null +++ b/adi_library/util_hbm/util_hbm.v @@ -0,0 +1,609 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +// This IP serves as storage interfacing element for external memories like +// HBM or DDR4 which have AXI3 or AXI4 data interfaces. +// +// The core leverages the axi_dmac as building blocks by merging an array of +// simplex DMA channels into duplex AXI channels. The core will split the +// incoming data from the source AXIS interface to multiple AXI channels, +// and in the read phase will merge the multiple AXI channels into a single +// AXIS destination interface. +// The number of duplex channels is set by syntheses parameter and must be +// set with the ratio of AXIS and AXI3/4 interface. +// +// Underflow or Overflow conditions are reported back to the data offload +// through the control/status interface. +// + +// Constraints: +// min(SRC_DATA_WIDTH,DST_DATA_WIDTH) / NUM_M >= 8 +// In case multiple AXI channels are used the source and destination AXIS +// interfaces widths must match. + +`timescale 1ns/100ps + +module util_hbm #( + parameter TX_RX_N = 1, + + parameter SRC_DATA_WIDTH = 512, + parameter DST_DATA_WIDTH = 512, + + parameter LENGTH_WIDTH = 32, + + // Memory interface parameters + parameter AXI_PROTOCOL = 0, // 0 - AXI4 ; 1 - AXI3 + parameter AXI_DATA_WIDTH = 256, + parameter AXI_ADDR_WIDTH = 32, + + parameter MEM_TYPE = 2, // 1 - DDR ; 2 - HBM + + // This will size the storage per master where each segment is 256MB + parameter HBM_SEGMENTS_PER_MASTER = 4, + parameter HBM_SEGMENT_INDEX = 0, + + // DDR parameters + parameter DDR_BASE_ADDDRESS = 0, + + // Number of AXI masters + parameter NUM_M = 2, + + // Data mover parameters + parameter SRC_FIFO_SIZE = 8, // In AXI bursts + parameter DST_FIFO_SIZE = 8 +) ( + input wr_request_enable, + input wr_request_valid, + output wr_request_ready, + input [LENGTH_WIDTH-1:0] wr_request_length, + output [LENGTH_WIDTH-1:0] wr_response_measured_length, + output reg wr_response_eot = 1'b0, + output wr_overflow, + + input rd_request_enable, + input rd_request_valid, + output rd_request_ready, + input [LENGTH_WIDTH-1:0] rd_request_length, + output reg rd_response_eot = 1'b0, + output rd_underflow, + + // Slave streaming AXI interface + input s_axis_aclk, + input s_axis_aresetn, + output s_axis_ready, + input s_axis_valid, + input [SRC_DATA_WIDTH-1:0] s_axis_data, + input [SRC_DATA_WIDTH/8-1:0] s_axis_strb, + input [SRC_DATA_WIDTH/8-1:0] s_axis_keep, + input [0:0] s_axis_user, + input s_axis_last, + + // Master streaming AXI interface + input m_axis_aclk, + input m_axis_aresetn, + input m_axis_ready, + output m_axis_valid, + output [DST_DATA_WIDTH-1:0] m_axis_data, + output [DST_DATA_WIDTH/8-1:0] m_axis_strb, + output [DST_DATA_WIDTH/8-1:0] m_axis_keep, + output [0:0] m_axis_user, + output m_axis_last, + + // Master AXI3 interface + input m_axi_aclk, + input m_axi_aresetn, + + // Write address + output [NUM_M*AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output [NUM_M*(8-(4*AXI_PROTOCOL))-1:0] m_axi_awlen, + output [NUM_M*3-1:0] m_axi_awsize, + output [NUM_M*2-1:0] m_axi_awburst, + output [NUM_M-1:0] m_axi_awvalid, + input [NUM_M-1:0] m_axi_awready, + + // Write data + output [NUM_M*AXI_DATA_WIDTH-1:0] m_axi_wdata, + output [NUM_M*(AXI_DATA_WIDTH/8)-1:0] m_axi_wstrb, + input [NUM_M-1:0] m_axi_wready, + output [NUM_M-1:0] m_axi_wvalid, + output [NUM_M-1:0] m_axi_wlast, + + // Write response + input [NUM_M-1:0] m_axi_bvalid, + input [NUM_M*2-1:0] m_axi_bresp, + output [NUM_M-1:0] m_axi_bready, + + // Read address + input [NUM_M-1:0] m_axi_arready, + output [NUM_M-1:0] m_axi_arvalid, + output [NUM_M*AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output [NUM_M*(8-(4*AXI_PROTOCOL))-1:0] m_axi_arlen, + output [NUM_M*3-1:0] m_axi_arsize, + output [NUM_M*2-1:0] m_axi_arburst, + + // Read data and response + input [NUM_M*AXI_DATA_WIDTH-1:0] m_axi_rdata, + output [NUM_M-1:0] m_axi_rready, + input [NUM_M-1:0] m_axi_rvalid, + input [NUM_M*2-1:0] m_axi_rresp, + input [NUM_M-1:0] m_axi_rlast +); + + localparam DMA_TYPE_AXI_MM = 0; + localparam DMA_TYPE_AXI_STREAM = 1; + localparam DMA_TYPE_FIFO = 2; + + localparam SRC_DATA_WIDTH_PER_M = SRC_DATA_WIDTH / NUM_M; + localparam DST_DATA_WIDTH_PER_M = DST_DATA_WIDTH / NUM_M; + + localparam AXI_BYTES_PER_BEAT_WIDTH = $clog2(AXI_DATA_WIDTH/8); + localparam SRC_BYTES_PER_BEAT_WIDTH = $clog2(SRC_DATA_WIDTH_PER_M/8); + localparam DST_BYTES_PER_BEAT_WIDTH = $clog2(DST_DATA_WIDTH_PER_M/8); + + // Size bursts to the max possible size + // AXI 3 1 burst is 16 beats + // AXI 4 1 burst is 256 beats + // Limit one burst to 4096 bytes + localparam MAX_BYTES_PER_BURST = (AXI_PROTOCOL ? 16 : 256) * AXI_DATA_WIDTH/8; + localparam MAX_BYTES_PER_BURST_LMT = MAX_BYTES_PER_BURST >= 4096 ? 4096 : + MAX_BYTES_PER_BURST; + localparam BYTES_PER_BURST_WIDTH = $clog2(MAX_BYTES_PER_BURST_LMT); + + localparam AXI_ALEN = (8-(4*AXI_PROTOCOL)); + + localparam NUM_M_LOG2 = $clog2(NUM_M); + + genvar i; + + wire [NUM_M-1:0] wr_request_ready_loc; + wire [NUM_M-1:0] rd_request_ready_loc; + wire [NUM_M-1:0] wr_request_eot_loc; + wire [NUM_M-1:0] rd_request_eot_loc; + wire [NUM_M-1:0] rd_response_valid_loc; + wire [NUM_M-1:0] wr_response_valid_loc; + wire wr_eot_pending_all; + wire rd_eot_pending_all; + + assign wr_request_ready = &wr_request_ready_loc; + assign rd_request_ready = &rd_request_ready_loc; + + // Aggregate end of transfer from all masters + reg [NUM_M-1:0] wr_eot_pending = {NUM_M{1'b0}}; + reg [NUM_M-1:0] rd_eot_pending = {NUM_M{1'b0}}; + + assign wr_eot_pending_all = &wr_eot_pending; + assign rd_eot_pending_all = &rd_eot_pending; + + wire [NUM_M-1:0] s_axis_ready_loc; + assign s_axis_ready = &s_axis_ready_loc; + + wire [NUM_M-1:0] m_axis_last_loc; + assign m_axis_last = &m_axis_last_loc; + + wire [NUM_M-1:0] m_axis_valid_loc; + assign m_axis_valid = &m_axis_valid_loc; + + wire [NUM_M-1:0] wr_response_ready_loc; + wire [NUM_M-1:0] rd_response_ready_loc; + + wire [NUM_M-1:0] wr_overflow_loc; + wire [NUM_M-1:0] rd_underflow_loc; + + // Measure stored data in case transfer is shorter than programmed, + // do the measurement only with the first master, all others should be + // similar. + localparam LW_PER_M = LENGTH_WIDTH-NUM_M_LOG2; + wire [NUM_M*BYTES_PER_BURST_WIDTH-1:0] wr_measured_burst_length; + reg [LW_PER_M-1:0] wr_response_measured_length_per_m = 'h0; + always @(posedge s_axis_aclk) begin + if (wr_request_enable == 1'b0) begin + wr_response_measured_length_per_m <= {LW_PER_M{1'h0}}; + end else if (wr_response_valid_loc[0] == 1'b1 && wr_response_ready_loc[0] == 1'b1) begin + wr_response_measured_length_per_m <= wr_response_measured_length_per_m + + {{LW_PER_M-BYTES_PER_BURST_WIDTH{1'b0}},wr_measured_burst_length[BYTES_PER_BURST_WIDTH-1:0]} + + {{LW_PER_M-1{1'b0}},~wr_request_eot_loc[0]}; + end else if (wr_response_eot == 1'b1) begin + wr_response_measured_length_per_m <= {LW_PER_M{1'h0}}; + end + end + assign wr_response_measured_length = {wr_response_measured_length_per_m,{NUM_M_LOG2{1'b1}}}; + + always @(posedge s_axis_aclk) begin + wr_response_eot <= wr_eot_pending_all; + end + + always @(posedge m_axis_aclk) begin + rd_response_eot <= rd_eot_pending_all; + end + + generate + for (i = 0; i < NUM_M; i=i+1) begin + + wire [11:0] rd_dbg_status; + wire rd_needs_reset; + wire s_axis_xfer_req; + wire m_axis_xfer_req; + + reg rd_needs_reset_d = 1'b0; + + // 2Gb (256MB) per segment + localparam ADDR_OFFSET = (MEM_TYPE == 1) ? DDR_BASE_ADDDRESS : + (HBM_SEGMENT_INDEX+i) * HBM_SEGMENTS_PER_MASTER * 256 * 1024 * 1024 ; + + always @(posedge s_axis_aclk) begin + if (wr_eot_pending_all) begin + wr_eot_pending[i] <= 1'b0; + end else if (wr_request_eot_loc[i] & wr_response_valid_loc[i]) begin + wr_eot_pending[i] <= 1'b1; + end + end + + // For last burst wait until all masters are done + assign wr_response_ready_loc[i] = wr_request_eot_loc[i] ? wr_eot_pending_all : wr_response_valid_loc[i]; + + // Overflow whenever s_axis_ready deasserts during capture (RX_PATH) + assign wr_overflow_loc[i] = TX_RX_N[0] ? 1'b0 : s_axis_xfer_req & ~s_axis_ready_loc[i]; + + // AXIS to AXI3 + axi_dmac_transfer #( + .DMA_DATA_WIDTH_SRC(SRC_DATA_WIDTH_PER_M), + .DMA_DATA_WIDTH_DEST(AXI_DATA_WIDTH), + .DMA_LENGTH_WIDTH(LENGTH_WIDTH), + .DMA_LENGTH_ALIGN(SRC_BYTES_PER_BEAT_WIDTH), + .BYTES_PER_BEAT_WIDTH_DEST(AXI_BYTES_PER_BEAT_WIDTH), + .BYTES_PER_BEAT_WIDTH_SRC(SRC_BYTES_PER_BEAT_WIDTH), + .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH), + .DMA_TYPE_DEST(DMA_TYPE_AXI_MM), + .DMA_TYPE_SRC(DMA_TYPE_AXI_STREAM), + .DMA_AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), + .DMA_2D_TRANSFER(1'b0), + .ASYNC_CLK_REQ_SRC(0), + .ASYNC_CLK_SRC_DEST(1), + .ASYNC_CLK_DEST_REQ(1), + .AXI_SLICE_DEST(1), + .AXI_SLICE_SRC(1), + .MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST_LMT), + .FIFO_SIZE(SRC_FIFO_SIZE), + .ID_WIDTH($clog2(SRC_FIFO_SIZE)), + .AXI_LENGTH_WIDTH_SRC(8-(4*AXI_PROTOCOL)), + .AXI_LENGTH_WIDTH_DEST(8-(4*AXI_PROTOCOL)), + .ENABLE_DIAGNOSTICS_IF(0), + .ALLOW_ASYM_MEM(1) + ) i_wr_transfer ( + .ctrl_clk(s_axis_aclk), + .ctrl_resetn(s_axis_aresetn), + + // Control interface + .ctrl_enable(wr_request_enable), + .ctrl_pause(1'b0), + .ctrl_hwdesc(1'b0), + + .req_valid(wr_request_valid), + .req_ready(wr_request_ready_loc[i]), + .req_dest_address(ADDR_OFFSET[AXI_ADDR_WIDTH-1:AXI_BYTES_PER_BEAT_WIDTH]), + .req_src_address('h0), + .req_sg_address('h0), + .req_x_length(wr_request_length >> NUM_M_LOG2), + .req_y_length(0), + .req_dest_stride(0), + .req_src_stride(0), + .req_sync_transfer_start(1'b0), + .req_last(1'b1), + + .req_eot(wr_request_eot_loc[i]), + .req_sg_desc_id(), + .req_measured_burst_length(wr_measured_burst_length[BYTES_PER_BURST_WIDTH*i+:BYTES_PER_BURST_WIDTH]), + .req_response_partial(), + .req_response_valid(wr_response_valid_loc[i]), + .req_response_ready(wr_response_ready_loc[i]), + + .m_dest_axi_aclk(m_axi_aclk), + .m_dest_axi_aresetn(m_axi_aresetn), + .m_src_axi_aclk(1'b0), + .m_src_axi_aresetn(1'b0), + .m_sg_axi_aclk(1'b0), + .m_sg_axi_aresetn(1'b0), + + .m_axi_awaddr(m_axi_awaddr[AXI_ADDR_WIDTH*i+:AXI_ADDR_WIDTH]), + .m_axi_awlen(m_axi_awlen[AXI_ALEN*i+:AXI_ALEN]), + .m_axi_awsize(m_axi_awsize[3*i+:3]), + .m_axi_awburst(m_axi_awburst[2*i+:2]), + .m_axi_awprot(), + .m_axi_awcache(), + .m_axi_awvalid(m_axi_awvalid[i]), + .m_axi_awready(m_axi_awready[i]), + + .m_axi_wdata(m_axi_wdata[AXI_DATA_WIDTH*i+:AXI_DATA_WIDTH]), + .m_axi_wstrb(m_axi_wstrb[(AXI_DATA_WIDTH/8)*i+:(AXI_DATA_WIDTH/8)]), + .m_axi_wready(m_axi_wready[i]), + .m_axi_wvalid(m_axi_wvalid[i]), + .m_axi_wlast(m_axi_wlast[i]), + + .m_axi_bvalid(m_axi_bvalid[i]), + .m_axi_bresp(m_axi_bresp[2*i+:2]), + .m_axi_bready(m_axi_bready[i]), + + .m_axi_arready(1'b0), + .m_axi_arvalid(), + .m_axi_araddr(), + .m_axi_arlen(), + .m_axi_arsize(), + .m_axi_arburst(), + .m_axi_arprot(), + .m_axi_arcache(), + + .m_axi_rdata('h0), + .m_axi_rlast(1'b0), + .m_axi_rready(), + .m_axi_rvalid(1'b0), + .m_axi_rresp(2'b00), + + .m_sg_axi_arready(1'b0), + .m_sg_axi_arvalid(), + .m_sg_axi_araddr(), + .m_sg_axi_arlen(), + .m_sg_axi_arsize(), + .m_sg_axi_arburst(), + .m_sg_axi_arprot(), + .m_sg_axi_arcache(), + + .m_sg_axi_rdata('h0), + .m_sg_axi_rlast(1'b0), + .m_sg_axi_rready(), + .m_sg_axi_rvalid(1'b0), + .m_sg_axi_rresp(2'b00), + + .s_axis_aclk(s_axis_aclk), + .s_axis_ready(s_axis_ready_loc[i]), + .s_axis_valid(s_axis_valid), + .s_axis_data(s_axis_data[SRC_DATA_WIDTH_PER_M*i+:SRC_DATA_WIDTH_PER_M]), + .s_axis_user(s_axis_user), + .s_axis_last(s_axis_last), + .s_axis_xfer_req(s_axis_xfer_req), + + .m_axis_aclk(1'b0), + .m_axis_ready(1'b1), + .m_axis_valid(), + .m_axis_data(), + .m_axis_last(), + .m_axis_xfer_req(), + + .fifo_wr_clk(1'b0), + .fifo_wr_en(1'b0), + .fifo_wr_din('b0), + .fifo_wr_overflow(), + .fifo_wr_sync(), + .fifo_wr_xfer_req(), + + .fifo_rd_clk(1'b0), + .fifo_rd_en(1'b0), + .fifo_rd_valid(), + .fifo_rd_dout(), + .fifo_rd_underflow(), + .fifo_rd_xfer_req(), + + // DBG + .dbg_dest_request_id(), + .dbg_dest_address_id(), + .dbg_dest_data_id(), + .dbg_dest_response_id(), + .dbg_src_request_id(), + .dbg_src_address_id(), + .dbg_src_data_id(), + .dbg_src_response_id(), + .dbg_status(), + + .dest_diag_level_bursts()); + + always @(posedge m_axis_aclk) begin + rd_needs_reset_d <= rd_needs_reset; + end + + // Generate an end of transfer at the end of flush marked by rd_needs_reset + always @(posedge m_axis_aclk) begin + if (rd_eot_pending_all) begin + rd_eot_pending[i] <= 1'b0; + end else if ((rd_request_eot_loc[i] & rd_response_valid_loc[i]) || + (~rd_needs_reset & rd_needs_reset_d)) begin + rd_eot_pending[i] <= 1'b1; + end + end + + assign rd_response_ready_loc[i] = rd_request_eot_loc[i] ? rd_eot_pending_all : rd_response_valid_loc[i]; + + // Underflow whenever m_axis_valid deasserts during play (TX_PATH) + assign rd_underflow_loc[i] = ~TX_RX_N[0] ? 1'b0 : m_axis_xfer_req & m_axis_ready & ~m_axis_valid_loc[i]; + + // AXI3 to MAXIS + axi_dmac_transfer #( + .DMA_DATA_WIDTH_SRC(AXI_DATA_WIDTH), + .DMA_DATA_WIDTH_DEST(DST_DATA_WIDTH_PER_M), + .DMA_LENGTH_WIDTH(LENGTH_WIDTH), + .DMA_LENGTH_ALIGN(DST_BYTES_PER_BEAT_WIDTH), + .BYTES_PER_BEAT_WIDTH_DEST(DST_BYTES_PER_BEAT_WIDTH), + .BYTES_PER_BEAT_WIDTH_SRC(AXI_BYTES_PER_BEAT_WIDTH), + .BYTES_PER_BURST_WIDTH(BYTES_PER_BURST_WIDTH), + .DMA_TYPE_DEST(DMA_TYPE_AXI_STREAM), + .DMA_TYPE_SRC(DMA_TYPE_AXI_MM), + .DMA_AXI_ADDR_WIDTH(AXI_ADDR_WIDTH), + .DMA_2D_TRANSFER(1'b0), + .ASYNC_CLK_REQ_SRC(1), + .ASYNC_CLK_SRC_DEST(1), + .ASYNC_CLK_DEST_REQ(0), + .AXI_SLICE_DEST(1), + .AXI_SLICE_SRC(1), + .MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST_LMT), + .FIFO_SIZE(DST_FIFO_SIZE), + .ID_WIDTH($clog2(DST_FIFO_SIZE)), + .AXI_LENGTH_WIDTH_SRC(8-(4*AXI_PROTOCOL)), + .AXI_LENGTH_WIDTH_DEST(8-(4*AXI_PROTOCOL)), + .ENABLE_DIAGNOSTICS_IF(0), + .ALLOW_ASYM_MEM(1) + ) i_rd_transfer ( + .ctrl_clk(m_axis_aclk), + .ctrl_resetn(m_axis_aresetn), + + // Control interface + .ctrl_enable(rd_request_enable), + .ctrl_pause(1'b0), + .ctrl_hwdesc(1'b0), + + .req_valid(rd_request_valid), + .req_ready(rd_request_ready_loc[i]), + .req_dest_address(0), + .req_src_address(ADDR_OFFSET[AXI_ADDR_WIDTH-1:AXI_BYTES_PER_BEAT_WIDTH]), + .req_sg_address('h0), + .req_x_length(rd_request_length >> NUM_M_LOG2), + .req_y_length(0), + .req_dest_stride(0), + .req_src_stride(0), + .req_sync_transfer_start(1'b0), + .req_last(1'b1), + + .req_eot(rd_request_eot_loc[i]), + .req_sg_desc_id(), + .req_measured_burst_length(), + .req_response_partial(), + .req_response_valid(rd_response_valid_loc[i]), + .req_response_ready(rd_response_ready_loc[i]), + + .m_dest_axi_aclk(1'b0), + .m_dest_axi_aresetn(1'b0), + .m_src_axi_aclk(m_axi_aclk), + .m_src_axi_aresetn(m_axi_aresetn), + .m_sg_axi_aclk(1'b0), + .m_sg_axi_aresetn(1'b0), + + .m_axi_awaddr(), + .m_axi_awlen(), + .m_axi_awsize(), + .m_axi_awburst(), + .m_axi_awprot(), + .m_axi_awcache(), + .m_axi_awvalid(), + .m_axi_awready(1'b1), + + .m_axi_wdata(), + .m_axi_wstrb(), + .m_axi_wready(1'b1), + .m_axi_wvalid(), + .m_axi_wlast(), + + .m_axi_bvalid(1'b0), + .m_axi_bresp(), + .m_axi_bready(), + + .m_axi_arready(m_axi_arready[i]), + .m_axi_arvalid(m_axi_arvalid[i]), + .m_axi_araddr(m_axi_araddr[AXI_ADDR_WIDTH*i+:AXI_ADDR_WIDTH]), + .m_axi_arlen(m_axi_arlen[AXI_ALEN*i+:AXI_ALEN]), + .m_axi_arsize(m_axi_arsize[3*i+:3]), + .m_axi_arburst(m_axi_arburst[2*i+:2]), + .m_axi_arprot(), + .m_axi_arcache(), + + .m_axi_rdata(m_axi_rdata[AXI_DATA_WIDTH*i+:AXI_DATA_WIDTH]), + .m_axi_rlast(m_axi_rlast[i]), + .m_axi_rready(m_axi_rready[i]), + .m_axi_rvalid(m_axi_rvalid[i]), + .m_axi_rresp(m_axi_rresp[2*i+:2]), + + .m_sg_axi_arready (1'b0), + .m_sg_axi_arvalid (), + .m_sg_axi_araddr (), + .m_sg_axi_arlen (), + .m_sg_axi_arsize (), + .m_sg_axi_arburst (), + .m_sg_axi_arprot (), + .m_sg_axi_arcache (), + + .m_sg_axi_rdata ('h0), + .m_sg_axi_rlast (1'b0), + .m_sg_axi_rready (), + .m_sg_axi_rvalid (1'b0), + .m_sg_axi_rresp (2'b00), + + .s_axis_aclk(1'b0), + .s_axis_ready(), + .s_axis_valid(1'b0), + .s_axis_data(), + .s_axis_user(), + .s_axis_last(), + .s_axis_xfer_req(), + + .m_axis_aclk(m_axis_aclk), + .m_axis_ready((m_axis_ready & m_axis_valid) | rd_needs_reset), + .m_axis_valid(m_axis_valid_loc[i]), + .m_axis_data(m_axis_data[DST_DATA_WIDTH_PER_M*i+:DST_DATA_WIDTH_PER_M]), + .m_axis_last(m_axis_last_loc[i]), + .m_axis_xfer_req(m_axis_xfer_req), + + .fifo_wr_clk(1'b0), + .fifo_wr_en(1'b0), + .fifo_wr_din('b0), + .fifo_wr_overflow(), + .fifo_wr_sync(), + .fifo_wr_xfer_req(), + + .fifo_rd_clk(1'b0), + .fifo_rd_en(1'b0), + .fifo_rd_valid(), + .fifo_rd_dout(), + .fifo_rd_underflow(), + .fifo_rd_xfer_req(), + + // DBG + .dbg_dest_request_id(), + .dbg_dest_address_id(), + .dbg_dest_data_id(), + .dbg_dest_response_id(), + .dbg_src_request_id(), + .dbg_src_address_id(), + .dbg_src_data_id(), + .dbg_src_response_id(), + .dbg_status(rd_dbg_status), + + .dest_diag_level_bursts()); + + assign rd_needs_reset = rd_dbg_status[11]; + + end + endgenerate + + assign wr_overflow = |wr_overflow_loc; + + assign rd_underflow = |rd_underflow_loc; + +endmodule diff --git a/adi_library/util_hbm/util_hbm.xpr b/adi_library/util_hbm/util_hbm.xpr new file mode 100644 index 00000000..38d01326 --- /dev/null +++ b/adi_library/util_hbm/util_hbm.xpr @@ -0,0 +1,413 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_hbm/util_hbm_constr.xdc b/adi_library/util_hbm/util_hbm_constr.xdc new file mode 100644 index 00000000..839c8608 --- /dev/null +++ b/adi_library/util_hbm/util_hbm_constr.xdc @@ -0,0 +1,303 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property ASYNC_REG TRUE \ + [get_cells -quiet -hier *cdc_sync_stage1_reg*] \ + [get_cells -quiet -hier *cdc_sync_stage2_reg*] + +# i_wr_transfer constraints +# .async_req_src(0), +# .async_src_dest(1), +# .async_dest_req(1), + +set req_clk [get_clocks -of_objects [get_ports s_axis_aclk]] +set src_clk [get_clocks -of_objects [get_ports s_axis_aclk]] +set dest_clk [get_clocks -of_objects [get_ports m_axi_aclk]] + +set_max_delay -quiet -datapath_only \ + -from $dest_clk \ + -to [get_cells -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_wr_transfer*i_sync_req_response_id* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $dest_clk] + +set_false_path -quiet \ + -from $dest_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_wr_transfer*i_sync_status_dest* && IS_SEQUENTIAL}] + +set_false_path -quiet \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_wr_transfer*i_sync_control_dest* && IS_SEQUENTIAL}] + +set_max_delay -quiet -datapath_only \ + -from $dest_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_wr_transfer*i_dest_response_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_wr_transfer*i_dest_response_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $req_clk] +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ + -filter {NAME =~ *i_wr_transfer*i_dest_response_fifo* && IS_SEQUENTIAL}] \ + -to $req_clk \ + [get_property -min PERIOD $req_clk] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_wr_transfer*i_sync_dest_request_id* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_wr_transfer*i_store_and_forward/i_dest_sync_id* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from $dest_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_wr_transfer*i_store_and_forward/i_src_sync_id* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -through [get_cells -quiet -hier \ + -filter {IS_SEQUENTIAL && NAME =~ *i_wr_transfer*i_store_and_forward/burst_len_mem_reg*}] \ + -to $dest_clk \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_wr_transfer*i_dest_req_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from $dest_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_wr_transfer*i_dest_req_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ + -filter {NAME =~ *i_wr_transfer*i_dest_req_fifo* && IS_SEQUENTIAL}] \ + -to $dest_clk \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_wr_transfer*i_src_dest_bl_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from $dest_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_wr_transfer*i_src_dest_bl_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ + -filter {NAME =~ *i_wr_transfer*i_src_dest_bl_fifo* && IS_SEQUENTIAL}] \ + -to $dest_clk \ + [get_property -min PERIOD $dest_clk] + + set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -through [get_cells -quiet -hier DP \ + -filter {NAME =~ *i_wr_transfer*i_request_arb/eot_mem_dest_reg*}] \ + -to $dest_clk \ + [get_property -min PERIOD $dest_clk] + +# i_rd_transfer constraints +# .async_req_src(1), +# .async_src_dest(1), +# .async_dest_req(0), + +set req_clk [get_clocks -of_objects [get_ports m_axis_aclk]] +set src_clk [get_clocks -of_objects [get_ports m_axi_aclk]] +set dest_clk [get_clocks -of_objects [get_ports m_axis_aclk]] + +set_max_delay -quiet -datapath_only \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_rd_transfer*i_sync_src_request_id* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $req_clk] + +set_false_path -quiet \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_rd_transfer*i_sync_status_src* && IS_SEQUENTIAL}] + +set_false_path -quiet \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_rd_transfer*i_sync_control_src* && IS_SEQUENTIAL}] + +set_max_delay -quiet -datapath_only \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_rd_transfer*i_src_req_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $req_clk] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_rd_transfer*i_src_req_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ + -filter {NAME =~ *i_rd_transfer*i_src_req_fifo* && IS_SEQUENTIAL}] \ + -to $src_clk \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from $req_clk \ + -through [get_cells -quiet -hier DP \ + -filter {NAME =~ *i_rd_transfer*i_request_arb/eot_mem_src_reg*}] \ + -to $src_clk \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_rd_transfer*i_rewind_req_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_rd_transfer*i_rewind_req_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $req_clk] + +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ + -filter {NAME =~ *i_rd_transfer*i_rewind_req_fifo* && IS_SEQUENTIAL}] \ + -to $req_clk \ + [get_property -min PERIOD $req_clk] + +set_false_path -quiet \ + -from $req_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_rd_transfer*sync_rewind/i_sync_out* && IS_SEQUENTIAL}] + +set_false_path -quiet \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_rd_transfer*sync_rewind/i_sync_in* && IS_SEQUENTIAL}] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_rd_transfer*i_sync_dest_request_id* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_rd_transfer*i_store_and_forward/i_dest_sync_id* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from $dest_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_rd_transfer*i_store_and_forward/i_src_sync_id* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -through [get_cells -quiet -hier \ + -filter {IS_SEQUENTIAL && NAME =~ *i_rd_transfer*i_store_and_forward/burst_len_mem_reg*}] \ + -to $dest_clk \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_rd_transfer*i_dest_req_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from $dest_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_rd_transfer*i_dest_req_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ + -filter {NAME =~ *i_rd_transfer*i_dest_req_fifo* && IS_SEQUENTIAL}] \ + -to $dest_clk \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_rd_transfer*i_src_dest_bl_fifo/zerodeep.i_waddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $src_clk] + +set_max_delay -quiet -datapath_only \ + -from $dest_clk \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_rd_transfer*i_src_dest_bl_fifo/zerodeep.i_raddr_sync* && IS_SEQUENTIAL}] \ + [get_property -min PERIOD $dest_clk] + +set_max_delay -quiet -datapath_only \ + -from [get_cells -quiet -hier *cdc_sync_fifo_ram_reg* \ + -filter {NAME =~ *i_rd_transfer*i_src_dest_bl_fifo* && IS_SEQUENTIAL}] \ + -to $dest_clk \ + [get_property -min PERIOD $dest_clk] + + set_max_delay -quiet -datapath_only \ + -from $src_clk \ + -through [get_cells -quiet -hier DP \ + -filter {NAME =~ *i_rd_transfer*i_request_arb/eot_mem_dest_reg*}] \ + -to $dest_clk \ + [get_property -min PERIOD $dest_clk] + +# +# Common to both dmas +# + +# Reset signals +set_false_path -quiet \ + -from [get_cells -quiet -hier *do_reset_reg* \ + -filter {NAME =~ *i_reset_manager* && IS_SEQUENTIAL}] \ + -to [get_pins -quiet -hier *reset_async_reg*/PRE] + +set_false_path -quiet \ + -from [get_cells -quiet -hier *reset_async_reg[0] \ + -filter {NAME =~ *i_reset_manager* && IS_SEQUENTIAL}] \ + -to [get_cells -quiet -hier *reset_async_reg[3]* \ + -filter {NAME =~ *i_reset_manager* && IS_SEQUENTIAL}] + +set_false_path -quiet \ + -from [get_cells -quiet -hier *reset_async_reg[0] \ + -filter {NAME =~ *i_reset_manager* && IS_SEQUENTIAL}] \ + -to [get_pins -quiet -hier *reset_sync_in_reg*/PRE \ + -filter {NAME =~ *i_reset_manager*}] + +set_false_path -quiet \ + -from [get_cells -quiet -hier *reset_sync_reg[0] \ + -filter {NAME =~ *i_reset_manager* && IS_SEQUENTIAL}] \ + -to [get_pins -quiet -hier *reset_sync_in_reg*/PRE \ + -filter {NAME =~ *i_reset_manager*}] + +set_property -dict { \ + SHREG_EXTRACT NO \ + ASYNC_REG TRUE \ + } [get_cells -quiet -hier *reset_async_reg*] + +set_property -dict { \ + SHREG_EXTRACT NO \ + ASYNC_REG TRUE \ + } [get_cells -quiet -hier *reset_sync_reg*] + diff --git a/adi_library/util_hbm/util_hbm_ip.tcl b/adi_library/util_hbm/util_hbm_ip.tcl new file mode 100644 index 00000000..00a70410 --- /dev/null +++ b/adi_library/util_hbm/util_hbm_ip.tcl @@ -0,0 +1,358 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_hbm +adi_ip_files util_hbm [list \ + "util_hbm_constr.xdc" \ + "util_hbm_ooc.ttcl" \ + "util_hbm.v" \ + "bd/bd.tcl" \ +] + +adi_ip_properties_lite util_hbm +adi_ip_ttcl util_dacfifo "util_hbm_ooc.ttcl" +adi_ip_bd util_hbm "bd/bd.tcl" + +set_property PROCESSING_ORDER LATE [ipx::get_files util_hbm_constr.xdc \ + -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] \ + -filter {NAME =~ *synthesis*}]] + +adi_ip_add_core_dependencies { \ + analog.com:user:util_cdc:1.0 \ + analog.com:user:axi_dmac:1.0 \ +} + +set_property display_name "ADI AXIS to HBM/DDR AXI bridge" [ipx::current_core] +set_property description "Bridge between a AXI Stream master/slave interface and an AXI Memory Mapped interface" [ipx::current_core] + +set max_axi_ifc 16 +set cc [ipx::current_core] + +adi_add_bus "s_axis" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"s_axis_ready" "TREADY"} \ + {"s_axis_valid" "TVALID"} \ + {"s_axis_data" "TDATA"} \ + {"s_axis_strb" "TSTRB"} \ + {"s_axis_keep" "TKEEP"} \ + {"s_axis_user" "TUSER"} \ + {"s_axis_last" "TLAST"}] + +adi_add_bus "m_axis" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"m_axis_ready" "TREADY"} \ + {"m_axis_valid" "TVALID"} \ + {"m_axis_data" "TDATA"} \ + {"m_axis_strb" "TSTRB"} \ + {"m_axis_keep" "TKEEP"} \ + {"m_axis_user" "TUSER"} \ + {"m_axis_last" "TLAST"}] + +adi_add_multi_bus $max_axi_ifc "MAXI_" "master" \ + "xilinx.com:interface:aximm_rtl:1.0" \ + "xilinx.com:interface:aximm:1.0" \ + [list \ + { "m_axi_araddr" "ARADDR" 32 "(spirit:decode(id('MODELPARAM_VALUE.AXI_ADDR_WIDTH')))"} \ + { "m_axi_arburst" "ARBURST" 2 } \ + { "m_axi_arlen" "ARLEN" 4 "8-(spirit:decode(id('MODELPARAM_VALUE.AXI_PROTOCOL')) * 4)"} \ + { "m_axi_arready" "ARREADY" 1 } \ + { "m_axi_arsize" "ARSIZE" 3 } \ + { "m_axi_arvalid" "ARVALID" 1 } \ + { "m_axi_awaddr" "AWADDR" 32 "(spirit:decode(id('MODELPARAM_VALUE.AXI_ADDR_WIDTH')) * 1)"} \ + { "m_axi_awburst" "AWBURST" 2 } \ + { "m_axi_awlen" "AWLEN" 4 "8-(spirit:decode(id('MODELPARAM_VALUE.AXI_PROTOCOL')) * 4)"} \ + { "m_axi_awready" "AWREADY" 1 } \ + { "m_axi_awsize" "AWSIZE" 3 } \ + { "m_axi_awvalid" "AWVALID" 1 } \ + { "m_axi_bready" "BREADY" 1 } \ + { "m_axi_bresp" "BRESP" 2 } \ + { "m_axi_bvalid" "BVALID" 1 } \ + { "m_axi_rdata" "RDATA" 32 "(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')))"} \ + { "m_axi_rlast" "RLAST" 1 } \ + { "m_axi_rready" "RREADY" 1 } \ + { "m_axi_rresp" "RRESP" 2 } \ + { "m_axi_rvalid" "RVALID" 1 } \ + { "m_axi_wdata" "WDATA" 32 "(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH')))"} \ + { "m_axi_wlast" "WLAST" 1 } \ + { "m_axi_wready" "WREADY" 1 } \ + { "m_axi_wstrb" "WSTRB" 4 "(spirit:decode(id('MODELPARAM_VALUE.AXI_DATA_WIDTH'))/8)"} \ + { "m_axi_wvalid" "WVALID" 1 } \ + ] \ + "(spirit:decode(id('MODELPARAM_VALUE.NUM_M')) > {i})" + +set ifc_list "" +for {set idx 0} {$idx < $max_axi_ifc} {incr idx} { + set ifc_list $ifc_list:MAXI_$idx + + ipx::add_address_space MAXI_$idx [ipx::current_core] + set_property master_address_space_ref MAXI_${idx} \ + [ipx::get_bus_interfaces MAXI_$idx \ + -of_objects [ipx::current_core]] + set_property range 4G [ipx::get_address_spaces MAXI_${idx}] + +} +adi_add_bus_clock "m_axi_aclk" $ifc_list "m_axi_aresetn" + +adi_add_bus "wr_ctrl" "slave" \ + "analog.com:interface:if_do_ctrl_rtl:1.0" \ + "analog.com:interface:if_do_ctrl:1.0" \ + [list {"wr_request_enable" "request_enable"} \ + {"wr_request_valid" "request_valid"} \ + {"wr_request_ready" "request_ready"} \ + {"wr_request_length" "request_length"} \ + {"wr_response_measured_length" "response_measured_length"} \ + {"wr_response_eot" "response_eot"} \ + {"wr_overflow" "status_overflow"} \ + ] + +adi_add_bus "rd_ctrl" "slave" \ + "analog.com:interface:if_do_ctrl_rtl:1.0" \ + "analog.com:interface:if_do_ctrl:1.0" \ + [list {"rd_request_enable" "request_enable"} \ + {"rd_request_valid" "request_valid"} \ + {"rd_request_ready" "request_ready"} \ + {"rd_request_length" "request_length"} \ + {"rd_response_eot" "response_eot"} \ + {"rd_underflow" "status_underflow"} \ + ] + +adi_add_bus_clock "s_axis_aclk" "s_axis:wr_ctrl" "s_axis_aresetn" +adi_add_bus_clock "m_axis_aclk" "m_axis:rd_ctrl" "m_axis_aresetn" + +# The core does not issue narrow bursts +foreach intf [ipx::get_bus_interfaces MAXI_* -of_objects $cc] { + set para [ipx::add_bus_parameter SUPPORTS_NARROW_BURST $intf] + set_property "VALUE" "0" $para +} + +# +# Parameters description +# +set_property -dict [list \ + "value_resolve_type" "user" \ + "value" 1 \ + "value_validation_type" "pairs" \ + "value_validation_pairs" {"TX (DAC)" 1 "RX (ADC)" 0} \ + ] \ + [ipx::get_user_parameters TX_RX_N -of_objects $cc] + +foreach dir {"SRC" "DST"} { + set_property -dict [list \ + "value_validation_type" "list" \ + "value_validation_list" "16 32 64 128 256 512 1024 2048 4096" \ + ] \ + [ipx::get_user_parameters ${dir}_DATA_WIDTH -of_objects $cc] +} + +set_property -dict [list \ + "value_validation_type" "pairs" \ + "value" "24" \ + "value_validation_pairs" {\ + "256MB" "28" \ + "512MB" "29" \ + "1GB" "30" \ + "2GB" "31" \ + "4GB" "32" \ + "8GB" "33" \ + "16GB" "34" \ + } \ + ] \ + [ipx::get_user_parameters LENGTH_WIDTH -of_objects $cc] + +set_property -dict [list \ + "value_resolve_type" "user" \ + "value" 2 \ + "value_validation_type" "pairs" \ + "value_validation_pairs" {"HBM" 2 "DDR" 1} \ + ] \ + [ipx::get_user_parameters MEM_TYPE -of_objects $cc] + +set_property -dict [list \ + "value_validation_type" "pairs" \ + "value" "0" \ + "value_validation_pairs" {"AXI3" "1" "AXI4" "0"} \ + ] \ + [ipx::get_user_parameters AXI_PROTOCOL -of_objects $cc] + +set_property -dict [list \ + "value_validation_type" "list" \ + "value_validation_list" "32 64 128 256 512 1024" \ + ] \ + [ipx::get_user_parameters AXI_DATA_WIDTH -of_objects $cc] + +set_property -dict [list \ + "value_validation_type" "list" \ + "value_validation_list" "1 2 4 8 16" \ + ] \ + [ipx::get_user_parameters NUM_M -of_objects $cc] + +set_property -dict [list \ + "value_validation_type" "list" \ + "value_validation_list" "2 4 8 16 32" \ + ] \ + [ipx::get_user_parameters SRC_FIFO_SIZE -of_objects $cc] + +set_property -dict [list \ + "value_validation_type" "list" \ + "value_validation_list" "2 4 8 16 32" \ + ] \ + [ipx::get_user_parameters DST_FIFO_SIZE -of_objects $cc] + +# 1 segment = 256MB +# HBM_SEGMENTS_PER_MASTER = Storage size (MB) / 256 (MB) / number of masters +set_property -dict [list \ + "enablement_value" "false" \ + "value_tcl_expr" {expr int(ceil(2**($LENGTH_WIDTH-28) / ${NUM_M}.0)) } \ + ] \ + [ipx::get_user_parameters HBM_SEGMENTS_PER_MASTER -of_objects $cc] + +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "0" \ + "value_validation_range_maximum" "15" \ + "enablement_tcl_expr" "\$MEM_TYPE == 2" \ + ] \ + [ipx::get_user_parameters HBM_SEGMENT_INDEX -of_objects $cc] + +set_property -dict [list \ + "value_validation_type" "range_long" \ + "value_validation_range_minimum" "0" \ + "value_validation_range_maximum" "4294967296" \ + "enablement_tcl_expr" "\$MEM_TYPE == 1" \ + ] \ + [ipx::get_user_parameters DDR_BASE_ADDDRESS -of_objects $cc] + +# +# GUI formatting +# + +set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] + +# General settings group +set group [ipgui::add_group -name "General Settings" -component $cc \ + -parent $page0 -display_name "General Settings"] + +set p [ipgui::get_guiparamspec -name "TX_RX_N" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $group +set_property -dict [list \ + "display_name" "Datapath type" \ + "widget" "comboBox" \ + ] $p + +set p [ipgui::get_guiparamspec -name "LENGTH_WIDTH" -component $cc] +ipgui::move_param -component $cc -order 1 $p -parent $group +set_property -dict [list \ + "display_name" "Storage size" \ + "tooltip" "Defines the amount of data can be stored starting from the base address of the storage."\ + ] $p + +# Offload interface group +set group [ipgui::add_group -name "Data Offload Interface" -component $cc \ + -parent $page0 -display_name "Data Offload Interface"] + +set p [ipgui::get_guiparamspec -name "SRC_DATA_WIDTH" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $group +set_property -dict [list \ + "display_name" "Source AXIS Bus Width" \ + "tooltip" "Source AXIS Bus Width (s_axis)" \ + ] $p + +set p [ipgui::get_guiparamspec -name "SRC_FIFO_SIZE" -component $cc] +ipgui::move_param -component $cc -order 1 $p -parent $group +set_property -dict [list \ + "display_name" "Write Buffer Size" \ + "tooltip" "Size of internal data mover buffer used for write to external memory. In AXI bursts, where one burst is max 4096 bytes or 2*AXI_DATA_WIDTH bytes for AXI3 or 32*AXI_DATA_WIDTH bytes for AXI4." \ + "widget" "comboBox" \ +] $p + +set p [ipgui::get_guiparamspec -name "DST_DATA_WIDTH" -component $cc] +ipgui::move_param -component $cc -order 2 $p -parent $group +set_property -dict [list \ + "display_name" "Destination AXIS Bus Width" \ + "tooltip" "Destination AXIS Bus Width (m_axis)" \ + ] $p + +set p [ipgui::get_guiparamspec -name "DST_FIFO_SIZE" -component $cc] +ipgui::move_param -component $cc -order 3 $p -parent $group +set_property -dict [list \ + "display_name" "Read Buffer Size" \ + "tooltip" "Size of internal data mover buffer used for read from the external memory. In AXI bursts, where one burst is max 4096 bytes or 2*AXI_DATA_WIDTH bytes for AXI3 or 32*AXI_DATA_WIDTH bytes for AXI4." \ + "widget" "comboBox" \ +] $p + +# Memory interface group +set group [ipgui::add_group -name "External Memory Interface" -component $cc \ + -parent $page0 -display_name "External Memory Interface"] + +set p [ipgui::get_guiparamspec -name "MEM_TYPE" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $group +set_property -dict [list \ + "display_name" "External Storage Type" \ + "tooltip" "External Storage Type" \ + "widget" "comboBox" \ +] $p + +set p [ipgui::get_guiparamspec -name "NUM_M" -component $cc] +ipgui::move_param -component $cc -order 1 $p -parent $group +set_property -dict [list \ + "display_name" "Number of AXI Masters" \ + "tooltip" "Number of AXI masters the data stream bus is split" \ + "widget" "comboBox" \ +] $p + +set p [ipgui::get_guiparamspec -name "AXI_PROTOCOL" -component $cc] +ipgui::move_param -component $cc -order 2 $p -parent $group +set_property -dict [list \ + "widget" "comboBox" \ + "display_name" "AXI Protocol" \ +] $p + +set p [ipgui::get_guiparamspec -name "AXI_DATA_WIDTH" -component $cc] +ipgui::move_param -component $cc -order 3 $p -parent $group +set_property -dict [list \ + "display_name" "AXI Data Bus Width" \ + "tooltip" "Bus Width: Memory-Mapped interface with valid range of 32-1024 bits" \ +] $p + +# HBM sub group +set hbm_group [ipgui::add_group -name "HBM Interface" -component $cc \ + -parent $group -display_name "HBM Interface"] + +set p [ipgui::get_guiparamspec -name "HBM_SEGMENTS_PER_MASTER" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $hbm_group +set_property -dict [list \ + "widget" {textEdit} \ + "display_name" "HBM sections per master" \ + "tooltip" "HBM sections (2Gb/256MB pseudo channels) per master" \ +] $p + +set p [ipgui::get_guiparamspec -name "HBM_SEGMENT_INDEX" -component $cc] +ipgui::move_param -component $cc -order 1 $p -parent $hbm_group +set_property -dict [list \ + "display_name" "First HBM section index" \ + "tooltip" "First used HBM section (2Gb pseudo channels).The base address where data is stored is generated based on this parameter" \ + "widget" "comboBox" \ +] $p + +# DDR sub group +set hbm_group [ipgui::add_group -name "DDR Interface" -component $cc \ + -parent $group -display_name "DDR Interface"] + +set p [ipgui::get_guiparamspec -name "DDR_BASE_ADDDRESS" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $hbm_group +set_property -dict [list \ + "display_name" "DDR base address" \ + "tooltip" "The base address where data is stored is generated based on this parameter" \ +] $p + +ipgui::remove_param -component $cc [ipgui::get_guiparamspec -name "AXI_ADDR_WIDTH" -component $cc] + +ipx::create_xgui_files [ipx::current_core] +ipx::save_core [ipx::current_core] diff --git a/adi_library/util_hbm/util_hbm_ooc.ttcl b/adi_library/util_hbm/util_hbm_ooc.ttcl new file mode 100644 index 00000000..bc0ab3a6 --- /dev/null +++ b/adi_library/util_hbm/util_hbm_ooc.ttcl @@ -0,0 +1,20 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +<: setFileUsedIn { out_of_context synthesis implementation } :> +<: ;#Component and file information :> +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName $ComponentName :> +<: setFileExtension "_ooc.xdc" :> + +# This XDC is used only for OOC mode of synthesis, implementation. +# These are default values for timing driven synthesis during OOC flow. +# These values will be overwritten during implementation with information +# from top level. + +create_clock -name s_axis_aclk -period 2.5 [get_ports s_axis_aclk] +create_clock -name m_axis_aclk -period 2.5 [get_ports m_axis_aclk] +create_clock -name m_axi_aclk -period 2.5 [get_ports m_axi_aclk] diff --git a/adi_library/util_hbm/xgui/util_hbm_v1_0.tcl b/adi_library/util_hbm/xgui/util_hbm_v1_0.tcl new file mode 100644 index 00000000..99b583fe --- /dev/null +++ b/adi_library/util_hbm/xgui/util_hbm_v1_0.tcl @@ -0,0 +1,273 @@ + +# Loading additional proc with user specified bodies to compute parameter values. +source [file join [file dirname [file dirname [info script]]] gui/util_hbm_v1_0.gtcl] + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + #Adding Group + set General_Settings [ipgui::add_group $IPINST -name "General Settings" -parent ${Page_0}] + ipgui::add_param $IPINST -name "TX_RX_N" -parent ${General_Settings} -widget comboBox + set LENGTH_WIDTH [ipgui::add_param $IPINST -name "LENGTH_WIDTH" -parent ${General_Settings}] + set_property tooltip {Defines the amount of data can be stored starting from the base address of the storage.} ${LENGTH_WIDTH} + + #Adding Group + set Data_Offload_Interface [ipgui::add_group $IPINST -name "Data Offload Interface" -parent ${Page_0}] + set SRC_DATA_WIDTH [ipgui::add_param $IPINST -name "SRC_DATA_WIDTH" -parent ${Data_Offload_Interface}] + set_property tooltip {Source AXIS Bus Width (s_axis)} ${SRC_DATA_WIDTH} + set SRC_FIFO_SIZE [ipgui::add_param $IPINST -name "SRC_FIFO_SIZE" -parent ${Data_Offload_Interface} -widget comboBox] + set_property tooltip {Size of internal data mover buffer used for write to external memory. In AXI bursts, where one burst is max 4096 bytes or 2*AXI_DATA_WIDTH bytes for AXI3 or 32*AXI_DATA_WIDTH bytes for AXI4.} ${SRC_FIFO_SIZE} + set DST_DATA_WIDTH [ipgui::add_param $IPINST -name "DST_DATA_WIDTH" -parent ${Data_Offload_Interface}] + set_property tooltip {Destination AXIS Bus Width (m_axis)} ${DST_DATA_WIDTH} + set DST_FIFO_SIZE [ipgui::add_param $IPINST -name "DST_FIFO_SIZE" -parent ${Data_Offload_Interface} -widget comboBox] + set_property tooltip {Size of internal data mover buffer used for read from the external memory. In AXI bursts, where one burst is max 4096 bytes or 2*AXI_DATA_WIDTH bytes for AXI3 or 32*AXI_DATA_WIDTH bytes for AXI4.} ${DST_FIFO_SIZE} + + #Adding Group + set External_Memory_Interface [ipgui::add_group $IPINST -name "External Memory Interface" -parent ${Page_0}] + ipgui::add_param $IPINST -name "MEM_TYPE" -parent ${External_Memory_Interface} -widget comboBox + set NUM_M [ipgui::add_param $IPINST -name "NUM_M" -parent ${External_Memory_Interface} -widget comboBox] + set_property tooltip {Number of AXI masters the data stream bus is split} ${NUM_M} + ipgui::add_param $IPINST -name "AXI_PROTOCOL" -parent ${External_Memory_Interface} -widget comboBox + set AXI_DATA_WIDTH [ipgui::add_param $IPINST -name "AXI_DATA_WIDTH" -parent ${External_Memory_Interface}] + set_property tooltip {Bus Width: Memory-Mapped interface with valid range of 32-1024 bits} ${AXI_DATA_WIDTH} + #Adding Group + set HBM_Interface [ipgui::add_group $IPINST -name "HBM Interface" -parent ${External_Memory_Interface}] + set HBM_SEGMENTS_PER_MASTER [ipgui::add_param $IPINST -name "HBM_SEGMENTS_PER_MASTER" -parent ${HBM_Interface}] + set_property tooltip {HBM sections (2Gb/256MB pseudo channels) per master} ${HBM_SEGMENTS_PER_MASTER} + set HBM_SEGMENT_INDEX [ipgui::add_param $IPINST -name "HBM_SEGMENT_INDEX" -parent ${HBM_Interface} -widget comboBox] + set_property tooltip {First used HBM section (2Gb pseudo channels).The base address where data is stored is generated based on this parameter} ${HBM_SEGMENT_INDEX} + + #Adding Group + set DDR_Interface [ipgui::add_group $IPINST -name "DDR Interface" -parent ${External_Memory_Interface}] + set DDR_BASE_ADDDRESS [ipgui::add_param $IPINST -name "DDR_BASE_ADDDRESS" -parent ${DDR_Interface}] + set_property tooltip {The base address where data is stored is generated based on this parameter} ${DDR_BASE_ADDDRESS} + + + + +} + +proc update_PARAM_VALUE.DDR_BASE_ADDDRESS { PARAM_VALUE.DDR_BASE_ADDDRESS PARAM_VALUE.MEM_TYPE } { + # Procedure called to update DDR_BASE_ADDDRESS when any of the dependent parameters in the arguments change + + set DDR_BASE_ADDDRESS ${PARAM_VALUE.DDR_BASE_ADDDRESS} + set MEM_TYPE ${PARAM_VALUE.MEM_TYPE} + set values(MEM_TYPE) [get_property value $MEM_TYPE] + if { [gen_USERPARAMETER_DDR_BASE_ADDDRESS_ENABLEMENT $values(MEM_TYPE)] } { + set_property enabled true $DDR_BASE_ADDDRESS + } else { + set_property enabled false $DDR_BASE_ADDDRESS + } +} + +proc validate_PARAM_VALUE.DDR_BASE_ADDDRESS { PARAM_VALUE.DDR_BASE_ADDDRESS } { + # Procedure called to validate DDR_BASE_ADDDRESS + return true +} + +proc update_PARAM_VALUE.HBM_SEGMENTS_PER_MASTER { PARAM_VALUE.HBM_SEGMENTS_PER_MASTER PARAM_VALUE.LENGTH_WIDTH PARAM_VALUE.NUM_M } { + # Procedure called to update HBM_SEGMENTS_PER_MASTER when any of the dependent parameters in the arguments change + + set HBM_SEGMENTS_PER_MASTER ${PARAM_VALUE.HBM_SEGMENTS_PER_MASTER} + set LENGTH_WIDTH ${PARAM_VALUE.LENGTH_WIDTH} + set NUM_M ${PARAM_VALUE.NUM_M} + set values(LENGTH_WIDTH) [get_property value $LENGTH_WIDTH] + set values(NUM_M) [get_property value $NUM_M] + set_property value [gen_USERPARAMETER_HBM_SEGMENTS_PER_MASTER_VALUE $values(LENGTH_WIDTH) $values(NUM_M)] $HBM_SEGMENTS_PER_MASTER +} + +proc validate_PARAM_VALUE.HBM_SEGMENTS_PER_MASTER { PARAM_VALUE.HBM_SEGMENTS_PER_MASTER } { + # Procedure called to validate HBM_SEGMENTS_PER_MASTER + return true +} + +proc update_PARAM_VALUE.HBM_SEGMENT_INDEX { PARAM_VALUE.HBM_SEGMENT_INDEX PARAM_VALUE.MEM_TYPE } { + # Procedure called to update HBM_SEGMENT_INDEX when any of the dependent parameters in the arguments change + + set HBM_SEGMENT_INDEX ${PARAM_VALUE.HBM_SEGMENT_INDEX} + set MEM_TYPE ${PARAM_VALUE.MEM_TYPE} + set values(MEM_TYPE) [get_property value $MEM_TYPE] + if { [gen_USERPARAMETER_HBM_SEGMENT_INDEX_ENABLEMENT $values(MEM_TYPE)] } { + set_property enabled true $HBM_SEGMENT_INDEX + } else { + set_property enabled false $HBM_SEGMENT_INDEX + } +} + +proc validate_PARAM_VALUE.HBM_SEGMENT_INDEX { PARAM_VALUE.HBM_SEGMENT_INDEX } { + # Procedure called to validate HBM_SEGMENT_INDEX + return true +} + +proc update_PARAM_VALUE.AXI_ADDR_WIDTH { PARAM_VALUE.AXI_ADDR_WIDTH } { + # Procedure called to update AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_ADDR_WIDTH { PARAM_VALUE.AXI_ADDR_WIDTH } { + # Procedure called to validate AXI_ADDR_WIDTH + return true +} + +proc update_PARAM_VALUE.AXI_DATA_WIDTH { PARAM_VALUE.AXI_DATA_WIDTH } { + # Procedure called to update AXI_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_DATA_WIDTH { PARAM_VALUE.AXI_DATA_WIDTH } { + # Procedure called to validate AXI_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.AXI_PROTOCOL { PARAM_VALUE.AXI_PROTOCOL } { + # Procedure called to update AXI_PROTOCOL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_PROTOCOL { PARAM_VALUE.AXI_PROTOCOL } { + # Procedure called to validate AXI_PROTOCOL + return true +} + +proc update_PARAM_VALUE.DST_DATA_WIDTH { PARAM_VALUE.DST_DATA_WIDTH } { + # Procedure called to update DST_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DST_DATA_WIDTH { PARAM_VALUE.DST_DATA_WIDTH } { + # Procedure called to validate DST_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.DST_FIFO_SIZE { PARAM_VALUE.DST_FIFO_SIZE } { + # Procedure called to update DST_FIFO_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DST_FIFO_SIZE { PARAM_VALUE.DST_FIFO_SIZE } { + # Procedure called to validate DST_FIFO_SIZE + return true +} + +proc update_PARAM_VALUE.LENGTH_WIDTH { PARAM_VALUE.LENGTH_WIDTH } { + # Procedure called to update LENGTH_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.LENGTH_WIDTH { PARAM_VALUE.LENGTH_WIDTH } { + # Procedure called to validate LENGTH_WIDTH + return true +} + +proc update_PARAM_VALUE.MEM_TYPE { PARAM_VALUE.MEM_TYPE } { + # Procedure called to update MEM_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.MEM_TYPE { PARAM_VALUE.MEM_TYPE } { + # Procedure called to validate MEM_TYPE + return true +} + +proc update_PARAM_VALUE.NUM_M { PARAM_VALUE.NUM_M } { + # Procedure called to update NUM_M when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_M { PARAM_VALUE.NUM_M } { + # Procedure called to validate NUM_M + return true +} + +proc update_PARAM_VALUE.SRC_DATA_WIDTH { PARAM_VALUE.SRC_DATA_WIDTH } { + # Procedure called to update SRC_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SRC_DATA_WIDTH { PARAM_VALUE.SRC_DATA_WIDTH } { + # Procedure called to validate SRC_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.SRC_FIFO_SIZE { PARAM_VALUE.SRC_FIFO_SIZE } { + # Procedure called to update SRC_FIFO_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SRC_FIFO_SIZE { PARAM_VALUE.SRC_FIFO_SIZE } { + # Procedure called to validate SRC_FIFO_SIZE + return true +} + +proc update_PARAM_VALUE.TX_RX_N { PARAM_VALUE.TX_RX_N } { + # Procedure called to update TX_RX_N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TX_RX_N { PARAM_VALUE.TX_RX_N } { + # Procedure called to validate TX_RX_N + return true +} + + +proc update_MODELPARAM_VALUE.TX_RX_N { MODELPARAM_VALUE.TX_RX_N PARAM_VALUE.TX_RX_N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TX_RX_N}] ${MODELPARAM_VALUE.TX_RX_N} +} + +proc update_MODELPARAM_VALUE.SRC_DATA_WIDTH { MODELPARAM_VALUE.SRC_DATA_WIDTH PARAM_VALUE.SRC_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SRC_DATA_WIDTH}] ${MODELPARAM_VALUE.SRC_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.DST_DATA_WIDTH { MODELPARAM_VALUE.DST_DATA_WIDTH PARAM_VALUE.DST_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DST_DATA_WIDTH}] ${MODELPARAM_VALUE.DST_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.LENGTH_WIDTH { MODELPARAM_VALUE.LENGTH_WIDTH PARAM_VALUE.LENGTH_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LENGTH_WIDTH}] ${MODELPARAM_VALUE.LENGTH_WIDTH} +} + +proc update_MODELPARAM_VALUE.AXI_PROTOCOL { MODELPARAM_VALUE.AXI_PROTOCOL PARAM_VALUE.AXI_PROTOCOL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_PROTOCOL}] ${MODELPARAM_VALUE.AXI_PROTOCOL} +} + +proc update_MODELPARAM_VALUE.AXI_DATA_WIDTH { MODELPARAM_VALUE.AXI_DATA_WIDTH PARAM_VALUE.AXI_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.AXI_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.AXI_ADDR_WIDTH { MODELPARAM_VALUE.AXI_ADDR_WIDTH PARAM_VALUE.AXI_ADDR_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.AXI_ADDR_WIDTH} +} + +proc update_MODELPARAM_VALUE.MEM_TYPE { MODELPARAM_VALUE.MEM_TYPE PARAM_VALUE.MEM_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.MEM_TYPE}] ${MODELPARAM_VALUE.MEM_TYPE} +} + +proc update_MODELPARAM_VALUE.HBM_SEGMENTS_PER_MASTER { MODELPARAM_VALUE.HBM_SEGMENTS_PER_MASTER PARAM_VALUE.HBM_SEGMENTS_PER_MASTER } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.HBM_SEGMENTS_PER_MASTER}] ${MODELPARAM_VALUE.HBM_SEGMENTS_PER_MASTER} +} + +proc update_MODELPARAM_VALUE.HBM_SEGMENT_INDEX { MODELPARAM_VALUE.HBM_SEGMENT_INDEX PARAM_VALUE.HBM_SEGMENT_INDEX } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.HBM_SEGMENT_INDEX}] ${MODELPARAM_VALUE.HBM_SEGMENT_INDEX} +} + +proc update_MODELPARAM_VALUE.DDR_BASE_ADDDRESS { MODELPARAM_VALUE.DDR_BASE_ADDDRESS PARAM_VALUE.DDR_BASE_ADDDRESS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DDR_BASE_ADDDRESS}] ${MODELPARAM_VALUE.DDR_BASE_ADDDRESS} +} + +proc update_MODELPARAM_VALUE.NUM_M { MODELPARAM_VALUE.NUM_M PARAM_VALUE.NUM_M } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_M}] ${MODELPARAM_VALUE.NUM_M} +} + +proc update_MODELPARAM_VALUE.SRC_FIFO_SIZE { MODELPARAM_VALUE.SRC_FIFO_SIZE PARAM_VALUE.SRC_FIFO_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SRC_FIFO_SIZE}] ${MODELPARAM_VALUE.SRC_FIFO_SIZE} +} + +proc update_MODELPARAM_VALUE.DST_FIFO_SIZE { MODELPARAM_VALUE.DST_FIFO_SIZE PARAM_VALUE.DST_FIFO_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DST_FIFO_SIZE}] ${MODELPARAM_VALUE.DST_FIFO_SIZE} +} + diff --git a/adi_library/util_i2c_mixer/Makefile b/adi_library/util_i2c_mixer/Makefile new file mode 100644 index 00000000..78cf821a --- /dev/null +++ b/adi_library/util_i2c_mixer/Makefile @@ -0,0 +1,13 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_i2c_mixer + +GENERIC_DEPS += util_i2c_mixer.vhd + +XILINX_DEPS += util_i2c_mixer_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/util_i2c_mixer/component.xml b/adi_library/util_i2c_mixer/component.xml new file mode 100644 index 00000000..2e3f3fd1 --- /dev/null +++ b/adi_library/util_i2c_mixer/component.xml @@ -0,0 +1,382 @@ + + + analog.com + user + util_i2c_mixer + 1.0 + + + upstream + + + + + + + SCL_O + + + upstream_scl_I + + + + + SCL_I + + + upstream_scl_O + + + + + SCL_T + + + upstream_scl_T + + + + + SDA_O + + + upstream_sda_I + + + + + SDA_I + + + upstream_sda_O + + + + + SDA_T + + + upstream_sda_T + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + VHDL + util_i2c_mixer + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 4ee188af + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + VHDL + util_i2c_mixer + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 4ee188af + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + e0d8b21d + + + + + + + upstream_scl_T + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + upstream_scl_I + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + upstream_scl_O + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + upstream_sda_T + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + upstream_sda_I + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + upstream_sda_O + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + downstream_scl_T + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + downstream_scl_I + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + downstream_scl_O + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + downstream_sda_T + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + downstream_sda_I + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + downstream_sda_O + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + C_WIDTH + C Width + 2 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + util_i2c_mixer.vhd + vhdlSource + CHECKSUM_4ee188af + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + util_i2c_mixer.vhd + vhdlSource + + + + xilinx_xpgui_view_fileset + + xgui/util_i2c_mixer_v1_0.tcl + tclSource + CHECKSUM_e0d8b21d + XGUI_VERSION_2 + + + + util_i2c_mixer_v1_0 + + + C_WIDTH + C Width + 2 + + + Component_Name + util_i2c_mixer_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + util_i2c_mixer_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:55:27Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_i2c_mixer/util_i2c_mixer.vhd b/adi_library/util_i2c_mixer/util_i2c_mixer.vhd new file mode 100644 index 00000000..c24d96dd --- /dev/null +++ b/adi_library/util_i2c_mixer/util_i2c_mixer.vhd @@ -0,0 +1,80 @@ +-- *************************************************************************** +-- *************************************************************************** +-- Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +-- +-- In this HDL repository, there are many different and unique modules, consisting +-- of various HDL (Verilog or VHDL) components. The individual modules are +-- developed independently, and may be accompanied by separate and unique license +-- terms. +-- +-- The user should read each of these license terms, and understand the +-- freedoms and responsibilities that he or she has by using this source/core. +-- +-- This core is distributed in the hope that it will be useful, but WITHOUT ANY +-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +-- A PARTICULAR PURPOSE. +-- +-- Redistribution and use of source or resulting binaries, with or without modification +-- of this file, are permitted under one of the following two license terms: +-- +-- 1. The GNU General Public License version 2 as published by the +-- Free Software Foundation, which can be found in the top level directory +-- of this repository (LICENSE_GPL2), and also online at: +-- +-- +-- OR +-- +-- 2. An ADI specific BSD license, which can be found in the top level directory +-- of this repository (LICENSE_ADIBSD), and also on-line at: +-- https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +-- This will allow to generate bit files and not release the source code, +-- as long as it attaches to an ADI device. +-- +-- *************************************************************************** +-- *************************************************************************** + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library unisim; +use unisim.all; + +entity util_i2c_mixer is + generic ( + C_WIDTH: integer := 2 + ); + port ( + upstream_scl_T : in std_logic; + upstream_scl_I : in std_logic; + upstream_scl_O : out std_logic; + upstream_sda_T : in std_logic; + upstream_sda_I : in std_logic; + upstream_sda_O : out std_logic; + + downstream_scl_T : out std_logic; + downstream_scl_I : in std_logic_vector(C_WIDTH - 1 downto 0); + downstream_scl_O : out std_logic_vector(C_WIDTH - 1 downto 0); + downstream_sda_T : out std_logic; + downstream_sda_I : in std_logic_vector(C_WIDTH - 1 downto 0); + downstream_sda_O : out std_logic_vector(C_WIDTH - 1 downto 0) + + ); +end util_i2c_mixer; + +architecture IMP of util_i2c_mixer is +begin + +upstream_scl_O <= '1' when (downstream_scl_I = (downstream_scl_I'range => '1')) else '0'; +upstream_sda_O <= '1' when (downstream_sda_I = (downstream_sda_I'range => '1')) else '0'; + +downstream_scl_T <= upstream_scl_T; +downstream_sda_T <= upstream_sda_T; + +GEN: for i in 0 to C_WIDTH - 1 generate + downstream_scl_O(i) <= upstream_scl_I; + downstream_sda_O(i) <= upstream_sda_I; +end generate GEN; + +end IMP; diff --git a/adi_library/util_i2c_mixer/util_i2c_mixer.xpr b/adi_library/util_i2c_mixer/util_i2c_mixer.xpr new file mode 100644 index 00000000..0478c956 --- /dev/null +++ b/adi_library/util_i2c_mixer/util_i2c_mixer.xpr @@ -0,0 +1,398 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_i2c_mixer/util_i2c_mixer_ip.tcl b/adi_library/util_i2c_mixer/util_i2c_mixer_ip.tcl new file mode 100644 index 00000000..eca01ac2 --- /dev/null +++ b/adi_library/util_i2c_mixer/util_i2c_mixer_ip.tcl @@ -0,0 +1,29 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_i2c_mixer +adi_ip_files util_i2c_mixer [list \ + "util_i2c_mixer.vhd" ] + +adi_ip_properties_lite util_i2c_mixer + + +adi_add_bus "upstream" "slave" \ + "xilinx.com:interface:iic_rtl:1.0" \ + "xilinx.com:interface:iic:1.0" \ + [list \ + {"upstream_scl_I" "SCL_O"} \ + {"upstream_scl_O" "SCL_I"} \ + {"upstream_scl_T" "SCL_T"} \ + {"upstream_sda_I" "SDA_O"} \ + {"upstream_sda_O" "SDA_I"} \ + {"upstream_sda_T" "SDA_T"} \ + ] + +ipx::save_core [ipx::current_core] diff --git a/adi_library/util_i2c_mixer/xgui/util_i2c_mixer_v1_0.tcl b/adi_library/util_i2c_mixer/xgui/util_i2c_mixer_v1_0.tcl new file mode 100644 index 00000000..42a5160f --- /dev/null +++ b/adi_library/util_i2c_mixer/xgui/util_i2c_mixer_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "C_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.C_WIDTH { PARAM_VALUE.C_WIDTH } { + # Procedure called to update C_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.C_WIDTH { PARAM_VALUE.C_WIDTH } { + # Procedure called to validate C_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.C_WIDTH { MODELPARAM_VALUE.C_WIDTH PARAM_VALUE.C_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.C_WIDTH}] ${MODELPARAM_VALUE.C_WIDTH} +} + diff --git a/adi_library/util_mfifo/Makefile b/adi_library/util_mfifo/Makefile new file mode 100644 index 00000000..e66d484c --- /dev/null +++ b/adi_library/util_mfifo/Makefile @@ -0,0 +1,14 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_mfifo + +GENERIC_DEPS += ../common/ad_mem.v +GENERIC_DEPS += util_mfifo.v + +XILINX_DEPS += util_mfifo_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/util_mfifo/component.xml b/adi_library/util_mfifo/component.xml new file mode 100644 index 00000000..31e1df83 --- /dev/null +++ b/adi_library/util_mfifo/component.xml @@ -0,0 +1,733 @@ + + + analog.com + user + util_mfifo + 1.0 + + + din_clk + + + + + + + CLK + + + din_clk + + + + + + ASSOCIATED_RESET + din_rst + + + + + din_rst + + + + + + + RST + + + din_rst + + + + + + dout_clk + + + + + + + CLK + + + dout_clk + + + + + + ASSOCIATED_RESET + dout_rst + + + + + dout_rst + + + + + + + RST + + + dout_rst + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_mfifo + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + d636a054 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_mfifo + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + d636a054 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + c91cec2f + + + + + + + din_rst + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + din_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + din_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + din_data_0 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + din_data_1 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + din_data_2 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + din_data_3 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + din_data_4 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + din_data_5 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + din_data_6 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + din_data_7 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dout_rst + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dout_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dout_valid + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dout_data_0 + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dout_data_1 + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + dout_data_2 + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + dout_data_3 + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + dout_data_4 + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout_data_5 + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout_data_6 + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout_data_7 + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + + + NUM_OF_CHANNELS + Num Of Channels + 4 + + + DIN_DATA_WIDTH + Din Data Width + 32 + + + ADDRESS_WIDTH + Address Width + 8 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../common/ad_mem.v + verilogSource + + + util_mfifo.v + verilogSource + CHECKSUM_86db3630 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_mem.v + verilogSource + + + util_mfifo.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/util_mfifo_v1_0.tcl + tclSource + CHECKSUM_c91cec2f + XGUI_VERSION_2 + + + + util_mfifo_v1_0 + + + NUM_OF_CHANNELS + Num Of Channels + 4 + + + DIN_DATA_WIDTH + Din Data Width + 32 + + + ADDRESS_WIDTH + Address Width + 8 + + + Component_Name + util_mfifo_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + util_mfifo_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:55:35Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_mfifo/util_mfifo.v b/adi_library/util_mfifo/util_mfifo.v new file mode 100644 index 00000000..0d9acffc --- /dev/null +++ b/adi_library/util_mfifo/util_mfifo.v @@ -0,0 +1,272 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_mfifo #( + + parameter NUM_OF_CHANNELS = 4, + parameter DIN_DATA_WIDTH = 32, + parameter ADDRESS_WIDTH = 8 +) ( + + // d-in interface + + input din_rst, + input din_clk, + input din_valid, + input [DIN_DATA_WIDTH-1:0] din_data_0, + input [DIN_DATA_WIDTH-1:0] din_data_1, + input [DIN_DATA_WIDTH-1:0] din_data_2, + input [DIN_DATA_WIDTH-1:0] din_data_3, + input [DIN_DATA_WIDTH-1:0] din_data_4, + input [DIN_DATA_WIDTH-1:0] din_data_5, + input [DIN_DATA_WIDTH-1:0] din_data_6, + input [DIN_DATA_WIDTH-1:0] din_data_7, + + // d-out interface + + input dout_rst, + input dout_clk, + output reg dout_valid, + output [15:0] dout_data_0, + output [15:0] dout_data_1, + output [15:0] dout_data_2, + output [15:0] dout_data_3, + output [15:0] dout_data_4, + output [15:0] dout_data_5, + output [15:0] dout_data_6, + output [15:0] dout_data_7 +); + + // internal registers + + reg din_dout_toggle_m1 = 'd0; + reg din_dout_toggle_m2 = 'd0; + reg din_dout_toggle_m3 = 'd0; + reg din_wr = 'd0; + reg [(ADDRESS_WIDTH-1):0] din_waddr = 'd0; + reg din_enable = 'd0; + reg din_toggle = 'd0; + reg dout_din_toggle_m1 = 'd0; + reg dout_din_toggle_m2 = 'd0; + reg dout_din_toggle_m3 = 'd0; + reg [ 4:0] dout_cnt = 'd0; + reg dout_ld = 'd0; + reg dout_ld_d = 'd0; + reg [(ADDRESS_WIDTH-1):0] dout_raddr = 'd0; + reg dout_enable = 'd0; + reg dout_toggle = 'd0; + reg [(DIN_DATA_WIDTH-1):0] dout_rdata_0 = 'd0; + reg [(DIN_DATA_WIDTH-1):0] dout_rdata_1 = 'd0; + reg [(DIN_DATA_WIDTH-1):0] dout_rdata_2 = 'd0; + reg [(DIN_DATA_WIDTH-1):0] dout_rdata_3 = 'd0; + reg [(DIN_DATA_WIDTH-1):0] dout_rdata_4 = 'd0; + reg [(DIN_DATA_WIDTH-1):0] dout_rdata_5 = 'd0; + reg [(DIN_DATA_WIDTH-1):0] dout_rdata_6 = 'd0; + reg [(DIN_DATA_WIDTH-1):0] dout_rdata_7 = 'd0; + + // internal signals + + wire [(DIN_DATA_WIDTH-1):0] din_wdata_s[0:7]; + wire din_waddr_max_s; + wire din_dout_toggle_s; + wire dout_raddr_max_s; + wire dout_rd_s; + wire dout_din_toggle_s; + wire [(DIN_DATA_WIDTH-1):0] dout_rdata_s[0:7]; + + // variables + + genvar n; + + // write interface + + assign din_wdata_s[7] = din_data_7; + assign din_wdata_s[6] = din_data_6; + assign din_wdata_s[5] = din_data_5; + assign din_wdata_s[4] = din_data_4; + assign din_wdata_s[3] = din_data_3; + assign din_wdata_s[2] = din_data_2; + assign din_wdata_s[1] = din_data_1; + assign din_wdata_s[0] = din_data_0; + assign din_waddr_max_s = & din_waddr; + assign din_dout_toggle_s = din_dout_toggle_m3 ^ din_dout_toggle_m2; + + always @(posedge din_clk or posedge din_rst) begin + if (din_rst == 1'b1) begin + din_dout_toggle_m1 <= 1'd0; + din_dout_toggle_m2 <= 1'd0; + din_dout_toggle_m3 <= 1'd0; + din_wr <= 1'd0; + din_waddr <= 'd0; + din_enable <= 1'd0; + din_toggle <= 1'd0; + end else begin + din_dout_toggle_m1 <= dout_toggle; + din_dout_toggle_m2 <= din_dout_toggle_m1; + din_dout_toggle_m3 <= din_dout_toggle_m2; + din_wr <= din_valid & din_enable; + if (din_dout_toggle_s == 1'b1) begin + din_waddr <= 'd0; + din_enable <= 1'b1; + end else if (din_wr == 1'b1) begin + din_waddr <= din_waddr + 1'b1; + if (din_waddr_max_s == 1) begin + din_enable <= 1'b0; + end + end + if ((din_wr == 1'b1) && (din_waddr_max_s == 1)) begin + din_toggle <= ~din_toggle; + end + end + end + + // read interface + + assign dout_raddr_max_s = & dout_raddr; + assign dout_rd_s = (dout_cnt == 5'd0) ? dout_enable : 1'b0; + assign dout_din_toggle_s = dout_din_toggle_m3 ^ dout_din_toggle_m2; + + always @(posedge dout_clk or posedge dout_rst) begin + if (dout_rst == 1'b1) begin + dout_din_toggle_m1 <= 1'd0; + dout_din_toggle_m2 <= 1'd0; + dout_din_toggle_m3 <= 1'd0; + dout_cnt <= 'd0; + dout_ld <= 'd0; + dout_ld_d <= 'd0; + dout_raddr <= 'd0; + dout_enable <= 1'd0; + dout_toggle <= 1'd1; + end else begin + dout_din_toggle_m1 <= din_toggle; + dout_din_toggle_m2 <= dout_din_toggle_m1; + dout_din_toggle_m3 <= dout_din_toggle_m2; + if ((dout_din_toggle_s == 1'b1) || (dout_cnt >= ((DIN_DATA_WIDTH/16) - 1))) begin + dout_cnt <= 'd0; + end else begin + dout_cnt <= dout_cnt + 1'b1; + end + dout_ld <= | dout_cnt; + dout_ld_d <= dout_ld; + if (dout_din_toggle_s == 1'b1) begin + dout_raddr <= 'd0; + dout_enable <= 1'b1; + end else if (dout_rd_s == 1'b1) begin + dout_raddr <= dout_raddr + 1'b1; + if (dout_raddr_max_s == 1'b1) begin + dout_enable <= 1'b0; + end + end + if ((dout_rd_s == 1'b1) && (dout_raddr_max_s == 1'b1)) begin + dout_toggle <= ~dout_toggle; + end + end + end + + always @(posedge dout_clk or posedge dout_rst) begin + if (dout_rst == 1'b1) begin + dout_valid <= 'd0; + dout_rdata_0 <= 'd0; + dout_rdata_1 <= 'd0; + dout_rdata_2 <= 'd0; + dout_rdata_3 <= 'd0; + dout_rdata_4 <= 'd0; + dout_rdata_5 <= 'd0; + dout_rdata_6 <= 'd0; + dout_rdata_7 <= 'd0; + end else begin + if (dout_ld_d == 1'b0) begin + dout_valid <= dout_enable; + dout_rdata_0 <= dout_rdata_s[0]; + dout_rdata_1 <= dout_rdata_s[1]; + dout_rdata_2 <= dout_rdata_s[2]; + dout_rdata_3 <= dout_rdata_s[3]; + dout_rdata_4 <= dout_rdata_s[4]; + dout_rdata_5 <= dout_rdata_s[5]; + dout_rdata_6 <= dout_rdata_s[6]; + dout_rdata_7 <= dout_rdata_s[7]; + end else begin + dout_valid <= dout_valid; + dout_rdata_0 <= {16'd0, dout_rdata_0[(DIN_DATA_WIDTH-1):16]}; + dout_rdata_1 <= {16'd0, dout_rdata_1[(DIN_DATA_WIDTH-1):16]}; + dout_rdata_2 <= {16'd0, dout_rdata_2[(DIN_DATA_WIDTH-1):16]}; + dout_rdata_3 <= {16'd0, dout_rdata_3[(DIN_DATA_WIDTH-1):16]}; + dout_rdata_4 <= {16'd0, dout_rdata_4[(DIN_DATA_WIDTH-1):16]}; + dout_rdata_5 <= {16'd0, dout_rdata_5[(DIN_DATA_WIDTH-1):16]}; + dout_rdata_6 <= {16'd0, dout_rdata_6[(DIN_DATA_WIDTH-1):16]}; + dout_rdata_7 <= {16'd0, dout_rdata_7[(DIN_DATA_WIDTH-1):16]}; + end + end + end + + assign dout_data_0 = dout_rdata_0[15:0]; + assign dout_data_1 = dout_rdata_1[15:0]; + assign dout_data_2 = dout_rdata_2[15:0]; + assign dout_data_3 = dout_rdata_3[15:0]; + assign dout_data_4 = dout_rdata_4[15:0]; + assign dout_data_5 = dout_rdata_5[15:0]; + assign dout_data_6 = dout_rdata_6[15:0]; + assign dout_data_7 = dout_rdata_7[15:0]; + + // instantiations + + generate + + if (NUM_OF_CHANNELS < 8) begin + for (n = NUM_OF_CHANNELS; n < 8; n = n + 1) begin: g_channels_unused + assign dout_rdata_s[n] = 'd0; + end + end + + for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_channels + ad_mem #( + .ADDRESS_WIDTH (ADDRESS_WIDTH), + .DATA_WIDTH (DIN_DATA_WIDTH) + ) i_mem ( + .clka (din_clk), + .wea (din_wr), + .addra (din_waddr), + .dina (din_wdata_s[n]), + .clkb (dout_clk), + .reb (1'b1), + .addrb (dout_raddr), + .doutb (dout_rdata_s[n])); + end + + endgenerate + +endmodule diff --git a/adi_library/util_mfifo/util_mfifo.xpr b/adi_library/util_mfifo/util_mfifo.xpr new file mode 100644 index 00000000..060665cb --- /dev/null +++ b/adi_library/util_mfifo/util_mfifo.xpr @@ -0,0 +1,406 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_mfifo/util_mfifo_constr.xdc b/adi_library/util_mfifo/util_mfifo_constr.xdc new file mode 100644 index 00000000..45842028 --- /dev/null +++ b/adi_library/util_mfifo/util_mfifo_constr.xdc @@ -0,0 +1,13 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property SHREG_EXTRACT NO [get_cells -hier *din_dout_toggle_m*] +set_property SHREG_EXTRACT NO [get_cells -hier *dout_din_toggle_m*] + +set_false_path -from [get_cells -hier *dout_toggle* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier *din_dout_toggle_m* -filter {primitive_subgroup == flop}] +set_false_path -from [get_cells -hier *din_toggle* -filter {primitive_subgroup == flop}] \ + -to [get_cells -hier *dout_din_toggle_m* -filter {primitive_subgroup == flop}] + diff --git a/adi_library/util_mfifo/util_mfifo_ip.tcl b/adi_library/util_mfifo/util_mfifo_ip.tcl new file mode 100644 index 00000000..4d579d66 --- /dev/null +++ b/adi_library/util_mfifo/util_mfifo_ip.tcl @@ -0,0 +1,43 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_mfifo +adi_ip_files util_mfifo [list \ + "$ad_hdl_dir/library/common/ad_mem.v" \ + "util_mfifo.v" ] + +adi_ip_properties_lite util_mfifo + +ipx::remove_all_bus_interface [ipx::current_core] +set_property driver_value 0 [ipx::get_ports *din_valid* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *din_data* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1} \ + [ipx::get_ports *_1* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2} \ + [ipx::get_ports *_2* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3} \ + [ipx::get_ports *_3* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4} \ + [ipx::get_ports *_4* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5} \ + [ipx::get_ports *_5* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6} \ + [ipx::get_ports *_6* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7} \ + [ipx::get_ports *_7* -of_objects [ipx::current_core]] + +ipx::infer_bus_interface din_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface din_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +ipx::infer_bus_interface dout_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface dout_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] + + diff --git a/adi_library/util_mfifo/xgui/util_mfifo_v1_0.tcl b/adi_library/util_mfifo/xgui/util_mfifo_v1_0.tcl new file mode 100644 index 00000000..c70acee7 --- /dev/null +++ b/adi_library/util_mfifo/xgui/util_mfifo_v1_0.tcl @@ -0,0 +1,55 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ADDRESS_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "DIN_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_OF_CHANNELS" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } { + # Procedure called to update ADDRESS_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } { + # Procedure called to validate ADDRESS_WIDTH + return true +} + +proc update_PARAM_VALUE.DIN_DATA_WIDTH { PARAM_VALUE.DIN_DATA_WIDTH } { + # Procedure called to update DIN_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DIN_DATA_WIDTH { PARAM_VALUE.DIN_DATA_WIDTH } { + # Procedure called to validate DIN_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to update NUM_OF_CHANNELS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to validate NUM_OF_CHANNELS + return true +} + + +proc update_MODELPARAM_VALUE.NUM_OF_CHANNELS { MODELPARAM_VALUE.NUM_OF_CHANNELS PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_CHANNELS}] ${MODELPARAM_VALUE.NUM_OF_CHANNELS} +} + +proc update_MODELPARAM_VALUE.DIN_DATA_WIDTH { MODELPARAM_VALUE.DIN_DATA_WIDTH PARAM_VALUE.DIN_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DIN_DATA_WIDTH}] ${MODELPARAM_VALUE.DIN_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.ADDRESS_WIDTH { MODELPARAM_VALUE.ADDRESS_WIDTH PARAM_VALUE.ADDRESS_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADDRESS_WIDTH}] ${MODELPARAM_VALUE.ADDRESS_WIDTH} +} + diff --git a/adi_library/util_mii_to_rmii/Makefile b/adi_library/util_mii_to_rmii/Makefile new file mode 100644 index 00000000..9145f8b7 --- /dev/null +++ b/adi_library/util_mii_to_rmii/Makefile @@ -0,0 +1,15 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_mii_to_rmii + +GENERIC_DEPS += mac_phy_link.v +GENERIC_DEPS += phy_mac_link.v +GENERIC_DEPS += util_mii_to_rmii.v + +XILINX_DEPS += util_mii_to_rmii_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/util_mii_to_rmii/component.xml b/adi_library/util_mii_to_rmii/component.xml new file mode 100644 index 00000000..f843ab28 --- /dev/null +++ b/adi_library/util_mii_to_rmii/component.xml @@ -0,0 +1,702 @@ + + + analog.com + user + util_mii_to_rmii + 1.0 + + + GMII + + + + + + + COL + + + mii_col + + + + + CRS + + + mii_crs + + + + + RXD + + + mii_rxd + + + + + RX_CLK + + + mii_rx_clk + + + + + RX_DV + + + mii_rx_dv + + + + + RX_ER + + + mii_rx_er + + + + + TXD + + + mac_txd + + + + + TX_CLK + + + mii_tx_clk + + + + + TX_EN + + + mac_tx_en + + + + + TX_ER + + + mac_tx_er + + + + + + + false + + + + + + MII + + + + + + + COL + + + mii_col + + + + + CRS + + + mii_crs + + + + + RXD + + + mii_rxd + + + + + RX_CLK + + + mii_rx_clk + + + + + RX_DV + + + mii_rx_dv + + + + + RX_ER + + + mii_rx_er + + + + + TXD + + + mac_txd + + + + + TX_CLK + + + mii_tx_clk + + + + + TX_EN + + + mac_tx_en + + + + + TX_ER + + + mac_tx_er + + + + + + + true + + + + + + RMII + + + + + + + CRS_DV + + + phy_crs_dv + + + + + RXD + + + phy_rxd + + + + + RX_ER + + + phy_rx_er + + + + + TXD + + + rmii_txd + + + + + TX_EN + + + rmii_tx_en + + + + + + reset_n + + + + + + + RST + + + reset_n + + + + + + ref_clk + + + + + + + CLK + + + ref_clk + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_mii_to_rmii + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 7f96d891 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_mii_to_rmii + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 7f96d891 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + c554a0dc + + + + + + + mac_tx_en + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + mac_txd + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + mac_tx_er + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + mii_tx_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + mii_rx_clk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + mii_col + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + mii_crs + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + mii_rx_dv + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + mii_rx_er + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + mii_rxd + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rmii_txd + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rmii_tx_en + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + phy_rxd + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + phy_crs_dv + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + phy_rx_er + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + ref_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + reset_n + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + INTF_CFG + Intf Cfg + 0 + + + RATE_10_100 + Rate 10 100 + 0 + + + + + + choice_pairs_7362e83f + 0 + 1 + + + choice_pairs_bf1c9d7a + 0 + 1 + + + + + xilinx_anylanguagesynthesis_view_fileset + + mac_phy_link.v + verilogSource + + + phy_mac_link.v + verilogSource + + + util_mii_to_rmii.v + verilogSource + CHECKSUM_4eec8a2d + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + mac_phy_link.v + verilogSource + + + phy_mac_link.v + verilogSource + + + util_mii_to_rmii.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/util_mii_to_rmii_v1_0.tcl + tclSource + CHECKSUM_7db2218e + XGUI_VERSION_2 + + + + MII to RMII Converter IP + + + INTF_CFG + Interface Selection + 0 + + + RATE_10_100 + Rate Selection + 0 + + + Component_Name + util_mii_to_rmii_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + util_mii_to_rmii + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:55:44Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_mii_to_rmii/mac_phy_link.v b/adi_library/util_mii_to_rmii/mac_phy_link.v new file mode 100644 index 00000000..5a9e5481 --- /dev/null +++ b/adi_library/util_mii_to_rmii/mac_phy_link.v @@ -0,0 +1,139 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** + +`timescale 1ns/100ps + +module mac_phy_link #( + parameter RATE_10_100 = 0 +) ( + input ref_clk, + input [3:0] mac_txd, + input reset_n, + input mac_tx_en, + input mac_tx_er, + output rmii_tx_en, + output [1:0] rmii_txd, + output mii_tx_clk +); + + wire dibit_sample; + wire [3:0] num_w; + wire tx_dibit; + wire [4:0] reg_count_w; + + reg [3:0] mac_txd_r = 4'b0; + reg mac_tx_en_r = 1'b0; + reg mac_tx_er_r = 1'b0; + reg mii_tx_clk_10_100_r = 1'b0; + reg [3:0] num_r = 4'b0; + reg [1:0] rmii_txd_r = 2'b0; + reg rmii_tx_en_r = 1'b0; + reg rising_tx_clk_r0 = 1'b0; + reg rising_tx_clk_r1 = 1'b0; + reg [4:0] reg_count = 5'b0; + + localparam DIV_REF_CLK = RATE_10_100 ? 10 : 1; + + always @(posedge ref_clk) begin + if (!reset_n) begin + num_r <= 0; + mii_tx_clk_10_100_r <= 1'b0; + end else if (num_w == DIV_REF_CLK) begin + num_r <= 0; + mii_tx_clk_10_100_r <= ~mii_tx_clk_10_100_r; + if (!mii_tx_clk_10_100_r) begin + rising_tx_clk_r0 <= 1'b1; + rising_tx_clk_r1 <= rising_tx_clk_r0; + end else begin + rising_tx_clk_r0 <= 1'b0; + rising_tx_clk_r1 <= rising_tx_clk_r0; + end + rising_tx_clk_r1 <= rising_tx_clk_r0; + end else begin + num_r <= num_w; + end + end + + always @(posedge ref_clk) begin + if (!reset_n) begin + mac_txd_r <= 4'b0; + mac_tx_en_r <= 1'b0; + mac_tx_er_r <= 1'b0; + end else begin + if (dibit_sample == 1'b1) begin + mac_txd_r <= mac_txd; + mac_tx_en_r <= mac_tx_en; + mac_tx_er_r <= mac_tx_er; + end + end + end + + always @(posedge ref_clk) begin + if (!reset_n) begin + rmii_txd_r <= 2'b0; + rmii_tx_en_r <= 1'b0; + end else begin + if (!tx_dibit) begin + rmii_txd_r[0] <= mac_txd_r[0] ^ mac_tx_er_r; + rmii_txd_r[1] <= mac_txd_r[1] | mac_tx_er_r; + rmii_tx_en_r <= mac_tx_en_r; + end else begin + rmii_txd_r[0] <= mac_txd_r[2] ^ mac_tx_er_r; + rmii_txd_r[1] <= mac_txd_r[3] | mac_tx_er_r; + rmii_tx_en_r <= mac_tx_en_r; + end + end + end + + always @(posedge ref_clk) begin + if (!reset_n) begin + reg_count <= 1'b0; + end else begin + if (reg_count_w == 5'b10011) begin + reg_count <= 1'b0; + end else begin + reg_count <= reg_count + 1; + end + end + end + + assign dibit_sample = RATE_10_100 ? ((reg_count_w == 5'b01001) ? 1'b1 : 1'b0) : rising_tx_clk_r1; + assign num_w = num_r + 1; + assign mii_tx_clk = mii_tx_clk_10_100_r; + assign reg_count_w = reg_count; + assign rmii_txd = rmii_txd_r; + assign rmii_tx_en = rmii_tx_en_r; + assign tx_dibit = ~mii_tx_clk; + +endmodule diff --git a/adi_library/util_mii_to_rmii/phy_mac_link.v b/adi_library/util_mii_to_rmii/phy_mac_link.v new file mode 100644 index 00000000..599302ae --- /dev/null +++ b/adi_library/util_mii_to_rmii/phy_mac_link.v @@ -0,0 +1,281 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** + +`timescale 1ns/100ps + +module phy_mac_link #( + parameter RATE_10_100 = 0 +) ( + input ref_clk, + input reset_n, + input [1:0] phy_rxd, + input phy_crs_dv, + input phy_rx_er, + output [3:0] mii_rxd, + output mii_rx_dv, + output mii_rx_er, + output mii_crs, + output mii_col, + output mii_rx_clk +); + + wire clk_phase_res; + wire data_valid_w; + wire dibit_sample; + wire eopack_w; + wire [3:0] num_w; + wire [3:0] reg_count_w; + wire sopack_w; + + reg mii_rx_clk_10_100_r = 1'b0; + reg [3:0] num_r = 4'b0; + reg [3:0] reg_count = 4'b0; + + reg clk_phase_r = 1'b0; + reg data_valid = 1'b0; + reg data_valid_d = 1'b0; + reg [1:0] eopack_r = 2'b0; + reg nibble_valid = 1'b0; + reg [1:0] sopack_r = 2'b0; + + reg [3:0] mii_rxd_r0 = 4'b0; + reg [3:0] mii_rxd_r1 = 4'b0; + reg [3:0] mii_rxd_r2 = 4'b0; + + reg mii_rx_er_r0 = 1'b0; + reg mii_rx_er_r1 = 1'b0; + reg mii_rx_er_r2 = 1'b0; + + reg mii_rx_dv_r0 = 1'b0; + reg mii_rx_dv_r1 = 1'b0; + reg mii_rx_dv_r2 = 1'b0; + reg mii_rx_dv_r3 = 1'b0; + + localparam DIV_REF_CLK = RATE_10_100 ? 10 : 1; + + always @(posedge ref_clk) begin + if (!reset_n) begin + num_r <= 0; + mii_rx_clk_10_100_r <= 1'b0; + end else if (num_w == DIV_REF_CLK) begin + num_r <= 0; + mii_rx_clk_10_100_r <= ~mii_rx_clk_10_100_r; + end else begin + num_r <= num_w; + end + end + + always @(posedge ref_clk) begin + if (!reset_n) begin + mii_rxd_r0 <= 4'b0; + mii_rxd_r1 <= 4'b0; + mii_rxd_r2 <= 4'b0; + end else begin + if (RATE_10_100) begin + if (dibit_sample) begin + mii_rxd_r0[3:2] <= phy_rxd; + mii_rxd_r0[1:0] <= mii_rxd_r0[3:2]; + if (nibble_valid | sopack_w) begin + mii_rxd_r1 <= mii_rxd_r0; + end + mii_rxd_r2 <= mii_rxd_r1; + end + end else begin + mii_rxd_r0[3:2] <= phy_rxd; + mii_rxd_r0[1:0] <= mii_rxd_r0[3:2]; + if (nibble_valid | sopack_w) begin + mii_rxd_r1 <= mii_rxd_r0; + end + mii_rxd_r2 <= mii_rxd_r1; + end + end + end + + always @(posedge ref_clk) begin + if (!reset_n) begin + mii_rx_er_r0 <= 1'b0; + mii_rx_er_r1 <= 1'b0; + mii_rx_er_r2 <= 1'b0; + end else begin + if (RATE_10_100) begin + if (dibit_sample) begin + mii_rx_er_r0 <= phy_rx_er; + mii_rx_er_r1 <= mii_rx_er_r0; + mii_rx_er_r2 <= mii_rx_er_r1; + end + end else begin + mii_rx_er_r0 <= phy_rx_er; + mii_rx_er_r1 <= mii_rx_er_r0; + mii_rx_er_r2 <= mii_rx_er_r1; + end + end + end + + always @(posedge ref_clk) begin + if (!reset_n) begin + mii_rx_dv_r0 <= 1'b0; + mii_rx_dv_r1 <= 1'b0; + mii_rx_dv_r2 <= 1'b0; + mii_rx_dv_r3 <= 1'b0; + end else begin + if (RATE_10_100) begin + if (dibit_sample) begin + mii_rx_dv_r0 <= phy_crs_dv; + mii_rx_dv_r1 <= mii_rx_dv_r0; + mii_rx_dv_r2 <= mii_rx_dv_r1; + mii_rx_dv_r3 <= mii_rx_dv_r2; + end + end else begin + mii_rx_dv_r0 <= phy_crs_dv; + mii_rx_dv_r1 <= mii_rx_dv_r0; + mii_rx_dv_r2 <= mii_rx_dv_r1; + mii_rx_dv_r3 <= mii_rx_dv_r2; + end + end + end + + always @(posedge ref_clk) begin + if (!reset_n || eopack_w) begin + sopack_r[1:0] <= 2'b0; + end else begin + if (RATE_10_100) begin + if (dibit_sample) begin + sopack_r[1] <= sopack_r[0]; + end + if (dibit_sample && (mii_rxd_r0[3:2] == 2'b01) && (mii_rx_dv_r0 == 1'b1) && (sopack_w == 1'b0)) begin + sopack_r[0] <= 1'b1; + end + end else begin + sopack_r[1] <= sopack_r[0]; + if ((mii_rxd_r0[3:2] == 2'b01) && (mii_rx_dv_r0 == 1'b1) && (sopack_w == 1'b0)) begin + sopack_r[0] <= 1'b1; + end + end + end + end + + always @(posedge ref_clk) begin + if (!reset_n || sopack_w) begin + eopack_r[1:0] <= 2'b0; + end else begin + if (RATE_10_100) begin + if (dibit_sample) begin + eopack_r[1] <= eopack_r[0]; + end + if (dibit_sample && (mii_rx_dv_r0 == 1'b0) && (mii_rx_dv_r1 == 1'b0) && (eopack_w == 1'b0)) begin + eopack_r[0] <= 1'b1; + end + end else begin + eopack_r[1] <= eopack_r[0]; + if ((mii_rx_dv_r0 == 1'b0) && (mii_rx_dv_r1 == 1'b0) && (eopack_w == 1'b0)) begin + eopack_r[0] <= 1'b1; + end + end + end + end + + always @(posedge ref_clk) begin + if (!reset_n) begin + data_valid <= 1'b0; + end else begin + if (RATE_10_100) begin + if (dibit_sample && sopack_w) begin + data_valid <= 1'b1; + end else if (dibit_sample && eopack_w) begin + data_valid <= 1'b0; + end + end else begin + if (sopack_w) begin + data_valid <= 1'b1; + end else if (eopack_w) begin + data_valid <= 1'b0; + end + end + end + end + + always @(posedge ref_clk) begin + if (!reset_n) begin + data_valid_d <= 1'b0; + end else begin + data_valid_d <= data_valid; + end + end + + always @(posedge ref_clk) begin + if (!reset_n) begin + clk_phase_r <= 1'b0; + nibble_valid <= 1'b0; + end else begin + if (sopack_w) begin + clk_phase_r <= mii_rx_clk; + nibble_valid <= 1'b0; + end else begin + if (RATE_10_100) begin + if (dibit_sample) begin + nibble_valid <= ~nibble_valid; + end + end else begin + nibble_valid <= ~nibble_valid; + end + end + end + end + + always @(posedge ref_clk) begin + if (!reset_n) begin + reg_count <= 1'b0; + end else begin + if (reg_count_w == 4'b1001) begin + reg_count <= 1'b0; + end else begin + reg_count <= reg_count + 1; + end + end + end + + assign clk_phase_res = clk_phase_r; + assign data_valid_w = RATE_10_100 ? data_valid : (clk_phase_res ? data_valid : data_valid_d); + assign dibit_sample = (reg_count_w == 4'b0101) ? 1'b1 : 1'b0; + assign eopack_w = eopack_r[0] & (!eopack_r[1]); + assign mii_crs = mii_rx_dv_r0; + assign mii_rxd = RATE_10_100 ? (mii_rx_dv ? mii_rxd_r1 : 4'b0) : (mii_rx_dv ? (clk_phase_res ? mii_rxd_r1 : mii_rxd_r2) : 4'b0); + assign mii_rx_clk = mii_rx_clk_10_100_r; + assign mii_rx_dv = data_valid_w ? 1'b1 : 1'b0; + assign mii_rx_er = mii_rx_er_r2; + assign num_w = num_r + 1; + assign reg_count_w = reg_count; + assign sopack_w = sopack_r[0] & (!sopack_r[1]); + +endmodule diff --git a/adi_library/util_mii_to_rmii/util_mii_to_rmii.v b/adi_library/util_mii_to_rmii/util_mii_to_rmii.v new file mode 100644 index 00000000..59fca826 --- /dev/null +++ b/adi_library/util_mii_to_rmii/util_mii_to_rmii.v @@ -0,0 +1,190 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_mii_to_rmii #( + parameter INTF_CFG = 0, + parameter RATE_10_100 = 0 +) ( + + // MAC to MII(PHY) + input mac_tx_en, + input [3:0] mac_txd, + input mac_tx_er, + //MII to MAC + output mii_tx_clk, + output mii_rx_clk, + output mii_col, + output mii_crs, + output mii_rx_dv, + output mii_rx_er, + output [3:0] mii_rxd, + // RMII to PHY + output [1:0] rmii_txd, + output rmii_tx_en, + // PHY to RMII + input [1:0] phy_rxd, + input phy_crs_dv, + input phy_rx_er, + // External + input ref_clk, + input reset_n +); + + reg mac_tx_en_r1 = 1'b0; + reg [3:0] mac_txd_r1 = 4'b0; + reg mac_tx_er_r1 = 1'b0; + reg phy_crs_dv_r1 = 1'b0; + reg [1:0] phy_rxd_r1 = 2'b0; + reg phy_rx_er_r1 = 1'b0; + reg mii_tx_clk_r1 = 1'b0; + reg mii_rx_clk_r1 = 1'b0; + reg mii_col_r1 = 1'b0; + reg mii_crs_r1 = 1'b0; + reg mii_rx_dv_r1 = 1'b0; + reg mii_rx_er_r1 = 1'b0; + reg [3:0] mii_rxd_r1 = 4'b0; + reg [1:0] rmii_txd_r1 = 2'b0; + reg rmii_tx_en_r1 = 1'b0; + reg mac_tx_en_r2 = 1'b0; + reg [3:0] mac_txd_r2 = 4'b0; + reg mac_tx_er_r2 = 1'b0; + reg phy_crs_dv_r2 = 1'b0; + reg [1:0] phy_rxd_r2 = 2'b0; + reg phy_rx_er_r2 = 1'b0; + + wire mii_tx_clk_r2; + wire mii_rx_clk_r2; + wire mii_col_r2; + wire mii_crs_r2; + wire mii_rx_dv_r2; + wire mii_rx_er_r2; + wire [3:0] mii_rxd_r2; + wire [1:0] rmii_txd_r2; + wire rmii_tx_en_r2; + + //inputs + always @(posedge ref_clk) begin + if (!reset_n) begin + mac_tx_en_r1 <= 1'b0; + mac_tx_en_r2 <= 1'b0; + mac_txd_r1 <= 4'b0; + mac_txd_r2 <= 4'b0; + mac_tx_er_r1 <= 1'b0; + mac_tx_er_r2 <= 1'b0; + phy_crs_dv_r1 <= 1'b0; + phy_crs_dv_r2 <= 1'b0; + phy_rxd_r1 <= 2'b0; + phy_rx_er_r1 <= 1'b0; + phy_rxd_r2 <= 2'b0; + end else begin + mac_tx_en_r1 <= mac_tx_en; + mac_tx_en_r2 <= mac_tx_en_r1; + mac_txd_r1 <= mac_txd; + mac_txd_r2 <= mac_txd_r1; + mac_tx_er_r1 <= mac_tx_er; + mac_tx_er_r2 <= mac_tx_er_r1; + phy_crs_dv_r1 <= phy_crs_dv; + phy_crs_dv_r2 <= phy_crs_dv_r1; + phy_rxd_r1 <= phy_rxd; + phy_rxd_r2 <= phy_rxd_r1; + phy_rx_er_r1 <= phy_rx_er; + phy_rx_er_r2 <= phy_rx_er_r1; + end + end + + //outputs + always @(posedge ref_clk) begin + if (!reset_n) begin + mii_col_r1 <= 1'b0; + mii_crs_r1 <= 1'b0; + mii_rx_dv_r1 <= 1'b0; + mii_rx_er_r1 <= 1'b0; + mii_rxd_r1 <= 4'b0; + rmii_txd_r1 <= 2'b0; + rmii_tx_en_r1 <= 1'b0; + mii_tx_clk_r1 <= 1'b0; + mii_rx_clk_r1 <= 1'b0; + end else begin + mii_tx_clk_r1 <= mii_tx_clk_r2; + mii_rx_clk_r1 <= mii_rx_clk_r2; + mii_col_r1 <= mii_crs_r2 & mac_tx_en_r2; + mii_crs_r1 <= mii_crs_r2; + mii_rx_dv_r1 <= mii_rx_dv_r2; + mii_rx_er_r1 <= mii_rx_er_r2; + mii_rxd_r1 <= mii_rxd_r2; + rmii_txd_r1 <= rmii_txd_r2; + rmii_tx_en_r1 <= rmii_tx_en_r2; + end + end + + assign mii_crs = mii_crs_r1; + assign mii_col = mii_col_r1; + assign mii_rx_dv = mii_rx_dv_r1; + assign mii_rx_er = mii_rx_er_r1; + assign mii_rxd = mii_rxd_r1; + assign rmii_txd = rmii_txd_r1; + assign rmii_tx_en = rmii_tx_en_r1; + assign mii_rx_clk = mii_rx_clk_r1; + assign mii_tx_clk = mii_tx_clk_r1; + + mac_phy_link #( + .RATE_10_100(RATE_10_100) + ) mac_phy_link_inst ( + .ref_clk(ref_clk), + .reset_n(reset_n), + .mac_tx_en(mac_tx_en_r2), + .mac_txd(mac_txd_r2), + .mac_tx_er(mac_tx_er_r2), + .mii_tx_clk(mii_tx_clk_r2), + .rmii_txd(rmii_txd_r2), + .rmii_tx_en(rmii_tx_en_r2)); + + phy_mac_link #( + .RATE_10_100(RATE_10_100) + ) phy_mac_link_inst ( + .ref_clk(ref_clk), + .reset_n(reset_n), + .mii_crs(mii_crs_r2), + .mii_rx_dv(mii_rx_dv_r2), + .mii_rx_er(mii_rx_er_r2), + .mii_rxd(mii_rxd_r2), + .mii_rx_clk(mii_rx_clk_r2), + .phy_rxd(phy_rxd_r2), + .phy_crs_dv(phy_crs_dv_r2), + .phy_rx_er(phy_rx_er_r2)); + +endmodule diff --git a/adi_library/util_mii_to_rmii/util_mii_to_rmii.xpr b/adi_library/util_mii_to_rmii/util_mii_to_rmii.xpr new file mode 100644 index 00000000..486b6e98 --- /dev/null +++ b/adi_library/util_mii_to_rmii/util_mii_to_rmii.xpr @@ -0,0 +1,413 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_mii_to_rmii/util_mii_to_rmii_ip.tcl b/adi_library/util_mii_to_rmii/util_mii_to_rmii_ip.tcl new file mode 100644 index 00000000..5e3da9b7 --- /dev/null +++ b/adi_library/util_mii_to_rmii/util_mii_to_rmii_ip.tcl @@ -0,0 +1,110 @@ +############################################################################### +## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_mii_to_rmii + +adi_ip_files util_mii_to_rmii [list \ + "mac_phy_link.v" \ + "phy_mac_link.v" \ + "util_mii_to_rmii.v" ] + +adi_ip_properties_lite util_mii_to_rmii + +adi_add_bus "GMII" "slave" \ + "xilinx.com:interface:gmii_rtl:1.0" \ + "xilinx.com:interface:gmii:1.0" \ + { + {"mii_col" "COL"} \ + {"mii_crs" "CRS"} \ + {"mii_rxd" "RXD"} \ + {"mii_rx_clk" "RX_CLK"} \ + {"mii_rx_dv" "RX_DV"} \ + {"mii_rx_er" "RX_ER"} \ + {"mac_txd" "TXD"} \ + {"mii_tx_clk" "TX_CLK"} \ + {"mac_tx_en" "TX_EN"} \ + {"mac_tx_er" "TX_ER"} \ + } + +adi_add_bus "MII" "slave" \ + "xilinx.com:interface:mii_rtl:1.0" \ + "xilinx.com:interface:mii:1.0" \ + { + {"mii_col" "COL"} \ + {"mii_crs" "CRS"} \ + {"mii_rxd" "RXD"} \ + {"mii_rx_clk" "RX_CLK"} \ + {"mii_rx_dv" "RX_DV"} \ + {"mii_rx_er" "RX_ER"} \ + {"mac_txd" "TXD"} \ + {"mii_tx_clk" "TX_CLK"} \ + {"mac_tx_en" "TX_EN"} \ + {"mac_tx_er" "TX_ER"} \ + } + +adi_add_bus "RMII" "master" \ + "xilinx.com:interface:rmii_rtl:1.0" \ + "xilinx.com:interface:rmii:1.0" \ + { + {"phy_crs_dv" "CRS_DV"} \ + {"phy_rxd" "RXD"} \ + {"phy_rx_er" "RX_ER"} \ + {"rmii_txd" "TXD"} \ + {"rmii_tx_en" "TX_EN"} \ + } + +adi_set_bus_dependency "MII" "MII" \ + "(spirit:decode(id('MODELPARAM_VALUE.INTF_CFG')) = 0)" +adi_set_bus_dependency "GMII" "GMII" \ + "(spirit:decode(id('MODELPARAM_VALUE.INTF_CFG')) = 1)" + +set cc [ipx::current_core] + +ipx::infer_bus_interface reset_n xilinx.com:signal:reset_rtl:1.0 $cc +ipx::infer_bus_interface ref_clk xilinx.com:signal:clock_rtl:1.0 $cc + +## Customize XGUI layout + +set_property display_name "util_mii_to_rmii" $cc +set_property description "MII to RMII Converter IP" $cc +set_property -dict [list \ + "value_validation_type" "pairs" \ + "value_validation_pairs" { \ + "MII" "0" \ + "GMII" "1" \ + } \ +] \ +[ipx::get_user_parameters INTF_CFG -of_objects $cc] + +set_property -dict [list \ + "value_validation_type" "pairs" \ + "value_validation_pairs" { \ + "100Mbps" "0" \ + "10Mbps" "1" \ + } \ +] \ +[ipx::get_user_parameters RATE_10_100 -of_objects $cc] + +ipgui::add_param -name "INTF_CFG" -component $cc +set p [ipgui::get_guiparamspec -name "INTF_CFG" -component $cc] +set_property -dict [list \ + "widget" "comboBox" \ + "display_name" "Interface Selection" \ +] $p + +ipgui::add_param -name "RATE_10_100" -component $cc +set p [ipgui::get_guiparamspec -name "RATE_10_100" -component $cc] +set_property -dict [list \ + "widget" "comboBox" \ + "display_name" "Rate Selection" \ +] $p + +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] +ipx::save_core $cc diff --git a/adi_library/util_mii_to_rmii/xgui/util_mii_to_rmii_v1_0.tcl b/adi_library/util_mii_to_rmii/xgui/util_mii_to_rmii_v1_0.tcl new file mode 100644 index 00000000..8d0a22ba --- /dev/null +++ b/adi_library/util_mii_to_rmii/xgui/util_mii_to_rmii_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "INTF_CFG" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "RATE_10_100" -parent ${Page_0} -widget comboBox + + +} + +proc update_PARAM_VALUE.INTF_CFG { PARAM_VALUE.INTF_CFG } { + # Procedure called to update INTF_CFG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.INTF_CFG { PARAM_VALUE.INTF_CFG } { + # Procedure called to validate INTF_CFG + return true +} + +proc update_PARAM_VALUE.RATE_10_100 { PARAM_VALUE.RATE_10_100 } { + # Procedure called to update RATE_10_100 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RATE_10_100 { PARAM_VALUE.RATE_10_100 } { + # Procedure called to validate RATE_10_100 + return true +} + + +proc update_MODELPARAM_VALUE.INTF_CFG { MODELPARAM_VALUE.INTF_CFG PARAM_VALUE.INTF_CFG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.INTF_CFG}] ${MODELPARAM_VALUE.INTF_CFG} +} + +proc update_MODELPARAM_VALUE.RATE_10_100 { MODELPARAM_VALUE.RATE_10_100 PARAM_VALUE.RATE_10_100 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RATE_10_100}] ${MODELPARAM_VALUE.RATE_10_100} +} + diff --git a/adi_library/util_pack/tb/.gitignore b/adi_library/util_pack/tb/.gitignore new file mode 100644 index 00000000..804d96e7 --- /dev/null +++ b/adi_library/util_pack/tb/.gitignore @@ -0,0 +1,2 @@ +run/ +vcd/ diff --git a/adi_library/util_pack/tb/cpack_tb b/adi_library/util_pack/tb/cpack_tb new file mode 100755 index 00000000..6bd48a5f --- /dev/null +++ b/adi_library/util_pack/tb/cpack_tb @@ -0,0 +1,12 @@ +#!/bin/bash + +SOURCE="cpack_tb.v" +SOURCE+=" ../util_cpack2/util_cpack2_impl.v" +SOURCE+=" ../util_pack_common/pack_ctrl.v" +SOURCE+=" ../util_pack_common/pack_interconnect.v" +SOURCE+=" ../util_pack_common/pack_network.v" +SOURCE+=" ../util_pack_common/pack_shell.v" +SOURCE+=" ../../common/ad_perfect_shuffle.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/util_pack/tb/cpack_tb.v b/adi_library/util_pack/tb/cpack_tb.v new file mode 100644 index 00000000..3d7e0059 --- /dev/null +++ b/adi_library/util_pack/tb/cpack_tb.v @@ -0,0 +1,177 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module cpack_tb; + parameter VCD_FILE = {`__FILE__,"cd"}; + parameter NUM_OF_CHANNELS = 4; + parameter SAMPLES_PER_CHANNEL = 1; + parameter ENABLE_RANDOM = 0; + + `define TIMEOUT 1500000 + `include "tb_base.v" + + localparam NUM_OF_PORTS = SAMPLES_PER_CHANNEL * NUM_OF_CHANNELS; + + reg fifo_wr_en = 1'b1; + reg [NUM_OF_PORTS*8-1:0] fifo_wr_data = 'h00; + + wire packed_fifo_wr_en; + wire [NUM_OF_PORTS*8-1:0] packed_fifo_wr_data; + reg [NUM_OF_PORTS*8-1:0] expected_packed_fifo_wr_data; + + reg [NUM_OF_CHANNELS-1:0] enable = 'h1; + reg [NUM_OF_CHANNELS-1:0] next_enable = 'h1; + + integer counter; + + always @(*) begin + if (counter == 15) do_trigger_reset(); + end + + always @(posedge clk) begin + if (trigger_reset == 1'b1) begin + if (enable != {NUM_OF_CHANNELS{1'b1}}) begin + enable <= enable + 1'b1; + end else begin + if (failed == 1'b0) + $display("SUCCESS"); + else + $display("FAILED"); + $finish; + end + end + end + + reg reset_data = 1'b0; + integer reset_counter = 'h00; + + always @(posedge clk) begin + if (reset == 1'b1) begin + reset_data <= 1'b1; + reset_counter <= 'h00; + end else begin + reset_counter <= reset_counter + 1'b1; + if (reset_counter == 'h5) begin + reset_data <= 1'b0; + end + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + counter <= 'h00; + end else if (packed_fifo_wr_en == 1'b1) begin + counter <= counter + 1; + end + end + + always @(posedge clk) begin + if (reset == 1'b0 && packed_fifo_wr_en == 1'b1 && + expected_packed_fifo_wr_data !== packed_fifo_wr_data) begin + failed <= 1'b1; + $display("Failed for enable mask: %x. Expected data %x, got %x", + enable, expected_packed_fifo_wr_data, packed_fifo_wr_data); + end + end + + integer i; + integer j; + integer h; + + always @(posedge clk) begin + if (reset == 1'b1) begin + j = 0; + for (h = 0; h < SAMPLES_PER_CHANNEL; h = h + 1) begin + for (i = 0; i < NUM_OF_CHANNELS; i = i + 1) begin + if (enable[i] == 1'b1) begin + fifo_wr_data[(i*SAMPLES_PER_CHANNEL+h)*8+:8] <= j; + j = j + 1; + end else begin + fifo_wr_data[(i*SAMPLES_PER_CHANNEL+h)*8+:8] <= 'hxx; + end + end + end + end else if (fifo_wr_en == 1'b1) begin + for (h = 0; h < SAMPLES_PER_CHANNEL; h = h + 1) begin + for (i = 0; i < NUM_OF_CHANNELS; i = i + 1) begin + if (enable[i] == 1'b1) begin + fifo_wr_data[(i*SAMPLES_PER_CHANNEL+h)*8+:8] <= j; + j = j + 1; + end + end + end + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + for (i = 0; i < NUM_OF_PORTS; i = i + 1) begin + expected_packed_fifo_wr_data[i*8+:8] <= i; + end + end else if (packed_fifo_wr_en == 1'b1) begin + for (i = 0; i < NUM_OF_PORTS; i = i + 1) begin + expected_packed_fifo_wr_data[i*8+:8] <= expected_packed_fifo_wr_data[i*8+:8] + NUM_OF_PORTS; + end + end + end + + always @(posedge clk) begin + if (reset_data == 1'b1) begin + fifo_wr_en <= 1'b0; + end else begin + fifo_wr_en <= ENABLE_RANDOM ? ($random & 1'b1) : ~fifo_wr_en; + end + end + + util_cpack2_impl #( + .NUM_OF_CHANNELS(NUM_OF_CHANNELS), + .SAMPLES_PER_CHANNEL(SAMPLES_PER_CHANNEL), + .SAMPLE_DATA_WIDTH(8) + ) i_cpack ( + .clk(clk), + .reset(reset), + + .enable(enable), + + .fifo_wr_en({NUM_OF_CHANNELS{fifo_wr_en}}), + .fifo_wr_data(fifo_wr_data), + + .packed_fifo_wr_en(packed_fifo_wr_en), + .packed_fifo_wr_data(packed_fifo_wr_data), + .packed_fifo_wr_overflow(1'b0)); + +endmodule diff --git a/adi_library/util_pack/tb/tb_base.v b/adi_library/util_pack/tb/tb_base.v new file mode 100644 index 00000000..169b98f8 --- /dev/null +++ b/adi_library/util_pack/tb/tb_base.v @@ -0,0 +1,67 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + + reg clk = 1'b1; + reg [3:0] reset_shift = 4'b1111; + reg trigger_reset = 1'b0; + wire reset; + + reg failed = 1'b0; + + initial + begin + if (VCD_FILE != "") begin + $dumpfile (VCD_FILE); + $dumpvars; + end + end + + always @(*) #10 clk <= ~clk; + always @(posedge clk) begin + if (trigger_reset == 1'b1) begin + reset_shift <= 4'b1111; + end else begin + reset_shift <= {reset_shift[2:0],1'b0}; + end + end + + assign reset = reset_shift[3]; + + task do_trigger_reset; + begin + @(posedge clk) trigger_reset <= 1'b1; + @(posedge clk) trigger_reset <= 1'b0; + end + endtask diff --git a/adi_library/util_pack/tb/underflow_tb b/adi_library/util_pack/tb/underflow_tb new file mode 100755 index 00000000..ac1c5c29 --- /dev/null +++ b/adi_library/util_pack/tb/underflow_tb @@ -0,0 +1,12 @@ +#!/bin/bash + +SOURCE="underflow_tb.v" +SOURCE+=" ../util_upack2/util_upack2_impl.v" +SOURCE+=" ../util_pack_common/pack_ctrl.v" +SOURCE+=" ../util_pack_common/pack_interconnect.v" +SOURCE+=" ../util_pack_common/pack_network.v" +SOURCE+=" ../util_pack_common/pack_shell.v" +SOURCE+=" ../../common/ad_perfect_shuffle.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/util_pack/tb/underflow_tb.v b/adi_library/util_pack/tb/underflow_tb.v new file mode 100644 index 00000000..c4b15aba --- /dev/null +++ b/adi_library/util_pack/tb/underflow_tb.v @@ -0,0 +1,118 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module underflow_tb; + parameter VCD_FILE = {`__FILE__,"cd"}; + parameter NUM_OF_CHANNELS = 8; + parameter SAMPLES_PER_CHANNEL = 4; + + `include "tb_base.v" + + initial + begin + #1500000 + if (failed == 1'b0) + $display("SUCCESS"); + else + $display("FAILED"); + $finish; + end + + localparam NUM_OF_PORTS = SAMPLES_PER_CHANNEL * NUM_OF_CHANNELS; + + reg fifo_rd_en = 1'b1; + wire [NUM_OF_PORTS*8-1:0] fifo_rd_data; + wire fifo_rd_valid; + wire fifo_rd_underflow; + + reg s_axis_valid = 1'b1; + wire s_axis_ready; + reg [NUM_OF_PORTS*8-1:0] s_axis_data = {NUM_OF_PORTS*8{1'b1}}; + + reg [NUM_OF_CHANNELS-1:0] enable = {NUM_OF_CHANNELS{1'b1}}; + integer counter = 0; + + always @(posedge clk) begin + if (fifo_rd_underflow == 1'b1 && fifo_rd_data != 'h00) begin + failed <= 1'b1; + end + if (fifo_rd_valid == 1'b1 && fifo_rd_data != {NUM_OF_PORTS*8{1'b1}}) begin + failed <= 1'b1; + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + counter <= 0; + s_axis_valid <= 1'b1; + end else begin + if (s_axis_valid == 1'b0) begin + if (counter == 8) begin + s_axis_valid <= 1'b1; + end + counter <= counter + 1; + end else if (s_axis_ready == 1'b1) begin + s_axis_valid <= 1'b0; + counter <= 0; + end + end + end + + always @(posedge clk) begin + fifo_rd_en <= $random & 1; + end + + util_upack2_impl #( + .NUM_OF_CHANNELS(NUM_OF_CHANNELS), + .SAMPLES_PER_CHANNEL(SAMPLES_PER_CHANNEL), + .SAMPLE_DATA_WIDTH(8) + ) i_unpack ( + .clk(clk), + .reset(reset), + + .enable(enable), + + .fifo_rd_en({NUM_OF_CHANNELS{fifo_rd_en}}), + .fifo_rd_data(fifo_rd_data), + .fifo_rd_valid(fifo_rd_valid), + .fifo_rd_underflow(fifo_rd_underflow), + + .s_axis_valid(s_axis_valid), + .s_axis_ready(s_axis_ready), + .s_axis_data(s_axis_data)); + +endmodule diff --git a/adi_library/util_pack/tb/upack_tb b/adi_library/util_pack/tb/upack_tb new file mode 100755 index 00000000..55d4a226 --- /dev/null +++ b/adi_library/util_pack/tb/upack_tb @@ -0,0 +1,12 @@ +#!/bin/bash + +SOURCE="upack_tb.v" +SOURCE+=" ../util_upack2/util_upack2_impl.v" +SOURCE+=" ../util_pack_common/pack_ctrl.v" +SOURCE+=" ../util_pack_common/pack_interconnect.v" +SOURCE+=" ../util_pack_common/pack_network.v" +SOURCE+=" ../util_pack_common/pack_shell.v" +SOURCE+=" ../../common/ad_perfect_shuffle.v" + +cd `dirname $0` +source ../../common/tb/run_tb.sh diff --git a/adi_library/util_pack/tb/upack_tb.v b/adi_library/util_pack/tb/upack_tb.v new file mode 100644 index 00000000..cc455c24 --- /dev/null +++ b/adi_library/util_pack/tb/upack_tb.v @@ -0,0 +1,168 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module upack_tb; + parameter VCD_FILE = {`__FILE__,"cd"}; + parameter NUM_OF_CHANNELS = 8; + parameter SAMPLES_PER_CHANNEL = 1; + parameter ENABLE_RANDOM = 0; + + `define TIMEOUT 1500000 + `include "tb_base.v" + + localparam NUM_OF_PORTS = SAMPLES_PER_CHANNEL * NUM_OF_CHANNELS; + + reg fifo_rd_en = 1'b1; + wire [NUM_OF_PORTS*8-1:0] fifo_rd_data; + reg [NUM_OF_PORTS*8-1:0] expected_fifo_rd_data = 'h00; + wire fifo_rd_valid; + + reg s_axis_valid = 1'b1; + wire s_axis_ready; + reg [NUM_OF_PORTS*8-1:0] s_axis_data = 'h00; + + reg [NUM_OF_CHANNELS-1:0] enable = 'h1; + reg [NUM_OF_CHANNELS-1:0] next_enable = 'h1; + + integer counter; + + always @(*) begin + if (counter == 15) do_trigger_reset(); + end + + always @(posedge clk) begin + if (trigger_reset == 1'b1) begin + if (enable != {NUM_OF_CHANNELS{1'b1}}) begin + enable <= enable + 1'b1; + end else begin + if (failed == 1'b0) + $display("SUCCESS"); + else + $display("FAILED"); + $finish; + end + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + counter <= 'h00; + end else if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1) begin + counter <= counter + 1; + end + end + + integer i; + + always @(posedge clk) begin + for (i = 0; i < NUM_OF_PORTS; i = i + 1) begin + if (reset == 1'b0 && fifo_rd_valid == 1'b1 && enable[i/SAMPLES_PER_CHANNEL] == 1'b1 && + fifo_rd_data[i*8+:8] !== expected_fifo_rd_data[i*8+:8]) begin + failed <= 1'b1; + $display("Failed for enable mask: %x. Expected data %x, got %x", + enable, expected_fifo_rd_data, fifo_rd_data); + i = NUM_OF_PORTS; + end + end + end + + integer j; + integer h; + + always @(posedge clk) begin + if (reset == 1'b1) begin + j = 0; + for (h = 0; h < SAMPLES_PER_CHANNEL; h = h + 1) begin + for (i = 0; i < NUM_OF_CHANNELS; i = i + 1) begin + if (enable[i] == 1'b1) begin + expected_fifo_rd_data[(i*SAMPLES_PER_CHANNEL+h)*8+:8] <= j; + j = j + 1; + end else begin + expected_fifo_rd_data[(i*SAMPLES_PER_CHANNEL+h)*8+:8] <= 'hxx; + end + end + end + end else if (fifo_rd_valid == 1'b1) begin + for (h = 0; h < SAMPLES_PER_CHANNEL; h = h + 1) begin + for (i = 0; i < NUM_OF_CHANNELS; i = i + 1) begin + if (enable[i] == 1'b1) begin + expected_fifo_rd_data[(i*SAMPLES_PER_CHANNEL+h)*8+:8] <= j; + j = j + 1; + end + end + end + end + end + + always @(posedge clk) begin + if (reset == 1'b1) begin + for (i = 0; i < NUM_OF_PORTS; i = i + 1) begin + s_axis_data[i*8+:8] <= i; + end + end else if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1) begin + for (i = 0; i < NUM_OF_PORTS; i = i + 1) begin + s_axis_data[i*8+:8] <= s_axis_data[i*8+:8] + NUM_OF_PORTS; + end + end + end + + always @(posedge clk) begin + fifo_rd_en <= ENABLE_RANDOM ? ($random & 1) : 1'b1; + if (s_axis_valid == 1'b0 || s_axis_ready == 1'b1) begin + s_axis_valid <= ENABLE_RANDOM ? ($random % 20) : 1'b1; + end + end + + util_upack2_impl #( + .NUM_OF_CHANNELS(NUM_OF_CHANNELS), + .SAMPLES_PER_CHANNEL(SAMPLES_PER_CHANNEL), + .SAMPLE_DATA_WIDTH(8) + ) i_unpack ( + .clk(clk), + .reset(reset), + + .enable(enable), + + .fifo_rd_en({NUM_OF_CHANNELS{fifo_rd_en}}), + .fifo_rd_data(fifo_rd_data), + .fifo_rd_valid(fifo_rd_valid), + + .s_axis_valid(s_axis_valid), + .s_axis_ready(s_axis_ready), + .s_axis_data(s_axis_valid ? s_axis_data : {NUM_OF_PORTS{8'hx}})); + +endmodule diff --git a/adi_library/util_pack/util_cpack2/Makefile b/adi_library/util_pack/util_cpack2/Makefile new file mode 100644 index 00000000..a0509afe --- /dev/null +++ b/adi_library/util_pack/util_cpack2/Makefile @@ -0,0 +1,24 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_cpack2 + +GENERIC_DEPS += ../../common/ad_perfect_shuffle.v +GENERIC_DEPS += ../util_pack_common/pack_ctrl.v +GENERIC_DEPS += ../util_pack_common/pack_interconnect.v +GENERIC_DEPS += ../util_pack_common/pack_network.v +GENERIC_DEPS += ../util_pack_common/pack_shell.v +GENERIC_DEPS += util_cpack2_impl.v + +XILINX_DEPS += util_cpack2.v +XILINX_DEPS += util_cpack2_ip.tcl + +XILINX_DEPS += ../../interfaces/fifo_wr.xml +XILINX_DEPS += ../../interfaces/fifo_wr_rtl.xml + +INTEL_DEPS += util_cpack2_hw.tcl + +include ../../scripts/library.mk diff --git a/adi_library/util_pack/util_cpack2/component.xml b/adi_library/util_pack/util_cpack2/component.xml new file mode 100644 index 00000000..e1f520cf --- /dev/null +++ b/adi_library/util_pack/util_cpack2/component.xml @@ -0,0 +1,3417 @@ + + + analog.com + user + util_cpack2 + 1.0 + + + packed_fifo_wr + + + + + + + EN + + + packed_fifo_wr_en + + + + + DATA + + + packed_fifo_wr_data + + + + + OVERFLOW + + + packed_fifo_wr_overflow + + + + + SYNC + + + packed_fifo_wr_sync + + + + + + packed_fifo_wr_signal_clock + packed_fifo_wr_signal_clock + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_BUSIF + packed_fifo_wr + + + ASSOCIATED_RESET + reset + + + + + packed_fifo_wr_signal_reset + packed_fifo_wr_signal_reset + + + + + + + RST + + + reset + + + + + + POLARITY + ACTIVE_HIGH + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_cpack2 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 31917087 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_cpack2 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 31917087 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 31df22aa + + + + + + + clk + + in + + + std_logic + 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fifo_wr_data_58 + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + fifo_wr_data_59 + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + fifo_wr_data_60 + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + fifo_wr_data_61 + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + fifo_wr_data_62 + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + fifo_wr_data_63 + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + packed_fifo_wr_en + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + packed_fifo_wr_overflow + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + packed_fifo_wr_sync + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + packed_fifo_wr_data + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + NUM_OF_CHANNELS + Num Of Channels + 4 + + + SAMPLES_PER_CHANNEL + Samples Per Channel + 1 + + + SAMPLE_DATA_WIDTH + Sample Data Width + 16 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../../common/ad_perfect_shuffle.v + verilogSource + + + ../util_pack_common/pack_ctrl.v + verilogSource + + + ../util_pack_common/pack_interconnect.v + verilogSource + + + ../util_pack_common/pack_network.v + verilogSource + + + ../util_pack_common/pack_shell.v + verilogSource + + + util_cpack2_impl.v + verilogSource + + + util_cpack2.v + verilogSource + CHECKSUM_c254821b + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../common/ad_perfect_shuffle.v + verilogSource + + + ../util_pack_common/pack_ctrl.v + verilogSource + + + ../util_pack_common/pack_interconnect.v + verilogSource + + + ../util_pack_common/pack_network.v + verilogSource + + + ../util_pack_common/pack_shell.v + verilogSource + + + util_cpack2_impl.v + verilogSource + + + util_cpack2.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/util_cpack2_v1_0.tcl + tclSource + CHECKSUM_31df22aa + XGUI_VERSION_2 + + + + util_cpack2_v1_0 + + + NUM_OF_CHANNELS + Number of Channels + 4 + + + SAMPLES_PER_CHANNEL + Samples per Channel + 1 + + + SAMPLE_DATA_WIDTH + Sample Width + 16 + + + Component_Name + util_cpack2_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + util_cpack2_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:55:56Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_pack/util_cpack2/util_cpack2.v b/adi_library/util_pack/util_cpack2/util_cpack2.v new file mode 100644 index 00000000..8006a249 --- /dev/null +++ b/adi_library/util_pack/util_cpack2/util_cpack2.v @@ -0,0 +1,301 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_cpack2 #( + parameter NUM_OF_CHANNELS = 4, + parameter SAMPLES_PER_CHANNEL = 1, + parameter SAMPLE_DATA_WIDTH = 16 +) ( + input clk, + input reset, + + input enable_0, + input enable_1, + input enable_2, + input enable_3, + input enable_4, + input enable_5, + input enable_6, + input enable_7, + input enable_8, + input enable_9, + input enable_10, + input enable_11, + input enable_12, + input enable_13, + input enable_14, + input enable_15, + input enable_16, + input enable_17, + input enable_18, + input enable_19, + input enable_20, + input enable_21, + input enable_22, + input enable_23, + input enable_24, + input enable_25, + input enable_26, + input enable_27, + input enable_28, + input enable_29, + input enable_30, + input enable_31, + input enable_32, + input enable_33, + input enable_34, + input enable_35, + input enable_36, + input enable_37, + input enable_38, + input enable_39, + input enable_40, + input enable_41, + input enable_42, + input enable_43, + input enable_44, + input enable_45, + input enable_46, + input enable_47, + input enable_48, + input enable_49, + input enable_50, + input enable_51, + input enable_52, + input enable_53, + input enable_54, + input enable_55, + input enable_56, + input enable_57, + input enable_58, + input enable_59, + input enable_60, + input enable_61, + input enable_62, + input enable_63, + + input fifo_wr_en, + output fifo_wr_overflow, + + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_0, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_1, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_2, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_3, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_4, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_5, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_6, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_7, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_8, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_9, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_10, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_11, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_12, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_13, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_14, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_15, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_16, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_17, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_18, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_19, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_20, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_21, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_22, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_23, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_24, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_25, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_26, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_27, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_28, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_29, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_30, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_31, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_32, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_33, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_34, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_35, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_36, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_37, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_38, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_39, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_40, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_41, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_42, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_43, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_44, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_45, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_46, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_47, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_48, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_49, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_50, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_51, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_52, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_53, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_54, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_55, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_56, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_57, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_58, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_59, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_60, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_61, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_62, + input [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data_63, + + output packed_fifo_wr_en, + input packed_fifo_wr_overflow, + output packed_fifo_wr_sync, + output [2**$clog2(NUM_OF_CHANNELS)*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] packed_fifo_wr_data +); + + localparam CHANNEL_DATA_WIDTH = SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL; + /* + * Round up to the next power of two and zero out the additional channels + * internally. + */ + localparam REAL_NUM_OF_CHANNELS = NUM_OF_CHANNELS > 32 ? 64 : + NUM_OF_CHANNELS > 16 ? 32 : + NUM_OF_CHANNELS > 8 ? 16 : + NUM_OF_CHANNELS > 4 ? 8 : + NUM_OF_CHANNELS > 2 ? 4 : + NUM_OF_CHANNELS > 1 ? 2 : 1; + + /* FIXME: Find out how to do this in the IP-XACT */ + + wire [REAL_NUM_OF_CHANNELS-1:0] enable; + wire [63:0] enable_s; + wire [CHANNEL_DATA_WIDTH*REAL_NUM_OF_CHANNELS-1:0] fifo_wr_data; + wire [CHANNEL_DATA_WIDTH*64-1:0] fifo_wr_data_s; + + assign enable_s = { + enable_63,enable_62,enable_61,enable_60,enable_59,enable_58,enable_57,enable_56, + enable_55,enable_54,enable_53,enable_52,enable_51,enable_50,enable_49,enable_48, + enable_47,enable_46,enable_45,enable_44,enable_43,enable_42,enable_41,enable_40, + enable_39,enable_38,enable_37,enable_36,enable_35,enable_34,enable_33,enable_32, + enable_31,enable_30,enable_29,enable_28,enable_27,enable_26,enable_25,enable_24, + enable_23,enable_22,enable_21,enable_20,enable_19,enable_18,enable_17,enable_16, + enable_15,enable_14,enable_13,enable_12,enable_11,enable_10,enable_9,enable_8, + enable_7,enable_6,enable_5,enable_4,enable_3,enable_2,enable_1,enable_0 + }; + assign enable = enable_s[REAL_NUM_OF_CHANNELS-1:0]; + + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*0+:CHANNEL_DATA_WIDTH] = fifo_wr_data_0; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*1+:CHANNEL_DATA_WIDTH] = fifo_wr_data_1; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*2+:CHANNEL_DATA_WIDTH] = fifo_wr_data_2; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*3+:CHANNEL_DATA_WIDTH] = fifo_wr_data_3; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*4+:CHANNEL_DATA_WIDTH] = fifo_wr_data_4; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*5+:CHANNEL_DATA_WIDTH] = fifo_wr_data_5; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*6+:CHANNEL_DATA_WIDTH] = fifo_wr_data_6; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*7+:CHANNEL_DATA_WIDTH] = fifo_wr_data_7; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*8+:CHANNEL_DATA_WIDTH] = fifo_wr_data_8; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*9+:CHANNEL_DATA_WIDTH] = fifo_wr_data_9; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*10+:CHANNEL_DATA_WIDTH] = fifo_wr_data_10; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*11+:CHANNEL_DATA_WIDTH] = fifo_wr_data_11; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*12+:CHANNEL_DATA_WIDTH] = fifo_wr_data_12; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*13+:CHANNEL_DATA_WIDTH] = fifo_wr_data_13; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*14+:CHANNEL_DATA_WIDTH] = fifo_wr_data_14; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*15+:CHANNEL_DATA_WIDTH] = fifo_wr_data_15; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*16+:CHANNEL_DATA_WIDTH] = fifo_wr_data_16; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*17+:CHANNEL_DATA_WIDTH] = fifo_wr_data_17; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*18+:CHANNEL_DATA_WIDTH] = fifo_wr_data_18; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*19+:CHANNEL_DATA_WIDTH] = fifo_wr_data_19; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*20+:CHANNEL_DATA_WIDTH] = fifo_wr_data_20; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*21+:CHANNEL_DATA_WIDTH] = fifo_wr_data_21; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*22+:CHANNEL_DATA_WIDTH] = fifo_wr_data_22; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*23+:CHANNEL_DATA_WIDTH] = fifo_wr_data_23; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*24+:CHANNEL_DATA_WIDTH] = fifo_wr_data_24; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*25+:CHANNEL_DATA_WIDTH] = fifo_wr_data_25; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*26+:CHANNEL_DATA_WIDTH] = fifo_wr_data_26; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*27+:CHANNEL_DATA_WIDTH] = fifo_wr_data_27; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*28+:CHANNEL_DATA_WIDTH] = fifo_wr_data_28; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*29+:CHANNEL_DATA_WIDTH] = fifo_wr_data_29; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*30+:CHANNEL_DATA_WIDTH] = fifo_wr_data_30; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*31+:CHANNEL_DATA_WIDTH] = fifo_wr_data_31; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*32+:CHANNEL_DATA_WIDTH] = fifo_wr_data_32; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*33+:CHANNEL_DATA_WIDTH] = fifo_wr_data_33; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*34+:CHANNEL_DATA_WIDTH] = fifo_wr_data_34; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*35+:CHANNEL_DATA_WIDTH] = fifo_wr_data_35; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*36+:CHANNEL_DATA_WIDTH] = fifo_wr_data_36; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*37+:CHANNEL_DATA_WIDTH] = fifo_wr_data_37; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*38+:CHANNEL_DATA_WIDTH] = fifo_wr_data_38; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*39+:CHANNEL_DATA_WIDTH] = fifo_wr_data_39; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*40+:CHANNEL_DATA_WIDTH] = fifo_wr_data_40; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*41+:CHANNEL_DATA_WIDTH] = fifo_wr_data_41; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*42+:CHANNEL_DATA_WIDTH] = fifo_wr_data_42; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*43+:CHANNEL_DATA_WIDTH] = fifo_wr_data_43; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*44+:CHANNEL_DATA_WIDTH] = fifo_wr_data_44; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*45+:CHANNEL_DATA_WIDTH] = fifo_wr_data_45; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*46+:CHANNEL_DATA_WIDTH] = fifo_wr_data_46; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*47+:CHANNEL_DATA_WIDTH] = fifo_wr_data_47; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*48+:CHANNEL_DATA_WIDTH] = fifo_wr_data_48; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*49+:CHANNEL_DATA_WIDTH] = fifo_wr_data_49; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*50+:CHANNEL_DATA_WIDTH] = fifo_wr_data_50; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*51+:CHANNEL_DATA_WIDTH] = fifo_wr_data_51; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*52+:CHANNEL_DATA_WIDTH] = fifo_wr_data_52; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*53+:CHANNEL_DATA_WIDTH] = fifo_wr_data_53; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*54+:CHANNEL_DATA_WIDTH] = fifo_wr_data_54; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*55+:CHANNEL_DATA_WIDTH] = fifo_wr_data_55; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*56+:CHANNEL_DATA_WIDTH] = fifo_wr_data_56; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*57+:CHANNEL_DATA_WIDTH] = fifo_wr_data_57; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*58+:CHANNEL_DATA_WIDTH] = fifo_wr_data_58; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*59+:CHANNEL_DATA_WIDTH] = fifo_wr_data_59; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*60+:CHANNEL_DATA_WIDTH] = fifo_wr_data_60; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*61+:CHANNEL_DATA_WIDTH] = fifo_wr_data_61; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*62+:CHANNEL_DATA_WIDTH] = fifo_wr_data_62; + assign fifo_wr_data_s[CHANNEL_DATA_WIDTH*63+:CHANNEL_DATA_WIDTH] = fifo_wr_data_63; + assign fifo_wr_data = fifo_wr_data_s[0+:REAL_NUM_OF_CHANNELS*CHANNEL_DATA_WIDTH]; + + util_cpack2_impl #( + .NUM_OF_CHANNELS (REAL_NUM_OF_CHANNELS), + .SAMPLE_DATA_WIDTH (SAMPLE_DATA_WIDTH), + .SAMPLES_PER_CHANNEL (SAMPLES_PER_CHANNEL) + ) i_cpack ( + .clk (clk), + .reset (reset), + + .enable (enable), + + .fifo_wr_en ({REAL_NUM_OF_CHANNELS{fifo_wr_en}}), + .fifo_wr_overflow (fifo_wr_overflow), + .fifo_wr_data (fifo_wr_data), + + .packed_fifo_wr_en (packed_fifo_wr_en), + .packed_fifo_wr_overflow (packed_fifo_wr_overflow), + .packed_fifo_wr_data (packed_fifo_wr_data), + .packed_fifo_wr_sync (packed_fifo_wr_sync)); + +endmodule diff --git a/adi_library/util_pack/util_cpack2/util_cpack2.xpr b/adi_library/util_pack/util_cpack2/util_cpack2.xpr new file mode 100644 index 00000000..8080b6a0 --- /dev/null +++ b/adi_library/util_pack/util_cpack2/util_cpack2.xpr @@ -0,0 +1,441 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_pack/util_cpack2/util_cpack2_hw.tcl b/adi_library/util_pack/util_cpack2/util_cpack2_hw.tcl new file mode 100644 index 00000000..d0409da5 --- /dev/null +++ b/adi_library/util_pack/util_cpack2/util_cpack2_hw.tcl @@ -0,0 +1,71 @@ +############################################################################### +## Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +source ../../../scripts/adi_env.tcl +source ../../scripts/adi_ip_intel.tcl + +ad_ip_create util_cpack2 {Channel Pack Utility v2} util_cpack_elab +ad_ip_files util_cpack2_impl [list \ + $ad_hdl_dir/library/common/ad_perfect_shuffle.v \ + ../util_pack_common/pack_ctrl.v \ + ../util_pack_common/pack_interconnect.v \ + ../util_pack_common/pack_network.v \ + ../util_pack_common/pack_shell.v \ + util_cpack2_impl.v ] + +# parameters + +ad_ip_parameter NUM_OF_CHANNELS INTEGER 4 true [list \ + DISPLAY_NAME "Number of Channels" \ + ALLOWED_RANGES {2, 4, 8, 16} +] + +ad_ip_parameter SAMPLES_PER_CHANNEL INTEGER 1 true [list \ + DISPLAY_NAME "Samples per Channel" +] + +ad_ip_parameter SAMPLE_DATA_WIDTH INTEGER 16 true [list \ + DISPLAY_NAME "Sample Data Width" +] + +# defaults + +proc util_cpack_elab {} { + set num_channels [get_parameter_value NUM_OF_CHANNELS] + set samples_per_channel [get_parameter_value SAMPLES_PER_CHANNEL] + set sample_data_width [get_parameter_value SAMPLE_DATA_WIDTH] + + set channel_data_width [expr $sample_data_width * $samples_per_channel] + set total_data_width [expr $num_channels * $channel_data_width] + + add_interface clk clock end + add_interface_port clk clk clk Input 1 + add_interface reset reset end + add_interface_port reset reset reset Input 1 + set_interface_property reset associatedClock clk + + ad_interface signal packed_fifo_wr_en output 1 valid + ad_interface signal packed_fifo_wr_sync output 1 sync + ad_interface signal packed_fifo_wr_data output $total_data_width data + ad_interface signal packed_fifo_wr_overflow input 1 ovf + + ad_interface signal fifo_wr_overflow output 1 ovf + + for {set n 0} {$n < $num_channels} {incr n} { + add_interface adc_ch_$n conduit end + add_interface_port adc_ch_$n enable_$n enable Input 1 + set_port_property enable_$n fragment_list [format "enable(%d:%d)" $n $n] + + add_interface_port adc_ch_$n fifo_wr_en_$n valid Input 1 + set_port_property fifo_wr_en_$n fragment_list [format "fifo_wr_en(%d)" $n] + add_interface_port adc_ch_$n fifo_wr_data_$n data Input $channel_data_width + set_port_property fifo_wr_data_$n fragment_list [format "fifo_wr_data(%d:%d)" \ + [expr ($n+1) * $channel_data_width - 1] [expr $n * $channel_data_width]] + set_interface_property adc_ch_$n associatedClock clk + set_interface_property adc_ch_$n associatedReset "" + } +} + diff --git a/adi_library/util_pack/util_cpack2/util_cpack2_impl.v b/adi_library/util_pack/util_cpack2/util_cpack2_impl.v new file mode 100644 index 00000000..0b7b7530 --- /dev/null +++ b/adi_library/util_pack/util_cpack2/util_cpack2_impl.v @@ -0,0 +1,143 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_cpack2_impl #( + parameter NUM_OF_CHANNELS = 4, + parameter SAMPLES_PER_CHANNEL = 1, + parameter SAMPLE_DATA_WIDTH = 16 +) ( + input clk, + input reset, + + input [NUM_OF_CHANNELS-1:0] enable, + + input [NUM_OF_CHANNELS-1:0] fifo_wr_en, + output fifo_wr_overflow, + input [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_wr_data, + + output reg packed_fifo_wr_en = 1'b0, + input packed_fifo_wr_overflow, + output reg packed_fifo_wr_sync = 1'b1, + output reg [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] packed_fifo_wr_data = 'h00 +); + + localparam TOTAL_DATA_WIDTH = SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL * NUM_OF_CHANNELS; + + // Control signals from the pack shell. + wire reset_data; + wire ready; + + // Interleaved version of `fifo_wr_data`. + wire [TOTAL_DATA_WIDTH-1:0] interleaved_data; + + // Output data and corresponding control signal from the routing network. + wire [TOTAL_DATA_WIDTH-1:0] out_data; + wire out_sync; + wire [NUM_OF_CHANNELS*SAMPLES_PER_CHANNEL-1:0] out_valid; + + /* + * Only the first signal of fifo_rd_en is used. All others are ignored. The + * only reason why fifo_rd_en has multiple entries is to keep the interface + * somewhat backwards compatible to the previous upack. + */ + wire data_wr_en = fifo_wr_en[0]; + + /* + * The cpack core itself has no backpressure. Overflows can only happen + * downstream. + */ + + assign fifo_wr_overflow = packed_fifo_wr_overflow; + + /* + * Data at the input of the routing network should be interleaved. The cpack + * core is supposed to accept deinterleaved data. This just rearrange the bits + * in the data vector and does not consume any FPGA resources. + */ + ad_perfect_shuffle #( + .NUM_GROUPS (NUM_OF_CHANNELS), + .WORDS_PER_GROUP (SAMPLES_PER_CHANNEL), + .WORD_WIDTH (SAMPLE_DATA_WIDTH) + ) i_interleave ( + .data_in (fifo_wr_data), + .data_out (interleaved_data)); + + pack_shell #( + .NUM_OF_CHANNELS (NUM_OF_CHANNELS), + .SAMPLES_PER_CHANNEL (SAMPLES_PER_CHANNEL), + .SAMPLE_DATA_WIDTH (SAMPLE_DATA_WIDTH), + .PACK (1) + ) i_pack_shell ( + .clk (clk), + .reset (reset), + + .reset_data (reset_data), + + .enable (enable), + .ce (data_wr_en), + .ready (ready), + .in_data (interleaved_data), + .out_data (out_data), + .out_sync (out_sync), + .out_valid (out_valid)); + + always @(posedge clk) begin + if (reset_data == 1'b1) begin + packed_fifo_wr_en <= 1'b0; + packed_fifo_wr_sync <= 1'b0; + end else if (ready == 1'b1 && data_wr_en == 1'b1) begin + packed_fifo_wr_en <= 1'b1; + packed_fifo_wr_sync <= out_sync; + end else begin + packed_fifo_wr_en <= 1'b0; + packed_fifo_wr_sync <= 1'b0; + end + end + + always @(posedge clk) begin: gen_packed_fifo_wr_data + integer i; + + if (data_wr_en == 1'b1) begin + for (i = 0; i < NUM_OF_CHANNELS * SAMPLES_PER_CHANNEL; i = i + 1) begin + if (out_valid[i] == 1'b1) begin + packed_fifo_wr_data[i*SAMPLE_DATA_WIDTH+:SAMPLE_DATA_WIDTH] <= out_data[i*SAMPLE_DATA_WIDTH+:SAMPLE_DATA_WIDTH]; + end + end + end + end + +endmodule diff --git a/adi_library/util_pack/util_cpack2/util_cpack2_ip.tcl b/adi_library/util_pack/util_cpack2/util_cpack2_ip.tcl new file mode 100644 index 00000000..bb959edf --- /dev/null +++ b/adi_library/util_pack/util_cpack2/util_cpack2_ip.tcl @@ -0,0 +1,52 @@ +############################################################################### +## Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_cpack2 +adi_ip_files util_cpack2 [list \ + "../../common/ad_perfect_shuffle.v" \ + "../util_pack_common/pack_ctrl.v" \ + "../util_pack_common/pack_interconnect.v" \ + "../util_pack_common/pack_network.v" \ + "../util_pack_common/pack_shell.v" \ + "util_cpack2_impl.v" \ + "util_cpack2.v" ] + +adi_ip_properties_lite util_cpack2 + +adi_add_bus "packed_fifo_wr" "master" \ + "analog.com:interface:fifo_wr_rtl:1.0" \ + "analog.com:interface:fifo_wr:1.0" \ + { \ + {"packed_fifo_wr_en" "EN"} \ + {"packed_fifo_wr_data" "DATA"} \ + {"packed_fifo_wr_overflow" "OVERFLOW"} \ + {"packed_fifo_wr_sync" "SYNC"} \ + } +adi_add_bus_clock "clk" "packed_fifo_wr" "reset" + +set cc [ipx::current_core] + +for {set i 1} {$i < 64} {incr i} { + set_property enablement_dependency "spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > $i" \ + [ipx::get_ports *_$i -of_objects $cc] +} + +foreach {k v} { \ + "NUM_OF_CHANNELS" "Number of Channels" \ + "SAMPLES_PER_CHANNEL" "Samples per Channel" \ + "SAMPLE_DATA_WIDTH" "Sample Width" \ + } { \ + set p [ipgui::get_guiparamspec -name $k -component $cc] +# ipgui::move_param -component $cc -order $i $p -parent $ + set_property -dict [list \ + DISPLAY_NAME $v \ + ] $p + incr i +} + +ipx::save_core [ipx::current_core] diff --git a/adi_library/util_pack/util_cpack2/xgui/util_cpack2_v1_0.tcl b/adi_library/util_pack/util_cpack2/xgui/util_cpack2_v1_0.tcl new file mode 100644 index 00000000..af369bd7 --- /dev/null +++ b/adi_library/util_pack/util_cpack2/xgui/util_cpack2_v1_0.tcl @@ -0,0 +1,55 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "NUM_OF_CHANNELS" -parent ${Page_0} + ipgui::add_param $IPINST -name "SAMPLES_PER_CHANNEL" -parent ${Page_0} + ipgui::add_param $IPINST -name "SAMPLE_DATA_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to update NUM_OF_CHANNELS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to validate NUM_OF_CHANNELS + return true +} + +proc update_PARAM_VALUE.SAMPLES_PER_CHANNEL { PARAM_VALUE.SAMPLES_PER_CHANNEL } { + # Procedure called to update SAMPLES_PER_CHANNEL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SAMPLES_PER_CHANNEL { PARAM_VALUE.SAMPLES_PER_CHANNEL } { + # Procedure called to validate SAMPLES_PER_CHANNEL + return true +} + +proc update_PARAM_VALUE.SAMPLE_DATA_WIDTH { PARAM_VALUE.SAMPLE_DATA_WIDTH } { + # Procedure called to update SAMPLE_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SAMPLE_DATA_WIDTH { PARAM_VALUE.SAMPLE_DATA_WIDTH } { + # Procedure called to validate SAMPLE_DATA_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.NUM_OF_CHANNELS { MODELPARAM_VALUE.NUM_OF_CHANNELS PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_CHANNELS}] ${MODELPARAM_VALUE.NUM_OF_CHANNELS} +} + +proc update_MODELPARAM_VALUE.SAMPLES_PER_CHANNEL { MODELPARAM_VALUE.SAMPLES_PER_CHANNEL PARAM_VALUE.SAMPLES_PER_CHANNEL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SAMPLES_PER_CHANNEL}] ${MODELPARAM_VALUE.SAMPLES_PER_CHANNEL} +} + +proc update_MODELPARAM_VALUE.SAMPLE_DATA_WIDTH { MODELPARAM_VALUE.SAMPLE_DATA_WIDTH PARAM_VALUE.SAMPLE_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SAMPLE_DATA_WIDTH}] ${MODELPARAM_VALUE.SAMPLE_DATA_WIDTH} +} + diff --git a/adi_library/util_pack/util_pack_common/pack_ctrl.v b/adi_library/util_pack/util_pack_common/pack_ctrl.v new file mode 100644 index 00000000..d4df07d7 --- /dev/null +++ b/adi_library/util_pack/util_pack_common/pack_ctrl.v @@ -0,0 +1,113 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module pack_ctrl #( + parameter PORT_ADDRESS_WIDTH = 2, + parameter MUX_ORDER = 1, + parameter MIN_STAGE = 0, + parameter NUM_STAGES = 2, + parameter PACK = 0 +) ( + input [PORT_ADDRESS_WIDTH-1:0] rotate, + input [2**PORT_ADDRESS_WIDTH*PORT_ADDRESS_WIDTH-1:0] prefix_count, + + output [2**PORT_ADDRESS_WIDTH*MUX_ORDER*NUM_STAGES-1:0] ctrl +); + + /* + * This module computes the control bits that are used to configure the MUXes + * in the pack interconect network. The controls are configured according to + * the specified global rotation and the prefix count of each of the outputs. + */ + + localparam NUM_OF_PORTS = 2**PORT_ADDRESS_WIDTH; + + wire [NUM_OF_PORTS*MUX_ORDER*NUM_STAGES-1:0] ctrl1; + reg [NUM_OF_PORTS*MUX_ORDER*NUM_STAGES-1:0] ctrl2; + + generate + genvar i, j, k; + integer n; + + localparam z = 2**MUX_ORDER; + + // This part is magic + for (i = 0; i < NUM_STAGES; i = i + 1) begin: ctrl_gen_outer + localparam k0 = 2**(PORT_ADDRESS_WIDTH - MUX_ORDER*(i+1)-MIN_STAGE); + localparam k1 = 2**(MUX_ORDER*(1+i)+MIN_STAGE); + + for (j = 0; j < NUM_OF_PORTS; j = j + 1) begin: ctrl_gen_inner + // Offset in the ctrl signal + localparam s = (i*NUM_OF_PORTS+j)*MUX_ORDER; + localparam m = (j % k1) * k0; + localparam n = j / k1; + + if (MUX_ORDER == 1 && j % 2 == 0) begin + // This is an optimization that only works for 2:1 MUXes + assign ctrl1[s] = ~ctrl1[s+1]; + end else begin + assign ctrl1[s+:MUX_ORDER] = (j - (prefix_count[m*PORT_ADDRESS_WIDTH+:PORT_ADDRESS_WIDTH] + n - rotate) / k0) % z; + end + end + end + + if (PACK == 0 || MUX_ORDER == 1) begin + // For 2:1 MUXes pack and unpack control is the same + assign ctrl = ctrl1; + end else begin + /* + * Transform demux control into mux control. The implementation here uses a + * priority encoder. + */ + for (i = 0; i < NUM_STAGES*NUM_OF_PORTS; i = i + z) begin: demux_gen_outer + localparam base = i*MUX_ORDER; + for (k = 0; k < z; k = k + 1) begin: demux_gen_inner + always @(ctrl1) begin + ctrl2[base+k*MUX_ORDER+:MUX_ORDER] <= {MUX_ORDER{1'b1}}; + for (n = 0; n < z; n = n + 1) begin + if (ctrl1[base+n*MUX_ORDER+:MUX_ORDER] == k) begin + ctrl2[base+k*MUX_ORDER+:MUX_ORDER] <= n[MUX_ORDER-1:0]; + end + end + end + end + end + assign ctrl = ctrl2; + end + endgenerate + +endmodule diff --git a/adi_library/util_pack/util_pack_common/pack_interconnect.v b/adi_library/util_pack/util_pack_common/pack_interconnect.v new file mode 100644 index 00000000..273b76ce --- /dev/null +++ b/adi_library/util_pack/util_pack_common/pack_interconnect.v @@ -0,0 +1,130 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module pack_interconnect #( + parameter PORT_DATA_WIDTH = 16, + parameter PORT_ADDRESS_WIDTH = 3, + parameter MUX_ORDER = 2, + parameter NUM_STAGES = 2, + parameter PACK = 0 // 0 = Unpack, 1 = Pack +) ( + input [2**PORT_ADDRESS_WIDTH*MUX_ORDER*NUM_STAGES-1:0] ctrl, + + input [PORT_DATA_WIDTH * 2**PORT_ADDRESS_WIDTH-1:0] data_in, + output [PORT_DATA_WIDTH * 2**PORT_ADDRESS_WIDTH-1:0] data_out +); + + /* + * This module implements the interconnect for pack or unpack core. + * The interconnect is made up of NUM_STAGES stages. Each stage is made up of + * multiple MUXs (one for each port) and a perfect shuffle. + * + * The number of inputs per MUX is 2**MUX_ORDER. + * The number of ports is 2**PORT_ADDRESS_WIDTH. + */ + + localparam NUM_PORTS = 2**PORT_ADDRESS_WIDTH; + localparam TOTAL_DATA_WIDTH = PORT_DATA_WIDTH * NUM_PORTS; + + wire [TOTAL_DATA_WIDTH-1:0] interconnect[0:NUM_STAGES]; + + assign interconnect[0] = data_in; + assign data_out = interconnect[NUM_STAGES]; + + generate + genvar i, j; + + localparam z = 2**MUX_ORDER; + localparam w = PORT_DATA_WIDTH; + localparam NUM_SWITCHES = NUM_PORTS / z; + + // Do perfect shuffle, either in forward or reverse direction + for (i = 0; i < NUM_STAGES; i = i + 1) begin: gen_stages + // Pack network are in the opposite direction + localparam ctrl_stage = PACK ? NUM_STAGES - i - 1 : i; + wire [TOTAL_DATA_WIDTH-1:0] shuffle_in; + wire [TOTAL_DATA_WIDTH-1:0] shuffle_out; + wire [TOTAL_DATA_WIDTH-1:0] mux_in; + wire [TOTAL_DATA_WIDTH-1:0] mux_out; + + // Unpack uses forward shuffle and pack a reverse shuffle + ad_perfect_shuffle #( + .NUM_GROUPS (PACK ? NUM_SWITCHES : z), + .WORDS_PER_GROUP (PACK ? z : NUM_SWITCHES), + .WORD_WIDTH (w) + ) i_shuffle ( + .data_in (shuffle_in), + .data_out (shuffle_out)); + + for (j = 0; j < NUM_PORTS; j = j + 1) begin: gen_ports + localparam ctrl_base = (ctrl_stage * NUM_PORTS + j) * MUX_ORDER; + localparam sel_base = j & ~(z-1); // base increments in 2**MUX_ORDER steps + + /* + * To be able to better share MUX control signals and reduce overall + * resource consumption the control signal gets rotated by the offset of + * MUX in a switch. + * + * E.g. a control signal of 0 for the first MUX means that the first + * input should be selected. A control signal of 0 for the second switch + * means that the second input will be used. To implement this (j % z) + * is added to the control signal when selecting the input bits. This + * addition does not result in additional resources being used. It just + * results in a different look-up table. + */ + + wire [MUX_ORDER-1:0] sel = ctrl[ctrl_base+:MUX_ORDER];// + j % z; + assign mux_out[j*w+:w] = mux_in[(sel_base+sel)*w+:w]; + end + + /* + * Pack is MUX followed by shuffle. + * Unpack is shuffle followed by MUX. + */ + if (PACK) begin + assign mux_in = interconnect[i]; + assign shuffle_in = mux_out; + assign interconnect[i+1] = shuffle_out; + end else begin + assign shuffle_in = interconnect[i]; + assign mux_in = shuffle_out; + assign interconnect[i+1] = mux_out; + end + end + endgenerate + +endmodule diff --git a/adi_library/util_pack/util_pack_common/pack_network.v b/adi_library/util_pack/util_pack_common/pack_network.v new file mode 100644 index 00000000..6547a6c0 --- /dev/null +++ b/adi_library/util_pack/util_pack_common/pack_network.v @@ -0,0 +1,107 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module pack_network #( + parameter PORT_ADDRESS_WIDTH = 1, + parameter MUX_ORDER = 1, + parameter MIN_STAGE = 1, + parameter NUM_STAGES = 1, + parameter PACK = 0, + parameter PORT_DATA_WIDTH = 16 +) ( + input clk, + input ce_ctrl, + + input [PORT_ADDRESS_WIDTH-1:0] rotate, + input [2**PORT_ADDRESS_WIDTH*PORT_ADDRESS_WIDTH-1:0] prefix_count, + + input [PORT_DATA_WIDTH * 2**PORT_ADDRESS_WIDTH-1:0] data_in, + output [PORT_DATA_WIDTH * 2**PORT_ADDRESS_WIDTH-1:0] data_out +); + + localparam CTRL_WIDTH = 2**PORT_ADDRESS_WIDTH * NUM_STAGES * MUX_ORDER; + + wire [CTRL_WIDTH-1:0] ctrl_s; + reg [CTRL_WIDTH-1:0] ctrl = 'h00; + wire [CTRL_WIDTH-1:0] ctrl_; + + pack_ctrl #( + .PORT_ADDRESS_WIDTH (PORT_ADDRESS_WIDTH), + .MUX_ORDER (MUX_ORDER), + .MIN_STAGE (MIN_STAGE), + .NUM_STAGES (NUM_STAGES), + .PACK (PACK) + ) i_ctrl ( + .rotate(rotate), + .prefix_count(prefix_count), + .ctrl(ctrl_s)); + + always @(posedge clk) begin + if (ce_ctrl == 1'b1) begin + ctrl <= ctrl_s; + end + end + + /* + * Special optimization for 2-MUXes. In this case both control signals are + * the same. + */ + generate + genvar i; + if (MUX_ORDER == 1) begin + for (i = 1; i < CTRL_WIDTH; i = i + 2) begin: gen_ctrl + assign ctrl_[i] = ctrl[i]; + assign ctrl_[i-1] = ~ctrl[i]; + end + end else begin + assign ctrl_ = ctrl; + end + endgenerate + + pack_interconnect #( + .PORT_DATA_WIDTH (PORT_DATA_WIDTH), + .PORT_ADDRESS_WIDTH (PORT_ADDRESS_WIDTH), + .MUX_ORDER (MUX_ORDER), + .NUM_STAGES (NUM_STAGES), + .PACK (PACK) + ) i_interconnect ( + .ctrl(ctrl_), + + .data_in(data_in), + .data_out(data_out)); + +endmodule diff --git a/adi_library/util_pack/util_pack_common/pack_shell.v b/adi_library/util_pack/util_pack_common/pack_shell.v new file mode 100644 index 00000000..3a236dc9 --- /dev/null +++ b/adi_library/util_pack/util_pack_common/pack_shell.v @@ -0,0 +1,528 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module pack_shell #( + parameter NUM_OF_CHANNELS = 4, + parameter SAMPLES_PER_CHANNEL = 1, + parameter SAMPLE_DATA_WIDTH = 16, + parameter PACK = 0 +) ( + input clk, + input reset, + + output reg reset_data = 1'b0, + + input [NUM_OF_CHANNELS-1:0] enable, + + input ce, + + output reg ready = 1'b0, + input [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] in_data, + + output [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] out_data, + output out_sync, + output [NUM_OF_CHANNELS*SAMPLES_PER_CHANNEL-1:0] out_valid +); + + // If the number of active channels can be a non-power of two + localparam NON_POWER_OF_TWO = NUM_OF_CHANNELS > 2; + + localparam CHANNEL_DATA_WIDTH = SAMPLES_PER_CHANNEL * SAMPLE_DATA_WIDTH; + + localparam TOTAL_DATA_WIDTH = CHANNEL_DATA_WIDTH * NUM_OF_CHANNELS; + localparam NUM_OF_SAMPLES = NUM_OF_CHANNELS * SAMPLES_PER_CHANNEL; + + /* + * Reset and control signals for the state machine. Data and control have + * separate resets since control is pipelined and needs to be taken out of + * reset before data so it can compute the control signals for the first data + * cycle. + */ + reg reset_ctrl = 1'b1; + reg startup_ctrl = 1'b0; + reg startup_ctrl2 = 1'b0; + reg [NUM_OF_CHANNELS-1:0] enable_int = 'h00; + + /* + * Internal copy of the enable signals. This is used to detect changes in the + * channel selection and reset the internal state when that happens. + */ + always @(posedge clk) begin + if (reset == 1'b1) begin + enable_int <= {NUM_OF_CHANNELS{1'b0}}; + end else begin + enable_int <= enable; + end + end + + /* + * The internal state is reset whenever the selected channels change. The + * control path is pipelined and computed one clock cycle in advance. This + * means the control path needs to be taken out of reset one clock cycle + * before the data path and a special startup cycles are required to compute + * the first sets of control signals. + * + * In the case where there is only one channel no control signals are needed + * and hence no startup cycle. In the case where there are two channels the + * control signal pipeline is one cycle, so one startup cycle is required. For + * more than two channels the startup pipeline is two channels and two startup + * cycles are required. + */ + always @(posedge clk) begin + if (reset == 1'b1 || enable == {NUM_OF_CHANNELS{1'b0}}) begin + reset_ctrl <= 1'b1; + reset_data <= 1'b1; + startup_ctrl <= 1'b0; + startup_ctrl2 <= 1'b0; + end else if (enable != enable_int) begin + reset_ctrl <= 1'b1; + reset_data <= 1'b1; + startup_ctrl <= 1'b1; + startup_ctrl2 <= 1'b1; + end else begin + reset_ctrl <= 1'b0; + reset_data <= NUM_OF_CHANNELS != 1 ? startup_ctrl2 : 1'b0; + startup_ctrl2 <= NON_POWER_OF_TWO && PACK == 0 ? reset_ctrl : 1'b0; + startup_ctrl <= reset_ctrl | startup_ctrl2; + end + end + + generate + if (NUM_OF_CHANNELS == 1) begin + /* + * In the one channel case there is not much to do. Nevertheless we should + * support it to allow generic designs where the number of channels is + * selected programmatically. + */ + assign out_data = in_data; + assign out_sync = 1'b1; + assign out_valid = {NUM_OF_SAMPLES{1'b1}}; + + always @(*) begin + ready <= ce & ~reset_data; + end + end else begin + localparam SAMPLE_ADDRESS_WIDTH = + NUM_OF_SAMPLES > 512 ? 10 : + NUM_OF_SAMPLES > 256 ? 9 : + NUM_OF_SAMPLES > 128 ? 8 : + NUM_OF_SAMPLES > 64 ? 7 : + NUM_OF_SAMPLES > 32 ? 6 : + NUM_OF_SAMPLES > 16 ? 5 : + NUM_OF_SAMPLES > 8 ? 4 : + NUM_OF_SAMPLES > 4 ? 3 : + NUM_OF_SAMPLES > 2 ? 2 : 1; + + /* + * `rotate` is used as an offset into the input data vector. When not all + * samples are enabled it can take multiple cycles for the input vector to + * be consumed. `rotate` points to the first sample in the input vector + * that should consumed next. E.g. when there are 4 channels, but only 2 + * are enabled `rotate` will oscillate between 0 and 2. If there are 4 + * channels and 3 are enabled it will cycle through the sequence 0, 3, 2, + * 1. + */ + reg [SAMPLE_ADDRESS_WIDTH-1:0] rotate = 'h00; + + /* + * `prefix_count` counts the number of disabled channels that precede a + * channel. E.g. if channel 0 is enabled and channel 1 and 2 are disabled + * the prefix count for channel 3 is 2. + */ + reg [SAMPLE_ADDRESS_WIDTH*NUM_OF_SAMPLES-1:0] prefix_count; + + /* + * Clock enable for all the control signals. When asserted the next cycle + * for the control signals should computed + */ + wire ce_ctrl; + + /* + * Extended version of the `enable` signal that takes SAMPLES_PER_CHANNEL + * into account. + */ + wire [NUM_OF_SAMPLES-1:0] samples_enable; + + /* + * Used to connect the different intermediary stages of the routing + * network. There can be up to three sub-networks. + */ + wire [TOTAL_DATA_WIDTH-1:0] data[0:2]; + + /* + * Unregistered version of `prefix_count`. This is used to add up the + * enable ports. + */ + wire [SAMPLE_ADDRESS_WIDTH-1:0] prefix_count_s[0:NUM_OF_SAMPLES]; + + /* + * Samples are interleaved, so the sample mask is just the channel mask + * concatenated with itself SAMPLES_PER_CHANNEL times. + */ + assign samples_enable = {SAMPLES_PER_CHANNEL{enable_int}}; + + /* + * Control pipeline is active and should compute the next state either + * during the startup phase or when a output data set is consumed. + */ + assign ce_ctrl = startup_ctrl | ce; + + /* First channel has no other channels before it */ + assign prefix_count_s[0] = 'h0; + + genvar i; + for (i = 0; i < NUM_OF_SAMPLES; i = i + 1) begin: gen_prefix_count + assign prefix_count_s[i+1] = prefix_count_s[i] + (samples_enable[i] ? 1'b0 : 1'b1); + + if (i < 2 || NUM_OF_CHANNELS <= 2) begin + /* This will only be one bit, no need to register it */ + always @(prefix_count_s[i]) begin + prefix_count[i*SAMPLE_ADDRESS_WIDTH+:SAMPLE_ADDRESS_WIDTH] <= prefix_count_s[i]; + end + end else begin + always @(posedge clk) begin + prefix_count[i*SAMPLE_ADDRESS_WIDTH+:SAMPLE_ADDRESS_WIDTH] <= prefix_count_s[i]; + end + end + end + + /* + * Number of enabled channels - 1. Zero enabled channels is not a valid + * configuration and storing it this way allows for better utilization. + */ + reg [SAMPLE_ADDRESS_WIDTH-1:0] enable_count = 'h0; + + always @(posedge clk) begin + /* + * `prefix_count` tracks the number of disabled channels. Invert it to + * get the number of enabled channels - 1 + */ + enable_count <= ~prefix_count_s[NUM_OF_SAMPLES]; + end + + if (NON_POWER_OF_TWO == 1 && PACK == 0) begin: gen_input_buffer + /* Delayed data vector. Data from the previous cycle. */ + reg [TOTAL_DATA_WIDTH-2*CHANNEL_DATA_WIDTH-1:0] data_d1 = 'h00; + + /* + * Same as `rotate`, but two pipeline stages ahead of the data path. + * This is needed to compute some of the other control signals ahead of + * time. + */ + reg [SAMPLE_ADDRESS_WIDTH:0] rotate_next; + + /* + * MSB of the rotate control signal. This is used to move the source + * data index to the delayed data vector. This will only ever be + * asserted for one clock cycle at a time. + */ + reg rotate_msb = 1'b0; + + /* + * Extended version of the normal control and data signals that can + * handle 2*NUM_OF_CHANNELS channels. + */ + wire [(SAMPLE_ADDRESS_WIDTH+1)*(2*NUM_OF_SAMPLES)-1:0] ext_prefix_count; + wire [TOTAL_DATA_WIDTH*2-1:0] ext_data_in; + wire [TOTAL_DATA_WIDTH*2-1:0] ext_data_out; + wire [TOTAL_DATA_WIDTH*2-1:0] ext_data_shuffled; + wire [SAMPLE_ADDRESS_WIDTH:0] rotate_next_next; + + /* + * This stage needs to handle 2*NUM_OF_CHANNELS channels so the prefix + * count needs to padded with an extra bit. + */ + for (i = 0; i < NUM_OF_SAMPLES; i = i + 1) begin: gen_ext_prefix_count1 + assign ext_prefix_count[i*(SAMPLE_ADDRESS_WIDTH+1)+:SAMPLE_ADDRESS_WIDTH+1] = {1'b0,prefix_count[i*SAMPLE_ADDRESS_WIDTH+:SAMPLE_ADDRESS_WIDTH]}; + end + + /* + * The inversion and the addition of the constant will be folded into + * the LUT that generates the control signals. This does not use up any + * extra resources. + */ + for (i = NUM_OF_SAMPLES; i < NUM_OF_SAMPLES * 2; i = i + 1) begin: gen_ext_prefix_count2 + assign ext_prefix_count[i*(SAMPLE_ADDRESS_WIDTH+1)+:SAMPLE_ADDRESS_WIDTH+1] = ~enable_count + i; + end + + /* + * For non power of two channel masks the previous data needs to be + * saved since a single read can span over two consecutive input data + * words. The lower two channels don't need to be saved since there are + * no configurations in which they'd be required. + */ + always @(posedge clk) begin + if (ce == 1'b1 && ready == 1'b1) begin /* Just ready ??? */ + data_d1 <= in_data[TOTAL_DATA_WIDTH-1:2*CHANNEL_DATA_WIDTH]; + end + end + + /* Three pipeline steps ahead of data */ + assign rotate_next_next = rotate_next[SAMPLE_ADDRESS_WIDTH-1:0] + enable_count + 1'b1; + + always @(posedge clk) begin + if (reset_ctrl == 1'b1) begin + ready <= 1'b0; + rotate_msb <= 1'b0; + + rotate <= 'h0; + rotate_next <= 'h0; + end else if (ce_ctrl == 1'b1) begin + ready <= 1'b0; + rotate_msb <= 1'b0; + + /* + * If the next cycle will consume more data than what is still + * available ready needs to be asserted and the network needs to be + * updated to source data from the delayed data register. + */ + if (rotate_next_next[SAMPLE_ADDRESS_WIDTH] & + |rotate_next_next[SAMPLE_ADDRESS_WIDTH-1:0]) begin + ready <= 1'b1; + rotate_msb <= 1'b1; + end + /* + * If the current cycle consumes all available data ready needs to + * be asserted, but only if it wasn't already asserted on the + * previous cycle due to overconsumption. + */ + if (rotate_next[SAMPLE_ADDRESS_WIDTH] == 1'b1 && rotate_msb == 1'b0) begin + ready <= 1'b1; + end + + rotate <= rotate_next; + rotate_next <= rotate_next_next; + end + end + + /* + * First stage of the routing network. We know that we have at least 4 + * channels and hence 8 input to the network, so we'll always use a + * 4-MUX based stage here. + */ + pack_network #( + .PORT_ADDRESS_WIDTH (SAMPLE_ADDRESS_WIDTH + 1), + .MUX_ORDER (2), + .MIN_STAGE (0), + .NUM_STAGES (1), + .PORT_DATA_WIDTH (SAMPLE_DATA_WIDTH) + ) i_ext_ctrl_interconnect ( + .clk (clk), + .ce_ctrl (ce_ctrl), + + .rotate ({rotate_msb,rotate}), + .prefix_count (ext_prefix_count), + + .data_in (ext_data_in), + .data_out (ext_data_out)); + + /* + * In order to go from this stage that has 2 * NUM_OF_SAMPLES inputs + * and output to the remainder of the network that has only NUM_OF_SAMPLES + * inputs and outputs every second two ports need to be skipped. I.e. + * port 2, 3, 6, 7... + * The shuffle groups all ports that are wanted into the first half of + * `ext_data_shuffled` and the unwanted ports into the second half which + * will be discarded. + */ + ad_perfect_shuffle #( + .NUM_GROUPS (NUM_OF_SAMPLES / 2), + .WORDS_PER_GROUP (2), + .WORD_WIDTH (2 * SAMPLE_DATA_WIDTH) + ) i_ext_shuffle ( + .data_in (ext_data_out), + .data_out (ext_data_shuffled)); + + assign ext_data_in = {data_d1,{2*CHANNEL_DATA_WIDTH{1'b0}},in_data}; + assign data[0] = ext_data_shuffled[0+:TOTAL_DATA_WIDTH]; + end else begin + always @(posedge clk) begin + if (reset_ctrl == 1'b1) begin + ready <= 1'b0; + rotate <= 'h0; + end else if (ce_ctrl == 1'b1) begin + /* + * When all samples in the input vector has been consumed ready is + * asserted for a single clock cycle. Here the number of enabled + * channels is always a power of two. That means the input vector is + * evenly divisible into the output data and there is no fractional + * residual data. I.e. when ready is asserted rotate is 0. + */ + {ready,rotate} <= rotate + enable_count + 1'b1; + end + end + + assign data[0] = in_data; + end + + /* + * The routing network can be built from any type of MUX. When it comes to + * resource usage 2:1 MUXes and 4:1 MUXes are the most efficient, both will + * require the same amount of LUTs. But a network built from 4:1 MUXes only uses + * half the number of stages of a network built from 2:1 MUXes, so it has a + * shorter routing delay and is the preferred architecture. + * + * For a pure 4:1 MUX network the number of ports is a power of 4. For a 2:1 MUX + * network the number of ports is a power of 2. To get the best from both worlds + * build the last stage from 2:1 MUXes when the number of ports is a power of + * 2 and use 4:1 MUXes for the other stages. + */ + for (i = 0; i < 2; i = i + 1) begin: gen_network + localparam MUX_ORDER = i == 0 ? 2 : 1; + localparam MIN_STAGE = PACK ? (i == 0 ? SAMPLE_ADDRESS_WIDTH % 2 : 0) : + (i == 0 ? NON_POWER_OF_TWO : SAMPLE_ADDRESS_WIDTH - 1); + localparam NUM_STAGES = PACK ? (i == 0 ? SAMPLE_ADDRESS_WIDTH / 2 : SAMPLE_ADDRESS_WIDTH % 2) : + (i == 0 ? (SAMPLE_ADDRESS_WIDTH - NON_POWER_OF_TWO) / 2 : + (SAMPLE_ADDRESS_WIDTH - NON_POWER_OF_TWO) % 2); + + if (NUM_STAGES > 0) begin + pack_network #( + .PACK (PACK), + .PORT_ADDRESS_WIDTH (SAMPLE_ADDRESS_WIDTH), + .MUX_ORDER (MUX_ORDER), + .MIN_STAGE (MIN_STAGE), + .NUM_STAGES (NUM_STAGES), + .PORT_DATA_WIDTH (SAMPLE_DATA_WIDTH) + ) i_ctrl_interconnect ( + .clk (clk), + .ce_ctrl (ce_ctrl), + + .rotate (rotate), + .prefix_count (prefix_count), + + .data_in (data[i]), + .data_out (data[i+1])); + end else begin + assign data[i+1] = data[i]; + end + end + + if (PACK == 1) begin: gen_pack + /* + * Mask the qualifies the samples in the out_data vector. There is on + * entry for each sample. If the entry is 1 that means the corresponding + * sample has valid data. If the entry is 0 the data is undefined. + */ + reg [NUM_OF_SAMPLES-1:0] valid = 'h00; + + /* + * Mask that qualifies the samples that overflowed in the previous + * cycle. + */ + reg [NUM_OF_SAMPLES-2*SAMPLES_PER_CHANNEL-1:0] prev_valid = 'h00; + + always @(posedge clk) begin + if (ce_ctrl == 1'b1) begin + {prev_valid,valid} <= (({NUM_OF_SAMPLES{1'b1}} >> ~enable_count) << rotate) | prev_valid; + end + end + + if (NON_POWER_OF_TWO == 1) begin: gen_output_buffer + localparam DELAYED_DATA_WIDTH = TOTAL_DATA_WIDTH - 2 * CHANNEL_DATA_WIDTH; + + /* + * Delayed data from the previous cycle. When the number of enabled + * channels is not a power of two it is possible that not all + * incoming data can be consumed in one cycle since there might not + * be enough room in the output vector anymore. In this case it needs + * to be delayed and will be used in the next cycle. + */ + reg [DELAYED_DATA_WIDTH-1:0] data_d1 = 'h00; + + /* + * `prev_valid` delayed by one clock cyle. This is to compensate for + * the control pipeline delay. + */ + reg [NUM_OF_SAMPLES-2*SAMPLES_PER_CHANNEL-1:0] prev_valid_d1 = 'h00; + + /* + * synchronization signal that indicates whether the first enabled + * channel is in the first output sample. This will always be true if + * the number of enabled channels is a power of two. + */ + reg sync = 1'b1; + + always @(posedge clk) begin + if (reset_ctrl == 1'b1) begin + sync <= 1'b1; + end else if (ready == 1'b1 && ce == 1'b1) begin + if (rotate == 'h0) begin + sync <= 1'b1; + end else begin + sync <= 1'b0; + end + end + end + + always @(posedge clk) begin + if (ce_ctrl == 1'b1) begin + prev_valid_d1 <= prev_valid; + end + end + + always @(posedge clk) begin + if (ce == 1'b1) begin + data_d1 <= data[2][DELAYED_DATA_WIDTH-1:0]; + end + end + + for (i = 0; i < NUM_OF_SAMPLES; i = i + 1) begin: gen_out_data + localparam w = SAMPLE_DATA_WIDTH; + localparam base = i * w; + if (base >= DELAYED_DATA_WIDTH) begin + assign out_data[base+:w] = data[2][base+:w]; + end else begin + assign out_data[base+:w] = prev_valid_d1[i] == 1'b1 ? data_d1[base+:w] : data[2][base+:w]; + end + end + + assign out_sync = sync; + end else begin + assign out_data = data[2]; + assign out_sync = 1'b1; + end + + assign out_valid = valid; + end else begin + assign out_sync = 1'b1; + assign out_valid = {NUM_OF_SAMPLES{1'b1}}; + assign out_data = data[2]; + end + end + endgenerate + +endmodule diff --git a/adi_library/util_pack/util_upack2/Makefile b/adi_library/util_pack/util_upack2/Makefile new file mode 100644 index 00000000..b77e0bec --- /dev/null +++ b/adi_library/util_pack/util_upack2/Makefile @@ -0,0 +1,21 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_upack2 + +GENERIC_DEPS += ../../common/ad_perfect_shuffle.v +GENERIC_DEPS += ../util_pack_common/pack_ctrl.v +GENERIC_DEPS += ../util_pack_common/pack_interconnect.v +GENERIC_DEPS += ../util_pack_common/pack_network.v +GENERIC_DEPS += ../util_pack_common/pack_shell.v +GENERIC_DEPS += util_upack2_impl.v + +XILINX_DEPS += util_upack2.v +XILINX_DEPS += util_upack2_ip.tcl + +INTEL_DEPS += util_upack2_hw.tcl + +include ../../scripts/library.mk diff --git a/adi_library/util_pack/util_upack2/component.xml b/adi_library/util_pack/util_upack2/component.xml new file mode 100644 index 00000000..4a36a6b7 --- /dev/null +++ b/adi_library/util_pack/util_upack2/component.xml @@ -0,0 +1,3220 @@ + + + analog.com + user + util_upack2 + 1.0 + + + s_axis + + + + + + + TREADY + + + s_axis_ready + + + + + TVALID + + + s_axis_valid + + + + + TDATA + + + s_axis_data + + + + + + s_axis_signal_clock + s_axis_signal_clock + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_BUSIF + s_axis + + + ASSOCIATED_RESET + reset + + + + + s_axis_signal_reset + s_axis_signal_reset + + + + + + + RST + + + reset + + + + + + POLARITY + ACTIVE_HIGH + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_upack2 + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 7207a499 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_upack2 + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 7207a499 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 31df22aa + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + reset + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + enable_0 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + enable_1 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + enable_2 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 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xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + fifo_rd_data_63 + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + s_axis_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_ready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axis_data + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + NUM_OF_CHANNELS + Num Of Channels + 4 + + + SAMPLES_PER_CHANNEL + Samples Per Channel + 1 + + + SAMPLE_DATA_WIDTH + Sample Data Width + 16 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../../common/ad_perfect_shuffle.v + verilogSource + + + ../util_pack_common/pack_ctrl.v + verilogSource + + + ../util_pack_common/pack_interconnect.v + verilogSource + + + ../util_pack_common/pack_network.v + verilogSource + + + ../util_pack_common/pack_shell.v + verilogSource + + + util_upack2_impl.v + verilogSource + + + util_upack2.v + verilogSource + CHECKSUM_afc8d127 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../common/ad_perfect_shuffle.v + verilogSource + + + ../util_pack_common/pack_ctrl.v + verilogSource + + + ../util_pack_common/pack_interconnect.v + verilogSource + + + ../util_pack_common/pack_network.v + verilogSource + + + ../util_pack_common/pack_shell.v + verilogSource + + + util_upack2_impl.v + verilogSource + + + util_upack2.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/util_upack2_v1_0.tcl + tclSource + CHECKSUM_31df22aa + XGUI_VERSION_2 + + + + util_upack2_v1_0 + + + NUM_OF_CHANNELS + Number of Channels + 4 + + + SAMPLES_PER_CHANNEL + Samples per Channel + 1 + + + SAMPLE_DATA_WIDTH + Sample Width + 16 + + + Component_Name + util_upack2_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + util_upack2_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:56:07Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_pack/util_upack2/util_upack2.v b/adi_library/util_pack/util_upack2/util_upack2.v new file mode 100644 index 00000000..3c53e745 --- /dev/null +++ b/adi_library/util_pack/util_upack2/util_upack2.v @@ -0,0 +1,300 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_upack2 #( + parameter NUM_OF_CHANNELS = 4, + parameter SAMPLES_PER_CHANNEL = 1, + parameter SAMPLE_DATA_WIDTH = 16 +) ( + input clk, + input reset, + + input enable_0, + input enable_1, + input enable_2, + input enable_3, + input enable_4, + input enable_5, + input enable_6, + input enable_7, + input enable_8, + input enable_9, + input enable_10, + input enable_11, + input enable_12, + input enable_13, + input enable_14, + input enable_15, + input enable_16, + input enable_17, + input enable_18, + input enable_19, + input enable_20, + input enable_21, + input enable_22, + input enable_23, + input enable_24, + input enable_25, + input enable_26, + input enable_27, + input enable_28, + input enable_29, + input enable_30, + input enable_31, + input enable_32, + input enable_33, + input enable_34, + input enable_35, + input enable_36, + input enable_37, + input enable_38, + input enable_39, + input enable_40, + input enable_41, + input enable_42, + input enable_43, + input enable_44, + input enable_45, + input enable_46, + input enable_47, + input enable_48, + input enable_49, + input enable_50, + input enable_51, + input enable_52, + input enable_53, + input enable_54, + input enable_55, + input enable_56, + input enable_57, + input enable_58, + input enable_59, + input enable_60, + input enable_61, + input enable_62, + input enable_63, + + input fifo_rd_en, + output fifo_rd_valid, + output fifo_rd_underflow, + + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_0, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_1, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_2, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_3, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_4, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_5, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_6, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_7, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_8, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_9, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_10, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_11, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_12, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_13, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_14, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_15, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_16, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_17, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_18, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_19, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_20, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_21, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_22, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_23, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_24, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_25, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_26, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_27, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_28, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_29, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_30, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_31, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_32, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_33, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_34, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_35, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_36, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_37, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_38, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_39, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_40, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_41, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_42, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_43, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_44, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_45, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_46, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_47, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_48, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_49, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_50, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_51, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_52, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_53, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_54, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_55, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_56, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_57, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_58, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_59, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_60, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_61, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_62, + output [SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data_63, + + input s_axis_valid, + output s_axis_ready, + input [2**$clog2(NUM_OF_CHANNELS)*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] s_axis_data +); + + localparam CHANNEL_DATA_WIDTH = SAMPLE_DATA_WIDTH * SAMPLES_PER_CHANNEL; + /* + * Round up to the next power of two and zero out the additional channels + * internally. + */ + localparam REAL_NUM_OF_CHANNELS = NUM_OF_CHANNELS > 32 ? 64 : + NUM_OF_CHANNELS > 16 ? 32 : + NUM_OF_CHANNELS > 8 ? 16 : + NUM_OF_CHANNELS > 4 ? 8 : + NUM_OF_CHANNELS > 2 ? 4 : + NUM_OF_CHANNELS > 1 ? 2 : 1; + + /* FIXME: Find out how to do this in the IP-XACT */ + + wire [63:0] enable_s; + wire [CHANNEL_DATA_WIDTH*REAL_NUM_OF_CHANNELS-1:0] fifo_rd_data; + wire [CHANNEL_DATA_WIDTH*64-1:0] fifo_rd_data_s; + + util_upack2_impl #( + .NUM_OF_CHANNELS(REAL_NUM_OF_CHANNELS), + .SAMPLE_DATA_WIDTH(SAMPLE_DATA_WIDTH), + .SAMPLES_PER_CHANNEL(SAMPLES_PER_CHANNEL) + ) i_upack ( + .clk (clk), + .reset (reset), + + .enable (enable_s[REAL_NUM_OF_CHANNELS-1:0]), + + .fifo_rd_en ({REAL_NUM_OF_CHANNELS{fifo_rd_en}}), + .fifo_rd_valid (fifo_rd_valid), + .fifo_rd_underflow (fifo_rd_underflow), + .fifo_rd_data (fifo_rd_data), + + .s_axis_valid (s_axis_valid), + .s_axis_ready (s_axis_ready), + .s_axis_data (s_axis_data)); + + assign enable_s = { + enable_63,enable_62,enable_61,enable_60,enable_59,enable_58,enable_57,enable_56, + enable_55,enable_54,enable_53,enable_52,enable_51,enable_50,enable_49,enable_48, + enable_47,enable_46,enable_45,enable_44,enable_43,enable_42,enable_41,enable_40, + enable_39,enable_38,enable_37,enable_36,enable_35,enable_34,enable_33,enable_32, + enable_31,enable_30,enable_29,enable_28,enable_27,enable_26,enable_25,enable_24, + enable_23,enable_22,enable_21,enable_20,enable_19,enable_18,enable_17,enable_16, + enable_15,enable_14,enable_13,enable_12,enable_11,enable_10,enable_9,enable_8, + enable_7,enable_6,enable_5,enable_4,enable_3,enable_2,enable_1,enable_0 + }; + + assign fifo_rd_data_s = {{(64-NUM_OF_CHANNELS)*CHANNEL_DATA_WIDTH{1'b0}},fifo_rd_data}; + + assign fifo_rd_data_0 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*0+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_1 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*1+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_2 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*2+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_3 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*3+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_4 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*4+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_5 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*5+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_6 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*6+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_7 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*7+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_8 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*8+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_9 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*9+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_10 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*10+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_11 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*11+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_12 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*12+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_13 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*13+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_14 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*14+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_15 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*15+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_16 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*16+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_17 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*17+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_18 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*18+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_19 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*19+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_20 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*20+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_21 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*21+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_22 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*22+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_23 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*23+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_24 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*24+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_25 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*25+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_26 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*26+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_27 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*27+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_28 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*28+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_29 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*29+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_30 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*30+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_31 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*31+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_32 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*32+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_33 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*33+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_34 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*34+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_35 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*35+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_36 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*36+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_37 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*37+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_38 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*38+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_39 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*39+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_40 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*40+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_41 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*41+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_42 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*42+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_43 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*43+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_44 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*44+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_45 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*45+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_46 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*46+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_47 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*47+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_48 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*48+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_49 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*49+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_50 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*50+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_51 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*51+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_52 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*52+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_53 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*53+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_54 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*54+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_55 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*55+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_56 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*56+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_57 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*57+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_58 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*58+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_59 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*59+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_60 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*60+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_61 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*61+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_62 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*62+:CHANNEL_DATA_WIDTH]; + assign fifo_rd_data_63 = fifo_rd_data_s[CHANNEL_DATA_WIDTH*63+:CHANNEL_DATA_WIDTH]; + +endmodule diff --git a/adi_library/util_pack/util_upack2/util_upack2.xpr b/adi_library/util_pack/util_upack2/util_upack2.xpr new file mode 100644 index 00000000..3c20d48a --- /dev/null +++ b/adi_library/util_pack/util_upack2/util_upack2.xpr @@ -0,0 +1,442 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_pack/util_upack2/util_upack2_hw.tcl b/adi_library/util_pack/util_upack2/util_upack2_hw.tcl new file mode 100644 index 00000000..2193c7a7 --- /dev/null +++ b/adi_library/util_pack/util_upack2/util_upack2_hw.tcl @@ -0,0 +1,94 @@ +############################################################################### +## Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +source ../../../scripts/adi_env.tcl +source ../../scripts/adi_ip_intel.tcl + +ad_ip_create util_upack2 {Channel Unpack Utility v2} util_upack_elab +ad_ip_files util_upack2_impl [list \ + $ad_hdl_dir/library/common/ad_perfect_shuffle.v \ + ../util_pack_common/pack_ctrl.v \ + ../util_pack_common/pack_interconnect.v \ + ../util_pack_common/pack_network.v \ + ../util_pack_common/pack_shell.v \ + util_upack2_impl.v ] + +# parameters + +ad_ip_parameter NUM_OF_CHANNELS INTEGER 4 true [list \ + DISPLAY_NAME "Number of Channels" +] + +ad_ip_parameter SAMPLES_PER_CHANNEL INTEGER 1 true [list \ + DISPLAY_NAME "Samples per Channel" +] + +ad_ip_parameter SAMPLE_DATA_WIDTH INTEGER 16 true [list \ + DISPLAY_NAME "Sample Data Width" +] + +ad_ip_parameter INTERFACE_TYPE INTEGER 0 false [list \ + DISPLAY_NAME "Interface Type" \ + ALLOWED_RANGES {"0:AXIS" "1:FIFO"} \ +] + + +# defaults + +proc util_upack_elab {} { + set num_channels [get_parameter_value NUM_OF_CHANNELS] + set samples_per_channel [get_parameter_value SAMPLES_PER_CHANNEL] + set sample_data_width [get_parameter_value SAMPLE_DATA_WIDTH] + set interface_type [get_parameter_value INTERFACE_TYPE] + + set channel_data_width [expr $sample_data_width * $samples_per_channel] + set total_data_width [expr $num_channels * $channel_data_width] + + add_interface clk clock end + add_interface_port clk clk clk Input 1 + add_interface reset reset end + add_interface_port reset reset reset Input 1 + set_interface_property reset associatedClock clk + + # This is a temporary hack and should be removed once all projects have been + # updated to use the AXI streaming interface to connect the the upack + if {$interface_type == 0} { + add_interface s_axis axi4stream end + set_interface_property s_axis associatedClock clk + set_interface_property s_axis associatedReset reset + add_interface_port s_axis s_axis_valid tvalid Input 1 + add_interface_port s_axis s_axis_ready tready Output 1 + add_interface_port s_axis s_axis_data tdata Input $total_data_width + } else { + ad_interface signal packed_fifo_rd_en output 1 valid + set_port_property packed_fifo_rd_en fragment_list "s_axis_ready" + ad_interface signal packed_fifo_rd_data input $total_data_width data + set_port_property packed_fifo_rd_data fragment_list \ + [format "s_axis_data(%d:0)" [expr $total_data_width - 1]] + ad_interface signal s_axis_valid input 1 valid + set_port_property s_axis_valid TERMINATION TRUE + set_port_property s_axis_valid TERMINATION_VALUE 1 + } + + ad_interface signal fifo_rd_underflow output 1 unf + + for {set n 0} {$n < $num_channels} {incr n} { + add_interface dac_ch_${n} conduit end + add_interface_port dac_ch_${n} enable_${n} enable Input 1 + set_port_property enable_${n} fragment_list "enable(${n}:${n})" + + add_interface_port dac_ch_${n} fifo_rd_en_${n} valid Input 1 + set_port_property fifo_rd_en_${n} fragment_list "fifo_rd_en(${n})" + add_interface_port dac_ch_${n} fifo_rd_valid_${n} data_valid Output 1 + set_port_property fifo_rd_valid_${n} fragment_list "fifo_rd_valid(0)" + add_interface_port dac_ch_${n} fifo_rd_data_${n} data Output $channel_data_width + set_port_property fifo_rd_data_${n} fragment_list [format "fifo_rd_data(%d:%d)" \ + [expr ($n+1) * $channel_data_width - 1] [expr $n * $channel_data_width]] + set_interface_property dac_ch_${n} associatedClock clk + set_interface_property dac_ch_${n} associatedReset "" + } +} + diff --git a/adi_library/util_pack/util_upack2/util_upack2_impl.v b/adi_library/util_pack/util_upack2/util_upack2_impl.v new file mode 100644 index 00000000..395a76fa --- /dev/null +++ b/adi_library/util_pack/util_upack2/util_upack2_impl.v @@ -0,0 +1,144 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_upack2_impl #( + parameter NUM_OF_CHANNELS = 4, + parameter SAMPLES_PER_CHANNEL = 1, + parameter SAMPLE_DATA_WIDTH = 16 +) ( + input clk, + input reset, + + input [NUM_OF_CHANNELS-1:0] enable, + + input [NUM_OF_CHANNELS-1:0] fifo_rd_en, + output reg fifo_rd_valid, + output reg fifo_rd_underflow, + output reg [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] fifo_rd_data, + + input s_axis_valid, + output s_axis_ready, + input [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] s_axis_data +); + + /* + * Final output data of the routing network that will be written to + * `fifo_rd_data` after being deinterleaved. + */ + wire [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] out_data; + + /* + * Deinterleaved version of `out_data` + */ + wire [NUM_OF_CHANNELS*SAMPLE_DATA_WIDTH*SAMPLES_PER_CHANNEL-1:0] deinterleaved_data; + + /* + * Internal read signal. + */ + wire data_rd_en; + + /* + * Control signals from/to the pack shell. + */ + wire ce; + wire ready; + wire reset_data; + + /* + * Only the first signal of fifo_rd_en is used. All others are ignored. The + * only reason why fifo_rd_en has multiple entries is to keep the interface + * somewhat backwards compatible to the previous upack. + */ + assign data_rd_en = fifo_rd_en[0]; + + assign ce = s_axis_valid & data_rd_en; + assign s_axis_ready = ready & ce; + + pack_shell #( + .NUM_OF_CHANNELS (NUM_OF_CHANNELS), + .SAMPLES_PER_CHANNEL (SAMPLES_PER_CHANNEL), + .SAMPLE_DATA_WIDTH (SAMPLE_DATA_WIDTH), + .PACK (0) + ) i_pack_shell ( + .clk (clk), + .reset (reset), + + .reset_data (reset_data), + + .enable (enable), + .ce (ce), + .ready (ready), + .in_data (s_axis_data), + .out_data (out_data), + + .out_valid (), + .out_sync ()); + + /* + * Data at the output of the routing network is interleaved. The upack + * core is supposed to produce deinterleaved data. This just rearrange the + * bits in the data vector and does not consume any FPGA resources. + */ + ad_perfect_shuffle #( + .NUM_GROUPS (SAMPLES_PER_CHANNEL), + .WORDS_PER_GROUP (NUM_OF_CHANNELS), + .WORD_WIDTH (SAMPLE_DATA_WIDTH) + ) i_deinterleave ( + .data_in (out_data), + .data_out (deinterleaved_data)); + + always @(posedge clk) begin + /* In case of an underflow the output vector should be zeroed */ + if (reset_data == 1'b1 || + (data_rd_en == 1'b1 && s_axis_valid == 1'b0)) begin + fifo_rd_data <= 'h00; + end else if (data_rd_en == 1'b1) begin + fifo_rd_data <= deinterleaved_data; + end + end + + always @(posedge clk) begin + if (data_rd_en == 1'b1) begin + fifo_rd_valid <= s_axis_valid & ~reset_data; + fifo_rd_underflow <= ~(s_axis_valid & ~reset_data); + end else begin + fifo_rd_valid <= 1'b0; + fifo_rd_underflow <= 1'b0; + end + end + +endmodule diff --git a/adi_library/util_pack/util_upack2/util_upack2_ip.tcl b/adi_library/util_pack/util_upack2/util_upack2_ip.tcl new file mode 100644 index 00000000..9a1c2b7d --- /dev/null +++ b/adi_library/util_pack/util_upack2/util_upack2_ip.tcl @@ -0,0 +1,52 @@ +############################################################################### +## Copyright (C) 2018-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_upack2 +adi_ip_files util_upack2 [list \ + "../../common/ad_perfect_shuffle.v" \ + "../util_pack_common/pack_ctrl.v" \ + "../util_pack_common/pack_interconnect.v" \ + "../util_pack_common/pack_network.v" \ + "../util_pack_common/pack_shell.v" \ + "util_upack2_impl.v" \ + "util_upack2.v" ] + +set_property source_mgmt_mode DisplayOnly [current_project] + +adi_ip_properties_lite util_upack2 + +adi_add_bus "s_axis" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [list {"s_axis_ready" "TREADY"} \ + {"s_axis_valid" "TVALID"} \ + {"s_axis_data" "TDATA"} \ + ] +adi_add_bus_clock "clk" "s_axis" "reset" + +set cc [ipx::current_core] + +for {set i 1} {$i < 64} {incr i} { + set_property enablement_dependency "spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > $i" \ + [ipx::get_ports *_$i -of_objects $cc] +} + +foreach {k v} { \ + "NUM_OF_CHANNELS" "Number of Channels" \ + "SAMPLES_PER_CHANNEL" "Samples per Channel" \ + "SAMPLE_DATA_WIDTH" "Sample Width" \ + } { \ + set p [ipgui::get_guiparamspec -name $k -component $cc] +# ipgui::move_param -component $cc -order $i $p -parent $ + set_property -dict [list \ + DISPLAY_NAME $v \ + ] $p + incr i +} + +ipx::save_core [ipx::current_core] diff --git a/adi_library/util_pack/util_upack2/xgui/util_upack2_v1_0.tcl b/adi_library/util_pack/util_upack2/xgui/util_upack2_v1_0.tcl new file mode 100644 index 00000000..af369bd7 --- /dev/null +++ b/adi_library/util_pack/util_upack2/xgui/util_upack2_v1_0.tcl @@ -0,0 +1,55 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "NUM_OF_CHANNELS" -parent ${Page_0} + ipgui::add_param $IPINST -name "SAMPLES_PER_CHANNEL" -parent ${Page_0} + ipgui::add_param $IPINST -name "SAMPLE_DATA_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to update NUM_OF_CHANNELS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to validate NUM_OF_CHANNELS + return true +} + +proc update_PARAM_VALUE.SAMPLES_PER_CHANNEL { PARAM_VALUE.SAMPLES_PER_CHANNEL } { + # Procedure called to update SAMPLES_PER_CHANNEL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SAMPLES_PER_CHANNEL { PARAM_VALUE.SAMPLES_PER_CHANNEL } { + # Procedure called to validate SAMPLES_PER_CHANNEL + return true +} + +proc update_PARAM_VALUE.SAMPLE_DATA_WIDTH { PARAM_VALUE.SAMPLE_DATA_WIDTH } { + # Procedure called to update SAMPLE_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SAMPLE_DATA_WIDTH { PARAM_VALUE.SAMPLE_DATA_WIDTH } { + # Procedure called to validate SAMPLE_DATA_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.NUM_OF_CHANNELS { MODELPARAM_VALUE.NUM_OF_CHANNELS PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_CHANNELS}] ${MODELPARAM_VALUE.NUM_OF_CHANNELS} +} + +proc update_MODELPARAM_VALUE.SAMPLES_PER_CHANNEL { MODELPARAM_VALUE.SAMPLES_PER_CHANNEL PARAM_VALUE.SAMPLES_PER_CHANNEL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SAMPLES_PER_CHANNEL}] ${MODELPARAM_VALUE.SAMPLES_PER_CHANNEL} +} + +proc update_MODELPARAM_VALUE.SAMPLE_DATA_WIDTH { MODELPARAM_VALUE.SAMPLE_DATA_WIDTH PARAM_VALUE.SAMPLE_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SAMPLE_DATA_WIDTH}] ${MODELPARAM_VALUE.SAMPLE_DATA_WIDTH} +} + diff --git a/adi_library/util_pad/Makefile b/adi_library/util_pad/Makefile new file mode 100644 index 00000000..7b2ec41f --- /dev/null +++ b/adi_library/util_pad/Makefile @@ -0,0 +1,13 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_pad + +GENERIC_DEPS += util_pad.v + +XILINX_DEPS += util_pad_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/util_pad/component.xml b/adi_library/util_pad/component.xml new file mode 100644 index 00000000..846b9087 --- /dev/null +++ b/adi_library/util_pad/component.xml @@ -0,0 +1,226 @@ + + + analog.com + user + util_pad + 1.0 + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_pad + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + b9c6e2ac + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_pad + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + b9c6e2ac + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 4f92a007 + + + + + + + data_in + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_out + + out + + 31 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + NUM_OF_SAMPLES + Num Of Samples + 2 + + + IN_BITS_PER_SAMPLE + In Bits Per Sample + 16 + + + OUT_BITS_PER_SAMPLE + Out Bits Per Sample + 16 + + + PADDING_TO_MSB_LSB_N + Padding To Msb Lsb N + 0 + + + SIGN_EXTEND + Sign Extend + 1 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + util_pad.v + verilogSource + CHECKSUM_b9c6e2ac + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + util_pad.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/util_pad_v1_0.tcl + tclSource + CHECKSUM_4f92a007 + XGUI_VERSION_2 + + + + util_pad_v1_0 + + + NUM_OF_SAMPLES + Num Of Samples + 2 + + + IN_BITS_PER_SAMPLE + In Bits Per Sample + 16 + + + OUT_BITS_PER_SAMPLE + Out Bits Per Sample + 16 + + + PADDING_TO_MSB_LSB_N + Padding To Msb Lsb N + 0 + + + SIGN_EXTEND + Sign Extend + 1 + + + Component_Name + util_pad_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + util_pad_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:56:14Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_pad/util_pad.v b/adi_library/util_pad/util_pad.v new file mode 100644 index 00000000..c3bd5b84 --- /dev/null +++ b/adi_library/util_pad/util_pad.v @@ -0,0 +1,83 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_pad #( + parameter NUM_OF_SAMPLES = 2, + parameter IN_BITS_PER_SAMPLE = 16, + parameter OUT_BITS_PER_SAMPLE = 16, + parameter PADDING_TO_MSB_LSB_N = 0, + parameter SIGN_EXTEND = 1 +) ( + input [NUM_OF_SAMPLES*IN_BITS_PER_SAMPLE-1:0] data_in, + output reg [NUM_OF_SAMPLES*OUT_BITS_PER_SAMPLE-1:0] data_out +); + + // Remove padding + if (IN_BITS_PER_SAMPLE >= OUT_BITS_PER_SAMPLE) begin + integer i; + always @(*) begin + for (i=0;i + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_pad/util_pad_ip.tcl b/adi_library/util_pad/util_pad_ip.tcl new file mode 100644 index 00000000..9432309a --- /dev/null +++ b/adi_library/util_pad/util_pad_ip.tcl @@ -0,0 +1,16 @@ +############################################################################### +## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_pad +adi_ip_files util_pad [list \ + "util_pad.v" ] + +adi_ip_properties_lite util_pad + +ipx::save_core [ipx::current_core] diff --git a/adi_library/util_pad/xgui/util_pad_v1_0.tcl b/adi_library/util_pad/xgui/util_pad_v1_0.tcl new file mode 100644 index 00000000..9a22dd87 --- /dev/null +++ b/adi_library/util_pad/xgui/util_pad_v1_0.tcl @@ -0,0 +1,85 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "IN_BITS_PER_SAMPLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_OF_SAMPLES" -parent ${Page_0} + ipgui::add_param $IPINST -name "OUT_BITS_PER_SAMPLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "PADDING_TO_MSB_LSB_N" -parent ${Page_0} + ipgui::add_param $IPINST -name "SIGN_EXTEND" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.IN_BITS_PER_SAMPLE { PARAM_VALUE.IN_BITS_PER_SAMPLE } { + # Procedure called to update IN_BITS_PER_SAMPLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IN_BITS_PER_SAMPLE { PARAM_VALUE.IN_BITS_PER_SAMPLE } { + # Procedure called to validate IN_BITS_PER_SAMPLE + return true +} + +proc update_PARAM_VALUE.NUM_OF_SAMPLES { PARAM_VALUE.NUM_OF_SAMPLES } { + # Procedure called to update NUM_OF_SAMPLES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_SAMPLES { PARAM_VALUE.NUM_OF_SAMPLES } { + # Procedure called to validate NUM_OF_SAMPLES + return true +} + +proc update_PARAM_VALUE.OUT_BITS_PER_SAMPLE { PARAM_VALUE.OUT_BITS_PER_SAMPLE } { + # Procedure called to update OUT_BITS_PER_SAMPLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_BITS_PER_SAMPLE { PARAM_VALUE.OUT_BITS_PER_SAMPLE } { + # Procedure called to validate OUT_BITS_PER_SAMPLE + return true +} + +proc update_PARAM_VALUE.PADDING_TO_MSB_LSB_N { PARAM_VALUE.PADDING_TO_MSB_LSB_N } { + # Procedure called to update PADDING_TO_MSB_LSB_N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PADDING_TO_MSB_LSB_N { PARAM_VALUE.PADDING_TO_MSB_LSB_N } { + # Procedure called to validate PADDING_TO_MSB_LSB_N + return true +} + +proc update_PARAM_VALUE.SIGN_EXTEND { PARAM_VALUE.SIGN_EXTEND } { + # Procedure called to update SIGN_EXTEND when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SIGN_EXTEND { PARAM_VALUE.SIGN_EXTEND } { + # Procedure called to validate SIGN_EXTEND + return true +} + + +proc update_MODELPARAM_VALUE.NUM_OF_SAMPLES { MODELPARAM_VALUE.NUM_OF_SAMPLES PARAM_VALUE.NUM_OF_SAMPLES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_SAMPLES}] ${MODELPARAM_VALUE.NUM_OF_SAMPLES} +} + +proc update_MODELPARAM_VALUE.IN_BITS_PER_SAMPLE { MODELPARAM_VALUE.IN_BITS_PER_SAMPLE PARAM_VALUE.IN_BITS_PER_SAMPLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IN_BITS_PER_SAMPLE}] ${MODELPARAM_VALUE.IN_BITS_PER_SAMPLE} +} + +proc update_MODELPARAM_VALUE.OUT_BITS_PER_SAMPLE { MODELPARAM_VALUE.OUT_BITS_PER_SAMPLE PARAM_VALUE.OUT_BITS_PER_SAMPLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_BITS_PER_SAMPLE}] ${MODELPARAM_VALUE.OUT_BITS_PER_SAMPLE} +} + +proc update_MODELPARAM_VALUE.PADDING_TO_MSB_LSB_N { MODELPARAM_VALUE.PADDING_TO_MSB_LSB_N PARAM_VALUE.PADDING_TO_MSB_LSB_N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PADDING_TO_MSB_LSB_N}] ${MODELPARAM_VALUE.PADDING_TO_MSB_LSB_N} +} + +proc update_MODELPARAM_VALUE.SIGN_EXTEND { MODELPARAM_VALUE.SIGN_EXTEND PARAM_VALUE.SIGN_EXTEND } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SIGN_EXTEND}] ${MODELPARAM_VALUE.SIGN_EXTEND} +} + diff --git a/adi_library/util_pulse_gen/Makefile b/adi_library/util_pulse_gen/Makefile new file mode 100644 index 00000000..c88c3a98 --- /dev/null +++ b/adi_library/util_pulse_gen/Makefile @@ -0,0 +1,13 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_pulse_gen + +GENERIC_DEPS += ../common/util_pulse_gen.v + +XILINX_DEPS += util_pulse_gen_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/util_pulse_gen/component.xml b/adi_library/util_pulse_gen/component.xml new file mode 100644 index 00000000..439ed05d --- /dev/null +++ b/adi_library/util_pulse_gen/component.xml @@ -0,0 +1,318 @@ + + + analog.com + user + util_pulse_gen + 1.0 + + + clk + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_RESET + rstn + + + + + rstn + + + + + + + RST + + + rstn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_pulse_gen + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 549b8bb7 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_pulse_gen + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 549b8bb7 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 936e6374 + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rstn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + pulse_width + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + pulse_period + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + load_config + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + pulse + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + pulse_counter + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + PULSE_WIDTH + Pulse Width + 7 + + + PULSE_PERIOD + Pulse Period + 100000000 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + ../common/util_pulse_gen.v + verilogSource + CHECKSUM_549b8bb7 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/util_pulse_gen.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/util_pulse_gen_v1_0.tcl + tclSource + CHECKSUM_936e6374 + XGUI_VERSION_2 + + + + util_pulse_gen_v1_0 + + + PULSE_WIDTH + Pulse Width + 7 + + + PULSE_PERIOD + Pulse Period + 100000000 + + + Component_Name + util_pulse_gen_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + util_pulse_gen_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:56:22Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_pulse_gen/util_pulse_gen.xpr b/adi_library/util_pulse_gen/util_pulse_gen.xpr new file mode 100644 index 00000000..37445c99 --- /dev/null +++ b/adi_library/util_pulse_gen/util_pulse_gen.xpr @@ -0,0 +1,399 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_pulse_gen/util_pulse_gen_ip.tcl b/adi_library/util_pulse_gen/util_pulse_gen_ip.tcl new file mode 100644 index 00000000..cdd3f129 --- /dev/null +++ b/adi_library/util_pulse_gen/util_pulse_gen_ip.tcl @@ -0,0 +1,20 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_pulse_gen +adi_ip_files util_pulse_gen [list \ + "$ad_hdl_dir/library/common/util_pulse_gen.v"] + +adi_ip_properties_lite util_pulse_gen +ipx::remove_all_bus_interface [ipx::current_core] + +ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/util_pulse_gen/xgui/util_pulse_gen_v1_0.tcl b/adi_library/util_pulse_gen/xgui/util_pulse_gen_v1_0.tcl new file mode 100644 index 00000000..f884512f --- /dev/null +++ b/adi_library/util_pulse_gen/xgui/util_pulse_gen_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "PULSE_PERIOD" -parent ${Page_0} + ipgui::add_param $IPINST -name "PULSE_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.PULSE_PERIOD { PARAM_VALUE.PULSE_PERIOD } { + # Procedure called to update PULSE_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_PERIOD { PARAM_VALUE.PULSE_PERIOD } { + # Procedure called to validate PULSE_PERIOD + return true +} + +proc update_PARAM_VALUE.PULSE_WIDTH { PARAM_VALUE.PULSE_WIDTH } { + # Procedure called to update PULSE_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PULSE_WIDTH { PARAM_VALUE.PULSE_WIDTH } { + # Procedure called to validate PULSE_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.PULSE_WIDTH { MODELPARAM_VALUE.PULSE_WIDTH PARAM_VALUE.PULSE_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_WIDTH}] ${MODELPARAM_VALUE.PULSE_WIDTH} +} + +proc update_MODELPARAM_VALUE.PULSE_PERIOD { MODELPARAM_VALUE.PULSE_PERIOD PARAM_VALUE.PULSE_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PULSE_PERIOD}] ${MODELPARAM_VALUE.PULSE_PERIOD} +} + diff --git a/adi_library/util_rfifo/Makefile b/adi_library/util_rfifo/Makefile new file mode 100644 index 00000000..bf2181e3 --- /dev/null +++ b/adi_library/util_rfifo/Makefile @@ -0,0 +1,18 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_rfifo + +GENERIC_DEPS += ../common/ad_mem.v +GENERIC_DEPS += util_rfifo.v + +XILINX_DEPS += util_rfifo_constr.xdc +XILINX_DEPS += util_rfifo_ip.tcl + +INTEL_DEPS += util_rfifo_constr.sdc +INTEL_DEPS += util_rfifo_hw.tcl + +include ../scripts/library.mk diff --git a/adi_library/util_rfifo/component.xml b/adi_library/util_rfifo/component.xml new file mode 100644 index 00000000..02475a84 --- /dev/null +++ b/adi_library/util_rfifo/component.xml @@ -0,0 +1,1774 @@ + + + analog.com + user + util_rfifo + 1.0 + + + din_clk + + + + + + + CLK + + + din_clk + + + + + + ASSOCIATED_RESET + din_rstn + + + + + dout_clk + + + + + + + CLK + + + dout_clk + + + + + + ASSOCIATED_RESET + dout_rst + + + + + din_rstn + + + + + + + RST + + + din_rstn + + + + + + POLARITY + ACTIVE_LOW + + + + + dout_rst + + + + + + + RST + + + dout_rst + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_rfifo + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 85e19357 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_rfifo + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + f5768c51 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 70b62934 + + + + + + + din_rstn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + din_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + din_enable_0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + din_valid_0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + din_valid_in_0 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + din_data_0 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + din_enable_1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + din_valid_1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + din_valid_in_1 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + din_data_1 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + din_enable_2 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + din_valid_2 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + din_valid_in_2 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + din_data_2 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + din_enable_3 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + din_valid_3 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + din_valid_in_3 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + din_data_3 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + din_enable_4 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + din_valid_4 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + din_valid_in_4 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + din_data_4 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + din_enable_5 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + din_valid_5 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + din_valid_in_5 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + din_data_5 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + din_enable_6 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + din_valid_6 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + din_valid_in_6 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + din_data_6 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + din_enable_7 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + din_valid_7 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + din_valid_in_7 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + din_data_7 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + din_unf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + dout_rst + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dout_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dout_enable_0 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + dout_valid_0 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + dout_valid_out_0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + dout_data_0 + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dout_enable_1 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + dout_valid_1 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + dout_valid_out_1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + dout_data_1 + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + dout_enable_2 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + dout_valid_2 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + dout_valid_out_2 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + dout_data_2 + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + dout_enable_3 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + dout_valid_3 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + dout_valid_out_3 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + dout_data_3 + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + dout_enable_4 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dout_valid_4 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dout_valid_out_4 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dout_data_4 + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout_enable_5 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dout_valid_5 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dout_valid_out_5 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dout_data_5 + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout_enable_6 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dout_valid_6 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dout_valid_out_6 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dout_data_6 + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout_enable_7 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dout_valid_7 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dout_valid_out_7 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + dout_data_7 + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout_unf + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + NUM_OF_CHANNELS + Num Of Channels + 4 + + + DIN_DATA_WIDTH + Din Data Width + 32 + + + DOUT_DATA_WIDTH + Dout Data Width + 64 + + + DIN_ADDRESS_WIDTH + Din Address Width + 8 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + util_rfifo_constr.xdc + xdc + + + ../common/ad_mem.v + verilogSource + + + util_rfifo.v + verilogSource + CHECKSUM_1e6c5072 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_mem.v + verilogSource + + + util_rfifo.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/util_rfifo_v1_0.tcl + tclSource + CHECKSUM_70b62934 + XGUI_VERSION_2 + + + + util_rfifo_v1_0 + + + NUM_OF_CHANNELS + Num Of Channels + 4 + + + DIN_DATA_WIDTH + Din Data Width + 32 + + + DOUT_DATA_WIDTH + Dout Data Width + 64 + + + DIN_ADDRESS_WIDTH + Din Address Width + 8 + + + Component_Name + util_rfifo_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + util_rfifo_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/util_rfifo + 1 + 2024-01-14T03:56:30Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_rfifo/util_rfifo.v b/adi_library/util_rfifo/util_rfifo.v new file mode 100644 index 00000000..608f5e75 --- /dev/null +++ b/adi_library/util_rfifo/util_rfifo.v @@ -0,0 +1,405 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_rfifo #( + + parameter NUM_OF_CHANNELS = 4, + parameter DIN_DATA_WIDTH = 32, + parameter DOUT_DATA_WIDTH = 64, + parameter DIN_ADDRESS_WIDTH = 8 +) ( + + // d-in interface + + input din_rstn, + input din_clk, + output din_enable_0, + output din_valid_0, + input din_valid_in_0, + input [DIN_DATA_WIDTH-1:0] din_data_0, + output din_enable_1, + output din_valid_1, + input din_valid_in_1, + input [DIN_DATA_WIDTH-1:0] din_data_1, + output din_enable_2, + output din_valid_2, + input din_valid_in_2, + input [DIN_DATA_WIDTH-1:0] din_data_2, + output din_enable_3, + output din_valid_3, + input din_valid_in_3, + input [DIN_DATA_WIDTH-1:0] din_data_3, + output din_enable_4, + output din_valid_4, + input din_valid_in_4, + input [DIN_DATA_WIDTH-1:0] din_data_4, + output din_enable_5, + output din_valid_5, + input din_valid_in_5, + input [DIN_DATA_WIDTH-1:0] din_data_5, + output din_enable_6, + output din_valid_6, + input din_valid_in_6, + input [DIN_DATA_WIDTH-1:0] din_data_6, + output din_enable_7, + output din_valid_7, + input din_valid_in_7, + input [DIN_DATA_WIDTH-1:0] din_data_7, + input din_unf, + + // d-out interface + + input dout_rst, + input dout_clk, + input dout_enable_0, + input dout_valid_0, + output dout_valid_out_0, + output [DOUT_DATA_WIDTH-1:0] dout_data_0, + input dout_enable_1, + input dout_valid_1, + output dout_valid_out_1, + output [DOUT_DATA_WIDTH-1:0] dout_data_1, + input dout_enable_2, + input dout_valid_2, + output dout_valid_out_2, + output [DOUT_DATA_WIDTH-1:0] dout_data_2, + input dout_enable_3, + input dout_valid_3, + output dout_valid_out_3, + output [DOUT_DATA_WIDTH-1:0] dout_data_3, + input dout_enable_4, + input dout_valid_4, + output dout_valid_out_4, + output [DOUT_DATA_WIDTH-1:0] dout_data_4, + input dout_enable_5, + input dout_valid_5, + output dout_valid_out_5, + output [DOUT_DATA_WIDTH-1:0] dout_data_5, + input dout_enable_6, + input dout_valid_6, + output dout_valid_out_6, + output [DOUT_DATA_WIDTH-1:0] dout_data_6, + input dout_enable_7, + input dout_valid_7, + output dout_valid_out_7, + output [DOUT_DATA_WIDTH-1:0] dout_data_7, + output reg dout_unf +); + + localparam M_MEM_RATIO = DOUT_DATA_WIDTH/DIN_DATA_WIDTH; + localparam ADDRESS_WIDTH = (DIN_ADDRESS_WIDTH > 5) ? DIN_ADDRESS_WIDTH : 5; + localparam DATA_WIDTH = DOUT_DATA_WIDTH * NUM_OF_CHANNELS; + localparam T_DIN_DATA_WIDTH = DIN_DATA_WIDTH * 8; + localparam T_DOUT_DATA_WIDTH = DOUT_DATA_WIDTH * 8; + + // internal registers + + reg [(DATA_WIDTH-1):0] din_wdata = 'd0; + reg [(ADDRESS_WIDTH-1):0] din_waddr = 'hc; + reg din_wr = 'd0; + reg din_valid = 'd0; + reg [ 6:0] din_req_cnt = 'd0; + reg [ 7:0] din_enable_m1 = 'd0; + reg [ 7:0] din_enable = 'd0; + reg din_req_t_m1 = 'd0; + reg din_req_t_m2 = 'd0; + reg din_req_t_m3 = 'd0; + reg din_req = 'd0; + reg din_init = 'd0; + reg din_unf_d = 'd0; + reg [ 7:0] dout_valid = 'd0; + reg [(T_DOUT_DATA_WIDTH+1):0] dout_data = 'd0; + reg [(DATA_WIDTH-1):0] dout_rdata = 'd0; + reg [ 7:0] dout_enable = 'd0; + reg dout_req_t = 'd0; + reg dout_init = 'd0; + reg [(ADDRESS_WIDTH-1):0] dout_raddr = 'd0; + reg dout_unf_m1 = 'd0; + + // internal signals + + wire [(T_DIN_DATA_WIDTH-1):0] din_data_s; + wire din_req_s; + wire [ 7:0] dout_enable_s; + wire [ 7:0] dout_valid_s; + wire [(T_DOUT_DATA_WIDTH+1):0] dout_data_s; + wire dout_init_s; + wire [(DATA_WIDTH-1):0] dout_rdata_s; + wire [ 2:0] din_wcnt_s; + + // variables + + // enables & valids + + assign din_enable_7 = din_enable[7]; + assign din_enable_6 = din_enable[6]; + assign din_enable_5 = din_enable[5]; + assign din_enable_4 = din_enable[4]; + assign din_enable_3 = din_enable[3]; + assign din_enable_2 = din_enable[2]; + assign din_enable_1 = din_enable[1]; + assign din_enable_0 = din_enable[0]; + + assign din_valid_7 = din_valid; + assign din_valid_6 = din_valid; + assign din_valid_5 = din_valid; + assign din_valid_4 = din_valid; + assign din_valid_3 = din_valid; + assign din_valid_2 = din_valid; + assign din_valid_1 = din_valid; + assign din_valid_0 = din_valid; + + assign din_data_s = {din_data_7, din_data_6, din_data_5, din_data_4, + din_data_3, din_data_2, din_data_1, din_data_0}; + + // simple data transfer-- no ovf/unf handling- read-bw > write-bw + // dout_width >= din_width only + + genvar n; + generate + for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_in + if (M_MEM_RATIO == 1) begin + always @(posedge din_clk) begin + if (din_valid_in_0 == 1'b1) begin + din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <= + din_data_s[((DIN_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH*n)]; + end + end + end else begin + always @(posedge din_clk) begin + if (din_valid_in_0 == 1'b1) begin + din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <= + {din_data_s[((DIN_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH*n)], + din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH+(DOUT_DATA_WIDTH*n))]}; + end + end + end + end + endgenerate + + generate + if (M_MEM_RATIO == 1) begin + assign din_wcnt_s = 'b0; + end else begin + reg [ 2:0] din_wcnt = 'd0; + + always @(posedge din_clk or negedge din_rstn) + if (din_rstn == 1'b0) begin + din_wcnt <= 'd0; + end else begin + if (din_valid_in_0 == 1'b1) begin + din_wcnt <= din_wcnt + 1'b1; + end + end + + assign din_wcnt_s = din_wcnt; + end + endgenerate + + always @(posedge din_clk or negedge din_rstn) begin + if (din_rstn == 1'b0) begin + din_waddr <= 'hc; + din_wr <= 1'd0; + end else begin + if ((din_req == 1'b1) && (din_init == 1'b1)) begin + din_waddr <= 'h18; + end else if (din_wr == 1'b1) begin + din_waddr <= din_waddr + 1'b1; + end + case (M_MEM_RATIO) + 8: din_wr <= din_valid_in_0 & din_wcnt_s[2] & din_wcnt_s[1] & din_wcnt_s[0]; + 4: din_wr <= din_valid_in_0 & din_wcnt_s[1] & din_wcnt_s[0]; + 2: din_wr <= din_valid_in_0 & din_wcnt_s[0]; + default: din_wr <= din_valid_in_0; + endcase + end + end + + always @(posedge din_clk or negedge din_rstn) begin + if (din_rstn == 1'b0) begin + din_valid <= 'd0; + din_req_cnt <= 'd0; + end else begin + din_valid <= din_req_cnt[6]; + if (din_req_s == 1'b1) begin + case (M_MEM_RATIO) + 8: din_req_cnt <= 7'h40; + 4: din_req_cnt <= 7'h60; + 2: din_req_cnt <= 7'h70; + default: din_req_cnt <= 7'h78; + endcase + end else if (din_req_cnt[6] == 1'b1) begin + din_req_cnt <= din_req_cnt + 1'b1; + end + end + end + + assign din_req_s = din_req_t_m3 ^ din_req_t_m2; + + always @(posedge din_clk or negedge din_rstn) begin + if (din_rstn == 1'b0) begin + din_enable_m1 <= 'd0; + din_enable <= 'd0; + din_req_t_m1 <= 'd0; + din_req_t_m2 <= 'd0; + din_req_t_m3 <= 'd0; + din_req <= 'd0; + din_init <= 'd0; + din_unf_d <= 'd0; + end else begin + din_enable_m1 <= dout_enable; + din_enable <= din_enable_m1; + din_req_t_m1 <= dout_req_t; + din_req_t_m2 <= din_req_t_m1; + din_req_t_m3 <= din_req_t_m2; + din_req <= din_req_s; + if (din_req_s == 1'b1) begin + din_init <= dout_init; + end + din_unf_d <= din_unf; + end + end + + // read interface (bus expansion and/or clock conversion) + + assign dout_enable_s = {dout_enable_7, dout_enable_6, dout_enable_5, dout_enable_4, + dout_enable_3, dout_enable_2, dout_enable_1, dout_enable_0}; + assign dout_valid_s = {dout_valid_7, dout_valid_6, dout_valid_5, dout_valid_4, + dout_valid_3, dout_valid_2, dout_valid_1, dout_valid_0}; + + generate + if (NUM_OF_CHANNELS >= 8) begin + assign dout_data_s = dout_rdata; + end else begin + assign dout_data_s[(T_DOUT_DATA_WIDTH+1):DATA_WIDTH] = 'd0; + assign dout_data_s[(DATA_WIDTH-1):0] = dout_rdata; + end + endgenerate + + assign dout_valid_out_7 = dout_valid[7]; + assign dout_valid_out_6 = dout_valid[6]; + assign dout_valid_out_5 = dout_valid[5]; + assign dout_valid_out_4 = dout_valid[4]; + assign dout_valid_out_3 = dout_valid[3]; + assign dout_valid_out_2 = dout_valid[2]; + assign dout_valid_out_1 = dout_valid[1]; + assign dout_valid_out_0 = dout_valid[0]; + + assign dout_data_7 = dout_data[((DOUT_DATA_WIDTH*8)-1):(DOUT_DATA_WIDTH*7)]; + assign dout_data_6 = dout_data[((DOUT_DATA_WIDTH*7)-1):(DOUT_DATA_WIDTH*6)]; + assign dout_data_5 = dout_data[((DOUT_DATA_WIDTH*6)-1):(DOUT_DATA_WIDTH*5)]; + assign dout_data_4 = dout_data[((DOUT_DATA_WIDTH*5)-1):(DOUT_DATA_WIDTH*4)]; + assign dout_data_3 = dout_data[((DOUT_DATA_WIDTH*4)-1):(DOUT_DATA_WIDTH*3)]; + assign dout_data_2 = dout_data[((DOUT_DATA_WIDTH*3)-1):(DOUT_DATA_WIDTH*2)]; + assign dout_data_1 = dout_data[((DOUT_DATA_WIDTH*2)-1):(DOUT_DATA_WIDTH*1)]; + assign dout_data_0 = dout_data[((DOUT_DATA_WIDTH*1)-1):(DOUT_DATA_WIDTH*0)]; + + always @(posedge dout_clk) begin + if (dout_rst == 1'b1) begin + dout_valid <= 8'd0; + end else begin + dout_valid <= dout_valid_s; + end + end + + generate + for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_out + always @(posedge dout_clk) begin + if (dout_rst == 1'b1) begin + dout_data[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <= 'd0; + end else if (dout_valid_s[n] == 1'b1) begin + dout_data[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <= + dout_data_s[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)]; + end + end + end + endgenerate + + always @(posedge dout_clk) begin + dout_rdata <= dout_rdata_s; + end + + assign dout_init_s = (dout_enable == dout_enable_s) ? 1'b0 : 1'b1; + + always @(posedge dout_clk) begin + if (dout_rst == 1'b1) begin + dout_enable <= 'd0; + dout_req_t <= 'd0; + dout_init <= 'd0; + dout_raddr <= 'd0; + end else begin + dout_enable <= dout_enable_s; + if (dout_init_s == 1'b1) begin + dout_req_t <= ~dout_req_t; + dout_init <= 1'd1; + dout_raddr <= 'd0; + end else if (dout_valid_s[0] == 1'b1) begin + if (dout_raddr[2:0] == 3'd7) begin + dout_req_t <= ~dout_req_t; + dout_init <= 1'd0; + end + dout_raddr <= dout_raddr + 1'b1; + end + end + end + + always @(posedge dout_clk) begin + if (dout_rst == 1'b1) begin + dout_unf_m1 <= 'd0; + dout_unf <= 'd0; + end else begin + dout_unf_m1 <= din_unf_d; + dout_unf <= dout_unf_m1; + end + end + + // instantiations + + ad_mem #( + .ADDRESS_WIDTH(ADDRESS_WIDTH), + .DATA_WIDTH(DATA_WIDTH) + ) i_mem ( + .clka (din_clk), + .wea (din_wr), + .addra (din_waddr), + .dina (din_wdata), + .clkb (dout_clk), + .reb (1'b1), + .addrb (dout_raddr), + .doutb (dout_rdata_s)); + +endmodule diff --git a/adi_library/util_rfifo/util_rfifo.xpr b/adi_library/util_rfifo/util_rfifo.xpr new file mode 100644 index 00000000..f5b6eaa7 --- /dev/null +++ b/adi_library/util_rfifo/util_rfifo.xpr @@ -0,0 +1,412 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_rfifo/util_rfifo_constr.sdc b/adi_library/util_rfifo/util_rfifo_constr.sdc new file mode 100644 index 00000000..37d5d0f7 --- /dev/null +++ b/adi_library/util_rfifo/util_rfifo_constr.sdc @@ -0,0 +1,10 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_false_path -from [get_registers *dout_enable*] -to [get_registers *din_enable_m1*] +set_false_path -from [get_registers *dout_req_t*] -to [get_registers *din_req_t_m1*] +set_false_path -from [get_registers *dout_init*] -to [get_registers *din_init*] +set_false_path -from [get_registers *din_unf_d*] -to [get_registers *dout_unf_m1*] + diff --git a/adi_library/util_rfifo/util_rfifo_constr.xdc b/adi_library/util_rfifo/util_rfifo_constr.xdc new file mode 100644 index 00000000..75ad6ed4 --- /dev/null +++ b/adi_library/util_rfifo/util_rfifo_constr.xdc @@ -0,0 +1,14 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *din_enable_m*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *din_req_t_m*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dout_unf_m*}] + +set_false_path -from [get_cells -hier -filter {name =~ *dout_enable* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_enable_m1* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *dout_req_t* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_req_t_m1* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *dout_init* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_init* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *din_unf* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dout_unf_m1* && IS_SEQUENTIAL}] + diff --git a/adi_library/util_rfifo/util_rfifo_hw.tcl b/adi_library/util_rfifo/util_rfifo_hw.tcl new file mode 100644 index 00000000..05fa7931 --- /dev/null +++ b/adi_library/util_rfifo/util_rfifo_hw.tcl @@ -0,0 +1,71 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +source ../../scripts/adi_env.tcl +source ../scripts/adi_ip_intel.tcl + +ad_ip_create util_rfifo {Utils Read FIFO} util_rfifo_elab +ad_ip_files util_rfifo [list\ + $ad_hdl_dir/library/common/ad_mem.v \ + util_rfifo.v \ + util_rfifo_constr.sdc] + +# parameters + +ad_ip_parameter NUM_OF_CHANNELS INTEGER 4 +ad_ip_parameter DIN_DATA_WIDTH INTEGER 32 +ad_ip_parameter DOUT_DATA_WIDTH INTEGER 64 +ad_ip_parameter DIN_ADDRESS_WIDTH INTEGER 8 + +# defaults + +ad_interface clock din_clk input 1 +ad_interface reset-n din_rstn input 1 if_din_clk +ad_interface clock dout_clk input 1 +ad_interface reset dout_rst input 1 if_dout_clk + +add_interface din_0 conduit end +add_interface_port din_0 din_enable_0 enable Output 1 +add_interface_port din_0 din_valid_0 valid Output 1 +add_interface_port din_0 din_valid_in_0 data_valid Input 1 +add_interface_port din_0 din_data_0 data Input DIN_DATA_WIDTH +set_interface_property din_0 associatedClock if_din_clk +set_interface_property din_0 associatedReset none + +add_interface dout_0 conduit end +add_interface_port dout_0 dout_enable_0 enable Input 1 +add_interface_port dout_0 dout_valid_0 valid Input 1 +add_interface_port dout_0 dout_valid_out_0 data_valid Output 1 +add_interface_port dout_0 dout_data_0 data Output DOUT_DATA_WIDTH +set_interface_property dout_0 associatedClock if_dout_clk +set_interface_property dout_0 associatedReset none + +ad_interface signal din_unf input 1 unf +ad_interface signal dout_unf output 1 unf + +proc util_rfifo_elab {} { + + for {set n 1} {$n < 8} {incr n} { + if {[get_parameter_value NUM_OF_CHANNELS] > $n} { + add_interface din_${n} conduit end + add_interface_port din_${n} din_enable_${n} enable Output 1 + add_interface_port din_${n} din_valid_${n} valid Output 1 + add_interface_port din_${n} din_valid_in_${n} data_valid Input 1 + add_interface_port din_${n} din_data_${n} data Input DIN_DATA_WIDTH + set_interface_property din_${n} associatedClock if_din_clk + set_interface_property din_${n} associatedReset none + + add_interface dout_${n} conduit end + add_interface_port dout_${n} dout_enable_${n} enable Input 1 + add_interface_port dout_${n} dout_valid_${n} valid Input 1 + add_interface_port dout_${n} dout_valid_out_${n} data_valid Output 1 + add_interface_port dout_${n} dout_data_${n} data Output DOUT_DATA_WIDTH + set_interface_property dout_${n} associatedClock if_dout_clk + set_interface_property dout_${n} associatedReset none + } + } +} + diff --git a/adi_library/util_rfifo/util_rfifo_ip.tcl b/adi_library/util_rfifo/util_rfifo_ip.tcl new file mode 100644 index 00000000..c82240ba --- /dev/null +++ b/adi_library/util_rfifo/util_rfifo_ip.tcl @@ -0,0 +1,48 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_rfifo +adi_ip_files util_rfifo [list \ + "$ad_hdl_dir/library/common/ad_mem.v" \ + "util_rfifo_constr.xdc" \ + "util_rfifo.v" ] + +adi_ip_properties_lite util_rfifo + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/util_rfifo} [ipx::current_core] + +ipx::remove_all_bus_interface [ipx::current_core] +set_property driver_value 0 [ipx::get_ports *dout_enable* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *dout_valid* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *din_valid_in* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *din_data* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *din_unf* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1} \ + [ipx::get_ports *_1* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2} \ + [ipx::get_ports *_2* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3} \ + [ipx::get_ports *_3* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4} \ + [ipx::get_ports *_4* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5} \ + [ipx::get_ports *_5* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6} \ + [ipx::get_ports *_6* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7} \ + [ipx::get_ports *_7* -of_objects [ipx::current_core]] + +ipx::infer_bus_interface din_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface dout_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface din_rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface dout_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] + + diff --git a/adi_library/util_rfifo/xgui/util_rfifo_v1_0.tcl b/adi_library/util_rfifo/xgui/util_rfifo_v1_0.tcl new file mode 100644 index 00000000..17c4c627 --- /dev/null +++ b/adi_library/util_rfifo/xgui/util_rfifo_v1_0.tcl @@ -0,0 +1,70 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DIN_ADDRESS_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "DIN_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "DOUT_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_OF_CHANNELS" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DIN_ADDRESS_WIDTH { PARAM_VALUE.DIN_ADDRESS_WIDTH } { + # Procedure called to update DIN_ADDRESS_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DIN_ADDRESS_WIDTH { PARAM_VALUE.DIN_ADDRESS_WIDTH } { + # Procedure called to validate DIN_ADDRESS_WIDTH + return true +} + +proc update_PARAM_VALUE.DIN_DATA_WIDTH { PARAM_VALUE.DIN_DATA_WIDTH } { + # Procedure called to update DIN_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DIN_DATA_WIDTH { PARAM_VALUE.DIN_DATA_WIDTH } { + # Procedure called to validate DIN_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.DOUT_DATA_WIDTH { PARAM_VALUE.DOUT_DATA_WIDTH } { + # Procedure called to update DOUT_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DOUT_DATA_WIDTH { PARAM_VALUE.DOUT_DATA_WIDTH } { + # Procedure called to validate DOUT_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to update NUM_OF_CHANNELS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to validate NUM_OF_CHANNELS + return true +} + + +proc update_MODELPARAM_VALUE.NUM_OF_CHANNELS { MODELPARAM_VALUE.NUM_OF_CHANNELS PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_CHANNELS}] ${MODELPARAM_VALUE.NUM_OF_CHANNELS} +} + +proc update_MODELPARAM_VALUE.DIN_DATA_WIDTH { MODELPARAM_VALUE.DIN_DATA_WIDTH PARAM_VALUE.DIN_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DIN_DATA_WIDTH}] ${MODELPARAM_VALUE.DIN_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.DOUT_DATA_WIDTH { MODELPARAM_VALUE.DOUT_DATA_WIDTH PARAM_VALUE.DOUT_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DOUT_DATA_WIDTH}] ${MODELPARAM_VALUE.DOUT_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.DIN_ADDRESS_WIDTH { MODELPARAM_VALUE.DIN_ADDRESS_WIDTH PARAM_VALUE.DIN_ADDRESS_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DIN_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.DIN_ADDRESS_WIDTH} +} + diff --git a/adi_library/util_sigma_delta_spi/Makefile b/adi_library/util_sigma_delta_spi/Makefile new file mode 100644 index 00000000..594d724e --- /dev/null +++ b/adi_library/util_sigma_delta_spi/Makefile @@ -0,0 +1,16 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_sigma_delta_spi + +GENERIC_DEPS += util_sigma_delta_spi.v + +XILINX_DEPS += util_sigma_delta_spi_ip.tcl + +XILINX_DEPS += ../spi_engine/interfaces/spi_master.xml +XILINX_DEPS += ../spi_engine/interfaces/spi_master_rtl.xml + +include ../scripts/library.mk diff --git a/adi_library/util_sigma_delta_spi/component.xml b/adi_library/util_sigma_delta_spi/component.xml new file mode 100644 index 00000000..c3e2e1a9 --- /dev/null +++ b/adi_library/util_sigma_delta_spi/component.xml @@ -0,0 +1,522 @@ + + + analog.com + user + util_sigma_delta_spi + 1.0 + + + m_spi + + + + + + + SCLK + + + m_sclk + + + + + SDI + + + m_sdi + + + + + SDO + + + m_sdo + + + + + SDO_T + + + m_sdo_t + + + + + CS + + + m_cs + + + + + + s_spi + + + + + + + SCLK + + + s_sclk + + + + + SDI + + + s_sdi + + + + + SDO + + + s_sdo + + + + + SDO_T + + + s_sdo_t + + + + + CS + + + s_cs + + + + + + m_spi_s_spi_signal_clock + m_spi_s_spi_signal_clock + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_BUSIF + m_spi:s_spi + + + ASSOCIATED_RESET + resetn + + + + + m_spi_s_spi_signal_reset + m_spi_s_spi_signal_reset + + + + + + + RST + + + resetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_sigma_delta_spi + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 1b2e346e + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_sigma_delta_spi + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 1b2e346e + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + dfe70b83 + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + resetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + spi_active + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_sclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_sdo + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_sdo_t + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_sdi + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_cs + + in + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_sclk + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_sdo + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_sdo_t + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + m_sdi + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + m_cs + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_ready + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + NUM_OF_CS + Num Of Cs + 1 + + + CS_PIN + Cs Pin + 0 + + + IDLE_TIMEOUT + Idle Timeout + 63 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + util_sigma_delta_spi.v + verilogSource + CHECKSUM_1b2e346e + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + util_sigma_delta_spi.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/util_sigma_delta_spi_v1_0.tcl + tclSource + CHECKSUM_dfe70b83 + XGUI_VERSION_2 + + + + util_sigma_delta_spi_v1_0 + + + NUM_OF_CS + Num Of Cs + 1 + + + CS_PIN + Cs Pin + 0 + + + IDLE_TIMEOUT + Idle Timeout + 63 + + + Component_Name + util_sigma_delta_spi_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + util_sigma_delta_spi_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:56:37Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_sigma_delta_spi/util_sigma_delta_spi.v b/adi_library/util_sigma_delta_spi/util_sigma_delta_spi.v new file mode 100644 index 00000000..e9ea123e --- /dev/null +++ b/adi_library/util_sigma_delta_spi/util_sigma_delta_spi.v @@ -0,0 +1,111 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_sigma_delta_spi #( + + parameter NUM_OF_CS = 1, + parameter CS_PIN = 0, + parameter IDLE_TIMEOUT = 63 +) ( + input clk, + input resetn, + + input spi_active, + + input s_sclk, + input s_sdo, + input s_sdo_t, + output s_sdi, + input [NUM_OF_CS-1:0] s_cs, + + output m_sclk, + output m_sdo, + output m_sdo_t, + input m_sdi, + output [NUM_OF_CS-1:0] m_cs, + + output reg data_ready +); + + /* + * For converters from the ADI SigmaDelta family the data ready interrupt signal + * uses the same physical wire as the the DOUT signal for the SPI bus. This + * module extracts the data ready signal from the SPI bus and makes sure to + * suppress false positives. The data ready signal is indicated by the converter + * by pulling DOUT low. This will only happen if the CS pin for the converter is + * low and no SPI transfer is active. There is a small delay between the end of + * the SPI transfer and the point where the converter starts to indicate the + * data ready signal. IDLE_TIMEOUT allows to specify the amount of clock cycles + * the bus needs to be idle before the data ready signal is detected. + */ + + assign m_sclk = s_sclk; + assign m_sdo = s_sdo; + assign m_sdo_t = s_sdo_t; + assign s_sdi = m_sdi; + assign m_cs = s_cs; + + reg [$clog2(IDLE_TIMEOUT)-1:0] counter = IDLE_TIMEOUT; + reg [2:0] sdi_d = 'h00; + + always @(posedge clk) begin + if (resetn == 1'b0) begin + counter <= IDLE_TIMEOUT; + end else begin + if (s_cs[CS_PIN] == 1'b0 && spi_active == 1'b0) begin + if (counter != 'h00) + counter <= counter - 1'b1; + end else begin + counter <= IDLE_TIMEOUT; + end + end + end + + always @(posedge clk) begin + /* The data ready signal is fully asynchronous */ + sdi_d <= {sdi_d[1:0], m_sdi}; + end + + always @(posedge clk) begin + if (counter == 'h00 && sdi_d[2] == 1'b0) begin + data_ready <= 1'b1; + end else begin + data_ready <= 1'b0; + end + end + +endmodule diff --git a/adi_library/util_sigma_delta_spi/util_sigma_delta_spi.xpr b/adi_library/util_sigma_delta_spi/util_sigma_delta_spi.xpr new file mode 100644 index 00000000..ff4a61f5 --- /dev/null +++ b/adi_library/util_sigma_delta_spi/util_sigma_delta_spi.xpr @@ -0,0 +1,399 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_sigma_delta_spi/util_sigma_delta_spi_ip.tcl b/adi_library/util_sigma_delta_spi/util_sigma_delta_spi_ip.tcl new file mode 100644 index 00000000..a90d8845 --- /dev/null +++ b/adi_library/util_sigma_delta_spi/util_sigma_delta_spi_ip.tcl @@ -0,0 +1,40 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_sigma_delta_spi +adi_ip_files util_sigma_delta_spi [list \ + "util_sigma_delta_spi.v" \ +] + +adi_ip_properties_lite util_sigma_delta_spi + +adi_add_bus "m_spi" "master" \ + "analog.com:interface:spi_master_rtl:1.0" \ + "analog.com:interface:spi_master:1.0" \ + { + {"m_sclk" "SCLK"} \ + {"m_sdi" "SDI"} \ + {"m_sdo" "SDO"} \ + {"m_sdo_t" "SDO_T"} \ + {"m_cs" "CS"} \ + } + +adi_add_bus "s_spi" "slave" \ + "analog.com:interface:spi_master_rtl:1.0" \ + "analog.com:interface:spi_master:1.0" \ + { + {"s_sclk" "SCLK"} \ + {"s_sdi" "SDI"} \ + {"s_sdo" "SDO"} \ + {"s_sdo_t" "SDO_T"} \ + {"s_cs" "CS"} \ + } + +adi_add_bus_clock "clk" "m_spi:s_spi" "resetn" + +ipx::save_core [ipx::current_core] diff --git a/adi_library/util_sigma_delta_spi/xgui/util_sigma_delta_spi_v1_0.tcl b/adi_library/util_sigma_delta_spi/xgui/util_sigma_delta_spi_v1_0.tcl new file mode 100644 index 00000000..1222eb1e --- /dev/null +++ b/adi_library/util_sigma_delta_spi/xgui/util_sigma_delta_spi_v1_0.tcl @@ -0,0 +1,55 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "CS_PIN" -parent ${Page_0} + ipgui::add_param $IPINST -name "IDLE_TIMEOUT" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_OF_CS" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.CS_PIN { PARAM_VALUE.CS_PIN } { + # Procedure called to update CS_PIN when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CS_PIN { PARAM_VALUE.CS_PIN } { + # Procedure called to validate CS_PIN + return true +} + +proc update_PARAM_VALUE.IDLE_TIMEOUT { PARAM_VALUE.IDLE_TIMEOUT } { + # Procedure called to update IDLE_TIMEOUT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.IDLE_TIMEOUT { PARAM_VALUE.IDLE_TIMEOUT } { + # Procedure called to validate IDLE_TIMEOUT + return true +} + +proc update_PARAM_VALUE.NUM_OF_CS { PARAM_VALUE.NUM_OF_CS } { + # Procedure called to update NUM_OF_CS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_CS { PARAM_VALUE.NUM_OF_CS } { + # Procedure called to validate NUM_OF_CS + return true +} + + +proc update_MODELPARAM_VALUE.NUM_OF_CS { MODELPARAM_VALUE.NUM_OF_CS PARAM_VALUE.NUM_OF_CS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_CS}] ${MODELPARAM_VALUE.NUM_OF_CS} +} + +proc update_MODELPARAM_VALUE.CS_PIN { MODELPARAM_VALUE.CS_PIN PARAM_VALUE.CS_PIN } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CS_PIN}] ${MODELPARAM_VALUE.CS_PIN} +} + +proc update_MODELPARAM_VALUE.IDLE_TIMEOUT { MODELPARAM_VALUE.IDLE_TIMEOUT PARAM_VALUE.IDLE_TIMEOUT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.IDLE_TIMEOUT}] ${MODELPARAM_VALUE.IDLE_TIMEOUT} +} + diff --git a/adi_library/util_tdd_sync/Makefile b/adi_library/util_tdd_sync/Makefile new file mode 100644 index 00000000..be698a8b --- /dev/null +++ b/adi_library/util_tdd_sync/Makefile @@ -0,0 +1,15 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_tdd_sync + +GENERIC_DEPS += ../common/util_pulse_gen.v +GENERIC_DEPS += util_tdd_sync.v + +XILINX_DEPS += util_tdd_sync_constr.xdc +XILINX_DEPS += util_tdd_sync_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/util_tdd_sync/component.xml b/adi_library/util_tdd_sync/component.xml new file mode 100644 index 00000000..7a91e465 --- /dev/null +++ b/adi_library/util_tdd_sync/component.xml @@ -0,0 +1,282 @@ + + + analog.com + user + util_tdd_sync + 1.0 + + + clk + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_RESET + rstn + + + + + rstn + + + + + + + RST + + + rstn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_tdd_sync + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + bd31316a + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_tdd_sync + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 42356555 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + fdcef067 + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rstn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sync_mode + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sync_in + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + sync_out + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + TDD_SYNC_PERIOD + Tdd Sync Period + 100000000 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + util_tdd_sync_constr.xdc + xdc + + + ../common/util_pulse_gen.v + verilogSource + + + util_tdd_sync.v + verilogSource + CHECKSUM_ce98bc75 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/util_pulse_gen.v + verilogSource + + + util_tdd_sync.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/util_tdd_sync_v1_0.tcl + tclSource + CHECKSUM_fdcef067 + XGUI_VERSION_2 + + + + util_tdd_sync_v1_0 + + + TDD_SYNC_PERIOD + Tdd Sync Period + 100000000 + + + Component_Name + util_tdd_sync_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + util_tdd_sync_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:56:45Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_tdd_sync/util_tdd_sync.v b/adi_library/util_tdd_sync/util_tdd_sync.v new file mode 100644 index 00000000..9fd3aa57 --- /dev/null +++ b/adi_library/util_tdd_sync/util_tdd_sync.v @@ -0,0 +1,98 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// +// Simple pulse generator for TDD control +// The module has two modes. In function of the state of sync_mode, +// the syncronization signal (sync_out) can get its value from an external +// source or from its internal generator. +// + +`timescale 1ns/1ps + +module util_tdd_sync #( + + parameter TDD_SYNC_PERIOD = 100000000 +) ( + input clk, + input rstn, + + input sync_mode, + + input sync_in, + output reg sync_out +); + + reg sync_mode_d1 = 1'b0; + reg sync_mode_d2 = 1'b0; + + wire sync_internal; + wire sync_external; + + // pulse generator + + util_pulse_gen #( + .PULSE_PERIOD(TDD_SYNC_PERIOD) + ) i_tdd_sync ( + .clk (clk), + .rstn (rstn), + .pulse_width (32'd0), + .pulse_period (32'd0), + .load_config (1'd0), + .pulse (sync_internal)); + + // synchronization logic + + always @(posedge clk) begin + if(rstn == 1'b0) begin + sync_mode_d1 <= 1'b0; + sync_mode_d2 <= 1'b0; + end else begin + sync_mode_d1 <= sync_mode; + sync_mode_d2 <= sync_mode_d1; + end + end + + // output logic + + assign sync_external = sync_in; + always @(posedge clk) begin + if(rstn == 1'b0) begin + sync_out <= 1'b0; + end else begin + sync_out <= (sync_mode_d2 == 1'b0) ? sync_internal : sync_external; + end + end + +endmodule diff --git a/adi_library/util_tdd_sync/util_tdd_sync.xpr b/adi_library/util_tdd_sync/util_tdd_sync.xpr new file mode 100644 index 00000000..129199b4 --- /dev/null +++ b/adi_library/util_tdd_sync/util_tdd_sync.xpr @@ -0,0 +1,412 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_tdd_sync/util_tdd_sync_constr.xdc b/adi_library/util_tdd_sync/util_tdd_sync_constr.xdc new file mode 100644 index 00000000..33aedc91 --- /dev/null +++ b/adi_library/util_tdd_sync/util_tdd_sync_constr.xdc @@ -0,0 +1,10 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property ASYNC_REG TRUE \ + [get_cells -hier *sync_mode_d*] + +set_false_path -to [get_pins -hier -filter {NAME =~ */sync_mode_d1_reg/D}] + diff --git a/adi_library/util_tdd_sync/util_tdd_sync_ip.tcl b/adi_library/util_tdd_sync/util_tdd_sync_ip.tcl new file mode 100644 index 00000000..262a274f --- /dev/null +++ b/adi_library/util_tdd_sync/util_tdd_sync_ip.tcl @@ -0,0 +1,23 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_tdd_sync +adi_ip_files util_tdd_sync [list \ + "$ad_hdl_dir/library/common/util_pulse_gen.v" \ + "util_tdd_sync_constr.xdc" \ + "util_tdd_sync.v"] + +adi_ip_properties_lite util_tdd_sync + +ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/util_tdd_sync/xgui/util_tdd_sync_v1_0.tcl b/adi_library/util_tdd_sync/xgui/util_tdd_sync_v1_0.tcl new file mode 100644 index 00000000..c0e10c9d --- /dev/null +++ b/adi_library/util_tdd_sync/xgui/util_tdd_sync_v1_0.tcl @@ -0,0 +1,25 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "TDD_SYNC_PERIOD" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.TDD_SYNC_PERIOD { PARAM_VALUE.TDD_SYNC_PERIOD } { + # Procedure called to update TDD_SYNC_PERIOD when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TDD_SYNC_PERIOD { PARAM_VALUE.TDD_SYNC_PERIOD } { + # Procedure called to validate TDD_SYNC_PERIOD + return true +} + + +proc update_MODELPARAM_VALUE.TDD_SYNC_PERIOD { MODELPARAM_VALUE.TDD_SYNC_PERIOD PARAM_VALUE.TDD_SYNC_PERIOD } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TDD_SYNC_PERIOD}] ${MODELPARAM_VALUE.TDD_SYNC_PERIOD} +} + diff --git a/adi_library/util_var_fifo/Makefile b/adi_library/util_var_fifo/Makefile new file mode 100644 index 00000000..b9097370 --- /dev/null +++ b/adi_library/util_var_fifo/Makefile @@ -0,0 +1,13 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_var_fifo + +GENERIC_DEPS += util_var_fifo.v + +XILINX_DEPS += util_var_fifo_ip.tcl + +include ../scripts/library.mk diff --git a/adi_library/util_var_fifo/component.xml b/adi_library/util_var_fifo/component.xml new file mode 100644 index 00000000..6f4105d3 --- /dev/null +++ b/adi_library/util_var_fifo/component.xml @@ -0,0 +1,412 @@ + + + analog.com + user + util_var_fifo + 1.0 + + + clk + + + + + + + CLK + + + clk + + + + + + ASSOCIATED_RESET + rst + + + + + rst + + + + + + + RST + + + rst + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_var_fifo + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + f71444ed + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_var_fifo + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + f71444ed + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 9fdedb52 + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + rst + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + depth + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_in + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_in_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_out + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + data_out_valid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + wea_w + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + en_w + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + addr_w + + out + + 12 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + din_w + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + en_r + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + addr_r + + out + + 12 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dout_r + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + DATA_WIDTH + Data Width + 32 + + + ADDRESS_WIDTH + Address Width + 13 + + + + + + xilinx_anylanguagesynthesis_view_fileset + + util_var_fifo.v + verilogSource + CHECKSUM_f71444ed + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + util_var_fifo.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/util_var_fifo_v1_0.tcl + tclSource + CHECKSUM_9fdedb52 + XGUI_VERSION_2 + + + + util_var_fifo_v1_0 + + + DATA_WIDTH + Data Width + 32 + + + ADDRESS_WIDTH + Address Width + 13 + + + Component_Name + util_var_fifo_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + util_var_fifo_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/util_var_fifo + 1 + 2024-01-14T03:56:53Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_var_fifo/util_var_fifo.v b/adi_library/util_var_fifo/util_var_fifo.v new file mode 100644 index 00000000..19fd7cb8 --- /dev/null +++ b/adi_library/util_var_fifo/util_var_fifo.v @@ -0,0 +1,170 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_var_fifo #( + + // parameters + + parameter DATA_WIDTH = 32, + parameter ADDRESS_WIDTH = 13 +) ( + input clk, + input rst, + + input [31:0] depth, + + input [DATA_WIDTH -1:0] data_in, + input data_in_valid, + + output [DATA_WIDTH-1:0] data_out, + output data_out_valid, + + output wea_w, + output en_w, + output [ADDRESS_WIDTH-1:0] addr_w, + output [DATA_WIDTH-1:0] din_w, + output en_r, + output [ADDRESS_WIDTH-1:0] addr_r, + input [DATA_WIDTH-1:0] dout_r +); + + localparam MAX_DEPTH = (2 ** ADDRESS_WIDTH) - 1; + + // internal registers + + reg [ADDRESS_WIDTH-1:0] addra = 'd0; + reg [ADDRESS_WIDTH-1:0] addrb = 'd0; + + reg [31:0] depth_d1 = 'd0; + reg [DATA_WIDTH-1:0] data_in_d1 = 'd0; + reg [DATA_WIDTH-1:0] data_in_d2 = 'd0; + reg [DATA_WIDTH-1:0] data_in_d3 = 'd0; + reg [DATA_WIDTH-1:0] data_in_d4 = 'd0; + reg data_active = 'd0; + reg fifo_active = 'd0; + + reg data_in_valid_d1 = 'd0; + reg data_in_valid_d2 = 'd0; + reg interpolation_on = 'd0; + reg interpolation_on_d1 = 'd0; + reg interpolation_by_2 = 'd0; + reg interpolation_by_2_d1 = 'd0; + reg [DATA_WIDTH-1:0] data_out_d1 = 'd0; + reg [DATA_WIDTH-1:0] data_out_d2 = 'd0; + reg [DATA_WIDTH-1:0] data_out_d3 = 'd0; + + // internal signals + + wire reset; + wire [DATA_WIDTH-1:0] data_out_s; + wire data_out_valid_s; + + assign reset = ((rst == 1'b1) || (depth != depth_d1) || (interpolation_on != interpolation_on_d1) || (interpolation_by_2 != interpolation_by_2_d1)) ? 1 : 0; + + assign data_out = fifo_active ? data_out_s : data_in_d4; + assign data_out_valid_s = data_active & data_in_valid; + assign data_out_valid = fifo_active ? data_out_valid_s : data_in_valid; + + assign wea_w = data_in_valid & fifo_active; + assign en_w = fifo_active; + assign addr_w = addra; + assign din_w = data_in; + assign en_r = fifo_active; + assign addr_r = addrb; + assign data_out_s = interpolation_on ? (interpolation_by_2 ? data_out_d2 : data_out_d3) : dout_r; + + // in case the interpolation is on, the data is available with one sample + // delay. If interpolation is off, the data is available with two or three + // sample delay. Add an extra delay if interpolation is on. + always @(posedge clk) begin + data_in_valid_d1 <= data_in_valid; + data_in_valid_d2 <= data_in_valid_d1; + interpolation_on_d1 = interpolation_on; + interpolation_by_2_d1 = interpolation_by_2; + if (data_in_valid == 1'b1) begin + if (data_in_valid_d1 == 1'b1) begin + interpolation_on <= 1'b0; + end else begin + interpolation_on <= 1'b1; + if (data_in_valid_d2 == 1'b1) begin + interpolation_by_2 <= 1'b1; + end else begin + interpolation_by_2 <= 1'b0; + end + end + end + if(data_out_valid == 1'b1) begin + data_out_d1 <= dout_r; + data_out_d2 <= data_out_d1; + data_out_d3 <= data_out_d2; + end + end + + always @(posedge clk) begin + depth_d1 <= depth; + if (depth == 32'h0) begin + fifo_active <= 0; + end else begin + fifo_active <= 1; + end + if (data_in_valid == 1'b1 && fifo_active == 1'b0) begin + data_in_d1 <= data_in; + data_in_d2 <= data_in_d1; + data_in_d3 <= data_in_d2; + data_in_d4 <= data_in_d3; + end + end + + always @(posedge clk) begin + if(reset == 1'b1 || fifo_active == 1'b0) begin + addra <= 0; + addrb <= 0; + data_active <= 1'b0; + end else begin + if (data_in_valid == 1'b1) begin + addra <= addra + 1; + if (data_active == 1'b1) begin + addrb <= addrb + 1; + end + end + if (addra > depth || addra > MAX_DEPTH - 2) begin + data_active <= 1'b1; + end + end + end + +endmodule diff --git a/adi_library/util_var_fifo/util_var_fifo.xpr b/adi_library/util_var_fifo/util_var_fifo.xpr new file mode 100644 index 00000000..49991aa7 --- /dev/null +++ b/adi_library/util_var_fifo/util_var_fifo.xpr @@ -0,0 +1,399 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_var_fifo/util_var_fifo_ip.tcl b/adi_library/util_var_fifo/util_var_fifo_ip.tcl new file mode 100644 index 00000000..268c8712 --- /dev/null +++ b/adi_library/util_var_fifo/util_var_fifo_ip.tcl @@ -0,0 +1,23 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_var_fifo +adi_ip_files util_var_fifo [list \ + "util_var_fifo.v" ] + +adi_ip_properties_lite util_var_fifo + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/util_var_fifo} [ipx::current_core] + +ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] + + diff --git a/adi_library/util_var_fifo/xgui/util_var_fifo_v1_0.tcl b/adi_library/util_var_fifo/xgui/util_var_fifo_v1_0.tcl new file mode 100644 index 00000000..5696bf7d --- /dev/null +++ b/adi_library/util_var_fifo/xgui/util_var_fifo_v1_0.tcl @@ -0,0 +1,40 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ADDRESS_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "DATA_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } { + # Procedure called to update ADDRESS_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADDRESS_WIDTH { PARAM_VALUE.ADDRESS_WIDTH } { + # Procedure called to validate ADDRESS_WIDTH + return true +} + +proc update_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to update DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DATA_WIDTH { PARAM_VALUE.DATA_WIDTH } { + # Procedure called to validate DATA_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.DATA_WIDTH { MODELPARAM_VALUE.DATA_WIDTH PARAM_VALUE.DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_WIDTH}] ${MODELPARAM_VALUE.DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.ADDRESS_WIDTH { MODELPARAM_VALUE.ADDRESS_WIDTH PARAM_VALUE.ADDRESS_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADDRESS_WIDTH}] ${MODELPARAM_VALUE.ADDRESS_WIDTH} +} + diff --git a/adi_library/util_wfifo/Makefile b/adi_library/util_wfifo/Makefile new file mode 100644 index 00000000..e065d97b --- /dev/null +++ b/adi_library/util_wfifo/Makefile @@ -0,0 +1,18 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_wfifo + +GENERIC_DEPS += ../common/ad_mem.v +GENERIC_DEPS += util_wfifo.v + +XILINX_DEPS += util_wfifo_constr.xdc +XILINX_DEPS += util_wfifo_ip.tcl + +INTEL_DEPS += util_wfifo_constr.sdc +INTEL_DEPS += util_wfifo_hw.tcl + +include ../scripts/library.mk diff --git a/adi_library/util_wfifo/component.xml b/adi_library/util_wfifo/component.xml new file mode 100644 index 00000000..bda66577 --- /dev/null +++ b/adi_library/util_wfifo/component.xml @@ -0,0 +1,1420 @@ + + + analog.com + user + util_wfifo + 1.0 + + + din_clk + + + + + + + CLK + + + din_clk + + + + + + ASSOCIATED_RESET + din_rst + + + + + din_rst + + + + + + + RST + + + din_rst + + + + + + dout_clk + + + + + + + CLK + + + dout_clk + + + + + + ASSOCIATED_RESET + dout_rstn + + + + + dout_rstn + + + + + + + RST + + + dout_rstn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_wfifo + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + ae0954fb + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_wfifo + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 9484c44c + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 70b62934 + + + + + + + din_rst + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + din_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + din_enable_0 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + din_valid_0 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + din_data_0 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + din_enable_1 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + din_valid_1 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + din_data_1 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + din_enable_2 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + din_valid_2 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + din_data_2 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + din_enable_3 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + din_valid_3 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + din_data_3 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + true + + + + + + din_enable_4 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + din_valid_4 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + din_data_4 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + din_enable_5 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + din_valid_5 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + din_data_5 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + din_enable_6 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + din_valid_6 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + din_data_6 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + din_enable_7 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + din_valid_7 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + din_data_7 + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + din_ovf + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dout_rstn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dout_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dout_enable_0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dout_valid_0 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dout_data_0 + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dout_enable_1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + dout_valid_1 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + dout_data_1 + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + dout_enable_2 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + dout_valid_2 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + dout_data_2 + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + dout_enable_3 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + dout_valid_3 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + dout_data_3 + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + true + + + + + + dout_enable_4 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout_valid_4 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout_data_4 + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout_enable_5 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout_valid_5 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout_data_5 + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout_enable_6 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout_valid_6 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout_data_6 + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout_enable_7 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout_valid_7 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout_data_7 + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + false + + + + + + dout_ovf + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + NUM_OF_CHANNELS + Num Of Channels + 4 + + + DIN_DATA_WIDTH + Din Data Width + 32 + + + DOUT_DATA_WIDTH + Dout Data Width + 64 + + + DIN_ADDRESS_WIDTH + Din Address Width + 8 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + util_wfifo_constr.xdc + xdc + + + ../common/ad_mem.v + verilogSource + + + util_wfifo.v + verilogSource + CHECKSUM_74ba504e + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../common/ad_mem.v + verilogSource + + + util_wfifo.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/util_wfifo_v1_0.tcl + tclSource + CHECKSUM_70b62934 + XGUI_VERSION_2 + + + + util_wfifo_v1_0 + + + NUM_OF_CHANNELS + Num Of Channels + 4 + + + DIN_DATA_WIDTH + Din Data Width + 32 + + + DOUT_DATA_WIDTH + Dout Data Width + 64 + + + DIN_ADDRESS_WIDTH + Din Address Width + 8 + + + Component_Name + util_wfifo_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + util_wfifo_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/util_wfifo + 1 + 2024-01-14T03:57:01Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/util_wfifo/util_wfifo.v b/adi_library/util_wfifo/util_wfifo.v new file mode 100644 index 00000000..a6dbb7c1 --- /dev/null +++ b/adi_library/util_wfifo/util_wfifo.v @@ -0,0 +1,343 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_wfifo #( + + parameter NUM_OF_CHANNELS = 4, + parameter DIN_DATA_WIDTH = 32, + parameter DOUT_DATA_WIDTH = 64, + parameter DIN_ADDRESS_WIDTH = 8 +) ( + + // d-in interface + + input din_rst, + input din_clk, + input din_enable_0, + input din_valid_0, + input [DIN_DATA_WIDTH-1:0] din_data_0, + input din_enable_1, + input din_valid_1, + input [DIN_DATA_WIDTH-1:0] din_data_1, + input din_enable_2, + input din_valid_2, + input [DIN_DATA_WIDTH-1:0] din_data_2, + input din_enable_3, + input din_valid_3, + input [DIN_DATA_WIDTH-1:0] din_data_3, + input din_enable_4, + input din_valid_4, + input [DIN_DATA_WIDTH-1:0] din_data_4, + input din_enable_5, + input din_valid_5, + input [DIN_DATA_WIDTH-1:0] din_data_5, + input din_enable_6, + input din_valid_6, + input [DIN_DATA_WIDTH-1:0] din_data_6, + input din_enable_7, + input din_valid_7, + input [DIN_DATA_WIDTH-1:0] din_data_7, + output reg din_ovf, + + // d-out interface + + input dout_rstn, + input dout_clk, + output dout_enable_0, + output dout_valid_0, + output [DOUT_DATA_WIDTH-1:0] dout_data_0, + output dout_enable_1, + output dout_valid_1, + output [DOUT_DATA_WIDTH-1:0] dout_data_1, + output dout_enable_2, + output dout_valid_2, + output [DOUT_DATA_WIDTH-1:0] dout_data_2, + output dout_enable_3, + output dout_valid_3, + output [DOUT_DATA_WIDTH-1:0] dout_data_3, + output dout_enable_4, + output dout_valid_4, + output [DOUT_DATA_WIDTH-1:0] dout_data_4, + output dout_enable_5, + output dout_valid_5, + output [DOUT_DATA_WIDTH-1:0] dout_data_5, + output dout_enable_6, + output dout_valid_6, + output [DOUT_DATA_WIDTH-1:0] dout_data_6, + output dout_enable_7, + output dout_valid_7, + output [DOUT_DATA_WIDTH-1:0] dout_data_7, + input dout_ovf +); + + localparam M_MEM_RATIO = DOUT_DATA_WIDTH/DIN_DATA_WIDTH; + localparam ADDRESS_WIDTH = (DIN_ADDRESS_WIDTH > 4) ? DIN_ADDRESS_WIDTH : 4; + localparam DATA_WIDTH = DOUT_DATA_WIDTH * NUM_OF_CHANNELS; + localparam T_DIN_DATA_WIDTH = DIN_DATA_WIDTH * 8; + localparam T_DOUT_DATA_WIDTH = DOUT_DATA_WIDTH * 8; + + // internal registers + + reg [(DATA_WIDTH-1):0] din_wdata = 'd0; + reg [ 7:0] din_enable = 'd0; + reg din_wr = 'd0; + reg [(ADDRESS_WIDTH-1):0] din_waddr = 'd0; + reg din_req_t = 'd0; + reg [(ADDRESS_WIDTH-4):0] din_rinit = 'd0; + reg din_ovf_m1 = 'd0; + reg dout_req_t_m1 = 'd0; + reg dout_req_t_m2 = 'd0; + reg dout_req_t_m3 = 'd0; + reg dout_req_t = 'd0; + reg [(ADDRESS_WIDTH-4):0] dout_rinit = 'd0; + reg dout_ovf_d = 'd0; + reg [ 3:0] dout_req_cnt = 'd0; + reg [(ADDRESS_WIDTH-1):0] dout_raddr = 'd8; + reg dout_rd_d = 'd0; + reg dout_valid = 'd0; + reg [ 7:0] dout_enable_m1 = 'd0; + reg [ 7:0] dout_enable = 'd0; + reg [(DATA_WIDTH-1):0] dout_rdata = 'd0; + + // internal signals + + wire [ 7:0] din_enable_s; + wire [ 7:0] din_valid_s; + wire [(T_DIN_DATA_WIDTH-1):0] din_data_s; + wire dout_req_t_s; + wire [(DATA_WIDTH-1):0] dout_rdata_s; + wire [(T_DOUT_DATA_WIDTH+1):0] dout_data_s; + wire [ 2:0] din_dcnt_s; + + // variables + + genvar n; + + // concat signals, valid_0 must always be active + + assign din_enable_s = { din_enable_7, din_enable_6, din_enable_5, din_enable_4, + din_enable_3, din_enable_2, din_enable_1, din_enable_0}; + assign din_valid_s = { din_valid_7, din_valid_6, din_valid_5, din_valid_4, + din_valid_3, din_valid_2, din_valid_1, din_valid_0}; + assign din_data_s = { din_data_7, din_data_6, din_data_5, din_data_4, + din_data_3, din_data_2, din_data_1, din_data_0}; + + // simple data transfer-- no ovf/unf handling- read-bw > write-bw (equal will NOT work) + // dout_width >= din_width only- + + generate + for (n = 0; n < NUM_OF_CHANNELS; n = n + 1) begin: g_in + if (M_MEM_RATIO == 1) begin + always @(posedge din_clk) begin + if (din_valid_s[n] == 1'b1) begin + din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <= + din_data_s[((DIN_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH*n)]; + end + end + end else begin + always @(posedge din_clk) begin + if (din_valid_s[n] == 1'b1) begin + din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DOUT_DATA_WIDTH*n)] <= + {din_data_s[((DIN_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH*n)], + din_wdata[((DOUT_DATA_WIDTH*(n+1))-1):(DIN_DATA_WIDTH+(DOUT_DATA_WIDTH*n))]}; + end + end + end + end + endgenerate + + generate + if (M_MEM_RATIO == 1) begin + assign din_dcnt_s = 'b0; + end else begin + reg [ 2:0] din_dcnt = 'd0; + + always @(posedge din_clk) + if (din_rst == 1'b1) begin + din_dcnt <= 'd0; + end else begin + if (din_valid_s[0] == 1'b1) begin + din_dcnt <= din_dcnt + 1'b1; + end + end + + assign din_dcnt_s = din_dcnt; + end + endgenerate + always @(posedge din_clk) begin + if (din_rst == 1'b1) begin + din_enable <= 8'd0; + din_wr <= 1'd0; + din_waddr <= 'd0; + din_req_t <= 1'd0; + din_rinit <= 'd0; + din_ovf_m1 <= 'd0; + din_ovf <= 'd0; + end else begin + din_enable <= din_enable_s; + case (M_MEM_RATIO) + 8: din_wr <= din_valid_s[0] & din_dcnt_s[0] & din_dcnt_s[1] & din_dcnt_s[2]; + 4: din_wr <= din_valid_s[0] & din_dcnt_s[0] & din_dcnt_s[1]; + 2: din_wr <= din_valid_s[0] & din_dcnt_s[0]; + default: din_wr <= din_valid_s[0]; + endcase + if (din_wr == 1'b1) begin + din_waddr <= din_waddr + 1'b1; + end + if ((din_wr == 1'b1) && (din_waddr[2:0] == 3'd7)) begin + din_req_t <= ~din_req_t; + din_rinit <= din_waddr[(ADDRESS_WIDTH-1):3]; + end + din_ovf_m1 <= dout_ovf_d; + din_ovf <= din_ovf_m1; + end + end + + // read interface (bus expansion and/or clock conversion) + + assign dout_req_t_s = dout_req_t_m3 ^ dout_req_t_m2; + + always @(posedge dout_clk or negedge dout_rstn) begin + if (dout_rstn == 1'b0) begin + dout_req_t_m1 <= 'd0; + dout_req_t_m2 <= 'd0; + dout_req_t_m3 <= 'd0; + dout_req_t <= 'd0; + dout_rinit <= 'd0; + dout_ovf_d <= 'd0; + end else begin + dout_req_t_m1 <= din_req_t; + dout_req_t_m2 <= dout_req_t_m1; + dout_req_t_m3 <= dout_req_t_m2; + dout_req_t <= dout_req_t_s; + if (dout_req_t_s == 1'b1) begin + dout_rinit <= din_rinit; + end + dout_ovf_d <= dout_ovf; + end + end + + always @(posedge dout_clk or negedge dout_rstn) begin + if (dout_rstn == 1'b0) begin + dout_req_cnt <= 'd0; + dout_raddr <= 'd8; + dout_rd_d <= 'd0; + dout_valid <= 'd0; + end else begin + if (dout_req_t == 1'b1) begin + dout_req_cnt <= 4'h8; + dout_raddr <= {dout_rinit, 3'd0}; + end else if (dout_req_cnt[3] == 1'b1) begin + dout_req_cnt <= dout_req_cnt + 1'b1; + dout_raddr <= dout_raddr + 1'b1; + end + dout_rd_d <= dout_req_cnt[3]; + dout_valid <= dout_rd_d; + end + end + + always @(posedge dout_clk or negedge dout_rstn) begin + if (dout_rstn == 1'b0) begin + dout_enable_m1 <= 'd0; + dout_enable <= 'd0; + end else begin + dout_enable_m1 <= din_enable; + dout_enable <= dout_enable_m1; + end + end + + always @(posedge dout_clk) begin + dout_rdata <= dout_rdata_s; + end + + generate + if (NUM_OF_CHANNELS >= 8) begin + assign dout_data_s = dout_rdata; + end else begin + assign dout_data_s[(T_DOUT_DATA_WIDTH+1):DATA_WIDTH] = 'd0; + assign dout_data_s[(DATA_WIDTH-1):0] = dout_rdata; + end + endgenerate + + assign dout_enable_7 = dout_enable[7]; + assign dout_valid_7 = dout_valid; + assign dout_data_7 = dout_data_s[((DOUT_DATA_WIDTH*8)-1):(DOUT_DATA_WIDTH*7)]; + + assign dout_enable_6 = dout_enable[6]; + assign dout_valid_6 = dout_valid; + assign dout_data_6 = dout_data_s[((DOUT_DATA_WIDTH*7)-1):(DOUT_DATA_WIDTH*6)]; + + assign dout_enable_5 = dout_enable[5]; + assign dout_valid_5 = dout_valid; + assign dout_data_5 = dout_data_s[((DOUT_DATA_WIDTH*6)-1):(DOUT_DATA_WIDTH*5)]; + + assign dout_enable_4 = dout_enable[4]; + assign dout_valid_4 = dout_valid; + assign dout_data_4 = dout_data_s[((DOUT_DATA_WIDTH*5)-1):(DOUT_DATA_WIDTH*4)]; + + assign dout_enable_3 = dout_enable[3]; + assign dout_valid_3 = dout_valid; + assign dout_data_3 = dout_data_s[((DOUT_DATA_WIDTH*4)-1):(DOUT_DATA_WIDTH*3)]; + + assign dout_enable_2 = dout_enable[2]; + assign dout_valid_2 = dout_valid; + assign dout_data_2 = dout_data_s[((DOUT_DATA_WIDTH*3)-1):(DOUT_DATA_WIDTH*2)]; + + assign dout_enable_1 = dout_enable[1]; + assign dout_valid_1 = dout_valid; + assign dout_data_1 = dout_data_s[((DOUT_DATA_WIDTH*2)-1):(DOUT_DATA_WIDTH*1)]; + + assign dout_enable_0 = dout_enable[0]; + assign dout_valid_0 = dout_valid; + assign dout_data_0 = dout_data_s[((DOUT_DATA_WIDTH*1)-1):(DOUT_DATA_WIDTH*0)]; + + // instantiations + + ad_mem #( + .ADDRESS_WIDTH(ADDRESS_WIDTH), + .DATA_WIDTH(DATA_WIDTH) + ) i_mem ( + .clka (din_clk), + .wea (din_wr), + .addra (din_waddr), + .dina (din_wdata), + .clkb (dout_clk), + .reb (1'b1), + .addrb (dout_raddr), + .doutb (dout_rdata_s)); + +endmodule diff --git a/adi_library/util_wfifo/util_wfifo.xpr b/adi_library/util_wfifo/util_wfifo.xpr new file mode 100644 index 00000000..c09984b8 --- /dev/null +++ b/adi_library/util_wfifo/util_wfifo.xpr @@ -0,0 +1,412 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/util_wfifo/util_wfifo_constr.sdc b/adi_library/util_wfifo/util_wfifo_constr.sdc new file mode 100644 index 00000000..08918cfe --- /dev/null +++ b/adi_library/util_wfifo/util_wfifo_constr.sdc @@ -0,0 +1,10 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_false_path -from [get_registers *din_enable*] -to [get_registers *dout_enable_m1*] +set_false_path -from [get_registers *din_req_t*] -to [get_registers *dout_req_t_m1*] +set_false_path -from [get_registers *din_rinit*] -to [get_registers *dout_rinit*] +set_false_path -from [get_registers *dout_ovf_d*] -to [get_registers *din_ovf_m1*] + diff --git a/adi_library/util_wfifo/util_wfifo_constr.xdc b/adi_library/util_wfifo/util_wfifo_constr.xdc new file mode 100644 index 00000000..a2b56041 --- /dev/null +++ b/adi_library/util_wfifo/util_wfifo_constr.xdc @@ -0,0 +1,14 @@ +############################################################################### +## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dout_enable_m*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *dout_req_t_m*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *din_ovf_m*}] + +set_false_path -from [get_cells -hier -filter {name =~ *din_enable* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dout_enable_m1* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *din_req_t* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dout_req_t_m1* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *din_rinit* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *dout_rinit* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *dout_ovf* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *din_ovf_m1* && IS_SEQUENTIAL}] + diff --git a/adi_library/util_wfifo/util_wfifo_hw.tcl b/adi_library/util_wfifo/util_wfifo_hw.tcl new file mode 100644 index 00000000..991df73f --- /dev/null +++ b/adi_library/util_wfifo/util_wfifo_hw.tcl @@ -0,0 +1,214 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +package require qsys 14.0 +source ../../scripts/adi_env.tcl +source ../scripts/adi_ip_intel.tcl + +set_module_property NAME util_wfifo +set_module_property DESCRIPTION "Utils Write FIFO" +set_module_property VERSION 1.0 +set_module_property GROUP "Analog Devices" +set_module_property DISPLAY_NAME util_wfifo +set_module_property ELABORATION_CALLBACK p_util_wfifo + +# files + +add_fileset quartus_synth QUARTUS_SYNTH "" "" +set_fileset_property quartus_synth TOP_LEVEL util_wfifo +add_fileset_file ad_mem.v VERILOG PATH $ad_hdl_dir/library/common/ad_mem.v +add_fileset_file util_wfifo.v VERILOG PATH util_wfifo.v TOP_LEVEL_FILE +add_fileset_file util_wfifo_constr.sdc SDC PATH util_wfifo_constr.sdc + +# parameters + +add_parameter NUM_OF_CHANNELS INTEGER 0 +set_parameter_property NUM_OF_CHANNELS DEFAULT_VALUE 4 +set_parameter_property NUM_OF_CHANNELS DISPLAY_NAME NUM_OF_CHANNELS +set_parameter_property NUM_OF_CHANNELS UNITS None +set_parameter_property NUM_OF_CHANNELS HDL_PARAMETER true + +add_parameter DIN_DATA_WIDTH INTEGER 0 +set_parameter_property DIN_DATA_WIDTH DEFAULT_VALUE 32 +set_parameter_property DIN_DATA_WIDTH DISPLAY_NAME DIN_DATA_WIDTH +set_parameter_property DIN_DATA_WIDTH UNITS None +set_parameter_property DIN_DATA_WIDTH HDL_PARAMETER true + +add_parameter DOUT_DATA_WIDTH INTEGER 0 +set_parameter_property DOUT_DATA_WIDTH DEFAULT_VALUE 64 +set_parameter_property DOUT_DATA_WIDTH DISPLAY_NAME DOUT_DATA_WIDTH +set_parameter_property DOUT_DATA_WIDTH UNITS None +set_parameter_property DOUT_DATA_WIDTH HDL_PARAMETER true + +add_parameter DIN_ADDRESS_WIDTH INTEGER 0 +set_parameter_property DIN_ADDRESS_WIDTH DEFAULT_VALUE 8 +set_parameter_property DIN_ADDRESS_WIDTH DISPLAY_NAME DIN_ADDRESS_WIDTH +set_parameter_property DIN_ADDRESS_WIDTH UNITS None +set_parameter_property DIN_ADDRESS_WIDTH HDL_PARAMETER true + +# defaults + +ad_interface clock din_clk input 1 +ad_interface reset din_rst input 1 if_din_clk + +ad_interface clock dout_clk input 1 +ad_interface reset-n dout_rstn input 1 if_dout_clk + +add_interface din_0 conduit end +add_interface_port din_0 din_enable_0 enable Input 1 +add_interface_port din_0 din_valid_0 valid Input 1 +add_interface_port din_0 din_data_0 data Input DIN_DATA_WIDTH + +set_interface_property din_0 associatedClock if_din_clk +set_interface_property din_0 associatedReset none + +add_interface dout_0 conduit end +add_interface_port dout_0 dout_enable_0 enable Output 1 +add_interface_port dout_0 dout_valid_0 valid Output 1 +add_interface_port dout_0 dout_data_0 data Output DOUT_DATA_WIDTH + +set_interface_property dout_0 associatedClock if_dout_clk +set_interface_property dout_0 associatedReset none + +ad_interface signal din_ovf output 1 ovf +ad_interface signal dout_ovf input 1 ovf + +proc p_util_wfifo {} { + + if {[get_parameter_value NUM_OF_CHANNELS] > 1} { + + add_interface din_1 conduit end + add_interface_port din_1 din_enable_1 enable Input 1 + add_interface_port din_1 din_valid_1 valid Input 1 + add_interface_port din_1 din_data_1 data Input DIN_DATA_WIDTH + + set_interface_property din_1 associatedClock if_din_clk + set_interface_property din_1 associatedReset none + + add_interface dout_1 conduit end + add_interface_port dout_1 dout_enable_1 enable Output 1 + add_interface_port dout_1 dout_valid_1 valid Output 1 + add_interface_port dout_1 dout_data_1 data Output DOUT_DATA_WIDTH + + set_interface_property dout_1 associatedClock if_dout_clk + set_interface_property dout_1 associatedReset none + } + + if {[get_parameter_value NUM_OF_CHANNELS] > 2} { + + add_interface din_2 conduit end + add_interface_port din_2 din_enable_2 enable Input 1 + add_interface_port din_2 din_valid_2 valid Input 1 + add_interface_port din_2 din_data_2 data Input DIN_DATA_WIDTH + + set_interface_property din_2 associatedClock if_din_clk + set_interface_property din_2 associatedReset none + + add_interface dout_2 conduit end + add_interface_port dout_2 dout_enable_2 enable Output 1 + add_interface_port dout_2 dout_valid_2 valid Output 1 + add_interface_port dout_2 dout_data_2 data Output DOUT_DATA_WIDTH + + set_interface_property dout_2 associatedClock if_dout_clk + set_interface_property dout_2 associatedReset none + } + + if {[get_parameter_value NUM_OF_CHANNELS] > 3} { + + add_interface din_3 conduit end + add_interface_port din_3 din_enable_3 enable Input 1 + add_interface_port din_3 din_valid_3 valid Input 1 + add_interface_port din_3 din_data_3 data Input DIN_DATA_WIDTH + + set_interface_property din_3 associatedClock if_din_clk + set_interface_property din_3 associatedReset none + + add_interface dout_3 conduit end + add_interface_port dout_3 dout_enable_3 enable Output 1 + add_interface_port dout_3 dout_valid_3 valid Output 1 + add_interface_port dout_3 dout_data_3 data Output DOUT_DATA_WIDTH + + set_interface_property dout_3 associatedClock if_dout_clk + set_interface_property dout_3 associatedReset none + } + + if {[get_parameter_value NUM_OF_CHANNELS] > 4} { + + add_interface din_4 conduit end + add_interface_port din_4 din_enable_4 enable Input 1 + add_interface_port din_4 din_valid_4 valid Input 1 + add_interface_port din_4 din_data_4 data Input DIN_DATA_WIDTH + + set_interface_property din_4 associatedClock if_din_clk + set_interface_property din_4 associatedReset none + + add_interface dout_4 conduit end + add_interface_port dout_4 dout_enable_4 enable Output 1 + add_interface_port dout_4 dout_valid_4 valid Output 1 + add_interface_port dout_4 dout_data_4 data Output DOUT_DATA_WIDTH + + set_interface_property dout_4 associatedClock if_dout_clk + set_interface_property dout_4 associatedReset none + } + + if {[get_parameter_value NUM_OF_CHANNELS] > 5} { + + add_interface din_5 conduit end + add_interface_port din_5 din_enable_5 enable Input 1 + add_interface_port din_5 din_valid_5 valid Input 1 + add_interface_port din_5 din_data_5 data Input DIN_DATA_WIDTH + + set_interface_property din_5 associatedClock if_din_clk + set_interface_property din_5 associatedReset none + + add_interface dout_5 conduit end + add_interface_port dout_5 dout_enable_5 enable Output 1 + add_interface_port dout_5 dout_valid_5 valid Output 1 + add_interface_port dout_5 dout_data_5 data Output DOUT_DATA_WIDTH + + set_interface_property dout_5 associatedClock if_dout_clk + set_interface_property dout_5 associatedReset none + } + + if {[get_parameter_value NUM_OF_CHANNELS] > 6} { + + add_interface din_6 conduit end + add_interface_port din_6 din_enable_6 enable Input 1 + add_interface_port din_6 din_valid_6 valid Input 1 + add_interface_port din_6 din_data_6 data Input DIN_DATA_WIDTH + + set_interface_property din_6 associatedClock if_din_clk + set_interface_property din_6 associatedReset none + + add_interface dout_6 conduit end + add_interface_port dout_6 dout_enable_6 enable Output 1 + add_interface_port dout_6 dout_valid_6 valid Output 1 + add_interface_port dout_6 dout_data_6 data Output DOUT_DATA_WIDTH + + set_interface_property dout_6 associatedClock if_dout_clk + set_interface_property dout_6 associatedReset none + } + + if {[get_parameter_value NUM_OF_CHANNELS] > 7} { + + add_interface din_7 conduit end + add_interface_port din_7 din_enable_7 enable Input 1 + add_interface_port din_7 din_valid_7 valid Input 1 + add_interface_port din_7 din_data_7 data Input DIN_DATA_WIDTH + + set_interface_property din_7 associatedClock if_din_clk + set_interface_property din_7 associatedReset none + + add_interface dout_7 conduit end + add_interface_port dout_7 dout_enable_7 enable Output 1 + add_interface_port dout_7 dout_valid_7 valid Output 1 + add_interface_port dout_7 dout_data_7 data Output DOUT_DATA_WIDTH + + set_interface_property dout_7 associatedClock if_dout_clk + set_interface_property dout_7 associatedReset none + } + +} + diff --git a/adi_library/util_wfifo/util_wfifo_ip.tcl b/adi_library/util_wfifo/util_wfifo_ip.tcl new file mode 100644 index 00000000..dc9f071a --- /dev/null +++ b/adi_library/util_wfifo/util_wfifo_ip.tcl @@ -0,0 +1,47 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_wfifo +adi_ip_files util_wfifo [list \ + "$ad_hdl_dir/library/common/ad_mem.v" \ + "util_wfifo_constr.xdc" \ + "util_wfifo.v" ] + +adi_ip_properties_lite util_wfifo + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/util_wfifo} [ipx::current_core] + +ipx::remove_all_bus_interface [ipx::current_core] +set_property driver_value 0 [ipx::get_ports *din_enable* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *din_valid* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *din_data* -of_objects [ipx::current_core]] +set_property driver_value 0 [ipx::get_ports *dout_ovf* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 1} \ + [ipx::get_ports *_1* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 2} \ + [ipx::get_ports *_2* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 3} \ + [ipx::get_ports *_3* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 4} \ + [ipx::get_ports *_4* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 5} \ + [ipx::get_ports *_5* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 6} \ + [ipx::get_ports *_6* -of_objects [ipx::current_core]] +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_CHANNELS')) > 7} \ + [ipx::get_ports *_7* -of_objects [ipx::current_core]] + +ipx::infer_bus_interface din_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface din_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface dout_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface dout_rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] + + diff --git a/adi_library/util_wfifo/xgui/util_wfifo_v1_0.tcl b/adi_library/util_wfifo/xgui/util_wfifo_v1_0.tcl new file mode 100644 index 00000000..17c4c627 --- /dev/null +++ b/adi_library/util_wfifo/xgui/util_wfifo_v1_0.tcl @@ -0,0 +1,70 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "DIN_ADDRESS_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "DIN_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "DOUT_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_OF_CHANNELS" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.DIN_ADDRESS_WIDTH { PARAM_VALUE.DIN_ADDRESS_WIDTH } { + # Procedure called to update DIN_ADDRESS_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DIN_ADDRESS_WIDTH { PARAM_VALUE.DIN_ADDRESS_WIDTH } { + # Procedure called to validate DIN_ADDRESS_WIDTH + return true +} + +proc update_PARAM_VALUE.DIN_DATA_WIDTH { PARAM_VALUE.DIN_DATA_WIDTH } { + # Procedure called to update DIN_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DIN_DATA_WIDTH { PARAM_VALUE.DIN_DATA_WIDTH } { + # Procedure called to validate DIN_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.DOUT_DATA_WIDTH { PARAM_VALUE.DOUT_DATA_WIDTH } { + # Procedure called to update DOUT_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DOUT_DATA_WIDTH { PARAM_VALUE.DOUT_DATA_WIDTH } { + # Procedure called to validate DOUT_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to update NUM_OF_CHANNELS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_CHANNELS { PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to validate NUM_OF_CHANNELS + return true +} + + +proc update_MODELPARAM_VALUE.NUM_OF_CHANNELS { MODELPARAM_VALUE.NUM_OF_CHANNELS PARAM_VALUE.NUM_OF_CHANNELS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_CHANNELS}] ${MODELPARAM_VALUE.NUM_OF_CHANNELS} +} + +proc update_MODELPARAM_VALUE.DIN_DATA_WIDTH { MODELPARAM_VALUE.DIN_DATA_WIDTH PARAM_VALUE.DIN_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DIN_DATA_WIDTH}] ${MODELPARAM_VALUE.DIN_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.DOUT_DATA_WIDTH { MODELPARAM_VALUE.DOUT_DATA_WIDTH PARAM_VALUE.DOUT_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DOUT_DATA_WIDTH}] ${MODELPARAM_VALUE.DOUT_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.DIN_ADDRESS_WIDTH { MODELPARAM_VALUE.DIN_ADDRESS_WIDTH PARAM_VALUE.DIN_ADDRESS_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DIN_ADDRESS_WIDTH}] ${MODELPARAM_VALUE.DIN_ADDRESS_WIDTH} +} + diff --git a/adi_library/xilinx/axi_adcfifo/Makefile b/adi_library/xilinx/axi_adcfifo/Makefile new file mode 100644 index 00000000..b655d0a4 --- /dev/null +++ b/adi_library/xilinx/axi_adcfifo/Makefile @@ -0,0 +1,21 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_adcfifo + +XILINX_DEPS += ../../common/ad_axis_inf_rx.v +XILINX_DEPS += ../../common/ad_mem.v +XILINX_DEPS += ../../common/ad_mem_asym.v +XILINX_DEPS += ../../common/up_xfer_status.v +XILINX_DEPS += axi_adcfifo.v +XILINX_DEPS += axi_adcfifo_adc.v +XILINX_DEPS += axi_adcfifo_constr.xdc +XILINX_DEPS += axi_adcfifo_dma.v +XILINX_DEPS += axi_adcfifo_ip.tcl +XILINX_DEPS += axi_adcfifo_rd.v +XILINX_DEPS += axi_adcfifo_wr.v + +include ../../scripts/library.mk diff --git a/adi_library/xilinx/axi_adcfifo/axi_adcfifo.v b/adi_library/xilinx/axi_adcfifo/axi_adcfifo.v new file mode 100644 index 00000000..628b3e39 --- /dev/null +++ b/adi_library/xilinx/axi_adcfifo/axi_adcfifo.v @@ -0,0 +1,242 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adcfifo #( + + parameter ADC_DATA_WIDTH = 128, + parameter DMA_DATA_WIDTH = 64, + parameter AXI_DATA_WIDTH = 512, + parameter DMA_READY_ENABLE = 1, + parameter AXI_SIZE = 2, + parameter AXI_LENGTH = 16, + parameter AXI_ADDRESS = 32'h00000000, + parameter AXI_ADDRESS_LIMIT = 32'hffffffff +) ( + + // fifo interface + + input adc_rst, + input adc_clk, + input adc_wr, + input [ADC_DATA_WIDTH-1:0] adc_wdata, + output adc_wovf, + + // dma interface + + input dma_clk, + output dma_wr, + output [DMA_DATA_WIDTH-1:0] dma_wdata, + input dma_wready, + input dma_xfer_req, + output [ 3:0] dma_xfer_status, + + // axi interface + + input axi_clk, + input axi_resetn, + output axi_awvalid, + output [ 3:0] axi_awid, + output [ 1:0] axi_awburst, + output axi_awlock, + output [ 3:0] axi_awcache, + output [ 2:0] axi_awprot, + output [ 3:0] axi_awqos, + output [ 3:0] axi_awuser, + output [ 7:0] axi_awlen, + output [ 2:0] axi_awsize, + output [ 31:0] axi_awaddr, + input axi_awready, + output axi_wvalid, + output [AXI_DATA_WIDTH-1:0] axi_wdata, + output [(AXI_DATA_WIDTH/8)-1:0] axi_wstrb, + output axi_wlast, + output [ 3:0] axi_wuser, + input axi_wready, + input axi_bvalid, + input [ 3:0] axi_bid, + input [ 1:0] axi_bresp, + input [ 3:0] axi_buser, + output axi_bready, + output axi_arvalid, + output [ 3:0] axi_arid, + output [ 1:0] axi_arburst, + output axi_arlock, + output [ 3:0] axi_arcache, + output [ 2:0] axi_arprot, + output [ 3:0] axi_arqos, + output [ 3:0] axi_aruser, + output [ 7:0] axi_arlen, + output [ 2:0] axi_arsize, + output [ 31:0] axi_araddr, + input axi_arready, + input axi_rvalid, + input [ 3:0] axi_rid, + input [ 3:0] axi_ruser, + input [ 1:0] axi_rresp, + input axi_rlast, + input [AXI_DATA_WIDTH-1:0] axi_rdata, + output axi_rready +); + + // internal signals + + wire adc_dwr_s; + wire [AXI_DATA_WIDTH-1:0] adc_ddata_s; + wire axi_rd_req_s; + wire [ 31:0] axi_rd_addr_s; + wire [ 3:0] axi_xfer_status_s; + wire axi_drst_s; + wire axi_dvalid_s; + wire [AXI_DATA_WIDTH-1:0] axi_ddata_s; + wire axi_dready_s; + + // instantiations + + axi_adcfifo_adc #( + .AXI_DATA_WIDTH (AXI_DATA_WIDTH), + .ADC_DATA_WIDTH (ADC_DATA_WIDTH) + ) i_adc_if ( + .adc_rst (adc_rst), + .adc_clk (adc_clk), + .adc_wr (adc_wr), + .adc_wdata (adc_wdata), + .adc_wovf (adc_wovf), + .adc_dwr (adc_dwr_s), + .adc_ddata (adc_ddata_s), + .axi_drst (axi_drst_s), + .axi_clk (axi_clk), + .axi_xfer_status (axi_xfer_status_s)); + + axi_adcfifo_wr #( + .AXI_DATA_WIDTH (AXI_DATA_WIDTH), + .AXI_SIZE (AXI_SIZE), + .AXI_LENGTH (AXI_LENGTH), + .AXI_ADDRESS (AXI_ADDRESS), + .AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT) + ) i_wr ( + .dma_xfer_req (dma_xfer_req), + .axi_rd_req (axi_rd_req_s), + .axi_rd_addr (axi_rd_addr_s), + .adc_rst (adc_rst), + .adc_clk (adc_clk), + .adc_wr (adc_dwr_s), + .adc_wdata (adc_ddata_s), + .axi_clk (axi_clk), + .axi_resetn (axi_resetn), + .axi_awvalid (axi_awvalid), + .axi_awid (axi_awid), + .axi_awburst (axi_awburst), + .axi_awlock (axi_awlock), + .axi_awcache (axi_awcache), + .axi_awprot (axi_awprot), + .axi_awqos (axi_awqos), + .axi_awuser (axi_awuser), + .axi_awlen (axi_awlen), + .axi_awsize (axi_awsize), + .axi_awaddr (axi_awaddr), + .axi_awready (axi_awready), + .axi_wvalid (axi_wvalid), + .axi_wdata (axi_wdata), + .axi_wstrb (axi_wstrb), + .axi_wlast (axi_wlast), + .axi_wuser (axi_wuser), + .axi_wready (axi_wready), + .axi_bvalid (axi_bvalid), + .axi_bid (axi_bid), + .axi_bresp (axi_bresp), + .axi_buser (axi_buser), + .axi_bready (axi_bready), + .axi_dwovf (axi_xfer_status_s[0]), + .axi_dwunf (axi_xfer_status_s[1]), + .axi_werror (axi_xfer_status_s[2])); + + axi_adcfifo_rd #( + .AXI_DATA_WIDTH (AXI_DATA_WIDTH), + .AXI_SIZE (AXI_SIZE), + .AXI_LENGTH (AXI_LENGTH), + .AXI_ADDRESS (AXI_ADDRESS), + .AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT) + ) i_rd ( + .dma_xfer_req (dma_xfer_req), + .axi_rd_req (axi_rd_req_s), + .axi_rd_addr (axi_rd_addr_s), + .axi_clk (axi_clk), + .axi_resetn (axi_resetn), + .axi_arvalid (axi_arvalid), + .axi_arid (axi_arid), + .axi_arburst (axi_arburst), + .axi_arlock (axi_arlock), + .axi_arcache (axi_arcache), + .axi_arprot (axi_arprot), + .axi_arqos (axi_arqos), + .axi_aruser (axi_aruser), + .axi_arlen (axi_arlen), + .axi_arsize (axi_arsize), + .axi_araddr (axi_araddr), + .axi_arready (axi_arready), + .axi_rvalid (axi_rvalid), + .axi_rid (axi_rid), + .axi_ruser (axi_ruser), + .axi_rresp (axi_rresp), + .axi_rlast (axi_rlast), + .axi_rdata (axi_rdata), + .axi_rready (axi_rready), + .axi_rerror (axi_xfer_status_s[3]), + .axi_drst (axi_drst_s), + .axi_dvalid (axi_dvalid_s), + .axi_ddata (axi_ddata_s), + .axi_dready (axi_dready_s)); + + axi_adcfifo_dma #( + .AXI_DATA_WIDTH (AXI_DATA_WIDTH), + .DMA_DATA_WIDTH (DMA_DATA_WIDTH), + .DMA_READY_ENABLE (DMA_READY_ENABLE) + ) i_dma_if ( + .axi_clk (axi_clk), + .axi_drst (axi_drst_s), + .axi_dvalid (axi_dvalid_s), + .axi_ddata (axi_ddata_s), + .axi_dready (axi_dready_s), + .axi_xfer_status (axi_xfer_status_s), + .dma_clk (dma_clk), + .dma_wr (dma_wr), + .dma_wdata (dma_wdata), + .dma_wready (dma_wready), + .dma_xfer_req (dma_xfer_req), + .dma_xfer_status (dma_xfer_status)); + +endmodule diff --git a/adi_library/xilinx/axi_adcfifo/axi_adcfifo.xpr b/adi_library/xilinx/axi_adcfifo/axi_adcfifo.xpr new file mode 100644 index 00000000..40879b44 --- /dev/null +++ b/adi_library/xilinx/axi_adcfifo/axi_adcfifo.xpr @@ -0,0 +1,461 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v b/adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v new file mode 100644 index 00000000..386b4849 --- /dev/null +++ b/adi_library/xilinx/axi_adcfifo/axi_adcfifo_adc.v @@ -0,0 +1,126 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adcfifo_adc #( + + parameter ADC_DATA_WIDTH = 128, + parameter AXI_DATA_WIDTH = 512 +) ( + + // fifo interface + + input adc_rst, + input adc_clk, + input adc_wr, + input [ADC_DATA_WIDTH-1:0] adc_wdata, + output reg adc_wovf, + output reg adc_dwr, + output reg [AXI_DATA_WIDTH-1:0] adc_ddata, + + // axi interface + + input axi_drst, + input axi_clk, + input [ 3:0] axi_xfer_status +); + + localparam ADC_MEM_RATIO = AXI_DATA_WIDTH/ADC_DATA_WIDTH; + + // internal registers + + reg [ 2:0] adc_wcnt_int = 'd0; + + // internal signals + + wire [ 3:0] adc_xfer_status_s; + + // write interface: supports only 64, 128, 256 and 512 against 512 + + always @(posedge adc_clk) begin + if (adc_rst == 1'b1) begin + adc_wovf <= 'd0; + adc_wcnt_int <= 'd0; + adc_dwr <= 'd0; + adc_ddata <= 'd0; + end else begin + adc_wovf <= | adc_xfer_status_s; + adc_dwr <= (ADC_MEM_RATIO == 8) ? adc_wr & adc_wcnt_int[0] & adc_wcnt_int[1] & adc_wcnt_int[2] : + (ADC_MEM_RATIO == 4) ? adc_wr & adc_wcnt_int[0] & adc_wcnt_int[1] : + (ADC_MEM_RATIO == 2) ? adc_wr & adc_wcnt_int[0] : + (ADC_MEM_RATIO == 1) ? adc_wr : 'd0; + if (adc_wr == 1'b1) begin + adc_wcnt_int <= adc_wcnt_int + 1'b1; + case (ADC_MEM_RATIO) + 8: begin + adc_ddata[((ADC_DATA_WIDTH*8)-1):(ADC_DATA_WIDTH*7)] <= adc_wdata; + adc_ddata[((ADC_DATA_WIDTH*7)-1):(ADC_DATA_WIDTH*0)] <= + adc_ddata[((ADC_DATA_WIDTH*8)-1):(ADC_DATA_WIDTH*1)]; + end + 4: begin + adc_ddata[((ADC_DATA_WIDTH*4)-1):(ADC_DATA_WIDTH*3)] <= adc_wdata; + adc_ddata[((ADC_DATA_WIDTH*3)-1):(ADC_DATA_WIDTH*0)] <= + adc_ddata[((ADC_DATA_WIDTH*4)-1):(ADC_DATA_WIDTH*1)]; + end + 2: begin + adc_ddata[((ADC_DATA_WIDTH*2)-1):(ADC_DATA_WIDTH*1)] <= adc_wdata; + adc_ddata[((ADC_DATA_WIDTH*1)-1):(ADC_DATA_WIDTH*0)] <= + adc_ddata[((ADC_DATA_WIDTH*2)-1):(ADC_DATA_WIDTH*1)]; + end + 1: begin + adc_ddata <= adc_wdata; + end + default: begin + adc_ddata <= 'd0; + end + endcase + end + end + end + + // instantiations + + up_xfer_status #( + .DATA_WIDTH(4) + ) i_xfer_status ( + .up_rstn (~adc_rst), + .up_clk (adc_clk), + .up_data_status (adc_xfer_status_s), + .d_rst (axi_drst), + .d_clk (axi_clk), + .d_data_status (axi_xfer_status)); + +endmodule diff --git a/adi_library/xilinx/axi_adcfifo/axi_adcfifo_constr.xdc b/adi_library/xilinx/axi_adcfifo/axi_adcfifo_constr.xdc new file mode 100644 index 00000000..54fe4ed4 --- /dev/null +++ b/adi_library/xilinx/axi_adcfifo/axi_adcfifo_constr.xdc @@ -0,0 +1,34 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property ASYNC_REG TRUE \ + [get_cells -hier *axi_waddr_m1_reg*] \ + [get_cells -hier *axi_waddr_m2_reg*] \ + [get_cells -hier *adc_xfer_req_m_reg[0]*] \ + [get_cells -hier *axi_xfer_req_m_reg[0]*] + +set_false_path -from [get_cells -hier -filter {name =~ *dma_* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *axi_*_m* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *axi_* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *dma_*_m* && IS_SEQUENTIAL}] + +set_false_path -from [get_cells -hier -filter {name =~ *adc_* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *axi_*_m* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *axi_* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *adc_*_m* && IS_SEQUENTIAL}] + +set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *up_* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *d_xfer_* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *adc_rel_waddr* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *axi_rel_waddr* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *axi_waddr_rel_reg* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *dma_waddr_rel_reg* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *dma_raddr_rel_reg* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ *axi_raddr_rel_reg* && IS_SEQUENTIAL}] + +set_false_path -to [get_cells -hier -filter {name =~ *adc_xfer_req_m_reg[0]* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *axi_xfer_req_m_reg[0]* && IS_SEQUENTIAL}] diff --git a/adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v b/adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v new file mode 100644 index 00000000..9b13e49b --- /dev/null +++ b/adi_library/xilinx/axi_adcfifo/axi_adcfifo_dma.v @@ -0,0 +1,227 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adcfifo_dma #( + + parameter AXI_DATA_WIDTH = 512, + parameter DMA_DATA_WIDTH = 64, + parameter DMA_READY_ENABLE = 1 +) ( + input axi_clk, + input axi_drst, + input axi_dvalid, + input [AXI_DATA_WIDTH-1:0] axi_ddata, + output reg axi_dready, + input [ 3:0] axi_xfer_status, + + input dma_clk, + output dma_wr, + output [DMA_DATA_WIDTH-1:0] dma_wdata, + input dma_wready, + input dma_xfer_req, + output [ 3:0] dma_xfer_status +); + + localparam DMA_MEM_RATIO = AXI_DATA_WIDTH/DMA_DATA_WIDTH; + localparam DMA_ADDRESS_WIDTH = 8; + localparam AXI_ADDRESS_WIDTH = (DMA_MEM_RATIO == 2) ? (DMA_ADDRESS_WIDTH - 1) : + ((DMA_MEM_RATIO == 4) ? (DMA_ADDRESS_WIDTH - 2) : (DMA_ADDRESS_WIDTH - 3)); + + // internal registers + + reg [AXI_ADDRESS_WIDTH-1:0] axi_waddr = 'd0; + reg [ 2:0] axi_waddr_rel_count = 'd0; + reg axi_waddr_rel_t = 'd0; + reg [AXI_ADDRESS_WIDTH-1:0] axi_waddr_rel = 'd0; + reg [ 2:0] axi_raddr_rel_t_m = 'd0; + reg [DMA_ADDRESS_WIDTH-1:0] axi_raddr_rel = 'd0; + reg [DMA_ADDRESS_WIDTH-1:0] axi_addr_diff = 'd0; + reg dma_rst = 'd0; + reg [ 2:0] dma_waddr_rel_t_m = 'd0; + reg [AXI_ADDRESS_WIDTH-1:0] dma_waddr_rel = 'd0; + reg dma_rd = 'd0; + reg dma_rd_d = 'd0; + reg [DMA_DATA_WIDTH-1:0] dma_rdata_d = 'd0; + reg [DMA_ADDRESS_WIDTH-1:0] dma_raddr = 'd0; + reg [ 2:0] dma_raddr_rel_count = 'd0; + reg dma_raddr_rel_t = 'd0; + reg [DMA_ADDRESS_WIDTH-1:0] dma_raddr_rel = 'd0; + + // internal signals + + wire [DMA_ADDRESS_WIDTH:0] axi_addr_diff_s; + wire axi_raddr_rel_t_s; + wire [DMA_ADDRESS_WIDTH-1:0] axi_waddr_s; + wire dma_waddr_rel_t_s; + wire [DMA_ADDRESS_WIDTH-1:0] dma_waddr_rel_s; + wire dma_wready_s; + wire dma_rd_s; + wire [DMA_DATA_WIDTH-1:0] dma_rdata_s; + + // write interface + + always @(posedge axi_clk) begin + if (axi_drst == 1'b1) begin + axi_waddr <= 'd0; + axi_waddr_rel_count <= 'd0; + axi_waddr_rel_t <= 'd0; + axi_waddr_rel <= 'd0; + end else begin + if (axi_dvalid == 1'b1) begin + axi_waddr <= axi_waddr + 1'b1; + end + axi_waddr_rel_count <= axi_waddr_rel_count + 1'b1; + if (axi_waddr_rel_count == 3'd7) begin + axi_waddr_rel_t <= ~axi_waddr_rel_t; + axi_waddr_rel <= axi_waddr; + end + end + end + + assign axi_addr_diff_s = {1'b1, axi_waddr_s} - axi_raddr_rel; + assign axi_raddr_rel_t_s = axi_raddr_rel_t_m[2] ^ axi_raddr_rel_t_m[1]; + assign axi_waddr_s = (DMA_MEM_RATIO == 2) ? {axi_waddr, 1'd0} : + ((DMA_MEM_RATIO == 4) ? {axi_waddr, 2'd0} : {axi_waddr, 3'd0}); + + always @(posedge axi_clk) begin + if (axi_drst == 1'b1) begin + axi_raddr_rel_t_m <= 'd0; + axi_raddr_rel <= 'd0; + axi_addr_diff <= 'd0; + axi_dready <= 'd0; + end else begin + axi_raddr_rel_t_m <= {axi_raddr_rel_t_m[1:0], dma_raddr_rel_t}; + if (axi_raddr_rel_t_s == 1'b1) begin + axi_raddr_rel <= dma_raddr_rel; + end + axi_addr_diff <= axi_addr_diff_s[DMA_ADDRESS_WIDTH-1:0]; + if (axi_addr_diff >= 180) begin + axi_dready <= 1'b0; + end else if (axi_addr_diff <= 8) begin + axi_dready <= 1'b1; + end + end + end + + // read interface + + assign dma_waddr_rel_t_s = dma_waddr_rel_t_m[2] ^ dma_waddr_rel_t_m[1]; + assign dma_waddr_rel_s = (DMA_MEM_RATIO == 2) ? {dma_waddr_rel, 1'd0} : + ((DMA_MEM_RATIO == 4) ? {dma_waddr_rel, 2'd0} : {dma_waddr_rel, 3'd0}); + + always @(posedge dma_clk) begin + if (dma_xfer_req == 1'b0) begin + dma_rst <= 1'b1; + dma_waddr_rel_t_m <= 'd0; + dma_waddr_rel <= 'd0; + end else begin + dma_rst <= 1'b0; + dma_waddr_rel_t_m <= {dma_waddr_rel_t_m[1:0], axi_waddr_rel_t}; + if (dma_waddr_rel_t_s == 1'b1) begin + dma_waddr_rel <= axi_waddr_rel; + end + end + end + + assign dma_wready_s = (DMA_READY_ENABLE == 0) ? 1'b1 : dma_wready; + assign dma_rd_s = (dma_raddr == dma_waddr_rel_s) ? 1'b0 : dma_wready_s; + + always @(posedge dma_clk) begin + if (dma_xfer_req == 1'b0) begin + dma_rd <= 'd0; + dma_rd_d <= 'd0; + dma_rdata_d <= 'd0; + dma_raddr <= 'd0; + dma_raddr_rel_count <= 'd0; + dma_raddr_rel_t <= 'd0; + dma_raddr_rel <= 'd0; + end else begin + dma_rd <= dma_rd_s; + dma_rd_d <= dma_rd; + dma_rdata_d <= dma_rdata_s; + if (dma_rd_s == 1'b1) begin + dma_raddr <= dma_raddr + 1'b1; + end + dma_raddr_rel_count <= dma_raddr_rel_count + 1'b1; + if (dma_raddr_rel_count == 3'd7) begin + dma_raddr_rel_t <= ~dma_raddr_rel_t; + dma_raddr_rel <= dma_raddr; + end + end + end + + // instantiations + + ad_mem_asym #( + .A_ADDRESS_WIDTH (AXI_ADDRESS_WIDTH), + .A_DATA_WIDTH (AXI_DATA_WIDTH), + .B_ADDRESS_WIDTH (DMA_ADDRESS_WIDTH), + .B_DATA_WIDTH (DMA_DATA_WIDTH) + ) i_mem_asym ( + .clka (axi_clk), + .wea (axi_dvalid), + .addra (axi_waddr), + .dina (axi_ddata), + .clkb (dma_clk), + .reb (1'b1), + .addrb (dma_raddr), + .doutb (dma_rdata_s)); + + ad_axis_inf_rx #( + .DATA_WIDTH(DMA_DATA_WIDTH) + ) i_axis_inf ( + .clk (dma_clk), + .rst (dma_rst), + .valid (dma_rd_d), + .last (1'd0), + .data (dma_rdata_d), + .inf_valid (dma_wr), + .inf_last (), + .inf_data (dma_wdata), + .inf_ready (dma_wready)); + + up_xfer_status #( + .DATA_WIDTH(4) + ) i_xfer_status ( + .up_rstn (~dma_rst), + .up_clk (dma_clk), + .up_data_status (dma_xfer_status), + .d_rst (axi_drst), + .d_clk (axi_clk), + .d_data_status (axi_xfer_status)); + +endmodule diff --git a/adi_library/xilinx/axi_adcfifo/axi_adcfifo_ip.tcl b/adi_library/xilinx/axi_adcfifo/axi_adcfifo_ip.tcl new file mode 100644 index 00000000..4cc6c963 --- /dev/null +++ b/adi_library/xilinx/axi_adcfifo/axi_adcfifo_ip.tcl @@ -0,0 +1,91 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_adcfifo +adi_ip_files axi_adcfifo [list \ + "$ad_hdl_dir/library/common/ad_mem.v" \ + "$ad_hdl_dir/library/common/ad_mem_asym.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \ + "axi_adcfifo_adc.v" \ + "axi_adcfifo_dma.v" \ + "axi_adcfifo_wr.v" \ + "axi_adcfifo_rd.v" \ + "axi_adcfifo.v" \ + "axi_adcfifo_constr.xdc" ] + +adi_ip_properties_lite axi_adcfifo + +ipx::infer_bus_interface {\ + axi_awvalid \ + axi_awid \ + axi_awburst \ + axi_awlock \ + axi_awcache \ + axi_awprot \ + axi_awqos \ + axi_awuser \ + axi_awlen \ + axi_awsize \ + axi_awaddr \ + axi_awready \ + axi_wvalid \ + axi_wdata \ + axi_wstrb \ + axi_wlast \ + axi_wuser \ + axi_wready \ + axi_bvalid \ + axi_bid \ + axi_bresp \ + axi_buser \ + axi_bready \ + axi_arvalid \ + axi_arid \ + axi_arburst \ + axi_arlock \ + axi_arcache \ + axi_arprot \ + axi_arqos \ + axi_aruser \ + axi_arlen \ + axi_arsize \ + axi_araddr \ + axi_arready \ + axi_rvalid \ + axi_rid \ + axi_ruser \ + axi_rresp \ + axi_rlast \ + axi_rdata \ + axi_rready} \ +xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] + +ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface axi_resetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] +ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \ + -of_objects [ipx::current_core]] +set_property value axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ + -of_objects [ipx::get_bus_interfaces axi_clk \ + -of_objects [ipx::current_core]]] + +ipx::add_address_space axi [ipx::current_core] +set_property master_address_space_ref axi [ipx::get_bus_interfaces axi \ + -of_objects [ipx::current_core]] +set_property range 4294967296 [ipx::get_address_spaces axi \ + -of_objects [ipx::current_core]] +set_property width 512 [ipx::get_address_spaces axi \ + -of_objects [ipx::current_core]] + +ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface adc_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface adc_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v b/adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v new file mode 100644 index 00000000..bb4881c6 --- /dev/null +++ b/adi_library/xilinx/axi_adcfifo/axi_adcfifo_rd.v @@ -0,0 +1,201 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adcfifo_rd #( + + parameter AXI_DATA_WIDTH = 512, + parameter AXI_SIZE = 2, + parameter AXI_LENGTH = 16, + parameter AXI_ADDRESS = 32'h00000000, + parameter AXI_ADDRESS_LIMIT = 32'h00000000 +) ( + + // request and synchronization + + input dma_xfer_req, + + // read interface + + input axi_rd_req, + input [ 31:0] axi_rd_addr, + + // axi interface + + input axi_clk, + input axi_resetn, + output reg axi_arvalid, + output [ 3:0] axi_arid, + output [ 1:0] axi_arburst, + output axi_arlock, + output [ 3:0] axi_arcache, + output [ 2:0] axi_arprot, + output [ 3:0] axi_arqos, + output [ 3:0] axi_aruser, + output [ 7:0] axi_arlen, + output [ 2:0] axi_arsize, + output reg [ 31:0] axi_araddr, + input axi_arready, + input axi_rvalid, + input [ 3:0] axi_rid, + input [ 3:0] axi_ruser, + input [ 1:0] axi_rresp, + input axi_rlast, + input [AXI_DATA_WIDTH-1:0] axi_rdata, + output reg axi_rready, + + // axi status + + output reg axi_rerror, + + // fifo interface + + output reg axi_drst, + output reg axi_dvalid, + output reg [AXI_DATA_WIDTH-1:0] axi_ddata, + input axi_dready +); + + localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8; + localparam AXI_AWINCR = AXI_LENGTH * AXI_BYTE_WIDTH; + localparam BUF_THRESHOLD_LO = 6'd3; + localparam BUF_THRESHOLD_HI = 6'd60; + + // internal registers + + reg [ 31:0] axi_rd_addr_h = 'd0; + reg axi_rd = 'd0; + reg axi_rd_active = 'd0; + reg [ 2:0] axi_xfer_req_m = 'd0; + reg axi_xfer_init = 'd0; + reg axi_xfer_enable = 'd0; + + // internal signals + + wire axi_ready_s; + + // read is way too slow- buffer mode + + assign axi_ready_s = (~axi_arvalid | axi_arready) & axi_dready; + + always @(posedge axi_clk or negedge axi_resetn) begin + if (axi_resetn == 1'b0) begin + axi_rd_addr_h <= 'd0; + axi_rd <= 'd0; + axi_rd_active <= 'd0; + axi_xfer_req_m <= 'd0; + axi_xfer_init <= 'd0; + axi_xfer_enable <= 'd0; + end else begin + if (axi_xfer_init == 1'b1) begin + axi_rd_addr_h <= AXI_ADDRESS; + end else if (axi_rd_req == 1'b1) begin + axi_rd_addr_h <= axi_rd_addr; + end + if (axi_rd_active == 1'b1) begin + axi_rd <= 1'b0; + if ((axi_rvalid == 1'b1) && (axi_rlast == 1'b1)) begin + axi_rd_active <= 1'b0; + end + end else if ((axi_ready_s == 1'b1) && (axi_araddr < axi_rd_addr_h)) begin + axi_rd <= axi_xfer_enable; + axi_rd_active <= axi_xfer_enable; + end + axi_xfer_req_m <= {axi_xfer_req_m[1:0], dma_xfer_req}; + axi_xfer_init <= axi_xfer_req_m[1] & ~axi_xfer_req_m[2]; + axi_xfer_enable <= axi_xfer_req_m[2]; + end + end + + // address channel + + assign axi_arid = 4'b0000; + assign axi_arburst = 2'b01; + assign axi_arlock = 1'b0; + assign axi_arcache = 4'b0010; + assign axi_arprot = 3'b000; + assign axi_arqos = 4'b0000; + assign axi_aruser = 4'b0001; + assign axi_arlen = AXI_LENGTH - 1; + assign axi_arsize = AXI_SIZE; + + always @(posedge axi_clk or negedge axi_resetn) begin + if (axi_resetn == 1'b0) begin + axi_arvalid <= 'd0; + axi_araddr <= 'd0; + end else begin + if (axi_arvalid == 1'b1) begin + if (axi_arready == 1'b1) begin + axi_arvalid <= 1'b0; + end + end else begin + if (axi_rd == 1'b1) begin + axi_arvalid <= 1'b1; + end + end + if (axi_xfer_init == 1'b1) begin + axi_araddr <= AXI_ADDRESS; + end else if ((axi_arvalid == 1'b1) && (axi_arready == 1'b1)) begin + axi_araddr <= axi_araddr + AXI_AWINCR; + end + end + end + + // read data channel + + always @(posedge axi_clk or negedge axi_resetn) begin + if (axi_resetn == 1'b0) begin + axi_drst <= 'd1; + axi_dvalid <= 'd0; + axi_ddata <= 'd0; + axi_rready <= 'd0; + end else begin + axi_drst <= ~axi_xfer_req_m[1]; + axi_dvalid <= axi_rvalid; + axi_ddata <= axi_rdata; + axi_rready <= 1'b1; + end + end + + always @(posedge axi_clk or negedge axi_resetn) begin + if (axi_resetn == 1'b0) begin + axi_rerror <= 'd0; + end else begin + axi_rerror <= axi_rvalid & axi_rresp[1]; + end + end + +endmodule diff --git a/adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v b/adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v new file mode 100644 index 00000000..cd1d2200 --- /dev/null +++ b/adi_library/xilinx/axi_adcfifo/axi_adcfifo_wr.v @@ -0,0 +1,422 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adcfifo_wr #( + + parameter AXI_DATA_WIDTH = 512, + parameter AXI_SIZE = 2, + parameter AXI_LENGTH = 16, + parameter AXI_ADDRESS = 32'h00000000, + parameter AXI_ADDRESS_LIMIT = 32'h00000000 +) ( + + // request and synchronization + + input dma_xfer_req, + + // read interface + + output reg axi_rd_req, + output reg [ 31:0] axi_rd_addr, + + // fifo interface + + input adc_rst, + input adc_clk, + input adc_wr, + input [AXI_DATA_WIDTH-1:0] adc_wdata, + + // axi interface + + input axi_clk, + input axi_resetn, + output reg axi_awvalid, + output [ 3:0] axi_awid, + output [ 1:0] axi_awburst, + output axi_awlock, + output [ 3:0] axi_awcache, + output [ 2:0] axi_awprot, + output [ 3:0] axi_awqos, + output [ 3:0] axi_awuser, + output [ 7:0] axi_awlen, + output [ 2:0] axi_awsize, + output reg [ 31:0] axi_awaddr, + input axi_awready, + output axi_wvalid, + output [AXI_DATA_WIDTH-1:0] axi_wdata, + output [AXI_BYTE_WIDTH-1:0] axi_wstrb, + output axi_wlast, + output [ 3:0] axi_wuser, + input axi_wready, + input axi_bvalid, + input [ 3:0] axi_bid, + input [ 1:0] axi_bresp, + input [ 3:0] axi_buser, + output axi_bready, + + // axi status + + output reg axi_dwovf, + output reg axi_dwunf, + output reg axi_werror +); + + localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8; + localparam AXI_AWINCR = AXI_LENGTH * AXI_BYTE_WIDTH; + localparam BUF_THRESHOLD_LO = 8'd6; + localparam BUF_THRESHOLD_HI = 8'd250; + + // internal registers + + reg [ 2:0] adc_xfer_req_m = 'd0; + reg adc_xfer_init = 'd0; + reg adc_xfer_limit = 'd0; + reg adc_xfer_enable = 'd0; + reg [ 31:0] adc_xfer_addr = 'd0; + reg [ 7:0] adc_waddr = 'd0; + reg [ 7:0] adc_waddr_g = 'd0; + reg adc_rel_enable = 'd0; + reg adc_rel_toggle = 'd0; + reg [ 7:0] adc_rel_waddr = 'd0; + reg [ 2:0] axi_rel_toggle_m = 'd0; + reg [ 7:0] axi_rel_waddr = 'd0; + reg [ 7:0] axi_waddr_m1 = 'd0; + reg [ 7:0] axi_waddr_m2 = 'd0; + reg [ 7:0] axi_waddr = 'd0; + reg [ 7:0] axi_addr_diff = 'd0; + reg axi_almost_full = 'd0; + reg axi_almost_empty = 'd0; + reg [ 2:0] axi_xfer_req_m = 'd0; + reg axi_xfer_init = 'd0; + reg [ 7:0] axi_raddr = 'd0; + reg axi_rd = 'd0; + reg axi_rlast = 'd0; + reg axi_rd_d = 'd0; + reg axi_rlast_d = 'd0; + reg [AXI_DATA_WIDTH-1:0] axi_rdata_d = 'd0; + reg axi_reset = 'd0; + + // internal signals + + wire axi_rel_toggle_s; + wire [ 8:0] axi_addr_diff_s; + wire axi_wready_s; + wire axi_rd_s; + wire axi_req_s; + wire axi_rlast_s; + wire [AXI_DATA_WIDTH-1:0] axi_rdata_s; + + // binary to grey conversion + + function [7:0] b2g; + input [7:0] b; + reg [7:0] g; + begin + g[7] = b[7]; + g[6] = b[7] ^ b[6]; + g[5] = b[6] ^ b[5]; + g[4] = b[5] ^ b[4]; + g[3] = b[4] ^ b[3]; + g[2] = b[3] ^ b[2]; + g[1] = b[2] ^ b[1]; + g[0] = b[1] ^ b[0]; + b2g = g; + end + endfunction + + // grey to binary conversion + + function [7:0] g2b; + input [7:0] g; + reg [7:0] b; + begin + b[7] = g[7]; + b[6] = b[7] ^ g[6]; + b[5] = b[6] ^ g[5]; + b[4] = b[5] ^ g[4]; + b[3] = b[4] ^ g[3]; + b[2] = b[3] ^ g[2]; + b[1] = b[2] ^ g[1]; + b[0] = b[1] ^ g[0]; + g2b = b; + end + endfunction + + // fifo interface + + always @(posedge adc_clk) begin + if (adc_rst == 1'b1) begin + adc_waddr <= 'd0; + adc_waddr_g <= 'd0; + adc_xfer_req_m <= 'd0; + adc_xfer_init <= 'd0; + adc_xfer_limit <= 'd0; + adc_xfer_enable <= 'd0; + adc_xfer_addr <= 'd0; + adc_rel_enable <= 'd0; + adc_rel_toggle <= 'd0; + adc_rel_waddr <= 'd0; + end else begin + if ((adc_wr == 1'b1) && (adc_xfer_enable == 1'b1)) begin + adc_waddr <= adc_waddr + 1'b1; + end + adc_waddr_g <= b2g(adc_waddr); + adc_xfer_req_m <= {adc_xfer_req_m[1:0], dma_xfer_req}; + adc_xfer_init <= adc_xfer_req_m[1] & ~adc_xfer_req_m[2]; + if (adc_xfer_init == 1'b1) begin + adc_xfer_limit <= 1'd1; + end else if ((adc_xfer_addr >= AXI_ADDRESS_LIMIT) || (adc_xfer_enable == 1'b0)) begin + adc_xfer_limit <= 1'd0; + end + if (adc_xfer_init == 1'b1) begin + adc_xfer_enable <= 1'b1; + adc_xfer_addr <= AXI_ADDRESS; + end else if ((adc_waddr[1:0] == 2'h3) && (adc_wr == 1'b1)) begin + adc_xfer_enable <= adc_xfer_req_m[2] & adc_xfer_limit; + adc_xfer_addr <= adc_xfer_addr + AXI_AWINCR; + end + if (adc_waddr[1:0] == 2'h3) begin + adc_rel_enable <= adc_wr; + end else begin + adc_rel_enable <= 1'd0; + end + if (adc_rel_enable == 1'b1) begin + adc_rel_toggle <= ~adc_rel_toggle; + adc_rel_waddr <= adc_waddr; + end + end + end + + // fifo signals on axi side + + assign axi_rel_toggle_s = axi_rel_toggle_m[2] ^ axi_rel_toggle_m[1]; + + always @(posedge axi_clk or negedge axi_resetn) begin + if (axi_resetn == 1'b0) begin + axi_rel_toggle_m <= 'd0; + axi_rel_waddr <= 'd0; + axi_waddr_m1 <= 'd0; + axi_waddr_m2 <= 'd0; + axi_waddr <= 'd0; + end else begin + axi_rel_toggle_m <= {axi_rel_toggle_m[1:0], adc_rel_toggle}; + if (axi_rel_toggle_s == 1'b1) begin + axi_rel_waddr <= adc_rel_waddr; + end + axi_waddr_m1 <= adc_waddr_g; + axi_waddr_m2 <= axi_waddr_m1; + axi_waddr <= g2b(axi_waddr_m2); + end + end + + // overflow (no underflow possible) + + assign axi_addr_diff_s = {1'b1, axi_waddr} - axi_raddr; + + always @(posedge axi_clk or negedge axi_resetn) begin + if (axi_resetn == 1'b0) begin + axi_addr_diff <= 'd0; + axi_almost_full <= 'd0; + axi_dwunf <= 'd0; + axi_almost_empty <= 'd0; + axi_dwovf <= 'd0; + end else begin + axi_addr_diff <= axi_addr_diff_s[7:0]; + if (axi_addr_diff > BUF_THRESHOLD_HI) begin + axi_almost_full <= 1'b1; + axi_dwunf <= axi_almost_empty; + end else begin + axi_almost_full <= 1'b0; + axi_dwunf <= 1'b0; + end + if (axi_addr_diff < BUF_THRESHOLD_LO) begin + axi_almost_empty <= 1'b1; + axi_dwovf <= axi_almost_full; + end else begin + axi_almost_empty <= 1'b0; + axi_dwovf <= 1'b0; + end + end + end + + // transfer request is required to keep things in sync + + always @(posedge axi_clk or negedge axi_resetn) begin + if (axi_resetn == 1'b0) begin + axi_xfer_req_m <= 'd0; + axi_xfer_init <= 'd0; + end else begin + axi_xfer_req_m <= {axi_xfer_req_m[1:0], dma_xfer_req}; + axi_xfer_init <= axi_xfer_req_m[1] & ~axi_xfer_req_m[2]; + end + end + + // read is initiated if xfer enabled + + assign axi_wready_s = ~axi_wvalid | axi_wready; + assign axi_rd_s = (axi_rel_waddr == axi_raddr) ? 1'b0 : axi_wready_s; + assign axi_req_s = (axi_raddr[1:0] == 2'h0) ? axi_rd_s : 1'b0; + assign axi_rlast_s = (axi_raddr[1:0] == 2'h3) ? axi_rd_s : 1'b0; + + always @(posedge axi_clk or negedge axi_resetn) begin + if (axi_resetn == 1'b0) begin + axi_raddr <= 'd0; + axi_rd <= 'd0; + axi_rlast <= 'd0; + axi_rd_d <= 'd0; + axi_rlast_d <= 'd0; + axi_rdata_d <= 'd0; + end else begin + if (axi_rd_s == 1'b1) begin + axi_raddr <= axi_raddr + 1'b1; + end + axi_rd <= axi_rd_s; + axi_rlast <= axi_rlast_s; + axi_rd_d <= axi_rd; + axi_rlast_d <= axi_rlast; + axi_rdata_d <= axi_rdata_s; + end + end + + // send read request for every burst about to be completed + + always @(posedge axi_clk or negedge axi_resetn) begin + if (axi_resetn == 1'b0) begin + axi_rd_req <= 'd0; + axi_rd_addr <= 'd0; + end else begin + axi_rd_req <= axi_rlast_s; + if (axi_xfer_init == 1'b1) begin + axi_rd_addr <= AXI_ADDRESS; + end else if (axi_rd_req == 1'b1) begin + axi_rd_addr <= axi_rd_addr + AXI_AWINCR; + end + end + end + + // address channel + + assign axi_awid = 4'b0000; + assign axi_awburst = 2'b01; + assign axi_awlock = 1'b0; + assign axi_awcache = 4'b0010; + assign axi_awprot = 3'b000; + assign axi_awqos = 4'b0000; + assign axi_awuser = 4'b0001; + assign axi_awlen = AXI_LENGTH - 1; + assign axi_awsize = AXI_SIZE; + + always @(posedge axi_clk or negedge axi_resetn) begin + if (axi_resetn == 1'b0) begin + axi_awvalid <= 'd0; + axi_awaddr <= 'd0; + end else begin + if (axi_awvalid == 1'b1) begin + if (axi_awready == 1'b1) begin + axi_awvalid <= 1'b0; + end + end else begin + if (axi_req_s == 1'b1) begin + axi_awvalid <= 1'b1; + end + end + if (axi_xfer_init == 1'b1) begin + axi_awaddr <= AXI_ADDRESS; + end else if ((axi_awvalid == 1'b1) && (axi_awready == 1'b1)) begin + axi_awaddr <= axi_awaddr + AXI_AWINCR; + end + end + end + + // write channel + + assign axi_wstrb = {AXI_BYTE_WIDTH{1'b1}}; + assign axi_wuser = 4'b0000; + + // response channel + + assign axi_bready = 1'b1; + + always @(posedge axi_clk or negedge axi_resetn) begin + if (axi_resetn == 1'b0) begin + axi_werror <= 'd0; + end else begin + axi_werror <= axi_bvalid & axi_bready & axi_bresp[1]; + end + end + + // fifo needs a reset + + always @(posedge axi_clk or negedge axi_resetn) begin + if (axi_resetn == 1'b0) begin + axi_reset <= 1'b1; + end else begin + axi_reset <= 1'b0; + end + end + + // interface handler + + ad_axis_inf_rx #( + .DATA_WIDTH(AXI_DATA_WIDTH) + ) i_axis_inf ( + .clk (axi_clk), + .rst (axi_reset), + .valid (axi_rd_d), + .last (axi_rlast_d), + .data (axi_rdata_d), + .inf_valid (axi_wvalid), + .inf_last (axi_wlast), + .inf_data (axi_wdata), + .inf_ready (axi_wready)); + + // buffer + + ad_mem #( + .DATA_WIDTH(AXI_DATA_WIDTH), + .ADDRESS_WIDTH(8) + ) i_mem ( + .clka (adc_clk), + .wea (adc_wr), + .addra (adc_waddr), + .dina (adc_wdata), + .clkb (axi_clk), + .reb (1'b1), + .addrb (axi_raddr), + .doutb (axi_rdata_s)); + +endmodule diff --git a/adi_library/xilinx/axi_adcfifo/component.xml b/adi_library/xilinx/axi_adcfifo/component.xml new file mode 100644 index 00000000..0765e5e8 --- /dev/null +++ b/adi_library/xilinx/axi_adcfifo/component.xml @@ -0,0 +1,1632 @@ + + + analog.com + user + axi_adcfifo + 1.0 + + + axi + + + + + + + + + AWID + + + axi_awid + + + + + AWADDR + + + axi_awaddr + + + + + AWLEN + + + axi_awlen + + + + + AWSIZE + + + axi_awsize + + + + + AWBURST + + + axi_awburst + + + + + AWLOCK + + + axi_awlock + + + + + AWCACHE + + + axi_awcache + + + + + AWPROT + + + axi_awprot + + + + + AWQOS + + + axi_awqos + + + + + AWUSER + + + axi_awuser + + + + + AWVALID + + + axi_awvalid + + + + + AWREADY + + + axi_awready + + + + + WDATA + + + axi_wdata + + + + + WSTRB + + + axi_wstrb + + + + + WLAST + + + axi_wlast + + + + + WUSER + + + axi_wuser + + + + + WVALID + + + axi_wvalid + + + + + WREADY + + + axi_wready + + + + + BID + + + axi_bid + + + + + BRESP + + + axi_bresp + + + + + BUSER + + + axi_buser + + + + + BVALID + + + axi_bvalid + + + + + BREADY + + + axi_bready + + + + + ARID + + + axi_arid + + + + + ARADDR + + + axi_araddr + + + + + ARLEN + + + axi_arlen + + + + + ARSIZE + + + axi_arsize + + + + + ARBURST + + + axi_arburst + + + + + ARLOCK + + + axi_arlock + + + + + ARCACHE + + + axi_arcache + + + + + ARPROT + + + axi_arprot + + + + + ARQOS + + + axi_arqos + + + + + ARUSER + + + axi_aruser + + + + + ARVALID + + + axi_arvalid + + + + + ARREADY + + + axi_arready + + + + + RID + + + axi_rid + + + + + RDATA + + + axi_rdata + + + + + RRESP + + + axi_rresp + + + + + RLAST + + + axi_rlast + + + + + RUSER + + + axi_ruser + + + + + RVALID + + + axi_rvalid + + + + + RREADY + + + axi_rready + + + + + + axi_clk + + + + + + + CLK + + + axi_clk + + + + + + ASSOCIATED_BUSIF + axi + + + ASSOCIATED_RESET + axi_resetn + + + + + axi_resetn + + + + + + + RST + + + axi_resetn + + + + + + POLARITY + ACTIVE_LOW + + + + + dma_clk + + + + + + + CLK + + + dma_clk + + + + + + adc_clk + + + + + + + CLK + + + adc_clk + + + + + + ASSOCIATED_RESET + adc_rst + + + + + adc_rst + + + + + + + RST + + + adc_rst + + + + + + + + axi + 4294967296 + 512 + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_adcfifo + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 83221eac + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_adcfifo + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + ee0a0da4 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + 9aae2ee9 + + + + + + + adc_rst + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_wr + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_wdata + + in + + 127 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + adc_wovf + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_wr + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_wdata + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_wready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_xfer_req + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_xfer_status + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_resetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_awvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_awid + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_awburst + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_awlock + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_awcache + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_awprot + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_awqos + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_awuser + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_awlen + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_awsize + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_awaddr + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_awready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_wvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_wdata + + out + + 511 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_wstrb + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_wlast + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_wuser + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_wready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_bvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_bid + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_bresp + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_buser + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_bready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_arvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_arid + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_arburst + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_arlock + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_arcache + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_arprot + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_arqos + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_aruser + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_arlen + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_arsize + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_araddr + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_arready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_rvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_rid + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_ruser + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_rresp + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_rlast + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_rdata + + in + + 511 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_rready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + ADC_DATA_WIDTH + Adc Data Width + 128 + + + DMA_DATA_WIDTH + Dma Data Width + 64 + + + AXI_DATA_WIDTH + Axi Data Width + 512 + + + DMA_READY_ENABLE + Dma Ready Enable + 1 + + + AXI_SIZE + Axi Size + 2 + + + AXI_LENGTH + Axi Length + 16 + + + AXI_ADDRESS + Axi Address + 0x00000000 + + + AXI_ADDRESS_LIMIT + Axi Address Limit + 0xFFFFFFFF + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + axi_adcfifo_constr.xdc + xdc + + + ../../common/ad_axis_inf_rx.v + verilogSource + + + ../../common/ad_mem.v + verilogSource + + + ../../common/ad_mem_asym.v + verilogSource + + + axi_adcfifo_adc.v + verilogSource + + + axi_adcfifo_dma.v + verilogSource + + + axi_adcfifo_rd.v + verilogSource + + + axi_adcfifo_wr.v + verilogSource + + + ../../common/up_xfer_status.v + verilogSource + + + axi_adcfifo.v + verilogSource + CHECKSUM_e9086634 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../common/ad_axis_inf_rx.v + verilogSource + + + ../../common/ad_mem.v + verilogSource + + + ../../common/ad_mem_asym.v + verilogSource + + + axi_adcfifo_adc.v + verilogSource + + + axi_adcfifo_dma.v + verilogSource + + + axi_adcfifo_rd.v + verilogSource + + + axi_adcfifo_wr.v + verilogSource + + + ../../common/up_xfer_status.v + verilogSource + + + axi_adcfifo.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_adcfifo_v1_0.tcl + tclSource + CHECKSUM_9aae2ee9 + XGUI_VERSION_2 + + + + axi_adcfifo_v1_0 + + + ADC_DATA_WIDTH + Adc Data Width + 128 + + + DMA_DATA_WIDTH + Dma Data Width + 64 + + + AXI_DATA_WIDTH + Axi Data Width + 512 + + + DMA_READY_ENABLE + Dma Ready Enable + 1 + + + AXI_SIZE + Axi Size + 2 + + + AXI_LENGTH + Axi Length + 16 + + + AXI_ADDRESS + Axi Address + 0x00000000 + + + AXI_ADDRESS_LIMIT + Axi Address Limit + 0xFFFFFFFF + + + Component_Name + axi_adcfifo_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_adcfifo_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:57:14Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/xilinx/axi_adcfifo/xgui/axi_adcfifo_v1_0.tcl b/adi_library/xilinx/axi_adcfifo/xgui/axi_adcfifo_v1_0.tcl new file mode 100644 index 00000000..7fac49d2 --- /dev/null +++ b/adi_library/xilinx/axi_adcfifo/xgui/axi_adcfifo_v1_0.tcl @@ -0,0 +1,130 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "ADC_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "AXI_ADDRESS" -parent ${Page_0} + ipgui::add_param $IPINST -name "AXI_ADDRESS_LIMIT" -parent ${Page_0} + ipgui::add_param $IPINST -name "AXI_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "AXI_LENGTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "AXI_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "DMA_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "DMA_READY_ENABLE" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.ADC_DATA_WIDTH { PARAM_VALUE.ADC_DATA_WIDTH } { + # Procedure called to update ADC_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ADC_DATA_WIDTH { PARAM_VALUE.ADC_DATA_WIDTH } { + # Procedure called to validate ADC_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.AXI_ADDRESS { PARAM_VALUE.AXI_ADDRESS } { + # Procedure called to update AXI_ADDRESS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_ADDRESS { PARAM_VALUE.AXI_ADDRESS } { + # Procedure called to validate AXI_ADDRESS + return true +} + +proc update_PARAM_VALUE.AXI_ADDRESS_LIMIT { PARAM_VALUE.AXI_ADDRESS_LIMIT } { + # Procedure called to update AXI_ADDRESS_LIMIT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_ADDRESS_LIMIT { PARAM_VALUE.AXI_ADDRESS_LIMIT } { + # Procedure called to validate AXI_ADDRESS_LIMIT + return true +} + +proc update_PARAM_VALUE.AXI_DATA_WIDTH { PARAM_VALUE.AXI_DATA_WIDTH } { + # Procedure called to update AXI_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_DATA_WIDTH { PARAM_VALUE.AXI_DATA_WIDTH } { + # Procedure called to validate AXI_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.AXI_LENGTH { PARAM_VALUE.AXI_LENGTH } { + # Procedure called to update AXI_LENGTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_LENGTH { PARAM_VALUE.AXI_LENGTH } { + # Procedure called to validate AXI_LENGTH + return true +} + +proc update_PARAM_VALUE.AXI_SIZE { PARAM_VALUE.AXI_SIZE } { + # Procedure called to update AXI_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_SIZE { PARAM_VALUE.AXI_SIZE } { + # Procedure called to validate AXI_SIZE + return true +} + +proc update_PARAM_VALUE.DMA_DATA_WIDTH { PARAM_VALUE.DMA_DATA_WIDTH } { + # Procedure called to update DMA_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_DATA_WIDTH { PARAM_VALUE.DMA_DATA_WIDTH } { + # Procedure called to validate DMA_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.DMA_READY_ENABLE { PARAM_VALUE.DMA_READY_ENABLE } { + # Procedure called to update DMA_READY_ENABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_READY_ENABLE { PARAM_VALUE.DMA_READY_ENABLE } { + # Procedure called to validate DMA_READY_ENABLE + return true +} + + +proc update_MODELPARAM_VALUE.ADC_DATA_WIDTH { MODELPARAM_VALUE.ADC_DATA_WIDTH PARAM_VALUE.ADC_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ADC_DATA_WIDTH}] ${MODELPARAM_VALUE.ADC_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.DMA_DATA_WIDTH { MODELPARAM_VALUE.DMA_DATA_WIDTH PARAM_VALUE.DMA_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_DATA_WIDTH}] ${MODELPARAM_VALUE.DMA_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.AXI_DATA_WIDTH { MODELPARAM_VALUE.AXI_DATA_WIDTH PARAM_VALUE.AXI_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.AXI_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.DMA_READY_ENABLE { MODELPARAM_VALUE.DMA_READY_ENABLE PARAM_VALUE.DMA_READY_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_READY_ENABLE}] ${MODELPARAM_VALUE.DMA_READY_ENABLE} +} + +proc update_MODELPARAM_VALUE.AXI_SIZE { MODELPARAM_VALUE.AXI_SIZE PARAM_VALUE.AXI_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_SIZE}] ${MODELPARAM_VALUE.AXI_SIZE} +} + +proc update_MODELPARAM_VALUE.AXI_LENGTH { MODELPARAM_VALUE.AXI_LENGTH PARAM_VALUE.AXI_LENGTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_LENGTH}] ${MODELPARAM_VALUE.AXI_LENGTH} +} + +proc update_MODELPARAM_VALUE.AXI_ADDRESS { MODELPARAM_VALUE.AXI_ADDRESS PARAM_VALUE.AXI_ADDRESS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_ADDRESS}] ${MODELPARAM_VALUE.AXI_ADDRESS} +} + +proc update_MODELPARAM_VALUE.AXI_ADDRESS_LIMIT { MODELPARAM_VALUE.AXI_ADDRESS_LIMIT PARAM_VALUE.AXI_ADDRESS_LIMIT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_ADDRESS_LIMIT}] ${MODELPARAM_VALUE.AXI_ADDRESS_LIMIT} +} + diff --git a/adi_library/xilinx/axi_adxcvr/Makefile b/adi_library/xilinx/axi_adxcvr/Makefile new file mode 100644 index 00000000..183ca9bf --- /dev/null +++ b/adi_library/xilinx/axi_adxcvr/Makefile @@ -0,0 +1,24 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_adxcvr + +XILINX_DEPS += ../../common/up_axi.v +XILINX_DEPS += axi_adxcvr.v +XILINX_DEPS += axi_adxcvr_es.v +XILINX_DEPS += axi_adxcvr_ip.tcl +XILINX_DEPS += axi_adxcvr_mdrp.v +XILINX_DEPS += axi_adxcvr_mstatus.v +XILINX_DEPS += axi_adxcvr_up.v + +XILINX_DEPS += ../../interfaces/if_xcvr_ch.xml +XILINX_DEPS += ../../interfaces/if_xcvr_ch_rtl.xml +XILINX_DEPS += ../../interfaces/if_xcvr_cm.xml +XILINX_DEPS += ../../interfaces/if_xcvr_cm_rtl.xml + +XILINX_INTERFACE_DEPS += interfaces + +include ../../scripts/library.mk diff --git a/adi_library/xilinx/axi_adxcvr/axi_adxcvr.v b/adi_library/xilinx/axi_adxcvr/axi_adxcvr.v new file mode 100644 index 00000000..58ca8409 --- /dev/null +++ b/adi_library/xilinx/axi_adxcvr/axi_adxcvr.v @@ -0,0 +1,4347 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// AUTO GENERATED BY axi_adxcvr.pl, DO NOT MODIFY! + +`timescale 1ns/1ps + +module axi_adxcvr #( + + // parameters + + parameter integer ID = 0, + parameter integer NUM_OF_LANES = 8, + parameter integer XCVR_TYPE = 0, + parameter integer LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B + parameter FPGA_TECHNOLOGY = 0, + parameter FPGA_FAMILY = 0, + parameter SPEED_GRADE = 0, + parameter DEV_PACKAGE = 0, + parameter [15:0] FPGA_VOLTAGE = 0, + parameter integer TX_OR_RX_N = 0, + parameter integer QPLL_ENABLE = 1, + parameter LPM_OR_DFE_N = 1, + parameter [ 2:0] RATE = 3'd0, + parameter [ 4:0] TX_DIFFCTRL = 5'd8, + parameter [ 4:0] TX_POSTCURSOR = 5'd0, + parameter [ 4:0] TX_PRECURSOR = 5'd0, + parameter [ 1:0] SYS_CLK_SEL = 2'd3, + parameter [ 2:0] OUT_CLK_SEL = 3'd4 +) ( + output up_cm_enb_0, + output [11:0] up_cm_addr_0, + output up_cm_wr_0, + output [15:0] up_cm_wdata_0, + input [15:0] up_cm_rdata_0, + input up_cm_ready_0, + + output up_es_enb_0, + output [11:0] up_es_addr_0, + output up_es_wr_0, + output up_es_reset_0, + output [15:0] up_es_wdata_0, + input [15:0] up_es_rdata_0, + input up_es_ready_0, + + input up_ch_pll_locked_0, + output up_ch_rst_0, + output up_ch_user_ready_0, + input up_ch_rst_done_0, + output up_ch_prbsforceerr_0, + output [ 3:0] up_ch_prbssel_0, + output up_ch_prbscntreset_0, + input up_ch_prbserr_0, + input up_ch_prbslocked_0, + input [ 1:0] up_ch_bufstatus_0, + output up_ch_bufstatus_rst_0, + output up_ch_lpm_dfe_n_0, + output [ 2:0] up_ch_rate_0, + output [ 1:0] up_ch_sys_clk_sel_0, + output [ 2:0] up_ch_out_clk_sel_0, + output [ 4:0] up_ch_tx_diffctrl_0, + output [ 4:0] up_ch_tx_postcursor_0, + output [ 4:0] up_ch_tx_precursor_0, + output up_ch_enb_0, + output [11:0] up_ch_addr_0, + output up_ch_wr_0, + output [15:0] up_ch_wdata_0, + input [15:0] up_ch_rdata_0, + input up_ch_ready_0, + + output up_es_enb_1, + output [11:0] up_es_addr_1, + output up_es_wr_1, + output up_es_reset_1, + output [15:0] up_es_wdata_1, + input [15:0] up_es_rdata_1, + input up_es_ready_1, + + input up_ch_pll_locked_1, + output up_ch_rst_1, + output up_ch_user_ready_1, + input up_ch_rst_done_1, + output up_ch_prbsforceerr_1, + output [ 3:0] up_ch_prbssel_1, + output up_ch_prbscntreset_1, + input up_ch_prbserr_1, + input up_ch_prbslocked_1, + input [ 1:0] up_ch_bufstatus_1, + output up_ch_bufstatus_rst_1, + output up_ch_lpm_dfe_n_1, + output [ 2:0] up_ch_rate_1, + output [ 1:0] up_ch_sys_clk_sel_1, + output [ 2:0] up_ch_out_clk_sel_1, + output [ 4:0] up_ch_tx_diffctrl_1, + output [ 4:0] up_ch_tx_postcursor_1, + output [ 4:0] up_ch_tx_precursor_1, + output up_ch_enb_1, + output [11:0] up_ch_addr_1, + output up_ch_wr_1, + output [15:0] up_ch_wdata_1, + input [15:0] up_ch_rdata_1, + input up_ch_ready_1, + + output up_es_enb_2, + output [11:0] up_es_addr_2, + output up_es_wr_2, + output up_es_reset_2, + output [15:0] up_es_wdata_2, + input [15:0] up_es_rdata_2, + input up_es_ready_2, + + input up_ch_pll_locked_2, + output up_ch_rst_2, + output up_ch_user_ready_2, + input up_ch_rst_done_2, + output up_ch_prbsforceerr_2, + output [ 3:0] up_ch_prbssel_2, + output up_ch_prbscntreset_2, + input up_ch_prbserr_2, + input up_ch_prbslocked_2, + input [ 1:0] up_ch_bufstatus_2, + output up_ch_bufstatus_rst_2, + output up_ch_lpm_dfe_n_2, + output [ 2:0] up_ch_rate_2, + output [ 1:0] up_ch_sys_clk_sel_2, + output [ 2:0] up_ch_out_clk_sel_2, + output [ 4:0] up_ch_tx_diffctrl_2, + output [ 4:0] up_ch_tx_postcursor_2, + output [ 4:0] up_ch_tx_precursor_2, + output up_ch_enb_2, + output [11:0] up_ch_addr_2, + output up_ch_wr_2, + output [15:0] up_ch_wdata_2, + input [15:0] up_ch_rdata_2, + input up_ch_ready_2, + + output up_es_enb_3, + output [11:0] up_es_addr_3, + output up_es_wr_3, + output up_es_reset_3, + output [15:0] up_es_wdata_3, + input [15:0] up_es_rdata_3, + input up_es_ready_3, + + input up_ch_pll_locked_3, + output up_ch_rst_3, + output up_ch_user_ready_3, + input up_ch_rst_done_3, + output up_ch_prbsforceerr_3, + output [ 3:0] up_ch_prbssel_3, + output up_ch_prbscntreset_3, + input up_ch_prbserr_3, + input up_ch_prbslocked_3, + input [ 1:0] up_ch_bufstatus_3, + output up_ch_bufstatus_rst_3, + output up_ch_lpm_dfe_n_3, + output [ 2:0] up_ch_rate_3, + output [ 1:0] up_ch_sys_clk_sel_3, + output [ 2:0] up_ch_out_clk_sel_3, + output [ 4:0] up_ch_tx_diffctrl_3, + output [ 4:0] up_ch_tx_postcursor_3, + output [ 4:0] up_ch_tx_precursor_3, + output up_ch_enb_3, + output [11:0] up_ch_addr_3, + output up_ch_wr_3, + output [15:0] up_ch_wdata_3, + input [15:0] up_ch_rdata_3, + input up_ch_ready_3, + + output up_cm_enb_4, + output [11:0] up_cm_addr_4, + output up_cm_wr_4, + output [15:0] up_cm_wdata_4, + input [15:0] up_cm_rdata_4, + input up_cm_ready_4, + + output up_es_enb_4, + output [11:0] up_es_addr_4, + output up_es_wr_4, + output up_es_reset_4, + output [15:0] up_es_wdata_4, + input [15:0] up_es_rdata_4, + input up_es_ready_4, + + input up_ch_pll_locked_4, + output up_ch_rst_4, + output up_ch_user_ready_4, + input up_ch_rst_done_4, + output up_ch_prbsforceerr_4, + output [ 3:0] up_ch_prbssel_4, + output up_ch_prbscntreset_4, + input up_ch_prbserr_4, + input up_ch_prbslocked_4, + input [ 1:0] up_ch_bufstatus_4, + output up_ch_bufstatus_rst_4, + output up_ch_lpm_dfe_n_4, + output [ 2:0] up_ch_rate_4, + output [ 1:0] up_ch_sys_clk_sel_4, + output [ 2:0] up_ch_out_clk_sel_4, + output [ 4:0] up_ch_tx_diffctrl_4, + output [ 4:0] up_ch_tx_postcursor_4, + output [ 4:0] up_ch_tx_precursor_4, + output up_ch_enb_4, + output [11:0] up_ch_addr_4, + output up_ch_wr_4, + output [15:0] up_ch_wdata_4, + input [15:0] up_ch_rdata_4, + input up_ch_ready_4, + + output up_es_enb_5, + output [11:0] up_es_addr_5, + output up_es_wr_5, + output up_es_reset_5, + output [15:0] up_es_wdata_5, + input [15:0] up_es_rdata_5, + input up_es_ready_5, + + input up_ch_pll_locked_5, + output up_ch_rst_5, + output up_ch_user_ready_5, + input up_ch_rst_done_5, + output up_ch_prbsforceerr_5, + output [ 3:0] up_ch_prbssel_5, + output up_ch_prbscntreset_5, + input up_ch_prbserr_5, + input up_ch_prbslocked_5, + input [ 1:0] up_ch_bufstatus_5, + output up_ch_bufstatus_rst_5, + output up_ch_lpm_dfe_n_5, + output [ 2:0] up_ch_rate_5, + output [ 1:0] up_ch_sys_clk_sel_5, + output [ 2:0] up_ch_out_clk_sel_5, + output [ 4:0] up_ch_tx_diffctrl_5, + output [ 4:0] up_ch_tx_postcursor_5, + output [ 4:0] up_ch_tx_precursor_5, + output up_ch_enb_5, + output [11:0] up_ch_addr_5, + output up_ch_wr_5, + output [15:0] up_ch_wdata_5, + input [15:0] up_ch_rdata_5, + input up_ch_ready_5, + + output up_es_enb_6, + output [11:0] up_es_addr_6, + output up_es_wr_6, + output up_es_reset_6, + output [15:0] up_es_wdata_6, + input [15:0] up_es_rdata_6, + input up_es_ready_6, + + input up_ch_pll_locked_6, + output up_ch_rst_6, + output up_ch_user_ready_6, + input up_ch_rst_done_6, + output up_ch_prbsforceerr_6, + output [ 3:0] up_ch_prbssel_6, + output up_ch_prbscntreset_6, + input up_ch_prbserr_6, + input up_ch_prbslocked_6, + input [ 1:0] up_ch_bufstatus_6, + output up_ch_bufstatus_rst_6, + output up_ch_lpm_dfe_n_6, + output [ 2:0] up_ch_rate_6, + output [ 1:0] up_ch_sys_clk_sel_6, + output [ 2:0] up_ch_out_clk_sel_6, + output [ 4:0] up_ch_tx_diffctrl_6, + output [ 4:0] up_ch_tx_postcursor_6, + output [ 4:0] up_ch_tx_precursor_6, + output up_ch_enb_6, + output [11:0] up_ch_addr_6, + output up_ch_wr_6, + output [15:0] up_ch_wdata_6, + input [15:0] up_ch_rdata_6, + input up_ch_ready_6, + + output up_es_enb_7, + output [11:0] up_es_addr_7, + output up_es_wr_7, + output up_es_reset_7, + output [15:0] up_es_wdata_7, + input [15:0] up_es_rdata_7, + input up_es_ready_7, + + input up_ch_pll_locked_7, + output up_ch_rst_7, + output up_ch_user_ready_7, + input up_ch_rst_done_7, + output up_ch_prbsforceerr_7, + output [ 3:0] up_ch_prbssel_7, + output up_ch_prbscntreset_7, + input up_ch_prbserr_7, + input up_ch_prbslocked_7, + input [ 1:0] up_ch_bufstatus_7, + output up_ch_bufstatus_rst_7, + output up_ch_lpm_dfe_n_7, + output [ 2:0] up_ch_rate_7, + output [ 1:0] up_ch_sys_clk_sel_7, + output [ 2:0] up_ch_out_clk_sel_7, + output [ 4:0] up_ch_tx_diffctrl_7, + output [ 4:0] up_ch_tx_postcursor_7, + output [ 4:0] up_ch_tx_precursor_7, + output up_ch_enb_7, + output [11:0] up_ch_addr_7, + output up_ch_wr_7, + output [15:0] up_ch_wdata_7, + input [15:0] up_ch_rdata_7, + input up_ch_ready_7, + + output up_cm_enb_8, + output [11:0] up_cm_addr_8, + output up_cm_wr_8, + output [15:0] up_cm_wdata_8, + input [15:0] up_cm_rdata_8, + input up_cm_ready_8, + + output up_es_enb_8, + output [11:0] up_es_addr_8, + output up_es_wr_8, + output up_es_reset_8, + output [15:0] up_es_wdata_8, + input [15:0] up_es_rdata_8, + input up_es_ready_8, + + input up_ch_pll_locked_8, + output up_ch_rst_8, + output up_ch_user_ready_8, + input up_ch_rst_done_8, + output up_ch_prbsforceerr_8, + output [ 3:0] up_ch_prbssel_8, + output up_ch_prbscntreset_8, + input up_ch_prbserr_8, + input up_ch_prbslocked_8, + input [ 1:0] up_ch_bufstatus_8, + output up_ch_bufstatus_rst_8, + output up_ch_lpm_dfe_n_8, + output [ 2:0] up_ch_rate_8, + output [ 1:0] up_ch_sys_clk_sel_8, + output [ 2:0] up_ch_out_clk_sel_8, + output [ 4:0] up_ch_tx_diffctrl_8, + output [ 4:0] up_ch_tx_postcursor_8, + output [ 4:0] up_ch_tx_precursor_8, + output up_ch_enb_8, + output [11:0] up_ch_addr_8, + output up_ch_wr_8, + output [15:0] up_ch_wdata_8, + input [15:0] up_ch_rdata_8, + input up_ch_ready_8, + + output up_es_enb_9, + output [11:0] up_es_addr_9, + output up_es_wr_9, + output up_es_reset_9, + output [15:0] up_es_wdata_9, + input [15:0] up_es_rdata_9, + input up_es_ready_9, + + input up_ch_pll_locked_9, + output up_ch_rst_9, + output up_ch_user_ready_9, + input up_ch_rst_done_9, + output up_ch_prbsforceerr_9, + output [ 3:0] up_ch_prbssel_9, + output up_ch_prbscntreset_9, + input up_ch_prbserr_9, + input up_ch_prbslocked_9, + input [ 1:0] up_ch_bufstatus_9, + output up_ch_bufstatus_rst_9, + output up_ch_lpm_dfe_n_9, + output [ 2:0] up_ch_rate_9, + output [ 1:0] up_ch_sys_clk_sel_9, + output [ 2:0] up_ch_out_clk_sel_9, + output [ 4:0] up_ch_tx_diffctrl_9, + output [ 4:0] up_ch_tx_postcursor_9, + output [ 4:0] up_ch_tx_precursor_9, + output up_ch_enb_9, + output [11:0] up_ch_addr_9, + output up_ch_wr_9, + output [15:0] up_ch_wdata_9, + input [15:0] up_ch_rdata_9, + input up_ch_ready_9, + + output up_es_enb_10, + output [11:0] up_es_addr_10, + output up_es_wr_10, + output up_es_reset_10, + output [15:0] up_es_wdata_10, + input [15:0] up_es_rdata_10, + input up_es_ready_10, + + input up_ch_pll_locked_10, + output up_ch_rst_10, + output up_ch_user_ready_10, + input up_ch_rst_done_10, + output up_ch_prbsforceerr_10, + output [ 3:0] up_ch_prbssel_10, + output up_ch_prbscntreset_10, + input up_ch_prbserr_10, + input up_ch_prbslocked_10, + input [ 1:0] up_ch_bufstatus_10, + output up_ch_bufstatus_rst_10, + output up_ch_lpm_dfe_n_10, + output [ 2:0] up_ch_rate_10, + output [ 1:0] up_ch_sys_clk_sel_10, + output [ 2:0] up_ch_out_clk_sel_10, + output [ 4:0] up_ch_tx_diffctrl_10, + output [ 4:0] up_ch_tx_postcursor_10, + output [ 4:0] up_ch_tx_precursor_10, + output up_ch_enb_10, + output [11:0] up_ch_addr_10, + output up_ch_wr_10, + output [15:0] up_ch_wdata_10, + input [15:0] up_ch_rdata_10, + input up_ch_ready_10, + + output up_es_enb_11, + output [11:0] up_es_addr_11, + output up_es_wr_11, + output up_es_reset_11, + output [15:0] up_es_wdata_11, + input [15:0] up_es_rdata_11, + input up_es_ready_11, + + input up_ch_pll_locked_11, + output up_ch_rst_11, + output up_ch_user_ready_11, + input up_ch_rst_done_11, + output up_ch_prbsforceerr_11, + output [ 3:0] up_ch_prbssel_11, + output up_ch_prbscntreset_11, + input up_ch_prbserr_11, + input up_ch_prbslocked_11, + input [ 1:0] up_ch_bufstatus_11, + output up_ch_bufstatus_rst_11, + output up_ch_lpm_dfe_n_11, + output [ 2:0] up_ch_rate_11, + output [ 1:0] up_ch_sys_clk_sel_11, + output [ 2:0] up_ch_out_clk_sel_11, + output [ 4:0] up_ch_tx_diffctrl_11, + output [ 4:0] up_ch_tx_postcursor_11, + output [ 4:0] up_ch_tx_precursor_11, + output up_ch_enb_11, + output [11:0] up_ch_addr_11, + output up_ch_wr_11, + output [15:0] up_ch_wdata_11, + input [15:0] up_ch_rdata_11, + input up_ch_ready_11, + + output up_cm_enb_12, + output [11:0] up_cm_addr_12, + output up_cm_wr_12, + output [15:0] up_cm_wdata_12, + input [15:0] up_cm_rdata_12, + input up_cm_ready_12, + + output up_es_enb_12, + output [11:0] up_es_addr_12, + output up_es_wr_12, + output up_es_reset_12, + output [15:0] up_es_wdata_12, + input [15:0] up_es_rdata_12, + input up_es_ready_12, + + input up_ch_pll_locked_12, + output up_ch_rst_12, + output up_ch_user_ready_12, + input up_ch_rst_done_12, + output up_ch_prbsforceerr_12, + output [ 3:0] up_ch_prbssel_12, + output up_ch_prbscntreset_12, + input up_ch_prbserr_12, + input up_ch_prbslocked_12, + input [ 1:0] up_ch_bufstatus_12, + output up_ch_bufstatus_rst_12, + output up_ch_lpm_dfe_n_12, + output [ 2:0] up_ch_rate_12, + output [ 1:0] up_ch_sys_clk_sel_12, + output [ 2:0] up_ch_out_clk_sel_12, + output [ 4:0] up_ch_tx_diffctrl_12, + output [ 4:0] up_ch_tx_postcursor_12, + output [ 4:0] up_ch_tx_precursor_12, + output up_ch_enb_12, + output [11:0] up_ch_addr_12, + output up_ch_wr_12, + output [15:0] up_ch_wdata_12, + input [15:0] up_ch_rdata_12, + input up_ch_ready_12, + + output up_es_enb_13, + output [11:0] up_es_addr_13, + output up_es_wr_13, + output up_es_reset_13, + output [15:0] up_es_wdata_13, + input [15:0] up_es_rdata_13, + input up_es_ready_13, + + input up_ch_pll_locked_13, + output up_ch_rst_13, + output up_ch_user_ready_13, + input up_ch_rst_done_13, + output up_ch_prbsforceerr_13, + output [ 3:0] up_ch_prbssel_13, + output up_ch_prbscntreset_13, + input up_ch_prbserr_13, + input up_ch_prbslocked_13, + input [ 1:0] up_ch_bufstatus_13, + output up_ch_bufstatus_rst_13, + output up_ch_lpm_dfe_n_13, + output [ 2:0] up_ch_rate_13, + output [ 1:0] up_ch_sys_clk_sel_13, + output [ 2:0] up_ch_out_clk_sel_13, + output [ 4:0] up_ch_tx_diffctrl_13, + output [ 4:0] up_ch_tx_postcursor_13, + output [ 4:0] up_ch_tx_precursor_13, + output up_ch_enb_13, + output [11:0] up_ch_addr_13, + output up_ch_wr_13, + output [15:0] up_ch_wdata_13, + input [15:0] up_ch_rdata_13, + input up_ch_ready_13, + + output up_es_enb_14, + output [11:0] up_es_addr_14, + output up_es_wr_14, + output up_es_reset_14, + output [15:0] up_es_wdata_14, + input [15:0] up_es_rdata_14, + input up_es_ready_14, + + input up_ch_pll_locked_14, + output up_ch_rst_14, + output up_ch_user_ready_14, + input up_ch_rst_done_14, + output up_ch_prbsforceerr_14, + output [ 3:0] up_ch_prbssel_14, + output up_ch_prbscntreset_14, + input up_ch_prbserr_14, + input up_ch_prbslocked_14, + input [ 1:0] up_ch_bufstatus_14, + output up_ch_bufstatus_rst_14, + output up_ch_lpm_dfe_n_14, + output [ 2:0] up_ch_rate_14, + output [ 1:0] up_ch_sys_clk_sel_14, + output [ 2:0] up_ch_out_clk_sel_14, + output [ 4:0] up_ch_tx_diffctrl_14, + output [ 4:0] up_ch_tx_postcursor_14, + output [ 4:0] up_ch_tx_precursor_14, + output up_ch_enb_14, + output [11:0] up_ch_addr_14, + output up_ch_wr_14, + output [15:0] up_ch_wdata_14, + input [15:0] up_ch_rdata_14, + input up_ch_ready_14, + + output up_es_enb_15, + output [11:0] up_es_addr_15, + output up_es_wr_15, + output up_es_reset_15, + output [15:0] up_es_wdata_15, + input [15:0] up_es_rdata_15, + input up_es_ready_15, + + input up_ch_pll_locked_15, + output up_ch_rst_15, + output up_ch_user_ready_15, + input up_ch_rst_done_15, + output up_ch_prbsforceerr_15, + output [ 3:0] up_ch_prbssel_15, + output up_ch_prbscntreset_15, + input up_ch_prbserr_15, + input up_ch_prbslocked_15, + input [ 1:0] up_ch_bufstatus_15, + output up_ch_bufstatus_rst_15, + output up_ch_lpm_dfe_n_15, + output [ 2:0] up_ch_rate_15, + output [ 1:0] up_ch_sys_clk_sel_15, + output [ 2:0] up_ch_out_clk_sel_15, + output [ 4:0] up_ch_tx_diffctrl_15, + output [ 4:0] up_ch_tx_postcursor_15, + output [ 4:0] up_ch_tx_precursor_15, + output up_ch_enb_15, + output [11:0] up_ch_addr_15, + output up_ch_wr_15, + output [15:0] up_ch_wdata_15, + input [15:0] up_ch_rdata_15, + input up_ch_ready_15, + + output up_cm_enb_16, + output [11:0] up_cm_addr_16, + output up_cm_wr_16, + output [15:0] up_cm_wdata_16, + input [15:0] up_cm_rdata_16, + input up_cm_ready_16, + + output up_es_enb_16, + output [11:0] up_es_addr_16, + output up_es_wr_16, + output up_es_reset_16, + output [15:0] up_es_wdata_16, + input [15:0] up_es_rdata_16, + input up_es_ready_16, + + input up_ch_pll_locked_16, + output up_ch_rst_16, + output up_ch_user_ready_16, + input up_ch_rst_done_16, + output up_ch_prbsforceerr_16, + output [ 3:0] up_ch_prbssel_16, + output up_ch_prbscntreset_16, + input up_ch_prbserr_16, + input up_ch_prbslocked_16, + input [ 1:0] up_ch_bufstatus_16, + output up_ch_bufstatus_rst_16, + output up_ch_lpm_dfe_n_16, + output [ 2:0] up_ch_rate_16, + output [ 1:0] up_ch_sys_clk_sel_16, + output [ 2:0] up_ch_out_clk_sel_16, + output [ 4:0] up_ch_tx_diffctrl_16, + output [ 4:0] up_ch_tx_postcursor_16, + output [ 4:0] up_ch_tx_precursor_16, + output up_ch_enb_16, + output [11:0] up_ch_addr_16, + output up_ch_wr_16, + output [15:0] up_ch_wdata_16, + input [15:0] up_ch_rdata_16, + input up_ch_ready_16, + + output up_es_enb_17, + output [11:0] up_es_addr_17, + output up_es_wr_17, + output up_es_reset_17, + output [15:0] up_es_wdata_17, + input [15:0] up_es_rdata_17, + input up_es_ready_17, + + input up_ch_pll_locked_17, + output up_ch_rst_17, + output up_ch_user_ready_17, + input up_ch_rst_done_17, + output up_ch_prbsforceerr_17, + output [ 3:0] up_ch_prbssel_17, + output up_ch_prbscntreset_17, + input up_ch_prbserr_17, + input up_ch_prbslocked_17, + input [ 1:0] up_ch_bufstatus_17, + output up_ch_bufstatus_rst_17, + output up_ch_lpm_dfe_n_17, + output [ 2:0] up_ch_rate_17, + output [ 1:0] up_ch_sys_clk_sel_17, + output [ 2:0] up_ch_out_clk_sel_17, + output [ 4:0] up_ch_tx_diffctrl_17, + output [ 4:0] up_ch_tx_postcursor_17, + output [ 4:0] up_ch_tx_precursor_17, + output up_ch_enb_17, + output [11:0] up_ch_addr_17, + output up_ch_wr_17, + output [15:0] up_ch_wdata_17, + input [15:0] up_ch_rdata_17, + input up_ch_ready_17, + + output up_es_enb_18, + output [11:0] up_es_addr_18, + output up_es_wr_18, + output up_es_reset_18, + output [15:0] up_es_wdata_18, + input [15:0] up_es_rdata_18, + input up_es_ready_18, + + input up_ch_pll_locked_18, + output up_ch_rst_18, + output up_ch_user_ready_18, + input up_ch_rst_done_18, + output up_ch_prbsforceerr_18, + output [ 3:0] up_ch_prbssel_18, + output up_ch_prbscntreset_18, + input up_ch_prbserr_18, + input up_ch_prbslocked_18, + input [ 1:0] up_ch_bufstatus_18, + output up_ch_bufstatus_rst_18, + output up_ch_lpm_dfe_n_18, + output [ 2:0] up_ch_rate_18, + output [ 1:0] up_ch_sys_clk_sel_18, + output [ 2:0] up_ch_out_clk_sel_18, + output [ 4:0] up_ch_tx_diffctrl_18, + output [ 4:0] up_ch_tx_postcursor_18, + output [ 4:0] up_ch_tx_precursor_18, + output up_ch_enb_18, + output [11:0] up_ch_addr_18, + output up_ch_wr_18, + output [15:0] up_ch_wdata_18, + input [15:0] up_ch_rdata_18, + input up_ch_ready_18, + + output up_es_enb_19, + output [11:0] up_es_addr_19, + output up_es_wr_19, + output up_es_reset_19, + output [15:0] up_es_wdata_19, + input [15:0] up_es_rdata_19, + input up_es_ready_19, + + input up_ch_pll_locked_19, + output up_ch_rst_19, + output up_ch_user_ready_19, + input up_ch_rst_done_19, + output up_ch_prbsforceerr_19, + output [ 3:0] up_ch_prbssel_19, + output up_ch_prbscntreset_19, + input up_ch_prbserr_19, + input up_ch_prbslocked_19, + input [ 1:0] up_ch_bufstatus_19, + output up_ch_bufstatus_rst_19, + output up_ch_lpm_dfe_n_19, + output [ 2:0] up_ch_rate_19, + output [ 1:0] up_ch_sys_clk_sel_19, + output [ 2:0] up_ch_out_clk_sel_19, + output [ 4:0] up_ch_tx_diffctrl_19, + output [ 4:0] up_ch_tx_postcursor_19, + output [ 4:0] up_ch_tx_precursor_19, + output up_ch_enb_19, + output [11:0] up_ch_addr_19, + output up_ch_wr_19, + output [15:0] up_ch_wdata_19, + input [15:0] up_ch_rdata_19, + input up_ch_ready_19, + + output up_cm_enb_20, + output [11:0] up_cm_addr_20, + output up_cm_wr_20, + output [15:0] up_cm_wdata_20, + input [15:0] up_cm_rdata_20, + input up_cm_ready_20, + + output up_es_enb_20, + output [11:0] up_es_addr_20, + output up_es_wr_20, + output up_es_reset_20, + output [15:0] up_es_wdata_20, + input [15:0] up_es_rdata_20, + input up_es_ready_20, + + input up_ch_pll_locked_20, + output up_ch_rst_20, + output up_ch_user_ready_20, + input up_ch_rst_done_20, + output up_ch_prbsforceerr_20, + output [ 3:0] up_ch_prbssel_20, + output up_ch_prbscntreset_20, + input up_ch_prbserr_20, + input up_ch_prbslocked_20, + input [ 1:0] up_ch_bufstatus_20, + output up_ch_bufstatus_rst_20, + output up_ch_lpm_dfe_n_20, + output [ 2:0] up_ch_rate_20, + output [ 1:0] up_ch_sys_clk_sel_20, + output [ 2:0] up_ch_out_clk_sel_20, + output [ 4:0] up_ch_tx_diffctrl_20, + output [ 4:0] up_ch_tx_postcursor_20, + output [ 4:0] up_ch_tx_precursor_20, + output up_ch_enb_20, + output [11:0] up_ch_addr_20, + output up_ch_wr_20, + output [15:0] up_ch_wdata_20, + input [15:0] up_ch_rdata_20, + input up_ch_ready_20, + + output up_es_enb_21, + output [11:0] up_es_addr_21, + output up_es_wr_21, + output up_es_reset_21, + output [15:0] up_es_wdata_21, + input [15:0] up_es_rdata_21, + input up_es_ready_21, + + input up_ch_pll_locked_21, + output up_ch_rst_21, + output up_ch_user_ready_21, + input up_ch_rst_done_21, + output up_ch_prbsforceerr_21, + output [ 3:0] up_ch_prbssel_21, + output up_ch_prbscntreset_21, + input up_ch_prbserr_21, + input up_ch_prbslocked_21, + input [ 1:0] up_ch_bufstatus_21, + output up_ch_bufstatus_rst_21, + output up_ch_lpm_dfe_n_21, + output [ 2:0] up_ch_rate_21, + output [ 1:0] up_ch_sys_clk_sel_21, + output [ 2:0] up_ch_out_clk_sel_21, + output [ 4:0] up_ch_tx_diffctrl_21, + output [ 4:0] up_ch_tx_postcursor_21, + output [ 4:0] up_ch_tx_precursor_21, + output up_ch_enb_21, + output [11:0] up_ch_addr_21, + output up_ch_wr_21, + output [15:0] up_ch_wdata_21, + input [15:0] up_ch_rdata_21, + input up_ch_ready_21, + + output up_es_enb_22, + output [11:0] up_es_addr_22, + output up_es_wr_22, + output up_es_reset_22, + output [15:0] up_es_wdata_22, + input [15:0] up_es_rdata_22, + input up_es_ready_22, + + input up_ch_pll_locked_22, + output up_ch_rst_22, + output up_ch_user_ready_22, + input up_ch_rst_done_22, + output up_ch_prbsforceerr_22, + output [ 3:0] up_ch_prbssel_22, + output up_ch_prbscntreset_22, + input up_ch_prbserr_22, + input up_ch_prbslocked_22, + input [ 1:0] up_ch_bufstatus_22, + output up_ch_bufstatus_rst_22, + output up_ch_lpm_dfe_n_22, + output [ 2:0] up_ch_rate_22, + output [ 1:0] up_ch_sys_clk_sel_22, + output [ 2:0] up_ch_out_clk_sel_22, + output [ 4:0] up_ch_tx_diffctrl_22, + output [ 4:0] up_ch_tx_postcursor_22, + output [ 4:0] up_ch_tx_precursor_22, + output up_ch_enb_22, + output [11:0] up_ch_addr_22, + output up_ch_wr_22, + output [15:0] up_ch_wdata_22, + input [15:0] up_ch_rdata_22, + input up_ch_ready_22, + + output up_es_enb_23, + output [11:0] up_es_addr_23, + output up_es_wr_23, + output up_es_reset_23, + output [15:0] up_es_wdata_23, + input [15:0] up_es_rdata_23, + input up_es_ready_23, + + input up_ch_pll_locked_23, + output up_ch_rst_23, + output up_ch_user_ready_23, + input up_ch_rst_done_23, + output up_ch_prbsforceerr_23, + output [ 3:0] up_ch_prbssel_23, + output up_ch_prbscntreset_23, + input up_ch_prbserr_23, + input up_ch_prbslocked_23, + input [ 1:0] up_ch_bufstatus_23, + output up_ch_bufstatus_rst_23, + output up_ch_lpm_dfe_n_23, + output [ 2:0] up_ch_rate_23, + output [ 1:0] up_ch_sys_clk_sel_23, + output [ 2:0] up_ch_out_clk_sel_23, + output [ 4:0] up_ch_tx_diffctrl_23, + output [ 4:0] up_ch_tx_postcursor_23, + output [ 4:0] up_ch_tx_precursor_23, + output up_ch_enb_23, + output [11:0] up_ch_addr_23, + output up_ch_wr_23, + output [15:0] up_ch_wdata_23, + input [15:0] up_ch_rdata_23, + input up_ch_ready_23, + + output up_cm_enb_24, + output [11:0] up_cm_addr_24, + output up_cm_wr_24, + output [15:0] up_cm_wdata_24, + input [15:0] up_cm_rdata_24, + input up_cm_ready_24, + + output up_es_enb_24, + output [11:0] up_es_addr_24, + output up_es_wr_24, + output up_es_reset_24, + output [15:0] up_es_wdata_24, + input [15:0] up_es_rdata_24, + input up_es_ready_24, + + input up_ch_pll_locked_24, + output up_ch_rst_24, + output up_ch_user_ready_24, + input up_ch_rst_done_24, + output up_ch_prbsforceerr_24, + output [ 3:0] up_ch_prbssel_24, + output up_ch_prbscntreset_24, + input up_ch_prbserr_24, + input up_ch_prbslocked_24, + input [ 1:0] up_ch_bufstatus_24, + output up_ch_bufstatus_rst_24, + output up_ch_lpm_dfe_n_24, + output [ 2:0] up_ch_rate_24, + output [ 1:0] up_ch_sys_clk_sel_24, + output [ 2:0] up_ch_out_clk_sel_24, + output [ 4:0] up_ch_tx_diffctrl_24, + output [ 4:0] up_ch_tx_postcursor_24, + output [ 4:0] up_ch_tx_precursor_24, + output up_ch_enb_24, + output [11:0] up_ch_addr_24, + output up_ch_wr_24, + output [15:0] up_ch_wdata_24, + input [15:0] up_ch_rdata_24, + input up_ch_ready_24, + + output up_es_enb_25, + output [11:0] up_es_addr_25, + output up_es_wr_25, + output up_es_reset_25, + output [15:0] up_es_wdata_25, + input [15:0] up_es_rdata_25, + input up_es_ready_25, + + input up_ch_pll_locked_25, + output up_ch_rst_25, + output up_ch_user_ready_25, + input up_ch_rst_done_25, + output up_ch_prbsforceerr_25, + output [ 3:0] up_ch_prbssel_25, + output up_ch_prbscntreset_25, + input up_ch_prbserr_25, + input up_ch_prbslocked_25, + input [ 1:0] up_ch_bufstatus_25, + output up_ch_bufstatus_rst_25, + output up_ch_lpm_dfe_n_25, + output [ 2:0] up_ch_rate_25, + output [ 1:0] up_ch_sys_clk_sel_25, + output [ 2:0] up_ch_out_clk_sel_25, + output [ 4:0] up_ch_tx_diffctrl_25, + output [ 4:0] up_ch_tx_postcursor_25, + output [ 4:0] up_ch_tx_precursor_25, + output up_ch_enb_25, + output [11:0] up_ch_addr_25, + output up_ch_wr_25, + output [15:0] up_ch_wdata_25, + input [15:0] up_ch_rdata_25, + input up_ch_ready_25, + + output up_es_enb_26, + output [11:0] up_es_addr_26, + output up_es_wr_26, + output up_es_reset_26, + output [15:0] up_es_wdata_26, + input [15:0] up_es_rdata_26, + input up_es_ready_26, + + input up_ch_pll_locked_26, + output up_ch_rst_26, + output up_ch_user_ready_26, + input up_ch_rst_done_26, + output up_ch_prbsforceerr_26, + output [ 3:0] up_ch_prbssel_26, + output up_ch_prbscntreset_26, + input up_ch_prbserr_26, + input up_ch_prbslocked_26, + input [ 1:0] up_ch_bufstatus_26, + output up_ch_bufstatus_rst_26, + output up_ch_lpm_dfe_n_26, + output [ 2:0] up_ch_rate_26, + output [ 1:0] up_ch_sys_clk_sel_26, + output [ 2:0] up_ch_out_clk_sel_26, + output [ 4:0] up_ch_tx_diffctrl_26, + output [ 4:0] up_ch_tx_postcursor_26, + output [ 4:0] up_ch_tx_precursor_26, + output up_ch_enb_26, + output [11:0] up_ch_addr_26, + output up_ch_wr_26, + output [15:0] up_ch_wdata_26, + input [15:0] up_ch_rdata_26, + input up_ch_ready_26, + + output up_es_enb_27, + output [11:0] up_es_addr_27, + output up_es_wr_27, + output up_es_reset_27, + output [15:0] up_es_wdata_27, + input [15:0] up_es_rdata_27, + input up_es_ready_27, + + input up_ch_pll_locked_27, + output up_ch_rst_27, + output up_ch_user_ready_27, + input up_ch_rst_done_27, + output up_ch_prbsforceerr_27, + output [ 3:0] up_ch_prbssel_27, + output up_ch_prbscntreset_27, + input up_ch_prbserr_27, + input up_ch_prbslocked_27, + input [ 1:0] up_ch_bufstatus_27, + output up_ch_bufstatus_rst_27, + output up_ch_lpm_dfe_n_27, + output [ 2:0] up_ch_rate_27, + output [ 1:0] up_ch_sys_clk_sel_27, + output [ 2:0] up_ch_out_clk_sel_27, + output [ 4:0] up_ch_tx_diffctrl_27, + output [ 4:0] up_ch_tx_postcursor_27, + output [ 4:0] up_ch_tx_precursor_27, + output up_ch_enb_27, + output [11:0] up_ch_addr_27, + output up_ch_wr_27, + output [15:0] up_ch_wdata_27, + input [15:0] up_ch_rdata_27, + input up_ch_ready_27, + + output up_cm_enb_28, + output [11:0] up_cm_addr_28, + output up_cm_wr_28, + output [15:0] up_cm_wdata_28, + input [15:0] up_cm_rdata_28, + input up_cm_ready_28, + + output up_es_enb_28, + output [11:0] up_es_addr_28, + output up_es_wr_28, + output up_es_reset_28, + output [15:0] up_es_wdata_28, + input [15:0] up_es_rdata_28, + input up_es_ready_28, + + input up_ch_pll_locked_28, + output up_ch_rst_28, + output up_ch_user_ready_28, + input up_ch_rst_done_28, + output up_ch_prbsforceerr_28, + output [ 3:0] up_ch_prbssel_28, + output up_ch_prbscntreset_28, + input up_ch_prbserr_28, + input up_ch_prbslocked_28, + input [ 1:0] up_ch_bufstatus_28, + output up_ch_bufstatus_rst_28, + output up_ch_lpm_dfe_n_28, + output [ 2:0] up_ch_rate_28, + output [ 1:0] up_ch_sys_clk_sel_28, + output [ 2:0] up_ch_out_clk_sel_28, + output [ 4:0] up_ch_tx_diffctrl_28, + output [ 4:0] up_ch_tx_postcursor_28, + output [ 4:0] up_ch_tx_precursor_28, + output up_ch_enb_28, + output [11:0] up_ch_addr_28, + output up_ch_wr_28, + output [15:0] up_ch_wdata_28, + input [15:0] up_ch_rdata_28, + input up_ch_ready_28, + + output up_es_enb_29, + output [11:0] up_es_addr_29, + output up_es_wr_29, + output up_es_reset_29, + output [15:0] up_es_wdata_29, + input [15:0] up_es_rdata_29, + input up_es_ready_29, + + input up_ch_pll_locked_29, + output up_ch_rst_29, + output up_ch_user_ready_29, + input up_ch_rst_done_29, + output up_ch_prbsforceerr_29, + output [ 3:0] up_ch_prbssel_29, + output up_ch_prbscntreset_29, + input up_ch_prbserr_29, + input up_ch_prbslocked_29, + input [ 1:0] up_ch_bufstatus_29, + output up_ch_bufstatus_rst_29, + output up_ch_lpm_dfe_n_29, + output [ 2:0] up_ch_rate_29, + output [ 1:0] up_ch_sys_clk_sel_29, + output [ 2:0] up_ch_out_clk_sel_29, + output [ 4:0] up_ch_tx_diffctrl_29, + output [ 4:0] up_ch_tx_postcursor_29, + output [ 4:0] up_ch_tx_precursor_29, + output up_ch_enb_29, + output [11:0] up_ch_addr_29, + output up_ch_wr_29, + output [15:0] up_ch_wdata_29, + input [15:0] up_ch_rdata_29, + input up_ch_ready_29, + + output up_es_enb_30, + output [11:0] up_es_addr_30, + output up_es_wr_30, + output up_es_reset_30, + output [15:0] up_es_wdata_30, + input [15:0] up_es_rdata_30, + input up_es_ready_30, + + input up_ch_pll_locked_30, + output up_ch_rst_30, + output up_ch_user_ready_30, + input up_ch_rst_done_30, + output up_ch_prbsforceerr_30, + output [ 3:0] up_ch_prbssel_30, + output up_ch_prbscntreset_30, + input up_ch_prbserr_30, + input up_ch_prbslocked_30, + input [ 1:0] up_ch_bufstatus_30, + output up_ch_bufstatus_rst_30, + output up_ch_lpm_dfe_n_30, + output [ 2:0] up_ch_rate_30, + output [ 1:0] up_ch_sys_clk_sel_30, + output [ 2:0] up_ch_out_clk_sel_30, + output [ 4:0] up_ch_tx_diffctrl_30, + output [ 4:0] up_ch_tx_postcursor_30, + output [ 4:0] up_ch_tx_precursor_30, + output up_ch_enb_30, + output [11:0] up_ch_addr_30, + output up_ch_wr_30, + output [15:0] up_ch_wdata_30, + input [15:0] up_ch_rdata_30, + input up_ch_ready_30, + + output up_es_enb_31, + output [11:0] up_es_addr_31, + output up_es_wr_31, + output up_es_reset_31, + output [15:0] up_es_wdata_31, + input [15:0] up_es_rdata_31, + input up_es_ready_31, + + input up_ch_pll_locked_31, + output up_ch_rst_31, + output up_ch_user_ready_31, + input up_ch_rst_done_31, + output up_ch_prbsforceerr_31, + output [ 3:0] up_ch_prbssel_31, + output up_ch_prbscntreset_31, + input up_ch_prbserr_31, + input up_ch_prbslocked_31, + input [ 1:0] up_ch_bufstatus_31, + output up_ch_bufstatus_rst_31, + output up_ch_lpm_dfe_n_31, + output [ 2:0] up_ch_rate_31, + output [ 1:0] up_ch_sys_clk_sel_31, + output [ 2:0] up_ch_out_clk_sel_31, + output [ 4:0] up_ch_tx_diffctrl_31, + output [ 4:0] up_ch_tx_postcursor_31, + output [ 4:0] up_ch_tx_precursor_31, + output up_ch_enb_31, + output [11:0] up_ch_addr_31, + output up_ch_wr_31, + output [15:0] up_ch_wdata_31, + input [15:0] up_ch_rdata_31, + input up_ch_ready_31, + + input s_axi_aclk, + input s_axi_aresetn, + output up_status, + output up_pll_rst, + + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready, + + output m_axi_awvalid, + output [31:0] m_axi_awaddr, + output [ 2:0] m_axi_awprot, + input m_axi_awready, + output m_axi_wvalid, + output [31:0] m_axi_wdata, + output [ 3:0] m_axi_wstrb, + input m_axi_wready, + input m_axi_bvalid, + input [ 1:0] m_axi_bresp, + output m_axi_bready, + output m_axi_arvalid, + output [31:0] m_axi_araddr, + output [ 2:0] m_axi_arprot, + input m_axi_arready, + input m_axi_rvalid, + input [31:0] m_axi_rdata, + input [ 1:0] m_axi_rresp, + output m_axi_rready +); + + // internal signals + + wire [ 7:0] up_cm_sel; + wire up_cm_enb; + wire [11:0] up_cm_addr; + wire up_cm_wr; + wire [15:0] up_cm_wdata; + wire [15:0] up_cm_rdata_0_s; + wire up_cm_ready_0_s; + wire [15:0] up_cm_rdata_4_s; + wire up_cm_ready_4_s; + wire [15:0] up_cm_rdata_8_s; + wire up_cm_ready_8_s; + wire [15:0] up_cm_rdata_12_s; + wire up_cm_ready_12_s; + wire [15:0] up_cm_rdata_16_s; + wire up_cm_ready_16_s; + wire [15:0] up_cm_rdata_20_s; + wire up_cm_ready_20_s; + wire [15:0] up_cm_rdata_24_s; + wire up_cm_ready_24_s; + wire [15:0] up_cm_rdata_28_s; + wire up_cm_ready_28_s; + wire [ 7:0] up_es_sel; + wire up_es_enb; + wire [11:0] up_es_addr; + wire up_es_wr; + wire [15:0] up_es_wdata; + wire [15:0] up_es_rdata_0_s; + wire up_es_ready_0_s; + wire [15:0] up_es_rdata_1_s; + wire up_es_ready_1_s; + wire [15:0] up_es_rdata_2_s; + wire up_es_ready_2_s; + wire [15:0] up_es_rdata_3_s; + wire up_es_ready_3_s; + wire [15:0] up_es_rdata_4_s; + wire up_es_ready_4_s; + wire [15:0] up_es_rdata_5_s; + wire up_es_ready_5_s; + wire [15:0] up_es_rdata_6_s; + wire up_es_ready_6_s; + wire [15:0] up_es_rdata_7_s; + wire up_es_ready_7_s; + wire [15:0] up_es_rdata_8_s; + wire up_es_ready_8_s; + wire [15:0] up_es_rdata_9_s; + wire up_es_ready_9_s; + wire [15:0] up_es_rdata_10_s; + wire up_es_ready_10_s; + wire [15:0] up_es_rdata_11_s; + wire up_es_ready_11_s; + wire [15:0] up_es_rdata_12_s; + wire up_es_ready_12_s; + wire [15:0] up_es_rdata_13_s; + wire up_es_ready_13_s; + wire [15:0] up_es_rdata_14_s; + wire up_es_ready_14_s; + wire [15:0] up_es_rdata_15_s; + wire up_es_ready_15_s; + wire [15:0] up_es_rdata_16_s; + wire up_es_ready_16_s; + wire [15:0] up_es_rdata_17_s; + wire up_es_ready_17_s; + wire [15:0] up_es_rdata_18_s; + wire up_es_ready_18_s; + wire [15:0] up_es_rdata_19_s; + wire up_es_ready_19_s; + wire [15:0] up_es_rdata_20_s; + wire up_es_ready_20_s; + wire [15:0] up_es_rdata_21_s; + wire up_es_ready_21_s; + wire [15:0] up_es_rdata_22_s; + wire up_es_ready_22_s; + wire [15:0] up_es_rdata_23_s; + wire up_es_ready_23_s; + wire [15:0] up_es_rdata_24_s; + wire up_es_ready_24_s; + wire [15:0] up_es_rdata_25_s; + wire up_es_ready_25_s; + wire [15:0] up_es_rdata_26_s; + wire up_es_ready_26_s; + wire [15:0] up_es_rdata_27_s; + wire up_es_ready_27_s; + wire [15:0] up_es_rdata_28_s; + wire up_es_ready_28_s; + wire [15:0] up_es_rdata_29_s; + wire up_es_ready_29_s; + wire [15:0] up_es_rdata_30_s; + wire up_es_ready_30_s; + wire [15:0] up_es_rdata_31_s; + wire up_es_ready_31_s; + wire up_ch_rst; + wire up_ch_user_ready; + wire up_ch_lpm_dfe_n; + wire [ 2:0] up_ch_rate; + wire [ 1:0] up_ch_sys_clk_sel; + wire [ 2:0] up_ch_out_clk_sel; + wire [ 4:0] up_ch_tx_diffctrl; + wire [ 4:0] up_ch_tx_postcursor; + wire [ 4:0] up_ch_tx_precursor; + wire up_ch_prbsforceerr; + wire [ 3:0] up_ch_prbssel; + wire up_ch_prbscntreset; + wire up_ch_bufstatus_rst; + wire up_ch_pll_locked_0_s; + wire up_ch_rst_done_0_s; + wire up_ch_prbserr_0_s; + wire up_ch_prbslocked_0_s; + wire [ 1:0] up_ch_bufstatus_0_s; + wire up_ch_pll_locked_1_s; + wire up_ch_rst_done_1_s; + wire up_ch_prbserr_1_s; + wire up_ch_prbslocked_1_s; + wire [ 1:0] up_ch_bufstatus_1_s; + wire up_ch_pll_locked_2_s; + wire up_ch_rst_done_2_s; + wire up_ch_prbserr_2_s; + wire up_ch_prbslocked_2_s; + wire [ 1:0] up_ch_bufstatus_2_s; + wire up_ch_pll_locked_3_s; + wire up_ch_rst_done_3_s; + wire up_ch_prbserr_3_s; + wire up_ch_prbslocked_3_s; + wire [ 1:0] up_ch_bufstatus_3_s; + wire up_ch_pll_locked_4_s; + wire up_ch_rst_done_4_s; + wire up_ch_prbserr_4_s; + wire up_ch_prbslocked_4_s; + wire [ 1:0] up_ch_bufstatus_4_s; + wire up_ch_pll_locked_5_s; + wire up_ch_rst_done_5_s; + wire up_ch_prbserr_5_s; + wire up_ch_prbslocked_5_s; + wire [ 1:0] up_ch_bufstatus_5_s; + wire up_ch_pll_locked_6_s; + wire up_ch_rst_done_6_s; + wire up_ch_prbserr_6_s; + wire up_ch_prbslocked_6_s; + wire [ 1:0] up_ch_bufstatus_6_s; + wire up_ch_pll_locked_7_s; + wire up_ch_rst_done_7_s; + wire up_ch_prbserr_7_s; + wire up_ch_prbslocked_7_s; + wire [ 1:0] up_ch_bufstatus_7_s; + wire up_ch_pll_locked_8_s; + wire up_ch_rst_done_8_s; + wire up_ch_prbserr_8_s; + wire up_ch_prbslocked_8_s; + wire [ 1:0] up_ch_bufstatus_8_s; + wire up_ch_pll_locked_9_s; + wire up_ch_rst_done_9_s; + wire up_ch_prbserr_9_s; + wire up_ch_prbslocked_9_s; + wire [ 1:0] up_ch_bufstatus_9_s; + wire up_ch_pll_locked_10_s; + wire up_ch_rst_done_10_s; + wire up_ch_prbserr_10_s; + wire up_ch_prbslocked_10_s; + wire [ 1:0] up_ch_bufstatus_10_s; + wire up_ch_pll_locked_11_s; + wire up_ch_rst_done_11_s; + wire up_ch_prbserr_11_s; + wire up_ch_prbslocked_11_s; + wire [ 1:0] up_ch_bufstatus_11_s; + wire up_ch_pll_locked_12_s; + wire up_ch_rst_done_12_s; + wire up_ch_prbserr_12_s; + wire up_ch_prbslocked_12_s; + wire [ 1:0] up_ch_bufstatus_12_s; + wire up_ch_pll_locked_13_s; + wire up_ch_rst_done_13_s; + wire up_ch_prbserr_13_s; + wire up_ch_prbslocked_13_s; + wire [ 1:0] up_ch_bufstatus_13_s; + wire up_ch_pll_locked_14_s; + wire up_ch_rst_done_14_s; + wire up_ch_prbserr_14_s; + wire up_ch_prbslocked_14_s; + wire [ 1:0] up_ch_bufstatus_14_s; + wire up_ch_pll_locked_15_s; + wire up_ch_rst_done_15_s; + wire up_ch_prbserr_15_s; + wire up_ch_prbslocked_15_s; + wire [ 1:0] up_ch_bufstatus_15_s; + wire up_ch_pll_locked_16_s; + wire up_ch_rst_done_16_s; + wire up_ch_prbserr_16_s; + wire up_ch_prbslocked_16_s; + wire [ 1:0] up_ch_bufstatus_16_s; + wire up_ch_pll_locked_17_s; + wire up_ch_rst_done_17_s; + wire up_ch_prbserr_17_s; + wire up_ch_prbslocked_17_s; + wire [ 1:0] up_ch_bufstatus_17_s; + wire up_ch_pll_locked_18_s; + wire up_ch_rst_done_18_s; + wire up_ch_prbserr_18_s; + wire up_ch_prbslocked_18_s; + wire [ 1:0] up_ch_bufstatus_18_s; + wire up_ch_pll_locked_19_s; + wire up_ch_rst_done_19_s; + wire up_ch_prbserr_19_s; + wire up_ch_prbslocked_19_s; + wire [ 1:0] up_ch_bufstatus_19_s; + wire up_ch_pll_locked_20_s; + wire up_ch_rst_done_20_s; + wire up_ch_prbserr_20_s; + wire up_ch_prbslocked_20_s; + wire [ 1:0] up_ch_bufstatus_20_s; + wire up_ch_pll_locked_21_s; + wire up_ch_rst_done_21_s; + wire up_ch_prbserr_21_s; + wire up_ch_prbslocked_21_s; + wire [ 1:0] up_ch_bufstatus_21_s; + wire up_ch_pll_locked_22_s; + wire up_ch_rst_done_22_s; + wire up_ch_prbserr_22_s; + wire up_ch_prbslocked_22_s; + wire [ 1:0] up_ch_bufstatus_22_s; + wire up_ch_pll_locked_23_s; + wire up_ch_rst_done_23_s; + wire up_ch_prbserr_23_s; + wire up_ch_prbslocked_23_s; + wire [ 1:0] up_ch_bufstatus_23_s; + wire up_ch_pll_locked_24_s; + wire up_ch_rst_done_24_s; + wire up_ch_prbserr_24_s; + wire up_ch_prbslocked_24_s; + wire [ 1:0] up_ch_bufstatus_24_s; + wire up_ch_pll_locked_25_s; + wire up_ch_rst_done_25_s; + wire up_ch_prbserr_25_s; + wire up_ch_prbslocked_25_s; + wire [ 1:0] up_ch_bufstatus_25_s; + wire up_ch_pll_locked_26_s; + wire up_ch_rst_done_26_s; + wire up_ch_prbserr_26_s; + wire up_ch_prbslocked_26_s; + wire [ 1:0] up_ch_bufstatus_26_s; + wire up_ch_pll_locked_27_s; + wire up_ch_rst_done_27_s; + wire up_ch_prbserr_27_s; + wire up_ch_prbslocked_27_s; + wire [ 1:0] up_ch_bufstatus_27_s; + wire up_ch_pll_locked_28_s; + wire up_ch_rst_done_28_s; + wire up_ch_prbserr_28_s; + wire up_ch_prbslocked_28_s; + wire [ 1:0] up_ch_bufstatus_28_s; + wire up_ch_pll_locked_29_s; + wire up_ch_rst_done_29_s; + wire up_ch_prbserr_29_s; + wire up_ch_prbslocked_29_s; + wire [ 1:0] up_ch_bufstatus_29_s; + wire up_ch_pll_locked_30_s; + wire up_ch_rst_done_30_s; + wire up_ch_prbserr_30_s; + wire up_ch_prbslocked_30_s; + wire [ 1:0] up_ch_bufstatus_30_s; + wire up_ch_pll_locked_31_s; + wire up_ch_rst_done_31_s; + wire up_ch_prbserr_31_s; + wire up_ch_prbslocked_31_s; + wire [ 1:0] up_ch_bufstatus_31_s; + wire [ 7:0] up_ch_sel; + wire up_ch_enb; + wire [11:0] up_ch_addr; + wire up_ch_wr; + wire [15:0] up_ch_wdata; + wire [15:0] up_ch_rdata_0_s; + wire up_ch_ready_0_s; + wire [15:0] up_ch_rdata_1_s; + wire up_ch_ready_1_s; + wire [15:0] up_ch_rdata_2_s; + wire up_ch_ready_2_s; + wire [15:0] up_ch_rdata_3_s; + wire up_ch_ready_3_s; + wire [15:0] up_ch_rdata_4_s; + wire up_ch_ready_4_s; + wire [15:0] up_ch_rdata_5_s; + wire up_ch_ready_5_s; + wire [15:0] up_ch_rdata_6_s; + wire up_ch_ready_6_s; + wire [15:0] up_ch_rdata_7_s; + wire up_ch_ready_7_s; + wire [15:0] up_ch_rdata_8_s; + wire up_ch_ready_8_s; + wire [15:0] up_ch_rdata_9_s; + wire up_ch_ready_9_s; + wire [15:0] up_ch_rdata_10_s; + wire up_ch_ready_10_s; + wire [15:0] up_ch_rdata_11_s; + wire up_ch_ready_11_s; + wire [15:0] up_ch_rdata_12_s; + wire up_ch_ready_12_s; + wire [15:0] up_ch_rdata_13_s; + wire up_ch_ready_13_s; + wire [15:0] up_ch_rdata_14_s; + wire up_ch_ready_14_s; + wire [15:0] up_ch_rdata_15_s; + wire up_ch_ready_15_s; + wire [15:0] up_ch_rdata_16_s; + wire up_ch_ready_16_s; + wire [15:0] up_ch_rdata_17_s; + wire up_ch_ready_17_s; + wire [15:0] up_ch_rdata_18_s; + wire up_ch_ready_18_s; + wire [15:0] up_ch_rdata_19_s; + wire up_ch_ready_19_s; + wire [15:0] up_ch_rdata_20_s; + wire up_ch_ready_20_s; + wire [15:0] up_ch_rdata_21_s; + wire up_ch_ready_21_s; + wire [15:0] up_ch_rdata_22_s; + wire up_ch_ready_22_s; + wire [15:0] up_ch_rdata_23_s; + wire up_ch_ready_23_s; + wire [15:0] up_ch_rdata_24_s; + wire up_ch_ready_24_s; + wire [15:0] up_ch_rdata_25_s; + wire up_ch_ready_25_s; + wire [15:0] up_ch_rdata_26_s; + wire up_ch_ready_26_s; + wire [15:0] up_ch_rdata_27_s; + wire up_ch_ready_27_s; + wire [15:0] up_ch_rdata_28_s; + wire up_ch_ready_28_s; + wire [15:0] up_ch_rdata_29_s; + wire up_ch_ready_29_s; + wire [15:0] up_ch_rdata_30_s; + wire up_ch_ready_30_s; + wire [15:0] up_ch_rdata_31_s; + wire up_ch_ready_31_s; + wire up_es_req; + wire up_es_ack; + wire [ 4:0] up_es_pscale; + wire [ 1:0] up_es_vrange; + wire [ 7:0] up_es_vstep; + wire [ 7:0] up_es_vmax; + wire [ 7:0] up_es_vmin; + wire [11:0] up_es_hmax; + wire [11:0] up_es_hmin; + wire [11:0] up_es_hstep; + wire [31:0] up_es_saddr; + wire up_es_status; + wire up_rstn; + wire up_clk; + wire up_wreq; + wire [ 9:0] up_waddr; + wire [31:0] up_wdata; + wire up_wack; + wire up_rreq; + wire [ 9:0] up_raddr; + wire [31:0] up_rdata; + wire up_rack; + wire [15:0] up_es_reset; + + assign up_es_reset_0 = up_es_reset[0]; + assign up_es_reset_1 = up_es_reset[1]; + assign up_es_reset_2 = up_es_reset[2]; + assign up_es_reset_3 = up_es_reset[3]; + assign up_es_reset_4 = up_es_reset[4]; + assign up_es_reset_5 = up_es_reset[5]; + assign up_es_reset_6 = up_es_reset[6]; + assign up_es_reset_7 = up_es_reset[7]; + assign up_es_reset_8 = up_es_reset[8]; + assign up_es_reset_9 = up_es_reset[9]; + assign up_es_reset_10 = up_es_reset[10]; + assign up_es_reset_11 = up_es_reset[11]; + assign up_es_reset_12 = up_es_reset[12]; + assign up_es_reset_13 = up_es_reset[13]; + assign up_es_reset_14 = up_es_reset[14]; + assign up_es_reset_15 = up_es_reset[15]; + + // channel broadcast + + assign up_rstn = s_axi_aresetn; + assign up_clk = s_axi_aclk; + + assign up_cm_addr_0 = up_cm_addr; + assign up_cm_wr_0 = up_cm_wr; + assign up_cm_wdata_0 = up_cm_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (0), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_cm_0 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_cm_sel), + .up_enb (up_cm_enb), + .up_enb_out (up_cm_enb_0), + .up_rdata_in (16'd0), + .up_ready_in (1'd0), + .up_rdata (up_cm_rdata_0), + .up_ready (up_cm_ready_0), + .up_rdata_out (up_cm_rdata_0_s), + .up_ready_out (up_cm_ready_0_s)); + + assign up_es_addr_0 = up_es_addr; + assign up_es_wr_0 = up_es_wr; + assign up_es_wdata_0 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (0), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_0 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_0), + .up_rdata_in (16'd0), + .up_ready_in (1'd0), + .up_rdata (up_es_rdata_0), + .up_ready (up_es_ready_0), + .up_rdata_out (up_es_rdata_0_s), + .up_ready_out (up_es_ready_0_s)); + + assign up_ch_rst_0 = up_ch_rst; + assign up_ch_user_ready_0 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_0 = up_ch_lpm_dfe_n; + assign up_ch_rate_0 = up_ch_rate; + assign up_ch_sys_clk_sel_0 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_0 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_0 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_0 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_0 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_0 = up_ch_prbsforceerr; + assign up_ch_prbssel_0 = up_ch_prbssel; + assign up_ch_prbscntreset_0 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_0 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (0), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_0 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (1'd1), + .up_rst_done_in (1'd1), + .up_prbserr_in (1'd0), + .up_prbslocked_in (1'd1), + .up_bufstatus_in (2'd00), + .up_pll_locked (up_ch_pll_locked_0), + .up_rst_done (up_ch_rst_done_0), + .up_prbserr (up_ch_prbserr_0), + .up_prbslocked (up_ch_prbslocked_0), + .up_bufstatus (up_ch_bufstatus_0), + .up_pll_locked_out (up_ch_pll_locked_0_s), + .up_rst_done_out (up_ch_rst_done_0_s), + .up_prbserr_out (up_ch_prbserr_0_s), + .up_prbslocked_out (up_ch_prbslocked_0_s), + .up_bufstatus_out (up_ch_bufstatus_0_s)); + + assign up_ch_addr_0 = up_ch_addr; + assign up_ch_wr_0 = up_ch_wr; + assign up_ch_wdata_0 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (0), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_0 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_0), + .up_rdata_in (16'd0), + .up_ready_in (1'd0), + .up_rdata (up_ch_rdata_0), + .up_ready (up_ch_ready_0), + .up_rdata_out (up_ch_rdata_0_s), + .up_ready_out (up_ch_ready_0_s)); + + assign up_es_addr_1 = up_es_addr; + assign up_es_wr_1 = up_es_wr; + assign up_es_wdata_1 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (1), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_1 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_1), + .up_rdata_in (up_es_rdata_0_s), + .up_ready_in (up_es_ready_0_s), + .up_rdata (up_es_rdata_1), + .up_ready (up_es_ready_1), + .up_rdata_out (up_es_rdata_1_s), + .up_ready_out (up_es_ready_1_s)); + + assign up_ch_rst_1 = up_ch_rst; + assign up_ch_user_ready_1 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_1 = up_ch_lpm_dfe_n; + assign up_ch_rate_1 = up_ch_rate; + assign up_ch_sys_clk_sel_1 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_1 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_1 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_1 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_1 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_1 = up_ch_prbsforceerr; + assign up_ch_prbssel_1 = up_ch_prbssel; + assign up_ch_prbscntreset_1 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_1 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (1), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_1 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_0_s), + .up_rst_done_in (up_ch_rst_done_0_s), + .up_prbserr_in (up_ch_prbserr_0_s), + .up_prbslocked_in (up_ch_prbslocked_0_s), + .up_bufstatus_in (up_ch_bufstatus_0_s), + .up_pll_locked (up_ch_pll_locked_1), + .up_rst_done (up_ch_rst_done_1), + .up_prbserr (up_ch_prbserr_1), + .up_prbslocked (up_ch_prbslocked_1), + .up_bufstatus (up_ch_bufstatus_1), + .up_pll_locked_out (up_ch_pll_locked_1_s), + .up_rst_done_out (up_ch_rst_done_1_s), + .up_prbserr_out (up_ch_prbserr_1_s), + .up_prbslocked_out (up_ch_prbslocked_1_s), + .up_bufstatus_out (up_ch_bufstatus_1_s)); + + assign up_ch_addr_1 = up_ch_addr; + assign up_ch_wr_1 = up_ch_wr; + assign up_ch_wdata_1 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (1), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_1 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_1), + .up_rdata_in (up_ch_rdata_0_s), + .up_ready_in (up_ch_ready_0_s), + .up_rdata (up_ch_rdata_1), + .up_ready (up_ch_ready_1), + .up_rdata_out (up_ch_rdata_1_s), + .up_ready_out (up_ch_ready_1_s)); + + assign up_es_addr_2 = up_es_addr; + assign up_es_wr_2 = up_es_wr; + assign up_es_wdata_2 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (2), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_2 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_2), + .up_rdata_in (up_es_rdata_1_s), + .up_ready_in (up_es_ready_1_s), + .up_rdata (up_es_rdata_2), + .up_ready (up_es_ready_2), + .up_rdata_out (up_es_rdata_2_s), + .up_ready_out (up_es_ready_2_s)); + + assign up_ch_rst_2 = up_ch_rst; + assign up_ch_user_ready_2 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_2 = up_ch_lpm_dfe_n; + assign up_ch_rate_2 = up_ch_rate; + assign up_ch_sys_clk_sel_2 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_2 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_2 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_2 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_2 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_2 = up_ch_prbsforceerr; + assign up_ch_prbssel_2 = up_ch_prbssel; + assign up_ch_prbscntreset_2 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_2 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (2), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_2 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_1_s), + .up_rst_done_in (up_ch_rst_done_1_s), + .up_prbserr_in (up_ch_prbserr_1_s), + .up_prbslocked_in (up_ch_prbslocked_1_s), + .up_bufstatus_in (up_ch_bufstatus_1_s), + .up_pll_locked (up_ch_pll_locked_2), + .up_rst_done (up_ch_rst_done_2), + .up_prbserr (up_ch_prbserr_2), + .up_prbslocked (up_ch_prbslocked_2), + .up_bufstatus (up_ch_bufstatus_2), + .up_pll_locked_out (up_ch_pll_locked_2_s), + .up_rst_done_out (up_ch_rst_done_2_s), + .up_prbserr_out (up_ch_prbserr_2_s), + .up_prbslocked_out (up_ch_prbslocked_2_s), + .up_bufstatus_out (up_ch_bufstatus_2_s)); + + assign up_ch_addr_2 = up_ch_addr; + assign up_ch_wr_2 = up_ch_wr; + assign up_ch_wdata_2 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (2), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_2 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_2), + .up_rdata_in (up_ch_rdata_1_s), + .up_ready_in (up_ch_ready_1_s), + .up_rdata (up_ch_rdata_2), + .up_ready (up_ch_ready_2), + .up_rdata_out (up_ch_rdata_2_s), + .up_ready_out (up_ch_ready_2_s)); + + assign up_es_addr_3 = up_es_addr; + assign up_es_wr_3 = up_es_wr; + assign up_es_wdata_3 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (3), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_3 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_3), + .up_rdata_in (up_es_rdata_2_s), + .up_ready_in (up_es_ready_2_s), + .up_rdata (up_es_rdata_3), + .up_ready (up_es_ready_3), + .up_rdata_out (up_es_rdata_3_s), + .up_ready_out (up_es_ready_3_s)); + + assign up_ch_rst_3 = up_ch_rst; + assign up_ch_user_ready_3 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_3 = up_ch_lpm_dfe_n; + assign up_ch_rate_3 = up_ch_rate; + assign up_ch_sys_clk_sel_3 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_3 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_3 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_3 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_3 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_3 = up_ch_prbsforceerr; + assign up_ch_prbssel_3 = up_ch_prbssel; + assign up_ch_prbscntreset_3 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_3 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (3), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_3 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_2_s), + .up_rst_done_in (up_ch_rst_done_2_s), + .up_prbserr_in (up_ch_prbserr_2_s), + .up_prbslocked_in (up_ch_prbslocked_2_s), + .up_bufstatus_in (up_ch_bufstatus_2_s), + .up_pll_locked (up_ch_pll_locked_3), + .up_rst_done (up_ch_rst_done_3), + .up_prbserr (up_ch_prbserr_3), + .up_prbslocked (up_ch_prbslocked_3), + .up_bufstatus (up_ch_bufstatus_3), + .up_pll_locked_out (up_ch_pll_locked_3_s), + .up_rst_done_out (up_ch_rst_done_3_s), + .up_prbserr_out (up_ch_prbserr_3_s), + .up_prbslocked_out (up_ch_prbslocked_3_s), + .up_bufstatus_out (up_ch_bufstatus_3_s)); + + assign up_ch_addr_3 = up_ch_addr; + assign up_ch_wr_3 = up_ch_wr; + assign up_ch_wdata_3 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (3), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_3 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_3), + .up_rdata_in (up_ch_rdata_2_s), + .up_ready_in (up_ch_ready_2_s), + .up_rdata (up_ch_rdata_3), + .up_ready (up_ch_ready_3), + .up_rdata_out (up_ch_rdata_3_s), + .up_ready_out (up_ch_ready_3_s)); + + assign up_cm_addr_4 = up_cm_addr; + assign up_cm_wr_4 = up_cm_wr; + assign up_cm_wdata_4 = up_cm_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (4), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_cm_4 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_cm_sel), + .up_enb (up_cm_enb), + .up_enb_out (up_cm_enb_4), + .up_rdata_in (up_cm_rdata_0_s), + .up_ready_in (up_cm_ready_0_s), + .up_rdata (up_cm_rdata_4), + .up_ready (up_cm_ready_4), + .up_rdata_out (up_cm_rdata_4_s), + .up_ready_out (up_cm_ready_4_s)); + + assign up_es_addr_4 = up_es_addr; + assign up_es_wr_4 = up_es_wr; + assign up_es_wdata_4 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (4), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_4 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_4), + .up_rdata_in (up_es_rdata_3_s), + .up_ready_in (up_es_ready_3_s), + .up_rdata (up_es_rdata_4), + .up_ready (up_es_ready_4), + .up_rdata_out (up_es_rdata_4_s), + .up_ready_out (up_es_ready_4_s)); + + assign up_ch_rst_4 = up_ch_rst; + assign up_ch_user_ready_4 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_4 = up_ch_lpm_dfe_n; + assign up_ch_rate_4 = up_ch_rate; + assign up_ch_sys_clk_sel_4 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_4 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_4 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_4 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_4 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_4 = up_ch_prbsforceerr; + assign up_ch_prbssel_4 = up_ch_prbssel; + assign up_ch_prbscntreset_4 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_4 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (4), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_4 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_3_s), + .up_rst_done_in (up_ch_rst_done_3_s), + .up_prbserr_in (up_ch_prbserr_3_s), + .up_prbslocked_in (up_ch_prbslocked_3_s), + .up_bufstatus_in (up_ch_bufstatus_3_s), + .up_pll_locked (up_ch_pll_locked_4), + .up_rst_done (up_ch_rst_done_4), + .up_prbserr (up_ch_prbserr_4), + .up_prbslocked (up_ch_prbslocked_4), + .up_bufstatus (up_ch_bufstatus_4), + .up_pll_locked_out (up_ch_pll_locked_4_s), + .up_rst_done_out (up_ch_rst_done_4_s), + .up_prbserr_out (up_ch_prbserr_4_s), + .up_prbslocked_out (up_ch_prbslocked_4_s), + .up_bufstatus_out (up_ch_bufstatus_4_s)); + + assign up_ch_addr_4 = up_ch_addr; + assign up_ch_wr_4 = up_ch_wr; + assign up_ch_wdata_4 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (4), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_4 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_4), + .up_rdata_in (up_ch_rdata_3_s), + .up_ready_in (up_ch_ready_3_s), + .up_rdata (up_ch_rdata_4), + .up_ready (up_ch_ready_4), + .up_rdata_out (up_ch_rdata_4_s), + .up_ready_out (up_ch_ready_4_s)); + + assign up_es_addr_5 = up_es_addr; + assign up_es_wr_5 = up_es_wr; + assign up_es_wdata_5 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (5), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_5 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_5), + .up_rdata_in (up_es_rdata_4_s), + .up_ready_in (up_es_ready_4_s), + .up_rdata (up_es_rdata_5), + .up_ready (up_es_ready_5), + .up_rdata_out (up_es_rdata_5_s), + .up_ready_out (up_es_ready_5_s)); + + assign up_ch_rst_5 = up_ch_rst; + assign up_ch_user_ready_5 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_5 = up_ch_lpm_dfe_n; + assign up_ch_rate_5 = up_ch_rate; + assign up_ch_sys_clk_sel_5 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_5 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_5 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_5 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_5 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_5 = up_ch_prbsforceerr; + assign up_ch_prbssel_5 = up_ch_prbssel; + assign up_ch_prbscntreset_5 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_5 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (5), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_5 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_4_s), + .up_rst_done_in (up_ch_rst_done_4_s), + .up_prbserr_in (up_ch_prbserr_4_s), + .up_prbslocked_in (up_ch_prbslocked_4_s), + .up_bufstatus_in (up_ch_bufstatus_4_s), + .up_pll_locked (up_ch_pll_locked_5), + .up_rst_done (up_ch_rst_done_5), + .up_prbserr (up_ch_prbserr_5), + .up_prbslocked (up_ch_prbslocked_5), + .up_bufstatus (up_ch_bufstatus_5), + .up_pll_locked_out (up_ch_pll_locked_5_s), + .up_rst_done_out (up_ch_rst_done_5_s), + .up_prbserr_out (up_ch_prbserr_5_s), + .up_prbslocked_out (up_ch_prbslocked_5_s), + .up_bufstatus_out (up_ch_bufstatus_5_s)); + + assign up_ch_addr_5 = up_ch_addr; + assign up_ch_wr_5 = up_ch_wr; + assign up_ch_wdata_5 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (5), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_5 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_5), + .up_rdata_in (up_ch_rdata_4_s), + .up_ready_in (up_ch_ready_4_s), + .up_rdata (up_ch_rdata_5), + .up_ready (up_ch_ready_5), + .up_rdata_out (up_ch_rdata_5_s), + .up_ready_out (up_ch_ready_5_s)); + + assign up_es_addr_6 = up_es_addr; + assign up_es_wr_6 = up_es_wr; + assign up_es_wdata_6 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (6), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_6 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_6), + .up_rdata_in (up_es_rdata_5_s), + .up_ready_in (up_es_ready_5_s), + .up_rdata (up_es_rdata_6), + .up_ready (up_es_ready_6), + .up_rdata_out (up_es_rdata_6_s), + .up_ready_out (up_es_ready_6_s)); + + assign up_ch_rst_6 = up_ch_rst; + assign up_ch_user_ready_6 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_6 = up_ch_lpm_dfe_n; + assign up_ch_rate_6 = up_ch_rate; + assign up_ch_sys_clk_sel_6 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_6 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_6 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_6 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_6 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_6 = up_ch_prbsforceerr; + assign up_ch_prbssel_6 = up_ch_prbssel; + assign up_ch_prbscntreset_6 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_6 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (6), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_6 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_5_s), + .up_rst_done_in (up_ch_rst_done_5_s), + .up_prbserr_in (up_ch_prbserr_5_s), + .up_prbslocked_in (up_ch_prbslocked_5_s), + .up_bufstatus_in (up_ch_bufstatus_5_s), + .up_pll_locked (up_ch_pll_locked_6), + .up_rst_done (up_ch_rst_done_6), + .up_prbserr (up_ch_prbserr_6), + .up_prbslocked (up_ch_prbslocked_6), + .up_bufstatus (up_ch_bufstatus_6), + .up_pll_locked_out (up_ch_pll_locked_6_s), + .up_rst_done_out (up_ch_rst_done_6_s), + .up_prbserr_out (up_ch_prbserr_6_s), + .up_prbslocked_out (up_ch_prbslocked_6_s), + .up_bufstatus_out (up_ch_bufstatus_6_s)); + + assign up_ch_addr_6 = up_ch_addr; + assign up_ch_wr_6 = up_ch_wr; + assign up_ch_wdata_6 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (6), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_6 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_6), + .up_rdata_in (up_ch_rdata_5_s), + .up_ready_in (up_ch_ready_5_s), + .up_rdata (up_ch_rdata_6), + .up_ready (up_ch_ready_6), + .up_rdata_out (up_ch_rdata_6_s), + .up_ready_out (up_ch_ready_6_s)); + + assign up_es_addr_7 = up_es_addr; + assign up_es_wr_7 = up_es_wr; + assign up_es_wdata_7 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (7), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_7 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_7), + .up_rdata_in (up_es_rdata_6_s), + .up_ready_in (up_es_ready_6_s), + .up_rdata (up_es_rdata_7), + .up_ready (up_es_ready_7), + .up_rdata_out (up_es_rdata_7_s), + .up_ready_out (up_es_ready_7_s)); + + assign up_ch_rst_7 = up_ch_rst; + assign up_ch_user_ready_7 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_7 = up_ch_lpm_dfe_n; + assign up_ch_rate_7 = up_ch_rate; + assign up_ch_sys_clk_sel_7 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_7 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_7 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_7 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_7 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_7 = up_ch_prbsforceerr; + assign up_ch_prbssel_7 = up_ch_prbssel; + assign up_ch_prbscntreset_7 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_7 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (7), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_7 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_6_s), + .up_rst_done_in (up_ch_rst_done_6_s), + .up_prbserr_in (up_ch_prbserr_6_s), + .up_prbslocked_in (up_ch_prbslocked_6_s), + .up_bufstatus_in (up_ch_bufstatus_6_s), + .up_pll_locked (up_ch_pll_locked_7), + .up_rst_done (up_ch_rst_done_7), + .up_prbserr (up_ch_prbserr_7), + .up_prbslocked (up_ch_prbslocked_7), + .up_bufstatus (up_ch_bufstatus_7), + .up_pll_locked_out (up_ch_pll_locked_7_s), + .up_rst_done_out (up_ch_rst_done_7_s), + .up_prbserr_out (up_ch_prbserr_7_s), + .up_prbslocked_out (up_ch_prbslocked_7_s), + .up_bufstatus_out (up_ch_bufstatus_7_s)); + + assign up_ch_addr_7 = up_ch_addr; + assign up_ch_wr_7 = up_ch_wr; + assign up_ch_wdata_7 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (7), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_7 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_7), + .up_rdata_in (up_ch_rdata_6_s), + .up_ready_in (up_ch_ready_6_s), + .up_rdata (up_ch_rdata_7), + .up_ready (up_ch_ready_7), + .up_rdata_out (up_ch_rdata_7_s), + .up_ready_out (up_ch_ready_7_s)); + + assign up_cm_addr_8 = up_cm_addr; + assign up_cm_wr_8 = up_cm_wr; + assign up_cm_wdata_8 = up_cm_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (8), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_cm_8 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_cm_sel), + .up_enb (up_cm_enb), + .up_enb_out (up_cm_enb_8), + .up_rdata_in (up_cm_rdata_4_s), + .up_ready_in (up_cm_ready_4_s), + .up_rdata (up_cm_rdata_8), + .up_ready (up_cm_ready_8), + .up_rdata_out (up_cm_rdata_8_s), + .up_ready_out (up_cm_ready_8_s)); + + assign up_es_addr_8 = up_es_addr; + assign up_es_wr_8 = up_es_wr; + assign up_es_wdata_8 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (8), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_8 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_8), + .up_rdata_in (up_es_rdata_7_s), + .up_ready_in (up_es_ready_7_s), + .up_rdata (up_es_rdata_8), + .up_ready (up_es_ready_8), + .up_rdata_out (up_es_rdata_8_s), + .up_ready_out (up_es_ready_8_s)); + + assign up_ch_rst_8 = up_ch_rst; + assign up_ch_user_ready_8 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_8 = up_ch_lpm_dfe_n; + assign up_ch_rate_8 = up_ch_rate; + assign up_ch_sys_clk_sel_8 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_8 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_8 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_8 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_8 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_8 = up_ch_prbsforceerr; + assign up_ch_prbssel_8 = up_ch_prbssel; + assign up_ch_prbscntreset_8 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_8 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (8), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_8 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_7_s), + .up_rst_done_in (up_ch_rst_done_7_s), + .up_prbserr_in (up_ch_prbserr_7_s), + .up_prbslocked_in (up_ch_prbslocked_7_s), + .up_bufstatus_in (up_ch_bufstatus_7_s), + .up_pll_locked (up_ch_pll_locked_8), + .up_rst_done (up_ch_rst_done_8), + .up_prbserr (up_ch_prbserr_8), + .up_prbslocked (up_ch_prbslocked_8), + .up_bufstatus (up_ch_bufstatus_8), + .up_pll_locked_out (up_ch_pll_locked_8_s), + .up_rst_done_out (up_ch_rst_done_8_s), + .up_prbserr_out (up_ch_prbserr_8_s), + .up_prbslocked_out (up_ch_prbslocked_8_s), + .up_bufstatus_out (up_ch_bufstatus_8_s)); + + assign up_ch_addr_8 = up_ch_addr; + assign up_ch_wr_8 = up_ch_wr; + assign up_ch_wdata_8 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (8), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_8 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_8), + .up_rdata_in (up_ch_rdata_7_s), + .up_ready_in (up_ch_ready_7_s), + .up_rdata (up_ch_rdata_8), + .up_ready (up_ch_ready_8), + .up_rdata_out (up_ch_rdata_8_s), + .up_ready_out (up_ch_ready_8_s)); + + assign up_es_addr_9 = up_es_addr; + assign up_es_wr_9 = up_es_wr; + assign up_es_wdata_9 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (9), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_9 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_9), + .up_rdata_in (up_es_rdata_8_s), + .up_ready_in (up_es_ready_8_s), + .up_rdata (up_es_rdata_9), + .up_ready (up_es_ready_9), + .up_rdata_out (up_es_rdata_9_s), + .up_ready_out (up_es_ready_9_s)); + + assign up_ch_rst_9 = up_ch_rst; + assign up_ch_user_ready_9 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_9 = up_ch_lpm_dfe_n; + assign up_ch_rate_9 = up_ch_rate; + assign up_ch_sys_clk_sel_9 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_9 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_9 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_9 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_9 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_9 = up_ch_prbsforceerr; + assign up_ch_prbssel_9 = up_ch_prbssel; + assign up_ch_prbscntreset_9 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_9 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (9), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_9 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_8_s), + .up_rst_done_in (up_ch_rst_done_8_s), + .up_prbserr_in (up_ch_prbserr_8_s), + .up_prbslocked_in (up_ch_prbslocked_8_s), + .up_bufstatus_in (up_ch_bufstatus_8_s), + .up_pll_locked (up_ch_pll_locked_9), + .up_rst_done (up_ch_rst_done_9), + .up_prbserr (up_ch_prbserr_9), + .up_prbslocked (up_ch_prbslocked_9), + .up_bufstatus (up_ch_bufstatus_9), + .up_pll_locked_out (up_ch_pll_locked_9_s), + .up_rst_done_out (up_ch_rst_done_9_s), + .up_prbserr_out (up_ch_prbserr_9_s), + .up_prbslocked_out (up_ch_prbslocked_9_s), + .up_bufstatus_out (up_ch_bufstatus_9_s)); + + assign up_ch_addr_9 = up_ch_addr; + assign up_ch_wr_9 = up_ch_wr; + assign up_ch_wdata_9 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (9), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_9 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_9), + .up_rdata_in (up_ch_rdata_8_s), + .up_ready_in (up_ch_ready_8_s), + .up_rdata (up_ch_rdata_9), + .up_ready (up_ch_ready_9), + .up_rdata_out (up_ch_rdata_9_s), + .up_ready_out (up_ch_ready_9_s)); + + assign up_es_addr_10 = up_es_addr; + assign up_es_wr_10 = up_es_wr; + assign up_es_wdata_10 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (10), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_10 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_10), + .up_rdata_in (up_es_rdata_9_s), + .up_ready_in (up_es_ready_9_s), + .up_rdata (up_es_rdata_10), + .up_ready (up_es_ready_10), + .up_rdata_out (up_es_rdata_10_s), + .up_ready_out (up_es_ready_10_s)); + + assign up_ch_rst_10 = up_ch_rst; + assign up_ch_user_ready_10 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_10 = up_ch_lpm_dfe_n; + assign up_ch_rate_10 = up_ch_rate; + assign up_ch_sys_clk_sel_10 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_10 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_10 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_10 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_10 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_10 = up_ch_prbsforceerr; + assign up_ch_prbssel_10 = up_ch_prbssel; + assign up_ch_prbscntreset_10 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_10 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (10), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_10 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_9_s), + .up_rst_done_in (up_ch_rst_done_9_s), + .up_prbserr_in (up_ch_prbserr_9_s), + .up_prbslocked_in (up_ch_prbslocked_9_s), + .up_bufstatus_in (up_ch_bufstatus_9_s), + .up_pll_locked (up_ch_pll_locked_10), + .up_rst_done (up_ch_rst_done_10), + .up_prbserr (up_ch_prbserr_10), + .up_prbslocked (up_ch_prbslocked_10), + .up_bufstatus (up_ch_bufstatus_10), + .up_pll_locked_out (up_ch_pll_locked_10_s), + .up_rst_done_out (up_ch_rst_done_10_s), + .up_prbserr_out (up_ch_prbserr_10_s), + .up_prbslocked_out (up_ch_prbslocked_10_s), + .up_bufstatus_out (up_ch_bufstatus_10_s)); + + assign up_ch_addr_10 = up_ch_addr; + assign up_ch_wr_10 = up_ch_wr; + assign up_ch_wdata_10 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (10), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_10 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_10), + .up_rdata_in (up_ch_rdata_9_s), + .up_ready_in (up_ch_ready_9_s), + .up_rdata (up_ch_rdata_10), + .up_ready (up_ch_ready_10), + .up_rdata_out (up_ch_rdata_10_s), + .up_ready_out (up_ch_ready_10_s)); + + assign up_es_addr_11 = up_es_addr; + assign up_es_wr_11 = up_es_wr; + assign up_es_wdata_11 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (11), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_11 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_11), + .up_rdata_in (up_es_rdata_10_s), + .up_ready_in (up_es_ready_10_s), + .up_rdata (up_es_rdata_11), + .up_ready (up_es_ready_11), + .up_rdata_out (up_es_rdata_11_s), + .up_ready_out (up_es_ready_11_s)); + + assign up_ch_rst_11 = up_ch_rst; + assign up_ch_user_ready_11 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_11 = up_ch_lpm_dfe_n; + assign up_ch_rate_11 = up_ch_rate; + assign up_ch_sys_clk_sel_11 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_11 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_11 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_11 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_11 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_11 = up_ch_prbsforceerr; + assign up_ch_prbssel_11 = up_ch_prbssel; + assign up_ch_prbscntreset_11 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_11 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (11), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_11 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_10_s), + .up_rst_done_in (up_ch_rst_done_10_s), + .up_prbserr_in (up_ch_prbserr_10_s), + .up_prbslocked_in (up_ch_prbslocked_10_s), + .up_bufstatus_in (up_ch_bufstatus_10_s), + .up_pll_locked (up_ch_pll_locked_11), + .up_rst_done (up_ch_rst_done_11), + .up_prbserr (up_ch_prbserr_11), + .up_prbslocked (up_ch_prbslocked_11), + .up_bufstatus (up_ch_bufstatus_11), + .up_pll_locked_out (up_ch_pll_locked_11_s), + .up_rst_done_out (up_ch_rst_done_11_s), + .up_prbserr_out (up_ch_prbserr_11_s), + .up_prbslocked_out (up_ch_prbslocked_11_s), + .up_bufstatus_out (up_ch_bufstatus_11_s)); + + assign up_ch_addr_11 = up_ch_addr; + assign up_ch_wr_11 = up_ch_wr; + assign up_ch_wdata_11 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (11), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_11 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_11), + .up_rdata_in (up_ch_rdata_10_s), + .up_ready_in (up_ch_ready_10_s), + .up_rdata (up_ch_rdata_11), + .up_ready (up_ch_ready_11), + .up_rdata_out (up_ch_rdata_11_s), + .up_ready_out (up_ch_ready_11_s)); + + assign up_cm_addr_12 = up_cm_addr; + assign up_cm_wr_12 = up_cm_wr; + assign up_cm_wdata_12 = up_cm_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (12), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_cm_12 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_cm_sel), + .up_enb (up_cm_enb), + .up_enb_out (up_cm_enb_12), + .up_rdata_in (up_cm_rdata_8_s), + .up_ready_in (up_cm_ready_8_s), + .up_rdata (up_cm_rdata_12), + .up_ready (up_cm_ready_12), + .up_rdata_out (up_cm_rdata_12_s), + .up_ready_out (up_cm_ready_12_s)); + + assign up_es_addr_12 = up_es_addr; + assign up_es_wr_12 = up_es_wr; + assign up_es_wdata_12 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (12), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_12 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_12), + .up_rdata_in (up_es_rdata_11_s), + .up_ready_in (up_es_ready_11_s), + .up_rdata (up_es_rdata_12), + .up_ready (up_es_ready_12), + .up_rdata_out (up_es_rdata_12_s), + .up_ready_out (up_es_ready_12_s)); + + assign up_ch_rst_12 = up_ch_rst; + assign up_ch_user_ready_12 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_12 = up_ch_lpm_dfe_n; + assign up_ch_rate_12 = up_ch_rate; + assign up_ch_sys_clk_sel_12 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_12 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_12 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_12 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_12 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_12 = up_ch_prbsforceerr; + assign up_ch_prbssel_12 = up_ch_prbssel; + assign up_ch_prbscntreset_12 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_12 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (12), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_12 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_11_s), + .up_rst_done_in (up_ch_rst_done_11_s), + .up_prbserr_in (up_ch_prbserr_11_s), + .up_prbslocked_in (up_ch_prbslocked_11_s), + .up_bufstatus_in (up_ch_bufstatus_11_s), + .up_pll_locked (up_ch_pll_locked_12), + .up_rst_done (up_ch_rst_done_12), + .up_prbserr (up_ch_prbserr_12), + .up_prbslocked (up_ch_prbslocked_12), + .up_bufstatus (up_ch_bufstatus_12), + .up_pll_locked_out (up_ch_pll_locked_12_s), + .up_rst_done_out (up_ch_rst_done_12_s), + .up_prbserr_out (up_ch_prbserr_12_s), + .up_prbslocked_out (up_ch_prbslocked_12_s), + .up_bufstatus_out (up_ch_bufstatus_12_s)); + + assign up_ch_addr_12 = up_ch_addr; + assign up_ch_wr_12 = up_ch_wr; + assign up_ch_wdata_12 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (12), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_12 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_12), + .up_rdata_in (up_ch_rdata_11_s), + .up_ready_in (up_ch_ready_11_s), + .up_rdata (up_ch_rdata_12), + .up_ready (up_ch_ready_12), + .up_rdata_out (up_ch_rdata_12_s), + .up_ready_out (up_ch_ready_12_s)); + + assign up_es_addr_13 = up_es_addr; + assign up_es_wr_13 = up_es_wr; + assign up_es_wdata_13 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (13), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_13 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_13), + .up_rdata_in (up_es_rdata_12_s), + .up_ready_in (up_es_ready_12_s), + .up_rdata (up_es_rdata_13), + .up_ready (up_es_ready_13), + .up_rdata_out (up_es_rdata_13_s), + .up_ready_out (up_es_ready_13_s)); + + assign up_ch_rst_13 = up_ch_rst; + assign up_ch_user_ready_13 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_13 = up_ch_lpm_dfe_n; + assign up_ch_rate_13 = up_ch_rate; + assign up_ch_sys_clk_sel_13 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_13 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_13 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_13 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_13 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_13 = up_ch_prbsforceerr; + assign up_ch_prbssel_13 = up_ch_prbssel; + assign up_ch_prbscntreset_13 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_13 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (13), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_13 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_12_s), + .up_rst_done_in (up_ch_rst_done_12_s), + .up_prbserr_in (up_ch_prbserr_12_s), + .up_prbslocked_in (up_ch_prbslocked_12_s), + .up_bufstatus_in (up_ch_bufstatus_12_s), + .up_pll_locked (up_ch_pll_locked_13), + .up_rst_done (up_ch_rst_done_13), + .up_prbserr (up_ch_prbserr_13), + .up_prbslocked (up_ch_prbslocked_13), + .up_bufstatus (up_ch_bufstatus_13), + .up_pll_locked_out (up_ch_pll_locked_13_s), + .up_rst_done_out (up_ch_rst_done_13_s), + .up_prbserr_out (up_ch_prbserr_13_s), + .up_prbslocked_out (up_ch_prbslocked_13_s), + .up_bufstatus_out (up_ch_bufstatus_13_s)); + + assign up_ch_addr_13 = up_ch_addr; + assign up_ch_wr_13 = up_ch_wr; + assign up_ch_wdata_13 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (13), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_13 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_13), + .up_rdata_in (up_ch_rdata_12_s), + .up_ready_in (up_ch_ready_12_s), + .up_rdata (up_ch_rdata_13), + .up_ready (up_ch_ready_13), + .up_rdata_out (up_ch_rdata_13_s), + .up_ready_out (up_ch_ready_13_s)); + + assign up_es_addr_14 = up_es_addr; + assign up_es_wr_14 = up_es_wr; + assign up_es_wdata_14 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (14), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_14 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_14), + .up_rdata_in (up_es_rdata_13_s), + .up_ready_in (up_es_ready_13_s), + .up_rdata (up_es_rdata_14), + .up_ready (up_es_ready_14), + .up_rdata_out (up_es_rdata_14_s), + .up_ready_out (up_es_ready_14_s)); + + assign up_ch_rst_14 = up_ch_rst; + assign up_ch_user_ready_14 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_14 = up_ch_lpm_dfe_n; + assign up_ch_rate_14 = up_ch_rate; + assign up_ch_sys_clk_sel_14 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_14 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_14 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_14 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_14 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_14 = up_ch_prbsforceerr; + assign up_ch_prbssel_14 = up_ch_prbssel; + assign up_ch_prbscntreset_14 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_14 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (14), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_14 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_13_s), + .up_rst_done_in (up_ch_rst_done_13_s), + .up_prbserr_in (up_ch_prbserr_13_s), + .up_prbslocked_in (up_ch_prbslocked_13_s), + .up_bufstatus_in (up_ch_bufstatus_13_s), + .up_pll_locked (up_ch_pll_locked_14), + .up_rst_done (up_ch_rst_done_14), + .up_prbserr (up_ch_prbserr_14), + .up_prbslocked (up_ch_prbslocked_14), + .up_bufstatus (up_ch_bufstatus_14), + .up_pll_locked_out (up_ch_pll_locked_14_s), + .up_rst_done_out (up_ch_rst_done_14_s), + .up_prbserr_out (up_ch_prbserr_14_s), + .up_prbslocked_out (up_ch_prbslocked_14_s), + .up_bufstatus_out (up_ch_bufstatus_14_s)); + + assign up_ch_addr_14 = up_ch_addr; + assign up_ch_wr_14 = up_ch_wr; + assign up_ch_wdata_14 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (14), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_14 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_14), + .up_rdata_in (up_ch_rdata_13_s), + .up_ready_in (up_ch_ready_13_s), + .up_rdata (up_ch_rdata_14), + .up_ready (up_ch_ready_14), + .up_rdata_out (up_ch_rdata_14_s), + .up_ready_out (up_ch_ready_14_s)); + + assign up_es_addr_15 = up_es_addr; + assign up_es_wr_15 = up_es_wr; + assign up_es_wdata_15 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (15), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_15 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_15), + .up_rdata_in (up_es_rdata_14_s), + .up_ready_in (up_es_ready_14_s), + .up_rdata (up_es_rdata_15), + .up_ready (up_es_ready_15), + .up_rdata_out (up_es_rdata_15_s), + .up_ready_out (up_es_ready_15_s)); + + assign up_ch_rst_15 = up_ch_rst; + assign up_ch_user_ready_15 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_15 = up_ch_lpm_dfe_n; + assign up_ch_rate_15 = up_ch_rate; + assign up_ch_sys_clk_sel_15 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_15 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_15 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_15 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_15 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_15 = up_ch_prbsforceerr; + assign up_ch_prbssel_15 = up_ch_prbssel; + assign up_ch_prbscntreset_15 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_15 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (15), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_15 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_14_s), + .up_rst_done_in (up_ch_rst_done_14_s), + .up_prbserr_in (up_ch_prbserr_14_s), + .up_prbslocked_in (up_ch_prbslocked_14_s), + .up_bufstatus_in (up_ch_bufstatus_14_s), + .up_pll_locked (up_ch_pll_locked_15), + .up_rst_done (up_ch_rst_done_15), + .up_prbserr (up_ch_prbserr_15), + .up_prbslocked (up_ch_prbslocked_15), + .up_bufstatus (up_ch_bufstatus_15), + .up_pll_locked_out (up_ch_pll_locked_15_s), + .up_rst_done_out (up_ch_rst_done_15_s), + .up_prbserr_out (up_ch_prbserr_15_s), + .up_prbslocked_out (up_ch_prbslocked_15_s), + .up_bufstatus_out (up_ch_bufstatus_15_s)); + + assign up_ch_addr_15 = up_ch_addr; + assign up_ch_wr_15 = up_ch_wr; + assign up_ch_wdata_15 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (15), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_15 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_15), + .up_rdata_in (up_ch_rdata_14_s), + .up_ready_in (up_ch_ready_14_s), + .up_rdata (up_ch_rdata_15), + .up_ready (up_ch_ready_15), + .up_rdata_out (up_ch_rdata_15_s), + .up_ready_out (up_ch_ready_15_s)); + + assign up_cm_addr_16 = up_cm_addr; + assign up_cm_wr_16 = up_cm_wr; + assign up_cm_wdata_16 = up_cm_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (16), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_cm_16 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_cm_sel), + .up_enb (up_cm_enb), + .up_enb_out (up_cm_enb_16), + .up_rdata_in (up_cm_rdata_12_s), + .up_ready_in (up_cm_ready_12_s), + .up_rdata (up_cm_rdata_16), + .up_ready (up_cm_ready_16), + .up_rdata_out (up_cm_rdata_16_s), + .up_ready_out (up_cm_ready_16_s)); + + assign up_es_addr_16 = up_es_addr; + assign up_es_wr_16 = up_es_wr; + assign up_es_wdata_16 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (16), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_16 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_16), + .up_rdata_in (up_es_rdata_15_s), + .up_ready_in (up_es_ready_15_s), + .up_rdata (up_es_rdata_16), + .up_ready (up_es_ready_16), + .up_rdata_out (up_es_rdata_16_s), + .up_ready_out (up_es_ready_16_s)); + + assign up_ch_rst_16 = up_ch_rst; + assign up_ch_user_ready_16 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_16 = up_ch_lpm_dfe_n; + assign up_ch_rate_16 = up_ch_rate; + assign up_ch_sys_clk_sel_16 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_16 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_16 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_16 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_16 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_16 = up_ch_prbsforceerr; + assign up_ch_prbssel_16 = up_ch_prbssel; + assign up_ch_prbscntreset_16 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_16 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (16), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_16 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_15_s), + .up_rst_done_in (up_ch_rst_done_15_s), + .up_prbserr_in (up_ch_prbserr_15_s), + .up_prbslocked_in (up_ch_prbslocked_15_s), + .up_bufstatus_in (up_ch_bufstatus_15_s), + .up_pll_locked (up_ch_pll_locked_16), + .up_rst_done (up_ch_rst_done_16), + .up_prbserr (up_ch_prbserr_16), + .up_prbslocked (up_ch_prbslocked_16), + .up_bufstatus (up_ch_bufstatus_16), + .up_pll_locked_out (up_ch_pll_locked_16_s), + .up_rst_done_out (up_ch_rst_done_16_s), + .up_prbserr_out (up_ch_prbserr_16_s), + .up_prbslocked_out (up_ch_prbslocked_16_s), + .up_bufstatus_out (up_ch_bufstatus_16_s)); + + assign up_ch_addr_16 = up_ch_addr; + assign up_ch_wr_16 = up_ch_wr; + assign up_ch_wdata_16 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (16), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_16 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_16), + .up_rdata_in (up_ch_rdata_15_s), + .up_ready_in (up_ch_ready_15_s), + .up_rdata (up_ch_rdata_16), + .up_ready (up_ch_ready_16), + .up_rdata_out (up_ch_rdata_16_s), + .up_ready_out (up_ch_ready_16_s)); + + assign up_es_addr_17 = up_es_addr; + assign up_es_wr_17 = up_es_wr; + assign up_es_wdata_17 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (17), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_17 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_17), + .up_rdata_in (up_es_rdata_16_s), + .up_ready_in (up_es_ready_16_s), + .up_rdata (up_es_rdata_17), + .up_ready (up_es_ready_17), + .up_rdata_out (up_es_rdata_17_s), + .up_ready_out (up_es_ready_17_s)); + + assign up_ch_rst_17 = up_ch_rst; + assign up_ch_user_ready_17 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_17 = up_ch_lpm_dfe_n; + assign up_ch_rate_17 = up_ch_rate; + assign up_ch_sys_clk_sel_17 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_17 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_17 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_17 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_17 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_17 = up_ch_prbsforceerr; + assign up_ch_prbssel_17 = up_ch_prbssel; + assign up_ch_prbscntreset_17 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_17 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (17), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_17 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_16_s), + .up_rst_done_in (up_ch_rst_done_16_s), + .up_prbserr_in (up_ch_prbserr_16_s), + .up_prbslocked_in (up_ch_prbslocked_16_s), + .up_bufstatus_in (up_ch_bufstatus_16_s), + .up_pll_locked (up_ch_pll_locked_17), + .up_rst_done (up_ch_rst_done_17), + .up_prbserr (up_ch_prbserr_17), + .up_prbslocked (up_ch_prbslocked_17), + .up_bufstatus (up_ch_bufstatus_17), + .up_pll_locked_out (up_ch_pll_locked_17_s), + .up_rst_done_out (up_ch_rst_done_17_s), + .up_prbserr_out (up_ch_prbserr_17_s), + .up_prbslocked_out (up_ch_prbslocked_17_s), + .up_bufstatus_out (up_ch_bufstatus_17_s)); + + assign up_ch_addr_17 = up_ch_addr; + assign up_ch_wr_17 = up_ch_wr; + assign up_ch_wdata_17 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (17), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_17 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_17), + .up_rdata_in (up_ch_rdata_16_s), + .up_ready_in (up_ch_ready_16_s), + .up_rdata (up_ch_rdata_17), + .up_ready (up_ch_ready_17), + .up_rdata_out (up_ch_rdata_17_s), + .up_ready_out (up_ch_ready_17_s)); + + assign up_es_addr_18 = up_es_addr; + assign up_es_wr_18 = up_es_wr; + assign up_es_wdata_18 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (18), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_18 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_18), + .up_rdata_in (up_es_rdata_17_s), + .up_ready_in (up_es_ready_17_s), + .up_rdata (up_es_rdata_18), + .up_ready (up_es_ready_18), + .up_rdata_out (up_es_rdata_18_s), + .up_ready_out (up_es_ready_18_s)); + + assign up_ch_rst_18 = up_ch_rst; + assign up_ch_user_ready_18 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_18 = up_ch_lpm_dfe_n; + assign up_ch_rate_18 = up_ch_rate; + assign up_ch_sys_clk_sel_18 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_18 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_18 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_18 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_18 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_18 = up_ch_prbsforceerr; + assign up_ch_prbssel_18 = up_ch_prbssel; + assign up_ch_prbscntreset_18 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_18 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (18), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_18 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_17_s), + .up_rst_done_in (up_ch_rst_done_17_s), + .up_prbserr_in (up_ch_prbserr_17_s), + .up_prbslocked_in (up_ch_prbslocked_17_s), + .up_bufstatus_in (up_ch_bufstatus_17_s), + .up_pll_locked (up_ch_pll_locked_18), + .up_rst_done (up_ch_rst_done_18), + .up_prbserr (up_ch_prbserr_18), + .up_prbslocked (up_ch_prbslocked_18), + .up_bufstatus (up_ch_bufstatus_18), + .up_pll_locked_out (up_ch_pll_locked_18_s), + .up_rst_done_out (up_ch_rst_done_18_s), + .up_prbserr_out (up_ch_prbserr_18_s), + .up_prbslocked_out (up_ch_prbslocked_18_s), + .up_bufstatus_out (up_ch_bufstatus_18_s)); + + assign up_ch_addr_18 = up_ch_addr; + assign up_ch_wr_18 = up_ch_wr; + assign up_ch_wdata_18 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (18), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_18 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_18), + .up_rdata_in (up_ch_rdata_17_s), + .up_ready_in (up_ch_ready_17_s), + .up_rdata (up_ch_rdata_18), + .up_ready (up_ch_ready_18), + .up_rdata_out (up_ch_rdata_18_s), + .up_ready_out (up_ch_ready_18_s)); + + assign up_es_addr_19 = up_es_addr; + assign up_es_wr_19 = up_es_wr; + assign up_es_wdata_19 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (19), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_19 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_19), + .up_rdata_in (up_es_rdata_18_s), + .up_ready_in (up_es_ready_18_s), + .up_rdata (up_es_rdata_19), + .up_ready (up_es_ready_19), + .up_rdata_out (up_es_rdata_19_s), + .up_ready_out (up_es_ready_19_s)); + + assign up_ch_rst_19 = up_ch_rst; + assign up_ch_user_ready_19 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_19 = up_ch_lpm_dfe_n; + assign up_ch_rate_19 = up_ch_rate; + assign up_ch_sys_clk_sel_19 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_19 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_19 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_19 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_19 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_19 = up_ch_prbsforceerr; + assign up_ch_prbssel_19 = up_ch_prbssel; + assign up_ch_prbscntreset_19 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_19 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (19), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_19 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_18_s), + .up_rst_done_in (up_ch_rst_done_18_s), + .up_prbserr_in (up_ch_prbserr_18_s), + .up_prbslocked_in (up_ch_prbslocked_18_s), + .up_bufstatus_in (up_ch_bufstatus_18_s), + .up_pll_locked (up_ch_pll_locked_19), + .up_rst_done (up_ch_rst_done_19), + .up_prbserr (up_ch_prbserr_19), + .up_prbslocked (up_ch_prbslocked_19), + .up_bufstatus (up_ch_bufstatus_19), + .up_pll_locked_out (up_ch_pll_locked_19_s), + .up_rst_done_out (up_ch_rst_done_19_s), + .up_prbserr_out (up_ch_prbserr_19_s), + .up_prbslocked_out (up_ch_prbslocked_19_s), + .up_bufstatus_out (up_ch_bufstatus_19_s)); + + assign up_ch_addr_19 = up_ch_addr; + assign up_ch_wr_19 = up_ch_wr; + assign up_ch_wdata_19 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (19), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_19 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_19), + .up_rdata_in (up_ch_rdata_18_s), + .up_ready_in (up_ch_ready_18_s), + .up_rdata (up_ch_rdata_19), + .up_ready (up_ch_ready_19), + .up_rdata_out (up_ch_rdata_19_s), + .up_ready_out (up_ch_ready_19_s)); + + assign up_cm_addr_20 = up_cm_addr; + assign up_cm_wr_20 = up_cm_wr; + assign up_cm_wdata_20 = up_cm_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (20), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_cm_20 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_cm_sel), + .up_enb (up_cm_enb), + .up_enb_out (up_cm_enb_20), + .up_rdata_in (up_cm_rdata_16_s), + .up_ready_in (up_cm_ready_16_s), + .up_rdata (up_cm_rdata_20), + .up_ready (up_cm_ready_20), + .up_rdata_out (up_cm_rdata_20_s), + .up_ready_out (up_cm_ready_20_s)); + + assign up_es_addr_20 = up_es_addr; + assign up_es_wr_20 = up_es_wr; + assign up_es_wdata_20 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (20), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_20 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_20), + .up_rdata_in (up_es_rdata_19_s), + .up_ready_in (up_es_ready_19_s), + .up_rdata (up_es_rdata_20), + .up_ready (up_es_ready_20), + .up_rdata_out (up_es_rdata_20_s), + .up_ready_out (up_es_ready_20_s)); + + assign up_ch_rst_20 = up_ch_rst; + assign up_ch_user_ready_20 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_20 = up_ch_lpm_dfe_n; + assign up_ch_rate_20 = up_ch_rate; + assign up_ch_sys_clk_sel_20 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_20 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_20 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_20 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_20 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_20 = up_ch_prbsforceerr; + assign up_ch_prbssel_20 = up_ch_prbssel; + assign up_ch_prbscntreset_20 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_20 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (20), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_20 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_19_s), + .up_rst_done_in (up_ch_rst_done_19_s), + .up_prbserr_in (up_ch_prbserr_19_s), + .up_prbslocked_in (up_ch_prbslocked_19_s), + .up_bufstatus_in (up_ch_bufstatus_19_s), + .up_pll_locked (up_ch_pll_locked_20), + .up_rst_done (up_ch_rst_done_20), + .up_prbserr (up_ch_prbserr_20), + .up_prbslocked (up_ch_prbslocked_20), + .up_bufstatus (up_ch_bufstatus_20), + .up_pll_locked_out (up_ch_pll_locked_20_s), + .up_rst_done_out (up_ch_rst_done_20_s), + .up_prbserr_out (up_ch_prbserr_20_s), + .up_prbslocked_out (up_ch_prbslocked_20_s), + .up_bufstatus_out (up_ch_bufstatus_20_s)); + + assign up_ch_addr_20 = up_ch_addr; + assign up_ch_wr_20 = up_ch_wr; + assign up_ch_wdata_20 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (20), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_20 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_20), + .up_rdata_in (up_ch_rdata_19_s), + .up_ready_in (up_ch_ready_19_s), + .up_rdata (up_ch_rdata_20), + .up_ready (up_ch_ready_20), + .up_rdata_out (up_ch_rdata_20_s), + .up_ready_out (up_ch_ready_20_s)); + + assign up_es_addr_21 = up_es_addr; + assign up_es_wr_21 = up_es_wr; + assign up_es_wdata_21 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (21), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_21 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_21), + .up_rdata_in (up_es_rdata_20_s), + .up_ready_in (up_es_ready_20_s), + .up_rdata (up_es_rdata_21), + .up_ready (up_es_ready_21), + .up_rdata_out (up_es_rdata_21_s), + .up_ready_out (up_es_ready_21_s)); + + assign up_ch_rst_21 = up_ch_rst; + assign up_ch_user_ready_21 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_21 = up_ch_lpm_dfe_n; + assign up_ch_rate_21 = up_ch_rate; + assign up_ch_sys_clk_sel_21 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_21 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_21 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_21 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_21 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_21 = up_ch_prbsforceerr; + assign up_ch_prbssel_21 = up_ch_prbssel; + assign up_ch_prbscntreset_21 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_21 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (21), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_21 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_20_s), + .up_rst_done_in (up_ch_rst_done_20_s), + .up_prbserr_in (up_ch_prbserr_20_s), + .up_prbslocked_in (up_ch_prbslocked_20_s), + .up_bufstatus_in (up_ch_bufstatus_20_s), + .up_pll_locked (up_ch_pll_locked_21), + .up_rst_done (up_ch_rst_done_21), + .up_prbserr (up_ch_prbserr_21), + .up_prbslocked (up_ch_prbslocked_21), + .up_bufstatus (up_ch_bufstatus_21), + .up_pll_locked_out (up_ch_pll_locked_21_s), + .up_rst_done_out (up_ch_rst_done_21_s), + .up_prbserr_out (up_ch_prbserr_21_s), + .up_prbslocked_out (up_ch_prbslocked_21_s), + .up_bufstatus_out (up_ch_bufstatus_21_s)); + + assign up_ch_addr_21 = up_ch_addr; + assign up_ch_wr_21 = up_ch_wr; + assign up_ch_wdata_21 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (21), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_21 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_21), + .up_rdata_in (up_ch_rdata_20_s), + .up_ready_in (up_ch_ready_20_s), + .up_rdata (up_ch_rdata_21), + .up_ready (up_ch_ready_21), + .up_rdata_out (up_ch_rdata_21_s), + .up_ready_out (up_ch_ready_21_s)); + + assign up_es_addr_22 = up_es_addr; + assign up_es_wr_22 = up_es_wr; + assign up_es_wdata_22 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (22), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_22 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_22), + .up_rdata_in (up_es_rdata_21_s), + .up_ready_in (up_es_ready_21_s), + .up_rdata (up_es_rdata_22), + .up_ready (up_es_ready_22), + .up_rdata_out (up_es_rdata_22_s), + .up_ready_out (up_es_ready_22_s)); + + assign up_ch_rst_22 = up_ch_rst; + assign up_ch_user_ready_22 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_22 = up_ch_lpm_dfe_n; + assign up_ch_rate_22 = up_ch_rate; + assign up_ch_sys_clk_sel_22 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_22 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_22 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_22 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_22 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_22 = up_ch_prbsforceerr; + assign up_ch_prbssel_22 = up_ch_prbssel; + assign up_ch_prbscntreset_22 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_22 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (22), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_22 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_21_s), + .up_rst_done_in (up_ch_rst_done_21_s), + .up_prbserr_in (up_ch_prbserr_21_s), + .up_prbslocked_in (up_ch_prbslocked_21_s), + .up_bufstatus_in (up_ch_bufstatus_21_s), + .up_pll_locked (up_ch_pll_locked_22), + .up_rst_done (up_ch_rst_done_22), + .up_prbserr (up_ch_prbserr_22), + .up_prbslocked (up_ch_prbslocked_22), + .up_bufstatus (up_ch_bufstatus_22), + .up_pll_locked_out (up_ch_pll_locked_22_s), + .up_rst_done_out (up_ch_rst_done_22_s), + .up_prbserr_out (up_ch_prbserr_22_s), + .up_prbslocked_out (up_ch_prbslocked_22_s), + .up_bufstatus_out (up_ch_bufstatus_22_s)); + + assign up_ch_addr_22 = up_ch_addr; + assign up_ch_wr_22 = up_ch_wr; + assign up_ch_wdata_22 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (22), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_22 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_22), + .up_rdata_in (up_ch_rdata_21_s), + .up_ready_in (up_ch_ready_21_s), + .up_rdata (up_ch_rdata_22), + .up_ready (up_ch_ready_22), + .up_rdata_out (up_ch_rdata_22_s), + .up_ready_out (up_ch_ready_22_s)); + + assign up_es_addr_23 = up_es_addr; + assign up_es_wr_23 = up_es_wr; + assign up_es_wdata_23 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (23), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_23 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_23), + .up_rdata_in (up_es_rdata_22_s), + .up_ready_in (up_es_ready_22_s), + .up_rdata (up_es_rdata_23), + .up_ready (up_es_ready_23), + .up_rdata_out (up_es_rdata_23_s), + .up_ready_out (up_es_ready_23_s)); + + assign up_ch_rst_23 = up_ch_rst; + assign up_ch_user_ready_23 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_23 = up_ch_lpm_dfe_n; + assign up_ch_rate_23 = up_ch_rate; + assign up_ch_sys_clk_sel_23 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_23 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_23 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_23 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_23 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_23 = up_ch_prbsforceerr; + assign up_ch_prbssel_23 = up_ch_prbssel; + assign up_ch_prbscntreset_23 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_23 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (23), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_23 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_22_s), + .up_rst_done_in (up_ch_rst_done_22_s), + .up_prbserr_in (up_ch_prbserr_22_s), + .up_prbslocked_in (up_ch_prbslocked_22_s), + .up_bufstatus_in (up_ch_bufstatus_22_s), + .up_pll_locked (up_ch_pll_locked_23), + .up_rst_done (up_ch_rst_done_23), + .up_prbserr (up_ch_prbserr_23), + .up_prbslocked (up_ch_prbslocked_23), + .up_bufstatus (up_ch_bufstatus_23), + .up_pll_locked_out (up_ch_pll_locked_23_s), + .up_rst_done_out (up_ch_rst_done_23_s), + .up_prbserr_out (up_ch_prbserr_23_s), + .up_prbslocked_out (up_ch_prbslocked_23_s), + .up_bufstatus_out (up_ch_bufstatus_23_s)); + + assign up_ch_addr_23 = up_ch_addr; + assign up_ch_wr_23 = up_ch_wr; + assign up_ch_wdata_23 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (23), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_23 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_23), + .up_rdata_in (up_ch_rdata_22_s), + .up_ready_in (up_ch_ready_22_s), + .up_rdata (up_ch_rdata_23), + .up_ready (up_ch_ready_23), + .up_rdata_out (up_ch_rdata_23_s), + .up_ready_out (up_ch_ready_23_s)); + + assign up_cm_addr_24 = up_cm_addr; + assign up_cm_wr_24 = up_cm_wr; + assign up_cm_wdata_24 = up_cm_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (24), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_cm_24 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_cm_sel), + .up_enb (up_cm_enb), + .up_enb_out (up_cm_enb_24), + .up_rdata_in (up_cm_rdata_20_s), + .up_ready_in (up_cm_ready_20_s), + .up_rdata (up_cm_rdata_24), + .up_ready (up_cm_ready_24), + .up_rdata_out (up_cm_rdata_24_s), + .up_ready_out (up_cm_ready_24_s)); + + assign up_es_addr_24 = up_es_addr; + assign up_es_wr_24 = up_es_wr; + assign up_es_wdata_24 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (24), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_24 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_24), + .up_rdata_in (up_es_rdata_23_s), + .up_ready_in (up_es_ready_23_s), + .up_rdata (up_es_rdata_24), + .up_ready (up_es_ready_24), + .up_rdata_out (up_es_rdata_24_s), + .up_ready_out (up_es_ready_24_s)); + + assign up_ch_rst_24 = up_ch_rst; + assign up_ch_user_ready_24 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_24 = up_ch_lpm_dfe_n; + assign up_ch_rate_24 = up_ch_rate; + assign up_ch_sys_clk_sel_24 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_24 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_24 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_24 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_24 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_24 = up_ch_prbsforceerr; + assign up_ch_prbssel_24 = up_ch_prbssel; + assign up_ch_prbscntreset_24 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_24 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (24), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_24 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_23_s), + .up_rst_done_in (up_ch_rst_done_23_s), + .up_prbserr_in (up_ch_prbserr_23_s), + .up_prbslocked_in (up_ch_prbslocked_23_s), + .up_bufstatus_in (up_ch_bufstatus_23_s), + .up_pll_locked (up_ch_pll_locked_24), + .up_rst_done (up_ch_rst_done_24), + .up_prbserr (up_ch_prbserr_24), + .up_prbslocked (up_ch_prbslocked_24), + .up_bufstatus (up_ch_bufstatus_24), + .up_pll_locked_out (up_ch_pll_locked_24_s), + .up_rst_done_out (up_ch_rst_done_24_s), + .up_prbserr_out (up_ch_prbserr_24_s), + .up_prbslocked_out (up_ch_prbslocked_24_s), + .up_bufstatus_out (up_ch_bufstatus_24_s)); + + assign up_ch_addr_24 = up_ch_addr; + assign up_ch_wr_24 = up_ch_wr; + assign up_ch_wdata_24 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (24), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_24 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_24), + .up_rdata_in (up_ch_rdata_23_s), + .up_ready_in (up_ch_ready_23_s), + .up_rdata (up_ch_rdata_24), + .up_ready (up_ch_ready_24), + .up_rdata_out (up_ch_rdata_24_s), + .up_ready_out (up_ch_ready_24_s)); + + assign up_es_addr_25 = up_es_addr; + assign up_es_wr_25 = up_es_wr; + assign up_es_wdata_25 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (25), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_25 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_25), + .up_rdata_in (up_es_rdata_24_s), + .up_ready_in (up_es_ready_24_s), + .up_rdata (up_es_rdata_25), + .up_ready (up_es_ready_25), + .up_rdata_out (up_es_rdata_25_s), + .up_ready_out (up_es_ready_25_s)); + + assign up_ch_rst_25 = up_ch_rst; + assign up_ch_user_ready_25 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_25 = up_ch_lpm_dfe_n; + assign up_ch_rate_25 = up_ch_rate; + assign up_ch_sys_clk_sel_25 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_25 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_25 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_25 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_25 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_25 = up_ch_prbsforceerr; + assign up_ch_prbssel_25 = up_ch_prbssel; + assign up_ch_prbscntreset_25 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_25 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (25), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_25 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_24_s), + .up_rst_done_in (up_ch_rst_done_24_s), + .up_prbserr_in (up_ch_prbserr_24_s), + .up_prbslocked_in (up_ch_prbslocked_24_s), + .up_bufstatus_in (up_ch_bufstatus_24_s), + .up_pll_locked (up_ch_pll_locked_25), + .up_rst_done (up_ch_rst_done_25), + .up_prbserr (up_ch_prbserr_25), + .up_prbslocked (up_ch_prbslocked_25), + .up_bufstatus (up_ch_bufstatus_25), + .up_pll_locked_out (up_ch_pll_locked_25_s), + .up_rst_done_out (up_ch_rst_done_25_s), + .up_prbserr_out (up_ch_prbserr_25_s), + .up_prbslocked_out (up_ch_prbslocked_25_s), + .up_bufstatus_out (up_ch_bufstatus_25_s)); + + assign up_ch_addr_25 = up_ch_addr; + assign up_ch_wr_25 = up_ch_wr; + assign up_ch_wdata_25 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (25), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_25 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_25), + .up_rdata_in (up_ch_rdata_24_s), + .up_ready_in (up_ch_ready_24_s), + .up_rdata (up_ch_rdata_25), + .up_ready (up_ch_ready_25), + .up_rdata_out (up_ch_rdata_25_s), + .up_ready_out (up_ch_ready_25_s)); + + assign up_es_addr_26 = up_es_addr; + assign up_es_wr_26 = up_es_wr; + assign up_es_wdata_26 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (26), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_26 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_26), + .up_rdata_in (up_es_rdata_25_s), + .up_ready_in (up_es_ready_25_s), + .up_rdata (up_es_rdata_26), + .up_ready (up_es_ready_26), + .up_rdata_out (up_es_rdata_26_s), + .up_ready_out (up_es_ready_26_s)); + + assign up_ch_rst_26 = up_ch_rst; + assign up_ch_user_ready_26 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_26 = up_ch_lpm_dfe_n; + assign up_ch_rate_26 = up_ch_rate; + assign up_ch_sys_clk_sel_26 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_26 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_26 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_26 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_26 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_26 = up_ch_prbsforceerr; + assign up_ch_prbssel_26 = up_ch_prbssel; + assign up_ch_prbscntreset_26 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_26 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (26), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_26 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_25_s), + .up_rst_done_in (up_ch_rst_done_25_s), + .up_prbserr_in (up_ch_prbserr_25_s), + .up_prbslocked_in (up_ch_prbslocked_25_s), + .up_bufstatus_in (up_ch_bufstatus_25_s), + .up_pll_locked (up_ch_pll_locked_26), + .up_rst_done (up_ch_rst_done_26), + .up_prbserr (up_ch_prbserr_26), + .up_prbslocked (up_ch_prbslocked_26), + .up_bufstatus (up_ch_bufstatus_26), + .up_pll_locked_out (up_ch_pll_locked_26_s), + .up_rst_done_out (up_ch_rst_done_26_s), + .up_prbserr_out (up_ch_prbserr_26_s), + .up_prbslocked_out (up_ch_prbslocked_26_s), + .up_bufstatus_out (up_ch_bufstatus_26_s)); + + assign up_ch_addr_26 = up_ch_addr; + assign up_ch_wr_26 = up_ch_wr; + assign up_ch_wdata_26 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (26), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_26 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_26), + .up_rdata_in (up_ch_rdata_25_s), + .up_ready_in (up_ch_ready_25_s), + .up_rdata (up_ch_rdata_26), + .up_ready (up_ch_ready_26), + .up_rdata_out (up_ch_rdata_26_s), + .up_ready_out (up_ch_ready_26_s)); + + assign up_es_addr_27 = up_es_addr; + assign up_es_wr_27 = up_es_wr; + assign up_es_wdata_27 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (27), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_27 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_27), + .up_rdata_in (up_es_rdata_26_s), + .up_ready_in (up_es_ready_26_s), + .up_rdata (up_es_rdata_27), + .up_ready (up_es_ready_27), + .up_rdata_out (up_es_rdata_27_s), + .up_ready_out (up_es_ready_27_s)); + + assign up_ch_rst_27 = up_ch_rst; + assign up_ch_user_ready_27 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_27 = up_ch_lpm_dfe_n; + assign up_ch_rate_27 = up_ch_rate; + assign up_ch_sys_clk_sel_27 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_27 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_27 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_27 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_27 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_27 = up_ch_prbsforceerr; + assign up_ch_prbssel_27 = up_ch_prbssel; + assign up_ch_prbscntreset_27 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_27 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (27), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_27 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_26_s), + .up_rst_done_in (up_ch_rst_done_26_s), + .up_prbserr_in (up_ch_prbserr_26_s), + .up_prbslocked_in (up_ch_prbslocked_26_s), + .up_bufstatus_in (up_ch_bufstatus_26_s), + .up_pll_locked (up_ch_pll_locked_27), + .up_rst_done (up_ch_rst_done_27), + .up_prbserr (up_ch_prbserr_27), + .up_prbslocked (up_ch_prbslocked_27), + .up_bufstatus (up_ch_bufstatus_27), + .up_pll_locked_out (up_ch_pll_locked_27_s), + .up_rst_done_out (up_ch_rst_done_27_s), + .up_prbserr_out (up_ch_prbserr_27_s), + .up_prbslocked_out (up_ch_prbslocked_27_s), + .up_bufstatus_out (up_ch_bufstatus_27_s)); + + assign up_ch_addr_27 = up_ch_addr; + assign up_ch_wr_27 = up_ch_wr; + assign up_ch_wdata_27 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (27), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_27 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_27), + .up_rdata_in (up_ch_rdata_26_s), + .up_ready_in (up_ch_ready_26_s), + .up_rdata (up_ch_rdata_27), + .up_ready (up_ch_ready_27), + .up_rdata_out (up_ch_rdata_27_s), + .up_ready_out (up_ch_ready_27_s)); + + assign up_cm_addr_28 = up_cm_addr; + assign up_cm_wr_28 = up_cm_wr; + assign up_cm_wdata_28 = up_cm_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (28), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_cm_28 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_cm_sel), + .up_enb (up_cm_enb), + .up_enb_out (up_cm_enb_28), + .up_rdata_in (up_cm_rdata_24_s), + .up_ready_in (up_cm_ready_24_s), + .up_rdata (up_cm_rdata_28), + .up_ready (up_cm_ready_28), + .up_rdata_out (up_cm_rdata_28_s), + .up_ready_out (up_cm_ready_28_s)); + + assign up_es_addr_28 = up_es_addr; + assign up_es_wr_28 = up_es_wr; + assign up_es_wdata_28 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (28), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_28 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_28), + .up_rdata_in (up_es_rdata_27_s), + .up_ready_in (up_es_ready_27_s), + .up_rdata (up_es_rdata_28), + .up_ready (up_es_ready_28), + .up_rdata_out (up_es_rdata_28_s), + .up_ready_out (up_es_ready_28_s)); + + assign up_ch_rst_28 = up_ch_rst; + assign up_ch_user_ready_28 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_28 = up_ch_lpm_dfe_n; + assign up_ch_rate_28 = up_ch_rate; + assign up_ch_sys_clk_sel_28 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_28 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_28 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_28 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_28 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_28 = up_ch_prbsforceerr; + assign up_ch_prbssel_28 = up_ch_prbssel; + assign up_ch_prbscntreset_28 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_28 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (28), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_28 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_27_s), + .up_rst_done_in (up_ch_rst_done_27_s), + .up_prbserr_in (up_ch_prbserr_27_s), + .up_prbslocked_in (up_ch_prbslocked_27_s), + .up_bufstatus_in (up_ch_bufstatus_27_s), + .up_pll_locked (up_ch_pll_locked_28), + .up_rst_done (up_ch_rst_done_28), + .up_prbserr (up_ch_prbserr_28), + .up_prbslocked (up_ch_prbslocked_28), + .up_bufstatus (up_ch_bufstatus_28), + .up_pll_locked_out (up_ch_pll_locked_28_s), + .up_rst_done_out (up_ch_rst_done_28_s), + .up_prbserr_out (up_ch_prbserr_28_s), + .up_prbslocked_out (up_ch_prbslocked_28_s), + .up_bufstatus_out (up_ch_bufstatus_28_s)); + + assign up_ch_addr_28 = up_ch_addr; + assign up_ch_wr_28 = up_ch_wr; + assign up_ch_wdata_28 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (28), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_28 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_28), + .up_rdata_in (up_ch_rdata_27_s), + .up_ready_in (up_ch_ready_27_s), + .up_rdata (up_ch_rdata_28), + .up_ready (up_ch_ready_28), + .up_rdata_out (up_ch_rdata_28_s), + .up_ready_out (up_ch_ready_28_s)); + + assign up_es_addr_29 = up_es_addr; + assign up_es_wr_29 = up_es_wr; + assign up_es_wdata_29 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (29), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_29 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_29), + .up_rdata_in (up_es_rdata_28_s), + .up_ready_in (up_es_ready_28_s), + .up_rdata (up_es_rdata_29), + .up_ready (up_es_ready_29), + .up_rdata_out (up_es_rdata_29_s), + .up_ready_out (up_es_ready_29_s)); + + assign up_ch_rst_29 = up_ch_rst; + assign up_ch_user_ready_29 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_29 = up_ch_lpm_dfe_n; + assign up_ch_rate_29 = up_ch_rate; + assign up_ch_sys_clk_sel_29 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_29 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_29 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_29 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_29 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_29 = up_ch_prbsforceerr; + assign up_ch_prbssel_29 = up_ch_prbssel; + assign up_ch_prbscntreset_29 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_29 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (29), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_29 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_28_s), + .up_rst_done_in (up_ch_rst_done_28_s), + .up_prbserr_in (up_ch_prbserr_28_s), + .up_prbslocked_in (up_ch_prbslocked_28_s), + .up_bufstatus_in (up_ch_bufstatus_28_s), + .up_pll_locked (up_ch_pll_locked_29), + .up_rst_done (up_ch_rst_done_29), + .up_prbserr (up_ch_prbserr_29), + .up_prbslocked (up_ch_prbslocked_29), + .up_bufstatus (up_ch_bufstatus_29), + .up_pll_locked_out (up_ch_pll_locked_29_s), + .up_rst_done_out (up_ch_rst_done_29_s), + .up_prbserr_out (up_ch_prbserr_29_s), + .up_prbslocked_out (up_ch_prbslocked_29_s), + .up_bufstatus_out (up_ch_bufstatus_29_s)); + + assign up_ch_addr_29 = up_ch_addr; + assign up_ch_wr_29 = up_ch_wr; + assign up_ch_wdata_29 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (29), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_29 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_29), + .up_rdata_in (up_ch_rdata_28_s), + .up_ready_in (up_ch_ready_28_s), + .up_rdata (up_ch_rdata_29), + .up_ready (up_ch_ready_29), + .up_rdata_out (up_ch_rdata_29_s), + .up_ready_out (up_ch_ready_29_s)); + + assign up_es_addr_30 = up_es_addr; + assign up_es_wr_30 = up_es_wr; + assign up_es_wdata_30 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (30), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_30 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_30), + .up_rdata_in (up_es_rdata_29_s), + .up_ready_in (up_es_ready_29_s), + .up_rdata (up_es_rdata_30), + .up_ready (up_es_ready_30), + .up_rdata_out (up_es_rdata_30_s), + .up_ready_out (up_es_ready_30_s)); + + assign up_ch_rst_30 = up_ch_rst; + assign up_ch_user_ready_30 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_30 = up_ch_lpm_dfe_n; + assign up_ch_rate_30 = up_ch_rate; + assign up_ch_sys_clk_sel_30 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_30 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_30 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_30 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_30 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_30 = up_ch_prbsforceerr; + assign up_ch_prbssel_30 = up_ch_prbssel; + assign up_ch_prbscntreset_30 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_30 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (30), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_30 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_29_s), + .up_rst_done_in (up_ch_rst_done_29_s), + .up_prbserr_in (up_ch_prbserr_29_s), + .up_prbslocked_in (up_ch_prbslocked_29_s), + .up_bufstatus_in (up_ch_bufstatus_29_s), + .up_pll_locked (up_ch_pll_locked_30), + .up_rst_done (up_ch_rst_done_30), + .up_prbserr (up_ch_prbserr_30), + .up_prbslocked (up_ch_prbslocked_30), + .up_bufstatus (up_ch_bufstatus_30), + .up_pll_locked_out (up_ch_pll_locked_30_s), + .up_rst_done_out (up_ch_rst_done_30_s), + .up_prbserr_out (up_ch_prbserr_30_s), + .up_prbslocked_out (up_ch_prbslocked_30_s), + .up_bufstatus_out (up_ch_bufstatus_30_s)); + + assign up_ch_addr_30 = up_ch_addr; + assign up_ch_wr_30 = up_ch_wr; + assign up_ch_wdata_30 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (30), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_30 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_30), + .up_rdata_in (up_ch_rdata_29_s), + .up_ready_in (up_ch_ready_29_s), + .up_rdata (up_ch_rdata_30), + .up_ready (up_ch_ready_30), + .up_rdata_out (up_ch_rdata_30_s), + .up_ready_out (up_ch_ready_30_s)); + + assign up_es_addr_31 = up_es_addr; + assign up_es_wr_31 = up_es_wr; + assign up_es_wdata_31 = up_es_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (31), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_es_31 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_es_sel), + .up_enb (up_es_enb), + .up_enb_out (up_es_enb_31), + .up_rdata_in (up_es_rdata_30_s), + .up_ready_in (up_es_ready_30_s), + .up_rdata (up_es_rdata_31), + .up_ready (up_es_ready_31), + .up_rdata_out (up_es_rdata_31_s), + .up_ready_out (up_es_ready_31_s)); + + assign up_ch_rst_31 = up_ch_rst; + assign up_ch_user_ready_31 = up_ch_user_ready; + assign up_ch_lpm_dfe_n_31 = up_ch_lpm_dfe_n; + assign up_ch_rate_31 = up_ch_rate; + assign up_ch_sys_clk_sel_31 = up_ch_sys_clk_sel; + assign up_ch_out_clk_sel_31 = up_ch_out_clk_sel; + assign up_ch_tx_diffctrl_31 = up_ch_tx_diffctrl; + assign up_ch_tx_postcursor_31 = up_ch_tx_postcursor; + assign up_ch_tx_precursor_31 = up_ch_tx_precursor; + assign up_ch_prbsforceerr_31 = up_ch_prbsforceerr; + assign up_ch_prbssel_31 = up_ch_prbssel; + assign up_ch_prbscntreset_31 = up_ch_prbscntreset; + assign up_ch_bufstatus_rst_31 = up_ch_bufstatus_rst; + + axi_adxcvr_mstatus #( + .XCVR_ID (31), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mstatus_ch_31 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_pll_locked_in (up_ch_pll_locked_30_s), + .up_rst_done_in (up_ch_rst_done_30_s), + .up_prbserr_in (up_ch_prbserr_30_s), + .up_prbslocked_in (up_ch_prbslocked_30_s), + .up_bufstatus_in (up_ch_bufstatus_30_s), + .up_pll_locked (up_ch_pll_locked_31), + .up_rst_done (up_ch_rst_done_31), + .up_prbserr (up_ch_prbserr_31), + .up_prbslocked (up_ch_prbslocked_31), + .up_bufstatus (up_ch_bufstatus_31), + .up_pll_locked_out (up_ch_pll_locked_31_s), + .up_rst_done_out (up_ch_rst_done_31_s), + .up_prbserr_out (up_ch_prbserr_31_s), + .up_prbslocked_out (up_ch_prbslocked_31_s), + .up_bufstatus_out (up_ch_bufstatus_31_s)); + + assign up_ch_addr_31 = up_ch_addr; + assign up_ch_wr_31 = up_ch_wr; + assign up_ch_wdata_31 = up_ch_wdata; + + axi_adxcvr_mdrp #( + .XCVR_ID (31), + .NUM_OF_LANES (NUM_OF_LANES) + ) i_mdrp_ch_31 ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_sel (up_ch_sel), + .up_enb (up_ch_enb), + .up_enb_out (up_ch_enb_31), + .up_rdata_in (up_ch_rdata_30_s), + .up_ready_in (up_ch_ready_30_s), + .up_rdata (up_ch_rdata_31), + .up_ready (up_ch_ready_31), + .up_rdata_out (up_ch_rdata_31_s), + .up_ready_out (up_ch_ready_31_s)); + + axi_adxcvr_es #( + .XCVR_TYPE (XCVR_TYPE), + .TX_OR_RX_N (TX_OR_RX_N) + ) i_es ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb), + .up_es_addr (up_es_addr), + .up_es_wr (up_es_wr), + .up_es_wdata (up_es_wdata), + .up_es_rdata (up_es_rdata_15_s), + .up_es_ready (up_es_ready_15_s), + .up_ch_lpm_dfe_n (up_ch_lpm_dfe_n), + .up_es_req (up_es_req), + .up_es_ack (up_es_ack), + .up_es_pscale (up_es_pscale), + .up_es_vrange (up_es_vrange), + .up_es_vstep (up_es_vstep), + .up_es_vmax (up_es_vmax), + .up_es_vmin (up_es_vmin), + .up_es_hmax (up_es_hmax), + .up_es_hmin (up_es_hmin), + .up_es_hstep (up_es_hstep), + .up_es_saddr (up_es_saddr), + .up_es_status (up_es_status), + .up_axi_awvalid (m_axi_awvalid), + .up_axi_awaddr (m_axi_awaddr), + .up_axi_awprot (m_axi_awprot), + .up_axi_awready (m_axi_awready), + .up_axi_wvalid (m_axi_wvalid), + .up_axi_wdata (m_axi_wdata), + .up_axi_wstrb (m_axi_wstrb), + .up_axi_wready (m_axi_wready), + .up_axi_bvalid (m_axi_bvalid), + .up_axi_bresp (m_axi_bresp), + .up_axi_bready (m_axi_bready), + .up_axi_arvalid (m_axi_arvalid), + .up_axi_araddr (m_axi_araddr), + .up_axi_arprot (m_axi_arprot), + .up_axi_arready (m_axi_arready), + .up_axi_rvalid (m_axi_rvalid), + .up_axi_rdata (m_axi_rdata), + .up_axi_rresp (m_axi_rresp), + .up_axi_rready (m_axi_rready)); + + axi_adxcvr_up #( + .ID (ID), + .LINK_MODE (LINK_MODE), + .NUM_OF_LANES (NUM_OF_LANES), + .XCVR_TYPE (XCVR_TYPE), + .FPGA_TECHNOLOGY(FPGA_TECHNOLOGY), + .FPGA_FAMILY(FPGA_FAMILY), + .SPEED_GRADE(SPEED_GRADE), + .DEV_PACKAGE(DEV_PACKAGE), + .FPGA_VOLTAGE(FPGA_VOLTAGE), + .TX_OR_RX_N (TX_OR_RX_N), + .QPLL_ENABLE (QPLL_ENABLE), + .LPM_OR_DFE_N (LPM_OR_DFE_N), + .RATE (RATE), + .TX_DIFFCTRL (TX_DIFFCTRL), + .TX_POSTCURSOR (TX_POSTCURSOR), + .TX_PRECURSOR (TX_PRECURSOR), + .SYS_CLK_SEL (SYS_CLK_SEL), + .OUT_CLK_SEL (OUT_CLK_SEL) + ) i_up ( + .up_cm_sel (up_cm_sel), + .up_cm_enb (up_cm_enb), + .up_cm_addr (up_cm_addr), + .up_cm_wr (up_cm_wr), + .up_cm_wdata (up_cm_wdata), + .up_cm_rdata (up_cm_rdata_12_s), + .up_cm_ready (up_cm_ready_12_s), + .up_ch_pll_locked (up_ch_pll_locked_15_s), + .up_ch_rst (up_ch_rst), + .up_ch_user_ready (up_ch_user_ready), + .up_ch_rst_done (up_ch_rst_done_15_s), + .up_ch_prbsforceerr (up_ch_prbsforceerr), + .up_ch_prbssel (up_ch_prbssel), + .up_ch_prbscntreset (up_ch_prbscntreset), + .up_ch_prbserr (up_ch_prbserr_15_s), + .up_ch_prbslocked (up_ch_prbslocked_15_s), + .up_ch_bufstatus (up_ch_bufstatus_15_s), + .up_ch_bufstatus_rst (up_ch_bufstatus_rst), + .up_ch_lpm_dfe_n (up_ch_lpm_dfe_n), + .up_ch_rate (up_ch_rate), + .up_ch_sys_clk_sel (up_ch_sys_clk_sel), + .up_ch_out_clk_sel (up_ch_out_clk_sel), + .up_ch_tx_diffctrl (up_ch_tx_diffctrl), + .up_ch_tx_postcursor (up_ch_tx_postcursor), + .up_ch_tx_precursor (up_ch_tx_precursor), + .up_ch_sel (up_ch_sel), + .up_ch_enb (up_ch_enb), + .up_ch_addr (up_ch_addr), + .up_ch_wr (up_ch_wr), + .up_ch_wdata (up_ch_wdata), + .up_ch_rdata (up_ch_rdata_15_s), + .up_ch_ready (up_ch_ready_15_s), + .up_es_sel (up_es_sel), + .up_es_req (up_es_req), + .up_es_ack (up_es_ack), + .up_es_reset (up_es_reset), + .up_es_pscale (up_es_pscale), + .up_es_vrange (up_es_vrange), + .up_es_vstep (up_es_vstep), + .up_es_vmax (up_es_vmax), + .up_es_vmin (up_es_vmin), + .up_es_hmax (up_es_hmax), + .up_es_hmin (up_es_hmin), + .up_es_hstep (up_es_hstep), + .up_es_saddr (up_es_saddr), + .up_es_status (up_es_status), + .up_status (up_status), + .up_pll_rst (up_pll_rst), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + + up_axi #( + .AXI_ADDRESS_WIDTH (12) + ) i_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq), + .up_waddr (up_waddr), + .up_wdata (up_wdata), + .up_wack (up_wack), + .up_rreq (up_rreq), + .up_raddr (up_raddr), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/xilinx/axi_adxcvr/axi_adxcvr.xpr b/adi_library/xilinx/axi_adxcvr/axi_adxcvr.xpr new file mode 100644 index 00000000..fa43b425 --- /dev/null +++ b/adi_library/xilinx/axi_adxcvr/axi_adxcvr.xpr @@ -0,0 +1,448 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v b/adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v new file mode 100644 index 00000000..1dd81b3d --- /dev/null +++ b/adi_library/xilinx/axi_adxcvr/axi_adxcvr_es.v @@ -0,0 +1,570 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adxcvr_es ( + + // up interface + + input up_rstn, + input up_clk, + output up_es_enb, + output [11:0] up_es_addr, + output up_es_wr, + output [15:0] up_es_wdata, + input [15:0] up_es_rdata, + input up_es_ready, + input up_ch_lpm_dfe_n, + input up_es_req, + output up_es_ack, + input [ 4:0] up_es_pscale, + input [ 1:0] up_es_vrange, + input [ 7:0] up_es_vstep, + input [ 7:0] up_es_vmax, + input [ 7:0] up_es_vmin, + input [11:0] up_es_hmax, + input [11:0] up_es_hmin, + input [11:0] up_es_hstep, + input [31:0] up_es_saddr, + output up_es_status, + + // axi interface + + output up_axi_awvalid, + output [31:0] up_axi_awaddr, + output [ 2:0] up_axi_awprot, + input up_axi_awready, + output up_axi_wvalid, + output [31:0] up_axi_wdata, + output [ 3:0] up_axi_wstrb, + input up_axi_wready, + input up_axi_bvalid, + input [ 1:0] up_axi_bresp, + output up_axi_bready, + output up_axi_arvalid, + output [31:0] up_axi_araddr, + output [ 2:0] up_axi_arprot, + input up_axi_arready, + input up_axi_rvalid, + input [31:0] up_axi_rdata, + input [ 1:0] up_axi_rresp, + output up_axi_rready +); + + // parameters + + parameter integer XCVR_TYPE = 0; + parameter integer TX_OR_RX_N = 0; + + // local parameters + + localparam GTXE2 = 2; + localparam GTHE3 = 5; + localparam GTHE4 = 8; + localparam GTYE4 = 9; + + // addresses + + localparam [11:0] ES_DRP_CTRL_ADDR = (XCVR_TYPE == GTXE2) ? 12'h03d : (XCVR_TYPE == GTHE3) ? 12'h03c : 12'h03c; + localparam [11:0] ES_DRP_HOFFSET_ADDR = (XCVR_TYPE == GTXE2) ? 12'h03c : (XCVR_TYPE == GTHE3) ? 12'h04f : 12'h04f; + localparam [11:0] ES_DRP_VOFFSET_ADDR = (XCVR_TYPE == GTXE2) ? 12'h03b : (XCVR_TYPE == GTHE3) ? 12'h097 : 12'h097; + localparam [11:0] ES_DRP_STATUS_ADDR = (XCVR_TYPE == GTXE2) ? 12'h151 : (XCVR_TYPE == GTHE3) ? 12'h153 : 12'h253; + localparam [11:0] ES_DRP_SCNT_ADDR = (XCVR_TYPE == GTXE2) ? 12'h150 : (XCVR_TYPE == GTHE3) ? 12'h152 : 12'h252; + localparam [11:0] ES_DRP_ECNT_ADDR = (XCVR_TYPE == GTXE2) ? 12'h14f : (XCVR_TYPE == GTHE3) ? 12'h151 : 12'h251; + + // fsm-states + + localparam [ 4:0] ES_FSM_IDLE = 6'h00; + localparam [ 4:0] ES_FSM_HOFFSET_READ = 6'h01; + localparam [ 4:0] ES_FSM_HOFFSET_RRDY = 6'h02; + localparam [ 4:0] ES_FSM_HOFFSET_WRITE = 6'h03; + localparam [ 4:0] ES_FSM_HOFFSET_WRDY = 6'h04; + localparam [ 4:0] ES_FSM_VOFFSET_READ = 6'h05; + localparam [ 4:0] ES_FSM_VOFFSET_RRDY = 6'h06; + localparam [ 4:0] ES_FSM_VOFFSET_WRITE = 6'h07; + localparam [ 4:0] ES_FSM_VOFFSET_WRDY = 6'h08; + localparam [ 4:0] ES_FSM_CTRL_READ = 6'h09; + localparam [ 4:0] ES_FSM_CTRL_RRDY = 6'h0a; + localparam [ 4:0] ES_FSM_START_WRITE = 6'h0b; + localparam [ 4:0] ES_FSM_START_WRDY = 6'h0c; + localparam [ 4:0] ES_FSM_STATUS_READ = 6'h0d; + localparam [ 4:0] ES_FSM_STATUS_RRDY = 6'h0e; + localparam [ 4:0] ES_FSM_STOP_WRITE = 6'h0f; + localparam [ 4:0] ES_FSM_STOP_WRDY = 6'h10; + localparam [ 4:0] ES_FSM_SCNT_READ = 6'h11; + localparam [ 4:0] ES_FSM_SCNT_RRDY = 6'h12; + localparam [ 4:0] ES_FSM_ECNT_READ = 6'h13; + localparam [ 4:0] ES_FSM_ECNT_RRDY = 6'h14; + localparam [ 4:0] ES_FSM_AXI_WRITE = 6'h15; + localparam [ 4:0] ES_FSM_AXI_READY = 6'h16; + localparam [ 4:0] ES_FSM_UPDATE = 6'h17; + + // internal registers + + reg up_awvalid = 'd0; + reg [31:0] up_awaddr = 'd0; + reg up_wvalid = 'd0; + reg [31:0] up_wdata = 'd0; + reg up_status = 'd0; + reg up_ut = 'd0; + reg [31:0] up_daddr = 'd0; + reg [11:0] up_hindex = 'd0; + reg [ 7:0] up_vindex = 'd0; + reg [15:0] up_hdata = 'd0; + reg [15:0] up_vdata = 'd0; + reg [15:0] up_cdata = 'd0; + reg [15:0] up_sdata = 'd0; + reg [15:0] up_edata = 'd0; + reg up_req_d = 'd0; + reg up_ack = 'd0; + reg [ 4:0] up_fsm = 'd0; + reg up_enb = 'd0; + reg [11:0] up_addr = 'd0; + reg up_wr = 'd0; + reg [15:0] up_data = 'd0; + + // internal signals + + wire up_heos_s; + wire up_eos_s; + wire up_ut_s; + wire [ 7:0] up_vindex_m_s; + wire [ 7:0] up_vindex_n_s; + wire [ 7:0] up_vindex_s; + wire up_start_s; + + // axi interface + + generate + if (TX_OR_RX_N == 1) begin + assign up_axi_awvalid = 1'b0; + assign up_axi_awaddr = 32'd0; + assign up_axi_awprot = 3'd0; + assign up_axi_wvalid = 1'b0; + assign up_axi_wdata = 32'd0; + assign up_axi_wstrb = 4'hf; + assign up_axi_bready = 1'b1; + assign up_axi_arvalid = 1'b0; + assign up_axi_araddr = 32'd0; + assign up_axi_arprot = 3'd0; + assign up_axi_rready = 1'b1; + end else begin + assign up_axi_awvalid = up_awvalid; + assign up_axi_awaddr = up_awaddr; + assign up_axi_awprot = 3'd0; + assign up_axi_wvalid = up_wvalid; + assign up_axi_wdata = up_wdata; + assign up_axi_wstrb = 4'hf; + assign up_axi_bready = 1'b1; + assign up_axi_arvalid = 1'b0; + assign up_axi_araddr = 32'd0; + assign up_axi_arprot = 3'd0; + assign up_axi_rready = 1'b1; + end + endgenerate + + // reconfig interface + + generate + if (TX_OR_RX_N == 1) begin + assign up_es_ack = 1'b1; + assign up_es_enb = 1'b0; + assign up_es_addr = 12'd0; + assign up_es_wr = 1'd0; + assign up_es_wdata = 16'd0; + assign up_es_status = 1'd0; + end else begin + assign up_es_ack = up_ack; + assign up_es_enb = up_enb; + assign up_es_addr = up_addr; + assign up_es_wr = up_wr; + assign up_es_wdata = up_data; + assign up_es_status = up_status; + end + endgenerate + + // axi write + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_awvalid <= 'b0; + up_awaddr <= 'd0; + up_wvalid <= 'b0; + up_wdata <= 'd0; + up_status <= 'd0; + end else begin + if ((up_awvalid == 1'b1) && (up_axi_awready == 1'b1)) begin + up_awvalid <= 1'b0; + up_awaddr <= 32'd0; + end else if (up_fsm == ES_FSM_AXI_WRITE) begin + up_awvalid <= 1'b1; + up_awaddr <= up_daddr; + end + if ((up_wvalid == 1'b1) && (up_axi_wready == 1'b1)) begin + up_wvalid <= 1'b0; + up_wdata <= 32'd0; + end else if (up_fsm == ES_FSM_AXI_WRITE) begin + up_wvalid <= 1'b1; + up_wdata <= {up_sdata, up_edata}; + end + if (up_axi_bvalid == 1'b1) begin + up_status <= | up_axi_bresp; + end + end + end + + // prescale, horizontal and vertical offsets + + assign up_heos_s = (up_hindex == up_es_hmax) ? up_ut : 1'b0; + assign up_eos_s = (up_vindex == up_es_vmax) ? up_heos_s : 1'b0; + + assign up_ut_s = up_ut & ~up_ch_lpm_dfe_n; + assign up_vindex_m_s = ~up_vindex + 1'b1; + assign up_vindex_n_s = {1'b1, up_vindex_m_s[6:0]}; + assign up_vindex_s = (up_vindex[7] == 1'b1) ? up_vindex_n_s : up_vindex; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_ut <= 'd0; + up_daddr <= 'd0; + up_hindex <= 'd0; + up_vindex <= 'd0; + end else begin + if (up_fsm == ES_FSM_IDLE) begin + up_ut <= up_ch_lpm_dfe_n; + up_daddr <= up_es_saddr; + up_hindex <= up_es_hmin; + up_vindex <= up_es_vmin; + end else if (up_fsm == ES_FSM_UPDATE) begin + up_ut <= ~up_ut | up_ch_lpm_dfe_n; + up_daddr <= up_daddr + 3'd4; + if (up_heos_s == 1'b1) begin + up_hindex <= up_es_hmin; + end else if (up_ut == 1'b1) begin + up_hindex <= up_hindex + up_es_hstep; + end + if (up_heos_s == 1'b1) begin + up_vindex <= up_vindex + up_es_vstep; + end + end + end + end + + // read-modify-write + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_hdata <= 'd0; + up_vdata <= 'd0; + up_cdata <= 'd0; + up_sdata <= 'd0; + up_edata <= 'd0; + end else begin + if ((up_fsm == ES_FSM_HOFFSET_RRDY) && (up_es_ready == 1'b1)) begin + up_hdata <= up_es_rdata; + end + if ((up_fsm == ES_FSM_VOFFSET_RRDY) && (up_es_ready == 1'b1)) begin + up_vdata <= up_es_rdata; + end + if ((up_fsm == ES_FSM_CTRL_RRDY) && (up_es_ready == 1'b1)) begin + up_cdata <= up_es_rdata; + end + if ((up_fsm == ES_FSM_SCNT_RRDY) && (up_es_ready == 1'b1)) begin + up_sdata <= up_es_rdata; + end + if ((up_fsm == ES_FSM_ECNT_RRDY) && (up_es_ready == 1'b1)) begin + up_edata <= up_es_rdata; + end + end + end + + // request, start and ack + + assign up_start_s = up_es_req & ~up_req_d; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_req_d <= 1'b0; + up_ack <= 1'b0; + end else begin + up_req_d <= up_es_req; + if (up_fsm == ES_FSM_UPDATE) begin + up_ack <= up_eos_s | ~up_es_req; + end else begin + up_ack <= 1'b0; + end + end + end + + // es-fsm + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_fsm <= ES_FSM_IDLE; + end else begin + case (up_fsm) + ES_FSM_IDLE: begin + if (up_start_s == 1'b1) begin + up_fsm <= ES_FSM_HOFFSET_READ; + end else begin + up_fsm <= ES_FSM_IDLE; + end + end + ES_FSM_HOFFSET_READ: begin + up_fsm <= ES_FSM_HOFFSET_RRDY; + end + ES_FSM_HOFFSET_RRDY: begin + if (up_es_ready == 1'b1) begin + up_fsm <= ES_FSM_HOFFSET_WRITE; + end else begin + up_fsm <= ES_FSM_HOFFSET_RRDY; + end + end + ES_FSM_HOFFSET_WRITE: begin + up_fsm <= ES_FSM_HOFFSET_WRDY; + end + ES_FSM_HOFFSET_WRDY: begin + if (up_es_ready == 1'b1) begin + up_fsm <= ES_FSM_VOFFSET_READ; + end else begin + up_fsm <= ES_FSM_HOFFSET_WRDY; + end + end + ES_FSM_VOFFSET_READ: begin + up_fsm <= ES_FSM_VOFFSET_RRDY; + end + ES_FSM_VOFFSET_RRDY: begin + if (up_es_ready == 1'b1) begin + up_fsm <= ES_FSM_VOFFSET_WRITE; + end else begin + up_fsm <= ES_FSM_VOFFSET_RRDY; + end + end + ES_FSM_VOFFSET_WRITE: begin + up_fsm <= ES_FSM_VOFFSET_WRDY; + end + ES_FSM_VOFFSET_WRDY: begin + if (up_es_ready == 1'b1) begin + up_fsm <= ES_FSM_CTRL_READ; + end else begin + up_fsm <= ES_FSM_VOFFSET_WRDY; + end + end + ES_FSM_CTRL_READ: begin + up_fsm <= ES_FSM_CTRL_RRDY; + end + ES_FSM_CTRL_RRDY: begin + if (up_es_ready == 1'b1) begin + up_fsm <= ES_FSM_START_WRITE; + end else begin + up_fsm <= ES_FSM_CTRL_RRDY; + end + end + ES_FSM_START_WRITE: begin + up_fsm <= ES_FSM_START_WRDY; + end + ES_FSM_START_WRDY: begin + if (up_es_ready == 1'b1) begin + up_fsm <= ES_FSM_STATUS_READ; + end else begin + up_fsm <= ES_FSM_START_WRDY; + end + end + ES_FSM_STATUS_READ: begin + up_fsm <= ES_FSM_STATUS_RRDY; + end + ES_FSM_STATUS_RRDY: begin + if (up_es_ready == 1'b0) begin + up_fsm <= ES_FSM_STATUS_RRDY; + end else if (up_es_rdata[3:0] == 4'b0101) begin + up_fsm <= ES_FSM_STOP_WRITE; + end else begin + up_fsm <= ES_FSM_STATUS_READ; + end + end + ES_FSM_STOP_WRITE: begin + up_fsm <= ES_FSM_STOP_WRDY; + end + ES_FSM_STOP_WRDY: begin + if (up_es_ready == 1'b1) begin + up_fsm <= ES_FSM_SCNT_READ; + end else begin + up_fsm <= ES_FSM_STOP_WRDY; + end + end + ES_FSM_SCNT_READ: begin + up_fsm <= ES_FSM_SCNT_RRDY; + end + ES_FSM_SCNT_RRDY: begin + if (up_es_ready == 1'b1) begin + up_fsm <= ES_FSM_ECNT_READ; + end else begin + up_fsm <= ES_FSM_SCNT_RRDY; + end + end + ES_FSM_ECNT_READ: begin + up_fsm <= ES_FSM_ECNT_RRDY; + end + ES_FSM_ECNT_RRDY: begin + if (up_es_ready == 1'b1) begin + up_fsm <= ES_FSM_AXI_WRITE; + end else begin + up_fsm <= ES_FSM_ECNT_RRDY; + end + end + ES_FSM_AXI_WRITE: begin + up_fsm <= ES_FSM_AXI_READY; + end + ES_FSM_AXI_READY: begin + if (up_axi_bvalid == 1'b1) begin + up_fsm <= ES_FSM_UPDATE; + end else begin + up_fsm <= ES_FSM_AXI_READY; + end + end + ES_FSM_UPDATE: begin + if ((up_eos_s == 1'b1) || (up_es_req == 1'b0)) begin + up_fsm <= ES_FSM_IDLE; + end else if (up_ut == 1'b1) begin + up_fsm <= ES_FSM_HOFFSET_READ; + end else begin + up_fsm <= ES_FSM_VOFFSET_READ; + end + end + default: begin + up_fsm <= ES_FSM_IDLE; + end + endcase + end + end + + // channel access + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_enb <= 'd0; + up_addr <= 'd0; + up_wr <= 'd0; + up_data <= 'd0; + end else begin + case (up_fsm) + ES_FSM_HOFFSET_READ: begin + up_enb <= 1'b1; + up_addr <= ES_DRP_HOFFSET_ADDR; + up_wr <= 1'b0; + up_data <= 16'h0000; + end + ES_FSM_HOFFSET_WRITE: begin + up_enb <= 1'b1; + up_addr <= ES_DRP_HOFFSET_ADDR; + up_wr <= 1'b1; + if (XCVR_TYPE != GTXE2) begin + up_data <= {up_hindex, up_hdata[3:0]}; + end else begin + up_data <= {up_hdata[15:12], up_hindex}; + end + end + ES_FSM_VOFFSET_READ: begin + up_enb <= 1'b1; + up_addr <= ES_DRP_VOFFSET_ADDR; + up_wr <= 1'b0; + up_data <= 16'h0000; + end + ES_FSM_VOFFSET_WRITE: begin + up_enb <= 1'b1; + up_addr <= ES_DRP_VOFFSET_ADDR; + up_wr <= 1'b1; + if (XCVR_TYPE != GTXE2) begin + up_data <= {up_vdata[15:11], up_vindex_s[7], up_ut_s, up_vindex_s[6:0], up_es_vrange}; + end else begin + up_data <= {up_es_pscale, up_vdata[10:9], up_ut_s, up_vindex_s}; + end + end + ES_FSM_CTRL_READ: begin + up_enb <= 1'b1; + up_addr <= ES_DRP_CTRL_ADDR; + up_wr <= 1'b0; + up_data <= 16'h0000; + end + ES_FSM_START_WRITE: begin + up_enb <= 1'b1; + up_addr <= ES_DRP_CTRL_ADDR; + up_wr <= 1'b1; + if (XCVR_TYPE != GTXE2) begin + up_data <= {6'd1, 2'b11, up_cdata[7:5], up_es_pscale}; + end else begin + up_data <= {up_cdata[15:10], 2'b11, up_cdata[7:6], 6'd1}; + end + end + ES_FSM_STATUS_READ: begin + up_enb <= 1'b1; + up_addr <= ES_DRP_STATUS_ADDR; + up_wr <= 1'b0; + up_data <= 16'h0000; + end + ES_FSM_STOP_WRITE: begin + up_enb <= 1'b1; + up_addr <= ES_DRP_CTRL_ADDR; + up_wr <= 1'b1; + if (XCVR_TYPE != GTXE2) begin + up_data <= {6'd0, 2'b11, up_cdata[7:5], up_es_pscale}; + end else begin + up_data <= {up_cdata[15:10], 2'b11, up_cdata[7:6], 6'd0}; + end + end + ES_FSM_SCNT_READ: begin + up_enb <= 1'b1; + up_addr <= ES_DRP_SCNT_ADDR; + up_wr <= 1'b0; + up_data <= 16'h0000; + end + ES_FSM_ECNT_READ: begin + up_enb <= 1'b1; + up_addr <= ES_DRP_ECNT_ADDR; + up_wr <= 1'b0; + up_data <= 16'h0000; + end + default: begin + up_enb <= 1'b0; + up_addr <= 9'h000; + up_wr <= 1'b0; + up_data <= 16'h0000; + end + endcase + end + end + +endmodule diff --git a/adi_library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl b/adi_library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl new file mode 100644 index 00000000..9cc9cb53 --- /dev/null +++ b/adi_library/xilinx/axi_adxcvr/axi_adxcvr_ip.tcl @@ -0,0 +1,417 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +## AUTO GENERATED BY axi_adxcvr.pl, DO NOT MODIFY! +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_adxcvr +adi_ip_files axi_adxcvr [list \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \ + "axi_adxcvr_es.v" \ + "axi_adxcvr_up.v" \ + "axi_adxcvr_mdrp.v" \ + "axi_adxcvr_mstatus.v" \ + "axi_adxcvr.v" ] + +adi_ip_properties axi_adxcvr +adi_ip_infer_mm_interfaces axi_adxcvr + +adi_init_bd_tcl +adi_ip_bd axi_adxcvr "bd/bd.tcl" + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/axi_adxcvr} [ipx::current_core] + +set cc [ipx::current_core] + +# Arrange GUI page layout +set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] +# Link layer mode +set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $page0 +set_property -dict [list \ + "display_name" "Link Layer mode" \ + "tooltip" "Link Layer mode" \ + "widget" "comboBox" \ +] $p + +set_property -dict [list \ + value_validation_type pairs \ + value_validation_pairs {64B66B 2 8B10B 1} \ +] [ipx::get_user_parameters $p -of_objects $cc] + +set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]] + +set_property master_address_space_ref m_axi \ + [ipx::get_bus_interfaces m_axi \ + -of_objects [ipx::current_core]] + +for {set n 0} {$n < 32} {incr n} { + + if {($n%4) == 0} { + adi_if_infer_bus analog.com:interface:if_xcvr_cm master up_cm_${n} [list \ + "enb up_cm_enb_${n} "\ + "addr up_cm_addr_${n} "\ + "wr up_cm_wr_${n} "\ + "wdata up_cm_wdata_${n} "\ + "rdata up_cm_rdata_${n} "\ + "ready up_cm_ready_${n} "] + } + + adi_if_infer_bus analog.com:interface:if_xcvr_cm master up_es_${n} [list \ + "enb up_es_enb_${n} "\ + "addr up_es_addr_${n} "\ + "wr up_es_wr_${n} "\ + "reset up_es_reset_${n} "\ + "wdata up_es_wdata_${n} "\ + "rdata up_es_rdata_${n} "\ + "ready up_es_ready_${n} "] + + adi_if_infer_bus analog.com:interface:if_xcvr_ch master up_ch_${n} [list \ + "pll_locked up_ch_pll_locked_${n} "\ + "rst up_ch_rst_${n} "\ + "user_ready up_ch_user_ready_${n} "\ + "rst_done up_ch_rst_done_${n} "\ + "prbsforceerr up_ch_prbsforceerr_${n}"\ + "prbssel up_ch_prbssel_${n} "\ + "prbscntreset up_ch_prbscntreset_${n}"\ + "prbserr up_ch_prbserr_${n} "\ + "prbslocked up_ch_prbslocked_${n} "\ + "bufstatus up_ch_bufstatus_${n} "\ + "bufstatus_rst up_ch_bufstatus_rst_${n}"\ + "lpm_dfe_n up_ch_lpm_dfe_n_${n} "\ + "rate up_ch_rate_${n} "\ + "sys_clk_sel up_ch_sys_clk_sel_${n} "\ + "out_clk_sel up_ch_out_clk_sel_${n} "\ + "tx_diffctrl up_ch_tx_diffctrl_${n} "\ + "tx_postcursor up_ch_tx_postcursor_${n} "\ + "tx_precursor up_ch_tx_precursor_${n} "\ + "enb up_ch_enb_${n} "\ + "addr up_ch_addr_${n} "\ + "wr up_ch_wr_${n} "\ + "wdata up_ch_wdata_${n} "\ + "rdata up_ch_rdata_${n} "\ + "ready up_ch_ready_${n} "] + +} + +ipx::infer_bus_interface up_pll_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] +ipx::add_bus_parameter POLARITY [ipx::get_bus_interfaces up_pll_rst -of_objects [ipx::current_core]] +set_property VALUE ACTIVE_HIGH [ipx::get_bus_parameters POLARITY -of [ipx::get_bus_interfaces up_pll_rst]] + +ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +ipx::associate_bus_interfaces -clock s_axi_aclk -reset up_pll_rst -remove [ipx::current_core] + +set_property value s_axi:m_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ + -of_objects [ipx::get_bus_interfaces s_axi_aclk -of_objects [ipx::current_core]]] + +set_property enablement_dependency \ + {spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0} \ + [ipx::get_bus_interfaces m_axi -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0))} \ + [ipx::get_bus_interfaces up_es_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0} \ + [ipx::get_bus_interfaces up_ch_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 0))} \ + [ipx::get_bus_interfaces up_cm_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1))} \ + [ipx::get_bus_interfaces up_es_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 1} \ + [ipx::get_bus_interfaces up_ch_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2))} \ + [ipx::get_bus_interfaces up_es_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 2} \ + [ipx::get_bus_interfaces up_ch_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3))} \ + [ipx::get_bus_interfaces up_es_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 3} \ + [ipx::get_bus_interfaces up_ch_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4))} \ + [ipx::get_bus_interfaces up_es_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4} \ + [ipx::get_bus_interfaces up_ch_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 4))} \ + [ipx::get_bus_interfaces up_cm_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5))} \ + [ipx::get_bus_interfaces up_es_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 5} \ + [ipx::get_bus_interfaces up_ch_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6))} \ + [ipx::get_bus_interfaces up_es_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 6} \ + [ipx::get_bus_interfaces up_ch_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7))} \ + [ipx::get_bus_interfaces up_es_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 7} \ + [ipx::get_bus_interfaces up_ch_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8))} \ + [ipx::get_bus_interfaces up_es_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8} \ + [ipx::get_bus_interfaces up_ch_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 8))} \ + [ipx::get_bus_interfaces up_cm_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 9))} \ + [ipx::get_bus_interfaces up_es_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 9} \ + [ipx::get_bus_interfaces up_ch_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 10))} \ + [ipx::get_bus_interfaces up_es_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 10} \ + [ipx::get_bus_interfaces up_ch_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 11))} \ + [ipx::get_bus_interfaces up_es_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 11} \ + [ipx::get_bus_interfaces up_ch_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12))} \ + [ipx::get_bus_interfaces up_es_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12} \ + [ipx::get_bus_interfaces up_ch_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 12))} \ + [ipx::get_bus_interfaces up_cm_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 13))} \ + [ipx::get_bus_interfaces up_es_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 13} \ + [ipx::get_bus_interfaces up_ch_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 14))} \ + [ipx::get_bus_interfaces up_es_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 14} \ + [ipx::get_bus_interfaces up_ch_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 15))} \ + [ipx::get_bus_interfaces up_es_15 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 15} \ + [ipx::get_bus_interfaces up_ch_15 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 16))} \ + [ipx::get_bus_interfaces up_es_16 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 16} \ + [ipx::get_bus_interfaces up_ch_16 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 16))} \ + [ipx::get_bus_interfaces up_cm_16 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 17))} \ + [ipx::get_bus_interfaces up_es_17 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 17} \ + [ipx::get_bus_interfaces up_ch_17 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 18))} \ + [ipx::get_bus_interfaces up_es_18 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 18} \ + [ipx::get_bus_interfaces up_ch_18 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 19))} \ + [ipx::get_bus_interfaces up_es_19 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 19} \ + [ipx::get_bus_interfaces up_ch_19 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 20))} \ + [ipx::get_bus_interfaces up_es_20 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 20} \ + [ipx::get_bus_interfaces up_ch_20 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 20))} \ + [ipx::get_bus_interfaces up_cm_20 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 21))} \ + [ipx::get_bus_interfaces up_es_21 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 21} \ + [ipx::get_bus_interfaces up_ch_21 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 22))} \ + [ipx::get_bus_interfaces up_es_22 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 22} \ + [ipx::get_bus_interfaces up_ch_22 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 23))} \ + [ipx::get_bus_interfaces up_es_23 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 23} \ + [ipx::get_bus_interfaces up_ch_23 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 24))} \ + [ipx::get_bus_interfaces up_es_24 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 24} \ + [ipx::get_bus_interfaces up_ch_24 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 24))} \ + [ipx::get_bus_interfaces up_cm_24 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 25))} \ + [ipx::get_bus_interfaces up_es_25 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 25} \ + [ipx::get_bus_interfaces up_ch_25 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 26))} \ + [ipx::get_bus_interfaces up_es_26 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 26} \ + [ipx::get_bus_interfaces up_ch_26 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 27))} \ + [ipx::get_bus_interfaces up_es_27 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 27} \ + [ipx::get_bus_interfaces up_ch_27 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 28))} \ + [ipx::get_bus_interfaces up_es_28 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 28} \ + [ipx::get_bus_interfaces up_ch_28 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.QPLL_ENABLE')) = 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 28))} \ + [ipx::get_bus_interfaces up_cm_28 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 29))} \ + [ipx::get_bus_interfaces up_es_29 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 29} \ + [ipx::get_bus_interfaces up_ch_29 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 30))} \ + [ipx::get_bus_interfaces up_es_30 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 30} \ + [ipx::get_bus_interfaces up_ch_30 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {((spirit:decode(id('MODELPARAM_VALUE.TX_OR_RX_N')) = 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 31))} \ + [ipx::get_bus_interfaces up_es_31 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.NUM_OF_LANES')) > 31} \ + [ipx::get_bus_interfaces up_ch_31 -of_objects [ipx::current_core]] + +adi_add_auto_fpga_spec_params +ipx::create_xgui_files [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v b/adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v new file mode 100644 index 00000000..b705dfa6 --- /dev/null +++ b/adi_library/xilinx/axi_adxcvr/axi_adxcvr_mdrp.v @@ -0,0 +1,159 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module axi_adxcvr_mdrp ( + + input up_rstn, + input up_clk, + + input [ 7:0] up_sel, + input up_enb, + output up_enb_out, + input [15:0] up_rdata_in, + input up_ready_in, + input [15:0] up_rdata, + input up_ready, + output [15:0] up_rdata_out, + output up_ready_out +); + + // parameters + + parameter integer XCVR_ID = 0; + parameter integer NUM_OF_LANES = 8; + + // internal registers + + reg [15:0] up_rdata_int = 'd0; + reg up_ready_int = 'd0; + reg up_ready_mi = 'd0; + reg [15:0] up_rdata_i = 'd0; + reg up_ready_i = 'd0; + reg [15:0] up_rdata_m = 'd0; + reg up_ready_m = 'd0; + + // internal signals + + wire up_ready_s; + wire [15:0] up_rdata_mi_s; + wire up_ready_mi_s; + + // disable if not selected + + assign up_rdata_out = up_rdata_int; + assign up_ready_out = up_ready_int; + + assign up_enb_out = (up_sel == 8'hff || up_sel == XCVR_ID) ? up_enb : 1'b0; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_rdata_int <= 16'd0; + up_ready_int <= 1'b0; + end else begin + case (up_sel) + 8'hff: begin + up_rdata_int <= up_rdata_mi_s; + up_ready_int <= up_ready_mi_s & ~up_ready_mi; + end + XCVR_ID: begin + up_rdata_int <= up_rdata; + up_ready_int <= up_ready; + end + default: begin + up_rdata_int <= up_rdata_in; + up_ready_int <= up_ready_in; + end + endcase + end + end + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_ready_mi <= 1'b0; + end else begin + up_ready_mi <= up_ready_mi_s; + end + end + + assign up_rdata_mi_s = up_rdata_m | up_rdata_i; + assign up_ready_mi_s = up_ready_m & up_ready_i; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_rdata_i <= 16'd0; + up_ready_i <= 1'b0; + end else begin + if (up_ready_in == 1'b1 || XCVR_ID == 0) begin + up_rdata_i <= up_rdata_in; + up_ready_i <= 1'b1; + end else if (up_enb == 1'b1) begin + up_rdata_i <= 16'd0; + up_ready_i <= 1'b0; + end + end + end + + generate + if (XCVR_ID < NUM_OF_LANES) begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_rdata_m <= 16'd0; + up_ready_m <= 1'b0; + end else begin + if (up_ready == 1'b1) begin + up_rdata_m <= up_rdata; + up_ready_m <= 1'b1; + end else if (up_enb == 1'b1) begin + up_rdata_m <= 16'd0; + up_ready_m <= 1'b0; + end + end + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_rdata_m <= 16'd0; + up_ready_m <= 1'b0; + end else begin + up_rdata_m <= 16'd0; + up_ready_m <= 1'b1; + end + end + end + endgenerate + +endmodule diff --git a/adi_library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v b/adi_library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v new file mode 100644 index 00000000..325be6be --- /dev/null +++ b/adi_library/xilinx/axi_adxcvr/axi_adxcvr_mstatus.v @@ -0,0 +1,112 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module axi_adxcvr_mstatus ( + + input up_rstn, + input up_clk, + + input up_pll_locked_in, + input up_rst_done_in, + input up_prbserr_in, + input up_prbslocked_in, + input [ 1:0] up_bufstatus_in, + input up_pll_locked, + input up_rst_done, + input up_prbserr, + input up_prbslocked, + input [ 1:0] up_bufstatus, + output up_pll_locked_out, + output up_rst_done_out, + output up_prbserr_out, + output up_prbslocked_out, + output [ 1:0] up_bufstatus_out +); + + // parameters + + parameter integer XCVR_ID = 0; + parameter integer NUM_OF_LANES = 8; + + // internal registers + + reg up_pll_locked_int = 'd0; + reg up_rst_done_int = 'd0; + reg up_prbserr_int = 'd0; + reg up_prbslocked_int = 'd0; + reg [ 1:0] up_bufstatus_int = 2'd00; + + // internal signals + + wire up_pll_locked_s; + wire up_rst_done_s; + wire up_prbserr_s; + wire up_prbslocked_s; + wire [ 1:0] up_bufstatus_s; + + // daisy-chain the signals + + assign up_pll_locked_out = up_pll_locked_int; + assign up_rst_done_out = up_rst_done_int; + assign up_prbserr_out = up_prbserr_int; + assign up_prbslocked_out = up_prbslocked_int; + assign up_bufstatus_out = up_bufstatus_int; + + assign up_pll_locked_s = (XCVR_ID < NUM_OF_LANES) ? up_pll_locked : 1'b1; + assign up_rst_done_s = (XCVR_ID < NUM_OF_LANES) ? up_rst_done : 1'b1; + assign up_prbserr_s = (XCVR_ID < NUM_OF_LANES) ? up_prbserr : 1'b0; + assign up_prbslocked_s = (XCVR_ID < NUM_OF_LANES) ? up_prbslocked : 1'b1; + assign up_bufstatus_s = (XCVR_ID < NUM_OF_LANES) ? up_bufstatus : 2'b00; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_pll_locked_int <= 1'd0; + up_rst_done_int <= 1'd0; + up_prbserr_int <= 1'd0; + up_prbslocked_int <= 1'd0; + up_bufstatus_int <= 2'd00; + end else begin + up_pll_locked_int <= up_pll_locked_in & up_pll_locked_s; + up_rst_done_int <= up_rst_done_in & up_rst_done_s; + up_prbserr_int <= up_prbserr_in | up_prbserr_s; + up_prbslocked_int <= up_prbslocked_in & up_prbslocked_s; + up_bufstatus_int[0] <= up_bufstatus_in[0] | up_bufstatus_s[0]; + up_bufstatus_int[1] <= up_bufstatus_in[1] | up_bufstatus_s[1]; + end + end + +endmodule diff --git a/adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v b/adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v new file mode 100644 index 00000000..3ac801e0 --- /dev/null +++ b/adi_library/xilinx/axi_adxcvr/axi_adxcvr_up.v @@ -0,0 +1,576 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_adxcvr_up #( + + // parameters + + parameter integer ID = 0, + parameter integer NUM_OF_LANES = 8, + parameter integer XCVR_TYPE = 0, + parameter integer LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B + parameter [ 7:0] FPGA_TECHNOLOGY = 0, + parameter [ 7:0] FPGA_FAMILY = 0, + parameter [ 7:0] SPEED_GRADE = 0, + parameter [ 7:0] DEV_PACKAGE = 0, + parameter [15:0] FPGA_VOLTAGE = 0, + parameter integer TX_OR_RX_N = 0, + parameter integer QPLL_ENABLE = 1, + parameter LPM_OR_DFE_N = 1, + parameter [ 2:0] RATE = 3'd0, + parameter [ 3:0] TX_DIFFCTRL = 4'd8, + parameter [ 4:0] TX_POSTCURSOR = 5'd0, + parameter [ 4:0] TX_PRECURSOR = 5'd0, + parameter [ 1:0] SYS_CLK_SEL = 2'd3, + parameter [ 2:0] OUT_CLK_SEL = 3'd4 +) ( + + // common + + output [ 7:0] up_cm_sel, + output up_cm_enb, + output [11:0] up_cm_addr, + output up_cm_wr, + output [15:0] up_cm_wdata, + input [15:0] up_cm_rdata, + input up_cm_ready, + + // channel + + input up_ch_pll_locked, + output up_ch_rst, + output up_ch_user_ready, + input up_ch_rst_done, + output up_ch_prbsforceerr, + output [ 3:0] up_ch_prbssel, + output up_ch_prbscntreset, + input up_ch_prbserr, + input up_ch_prbslocked, + input [ 1:0] up_ch_bufstatus, + output up_ch_bufstatus_rst, + output up_ch_lpm_dfe_n, + output [ 2:0] up_ch_rate, + output [ 1:0] up_ch_sys_clk_sel, + output [ 2:0] up_ch_out_clk_sel, + output [ 4:0] up_ch_tx_diffctrl, + output [ 4:0] up_ch_tx_postcursor, + output [ 4:0] up_ch_tx_precursor, + output [ 7:0] up_ch_sel, + output up_ch_enb, + output [11:0] up_ch_addr, + output up_ch_wr, + output [15:0] up_ch_wdata, + input [15:0] up_ch_rdata, + input up_ch_ready, + + // eye-scan + + output [ 7:0] up_es_sel, + output up_es_req, + output reg [15:0] up_es_reset = 'h0, + input up_es_ack, + output [ 4:0] up_es_pscale, + output [ 1:0] up_es_vrange, + output [ 7:0] up_es_vstep, + output [ 7:0] up_es_vmax, + output [ 7:0] up_es_vmin, + output [11:0] up_es_hmax, + output [11:0] up_es_hmin, + output [11:0] up_es_hstep, + output [31:0] up_es_saddr, + input up_es_status, + + // status + + output up_status, + output up_pll_rst, + + // bus interface + + input up_rstn, + input up_clk, + input up_wreq, + input [ 9:0] up_waddr, + input [31:0] up_wdata, + output up_wack, + input up_rreq, + input [ 9:0] up_raddr, + output [31:0] up_rdata, + output up_rack +); + + // parameters + + localparam [31:0] VERSION = 32'h00110561; + + // internal registers + + reg up_wreq_d = 'd0; + reg [31:0] up_scratch = 'd0; + reg up_resetn = 'd0; + reg [ 3:0] up_pll_rst_cnt = 'd0; + reg [ 3:0] up_rst_cnt = 'd0; + reg [ 6:0] up_user_ready_cnt = 'd0; + reg up_status_int = 'd0; + reg up_lpm_dfe_n = LPM_OR_DFE_N; + reg [ 2:0] up_rate = RATE; + reg [ 1:0] up_sys_clk_sel = SYS_CLK_SEL; + reg [ 2:0] up_out_clk_sel = OUT_CLK_SEL; + reg [ 4:0] up_tx_diffctrl = TX_DIFFCTRL; + reg [ 4:0] up_tx_postcursor = TX_POSTCURSOR; + reg [ 4:0] up_tx_precursor = TX_PRECURSOR; + reg [ 7:0] up_icm_sel = 'd0; + reg up_icm_enb = 'd0; + reg up_icm_wr = 'd0; + reg [28:0] up_icm_data = 'd0; + reg [15:0] up_icm_rdata = 'd0; + reg up_icm_busy = 'd0; + reg [ 7:0] up_ich_sel = 'd0; + reg up_ich_enb = 'd0; + reg up_ich_wr = 'd0; + reg [28:0] up_ich_data = 'd0; + reg [15:0] up_ich_rdata = 'd0; + reg up_ich_busy = 'd0; + reg [ 7:0] up_ies_sel = 'd0; + reg up_ies_req = 'd0; + reg [ 4:0] up_ies_prescale = 'd0; + reg [ 1:0] up_ies_voffset_range = 'd0; + reg [ 7:0] up_ies_voffset_step = 'd0; + reg [ 7:0] up_ies_voffset_max = 'd0; + reg [ 7:0] up_ies_voffset_min = 'd0; + reg [11:0] up_ies_hoffset_max = 'd0; + reg [11:0] up_ies_hoffset_min = 'd0; + reg [11:0] up_ies_hoffset_step = 'd0; + reg [31:0] up_ies_start_addr = 'd0; + reg up_ies_status = 'd0; + reg up_rreq_d = 'd0; + reg [31:0] up_rdata_d = 'd0; + reg [3:0] up_prbssel = 'd0; + reg up_prbscntreset = 'd1; + reg up_prbsforceerr = 'd0; + reg up_bufstatus_rst = 'd1; + + // internal signals + + wire [31:0] up_rparam_s; + + // defaults + + assign up_wack = up_wreq_d; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wreq_d <= 'd0; + up_scratch <= 'd0; + end else begin + up_wreq_d <= up_wreq; + if ((up_wreq == 1'b1) && (up_waddr == 10'h002)) begin + up_scratch <= up_wdata; + end + end + end + + // reset-controller + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_resetn <= 'd0; + up_bufstatus_rst <= 1'b1; + end else begin + if ((up_wreq == 1'b1) && (up_waddr == 10'h004)) begin + up_resetn <= up_wdata[0]; + up_bufstatus_rst <= up_wdata[1]; + end + end + end + + assign up_pll_rst = up_pll_rst_cnt[3]; + assign up_ch_rst = up_rst_cnt[3]; + assign up_ch_user_ready = up_user_ready_cnt[6]; + assign up_status = up_status_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_pll_rst_cnt <= 4'h8; + up_rst_cnt <= 4'h8; + up_user_ready_cnt <= 7'h00; + up_status_int <= 1'b0; + end else begin + if (up_resetn == 1'b0) begin + up_pll_rst_cnt <= 4'h8; + end else if (up_pll_rst_cnt[3] == 1'b1) begin + up_pll_rst_cnt <= up_pll_rst_cnt + 1'b1; + end + if ((up_resetn == 1'b0) || (up_pll_rst_cnt[3] == 1'b1) || + (up_ch_pll_locked == 1'b0)) begin + up_rst_cnt <= 4'h8; + end else if (up_rst_cnt[3] == 1'b1) begin + up_rst_cnt <= up_rst_cnt + 1'b1; + end + if ((up_resetn == 1'b0) || (up_rst_cnt[3] == 1'b1)) begin + up_user_ready_cnt <= 7'h00; + end else if (up_user_ready_cnt[6] == 1'b0) begin + up_user_ready_cnt <= up_user_ready_cnt + 1'b1; + end + if ((up_resetn == 1'b0) || (up_ch_pll_locked == 1'b0)) begin + up_status_int <= 1'b0; + end else if (up_ch_rst_done == 1'b1) begin + up_status_int <= 1'b1; + end + end + end + + // control signals + + assign up_ch_lpm_dfe_n = up_lpm_dfe_n; + assign up_ch_rate = up_rate; + assign up_ch_sys_clk_sel = up_sys_clk_sel; + assign up_ch_out_clk_sel = up_out_clk_sel; + assign up_ch_tx_diffctrl = up_tx_diffctrl; + assign up_ch_tx_postcursor = up_tx_postcursor; + assign up_ch_tx_precursor = up_tx_precursor; + assign up_ch_prbssel = up_prbssel; + assign up_ch_prbscntreset = up_prbscntreset; + assign up_ch_prbsforceerr = up_prbsforceerr; + assign up_ch_bufstatus_rst = up_bufstatus_rst; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_lpm_dfe_n <= LPM_OR_DFE_N; + up_rate <= RATE; + up_sys_clk_sel <= SYS_CLK_SEL; + up_out_clk_sel <= OUT_CLK_SEL; + up_tx_diffctrl <= TX_DIFFCTRL; + up_tx_postcursor <= TX_POSTCURSOR; + up_tx_precursor <= TX_PRECURSOR; + up_prbssel <= 4'b0; + up_prbscntreset <= 1'b1; + up_prbsforceerr <= 1'b0; + end else begin + if ((up_wreq == 1'b1) && (up_waddr == 10'h008)) begin + up_lpm_dfe_n <= up_wdata[12]; + up_rate <= up_wdata[10:8]; + up_sys_clk_sel <= up_wdata[5:4]; + up_out_clk_sel <= up_wdata[2:0]; + end + if ((up_wreq == 1'b1) && (up_waddr == 10'h030)) begin + up_tx_diffctrl <= up_wdata[4:0]; + end + if ((up_wreq == 1'b1) && (up_waddr == 10'h031)) begin + up_tx_postcursor <= up_wdata[4:0]; + end + if ((up_wreq == 1'b1) && (up_waddr == 10'h032)) begin + up_tx_precursor <= up_wdata[4:0]; + end + if ((up_wreq == 1'b1) && (up_waddr == 10'h060)) begin + up_prbssel <= up_wdata[3:0]; + up_prbscntreset <= up_wdata[8]; + up_prbsforceerr <= up_wdata[16]; + end + end + end + + // common access + + assign up_cm_sel = up_icm_sel; + assign up_cm_enb = up_icm_enb; + assign up_cm_wr = up_icm_wr; + assign up_cm_addr = up_icm_data[27:16]; + assign up_cm_wdata = up_icm_data[15:0]; + + generate + if (QPLL_ENABLE == 0) begin + always @(posedge up_clk) begin + up_icm_sel <= 'd0; + up_icm_enb <= 'd0; + up_icm_wr <= 'd0; + up_icm_data <= 'd0; + up_icm_rdata <= 'd0; + up_icm_busy <= 'd0; + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_icm_sel <= 'd0; + up_icm_enb <= 'd0; + up_icm_wr <= 'd0; + up_icm_data <= 'd0; + up_icm_rdata <= 'd0; + up_icm_busy <= 'd0; + end else begin + if ((up_wreq == 1'b1) && (up_waddr == 10'h010)) begin + up_icm_sel <= up_wdata[7:0]; + end + if ((up_wreq == 1'b1) && (up_waddr == 10'h011)) begin + up_icm_enb <= 1'b1; + up_icm_wr <= up_wdata[28]; + end else begin + up_icm_enb <= 1'b0; + up_icm_wr <= 1'b0; + end + if ((up_wreq == 1'b1) && (up_waddr == 10'h011)) begin + up_icm_data <= up_wdata[28:0]; + end + if (up_cm_ready == 1'b1) begin + up_icm_rdata <= up_cm_rdata; + up_icm_busy <= 1'b0; + end else if ((up_wreq == 1'b1) && (up_waddr == 10'h011)) begin + up_icm_rdata <= 16'd0; + up_icm_busy <= 1'b1; + end + end + end + end + endgenerate + + // channel access + + assign up_ch_sel = up_ich_sel; + assign up_ch_enb = up_ich_enb; + assign up_ch_wr = up_ich_wr; + assign up_ch_addr = up_ich_data[27:16]; + assign up_ch_wdata = up_ich_data[15:0]; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_ich_sel <= 'd0; + up_ich_enb <= 'd0; + up_ich_wr <= 'd0; + up_ich_data <= 'd0; + up_ich_rdata <= 'd0; + up_ich_busy <= 'd0; + end else begin + if ((up_wreq == 1'b1) && (up_waddr == 10'h018)) begin + up_ich_sel <= up_wdata[7:0]; + end + if ((up_wreq == 1'b1) && (up_waddr == 10'h019)) begin + up_ich_enb <= 1'b1; + up_ich_wr <= up_wdata[28]; + end else begin + up_ich_enb <= 1'b0; + up_ich_wr <= 1'b0; + end + if ((up_wreq == 1'b1) && (up_waddr == 10'h019)) begin + up_ich_data <= up_wdata[28:0]; + end + if (up_ch_ready == 1'b1) begin + up_ich_rdata <= up_ch_rdata; + up_ich_busy <= 1'b0; + end else if ((up_wreq == 1'b1) && (up_waddr == 10'h019)) begin + up_ich_rdata <= 16'd0; + up_ich_busy <= 1'b1; + end + end + end + + // eye-scan + + assign up_es_sel = up_ies_sel; + assign up_es_req = up_ies_req; + assign up_es_pscale = up_ies_prescale; + assign up_es_vrange = up_ies_voffset_range; + assign up_es_vstep = up_ies_voffset_step; + assign up_es_vmax = up_ies_voffset_max; + assign up_es_vmin = up_ies_voffset_min; + assign up_es_hmax = up_ies_hoffset_max; + assign up_es_hmin = up_ies_hoffset_min; + assign up_es_hstep = up_ies_hoffset_step; + assign up_es_saddr = up_ies_start_addr; + + generate + if (TX_OR_RX_N == 1) begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_ies_sel <= 'd0; + up_ies_req <= 'd0; + up_ies_prescale <= 'd0; + up_ies_voffset_range <= 'd0; + up_ies_voffset_step <= 'd0; + up_ies_voffset_max <= 'd0; + up_ies_voffset_min <= 'd0; + up_ies_hoffset_max <= 'd0; + up_ies_hoffset_min <= 'd0; + up_ies_hoffset_step <= 'd0; + up_ies_start_addr <= 'd0; + up_ies_status <= 'd0; + up_es_reset <= 'd0; + end else begin + up_ies_sel <= 'd0; + up_ies_req <= 'd0; + up_ies_prescale <= 'd0; + up_ies_voffset_range <= 'd0; + up_ies_voffset_step <= 'd0; + up_ies_voffset_max <= 'd0; + up_ies_voffset_min <= 'd0; + up_ies_hoffset_max <= 'd0; + up_ies_hoffset_min <= 'd0; + up_ies_hoffset_step <= 'd0; + up_ies_start_addr <= 'd0; + up_ies_status <= 'd0; + up_es_reset <= 'd0; + end + end + end else begin + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_ies_sel <= 'd0; + up_ies_req <= 'd0; + up_ies_prescale <= 'd0; + up_ies_voffset_range <= 'd0; + up_ies_voffset_step <= 'd0; + up_ies_voffset_max <= 'd0; + up_ies_voffset_min <= 'd0; + up_ies_hoffset_max <= 'd0; + up_ies_hoffset_min <= 'd0; + up_ies_hoffset_step <= 'd0; + up_ies_start_addr <= 'd0; + up_ies_status <= 'd0; + up_es_reset <= 'd0; + end else begin + if ((up_wreq == 1'b1) && (up_waddr == 10'h020)) begin + up_ies_sel <= up_wdata[7:0]; + end + if (up_es_ack == 1'b1) begin + up_ies_req <= 1'b0; + end else if ((up_wreq == 1'b1) && (up_waddr == 10'h028)) begin + up_ies_req <= up_wdata[0]; + end + if ((up_wreq == 1'b1) && (up_waddr == 10'h029)) begin + up_ies_prescale <= up_wdata[4:0]; + end + if ((up_wreq == 1'b1) && (up_waddr == 10'h02a)) begin + up_ies_voffset_range <= up_wdata[25:24]; + up_ies_voffset_step <= up_wdata[23:16]; + up_ies_voffset_max <= up_wdata[15:8]; + up_ies_voffset_min <= up_wdata[7:0]; + end + if ((up_wreq == 1'b1) && (up_waddr == 10'h02b)) begin + up_ies_hoffset_max <= up_wdata[27:16]; + up_ies_hoffset_min <= up_wdata[11:0]; + end + if ((up_wreq == 1'b1) && (up_waddr == 10'h02c)) begin + up_ies_hoffset_step <= up_wdata[11:0]; + end + if ((up_wreq == 1'b1) && (up_waddr == 10'h02d)) begin + up_ies_start_addr <= up_wdata; + end + if (up_es_status == 1'b1) begin + up_ies_status <= 1'b1; + end else if ((up_wreq == 1'b1) && (up_waddr == 10'h02e)) begin + up_ies_status <= up_ies_status & ~up_wdata[0]; + end + if ((up_wreq == 1'b1) && (up_waddr == 10'h02f)) begin + up_es_reset <= up_wdata[15:0]; + end + end + end + end + endgenerate + + // read interface + + assign up_rack = up_rreq_d; + assign up_rdata = up_rdata_d; + + assign up_rparam_s[31:24] = 8'd0; + + // xilinx specific + + assign up_rparam_s[23:21] = 3'd0; + assign up_rparam_s[20:20] = (QPLL_ENABLE == 0) ? 1'b0 : 1'b1; + assign up_rparam_s[19:16] = XCVR_TYPE[3:0]; + + // generic + + assign up_rparam_s[15:14] = 2'd0; + assign up_rparam_s[13:12] = LINK_MODE[1:0]; + assign up_rparam_s[11: 9] = 3'd0; + assign up_rparam_s[ 8: 8] = (TX_OR_RX_N == 0) ? 1'b0 : 1'b1; + assign up_rparam_s[ 7: 0] = NUM_OF_LANES; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rreq_d <= 'd0; + up_rdata_d <= 'd0; + end else begin + up_rreq_d <= up_rreq; + if (up_rreq == 1'b1) begin + case (up_raddr) + 10'h000: up_rdata_d <= VERSION; + 10'h001: up_rdata_d <= ID; + 10'h002: up_rdata_d <= up_scratch; + 10'h004: up_rdata_d <= {30'd0, up_bufstatus_rst, up_resetn}; + 10'h005: up_rdata_d <= {25'd0, up_ch_bufstatus[1], up_ch_bufstatus[0], ~up_ch_pll_locked, 3'b0, up_status_int}; + 10'h006: up_rdata_d <= {17'd0, up_user_ready_cnt, up_rst_cnt, up_pll_rst_cnt}; + 10'h007: up_rdata_d <= {FPGA_TECHNOLOGY,FPGA_FAMILY,SPEED_GRADE,DEV_PACKAGE}; // [8,8,8,8] + 10'h008: up_rdata_d <= {19'd0, up_lpm_dfe_n, 1'd0, up_rate, 2'd0, up_sys_clk_sel, 1'd0, up_out_clk_sel}; + 10'h009: up_rdata_d <= up_rparam_s; + 10'h010: up_rdata_d <= {24'd0, up_icm_sel}; + 10'h011: up_rdata_d <= {3'd0, up_icm_data}; + 10'h012: up_rdata_d <= {15'd0, up_icm_busy, up_icm_rdata}; + 10'h018: up_rdata_d <= {24'd0, up_ich_sel}; + 10'h019: up_rdata_d <= {3'd0, up_ich_data}; + 10'h01a: up_rdata_d <= {15'd0, up_ich_busy, up_ich_rdata}; + 10'h020: up_rdata_d <= {24'd0, up_ies_sel}; + 10'h028: up_rdata_d <= {31'd0, up_ies_req}; + 10'h029: up_rdata_d <= {27'd0, up_ies_prescale}; + 10'h02a: up_rdata_d <= {6'd0, up_ies_voffset_range, up_ies_voffset_step, up_ies_voffset_max, up_ies_voffset_min}; + 10'h02b: up_rdata_d <= {4'd0, up_ies_hoffset_max, 4'd0, up_ies_hoffset_min}; + 10'h02c: up_rdata_d <= {20'd0, up_ies_hoffset_step}; + 10'h02d: up_rdata_d <= up_ies_start_addr; + 10'h02e: up_rdata_d <= {31'd0, up_es_status}; + 10'h02f: up_rdata_d <= {16'd0, up_es_reset}; + 10'h030: up_rdata_d <= up_tx_diffctrl; + 10'h031: up_rdata_d <= up_tx_postcursor; + 10'h032: up_rdata_d <= up_tx_precursor; + 10'h050: up_rdata_d <= {16'd0, FPGA_VOLTAGE}; // mV + 10'h060: up_rdata_d <= {8'b0, + 7'b0,up_prbsforceerr, + 7'b0,up_prbscntreset, + 4'b0,up_prbssel}; + 10'h061: up_rdata_d <= {16'b0, + 7'b0,up_ch_prbserr, + 7'b0,up_ch_prbslocked}; + default: up_rdata_d <= 32'd0; + endcase + end else begin + up_rdata_d <= 32'd0; + end + end + end + +endmodule diff --git a/adi_library/xilinx/axi_adxcvr/bd/bd.tcl b/adi_library/xilinx/axi_adxcvr/bd/bd.tcl new file mode 100644 index 00000000..a12c10a3 --- /dev/null +++ b/adi_library/xilinx/axi_adxcvr/bd/bd.tcl @@ -0,0 +1,51 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_only $ip " \ + DEV_PACKAGE \ + SPEED_GRADE \ + FPGA_FAMILY \ + FPGA_TECHNOLOGY" + + bd::mark_propagate_override $ip " \ + FPGA_VOLTAGE \ + XCVR_TYPE" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/xilinx/axi_adxcvr/component.xml b/adi_library/xilinx/axi_adxcvr/component.xml new file mode 100644 index 00000000..0bbb674a --- /dev/null +++ b/adi_library/xilinx/axi_adxcvr/component.xml @@ -0,0 +1,27269 @@ + + + analog.com + user + axi_adxcvr + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi:m_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + m_axi + + + + + + + + + AWADDR + + + m_axi_awaddr + + + + + AWPROT + + + m_axi_awprot + + + + + AWVALID + + + m_axi_awvalid + + + + + AWREADY + + + m_axi_awready + + + + + WDATA + + + m_axi_wdata + + + + + WSTRB + + + m_axi_wstrb + + + + + WVALID + + + m_axi_wvalid + + + + + WREADY + + + m_axi_wready + + + + + BRESP + + + m_axi_bresp + + + + + BVALID + + + m_axi_bvalid + + + + + BREADY + + + m_axi_bready + + + + + ARADDR + + + m_axi_araddr + + + + + ARPROT + + + m_axi_arprot + + + + + ARVALID + + + m_axi_arvalid + + + + + ARREADY + + + m_axi_arready + + + + + RDATA + + + m_axi_rdata + + + + + RRESP + + + m_axi_rresp + + + + + RVALID + + + m_axi_rvalid + + + + + RREADY + + + m_axi_rready + + + + + + + true + + + + + + up_pll_rst + + + + + + + RST + + + up_pll_rst + + + + + + POLARITY + ACTIVE_HIGH + + + + + up_cm_0 + + + + + + + enb + + + up_cm_enb_0 + + + + + addr + + + up_cm_addr_0 + + + + + wr + + + up_cm_wr_0 + + + + + wdata + + + up_cm_wdata_0 + + + + + rdata + + + up_cm_rdata_0 + + + + + ready + + + up_cm_ready_0 + + + + + + + true + + + + + + up_es_0 + + + + + + + enb + + + up_es_enb_0 + + + + + addr + + + up_es_addr_0 + + + + + wr + + + up_es_wr_0 + + + + + reset + + + up_es_reset_0 + + + + + wdata + + + up_es_wdata_0 + + + + + rdata + + + up_es_rdata_0 + + + + + ready + + + up_es_ready_0 + + + + + + + true + + + + + + up_ch_0 + + + + + + + pll_locked + + + up_ch_pll_locked_0 + + + + + rst + + + up_ch_rst_0 + + + + + user_ready + + + up_ch_user_ready_0 + + + + + rst_done + + + up_ch_rst_done_0 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+ choice_pairs_fc01a186 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + + + + + xilinx_anylanguagesynthesis_view_fileset + + axi_adxcvr_es.v + verilogSource + + + axi_adxcvr_mdrp.v + verilogSource + + + axi_adxcvr_mstatus.v + verilogSource + + + axi_adxcvr_up.v + verilogSource + + + ../../common/up_axi.v + verilogSource + + + ../../scripts/adi_xilinx_device_info_enc.tcl + tclSource + + + axi_adxcvr.v + verilogSource + CHECKSUM_7c4853b1 + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + axi_adxcvr_es.v + verilogSource + + + axi_adxcvr_mdrp.v + verilogSource + + + axi_adxcvr_mstatus.v + verilogSource + + + axi_adxcvr_up.v + verilogSource + + + ../../common/up_axi.v + verilogSource + + + ../../scripts/adi_xilinx_device_info_enc.tcl + tclSource + + + axi_adxcvr.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_adxcvr_v1_0.tcl + tclSource + CHECKSUM_ab0e6f88 + XGUI_VERSION_2 + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + axi_adxcvr_v1_0 + + + ID + Id + 0 + + + NUM_OF_LANES + Num Of Lanes + 8 + + + XCVR_TYPE + Xcvr Type + 0 + + + LINK_MODE + Link Layer mode + 1 + + + FPGA_TECHNOLOGY + Fpga Technology + 0 + + + FPGA_FAMILY + Fpga Family + 0 + + + SPEED_GRADE + Speed Grade + 0 + + + DEV_PACKAGE + Dev Package + 0 + + + FPGA_VOLTAGE + Fpga Voltage + 0 + + + TX_OR_RX_N + Tx Or Rx N + 0 + + + QPLL_ENABLE + Qpll Enable + 1 + + + LPM_OR_DFE_N + Lpm Or Dfe N + 1 + + + RATE + Rate + "000" + + + TX_DIFFCTRL + Tx Diffctrl + "01000" + + + TX_POSTCURSOR + Tx Postcursor + "00000" + + + TX_PRECURSOR + Tx Precursor + "00000" + + + SYS_CLK_SEL + Sys Clk Sel + "11" + + + OUT_CLK_SEL + Out Clk Sel + "100" + + + Component_Name + axi_adxcvr_v1_0 + + + + + + virtex7 + + + /Analog_Devices + + axi_adxcvr_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/axi_adxcvr + 1 + 2024-01-14T03:57:27Z + + + 2023.2.1 + + + + + + + + diff --git a/adi_library/xilinx/axi_adxcvr/temporary_case_dependencies.mk b/adi_library/xilinx/axi_adxcvr/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/xilinx/axi_adxcvr/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/xilinx/axi_adxcvr/xgui/axi_adxcvr_v1_0.tcl b/adi_library/xilinx/axi_adxcvr/xgui/axi_adxcvr_v1_0.tcl new file mode 100644 index 00000000..16f433b1 --- /dev/null +++ b/adi_library/xilinx/axi_adxcvr/xgui/axi_adxcvr_v1_0.tcl @@ -0,0 +1,283 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "LINK_MODE" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "ID" -parent ${Page_0} + ipgui::add_param $IPINST -name "LPM_OR_DFE_N" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_OF_LANES" -parent ${Page_0} + ipgui::add_param $IPINST -name "OUT_CLK_SEL" -parent ${Page_0} + ipgui::add_param $IPINST -name "QPLL_ENABLE" -parent ${Page_0} + ipgui::add_param $IPINST -name "RATE" -parent ${Page_0} + ipgui::add_param $IPINST -name "SYS_CLK_SEL" -parent ${Page_0} + ipgui::add_param $IPINST -name "TX_DIFFCTRL" -parent ${Page_0} + ipgui::add_param $IPINST -name "TX_OR_RX_N" -parent ${Page_0} + ipgui::add_param $IPINST -name "TX_POSTCURSOR" -parent ${Page_0} + ipgui::add_param $IPINST -name "TX_PRECURSOR" -parent ${Page_0} + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "XCVR_TYPE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_VOLTAGE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_TECHNOLOGY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "FPGA_FAMILY" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "SPEED_GRADE" -parent ${FPGA_info} -widget comboBox + ipgui::add_param $IPINST -name "DEV_PACKAGE" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to update DEV_PACKAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DEV_PACKAGE { PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to validate DEV_PACKAGE + return true +} + +proc update_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to update FPGA_FAMILY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_FAMILY { PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to validate FPGA_FAMILY + return true +} + +proc update_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to update FPGA_TECHNOLOGY when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_TECHNOLOGY { PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to validate FPGA_TECHNOLOGY + return true +} + +proc update_PARAM_VALUE.FPGA_VOLTAGE { PARAM_VALUE.FPGA_VOLTAGE } { + # Procedure called to update FPGA_VOLTAGE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.FPGA_VOLTAGE { PARAM_VALUE.FPGA_VOLTAGE } { + # Procedure called to validate FPGA_VOLTAGE + return true +} + +proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to update ID when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } { + # Procedure called to validate ID + return true +} + +proc update_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } { + # Procedure called to update LINK_MODE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } { + # Procedure called to validate LINK_MODE + return true +} + +proc update_PARAM_VALUE.LPM_OR_DFE_N { PARAM_VALUE.LPM_OR_DFE_N } { + # Procedure called to update LPM_OR_DFE_N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.LPM_OR_DFE_N { PARAM_VALUE.LPM_OR_DFE_N } { + # Procedure called to validate LPM_OR_DFE_N + return true +} + +proc update_PARAM_VALUE.NUM_OF_LANES { PARAM_VALUE.NUM_OF_LANES } { + # Procedure called to update NUM_OF_LANES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_LANES { PARAM_VALUE.NUM_OF_LANES } { + # Procedure called to validate NUM_OF_LANES + return true +} + +proc update_PARAM_VALUE.OUT_CLK_SEL { PARAM_VALUE.OUT_CLK_SEL } { + # Procedure called to update OUT_CLK_SEL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.OUT_CLK_SEL { PARAM_VALUE.OUT_CLK_SEL } { + # Procedure called to validate OUT_CLK_SEL + return true +} + +proc update_PARAM_VALUE.QPLL_ENABLE { PARAM_VALUE.QPLL_ENABLE } { + # Procedure called to update QPLL_ENABLE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.QPLL_ENABLE { PARAM_VALUE.QPLL_ENABLE } { + # Procedure called to validate QPLL_ENABLE + return true +} + +proc update_PARAM_VALUE.RATE { PARAM_VALUE.RATE } { + # Procedure called to update RATE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RATE { PARAM_VALUE.RATE } { + # Procedure called to validate RATE + return true +} + +proc update_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to update SPEED_GRADE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SPEED_GRADE { PARAM_VALUE.SPEED_GRADE } { + # Procedure called to validate SPEED_GRADE + return true +} + +proc update_PARAM_VALUE.SYS_CLK_SEL { PARAM_VALUE.SYS_CLK_SEL } { + # Procedure called to update SYS_CLK_SEL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SYS_CLK_SEL { PARAM_VALUE.SYS_CLK_SEL } { + # Procedure called to validate SYS_CLK_SEL + return true +} + +proc update_PARAM_VALUE.TX_DIFFCTRL { PARAM_VALUE.TX_DIFFCTRL } { + # Procedure called to update TX_DIFFCTRL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TX_DIFFCTRL { PARAM_VALUE.TX_DIFFCTRL } { + # Procedure called to validate TX_DIFFCTRL + return true +} + +proc update_PARAM_VALUE.TX_OR_RX_N { PARAM_VALUE.TX_OR_RX_N } { + # Procedure called to update TX_OR_RX_N when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TX_OR_RX_N { PARAM_VALUE.TX_OR_RX_N } { + # Procedure called to validate TX_OR_RX_N + return true +} + +proc update_PARAM_VALUE.TX_POSTCURSOR { PARAM_VALUE.TX_POSTCURSOR } { + # Procedure called to update TX_POSTCURSOR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TX_POSTCURSOR { PARAM_VALUE.TX_POSTCURSOR } { + # Procedure called to validate TX_POSTCURSOR + return true +} + +proc update_PARAM_VALUE.TX_PRECURSOR { PARAM_VALUE.TX_PRECURSOR } { + # Procedure called to update TX_PRECURSOR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TX_PRECURSOR { PARAM_VALUE.TX_PRECURSOR } { + # Procedure called to validate TX_PRECURSOR + return true +} + +proc update_PARAM_VALUE.XCVR_TYPE { PARAM_VALUE.XCVR_TYPE } { + # Procedure called to update XCVR_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.XCVR_TYPE { PARAM_VALUE.XCVR_TYPE } { + # Procedure called to validate XCVR_TYPE + return true +} + + +proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID} +} + +proc update_MODELPARAM_VALUE.NUM_OF_LANES { MODELPARAM_VALUE.NUM_OF_LANES PARAM_VALUE.NUM_OF_LANES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_LANES}] ${MODELPARAM_VALUE.NUM_OF_LANES} +} + +proc update_MODELPARAM_VALUE.XCVR_TYPE { MODELPARAM_VALUE.XCVR_TYPE PARAM_VALUE.XCVR_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.XCVR_TYPE}] ${MODELPARAM_VALUE.XCVR_TYPE} +} + +proc update_MODELPARAM_VALUE.LINK_MODE { MODELPARAM_VALUE.LINK_MODE PARAM_VALUE.LINK_MODE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LINK_MODE}] ${MODELPARAM_VALUE.LINK_MODE} +} + +proc update_MODELPARAM_VALUE.FPGA_TECHNOLOGY { MODELPARAM_VALUE.FPGA_TECHNOLOGY PARAM_VALUE.FPGA_TECHNOLOGY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_TECHNOLOGY}] ${MODELPARAM_VALUE.FPGA_TECHNOLOGY} +} + +proc update_MODELPARAM_VALUE.FPGA_FAMILY { MODELPARAM_VALUE.FPGA_FAMILY PARAM_VALUE.FPGA_FAMILY } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_FAMILY}] ${MODELPARAM_VALUE.FPGA_FAMILY} +} + +proc update_MODELPARAM_VALUE.SPEED_GRADE { MODELPARAM_VALUE.SPEED_GRADE PARAM_VALUE.SPEED_GRADE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SPEED_GRADE}] ${MODELPARAM_VALUE.SPEED_GRADE} +} + +proc update_MODELPARAM_VALUE.DEV_PACKAGE { MODELPARAM_VALUE.DEV_PACKAGE PARAM_VALUE.DEV_PACKAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DEV_PACKAGE}] ${MODELPARAM_VALUE.DEV_PACKAGE} +} + +proc update_MODELPARAM_VALUE.FPGA_VOLTAGE { MODELPARAM_VALUE.FPGA_VOLTAGE PARAM_VALUE.FPGA_VOLTAGE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.FPGA_VOLTAGE}] ${MODELPARAM_VALUE.FPGA_VOLTAGE} +} + +proc update_MODELPARAM_VALUE.TX_OR_RX_N { MODELPARAM_VALUE.TX_OR_RX_N PARAM_VALUE.TX_OR_RX_N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TX_OR_RX_N}] ${MODELPARAM_VALUE.TX_OR_RX_N} +} + +proc update_MODELPARAM_VALUE.QPLL_ENABLE { MODELPARAM_VALUE.QPLL_ENABLE PARAM_VALUE.QPLL_ENABLE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.QPLL_ENABLE}] ${MODELPARAM_VALUE.QPLL_ENABLE} +} + +proc update_MODELPARAM_VALUE.LPM_OR_DFE_N { MODELPARAM_VALUE.LPM_OR_DFE_N PARAM_VALUE.LPM_OR_DFE_N } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LPM_OR_DFE_N}] ${MODELPARAM_VALUE.LPM_OR_DFE_N} +} + +proc update_MODELPARAM_VALUE.RATE { MODELPARAM_VALUE.RATE PARAM_VALUE.RATE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RATE}] ${MODELPARAM_VALUE.RATE} +} + +proc update_MODELPARAM_VALUE.TX_DIFFCTRL { MODELPARAM_VALUE.TX_DIFFCTRL PARAM_VALUE.TX_DIFFCTRL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TX_DIFFCTRL}] ${MODELPARAM_VALUE.TX_DIFFCTRL} +} + +proc update_MODELPARAM_VALUE.TX_POSTCURSOR { MODELPARAM_VALUE.TX_POSTCURSOR PARAM_VALUE.TX_POSTCURSOR } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TX_POSTCURSOR}] ${MODELPARAM_VALUE.TX_POSTCURSOR} +} + +proc update_MODELPARAM_VALUE.TX_PRECURSOR { MODELPARAM_VALUE.TX_PRECURSOR PARAM_VALUE.TX_PRECURSOR } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TX_PRECURSOR}] ${MODELPARAM_VALUE.TX_PRECURSOR} +} + +proc update_MODELPARAM_VALUE.SYS_CLK_SEL { MODELPARAM_VALUE.SYS_CLK_SEL PARAM_VALUE.SYS_CLK_SEL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SYS_CLK_SEL}] ${MODELPARAM_VALUE.SYS_CLK_SEL} +} + +proc update_MODELPARAM_VALUE.OUT_CLK_SEL { MODELPARAM_VALUE.OUT_CLK_SEL PARAM_VALUE.OUT_CLK_SEL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.OUT_CLK_SEL}] ${MODELPARAM_VALUE.OUT_CLK_SEL} +} + diff --git a/adi_library/xilinx/axi_dacfifo/Makefile b/adi_library/xilinx/axi_dacfifo/Makefile new file mode 100644 index 00000000..801b9168 --- /dev/null +++ b/adi_library/xilinx/axi_dacfifo/Makefile @@ -0,0 +1,22 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_dacfifo + +XILINX_DEPS += ../../common/ad_axis_inf_rx.v +XILINX_DEPS += ../../common/ad_b2g.v +XILINX_DEPS += ../../common/ad_g2b.v +XILINX_DEPS += ../../common/ad_mem.v +XILINX_DEPS += ../../common/ad_mem_asym.v +XILINX_DEPS += ../../util_dacfifo/util_dacfifo_bypass.v +XILINX_DEPS += axi_dacfifo.v +XILINX_DEPS += axi_dacfifo_address_buffer.v +XILINX_DEPS += axi_dacfifo_constr.xdc +XILINX_DEPS += axi_dacfifo_ip.tcl +XILINX_DEPS += axi_dacfifo_rd.v +XILINX_DEPS += axi_dacfifo_wr.v + +include ../../scripts/library.mk diff --git a/adi_library/xilinx/axi_dacfifo/axi_dacfifo.v b/adi_library/xilinx/axi_dacfifo/axi_dacfifo.v new file mode 100644 index 00000000..ad5f5665 --- /dev/null +++ b/adi_library/xilinx/axi_dacfifo/axi_dacfifo.v @@ -0,0 +1,282 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dacfifo #( + + parameter DAC_DATA_WIDTH = 64, + parameter DMA_DATA_WIDTH = 64, + parameter AXI_DATA_WIDTH = 512, + parameter AXI_SIZE = 2, + parameter AXI_LENGTH = 15, + parameter AXI_ADDRESS = 32'h00000000, + parameter AXI_ADDRESS_LIMIT = 32'hffffffff +) ( + + // dma interface (AXI Stream) + + input dma_clk, + input dma_rst, + input dma_valid, + input [(DMA_DATA_WIDTH-1):0] dma_data, + output reg dma_ready, + input dma_xfer_req, + input dma_xfer_last, + + // dac interface + + input dac_clk, + input dac_rst, + input dac_valid, + output reg [(DAC_DATA_WIDTH-1):0] dac_data, + output reg dac_dunf, + output reg dac_xfer_out, + + input bypass, + + // axi interface + + input axi_clk, + input axi_resetn, + output axi_awvalid, + output [ 3:0] axi_awid, + output [ 1:0] axi_awburst, + output axi_awlock, + output [ 3:0] axi_awcache, + output [ 2:0] axi_awprot, + output [ 3:0] axi_awqos, + output [ 7:0] axi_awlen, + output [ 2:0] axi_awsize, + output [ 31:0] axi_awaddr, + input axi_awready, + output axi_wvalid, + output [(AXI_DATA_WIDTH-1):0] axi_wdata, + output [(AXI_DATA_WIDTH/8-1):0] axi_wstrb, + output axi_wlast, + input axi_wready, + input axi_bvalid, + input [ 3:0] axi_bid, + input [ 1:0] axi_bresp, + output axi_bready, + output axi_arvalid, + output [ 3:0] axi_arid, + output [ 1:0] axi_arburst, + output axi_arlock, + output [ 3:0] axi_arcache, + output [ 2:0] axi_arprot, + output [ 3:0] axi_arqos, + output [ 7:0] axi_arlen, + output [ 2:0] axi_arsize, + output [ 31:0] axi_araddr, + input axi_arready, + input axi_rvalid, + input [ 3:0] axi_rid, + input [ 1:0] axi_rresp, + input axi_rlast, + input [(AXI_DATA_WIDTH-1):0] axi_rdata, + output axi_rready +); + + localparam FIFO_BYPASS = (DAC_DATA_WIDTH == DMA_DATA_WIDTH) ? 1 : 0; + + reg dma_bypass_m1 = 1'b0; + reg dma_bypass = 1'b0; + reg dac_bypass_m1 = 1'b0; + reg dac_bypass = 1'b0; + reg dac_xfer_out_m1 = 1'b0; + reg dac_xfer_out_bypass = 1'b0; + + wire axi_xfer_req_s; + (* dont_touch = "true" *) wire [31:0] axi_last_addr_s; + (* dont_touch = "true" *) wire [ 7:0] axi_last_beats_s; + wire [ 3:0] dma_last_beats_s; + wire [(DAC_DATA_WIDTH-1):0] dac_data_fifo_s; + wire [(DAC_DATA_WIDTH-1):0] dac_data_bypass_s; + wire dac_xfer_fifo_out_s; + wire dac_dunf_fifo_s; + wire dac_dunf_bypass_s; + wire dma_ready_wr_s; + + axi_dacfifo_wr #( + .AXI_DATA_WIDTH (AXI_DATA_WIDTH), + .DMA_DATA_WIDTH (DMA_DATA_WIDTH), + .AXI_SIZE (AXI_SIZE), + .AXI_LENGTH (AXI_LENGTH), + .AXI_ADDRESS (AXI_ADDRESS), + .AXI_ADDRESS_LIMIT (AXI_ADDRESS_LIMIT), + .DMA_MEM_ADDRESS_WIDTH (12) + ) i_wr ( + .dma_clk (dma_clk), + .dma_rst (dma_rst), + .dma_data (dma_data), + .dma_ready (dma_ready), + .dma_ready_out (dma_ready_wr_s), + .dma_valid (dma_valid), + .dma_xfer_req (dma_xfer_req), + .dma_xfer_last (dma_xfer_last), + .dma_last_beats (dma_last_beats_s), + .axi_last_addr (axi_last_addr_s), + .axi_last_beats (axi_last_beats_s), + .axi_xfer_out (axi_xfer_req_s), + .axi_clk (axi_clk), + .axi_resetn (axi_resetn), + .axi_awvalid (axi_awvalid), + .axi_awid (axi_awid), + .axi_awburst (axi_awburst), + .axi_awlock (axi_awlock), + .axi_awcache (axi_awcache), + .axi_awprot (axi_awprot), + .axi_awqos (axi_awqos), + .axi_awlen (axi_awlen), + .axi_awsize (axi_awsize), + .axi_awaddr (axi_awaddr), + .axi_awready (axi_awready), + .axi_wvalid (axi_wvalid), + .axi_wdata (axi_wdata), + .axi_wstrb (axi_wstrb), + .axi_wlast (axi_wlast), + .axi_wready (axi_wready), + .axi_bvalid (axi_bvalid), + .axi_bid (axi_bid), + .axi_bresp (axi_bresp), + .axi_bready (axi_bready), + .axi_werror (axi_werror)); + + axi_dacfifo_rd #( + .AXI_DATA_WIDTH (AXI_DATA_WIDTH), + .AXI_SIZE (AXI_SIZE), + .AXI_LENGTH (AXI_LENGTH), + .AXI_ADDRESS (AXI_ADDRESS), + .DAC_DATA_WIDTH (DAC_DATA_WIDTH), + .DAC_MEM_ADDRESS_WIDTH (12) + ) i_rd ( + .axi_xfer_req (axi_xfer_req_s), + .axi_last_raddr (axi_last_addr_s), + .axi_last_beats (axi_last_beats_s), + .axi_clk (axi_clk), + .axi_resetn (axi_resetn), + .axi_arvalid (axi_arvalid), + .axi_arid (axi_arid), + .axi_arburst (axi_arburst), + .axi_arlock (axi_arlock), + .axi_arcache (axi_arcache), + .axi_arprot (axi_arprot), + .axi_arqos (axi_arqos), + .axi_arlen (axi_arlen), + .axi_arsize (axi_arsize), + .axi_araddr (axi_araddr), + .axi_arready (axi_arready), + .axi_rvalid (axi_rvalid), + .axi_rid (axi_rid), + .axi_rresp (axi_rresp), + .axi_rlast (axi_rlast), + .axi_rdata (axi_rdata), + .axi_rready (axi_rready), + .axi_rerror (axi_rerror), + .dma_last_beats (dma_last_beats_s), + .dac_clk (dac_clk), + .dac_rst (dac_rst), + .dac_valid (dac_valid), + .dac_data (dac_data_fifo_s), + .dac_xfer_out (dac_xfer_fifo_out_s), + .dac_dunf (dac_dunf_fifo_s)); + + // bypass logic -- supported if DAC_DATA_WIDTH == DMA_DATA_WIDTH + + generate + if (FIFO_BYPASS) begin + + util_dacfifo_bypass #( + .DAC_DATA_WIDTH (DAC_DATA_WIDTH), + .DMA_DATA_WIDTH (DMA_DATA_WIDTH) + ) i_dacfifo_bypass ( + .dma_clk(dma_clk), + .dma_data(dma_data), + .dma_ready(dma_ready), + .dma_ready_out(dma_ready_bypass_s), + .dma_valid(dma_valid), + .dma_xfer_req(dma_xfer_req), + .dac_clk(dac_clk), + .dac_rst(dac_rst), + .dac_valid(dac_valid), + .dac_data(dac_data_bypass_s), + .dac_dunf(dac_dunf_bypass_s)); + + always @(posedge dma_clk) begin + dma_bypass_m1 <= bypass; + dma_bypass <= dma_bypass_m1; + end + + always @(posedge dac_clk) begin + dac_bypass_m1 <= bypass; + dac_bypass <= dac_bypass_m1; + dac_xfer_out_m1 <= dma_xfer_req; + dac_xfer_out_bypass <= dac_xfer_out_m1; + end + + // mux for the dma_ready + + always @(posedge dma_clk) begin + dma_ready <= (dma_bypass) ? dma_ready_bypass_s : dma_ready_wr_s; + end + + // mux for dac data + + always @(posedge dac_clk) begin + if (dac_valid) begin + dac_data <= (dac_bypass) ? dac_data_bypass_s : dac_data_fifo_s; + end + dac_xfer_out <= (dac_bypass) ? dac_xfer_out_bypass : dac_xfer_fifo_out_s; + dac_dunf <= (dac_bypass) ? dac_dunf_bypass_s : dac_dunf_fifo_s; + end + + end else begin /* if (~FIFO_BYPASS) */ + + always @(posedge dma_clk) begin + dma_ready <= dma_ready_wr_s; + end + always @(posedge dac_clk) begin + if (dac_valid) begin + dac_data <= dac_data_fifo_s; + end + dac_xfer_out <= dac_xfer_fifo_out_s; + dac_dunf <= dac_dunf_fifo_s; + end + + end + endgenerate + +endmodule diff --git a/adi_library/xilinx/axi_dacfifo/axi_dacfifo.xpr b/adi_library/xilinx/axi_dacfifo/axi_dacfifo.xpr new file mode 100644 index 00000000..5bd0e755 --- /dev/null +++ b/adi_library/xilinx/axi_dacfifo/axi_dacfifo.xpr @@ -0,0 +1,468 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v b/adi_library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v new file mode 100644 index 00000000..aed1457c --- /dev/null +++ b/adi_library/xilinx/axi_dacfifo/axi_dacfifo_address_buffer.v @@ -0,0 +1,78 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dacfifo_address_buffer #( + + parameter ADDRESS_WIDTH = 4, + parameter DATA_WIDTH = 16 +) ( + input clk, + input rst, + input wea, + input [DATA_WIDTH-1:0] din, + + input rea, + output [DATA_WIDTH-1:0] dout +); + + reg [ADDRESS_WIDTH-1:0] waddr; + reg [ADDRESS_WIDTH-1:0] raddr; + + always @(posedge clk) begin + if (rst == 1'b1) begin + waddr <= 0; + raddr <= 0; + end else begin + waddr <= (wea == 1'b1) ? waddr + 1'b1 : waddr; + raddr <= (rea == 1'b1) ? raddr + 1'b1 : raddr; + end + end + + ad_mem #( + .DATA_WIDTH (DATA_WIDTH), + .ADDRESS_WIDTH (ADDRESS_WIDTH) + ) i_mem ( + .clka (clk), + .wea (wea), + .addra (waddr), + .dina (din), + .clkb (clk), + .reb (1'b1), + .addrb (raddr), + .doutb (dout)); + +endmodule diff --git a/adi_library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc b/adi_library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc new file mode 100644 index 00000000..0eed1737 --- /dev/null +++ b/adi_library/xilinx/axi_dacfifo/axi_dacfifo_constr.xdc @@ -0,0 +1,57 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property ASYNC_REG TRUE \ + [get_cells -hier *dma_mem_*_m*] \ + [get_cells -hier *axi_xfer_*_m*] \ + [get_cells -hier *axi_mem_*_m*] \ + [get_cells -hier *axi_dma_*_m*] \ + [get_cells -hier *dac_mem_*_m*] \ + [get_cells -hier *dac_xfer_*_m*] \ + [get_cells -hier *dac_last_*_m*] \ + [get_cells -hier *dac_bypass_m*] + +# AXI clk to DMA clk +set_false_path -from [get_cells -hier -filter {name =~ */axi_mem_raddr_g* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ */dma_mem_raddr_m1* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ */axi_mem_last_read_toggle* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ */dma_mem_last_read_toggle_m_* && IS_SEQUENTIAL}] + +# DAC clk to DMA clk +set_false_path -from [get_cells -hier -filter {name =~ */dac_mem_raddr_g* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ */dma_mem_raddr_m1_* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ */dma_rst_m1_reg && IS_SEQUENTIAL}] + + +# DMA clk to AXI clk +set_false_path -from [get_cells -hier -filter {name =~ */dma_last_beats* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ */axi_dma_last_beats_m1* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ */dma_mem_waddr_g* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ */axi_mem_waddr_m1* && IS_SEQUENTIAL}] +#ignore timing only on the data, the synchronous reset of the FF is connected to the same clock domain +set_false_path -through [get_pins -hier -filter {name =~ */axi_xfer_req_m_reg[0]/D}] + +# DAC clk to AXI clk +set_false_path -from [get_cells -hier -filter {name =~ */dac_mem_raddr_g* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ */axi_mem_raddr_m1* && IS_SEQUENTIAL}] + +# DMA clk to DAC clk +set_false_path -from [get_cells -hier -filter {name =~ */dma_mem_waddr_g* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ */dac_mem_waddr_m1* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ */dma_last_beats* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ */dac_last_beats_m* && IS_SEQUENTIAL}] +#ignore timing only on the data, the synchronous reset of the FF is connected to the same clock domain +set_false_path -through [get_pins -hier -filter {name =~ */dac_xfer_out_m1_reg*/D}] + +# AXI clk to DAC clk +set_false_path -from [get_cells -hier -filter {name =~ */axi_mem_laddr* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ */dac_mem_laddr* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ */axi_mem_laddr_toggle* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ */dac_mem_laddr_toggle_m* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ */axi_mem_waddr_g* && IS_SEQUENTIAL}] \ + -to [get_cells -hier -filter {name =~ */dac_mem_waddr_m1* && IS_SEQUENTIAL}] +#ignore timing only on the data, the synchronous reset of the FF is connected to the same clock domain +set_false_path -through [get_pins -hier -filter {name =~ */dac_xfer_req_m_reg[0]/D}] + diff --git a/adi_library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl b/adi_library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl new file mode 100644 index 00000000..6b6a5475 --- /dev/null +++ b/adi_library/xilinx/axi_dacfifo/axi_dacfifo_ip.tcl @@ -0,0 +1,89 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# ip +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create axi_dacfifo + +adi_ip_files axi_dacfifo [list \ + "$ad_hdl_dir/library/common/ad_g2b.v" \ + "$ad_hdl_dir/library/common/ad_b2g.v" \ + "$ad_hdl_dir/library/common/ad_mem_asym.v" \ + "$ad_hdl_dir/library/common/ad_mem.v" \ + "$ad_hdl_dir/library/common/ad_axis_inf_rx.v" \ + "$ad_hdl_dir/library/util_dacfifo/util_dacfifo_bypass.v" \ + "axi_dacfifo_constr.xdc" \ + "axi_dacfifo_wr.v" \ + "axi_dacfifo_rd.v" \ + "axi_dacfifo_address_buffer.v" \ + "axi_dacfifo.v"] + +adi_ip_properties_lite axi_dacfifo + +ipx::infer_bus_interface {\ + axi_awvalid \ + axi_awid \ + axi_awburst \ + axi_awlock \ + axi_awcache \ + axi_awprot \ + axi_awqos \ + axi_awlen \ + axi_awsize \ + axi_awaddr \ + axi_awready \ + axi_wvalid \ + axi_wdata \ + axi_wstrb \ + axi_wlast \ + axi_wready \ + axi_bvalid \ + axi_bid \ + axi_bresp \ + axi_bready \ + axi_arvalid \ + axi_arid \ + axi_arburst \ + axi_arlock \ + axi_arcache \ + axi_arprot \ + axi_arqos \ + axi_arlen \ + axi_arsize \ + axi_araddr \ + axi_arready \ + axi_rvalid \ + axi_rid \ + axi_rresp \ + axi_rlast \ + axi_rdata \ + axi_rready} \ +xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] + +ipx::infer_bus_interface axi_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface axi_resetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] +ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces axi_clk \ + -of_objects [ipx::current_core]] +set_property value axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ + -of_objects [ipx::get_bus_interfaces axi_clk \ + -of_objects [ipx::current_core]]] + +ipx::add_address_space axi [ipx::current_core] +set_property master_address_space_ref axi [ipx::get_bus_interfaces axi \ + -of_objects [ipx::current_core]] +set_property range 4294967296 [ipx::get_address_spaces axi \ + -of_objects [ipx::current_core]] +set_property width 512 [ipx::get_address_spaces axi \ + -of_objects [ipx::current_core]] + +ipx::infer_bus_interface dma_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface dma_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface dac_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface dac_rst xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] + diff --git a/adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v b/adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v new file mode 100644 index 00000000..549f1a04 --- /dev/null +++ b/adi_library/xilinx/axi_dacfifo/axi_dacfifo_rd.v @@ -0,0 +1,483 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module axi_dacfifo_rd #( + + parameter AXI_DATA_WIDTH = 512, + parameter AXI_SIZE = 2, + parameter AXI_LENGTH = 15, + parameter AXI_ADDRESS = 32'h00000000, + parameter DAC_DATA_WIDTH = 64, + parameter DAC_MEM_ADDRESS_WIDTH = 8 +) ( + + // xfer last for read/write synchronization + + input axi_xfer_req, + input [31:0] axi_last_raddr, + input [ 7:0] axi_last_beats, + + // axi read address and read data channels + + input axi_clk, + input axi_resetn, + output reg axi_arvalid, + output [ 3:0] axi_arid, + output [ 1:0] axi_arburst, + output axi_arlock, + output [ 3:0] axi_arcache, + output [ 2:0] axi_arprot, + output [ 3:0] axi_arqos, + output [ 7:0] axi_arlen, + output [ 2:0] axi_arsize, + output reg [31:0] axi_araddr, + input axi_arready, + input axi_rvalid, + input [ 3:0] axi_rid, + input [ 1:0] axi_rresp, + input axi_rlast, + input [(AXI_DATA_WIDTH-1):0] axi_rdata, + output reg axi_rready, + + // axi status + + output reg axi_rerror, + + // DAC interface + + input [ 3:0] dma_last_beats, + + input dac_clk, + input dac_rst, + input dac_valid, + output [(DAC_DATA_WIDTH-1):0] dac_data, + output dac_xfer_out, + output reg dac_dunf +); + + `define max(a,b) {(a) > (b) ? (a) : (b)} + `define min(a,b) {(a) < (b) ? (a) : (b)} + + localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8; + localparam AXI_ARINCR = (AXI_LENGTH + 1) * AXI_BYTE_WIDTH; + + localparam MIN_WIDTH = `min(AXI_DATA_WIDTH, DAC_DATA_WIDTH); + localparam MAX_WIDTH = `max(AXI_DATA_WIDTH, DAC_DATA_WIDTH); + localparam MEM_RATIO = MAX_WIDTH/MIN_WIDTH; + localparam AXI_BIGGER = (MAX_WIDTH == AXI_DATA_WIDTH) ? 1 : 0; + + localparam AXI_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DAC_MEM_ADDRESS_WIDTH : + (MEM_RATIO == 2) ? (DAC_MEM_ADDRESS_WIDTH + ((AXI_BIGGER == 1) ? (-1) : 1)) : + (MEM_RATIO == 4) ? (DAC_MEM_ADDRESS_WIDTH + ((AXI_BIGGER == 1) ? (-2) : 2)) : + (MEM_RATIO == 8) ? (DAC_MEM_ADDRESS_WIDTH + ((AXI_BIGGER == 1) ? (-3) : 3)) : + (DAC_MEM_ADDRESS_WIDTH + ((AXI_BIGGER == 1) ? (-4) : 4)); + + localparam AXI_BUF_THRESHOLD_HI = (AXI_BIGGER) ? (2 * (AXI_LENGTH+1)) : (2 * (AXI_LENGTH+1) * MEM_RATIO); + localparam DAC_BUF_THRESHOLD_HI = (AXI_BIGGER) ? (2 * (AXI_LENGTH+1) * MEM_RATIO) : (2 * (AXI_LENGTH+1)); + + localparam IDLE = 5'b00001; + localparam XFER_STAGING = 5'b00010; + localparam XFER_FULL_BURST = 5'b00100; + localparam XFER_PARTIAL_BURST = 5'b01000; + localparam XFER_END = 5'b10000; + + // internal registers + + reg axi_data_req = 1'b0; + reg [ 4:0] axi_read_state = 5'b0; + reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr = 'd0; + (* dont_touch = "true" *) reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_laddr = 'd0; + reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_g = 'd0; + (* dont_touch = "true" *) reg axi_mem_laddr_toggle = 1'b0; + reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr = 'd0; + reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_m1 = 'd0; + reg [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_m2 = 'd0; + reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_addr_diff = 'd0; + reg [31:0] axi_araddr_prev = 'd0; + + reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_raddr = 'd0; + reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_raddr_g = 'd0; + reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_waddr = 'd0; + reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_waddr_m1 = 'd0; + reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2 = 'd0; + reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_laddr = 'd0; + reg [ 3:0] dac_mem_laddr_toggle_m = 4'd0; + reg [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_laddr_b = 'd0; + reg dac_mem_valid = 1'b0; + reg dac_mem_enable = 1'b0; + reg [ 2:0] dac_xfer_req_m = 3'b0; + reg [ 3:0] dac_last_beats = 4'b0; + reg [ 3:0] dac_last_beats_m = 4'b0; + + // internal signals + + wire axi_fifo_reset_s; + wire axi_dvalid_s; + wire axi_dlast_s; + wire [ AXI_MEM_ADDRESS_WIDTH:0] axi_mem_addr_diff_s; + wire [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_s; + wire [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_s; + wire [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_laddr_s; + wire [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_b2g_s; + wire [(DAC_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_m2_g2b_s; + + wire [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_raddr_b2g_s; + wire [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2_g2b_s; + wire [ DAC_MEM_ADDRESS_WIDTH:0] dac_mem_addr_diff_s; + wire [(DAC_MEM_ADDRESS_WIDTH-1):0] dac_mem_laddr_s; + + // Asymmetric memory to transfer data from AXI_MM interface to DAC FIFO + // interface + + ad_mem_asym #( + .A_ADDRESS_WIDTH (AXI_MEM_ADDRESS_WIDTH), + .A_DATA_WIDTH (AXI_DATA_WIDTH), + .B_ADDRESS_WIDTH (DAC_MEM_ADDRESS_WIDTH), + .B_DATA_WIDTH (DAC_DATA_WIDTH) + ) i_mem_asym ( + .clka (axi_clk), + .wea (axi_dvalid_s), + .addra (axi_mem_waddr), + .dina (axi_rdata), + .clkb (dac_clk), + .reb (1'b1), + .addrb (dac_mem_raddr), + .doutb (dac_data)); + + // reset signals + + assign axi_fifo_reset_s = (axi_resetn == 1'b0) || (axi_xfer_req == 1'b0); + assign dac_fifo_reset_s = (dac_rst == 1'b1) || (dac_xfer_req_m[2] == 1'b0); + + // FSM to generate the all the AXI Read transactions + + always @(posedge axi_clk) begin + if (axi_fifo_reset_s == 1'b1) begin + axi_read_state <= IDLE; + end else begin + case (axi_read_state) + IDLE : begin + if (axi_data_req == 1'b1) begin + axi_read_state <= XFER_STAGING; + end else begin + axi_read_state <= IDLE; + end + end + XFER_STAGING : begin + if (axi_araddr + AXI_ARINCR <= axi_last_raddr) begin + axi_read_state <= XFER_FULL_BURST; + end else begin + axi_read_state <= XFER_PARTIAL_BURST; + end + end + XFER_FULL_BURST : begin + if (axi_rready && axi_rvalid && axi_rlast) begin + if (axi_araddr_prev == axi_last_raddr) begin + axi_read_state <= XFER_END; + end else begin + axi_read_state <= IDLE; + end + end else begin + axi_read_state <= XFER_FULL_BURST; + end + end + XFER_PARTIAL_BURST : begin + if (axi_rready && axi_rvalid && axi_rlast) begin + axi_read_state <= XFER_END; + end else begin + axi_read_state <= XFER_PARTIAL_BURST; + end + end + XFER_END : begin + axi_read_state <= IDLE; + end + default : begin + axi_read_state <= IDLE; + end + endcase + end + end + + // AXI read address channel + + always @(posedge axi_clk) begin + if (axi_fifo_reset_s == 1'b1) begin + axi_arvalid <= 'd0; + axi_araddr <= AXI_ADDRESS; + axi_araddr_prev <= AXI_ADDRESS; + end else begin + if (axi_arvalid == 1'b1) begin + if (axi_arready == 1'b1) begin + axi_arvalid <= 1'b0; + end + end else begin + if (axi_read_state == XFER_STAGING) begin + axi_arvalid <= 1'b1; + end + end + // AXI read address generation + if ((axi_arvalid == 1'b1) && (axi_arready == 1'b1)) begin + axi_araddr <= (axi_read_state == XFER_FULL_BURST) ? (axi_araddr + AXI_ARINCR) : + (axi_read_state == XFER_PARTIAL_BURST) ? AXI_ADDRESS : axi_araddr; + axi_araddr_prev <= axi_araddr; + end + end + end + + assign axi_arid = 4'b0000; + assign axi_arburst = 2'b01; + assign axi_arlock = 1'b0; + assign axi_arcache = 4'b0010; + assign axi_arprot = 3'b000; + assign axi_arqos = 4'b0000; + assign axi_arlen = (axi_read_state == XFER_FULL_BURST) ? AXI_LENGTH : + (axi_read_state == XFER_PARTIAL_BURST) ? axi_last_beats : AXI_LENGTH; + assign axi_arsize = AXI_SIZE; + + // AXI read data channel + + assign axi_dvalid_s = axi_rvalid & axi_rready & axi_xfer_req; + assign axi_dlast_s = (axi_araddr_prev == axi_last_raddr) ? axi_rlast : 0; + + always @(posedge axi_clk) begin + if (axi_fifo_reset_s == 1'b1) begin + axi_rready <= 1'b0; + axi_rerror <= 'd0; + end else begin + axi_rready <= axi_rvalid; + axi_rerror <= axi_rvalid & axi_rresp[1]; + end + end + + // ASYNC MEM write control + + always @(posedge axi_clk) begin + if (axi_fifo_reset_s == 1'b1) begin + axi_mem_waddr <= 'd0; + axi_mem_waddr_g <= 'd0; + axi_mem_laddr <= {AXI_MEM_ADDRESS_WIDTH{1'b1}}; + axi_mem_laddr_toggle <= 0; + end else begin + if (axi_dvalid_s == 1'b1) begin + axi_mem_waddr <= axi_mem_waddr + 1'b1; + if (axi_dlast_s == 1'b1) begin + axi_mem_laddr <= axi_mem_waddr; + axi_mem_laddr_toggle <= ~axi_mem_laddr_toggle; + end + end + axi_mem_waddr_g <= axi_mem_waddr_b2g_s; + end + end + + ad_b2g #( + .DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH) + ) i_axi_mem_waddr_b2g ( + .din (axi_mem_waddr_s), + .dout (axi_mem_waddr_b2g_s)); + + assign axi_mem_raddr_s = (MEM_RATIO == 1) ? axi_mem_raddr : + (MEM_RATIO == 2) ? ((AXI_BIGGER == 1) ? axi_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):1] : {axi_mem_raddr, 1'b0}) : + (MEM_RATIO == 4) ? ((AXI_BIGGER == 1) ? axi_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):2] : {axi_mem_raddr, 2'b0}) : + (MEM_RATIO == 8) ? ((AXI_BIGGER == 1) ? axi_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):3] : {axi_mem_raddr, 3'b0}) : + ((AXI_BIGGER == 1) ? axi_mem_raddr[(DAC_MEM_ADDRESS_WIDTH-1):4] : {axi_mem_raddr, 4'b0}); + assign axi_mem_waddr_s = (MEM_RATIO == 1) ? axi_mem_waddr : + (MEM_RATIO == 2) ? ((AXI_BIGGER == 1) ? {axi_mem_waddr, 1'b0} : axi_mem_waddr[AXI_MEM_ADDRESS_WIDTH-1:1]) : + (MEM_RATIO == 4) ? ((AXI_BIGGER == 1) ? {axi_mem_waddr, 2'b0} : axi_mem_waddr[AXI_MEM_ADDRESS_WIDTH-1:2]) : + (MEM_RATIO == 8) ? ((AXI_BIGGER == 1) ? {axi_mem_waddr, 3'b0} : axi_mem_waddr[AXI_MEM_ADDRESS_WIDTH-1:3]) : + ((AXI_BIGGER == 1) ? {axi_mem_waddr, 4'b0} : axi_mem_waddr[AXI_MEM_ADDRESS_WIDTH-1:4]); + + assign axi_mem_laddr_s = (MEM_RATIO == 1) ? axi_mem_laddr : + (MEM_RATIO == 2) ? ((AXI_BIGGER == 1) ? {axi_mem_laddr, 1'b0} : axi_mem_laddr[AXI_MEM_ADDRESS_WIDTH-1:1]) : + (MEM_RATIO == 4) ? ((AXI_BIGGER == 1) ? {axi_mem_laddr, 2'b0} : axi_mem_laddr[AXI_MEM_ADDRESS_WIDTH-1:2]) : + (MEM_RATIO == 8) ? ((AXI_BIGGER == 1) ? {axi_mem_laddr, 3'b0} : axi_mem_laddr[AXI_MEM_ADDRESS_WIDTH-1:3]) : + ((AXI_BIGGER == 1) ? {axi_mem_laddr, 4'b0} : axi_mem_laddr[AXI_MEM_ADDRESS_WIDTH-1:4]); + + assign axi_mem_addr_diff_s = {1'b1, axi_mem_waddr} - axi_mem_raddr_s; + + always @(posedge axi_clk) begin + if (axi_fifo_reset_s == 1'b1) begin + axi_mem_addr_diff <= 'd0; + axi_mem_raddr <= 'd0; + axi_mem_raddr_m1 <= 'd0; + axi_mem_raddr_m2 <= 'd0; + axi_data_req <= 'd0; + end else begin + axi_mem_raddr_m1 <= dac_mem_raddr_g; + axi_mem_raddr_m2 <= axi_mem_raddr_m1; + axi_mem_raddr <= axi_mem_raddr_m2_g2b_s; + axi_mem_addr_diff <= axi_mem_addr_diff_s[AXI_MEM_ADDRESS_WIDTH-1:0]; + // requesting AXI read access from the memory, if there is enough space + // for a full burst in the async buffer + if (axi_mem_addr_diff >= AXI_BUF_THRESHOLD_HI) begin + axi_data_req <= 1'b0; + end else begin + axi_data_req <= 1'b1; + end + end + end + + ad_g2b #( + .DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH) + ) i_axi_mem_raddr_m2_g2b ( + .din (axi_mem_raddr_m2), + .dout (axi_mem_raddr_m2_g2b_s)); + + // CDC for xfer_req signal + + always @(posedge dac_clk) begin + if (dac_rst == 1'b1) begin + dac_xfer_req_m <= 3'b0; + end else begin + dac_xfer_req_m <= {dac_xfer_req_m[1:0], axi_xfer_req}; + end + end + + assign dac_xfer_out = dac_xfer_req_m[2] & dac_mem_valid; + + // CDC for write addresses from the DDRx clock domain + always @(posedge dac_clk) begin + if (dac_fifo_reset_s == 1'b1) begin + dac_mem_waddr <= 'b0; + dac_mem_waddr_m1 <= 'b0; + dac_mem_waddr_m2 <= 'b0; + dac_mem_laddr_toggle_m <= 4'b0; + dac_mem_laddr <= 'b0; + end else begin + dac_mem_waddr_m1 <= axi_mem_waddr_g; + dac_mem_waddr_m2 <= dac_mem_waddr_m1; + dac_mem_waddr <= dac_mem_waddr_m2_g2b_s; + dac_mem_laddr_toggle_m <= {dac_mem_laddr_toggle_m[2:0], axi_mem_laddr_toggle}; + dac_mem_laddr <= (dac_mem_laddr_toggle_m[2] ^ dac_mem_laddr_toggle_m[1]) ? + axi_mem_laddr_s : + dac_mem_laddr; + end + end + + assign dac_laddr_wea = dac_mem_laddr_toggle_m[3] ^ dac_mem_laddr_toggle_m[2]; + assign dac_laddr_rea = ((dac_mem_raddr == dac_mem_laddr_b) && + (dac_xfer_out == 1'b1)) ? 1'b1 :1'b0; + + axi_dacfifo_address_buffer #( + .ADDRESS_WIDTH (4), + .DATA_WIDTH (DAC_MEM_ADDRESS_WIDTH) + ) i_laddress_buffer ( + .clk (dac_clk), + .rst (dac_fifo_reset_s), + .wea (dac_laddr_wea), + .din (dac_mem_laddr), + .rea (dac_laddr_rea), + .dout (dac_mem_laddr_s)); + + ad_g2b #( + .DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH) + ) i_dac_mem_waddr_m2_g2b ( + .din (dac_mem_waddr_m2), + .dout (dac_mem_waddr_m2_g2b_s)); + + assign dac_mem_addr_diff_s = {1'b1, dac_mem_waddr} - dac_mem_raddr; + + // ASYNC MEM read control + + always @(posedge dac_clk) begin + if (dac_fifo_reset_s == 1'b1) begin + dac_mem_enable <= 1'b0; + dac_mem_valid <= 1'b0; + end else begin + if (dac_mem_dunf_s == 1'b1) begin + dac_mem_enable <= 1'b0; + end else if (dac_mem_addr_diff_s[(DAC_MEM_ADDRESS_WIDTH-1):0] >= DAC_BUF_THRESHOLD_HI) begin + dac_mem_enable <= 1'b1; + end + dac_mem_valid <= (dac_mem_enable) ? dac_valid : 1'b0; + end + end + + // CDC for the dma_last_beats + + always @(posedge dac_clk) begin + if (dac_fifo_reset_s == 1'b1) begin + dac_last_beats <= 4'b0; + dac_last_beats_m <= 4'b0; + end else begin + dac_last_beats_m <= dma_last_beats; + dac_last_beats <= dac_last_beats_m; + end + end + + // If the MEM_RATIO is grater than one, it can happen that not all the DAC beats from + // an AXI beat are valid. In this case the invalid data is dropped. + // The axi_dlast indicates the last AXI beat. The valid number of DAC beats on the last AXI beat + // commes from the AXI write module. (axi_dacfifo_wr.v) + + always @(posedge dac_clk) begin + if (dac_fifo_reset_s == 1'b1) begin + dac_mem_raddr <= 'd0; + dac_mem_laddr_b <= 'd0; + dac_mem_raddr_g <= 'd0; + end else begin + dac_mem_laddr_b <= dac_mem_laddr_s; + if (dac_mem_valid == 1'b1) begin + if ((dac_last_beats != 0) && + (dac_mem_raddr == (dac_mem_laddr_b + dac_last_beats - 1))) begin + dac_mem_raddr <= dac_mem_raddr + (MEM_RATIO - (dac_last_beats - 1)); + end else begin + dac_mem_raddr <= dac_mem_raddr + 1'b1; + end + end + dac_mem_raddr_g <= dac_mem_raddr_b2g_s; + end + end + + ad_b2g #( + .DATA_WIDTH(DAC_MEM_ADDRESS_WIDTH) + ) i_dac_mem_raddr_b2g ( + .din (dac_mem_raddr), + .dout (dac_mem_raddr_b2g_s)); + + // underflow generation, there is no overflow + + assign dac_mem_dunf_s = (dac_mem_addr_diff_s[(DAC_MEM_ADDRESS_WIDTH-1):0] == 0) ? 1'b1 : 1'b0; + + always @(posedge dac_clk) begin + if(dac_fifo_reset_s == 1'b1) begin + dac_dunf <= 1'b0; + end else begin + dac_dunf <= dac_mem_dunf_s; + end + end + +endmodule diff --git a/adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v b/adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v new file mode 100644 index 00000000..66bb6b4b --- /dev/null +++ b/adi_library/xilinx/axi_dacfifo/axi_dacfifo_wr.v @@ -0,0 +1,567 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +`timescale 1ns/100ps + +module axi_dacfifo_wr #( + + parameter AXI_DATA_WIDTH = 512, + parameter DMA_DATA_WIDTH = 64, + parameter AXI_SIZE = 6, + parameter AXI_LENGTH = 15, + parameter AXI_ADDRESS = 32'h00000000, + parameter AXI_ADDRESS_LIMIT = 32'h00000000, + parameter DMA_MEM_ADDRESS_WIDTH = 8 +) ( + + // dma fifo interface + + input dma_clk, + input dma_rst, + input [(DMA_DATA_WIDTH-1):0] dma_data, + input dma_ready, + output reg dma_ready_out, + input dma_valid, + + // request and syncronizaiton + + input dma_xfer_req, + input dma_xfer_last, + (* dont_touch = "true" *) output reg [ 3:0] dma_last_beats, + + // last address for read side + + output reg [31:0] axi_last_addr, + output reg [ 7:0] axi_last_beats, + output reg axi_xfer_out, + + // axi write address, write data and write response channels + + input axi_clk, + input axi_resetn, + output reg axi_awvalid, + output [ 3:0] axi_awid, + output [ 1:0] axi_awburst, + output axi_awlock, + output [ 3:0] axi_awcache, + output [ 2:0] axi_awprot, + output [ 3:0] axi_awqos, + output [ 7:0] axi_awlen, + output [ 2:0] axi_awsize, + output reg [31:0] axi_awaddr, + input axi_awready, + output axi_wvalid, + output [(AXI_DATA_WIDTH-1):0] axi_wdata, + output [((AXI_DATA_WIDTH/8)-1):0] axi_wstrb, + output axi_wlast, + input axi_wready, + input axi_bvalid, + input [ 3:0] axi_bid, + input [ 1:0] axi_bresp, + output axi_bready, + + output reg axi_werror +); + + `define max(a,b) {(a) > (b) ? (a) : (b)} + `define min(a,b) {(a) < (b) ? (a) : (b)} + + localparam MIN_WIDTH = `min(AXI_DATA_WIDTH, DMA_DATA_WIDTH); + localparam MAX_WIDTH = `max(AXI_DATA_WIDTH, DMA_DATA_WIDTH); + localparam MEM_RATIO = MAX_WIDTH/MIN_WIDTH; + localparam AXI_BIGGER = (MAX_WIDTH == AXI_DATA_WIDTH) ? 1 : 0; + + localparam AXI_MEM_ADDRESS_WIDTH = (MEM_RATIO == 1) ? DMA_MEM_ADDRESS_WIDTH : + (MEM_RATIO == 2) ? (DMA_MEM_ADDRESS_WIDTH + ((AXI_BIGGER == 1) ? (-1) : 1)) : + (MEM_RATIO == 4) ? (DMA_MEM_ADDRESS_WIDTH + ((AXI_BIGGER == 1) ? (-2) : 2)) : + (MEM_RATIO == 8) ? (DMA_MEM_ADDRESS_WIDTH + ((AXI_BIGGER == 1) ? (-3) : 3)) : + (DMA_MEM_ADDRESS_WIDTH + ((AXI_BIGGER == 1) ? (-4) : 4)); + + localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8; + localparam AXI_AWINCR = (AXI_LENGTH + 1) * AXI_BYTE_WIDTH; + localparam DMA_BUF_THRESHOLD_HI = {(DMA_MEM_ADDRESS_WIDTH){1'b1}} - 4; + + // FSM state definition + + localparam IDLE = 9'b000000001; + localparam XFER_STAGING = 9'b000000010; + localparam XFER_FULL_BURST = 9'b000000100; + localparam XFER_FB_WLAST = 9'b000001000; + localparam XFER_PARTIAL_BURST = 9'b000010000; + localparam XFER_PB_WLAST = 9'b000100000; + localparam XFER_LAST_BURST = 9'b001000000; + localparam XFER_LB_WLAST = 9'b010000000; + localparam XFER_END = 9'b100000000; + + // registers + + reg [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_waddr = 'd0; + reg [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_waddr_g = 'd0; + reg [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_addr_diff = 'd0; + reg [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr_m1 = 'd0; + reg [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2 = 'd0; + reg [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr = 'd0; + reg [ 2:0] dma_mem_last_read_toggle_m = 3'b0; + reg [ 1:0] dma_xfer_req_d = 2'b0; + + reg [(DMA_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_m1 = 'd0; + reg [(DMA_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_m2 = 'd0; + reg [(DMA_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr = 'd0; + reg axi_mem_rvalid = 1'b0; + reg axi_mem_rvalid_d = 1'b0; + reg axi_mem_last = 1'b0; + reg axi_mem_last_d = 1'b0; + reg [(AXI_DATA_WIDTH-1):0] axi_mem_rdata = 'd0; + reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr = 'd0; + reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_g = 'd0; + reg axi_mem_read_en_d = 1'b0; + reg [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_addr_diff = 'd0; + reg axi_mem_last_read_toggle = 1'b0; + reg [ 2:0] axi_xfer_req_m = 3'b0; + reg axi_xfer_posedge = 1'b0; + reg [ 7:0] axi_wvalid_counter = 8'b0; + reg [ 7:0] axi_last_burst_length = 8'b0; + (* dont_touch = "true" *)reg [ 8:0] axi_writer_state = 9'b0; + reg [ 3:0] axi_dma_last_beats_m1 = 4'b0; + reg [ 3:0] axi_dma_last_beats_m2 = 4'b0; + reg axi_xlast; + reg [ 3:0] axi_xfer_pburst_offset = 4'b1111; + + // internal signals + + wire dma_fifo_reset_s; + wire [(DMA_MEM_ADDRESS_WIDTH):0] dma_mem_addr_diff_s; + wire [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr_s; + wire dma_mem_last_read_s; + wire dma_xfer_posedge_s; + wire dma_mem_wea_s; + wire [(DMA_MEM_ADDRESS_WIDTH-1):0] dma_mem_waddr_b2g_s; + wire [(AXI_MEM_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2_g2b_s; + wire axi_mem_read_en_s; + wire [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_s; + wire [AXI_MEM_ADDRESS_WIDTH:0] axi_mem_addr_diff_s; + wire [(AXI_DATA_WIDTH-1):0] axi_mem_rdata_s; + wire axi_mem_rvalid_s; + wire axi_mem_last_s; + wire [(DMA_MEM_ADDRESS_WIDTH-1):0] axi_mem_waddr_m2_g2b_s; + wire [(AXI_MEM_ADDRESS_WIDTH-1):0] axi_mem_raddr_b2g_s; + wire axi_fifo_reset_s; + wire axi_waddr_ready_s; + wire axi_wready_s; + wire axi_partial_burst_s; + wire axi_xlast_s; + wire axi_reset_s; + + // Asymmetric memory to transfer data from DMAC interface to AXI Memory Map + // interface + + ad_mem_asym #( + .A_ADDRESS_WIDTH (DMA_MEM_ADDRESS_WIDTH), + .A_DATA_WIDTH (DMA_DATA_WIDTH), + .B_ADDRESS_WIDTH (AXI_MEM_ADDRESS_WIDTH), + .B_DATA_WIDTH (AXI_DATA_WIDTH) + ) i_mem_asym ( + .clka (dma_clk), + .wea (dma_mem_wea_s), + .addra (dma_mem_waddr), + .dina (dma_data), + .clkb (axi_clk), + .reb (1'b1), + .addrb (axi_mem_raddr), + .doutb (axi_mem_rdata_s)); + + assign axi_reset_s = ~axi_resetn; + ad_axis_inf_rx #( + .DATA_WIDTH(AXI_DATA_WIDTH) + ) i_axis_inf ( + .clk (axi_clk), + .rst (axi_reset_s), + .valid (axi_mem_rvalid_d), + .last (axi_mem_last_d), + .data (axi_mem_rdata), + .inf_valid (axi_wvalid), + .inf_last (axi_wlast), + .inf_data (axi_wdata), + .inf_ready (axi_wready)); + + // reset signals - all the registers reset at the positive edge of + // dma_xfer_req + + assign dma_xfer_posedge_s = ~dma_xfer_req_d[1] & dma_xfer_req_d[0]; + assign dma_fifo_reset_s = (dma_rst == 1'b1) || (dma_xfer_posedge_s == 1'b1); + assign axi_fifo_reset_s = (axi_resetn == 1'b0) || (axi_xfer_posedge == 1'b1); + + // DMA beat counter + + always @(posedge dma_clk) begin + dma_xfer_req_d <= {dma_xfer_req_d[0], dma_xfer_req}; + if (dma_fifo_reset_s == 1'b1) begin + dma_last_beats <= 4'b0; + end else begin + if (dma_mem_wea_s == 1'b1) begin + dma_last_beats <= (AXI_BIGGER == 1) ? ((dma_last_beats < MEM_RATIO-1) ? dma_last_beats + 4'b1 : 4'b0) : 4'b0; + end + end + end + + // ASYNC MEM write control + + assign dma_mem_addr_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s; + assign dma_mem_raddr_s = (MEM_RATIO == 1) ? dma_mem_raddr : + (MEM_RATIO == 2) ? ((AXI_BIGGER == 1) ? {dma_mem_raddr, 1'b0} : dma_mem_raddr[AXI_MEM_ADDRESS_WIDTH-1:1]) : + (MEM_RATIO == 4) ? ((AXI_BIGGER == 1) ? {dma_mem_raddr, 2'b0} : dma_mem_raddr[AXI_MEM_ADDRESS_WIDTH-1:2]) : + (MEM_RATIO == 8) ? ((AXI_BIGGER == 1) ? {dma_mem_raddr, 3'b0} : dma_mem_raddr[AXI_MEM_ADDRESS_WIDTH-1:3]) : + ((AXI_BIGGER == 1) ? {dma_mem_raddr, 4'b0} : dma_mem_raddr[AXI_MEM_ADDRESS_WIDTH-1:4]); + assign dma_mem_last_read_s = dma_mem_last_read_toggle_m[2] ^ dma_mem_last_read_toggle_m[1]; + assign dma_mem_wea_s = dma_xfer_req & dma_valid & dma_ready; + + always @(posedge dma_clk) begin + if (dma_fifo_reset_s == 1'b1) begin + dma_mem_waddr <= 'h0; + dma_mem_waddr_g <= 'h0; + dma_mem_last_read_toggle_m <= 3'b0; + end else begin + dma_mem_last_read_toggle_m = {dma_mem_last_read_toggle_m[1:0], axi_mem_last_read_toggle}; + if (dma_mem_wea_s == 1'b1) begin + dma_mem_waddr <= dma_mem_waddr + 1; + end + if (dma_mem_last_read_s == 1'b1) begin + dma_mem_waddr <= 'h0; + end + dma_mem_waddr_g <= dma_mem_waddr_b2g_s; + end + end + + ad_b2g #( + .DATA_WIDTH(DMA_MEM_ADDRESS_WIDTH) + ) i_dma_mem_waddr_b2g ( + .din (dma_mem_waddr), + .dout (dma_mem_waddr_b2g_s)); + + // The memory module request data until reaches the high threshold + + always @(posedge dma_clk) begin + if (dma_fifo_reset_s == 1'b1) begin + dma_mem_addr_diff <= 'b0; + dma_mem_raddr_m1 <= 'b0; + dma_mem_raddr_m2 <= 'b0; + dma_mem_raddr <= 'b0; + dma_ready_out <= 1'b1; + end else begin + dma_mem_raddr_m1 <= axi_mem_raddr_g; + dma_mem_raddr_m2 <= dma_mem_raddr_m1; + dma_mem_raddr <= dma_mem_raddr_m2_g2b_s; + dma_mem_addr_diff <= dma_mem_addr_diff_s[DMA_MEM_ADDRESS_WIDTH-1:0]; + if (dma_mem_addr_diff >= DMA_BUF_THRESHOLD_HI) begin + dma_ready_out <= 1'b0; + end else begin + dma_ready_out <= 1'b1; + end + end + end + + ad_g2b #( + .DATA_WIDTH(AXI_MEM_ADDRESS_WIDTH) + ) i_dma_mem_raddr_g2b ( + .din (dma_mem_raddr_m2), + .dout (dma_mem_raddr_m2_g2b_s)); + + assign axi_xlast_s = axi_wready & axi_wvalid & axi_wlast; + + // FSM to generate the necessary AXI Write transactions + + always @(posedge axi_clk) begin + if (axi_fifo_reset_s == 1'b1) begin + axi_writer_state <= IDLE; + axi_xlast <= 1'b0; + end + else + axi_xlast <= axi_xlast_s; + case (axi_writer_state) + IDLE : begin + if (axi_xfer_req_m[2] == 1'b1) begin + axi_writer_state <= XFER_STAGING; + end else begin + axi_writer_state <= IDLE; + end + end + XFER_STAGING : begin + if (axi_xfer_req_m[2] == 1'b1) begin + // there are enough data for one transaction + if (axi_mem_addr_diff >= AXI_LENGTH) begin + axi_writer_state <= XFER_FULL_BURST; + end else begin + axi_writer_state <= XFER_STAGING; + end + end else if (axi_xfer_pburst_offset == 4'b0) begin // DMA transfer was finished + if ((axi_mem_addr_diff > 0) || + (axi_dma_last_beats_m2 > 0)) begin + axi_writer_state <= XFER_PARTIAL_BURST; + end else begin + axi_writer_state <= XFER_END; + end + end else begin + axi_writer_state <= XFER_STAGING; + end + end + // AXI transaction with full burst length + XFER_FULL_BURST : begin + if ((axi_wvalid_counter == axi_awlen) && (axi_mem_rvalid_s == 1'b1)) begin + axi_writer_state <= XFER_FB_WLAST; + end else begin + axi_writer_state <= XFER_FULL_BURST; + end + end + // Wait for the end of the transaction + XFER_FB_WLAST : begin + if (axi_xlast == 1'b1) begin + axi_writer_state <= XFER_STAGING; + end else begin + axi_writer_state <= XFER_FB_WLAST; + end + end + // AXI transaction with the remaining data, burst length is less than + // the maximum supported burst length + XFER_PARTIAL_BURST : begin + if ((axi_wvalid_counter == axi_awlen) && (axi_mem_rvalid_s == 1'b1)) begin + axi_writer_state <= XFER_PB_WLAST; + end else begin + axi_writer_state <= XFER_PARTIAL_BURST; + end + end + // Wait for the end of the transaction + XFER_PB_WLAST : begin + if (axi_xlast == 1'b1) begin + axi_writer_state <= XFER_END; + end else begin + axi_writer_state <= XFER_PB_WLAST; + end + end + XFER_END : begin + axi_writer_state <= IDLE; + end + default : begin + axi_writer_state <= IDLE; + end + endcase + end + + // FSM outputs + + assign axi_mem_read_en_s = ((axi_writer_state == XFER_FULL_BURST) || + (axi_writer_state == XFER_PARTIAL_BURST)) ? 1 : 0; + assign axi_partial_burst_s = ((axi_writer_state == XFER_PARTIAL_BURST) || + (axi_writer_state == XFER_PB_WLAST)) ? 1 : 0; + + // CDC for the memory write address, xfer_req and xfer_last + + always @(posedge axi_clk) begin + if (axi_resetn == 1'b0) begin + axi_xfer_req_m <= 3'b0; + axi_xfer_posedge <= 1'b0; + end else begin + axi_xfer_req_m <= {axi_xfer_req_m[1:0], dma_xfer_req}; + axi_xfer_posedge <= ~axi_xfer_req_m[2] & axi_xfer_req_m[1]; + end + end + + always @(posedge axi_clk) begin + if (axi_fifo_reset_s == 1'b1) begin + axi_mem_waddr_m1 <= 'b0; + axi_mem_waddr_m2 <= 'b0; + axi_mem_waddr <= 'b0; + axi_xfer_pburst_offset <= 4'b1111; + end else begin + axi_mem_waddr_m1 <= dma_mem_waddr_g; + axi_mem_waddr_m2 <= axi_mem_waddr_m1; + axi_mem_waddr <= axi_mem_waddr_m2_g2b_s; + if ((axi_xfer_req_m[2] == 0) && (axi_xfer_pburst_offset > 0)) begin + axi_xfer_pburst_offset <= axi_xfer_pburst_offset - 4'b1; + end + end + end + + ad_g2b #( + .DATA_WIDTH(DMA_MEM_ADDRESS_WIDTH) + ) i_axi_mem_waddr_g2b ( + .din (axi_mem_waddr_m2), + .dout (axi_mem_waddr_m2_g2b_s)); + + // ASYNC MEM read control + + assign axi_mem_waddr_s = (MEM_RATIO == 1) ? axi_mem_waddr : + (MEM_RATIO == 2) ? ((AXI_BIGGER == 1) ? axi_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):1] : {axi_mem_waddr, 1'b0}) : + (MEM_RATIO == 4) ? ((AXI_BIGGER == 1) ? axi_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):2] : {axi_mem_waddr, 2'b0}) : + (MEM_RATIO == 8) ? ((AXI_BIGGER == 1) ? axi_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):3] : {axi_mem_waddr, 3'b0}) : + ((AXI_BIGGER == 1) ? axi_mem_waddr[(DMA_MEM_ADDRESS_WIDTH-1):4] : {axi_mem_waddr, 4'b0}); + assign axi_mem_addr_diff_s = {1'b1, axi_mem_waddr_s} - axi_mem_raddr; + + always @(posedge axi_clk) begin + if (axi_fifo_reset_s == 1'b1) begin + axi_mem_addr_diff <= 'b0; + axi_mem_read_en_d <= 1'b0; + end else begin + axi_mem_addr_diff <= axi_mem_addr_diff_s[(AXI_MEM_ADDRESS_WIDTH-1):0]; + axi_mem_read_en_d <= axi_mem_read_en_s; + end + end + + assign axi_wready_s = ~axi_wvalid | axi_wready; + assign axi_mem_rvalid_s = axi_mem_read_en_s & axi_wready_s; + assign axi_mem_last_s = (axi_wvalid_counter == axi_awlen) ? axi_mem_rvalid_s : 1'b0; + + always @(posedge axi_clk) begin + if (axi_fifo_reset_s == 1'b1) begin + axi_mem_rvalid <= 1'b0; + axi_mem_rvalid_d <= 1'b0; + axi_mem_last <= 1'b0; + axi_mem_last_d <= 1'b0; + axi_mem_rdata <= 'b0; + axi_mem_raddr <= 'b0; + axi_wvalid_counter <= 8'b0; + axi_mem_last_read_toggle <= 1'b0; + axi_mem_raddr_g <= 'b0; + end else begin + axi_mem_rvalid <= axi_mem_rvalid_s; + axi_mem_rvalid_d <= axi_mem_rvalid; + axi_mem_last <= axi_mem_last_s; + axi_mem_last_d <= axi_mem_last; + axi_mem_rdata <= axi_mem_rdata_s; + if (axi_mem_rvalid_s == 1'b1) begin + axi_mem_raddr <= axi_mem_raddr + 1; + axi_wvalid_counter <= (axi_wvalid_counter == axi_awlen) ? 0 : axi_wvalid_counter + 1; + end + if (axi_writer_state == XFER_END) begin + axi_mem_raddr <= 'b0; + axi_mem_last_read_toggle <= ~axi_mem_last_read_toggle; + end + axi_mem_raddr_g <= axi_mem_raddr_b2g_s; + end + end + + ad_b2g #( + .DATA_WIDTH(AXI_MEM_ADDRESS_WIDTH) + ) i_axi_mem_raddr_b2g ( + .din (axi_mem_raddr), + .dout (axi_mem_raddr_b2g_s)); + + // AXI Memory Map interface write address channel + + assign axi_awid = 4'b0000; + assign axi_awburst = 2'b01; // INCR (Incrementing address burst) + assign axi_awlock = 1'b0; // Normal access + assign axi_awcache = 4'b0010; // Cacheable, but not allocate + assign axi_awprot = 3'b000; // Normal, secure, data access + assign axi_awqos = 4'b0000; // Not used + assign axi_awlen = (axi_partial_burst_s == 1'b1) ? axi_last_burst_length : AXI_LENGTH; + assign axi_awsize = AXI_SIZE; + + assign axi_waddr_ready_s = axi_mem_read_en_s & ~axi_mem_read_en_d; + + always @(posedge axi_clk) begin + if (axi_fifo_reset_s == 1'b1) begin + axi_awvalid <= 'd0; + axi_awaddr <= AXI_ADDRESS; + axi_xfer_out <= 1'b0; + end else begin + if (axi_awvalid == 1'b1) begin + if (axi_awready == 1'b1) begin + axi_awvalid <= 1'b0; + end + end else begin + if (axi_waddr_ready_s == 1'b1) begin + axi_awvalid <= 1'b1; + end + end + if ((axi_awvalid == 1'b1) && (axi_awready == 1'b1)) begin + axi_awaddr <= (axi_writer_state == XFER_FULL_BURST) ? (axi_awaddr + AXI_AWINCR) : + (axi_writer_state == XFER_PARTIAL_BURST) ? (axi_awaddr + axi_last_burst_length * AXI_BYTE_WIDTH) : + (axi_awaddr + AXI_AWINCR); + end + if (axi_writer_state == XFER_END) begin + axi_xfer_out <= 1'b1; + end + end + end + + // write data channel controls + + assign axi_wstrb = {AXI_BYTE_WIDTH{1'b1}}; + + // response channel + + assign axi_bready = 1'b1; + + always @(posedge axi_clk) begin + if (axi_fifo_reset_s == 1'b1) begin + axi_werror <= 'd0; + end else begin + axi_werror <= axi_bvalid & axi_bresp[1]; + end + end + + // AXI last address and last burst length + + assign axi_dma_last_beats_active_s = (axi_dma_last_beats_m2 > 0) ? 1'b1 : 1'b0; + always @(posedge axi_clk) begin + if (axi_fifo_reset_s == 1'b1) begin + axi_dma_last_beats_m1 <= 0; + axi_dma_last_beats_m2 <= 0; + axi_last_burst_length <= AXI_LENGTH; + end else begin + axi_dma_last_beats_m1 <= dma_last_beats; + axi_dma_last_beats_m2 <= axi_dma_last_beats_m1; + axi_last_burst_length <= ((axi_partial_burst_s) && + (axi_waddr_ready_s) && + (axi_dma_last_beats_active_s)) ? axi_mem_addr_diff : + ((axi_partial_burst_s) && + (axi_waddr_ready_s) && + (~axi_dma_last_beats_active_s)) ? (axi_mem_addr_diff-1) : + axi_last_burst_length; + end + end + + always @(posedge axi_clk) begin + if(axi_fifo_reset_s == 1'b1) begin + axi_last_addr <= AXI_ADDRESS; + axi_last_beats <= 8'b0; + end else begin + if ((axi_awready == 1'b1) && (axi_awvalid == 1'b1)) begin + axi_last_addr <= axi_awaddr & (~AXI_AWINCR+1); + axi_last_beats <= axi_last_burst_length; + end + end + end + +endmodule diff --git a/adi_library/xilinx/axi_dacfifo/component.xml b/adi_library/xilinx/axi_dacfifo/component.xml new file mode 100644 index 00000000..7cf4fc06 --- /dev/null +++ b/adi_library/xilinx/axi_dacfifo/component.xml @@ -0,0 +1,1559 @@ + + + analog.com + user + axi_dacfifo + 1.0 + + + axi + + + + + + + + + AWID + + + axi_awid + + + + + AWADDR + + + axi_awaddr + + + + + AWLEN + + + axi_awlen + + + + + AWSIZE + + + axi_awsize + + + + + AWBURST + + + axi_awburst + + + + + AWLOCK + + + axi_awlock + + + + + AWCACHE + + + axi_awcache + + + + + AWPROT + + + axi_awprot + + + + + AWQOS + + + axi_awqos + + + + + AWVALID + + + axi_awvalid + + + + + AWREADY + + + axi_awready + + + + + WDATA + + + axi_wdata + + + + + WSTRB + + + axi_wstrb + + + + + WLAST + + + axi_wlast + + + + + WVALID + + + axi_wvalid + + + + + WREADY + + + axi_wready + + + + + BID + + + axi_bid + + + + + BRESP + + + axi_bresp + + + + + BVALID + + + axi_bvalid + + + + + BREADY + + + axi_bready + + + + + ARID + + + axi_arid + + + + + ARADDR + + + axi_araddr + + + + + ARLEN + + + axi_arlen + + + + + ARSIZE + + + axi_arsize + + + + + ARBURST + + + axi_arburst + + + + + ARLOCK + + + axi_arlock + + + + + ARCACHE + + + axi_arcache + + + + + ARPROT + + + axi_arprot + + + + + ARQOS + + + axi_arqos + + + + + ARVALID + + + axi_arvalid + + + + + ARREADY + + + axi_arready + + + + + RID + + + axi_rid + + + + + RDATA + + + axi_rdata + + + + + RRESP + + + axi_rresp + + + + + RLAST + + + axi_rlast + + + + + RVALID + + + axi_rvalid + + + + + RREADY + + + axi_rready + + + + + + axi_clk + + + + + + + CLK + + + axi_clk + + + + + + ASSOCIATED_BUSIF + axi + + + ASSOCIATED_RESET + axi_resetn + + + + + axi_resetn + + + + + + + RST + + + axi_resetn + + + + + + POLARITY + ACTIVE_LOW + + + + + dma_clk + + + + + + + CLK + + + dma_clk + + + + + + ASSOCIATED_RESET + dma_rst + + + + + dma_rst + + + + + + + RST + + + dma_rst + + + + + + dac_clk + + + + + + + CLK + + + dac_clk + + + + + + ASSOCIATED_RESET + dac_rst + + + + + dac_rst + + + + + + + RST + + + dac_rst + + + + + + + + axi + 4294967296 + 512 + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_dacfifo + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 36fedcbb + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_dacfifo + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 6f634deb + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + bde7c6b3 + + + + + + + dma_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_rst + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_data + + in + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + dma_ready + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_xfer_req + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dma_xfer_last + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_rst + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_valid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_data + + out + + 63 + 0 + + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_dunf + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + dac_xfer_out + + out + + + reg + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + bypass + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_resetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_awvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_awid + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_awburst + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_awlock + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_awcache + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_awprot + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_awqos + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_awlen + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_awsize + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_awaddr + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_awready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_wvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_wdata + + out + + 511 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_wstrb + + out + + 63 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_wlast + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_wready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_bvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_bid + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_bresp + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_bready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_arvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_arid + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_arburst + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_arlock + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_arcache + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_arprot + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_arqos + + out + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_arlen + + out + + 7 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_arsize + + out + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_araddr + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + axi_arready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_rvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_rid + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_rresp + + in + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_rlast + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_rdata + + in + + 511 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + axi_rready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + DAC_DATA_WIDTH + Dac Data Width + 64 + + + DMA_DATA_WIDTH + Dma Data Width + 64 + + + AXI_DATA_WIDTH + Axi Data Width + 512 + + + AXI_SIZE + Axi Size + 2 + + + AXI_LENGTH + Axi Length + 15 + + + AXI_ADDRESS + Axi Address + 0x00000000 + + + AXI_ADDRESS_LIMIT + Axi Address Limit + 0xFFFFFFFF + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + + + xilinx_anylanguagesynthesis_view_fileset + + axi_dacfifo_constr.xdc + xdc + + + ../../common/ad_axis_inf_rx.v + verilogSource + + + ../../common/ad_b2g.v + verilogSource + + + ../../common/ad_g2b.v + verilogSource + + + ../../common/ad_mem.v + verilogSource + + + ../../common/ad_mem_asym.v + verilogSource + + + axi_dacfifo_address_buffer.v + verilogSource + + + axi_dacfifo_rd.v + verilogSource + + + axi_dacfifo_wr.v + verilogSource + + + ../../util_dacfifo/util_dacfifo_bypass.v + verilogSource + + + axi_dacfifo.v + verilogSource + CHECKSUM_042d71fe + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../common/ad_axis_inf_rx.v + verilogSource + + + ../../common/ad_b2g.v + verilogSource + + + ../../common/ad_g2b.v + verilogSource + + + ../../common/ad_mem.v + verilogSource + + + ../../common/ad_mem_asym.v + verilogSource + + + axi_dacfifo_address_buffer.v + verilogSource + + + axi_dacfifo_rd.v + verilogSource + + + axi_dacfifo_wr.v + verilogSource + + + ../../util_dacfifo/util_dacfifo_bypass.v + verilogSource + + + axi_dacfifo.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/axi_dacfifo_v1_0.tcl + tclSource + CHECKSUM_bde7c6b3 + XGUI_VERSION_2 + + + + axi_dacfifo_v1_0 + + + DAC_DATA_WIDTH + Dac Data Width + 64 + + + DMA_DATA_WIDTH + Dma Data Width + 64 + + + AXI_DATA_WIDTH + Axi Data Width + 512 + + + AXI_SIZE + Axi Size + 2 + + + AXI_LENGTH + Axi Length + 15 + + + AXI_ADDRESS + Axi Address + 0x00000000 + + + AXI_ADDRESS_LIMIT + Axi Address Limit + 0xFFFFFFFF + + + Component_Name + axi_dacfifo_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_dacfifo_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:57:40Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/xilinx/axi_dacfifo/xgui/axi_dacfifo_v1_0.tcl b/adi_library/xilinx/axi_dacfifo/xgui/axi_dacfifo_v1_0.tcl new file mode 100644 index 00000000..751d4694 --- /dev/null +++ b/adi_library/xilinx/axi_dacfifo/xgui/axi_dacfifo_v1_0.tcl @@ -0,0 +1,115 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "AXI_ADDRESS" -parent ${Page_0} + ipgui::add_param $IPINST -name "AXI_ADDRESS_LIMIT" -parent ${Page_0} + ipgui::add_param $IPINST -name "AXI_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "AXI_LENGTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "AXI_SIZE" -parent ${Page_0} + ipgui::add_param $IPINST -name "DAC_DATA_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "DMA_DATA_WIDTH" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.AXI_ADDRESS { PARAM_VALUE.AXI_ADDRESS } { + # Procedure called to update AXI_ADDRESS when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_ADDRESS { PARAM_VALUE.AXI_ADDRESS } { + # Procedure called to validate AXI_ADDRESS + return true +} + +proc update_PARAM_VALUE.AXI_ADDRESS_LIMIT { PARAM_VALUE.AXI_ADDRESS_LIMIT } { + # Procedure called to update AXI_ADDRESS_LIMIT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_ADDRESS_LIMIT { PARAM_VALUE.AXI_ADDRESS_LIMIT } { + # Procedure called to validate AXI_ADDRESS_LIMIT + return true +} + +proc update_PARAM_VALUE.AXI_DATA_WIDTH { PARAM_VALUE.AXI_DATA_WIDTH } { + # Procedure called to update AXI_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_DATA_WIDTH { PARAM_VALUE.AXI_DATA_WIDTH } { + # Procedure called to validate AXI_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.AXI_LENGTH { PARAM_VALUE.AXI_LENGTH } { + # Procedure called to update AXI_LENGTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_LENGTH { PARAM_VALUE.AXI_LENGTH } { + # Procedure called to validate AXI_LENGTH + return true +} + +proc update_PARAM_VALUE.AXI_SIZE { PARAM_VALUE.AXI_SIZE } { + # Procedure called to update AXI_SIZE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.AXI_SIZE { PARAM_VALUE.AXI_SIZE } { + # Procedure called to validate AXI_SIZE + return true +} + +proc update_PARAM_VALUE.DAC_DATA_WIDTH { PARAM_VALUE.DAC_DATA_WIDTH } { + # Procedure called to update DAC_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DAC_DATA_WIDTH { PARAM_VALUE.DAC_DATA_WIDTH } { + # Procedure called to validate DAC_DATA_WIDTH + return true +} + +proc update_PARAM_VALUE.DMA_DATA_WIDTH { PARAM_VALUE.DMA_DATA_WIDTH } { + # Procedure called to update DMA_DATA_WIDTH when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.DMA_DATA_WIDTH { PARAM_VALUE.DMA_DATA_WIDTH } { + # Procedure called to validate DMA_DATA_WIDTH + return true +} + + +proc update_MODELPARAM_VALUE.DAC_DATA_WIDTH { MODELPARAM_VALUE.DAC_DATA_WIDTH PARAM_VALUE.DAC_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DAC_DATA_WIDTH}] ${MODELPARAM_VALUE.DAC_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.DMA_DATA_WIDTH { MODELPARAM_VALUE.DMA_DATA_WIDTH PARAM_VALUE.DMA_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DMA_DATA_WIDTH}] ${MODELPARAM_VALUE.DMA_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.AXI_DATA_WIDTH { MODELPARAM_VALUE.AXI_DATA_WIDTH PARAM_VALUE.AXI_DATA_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.AXI_DATA_WIDTH} +} + +proc update_MODELPARAM_VALUE.AXI_SIZE { MODELPARAM_VALUE.AXI_SIZE PARAM_VALUE.AXI_SIZE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_SIZE}] ${MODELPARAM_VALUE.AXI_SIZE} +} + +proc update_MODELPARAM_VALUE.AXI_LENGTH { MODELPARAM_VALUE.AXI_LENGTH PARAM_VALUE.AXI_LENGTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_LENGTH}] ${MODELPARAM_VALUE.AXI_LENGTH} +} + +proc update_MODELPARAM_VALUE.AXI_ADDRESS { MODELPARAM_VALUE.AXI_ADDRESS PARAM_VALUE.AXI_ADDRESS } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_ADDRESS}] ${MODELPARAM_VALUE.AXI_ADDRESS} +} + +proc update_MODELPARAM_VALUE.AXI_ADDRESS_LIMIT { MODELPARAM_VALUE.AXI_ADDRESS_LIMIT PARAM_VALUE.AXI_ADDRESS_LIMIT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.AXI_ADDRESS_LIMIT}] ${MODELPARAM_VALUE.AXI_ADDRESS_LIMIT} +} + diff --git a/adi_library/xilinx/axi_xcvrlb/Makefile b/adi_library/xilinx/axi_xcvrlb/Makefile new file mode 100644 index 00000000..3535157b --- /dev/null +++ b/adi_library/xilinx/axi_xcvrlb/Makefile @@ -0,0 +1,20 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := axi_xcvrlb + +XILINX_DEPS += ../../common/ad_pnmon.v +XILINX_DEPS += ../../common/up_axi.v +XILINX_DEPS += ../../common/up_xfer_status.v +XILINX_DEPS += ../../xilinx/util_adxcvr/util_adxcvr_xch.v +XILINX_DEPS += axi_xcvrlb.v +XILINX_DEPS += axi_xcvrlb_1.v +XILINX_DEPS += axi_xcvrlb_constr.xdc +XILINX_DEPS += axi_xcvrlb_ip.tcl + +XILINX_LIB_DEPS += util_cdc + +include ../../scripts/library.mk diff --git a/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v b/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v new file mode 100644 index 00000000..befefe16 --- /dev/null +++ b/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.v @@ -0,0 +1,219 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module axi_xcvrlb #( + + // parameters + + parameter integer CPLL_FBDIV = 1, + parameter integer CPLL_FBDIV_4_5 = 5, + parameter NUM_OF_LANES = 1, + parameter integer XCVR_TYPE = 2 +) ( + + // transceiver interface + + input ref_clk, + input [(NUM_OF_LANES-1):0] rx_p, + input [(NUM_OF_LANES-1):0] rx_n, + output [(NUM_OF_LANES-1):0] tx_p, + output [(NUM_OF_LANES-1):0] tx_n, + + // axi interface + + input s_axi_aclk, + input s_axi_aresetn, + input s_axi_awvalid, + input [15:0] s_axi_awaddr, + input [ 2:0] s_axi_awprot, + output s_axi_awready, + input s_axi_wvalid, + input [31:0] s_axi_wdata, + input [ 3:0] s_axi_wstrb, + output s_axi_wready, + output s_axi_bvalid, + output [ 1:0] s_axi_bresp, + input s_axi_bready, + input s_axi_arvalid, + input [15:0] s_axi_araddr, + input [ 2:0] s_axi_arprot, + output s_axi_arready, + output s_axi_rvalid, + output [ 1:0] s_axi_rresp, + output [31:0] s_axi_rdata, + input s_axi_rready +); + + // internal registers + + reg up_wack = 'd0; + reg [31:0] up_scratch = 'd0; + reg up_resetn = 'd0; + reg [31:0] up_status = 'd0; + reg [31:0] up_pll_locked = 'd0; + reg up_rack = 'd0; + reg [31:0] up_rdata = 'd0; + + // internal signals + + wire up_rstn; + wire up_clk; + wire up_wreq_s; + wire [ 7:0] up_waddr_s; + wire [31:0] up_wdata_s; + wire up_rreq_s; + wire [ 7:0] up_raddr_s; + wire [31:0] up_status_s; + wire [31:0] up_pll_locked_s; + + // parameters + + localparam [31:0] VERSION = 32'h00100161; + + // defaults + + assign up_rstn = s_axi_aresetn; + assign up_clk = s_axi_aclk; + assign up_status_s[31:NUM_OF_LANES] = 'd0; + assign up_pll_locked_s[31:NUM_OF_LANES] = 'd0; + + // register access + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_wack <= 'd0; + up_scratch <= 'd0; + up_resetn <= 'd0; + up_status <= 'd0; + up_pll_locked <= 'd0; + end else begin + up_wack <= up_wreq_s; + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h02)) begin + up_scratch <= up_wdata_s; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h04)) begin + up_resetn <= up_wdata_s[0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h05)) begin + up_status <= up_status_s | (up_status & ~up_wdata_s); + end else begin + up_status <= up_status_s | up_status; + end + if ((up_wreq_s == 1'b1) && (up_waddr_s == 8'h06)) begin + up_pll_locked <= up_pll_locked_s | (up_pll_locked & ~up_wdata_s); + end else begin + up_pll_locked <= up_pll_locked_s | up_pll_locked; + end + end + end + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_rack <= 'd0; + up_rdata <= 'd0; + end else begin + up_rack <= up_rreq_s; + if (up_rreq_s == 1'b1) begin + case (up_raddr_s) + 10'h000: up_rdata <= VERSION; + 10'h002: up_rdata <= up_scratch; + 10'h004: up_rdata <= {31'd0, up_resetn}; + 10'h005: up_rdata <= up_status; + 10'h006: up_rdata <= up_pll_locked; + default: up_rdata <= 32'd0; + endcase + end else begin + up_rdata <= 32'd0; + end + end + end + + // instantiations + + genvar n; + generate + for (n = 0; n < NUM_OF_LANES; n = n + 1) begin: g_lanes + axi_xcvrlb_1 #( + .XCVR_TYPE (XCVR_TYPE), + .CPLL_FBDIV_4_5(CPLL_FBDIV_4_5), + .CPLL_FBDIV(CPLL_FBDIV) + ) i_xcvrlb_1 ( + .ref_clk (ref_clk), + .rx_p (rx_p[n]), + .rx_n (rx_n[n]), + .tx_p (tx_p[n]), + .tx_n (tx_n[n]), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_resetn (up_resetn), + .up_status (up_status_s[n]), + .up_pll_locked (up_pll_locked_s[n])); + end + endgenerate + + up_axi #( + .AXI_ADDRESS_WIDTH (10) + ) i_axi ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_axi_awvalid (s_axi_awvalid), + .up_axi_awaddr (s_axi_awaddr), + .up_axi_awready (s_axi_awready), + .up_axi_wvalid (s_axi_wvalid), + .up_axi_wdata (s_axi_wdata), + .up_axi_wstrb (s_axi_wstrb), + .up_axi_wready (s_axi_wready), + .up_axi_bvalid (s_axi_bvalid), + .up_axi_bresp (s_axi_bresp), + .up_axi_bready (s_axi_bready), + .up_axi_arvalid (s_axi_arvalid), + .up_axi_araddr (s_axi_araddr), + .up_axi_arready (s_axi_arready), + .up_axi_rvalid (s_axi_rvalid), + .up_axi_rresp (s_axi_rresp), + .up_axi_rdata (s_axi_rdata), + .up_axi_rready (s_axi_rready), + .up_wreq (up_wreq_s), + .up_waddr (up_waddr_s), + .up_wdata (up_wdata_s), + .up_wack (up_wack), + .up_rreq (up_rreq_s), + .up_raddr (up_raddr_s), + .up_rdata (up_rdata), + .up_rack (up_rack)); + +endmodule diff --git a/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr b/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr new file mode 100644 index 00000000..6756fd62 --- /dev/null +++ b/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb.xpr @@ -0,0 +1,447 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v b/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v new file mode 100644 index 00000000..e23dd973 --- /dev/null +++ b/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_1.v @@ -0,0 +1,326 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module axi_xcvrlb_1 #( + + // parameters + + parameter CPLL_FBDIV = 1, + parameter CPLL_FBDIV_4_5 = 5, + parameter XCVR_TYPE = 2 +) ( + + // transceiver interface + + input ref_clk, + input rx_p, + input rx_n, + output tx_p, + output tx_n, + + // processor interface + + input up_rstn, + input up_clk, + input up_resetn, + output up_status, + output up_pll_locked +); + + // internal registers + + reg [ 3:0] rx_kcount = 'd0; + reg rx_calign = 'd0; + reg [31:0] rx_data = 'd0; + reg [31:0] rx_pn_data = 'd0; + reg tx_charisk = 'd0; + reg [31:0] tx_data = 'd0; + reg [31:0] tx_pn_data = 'd0; + reg [ 3:0] up_pll_rst_cnt = 'd0; + reg [ 3:0] up_rst_cnt = 'd0; + reg [ 6:0] up_user_ready_cnt = 'd0; + reg up_status_int = 'd1; + + // internal signals + + wire clk; + wire rx_status_s; + wire [31:0] rx_pn_data_s; + wire rx_pn_oos_s; + wire rx_pn_err_s; + wire [ 3:0] rx_charisk_s; + wire [ 7:0] rx_error_s; + wire [31:0] rx_data_s; + wire up_pll_rst_s; + wire up_rst_s; + wire up_user_ready_s; + wire up_pll_locked_s; + wire up_rst_done_s; + wire up_pn_oos_s; + wire up_pn_err_s; + wire up_rx_pll_locked_s; + wire up_rx_rst_done_s; + wire up_tx_pll_locked_s; + wire up_tx_rst_done_s; + + // pn31 function + + function [31:0] pn31; + input [31:0] din; + reg [31:0] dout; + begin + dout[31] = din[31] ^ din[28]; + dout[30] = din[30] ^ din[27]; + dout[29] = din[29] ^ din[26]; + dout[28] = din[28] ^ din[25]; + dout[27] = din[27] ^ din[24]; + dout[26] = din[26] ^ din[23]; + dout[25] = din[25] ^ din[22]; + dout[24] = din[24] ^ din[21]; + dout[23] = din[23] ^ din[20]; + dout[22] = din[22] ^ din[19]; + dout[21] = din[21] ^ din[18]; + dout[20] = din[20] ^ din[17]; + dout[19] = din[19] ^ din[16]; + dout[18] = din[18] ^ din[15]; + dout[17] = din[17] ^ din[14]; + dout[16] = din[16] ^ din[13]; + dout[15] = din[15] ^ din[12]; + dout[14] = din[14] ^ din[11]; + dout[13] = din[13] ^ din[10]; + dout[12] = din[12] ^ din[ 9]; + dout[11] = din[11] ^ din[ 8]; + dout[10] = din[10] ^ din[ 7]; + dout[ 9] = din[ 9] ^ din[ 6]; + dout[ 8] = din[ 8] ^ din[ 5]; + dout[ 7] = din[ 7] ^ din[ 4]; + dout[ 6] = din[ 6] ^ din[ 3]; + dout[ 5] = din[ 5] ^ din[ 2]; + dout[ 4] = din[ 4] ^ din[ 1]; + dout[ 3] = din[ 3] ^ din[ 0]; + dout[ 2] = din[ 2] ^ din[31] ^ din[28]; + dout[ 1] = din[ 1] ^ din[30] ^ din[27]; + dout[ 0] = din[ 0] ^ din[29] ^ din[26]; + pn31 = dout; + end + endfunction + + // receive + + assign rx_status_s = ~(| rx_error_s); + assign rx_pn_data_s = (rx_pn_oos_s == 1'b1) ? rx_data : rx_pn_data; + + always @(posedge clk) begin + if (rx_status_s == 1'b0) begin + rx_kcount <= 4'd0; + rx_calign <= 1'd1; + end else if ((rx_charisk_s == 4'hf) && (rx_data_s == {4{8'hbc}})) begin + rx_kcount <= rx_kcount + 1'b1; + if (rx_kcount == 4'hf) begin + rx_calign <= 1'd0; + end + end + end + + always @(posedge clk) begin + if (rx_status_s == 1'b1) begin + rx_data[31:24] = rx_data_s[ 7: 0]; + rx_data[23:16] = rx_data_s[15: 8]; + rx_data[15: 8] = rx_data_s[23:16]; + rx_data[ 7: 0] = rx_data_s[31:24]; + end else begin + rx_data[31:24] = 8'hff; + rx_data[23:16] = 8'hff; + rx_data[15: 8] = 8'hff; + rx_data[ 7: 0] = 8'hff; + end + rx_pn_data <= pn31(rx_pn_data_s); + end + + // transmit + + always @(posedge clk) begin + if (rx_calign == 1'b0) begin + tx_charisk <= 1'd0; + tx_data[31:24] <= tx_pn_data[ 7: 0]; + tx_data[23:16] <= tx_pn_data[15: 8]; + tx_data[15: 8] <= tx_pn_data[23:16]; + tx_data[ 7: 0] <= tx_pn_data[31:24]; + tx_pn_data <= pn31(tx_pn_data); + end else begin + tx_charisk <= 1'd1; + tx_data[31:24] <= 8'hbc; + tx_data[23:16] <= 8'hbc; + tx_data[15: 8] <= 8'hbc; + tx_data[ 7: 0] <= 8'hbc; + tx_pn_data <= {32{1'b1}}; + end + end + + // reset & init + + assign up_status = up_status_int; + assign up_pll_rst_s = up_pll_rst_cnt[3]; + assign up_rst_s = up_rst_cnt[3]; + assign up_user_ready_s = up_user_ready_cnt[6]; + assign up_pll_locked_s = up_rx_pll_locked_s & up_tx_pll_locked_s; + assign up_pll_locked = up_pll_locked_s; + assign up_rst_done_s = up_rx_rst_done_s & up_tx_rst_done_s; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 0) begin + up_pll_rst_cnt <= 4'h8; + up_rst_cnt <= 4'h8; + up_user_ready_cnt <= 7'h00; + up_status_int <= 1'b1; + end else begin + if (up_resetn == 1'b0) begin + up_pll_rst_cnt <= 4'h8; + end else if (up_pll_rst_cnt[3] == 1'b1) begin + up_pll_rst_cnt <= up_pll_rst_cnt + 1'b1; + end + if ((up_resetn == 1'b0) || (up_pll_rst_cnt[3] == 1'b1) || + (up_pll_locked_s == 1'b0)) begin + up_rst_cnt <= 4'h8; + end else if (up_rst_cnt[3] == 1'b1) begin + up_rst_cnt <= up_rst_cnt + 1'b1; + end + if ((up_resetn == 1'b0) || (up_rst_cnt[3] == 1'b1)) begin + up_user_ready_cnt <= 7'h00; + end else if (up_user_ready_cnt[6] == 1'b0) begin + up_user_ready_cnt <= up_user_ready_cnt + 1'b1; + end + if ((up_resetn == 1'b0) || (up_rst_done_s == 1'b0)) begin + up_status_int <= 1'b1; + end else begin + up_status_int <= up_pn_oos_s | up_pn_err_s; + end + end + end + + // instantiations + + ad_pnmon #( + .DATA_WIDTH(32) + ) i_pnmon ( + .adc_clk (clk), + .adc_valid_in (1'b1), + .adc_data_in (rx_data), + .adc_data_pn (rx_pn_data), + .adc_pn_oos (rx_pn_oos_s), + .adc_pn_err (rx_pn_err_s)); + + up_xfer_status #( + .DATA_WIDTH(2) + ) i_xfer_status ( + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_data_status ({up_pn_err_s, up_pn_oos_s}), + .d_rst (1'b0), + .d_clk (clk), + .d_data_status ({rx_pn_err_s, rx_pn_oos_s})); + + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .TX_OUT_DIV (1), + .TX_CLK25_DIV (10), + .RX_OUT_DIV (1), + .RX_CLK25_DIV (10), + .RX_DFE_LPM_CFG (16'h0904), + .RX_PMA_CFG ('h00018480), + .RX_CDR_CFG ('h03000023ff10200020) + ) i_xch ( + .qpll2ch_clk (1'b0), + .qpll2ch_ref_clk (1'b0), + .qpll2ch_locked (1'b1), + .cpll_ref_clk (ref_clk), + .up_cpll_rst (up_pll_rst_s), + .rx_p (rx_p), + .rx_n (rx_n), + .rx_out_clk (clk), + .rx_clk (clk), + .rx_charisk (rx_charisk_s), + .rx_disperr (rx_error_s[3:0]), + .rx_notintable (rx_error_s[7:4]), + .rx_data (rx_data_s), + .rx_calign (rx_calign), + .tx_p (tx_p), + .tx_n (tx_n), + .tx_out_clk (), + .tx_clk (clk), + .tx_charisk ({4{tx_charisk}}), + .tx_data (tx_data), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (1'd0), + .up_es_addr (12'd0), + .up_es_wr (1'd0), + .up_es_wdata (16'd0), + .up_es_rdata (), + .up_es_ready (), + .up_rx_pll_locked (up_rx_pll_locked_s), + .up_rx_rst (up_rst_s), + .up_rx_user_ready (up_user_ready_s), + .up_rx_rst_done (up_rx_rst_done_s), + .up_rx_lpm_dfe_n (1'd0), + .up_rx_rate (3'd0), + .up_rx_sys_clk_sel (2'd0), + .up_rx_out_clk_sel (3'd2), + .up_rx_enb (1'd0), + .up_rx_addr (12'd0), + .up_rx_wr (1'd0), + .up_rx_wdata (16'd0), + .up_rx_rdata (), + .up_rx_ready (), + .up_tx_pll_locked (up_tx_pll_locked_s), + .up_tx_rst (up_rst_s), + .up_tx_user_ready (up_user_ready_s), + .up_tx_rst_done (up_tx_rst_done_s), + .up_tx_lpm_dfe_n (1'd0), + .up_tx_rate (3'd0), + .up_tx_sys_clk_sel (2'd0), + .up_tx_out_clk_sel (3'd2), + .up_tx_enb (1'd0), + .up_tx_addr (12'd0), + .up_tx_wr (1'd0), + .up_tx_wdata (16'd0), + .up_tx_rdata (), + .up_tx_ready ()); + +endmodule diff --git a/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_constr.xdc b/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_constr.xdc new file mode 100644 index 00000000..c92bc2c7 --- /dev/null +++ b/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_constr.xdc @@ -0,0 +1,16 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_state*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_rx_rst_done*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_tx_rst_done*}] + +set_false_path -to [get_cells -hier -filter {name =~ *up_rx_rst_done_m1_reg && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *up_tx_rst_done_m1_reg && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *d_xfer_state_m1_reg && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *up_xfer_toggle_m1_reg && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *up_data_status* && IS_SEQUENTIAL}] + diff --git a/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.tcl b/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.tcl new file mode 100644 index 00000000..a2c60747 --- /dev/null +++ b/adi_library/xilinx/axi_xcvrlb/axi_xcvrlb_ip.tcl @@ -0,0 +1,73 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create axi_xcvrlb +adi_ip_files axi_xcvrlb [list \ + "$ad_hdl_dir/library/xilinx/util_adxcvr/util_adxcvr_xch.v" \ + "$ad_hdl_dir/library/common/up_xfer_status.v" \ + "$ad_hdl_dir/library/common/ad_pnmon.v" \ + "$ad_hdl_dir/library/common/up_axi.v" \ + "axi_xcvrlb_constr.xdc" \ + "axi_xcvrlb_1.v" \ + "axi_xcvrlb.v" ] + +adi_ip_properties_lite axi_xcvrlb + +adi_init_bd_tcl +adi_ip_bd axi_xcvrlb "bd/bd.tcl" + +adi_ip_add_core_dependencies [list \ + analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \ +] + +ipx::remove_all_bus_interface [ipx::current_core] + +set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]] + +ipx::infer_bus_interface {\ + s_axi_awvalid \ + s_axi_awaddr \ + s_axi_awprot \ + s_axi_awready \ + s_axi_wvalid \ + s_axi_wdata \ + s_axi_wstrb \ + s_axi_wready \ + s_axi_bvalid \ + s_axi_bresp \ + s_axi_bready \ + s_axi_arvalid \ + s_axi_araddr \ + s_axi_arprot \ + s_axi_arready \ + s_axi_rvalid \ + s_axi_rdata \ + s_axi_rresp \ + s_axi_rready} \ +xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core] + +ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +ipx::add_bus_parameter ASSOCIATED_BUSIF [ipx::get_bus_interfaces s_axi_aclk \ + -of_objects [ipx::current_core]] +set_property value s_axi [ipx::get_bus_parameters ASSOCIATED_BUSIF \ + -of_objects [ipx::get_bus_interfaces s_axi_aclk \ + -of_objects [ipx::current_core]]] + +ipx::add_memory_map {s_axi} [ipx::current_core] +set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]] +ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]] +set_property range {1024} [ipx::get_address_blocks axi_lite \ + -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]] + +adi_add_auto_fpga_spec_params + +ipx::save_core [ipx::current_core] diff --git a/adi_library/xilinx/axi_xcvrlb/bd/bd.tcl b/adi_library/xilinx/axi_xcvrlb/bd/bd.tcl new file mode 100644 index 00000000..1a878a37 --- /dev/null +++ b/adi_library/xilinx/axi_xcvrlb/bd/bd.tcl @@ -0,0 +1,44 @@ +# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY! +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_override $ip " \ + XCVR_TYPE" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/xilinx/axi_xcvrlb/component.xml b/adi_library/xilinx/axi_xcvrlb/component.xml new file mode 100644 index 00000000..7d8996a4 --- /dev/null +++ b/adi_library/xilinx/axi_xcvrlb/component.xml @@ -0,0 +1,971 @@ + + + analog.com + user + axi_xcvrlb + 1.0 + + + s_axi + + + + + + + + + AWADDR + + + s_axi_awaddr + + + + + AWPROT + + + s_axi_awprot + + + + + AWVALID + + + s_axi_awvalid + + + + + AWREADY + + + s_axi_awready + + + + + WDATA + + + s_axi_wdata + + + + + WSTRB + + + s_axi_wstrb + + + + + WVALID + + + s_axi_wvalid + + + + + WREADY + + + s_axi_wready + + + + + BRESP + + + s_axi_bresp + + + + + BVALID + + + s_axi_bvalid + + + + + BREADY + + + s_axi_bready + + + + + ARADDR + + + s_axi_araddr + + + + + ARPROT + + + s_axi_arprot + + + + + ARVALID + + + s_axi_arvalid + + + + + ARREADY + + + s_axi_arready + + + + + RDATA + + + s_axi_rdata + + + + + RRESP + + + s_axi_rresp + + + + + RVALID + + + s_axi_rvalid + + + + + RREADY + + + s_axi_rready + + + + + + s_axi_aclk + + + + + + + CLK + + + s_axi_aclk + + + + + + ASSOCIATED_BUSIF + s_axi + + + ASSOCIATED_RESET + s_axi_aresetn + + + + + s_axi_aresetn + + + + + + + RST + + + s_axi_aresetn + + + + + + POLARITY + ACTIVE_LOW + + + + + + + s_axi + + axi_lite + 0 + 1024 + 0 + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + axi_xcvrlb + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + 05fbea40 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + axi_xcvrlb + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + 61f424a5 + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_xpgui_view_fileset + + + + viewChecksum + b1ece077 + + + + + xilinx_blockdiagram + Block Diagram + :vivado.xilinx.com:block.diagram + + xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset + + + xilinx_blockdiagram_view_fileset + + + + + + ref_clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + rx_p + + in + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + rx_n + + in + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + tx_p + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + tx_n + + out + + 0 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_aclk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_aresetn + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awaddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_awready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_wvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wdata + + in + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wstrb + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_wready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_bready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arvalid + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_araddr + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arprot + + in + + 2 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + s_axi_arready + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rvalid + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rresp + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rdata + + out + + 31 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + s_axi_rready + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + + CPLL_FBDIV + Cpll Fbdiv + 1 + + + CPLL_FBDIV_4_5 + Cpll Fbdiv 4 5 + 5 + + + NUM_OF_LANES + Num Of Lanes + 1 + + + XCVR_TYPE + Xcvr Type + 2 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_07421b06 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + + + + + xilinx_anylanguagesynthesis_view_fileset + + axi_xcvrlb_constr.xdc + xdc + + + ../../common/ad_pnmon.v + verilogSource + + + axi_xcvrlb_1.v + verilogSource + + + ../../common/up_axi.v + verilogSource + + + ../../common/up_xfer_status.v + verilogSource + + + ../util_adxcvr/util_adxcvr_xch.v + verilogSource + + + axi_xcvrlb.v + verilogSource + CHECKSUM_4e7e40b2 + + + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../common/ad_pnmon.v + verilogSource + + + axi_xcvrlb_1.v + verilogSource + + + ../../common/up_axi.v + verilogSource + + + ../../common/up_xfer_status.v + verilogSource + + + ../util_adxcvr/util_adxcvr_xch.v + verilogSource + + + axi_xcvrlb.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/axi_xcvrlb_v1_0.tcl + tclSource + CHECKSUM_b1ece077 + XGUI_VERSION_2 + + + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + axi_xcvrlb_v1_0 + + + CPLL_FBDIV + Cpll Fbdiv + 1 + + + CPLL_FBDIV_4_5 + Cpll Fbdiv 4 5 + 5 + + + NUM_OF_LANES + Num Of Lanes + 1 + + + XCVR_TYPE + Xcvr Type + 2 + + + Component_Name + axi_xcvrlb_v1_0 + + + + + + virtex7 + qvirtex7 + versal + kintex7 + kintex7l + qkintex7 + qkintex7l + akintex7 + artix7 + artix7l + aartix7 + qartix7 + zynq + qzynq + azynq + spartan7 + aspartan7 + virtexu + zynquplus + virtexuplus + virtexuplusHBM + virtexuplus58g + kintexuplus + artixuplus + kintexu + + + /Analog_Devices + + axi_xcvrlb_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:57:51Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/xilinx/axi_xcvrlb/temporary_case_dependencies.mk b/adi_library/xilinx/axi_xcvrlb/temporary_case_dependencies.mk new file mode 100644 index 00000000..a7c71eb3 --- /dev/null +++ b/adi_library/xilinx/axi_xcvrlb/temporary_case_dependencies.mk @@ -0,0 +1,2 @@ +CLEAN_TARGET += bd +CLEAN_TARGET += temporary_case_dependencies.mk diff --git a/adi_library/xilinx/axi_xcvrlb/xgui/axi_xcvrlb_v1_0.tcl b/adi_library/xilinx/axi_xcvrlb/xgui/axi_xcvrlb_v1_0.tcl new file mode 100644 index 00000000..0e44571f --- /dev/null +++ b/adi_library/xilinx/axi_xcvrlb/xgui/axi_xcvrlb_v1_0.tcl @@ -0,0 +1,70 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "CPLL_FBDIV" -parent ${Page_0} + ipgui::add_param $IPINST -name "CPLL_FBDIV_4_5" -parent ${Page_0} + ipgui::add_param $IPINST -name "NUM_OF_LANES" -parent ${Page_0} + ipgui::add_param $IPINST -name "XCVR_TYPE" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.CPLL_FBDIV { PARAM_VALUE.CPLL_FBDIV } { + # Procedure called to update CPLL_FBDIV when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CPLL_FBDIV { PARAM_VALUE.CPLL_FBDIV } { + # Procedure called to validate CPLL_FBDIV + return true +} + +proc update_PARAM_VALUE.CPLL_FBDIV_4_5 { PARAM_VALUE.CPLL_FBDIV_4_5 } { + # Procedure called to update CPLL_FBDIV_4_5 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CPLL_FBDIV_4_5 { PARAM_VALUE.CPLL_FBDIV_4_5 } { + # Procedure called to validate CPLL_FBDIV_4_5 + return true +} + +proc update_PARAM_VALUE.NUM_OF_LANES { PARAM_VALUE.NUM_OF_LANES } { + # Procedure called to update NUM_OF_LANES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.NUM_OF_LANES { PARAM_VALUE.NUM_OF_LANES } { + # Procedure called to validate NUM_OF_LANES + return true +} + +proc update_PARAM_VALUE.XCVR_TYPE { PARAM_VALUE.XCVR_TYPE } { + # Procedure called to update XCVR_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.XCVR_TYPE { PARAM_VALUE.XCVR_TYPE } { + # Procedure called to validate XCVR_TYPE + return true +} + + +proc update_MODELPARAM_VALUE.CPLL_FBDIV { MODELPARAM_VALUE.CPLL_FBDIV PARAM_VALUE.CPLL_FBDIV } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CPLL_FBDIV}] ${MODELPARAM_VALUE.CPLL_FBDIV} +} + +proc update_MODELPARAM_VALUE.CPLL_FBDIV_4_5 { MODELPARAM_VALUE.CPLL_FBDIV_4_5 PARAM_VALUE.CPLL_FBDIV_4_5 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CPLL_FBDIV_4_5}] ${MODELPARAM_VALUE.CPLL_FBDIV_4_5} +} + +proc update_MODELPARAM_VALUE.NUM_OF_LANES { MODELPARAM_VALUE.NUM_OF_LANES PARAM_VALUE.NUM_OF_LANES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.NUM_OF_LANES}] ${MODELPARAM_VALUE.NUM_OF_LANES} +} + +proc update_MODELPARAM_VALUE.XCVR_TYPE { MODELPARAM_VALUE.XCVR_TYPE PARAM_VALUE.XCVR_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.XCVR_TYPE}] ${MODELPARAM_VALUE.XCVR_TYPE} +} + diff --git a/adi_library/xilinx/common/ad_data_clk.v b/adi_library/xilinx/common/ad_data_clk.v new file mode 100644 index 00000000..08ac184d --- /dev/null +++ b/adi_library/xilinx/common/ad_data_clk.v @@ -0,0 +1,77 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_data_clk #( + + parameter SINGLE_ENDED = 0 +) ( + input rst, + output locked, + + input clk_in_p, + input clk_in_n, + output clk +); + + // internal signals + + wire clk_ibuf_s; + + // defaults + + assign locked = 1'b1; + + // instantiations + + generate + if (SINGLE_ENDED == 1) begin + IBUFG i_rx_clk_ibuf ( + .I (clk_in_p), + .O (clk_ibuf_s)); + end else begin + IBUFGDS i_rx_clk_ibuf ( + .I (clk_in_p), + .IB (clk_in_n), + .O (clk_ibuf_s)); + end + endgenerate + + BUFG i_clk_gbuf ( + .I (clk_ibuf_s), + .O (clk)); + +endmodule diff --git a/adi_library/xilinx/common/ad_data_in.v b/adi_library/xilinx/common/ad_data_in.v new file mode 100755 index 00000000..c1dcd1b2 --- /dev/null +++ b/adi_library/xilinx/common/ad_data_in.v @@ -0,0 +1,284 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_data_in #( + parameter SINGLE_ENDED = 0, + parameter FPGA_TECHNOLOGY = 0, + parameter DDR_SDR_N = 1, + parameter IDDR_CLK_EDGE ="SAME_EDGE", + // for 7 series devices + parameter IDELAY_TYPE = "VAR_LOAD", + // for ultrascale devices + parameter DELAY_FORMAT = "COUNT", + parameter US_DELAY_TYPE = "VAR_LOAD", + // for all + parameter IODELAY_ENABLE = 1, + parameter IODELAY_CTRL = 0, + parameter IODELAY_GROUP = "dev_if_delay_group", + parameter REFCLK_FREQUENCY = 200 +) ( + + // data interface + + input rx_clk, + input rx_data_in_p, + input rx_data_in_n, + output rx_data_p, + output rx_data_n, + + // delay-data interface + + input up_clk, + input up_dld, + input [ 4:0] up_dwdata, + output [ 4:0] up_drdata, + + // delay-cntrl interface + + input delay_clk, + input delay_rst, + output delay_locked +); + + // internal parameters + + localparam NONE = -1; + localparam SEVEN_SERIES = 1; + localparam ULTRASCALE = 2; + localparam ULTRASCALE_PLUS = 3; + + // do not instantiate an IDELAYCTRL if no IDELAY is instantiated + localparam IODELAY_CTRL_ENABLED = (IODELAY_ENABLE & IODELAY_CTRL); + localparam IODELAY_CTRL_SIM_DEVICE = (FPGA_TECHNOLOGY == ULTRASCALE_PLUS) ? "ULTRASCALE" : + (FPGA_TECHNOLOGY == ULTRASCALE) ? "ULTRASCALE" : "7SERIES"; + + localparam IODELAY_SIM_DEVICE = (FPGA_TECHNOLOGY == ULTRASCALE_PLUS) ? "ULTRASCALE_PLUS" : + (FPGA_TECHNOLOGY == ULTRASCALE) ? "ULTRASCALE" : "7SERIES"; + +/* +* For 7 series, IDELAYCTRL is enabled ALWAYS, meaning in the following situations: + * when IDELAY_TYPE = FIXED + * when IDELAY_TYPE = VARIABLE + * when IDELAY_TYPE = VAR_LOAD +**/ + +/* + * For UltraScale/UltraScale+: + * when DELAY_FORMAT = TIME: + * IDELAYCTRL must be used + * REFCLK_FREQUENCY must reflect the clock frequency of REF_CLK applied to + the IDELAYCTRL component + * DELAY_VALUE attribute represents an amount in ps + * The total delay through the IDELAYE3 is the align delay + DELAY_VALUE + * EN_VTC depends on DELAY_TYPE attribute: + * when FIXED mode: EN_VTC = 1 + * It must be actively manipulated when the delay line is used in + VARIABLE or VAR_LOAD mode + (this section is NOT IMPLEMENTED! More details in UG571, DELAY_TYPE = VAR_LOAD mode and VARIABLE mode) + + * when DELAY_FORMAT = COUNT: + * DO NOT use an IDELAYCTRL + * REFCLK_FREQUENCY must be set to default frequency (300MHz) + * Delay line represents an amount of taps (512 taps available) + * CNTVALUEIN/OUT[8:0] values represent the amount of taps the delay line + is set to + * EN_VTC = 0 + **/ + + // internal signals + + wire rx_data_ibuf_s; + wire rx_data_idelay_s; + wire [ 8:0] up_drdata_s; + + // internal registers + + reg en_vtc; + + // determine EN_VTC (VAR_LOAD and VARIABLE modes not implemented as in UG571) + + always @(posedge rx_clk) begin + if (DELAY_FORMAT == "TIME") begin + if (US_DELAY_TYPE == "FIXED") begin + en_vtc <= 1'b1; + end else begin // "VAR_LOAD", "VARIABLE" + en_vtc <= ~up_dld; + end + end else begin // "COUNT" + en_vtc <= 1'b0; + end + end + + // delay controller + + generate + if (IODELAY_CTRL_ENABLED == 0) begin + assign delay_locked = 1'b1; + end else begin + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYCTRL #( + .SIM_DEVICE (IODELAY_CTRL_SIM_DEVICE) + ) i_delay_ctrl ( + .RST (delay_rst), + .REFCLK (delay_clk), + .RDY (delay_locked)); + end + endgenerate + + // receive data interface, ibuf -> idelay -> iddr(if enabled) + + // ibuf + + generate + if (SINGLE_ENDED == 1) begin + IBUF i_rx_data_ibuf ( + .I (rx_data_in_p), + .O (rx_data_ibuf_s)); + end else begin + IBUFDS i_rx_data_ibuf ( + .I (rx_data_in_p), + .IB (rx_data_in_n), + .O (rx_data_ibuf_s)); + end + endgenerate + + // bypass IDELAY + + generate + if (IODELAY_ENABLE == 0) begin + assign rx_data_idelay_s = rx_data_ibuf_s; + assign up_drdata = 5'd0; + end + endgenerate + + // idelay + + generate + if (FPGA_TECHNOLOGY == SEVEN_SERIES && IODELAY_ENABLE == 1) begin + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYE2 #( + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("FALSE"), + .IDELAY_TYPE (IDELAY_TYPE), + .IDELAY_VALUE (0), + .REFCLK_FREQUENCY (REFCLK_FREQUENCY), + .PIPE_SEL ("FALSE"), + .SIGNAL_PATTERN ("DATA") + ) i_rx_data_idelay ( + .CE (1'b0), + .INC (1'b0), + .DATAIN (1'b0), + .LDPIPEEN (1'b0), + .CINVCTRL (1'b0), + .REGRST (1'b0), + .C (up_clk), + .IDATAIN (rx_data_ibuf_s), + .DATAOUT (rx_data_idelay_s), + .LD (up_dld), + .CNTVALUEIN (up_dwdata), + .CNTVALUEOUT (up_drdata)); + end + endgenerate + + generate + if ((FPGA_TECHNOLOGY == ULTRASCALE || FPGA_TECHNOLOGY == ULTRASCALE_PLUS) + && (IODELAY_ENABLE == 1)) begin + + assign up_drdata = up_drdata_s[8:4]; + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYE3 #( + .SIM_DEVICE (IODELAY_SIM_DEVICE), + .DELAY_SRC ("IDATAIN"), + .DELAY_TYPE (US_DELAY_TYPE), + .REFCLK_FREQUENCY (REFCLK_FREQUENCY), + .DELAY_FORMAT (DELAY_FORMAT) + ) i_rx_data_idelay ( + .CASC_RETURN (1'b0), + .CASC_IN (1'b0), + .CASC_OUT (), + .CE (1'b0), + .CLK (up_clk), + .INC (1'b0), + .LOAD (up_dld), + .CNTVALUEIN ({up_dwdata, 4'd0}), + .CNTVALUEOUT (up_drdata_s), + .DATAIN (1'b0), + .IDATAIN (rx_data_ibuf_s), + .DATAOUT (rx_data_idelay_s), + .RST (1'b0), + .EN_VTC (en_vtc)); + end + endgenerate + + // DDR or SDR + + generate + if (DDR_SDR_N == 1'b1) begin + // iddr + if (FPGA_TECHNOLOGY == ULTRASCALE || FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin + IDDRE1 #( + .DDR_CLK_EDGE (IDDR_CLK_EDGE) + ) i_rx_data_iddr ( + .R (1'b0), + .C (rx_clk), + .CB (~rx_clk), + .D (rx_data_idelay_s), + .Q1 (rx_data_p), + .Q2 (rx_data_n)); + end + + if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin + IDDR #( + .DDR_CLK_EDGE (IDDR_CLK_EDGE) + ) i_rx_data_iddr ( + .CE (1'b1), + .R (1'b0), + .S (1'b0), + .C (rx_clk), + .D (rx_data_idelay_s), + .Q1 (rx_data_p), + .Q2 (rx_data_n)); + end + // sdr + end else begin + assign rx_data_p = rx_data_idelay_s; + assign rx_data_n = 1'b0; + end + endgenerate + +endmodule diff --git a/adi_library/xilinx/common/ad_data_out.v b/adi_library/xilinx/common/ad_data_out.v new file mode 100755 index 00000000..68cd566d --- /dev/null +++ b/adi_library/xilinx/common/ad_data_out.v @@ -0,0 +1,278 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_data_out #( + + parameter FPGA_TECHNOLOGY = 0, + parameter SINGLE_ENDED = 0, + parameter IDDR_CLK_EDGE ="SAME_EDGE", + // for 7 series devices + parameter ODELAY_TYPE = "VAR_LOAD", + // for ultrascale devices + parameter DELAY_FORMAT = "COUNT", + parameter US_DELAY_TYPE = "VAR_LOAD", + // for all + parameter IODELAY_ENABLE = 0, + parameter IODELAY_CTRL = 0, + parameter IODELAY_GROUP = "dev_if_delay_group", + parameter REFCLK_FREQUENCY = 200 +) ( + + // data interface + + input tx_clk, + input tx_data_p, + input tx_data_n, + output tx_data_out_p, + output tx_data_out_n, + + // delay-data interface + + input up_clk, + input up_dld, + input [ 4:0] up_dwdata, + output [ 4:0] up_drdata, + + // delay-cntrl interface + + input delay_clk, + input delay_rst, + output delay_locked +); + + localparam NONE = -1; + localparam SEVEN_SERIES = 1; + localparam ULTRASCALE = 2; + localparam ULTRASCALE_PLUS = 3; + + // do not instantiate an IDELAYCTRL if no ODELAY is instantiated + localparam IODELAY_CTRL_ENABLED = (IODELAY_ENABLE & IODELAY_CTRL); + localparam IODELAY_CTRL_SIM_DEVICE = (FPGA_TECHNOLOGY == ULTRASCALE_PLUS) ? "ULTRASCALE" : + (FPGA_TECHNOLOGY == ULTRASCALE) ? "ULTRASCALE" : "7SERIES"; + + localparam IODELAY_SIM_DEVICE = (FPGA_TECHNOLOGY == ULTRASCALE_PLUS) ? "ULTRASCALE_PLUS" : + (FPGA_TECHNOLOGY == ULTRASCALE) ? "ULTRASCALE" : "7SERIES"; + +/* +* For 7 series, IDELAYCTRL is enabled ALWAYS, meaning in the following situations: + * when ODELAY_TYPE = FIXED + * when ODELAY_TYPE = VARIABLE + * when ODELAY_TYPE = VAR_LOAD +**/ + +/* + * For UltraScale/UltraScale+: + * when DELAY_FORMAT = TIME: + * IDELAYCTRL must be used + * REFCLK_FREQUENCY must reflect the clock frequency of REF_CLK applied to + the IDELAYCTRL component + * DELAY_VALUE attribute represents an amount in ps + * The total delay through the IDELAYE3 is the align delay + DELAY_VALUE + * EN_VTC depends on DELAY_TYPE attribute: + * when FIXED mode: EN_VTC = 1 + * It must be actively manipulated when the delay line is used in + VARIABLE or VAR_LOAD mode + (this section is NOT IMPLEMENTED! More details in UG571, DELAY_TYPE = VAR_LOAD mode and VARIABLE mode) + + * when DELAY_FORMAT = COUNT: + * DO NOT use an IDELAYCTRL + * REFCLK_FREQUENCY must be set to default frequency (300MHz) + * Delay line represents an amount of taps (512 taps available) + * CNTVALUEIN/OUT[8:0] values represent the amount of taps the delay line + is set to + * EN_VTC = 0 + **/ + + // internal signals + + wire tx_data_oddr_s; + wire tx_data_odelay_s; + + // internal registers + + reg en_vtc; + + // determine EN_VTC (VAR_LOAD and VARIABLE modes not implemented as in UG571) + + always @(posedge tx_clk) begin + if (DELAY_FORMAT == "TIME") begin + if (US_DELAY_TYPE == "FIXED") begin + en_vtc <= 1'b1; + end else begin // "VAR_LOAD", "VARIABLE" + en_vtc <= ~up_dld; + end + end else begin // "COUNT" + en_vtc <= 1'b0; + end + end + + // delay controller + + generate + if (IODELAY_CTRL_ENABLED == 0) begin + assign delay_locked = 1'b1; + end else begin + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYCTRL #( + .SIM_DEVICE (IODELAY_CTRL_SIM_DEVICE) + ) i_delay_ctrl ( + .RST (delay_rst), + .REFCLK (delay_clk), + .RDY (delay_locked)); + end + endgenerate + + // bypass ODELAY + + generate + if (IODELAY_ENABLE == 0) begin + assign tx_data_odelay_s = tx_data_oddr_s; + assign up_drdata = 5'd0; + end + endgenerate + + // transmit data interface, oddr -> odelay -> obuf + + // oddr + + generate + if ((FPGA_TECHNOLOGY == ULTRASCALE) || (FPGA_TECHNOLOGY == ULTRASCALE_PLUS)) begin + ODDRE1 #( + .SIM_DEVICE (IODELAY_SIM_DEVICE) + ) i_tx_data_oddr ( + .SR (1'b0), + .C (tx_clk), + .D1 (tx_data_n), + .D2 (tx_data_p), + .Q (tx_data_oddr_s)); + end + endgenerate + + generate + if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin + ODDR #( + .DDR_CLK_EDGE (IDDR_CLK_EDGE) + ) i_tx_data_oddr ( + .CE (1'b1), + .R (1'b0), + .S (1'b0), + .C (tx_clk), + .D1 (tx_data_n), + .D2 (tx_data_p), + .Q (tx_data_oddr_s)); + end + endgenerate + + // odelay + + generate + if (FPGA_TECHNOLOGY == SEVEN_SERIES && IODELAY_ENABLE == 1) begin + (* IODELAY_GROUP = IODELAY_GROUP *) + ODELAYE2 #( + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("ODATAIN"), + .HIGH_PERFORMANCE_MODE ("FALSE"), + .ODELAY_TYPE (ODELAY_TYPE), + .ODELAY_VALUE (0), + .REFCLK_FREQUENCY (REFCLK_FREQUENCY), + .PIPE_SEL ("FALSE"), + .SIGNAL_PATTERN ("DATA") + ) i_tx_data_odelay ( + .CE (1'b0), + .CLKIN (1'b0), + .INC (1'b0), + .LDPIPEEN (1'b0), + .CINVCTRL (1'b0), + .REGRST (1'b0), + .C (up_clk), + .ODATAIN (tx_data_oddr_s), + .DATAOUT (tx_data_odelay_s), + .LD (up_dld), + .CNTVALUEIN (up_dwdata), + .CNTVALUEOUT (up_drdata)); + end + endgenerate + + generate + if ((FPGA_TECHNOLOGY == ULTRASCALE_PLUS || FPGA_TECHNOLOGY == ULTRASCALE) + && (IODELAY_ENABLE == 1)) begin + + (* IODELAY_GROUP = IODELAY_GROUP *) + ODELAYE3 #( + .CASCADE ("NONE"), + .DELAY_FORMAT (DELAY_FORMAT), + .DELAY_TYPE (US_DELAY_TYPE), + .DELAY_VALUE (0), + .IS_CLK_INVERTED (1'b0), + .IS_RST_INVERTED (1'b0), + .REFCLK_FREQUENCY (REFCLK_FREQUENCY), + .SIM_DEVICE (IODELAY_SIM_DEVICE), + .UPDATE_MODE ("ASYNC") + ) i_tx_data_odelay ( + .CASC_RETURN (1'b0), + .CASC_IN (1'b0), + .CASC_OUT (), + .CE (1'b0), + .CLK (up_clk), + .INC (1'b0), + .LOAD (up_dld), + .CNTVALUEIN (up_dwdata), + .CNTVALUEOUT (up_drdata), + .ODATAIN (tx_data_oddr_s), + .DATAOUT (tx_data_odelay_s), + .RST (1'b0), + .EN_VTC (en_vtc)); + end + endgenerate + + // obuf + + generate + if (SINGLE_ENDED == 1) begin + assign tx_data_out_n = 1'b0; + OBUF i_tx_data_obuf ( + .I (tx_data_odelay_s), + .O (tx_data_out_p)); + end else begin + OBUFDS i_tx_data_obuf ( + .I (tx_data_odelay_s), + .O (tx_data_out_p), + .OB (tx_data_out_n)); + end + endgenerate + +endmodule diff --git a/adi_library/xilinx/common/ad_dcfilter.v b/adi_library/xilinx/common/ad_dcfilter.v new file mode 100644 index 00000000..c05b83aa --- /dev/null +++ b/adi_library/xilinx/common/ad_dcfilter.v @@ -0,0 +1,196 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// dc filter- y(n) = c*x(n) + (1-c)*y(n-1) + +`timescale 1ps/1ps + +module ad_dcfilter #( + + // data path disable + + parameter DISABLE = 0 +) ( + + // data interface + + input clk, + input valid, + input [15:0] data, + output valid_out, + output [15:0] data_out, + + // control interface + + input dcfilt_enb, + input [15:0] dcfilt_coeff, + input [15:0] dcfilt_offset +); + + // internal registers + + reg [15:0] dcfilt_coeff_d = 'd0; + reg [47:0] dc_offset = 'd0; + reg [47:0] dc_offset_d = 'd0; + reg valid_d = 'd0; + reg [15:0] data_d = 'd0; + reg valid_2d = 'd0; + reg [15:0] data_2d = 'd0; + reg [15:0] data_dcfilt = 'd0; + reg valid_int = 'd0; + reg [15:0] data_int = 'd0; + + // internal signals + + wire [47:0] dc_offset_s; + + // data-path disable + + generate + if (DISABLE == 1) begin + assign valid_out = valid; + assign data_out = data; + end else begin + assign valid_out = valid_int; + assign data_out = data_int; + end + endgenerate + + // dcfilt_coeff is flopped so to remove warnings from vivado + + always @(posedge clk) begin + dcfilt_coeff_d <= dcfilt_coeff; + end + + // removing dc offset + + always @(posedge clk) begin + dc_offset <= dc_offset_s; + dc_offset_d <= dc_offset; + valid_d <= valid; + if (valid == 1'b1) begin + data_d <= data + dcfilt_offset; + end + valid_2d <= valid_d; + data_2d <= data_d; + data_dcfilt <= data_d - dc_offset[32:17]; + if (dcfilt_enb == 1'b1) begin + valid_int <= valid_2d; + data_int <= data_dcfilt; + end else begin + valid_int <= valid_2d; + data_int <= data_2d; + end + end + + // dsp slice instance ((D-A)*B)+C + + DSP48E1 #( + .ACASCREG (1), + .ADREG (1), + .ALUMODEREG (0), + .AREG (1), + .AUTORESET_PATDET ("NO_RESET"), + .A_INPUT ("DIRECT"), + .BCASCREG (1), + .BREG (1), + .B_INPUT ("DIRECT"), + .CARRYINREG (0), + .CARRYINSELREG (0), + .CREG (1), + .DREG (0), + .INMODEREG (0), + .MASK (48'h3fffffffffff), + .MREG (1), + .OPMODEREG (0), + .PATTERN (48'h000000000000), + .PREG (1), + .SEL_MASK ("MASK"), + .SEL_PATTERN ("PATTERN"), + .USE_DPORT ("TRUE"), + .USE_MULT ("MULTIPLY"), + .USE_PATTERN_DETECT ("NO_PATDET"), + .USE_SIMD ("ONE48") + ) i_dsp48e1 ( + .CLK (clk), + .A ({{14{dc_offset_s[32]}}, dc_offset_s[32:17]}), + .B ({{2{dcfilt_coeff_d[15]}}, dcfilt_coeff_d}), + .C (dc_offset_d), + .D ({{9{data_d[15]}}, data_d}), + .MULTSIGNIN (1'd0), + .CARRYIN (1'd0), + .CARRYCASCIN (1'd0), + .ACIN (30'd0), + .BCIN (18'd0), + .PCIN (48'd0), + .P (dc_offset_s), + .MULTSIGNOUT (), + .CARRYOUT (), + .CARRYCASCOUT (), + .ACOUT (), + .BCOUT (), + .PCOUT (), + .ALUMODE (4'd0), + .CARRYINSEL (3'd0), + .INMODE (5'b01100), + .OPMODE (7'b0110101), + .PATTERNBDETECT (), + .PATTERNDETECT (), + .OVERFLOW (), + .UNDERFLOW (), + .CEA1 (1'd0), + .CEA2 (1'd1), + .CEAD (1'd1), + .CEALUMODE (1'd0), + .CEB1 (1'd0), + .CEB2 (1'd1), + .CEC (1'd1), + .CECARRYIN (1'd0), + .CECTRL (1'd0), + .CED (1'd1), + .CEINMODE (1'd0), + .CEM (1'd1), + .CEP (1'd0), + .RSTA (1'd0), + .RSTALLCARRYIN (1'd0), + .RSTALUMODE (1'd0), + .RSTB (1'd0), + .RSTC (1'd0), + .RSTCTRL (1'd0), + .RSTD (1'd0), + .RSTINMODE (1'd0), + .RSTM (1'd0), + .RSTP (1'd0)); + +endmodule diff --git a/adi_library/xilinx/common/ad_mmcm_drp.v b/adi_library/xilinx/common/ad_mmcm_drp.v new file mode 100644 index 00000000..bf19b4f2 --- /dev/null +++ b/adi_library/xilinx/common/ad_mmcm_drp.v @@ -0,0 +1,351 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// MMCM_OR_BUFR_N with DRP and device specific + +`timescale 1ns/100ps + +module ad_mmcm_drp #( + + parameter FPGA_TECHNOLOGY = 0, + parameter MMCM_CLKIN_PERIOD = 1.667, + parameter MMCM_CLKIN2_PERIOD = 1.667, + parameter MMCM_VCO_DIV = 6, + parameter MMCM_VCO_MUL = 12.000, + parameter MMCM_CLK0_DIV = 2.000, + parameter MMCM_CLK0_PHASE = 0.000, + parameter MMCM_CLK1_DIV = 6, + parameter MMCM_CLK1_PHASE = 0.000, + parameter MMCM_CLK2_DIV = 2.000, + parameter MMCM_CLK2_PHASE = 0.000 +) ( + + // clocks + + input clk, + input clk2, + input clk_sel, + input mmcm_rst, + output mmcm_clk_0, + output mmcm_clk_1, + output mmcm_clk_2, + + // drp interface + + input up_clk, + input up_rstn, + input up_drp_sel, + input up_drp_wr, + input [11:0] up_drp_addr, + input [15:0] up_drp_wdata, + output reg [15:0] up_drp_rdata, + output reg up_drp_ready, + output reg up_drp_locked +); + + localparam SEVEN_SERIES = 1; + localparam ULTRASCALE = 2; + localparam ULTRASCALE_PLUS = 3; + + // internal registers + + reg up_drp_locked_m1 = 'd0; + + // internal signals + + wire bufg_fb_clk_s; + wire mmcm_fb_clk_s; + wire mmcm_clk_0_s; + wire mmcm_clk_1_s; + wire mmcm_clk_2_s; + wire mmcm_locked_s; + wire [15:0] up_drp_rdata_s; + wire up_drp_ready_s; + + // drp read and locked + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_drp_rdata <= 'd0; + up_drp_ready <= 'd0; + up_drp_locked_m1 <= 1'd0; + up_drp_locked <= 1'd0; + end else begin + up_drp_rdata <= up_drp_rdata_s; + up_drp_ready <= up_drp_ready_s; + up_drp_locked_m1 <= mmcm_locked_s; + up_drp_locked <= up_drp_locked_m1; + end + end + + // instantiations + + generate + if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin + MMCME2_ADV #( + .BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("ZHOLD"), + .STARTUP_WAIT ("FALSE"), + .DIVCLK_DIVIDE (MMCM_VCO_DIV), + .CLKFBOUT_MULT_F (MMCM_VCO_MUL), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV), + .CLKOUT0_PHASE (MMCM_CLK0_PHASE), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKOUT1_DIVIDE (MMCM_CLK1_DIV), + .CLKOUT1_PHASE (MMCM_CLK1_PHASE), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKOUT2_DIVIDE (MMCM_CLK2_DIV), + .CLKOUT2_PHASE (MMCM_CLK2_PHASE), + .CLKOUT2_DUTY_CYCLE (0.500), + .CLKOUT2_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (MMCM_CLKIN_PERIOD), + .CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD), + .REF_JITTER1 (0.010) + ) i_mmcm ( + .CLKIN1 (clk), + .CLKFBIN (bufg_fb_clk_s), + .CLKFBOUT (mmcm_fb_clk_s), + .CLKOUT0 (mmcm_clk_0_s), + .CLKOUT1 (mmcm_clk_1_s), + .CLKOUT2 (mmcm_clk_2_s), + .LOCKED (mmcm_locked_s), + .DCLK (up_clk), + .DEN (up_drp_sel), + .DADDR (up_drp_addr[6:0]), + .DWE (up_drp_wr), + .DI (up_drp_wdata), + .DO (up_drp_rdata_s), + .DRDY (up_drp_ready_s), + .CLKFBOUTB (), + .CLKOUT0B (), + .CLKOUT1B (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + .CLKIN2 (clk2), + .CLKINSEL (clk_sel), + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .RST (mmcm_rst)); + + BUFG i_fb_clk_bufg ( + .I (mmcm_fb_clk_s), + .O (bufg_fb_clk_s)); + + BUFG i_clk_0_bufg ( + .I (mmcm_clk_0_s), + .O (mmcm_clk_0)); + + BUFG i_clk_1_bufg ( + .I (mmcm_clk_1_s), + .O (mmcm_clk_1)); + + BUFG i_clk_2_bufg ( + .I (mmcm_clk_2_s), + .O (mmcm_clk_2)); + + end else if (FPGA_TECHNOLOGY == ULTRASCALE) begin + MMCME3_ADV #( + .BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("AUTO"), + .STARTUP_WAIT ("FALSE"), + + .DIVCLK_DIVIDE (MMCM_VCO_DIV), + .CLKFBOUT_MULT_F (MMCM_VCO_MUL), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV), + .CLKOUT0_PHASE (MMCM_CLK0_PHASE), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKOUT1_DIVIDE (MMCM_CLK1_DIV), + .CLKOUT1_PHASE (MMCM_CLK1_PHASE), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKOUT2_DIVIDE (MMCM_CLK2_DIV), + .CLKOUT2_PHASE (MMCM_CLK2_PHASE), + .CLKOUT2_DUTY_CYCLE (0.500), + .CLKOUT2_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (MMCM_CLKIN_PERIOD), + .CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD), + .REF_JITTER1 (0.010) + ) i_mmcme3 ( + .CLKIN1 (clk), + .CLKFBIN (bufg_fb_clk_s), + .CLKFBOUT (mmcm_fb_clk_s), + .CLKOUT0 (mmcm_clk_0_s), + .CLKOUT1 (mmcm_clk_1_s), + .CLKOUT2 (mmcm_clk_2_s), + .LOCKED (mmcm_locked_s), + .DCLK (up_clk), + .DEN (up_drp_sel), + .DADDR (up_drp_addr[6:0]), + .DWE (up_drp_wr), + .DI (up_drp_wdata), + .DO (up_drp_rdata_s), + .DRDY (up_drp_ready_s), + .CLKFBOUTB (), + .CLKOUT0B (), + .CLKOUT1B (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + .CLKIN2 (clk2), + .CLKINSEL (clk_sel), + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .CDDCREQ (1'b0), + .CDDCDONE (), + .RST (mmcm_rst)); + + BUFG i_fb_clk_bufg ( + .I (mmcm_fb_clk_s), + .O (bufg_fb_clk_s)); + + BUFG i_clk_0_bufg ( + .I (mmcm_clk_0_s), + .O (mmcm_clk_0)); + + BUFG i_clk_1_bufg ( + .I (mmcm_clk_1_s), + .O (mmcm_clk_1)); + + BUFG i_clk_2_bufg ( + .I (mmcm_clk_2_s), + .O (mmcm_clk_2)); + + end else if (FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin + MMCME4_ADV #( + .BANDWIDTH ("OPTIMIZED"), + .CLKOUT4_CASCADE ("FALSE"), + .COMPENSATION ("AUTO"), + .STARTUP_WAIT ("FALSE"), + + .DIVCLK_DIVIDE (MMCM_VCO_DIV), + .CLKFBOUT_MULT_F (MMCM_VCO_MUL), + .CLKFBOUT_PHASE (0.000), + .CLKFBOUT_USE_FINE_PS ("FALSE"), + .CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV), + .CLKOUT0_PHASE (MMCM_CLK0_PHASE), + .CLKOUT0_DUTY_CYCLE (0.500), + .CLKOUT0_USE_FINE_PS ("FALSE"), + .CLKOUT1_DIVIDE (MMCM_CLK1_DIV), + .CLKOUT1_PHASE (MMCM_CLK1_PHASE), + .CLKOUT1_DUTY_CYCLE (0.500), + .CLKOUT1_USE_FINE_PS ("FALSE"), + .CLKOUT2_DIVIDE (MMCM_CLK2_DIV), + .CLKOUT2_PHASE (MMCM_CLK2_PHASE), + .CLKOUT2_DUTY_CYCLE (0.500), + .CLKOUT2_USE_FINE_PS ("FALSE"), + .CLKIN1_PERIOD (MMCM_CLKIN_PERIOD), + .CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD) + ) i_mmcme4 ( + .CLKIN1 (clk), + .CLKFBIN (bufg_fb_clk_s), + .CLKFBOUT (mmcm_fb_clk_s), + .CLKOUT0 (mmcm_clk_0_s), + .CLKOUT1 (mmcm_clk_1_s), + .CLKOUT2 (mmcm_clk_2_s), + .LOCKED (mmcm_locked_s), + .DCLK (up_clk), + .DEN (up_drp_sel), + .DADDR (up_drp_addr[6:0]), + .DWE (up_drp_wr), + .DI (up_drp_wdata), + .DO (up_drp_rdata_s), + .DRDY (up_drp_ready_s), + .CLKFBOUTB (), + .CLKOUT0B (), + .CLKOUT1B (), + .CLKOUT2B (), + .CLKOUT3 (), + .CLKOUT3B (), + .CLKOUT4 (), + .CLKOUT5 (), + .CLKOUT6 (), + .CLKIN2 (clk2), + .CLKINSEL (clk_sel), + .PSCLK (1'b0), + .PSEN (1'b0), + .PSINCDEC (1'b0), + .PSDONE (), + .CLKINSTOPPED (), + .CLKFBSTOPPED (), + .PWRDWN (1'b0), + .CDDCREQ (1'b0), + .CDDCDONE (), + .RST (mmcm_rst)); + + BUFG i_fb_clk_bufg ( + .I (mmcm_fb_clk_s), + .O (bufg_fb_clk_s)); + + BUFG i_clk_0_bufg ( + .I (mmcm_clk_0_s), + .O (mmcm_clk_0)); + + BUFG i_clk_1_bufg ( + .I (mmcm_clk_1_s), + .O (mmcm_clk_1)); + + BUFG i_clk_2_bufg ( + .I (mmcm_clk_2_s), + .O (mmcm_clk_2)); + + end + endgenerate + +endmodule diff --git a/adi_library/xilinx/common/ad_mul.v b/adi_library/xilinx/common/ad_mul.v new file mode 100644 index 00000000..aeaac430 --- /dev/null +++ b/adi_library/xilinx/common/ad_mul.v @@ -0,0 +1,83 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ps/1ps + +module ad_mul #( + + parameter A_DATA_WIDTH = 17, + parameter B_DATA_WIDTH = 17, + parameter DELAY_DATA_WIDTH = 16 +) ( + + // data_p = data_a * data_b; + + input clk, + input [ A_DATA_WIDTH-1:0] data_a, + input [ B_DATA_WIDTH-1:0] data_b, + output [A_DATA_WIDTH + B_DATA_WIDTH-1:0] data_p, + + // delay interface + + input [(DELAY_DATA_WIDTH-1):0] ddata_in, + output reg [(DELAY_DATA_WIDTH-1):0] ddata_out +); + + // internal registers + + reg [(DELAY_DATA_WIDTH-1):0] p1_ddata = 'd0; + reg [(DELAY_DATA_WIDTH-1):0] p2_ddata = 'd0; + + // a/b reg, m-reg, p-reg delay match + + always @(posedge clk) begin + p1_ddata <= ddata_in; + p2_ddata <= p1_ddata; + ddata_out <= p2_ddata; + end + + MULT_MACRO #( + .LATENCY (3), + .WIDTH_A (A_DATA_WIDTH), + .WIDTH_B (B_DATA_WIDTH) + ) i_mult_macro ( + .CE (1'b1), + .RST (1'b0), + .CLK (clk), + .A (data_a), + .B (data_b), + .P (data_p)); + +endmodule diff --git a/adi_library/xilinx/common/ad_rst_constr.xdc b/adi_library/xilinx/common/ad_rst_constr.xdc new file mode 100644 index 00000000..b39c7b7a --- /dev/null +++ b/adi_library/xilinx/common/ad_rst_constr.xdc @@ -0,0 +1,14 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# the "-quiet" option is added for the axi_spi_engine ip where the ad_rst.v +# module is not always inferred and this causes critical warnings + +set_property -quiet ASYNC_REG TRUE [get_cells -hierarchical -filter {name =~ *rst_async_d*_reg}] +set_property -quiet ASYNC_REG TRUE [get_cells -hierarchical -filter {name =~ *rst_sync_reg}] + +set_false_path -quiet -to [get_pins -hierarchical *rst_sync_reg/PRE] +set_false_path -quiet -to [get_pins -hierarchical *rst_async_d1_reg/PRE] +set_false_path -quiet -to [get_pins -hierarchical *rst_async_d2_reg/PRE] diff --git a/adi_library/xilinx/common/ad_serdes_clk.v b/adi_library/xilinx/common/ad_serdes_clk.v new file mode 100644 index 00000000..c438ac3b --- /dev/null +++ b/adi_library/xilinx/common/ad_serdes_clk.v @@ -0,0 +1,158 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// serial data output interface: serdes(x8) + +`timescale 1ps/1ps + +module ad_serdes_clk #( + + parameter FPGA_TECHNOLOGY = 0, + parameter DDR_OR_SDR_N = 1, + // single ended - 0 + // differential - 1 + parameter CLKIN_DS_OR_SE_N = 1, + parameter SERDES_FACTOR = 8, + parameter MMCM_OR_BUFR_N = 1, + parameter MMCM_CLKIN_PERIOD = 1.667, + parameter MMCM_VCO_DIV = 6, + parameter MMCM_VCO_MUL = 12.000, + parameter MMCM_CLK0_DIV = 2.000, + parameter MMCM_CLK1_DIV = 6 +) ( + + // clock and divided clock + + input rst, + input clk_in_p, + input clk_in_n, + output clk, + output div_clk, + output out_clk, + + // drp interface + + input up_clk, + input up_rstn, + input up_drp_sel, + input up_drp_wr, + input [11:0] up_drp_addr, + input [31:0] up_drp_wdata, + output [31:0] up_drp_rdata, + output up_drp_ready, + output up_drp_locked +); + + localparam BUFR_DIVIDE = (DDR_OR_SDR_N == 1'b1) ? SERDES_FACTOR / 2 : SERDES_FACTOR; + + // internal signals + + wire clk_in_s; + + // defaults + + assign up_drp_rdata[31:16] = 'd0; + + // instantiations + + generate + if (CLKIN_DS_OR_SE_N == 1) begin + IBUFGDS i_clk_in_ibuf ( + .I (clk_in_p), + .IB (clk_in_n), + .O (clk_in_s)); + end else begin + IBUF IBUF_inst ( + .O(clk_in_s), + .I(clk_in_p)); + end + endgenerate + + generate + if (MMCM_OR_BUFR_N == 1) begin + ad_mmcm_drp #( + .FPGA_TECHNOLOGY (FPGA_TECHNOLOGY), + .MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD), + .MMCM_CLKIN2_PERIOD (MMCM_CLKIN_PERIOD), + .MMCM_VCO_DIV (MMCM_VCO_DIV), + .MMCM_VCO_MUL (MMCM_VCO_MUL), + .MMCM_CLK0_DIV (MMCM_CLK0_DIV), + .MMCM_CLK0_PHASE (0.0), + .MMCM_CLK1_DIV (MMCM_CLK1_DIV), + .MMCM_CLK1_PHASE (0.0), + .MMCM_CLK2_DIV (MMCM_CLK0_DIV), + .MMCM_CLK2_PHASE (90.0) + ) i_mmcm_drp ( + .clk (clk_in_s), + .clk2 (1'b0), + .clk_sel (1'b1), + .mmcm_rst (rst), + .mmcm_clk_0 (clk), + .mmcm_clk_1 (div_clk), + .mmcm_clk_2 (out_clk), + .up_clk (up_clk), + .up_rstn (up_rstn), + .up_drp_sel (up_drp_sel), + .up_drp_wr (up_drp_wr), + .up_drp_addr (up_drp_addr), + .up_drp_wdata (up_drp_wdata[15:0]), + .up_drp_rdata (up_drp_rdata[15:0]), + .up_drp_ready (up_drp_ready), + .up_drp_locked (up_drp_locked)); + end + endgenerate + + generate + if (MMCM_OR_BUFR_N == 0) begin + BUFIO i_clk_buf ( + .I (clk_in_s), + .O (clk)); + + BUFR #( + .BUFR_DIVIDE(BUFR_DIVIDE) + ) i_div_clk_buf ( + .CLR (1'b0), + .CE (1'b1), + .I (clk_in_s), + .O (div_clk)); + + assign out_clk = clk; + assign up_drp_rdata[15:0] = 'd0; + assign up_drp_ready = 'd0; + assign up_drp_locked = 'd0; + + end + endgenerate + +endmodule diff --git a/adi_library/xilinx/common/ad_serdes_in.v b/adi_library/xilinx/common/ad_serdes_in.v new file mode 100644 index 00000000..b9218b6d --- /dev/null +++ b/adi_library/xilinx/common/ad_serdes_in.v @@ -0,0 +1,337 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ps/1ps + +module ad_serdes_in #( + + parameter FPGA_TECHNOLOGY = 0, + parameter CMOS_LVDS_N = 0, + parameter DDR_OR_SDR_N = 0, + parameter SERDES_FACTOR = 8, + parameter DATA_WIDTH = 16, + parameter DRP_WIDTH = 5, + parameter IODELAY_ENABLE = 1, + parameter IODELAY_CTRL = 0, + parameter IODELAY_GROUP = "dev_if_delay_group", + parameter REFCLK_FREQUENCY = 200 +) ( + + // reset and clocks + + input rst, + input clk, + input div_clk, + + // data interface + + output [(DATA_WIDTH-1):0] data_s0, // last bit received + output [(DATA_WIDTH-1):0] data_s1, + output [(DATA_WIDTH-1):0] data_s2, + output [(DATA_WIDTH-1):0] data_s3, + output [(DATA_WIDTH-1):0] data_s4, + output [(DATA_WIDTH-1):0] data_s5, + output [(DATA_WIDTH-1):0] data_s6, + output [(DATA_WIDTH-1):0] data_s7, // 1st bit received + input [(DATA_WIDTH-1):0] data_in_p, + input [(DATA_WIDTH-1):0] data_in_n, + + // delay-data interface + + input up_clk, + input [(DATA_WIDTH-1):0] up_dld, + input [((DATA_WIDTH*DRP_WIDTH)-1):0] up_dwdata, + output [((DATA_WIDTH*DRP_WIDTH)-1):0] up_drdata, + + // delay-control interface + + input delay_clk, + input delay_rst, + output delay_locked +); + + localparam SEVEN_SERIES = 1; + localparam ULTRASCALE = 2; + localparam ULTRASCALE_PLUS = 3; + localparam DATA_RATE = (DDR_OR_SDR_N) ? "DDR" : "SDR"; + + localparam IODELAY_CTRL_ENABLED = (IODELAY_ENABLE == 1) ? IODELAY_CTRL : 0; + localparam SIM_DEVICE = FPGA_TECHNOLOGY == SEVEN_SERIES ? "7SERIES" : + FPGA_TECHNOLOGY == ULTRASCALE ? "ULTRASCALE" : + FPGA_TECHNOLOGY == ULTRASCALE_PLUS ? "ULTRASCALE_PLUS" : + "UNSUPPORTED"; + // when ULTRASCALE_PLUS, use ULTRASCALE because IDELAYCTRL is the same for both + // and doesn't know ULTRASCALE_PLUS string + localparam SIM_DEVICE_IDELAYCTRL = FPGA_TECHNOLOGY == SEVEN_SERIES ? "7SERIES" : + FPGA_TECHNOLOGY == ULTRASCALE ? "ULTRASCALE" : + FPGA_TECHNOLOGY == ULTRASCALE_PLUS ? "ULTRASCALE" : + "UNSUPPORTED"; + // internal registers + + reg [6:0] serdes_rst_seq; + + // internal signals + + wire [(DATA_WIDTH-1):0] data_in_ibuf_s; + wire [(DATA_WIDTH-1):0] data_in_idelay_s; + wire [(DATA_WIDTH-1):0] data_shift1_s; + wire [(DATA_WIDTH-1):0] data_shift2_s; + wire serdes_rst = serdes_rst_seq[6]; + + // delay controller + + generate + if (IODELAY_CTRL_ENABLED == 1) begin + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYCTRL #( + .SIM_DEVICE(SIM_DEVICE_IDELAYCTRL) + ) i_delay_ctrl ( + .RST (delay_rst), + .REFCLK (delay_clk), + .RDY (delay_locked)); + end else begin + assign delay_locked = 1'b1; + end + endgenerate + + // received data interface: ibuf -> idelay -> iserdes + + // ibuf + + genvar l_inst; + generate + for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_io + if (CMOS_LVDS_N == 0) begin + IBUFDS i_ibuf ( + .I (data_in_p[l_inst]), + .IB (data_in_n[l_inst]), + .O (data_in_ibuf_s[l_inst])); + end else begin + IBUF i_ibuf ( + .I (data_in_p[l_inst]), + .O (data_in_ibuf_s[l_inst])); + end + end + endgenerate + + // bypass IDELAY + + generate + if (IODELAY_ENABLE == 0) begin + assign data_in_idelay_s = data_in_ibuf_s; + end + endgenerate + + always @ (posedge div_clk) begin + if (rst) begin + serdes_rst_seq [6:0] <= 7'b0001110; + end else begin + serdes_rst_seq [6:0] <= {serdes_rst_seq [5:0], 1'b0}; + end + end + + // idelay + iserdes + + generate + if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin + for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data + + if (IODELAY_ENABLE == 1) begin + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYE2 #( + .CINVCTRL_SEL ("FALSE"), + .DELAY_SRC ("IDATAIN"), + .HIGH_PERFORMANCE_MODE ("FALSE"), + .IDELAY_TYPE ("VAR_LOAD"), + .IDELAY_VALUE (0), + .REFCLK_FREQUENCY (REFCLK_FREQUENCY), + .PIPE_SEL ("FALSE"), + .SIGNAL_PATTERN ("DATA") + ) i_idelay ( + .CE (1'b0), + .INC (1'b0), + .DATAIN (1'b0), + .LDPIPEEN (1'b0), + .CINVCTRL (1'b0), + .REGRST (1'b0), + .C (up_clk), + .IDATAIN (data_in_ibuf_s[l_inst]), + .DATAOUT (data_in_idelay_s[l_inst]), + .LD (up_dld[l_inst]), + .CNTVALUEIN (up_dwdata[DRP_WIDTH*l_inst +: DRP_WIDTH]), + .CNTVALUEOUT (up_drdata[DRP_WIDTH*l_inst +: DRP_WIDTH])); + end + + ISERDESE2 #( + .DATA_RATE (DATA_RATE), + .DATA_WIDTH (SERDES_FACTOR), + .DYN_CLKDIV_INV_EN ("FALSE"), + .DYN_CLK_INV_EN ("FALSE"), + .INIT_Q1 (1'b0), + .INIT_Q2 (1'b0), + .INIT_Q3 (1'b0), + .INIT_Q4 (1'b0), + .INTERFACE_TYPE ("NETWORKING"), + .IOBDELAY ("IFD"), + .NUM_CE (2), + .OFB_USED ("FALSE"), + .SERDES_MODE ("MASTER"), + .SRVAL_Q1 (1'b0), + .SRVAL_Q2 (1'b0), + .SRVAL_Q3 (1'b0), + .SRVAL_Q4 (1'b0) + ) i_iserdes ( + .O (), + .Q1 (data_s0[l_inst]), + .Q2 (data_s1[l_inst]), + .Q3 (data_s2[l_inst]), + .Q4 (data_s3[l_inst]), + .Q5 (data_s4[l_inst]), + .Q6 (data_s5[l_inst]), + .Q7 (data_s6[l_inst]), + .Q8 (data_s7[l_inst]), + .SHIFTOUT1 (), + .SHIFTOUT2 (), + .BITSLIP (1'b0), + .CE1 (1'b1), + .CE2 (1'b1), + .CLKDIVP (1'b0), + .CLK (clk), + .CLKB (~clk), + .CLKDIV (div_clk), + .OCLK (1'b0), + .DYNCLKDIVSEL (1'b0), + .DYNCLKSEL (1'b0), + .D (1'b0), + .DDLY (data_in_idelay_s[l_inst]), + .OFB (1'b0), + .OCLKB (1'b0), + .RST (serdes_rst), + .SHIFTIN1 (1'b0), + .SHIFTIN2 (1'b0)); + end /* g_data */ + + end + endgenerate + + generate + if (FPGA_TECHNOLOGY == ULTRASCALE || FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin + for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data + + wire div_dld; + wire en_vtc; + wire ld_cnt; + reg [4:0] vtc_cnt = {5{1'b1}}; + + sync_event sync_load ( + .in_clk (up_clk), + .in_event (up_dld[l_inst]), + .out_clk (div_clk), + .out_event (div_dld)); + + if (IODELAY_ENABLE == 1) begin + (* IODELAY_GROUP = IODELAY_GROUP *) + IDELAYE3 #( + .CASCADE ("NONE"), // Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE) + .DELAY_FORMAT ("TIME"), // Units of the DELAY_VALUE (COUNT, TIME) + .DELAY_SRC ("IDATAIN"), // Delay input (DATAIN, IDATAIN) + .DELAY_TYPE ("VAR_LOAD"), // Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD) + .DELAY_VALUE (0), // Input delay value setting + .IS_CLK_INVERTED (1'b0), // Optional inversion for CLK + .IS_RST_INVERTED (1'b0), // Optional inversion for RST + .REFCLK_FREQUENCY (500.0), // IDELAYCTRL clock input frequency in MHz (200.0-2667.0) + .SIM_DEVICE (SIM_DEVICE), // Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, + // ULTRASCALE_PLUS_ES2) + .UPDATE_MODE ("ASYNC") // Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC) + ) i_idelay ( + .CASC_OUT (), // 1-bit output: Cascade delay output to ODELAY input cascade + .CNTVALUEOUT (up_drdata[DRP_WIDTH*l_inst +: DRP_WIDTH]), // 9-bit output: Counter value output + .DATAOUT (data_in_idelay_s[l_inst]), // 1-bit output: Delayed data output + .CASC_IN (1'b0), // 1-bit input: Cascade delay input from slave ODELAY CASCADE_OUT + .CASC_RETURN (1'b0), // 1-bit input: Cascade delay returning from slave ODELAY DATAOUT + .CE (1'b0), // 1-bit input: Active high enable increment/decrement input + .CLK (div_clk), // 1-bit input: Clock input + .CNTVALUEIN (up_dwdata[DRP_WIDTH*l_inst +: DRP_WIDTH]), // 9-bit input: Counter value input + .DATAIN (1'b0), // 1-bit input: Data input from the logic + .EN_VTC (en_vtc), // 1-bit input: Keep delay constant over VT + .IDATAIN (data_in_ibuf_s[l_inst]), // 1-bit input: Data input from the IOBUF + .INC (1'b0), // 1-bit input: Increment / Decrement tap delay input + .LOAD (ld_cnt), // 1-bit input: Load DELAY_VALUE input + .RST (rst)); // 1-bit input: Asynchronous Reset to the DELAY_VALUE + end + + always @(posedge div_clk) begin + if (div_dld) begin + vtc_cnt <= 'h0; + end else if (~(&vtc_cnt)) begin + vtc_cnt <= vtc_cnt + 1; + end + end + + assign en_vtc = &vtc_cnt; + assign ld_cnt = ~vtc_cnt[4] & (&vtc_cnt[3:0]); + + ISERDESE3 #( + .DATA_WIDTH (8), // Parallel data width (4,8) + .FIFO_ENABLE ("FALSE"), // Enables the use of the FIFO + .FIFO_SYNC_MODE ("FALSE"), // Enables the use of internal 2-stage synchronizers on the FIFO + .IS_CLK_B_INVERTED (1'b0), // Optional inversion for CLK_B + .IS_CLK_INVERTED (1'b0), // Optional inversion for CLK + .IS_RST_INVERTED (1'b0), // Optional inversion for RST + .SIM_DEVICE (SIM_DEVICE) // Set the device version (ULTRASCALE, ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, + // ULTRASCALE_PLUS_ES2) + ) i_iserdes( + .FIFO_EMPTY (), // 1-bit output: FIFO empty flag + .INTERNAL_DIVCLK (), // 1-bit output: Internally divided down clock used when FIFO is + // disabled (do not connect) + .Q ({data_s0[l_inst], + data_s1[l_inst], + data_s2[l_inst], + data_s3[l_inst], + data_s4[l_inst], + data_s5[l_inst], + data_s6[l_inst], + data_s7[l_inst]}), // 8-bit registered output + .CLK (clk), // 1-bit input: High-speed clock + .CLKDIV (div_clk), // 1-bit input: Divided Clock + .CLK_B (~clk), // 1-bit input: Inversion of High-speed clock CLK + .D (data_in_idelay_s[l_inst]), // 1-bit input: Serial Data Input + .FIFO_RD_CLK (div_clk), // 1-bit input: FIFO read clock + .FIFO_RD_EN (1'b1), // 1-bit input: Enables reading the FIFO when asserted + .RST (serdes_rst)); // 1-bit input: Asynchronous Reset + end + end + endgenerate +endmodule diff --git a/adi_library/xilinx/common/ad_serdes_out.v b/adi_library/xilinx/common/ad_serdes_out.v new file mode 100644 index 00000000..a8d44716 --- /dev/null +++ b/adi_library/xilinx/common/ad_serdes_out.v @@ -0,0 +1,187 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// serial data output interface: serdes(x8) + +`timescale 1ps/1ps + +module ad_serdes_out #( + + parameter FPGA_TECHNOLOGY = 0, + parameter CMOS_LVDS_N = 0, + parameter DDR_OR_SDR_N = 1, + parameter SERDES_FACTOR = 8, + parameter DATA_WIDTH = 16 +) ( + + // reset and clocks + + input rst, + input clk, + input div_clk, + + // data interface + input data_oe, + input [(DATA_WIDTH-1):0] data_s0, // 1st bit to be transmitted + input [(DATA_WIDTH-1):0] data_s1, + input [(DATA_WIDTH-1):0] data_s2, + input [(DATA_WIDTH-1):0] data_s3, + input [(DATA_WIDTH-1):0] data_s4, + input [(DATA_WIDTH-1):0] data_s5, + input [(DATA_WIDTH-1):0] data_s6, + input [(DATA_WIDTH-1):0] data_s7, // last bit to be transmitted + output [(DATA_WIDTH-1):0] data_out_se, + output [(DATA_WIDTH-1):0] data_out_p, + output [(DATA_WIDTH-1):0] data_out_n +); + + localparam SEVEN_SERIES = 1; + localparam ULTRASCALE = 2; + localparam ULTRASCALE_PLUS = 3; + localparam DR_OQ_DDR = DDR_OR_SDR_N == 1'b1 ? "DDR": "SDR"; + + localparam SIM_DEVICE = FPGA_TECHNOLOGY == SEVEN_SERIES ? "7SERIES" : + FPGA_TECHNOLOGY == ULTRASCALE ? "ULTRASCALE" : + FPGA_TECHNOLOGY == ULTRASCALE_PLUS ? "ULTRASCALE_PLUS" : + "UNSUPPORTED"; + + // internal registers + + reg [6:0] serdes_rst_seq; + + // internal signals + + wire [(DATA_WIDTH-1):0] data_out_s; + wire [(DATA_WIDTH-1):0] serdes_shift1_s; + wire [(DATA_WIDTH-1):0] serdes_shift2_s; + wire [(DATA_WIDTH-1):0] data_t; + wire buffer_disable; + wire serdes_rst = serdes_rst_seq[6]; + + // instantiations + + assign data_out_se = data_out_s; + assign buffer_disable = ~data_oe; + + always @ (posedge div_clk) begin + if (rst) begin + serdes_rst_seq [6:0] <= 7'b0001110; + end else begin + serdes_rst_seq [6:0] <= {serdes_rst_seq [5:0], 1'b0}; + end + end + + // transmit data path: oserdes -> obuf + + genvar l_inst; + generate + for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data + + // oserdes + + if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin + OSERDESE2 #( + .DATA_RATE_OQ (DR_OQ_DDR), + .DATA_RATE_TQ ("SDR"), + .DATA_WIDTH (SERDES_FACTOR), + .TRISTATE_WIDTH (1), + .SERDES_MODE ("MASTER") + ) i_serdes ( + .D1 (data_s0[l_inst]), + .D2 (data_s1[l_inst]), + .D3 (data_s2[l_inst]), + .D4 (data_s3[l_inst]), + .D5 (data_s4[l_inst]), + .D6 (data_s5[l_inst]), + .D7 (data_s6[l_inst]), + .D8 (data_s7[l_inst]), + .T1 (buffer_disable), + .T2 (buffer_disable), + .T3 (buffer_disable), + .T4 (buffer_disable), + .SHIFTIN1 (1'b0), + .SHIFTIN2 (1'b0), + .SHIFTOUT1 (), + .SHIFTOUT2 (), + .OCE (1'b1), + .CLK (clk), + .CLKDIV (div_clk), + .OQ (data_out_s[l_inst]), + .TQ (data_t[l_inst]), + .OFB (), + .TFB (), + .TBYTEIN (1'b0), + .TBYTEOUT (), + .TCE (1'b1), + .RST (serdes_rst)); + end + + if (FPGA_TECHNOLOGY == ULTRASCALE || FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin + OSERDESE3 #( + .DATA_WIDTH (SERDES_FACTOR), + .SIM_DEVICE (SIM_DEVICE) + ) i_serdes ( + .D ({data_s7[l_inst], + data_s6[l_inst], + data_s5[l_inst], + data_s4[l_inst], + data_s3[l_inst], + data_s2[l_inst], + data_s1[l_inst], + data_s0[l_inst]}), + .T (buffer_disable), + .CLK (clk), + .CLKDIV (div_clk), + .OQ (data_out_s[l_inst]), + .T_OUT (data_t[l_inst]), + .RST (serdes_rst)); + end + + // obuf + + if (CMOS_LVDS_N == 0) begin + OBUFTDS i_obuftds ( + .T (data_t[l_inst]), + .I (data_out_s[l_inst]), + .O (data_out_p[l_inst]), + .OB (data_out_n[l_inst])); + end else begin + OBUFT i_obuf ( + .T (data_t[l_inst]), + .I (data_out_s[l_inst]), + .O (data_out_p[l_inst])); + end + end + endgenerate +endmodule diff --git a/adi_library/xilinx/common/up_clock_mon_constr.xdc b/adi_library/xilinx/common/up_clock_mon_constr.xdc new file mode 100644 index 00000000..8bb0ae34 --- /dev/null +++ b/adi_library/xilinx/common/up_clock_mon_constr.xdc @@ -0,0 +1,13 @@ +############################################################################### +## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property ASYNC_REG true [get_cells -hierarchical -filter {name =~ *up_count_running_m*}] +set_property ASYNC_REG true [get_cells -hierarchical -filter {name =~ *d_count_run_m*}] +set_property ASYNC_REG true [get_cells -hierarchical -filter {name =~ *up_d_count_reg*}] + +set_false_path -from [get_cells -hierarchical -filter {name =~ *d_count_run_m3_reg* && IS_SEQUENTIAL}] -to [get_cells -hierarchical -filter {name =~ *up_count_running_m1_reg* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hierarchical -filter {name =~ *up_count_run_reg* && IS_SEQUENTIAL}] -to [get_cells -hierarchical -filter {name =~ *d_count_run_m1_reg* && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hierarchical -filter {name =~ *d_count_reg* && IS_SEQUENTIAL}] -to [get_cells -hierarchical -filter {name =~ *up_d_count_reg* && IS_SEQUENTIAL}] + diff --git a/adi_library/xilinx/common/up_xfer_cntrl_constr.xdc b/adi_library/xilinx/common/up_xfer_cntrl_constr.xdc new file mode 100644 index 00000000..34c1783b --- /dev/null +++ b/adi_library/xilinx/common/up_xfer_cntrl_constr.xdc @@ -0,0 +1,11 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_state*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_toggle_m*}] + +set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}] diff --git a/adi_library/xilinx/common/up_xfer_status_constr.xdc b/adi_library/xilinx/common/up_xfer_status_constr.xdc new file mode 100644 index 00000000..e5964379 --- /dev/null +++ b/adi_library/xilinx/common/up_xfer_status_constr.xdc @@ -0,0 +1,11 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *d_xfer_state*}] +set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *up_xfer_toggle_m*}] + +set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_toggle_m1_reg && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_state_m1_reg && IS_SEQUENTIAL}] +set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_data* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_data_status* && IS_SEQUENTIAL}] diff --git a/adi_library/xilinx/util_adxcvr/Makefile b/adi_library/xilinx/util_adxcvr/Makefile new file mode 100644 index 00000000..dd7b55d5 --- /dev/null +++ b/adi_library/xilinx/util_adxcvr/Makefile @@ -0,0 +1,26 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_adxcvr + +XILINX_DEPS += ../../jesd204/jesd204_common/sync_header_align.v +XILINX_DEPS += bd/bd.tcl +XILINX_DEPS += util_adxcvr.v +XILINX_DEPS += util_adxcvr_constr.xdc +XILINX_DEPS += util_adxcvr_ip.tcl +XILINX_DEPS += util_adxcvr_xch.v +XILINX_DEPS += util_adxcvr_xcm.v + +XILINX_DEPS += ../../interfaces/if_xcvr_ch.xml +XILINX_DEPS += ../../interfaces/if_xcvr_ch_rtl.xml +XILINX_DEPS += ../../interfaces/if_xcvr_cm.xml +XILINX_DEPS += ../../interfaces/if_xcvr_cm_rtl.xml + +XILINX_LIB_DEPS += util_cdc + +XILINX_INTERFACE_DEPS += interfaces + +include ../../scripts/library.mk diff --git a/adi_library/xilinx/util_adxcvr/bd/bd.tcl b/adi_library/xilinx/util_adxcvr/bd/bd.tcl new file mode 100644 index 00000000..195721bd --- /dev/null +++ b/adi_library/xilinx/util_adxcvr/bd/bd.tcl @@ -0,0 +1,49 @@ +############################################################################### +## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +proc init {cellpath otherInfo} { + set ip [get_bd_cells $cellpath] + + bd::mark_propagate_override $ip " \ + XCVR_TYPE CH_HSPMUX PPF0_CFG RXPI_CFG0 RXPI_CFG1 RTX_BUF_CML_CTRL \ + QPLL_LPF RXCDR_CFG3_GEN2 RXCDR_CFG3_GEN3 RXCDR_CFG3_GEN4 TX_PI_BIASSET" + + adi_auto_assign_device_spec $cellpath +} + +# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl) +proc adi_auto_assign_device_spec {cellpath} { + + set ip [get_bd_cells $cellpath] + set ip_param_list [list_property $ip] + set ip_path [bd::get_vlnv_dir [get_property VLNV $ip]] + + set parent_dir "../" + for {set x 1} {$x<=4} {incr x} { + set linkname ${ip_path}${parent_dir}scripts/adi_xilinx_device_info_enc.tcl + if { [file exists $linkname] } { + source ${ip_path}${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl + break + } + append parent_dir "../" + } + + # Find predefindes auto assignable parameters + foreach i $auto_set_param_list { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } + + # Find predefindes auto assignable/overwritable parameters + foreach i $auto_set_param_list_overwritable { + if { [lsearch $ip_param_list "CONFIG.$i"] > 0 } { + set val [adi_device_spec $cellpath $i] + set_property CONFIG.$i $val $ip + } + } +} + diff --git a/adi_library/xilinx/util_adxcvr/component.xml b/adi_library/xilinx/util_adxcvr/component.xml new file mode 100644 index 00000000..68644ece --- /dev/null +++ b/adi_library/xilinx/util_adxcvr/component.xml @@ -0,0 +1,67541 @@ + + + analog.com + user + util_adxcvr + 1.0 + + + up_clk + + + + + + + CLK + + + up_clk + + + + + + ASSOCIATED_RESET + up_rstn + + + + + cpll_ref_clk_0 + + + + + + + CLK + + + cpll_ref_clk_0 + + + + + + ASSOCIATED_RESET + up_rx_rst_0:up_tx_rst_0 + + + + + rx_out_clk_0 + + + + + + + CLK + + + rx_out_clk_0 + + + + + + tx_out_clk_0 + + + + + + + CLK + + + tx_out_clk_0 + + + + + + rx_clk_0 + + + + + + + CLK + + + rx_clk_0 + + + + + + tx_clk_0 + + + + + + + CLK + + + tx_clk_0 + + + + + + qpll_ref_clk_0 + + + + + + + CLK + + + qpll_ref_clk_0 + + + + + + cpll_ref_clk_1 + + + + + + + CLK + + + cpll_ref_clk_1 + + + + + + ASSOCIATED_RESET + up_rx_rst_1:up_tx_rst_1 + + + + + rx_out_clk_1 + + + + + + + CLK + + + rx_out_clk_1 + + + + + + tx_out_clk_1 + + + + + + + CLK + + + tx_out_clk_1 + + + + + + rx_clk_1 + + + + + + + CLK + + + rx_clk_1 + + + + + + tx_clk_1 + + + + + + + CLK + + + tx_clk_1 + + + + + + cpll_ref_clk_2 + + + + + + + CLK + + + cpll_ref_clk_2 + + + + + + ASSOCIATED_RESET + up_rx_rst_2:up_tx_rst_2 + + + + + rx_out_clk_2 + + + + + + + CLK + + + rx_out_clk_2 + + + + + + tx_out_clk_2 + + + + + + + CLK + + + tx_out_clk_2 + + + + + + rx_clk_2 + + + + + + + CLK + + + rx_clk_2 + + + + + + tx_clk_2 + + + + + + + CLK + + + tx_clk_2 + + + + + + cpll_ref_clk_3 + + + + + + + CLK + + + cpll_ref_clk_3 + + + + + + ASSOCIATED_RESET + up_rx_rst_3:up_tx_rst_3 + + + + + rx_out_clk_3 + + + + + + + CLK + + + rx_out_clk_3 + + + + + + tx_out_clk_3 + + + + + + + CLK + + + tx_out_clk_3 + + + + + + rx_clk_3 + + + + + + + CLK + + + rx_clk_3 + + + + + + tx_clk_3 + + + + + + + CLK + + + tx_clk_3 + + + + + + cpll_ref_clk_4 + + + + + + + CLK + + + cpll_ref_clk_4 + + + + + + ASSOCIATED_RESET + up_rx_rst_4:up_tx_rst_4 + + + + + rx_out_clk_4 + + + + + + + CLK + + + rx_out_clk_4 + + + + + + tx_out_clk_4 + + + + + + + CLK + + + tx_out_clk_4 + + + + + + rx_clk_4 + + + + + + + CLK + + + rx_clk_4 + + + + + + tx_clk_4 + + + + + + + CLK + + + tx_clk_4 + + + + + + qpll_ref_clk_4 + + + + + + + CLK + + + qpll_ref_clk_4 + + + + + + cpll_ref_clk_5 + + + + + + + CLK + + + cpll_ref_clk_5 + + + + + + ASSOCIATED_RESET + up_rx_rst_5:up_tx_rst_5 + + + + + rx_out_clk_5 + + + + + + + CLK + + + rx_out_clk_5 + + + + + + tx_out_clk_5 + + + + + + + CLK + + + tx_out_clk_5 + + + + + + rx_clk_5 + + + + + + + CLK + + + rx_clk_5 + + + + + + tx_clk_5 + + + + + + + CLK + + + tx_clk_5 + + + + + + cpll_ref_clk_6 + + + + + + + CLK + + + cpll_ref_clk_6 + + + + + + ASSOCIATED_RESET + up_rx_rst_6:up_tx_rst_6 + + + + + rx_out_clk_6 + + + + + + + CLK + + + rx_out_clk_6 + + + + + + tx_out_clk_6 + + + + + + + CLK + + + tx_out_clk_6 + + + + + + rx_clk_6 + + + + + + + CLK + + + rx_clk_6 + + + + + + tx_clk_6 + + + + + + + CLK + + + tx_clk_6 + + + + + + cpll_ref_clk_7 + + + + + + + CLK + + + cpll_ref_clk_7 + + + + + + ASSOCIATED_RESET + up_rx_rst_7:up_tx_rst_7 + + + + + rx_out_clk_7 + + + + + + + CLK + + + rx_out_clk_7 + + + + + + tx_out_clk_7 + + + + + + + CLK + + + tx_out_clk_7 + + + + + + rx_clk_7 + + + + + + + CLK + + + rx_clk_7 + + + + + + tx_clk_7 + + + + + + + CLK + + + tx_clk_7 + + + + + + cpll_ref_clk_8 + + + + + + + CLK + + + cpll_ref_clk_8 + + + + + + ASSOCIATED_RESET + up_rx_rst_8:up_tx_rst_8 + + + + + rx_out_clk_8 + + + + + + + CLK + + + rx_out_clk_8 + + + + + + tx_out_clk_8 + + + + + + + CLK + + + tx_out_clk_8 + + + + + + rx_clk_8 + + + + + + + CLK + + + rx_clk_8 + + + + + + tx_clk_8 + + + + + + + CLK + + + tx_clk_8 + + + + + + qpll_ref_clk_8 + + + + + + + CLK + + + qpll_ref_clk_8 + + + + + + cpll_ref_clk_9 + + + + + + + CLK + + + cpll_ref_clk_9 + + + + + + ASSOCIATED_RESET + up_rx_rst_9:up_tx_rst_9 + + + + + rx_out_clk_9 + + + + + + + CLK + + + rx_out_clk_9 + + + + + + tx_out_clk_9 + + + + + + + CLK + + + tx_out_clk_9 + + + + + + rx_clk_9 + + + + + + + CLK + + + rx_clk_9 + + + + + + tx_clk_9 + + + + + + + CLK + + + tx_clk_9 + + + + + + cpll_ref_clk_10 + + + + + + + CLK + + + cpll_ref_clk_10 + + + + + + ASSOCIATED_RESET + up_rx_rst_10:up_tx_rst_10 + + + + + rx_out_clk_10 + + + + + + + CLK + + + rx_out_clk_10 + + + + + + tx_out_clk_10 + + + + + + + CLK + + + tx_out_clk_10 + + + + + + rx_clk_10 + + + + + + + CLK + + + rx_clk_10 + + + + + + tx_clk_10 + + + + + + + CLK + + + tx_clk_10 + + + + + + cpll_ref_clk_11 + + + + + + + CLK + + + cpll_ref_clk_11 + + + + + + ASSOCIATED_RESET + up_rx_rst_11:up_tx_rst_11 + + + + + rx_out_clk_11 + + + + + + + CLK + + + rx_out_clk_11 + + + + + + tx_out_clk_11 + + + + + + + CLK + + + tx_out_clk_11 + + + + + + rx_clk_11 + + + + + + + CLK + + + rx_clk_11 + + + + + + tx_clk_11 + + + + + + + CLK + + + tx_clk_11 + + + + + + cpll_ref_clk_12 + + + + + + + CLK + + + cpll_ref_clk_12 + + + + + + ASSOCIATED_RESET + up_rx_rst_12:up_tx_rst_12 + + + + + rx_out_clk_12 + + + + + + + CLK + + + rx_out_clk_12 + + + + + + tx_out_clk_12 + + + + + + + CLK + + + tx_out_clk_12 + + + + + + rx_clk_12 + + + + + + + CLK + + + rx_clk_12 + + + + + + tx_clk_12 + + + + + + + CLK + + + tx_clk_12 + + + + + + qpll_ref_clk_12 + + + + + + + CLK + + + qpll_ref_clk_12 + + + + + + cpll_ref_clk_13 + + + + + + + CLK + + + cpll_ref_clk_13 + + + + + + ASSOCIATED_RESET + up_rx_rst_13:up_tx_rst_13 + + + + + rx_out_clk_13 + + + + + + + CLK + + + rx_out_clk_13 + + + + + + tx_out_clk_13 + + + + + + + CLK + + + tx_out_clk_13 + + + + + + rx_clk_13 + + + + + + + CLK + + + rx_clk_13 + + + + + + tx_clk_13 + + + + + + + CLK + + + tx_clk_13 + + + + + + cpll_ref_clk_14 + + + + + + + CLK + + + cpll_ref_clk_14 + + + + + + ASSOCIATED_RESET + up_rx_rst_14:up_tx_rst_14 + + + + + rx_out_clk_14 + + + + + + + CLK + + + rx_out_clk_14 + + + + + + tx_out_clk_14 + + + + + + + CLK + + + tx_out_clk_14 + + + + + + rx_clk_14 + + + + + + + CLK + + + rx_clk_14 + + + + + + tx_clk_14 + + + + + + + CLK + + + tx_clk_14 + + + + + + cpll_ref_clk_15 + + + + + + + CLK + + + cpll_ref_clk_15 + + + + + + ASSOCIATED_RESET + up_rx_rst_15:up_tx_rst_15 + + + + + rx_out_clk_15 + + + + + + + CLK + + + rx_out_clk_15 + + + + + + tx_out_clk_15 + + + + + + + CLK + + + tx_out_clk_15 + + + + + + rx_clk_15 + + + + + + + CLK + + + rx_clk_15 + + + + + + tx_clk_15 + + + + + + + CLK + + + tx_clk_15 + + + + + + cpll_ref_clk_16 + + + + + + + CLK + + + cpll_ref_clk_16 + + + + + + ASSOCIATED_RESET + up_rx_rst_16:up_tx_rst_16 + + + + + rx_out_clk_16 + + + + + + + CLK + + + rx_out_clk_16 + + + + + + tx_out_clk_16 + + + + + + + CLK + + + tx_out_clk_16 + + + + + + rx_clk_16 + + + + + + + CLK + + + rx_clk_16 + + + + + + tx_clk_16 + + + + + + + CLK + + + tx_clk_16 + + + + + + qpll_ref_clk_16 + + + + + + + CLK + + + qpll_ref_clk_16 + + + + + + cpll_ref_clk_17 + + + + + + + CLK + + + cpll_ref_clk_17 + + + + + + ASSOCIATED_RESET + up_rx_rst_17:up_tx_rst_17 + + + + + rx_out_clk_17 + + + + + + + CLK + + + rx_out_clk_17 + + + + + + tx_out_clk_17 + + + + + + + CLK + + + tx_out_clk_17 + + + + + + rx_clk_17 + + + + + + + CLK + + + rx_clk_17 + + + + + + tx_clk_17 + + + + + + + CLK + + + tx_clk_17 + + + + + + cpll_ref_clk_18 + + + + + + + CLK + + + cpll_ref_clk_18 + + + + + + ASSOCIATED_RESET + up_rx_rst_18:up_tx_rst_18 + + + + + rx_out_clk_18 + + + + + + + CLK + + + rx_out_clk_18 + + + + + + tx_out_clk_18 + + + + + + + CLK + + + tx_out_clk_18 + + + + + + rx_clk_18 + + + + + + + CLK + + + rx_clk_18 + + + + + + tx_clk_18 + + + + + + + CLK + + + tx_clk_18 + + + + + + cpll_ref_clk_19 + + + + + + + CLK + + + cpll_ref_clk_19 + + + + + + ASSOCIATED_RESET + up_rx_rst_19:up_tx_rst_19 + + + + + rx_out_clk_19 + + + + + + + CLK + + + rx_out_clk_19 + + + + + + tx_out_clk_19 + + + + + + + CLK + + + tx_out_clk_19 + + + + + + rx_clk_19 + + + + + + + CLK + + + rx_clk_19 + + + + + + tx_clk_19 + + + + + + + CLK + + + tx_clk_19 + + + + + + cpll_ref_clk_20 + + + + + + + CLK + + + cpll_ref_clk_20 + + + + + + ASSOCIATED_RESET + up_rx_rst_20:up_tx_rst_20 + + + + + rx_out_clk_20 + + + + + + + CLK + + + rx_out_clk_20 + + + + + + tx_out_clk_20 + + + + + + + CLK + + + tx_out_clk_20 + + + + + + rx_clk_20 + + + + + + + CLK + + + rx_clk_20 + + + + + + tx_clk_20 + + + + + + + CLK + + + tx_clk_20 + + + + + + qpll_ref_clk_20 + + + + + + + CLK + + + qpll_ref_clk_20 + + + + + + cpll_ref_clk_21 + + + + + + + CLK + + + cpll_ref_clk_21 + + + + + + ASSOCIATED_RESET + up_rx_rst_21:up_tx_rst_21 + + + + + rx_out_clk_21 + + + + + + + CLK + + + rx_out_clk_21 + + + + + + tx_out_clk_21 + + + + + + + CLK + + + tx_out_clk_21 + + + + + + rx_clk_21 + + + + + + + CLK + + + rx_clk_21 + + + + + + tx_clk_21 + + + + + + + CLK + + + tx_clk_21 + + + + + + cpll_ref_clk_22 + + + + + + + CLK + + + cpll_ref_clk_22 + + + + + + ASSOCIATED_RESET + up_rx_rst_22:up_tx_rst_22 + + + + + rx_out_clk_22 + + + + + + + CLK + + + rx_out_clk_22 + + + + + + tx_out_clk_22 + + + + + + + CLK + + + tx_out_clk_22 + + + + + + rx_clk_22 + + + + + + + CLK + + + rx_clk_22 + + + + + + tx_clk_22 + + + + + + + CLK + + + tx_clk_22 + + + + + + cpll_ref_clk_23 + + + + + + + CLK + + + cpll_ref_clk_23 + + + + + + ASSOCIATED_RESET + up_rx_rst_23:up_tx_rst_23 + + + + + rx_out_clk_23 + + + + + + + CLK + + + rx_out_clk_23 + + + + + + tx_out_clk_23 + + + + + + + CLK + + + tx_out_clk_23 + + + + + + rx_clk_23 + + + + + + + CLK + + + rx_clk_23 + + + + + + tx_clk_23 + + + + + + + CLK + + + tx_clk_23 + + + + + + cpll_ref_clk_24 + + + + + + + CLK + + + cpll_ref_clk_24 + + + + + + ASSOCIATED_RESET + up_rx_rst_24:up_tx_rst_24 + + + + + rx_out_clk_24 + + + + + + + CLK + + + rx_out_clk_24 + + + + + + tx_out_clk_24 + + + + + + + CLK + + + tx_out_clk_24 + + + + + + rx_clk_24 + + + + + + + CLK + + + rx_clk_24 + + + + + + tx_clk_24 + + + + + + + CLK + + + tx_clk_24 + + + + + + qpll_ref_clk_24 + + + + + + + CLK + + + qpll_ref_clk_24 + + + + + + cpll_ref_clk_25 + + + + + + + CLK + + + cpll_ref_clk_25 + + + + + + ASSOCIATED_RESET + up_rx_rst_25:up_tx_rst_25 + + + + + rx_out_clk_25 + + + + + + + CLK + + + rx_out_clk_25 + + + + + + tx_out_clk_25 + + + + + + + CLK + + + tx_out_clk_25 + + + + + + rx_clk_25 + + + + + + + CLK + + + rx_clk_25 + + + + + + tx_clk_25 + + + + + + + CLK + + + tx_clk_25 + + + + + + cpll_ref_clk_26 + + + + + + + CLK + + + cpll_ref_clk_26 + + + + + + ASSOCIATED_RESET + up_rx_rst_26:up_tx_rst_26 + + + + + rx_out_clk_26 + + + + + + + CLK + + + rx_out_clk_26 + + + + + + tx_out_clk_26 + + + + + + + CLK + + + tx_out_clk_26 + + + + + + rx_clk_26 + + + + + + + CLK + + + rx_clk_26 + + + + + + tx_clk_26 + + + + + + + CLK + + + tx_clk_26 + + + + + + cpll_ref_clk_27 + + + + + + + CLK + + + cpll_ref_clk_27 + + + + + + ASSOCIATED_RESET + up_rx_rst_27:up_tx_rst_27 + + + + + rx_out_clk_27 + + + + + + + CLK + + + rx_out_clk_27 + + + + + + tx_out_clk_27 + + + + + + + CLK + + + tx_out_clk_27 + + + + + + rx_clk_27 + + + + + + + CLK + + + rx_clk_27 + + + + + + tx_clk_27 + + + + + + + CLK + + + tx_clk_27 + + + + + + cpll_ref_clk_28 + + + + + + + CLK + + + cpll_ref_clk_28 + + + + + + ASSOCIATED_RESET + up_rx_rst_28:up_tx_rst_28 + + + + + rx_out_clk_28 + + + + + + + CLK + + + rx_out_clk_28 + + + + + + tx_out_clk_28 + + + + + + + CLK + + + tx_out_clk_28 + + + + + + rx_clk_28 + + + + + + + CLK + + + rx_clk_28 + + + + + + tx_clk_28 + + + + + + + CLK + + + tx_clk_28 + + + + + + qpll_ref_clk_28 + + + + + + + CLK + + + qpll_ref_clk_28 + + + + + + cpll_ref_clk_29 + + + + + + + CLK + + + cpll_ref_clk_29 + + + + + + ASSOCIATED_RESET + up_rx_rst_29:up_tx_rst_29 + + + + + rx_out_clk_29 + + + + + + + CLK + + + rx_out_clk_29 + + + + + + tx_out_clk_29 + + + + + + + CLK + + + tx_out_clk_29 + + + + + + rx_clk_29 + + + + + + + CLK + + + rx_clk_29 + + + + + + tx_clk_29 + + + + + + + CLK + + + tx_clk_29 + + + + + + cpll_ref_clk_30 + + + + + + + CLK + + + cpll_ref_clk_30 + + + + + + ASSOCIATED_RESET + up_rx_rst_30:up_tx_rst_30 + + + + + rx_out_clk_30 + + + + + + + CLK + + + rx_out_clk_30 + + + + + + tx_out_clk_30 + + + + + + + CLK + + + tx_out_clk_30 + + + + + + rx_clk_30 + + + + + + + CLK + + + rx_clk_30 + + + + + + tx_clk_30 + + + + + + + CLK + + + tx_clk_30 + + + + + + cpll_ref_clk_31 + + + + + + + CLK + + + cpll_ref_clk_31 + + + + + + ASSOCIATED_RESET + up_rx_rst_31:up_tx_rst_31 + + + + + rx_out_clk_31 + + + + + + + CLK + + + rx_out_clk_31 + + + + + + tx_out_clk_31 + + + + + + + CLK + + + tx_out_clk_31 + + + + + + rx_clk_31 + + + + + + + CLK + + + rx_clk_31 + + + + + + tx_clk_31 + + + + + + + CLK + + + tx_clk_31 + + + + + + rx_clk_2x_0 + + + + + + + CLK + + + rx_clk_2x_0 + + + + + + tx_clk_2x_0 + + + + + + + CLK + + + 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xilinx_anylanguagebehavioralsimulation + + + + + + up_tx_pll_locked_31 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + up_tx_rst_31 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + + false + + + + + + up_tx_user_ready_31 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + up_tx_rst_done_31 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + up_tx_bufstatus_31 + + out + + 1 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + up_tx_prbsforceerr_31 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + up_tx_prbssel_31 + + in + + 3 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + 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xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + up_tx_enb_31 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + up_tx_addr_31 + + in + + 11 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + up_tx_wr_31 + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + up_tx_wdata_31 + + in + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + up_tx_rdata_31 + + out + + 15 + 0 + + + + std_logic_vector + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + up_tx_ready_31 + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + XCVR_TYPE + Xcvr Type + 0 + + + RX_LANE_RATE + Rx Lane Rate + 12.5 + + + TX_LANE_RATE + Tx Lane Rate + 12.5 + + + LINK_MODE + Link Mode + 1 + + + DATA_PATH_WIDTH + Data Path Width + 4 + + + QPLL_REFCLK_DIV + Qpll Refclk Div + 1 + + + QPLL_FBDIV_RATIO + Qpll Fbdiv Ratio + 1 + + + POR_CFG + Por Cfg + 0x0006 + + + PPF0_CFG + Ppf0 Cfg + 0x0600 + + + PPF1_CFG + Ppf1 Cfg + 0x0600 + + + QPLL_CFG + Qpll Cfg + "000011010000000000110000001" + + + QPLL_FBDIV + Qpll Fbdiv + "0000110000" + + + QPLL_CFG0 + Qpll Cfg0 + 0x331C + + + QPLL_CFG1 + Qpll Cfg1 + 0xD038 + + + QPLL_CFG1_G3 + Qpll Cfg1 G3 + 0xD038 + + + QPLL_CFG2 + Qpll Cfg2 + 0x0FC0 + + + QPLL_CFG2_G3 + Qpll Cfg2 G3 + 0x0FC0 + + + QPLL_CFG3 + Qpll Cfg3 + 0x0120 + + + QPLL_CFG4 + Qpll Cfg4 + 0x0003 + + + QPLL_CP_G3 + Qpll Cp G3 + "0000011111" + + + QPLL_LPF + Qpll Lpf + "0100110111" + + + QPLL_CP + Qpll Cp + "0001111111" + + + CPLL_FBDIV + Cpll Fbdiv + 2 + + + CPLL_FBDIV_4_5 + Cpll Fbdiv 4 5 + 5 + + + CPLL_CFG0 + Cpll Cfg0 + 0x01FA + + + CPLL_CFG1 + Cpll Cfg1 + 0x0023 + + + CPLL_CFG2 + Cpll Cfg2 + 0x0002 + + + CPLL_CFG3 + Cpll Cfg3 + 0x0000 + + + CH_HSPMUX + Ch Hspmux + 0x2424 + + + PREIQ_FREQ_BST + Preiq Freq Bst + 0 + + + RXPI_CFG0 + Rxpi Cfg0 + 0x0002 + + + RXPI_CFG1 + Rxpi Cfg1 + 0x0015 + + + RTX_BUF_CML_CTRL + Rtx Buf Cml Ctrl + "011" + + + TX_NUM_OF_LANES + Tx Num Of Lanes + 8 + + + TX_OUT_DIV + Tx Out Div + 1 + + + TX_CLK25_DIV + Tx Clk25 Div + 20 + + + TX_LANE_INVERT + Tx Lane Invert + 0 + + + TX_PI_BIASSET + Tx Pi Biasset + 1 + + + TXPI_CFG + Txpi Cfg + 0x0054 + + + A_TXDIFFCTRL + A Txdiffctrl + "10110" + + + RX_NUM_OF_LANES + Rx Num Of Lanes + 8 + + + RX_OUT_DIV + Rx Out Div + 1 + + + RX_CLK25_DIV + Rx Clk25 Div + 20 + + + RX_DFE_LPM_CFG + Rx Dfe Lpm Cfg + 0x0104 + + + RX_PMA_CFG + Rx Pma Cfg + 0x001E7080 + + + RX_CDR_CFG + Rx Cdr Cfg + 0x0B000023FF10400020 + + + RXCDR_CFG0 + Rxcdr Cfg0 + 0x0002 + + + RXCDR_CFG2 + Rxcdr Cfg2 + 0x0269 + + + RXCDR_CFG2_GEN2 + Rxcdr Cfg2 Gen2 + "1001100101" + + + RXCDR_CFG2_GEN4 + Rxcdr Cfg2 Gen4 + 0x00B4 + + + RXCDR_CFG3 + Rxcdr Cfg3 + 0x0012 + + + RXCDR_CFG3_GEN2 + Rxcdr Cfg3 Gen2 + "011010" + + + RXCDR_CFG3_GEN3 + Rxcdr Cfg3 Gen3 + 0x0012 + + + RXCDR_CFG3_GEN4 + Rxcdr Cfg3 Gen4 + 0x0024 + + + RXDFE_KH_CFG2 + Rxdfe Kh Cfg2 + 0x0200 + + + RXDFE_KH_CFG3 + Rxdfe Kh Cfg3 + 0x4101 + + + RX_WIDEMODE_CDR + Rx Widemode Cdr + "00" + + + RX_XMODE_SEL + Rx Xmode Sel + "1" + + + TXDRV_FREQBAND + Txdrv Freqband + 0 + + + TXFE_CFG0 + Txfe Cfg0 + 0x03C2 + + + TXFE_CFG1 + Txfe Cfg1 + 0x6C00 + + + TXFE_CFG2 + Txfe Cfg2 + 0x6C00 + + + TXFE_CFG3 + Txfe Cfg3 + 0x6C00 + + + TXPI_CFG0 + Txpi Cfg0 + 0x0300 + + + TXPI_CFG1 + Txpi Cfg1 + 0x1000 + + + TXSWBST_EN + Txswbst En + 0 + + + RX_LANE_INVERT + Rx Lane Invert + 0 + + + + + + choice_list_74b5137e + ACTIVE_HIGH + ACTIVE_LOW + + + choice_pairs_07421b06 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + 10 + + + choice_pairs_1942b210 + 2 + 1 + + + + + xilinx_anylanguagesynthesis_view_fileset + + util_adxcvr_constr.xdc + xdc + + + ../../jesd204/jesd204_common/sync_header_align.v + verilogSource + + + util_adxcvr_xch.v + verilogSource + + + util_adxcvr_xcm.v + verilogSource + + + ../../scripts/adi_xilinx_device_info_enc.tcl + tclSource + + + bd/bd.tcl + tclSource + + + util_adxcvr.v + verilogSource + CHECKSUM_ec24f6a3 + + + + xilinx_anylanguagesynthesis_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + ../../jesd204/jesd204_common/sync_header_align.v + verilogSource + + + util_adxcvr_xch.v + verilogSource + + + util_adxcvr_xcm.v + verilogSource + + + ../../scripts/adi_xilinx_device_info_enc.tcl + tclSource + + + bd/bd.tcl + tclSource + + + util_adxcvr.v + verilogSource + + + + xilinx_anylanguagebehavioralsimulation_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + + + xilinx_xpgui_view_fileset + + xgui/util_adxcvr_v1_0.tcl + tclSource + CHECKSUM_fedc5936 + XGUI_VERSION_2 + + + + xilinx_xpgui_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + xilinx_blockdiagram_view_fileset + + bd/bd.tcl + tclSource + + + + xilinx_blockdiagram_analog_com_user_util_cdc_1_0__ref_view_fileset + + + + + + + + xilinx_utilityxitfiles_view_fileset + + gui/util_adxcvr_v1_0.gtcl + GTCL + + + + util_adxcvr_v1_0 + + + XCVR_TYPE + Xcvr Type + 0 + + + RX_LANE_RATE + Rx Lane Rate (Gbps) + 12.5 + + + TX_LANE_RATE + Tx Lane Rate (Gbps) + 12.5 + + + LINK_MODE + Link Layer mode + 1 + + + DATA_PATH_WIDTH + Data Path Width + 4 + + + + true + + + + + + QPLL_REFCLK_DIV + Qpll Refclk Div + 1 + + + QPLL_FBDIV_RATIO + Qpll Fbdiv Ratio + 1 + + + POR_CFG + Por Cfg + 0x0006 + + + PPF0_CFG + Ppf0 Cfg + 0x0600 + + + PPF1_CFG + Ppf1 Cfg + 0x0600 + + + QPLL_CFG + Qpll Cfg + "000011010000000000110000001" + + + QPLL_FBDIV + Qpll Fbdiv + "0000110000" + + + QPLL_CFG0 + Qpll Cfg0 + 0x331C + + + QPLL_CFG1 + Qpll Cfg1 + 0xD038 + + + QPLL_CFG1_G3 + Qpll Cfg1 G3 + 0xD038 + + + QPLL_CFG2 + Qpll Cfg2 + 0x0FC0 + + + QPLL_CFG2_G3 + Qpll Cfg2 G3 + 0x0FC0 + + + QPLL_CFG3 + Qpll Cfg3 + 0x0120 + + + QPLL_CFG4 + Qpll Cfg4 + 0x0003 + + + QPLL_CP_G3 + Qpll Cp G3 + "0000011111" + + + QPLL_LPF + Qpll Lpf + "0100110111" + + + QPLL_CP + Qpll Cp + "0001111111" + + + CPLL_FBDIV + Cpll Fbdiv + 2 + + + CPLL_FBDIV_4_5 + Cpll Fbdiv 4 5 + 5 + + + CPLL_CFG0 + Cpll Cfg0 + 0x01FA + + + CPLL_CFG1 + Cpll Cfg1 + 0x0023 + + + CPLL_CFG2 + Cpll Cfg2 + 0x0002 + + + CPLL_CFG3 + Cpll Cfg3 + 0x0000 + + + CH_HSPMUX + Ch Hspmux + 0x2424 + + + PREIQ_FREQ_BST + Preiq Freq Bst + 0 + + + RXPI_CFG0 + Rxpi Cfg0 + 0x0002 + + + RXPI_CFG1 + Rxpi Cfg1 + 0x0015 + + + RTX_BUF_CML_CTRL + Rtx Buf Cml Ctrl + "011" + + + TX_NUM_OF_LANES + Tx Num Of Lanes + 8 + + + TX_OUT_DIV + Tx Out Div + 1 + + + TX_CLK25_DIV + Tx Clk25 Div + 20 + + + TX_LANE_INVERT + Tx Lane Invert + 0 + + + TX_PI_BIASSET + Tx Pi Biasset + 1 + + + TXPI_CFG + Txpi Cfg + 0x0054 + + + A_TXDIFFCTRL + A Txdiffctrl + "10110" + + + RX_NUM_OF_LANES + Rx Num Of Lanes + 8 + + + RX_OUT_DIV + Rx Out Div + 1 + + + RX_CLK25_DIV + Rx Clk25 Div + 20 + + + RX_DFE_LPM_CFG + Rx Dfe Lpm Cfg + 0x0104 + + + RX_PMA_CFG + Rx Pma Cfg + 0x001E7080 + + + RX_CDR_CFG + Rx Cdr Cfg + 0x0B000023FF10400020 + + + RXCDR_CFG0 + Rxcdr Cfg0 + 0x0002 + + + RXCDR_CFG2 + Rxcdr Cfg2 + 0x0269 + + + RXCDR_CFG2_GEN2 + Rxcdr Cfg2 Gen2 + "1001100101" + + + RXCDR_CFG2_GEN4 + Rxcdr Cfg2 Gen4 + 0x00B4 + + + RXCDR_CFG3 + Rxcdr Cfg3 + 0x0012 + + + RXCDR_CFG3_GEN2 + Rxcdr Cfg3 Gen2 + "011010" + + + RXCDR_CFG3_GEN3 + Rxcdr Cfg3 Gen3 + 0x0012 + + + RXCDR_CFG3_GEN4 + Rxcdr Cfg3 Gen4 + 0x0024 + + + RXDFE_KH_CFG2 + Rxdfe Kh Cfg2 + 0x0200 + + + RXDFE_KH_CFG3 + Rxdfe Kh Cfg3 + 0x4101 + + + RX_WIDEMODE_CDR + Rx Widemode Cdr + "00" + + + RX_XMODE_SEL + Rx Xmode Sel + "1" + + + TXDRV_FREQBAND + Txdrv Freqband + 0 + + + TXFE_CFG0 + Txfe Cfg0 + 0x03C2 + + + TXFE_CFG1 + Txfe Cfg1 + 0x6C00 + + + TXFE_CFG2 + Txfe Cfg2 + 0x6C00 + + + TXFE_CFG3 + Txfe Cfg3 + 0x6C00 + + + TXPI_CFG0 + Txpi Cfg0 + 0x0300 + + + TXPI_CFG1 + Txpi Cfg1 + 0x1000 + + + TXSWBST_EN + Txswbst En + 0 + + + RX_LANE_INVERT + Rx Lane Invert + 0 + + + Component_Name + util_adxcvr_v1_0 + + + + + + virtex7 + + + /Analog_Devices + + util_adxcvr_v1_0 + level_2 + package_project + Analog Devices + https://wiki.analog.com/resources/fpga/docs/util_xcvr + 1 + 2024-01-14T03:58:03Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/xilinx/util_adxcvr/gui/util_adxcvr_v1_0.gtcl b/adi_library/xilinx/util_adxcvr/gui/util_adxcvr_v1_0.gtcl new file mode 100644 index 00000000..1d1e7b62 --- /dev/null +++ b/adi_library/xilinx/util_adxcvr/gui/util_adxcvr_v1_0.gtcl @@ -0,0 +1,12 @@ +# This file is automatically written. Do not modify. +proc gen_USERPARAMETER_DATA_PATH_WIDTH_ENABLEMENT {LINK_MODE } {expr $LINK_MODE==1} +proc gen_USERPARAMETER_DATA_PATH_WIDTH_VALUE {LINK_MODE } {expr $LINK_MODE*4} +proc gen_USERPARAMETER_PPF0_CFG_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x800 : 0x600]]} +proc gen_USERPARAMETER_QPLL_LPF_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x37f : 0x137]]} +proc gen_USERPARAMETER_CH_HSPMUX_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x2424 : {$XCVR_TYPE == 9} ? 0x2020 : 0x0]]} +proc gen_USERPARAMETER_RXPI_CFG0_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x2 : {$XCVR_TYPE == 9} ? 0x100 : 0x0]]} +proc gen_USERPARAMETER_RXPI_CFG1_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x15 : 0x0]]} +proc gen_USERPARAMETER_RTX_BUF_CML_CTRL_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x3 : 0x0]]} +proc gen_USERPARAMETER_TX_PI_BIASSET_VALUE {XCVR_TYPE } {expr {$XCVR_TYPE == 9} ? 0 : 1} +proc gen_USERPARAMETER_RXCDR_CFG3_GEN2_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x12 : 0x1a ]]} +proc gen_USERPARAMETER_RXCDR_CFG3_GEN4_VALUE {XCVR_TYPE } {expr [format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x12 : 0x24 ]]} diff --git a/adi_library/xilinx/util_adxcvr/util_adxcvr.v b/adi_library/xilinx/util_adxcvr/util_adxcvr.v new file mode 100644 index 00000000..ee127ba9 --- /dev/null +++ b/adi_library/xilinx/util_adxcvr/util_adxcvr.v @@ -0,0 +1,7934 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** +// AUTO GENERATED BY util_adxcvr.pl, DO NOT MODIFY! + +`timescale 1ns/1ps + +module util_adxcvr #( + + // gtxe2(2), gthe3(5), gthe4(8), gtye4(9) + + parameter integer XCVR_TYPE = 0, + + parameter real RX_LANE_RATE = 12.5, + parameter real TX_LANE_RATE = 12.5, + + parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B + /* Only 4 is supported at the moment for 8b/10b and 8 for 64b */ + parameter DATA_PATH_WIDTH = LINK_MODE == 2 ? 8 : 4, + + // qpll-configuration + + parameter integer QPLL_REFCLK_DIV = 1, + parameter integer QPLL_FBDIV_RATIO = 1, + parameter [15:0] POR_CFG = 16'b0000000000000110, + parameter [15:0] PPF0_CFG = 16'b0000011000000000, + parameter [15:0] PPF1_CFG = 16'b0000011000000000, + parameter [26:0] QPLL_CFG = 27'h0680181, + parameter [ 9:0] QPLL_FBDIV = 10'b0000110000, + parameter [15:0] QPLL_CFG0 = 16'b0011001100011100, + parameter [15:0] QPLL_CFG1 = 16'b1101000000111000, + parameter [15:0] QPLL_CFG1_G3 = 16'b1101000000111000, + parameter [15:0] QPLL_CFG2 = 16'b0000111111000000, + parameter [15:0] QPLL_CFG2_G3 = 16'b0000111111000000, + parameter [15:0] QPLL_CFG3 = 16'b0000000100100000, + parameter [15:0] QPLL_CFG4 = 16'b0000000000000011, + parameter [15:0] QPLL_CP_G3 = 10'b0000011111, + parameter [15:0] QPLL_LPF = 10'b0100110111, + parameter [15:0] QPLL_CP = 10'b0001111111, + + // cpll-configuration + + parameter integer CPLL_FBDIV = 2, + parameter integer CPLL_FBDIV_4_5 = 5, + parameter [15:0] CPLL_CFG0 = 16'b0000000111111010, + parameter [15:0] CPLL_CFG1 = 16'b0000000000100011, + parameter [15:0] CPLL_CFG2 = 16'b0000000000000010, + parameter [15:0] CPLL_CFG3 = 16'b0000000000000000, + parameter [15:0] CH_HSPMUX = 16'b0010010000100100, + parameter integer PREIQ_FREQ_BST = 0, + parameter [15:0] RXPI_CFG0 = 16'b0000000000000010, + parameter [15:0] RXPI_CFG1 = 16'b0000000000010101, + parameter [2:0] RTX_BUF_CML_CTRL = 3'b011, + + // tx-configuration + + parameter integer TX_NUM_OF_LANES = 8, + parameter integer TX_OUT_DIV = 1, + parameter integer TX_CLK25_DIV = 20, + parameter integer TX_LANE_INVERT = 0, + parameter [15:0] TX_PI_BIASSET = 1, + parameter [15:0] TXPI_CFG = 16'b0000000001010100, + parameter [15:0] A_TXDIFFCTRL = 5'b10110, + + // rx-configuration + + parameter integer RX_NUM_OF_LANES = 8, + parameter integer RX_OUT_DIV = 1, + parameter integer RX_CLK25_DIV = 20, + parameter [15:0] RX_DFE_LPM_CFG = 16'h0104, + parameter [31:0] RX_PMA_CFG = 32'h001e7080, + parameter [72:0] RX_CDR_CFG = 72'h0b000023ff10400020, + parameter [15:0] RXCDR_CFG0 = 16'b0000000000000010, + parameter [15:0] RXCDR_CFG2 = 16'b0000001001101001, + parameter [ 9:0] RXCDR_CFG2_GEN2 = 10'b1001100101, + parameter [15:0] RXCDR_CFG2_GEN4 = 16'b0000000010110100, + parameter [15:0] RXCDR_CFG3 = 16'b0000000000010010, + parameter [ 5:0] RXCDR_CFG3_GEN2 = 6'b011010, + parameter [15:0] RXCDR_CFG3_GEN3 = 16'b0000000000010010, + parameter [15:0] RXCDR_CFG3_GEN4 = 16'b0000000000100100, + parameter [15:0] RXDFE_KH_CFG2 = 16'h0200, + parameter [15:0] RXDFE_KH_CFG3 = 16'h4101, + parameter [ 1:0] RX_WIDEMODE_CDR = 2'b00, + parameter [ 0:0] RX_XMODE_SEL = 1'b1, + parameter integer TXDRV_FREQBAND = 0, + parameter [15:0] TXFE_CFG0 = 16'b0000001111000010, + parameter [15:0] TXFE_CFG1 = 16'b0110110000000000, + parameter [15:0] TXFE_CFG2 = 16'b0110110000000000, + parameter [15:0] TXFE_CFG3 = 16'b0110110000000000, + parameter [15:0] TXPI_CFG0 = 16'b0000001100000000, + parameter [15:0] TXPI_CFG1 = 16'b0001000000000000, + parameter integer TXSWBST_EN = 0, + parameter integer RX_LANE_INVERT = 0 +) ( + + input up_rstn, + input up_clk, + + input qpll_ref_clk_0, + input up_qpll_rst_0, + input cpll_ref_clk_0, + input up_cpll_rst_0, + + input rx_0_p, + input rx_0_n, + output rx_out_clk_0, + output rx_out_clk_div2_0, + input rx_clk_0, + input rx_clk_2x_0, + output [DATA_PATH_WIDTH-1:0] rx_charisk_0, + output [DATA_PATH_WIDTH-1:0] rx_disperr_0, + output [DATA_PATH_WIDTH-1:0] rx_notintable_0, + output [DATA_PATH_WIDTH*8-1:0] rx_data_0, + input rx_calign_0, + output [1:0] rx_header_0, + output rx_block_sync_0, + + output tx_0_p, + output tx_0_n, + output tx_out_clk_0, + output tx_out_clk_div2_0, + input tx_clk_0, + input tx_clk_2x_0, + input [DATA_PATH_WIDTH-1:0] tx_charisk_0, + input [DATA_PATH_WIDTH*8-1:0] tx_data_0, + input [1:0] tx_header_0, + + input up_cm_enb_0, + input [11:0] up_cm_addr_0, + input up_cm_wr_0, + input [15:0] up_cm_wdata_0, + output [15:0] up_cm_rdata_0, + output up_cm_ready_0, + input up_es_enb_0, + input [11:0] up_es_addr_0, + input up_es_wr_0, + input [15:0] up_es_wdata_0, + output [15:0] up_es_rdata_0, + output up_es_ready_0, + input up_es_reset_0, + output up_rx_pll_locked_0, + input up_rx_rst_0, + input up_rx_user_ready_0, + output up_rx_rst_done_0, + input [ 3:0] up_rx_prbssel_0, + input up_rx_prbscntreset_0, + output up_rx_prbserr_0, + output up_rx_prbslocked_0, + output [ 1:0] up_rx_bufstatus_0, + input up_rx_bufstatus_rst_0, + input up_rx_lpm_dfe_n_0, + input [ 2:0] up_rx_rate_0, + input [ 1:0] up_rx_sys_clk_sel_0, + input [ 2:0] up_rx_out_clk_sel_0, + input up_rx_enb_0, + input [11:0] up_rx_addr_0, + input up_rx_wr_0, + input [15:0] up_rx_wdata_0, + output [15:0] up_rx_rdata_0, + output up_rx_ready_0, + output up_tx_pll_locked_0, + input up_tx_rst_0, + input up_tx_user_ready_0, + output up_tx_rst_done_0, + output [ 1:0] up_tx_bufstatus_0, + input up_tx_prbsforceerr_0, + input [ 3:0] up_tx_prbssel_0, + input up_tx_lpm_dfe_n_0, + input [ 2:0] up_tx_rate_0, + input [ 1:0] up_tx_sys_clk_sel_0, + input [ 2:0] up_tx_out_clk_sel_0, + input [ 4:0] up_tx_diffctrl_0, + input [ 4:0] up_tx_postcursor_0, + input [ 4:0] up_tx_precursor_0, + input up_tx_enb_0, + input [11:0] up_tx_addr_0, + input up_tx_wr_0, + input [15:0] up_tx_wdata_0, + output [15:0] up_tx_rdata_0, + output up_tx_ready_0, + + input cpll_ref_clk_1, + input up_cpll_rst_1, + + input rx_1_p, + input rx_1_n, + output rx_out_clk_1, + output rx_out_clk_div2_1, + input rx_clk_1, + input rx_clk_2x_1, + output [DATA_PATH_WIDTH-1:0] rx_charisk_1, + output [DATA_PATH_WIDTH-1:0] rx_disperr_1, + output [DATA_PATH_WIDTH-1:0] rx_notintable_1, + output [DATA_PATH_WIDTH*8-1:0] rx_data_1, + input rx_calign_1, + output [1:0] rx_header_1, + output rx_block_sync_1, + + output tx_1_p, + output tx_1_n, + output tx_out_clk_1, + output tx_out_clk_div2_1, + input tx_clk_1, + input tx_clk_2x_1, + input [DATA_PATH_WIDTH-1:0] tx_charisk_1, + input [DATA_PATH_WIDTH*8-1:0] tx_data_1, + input [1:0] tx_header_1, + + input up_es_enb_1, + input [11:0] up_es_addr_1, + input up_es_wr_1, + input [15:0] up_es_wdata_1, + output [15:0] up_es_rdata_1, + output up_es_ready_1, + input up_es_reset_1, + output up_rx_pll_locked_1, + input up_rx_rst_1, + input up_rx_user_ready_1, + output up_rx_rst_done_1, + input [ 3:0] up_rx_prbssel_1, + input up_rx_prbscntreset_1, + output up_rx_prbserr_1, + output up_rx_prbslocked_1, + output [ 1:0] up_rx_bufstatus_1, + input up_rx_bufstatus_rst_1, + input up_rx_lpm_dfe_n_1, + input [ 2:0] up_rx_rate_1, + input [ 1:0] up_rx_sys_clk_sel_1, + input [ 2:0] up_rx_out_clk_sel_1, + input up_rx_enb_1, + input [11:0] up_rx_addr_1, + input up_rx_wr_1, + input [15:0] up_rx_wdata_1, + output [15:0] up_rx_rdata_1, + output up_rx_ready_1, + output up_tx_pll_locked_1, + input up_tx_rst_1, + input up_tx_user_ready_1, + output up_tx_rst_done_1, + output [ 1:0] up_tx_bufstatus_1, + input up_tx_prbsforceerr_1, + input [ 3:0] up_tx_prbssel_1, + input up_tx_lpm_dfe_n_1, + input [ 2:0] up_tx_rate_1, + input [ 1:0] up_tx_sys_clk_sel_1, + input [ 2:0] up_tx_out_clk_sel_1, + input [ 4:0] up_tx_diffctrl_1, + input [ 4:0] up_tx_postcursor_1, + input [ 4:0] up_tx_precursor_1, + input up_tx_enb_1, + input [11:0] up_tx_addr_1, + input up_tx_wr_1, + input [15:0] up_tx_wdata_1, + output [15:0] up_tx_rdata_1, + output up_tx_ready_1, + + input cpll_ref_clk_2, + input up_cpll_rst_2, + + input rx_2_p, + input rx_2_n, + output rx_out_clk_2, + output rx_out_clk_div2_2, + input rx_clk_2, + input rx_clk_2x_2, + output [DATA_PATH_WIDTH-1:0] rx_charisk_2, + output [DATA_PATH_WIDTH-1:0] rx_disperr_2, + output [DATA_PATH_WIDTH-1:0] rx_notintable_2, + output [DATA_PATH_WIDTH*8-1:0] rx_data_2, + input rx_calign_2, + output [1:0] rx_header_2, + output rx_block_sync_2, + + output tx_2_p, + output tx_2_n, + output tx_out_clk_2, + output tx_out_clk_div2_2, + input tx_clk_2, + input tx_clk_2x_2, + input [DATA_PATH_WIDTH-1:0] tx_charisk_2, + input [DATA_PATH_WIDTH*8-1:0] tx_data_2, + input [1:0] tx_header_2, + + input up_es_enb_2, + input [11:0] up_es_addr_2, + input up_es_wr_2, + input [15:0] up_es_wdata_2, + output [15:0] up_es_rdata_2, + output up_es_ready_2, + input up_es_reset_2, + output up_rx_pll_locked_2, + input up_rx_rst_2, + input up_rx_user_ready_2, + output up_rx_rst_done_2, + input [ 3:0] up_rx_prbssel_2, + input up_rx_prbscntreset_2, + output up_rx_prbserr_2, + output up_rx_prbslocked_2, + output [ 1:0] up_rx_bufstatus_2, + input up_rx_bufstatus_rst_2, + input up_rx_lpm_dfe_n_2, + input [ 2:0] up_rx_rate_2, + input [ 1:0] up_rx_sys_clk_sel_2, + input [ 2:0] up_rx_out_clk_sel_2, + input up_rx_enb_2, + input [11:0] up_rx_addr_2, + input up_rx_wr_2, + input [15:0] up_rx_wdata_2, + output [15:0] up_rx_rdata_2, + output up_rx_ready_2, + output up_tx_pll_locked_2, + input up_tx_rst_2, + input up_tx_user_ready_2, + output up_tx_rst_done_2, + output [ 1:0] up_tx_bufstatus_2, + input up_tx_prbsforceerr_2, + input [ 3:0] up_tx_prbssel_2, + input up_tx_lpm_dfe_n_2, + input [ 2:0] up_tx_rate_2, + input [ 1:0] up_tx_sys_clk_sel_2, + input [ 2:0] up_tx_out_clk_sel_2, + input [ 4:0] up_tx_diffctrl_2, + input [ 4:0] up_tx_postcursor_2, + input [ 4:0] up_tx_precursor_2, + input up_tx_enb_2, + input [11:0] up_tx_addr_2, + input up_tx_wr_2, + input [15:0] up_tx_wdata_2, + output [15:0] up_tx_rdata_2, + output up_tx_ready_2, + + input cpll_ref_clk_3, + input up_cpll_rst_3, + + input rx_3_p, + input rx_3_n, + output rx_out_clk_3, + output rx_out_clk_div2_3, + input rx_clk_3, + input rx_clk_2x_3, + output [DATA_PATH_WIDTH-1:0] rx_charisk_3, + output [DATA_PATH_WIDTH-1:0] rx_disperr_3, + output [DATA_PATH_WIDTH-1:0] rx_notintable_3, + output [DATA_PATH_WIDTH*8-1:0] rx_data_3, + input rx_calign_3, + output [1:0] rx_header_3, + output rx_block_sync_3, + + output tx_3_p, + output tx_3_n, + output tx_out_clk_3, + output tx_out_clk_div2_3, + input tx_clk_3, + input tx_clk_2x_3, + input [DATA_PATH_WIDTH-1:0] tx_charisk_3, + input [DATA_PATH_WIDTH*8-1:0] tx_data_3, + input [1:0] tx_header_3, + + input up_es_enb_3, + input [11:0] up_es_addr_3, + input up_es_wr_3, + input [15:0] up_es_wdata_3, + output [15:0] up_es_rdata_3, + output up_es_ready_3, + input up_es_reset_3, + output up_rx_pll_locked_3, + input up_rx_rst_3, + input up_rx_user_ready_3, + output up_rx_rst_done_3, + input [ 3:0] up_rx_prbssel_3, + input up_rx_prbscntreset_3, + output up_rx_prbserr_3, + output up_rx_prbslocked_3, + output [ 1:0] up_rx_bufstatus_3, + input up_rx_bufstatus_rst_3, + input up_rx_lpm_dfe_n_3, + input [ 2:0] up_rx_rate_3, + input [ 1:0] up_rx_sys_clk_sel_3, + input [ 2:0] up_rx_out_clk_sel_3, + input up_rx_enb_3, + input [11:0] up_rx_addr_3, + input up_rx_wr_3, + input [15:0] up_rx_wdata_3, + output [15:0] up_rx_rdata_3, + output up_rx_ready_3, + output up_tx_pll_locked_3, + input up_tx_rst_3, + input up_tx_user_ready_3, + output up_tx_rst_done_3, + output [ 1:0] up_tx_bufstatus_3, + input up_tx_prbsforceerr_3, + input [ 3:0] up_tx_prbssel_3, + input up_tx_lpm_dfe_n_3, + input [ 2:0] up_tx_rate_3, + input [ 1:0] up_tx_sys_clk_sel_3, + input [ 2:0] up_tx_out_clk_sel_3, + input [ 4:0] up_tx_diffctrl_3, + input [ 4:0] up_tx_postcursor_3, + input [ 4:0] up_tx_precursor_3, + input up_tx_enb_3, + input [11:0] up_tx_addr_3, + input up_tx_wr_3, + input [15:0] up_tx_wdata_3, + output [15:0] up_tx_rdata_3, + output up_tx_ready_3, + + input qpll_ref_clk_4, + input up_qpll_rst_4, + input cpll_ref_clk_4, + input up_cpll_rst_4, + + input rx_4_p, + input rx_4_n, + output rx_out_clk_4, + output rx_out_clk_div2_4, + input rx_clk_4, + input rx_clk_2x_4, + output [DATA_PATH_WIDTH-1:0] rx_charisk_4, + output [DATA_PATH_WIDTH-1:0] rx_disperr_4, + output [DATA_PATH_WIDTH-1:0] rx_notintable_4, + output [DATA_PATH_WIDTH*8-1:0] rx_data_4, + input rx_calign_4, + output [1:0] rx_header_4, + output rx_block_sync_4, + + output tx_4_p, + output tx_4_n, + output tx_out_clk_4, + output tx_out_clk_div2_4, + input tx_clk_4, + input tx_clk_2x_4, + input [DATA_PATH_WIDTH-1:0] tx_charisk_4, + input [DATA_PATH_WIDTH*8-1:0] tx_data_4, + input [1:0] tx_header_4, + + input up_cm_enb_4, + input [11:0] up_cm_addr_4, + input up_cm_wr_4, + input [15:0] up_cm_wdata_4, + output [15:0] up_cm_rdata_4, + output up_cm_ready_4, + input up_es_enb_4, + input [11:0] up_es_addr_4, + input up_es_wr_4, + input [15:0] up_es_wdata_4, + output [15:0] up_es_rdata_4, + output up_es_ready_4, + input up_es_reset_4, + output up_rx_pll_locked_4, + input up_rx_rst_4, + input up_rx_user_ready_4, + output up_rx_rst_done_4, + input [ 3:0] up_rx_prbssel_4, + input up_rx_prbscntreset_4, + output up_rx_prbserr_4, + output up_rx_prbslocked_4, + output [ 1:0] up_rx_bufstatus_4, + input up_rx_bufstatus_rst_4, + input up_rx_lpm_dfe_n_4, + input [ 2:0] up_rx_rate_4, + input [ 1:0] up_rx_sys_clk_sel_4, + input [ 2:0] up_rx_out_clk_sel_4, + input up_rx_enb_4, + input [11:0] up_rx_addr_4, + input up_rx_wr_4, + input [15:0] up_rx_wdata_4, + output [15:0] up_rx_rdata_4, + output up_rx_ready_4, + output up_tx_pll_locked_4, + input up_tx_rst_4, + input up_tx_user_ready_4, + output up_tx_rst_done_4, + output [ 1:0] up_tx_bufstatus_4, + input up_tx_prbsforceerr_4, + input [ 3:0] up_tx_prbssel_4, + input up_tx_lpm_dfe_n_4, + input [ 2:0] up_tx_rate_4, + input [ 1:0] up_tx_sys_clk_sel_4, + input [ 2:0] up_tx_out_clk_sel_4, + input [ 4:0] up_tx_diffctrl_4, + input [ 4:0] up_tx_postcursor_4, + input [ 4:0] up_tx_precursor_4, + input up_tx_enb_4, + input [11:0] up_tx_addr_4, + input up_tx_wr_4, + input [15:0] up_tx_wdata_4, + output [15:0] up_tx_rdata_4, + output up_tx_ready_4, + + input cpll_ref_clk_5, + input up_cpll_rst_5, + + input rx_5_p, + input rx_5_n, + output rx_out_clk_5, + output rx_out_clk_div2_5, + input rx_clk_5, + input rx_clk_2x_5, + output [DATA_PATH_WIDTH-1:0] rx_charisk_5, + output [DATA_PATH_WIDTH-1:0] rx_disperr_5, + output [DATA_PATH_WIDTH-1:0] rx_notintable_5, + output [DATA_PATH_WIDTH*8-1:0] rx_data_5, + input rx_calign_5, + output [1:0] rx_header_5, + output rx_block_sync_5, + + output tx_5_p, + output tx_5_n, + output tx_out_clk_5, + output tx_out_clk_div2_5, + input tx_clk_5, + input tx_clk_2x_5, + input [DATA_PATH_WIDTH-1:0] tx_charisk_5, + input [DATA_PATH_WIDTH*8-1:0] tx_data_5, + input [1:0] tx_header_5, + + input up_es_enb_5, + input [11:0] up_es_addr_5, + input up_es_wr_5, + input [15:0] up_es_wdata_5, + output [15:0] up_es_rdata_5, + output up_es_ready_5, + input up_es_reset_5, + output up_rx_pll_locked_5, + input up_rx_rst_5, + input up_rx_user_ready_5, + output up_rx_rst_done_5, + input [ 3:0] up_rx_prbssel_5, + input up_rx_prbscntreset_5, + output up_rx_prbserr_5, + output up_rx_prbslocked_5, + output [ 1:0] up_rx_bufstatus_5, + input up_rx_bufstatus_rst_5, + input up_rx_lpm_dfe_n_5, + input [ 2:0] up_rx_rate_5, + input [ 1:0] up_rx_sys_clk_sel_5, + input [ 2:0] up_rx_out_clk_sel_5, + input up_rx_enb_5, + input [11:0] up_rx_addr_5, + input up_rx_wr_5, + input [15:0] up_rx_wdata_5, + output [15:0] up_rx_rdata_5, + output up_rx_ready_5, + output up_tx_pll_locked_5, + input up_tx_rst_5, + input up_tx_user_ready_5, + output up_tx_rst_done_5, + output [ 1:0] up_tx_bufstatus_5, + input up_tx_prbsforceerr_5, + input [ 3:0] up_tx_prbssel_5, + input up_tx_lpm_dfe_n_5, + input [ 2:0] up_tx_rate_5, + input [ 1:0] up_tx_sys_clk_sel_5, + input [ 2:0] up_tx_out_clk_sel_5, + input [ 4:0] up_tx_diffctrl_5, + input [ 4:0] up_tx_postcursor_5, + input [ 4:0] up_tx_precursor_5, + input up_tx_enb_5, + input [11:0] up_tx_addr_5, + input up_tx_wr_5, + input [15:0] up_tx_wdata_5, + output [15:0] up_tx_rdata_5, + output up_tx_ready_5, + + input cpll_ref_clk_6, + input up_cpll_rst_6, + + input rx_6_p, + input rx_6_n, + output rx_out_clk_6, + output rx_out_clk_div2_6, + input rx_clk_6, + input rx_clk_2x_6, + output [DATA_PATH_WIDTH-1:0] rx_charisk_6, + output [DATA_PATH_WIDTH-1:0] rx_disperr_6, + output [DATA_PATH_WIDTH-1:0] rx_notintable_6, + output [DATA_PATH_WIDTH*8-1:0] rx_data_6, + input rx_calign_6, + output [1:0] rx_header_6, + output rx_block_sync_6, + + output tx_6_p, + output tx_6_n, + output tx_out_clk_6, + output tx_out_clk_div2_6, + input tx_clk_6, + input tx_clk_2x_6, + input [DATA_PATH_WIDTH-1:0] tx_charisk_6, + input [DATA_PATH_WIDTH*8-1:0] tx_data_6, + input [1:0] tx_header_6, + + input up_es_enb_6, + input [11:0] up_es_addr_6, + input up_es_wr_6, + input [15:0] up_es_wdata_6, + output [15:0] up_es_rdata_6, + output up_es_ready_6, + input up_es_reset_6, + output up_rx_pll_locked_6, + input up_rx_rst_6, + input up_rx_user_ready_6, + output up_rx_rst_done_6, + input [ 3:0] up_rx_prbssel_6, + input up_rx_prbscntreset_6, + output up_rx_prbserr_6, + output up_rx_prbslocked_6, + output [ 1:0] up_rx_bufstatus_6, + input up_rx_bufstatus_rst_6, + input up_rx_lpm_dfe_n_6, + input [ 2:0] up_rx_rate_6, + input [ 1:0] up_rx_sys_clk_sel_6, + input [ 2:0] up_rx_out_clk_sel_6, + input up_rx_enb_6, + input [11:0] up_rx_addr_6, + input up_rx_wr_6, + input [15:0] up_rx_wdata_6, + output [15:0] up_rx_rdata_6, + output up_rx_ready_6, + output up_tx_pll_locked_6, + input up_tx_rst_6, + input up_tx_user_ready_6, + output up_tx_rst_done_6, + output [ 1:0] up_tx_bufstatus_6, + input up_tx_prbsforceerr_6, + input [ 3:0] up_tx_prbssel_6, + input up_tx_lpm_dfe_n_6, + input [ 2:0] up_tx_rate_6, + input [ 1:0] up_tx_sys_clk_sel_6, + input [ 2:0] up_tx_out_clk_sel_6, + input [ 4:0] up_tx_diffctrl_6, + input [ 4:0] up_tx_postcursor_6, + input [ 4:0] up_tx_precursor_6, + input up_tx_enb_6, + input [11:0] up_tx_addr_6, + input up_tx_wr_6, + input [15:0] up_tx_wdata_6, + output [15:0] up_tx_rdata_6, + output up_tx_ready_6, + + input cpll_ref_clk_7, + input up_cpll_rst_7, + + input rx_7_p, + input rx_7_n, + output rx_out_clk_7, + output rx_out_clk_div2_7, + input rx_clk_7, + input rx_clk_2x_7, + output [DATA_PATH_WIDTH-1:0] rx_charisk_7, + output [DATA_PATH_WIDTH-1:0] rx_disperr_7, + output [DATA_PATH_WIDTH-1:0] rx_notintable_7, + output [DATA_PATH_WIDTH*8-1:0] rx_data_7, + input rx_calign_7, + output [1:0] rx_header_7, + output rx_block_sync_7, + + output tx_7_p, + output tx_7_n, + output tx_out_clk_7, + output tx_out_clk_div2_7, + input tx_clk_7, + input tx_clk_2x_7, + input [DATA_PATH_WIDTH-1:0] tx_charisk_7, + input [DATA_PATH_WIDTH*8-1:0] tx_data_7, + input [1:0] tx_header_7, + + input up_es_enb_7, + input [11:0] up_es_addr_7, + input up_es_wr_7, + input [15:0] up_es_wdata_7, + output [15:0] up_es_rdata_7, + output up_es_ready_7, + input up_es_reset_7, + output up_rx_pll_locked_7, + input up_rx_rst_7, + input up_rx_user_ready_7, + output up_rx_rst_done_7, + input [ 3:0] up_rx_prbssel_7, + input up_rx_prbscntreset_7, + output up_rx_prbserr_7, + output up_rx_prbslocked_7, + output [ 1:0] up_rx_bufstatus_7, + input up_rx_bufstatus_rst_7, + input up_rx_lpm_dfe_n_7, + input [ 2:0] up_rx_rate_7, + input [ 1:0] up_rx_sys_clk_sel_7, + input [ 2:0] up_rx_out_clk_sel_7, + input up_rx_enb_7, + input [11:0] up_rx_addr_7, + input up_rx_wr_7, + input [15:0] up_rx_wdata_7, + output [15:0] up_rx_rdata_7, + output up_rx_ready_7, + output up_tx_pll_locked_7, + input up_tx_rst_7, + input up_tx_user_ready_7, + output up_tx_rst_done_7, + output [ 1:0] up_tx_bufstatus_7, + input up_tx_prbsforceerr_7, + input [ 3:0] up_tx_prbssel_7, + input up_tx_lpm_dfe_n_7, + input [ 2:0] up_tx_rate_7, + input [ 1:0] up_tx_sys_clk_sel_7, + input [ 2:0] up_tx_out_clk_sel_7, + input [ 4:0] up_tx_diffctrl_7, + input [ 4:0] up_tx_postcursor_7, + input [ 4:0] up_tx_precursor_7, + input up_tx_enb_7, + input [11:0] up_tx_addr_7, + input up_tx_wr_7, + input [15:0] up_tx_wdata_7, + output [15:0] up_tx_rdata_7, + output up_tx_ready_7, + + input qpll_ref_clk_8, + input up_qpll_rst_8, + input cpll_ref_clk_8, + input up_cpll_rst_8, + + input rx_8_p, + input rx_8_n, + output rx_out_clk_8, + output rx_out_clk_div2_8, + input rx_clk_8, + input rx_clk_2x_8, + output [DATA_PATH_WIDTH-1:0] rx_charisk_8, + output [DATA_PATH_WIDTH-1:0] rx_disperr_8, + output [DATA_PATH_WIDTH-1:0] rx_notintable_8, + output [DATA_PATH_WIDTH*8-1:0] rx_data_8, + input rx_calign_8, + output [1:0] rx_header_8, + output rx_block_sync_8, + + output tx_8_p, + output tx_8_n, + output tx_out_clk_8, + output tx_out_clk_div2_8, + input tx_clk_8, + input tx_clk_2x_8, + input [DATA_PATH_WIDTH-1:0] tx_charisk_8, + input [DATA_PATH_WIDTH*8-1:0] tx_data_8, + input [1:0] tx_header_8, + + input up_cm_enb_8, + input [11:0] up_cm_addr_8, + input up_cm_wr_8, + input [15:0] up_cm_wdata_8, + output [15:0] up_cm_rdata_8, + output up_cm_ready_8, + input up_es_enb_8, + input [11:0] up_es_addr_8, + input up_es_wr_8, + input [15:0] up_es_wdata_8, + output [15:0] up_es_rdata_8, + output up_es_ready_8, + input up_es_reset_8, + output up_rx_pll_locked_8, + input up_rx_rst_8, + input up_rx_user_ready_8, + output up_rx_rst_done_8, + input [ 3:0] up_rx_prbssel_8, + input up_rx_prbscntreset_8, + output up_rx_prbserr_8, + output up_rx_prbslocked_8, + output [ 1:0] up_rx_bufstatus_8, + input up_rx_bufstatus_rst_8, + input up_rx_lpm_dfe_n_8, + input [ 2:0] up_rx_rate_8, + input [ 1:0] up_rx_sys_clk_sel_8, + input [ 2:0] up_rx_out_clk_sel_8, + input up_rx_enb_8, + input [11:0] up_rx_addr_8, + input up_rx_wr_8, + input [15:0] up_rx_wdata_8, + output [15:0] up_rx_rdata_8, + output up_rx_ready_8, + output up_tx_pll_locked_8, + input up_tx_rst_8, + input up_tx_user_ready_8, + output up_tx_rst_done_8, + output [ 1:0] up_tx_bufstatus_8, + input up_tx_prbsforceerr_8, + input [ 3:0] up_tx_prbssel_8, + input up_tx_lpm_dfe_n_8, + input [ 2:0] up_tx_rate_8, + input [ 1:0] up_tx_sys_clk_sel_8, + input [ 2:0] up_tx_out_clk_sel_8, + input [ 4:0] up_tx_diffctrl_8, + input [ 4:0] up_tx_postcursor_8, + input [ 4:0] up_tx_precursor_8, + input up_tx_enb_8, + input [11:0] up_tx_addr_8, + input up_tx_wr_8, + input [15:0] up_tx_wdata_8, + output [15:0] up_tx_rdata_8, + output up_tx_ready_8, + + input cpll_ref_clk_9, + input up_cpll_rst_9, + + input rx_9_p, + input rx_9_n, + output rx_out_clk_9, + output rx_out_clk_div2_9, + input rx_clk_9, + input rx_clk_2x_9, + output [DATA_PATH_WIDTH-1:0] rx_charisk_9, + output [DATA_PATH_WIDTH-1:0] rx_disperr_9, + output [DATA_PATH_WIDTH-1:0] rx_notintable_9, + output [DATA_PATH_WIDTH*8-1:0] rx_data_9, + input rx_calign_9, + output [1:0] rx_header_9, + output rx_block_sync_9, + + output tx_9_p, + output tx_9_n, + output tx_out_clk_9, + output tx_out_clk_div2_9, + input tx_clk_9, + input tx_clk_2x_9, + input [DATA_PATH_WIDTH-1:0] tx_charisk_9, + input [DATA_PATH_WIDTH*8-1:0] tx_data_9, + input [1:0] tx_header_9, + + input up_es_enb_9, + input [11:0] up_es_addr_9, + input up_es_wr_9, + input [15:0] up_es_wdata_9, + output [15:0] up_es_rdata_9, + output up_es_ready_9, + input up_es_reset_9, + output up_rx_pll_locked_9, + input up_rx_rst_9, + input up_rx_user_ready_9, + output up_rx_rst_done_9, + input [ 3:0] up_rx_prbssel_9, + input up_rx_prbscntreset_9, + output up_rx_prbserr_9, + output up_rx_prbslocked_9, + output [ 1:0] up_rx_bufstatus_9, + input up_rx_bufstatus_rst_9, + input up_rx_lpm_dfe_n_9, + input [ 2:0] up_rx_rate_9, + input [ 1:0] up_rx_sys_clk_sel_9, + input [ 2:0] up_rx_out_clk_sel_9, + input up_rx_enb_9, + input [11:0] up_rx_addr_9, + input up_rx_wr_9, + input [15:0] up_rx_wdata_9, + output [15:0] up_rx_rdata_9, + output up_rx_ready_9, + output up_tx_pll_locked_9, + input up_tx_rst_9, + input up_tx_user_ready_9, + output up_tx_rst_done_9, + output [ 1:0] up_tx_bufstatus_9, + input up_tx_prbsforceerr_9, + input [ 3:0] up_tx_prbssel_9, + input up_tx_lpm_dfe_n_9, + input [ 2:0] up_tx_rate_9, + input [ 1:0] up_tx_sys_clk_sel_9, + input [ 2:0] up_tx_out_clk_sel_9, + input [ 4:0] up_tx_diffctrl_9, + input [ 4:0] up_tx_postcursor_9, + input [ 4:0] up_tx_precursor_9, + input up_tx_enb_9, + input [11:0] up_tx_addr_9, + input up_tx_wr_9, + input [15:0] up_tx_wdata_9, + output [15:0] up_tx_rdata_9, + output up_tx_ready_9, + + input cpll_ref_clk_10, + input up_cpll_rst_10, + + input rx_10_p, + input rx_10_n, + output rx_out_clk_10, + output rx_out_clk_div2_10, + input rx_clk_10, + input rx_clk_2x_10, + output [DATA_PATH_WIDTH-1:0] rx_charisk_10, + output [DATA_PATH_WIDTH-1:0] rx_disperr_10, + output [DATA_PATH_WIDTH-1:0] rx_notintable_10, + output [DATA_PATH_WIDTH*8-1:0] rx_data_10, + input rx_calign_10, + output [1:0] rx_header_10, + output rx_block_sync_10, + + output tx_10_p, + output tx_10_n, + output tx_out_clk_10, + output tx_out_clk_div2_10, + input tx_clk_10, + input tx_clk_2x_10, + input [DATA_PATH_WIDTH-1:0] tx_charisk_10, + input [DATA_PATH_WIDTH*8-1:0] tx_data_10, + input [1:0] tx_header_10, + + input up_es_enb_10, + input [11:0] up_es_addr_10, + input up_es_wr_10, + input [15:0] up_es_wdata_10, + output [15:0] up_es_rdata_10, + output up_es_ready_10, + input up_es_reset_10, + output up_rx_pll_locked_10, + input up_rx_rst_10, + input up_rx_user_ready_10, + output up_rx_rst_done_10, + input [ 3:0] up_rx_prbssel_10, + input up_rx_prbscntreset_10, + output up_rx_prbserr_10, + output up_rx_prbslocked_10, + output [ 1:0] up_rx_bufstatus_10, + input up_rx_bufstatus_rst_10, + input up_rx_lpm_dfe_n_10, + input [ 2:0] up_rx_rate_10, + input [ 1:0] up_rx_sys_clk_sel_10, + input [ 2:0] up_rx_out_clk_sel_10, + input up_rx_enb_10, + input [11:0] up_rx_addr_10, + input up_rx_wr_10, + input [15:0] up_rx_wdata_10, + output [15:0] up_rx_rdata_10, + output up_rx_ready_10, + output up_tx_pll_locked_10, + input up_tx_rst_10, + input up_tx_user_ready_10, + output up_tx_rst_done_10, + output [ 1:0] up_tx_bufstatus_10, + input up_tx_prbsforceerr_10, + input [ 3:0] up_tx_prbssel_10, + input up_tx_lpm_dfe_n_10, + input [ 2:0] up_tx_rate_10, + input [ 1:0] up_tx_sys_clk_sel_10, + input [ 2:0] up_tx_out_clk_sel_10, + input [ 4:0] up_tx_diffctrl_10, + input [ 4:0] up_tx_postcursor_10, + input [ 4:0] up_tx_precursor_10, + input up_tx_enb_10, + input [11:0] up_tx_addr_10, + input up_tx_wr_10, + input [15:0] up_tx_wdata_10, + output [15:0] up_tx_rdata_10, + output up_tx_ready_10, + + input cpll_ref_clk_11, + input up_cpll_rst_11, + + input rx_11_p, + input rx_11_n, + output rx_out_clk_11, + output rx_out_clk_div2_11, + input rx_clk_11, + input rx_clk_2x_11, + output [DATA_PATH_WIDTH-1:0] rx_charisk_11, + output [DATA_PATH_WIDTH-1:0] rx_disperr_11, + output [DATA_PATH_WIDTH-1:0] rx_notintable_11, + output [DATA_PATH_WIDTH*8-1:0] rx_data_11, + input rx_calign_11, + output [1:0] rx_header_11, + output rx_block_sync_11, + + output tx_11_p, + output tx_11_n, + output tx_out_clk_11, + output tx_out_clk_div2_11, + input tx_clk_11, + input tx_clk_2x_11, + input [DATA_PATH_WIDTH-1:0] tx_charisk_11, + input [DATA_PATH_WIDTH*8-1:0] tx_data_11, + input [1:0] tx_header_11, + + input up_es_enb_11, + input [11:0] up_es_addr_11, + input up_es_wr_11, + input [15:0] up_es_wdata_11, + output [15:0] up_es_rdata_11, + output up_es_ready_11, + input up_es_reset_11, + output up_rx_pll_locked_11, + input up_rx_rst_11, + input up_rx_user_ready_11, + output up_rx_rst_done_11, + input [ 3:0] up_rx_prbssel_11, + input up_rx_prbscntreset_11, + output up_rx_prbserr_11, + output up_rx_prbslocked_11, + output [ 1:0] up_rx_bufstatus_11, + input up_rx_bufstatus_rst_11, + input up_rx_lpm_dfe_n_11, + input [ 2:0] up_rx_rate_11, + input [ 1:0] up_rx_sys_clk_sel_11, + input [ 2:0] up_rx_out_clk_sel_11, + input up_rx_enb_11, + input [11:0] up_rx_addr_11, + input up_rx_wr_11, + input [15:0] up_rx_wdata_11, + output [15:0] up_rx_rdata_11, + output up_rx_ready_11, + output up_tx_pll_locked_11, + input up_tx_rst_11, + input up_tx_user_ready_11, + output up_tx_rst_done_11, + output [ 1:0] up_tx_bufstatus_11, + input up_tx_prbsforceerr_11, + input [ 3:0] up_tx_prbssel_11, + input up_tx_lpm_dfe_n_11, + input [ 2:0] up_tx_rate_11, + input [ 1:0] up_tx_sys_clk_sel_11, + input [ 2:0] up_tx_out_clk_sel_11, + input [ 4:0] up_tx_diffctrl_11, + input [ 4:0] up_tx_postcursor_11, + input [ 4:0] up_tx_precursor_11, + input up_tx_enb_11, + input [11:0] up_tx_addr_11, + input up_tx_wr_11, + input [15:0] up_tx_wdata_11, + output [15:0] up_tx_rdata_11, + output up_tx_ready_11, + + input qpll_ref_clk_12, + input up_qpll_rst_12, + input cpll_ref_clk_12, + input up_cpll_rst_12, + + input rx_12_p, + input rx_12_n, + output rx_out_clk_12, + output rx_out_clk_div2_12, + input rx_clk_12, + input rx_clk_2x_12, + output [DATA_PATH_WIDTH-1:0] rx_charisk_12, + output [DATA_PATH_WIDTH-1:0] rx_disperr_12, + output [DATA_PATH_WIDTH-1:0] rx_notintable_12, + output [DATA_PATH_WIDTH*8-1:0] rx_data_12, + input rx_calign_12, + output [1:0] rx_header_12, + output rx_block_sync_12, + + output tx_12_p, + output tx_12_n, + output tx_out_clk_12, + output tx_out_clk_div2_12, + input tx_clk_12, + input tx_clk_2x_12, + input [DATA_PATH_WIDTH-1:0] tx_charisk_12, + input [DATA_PATH_WIDTH*8-1:0] tx_data_12, + input [1:0] tx_header_12, + + input up_cm_enb_12, + input [11:0] up_cm_addr_12, + input up_cm_wr_12, + input [15:0] up_cm_wdata_12, + output [15:0] up_cm_rdata_12, + output up_cm_ready_12, + input up_es_enb_12, + input [11:0] up_es_addr_12, + input up_es_wr_12, + input [15:0] up_es_wdata_12, + output [15:0] up_es_rdata_12, + output up_es_ready_12, + input up_es_reset_12, + output up_rx_pll_locked_12, + input up_rx_rst_12, + input up_rx_user_ready_12, + output up_rx_rst_done_12, + input [ 3:0] up_rx_prbssel_12, + input up_rx_prbscntreset_12, + output up_rx_prbserr_12, + output up_rx_prbslocked_12, + output [ 1:0] up_rx_bufstatus_12, + input up_rx_bufstatus_rst_12, + input up_rx_lpm_dfe_n_12, + input [ 2:0] up_rx_rate_12, + input [ 1:0] up_rx_sys_clk_sel_12, + input [ 2:0] up_rx_out_clk_sel_12, + input up_rx_enb_12, + input [11:0] up_rx_addr_12, + input up_rx_wr_12, + input [15:0] up_rx_wdata_12, + output [15:0] up_rx_rdata_12, + output up_rx_ready_12, + output up_tx_pll_locked_12, + input up_tx_rst_12, + input up_tx_user_ready_12, + output up_tx_rst_done_12, + output [ 1:0] up_tx_bufstatus_12, + input up_tx_prbsforceerr_12, + input [ 3:0] up_tx_prbssel_12, + input up_tx_lpm_dfe_n_12, + input [ 2:0] up_tx_rate_12, + input [ 1:0] up_tx_sys_clk_sel_12, + input [ 2:0] up_tx_out_clk_sel_12, + input [ 4:0] up_tx_diffctrl_12, + input [ 4:0] up_tx_postcursor_12, + input [ 4:0] up_tx_precursor_12, + input up_tx_enb_12, + input [11:0] up_tx_addr_12, + input up_tx_wr_12, + input [15:0] up_tx_wdata_12, + output [15:0] up_tx_rdata_12, + output up_tx_ready_12, + + input cpll_ref_clk_13, + input up_cpll_rst_13, + + input rx_13_p, + input rx_13_n, + output rx_out_clk_13, + output rx_out_clk_div2_13, + input rx_clk_13, + input rx_clk_2x_13, + output [DATA_PATH_WIDTH-1:0] rx_charisk_13, + output [DATA_PATH_WIDTH-1:0] rx_disperr_13, + output [DATA_PATH_WIDTH-1:0] rx_notintable_13, + output [DATA_PATH_WIDTH*8-1:0] rx_data_13, + input rx_calign_13, + output [1:0] rx_header_13, + output rx_block_sync_13, + + output tx_13_p, + output tx_13_n, + output tx_out_clk_13, + output tx_out_clk_div2_13, + input tx_clk_13, + input tx_clk_2x_13, + input [DATA_PATH_WIDTH-1:0] tx_charisk_13, + input [DATA_PATH_WIDTH*8-1:0] tx_data_13, + input [1:0] tx_header_13, + + input up_es_enb_13, + input [11:0] up_es_addr_13, + input up_es_wr_13, + input [15:0] up_es_wdata_13, + output [15:0] up_es_rdata_13, + output up_es_ready_13, + input up_es_reset_13, + output up_rx_pll_locked_13, + input up_rx_rst_13, + input up_rx_user_ready_13, + output up_rx_rst_done_13, + input [ 3:0] up_rx_prbssel_13, + input up_rx_prbscntreset_13, + output up_rx_prbserr_13, + output up_rx_prbslocked_13, + output [ 1:0] up_rx_bufstatus_13, + input up_rx_bufstatus_rst_13, + input up_rx_lpm_dfe_n_13, + input [ 2:0] up_rx_rate_13, + input [ 1:0] up_rx_sys_clk_sel_13, + input [ 2:0] up_rx_out_clk_sel_13, + input up_rx_enb_13, + input [11:0] up_rx_addr_13, + input up_rx_wr_13, + input [15:0] up_rx_wdata_13, + output [15:0] up_rx_rdata_13, + output up_rx_ready_13, + output up_tx_pll_locked_13, + input up_tx_rst_13, + input up_tx_user_ready_13, + output up_tx_rst_done_13, + output [ 1:0] up_tx_bufstatus_13, + input up_tx_prbsforceerr_13, + input [ 3:0] up_tx_prbssel_13, + input up_tx_lpm_dfe_n_13, + input [ 2:0] up_tx_rate_13, + input [ 1:0] up_tx_sys_clk_sel_13, + input [ 2:0] up_tx_out_clk_sel_13, + input [ 4:0] up_tx_diffctrl_13, + input [ 4:0] up_tx_postcursor_13, + input [ 4:0] up_tx_precursor_13, + input up_tx_enb_13, + input [11:0] up_tx_addr_13, + input up_tx_wr_13, + input [15:0] up_tx_wdata_13, + output [15:0] up_tx_rdata_13, + output up_tx_ready_13, + + input cpll_ref_clk_14, + input up_cpll_rst_14, + + input rx_14_p, + input rx_14_n, + output rx_out_clk_14, + output rx_out_clk_div2_14, + input rx_clk_14, + input rx_clk_2x_14, + output [DATA_PATH_WIDTH-1:0] rx_charisk_14, + output [DATA_PATH_WIDTH-1:0] rx_disperr_14, + output [DATA_PATH_WIDTH-1:0] rx_notintable_14, + output [DATA_PATH_WIDTH*8-1:0] rx_data_14, + input rx_calign_14, + output [1:0] rx_header_14, + output rx_block_sync_14, + + output tx_14_p, + output tx_14_n, + output tx_out_clk_14, + output tx_out_clk_div2_14, + input tx_clk_14, + input tx_clk_2x_14, + input [DATA_PATH_WIDTH-1:0] tx_charisk_14, + input [DATA_PATH_WIDTH*8-1:0] tx_data_14, + input [1:0] tx_header_14, + + input up_es_enb_14, + input [11:0] up_es_addr_14, + input up_es_wr_14, + input [15:0] up_es_wdata_14, + output [15:0] up_es_rdata_14, + output up_es_ready_14, + input up_es_reset_14, + output up_rx_pll_locked_14, + input up_rx_rst_14, + input up_rx_user_ready_14, + output up_rx_rst_done_14, + input [ 3:0] up_rx_prbssel_14, + input up_rx_prbscntreset_14, + output up_rx_prbserr_14, + output up_rx_prbslocked_14, + output [ 1:0] up_rx_bufstatus_14, + input up_rx_bufstatus_rst_14, + input up_rx_lpm_dfe_n_14, + input [ 2:0] up_rx_rate_14, + input [ 1:0] up_rx_sys_clk_sel_14, + input [ 2:0] up_rx_out_clk_sel_14, + input up_rx_enb_14, + input [11:0] up_rx_addr_14, + input up_rx_wr_14, + input [15:0] up_rx_wdata_14, + output [15:0] up_rx_rdata_14, + output up_rx_ready_14, + output up_tx_pll_locked_14, + input up_tx_rst_14, + input up_tx_user_ready_14, + output up_tx_rst_done_14, + output [ 1:0] up_tx_bufstatus_14, + input up_tx_prbsforceerr_14, + input [ 3:0] up_tx_prbssel_14, + input up_tx_lpm_dfe_n_14, + input [ 2:0] up_tx_rate_14, + input [ 1:0] up_tx_sys_clk_sel_14, + input [ 2:0] up_tx_out_clk_sel_14, + input [ 4:0] up_tx_diffctrl_14, + input [ 4:0] up_tx_postcursor_14, + input [ 4:0] up_tx_precursor_14, + input up_tx_enb_14, + input [11:0] up_tx_addr_14, + input up_tx_wr_14, + input [15:0] up_tx_wdata_14, + output [15:0] up_tx_rdata_14, + output up_tx_ready_14, + + input cpll_ref_clk_15, + input up_cpll_rst_15, + + input rx_15_p, + input rx_15_n, + output rx_out_clk_15, + output rx_out_clk_div2_15, + input rx_clk_15, + input rx_clk_2x_15, + output [DATA_PATH_WIDTH-1:0] rx_charisk_15, + output [DATA_PATH_WIDTH-1:0] rx_disperr_15, + output [DATA_PATH_WIDTH-1:0] rx_notintable_15, + output [DATA_PATH_WIDTH*8-1:0] rx_data_15, + input rx_calign_15, + output [1:0] rx_header_15, + output rx_block_sync_15, + + output tx_15_p, + output tx_15_n, + output tx_out_clk_15, + output tx_out_clk_div2_15, + input tx_clk_15, + input tx_clk_2x_15, + input [DATA_PATH_WIDTH-1:0] tx_charisk_15, + input [DATA_PATH_WIDTH*8-1:0] tx_data_15, + input [1:0] tx_header_15, + + input up_es_enb_15, + input [11:0] up_es_addr_15, + input up_es_wr_15, + input [15:0] up_es_wdata_15, + output [15:0] up_es_rdata_15, + output up_es_ready_15, + input up_es_reset_15, + output up_rx_pll_locked_15, + input up_rx_rst_15, + input up_rx_user_ready_15, + output up_rx_rst_done_15, + input [ 3:0] up_rx_prbssel_15, + input up_rx_prbscntreset_15, + output up_rx_prbserr_15, + output up_rx_prbslocked_15, + output [ 1:0] up_rx_bufstatus_15, + input up_rx_bufstatus_rst_15, + input up_rx_lpm_dfe_n_15, + input [ 2:0] up_rx_rate_15, + input [ 1:0] up_rx_sys_clk_sel_15, + input [ 2:0] up_rx_out_clk_sel_15, + input up_rx_enb_15, + input [11:0] up_rx_addr_15, + input up_rx_wr_15, + input [15:0] up_rx_wdata_15, + output [15:0] up_rx_rdata_15, + output up_rx_ready_15, + output up_tx_pll_locked_15, + input up_tx_rst_15, + input up_tx_user_ready_15, + output up_tx_rst_done_15, + output [ 1:0] up_tx_bufstatus_15, + input up_tx_prbsforceerr_15, + input [ 3:0] up_tx_prbssel_15, + input up_tx_lpm_dfe_n_15, + input [ 2:0] up_tx_rate_15, + input [ 1:0] up_tx_sys_clk_sel_15, + input [ 2:0] up_tx_out_clk_sel_15, + input [ 4:0] up_tx_diffctrl_15, + input [ 4:0] up_tx_postcursor_15, + input [ 4:0] up_tx_precursor_15, + input up_tx_enb_15, + input [11:0] up_tx_addr_15, + input up_tx_wr_15, + input [15:0] up_tx_wdata_15, + output [15:0] up_tx_rdata_15, + output up_tx_ready_15, + + input qpll_ref_clk_16, + input up_qpll_rst_16, + input cpll_ref_clk_16, + input up_cpll_rst_16, + + input rx_16_p, + input rx_16_n, + output rx_out_clk_16, + output rx_out_clk_div2_16, + input rx_clk_16, + input rx_clk_2x_16, + output [DATA_PATH_WIDTH-1:0] rx_charisk_16, + output [DATA_PATH_WIDTH-1:0] rx_disperr_16, + output [DATA_PATH_WIDTH-1:0] rx_notintable_16, + output [DATA_PATH_WIDTH*8-1:0] rx_data_16, + input rx_calign_16, + output [1:0] rx_header_16, + output rx_block_sync_16, + + output tx_16_p, + output tx_16_n, + output tx_out_clk_16, + output tx_out_clk_div2_16, + input tx_clk_16, + input tx_clk_2x_16, + input [DATA_PATH_WIDTH-1:0] tx_charisk_16, + input [DATA_PATH_WIDTH*8-1:0] tx_data_16, + input [1:0] tx_header_16, + + input up_cm_enb_16, + input [11:0] up_cm_addr_16, + input up_cm_wr_16, + input [15:0] up_cm_wdata_16, + output [15:0] up_cm_rdata_16, + output up_cm_ready_16, + input up_es_enb_16, + input [11:0] up_es_addr_16, + input up_es_wr_16, + input [15:0] up_es_wdata_16, + output [15:0] up_es_rdata_16, + output up_es_ready_16, + input up_es_reset_16, + output up_rx_pll_locked_16, + input up_rx_rst_16, + input up_rx_user_ready_16, + output up_rx_rst_done_16, + input [ 3:0] up_rx_prbssel_16, + input up_rx_prbscntreset_16, + output up_rx_prbserr_16, + output up_rx_prbslocked_16, + output [ 1:0] up_rx_bufstatus_16, + input up_rx_bufstatus_rst_16, + input up_rx_lpm_dfe_n_16, + input [ 2:0] up_rx_rate_16, + input [ 1:0] up_rx_sys_clk_sel_16, + input [ 2:0] up_rx_out_clk_sel_16, + input up_rx_enb_16, + input [11:0] up_rx_addr_16, + input up_rx_wr_16, + input [15:0] up_rx_wdata_16, + output [15:0] up_rx_rdata_16, + output up_rx_ready_16, + output up_tx_pll_locked_16, + input up_tx_rst_16, + input up_tx_user_ready_16, + output up_tx_rst_done_16, + output [ 1:0] up_tx_bufstatus_16, + input up_tx_prbsforceerr_16, + input [ 3:0] up_tx_prbssel_16, + input up_tx_lpm_dfe_n_16, + input [ 2:0] up_tx_rate_16, + input [ 1:0] up_tx_sys_clk_sel_16, + input [ 2:0] up_tx_out_clk_sel_16, + input [ 4:0] up_tx_diffctrl_16, + input [ 4:0] up_tx_postcursor_16, + input [ 4:0] up_tx_precursor_16, + input up_tx_enb_16, + input [11:0] up_tx_addr_16, + input up_tx_wr_16, + input [15:0] up_tx_wdata_16, + output [15:0] up_tx_rdata_16, + output up_tx_ready_16, + + input cpll_ref_clk_17, + input up_cpll_rst_17, + + input rx_17_p, + input rx_17_n, + output rx_out_clk_17, + output rx_out_clk_div2_17, + input rx_clk_17, + input rx_clk_2x_17, + output [DATA_PATH_WIDTH-1:0] rx_charisk_17, + output [DATA_PATH_WIDTH-1:0] rx_disperr_17, + output [DATA_PATH_WIDTH-1:0] rx_notintable_17, + output [DATA_PATH_WIDTH*8-1:0] rx_data_17, + input rx_calign_17, + output [1:0] rx_header_17, + output rx_block_sync_17, + + output tx_17_p, + output tx_17_n, + output tx_out_clk_17, + output tx_out_clk_div2_17, + input tx_clk_17, + input tx_clk_2x_17, + input [DATA_PATH_WIDTH-1:0] tx_charisk_17, + input [DATA_PATH_WIDTH*8-1:0] tx_data_17, + input [1:0] tx_header_17, + + input up_es_enb_17, + input [11:0] up_es_addr_17, + input up_es_wr_17, + input [15:0] up_es_wdata_17, + output [15:0] up_es_rdata_17, + output up_es_ready_17, + input up_es_reset_17, + output up_rx_pll_locked_17, + input up_rx_rst_17, + input up_rx_user_ready_17, + output up_rx_rst_done_17, + input [ 3:0] up_rx_prbssel_17, + input up_rx_prbscntreset_17, + output up_rx_prbserr_17, + output up_rx_prbslocked_17, + output [ 1:0] up_rx_bufstatus_17, + input up_rx_bufstatus_rst_17, + input up_rx_lpm_dfe_n_17, + input [ 2:0] up_rx_rate_17, + input [ 1:0] up_rx_sys_clk_sel_17, + input [ 2:0] up_rx_out_clk_sel_17, + input up_rx_enb_17, + input [11:0] up_rx_addr_17, + input up_rx_wr_17, + input [15:0] up_rx_wdata_17, + output [15:0] up_rx_rdata_17, + output up_rx_ready_17, + output up_tx_pll_locked_17, + input up_tx_rst_17, + input up_tx_user_ready_17, + output up_tx_rst_done_17, + output [ 1:0] up_tx_bufstatus_17, + input up_tx_prbsforceerr_17, + input [ 3:0] up_tx_prbssel_17, + input up_tx_lpm_dfe_n_17, + input [ 2:0] up_tx_rate_17, + input [ 1:0] up_tx_sys_clk_sel_17, + input [ 2:0] up_tx_out_clk_sel_17, + input [ 4:0] up_tx_diffctrl_17, + input [ 4:0] up_tx_postcursor_17, + input [ 4:0] up_tx_precursor_17, + input up_tx_enb_17, + input [11:0] up_tx_addr_17, + input up_tx_wr_17, + input [15:0] up_tx_wdata_17, + output [15:0] up_tx_rdata_17, + output up_tx_ready_17, + + input cpll_ref_clk_18, + input up_cpll_rst_18, + + input rx_18_p, + input rx_18_n, + output rx_out_clk_18, + output rx_out_clk_div2_18, + input rx_clk_18, + input rx_clk_2x_18, + output [DATA_PATH_WIDTH-1:0] rx_charisk_18, + output [DATA_PATH_WIDTH-1:0] rx_disperr_18, + output [DATA_PATH_WIDTH-1:0] rx_notintable_18, + output [DATA_PATH_WIDTH*8-1:0] rx_data_18, + input rx_calign_18, + output [1:0] rx_header_18, + output rx_block_sync_18, + + output tx_18_p, + output tx_18_n, + output tx_out_clk_18, + output tx_out_clk_div2_18, + input tx_clk_18, + input tx_clk_2x_18, + input [DATA_PATH_WIDTH-1:0] tx_charisk_18, + input [DATA_PATH_WIDTH*8-1:0] tx_data_18, + input [1:0] tx_header_18, + + input up_es_enb_18, + input [11:0] up_es_addr_18, + input up_es_wr_18, + input [15:0] up_es_wdata_18, + output [15:0] up_es_rdata_18, + output up_es_ready_18, + input up_es_reset_18, + output up_rx_pll_locked_18, + input up_rx_rst_18, + input up_rx_user_ready_18, + output up_rx_rst_done_18, + input [ 3:0] up_rx_prbssel_18, + input up_rx_prbscntreset_18, + output up_rx_prbserr_18, + output up_rx_prbslocked_18, + output [ 1:0] up_rx_bufstatus_18, + input up_rx_bufstatus_rst_18, + input up_rx_lpm_dfe_n_18, + input [ 2:0] up_rx_rate_18, + input [ 1:0] up_rx_sys_clk_sel_18, + input [ 2:0] up_rx_out_clk_sel_18, + input up_rx_enb_18, + input [11:0] up_rx_addr_18, + input up_rx_wr_18, + input [15:0] up_rx_wdata_18, + output [15:0] up_rx_rdata_18, + output up_rx_ready_18, + output up_tx_pll_locked_18, + input up_tx_rst_18, + input up_tx_user_ready_18, + output up_tx_rst_done_18, + output [ 1:0] up_tx_bufstatus_18, + input up_tx_prbsforceerr_18, + input [ 3:0] up_tx_prbssel_18, + input up_tx_lpm_dfe_n_18, + input [ 2:0] up_tx_rate_18, + input [ 1:0] up_tx_sys_clk_sel_18, + input [ 2:0] up_tx_out_clk_sel_18, + input [ 4:0] up_tx_diffctrl_18, + input [ 4:0] up_tx_postcursor_18, + input [ 4:0] up_tx_precursor_18, + input up_tx_enb_18, + input [11:0] up_tx_addr_18, + input up_tx_wr_18, + input [15:0] up_tx_wdata_18, + output [15:0] up_tx_rdata_18, + output up_tx_ready_18, + + input cpll_ref_clk_19, + input up_cpll_rst_19, + + input rx_19_p, + input rx_19_n, + output rx_out_clk_19, + output rx_out_clk_div2_19, + input rx_clk_19, + input rx_clk_2x_19, + output [DATA_PATH_WIDTH-1:0] rx_charisk_19, + output [DATA_PATH_WIDTH-1:0] rx_disperr_19, + output [DATA_PATH_WIDTH-1:0] rx_notintable_19, + output [DATA_PATH_WIDTH*8-1:0] rx_data_19, + input rx_calign_19, + output [1:0] rx_header_19, + output rx_block_sync_19, + + output tx_19_p, + output tx_19_n, + output tx_out_clk_19, + output tx_out_clk_div2_19, + input tx_clk_19, + input tx_clk_2x_19, + input [DATA_PATH_WIDTH-1:0] tx_charisk_19, + input [DATA_PATH_WIDTH*8-1:0] tx_data_19, + input [1:0] tx_header_19, + + input up_es_enb_19, + input [11:0] up_es_addr_19, + input up_es_wr_19, + input [15:0] up_es_wdata_19, + output [15:0] up_es_rdata_19, + output up_es_ready_19, + input up_es_reset_19, + output up_rx_pll_locked_19, + input up_rx_rst_19, + input up_rx_user_ready_19, + output up_rx_rst_done_19, + input [ 3:0] up_rx_prbssel_19, + input up_rx_prbscntreset_19, + output up_rx_prbserr_19, + output up_rx_prbslocked_19, + output [ 1:0] up_rx_bufstatus_19, + input up_rx_bufstatus_rst_19, + input up_rx_lpm_dfe_n_19, + input [ 2:0] up_rx_rate_19, + input [ 1:0] up_rx_sys_clk_sel_19, + input [ 2:0] up_rx_out_clk_sel_19, + input up_rx_enb_19, + input [11:0] up_rx_addr_19, + input up_rx_wr_19, + input [15:0] up_rx_wdata_19, + output [15:0] up_rx_rdata_19, + output up_rx_ready_19, + output up_tx_pll_locked_19, + input up_tx_rst_19, + input up_tx_user_ready_19, + output up_tx_rst_done_19, + output [ 1:0] up_tx_bufstatus_19, + input up_tx_prbsforceerr_19, + input [ 3:0] up_tx_prbssel_19, + input up_tx_lpm_dfe_n_19, + input [ 2:0] up_tx_rate_19, + input [ 1:0] up_tx_sys_clk_sel_19, + input [ 2:0] up_tx_out_clk_sel_19, + input [ 4:0] up_tx_diffctrl_19, + input [ 4:0] up_tx_postcursor_19, + input [ 4:0] up_tx_precursor_19, + input up_tx_enb_19, + input [11:0] up_tx_addr_19, + input up_tx_wr_19, + input [15:0] up_tx_wdata_19, + output [15:0] up_tx_rdata_19, + output up_tx_ready_19, + + input qpll_ref_clk_20, + input up_qpll_rst_20, + input cpll_ref_clk_20, + input up_cpll_rst_20, + + input rx_20_p, + input rx_20_n, + output rx_out_clk_20, + output rx_out_clk_div2_20, + input rx_clk_20, + input rx_clk_2x_20, + output [DATA_PATH_WIDTH-1:0] rx_charisk_20, + output [DATA_PATH_WIDTH-1:0] rx_disperr_20, + output [DATA_PATH_WIDTH-1:0] rx_notintable_20, + output [DATA_PATH_WIDTH*8-1:0] rx_data_20, + input rx_calign_20, + output [1:0] rx_header_20, + output rx_block_sync_20, + + output tx_20_p, + output tx_20_n, + output tx_out_clk_20, + output tx_out_clk_div2_20, + input tx_clk_20, + input tx_clk_2x_20, + input [DATA_PATH_WIDTH-1:0] tx_charisk_20, + input [DATA_PATH_WIDTH*8-1:0] tx_data_20, + input [1:0] tx_header_20, + + input up_cm_enb_20, + input [11:0] up_cm_addr_20, + input up_cm_wr_20, + input [15:0] up_cm_wdata_20, + output [15:0] up_cm_rdata_20, + output up_cm_ready_20, + input up_es_enb_20, + input [11:0] up_es_addr_20, + input up_es_wr_20, + input [15:0] up_es_wdata_20, + output [15:0] up_es_rdata_20, + output up_es_ready_20, + input up_es_reset_20, + output up_rx_pll_locked_20, + input up_rx_rst_20, + input up_rx_user_ready_20, + output up_rx_rst_done_20, + input [ 3:0] up_rx_prbssel_20, + input up_rx_prbscntreset_20, + output up_rx_prbserr_20, + output up_rx_prbslocked_20, + output [ 1:0] up_rx_bufstatus_20, + input up_rx_bufstatus_rst_20, + input up_rx_lpm_dfe_n_20, + input [ 2:0] up_rx_rate_20, + input [ 1:0] up_rx_sys_clk_sel_20, + input [ 2:0] up_rx_out_clk_sel_20, + input up_rx_enb_20, + input [11:0] up_rx_addr_20, + input up_rx_wr_20, + input [15:0] up_rx_wdata_20, + output [15:0] up_rx_rdata_20, + output up_rx_ready_20, + output up_tx_pll_locked_20, + input up_tx_rst_20, + input up_tx_user_ready_20, + output up_tx_rst_done_20, + output [ 1:0] up_tx_bufstatus_20, + input up_tx_prbsforceerr_20, + input [ 3:0] up_tx_prbssel_20, + input up_tx_lpm_dfe_n_20, + input [ 2:0] up_tx_rate_20, + input [ 1:0] up_tx_sys_clk_sel_20, + input [ 2:0] up_tx_out_clk_sel_20, + input [ 4:0] up_tx_diffctrl_20, + input [ 4:0] up_tx_postcursor_20, + input [ 4:0] up_tx_precursor_20, + input up_tx_enb_20, + input [11:0] up_tx_addr_20, + input up_tx_wr_20, + input [15:0] up_tx_wdata_20, + output [15:0] up_tx_rdata_20, + output up_tx_ready_20, + + input cpll_ref_clk_21, + input up_cpll_rst_21, + + input rx_21_p, + input rx_21_n, + output rx_out_clk_21, + output rx_out_clk_div2_21, + input rx_clk_21, + input rx_clk_2x_21, + output [DATA_PATH_WIDTH-1:0] rx_charisk_21, + output [DATA_PATH_WIDTH-1:0] rx_disperr_21, + output [DATA_PATH_WIDTH-1:0] rx_notintable_21, + output [DATA_PATH_WIDTH*8-1:0] rx_data_21, + input rx_calign_21, + output [1:0] rx_header_21, + output rx_block_sync_21, + + output tx_21_p, + output tx_21_n, + output tx_out_clk_21, + output tx_out_clk_div2_21, + input tx_clk_21, + input tx_clk_2x_21, + input [DATA_PATH_WIDTH-1:0] tx_charisk_21, + input [DATA_PATH_WIDTH*8-1:0] tx_data_21, + input [1:0] tx_header_21, + + input up_es_enb_21, + input [11:0] up_es_addr_21, + input up_es_wr_21, + input [15:0] up_es_wdata_21, + output [15:0] up_es_rdata_21, + output up_es_ready_21, + input up_es_reset_21, + output up_rx_pll_locked_21, + input up_rx_rst_21, + input up_rx_user_ready_21, + output up_rx_rst_done_21, + input [ 3:0] up_rx_prbssel_21, + input up_rx_prbscntreset_21, + output up_rx_prbserr_21, + output up_rx_prbslocked_21, + output [ 1:0] up_rx_bufstatus_21, + input up_rx_bufstatus_rst_21, + input up_rx_lpm_dfe_n_21, + input [ 2:0] up_rx_rate_21, + input [ 1:0] up_rx_sys_clk_sel_21, + input [ 2:0] up_rx_out_clk_sel_21, + input up_rx_enb_21, + input [11:0] up_rx_addr_21, + input up_rx_wr_21, + input [15:0] up_rx_wdata_21, + output [15:0] up_rx_rdata_21, + output up_rx_ready_21, + output up_tx_pll_locked_21, + input up_tx_rst_21, + input up_tx_user_ready_21, + output up_tx_rst_done_21, + output [ 1:0] up_tx_bufstatus_21, + input up_tx_prbsforceerr_21, + input [ 3:0] up_tx_prbssel_21, + input up_tx_lpm_dfe_n_21, + input [ 2:0] up_tx_rate_21, + input [ 1:0] up_tx_sys_clk_sel_21, + input [ 2:0] up_tx_out_clk_sel_21, + input [ 4:0] up_tx_diffctrl_21, + input [ 4:0] up_tx_postcursor_21, + input [ 4:0] up_tx_precursor_21, + input up_tx_enb_21, + input [11:0] up_tx_addr_21, + input up_tx_wr_21, + input [15:0] up_tx_wdata_21, + output [15:0] up_tx_rdata_21, + output up_tx_ready_21, + + input cpll_ref_clk_22, + input up_cpll_rst_22, + + input rx_22_p, + input rx_22_n, + output rx_out_clk_22, + output rx_out_clk_div2_22, + input rx_clk_22, + input rx_clk_2x_22, + output [DATA_PATH_WIDTH-1:0] rx_charisk_22, + output [DATA_PATH_WIDTH-1:0] rx_disperr_22, + output [DATA_PATH_WIDTH-1:0] rx_notintable_22, + output [DATA_PATH_WIDTH*8-1:0] rx_data_22, + input rx_calign_22, + output [1:0] rx_header_22, + output rx_block_sync_22, + + output tx_22_p, + output tx_22_n, + output tx_out_clk_22, + output tx_out_clk_div2_22, + input tx_clk_22, + input tx_clk_2x_22, + input [DATA_PATH_WIDTH-1:0] tx_charisk_22, + input [DATA_PATH_WIDTH*8-1:0] tx_data_22, + input [1:0] tx_header_22, + + input up_es_enb_22, + input [11:0] up_es_addr_22, + input up_es_wr_22, + input [15:0] up_es_wdata_22, + output [15:0] up_es_rdata_22, + output up_es_ready_22, + input up_es_reset_22, + output up_rx_pll_locked_22, + input up_rx_rst_22, + input up_rx_user_ready_22, + output up_rx_rst_done_22, + input [ 3:0] up_rx_prbssel_22, + input up_rx_prbscntreset_22, + output up_rx_prbserr_22, + output up_rx_prbslocked_22, + output [ 1:0] up_rx_bufstatus_22, + input up_rx_bufstatus_rst_22, + input up_rx_lpm_dfe_n_22, + input [ 2:0] up_rx_rate_22, + input [ 1:0] up_rx_sys_clk_sel_22, + input [ 2:0] up_rx_out_clk_sel_22, + input up_rx_enb_22, + input [11:0] up_rx_addr_22, + input up_rx_wr_22, + input [15:0] up_rx_wdata_22, + output [15:0] up_rx_rdata_22, + output up_rx_ready_22, + output up_tx_pll_locked_22, + input up_tx_rst_22, + input up_tx_user_ready_22, + output up_tx_rst_done_22, + output [ 1:0] up_tx_bufstatus_22, + input up_tx_prbsforceerr_22, + input [ 3:0] up_tx_prbssel_22, + input up_tx_lpm_dfe_n_22, + input [ 2:0] up_tx_rate_22, + input [ 1:0] up_tx_sys_clk_sel_22, + input [ 2:0] up_tx_out_clk_sel_22, + input [ 4:0] up_tx_diffctrl_22, + input [ 4:0] up_tx_postcursor_22, + input [ 4:0] up_tx_precursor_22, + input up_tx_enb_22, + input [11:0] up_tx_addr_22, + input up_tx_wr_22, + input [15:0] up_tx_wdata_22, + output [15:0] up_tx_rdata_22, + output up_tx_ready_22, + + input cpll_ref_clk_23, + input up_cpll_rst_23, + + input rx_23_p, + input rx_23_n, + output rx_out_clk_23, + output rx_out_clk_div2_23, + input rx_clk_23, + input rx_clk_2x_23, + output [DATA_PATH_WIDTH-1:0] rx_charisk_23, + output [DATA_PATH_WIDTH-1:0] rx_disperr_23, + output [DATA_PATH_WIDTH-1:0] rx_notintable_23, + output [DATA_PATH_WIDTH*8-1:0] rx_data_23, + input rx_calign_23, + output [1:0] rx_header_23, + output rx_block_sync_23, + + output tx_23_p, + output tx_23_n, + output tx_out_clk_23, + output tx_out_clk_div2_23, + input tx_clk_23, + input tx_clk_2x_23, + input [DATA_PATH_WIDTH-1:0] tx_charisk_23, + input [DATA_PATH_WIDTH*8-1:0] tx_data_23, + input [1:0] tx_header_23, + + input up_es_enb_23, + input [11:0] up_es_addr_23, + input up_es_wr_23, + input [15:0] up_es_wdata_23, + output [15:0] up_es_rdata_23, + output up_es_ready_23, + input up_es_reset_23, + output up_rx_pll_locked_23, + input up_rx_rst_23, + input up_rx_user_ready_23, + output up_rx_rst_done_23, + input [ 3:0] up_rx_prbssel_23, + input up_rx_prbscntreset_23, + output up_rx_prbserr_23, + output up_rx_prbslocked_23, + output [ 1:0] up_rx_bufstatus_23, + input up_rx_bufstatus_rst_23, + input up_rx_lpm_dfe_n_23, + input [ 2:0] up_rx_rate_23, + input [ 1:0] up_rx_sys_clk_sel_23, + input [ 2:0] up_rx_out_clk_sel_23, + input up_rx_enb_23, + input [11:0] up_rx_addr_23, + input up_rx_wr_23, + input [15:0] up_rx_wdata_23, + output [15:0] up_rx_rdata_23, + output up_rx_ready_23, + output up_tx_pll_locked_23, + input up_tx_rst_23, + input up_tx_user_ready_23, + output up_tx_rst_done_23, + output [ 1:0] up_tx_bufstatus_23, + input up_tx_prbsforceerr_23, + input [ 3:0] up_tx_prbssel_23, + input up_tx_lpm_dfe_n_23, + input [ 2:0] up_tx_rate_23, + input [ 1:0] up_tx_sys_clk_sel_23, + input [ 2:0] up_tx_out_clk_sel_23, + input [ 4:0] up_tx_diffctrl_23, + input [ 4:0] up_tx_postcursor_23, + input [ 4:0] up_tx_precursor_23, + input up_tx_enb_23, + input [11:0] up_tx_addr_23, + input up_tx_wr_23, + input [15:0] up_tx_wdata_23, + output [15:0] up_tx_rdata_23, + output up_tx_ready_23, + + input qpll_ref_clk_24, + input up_qpll_rst_24, + input cpll_ref_clk_24, + input up_cpll_rst_24, + + input rx_24_p, + input rx_24_n, + output rx_out_clk_24, + output rx_out_clk_div2_24, + input rx_clk_24, + input rx_clk_2x_24, + output [DATA_PATH_WIDTH-1:0] rx_charisk_24, + output [DATA_PATH_WIDTH-1:0] rx_disperr_24, + output [DATA_PATH_WIDTH-1:0] rx_notintable_24, + output [DATA_PATH_WIDTH*8-1:0] rx_data_24, + input rx_calign_24, + output [1:0] rx_header_24, + output rx_block_sync_24, + + output tx_24_p, + output tx_24_n, + output tx_out_clk_24, + output tx_out_clk_div2_24, + input tx_clk_24, + input tx_clk_2x_24, + input [DATA_PATH_WIDTH-1:0] tx_charisk_24, + input [DATA_PATH_WIDTH*8-1:0] tx_data_24, + input [1:0] tx_header_24, + + input up_cm_enb_24, + input [11:0] up_cm_addr_24, + input up_cm_wr_24, + input [15:0] up_cm_wdata_24, + output [15:0] up_cm_rdata_24, + output up_cm_ready_24, + input up_es_enb_24, + input [11:0] up_es_addr_24, + input up_es_wr_24, + input [15:0] up_es_wdata_24, + output [15:0] up_es_rdata_24, + output up_es_ready_24, + input up_es_reset_24, + output up_rx_pll_locked_24, + input up_rx_rst_24, + input up_rx_user_ready_24, + output up_rx_rst_done_24, + input [ 3:0] up_rx_prbssel_24, + input up_rx_prbscntreset_24, + output up_rx_prbserr_24, + output up_rx_prbslocked_24, + output [ 1:0] up_rx_bufstatus_24, + input up_rx_bufstatus_rst_24, + input up_rx_lpm_dfe_n_24, + input [ 2:0] up_rx_rate_24, + input [ 1:0] up_rx_sys_clk_sel_24, + input [ 2:0] up_rx_out_clk_sel_24, + input up_rx_enb_24, + input [11:0] up_rx_addr_24, + input up_rx_wr_24, + input [15:0] up_rx_wdata_24, + output [15:0] up_rx_rdata_24, + output up_rx_ready_24, + output up_tx_pll_locked_24, + input up_tx_rst_24, + input up_tx_user_ready_24, + output up_tx_rst_done_24, + output [ 1:0] up_tx_bufstatus_24, + input up_tx_prbsforceerr_24, + input [ 3:0] up_tx_prbssel_24, + input up_tx_lpm_dfe_n_24, + input [ 2:0] up_tx_rate_24, + input [ 1:0] up_tx_sys_clk_sel_24, + input [ 2:0] up_tx_out_clk_sel_24, + input [ 4:0] up_tx_diffctrl_24, + input [ 4:0] up_tx_postcursor_24, + input [ 4:0] up_tx_precursor_24, + input up_tx_enb_24, + input [11:0] up_tx_addr_24, + input up_tx_wr_24, + input [15:0] up_tx_wdata_24, + output [15:0] up_tx_rdata_24, + output up_tx_ready_24, + + input cpll_ref_clk_25, + input up_cpll_rst_25, + + input rx_25_p, + input rx_25_n, + output rx_out_clk_25, + output rx_out_clk_div2_25, + input rx_clk_25, + input rx_clk_2x_25, + output [DATA_PATH_WIDTH-1:0] rx_charisk_25, + output [DATA_PATH_WIDTH-1:0] rx_disperr_25, + output [DATA_PATH_WIDTH-1:0] rx_notintable_25, + output [DATA_PATH_WIDTH*8-1:0] rx_data_25, + input rx_calign_25, + output [1:0] rx_header_25, + output rx_block_sync_25, + + output tx_25_p, + output tx_25_n, + output tx_out_clk_25, + output tx_out_clk_div2_25, + input tx_clk_25, + input tx_clk_2x_25, + input [DATA_PATH_WIDTH-1:0] tx_charisk_25, + input [DATA_PATH_WIDTH*8-1:0] tx_data_25, + input [1:0] tx_header_25, + + input up_es_enb_25, + input [11:0] up_es_addr_25, + input up_es_wr_25, + input [15:0] up_es_wdata_25, + output [15:0] up_es_rdata_25, + output up_es_ready_25, + input up_es_reset_25, + output up_rx_pll_locked_25, + input up_rx_rst_25, + input up_rx_user_ready_25, + output up_rx_rst_done_25, + input [ 3:0] up_rx_prbssel_25, + input up_rx_prbscntreset_25, + output up_rx_prbserr_25, + output up_rx_prbslocked_25, + output [ 1:0] up_rx_bufstatus_25, + input up_rx_bufstatus_rst_25, + input up_rx_lpm_dfe_n_25, + input [ 2:0] up_rx_rate_25, + input [ 1:0] up_rx_sys_clk_sel_25, + input [ 2:0] up_rx_out_clk_sel_25, + input up_rx_enb_25, + input [11:0] up_rx_addr_25, + input up_rx_wr_25, + input [15:0] up_rx_wdata_25, + output [15:0] up_rx_rdata_25, + output up_rx_ready_25, + output up_tx_pll_locked_25, + input up_tx_rst_25, + input up_tx_user_ready_25, + output up_tx_rst_done_25, + output [ 1:0] up_tx_bufstatus_25, + input up_tx_prbsforceerr_25, + input [ 3:0] up_tx_prbssel_25, + input up_tx_lpm_dfe_n_25, + input [ 2:0] up_tx_rate_25, + input [ 1:0] up_tx_sys_clk_sel_25, + input [ 2:0] up_tx_out_clk_sel_25, + input [ 4:0] up_tx_diffctrl_25, + input [ 4:0] up_tx_postcursor_25, + input [ 4:0] up_tx_precursor_25, + input up_tx_enb_25, + input [11:0] up_tx_addr_25, + input up_tx_wr_25, + input [15:0] up_tx_wdata_25, + output [15:0] up_tx_rdata_25, + output up_tx_ready_25, + + input cpll_ref_clk_26, + input up_cpll_rst_26, + + input rx_26_p, + input rx_26_n, + output rx_out_clk_26, + output rx_out_clk_div2_26, + input rx_clk_26, + input rx_clk_2x_26, + output [DATA_PATH_WIDTH-1:0] rx_charisk_26, + output [DATA_PATH_WIDTH-1:0] rx_disperr_26, + output [DATA_PATH_WIDTH-1:0] rx_notintable_26, + output [DATA_PATH_WIDTH*8-1:0] rx_data_26, + input rx_calign_26, + output [1:0] rx_header_26, + output rx_block_sync_26, + + output tx_26_p, + output tx_26_n, + output tx_out_clk_26, + output tx_out_clk_div2_26, + input tx_clk_26, + input tx_clk_2x_26, + input [DATA_PATH_WIDTH-1:0] tx_charisk_26, + input [DATA_PATH_WIDTH*8-1:0] tx_data_26, + input [1:0] tx_header_26, + + input up_es_enb_26, + input [11:0] up_es_addr_26, + input up_es_wr_26, + input [15:0] up_es_wdata_26, + output [15:0] up_es_rdata_26, + output up_es_ready_26, + input up_es_reset_26, + output up_rx_pll_locked_26, + input up_rx_rst_26, + input up_rx_user_ready_26, + output up_rx_rst_done_26, + input [ 3:0] up_rx_prbssel_26, + input up_rx_prbscntreset_26, + output up_rx_prbserr_26, + output up_rx_prbslocked_26, + output [ 1:0] up_rx_bufstatus_26, + input up_rx_bufstatus_rst_26, + input up_rx_lpm_dfe_n_26, + input [ 2:0] up_rx_rate_26, + input [ 1:0] up_rx_sys_clk_sel_26, + input [ 2:0] up_rx_out_clk_sel_26, + input up_rx_enb_26, + input [11:0] up_rx_addr_26, + input up_rx_wr_26, + input [15:0] up_rx_wdata_26, + output [15:0] up_rx_rdata_26, + output up_rx_ready_26, + output up_tx_pll_locked_26, + input up_tx_rst_26, + input up_tx_user_ready_26, + output up_tx_rst_done_26, + output [ 1:0] up_tx_bufstatus_26, + input up_tx_prbsforceerr_26, + input [ 3:0] up_tx_prbssel_26, + input up_tx_lpm_dfe_n_26, + input [ 2:0] up_tx_rate_26, + input [ 1:0] up_tx_sys_clk_sel_26, + input [ 2:0] up_tx_out_clk_sel_26, + input [ 4:0] up_tx_diffctrl_26, + input [ 4:0] up_tx_postcursor_26, + input [ 4:0] up_tx_precursor_26, + input up_tx_enb_26, + input [11:0] up_tx_addr_26, + input up_tx_wr_26, + input [15:0] up_tx_wdata_26, + output [15:0] up_tx_rdata_26, + output up_tx_ready_26, + + input cpll_ref_clk_27, + input up_cpll_rst_27, + + input rx_27_p, + input rx_27_n, + output rx_out_clk_27, + output rx_out_clk_div2_27, + input rx_clk_27, + input rx_clk_2x_27, + output [DATA_PATH_WIDTH-1:0] rx_charisk_27, + output [DATA_PATH_WIDTH-1:0] rx_disperr_27, + output [DATA_PATH_WIDTH-1:0] rx_notintable_27, + output [DATA_PATH_WIDTH*8-1:0] rx_data_27, + input rx_calign_27, + output [1:0] rx_header_27, + output rx_block_sync_27, + + output tx_27_p, + output tx_27_n, + output tx_out_clk_27, + output tx_out_clk_div2_27, + input tx_clk_27, + input tx_clk_2x_27, + input [DATA_PATH_WIDTH-1:0] tx_charisk_27, + input [DATA_PATH_WIDTH*8-1:0] tx_data_27, + input [1:0] tx_header_27, + + input up_es_enb_27, + input [11:0] up_es_addr_27, + input up_es_wr_27, + input [15:0] up_es_wdata_27, + output [15:0] up_es_rdata_27, + output up_es_ready_27, + input up_es_reset_27, + output up_rx_pll_locked_27, + input up_rx_rst_27, + input up_rx_user_ready_27, + output up_rx_rst_done_27, + input [ 3:0] up_rx_prbssel_27, + input up_rx_prbscntreset_27, + output up_rx_prbserr_27, + output up_rx_prbslocked_27, + output [ 1:0] up_rx_bufstatus_27, + input up_rx_bufstatus_rst_27, + input up_rx_lpm_dfe_n_27, + input [ 2:0] up_rx_rate_27, + input [ 1:0] up_rx_sys_clk_sel_27, + input [ 2:0] up_rx_out_clk_sel_27, + input up_rx_enb_27, + input [11:0] up_rx_addr_27, + input up_rx_wr_27, + input [15:0] up_rx_wdata_27, + output [15:0] up_rx_rdata_27, + output up_rx_ready_27, + output up_tx_pll_locked_27, + input up_tx_rst_27, + input up_tx_user_ready_27, + output up_tx_rst_done_27, + output [ 1:0] up_tx_bufstatus_27, + input up_tx_prbsforceerr_27, + input [ 3:0] up_tx_prbssel_27, + input up_tx_lpm_dfe_n_27, + input [ 2:0] up_tx_rate_27, + input [ 1:0] up_tx_sys_clk_sel_27, + input [ 2:0] up_tx_out_clk_sel_27, + input [ 4:0] up_tx_diffctrl_27, + input [ 4:0] up_tx_postcursor_27, + input [ 4:0] up_tx_precursor_27, + input up_tx_enb_27, + input [11:0] up_tx_addr_27, + input up_tx_wr_27, + input [15:0] up_tx_wdata_27, + output [15:0] up_tx_rdata_27, + output up_tx_ready_27, + + input qpll_ref_clk_28, + input up_qpll_rst_28, + input cpll_ref_clk_28, + input up_cpll_rst_28, + + input rx_28_p, + input rx_28_n, + output rx_out_clk_28, + output rx_out_clk_div2_28, + input rx_clk_28, + input rx_clk_2x_28, + output [DATA_PATH_WIDTH-1:0] rx_charisk_28, + output [DATA_PATH_WIDTH-1:0] rx_disperr_28, + output [DATA_PATH_WIDTH-1:0] rx_notintable_28, + output [DATA_PATH_WIDTH*8-1:0] rx_data_28, + input rx_calign_28, + output [1:0] rx_header_28, + output rx_block_sync_28, + + output tx_28_p, + output tx_28_n, + output tx_out_clk_28, + output tx_out_clk_div2_28, + input tx_clk_28, + input tx_clk_2x_28, + input [DATA_PATH_WIDTH-1:0] tx_charisk_28, + input [DATA_PATH_WIDTH*8-1:0] tx_data_28, + input [1:0] tx_header_28, + + input up_cm_enb_28, + input [11:0] up_cm_addr_28, + input up_cm_wr_28, + input [15:0] up_cm_wdata_28, + output [15:0] up_cm_rdata_28, + output up_cm_ready_28, + input up_es_enb_28, + input [11:0] up_es_addr_28, + input up_es_wr_28, + input [15:0] up_es_wdata_28, + output [15:0] up_es_rdata_28, + output up_es_ready_28, + input up_es_reset_28, + output up_rx_pll_locked_28, + input up_rx_rst_28, + input up_rx_user_ready_28, + output up_rx_rst_done_28, + input [ 3:0] up_rx_prbssel_28, + input up_rx_prbscntreset_28, + output up_rx_prbserr_28, + output up_rx_prbslocked_28, + output [ 1:0] up_rx_bufstatus_28, + input up_rx_bufstatus_rst_28, + input up_rx_lpm_dfe_n_28, + input [ 2:0] up_rx_rate_28, + input [ 1:0] up_rx_sys_clk_sel_28, + input [ 2:0] up_rx_out_clk_sel_28, + input up_rx_enb_28, + input [11:0] up_rx_addr_28, + input up_rx_wr_28, + input [15:0] up_rx_wdata_28, + output [15:0] up_rx_rdata_28, + output up_rx_ready_28, + output up_tx_pll_locked_28, + input up_tx_rst_28, + input up_tx_user_ready_28, + output up_tx_rst_done_28, + output [ 1:0] up_tx_bufstatus_28, + input up_tx_prbsforceerr_28, + input [ 3:0] up_tx_prbssel_28, + input up_tx_lpm_dfe_n_28, + input [ 2:0] up_tx_rate_28, + input [ 1:0] up_tx_sys_clk_sel_28, + input [ 2:0] up_tx_out_clk_sel_28, + input [ 4:0] up_tx_diffctrl_28, + input [ 4:0] up_tx_postcursor_28, + input [ 4:0] up_tx_precursor_28, + input up_tx_enb_28, + input [11:0] up_tx_addr_28, + input up_tx_wr_28, + input [15:0] up_tx_wdata_28, + output [15:0] up_tx_rdata_28, + output up_tx_ready_28, + + input cpll_ref_clk_29, + input up_cpll_rst_29, + + input rx_29_p, + input rx_29_n, + output rx_out_clk_29, + output rx_out_clk_div2_29, + input rx_clk_29, + input rx_clk_2x_29, + output [DATA_PATH_WIDTH-1:0] rx_charisk_29, + output [DATA_PATH_WIDTH-1:0] rx_disperr_29, + output [DATA_PATH_WIDTH-1:0] rx_notintable_29, + output [DATA_PATH_WIDTH*8-1:0] rx_data_29, + input rx_calign_29, + output [1:0] rx_header_29, + output rx_block_sync_29, + + output tx_29_p, + output tx_29_n, + output tx_out_clk_29, + output tx_out_clk_div2_29, + input tx_clk_29, + input tx_clk_2x_29, + input [DATA_PATH_WIDTH-1:0] tx_charisk_29, + input [DATA_PATH_WIDTH*8-1:0] tx_data_29, + input [1:0] tx_header_29, + + input up_es_enb_29, + input [11:0] up_es_addr_29, + input up_es_wr_29, + input [15:0] up_es_wdata_29, + output [15:0] up_es_rdata_29, + output up_es_ready_29, + input up_es_reset_29, + output up_rx_pll_locked_29, + input up_rx_rst_29, + input up_rx_user_ready_29, + output up_rx_rst_done_29, + input [ 3:0] up_rx_prbssel_29, + input up_rx_prbscntreset_29, + output up_rx_prbserr_29, + output up_rx_prbslocked_29, + output [ 1:0] up_rx_bufstatus_29, + input up_rx_bufstatus_rst_29, + input up_rx_lpm_dfe_n_29, + input [ 2:0] up_rx_rate_29, + input [ 1:0] up_rx_sys_clk_sel_29, + input [ 2:0] up_rx_out_clk_sel_29, + input up_rx_enb_29, + input [11:0] up_rx_addr_29, + input up_rx_wr_29, + input [15:0] up_rx_wdata_29, + output [15:0] up_rx_rdata_29, + output up_rx_ready_29, + output up_tx_pll_locked_29, + input up_tx_rst_29, + input up_tx_user_ready_29, + output up_tx_rst_done_29, + output [ 1:0] up_tx_bufstatus_29, + input up_tx_prbsforceerr_29, + input [ 3:0] up_tx_prbssel_29, + input up_tx_lpm_dfe_n_29, + input [ 2:0] up_tx_rate_29, + input [ 1:0] up_tx_sys_clk_sel_29, + input [ 2:0] up_tx_out_clk_sel_29, + input [ 4:0] up_tx_diffctrl_29, + input [ 4:0] up_tx_postcursor_29, + input [ 4:0] up_tx_precursor_29, + input up_tx_enb_29, + input [11:0] up_tx_addr_29, + input up_tx_wr_29, + input [15:0] up_tx_wdata_29, + output [15:0] up_tx_rdata_29, + output up_tx_ready_29, + + input cpll_ref_clk_30, + input up_cpll_rst_30, + + input rx_30_p, + input rx_30_n, + output rx_out_clk_30, + output rx_out_clk_div2_30, + input rx_clk_30, + input rx_clk_2x_30, + output [DATA_PATH_WIDTH-1:0] rx_charisk_30, + output [DATA_PATH_WIDTH-1:0] rx_disperr_30, + output [DATA_PATH_WIDTH-1:0] rx_notintable_30, + output [DATA_PATH_WIDTH*8-1:0] rx_data_30, + input rx_calign_30, + output [1:0] rx_header_30, + output rx_block_sync_30, + + output tx_30_p, + output tx_30_n, + output tx_out_clk_30, + output tx_out_clk_div2_30, + input tx_clk_30, + input tx_clk_2x_30, + input [DATA_PATH_WIDTH-1:0] tx_charisk_30, + input [DATA_PATH_WIDTH*8-1:0] tx_data_30, + input [1:0] tx_header_30, + + input up_es_enb_30, + input [11:0] up_es_addr_30, + input up_es_wr_30, + input [15:0] up_es_wdata_30, + output [15:0] up_es_rdata_30, + output up_es_ready_30, + input up_es_reset_30, + output up_rx_pll_locked_30, + input up_rx_rst_30, + input up_rx_user_ready_30, + output up_rx_rst_done_30, + input [ 3:0] up_rx_prbssel_30, + input up_rx_prbscntreset_30, + output up_rx_prbserr_30, + output up_rx_prbslocked_30, + output [ 1:0] up_rx_bufstatus_30, + input up_rx_bufstatus_rst_30, + input up_rx_lpm_dfe_n_30, + input [ 2:0] up_rx_rate_30, + input [ 1:0] up_rx_sys_clk_sel_30, + input [ 2:0] up_rx_out_clk_sel_30, + input up_rx_enb_30, + input [11:0] up_rx_addr_30, + input up_rx_wr_30, + input [15:0] up_rx_wdata_30, + output [15:0] up_rx_rdata_30, + output up_rx_ready_30, + output up_tx_pll_locked_30, + input up_tx_rst_30, + input up_tx_user_ready_30, + output up_tx_rst_done_30, + output [ 1:0] up_tx_bufstatus_30, + input up_tx_prbsforceerr_30, + input [ 3:0] up_tx_prbssel_30, + input up_tx_lpm_dfe_n_30, + input [ 2:0] up_tx_rate_30, + input [ 1:0] up_tx_sys_clk_sel_30, + input [ 2:0] up_tx_out_clk_sel_30, + input [ 4:0] up_tx_diffctrl_30, + input [ 4:0] up_tx_postcursor_30, + input [ 4:0] up_tx_precursor_30, + input up_tx_enb_30, + input [11:0] up_tx_addr_30, + input up_tx_wr_30, + input [15:0] up_tx_wdata_30, + output [15:0] up_tx_rdata_30, + output up_tx_ready_30, + + input cpll_ref_clk_31, + input up_cpll_rst_31, + + input rx_31_p, + input rx_31_n, + output rx_out_clk_31, + output rx_out_clk_div2_31, + input rx_clk_31, + input rx_clk_2x_31, + output [DATA_PATH_WIDTH-1:0] rx_charisk_31, + output [DATA_PATH_WIDTH-1:0] rx_disperr_31, + output [DATA_PATH_WIDTH-1:0] rx_notintable_31, + output [DATA_PATH_WIDTH*8-1:0] rx_data_31, + input rx_calign_31, + output [1:0] rx_header_31, + output rx_block_sync_31, + + output tx_31_p, + output tx_31_n, + output tx_out_clk_31, + output tx_out_clk_div2_31, + input tx_clk_31, + input tx_clk_2x_31, + input [DATA_PATH_WIDTH-1:0] tx_charisk_31, + input [DATA_PATH_WIDTH*8-1:0] tx_data_31, + input [1:0] tx_header_31, + + input up_es_enb_31, + input [11:0] up_es_addr_31, + input up_es_wr_31, + input [15:0] up_es_wdata_31, + output [15:0] up_es_rdata_31, + output up_es_ready_31, + input up_es_reset_31, + output up_rx_pll_locked_31, + input up_rx_rst_31, + input up_rx_user_ready_31, + output up_rx_rst_done_31, + input [ 3:0] up_rx_prbssel_31, + input up_rx_prbscntreset_31, + output up_rx_prbserr_31, + output up_rx_prbslocked_31, + output [ 1:0] up_rx_bufstatus_31, + input up_rx_bufstatus_rst_31, + input up_rx_lpm_dfe_n_31, + input [ 2:0] up_rx_rate_31, + input [ 1:0] up_rx_sys_clk_sel_31, + input [ 2:0] up_rx_out_clk_sel_31, + input up_rx_enb_31, + input [11:0] up_rx_addr_31, + input up_rx_wr_31, + input [15:0] up_rx_wdata_31, + output [15:0] up_rx_rdata_31, + output up_rx_ready_31, + output up_tx_pll_locked_31, + input up_tx_rst_31, + input up_tx_user_ready_31, + output up_tx_rst_done_31, + output [ 1:0] up_tx_bufstatus_31, + input up_tx_prbsforceerr_31, + input [ 3:0] up_tx_prbssel_31, + input up_tx_lpm_dfe_n_31, + input [ 2:0] up_tx_rate_31, + input [ 1:0] up_tx_sys_clk_sel_31, + input [ 2:0] up_tx_out_clk_sel_31, + input [ 4:0] up_tx_diffctrl_31, + input [ 4:0] up_tx_postcursor_31, + input [ 4:0] up_tx_precursor_31, + input up_tx_enb_31, + input [11:0] up_tx_addr_31, + input up_tx_wr_31, + input [15:0] up_tx_wdata_31, + output [15:0] up_tx_rdata_31, + output up_tx_ready_31 +); + + // parameters + + localparam integer NUM_OF_LANES = (TX_NUM_OF_LANES > RX_NUM_OF_LANES) ? + TX_NUM_OF_LANES : RX_NUM_OF_LANES; + + // internal signals + + wire qpll2ch_clk_0; + wire qpll2ch_ref_clk_0; + wire qpll2ch_locked_0; + wire qpll1_clk_0; + wire qpll1_ref_clk_0; + wire qpll1_locked_0; + wire [ 1:0] sys_clk_sel_0; + wire qpll_sel_0; + wire qpll2ch_clk_4; + wire qpll2ch_ref_clk_4; + wire qpll2ch_locked_4; + wire qpll1_clk_4; + wire qpll1_ref_clk_4; + wire qpll1_locked_4; + wire [ 1:0] sys_clk_sel_4; + wire qpll_sel_4; + wire qpll2ch_clk_8; + wire qpll2ch_ref_clk_8; + wire qpll2ch_locked_8; + wire qpll1_clk_8; + wire qpll1_ref_clk_8; + wire qpll1_locked_8; + wire [ 1:0] sys_clk_sel_8; + wire qpll_sel_8; + wire qpll2ch_clk_12; + wire qpll2ch_ref_clk_12; + wire qpll2ch_locked_12; + wire qpll1_clk_12; + wire qpll1_ref_clk_12; + wire qpll1_locked_12; + wire [ 1:0] sys_clk_sel_12; + wire qpll_sel_12; + wire qpll2ch_clk_16; + wire qpll2ch_ref_clk_16; + wire qpll2ch_locked_16; + wire qpll1_clk_16; + wire qpll1_ref_clk_16; + wire qpll1_locked_16; + wire [ 1:0] sys_clk_sel_16; + wire qpll_sel_16; + wire qpll2ch_clk_20; + wire qpll2ch_ref_clk_20; + wire qpll2ch_locked_20; + wire qpll1_clk_20; + wire qpll1_ref_clk_20; + wire qpll1_locked_20; + wire [ 1:0] sys_clk_sel_20; + wire qpll_sel_20; + wire qpll2ch_clk_24; + wire qpll2ch_ref_clk_24; + wire qpll2ch_locked_24; + wire qpll1_clk_24; + wire qpll1_ref_clk_24; + wire qpll1_locked_24; + wire [ 1:0] sys_clk_sel_24; + wire qpll_sel_24; + wire qpll2ch_clk_28; + wire qpll2ch_ref_clk_28; + wire qpll2ch_locked_28; + wire qpll1_clk_28; + wire qpll1_ref_clk_28; + wire qpll1_locked_28; + wire [ 1:0] sys_clk_sel_28; + wire qpll_sel_28; + + assign sys_clk_sel_0 = up_tx_sys_clk_sel_0 | up_tx_sys_clk_sel_1 | up_tx_sys_clk_sel_2 | up_tx_sys_clk_sel_3 | + up_rx_sys_clk_sel_0 | up_rx_sys_clk_sel_1 | up_rx_sys_clk_sel_2 | up_rx_sys_clk_sel_3; + assign qpll_sel_0 = sys_clk_sel_0 == 2'd3 ? 0 : 1; + assign sys_clk_sel_4 = up_tx_sys_clk_sel_4 | up_tx_sys_clk_sel_5 | up_tx_sys_clk_sel_6 | up_tx_sys_clk_sel_7 | + up_rx_sys_clk_sel_4 | up_rx_sys_clk_sel_5 | up_rx_sys_clk_sel_6 | up_rx_sys_clk_sel_7; + assign qpll_sel_4 = sys_clk_sel_4 == 2'd3 ? 0 : 1; + assign sys_clk_sel_8 = up_tx_sys_clk_sel_8 | up_tx_sys_clk_sel_9 | up_tx_sys_clk_sel_10 | up_tx_sys_clk_sel_11 | + up_rx_sys_clk_sel_8 | up_rx_sys_clk_sel_9 | up_rx_sys_clk_sel_10 | up_rx_sys_clk_sel_11; + assign qpll_sel_8 = sys_clk_sel_8 == 2'd3 ? 0 : 1; + assign sys_clk_sel_12 = up_tx_sys_clk_sel_12 | up_tx_sys_clk_sel_13 | up_tx_sys_clk_sel_14 | up_tx_sys_clk_sel_15 | + up_rx_sys_clk_sel_12 | up_rx_sys_clk_sel_13 | up_rx_sys_clk_sel_14 | up_rx_sys_clk_sel_15; + assign qpll_sel_12 = sys_clk_sel_12 == 2'd3 ? 0 : 1; + assign sys_clk_sel_16 = up_tx_sys_clk_sel_16 | up_tx_sys_clk_sel_17 | up_tx_sys_clk_sel_18 | up_tx_sys_clk_sel_19 | + up_rx_sys_clk_sel_16 | up_rx_sys_clk_sel_17 | up_rx_sys_clk_sel_18 | up_rx_sys_clk_sel_19; + assign qpll_sel_16 = sys_clk_sel_16 == 2'd3 ? 0 : 1; + assign sys_clk_sel_20 = up_tx_sys_clk_sel_20 | up_tx_sys_clk_sel_21 | up_tx_sys_clk_sel_22 | up_tx_sys_clk_sel_23 | + up_rx_sys_clk_sel_20 | up_rx_sys_clk_sel_21 | up_rx_sys_clk_sel_22 | up_rx_sys_clk_sel_23; + assign qpll_sel_20 = sys_clk_sel_20 == 2'd3 ? 0 : 1; + assign sys_clk_sel_24 = up_tx_sys_clk_sel_24 | up_tx_sys_clk_sel_25 | up_tx_sys_clk_sel_26 | up_tx_sys_clk_sel_27 | + up_rx_sys_clk_sel_24 | up_rx_sys_clk_sel_25 | up_rx_sys_clk_sel_26 | up_rx_sys_clk_sel_27; + assign qpll_sel_24 = sys_clk_sel_24 == 2'd3 ? 0 : 1; + assign sys_clk_sel_28 = up_tx_sys_clk_sel_28 | up_tx_sys_clk_sel_29 | up_tx_sys_clk_sel_30 | up_tx_sys_clk_sel_31 | + up_rx_sys_clk_sel_28 | up_rx_sys_clk_sel_29 | up_rx_sys_clk_sel_30 | up_rx_sys_clk_sel_31; + assign qpll_sel_28 = sys_clk_sel_28 == 2'd3 ? 0 : 1; + + // instantiations + + generate + if (NUM_OF_LANES >= 1) begin + util_adxcvr_xcm #( + .XCVR_TYPE (XCVR_TYPE), + .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .POR_CFG (POR_CFG), + .PPF0_CFG (PPF0_CFG), + .PPF1_CFG (PPF1_CFG), + .QPLL_CFG (QPLL_CFG), + .QPLL_FBDIV (QPLL_FBDIV), + .QPLL_CFG0 (QPLL_CFG0), + .QPLL_CFG1 (QPLL_CFG1), + .QPLL_CFG1_G3 (QPLL_CFG1_G3), + .QPLL_CFG2 (QPLL_CFG2), + .QPLL_CFG2_G3 (QPLL_CFG2_G3), + .QPLL_CFG3 (QPLL_CFG3), + .QPLL_CP_G3 (QPLL_CP_G3), + .QPLL_LPF (QPLL_LPF), + .QPLL_CP (QPLL_CP), + .QPLL_CFG4 (QPLL_CFG4) + ) i_xcm_0 ( + .qpll_ref_clk (qpll_ref_clk_0), + .qpll_sel (qpll_sel_0), + .qpll2ch_clk (qpll2ch_clk_0), + .qpll2ch_ref_clk (qpll2ch_ref_clk_0), + .qpll2ch_locked (qpll2ch_locked_0), + .qpll1_clk (qpll1_clk_0), + .qpll1_ref_clk (qpll1_ref_clk_0), + .qpll1_locked (qpll1_locked_0), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_qpll_rst (up_qpll_rst_0), + .up_cm_enb (up_cm_enb_0), + .up_cm_addr (up_cm_addr_0), + .up_cm_wr (up_cm_wr_0), + .up_cm_wdata (up_cm_wdata_0), + .up_cm_rdata (up_cm_rdata_0), + .up_cm_ready (up_cm_ready_0)); + end else begin + assign qpll2ch_clk_0 = 1'd0; + assign qpll2ch_ref_clk_0 = 1'd0; + assign qpll2ch_locked_0 = 1'd0; + assign qpll1_clk_0 = 1'd0; + assign qpll1_ref_clk_0 = 1'd0; + assign qpll1_locked_0 = 1'd0; + assign up_cm_rdata_0 = 16'd0; + assign up_cm_ready_0 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 1) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 0) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 0) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_0 ( + .qpll2ch_clk (qpll2ch_clk_0), + .qpll2ch_ref_clk (qpll2ch_ref_clk_0), + .qpll2ch_locked (qpll2ch_locked_0), + .qpll1_clk (qpll1_clk_0), + .qpll1_ref_clk (qpll1_ref_clk_0), + .qpll1_locked (qpll1_locked_0), + .cpll_ref_clk (cpll_ref_clk_0), + .up_cpll_rst (up_cpll_rst_0), + .rx_p (rx_0_p), + .rx_n (rx_0_n), + .rx_out_clk (rx_out_clk_0), + .rx_out_clk_div2 (rx_out_clk_div2_0), + .rx_clk (rx_clk_0), + .rx_clk_2x (rx_clk_2x_0), + .rx_charisk (rx_charisk_0), + .rx_disperr (rx_disperr_0), + .rx_notintable (rx_notintable_0), + .rx_data (rx_data_0), + .rx_calign (rx_calign_0), + .rx_header(rx_header_0), + .rx_block_sync(rx_block_sync_0), + .tx_p (tx_0_p), + .tx_n (tx_0_n), + .tx_out_clk (tx_out_clk_0), + .tx_out_clk_div2 (tx_out_clk_div2_0), + .tx_clk (tx_clk_0), + .tx_clk_2x (tx_clk_2x_0), + .tx_charisk (tx_charisk_0), + .tx_data (tx_data_0), + .tx_header (tx_header_0), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_0), + .up_es_addr (up_es_addr_0), + .up_es_wr (up_es_wr_0), + .up_es_wdata (up_es_wdata_0), + .up_es_rdata (up_es_rdata_0), + .up_es_ready (up_es_ready_0), + .up_es_reset (up_es_reset_0), + .up_rx_pll_locked (up_rx_pll_locked_0), + .up_rx_rst (up_rx_rst_0), + .up_rx_user_ready (up_rx_user_ready_0), + .up_rx_rst_done (up_rx_rst_done_0), + .up_rx_prbssel (up_rx_prbssel_0), + .up_rx_prbscntreset (up_rx_prbscntreset_0), + .up_rx_prbserr (up_rx_prbserr_0), + .up_rx_prbslocked (up_rx_prbslocked_0), + .up_rx_bufstatus (up_rx_bufstatus_0), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_0), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_0), + .up_rx_rate (up_rx_rate_0), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_0), + .up_rx_out_clk_sel (up_rx_out_clk_sel_0), + .up_rx_enb (up_rx_enb_0), + .up_rx_addr (up_rx_addr_0), + .up_rx_wr (up_rx_wr_0), + .up_rx_wdata (up_rx_wdata_0), + .up_rx_rdata (up_rx_rdata_0), + .up_rx_ready (up_rx_ready_0), + .up_tx_pll_locked (up_tx_pll_locked_0), + .up_tx_rst (up_tx_rst_0), + .up_tx_user_ready (up_tx_user_ready_0), + .up_tx_rst_done (up_tx_rst_done_0), + .up_tx_bufstatus (up_tx_bufstatus_0), + .up_tx_prbsforceerr (up_tx_prbsforceerr_0), + .up_tx_prbssel (up_tx_prbssel_0), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_0), + .up_tx_rate (up_tx_rate_0), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_0), + .up_tx_out_clk_sel (up_tx_out_clk_sel_0), + .up_tx_diffctrl (up_tx_diffctrl_0), + .up_tx_postcursor (up_tx_postcursor_0), + .up_tx_precursor (up_tx_precursor_0), + .up_tx_enb (up_tx_enb_0), + .up_tx_addr (up_tx_addr_0), + .up_tx_wr (up_tx_wr_0), + .up_tx_wdata (up_tx_wdata_0), + .up_tx_rdata (up_tx_rdata_0), + .up_tx_ready (up_tx_ready_0)); + end else begin + assign rx_out_clk_0 = 1'd0; + assign rx_charisk_0 = 4'd0; + assign rx_disperr_0 = 4'd0; + assign rx_notintable_0 = 4'd0; + assign rx_data_0 = 32'd0; + assign tx_0_p = 1'd0; + assign tx_0_n = 1'd0; + assign tx_out_clk_0 = 1'd0; + assign up_es_rdata_0 = 16'd0; + assign up_es_ready_0 = 1'd0; + assign up_rx_pll_locked_0 = 1'd0; + assign up_rx_rst_done_0 = 1'd0; + assign up_rx_rdata_0 = 16'd0; + assign up_rx_ready_0 = 1'd0; + assign up_tx_pll_locked_0 = 1'd0; + assign up_tx_rst_done_0 = 1'd0; + assign up_tx_rdata_0 = 16'd0; + assign up_tx_ready_0 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 2) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 1) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 1) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_1 ( + .qpll2ch_clk (qpll2ch_clk_0), + .qpll2ch_ref_clk (qpll2ch_ref_clk_0), + .qpll2ch_locked (qpll2ch_locked_0), + .qpll1_clk (qpll1_clk_0), + .qpll1_ref_clk (qpll1_ref_clk_0), + .qpll1_locked (qpll1_locked_0), + .cpll_ref_clk (cpll_ref_clk_1), + .up_cpll_rst (up_cpll_rst_1), + .rx_p (rx_1_p), + .rx_n (rx_1_n), + .rx_out_clk (rx_out_clk_1), + .rx_out_clk_div2 (rx_out_clk_div2_1), + .rx_clk (rx_clk_1), + .rx_clk_2x (rx_clk_2x_1), + .rx_charisk (rx_charisk_1), + .rx_disperr (rx_disperr_1), + .rx_notintable (rx_notintable_1), + .rx_data (rx_data_1), + .rx_calign (rx_calign_1), + .rx_header(rx_header_1), + .rx_block_sync(rx_block_sync_1), + .tx_p (tx_1_p), + .tx_n (tx_1_n), + .tx_out_clk (tx_out_clk_1), + .tx_out_clk_div2 (tx_out_clk_div2_1), + .tx_clk (tx_clk_1), + .tx_clk_2x (tx_clk_2x_1), + .tx_charisk (tx_charisk_1), + .tx_data (tx_data_1), + .tx_header (tx_header_1), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_1), + .up_es_addr (up_es_addr_1), + .up_es_wr (up_es_wr_1), + .up_es_wdata (up_es_wdata_1), + .up_es_rdata (up_es_rdata_1), + .up_es_ready (up_es_ready_1), + .up_es_reset (up_es_reset_1), + .up_rx_pll_locked (up_rx_pll_locked_1), + .up_rx_rst (up_rx_rst_1), + .up_rx_user_ready (up_rx_user_ready_1), + .up_rx_rst_done (up_rx_rst_done_1), + .up_rx_prbssel (up_rx_prbssel_1), + .up_rx_prbscntreset (up_rx_prbscntreset_1), + .up_rx_prbserr (up_rx_prbserr_1), + .up_rx_prbslocked (up_rx_prbslocked_1), + .up_rx_bufstatus (up_rx_bufstatus_1), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_1), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_1), + .up_rx_rate (up_rx_rate_1), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_1), + .up_rx_out_clk_sel (up_rx_out_clk_sel_1), + .up_rx_enb (up_rx_enb_1), + .up_rx_addr (up_rx_addr_1), + .up_rx_wr (up_rx_wr_1), + .up_rx_wdata (up_rx_wdata_1), + .up_rx_rdata (up_rx_rdata_1), + .up_rx_ready (up_rx_ready_1), + .up_tx_pll_locked (up_tx_pll_locked_1), + .up_tx_rst (up_tx_rst_1), + .up_tx_user_ready (up_tx_user_ready_1), + .up_tx_rst_done (up_tx_rst_done_1), + .up_tx_bufstatus (up_tx_bufstatus_1), + .up_tx_prbsforceerr (up_tx_prbsforceerr_1), + .up_tx_prbssel (up_tx_prbssel_1), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_1), + .up_tx_rate (up_tx_rate_1), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_1), + .up_tx_out_clk_sel (up_tx_out_clk_sel_1), + .up_tx_diffctrl (up_tx_diffctrl_1), + .up_tx_postcursor (up_tx_postcursor_1), + .up_tx_precursor (up_tx_precursor_1), + .up_tx_enb (up_tx_enb_1), + .up_tx_addr (up_tx_addr_1), + .up_tx_wr (up_tx_wr_1), + .up_tx_wdata (up_tx_wdata_1), + .up_tx_rdata (up_tx_rdata_1), + .up_tx_ready (up_tx_ready_1)); + end else begin + assign rx_out_clk_1 = 1'd0; + assign rx_charisk_1 = 4'd0; + assign rx_disperr_1 = 4'd0; + assign rx_notintable_1 = 4'd0; + assign rx_data_1 = 32'd0; + assign tx_1_p = 1'd0; + assign tx_1_n = 1'd0; + assign tx_out_clk_1 = 1'd0; + assign up_es_rdata_1 = 16'd0; + assign up_es_ready_1 = 1'd0; + assign up_rx_pll_locked_1 = 1'd0; + assign up_rx_rst_done_1 = 1'd0; + assign up_rx_rdata_1 = 16'd0; + assign up_rx_ready_1 = 1'd0; + assign up_tx_pll_locked_1 = 1'd0; + assign up_tx_rst_done_1 = 1'd0; + assign up_tx_rdata_1 = 16'd0; + assign up_tx_ready_1 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 3) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 2) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 2) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_2 ( + .qpll2ch_clk (qpll2ch_clk_0), + .qpll2ch_ref_clk (qpll2ch_ref_clk_0), + .qpll2ch_locked (qpll2ch_locked_0), + .qpll1_clk (qpll1_clk_0), + .qpll1_ref_clk (qpll1_ref_clk_0), + .qpll1_locked (qpll1_locked_0), + .cpll_ref_clk (cpll_ref_clk_2), + .up_cpll_rst (up_cpll_rst_2), + .rx_p (rx_2_p), + .rx_n (rx_2_n), + .rx_out_clk (rx_out_clk_2), + .rx_out_clk_div2 (rx_out_clk_div2_2), + .rx_clk (rx_clk_2), + .rx_clk_2x (rx_clk_2x_2), + .rx_charisk (rx_charisk_2), + .rx_disperr (rx_disperr_2), + .rx_notintable (rx_notintable_2), + .rx_data (rx_data_2), + .rx_calign (rx_calign_2), + .rx_header(rx_header_2), + .rx_block_sync(rx_block_sync_2), + .tx_p (tx_2_p), + .tx_n (tx_2_n), + .tx_out_clk (tx_out_clk_2), + .tx_out_clk_div2 (tx_out_clk_div2_2), + .tx_clk (tx_clk_2), + .tx_clk_2x (tx_clk_2x_2), + .tx_charisk (tx_charisk_2), + .tx_data (tx_data_2), + .tx_header (tx_header_2), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_2), + .up_es_addr (up_es_addr_2), + .up_es_wr (up_es_wr_2), + .up_es_wdata (up_es_wdata_2), + .up_es_rdata (up_es_rdata_2), + .up_es_ready (up_es_ready_2), + .up_es_reset (up_es_reset_2), + .up_rx_pll_locked (up_rx_pll_locked_2), + .up_rx_rst (up_rx_rst_2), + .up_rx_user_ready (up_rx_user_ready_2), + .up_rx_rst_done (up_rx_rst_done_2), + .up_rx_prbssel (up_rx_prbssel_2), + .up_rx_prbscntreset (up_rx_prbscntreset_2), + .up_rx_prbserr (up_rx_prbserr_2), + .up_rx_prbslocked (up_rx_prbslocked_2), + .up_rx_bufstatus (up_rx_bufstatus_2), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_2), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_2), + .up_rx_rate (up_rx_rate_2), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_2), + .up_rx_out_clk_sel (up_rx_out_clk_sel_2), + .up_rx_enb (up_rx_enb_2), + .up_rx_addr (up_rx_addr_2), + .up_rx_wr (up_rx_wr_2), + .up_rx_wdata (up_rx_wdata_2), + .up_rx_rdata (up_rx_rdata_2), + .up_rx_ready (up_rx_ready_2), + .up_tx_pll_locked (up_tx_pll_locked_2), + .up_tx_rst (up_tx_rst_2), + .up_tx_user_ready (up_tx_user_ready_2), + .up_tx_rst_done (up_tx_rst_done_2), + .up_tx_bufstatus (up_tx_bufstatus_2), + .up_tx_prbsforceerr (up_tx_prbsforceerr_2), + .up_tx_prbssel (up_tx_prbssel_2), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_2), + .up_tx_rate (up_tx_rate_2), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_2), + .up_tx_out_clk_sel (up_tx_out_clk_sel_2), + .up_tx_diffctrl (up_tx_diffctrl_2), + .up_tx_postcursor (up_tx_postcursor_2), + .up_tx_precursor (up_tx_precursor_2), + .up_tx_enb (up_tx_enb_2), + .up_tx_addr (up_tx_addr_2), + .up_tx_wr (up_tx_wr_2), + .up_tx_wdata (up_tx_wdata_2), + .up_tx_rdata (up_tx_rdata_2), + .up_tx_ready (up_tx_ready_2)); + end else begin + assign rx_out_clk_2 = 1'd0; + assign rx_charisk_2 = 4'd0; + assign rx_disperr_2 = 4'd0; + assign rx_notintable_2 = 4'd0; + assign rx_data_2 = 32'd0; + assign tx_2_p = 1'd0; + assign tx_2_n = 1'd0; + assign tx_out_clk_2 = 1'd0; + assign up_es_rdata_2 = 16'd0; + assign up_es_ready_2 = 1'd0; + assign up_rx_pll_locked_2 = 1'd0; + assign up_rx_rst_done_2 = 1'd0; + assign up_rx_rdata_2 = 16'd0; + assign up_rx_ready_2 = 1'd0; + assign up_tx_pll_locked_2 = 1'd0; + assign up_tx_rst_done_2 = 1'd0; + assign up_tx_rdata_2 = 16'd0; + assign up_tx_ready_2 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 4) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 3) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 3) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_3 ( + .qpll2ch_clk (qpll2ch_clk_0), + .qpll2ch_ref_clk (qpll2ch_ref_clk_0), + .qpll2ch_locked (qpll2ch_locked_0), + .qpll1_clk (qpll1_clk_0), + .qpll1_ref_clk (qpll1_ref_clk_0), + .qpll1_locked (qpll1_locked_0), + .cpll_ref_clk (cpll_ref_clk_3), + .up_cpll_rst (up_cpll_rst_3), + .rx_p (rx_3_p), + .rx_n (rx_3_n), + .rx_out_clk (rx_out_clk_3), + .rx_out_clk_div2 (rx_out_clk_div2_3), + .rx_clk (rx_clk_3), + .rx_clk_2x (rx_clk_2x_3), + .rx_charisk (rx_charisk_3), + .rx_disperr (rx_disperr_3), + .rx_notintable (rx_notintable_3), + .rx_data (rx_data_3), + .rx_calign (rx_calign_3), + .rx_header(rx_header_3), + .rx_block_sync(rx_block_sync_3), + .tx_p (tx_3_p), + .tx_n (tx_3_n), + .tx_out_clk (tx_out_clk_3), + .tx_out_clk_div2 (tx_out_clk_div2_3), + .tx_clk (tx_clk_3), + .tx_clk_2x (tx_clk_2x_3), + .tx_charisk (tx_charisk_3), + .tx_data (tx_data_3), + .tx_header (tx_header_3), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_3), + .up_es_addr (up_es_addr_3), + .up_es_wr (up_es_wr_3), + .up_es_wdata (up_es_wdata_3), + .up_es_rdata (up_es_rdata_3), + .up_es_ready (up_es_ready_3), + .up_es_reset (up_es_reset_3), + .up_rx_pll_locked (up_rx_pll_locked_3), + .up_rx_rst (up_rx_rst_3), + .up_rx_user_ready (up_rx_user_ready_3), + .up_rx_rst_done (up_rx_rst_done_3), + .up_rx_prbssel (up_rx_prbssel_3), + .up_rx_prbscntreset (up_rx_prbscntreset_3), + .up_rx_prbserr (up_rx_prbserr_3), + .up_rx_prbslocked (up_rx_prbslocked_3), + .up_rx_bufstatus (up_rx_bufstatus_3), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_3), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_3), + .up_rx_rate (up_rx_rate_3), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_3), + .up_rx_out_clk_sel (up_rx_out_clk_sel_3), + .up_rx_enb (up_rx_enb_3), + .up_rx_addr (up_rx_addr_3), + .up_rx_wr (up_rx_wr_3), + .up_rx_wdata (up_rx_wdata_3), + .up_rx_rdata (up_rx_rdata_3), + .up_rx_ready (up_rx_ready_3), + .up_tx_pll_locked (up_tx_pll_locked_3), + .up_tx_rst (up_tx_rst_3), + .up_tx_user_ready (up_tx_user_ready_3), + .up_tx_rst_done (up_tx_rst_done_3), + .up_tx_bufstatus (up_tx_bufstatus_3), + .up_tx_prbsforceerr (up_tx_prbsforceerr_3), + .up_tx_prbssel (up_tx_prbssel_3), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_3), + .up_tx_rate (up_tx_rate_3), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_3), + .up_tx_out_clk_sel (up_tx_out_clk_sel_3), + .up_tx_diffctrl (up_tx_diffctrl_3), + .up_tx_postcursor (up_tx_postcursor_3), + .up_tx_precursor (up_tx_precursor_3), + .up_tx_enb (up_tx_enb_3), + .up_tx_addr (up_tx_addr_3), + .up_tx_wr (up_tx_wr_3), + .up_tx_wdata (up_tx_wdata_3), + .up_tx_rdata (up_tx_rdata_3), + .up_tx_ready (up_tx_ready_3)); + end else begin + assign rx_out_clk_3 = 1'd0; + assign rx_charisk_3 = 4'd0; + assign rx_disperr_3 = 4'd0; + assign rx_notintable_3 = 4'd0; + assign rx_data_3 = 32'd0; + assign tx_3_p = 1'd0; + assign tx_3_n = 1'd0; + assign tx_out_clk_3 = 1'd0; + assign up_es_rdata_3 = 16'd0; + assign up_es_ready_3 = 1'd0; + assign up_rx_pll_locked_3 = 1'd0; + assign up_rx_rst_done_3 = 1'd0; + assign up_rx_rdata_3 = 16'd0; + assign up_rx_ready_3 = 1'd0; + assign up_tx_pll_locked_3 = 1'd0; + assign up_tx_rst_done_3 = 1'd0; + assign up_tx_rdata_3 = 16'd0; + assign up_tx_ready_3 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 5) begin + util_adxcvr_xcm #( + .XCVR_TYPE (XCVR_TYPE), + .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .POR_CFG (POR_CFG), + .PPF0_CFG (PPF0_CFG), + .PPF1_CFG (PPF1_CFG), + .QPLL_CFG (QPLL_CFG), + .QPLL_FBDIV (QPLL_FBDIV), + .QPLL_CFG0 (QPLL_CFG0), + .QPLL_CFG1 (QPLL_CFG1), + .QPLL_CFG1_G3 (QPLL_CFG1_G3), + .QPLL_CFG2 (QPLL_CFG2), + .QPLL_CFG2_G3 (QPLL_CFG2_G3), + .QPLL_CFG3 (QPLL_CFG3), + .QPLL_CP_G3 (QPLL_CP_G3), + .QPLL_LPF (QPLL_LPF), + .QPLL_CP (QPLL_CP), + .QPLL_CFG4 (QPLL_CFG4) + ) i_xcm_4 ( + .qpll_ref_clk (qpll_ref_clk_4), + .qpll_sel (qpll_sel_4), + .qpll2ch_clk (qpll2ch_clk_4), + .qpll2ch_ref_clk (qpll2ch_ref_clk_4), + .qpll2ch_locked (qpll2ch_locked_4), + .qpll1_clk (qpll1_clk_4), + .qpll1_ref_clk (qpll1_ref_clk_4), + .qpll1_locked (qpll1_locked_4), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_qpll_rst (up_qpll_rst_4), + .up_cm_enb (up_cm_enb_4), + .up_cm_addr (up_cm_addr_4), + .up_cm_wr (up_cm_wr_4), + .up_cm_wdata (up_cm_wdata_4), + .up_cm_rdata (up_cm_rdata_4), + .up_cm_ready (up_cm_ready_4)); + end else begin + assign qpll2ch_clk_4 = 1'd0; + assign qpll2ch_ref_clk_4 = 1'd0; + assign qpll2ch_locked_4 = 1'd0; + assign qpll1_clk_4 = 1'd0; + assign qpll1_ref_clk_4 = 1'd0; + assign qpll1_locked_4 = 1'd0; + assign up_cm_rdata_4 = 16'd0; + assign up_cm_ready_4 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 5) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 4) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 4) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_4 ( + .qpll2ch_clk (qpll2ch_clk_4), + .qpll2ch_ref_clk (qpll2ch_ref_clk_4), + .qpll2ch_locked (qpll2ch_locked_4), + .qpll1_clk (qpll1_clk_4), + .qpll1_ref_clk (qpll1_ref_clk_4), + .qpll1_locked (qpll1_locked_4), + .cpll_ref_clk (cpll_ref_clk_4), + .up_cpll_rst (up_cpll_rst_4), + .rx_p (rx_4_p), + .rx_n (rx_4_n), + .rx_out_clk (rx_out_clk_4), + .rx_out_clk_div2 (rx_out_clk_div2_4), + .rx_clk (rx_clk_4), + .rx_clk_2x (rx_clk_2x_4), + .rx_charisk (rx_charisk_4), + .rx_disperr (rx_disperr_4), + .rx_notintable (rx_notintable_4), + .rx_data (rx_data_4), + .rx_calign (rx_calign_4), + .rx_header(rx_header_4), + .rx_block_sync(rx_block_sync_4), + .tx_p (tx_4_p), + .tx_n (tx_4_n), + .tx_out_clk (tx_out_clk_4), + .tx_out_clk_div2 (tx_out_clk_div2_4), + .tx_clk (tx_clk_4), + .tx_clk_2x (tx_clk_2x_4), + .tx_charisk (tx_charisk_4), + .tx_data (tx_data_4), + .tx_header (tx_header_4), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_4), + .up_es_addr (up_es_addr_4), + .up_es_wr (up_es_wr_4), + .up_es_wdata (up_es_wdata_4), + .up_es_rdata (up_es_rdata_4), + .up_es_ready (up_es_ready_4), + .up_es_reset (up_es_reset_4), + .up_rx_pll_locked (up_rx_pll_locked_4), + .up_rx_rst (up_rx_rst_4), + .up_rx_user_ready (up_rx_user_ready_4), + .up_rx_rst_done (up_rx_rst_done_4), + .up_rx_prbssel (up_rx_prbssel_4), + .up_rx_prbscntreset (up_rx_prbscntreset_4), + .up_rx_prbserr (up_rx_prbserr_4), + .up_rx_prbslocked (up_rx_prbslocked_4), + .up_rx_bufstatus (up_rx_bufstatus_4), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_4), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_4), + .up_rx_rate (up_rx_rate_4), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_4), + .up_rx_out_clk_sel (up_rx_out_clk_sel_4), + .up_rx_enb (up_rx_enb_4), + .up_rx_addr (up_rx_addr_4), + .up_rx_wr (up_rx_wr_4), + .up_rx_wdata (up_rx_wdata_4), + .up_rx_rdata (up_rx_rdata_4), + .up_rx_ready (up_rx_ready_4), + .up_tx_pll_locked (up_tx_pll_locked_4), + .up_tx_rst (up_tx_rst_4), + .up_tx_user_ready (up_tx_user_ready_4), + .up_tx_rst_done (up_tx_rst_done_4), + .up_tx_bufstatus (up_tx_bufstatus_4), + .up_tx_prbsforceerr (up_tx_prbsforceerr_4), + .up_tx_prbssel (up_tx_prbssel_4), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_4), + .up_tx_rate (up_tx_rate_4), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_4), + .up_tx_out_clk_sel (up_tx_out_clk_sel_4), + .up_tx_diffctrl (up_tx_diffctrl_4), + .up_tx_postcursor (up_tx_postcursor_4), + .up_tx_precursor (up_tx_precursor_4), + .up_tx_enb (up_tx_enb_4), + .up_tx_addr (up_tx_addr_4), + .up_tx_wr (up_tx_wr_4), + .up_tx_wdata (up_tx_wdata_4), + .up_tx_rdata (up_tx_rdata_4), + .up_tx_ready (up_tx_ready_4)); + end else begin + assign rx_out_clk_4 = 1'd0; + assign rx_charisk_4 = 4'd0; + assign rx_disperr_4 = 4'd0; + assign rx_notintable_4 = 4'd0; + assign rx_data_4 = 32'd0; + assign tx_4_p = 1'd0; + assign tx_4_n = 1'd0; + assign tx_out_clk_4 = 1'd0; + assign up_es_rdata_4 = 16'd0; + assign up_es_ready_4 = 1'd0; + assign up_rx_pll_locked_4 = 1'd0; + assign up_rx_rst_done_4 = 1'd0; + assign up_rx_rdata_4 = 16'd0; + assign up_rx_ready_4 = 1'd0; + assign up_tx_pll_locked_4 = 1'd0; + assign up_tx_rst_done_4 = 1'd0; + assign up_tx_rdata_4 = 16'd0; + assign up_tx_ready_4 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 6) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 5) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 5) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_5 ( + .qpll2ch_clk (qpll2ch_clk_4), + .qpll2ch_ref_clk (qpll2ch_ref_clk_4), + .qpll2ch_locked (qpll2ch_locked_4), + .qpll1_clk (qpll1_clk_4), + .qpll1_ref_clk (qpll1_ref_clk_4), + .qpll1_locked (qpll1_locked_4), + .cpll_ref_clk (cpll_ref_clk_5), + .up_cpll_rst (up_cpll_rst_5), + .rx_p (rx_5_p), + .rx_n (rx_5_n), + .rx_out_clk (rx_out_clk_5), + .rx_out_clk_div2 (rx_out_clk_div2_5), + .rx_clk (rx_clk_5), + .rx_clk_2x (rx_clk_2x_5), + .rx_charisk (rx_charisk_5), + .rx_disperr (rx_disperr_5), + .rx_notintable (rx_notintable_5), + .rx_data (rx_data_5), + .rx_calign (rx_calign_5), + .rx_header(rx_header_5), + .rx_block_sync(rx_block_sync_5), + .tx_p (tx_5_p), + .tx_n (tx_5_n), + .tx_out_clk (tx_out_clk_5), + .tx_out_clk_div2 (tx_out_clk_div2_5), + .tx_clk (tx_clk_5), + .tx_clk_2x (tx_clk_2x_5), + .tx_charisk (tx_charisk_5), + .tx_data (tx_data_5), + .tx_header (tx_header_5), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_5), + .up_es_addr (up_es_addr_5), + .up_es_wr (up_es_wr_5), + .up_es_wdata (up_es_wdata_5), + .up_es_rdata (up_es_rdata_5), + .up_es_ready (up_es_ready_5), + .up_es_reset (up_es_reset_5), + .up_rx_pll_locked (up_rx_pll_locked_5), + .up_rx_rst (up_rx_rst_5), + .up_rx_user_ready (up_rx_user_ready_5), + .up_rx_rst_done (up_rx_rst_done_5), + .up_rx_prbssel (up_rx_prbssel_5), + .up_rx_prbscntreset (up_rx_prbscntreset_5), + .up_rx_prbserr (up_rx_prbserr_5), + .up_rx_prbslocked (up_rx_prbslocked_5), + .up_rx_bufstatus (up_rx_bufstatus_5), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_5), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_5), + .up_rx_rate (up_rx_rate_5), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_5), + .up_rx_out_clk_sel (up_rx_out_clk_sel_5), + .up_rx_enb (up_rx_enb_5), + .up_rx_addr (up_rx_addr_5), + .up_rx_wr (up_rx_wr_5), + .up_rx_wdata (up_rx_wdata_5), + .up_rx_rdata (up_rx_rdata_5), + .up_rx_ready (up_rx_ready_5), + .up_tx_pll_locked (up_tx_pll_locked_5), + .up_tx_rst (up_tx_rst_5), + .up_tx_user_ready (up_tx_user_ready_5), + .up_tx_rst_done (up_tx_rst_done_5), + .up_tx_bufstatus (up_tx_bufstatus_5), + .up_tx_prbsforceerr (up_tx_prbsforceerr_5), + .up_tx_prbssel (up_tx_prbssel_5), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_5), + .up_tx_rate (up_tx_rate_5), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_5), + .up_tx_out_clk_sel (up_tx_out_clk_sel_5), + .up_tx_diffctrl (up_tx_diffctrl_5), + .up_tx_postcursor (up_tx_postcursor_5), + .up_tx_precursor (up_tx_precursor_5), + .up_tx_enb (up_tx_enb_5), + .up_tx_addr (up_tx_addr_5), + .up_tx_wr (up_tx_wr_5), + .up_tx_wdata (up_tx_wdata_5), + .up_tx_rdata (up_tx_rdata_5), + .up_tx_ready (up_tx_ready_5)); + end else begin + assign rx_out_clk_5 = 1'd0; + assign rx_charisk_5 = 4'd0; + assign rx_disperr_5 = 4'd0; + assign rx_notintable_5 = 4'd0; + assign rx_data_5 = 32'd0; + assign tx_5_p = 1'd0; + assign tx_5_n = 1'd0; + assign tx_out_clk_5 = 1'd0; + assign up_es_rdata_5 = 16'd0; + assign up_es_ready_5 = 1'd0; + assign up_rx_pll_locked_5 = 1'd0; + assign up_rx_rst_done_5 = 1'd0; + assign up_rx_rdata_5 = 16'd0; + assign up_rx_ready_5 = 1'd0; + assign up_tx_pll_locked_5 = 1'd0; + assign up_tx_rst_done_5 = 1'd0; + assign up_tx_rdata_5 = 16'd0; + assign up_tx_ready_5 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 7) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 6) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 6) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_6 ( + .qpll2ch_clk (qpll2ch_clk_4), + .qpll2ch_ref_clk (qpll2ch_ref_clk_4), + .qpll2ch_locked (qpll2ch_locked_4), + .qpll1_clk (qpll1_clk_4), + .qpll1_ref_clk (qpll1_ref_clk_4), + .qpll1_locked (qpll1_locked_4), + .cpll_ref_clk (cpll_ref_clk_6), + .up_cpll_rst (up_cpll_rst_6), + .rx_p (rx_6_p), + .rx_n (rx_6_n), + .rx_out_clk (rx_out_clk_6), + .rx_out_clk_div2 (rx_out_clk_div2_6), + .rx_clk (rx_clk_6), + .rx_clk_2x (rx_clk_2x_6), + .rx_charisk (rx_charisk_6), + .rx_disperr (rx_disperr_6), + .rx_notintable (rx_notintable_6), + .rx_data (rx_data_6), + .rx_calign (rx_calign_6), + .rx_header(rx_header_6), + .rx_block_sync(rx_block_sync_6), + .tx_p (tx_6_p), + .tx_n (tx_6_n), + .tx_out_clk (tx_out_clk_6), + .tx_out_clk_div2 (tx_out_clk_div2_6), + .tx_clk (tx_clk_6), + .tx_clk_2x (tx_clk_2x_6), + .tx_charisk (tx_charisk_6), + .tx_data (tx_data_6), + .tx_header (tx_header_6), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_6), + .up_es_addr (up_es_addr_6), + .up_es_wr (up_es_wr_6), + .up_es_wdata (up_es_wdata_6), + .up_es_rdata (up_es_rdata_6), + .up_es_ready (up_es_ready_6), + .up_es_reset (up_es_reset_6), + .up_rx_pll_locked (up_rx_pll_locked_6), + .up_rx_rst (up_rx_rst_6), + .up_rx_user_ready (up_rx_user_ready_6), + .up_rx_rst_done (up_rx_rst_done_6), + .up_rx_prbssel (up_rx_prbssel_6), + .up_rx_prbscntreset (up_rx_prbscntreset_6), + .up_rx_prbserr (up_rx_prbserr_6), + .up_rx_prbslocked (up_rx_prbslocked_6), + .up_rx_bufstatus (up_rx_bufstatus_6), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_6), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_6), + .up_rx_rate (up_rx_rate_6), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_6), + .up_rx_out_clk_sel (up_rx_out_clk_sel_6), + .up_rx_enb (up_rx_enb_6), + .up_rx_addr (up_rx_addr_6), + .up_rx_wr (up_rx_wr_6), + .up_rx_wdata (up_rx_wdata_6), + .up_rx_rdata (up_rx_rdata_6), + .up_rx_ready (up_rx_ready_6), + .up_tx_pll_locked (up_tx_pll_locked_6), + .up_tx_rst (up_tx_rst_6), + .up_tx_user_ready (up_tx_user_ready_6), + .up_tx_rst_done (up_tx_rst_done_6), + .up_tx_bufstatus (up_tx_bufstatus_6), + .up_tx_prbsforceerr (up_tx_prbsforceerr_6), + .up_tx_prbssel (up_tx_prbssel_6), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_6), + .up_tx_rate (up_tx_rate_6), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_6), + .up_tx_out_clk_sel (up_tx_out_clk_sel_6), + .up_tx_diffctrl (up_tx_diffctrl_6), + .up_tx_postcursor (up_tx_postcursor_6), + .up_tx_precursor (up_tx_precursor_6), + .up_tx_enb (up_tx_enb_6), + .up_tx_addr (up_tx_addr_6), + .up_tx_wr (up_tx_wr_6), + .up_tx_wdata (up_tx_wdata_6), + .up_tx_rdata (up_tx_rdata_6), + .up_tx_ready (up_tx_ready_6)); + end else begin + assign rx_out_clk_6 = 1'd0; + assign rx_charisk_6 = 4'd0; + assign rx_disperr_6 = 4'd0; + assign rx_notintable_6 = 4'd0; + assign rx_data_6 = 32'd0; + assign tx_6_p = 1'd0; + assign tx_6_n = 1'd0; + assign tx_out_clk_6 = 1'd0; + assign up_es_rdata_6 = 16'd0; + assign up_es_ready_6 = 1'd0; + assign up_rx_pll_locked_6 = 1'd0; + assign up_rx_rst_done_6 = 1'd0; + assign up_rx_rdata_6 = 16'd0; + assign up_rx_ready_6 = 1'd0; + assign up_tx_pll_locked_6 = 1'd0; + assign up_tx_rst_done_6 = 1'd0; + assign up_tx_rdata_6 = 16'd0; + assign up_tx_ready_6 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 8) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 7) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 7) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_7 ( + .qpll2ch_clk (qpll2ch_clk_4), + .qpll2ch_ref_clk (qpll2ch_ref_clk_4), + .qpll2ch_locked (qpll2ch_locked_4), + .qpll1_clk (qpll1_clk_4), + .qpll1_ref_clk (qpll1_ref_clk_4), + .qpll1_locked (qpll1_locked_4), + .cpll_ref_clk (cpll_ref_clk_7), + .up_cpll_rst (up_cpll_rst_7), + .rx_p (rx_7_p), + .rx_n (rx_7_n), + .rx_out_clk (rx_out_clk_7), + .rx_out_clk_div2 (rx_out_clk_div2_7), + .rx_clk (rx_clk_7), + .rx_clk_2x (rx_clk_2x_7), + .rx_charisk (rx_charisk_7), + .rx_disperr (rx_disperr_7), + .rx_notintable (rx_notintable_7), + .rx_data (rx_data_7), + .rx_calign (rx_calign_7), + .rx_header(rx_header_7), + .rx_block_sync(rx_block_sync_7), + .tx_p (tx_7_p), + .tx_n (tx_7_n), + .tx_out_clk (tx_out_clk_7), + .tx_out_clk_div2 (tx_out_clk_div2_7), + .tx_clk (tx_clk_7), + .tx_clk_2x (tx_clk_2x_7), + .tx_charisk (tx_charisk_7), + .tx_data (tx_data_7), + .tx_header (tx_header_7), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_7), + .up_es_addr (up_es_addr_7), + .up_es_wr (up_es_wr_7), + .up_es_wdata (up_es_wdata_7), + .up_es_rdata (up_es_rdata_7), + .up_es_ready (up_es_ready_7), + .up_es_reset (up_es_reset_7), + .up_rx_pll_locked (up_rx_pll_locked_7), + .up_rx_rst (up_rx_rst_7), + .up_rx_user_ready (up_rx_user_ready_7), + .up_rx_rst_done (up_rx_rst_done_7), + .up_rx_prbssel (up_rx_prbssel_7), + .up_rx_prbscntreset (up_rx_prbscntreset_7), + .up_rx_prbserr (up_rx_prbserr_7), + .up_rx_prbslocked (up_rx_prbslocked_7), + .up_rx_bufstatus (up_rx_bufstatus_7), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_7), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_7), + .up_rx_rate (up_rx_rate_7), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_7), + .up_rx_out_clk_sel (up_rx_out_clk_sel_7), + .up_rx_enb (up_rx_enb_7), + .up_rx_addr (up_rx_addr_7), + .up_rx_wr (up_rx_wr_7), + .up_rx_wdata (up_rx_wdata_7), + .up_rx_rdata (up_rx_rdata_7), + .up_rx_ready (up_rx_ready_7), + .up_tx_pll_locked (up_tx_pll_locked_7), + .up_tx_rst (up_tx_rst_7), + .up_tx_user_ready (up_tx_user_ready_7), + .up_tx_rst_done (up_tx_rst_done_7), + .up_tx_bufstatus (up_tx_bufstatus_7), + .up_tx_prbsforceerr (up_tx_prbsforceerr_7), + .up_tx_prbssel (up_tx_prbssel_7), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_7), + .up_tx_rate (up_tx_rate_7), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_7), + .up_tx_out_clk_sel (up_tx_out_clk_sel_7), + .up_tx_diffctrl (up_tx_diffctrl_7), + .up_tx_postcursor (up_tx_postcursor_7), + .up_tx_precursor (up_tx_precursor_7), + .up_tx_enb (up_tx_enb_7), + .up_tx_addr (up_tx_addr_7), + .up_tx_wr (up_tx_wr_7), + .up_tx_wdata (up_tx_wdata_7), + .up_tx_rdata (up_tx_rdata_7), + .up_tx_ready (up_tx_ready_7)); + end else begin + assign rx_out_clk_7 = 1'd0; + assign rx_charisk_7 = 4'd0; + assign rx_disperr_7 = 4'd0; + assign rx_notintable_7 = 4'd0; + assign rx_data_7 = 32'd0; + assign tx_7_p = 1'd0; + assign tx_7_n = 1'd0; + assign tx_out_clk_7 = 1'd0; + assign up_es_rdata_7 = 16'd0; + assign up_es_ready_7 = 1'd0; + assign up_rx_pll_locked_7 = 1'd0; + assign up_rx_rst_done_7 = 1'd0; + assign up_rx_rdata_7 = 16'd0; + assign up_rx_ready_7 = 1'd0; + assign up_tx_pll_locked_7 = 1'd0; + assign up_tx_rst_done_7 = 1'd0; + assign up_tx_rdata_7 = 16'd0; + assign up_tx_ready_7 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 9) begin + util_adxcvr_xcm #( + .XCVR_TYPE (XCVR_TYPE), + .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .POR_CFG (POR_CFG), + .PPF0_CFG (PPF0_CFG), + .PPF1_CFG (PPF1_CFG), + .QPLL_CFG (QPLL_CFG), + .QPLL_FBDIV (QPLL_FBDIV), + .QPLL_CFG0 (QPLL_CFG0), + .QPLL_CFG1 (QPLL_CFG1), + .QPLL_CFG1_G3 (QPLL_CFG1_G3), + .QPLL_CFG2 (QPLL_CFG2), + .QPLL_CFG2_G3 (QPLL_CFG2_G3), + .QPLL_CFG3 (QPLL_CFG3), + .QPLL_CP_G3 (QPLL_CP_G3), + .QPLL_LPF (QPLL_LPF), + .QPLL_CP (QPLL_CP), + .QPLL_CFG4 (QPLL_CFG4) + ) i_xcm_8 ( + .qpll_ref_clk (qpll_ref_clk_8), + .qpll_sel (qpll_sel_8), + .qpll2ch_clk (qpll2ch_clk_8), + .qpll2ch_ref_clk (qpll2ch_ref_clk_8), + .qpll2ch_locked (qpll2ch_locked_8), + .qpll1_clk (qpll1_clk_8), + .qpll1_ref_clk (qpll1_ref_clk_8), + .qpll1_locked (qpll1_locked_8), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_qpll_rst (up_qpll_rst_8), + .up_cm_enb (up_cm_enb_8), + .up_cm_addr (up_cm_addr_8), + .up_cm_wr (up_cm_wr_8), + .up_cm_wdata (up_cm_wdata_8), + .up_cm_rdata (up_cm_rdata_8), + .up_cm_ready (up_cm_ready_8)); + end else begin + assign qpll2ch_clk_8 = 1'd0; + assign qpll2ch_ref_clk_8 = 1'd0; + assign qpll2ch_locked_8 = 1'd0; + assign qpll1_clk_8 = 1'd0; + assign qpll1_ref_clk_8 = 1'd0; + assign qpll1_locked_8 = 1'd0; + assign up_cm_rdata_8 = 16'd0; + assign up_cm_ready_8 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 9) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 8) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 8) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_8 ( + .qpll2ch_clk (qpll2ch_clk_8), + .qpll2ch_ref_clk (qpll2ch_ref_clk_8), + .qpll2ch_locked (qpll2ch_locked_8), + .qpll1_clk (qpll1_clk_8), + .qpll1_ref_clk (qpll1_ref_clk_8), + .qpll1_locked (qpll1_locked_8), + .cpll_ref_clk (cpll_ref_clk_8), + .up_cpll_rst (up_cpll_rst_8), + .rx_p (rx_8_p), + .rx_n (rx_8_n), + .rx_out_clk (rx_out_clk_8), + .rx_out_clk_div2 (rx_out_clk_div2_8), + .rx_clk (rx_clk_8), + .rx_clk_2x (rx_clk_2x_8), + .rx_charisk (rx_charisk_8), + .rx_disperr (rx_disperr_8), + .rx_notintable (rx_notintable_8), + .rx_data (rx_data_8), + .rx_calign (rx_calign_8), + .rx_header(rx_header_8), + .rx_block_sync(rx_block_sync_8), + .tx_p (tx_8_p), + .tx_n (tx_8_n), + .tx_out_clk (tx_out_clk_8), + .tx_out_clk_div2 (tx_out_clk_div2_8), + .tx_clk (tx_clk_8), + .tx_clk_2x (tx_clk_2x_8), + .tx_charisk (tx_charisk_8), + .tx_data (tx_data_8), + .tx_header (tx_header_8), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_8), + .up_es_addr (up_es_addr_8), + .up_es_wr (up_es_wr_8), + .up_es_wdata (up_es_wdata_8), + .up_es_rdata (up_es_rdata_8), + .up_es_ready (up_es_ready_8), + .up_es_reset (up_es_reset_8), + .up_rx_pll_locked (up_rx_pll_locked_8), + .up_rx_rst (up_rx_rst_8), + .up_rx_user_ready (up_rx_user_ready_8), + .up_rx_rst_done (up_rx_rst_done_8), + .up_rx_prbssel (up_rx_prbssel_8), + .up_rx_prbscntreset (up_rx_prbscntreset_8), + .up_rx_prbserr (up_rx_prbserr_8), + .up_rx_prbslocked (up_rx_prbslocked_8), + .up_rx_bufstatus (up_rx_bufstatus_8), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_8), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_8), + .up_rx_rate (up_rx_rate_8), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_8), + .up_rx_out_clk_sel (up_rx_out_clk_sel_8), + .up_rx_enb (up_rx_enb_8), + .up_rx_addr (up_rx_addr_8), + .up_rx_wr (up_rx_wr_8), + .up_rx_wdata (up_rx_wdata_8), + .up_rx_rdata (up_rx_rdata_8), + .up_rx_ready (up_rx_ready_8), + .up_tx_pll_locked (up_tx_pll_locked_8), + .up_tx_rst (up_tx_rst_8), + .up_tx_user_ready (up_tx_user_ready_8), + .up_tx_rst_done (up_tx_rst_done_8), + .up_tx_bufstatus (up_tx_bufstatus_8), + .up_tx_prbsforceerr (up_tx_prbsforceerr_8), + .up_tx_prbssel (up_tx_prbssel_8), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_8), + .up_tx_rate (up_tx_rate_8), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_8), + .up_tx_out_clk_sel (up_tx_out_clk_sel_8), + .up_tx_diffctrl (up_tx_diffctrl_8), + .up_tx_postcursor (up_tx_postcursor_8), + .up_tx_precursor (up_tx_precursor_8), + .up_tx_enb (up_tx_enb_8), + .up_tx_addr (up_tx_addr_8), + .up_tx_wr (up_tx_wr_8), + .up_tx_wdata (up_tx_wdata_8), + .up_tx_rdata (up_tx_rdata_8), + .up_tx_ready (up_tx_ready_8)); + end else begin + assign rx_out_clk_8 = 1'd0; + assign rx_charisk_8 = 4'd0; + assign rx_disperr_8 = 4'd0; + assign rx_notintable_8 = 4'd0; + assign rx_data_8 = 32'd0; + assign tx_8_p = 1'd0; + assign tx_8_n = 1'd0; + assign tx_out_clk_8 = 1'd0; + assign up_es_rdata_8 = 16'd0; + assign up_es_ready_8 = 1'd0; + assign up_rx_pll_locked_8 = 1'd0; + assign up_rx_rst_done_8 = 1'd0; + assign up_rx_rdata_8 = 16'd0; + assign up_rx_ready_8 = 1'd0; + assign up_tx_pll_locked_8 = 1'd0; + assign up_tx_rst_done_8 = 1'd0; + assign up_tx_rdata_8 = 16'd0; + assign up_tx_ready_8 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 10) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 9) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 9) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_9 ( + .qpll2ch_clk (qpll2ch_clk_8), + .qpll2ch_ref_clk (qpll2ch_ref_clk_8), + .qpll2ch_locked (qpll2ch_locked_8), + .qpll1_clk (qpll1_clk_8), + .qpll1_ref_clk (qpll1_ref_clk_8), + .qpll1_locked (qpll1_locked_8), + .cpll_ref_clk (cpll_ref_clk_9), + .up_cpll_rst (up_cpll_rst_9), + .rx_p (rx_9_p), + .rx_n (rx_9_n), + .rx_out_clk (rx_out_clk_9), + .rx_out_clk_div2 (rx_out_clk_div2_9), + .rx_clk (rx_clk_9), + .rx_clk_2x (rx_clk_2x_9), + .rx_charisk (rx_charisk_9), + .rx_disperr (rx_disperr_9), + .rx_notintable (rx_notintable_9), + .rx_data (rx_data_9), + .rx_calign (rx_calign_9), + .rx_header(rx_header_9), + .rx_block_sync(rx_block_sync_9), + .tx_p (tx_9_p), + .tx_n (tx_9_n), + .tx_out_clk (tx_out_clk_9), + .tx_out_clk_div2 (tx_out_clk_div2_9), + .tx_clk (tx_clk_9), + .tx_clk_2x (tx_clk_2x_9), + .tx_charisk (tx_charisk_9), + .tx_data (tx_data_9), + .tx_header (tx_header_9), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_9), + .up_es_addr (up_es_addr_9), + .up_es_wr (up_es_wr_9), + .up_es_wdata (up_es_wdata_9), + .up_es_rdata (up_es_rdata_9), + .up_es_ready (up_es_ready_9), + .up_es_reset (up_es_reset_9), + .up_rx_pll_locked (up_rx_pll_locked_9), + .up_rx_rst (up_rx_rst_9), + .up_rx_user_ready (up_rx_user_ready_9), + .up_rx_rst_done (up_rx_rst_done_9), + .up_rx_prbssel (up_rx_prbssel_9), + .up_rx_prbscntreset (up_rx_prbscntreset_9), + .up_rx_prbserr (up_rx_prbserr_9), + .up_rx_prbslocked (up_rx_prbslocked_9), + .up_rx_bufstatus (up_rx_bufstatus_9), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_9), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_9), + .up_rx_rate (up_rx_rate_9), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_9), + .up_rx_out_clk_sel (up_rx_out_clk_sel_9), + .up_rx_enb (up_rx_enb_9), + .up_rx_addr (up_rx_addr_9), + .up_rx_wr (up_rx_wr_9), + .up_rx_wdata (up_rx_wdata_9), + .up_rx_rdata (up_rx_rdata_9), + .up_rx_ready (up_rx_ready_9), + .up_tx_pll_locked (up_tx_pll_locked_9), + .up_tx_rst (up_tx_rst_9), + .up_tx_user_ready (up_tx_user_ready_9), + .up_tx_rst_done (up_tx_rst_done_9), + .up_tx_bufstatus (up_tx_bufstatus_9), + .up_tx_prbsforceerr (up_tx_prbsforceerr_9), + .up_tx_prbssel (up_tx_prbssel_9), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_9), + .up_tx_rate (up_tx_rate_9), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_9), + .up_tx_out_clk_sel (up_tx_out_clk_sel_9), + .up_tx_diffctrl (up_tx_diffctrl_9), + .up_tx_postcursor (up_tx_postcursor_9), + .up_tx_precursor (up_tx_precursor_9), + .up_tx_enb (up_tx_enb_9), + .up_tx_addr (up_tx_addr_9), + .up_tx_wr (up_tx_wr_9), + .up_tx_wdata (up_tx_wdata_9), + .up_tx_rdata (up_tx_rdata_9), + .up_tx_ready (up_tx_ready_9)); + end else begin + assign rx_out_clk_9 = 1'd0; + assign rx_charisk_9 = 4'd0; + assign rx_disperr_9 = 4'd0; + assign rx_notintable_9 = 4'd0; + assign rx_data_9 = 32'd0; + assign tx_9_p = 1'd0; + assign tx_9_n = 1'd0; + assign tx_out_clk_9 = 1'd0; + assign up_es_rdata_9 = 16'd0; + assign up_es_ready_9 = 1'd0; + assign up_rx_pll_locked_9 = 1'd0; + assign up_rx_rst_done_9 = 1'd0; + assign up_rx_rdata_9 = 16'd0; + assign up_rx_ready_9 = 1'd0; + assign up_tx_pll_locked_9 = 1'd0; + assign up_tx_rst_done_9 = 1'd0; + assign up_tx_rdata_9 = 16'd0; + assign up_tx_ready_9 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 11) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 10) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 10) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_10 ( + .qpll2ch_clk (qpll2ch_clk_8), + .qpll2ch_ref_clk (qpll2ch_ref_clk_8), + .qpll2ch_locked (qpll2ch_locked_8), + .qpll1_clk (qpll1_clk_8), + .qpll1_ref_clk (qpll1_ref_clk_8), + .qpll1_locked (qpll1_locked_8), + .cpll_ref_clk (cpll_ref_clk_10), + .up_cpll_rst (up_cpll_rst_10), + .rx_p (rx_10_p), + .rx_n (rx_10_n), + .rx_out_clk (rx_out_clk_10), + .rx_out_clk_div2 (rx_out_clk_div2_10), + .rx_clk (rx_clk_10), + .rx_clk_2x (rx_clk_2x_10), + .rx_charisk (rx_charisk_10), + .rx_disperr (rx_disperr_10), + .rx_notintable (rx_notintable_10), + .rx_data (rx_data_10), + .rx_calign (rx_calign_10), + .rx_header(rx_header_10), + .rx_block_sync(rx_block_sync_10), + .tx_p (tx_10_p), + .tx_n (tx_10_n), + .tx_out_clk (tx_out_clk_10), + .tx_out_clk_div2 (tx_out_clk_div2_10), + .tx_clk (tx_clk_10), + .tx_clk_2x (tx_clk_2x_10), + .tx_charisk (tx_charisk_10), + .tx_data (tx_data_10), + .tx_header (tx_header_10), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_10), + .up_es_addr (up_es_addr_10), + .up_es_wr (up_es_wr_10), + .up_es_wdata (up_es_wdata_10), + .up_es_rdata (up_es_rdata_10), + .up_es_ready (up_es_ready_10), + .up_es_reset (up_es_reset_10), + .up_rx_pll_locked (up_rx_pll_locked_10), + .up_rx_rst (up_rx_rst_10), + .up_rx_user_ready (up_rx_user_ready_10), + .up_rx_rst_done (up_rx_rst_done_10), + .up_rx_prbssel (up_rx_prbssel_10), + .up_rx_prbscntreset (up_rx_prbscntreset_10), + .up_rx_prbserr (up_rx_prbserr_10), + .up_rx_prbslocked (up_rx_prbslocked_10), + .up_rx_bufstatus (up_rx_bufstatus_10), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_10), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_10), + .up_rx_rate (up_rx_rate_10), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_10), + .up_rx_out_clk_sel (up_rx_out_clk_sel_10), + .up_rx_enb (up_rx_enb_10), + .up_rx_addr (up_rx_addr_10), + .up_rx_wr (up_rx_wr_10), + .up_rx_wdata (up_rx_wdata_10), + .up_rx_rdata (up_rx_rdata_10), + .up_rx_ready (up_rx_ready_10), + .up_tx_pll_locked (up_tx_pll_locked_10), + .up_tx_rst (up_tx_rst_10), + .up_tx_user_ready (up_tx_user_ready_10), + .up_tx_rst_done (up_tx_rst_done_10), + .up_tx_bufstatus (up_tx_bufstatus_10), + .up_tx_prbsforceerr (up_tx_prbsforceerr_10), + .up_tx_prbssel (up_tx_prbssel_10), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_10), + .up_tx_rate (up_tx_rate_10), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_10), + .up_tx_out_clk_sel (up_tx_out_clk_sel_10), + .up_tx_diffctrl (up_tx_diffctrl_10), + .up_tx_postcursor (up_tx_postcursor_10), + .up_tx_precursor (up_tx_precursor_10), + .up_tx_enb (up_tx_enb_10), + .up_tx_addr (up_tx_addr_10), + .up_tx_wr (up_tx_wr_10), + .up_tx_wdata (up_tx_wdata_10), + .up_tx_rdata (up_tx_rdata_10), + .up_tx_ready (up_tx_ready_10)); + end else begin + assign rx_out_clk_10 = 1'd0; + assign rx_charisk_10 = 4'd0; + assign rx_disperr_10 = 4'd0; + assign rx_notintable_10 = 4'd0; + assign rx_data_10 = 32'd0; + assign tx_10_p = 1'd0; + assign tx_10_n = 1'd0; + assign tx_out_clk_10 = 1'd0; + assign up_es_rdata_10 = 16'd0; + assign up_es_ready_10 = 1'd0; + assign up_rx_pll_locked_10 = 1'd0; + assign up_rx_rst_done_10 = 1'd0; + assign up_rx_rdata_10 = 16'd0; + assign up_rx_ready_10 = 1'd0; + assign up_tx_pll_locked_10 = 1'd0; + assign up_tx_rst_done_10 = 1'd0; + assign up_tx_rdata_10 = 16'd0; + assign up_tx_ready_10 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 12) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 11) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 11) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_11 ( + .qpll2ch_clk (qpll2ch_clk_8), + .qpll2ch_ref_clk (qpll2ch_ref_clk_8), + .qpll2ch_locked (qpll2ch_locked_8), + .qpll1_clk (qpll1_clk_8), + .qpll1_ref_clk (qpll1_ref_clk_8), + .qpll1_locked (qpll1_locked_8), + .cpll_ref_clk (cpll_ref_clk_11), + .up_cpll_rst (up_cpll_rst_11), + .rx_p (rx_11_p), + .rx_n (rx_11_n), + .rx_out_clk (rx_out_clk_11), + .rx_out_clk_div2 (rx_out_clk_div2_11), + .rx_clk (rx_clk_11), + .rx_clk_2x (rx_clk_2x_11), + .rx_charisk (rx_charisk_11), + .rx_disperr (rx_disperr_11), + .rx_notintable (rx_notintable_11), + .rx_data (rx_data_11), + .rx_calign (rx_calign_11), + .rx_header(rx_header_11), + .rx_block_sync(rx_block_sync_11), + .tx_p (tx_11_p), + .tx_n (tx_11_n), + .tx_out_clk (tx_out_clk_11), + .tx_out_clk_div2 (tx_out_clk_div2_11), + .tx_clk (tx_clk_11), + .tx_clk_2x (tx_clk_2x_11), + .tx_charisk (tx_charisk_11), + .tx_data (tx_data_11), + .tx_header (tx_header_11), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_11), + .up_es_addr (up_es_addr_11), + .up_es_wr (up_es_wr_11), + .up_es_wdata (up_es_wdata_11), + .up_es_rdata (up_es_rdata_11), + .up_es_ready (up_es_ready_11), + .up_es_reset (up_es_reset_11), + .up_rx_pll_locked (up_rx_pll_locked_11), + .up_rx_rst (up_rx_rst_11), + .up_rx_user_ready (up_rx_user_ready_11), + .up_rx_rst_done (up_rx_rst_done_11), + .up_rx_prbssel (up_rx_prbssel_11), + .up_rx_prbscntreset (up_rx_prbscntreset_11), + .up_rx_prbserr (up_rx_prbserr_11), + .up_rx_prbslocked (up_rx_prbslocked_11), + .up_rx_bufstatus (up_rx_bufstatus_11), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_11), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_11), + .up_rx_rate (up_rx_rate_11), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_11), + .up_rx_out_clk_sel (up_rx_out_clk_sel_11), + .up_rx_enb (up_rx_enb_11), + .up_rx_addr (up_rx_addr_11), + .up_rx_wr (up_rx_wr_11), + .up_rx_wdata (up_rx_wdata_11), + .up_rx_rdata (up_rx_rdata_11), + .up_rx_ready (up_rx_ready_11), + .up_tx_pll_locked (up_tx_pll_locked_11), + .up_tx_rst (up_tx_rst_11), + .up_tx_user_ready (up_tx_user_ready_11), + .up_tx_rst_done (up_tx_rst_done_11), + .up_tx_bufstatus (up_tx_bufstatus_11), + .up_tx_prbsforceerr (up_tx_prbsforceerr_11), + .up_tx_prbssel (up_tx_prbssel_11), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_11), + .up_tx_rate (up_tx_rate_11), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_11), + .up_tx_out_clk_sel (up_tx_out_clk_sel_11), + .up_tx_diffctrl (up_tx_diffctrl_11), + .up_tx_postcursor (up_tx_postcursor_11), + .up_tx_precursor (up_tx_precursor_11), + .up_tx_enb (up_tx_enb_11), + .up_tx_addr (up_tx_addr_11), + .up_tx_wr (up_tx_wr_11), + .up_tx_wdata (up_tx_wdata_11), + .up_tx_rdata (up_tx_rdata_11), + .up_tx_ready (up_tx_ready_11)); + end else begin + assign rx_out_clk_11 = 1'd0; + assign rx_charisk_11 = 4'd0; + assign rx_disperr_11 = 4'd0; + assign rx_notintable_11 = 4'd0; + assign rx_data_11 = 32'd0; + assign tx_11_p = 1'd0; + assign tx_11_n = 1'd0; + assign tx_out_clk_11 = 1'd0; + assign up_es_rdata_11 = 16'd0; + assign up_es_ready_11 = 1'd0; + assign up_rx_pll_locked_11 = 1'd0; + assign up_rx_rst_done_11 = 1'd0; + assign up_rx_rdata_11 = 16'd0; + assign up_rx_ready_11 = 1'd0; + assign up_tx_pll_locked_11 = 1'd0; + assign up_tx_rst_done_11 = 1'd0; + assign up_tx_rdata_11 = 16'd0; + assign up_tx_ready_11 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 13) begin + util_adxcvr_xcm #( + .XCVR_TYPE (XCVR_TYPE), + .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .POR_CFG (POR_CFG), + .PPF0_CFG (PPF0_CFG), + .PPF1_CFG (PPF1_CFG), + .QPLL_CFG (QPLL_CFG), + .QPLL_FBDIV (QPLL_FBDIV), + .QPLL_CFG0 (QPLL_CFG0), + .QPLL_CFG1 (QPLL_CFG1), + .QPLL_CFG1_G3 (QPLL_CFG1_G3), + .QPLL_CFG2 (QPLL_CFG2), + .QPLL_CFG2_G3 (QPLL_CFG2_G3), + .QPLL_CFG3 (QPLL_CFG3), + .QPLL_CP_G3 (QPLL_CP_G3), + .QPLL_LPF (QPLL_LPF), + .QPLL_CP (QPLL_CP), + .QPLL_CFG4 (QPLL_CFG4) + ) i_xcm_12 ( + .qpll_ref_clk (qpll_ref_clk_12), + .qpll_sel (qpll_sel_12), + .qpll2ch_clk (qpll2ch_clk_12), + .qpll2ch_ref_clk (qpll2ch_ref_clk_12), + .qpll2ch_locked (qpll2ch_locked_12), + .qpll1_clk (qpll1_clk_12), + .qpll1_ref_clk (qpll1_ref_clk_12), + .qpll1_locked (qpll1_locked_12), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_qpll_rst (up_qpll_rst_12), + .up_cm_enb (up_cm_enb_12), + .up_cm_addr (up_cm_addr_12), + .up_cm_wr (up_cm_wr_12), + .up_cm_wdata (up_cm_wdata_12), + .up_cm_rdata (up_cm_rdata_12), + .up_cm_ready (up_cm_ready_12)); + end else begin + assign qpll2ch_clk_12 = 1'd0; + assign qpll2ch_ref_clk_12 = 1'd0; + assign qpll2ch_locked_12 = 1'd0; + assign qpll1_clk_12 = 1'd0; + assign qpll1_ref_clk_12 = 1'd0; + assign qpll1_locked_12 = 1'd0; + assign up_cm_rdata_12 = 16'd0; + assign up_cm_ready_12 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 13) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 12) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 12) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_12 ( + .qpll2ch_clk (qpll2ch_clk_12), + .qpll2ch_ref_clk (qpll2ch_ref_clk_12), + .qpll2ch_locked (qpll2ch_locked_12), + .qpll1_clk (qpll1_clk_12), + .qpll1_ref_clk (qpll1_ref_clk_12), + .qpll1_locked (qpll1_locked_12), + .cpll_ref_clk (cpll_ref_clk_12), + .up_cpll_rst (up_cpll_rst_12), + .rx_p (rx_12_p), + .rx_n (rx_12_n), + .rx_out_clk (rx_out_clk_12), + .rx_out_clk_div2 (rx_out_clk_div2_12), + .rx_clk (rx_clk_12), + .rx_clk_2x (rx_clk_2x_12), + .rx_charisk (rx_charisk_12), + .rx_disperr (rx_disperr_12), + .rx_notintable (rx_notintable_12), + .rx_data (rx_data_12), + .rx_calign (rx_calign_12), + .rx_header(rx_header_12), + .rx_block_sync(rx_block_sync_12), + .tx_p (tx_12_p), + .tx_n (tx_12_n), + .tx_out_clk (tx_out_clk_12), + .tx_out_clk_div2 (tx_out_clk_div2_12), + .tx_clk (tx_clk_12), + .tx_clk_2x (tx_clk_2x_12), + .tx_charisk (tx_charisk_12), + .tx_data (tx_data_12), + .tx_header (tx_header_12), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_12), + .up_es_addr (up_es_addr_12), + .up_es_wr (up_es_wr_12), + .up_es_wdata (up_es_wdata_12), + .up_es_rdata (up_es_rdata_12), + .up_es_ready (up_es_ready_12), + .up_es_reset (up_es_reset_12), + .up_rx_pll_locked (up_rx_pll_locked_12), + .up_rx_rst (up_rx_rst_12), + .up_rx_user_ready (up_rx_user_ready_12), + .up_rx_rst_done (up_rx_rst_done_12), + .up_rx_prbssel (up_rx_prbssel_12), + .up_rx_prbscntreset (up_rx_prbscntreset_12), + .up_rx_prbserr (up_rx_prbserr_12), + .up_rx_prbslocked (up_rx_prbslocked_12), + .up_rx_bufstatus (up_rx_bufstatus_12), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_12), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_12), + .up_rx_rate (up_rx_rate_12), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_12), + .up_rx_out_clk_sel (up_rx_out_clk_sel_12), + .up_rx_enb (up_rx_enb_12), + .up_rx_addr (up_rx_addr_12), + .up_rx_wr (up_rx_wr_12), + .up_rx_wdata (up_rx_wdata_12), + .up_rx_rdata (up_rx_rdata_12), + .up_rx_ready (up_rx_ready_12), + .up_tx_pll_locked (up_tx_pll_locked_12), + .up_tx_rst (up_tx_rst_12), + .up_tx_user_ready (up_tx_user_ready_12), + .up_tx_rst_done (up_tx_rst_done_12), + .up_tx_bufstatus (up_tx_bufstatus_12), + .up_tx_prbsforceerr (up_tx_prbsforceerr_12), + .up_tx_prbssel (up_tx_prbssel_12), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_12), + .up_tx_rate (up_tx_rate_12), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_12), + .up_tx_out_clk_sel (up_tx_out_clk_sel_12), + .up_tx_diffctrl (up_tx_diffctrl_12), + .up_tx_postcursor (up_tx_postcursor_12), + .up_tx_precursor (up_tx_precursor_12), + .up_tx_enb (up_tx_enb_12), + .up_tx_addr (up_tx_addr_12), + .up_tx_wr (up_tx_wr_12), + .up_tx_wdata (up_tx_wdata_12), + .up_tx_rdata (up_tx_rdata_12), + .up_tx_ready (up_tx_ready_12)); + end else begin + assign rx_out_clk_12 = 1'd0; + assign rx_charisk_12 = 4'd0; + assign rx_disperr_12 = 4'd0; + assign rx_notintable_12 = 4'd0; + assign rx_data_12 = 32'd0; + assign tx_12_p = 1'd0; + assign tx_12_n = 1'd0; + assign tx_out_clk_12 = 1'd0; + assign up_es_rdata_12 = 16'd0; + assign up_es_ready_12 = 1'd0; + assign up_rx_pll_locked_12 = 1'd0; + assign up_rx_rst_done_12 = 1'd0; + assign up_rx_rdata_12 = 16'd0; + assign up_rx_ready_12 = 1'd0; + assign up_tx_pll_locked_12 = 1'd0; + assign up_tx_rst_done_12 = 1'd0; + assign up_tx_rdata_12 = 16'd0; + assign up_tx_ready_12 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 14) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 13) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 13) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_13 ( + .qpll2ch_clk (qpll2ch_clk_12), + .qpll2ch_ref_clk (qpll2ch_ref_clk_12), + .qpll2ch_locked (qpll2ch_locked_12), + .qpll1_clk (qpll1_clk_12), + .qpll1_ref_clk (qpll1_ref_clk_12), + .qpll1_locked (qpll1_locked_12), + .cpll_ref_clk (cpll_ref_clk_13), + .up_cpll_rst (up_cpll_rst_13), + .rx_p (rx_13_p), + .rx_n (rx_13_n), + .rx_out_clk (rx_out_clk_13), + .rx_out_clk_div2 (rx_out_clk_div2_13), + .rx_clk (rx_clk_13), + .rx_clk_2x (rx_clk_2x_13), + .rx_charisk (rx_charisk_13), + .rx_disperr (rx_disperr_13), + .rx_notintable (rx_notintable_13), + .rx_data (rx_data_13), + .rx_calign (rx_calign_13), + .rx_header(rx_header_13), + .rx_block_sync(rx_block_sync_13), + .tx_p (tx_13_p), + .tx_n (tx_13_n), + .tx_out_clk (tx_out_clk_13), + .tx_out_clk_div2 (tx_out_clk_div2_13), + .tx_clk (tx_clk_13), + .tx_clk_2x (tx_clk_2x_13), + .tx_charisk (tx_charisk_13), + .tx_data (tx_data_13), + .tx_header (tx_header_13), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_13), + .up_es_addr (up_es_addr_13), + .up_es_wr (up_es_wr_13), + .up_es_wdata (up_es_wdata_13), + .up_es_rdata (up_es_rdata_13), + .up_es_ready (up_es_ready_13), + .up_es_reset (up_es_reset_13), + .up_rx_pll_locked (up_rx_pll_locked_13), + .up_rx_rst (up_rx_rst_13), + .up_rx_user_ready (up_rx_user_ready_13), + .up_rx_rst_done (up_rx_rst_done_13), + .up_rx_prbssel (up_rx_prbssel_13), + .up_rx_prbscntreset (up_rx_prbscntreset_13), + .up_rx_prbserr (up_rx_prbserr_13), + .up_rx_prbslocked (up_rx_prbslocked_13), + .up_rx_bufstatus (up_rx_bufstatus_13), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_13), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_13), + .up_rx_rate (up_rx_rate_13), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_13), + .up_rx_out_clk_sel (up_rx_out_clk_sel_13), + .up_rx_enb (up_rx_enb_13), + .up_rx_addr (up_rx_addr_13), + .up_rx_wr (up_rx_wr_13), + .up_rx_wdata (up_rx_wdata_13), + .up_rx_rdata (up_rx_rdata_13), + .up_rx_ready (up_rx_ready_13), + .up_tx_pll_locked (up_tx_pll_locked_13), + .up_tx_rst (up_tx_rst_13), + .up_tx_user_ready (up_tx_user_ready_13), + .up_tx_rst_done (up_tx_rst_done_13), + .up_tx_bufstatus (up_tx_bufstatus_13), + .up_tx_prbsforceerr (up_tx_prbsforceerr_13), + .up_tx_prbssel (up_tx_prbssel_13), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_13), + .up_tx_rate (up_tx_rate_13), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_13), + .up_tx_out_clk_sel (up_tx_out_clk_sel_13), + .up_tx_diffctrl (up_tx_diffctrl_13), + .up_tx_postcursor (up_tx_postcursor_13), + .up_tx_precursor (up_tx_precursor_13), + .up_tx_enb (up_tx_enb_13), + .up_tx_addr (up_tx_addr_13), + .up_tx_wr (up_tx_wr_13), + .up_tx_wdata (up_tx_wdata_13), + .up_tx_rdata (up_tx_rdata_13), + .up_tx_ready (up_tx_ready_13)); + end else begin + assign rx_out_clk_13 = 1'd0; + assign rx_charisk_13 = 4'd0; + assign rx_disperr_13 = 4'd0; + assign rx_notintable_13 = 4'd0; + assign rx_data_13 = 32'd0; + assign tx_13_p = 1'd0; + assign tx_13_n = 1'd0; + assign tx_out_clk_13 = 1'd0; + assign up_es_rdata_13 = 16'd0; + assign up_es_ready_13 = 1'd0; + assign up_rx_pll_locked_13 = 1'd0; + assign up_rx_rst_done_13 = 1'd0; + assign up_rx_rdata_13 = 16'd0; + assign up_rx_ready_13 = 1'd0; + assign up_tx_pll_locked_13 = 1'd0; + assign up_tx_rst_done_13 = 1'd0; + assign up_tx_rdata_13 = 16'd0; + assign up_tx_ready_13 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 15) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 14) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 14) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_14 ( + .qpll2ch_clk (qpll2ch_clk_12), + .qpll2ch_ref_clk (qpll2ch_ref_clk_12), + .qpll2ch_locked (qpll2ch_locked_12), + .qpll1_clk (qpll1_clk_12), + .qpll1_ref_clk (qpll1_ref_clk_12), + .qpll1_locked (qpll1_locked_12), + .cpll_ref_clk (cpll_ref_clk_14), + .up_cpll_rst (up_cpll_rst_14), + .rx_p (rx_14_p), + .rx_n (rx_14_n), + .rx_out_clk (rx_out_clk_14), + .rx_out_clk_div2 (rx_out_clk_div2_14), + .rx_clk (rx_clk_14), + .rx_clk_2x (rx_clk_2x_14), + .rx_charisk (rx_charisk_14), + .rx_disperr (rx_disperr_14), + .rx_notintable (rx_notintable_14), + .rx_data (rx_data_14), + .rx_calign (rx_calign_14), + .rx_header(rx_header_14), + .rx_block_sync(rx_block_sync_14), + .tx_p (tx_14_p), + .tx_n (tx_14_n), + .tx_out_clk (tx_out_clk_14), + .tx_out_clk_div2 (tx_out_clk_div2_14), + .tx_clk (tx_clk_14), + .tx_clk_2x (tx_clk_2x_14), + .tx_charisk (tx_charisk_14), + .tx_data (tx_data_14), + .tx_header (tx_header_14), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_14), + .up_es_addr (up_es_addr_14), + .up_es_wr (up_es_wr_14), + .up_es_wdata (up_es_wdata_14), + .up_es_rdata (up_es_rdata_14), + .up_es_ready (up_es_ready_14), + .up_es_reset (up_es_reset_14), + .up_rx_pll_locked (up_rx_pll_locked_14), + .up_rx_rst (up_rx_rst_14), + .up_rx_user_ready (up_rx_user_ready_14), + .up_rx_rst_done (up_rx_rst_done_14), + .up_rx_prbssel (up_rx_prbssel_14), + .up_rx_prbscntreset (up_rx_prbscntreset_14), + .up_rx_prbserr (up_rx_prbserr_14), + .up_rx_prbslocked (up_rx_prbslocked_14), + .up_rx_bufstatus (up_rx_bufstatus_14), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_14), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_14), + .up_rx_rate (up_rx_rate_14), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_14), + .up_rx_out_clk_sel (up_rx_out_clk_sel_14), + .up_rx_enb (up_rx_enb_14), + .up_rx_addr (up_rx_addr_14), + .up_rx_wr (up_rx_wr_14), + .up_rx_wdata (up_rx_wdata_14), + .up_rx_rdata (up_rx_rdata_14), + .up_rx_ready (up_rx_ready_14), + .up_tx_pll_locked (up_tx_pll_locked_14), + .up_tx_rst (up_tx_rst_14), + .up_tx_user_ready (up_tx_user_ready_14), + .up_tx_rst_done (up_tx_rst_done_14), + .up_tx_bufstatus (up_tx_bufstatus_14), + .up_tx_prbsforceerr (up_tx_prbsforceerr_14), + .up_tx_prbssel (up_tx_prbssel_14), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_14), + .up_tx_rate (up_tx_rate_14), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_14), + .up_tx_out_clk_sel (up_tx_out_clk_sel_14), + .up_tx_diffctrl (up_tx_diffctrl_14), + .up_tx_postcursor (up_tx_postcursor_14), + .up_tx_precursor (up_tx_precursor_14), + .up_tx_enb (up_tx_enb_14), + .up_tx_addr (up_tx_addr_14), + .up_tx_wr (up_tx_wr_14), + .up_tx_wdata (up_tx_wdata_14), + .up_tx_rdata (up_tx_rdata_14), + .up_tx_ready (up_tx_ready_14)); + end else begin + assign rx_out_clk_14 = 1'd0; + assign rx_charisk_14 = 4'd0; + assign rx_disperr_14 = 4'd0; + assign rx_notintable_14 = 4'd0; + assign rx_data_14 = 32'd0; + assign tx_14_p = 1'd0; + assign tx_14_n = 1'd0; + assign tx_out_clk_14 = 1'd0; + assign up_es_rdata_14 = 16'd0; + assign up_es_ready_14 = 1'd0; + assign up_rx_pll_locked_14 = 1'd0; + assign up_rx_rst_done_14 = 1'd0; + assign up_rx_rdata_14 = 16'd0; + assign up_rx_ready_14 = 1'd0; + assign up_tx_pll_locked_14 = 1'd0; + assign up_tx_rst_done_14 = 1'd0; + assign up_tx_rdata_14 = 16'd0; + assign up_tx_ready_14 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 16) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 15) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 15) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_15 ( + .qpll2ch_clk (qpll2ch_clk_12), + .qpll2ch_ref_clk (qpll2ch_ref_clk_12), + .qpll2ch_locked (qpll2ch_locked_12), + .qpll1_clk (qpll1_clk_12), + .qpll1_ref_clk (qpll1_ref_clk_12), + .qpll1_locked (qpll1_locked_12), + .cpll_ref_clk (cpll_ref_clk_15), + .up_cpll_rst (up_cpll_rst_15), + .rx_p (rx_15_p), + .rx_n (rx_15_n), + .rx_out_clk (rx_out_clk_15), + .rx_out_clk_div2 (rx_out_clk_div2_15), + .rx_clk (rx_clk_15), + .rx_clk_2x (rx_clk_2x_15), + .rx_charisk (rx_charisk_15), + .rx_disperr (rx_disperr_15), + .rx_notintable (rx_notintable_15), + .rx_data (rx_data_15), + .rx_calign (rx_calign_15), + .rx_header(rx_header_15), + .rx_block_sync(rx_block_sync_15), + .tx_p (tx_15_p), + .tx_n (tx_15_n), + .tx_out_clk (tx_out_clk_15), + .tx_out_clk_div2 (tx_out_clk_div2_15), + .tx_clk (tx_clk_15), + .tx_clk_2x (tx_clk_2x_15), + .tx_charisk (tx_charisk_15), + .tx_data (tx_data_15), + .tx_header (tx_header_15), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_15), + .up_es_addr (up_es_addr_15), + .up_es_wr (up_es_wr_15), + .up_es_wdata (up_es_wdata_15), + .up_es_rdata (up_es_rdata_15), + .up_es_ready (up_es_ready_15), + .up_es_reset (up_es_reset_15), + .up_rx_pll_locked (up_rx_pll_locked_15), + .up_rx_rst (up_rx_rst_15), + .up_rx_user_ready (up_rx_user_ready_15), + .up_rx_rst_done (up_rx_rst_done_15), + .up_rx_prbssel (up_rx_prbssel_15), + .up_rx_prbscntreset (up_rx_prbscntreset_15), + .up_rx_prbserr (up_rx_prbserr_15), + .up_rx_prbslocked (up_rx_prbslocked_15), + .up_rx_bufstatus (up_rx_bufstatus_15), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_15), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_15), + .up_rx_rate (up_rx_rate_15), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_15), + .up_rx_out_clk_sel (up_rx_out_clk_sel_15), + .up_rx_enb (up_rx_enb_15), + .up_rx_addr (up_rx_addr_15), + .up_rx_wr (up_rx_wr_15), + .up_rx_wdata (up_rx_wdata_15), + .up_rx_rdata (up_rx_rdata_15), + .up_rx_ready (up_rx_ready_15), + .up_tx_pll_locked (up_tx_pll_locked_15), + .up_tx_rst (up_tx_rst_15), + .up_tx_user_ready (up_tx_user_ready_15), + .up_tx_rst_done (up_tx_rst_done_15), + .up_tx_bufstatus (up_tx_bufstatus_15), + .up_tx_prbsforceerr (up_tx_prbsforceerr_15), + .up_tx_prbssel (up_tx_prbssel_15), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_15), + .up_tx_rate (up_tx_rate_15), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_15), + .up_tx_out_clk_sel (up_tx_out_clk_sel_15), + .up_tx_diffctrl (up_tx_diffctrl_15), + .up_tx_postcursor (up_tx_postcursor_15), + .up_tx_precursor (up_tx_precursor_15), + .up_tx_enb (up_tx_enb_15), + .up_tx_addr (up_tx_addr_15), + .up_tx_wr (up_tx_wr_15), + .up_tx_wdata (up_tx_wdata_15), + .up_tx_rdata (up_tx_rdata_15), + .up_tx_ready (up_tx_ready_15)); + end else begin + assign rx_out_clk_15 = 1'd0; + assign rx_charisk_15 = 4'd0; + assign rx_disperr_15 = 4'd0; + assign rx_notintable_15 = 4'd0; + assign rx_data_15 = 32'd0; + assign tx_15_p = 1'd0; + assign tx_15_n = 1'd0; + assign tx_out_clk_15 = 1'd0; + assign up_es_rdata_15 = 16'd0; + assign up_es_ready_15 = 1'd0; + assign up_rx_pll_locked_15 = 1'd0; + assign up_rx_rst_done_15 = 1'd0; + assign up_rx_rdata_15 = 16'd0; + assign up_rx_ready_15 = 1'd0; + assign up_tx_pll_locked_15 = 1'd0; + assign up_tx_rst_done_15 = 1'd0; + assign up_tx_rdata_15 = 16'd0; + assign up_tx_ready_15 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 17) begin + util_adxcvr_xcm #( + .XCVR_TYPE (XCVR_TYPE), + .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .POR_CFG (POR_CFG), + .PPF0_CFG (PPF0_CFG), + .PPF1_CFG (PPF1_CFG), + .QPLL_CFG (QPLL_CFG), + .QPLL_FBDIV (QPLL_FBDIV), + .QPLL_CFG0 (QPLL_CFG0), + .QPLL_CFG1 (QPLL_CFG1), + .QPLL_CFG1_G3 (QPLL_CFG1_G3), + .QPLL_CFG2 (QPLL_CFG2), + .QPLL_CFG2_G3 (QPLL_CFG2_G3), + .QPLL_CFG3 (QPLL_CFG3), + .QPLL_CP_G3 (QPLL_CP_G3), + .QPLL_LPF (QPLL_LPF), + .QPLL_CP (QPLL_CP), + .QPLL_CFG4 (QPLL_CFG4) + ) i_xcm_16 ( + .qpll_ref_clk (qpll_ref_clk_16), + .qpll_sel (qpll_sel_16), + .qpll2ch_clk (qpll2ch_clk_16), + .qpll2ch_ref_clk (qpll2ch_ref_clk_16), + .qpll2ch_locked (qpll2ch_locked_16), + .qpll1_clk (qpll1_clk_16), + .qpll1_ref_clk (qpll1_ref_clk_16), + .qpll1_locked (qpll1_locked_16), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_qpll_rst (up_qpll_rst_16), + .up_cm_enb (up_cm_enb_16), + .up_cm_addr (up_cm_addr_16), + .up_cm_wr (up_cm_wr_16), + .up_cm_wdata (up_cm_wdata_16), + .up_cm_rdata (up_cm_rdata_16), + .up_cm_ready (up_cm_ready_16)); + end else begin + assign qpll2ch_clk_16 = 1'd0; + assign qpll2ch_ref_clk_16 = 1'd0; + assign qpll2ch_locked_16 = 1'd0; + assign qpll1_clk_16 = 1'd0; + assign qpll1_ref_clk_16 = 1'd0; + assign qpll1_locked_16 = 1'd0; + assign up_cm_rdata_16 = 16'd0; + assign up_cm_ready_16 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 17) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 16) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 16) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_16 ( + .qpll2ch_clk (qpll2ch_clk_16), + .qpll2ch_ref_clk (qpll2ch_ref_clk_16), + .qpll2ch_locked (qpll2ch_locked_16), + .qpll1_clk (qpll1_clk_16), + .qpll1_ref_clk (qpll1_ref_clk_16), + .qpll1_locked (qpll1_locked_16), + .cpll_ref_clk (cpll_ref_clk_16), + .up_cpll_rst (up_cpll_rst_16), + .rx_p (rx_16_p), + .rx_n (rx_16_n), + .rx_out_clk (rx_out_clk_16), + .rx_out_clk_div2 (rx_out_clk_div2_16), + .rx_clk (rx_clk_16), + .rx_clk_2x (rx_clk_2x_16), + .rx_charisk (rx_charisk_16), + .rx_disperr (rx_disperr_16), + .rx_notintable (rx_notintable_16), + .rx_data (rx_data_16), + .rx_calign (rx_calign_16), + .rx_header(rx_header_16), + .rx_block_sync(rx_block_sync_16), + .tx_p (tx_16_p), + .tx_n (tx_16_n), + .tx_out_clk (tx_out_clk_16), + .tx_out_clk_div2 (tx_out_clk_div2_16), + .tx_clk (tx_clk_16), + .tx_clk_2x (tx_clk_2x_16), + .tx_charisk (tx_charisk_16), + .tx_data (tx_data_16), + .tx_header (tx_header_16), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_16), + .up_es_addr (up_es_addr_16), + .up_es_wr (up_es_wr_16), + .up_es_wdata (up_es_wdata_16), + .up_es_rdata (up_es_rdata_16), + .up_es_ready (up_es_ready_16), + .up_es_reset (up_es_reset_16), + .up_rx_pll_locked (up_rx_pll_locked_16), + .up_rx_rst (up_rx_rst_16), + .up_rx_user_ready (up_rx_user_ready_16), + .up_rx_rst_done (up_rx_rst_done_16), + .up_rx_prbssel (up_rx_prbssel_16), + .up_rx_prbscntreset (up_rx_prbscntreset_16), + .up_rx_prbserr (up_rx_prbserr_16), + .up_rx_prbslocked (up_rx_prbslocked_16), + .up_rx_bufstatus (up_rx_bufstatus_16), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_16), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_16), + .up_rx_rate (up_rx_rate_16), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_16), + .up_rx_out_clk_sel (up_rx_out_clk_sel_16), + .up_rx_enb (up_rx_enb_16), + .up_rx_addr (up_rx_addr_16), + .up_rx_wr (up_rx_wr_16), + .up_rx_wdata (up_rx_wdata_16), + .up_rx_rdata (up_rx_rdata_16), + .up_rx_ready (up_rx_ready_16), + .up_tx_pll_locked (up_tx_pll_locked_16), + .up_tx_rst (up_tx_rst_16), + .up_tx_user_ready (up_tx_user_ready_16), + .up_tx_rst_done (up_tx_rst_done_16), + .up_tx_bufstatus (up_tx_bufstatus_16), + .up_tx_prbsforceerr (up_tx_prbsforceerr_16), + .up_tx_prbssel (up_tx_prbssel_16), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_16), + .up_tx_rate (up_tx_rate_16), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_16), + .up_tx_out_clk_sel (up_tx_out_clk_sel_16), + .up_tx_diffctrl (up_tx_diffctrl_16), + .up_tx_postcursor (up_tx_postcursor_16), + .up_tx_precursor (up_tx_precursor_16), + .up_tx_enb (up_tx_enb_16), + .up_tx_addr (up_tx_addr_16), + .up_tx_wr (up_tx_wr_16), + .up_tx_wdata (up_tx_wdata_16), + .up_tx_rdata (up_tx_rdata_16), + .up_tx_ready (up_tx_ready_16)); + end else begin + assign rx_out_clk_16 = 1'd0; + assign rx_charisk_16 = 4'd0; + assign rx_disperr_16 = 4'd0; + assign rx_notintable_16 = 4'd0; + assign rx_data_16 = 32'd0; + assign tx_16_p = 1'd0; + assign tx_16_n = 1'd0; + assign tx_out_clk_16 = 1'd0; + assign up_es_rdata_16 = 16'd0; + assign up_es_ready_16 = 1'd0; + assign up_rx_pll_locked_16 = 1'd0; + assign up_rx_rst_done_16 = 1'd0; + assign up_rx_rdata_16 = 16'd0; + assign up_rx_ready_16 = 1'd0; + assign up_tx_pll_locked_16 = 1'd0; + assign up_tx_rst_done_16 = 1'd0; + assign up_tx_rdata_16 = 16'd0; + assign up_tx_ready_16 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 18) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 17) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 17) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_17 ( + .qpll2ch_clk (qpll2ch_clk_16), + .qpll2ch_ref_clk (qpll2ch_ref_clk_16), + .qpll2ch_locked (qpll2ch_locked_16), + .qpll1_clk (qpll1_clk_16), + .qpll1_ref_clk (qpll1_ref_clk_16), + .qpll1_locked (qpll1_locked_16), + .cpll_ref_clk (cpll_ref_clk_17), + .up_cpll_rst (up_cpll_rst_17), + .rx_p (rx_17_p), + .rx_n (rx_17_n), + .rx_out_clk (rx_out_clk_17), + .rx_out_clk_div2 (rx_out_clk_div2_17), + .rx_clk (rx_clk_17), + .rx_clk_2x (rx_clk_2x_17), + .rx_charisk (rx_charisk_17), + .rx_disperr (rx_disperr_17), + .rx_notintable (rx_notintable_17), + .rx_data (rx_data_17), + .rx_calign (rx_calign_17), + .rx_header(rx_header_17), + .rx_block_sync(rx_block_sync_17), + .tx_p (tx_17_p), + .tx_n (tx_17_n), + .tx_out_clk (tx_out_clk_17), + .tx_out_clk_div2 (tx_out_clk_div2_17), + .tx_clk (tx_clk_17), + .tx_clk_2x (tx_clk_2x_17), + .tx_charisk (tx_charisk_17), + .tx_data (tx_data_17), + .tx_header (tx_header_17), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_17), + .up_es_addr (up_es_addr_17), + .up_es_wr (up_es_wr_17), + .up_es_wdata (up_es_wdata_17), + .up_es_rdata (up_es_rdata_17), + .up_es_ready (up_es_ready_17), + .up_es_reset (up_es_reset_17), + .up_rx_pll_locked (up_rx_pll_locked_17), + .up_rx_rst (up_rx_rst_17), + .up_rx_user_ready (up_rx_user_ready_17), + .up_rx_rst_done (up_rx_rst_done_17), + .up_rx_prbssel (up_rx_prbssel_17), + .up_rx_prbscntreset (up_rx_prbscntreset_17), + .up_rx_prbserr (up_rx_prbserr_17), + .up_rx_prbslocked (up_rx_prbslocked_17), + .up_rx_bufstatus (up_rx_bufstatus_17), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_17), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_17), + .up_rx_rate (up_rx_rate_17), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_17), + .up_rx_out_clk_sel (up_rx_out_clk_sel_17), + .up_rx_enb (up_rx_enb_17), + .up_rx_addr (up_rx_addr_17), + .up_rx_wr (up_rx_wr_17), + .up_rx_wdata (up_rx_wdata_17), + .up_rx_rdata (up_rx_rdata_17), + .up_rx_ready (up_rx_ready_17), + .up_tx_pll_locked (up_tx_pll_locked_17), + .up_tx_rst (up_tx_rst_17), + .up_tx_user_ready (up_tx_user_ready_17), + .up_tx_rst_done (up_tx_rst_done_17), + .up_tx_bufstatus (up_tx_bufstatus_17), + .up_tx_prbsforceerr (up_tx_prbsforceerr_17), + .up_tx_prbssel (up_tx_prbssel_17), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_17), + .up_tx_rate (up_tx_rate_17), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_17), + .up_tx_out_clk_sel (up_tx_out_clk_sel_17), + .up_tx_diffctrl (up_tx_diffctrl_17), + .up_tx_postcursor (up_tx_postcursor_17), + .up_tx_precursor (up_tx_precursor_17), + .up_tx_enb (up_tx_enb_17), + .up_tx_addr (up_tx_addr_17), + .up_tx_wr (up_tx_wr_17), + .up_tx_wdata (up_tx_wdata_17), + .up_tx_rdata (up_tx_rdata_17), + .up_tx_ready (up_tx_ready_17)); + end else begin + assign rx_out_clk_17 = 1'd0; + assign rx_charisk_17 = 4'd0; + assign rx_disperr_17 = 4'd0; + assign rx_notintable_17 = 4'd0; + assign rx_data_17 = 32'd0; + assign tx_17_p = 1'd0; + assign tx_17_n = 1'd0; + assign tx_out_clk_17 = 1'd0; + assign up_es_rdata_17 = 16'd0; + assign up_es_ready_17 = 1'd0; + assign up_rx_pll_locked_17 = 1'd0; + assign up_rx_rst_done_17 = 1'd0; + assign up_rx_rdata_17 = 16'd0; + assign up_rx_ready_17 = 1'd0; + assign up_tx_pll_locked_17 = 1'd0; + assign up_tx_rst_done_17 = 1'd0; + assign up_tx_rdata_17 = 16'd0; + assign up_tx_ready_17 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 19) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 18) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 18) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_18 ( + .qpll2ch_clk (qpll2ch_clk_16), + .qpll2ch_ref_clk (qpll2ch_ref_clk_16), + .qpll2ch_locked (qpll2ch_locked_16), + .qpll1_clk (qpll1_clk_16), + .qpll1_ref_clk (qpll1_ref_clk_16), + .qpll1_locked (qpll1_locked_16), + .cpll_ref_clk (cpll_ref_clk_18), + .up_cpll_rst (up_cpll_rst_18), + .rx_p (rx_18_p), + .rx_n (rx_18_n), + .rx_out_clk (rx_out_clk_18), + .rx_out_clk_div2 (rx_out_clk_div2_18), + .rx_clk (rx_clk_18), + .rx_clk_2x (rx_clk_2x_18), + .rx_charisk (rx_charisk_18), + .rx_disperr (rx_disperr_18), + .rx_notintable (rx_notintable_18), + .rx_data (rx_data_18), + .rx_calign (rx_calign_18), + .rx_header(rx_header_18), + .rx_block_sync(rx_block_sync_18), + .tx_p (tx_18_p), + .tx_n (tx_18_n), + .tx_out_clk (tx_out_clk_18), + .tx_out_clk_div2 (tx_out_clk_div2_18), + .tx_clk (tx_clk_18), + .tx_clk_2x (tx_clk_2x_18), + .tx_charisk (tx_charisk_18), + .tx_data (tx_data_18), + .tx_header (tx_header_18), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_18), + .up_es_addr (up_es_addr_18), + .up_es_wr (up_es_wr_18), + .up_es_wdata (up_es_wdata_18), + .up_es_rdata (up_es_rdata_18), + .up_es_ready (up_es_ready_18), + .up_es_reset (up_es_reset_18), + .up_rx_pll_locked (up_rx_pll_locked_18), + .up_rx_rst (up_rx_rst_18), + .up_rx_user_ready (up_rx_user_ready_18), + .up_rx_rst_done (up_rx_rst_done_18), + .up_rx_prbssel (up_rx_prbssel_18), + .up_rx_prbscntreset (up_rx_prbscntreset_18), + .up_rx_prbserr (up_rx_prbserr_18), + .up_rx_prbslocked (up_rx_prbslocked_18), + .up_rx_bufstatus (up_rx_bufstatus_18), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_18), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_18), + .up_rx_rate (up_rx_rate_18), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_18), + .up_rx_out_clk_sel (up_rx_out_clk_sel_18), + .up_rx_enb (up_rx_enb_18), + .up_rx_addr (up_rx_addr_18), + .up_rx_wr (up_rx_wr_18), + .up_rx_wdata (up_rx_wdata_18), + .up_rx_rdata (up_rx_rdata_18), + .up_rx_ready (up_rx_ready_18), + .up_tx_pll_locked (up_tx_pll_locked_18), + .up_tx_rst (up_tx_rst_18), + .up_tx_user_ready (up_tx_user_ready_18), + .up_tx_rst_done (up_tx_rst_done_18), + .up_tx_bufstatus (up_tx_bufstatus_18), + .up_tx_prbsforceerr (up_tx_prbsforceerr_18), + .up_tx_prbssel (up_tx_prbssel_18), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_18), + .up_tx_rate (up_tx_rate_18), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_18), + .up_tx_out_clk_sel (up_tx_out_clk_sel_18), + .up_tx_diffctrl (up_tx_diffctrl_18), + .up_tx_postcursor (up_tx_postcursor_18), + .up_tx_precursor (up_tx_precursor_18), + .up_tx_enb (up_tx_enb_18), + .up_tx_addr (up_tx_addr_18), + .up_tx_wr (up_tx_wr_18), + .up_tx_wdata (up_tx_wdata_18), + .up_tx_rdata (up_tx_rdata_18), + .up_tx_ready (up_tx_ready_18)); + end else begin + assign rx_out_clk_18 = 1'd0; + assign rx_charisk_18 = 4'd0; + assign rx_disperr_18 = 4'd0; + assign rx_notintable_18 = 4'd0; + assign rx_data_18 = 32'd0; + assign tx_18_p = 1'd0; + assign tx_18_n = 1'd0; + assign tx_out_clk_18 = 1'd0; + assign up_es_rdata_18 = 16'd0; + assign up_es_ready_18 = 1'd0; + assign up_rx_pll_locked_18 = 1'd0; + assign up_rx_rst_done_18 = 1'd0; + assign up_rx_rdata_18 = 16'd0; + assign up_rx_ready_18 = 1'd0; + assign up_tx_pll_locked_18 = 1'd0; + assign up_tx_rst_done_18 = 1'd0; + assign up_tx_rdata_18 = 16'd0; + assign up_tx_ready_18 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 20) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 19) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 19) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_19 ( + .qpll2ch_clk (qpll2ch_clk_16), + .qpll2ch_ref_clk (qpll2ch_ref_clk_16), + .qpll2ch_locked (qpll2ch_locked_16), + .qpll1_clk (qpll1_clk_16), + .qpll1_ref_clk (qpll1_ref_clk_16), + .qpll1_locked (qpll1_locked_16), + .cpll_ref_clk (cpll_ref_clk_19), + .up_cpll_rst (up_cpll_rst_19), + .rx_p (rx_19_p), + .rx_n (rx_19_n), + .rx_out_clk (rx_out_clk_19), + .rx_out_clk_div2 (rx_out_clk_div2_19), + .rx_clk (rx_clk_19), + .rx_clk_2x (rx_clk_2x_19), + .rx_charisk (rx_charisk_19), + .rx_disperr (rx_disperr_19), + .rx_notintable (rx_notintable_19), + .rx_data (rx_data_19), + .rx_calign (rx_calign_19), + .rx_header(rx_header_19), + .rx_block_sync(rx_block_sync_19), + .tx_p (tx_19_p), + .tx_n (tx_19_n), + .tx_out_clk (tx_out_clk_19), + .tx_out_clk_div2 (tx_out_clk_div2_19), + .tx_clk (tx_clk_19), + .tx_clk_2x (tx_clk_2x_19), + .tx_charisk (tx_charisk_19), + .tx_data (tx_data_19), + .tx_header (tx_header_19), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_19), + .up_es_addr (up_es_addr_19), + .up_es_wr (up_es_wr_19), + .up_es_wdata (up_es_wdata_19), + .up_es_rdata (up_es_rdata_19), + .up_es_ready (up_es_ready_19), + .up_es_reset (up_es_reset_19), + .up_rx_pll_locked (up_rx_pll_locked_19), + .up_rx_rst (up_rx_rst_19), + .up_rx_user_ready (up_rx_user_ready_19), + .up_rx_rst_done (up_rx_rst_done_19), + .up_rx_prbssel (up_rx_prbssel_19), + .up_rx_prbscntreset (up_rx_prbscntreset_19), + .up_rx_prbserr (up_rx_prbserr_19), + .up_rx_prbslocked (up_rx_prbslocked_19), + .up_rx_bufstatus (up_rx_bufstatus_19), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_19), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_19), + .up_rx_rate (up_rx_rate_19), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_19), + .up_rx_out_clk_sel (up_rx_out_clk_sel_19), + .up_rx_enb (up_rx_enb_19), + .up_rx_addr (up_rx_addr_19), + .up_rx_wr (up_rx_wr_19), + .up_rx_wdata (up_rx_wdata_19), + .up_rx_rdata (up_rx_rdata_19), + .up_rx_ready (up_rx_ready_19), + .up_tx_pll_locked (up_tx_pll_locked_19), + .up_tx_rst (up_tx_rst_19), + .up_tx_user_ready (up_tx_user_ready_19), + .up_tx_rst_done (up_tx_rst_done_19), + .up_tx_bufstatus (up_tx_bufstatus_19), + .up_tx_prbsforceerr (up_tx_prbsforceerr_19), + .up_tx_prbssel (up_tx_prbssel_19), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_19), + .up_tx_rate (up_tx_rate_19), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_19), + .up_tx_out_clk_sel (up_tx_out_clk_sel_19), + .up_tx_diffctrl (up_tx_diffctrl_19), + .up_tx_postcursor (up_tx_postcursor_19), + .up_tx_precursor (up_tx_precursor_19), + .up_tx_enb (up_tx_enb_19), + .up_tx_addr (up_tx_addr_19), + .up_tx_wr (up_tx_wr_19), + .up_tx_wdata (up_tx_wdata_19), + .up_tx_rdata (up_tx_rdata_19), + .up_tx_ready (up_tx_ready_19)); + end else begin + assign rx_out_clk_19 = 1'd0; + assign rx_charisk_19 = 4'd0; + assign rx_disperr_19 = 4'd0; + assign rx_notintable_19 = 4'd0; + assign rx_data_19 = 32'd0; + assign tx_19_p = 1'd0; + assign tx_19_n = 1'd0; + assign tx_out_clk_19 = 1'd0; + assign up_es_rdata_19 = 16'd0; + assign up_es_ready_19 = 1'd0; + assign up_rx_pll_locked_19 = 1'd0; + assign up_rx_rst_done_19 = 1'd0; + assign up_rx_rdata_19 = 16'd0; + assign up_rx_ready_19 = 1'd0; + assign up_tx_pll_locked_19 = 1'd0; + assign up_tx_rst_done_19 = 1'd0; + assign up_tx_rdata_19 = 16'd0; + assign up_tx_ready_19 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 21) begin + util_adxcvr_xcm #( + .XCVR_TYPE (XCVR_TYPE), + .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .POR_CFG (POR_CFG), + .PPF0_CFG (PPF0_CFG), + .PPF1_CFG (PPF1_CFG), + .QPLL_CFG (QPLL_CFG), + .QPLL_FBDIV (QPLL_FBDIV), + .QPLL_CFG0 (QPLL_CFG0), + .QPLL_CFG1 (QPLL_CFG1), + .QPLL_CFG1_G3 (QPLL_CFG1_G3), + .QPLL_CFG2 (QPLL_CFG2), + .QPLL_CFG2_G3 (QPLL_CFG2_G3), + .QPLL_CFG3 (QPLL_CFG3), + .QPLL_CP_G3 (QPLL_CP_G3), + .QPLL_LPF (QPLL_LPF), + .QPLL_CP (QPLL_CP), + .QPLL_CFG4 (QPLL_CFG4) + ) i_xcm_20 ( + .qpll_ref_clk (qpll_ref_clk_20), + .qpll_sel (qpll_sel_20), + .qpll2ch_clk (qpll2ch_clk_20), + .qpll2ch_ref_clk (qpll2ch_ref_clk_20), + .qpll2ch_locked (qpll2ch_locked_20), + .qpll1_clk (qpll1_clk_20), + .qpll1_ref_clk (qpll1_ref_clk_20), + .qpll1_locked (qpll1_locked_20), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_qpll_rst (up_qpll_rst_20), + .up_cm_enb (up_cm_enb_20), + .up_cm_addr (up_cm_addr_20), + .up_cm_wr (up_cm_wr_20), + .up_cm_wdata (up_cm_wdata_20), + .up_cm_rdata (up_cm_rdata_20), + .up_cm_ready (up_cm_ready_20)); + end else begin + assign qpll2ch_clk_20 = 1'd0; + assign qpll2ch_ref_clk_20 = 1'd0; + assign qpll2ch_locked_20 = 1'd0; + assign qpll1_clk_20 = 1'd0; + assign qpll1_ref_clk_20 = 1'd0; + assign qpll1_locked_20 = 1'd0; + assign up_cm_rdata_20 = 16'd0; + assign up_cm_ready_20 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 21) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 20) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 20) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_20 ( + .qpll2ch_clk (qpll2ch_clk_20), + .qpll2ch_ref_clk (qpll2ch_ref_clk_20), + .qpll2ch_locked (qpll2ch_locked_20), + .qpll1_clk (qpll1_clk_20), + .qpll1_ref_clk (qpll1_ref_clk_20), + .qpll1_locked (qpll1_locked_20), + .cpll_ref_clk (cpll_ref_clk_20), + .up_cpll_rst (up_cpll_rst_20), + .rx_p (rx_20_p), + .rx_n (rx_20_n), + .rx_out_clk (rx_out_clk_20), + .rx_out_clk_div2 (rx_out_clk_div2_20), + .rx_clk (rx_clk_20), + .rx_clk_2x (rx_clk_2x_20), + .rx_charisk (rx_charisk_20), + .rx_disperr (rx_disperr_20), + .rx_notintable (rx_notintable_20), + .rx_data (rx_data_20), + .rx_calign (rx_calign_20), + .rx_header(rx_header_20), + .rx_block_sync(rx_block_sync_20), + .tx_p (tx_20_p), + .tx_n (tx_20_n), + .tx_out_clk (tx_out_clk_20), + .tx_out_clk_div2 (tx_out_clk_div2_20), + .tx_clk (tx_clk_20), + .tx_clk_2x (tx_clk_2x_20), + .tx_charisk (tx_charisk_20), + .tx_data (tx_data_20), + .tx_header (tx_header_20), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_20), + .up_es_addr (up_es_addr_20), + .up_es_wr (up_es_wr_20), + .up_es_wdata (up_es_wdata_20), + .up_es_rdata (up_es_rdata_20), + .up_es_ready (up_es_ready_20), + .up_es_reset (up_es_reset_20), + .up_rx_pll_locked (up_rx_pll_locked_20), + .up_rx_rst (up_rx_rst_20), + .up_rx_user_ready (up_rx_user_ready_20), + .up_rx_rst_done (up_rx_rst_done_20), + .up_rx_prbssel (up_rx_prbssel_20), + .up_rx_prbscntreset (up_rx_prbscntreset_20), + .up_rx_prbserr (up_rx_prbserr_20), + .up_rx_prbslocked (up_rx_prbslocked_20), + .up_rx_bufstatus (up_rx_bufstatus_20), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_20), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_20), + .up_rx_rate (up_rx_rate_20), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_20), + .up_rx_out_clk_sel (up_rx_out_clk_sel_20), + .up_rx_enb (up_rx_enb_20), + .up_rx_addr (up_rx_addr_20), + .up_rx_wr (up_rx_wr_20), + .up_rx_wdata (up_rx_wdata_20), + .up_rx_rdata (up_rx_rdata_20), + .up_rx_ready (up_rx_ready_20), + .up_tx_pll_locked (up_tx_pll_locked_20), + .up_tx_rst (up_tx_rst_20), + .up_tx_user_ready (up_tx_user_ready_20), + .up_tx_rst_done (up_tx_rst_done_20), + .up_tx_bufstatus (up_tx_bufstatus_20), + .up_tx_prbsforceerr (up_tx_prbsforceerr_20), + .up_tx_prbssel (up_tx_prbssel_20), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_20), + .up_tx_rate (up_tx_rate_20), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_20), + .up_tx_out_clk_sel (up_tx_out_clk_sel_20), + .up_tx_diffctrl (up_tx_diffctrl_20), + .up_tx_postcursor (up_tx_postcursor_20), + .up_tx_precursor (up_tx_precursor_20), + .up_tx_enb (up_tx_enb_20), + .up_tx_addr (up_tx_addr_20), + .up_tx_wr (up_tx_wr_20), + .up_tx_wdata (up_tx_wdata_20), + .up_tx_rdata (up_tx_rdata_20), + .up_tx_ready (up_tx_ready_20)); + end else begin + assign rx_out_clk_20 = 1'd0; + assign rx_charisk_20 = 4'd0; + assign rx_disperr_20 = 4'd0; + assign rx_notintable_20 = 4'd0; + assign rx_data_20 = 32'd0; + assign tx_20_p = 1'd0; + assign tx_20_n = 1'd0; + assign tx_out_clk_20 = 1'd0; + assign up_es_rdata_20 = 16'd0; + assign up_es_ready_20 = 1'd0; + assign up_rx_pll_locked_20 = 1'd0; + assign up_rx_rst_done_20 = 1'd0; + assign up_rx_rdata_20 = 16'd0; + assign up_rx_ready_20 = 1'd0; + assign up_tx_pll_locked_20 = 1'd0; + assign up_tx_rst_done_20 = 1'd0; + assign up_tx_rdata_20 = 16'd0; + assign up_tx_ready_20 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 22) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 21) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 21) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_21 ( + .qpll2ch_clk (qpll2ch_clk_20), + .qpll2ch_ref_clk (qpll2ch_ref_clk_20), + .qpll2ch_locked (qpll2ch_locked_20), + .qpll1_clk (qpll1_clk_20), + .qpll1_ref_clk (qpll1_ref_clk_20), + .qpll1_locked (qpll1_locked_20), + .cpll_ref_clk (cpll_ref_clk_21), + .up_cpll_rst (up_cpll_rst_21), + .rx_p (rx_21_p), + .rx_n (rx_21_n), + .rx_out_clk (rx_out_clk_21), + .rx_out_clk_div2 (rx_out_clk_div2_21), + .rx_clk (rx_clk_21), + .rx_clk_2x (rx_clk_2x_21), + .rx_charisk (rx_charisk_21), + .rx_disperr (rx_disperr_21), + .rx_notintable (rx_notintable_21), + .rx_data (rx_data_21), + .rx_calign (rx_calign_21), + .rx_header(rx_header_21), + .rx_block_sync(rx_block_sync_21), + .tx_p (tx_21_p), + .tx_n (tx_21_n), + .tx_out_clk (tx_out_clk_21), + .tx_out_clk_div2 (tx_out_clk_div2_21), + .tx_clk (tx_clk_21), + .tx_clk_2x (tx_clk_2x_21), + .tx_charisk (tx_charisk_21), + .tx_data (tx_data_21), + .tx_header (tx_header_21), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_21), + .up_es_addr (up_es_addr_21), + .up_es_wr (up_es_wr_21), + .up_es_wdata (up_es_wdata_21), + .up_es_rdata (up_es_rdata_21), + .up_es_ready (up_es_ready_21), + .up_es_reset (up_es_reset_21), + .up_rx_pll_locked (up_rx_pll_locked_21), + .up_rx_rst (up_rx_rst_21), + .up_rx_user_ready (up_rx_user_ready_21), + .up_rx_rst_done (up_rx_rst_done_21), + .up_rx_prbssel (up_rx_prbssel_21), + .up_rx_prbscntreset (up_rx_prbscntreset_21), + .up_rx_prbserr (up_rx_prbserr_21), + .up_rx_prbslocked (up_rx_prbslocked_21), + .up_rx_bufstatus (up_rx_bufstatus_21), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_21), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_21), + .up_rx_rate (up_rx_rate_21), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_21), + .up_rx_out_clk_sel (up_rx_out_clk_sel_21), + .up_rx_enb (up_rx_enb_21), + .up_rx_addr (up_rx_addr_21), + .up_rx_wr (up_rx_wr_21), + .up_rx_wdata (up_rx_wdata_21), + .up_rx_rdata (up_rx_rdata_21), + .up_rx_ready (up_rx_ready_21), + .up_tx_pll_locked (up_tx_pll_locked_21), + .up_tx_rst (up_tx_rst_21), + .up_tx_user_ready (up_tx_user_ready_21), + .up_tx_rst_done (up_tx_rst_done_21), + .up_tx_bufstatus (up_tx_bufstatus_21), + .up_tx_prbsforceerr (up_tx_prbsforceerr_21), + .up_tx_prbssel (up_tx_prbssel_21), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_21), + .up_tx_rate (up_tx_rate_21), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_21), + .up_tx_out_clk_sel (up_tx_out_clk_sel_21), + .up_tx_diffctrl (up_tx_diffctrl_21), + .up_tx_postcursor (up_tx_postcursor_21), + .up_tx_precursor (up_tx_precursor_21), + .up_tx_enb (up_tx_enb_21), + .up_tx_addr (up_tx_addr_21), + .up_tx_wr (up_tx_wr_21), + .up_tx_wdata (up_tx_wdata_21), + .up_tx_rdata (up_tx_rdata_21), + .up_tx_ready (up_tx_ready_21)); + end else begin + assign rx_out_clk_21 = 1'd0; + assign rx_charisk_21 = 4'd0; + assign rx_disperr_21 = 4'd0; + assign rx_notintable_21 = 4'd0; + assign rx_data_21 = 32'd0; + assign tx_21_p = 1'd0; + assign tx_21_n = 1'd0; + assign tx_out_clk_21 = 1'd0; + assign up_es_rdata_21 = 16'd0; + assign up_es_ready_21 = 1'd0; + assign up_rx_pll_locked_21 = 1'd0; + assign up_rx_rst_done_21 = 1'd0; + assign up_rx_rdata_21 = 16'd0; + assign up_rx_ready_21 = 1'd0; + assign up_tx_pll_locked_21 = 1'd0; + assign up_tx_rst_done_21 = 1'd0; + assign up_tx_rdata_21 = 16'd0; + assign up_tx_ready_21 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 23) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 22) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 22) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_22 ( + .qpll2ch_clk (qpll2ch_clk_20), + .qpll2ch_ref_clk (qpll2ch_ref_clk_20), + .qpll2ch_locked (qpll2ch_locked_20), + .qpll1_clk (qpll1_clk_20), + .qpll1_ref_clk (qpll1_ref_clk_20), + .qpll1_locked (qpll1_locked_20), + .cpll_ref_clk (cpll_ref_clk_22), + .up_cpll_rst (up_cpll_rst_22), + .rx_p (rx_22_p), + .rx_n (rx_22_n), + .rx_out_clk (rx_out_clk_22), + .rx_out_clk_div2 (rx_out_clk_div2_22), + .rx_clk (rx_clk_22), + .rx_clk_2x (rx_clk_2x_22), + .rx_charisk (rx_charisk_22), + .rx_disperr (rx_disperr_22), + .rx_notintable (rx_notintable_22), + .rx_data (rx_data_22), + .rx_calign (rx_calign_22), + .rx_header(rx_header_22), + .rx_block_sync(rx_block_sync_22), + .tx_p (tx_22_p), + .tx_n (tx_22_n), + .tx_out_clk (tx_out_clk_22), + .tx_out_clk_div2 (tx_out_clk_div2_22), + .tx_clk (tx_clk_22), + .tx_clk_2x (tx_clk_2x_22), + .tx_charisk (tx_charisk_22), + .tx_data (tx_data_22), + .tx_header (tx_header_22), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_22), + .up_es_addr (up_es_addr_22), + .up_es_wr (up_es_wr_22), + .up_es_wdata (up_es_wdata_22), + .up_es_rdata (up_es_rdata_22), + .up_es_ready (up_es_ready_22), + .up_es_reset (up_es_reset_22), + .up_rx_pll_locked (up_rx_pll_locked_22), + .up_rx_rst (up_rx_rst_22), + .up_rx_user_ready (up_rx_user_ready_22), + .up_rx_rst_done (up_rx_rst_done_22), + .up_rx_prbssel (up_rx_prbssel_22), + .up_rx_prbscntreset (up_rx_prbscntreset_22), + .up_rx_prbserr (up_rx_prbserr_22), + .up_rx_prbslocked (up_rx_prbslocked_22), + .up_rx_bufstatus (up_rx_bufstatus_22), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_22), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_22), + .up_rx_rate (up_rx_rate_22), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_22), + .up_rx_out_clk_sel (up_rx_out_clk_sel_22), + .up_rx_enb (up_rx_enb_22), + .up_rx_addr (up_rx_addr_22), + .up_rx_wr (up_rx_wr_22), + .up_rx_wdata (up_rx_wdata_22), + .up_rx_rdata (up_rx_rdata_22), + .up_rx_ready (up_rx_ready_22), + .up_tx_pll_locked (up_tx_pll_locked_22), + .up_tx_rst (up_tx_rst_22), + .up_tx_user_ready (up_tx_user_ready_22), + .up_tx_rst_done (up_tx_rst_done_22), + .up_tx_bufstatus (up_tx_bufstatus_22), + .up_tx_prbsforceerr (up_tx_prbsforceerr_22), + .up_tx_prbssel (up_tx_prbssel_22), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_22), + .up_tx_rate (up_tx_rate_22), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_22), + .up_tx_out_clk_sel (up_tx_out_clk_sel_22), + .up_tx_diffctrl (up_tx_diffctrl_22), + .up_tx_postcursor (up_tx_postcursor_22), + .up_tx_precursor (up_tx_precursor_22), + .up_tx_enb (up_tx_enb_22), + .up_tx_addr (up_tx_addr_22), + .up_tx_wr (up_tx_wr_22), + .up_tx_wdata (up_tx_wdata_22), + .up_tx_rdata (up_tx_rdata_22), + .up_tx_ready (up_tx_ready_22)); + end else begin + assign rx_out_clk_22 = 1'd0; + assign rx_charisk_22 = 4'd0; + assign rx_disperr_22 = 4'd0; + assign rx_notintable_22 = 4'd0; + assign rx_data_22 = 32'd0; + assign tx_22_p = 1'd0; + assign tx_22_n = 1'd0; + assign tx_out_clk_22 = 1'd0; + assign up_es_rdata_22 = 16'd0; + assign up_es_ready_22 = 1'd0; + assign up_rx_pll_locked_22 = 1'd0; + assign up_rx_rst_done_22 = 1'd0; + assign up_rx_rdata_22 = 16'd0; + assign up_rx_ready_22 = 1'd0; + assign up_tx_pll_locked_22 = 1'd0; + assign up_tx_rst_done_22 = 1'd0; + assign up_tx_rdata_22 = 16'd0; + assign up_tx_ready_22 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 24) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 23) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 23) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_23 ( + .qpll2ch_clk (qpll2ch_clk_20), + .qpll2ch_ref_clk (qpll2ch_ref_clk_20), + .qpll2ch_locked (qpll2ch_locked_20), + .qpll1_clk (qpll1_clk_20), + .qpll1_ref_clk (qpll1_ref_clk_20), + .qpll1_locked (qpll1_locked_20), + .cpll_ref_clk (cpll_ref_clk_23), + .up_cpll_rst (up_cpll_rst_23), + .rx_p (rx_23_p), + .rx_n (rx_23_n), + .rx_out_clk (rx_out_clk_23), + .rx_out_clk_div2 (rx_out_clk_div2_23), + .rx_clk (rx_clk_23), + .rx_clk_2x (rx_clk_2x_23), + .rx_charisk (rx_charisk_23), + .rx_disperr (rx_disperr_23), + .rx_notintable (rx_notintable_23), + .rx_data (rx_data_23), + .rx_calign (rx_calign_23), + .rx_header(rx_header_23), + .rx_block_sync(rx_block_sync_23), + .tx_p (tx_23_p), + .tx_n (tx_23_n), + .tx_out_clk (tx_out_clk_23), + .tx_out_clk_div2 (tx_out_clk_div2_23), + .tx_clk (tx_clk_23), + .tx_clk_2x (tx_clk_2x_23), + .tx_charisk (tx_charisk_23), + .tx_data (tx_data_23), + .tx_header (tx_header_23), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_23), + .up_es_addr (up_es_addr_23), + .up_es_wr (up_es_wr_23), + .up_es_wdata (up_es_wdata_23), + .up_es_rdata (up_es_rdata_23), + .up_es_ready (up_es_ready_23), + .up_es_reset (up_es_reset_23), + .up_rx_pll_locked (up_rx_pll_locked_23), + .up_rx_rst (up_rx_rst_23), + .up_rx_user_ready (up_rx_user_ready_23), + .up_rx_rst_done (up_rx_rst_done_23), + .up_rx_prbssel (up_rx_prbssel_23), + .up_rx_prbscntreset (up_rx_prbscntreset_23), + .up_rx_prbserr (up_rx_prbserr_23), + .up_rx_prbslocked (up_rx_prbslocked_23), + .up_rx_bufstatus (up_rx_bufstatus_23), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_23), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_23), + .up_rx_rate (up_rx_rate_23), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_23), + .up_rx_out_clk_sel (up_rx_out_clk_sel_23), + .up_rx_enb (up_rx_enb_23), + .up_rx_addr (up_rx_addr_23), + .up_rx_wr (up_rx_wr_23), + .up_rx_wdata (up_rx_wdata_23), + .up_rx_rdata (up_rx_rdata_23), + .up_rx_ready (up_rx_ready_23), + .up_tx_pll_locked (up_tx_pll_locked_23), + .up_tx_rst (up_tx_rst_23), + .up_tx_user_ready (up_tx_user_ready_23), + .up_tx_rst_done (up_tx_rst_done_23), + .up_tx_bufstatus (up_tx_bufstatus_23), + .up_tx_prbsforceerr (up_tx_prbsforceerr_23), + .up_tx_prbssel (up_tx_prbssel_23), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_23), + .up_tx_rate (up_tx_rate_23), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_23), + .up_tx_out_clk_sel (up_tx_out_clk_sel_23), + .up_tx_diffctrl (up_tx_diffctrl_23), + .up_tx_postcursor (up_tx_postcursor_23), + .up_tx_precursor (up_tx_precursor_23), + .up_tx_enb (up_tx_enb_23), + .up_tx_addr (up_tx_addr_23), + .up_tx_wr (up_tx_wr_23), + .up_tx_wdata (up_tx_wdata_23), + .up_tx_rdata (up_tx_rdata_23), + .up_tx_ready (up_tx_ready_23)); + end else begin + assign rx_out_clk_23 = 1'd0; + assign rx_charisk_23 = 4'd0; + assign rx_disperr_23 = 4'd0; + assign rx_notintable_23 = 4'd0; + assign rx_data_23 = 32'd0; + assign tx_23_p = 1'd0; + assign tx_23_n = 1'd0; + assign tx_out_clk_23 = 1'd0; + assign up_es_rdata_23 = 16'd0; + assign up_es_ready_23 = 1'd0; + assign up_rx_pll_locked_23 = 1'd0; + assign up_rx_rst_done_23 = 1'd0; + assign up_rx_rdata_23 = 16'd0; + assign up_rx_ready_23 = 1'd0; + assign up_tx_pll_locked_23 = 1'd0; + assign up_tx_rst_done_23 = 1'd0; + assign up_tx_rdata_23 = 16'd0; + assign up_tx_ready_23 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 25) begin + util_adxcvr_xcm #( + .XCVR_TYPE (XCVR_TYPE), + .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .POR_CFG (POR_CFG), + .PPF0_CFG (PPF0_CFG), + .PPF1_CFG (PPF1_CFG), + .QPLL_CFG (QPLL_CFG), + .QPLL_FBDIV (QPLL_FBDIV), + .QPLL_CFG0 (QPLL_CFG0), + .QPLL_CFG1 (QPLL_CFG1), + .QPLL_CFG1_G3 (QPLL_CFG1_G3), + .QPLL_CFG2 (QPLL_CFG2), + .QPLL_CFG2_G3 (QPLL_CFG2_G3), + .QPLL_CFG3 (QPLL_CFG3), + .QPLL_CP_G3 (QPLL_CP_G3), + .QPLL_LPF (QPLL_LPF), + .QPLL_CP (QPLL_CP), + .QPLL_CFG4 (QPLL_CFG4) + ) i_xcm_24 ( + .qpll_ref_clk (qpll_ref_clk_24), + .qpll_sel (qpll_sel_24), + .qpll2ch_clk (qpll2ch_clk_24), + .qpll2ch_ref_clk (qpll2ch_ref_clk_24), + .qpll2ch_locked (qpll2ch_locked_24), + .qpll1_clk (qpll1_clk_24), + .qpll1_ref_clk (qpll1_ref_clk_24), + .qpll1_locked (qpll1_locked_24), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_qpll_rst (up_qpll_rst_24), + .up_cm_enb (up_cm_enb_24), + .up_cm_addr (up_cm_addr_24), + .up_cm_wr (up_cm_wr_24), + .up_cm_wdata (up_cm_wdata_24), + .up_cm_rdata (up_cm_rdata_24), + .up_cm_ready (up_cm_ready_24)); + end else begin + assign qpll2ch_clk_24 = 1'd0; + assign qpll2ch_ref_clk_24 = 1'd0; + assign qpll2ch_locked_24 = 1'd0; + assign qpll1_clk_24 = 1'd0; + assign qpll1_ref_clk_24 = 1'd0; + assign qpll1_locked_24 = 1'd0; + assign up_cm_rdata_24 = 16'd0; + assign up_cm_ready_24 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 25) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 24) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 24) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_24 ( + .qpll2ch_clk (qpll2ch_clk_24), + .qpll2ch_ref_clk (qpll2ch_ref_clk_24), + .qpll2ch_locked (qpll2ch_locked_24), + .qpll1_clk (qpll1_clk_24), + .qpll1_ref_clk (qpll1_ref_clk_24), + .qpll1_locked (qpll1_locked_24), + .cpll_ref_clk (cpll_ref_clk_24), + .up_cpll_rst (up_cpll_rst_24), + .rx_p (rx_24_p), + .rx_n (rx_24_n), + .rx_out_clk (rx_out_clk_24), + .rx_out_clk_div2 (rx_out_clk_div2_24), + .rx_clk (rx_clk_24), + .rx_clk_2x (rx_clk_2x_24), + .rx_charisk (rx_charisk_24), + .rx_disperr (rx_disperr_24), + .rx_notintable (rx_notintable_24), + .rx_data (rx_data_24), + .rx_calign (rx_calign_24), + .rx_header(rx_header_24), + .rx_block_sync(rx_block_sync_24), + .tx_p (tx_24_p), + .tx_n (tx_24_n), + .tx_out_clk (tx_out_clk_24), + .tx_out_clk_div2 (tx_out_clk_div2_24), + .tx_clk (tx_clk_24), + .tx_clk_2x (tx_clk_2x_24), + .tx_charisk (tx_charisk_24), + .tx_data (tx_data_24), + .tx_header (tx_header_24), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_24), + .up_es_addr (up_es_addr_24), + .up_es_wr (up_es_wr_24), + .up_es_wdata (up_es_wdata_24), + .up_es_rdata (up_es_rdata_24), + .up_es_ready (up_es_ready_24), + .up_es_reset (up_es_reset_24), + .up_rx_pll_locked (up_rx_pll_locked_24), + .up_rx_rst (up_rx_rst_24), + .up_rx_user_ready (up_rx_user_ready_24), + .up_rx_rst_done (up_rx_rst_done_24), + .up_rx_prbssel (up_rx_prbssel_24), + .up_rx_prbscntreset (up_rx_prbscntreset_24), + .up_rx_prbserr (up_rx_prbserr_24), + .up_rx_prbslocked (up_rx_prbslocked_24), + .up_rx_bufstatus (up_rx_bufstatus_24), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_24), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_24), + .up_rx_rate (up_rx_rate_24), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_24), + .up_rx_out_clk_sel (up_rx_out_clk_sel_24), + .up_rx_enb (up_rx_enb_24), + .up_rx_addr (up_rx_addr_24), + .up_rx_wr (up_rx_wr_24), + .up_rx_wdata (up_rx_wdata_24), + .up_rx_rdata (up_rx_rdata_24), + .up_rx_ready (up_rx_ready_24), + .up_tx_pll_locked (up_tx_pll_locked_24), + .up_tx_rst (up_tx_rst_24), + .up_tx_user_ready (up_tx_user_ready_24), + .up_tx_rst_done (up_tx_rst_done_24), + .up_tx_bufstatus (up_tx_bufstatus_24), + .up_tx_prbsforceerr (up_tx_prbsforceerr_24), + .up_tx_prbssel (up_tx_prbssel_24), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_24), + .up_tx_rate (up_tx_rate_24), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_24), + .up_tx_out_clk_sel (up_tx_out_clk_sel_24), + .up_tx_diffctrl (up_tx_diffctrl_24), + .up_tx_postcursor (up_tx_postcursor_24), + .up_tx_precursor (up_tx_precursor_24), + .up_tx_enb (up_tx_enb_24), + .up_tx_addr (up_tx_addr_24), + .up_tx_wr (up_tx_wr_24), + .up_tx_wdata (up_tx_wdata_24), + .up_tx_rdata (up_tx_rdata_24), + .up_tx_ready (up_tx_ready_24)); + end else begin + assign rx_out_clk_24 = 1'd0; + assign rx_charisk_24 = 4'd0; + assign rx_disperr_24 = 4'd0; + assign rx_notintable_24 = 4'd0; + assign rx_data_24 = 32'd0; + assign tx_24_p = 1'd0; + assign tx_24_n = 1'd0; + assign tx_out_clk_24 = 1'd0; + assign up_es_rdata_24 = 16'd0; + assign up_es_ready_24 = 1'd0; + assign up_rx_pll_locked_24 = 1'd0; + assign up_rx_rst_done_24 = 1'd0; + assign up_rx_rdata_24 = 16'd0; + assign up_rx_ready_24 = 1'd0; + assign up_tx_pll_locked_24 = 1'd0; + assign up_tx_rst_done_24 = 1'd0; + assign up_tx_rdata_24 = 16'd0; + assign up_tx_ready_24 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 26) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 25) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 25) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_25 ( + .qpll2ch_clk (qpll2ch_clk_24), + .qpll2ch_ref_clk (qpll2ch_ref_clk_24), + .qpll2ch_locked (qpll2ch_locked_24), + .qpll1_clk (qpll1_clk_24), + .qpll1_ref_clk (qpll1_ref_clk_24), + .qpll1_locked (qpll1_locked_24), + .cpll_ref_clk (cpll_ref_clk_25), + .up_cpll_rst (up_cpll_rst_25), + .rx_p (rx_25_p), + .rx_n (rx_25_n), + .rx_out_clk (rx_out_clk_25), + .rx_out_clk_div2 (rx_out_clk_div2_25), + .rx_clk (rx_clk_25), + .rx_clk_2x (rx_clk_2x_25), + .rx_charisk (rx_charisk_25), + .rx_disperr (rx_disperr_25), + .rx_notintable (rx_notintable_25), + .rx_data (rx_data_25), + .rx_calign (rx_calign_25), + .rx_header(rx_header_25), + .rx_block_sync(rx_block_sync_25), + .tx_p (tx_25_p), + .tx_n (tx_25_n), + .tx_out_clk (tx_out_clk_25), + .tx_out_clk_div2 (tx_out_clk_div2_25), + .tx_clk (tx_clk_25), + .tx_clk_2x (tx_clk_2x_25), + .tx_charisk (tx_charisk_25), + .tx_data (tx_data_25), + .tx_header (tx_header_25), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_25), + .up_es_addr (up_es_addr_25), + .up_es_wr (up_es_wr_25), + .up_es_wdata (up_es_wdata_25), + .up_es_rdata (up_es_rdata_25), + .up_es_ready (up_es_ready_25), + .up_es_reset (up_es_reset_25), + .up_rx_pll_locked (up_rx_pll_locked_25), + .up_rx_rst (up_rx_rst_25), + .up_rx_user_ready (up_rx_user_ready_25), + .up_rx_rst_done (up_rx_rst_done_25), + .up_rx_prbssel (up_rx_prbssel_25), + .up_rx_prbscntreset (up_rx_prbscntreset_25), + .up_rx_prbserr (up_rx_prbserr_25), + .up_rx_prbslocked (up_rx_prbslocked_25), + .up_rx_bufstatus (up_rx_bufstatus_25), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_25), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_25), + .up_rx_rate (up_rx_rate_25), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_25), + .up_rx_out_clk_sel (up_rx_out_clk_sel_25), + .up_rx_enb (up_rx_enb_25), + .up_rx_addr (up_rx_addr_25), + .up_rx_wr (up_rx_wr_25), + .up_rx_wdata (up_rx_wdata_25), + .up_rx_rdata (up_rx_rdata_25), + .up_rx_ready (up_rx_ready_25), + .up_tx_pll_locked (up_tx_pll_locked_25), + .up_tx_rst (up_tx_rst_25), + .up_tx_user_ready (up_tx_user_ready_25), + .up_tx_rst_done (up_tx_rst_done_25), + .up_tx_bufstatus (up_tx_bufstatus_25), + .up_tx_prbsforceerr (up_tx_prbsforceerr_25), + .up_tx_prbssel (up_tx_prbssel_25), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_25), + .up_tx_rate (up_tx_rate_25), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_25), + .up_tx_out_clk_sel (up_tx_out_clk_sel_25), + .up_tx_diffctrl (up_tx_diffctrl_25), + .up_tx_postcursor (up_tx_postcursor_25), + .up_tx_precursor (up_tx_precursor_25), + .up_tx_enb (up_tx_enb_25), + .up_tx_addr (up_tx_addr_25), + .up_tx_wr (up_tx_wr_25), + .up_tx_wdata (up_tx_wdata_25), + .up_tx_rdata (up_tx_rdata_25), + .up_tx_ready (up_tx_ready_25)); + end else begin + assign rx_out_clk_25 = 1'd0; + assign rx_charisk_25 = 4'd0; + assign rx_disperr_25 = 4'd0; + assign rx_notintable_25 = 4'd0; + assign rx_data_25 = 32'd0; + assign tx_25_p = 1'd0; + assign tx_25_n = 1'd0; + assign tx_out_clk_25 = 1'd0; + assign up_es_rdata_25 = 16'd0; + assign up_es_ready_25 = 1'd0; + assign up_rx_pll_locked_25 = 1'd0; + assign up_rx_rst_done_25 = 1'd0; + assign up_rx_rdata_25 = 16'd0; + assign up_rx_ready_25 = 1'd0; + assign up_tx_pll_locked_25 = 1'd0; + assign up_tx_rst_done_25 = 1'd0; + assign up_tx_rdata_25 = 16'd0; + assign up_tx_ready_25 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 27) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 26) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 26) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_26 ( + .qpll2ch_clk (qpll2ch_clk_24), + .qpll2ch_ref_clk (qpll2ch_ref_clk_24), + .qpll2ch_locked (qpll2ch_locked_24), + .qpll1_clk (qpll1_clk_24), + .qpll1_ref_clk (qpll1_ref_clk_24), + .qpll1_locked (qpll1_locked_24), + .cpll_ref_clk (cpll_ref_clk_26), + .up_cpll_rst (up_cpll_rst_26), + .rx_p (rx_26_p), + .rx_n (rx_26_n), + .rx_out_clk (rx_out_clk_26), + .rx_out_clk_div2 (rx_out_clk_div2_26), + .rx_clk (rx_clk_26), + .rx_clk_2x (rx_clk_2x_26), + .rx_charisk (rx_charisk_26), + .rx_disperr (rx_disperr_26), + .rx_notintable (rx_notintable_26), + .rx_data (rx_data_26), + .rx_calign (rx_calign_26), + .rx_header(rx_header_26), + .rx_block_sync(rx_block_sync_26), + .tx_p (tx_26_p), + .tx_n (tx_26_n), + .tx_out_clk (tx_out_clk_26), + .tx_out_clk_div2 (tx_out_clk_div2_26), + .tx_clk (tx_clk_26), + .tx_clk_2x (tx_clk_2x_26), + .tx_charisk (tx_charisk_26), + .tx_data (tx_data_26), + .tx_header (tx_header_26), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_26), + .up_es_addr (up_es_addr_26), + .up_es_wr (up_es_wr_26), + .up_es_wdata (up_es_wdata_26), + .up_es_rdata (up_es_rdata_26), + .up_es_ready (up_es_ready_26), + .up_es_reset (up_es_reset_26), + .up_rx_pll_locked (up_rx_pll_locked_26), + .up_rx_rst (up_rx_rst_26), + .up_rx_user_ready (up_rx_user_ready_26), + .up_rx_rst_done (up_rx_rst_done_26), + .up_rx_prbssel (up_rx_prbssel_26), + .up_rx_prbscntreset (up_rx_prbscntreset_26), + .up_rx_prbserr (up_rx_prbserr_26), + .up_rx_prbslocked (up_rx_prbslocked_26), + .up_rx_bufstatus (up_rx_bufstatus_26), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_26), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_26), + .up_rx_rate (up_rx_rate_26), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_26), + .up_rx_out_clk_sel (up_rx_out_clk_sel_26), + .up_rx_enb (up_rx_enb_26), + .up_rx_addr (up_rx_addr_26), + .up_rx_wr (up_rx_wr_26), + .up_rx_wdata (up_rx_wdata_26), + .up_rx_rdata (up_rx_rdata_26), + .up_rx_ready (up_rx_ready_26), + .up_tx_pll_locked (up_tx_pll_locked_26), + .up_tx_rst (up_tx_rst_26), + .up_tx_user_ready (up_tx_user_ready_26), + .up_tx_rst_done (up_tx_rst_done_26), + .up_tx_bufstatus (up_tx_bufstatus_26), + .up_tx_prbsforceerr (up_tx_prbsforceerr_26), + .up_tx_prbssel (up_tx_prbssel_26), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_26), + .up_tx_rate (up_tx_rate_26), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_26), + .up_tx_out_clk_sel (up_tx_out_clk_sel_26), + .up_tx_diffctrl (up_tx_diffctrl_26), + .up_tx_postcursor (up_tx_postcursor_26), + .up_tx_precursor (up_tx_precursor_26), + .up_tx_enb (up_tx_enb_26), + .up_tx_addr (up_tx_addr_26), + .up_tx_wr (up_tx_wr_26), + .up_tx_wdata (up_tx_wdata_26), + .up_tx_rdata (up_tx_rdata_26), + .up_tx_ready (up_tx_ready_26)); + end else begin + assign rx_out_clk_26 = 1'd0; + assign rx_charisk_26 = 4'd0; + assign rx_disperr_26 = 4'd0; + assign rx_notintable_26 = 4'd0; + assign rx_data_26 = 32'd0; + assign tx_26_p = 1'd0; + assign tx_26_n = 1'd0; + assign tx_out_clk_26 = 1'd0; + assign up_es_rdata_26 = 16'd0; + assign up_es_ready_26 = 1'd0; + assign up_rx_pll_locked_26 = 1'd0; + assign up_rx_rst_done_26 = 1'd0; + assign up_rx_rdata_26 = 16'd0; + assign up_rx_ready_26 = 1'd0; + assign up_tx_pll_locked_26 = 1'd0; + assign up_tx_rst_done_26 = 1'd0; + assign up_tx_rdata_26 = 16'd0; + assign up_tx_ready_26 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 28) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 27) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 27) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_27 ( + .qpll2ch_clk (qpll2ch_clk_24), + .qpll2ch_ref_clk (qpll2ch_ref_clk_24), + .qpll2ch_locked (qpll2ch_locked_24), + .qpll1_clk (qpll1_clk_24), + .qpll1_ref_clk (qpll1_ref_clk_24), + .qpll1_locked (qpll1_locked_24), + .cpll_ref_clk (cpll_ref_clk_27), + .up_cpll_rst (up_cpll_rst_27), + .rx_p (rx_27_p), + .rx_n (rx_27_n), + .rx_out_clk (rx_out_clk_27), + .rx_out_clk_div2 (rx_out_clk_div2_27), + .rx_clk (rx_clk_27), + .rx_clk_2x (rx_clk_2x_27), + .rx_charisk (rx_charisk_27), + .rx_disperr (rx_disperr_27), + .rx_notintable (rx_notintable_27), + .rx_data (rx_data_27), + .rx_calign (rx_calign_27), + .rx_header(rx_header_27), + .rx_block_sync(rx_block_sync_27), + .tx_p (tx_27_p), + .tx_n (tx_27_n), + .tx_out_clk (tx_out_clk_27), + .tx_out_clk_div2 (tx_out_clk_div2_27), + .tx_clk (tx_clk_27), + .tx_clk_2x (tx_clk_2x_27), + .tx_charisk (tx_charisk_27), + .tx_data (tx_data_27), + .tx_header (tx_header_27), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_27), + .up_es_addr (up_es_addr_27), + .up_es_wr (up_es_wr_27), + .up_es_wdata (up_es_wdata_27), + .up_es_rdata (up_es_rdata_27), + .up_es_ready (up_es_ready_27), + .up_es_reset (up_es_reset_27), + .up_rx_pll_locked (up_rx_pll_locked_27), + .up_rx_rst (up_rx_rst_27), + .up_rx_user_ready (up_rx_user_ready_27), + .up_rx_rst_done (up_rx_rst_done_27), + .up_rx_prbssel (up_rx_prbssel_27), + .up_rx_prbscntreset (up_rx_prbscntreset_27), + .up_rx_prbserr (up_rx_prbserr_27), + .up_rx_prbslocked (up_rx_prbslocked_27), + .up_rx_bufstatus (up_rx_bufstatus_27), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_27), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_27), + .up_rx_rate (up_rx_rate_27), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_27), + .up_rx_out_clk_sel (up_rx_out_clk_sel_27), + .up_rx_enb (up_rx_enb_27), + .up_rx_addr (up_rx_addr_27), + .up_rx_wr (up_rx_wr_27), + .up_rx_wdata (up_rx_wdata_27), + .up_rx_rdata (up_rx_rdata_27), + .up_rx_ready (up_rx_ready_27), + .up_tx_pll_locked (up_tx_pll_locked_27), + .up_tx_rst (up_tx_rst_27), + .up_tx_user_ready (up_tx_user_ready_27), + .up_tx_rst_done (up_tx_rst_done_27), + .up_tx_bufstatus (up_tx_bufstatus_27), + .up_tx_prbsforceerr (up_tx_prbsforceerr_27), + .up_tx_prbssel (up_tx_prbssel_27), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_27), + .up_tx_rate (up_tx_rate_27), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_27), + .up_tx_out_clk_sel (up_tx_out_clk_sel_27), + .up_tx_diffctrl (up_tx_diffctrl_27), + .up_tx_postcursor (up_tx_postcursor_27), + .up_tx_precursor (up_tx_precursor_27), + .up_tx_enb (up_tx_enb_27), + .up_tx_addr (up_tx_addr_27), + .up_tx_wr (up_tx_wr_27), + .up_tx_wdata (up_tx_wdata_27), + .up_tx_rdata (up_tx_rdata_27), + .up_tx_ready (up_tx_ready_27)); + end else begin + assign rx_out_clk_27 = 1'd0; + assign rx_charisk_27 = 4'd0; + assign rx_disperr_27 = 4'd0; + assign rx_notintable_27 = 4'd0; + assign rx_data_27 = 32'd0; + assign tx_27_p = 1'd0; + assign tx_27_n = 1'd0; + assign tx_out_clk_27 = 1'd0; + assign up_es_rdata_27 = 16'd0; + assign up_es_ready_27 = 1'd0; + assign up_rx_pll_locked_27 = 1'd0; + assign up_rx_rst_done_27 = 1'd0; + assign up_rx_rdata_27 = 16'd0; + assign up_rx_ready_27 = 1'd0; + assign up_tx_pll_locked_27 = 1'd0; + assign up_tx_rst_done_27 = 1'd0; + assign up_tx_rdata_27 = 16'd0; + assign up_tx_ready_27 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 29) begin + util_adxcvr_xcm #( + .XCVR_TYPE (XCVR_TYPE), + .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .POR_CFG (POR_CFG), + .PPF0_CFG (PPF0_CFG), + .PPF1_CFG (PPF1_CFG), + .QPLL_CFG (QPLL_CFG), + .QPLL_FBDIV (QPLL_FBDIV), + .QPLL_CFG0 (QPLL_CFG0), + .QPLL_CFG1 (QPLL_CFG1), + .QPLL_CFG1_G3 (QPLL_CFG1_G3), + .QPLL_CFG2 (QPLL_CFG2), + .QPLL_CFG2_G3 (QPLL_CFG2_G3), + .QPLL_CFG3 (QPLL_CFG3), + .QPLL_CP_G3 (QPLL_CP_G3), + .QPLL_LPF (QPLL_LPF), + .QPLL_CP (QPLL_CP), + .QPLL_CFG4 (QPLL_CFG4) + ) i_xcm_28 ( + .qpll_ref_clk (qpll_ref_clk_28), + .qpll_sel (qpll_sel_28), + .qpll2ch_clk (qpll2ch_clk_28), + .qpll2ch_ref_clk (qpll2ch_ref_clk_28), + .qpll2ch_locked (qpll2ch_locked_28), + .qpll1_clk (qpll1_clk_28), + .qpll1_ref_clk (qpll1_ref_clk_28), + .qpll1_locked (qpll1_locked_28), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_qpll_rst (up_qpll_rst_28), + .up_cm_enb (up_cm_enb_28), + .up_cm_addr (up_cm_addr_28), + .up_cm_wr (up_cm_wr_28), + .up_cm_wdata (up_cm_wdata_28), + .up_cm_rdata (up_cm_rdata_28), + .up_cm_ready (up_cm_ready_28)); + end else begin + assign qpll2ch_clk_28 = 1'd0; + assign qpll2ch_ref_clk_28 = 1'd0; + assign qpll2ch_locked_28 = 1'd0; + assign qpll1_clk_28 = 1'd0; + assign qpll1_ref_clk_28 = 1'd0; + assign qpll1_locked_28 = 1'd0; + assign up_cm_rdata_28 = 16'd0; + assign up_cm_ready_28 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 29) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 28) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 28) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_28 ( + .qpll2ch_clk (qpll2ch_clk_28), + .qpll2ch_ref_clk (qpll2ch_ref_clk_28), + .qpll2ch_locked (qpll2ch_locked_28), + .qpll1_clk (qpll1_clk_28), + .qpll1_ref_clk (qpll1_ref_clk_28), + .qpll1_locked (qpll1_locked_28), + .cpll_ref_clk (cpll_ref_clk_28), + .up_cpll_rst (up_cpll_rst_28), + .rx_p (rx_28_p), + .rx_n (rx_28_n), + .rx_out_clk (rx_out_clk_28), + .rx_out_clk_div2 (rx_out_clk_div2_28), + .rx_clk (rx_clk_28), + .rx_clk_2x (rx_clk_2x_28), + .rx_charisk (rx_charisk_28), + .rx_disperr (rx_disperr_28), + .rx_notintable (rx_notintable_28), + .rx_data (rx_data_28), + .rx_calign (rx_calign_28), + .rx_header(rx_header_28), + .rx_block_sync(rx_block_sync_28), + .tx_p (tx_28_p), + .tx_n (tx_28_n), + .tx_out_clk (tx_out_clk_28), + .tx_out_clk_div2 (tx_out_clk_div2_28), + .tx_clk (tx_clk_28), + .tx_clk_2x (tx_clk_2x_28), + .tx_charisk (tx_charisk_28), + .tx_data (tx_data_28), + .tx_header (tx_header_28), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_28), + .up_es_addr (up_es_addr_28), + .up_es_wr (up_es_wr_28), + .up_es_wdata (up_es_wdata_28), + .up_es_rdata (up_es_rdata_28), + .up_es_ready (up_es_ready_28), + .up_es_reset (up_es_reset_28), + .up_rx_pll_locked (up_rx_pll_locked_28), + .up_rx_rst (up_rx_rst_28), + .up_rx_user_ready (up_rx_user_ready_28), + .up_rx_rst_done (up_rx_rst_done_28), + .up_rx_prbssel (up_rx_prbssel_28), + .up_rx_prbscntreset (up_rx_prbscntreset_28), + .up_rx_prbserr (up_rx_prbserr_28), + .up_rx_prbslocked (up_rx_prbslocked_28), + .up_rx_bufstatus (up_rx_bufstatus_28), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_28), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_28), + .up_rx_rate (up_rx_rate_28), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_28), + .up_rx_out_clk_sel (up_rx_out_clk_sel_28), + .up_rx_enb (up_rx_enb_28), + .up_rx_addr (up_rx_addr_28), + .up_rx_wr (up_rx_wr_28), + .up_rx_wdata (up_rx_wdata_28), + .up_rx_rdata (up_rx_rdata_28), + .up_rx_ready (up_rx_ready_28), + .up_tx_pll_locked (up_tx_pll_locked_28), + .up_tx_rst (up_tx_rst_28), + .up_tx_user_ready (up_tx_user_ready_28), + .up_tx_rst_done (up_tx_rst_done_28), + .up_tx_bufstatus (up_tx_bufstatus_28), + .up_tx_prbsforceerr (up_tx_prbsforceerr_28), + .up_tx_prbssel (up_tx_prbssel_28), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_28), + .up_tx_rate (up_tx_rate_28), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_28), + .up_tx_out_clk_sel (up_tx_out_clk_sel_28), + .up_tx_diffctrl (up_tx_diffctrl_28), + .up_tx_postcursor (up_tx_postcursor_28), + .up_tx_precursor (up_tx_precursor_28), + .up_tx_enb (up_tx_enb_28), + .up_tx_addr (up_tx_addr_28), + .up_tx_wr (up_tx_wr_28), + .up_tx_wdata (up_tx_wdata_28), + .up_tx_rdata (up_tx_rdata_28), + .up_tx_ready (up_tx_ready_28)); + end else begin + assign rx_out_clk_28 = 1'd0; + assign rx_charisk_28 = 4'd0; + assign rx_disperr_28 = 4'd0; + assign rx_notintable_28 = 4'd0; + assign rx_data_28 = 32'd0; + assign tx_28_p = 1'd0; + assign tx_28_n = 1'd0; + assign tx_out_clk_28 = 1'd0; + assign up_es_rdata_28 = 16'd0; + assign up_es_ready_28 = 1'd0; + assign up_rx_pll_locked_28 = 1'd0; + assign up_rx_rst_done_28 = 1'd0; + assign up_rx_rdata_28 = 16'd0; + assign up_rx_ready_28 = 1'd0; + assign up_tx_pll_locked_28 = 1'd0; + assign up_tx_rst_done_28 = 1'd0; + assign up_tx_rdata_28 = 16'd0; + assign up_tx_ready_28 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 30) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 29) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 29) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_29 ( + .qpll2ch_clk (qpll2ch_clk_28), + .qpll2ch_ref_clk (qpll2ch_ref_clk_28), + .qpll2ch_locked (qpll2ch_locked_28), + .qpll1_clk (qpll1_clk_28), + .qpll1_ref_clk (qpll1_ref_clk_28), + .qpll1_locked (qpll1_locked_28), + .cpll_ref_clk (cpll_ref_clk_29), + .up_cpll_rst (up_cpll_rst_29), + .rx_p (rx_29_p), + .rx_n (rx_29_n), + .rx_out_clk (rx_out_clk_29), + .rx_out_clk_div2 (rx_out_clk_div2_29), + .rx_clk (rx_clk_29), + .rx_clk_2x (rx_clk_2x_29), + .rx_charisk (rx_charisk_29), + .rx_disperr (rx_disperr_29), + .rx_notintable (rx_notintable_29), + .rx_data (rx_data_29), + .rx_calign (rx_calign_29), + .rx_header(rx_header_29), + .rx_block_sync(rx_block_sync_29), + .tx_p (tx_29_p), + .tx_n (tx_29_n), + .tx_out_clk (tx_out_clk_29), + .tx_out_clk_div2 (tx_out_clk_div2_29), + .tx_clk (tx_clk_29), + .tx_clk_2x (tx_clk_2x_29), + .tx_charisk (tx_charisk_29), + .tx_data (tx_data_29), + .tx_header (tx_header_29), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_29), + .up_es_addr (up_es_addr_29), + .up_es_wr (up_es_wr_29), + .up_es_wdata (up_es_wdata_29), + .up_es_rdata (up_es_rdata_29), + .up_es_ready (up_es_ready_29), + .up_es_reset (up_es_reset_29), + .up_rx_pll_locked (up_rx_pll_locked_29), + .up_rx_rst (up_rx_rst_29), + .up_rx_user_ready (up_rx_user_ready_29), + .up_rx_rst_done (up_rx_rst_done_29), + .up_rx_prbssel (up_rx_prbssel_29), + .up_rx_prbscntreset (up_rx_prbscntreset_29), + .up_rx_prbserr (up_rx_prbserr_29), + .up_rx_prbslocked (up_rx_prbslocked_29), + .up_rx_bufstatus (up_rx_bufstatus_29), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_29), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_29), + .up_rx_rate (up_rx_rate_29), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_29), + .up_rx_out_clk_sel (up_rx_out_clk_sel_29), + .up_rx_enb (up_rx_enb_29), + .up_rx_addr (up_rx_addr_29), + .up_rx_wr (up_rx_wr_29), + .up_rx_wdata (up_rx_wdata_29), + .up_rx_rdata (up_rx_rdata_29), + .up_rx_ready (up_rx_ready_29), + .up_tx_pll_locked (up_tx_pll_locked_29), + .up_tx_rst (up_tx_rst_29), + .up_tx_user_ready (up_tx_user_ready_29), + .up_tx_rst_done (up_tx_rst_done_29), + .up_tx_bufstatus (up_tx_bufstatus_29), + .up_tx_prbsforceerr (up_tx_prbsforceerr_29), + .up_tx_prbssel (up_tx_prbssel_29), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_29), + .up_tx_rate (up_tx_rate_29), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_29), + .up_tx_out_clk_sel (up_tx_out_clk_sel_29), + .up_tx_diffctrl (up_tx_diffctrl_29), + .up_tx_postcursor (up_tx_postcursor_29), + .up_tx_precursor (up_tx_precursor_29), + .up_tx_enb (up_tx_enb_29), + .up_tx_addr (up_tx_addr_29), + .up_tx_wr (up_tx_wr_29), + .up_tx_wdata (up_tx_wdata_29), + .up_tx_rdata (up_tx_rdata_29), + .up_tx_ready (up_tx_ready_29)); + end else begin + assign rx_out_clk_29 = 1'd0; + assign rx_charisk_29 = 4'd0; + assign rx_disperr_29 = 4'd0; + assign rx_notintable_29 = 4'd0; + assign rx_data_29 = 32'd0; + assign tx_29_p = 1'd0; + assign tx_29_n = 1'd0; + assign tx_out_clk_29 = 1'd0; + assign up_es_rdata_29 = 16'd0; + assign up_es_ready_29 = 1'd0; + assign up_rx_pll_locked_29 = 1'd0; + assign up_rx_rst_done_29 = 1'd0; + assign up_rx_rdata_29 = 16'd0; + assign up_rx_ready_29 = 1'd0; + assign up_tx_pll_locked_29 = 1'd0; + assign up_tx_rst_done_29 = 1'd0; + assign up_tx_rdata_29 = 16'd0; + assign up_tx_ready_29 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 31) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 30) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 30) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_30 ( + .qpll2ch_clk (qpll2ch_clk_28), + .qpll2ch_ref_clk (qpll2ch_ref_clk_28), + .qpll2ch_locked (qpll2ch_locked_28), + .qpll1_clk (qpll1_clk_28), + .qpll1_ref_clk (qpll1_ref_clk_28), + .qpll1_locked (qpll1_locked_28), + .cpll_ref_clk (cpll_ref_clk_30), + .up_cpll_rst (up_cpll_rst_30), + .rx_p (rx_30_p), + .rx_n (rx_30_n), + .rx_out_clk (rx_out_clk_30), + .rx_out_clk_div2 (rx_out_clk_div2_30), + .rx_clk (rx_clk_30), + .rx_clk_2x (rx_clk_2x_30), + .rx_charisk (rx_charisk_30), + .rx_disperr (rx_disperr_30), + .rx_notintable (rx_notintable_30), + .rx_data (rx_data_30), + .rx_calign (rx_calign_30), + .rx_header(rx_header_30), + .rx_block_sync(rx_block_sync_30), + .tx_p (tx_30_p), + .tx_n (tx_30_n), + .tx_out_clk (tx_out_clk_30), + .tx_out_clk_div2 (tx_out_clk_div2_30), + .tx_clk (tx_clk_30), + .tx_clk_2x (tx_clk_2x_30), + .tx_charisk (tx_charisk_30), + .tx_data (tx_data_30), + .tx_header (tx_header_30), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_30), + .up_es_addr (up_es_addr_30), + .up_es_wr (up_es_wr_30), + .up_es_wdata (up_es_wdata_30), + .up_es_rdata (up_es_rdata_30), + .up_es_ready (up_es_ready_30), + .up_es_reset (up_es_reset_30), + .up_rx_pll_locked (up_rx_pll_locked_30), + .up_rx_rst (up_rx_rst_30), + .up_rx_user_ready (up_rx_user_ready_30), + .up_rx_rst_done (up_rx_rst_done_30), + .up_rx_prbssel (up_rx_prbssel_30), + .up_rx_prbscntreset (up_rx_prbscntreset_30), + .up_rx_prbserr (up_rx_prbserr_30), + .up_rx_prbslocked (up_rx_prbslocked_30), + .up_rx_bufstatus (up_rx_bufstatus_30), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_30), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_30), + .up_rx_rate (up_rx_rate_30), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_30), + .up_rx_out_clk_sel (up_rx_out_clk_sel_30), + .up_rx_enb (up_rx_enb_30), + .up_rx_addr (up_rx_addr_30), + .up_rx_wr (up_rx_wr_30), + .up_rx_wdata (up_rx_wdata_30), + .up_rx_rdata (up_rx_rdata_30), + .up_rx_ready (up_rx_ready_30), + .up_tx_pll_locked (up_tx_pll_locked_30), + .up_tx_rst (up_tx_rst_30), + .up_tx_user_ready (up_tx_user_ready_30), + .up_tx_rst_done (up_tx_rst_done_30), + .up_tx_bufstatus (up_tx_bufstatus_30), + .up_tx_prbsforceerr (up_tx_prbsforceerr_30), + .up_tx_prbssel (up_tx_prbssel_30), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_30), + .up_tx_rate (up_tx_rate_30), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_30), + .up_tx_out_clk_sel (up_tx_out_clk_sel_30), + .up_tx_diffctrl (up_tx_diffctrl_30), + .up_tx_postcursor (up_tx_postcursor_30), + .up_tx_precursor (up_tx_precursor_30), + .up_tx_enb (up_tx_enb_30), + .up_tx_addr (up_tx_addr_30), + .up_tx_wr (up_tx_wr_30), + .up_tx_wdata (up_tx_wdata_30), + .up_tx_rdata (up_tx_rdata_30), + .up_tx_ready (up_tx_ready_30)); + end else begin + assign rx_out_clk_30 = 1'd0; + assign rx_charisk_30 = 4'd0; + assign rx_disperr_30 = 4'd0; + assign rx_notintable_30 = 4'd0; + assign rx_data_30 = 32'd0; + assign tx_30_p = 1'd0; + assign tx_30_n = 1'd0; + assign tx_out_clk_30 = 1'd0; + assign up_es_rdata_30 = 16'd0; + assign up_es_ready_30 = 1'd0; + assign up_rx_pll_locked_30 = 1'd0; + assign up_rx_rst_done_30 = 1'd0; + assign up_rx_rdata_30 = 16'd0; + assign up_rx_ready_30 = 1'd0; + assign up_tx_pll_locked_30 = 1'd0; + assign up_tx_rst_done_30 = 1'd0; + assign up_tx_rdata_30 = 16'd0; + assign up_tx_ready_30 = 1'd0; + end + endgenerate + + generate + if (NUM_OF_LANES >= 32) begin + util_adxcvr_xch #( + .XCVR_TYPE (XCVR_TYPE), + .LINK_MODE (LINK_MODE), + .DATA_PATH_WIDTH (DATA_PATH_WIDTH), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_4_5 (CPLL_FBDIV_4_5), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .TX_OUT_DIV (TX_OUT_DIV), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_POLARITY ((TX_LANE_INVERT >> 31) & 1), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TXPI_CFG (TXPI_CFG), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .RX_OUT_DIV (RX_OUT_DIV), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_PMA_CFG (RX_PMA_CFG), + .RX_CDR_CFG (RX_CDR_CFG), + .RX_POLARITY ((RX_LANE_INVERT >> 31) & 1), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_XMODE_SEL (RX_XMODE_SEL), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXSWBST_EN (TXSWBST_EN), + .CH_HSPMUX (CH_HSPMUX), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL) + ) i_xch_31 ( + .qpll2ch_clk (qpll2ch_clk_28), + .qpll2ch_ref_clk (qpll2ch_ref_clk_28), + .qpll2ch_locked (qpll2ch_locked_28), + .qpll1_clk (qpll1_clk_28), + .qpll1_ref_clk (qpll1_ref_clk_28), + .qpll1_locked (qpll1_locked_28), + .cpll_ref_clk (cpll_ref_clk_31), + .up_cpll_rst (up_cpll_rst_31), + .rx_p (rx_31_p), + .rx_n (rx_31_n), + .rx_out_clk (rx_out_clk_31), + .rx_out_clk_div2 (rx_out_clk_div2_31), + .rx_clk (rx_clk_31), + .rx_clk_2x (rx_clk_2x_31), + .rx_charisk (rx_charisk_31), + .rx_disperr (rx_disperr_31), + .rx_notintable (rx_notintable_31), + .rx_data (rx_data_31), + .rx_calign (rx_calign_31), + .rx_header(rx_header_31), + .rx_block_sync(rx_block_sync_31), + .tx_p (tx_31_p), + .tx_n (tx_31_n), + .tx_out_clk (tx_out_clk_31), + .tx_out_clk_div2 (tx_out_clk_div2_31), + .tx_clk (tx_clk_31), + .tx_clk_2x (tx_clk_2x_31), + .tx_charisk (tx_charisk_31), + .tx_data (tx_data_31), + .tx_header (tx_header_31), + .up_rstn (up_rstn), + .up_clk (up_clk), + .up_es_enb (up_es_enb_31), + .up_es_addr (up_es_addr_31), + .up_es_wr (up_es_wr_31), + .up_es_wdata (up_es_wdata_31), + .up_es_rdata (up_es_rdata_31), + .up_es_ready (up_es_ready_31), + .up_es_reset (up_es_reset_31), + .up_rx_pll_locked (up_rx_pll_locked_31), + .up_rx_rst (up_rx_rst_31), + .up_rx_user_ready (up_rx_user_ready_31), + .up_rx_rst_done (up_rx_rst_done_31), + .up_rx_prbssel (up_rx_prbssel_31), + .up_rx_prbscntreset (up_rx_prbscntreset_31), + .up_rx_prbserr (up_rx_prbserr_31), + .up_rx_prbslocked (up_rx_prbslocked_31), + .up_rx_bufstatus (up_rx_bufstatus_31), + .up_rx_bufstatus_rst (up_rx_bufstatus_rst_31), + .up_rx_lpm_dfe_n (up_rx_lpm_dfe_n_31), + .up_rx_rate (up_rx_rate_31), + .up_rx_sys_clk_sel (up_rx_sys_clk_sel_31), + .up_rx_out_clk_sel (up_rx_out_clk_sel_31), + .up_rx_enb (up_rx_enb_31), + .up_rx_addr (up_rx_addr_31), + .up_rx_wr (up_rx_wr_31), + .up_rx_wdata (up_rx_wdata_31), + .up_rx_rdata (up_rx_rdata_31), + .up_rx_ready (up_rx_ready_31), + .up_tx_pll_locked (up_tx_pll_locked_31), + .up_tx_rst (up_tx_rst_31), + .up_tx_user_ready (up_tx_user_ready_31), + .up_tx_rst_done (up_tx_rst_done_31), + .up_tx_bufstatus (up_tx_bufstatus_31), + .up_tx_prbsforceerr (up_tx_prbsforceerr_31), + .up_tx_prbssel (up_tx_prbssel_31), + .up_tx_lpm_dfe_n (up_tx_lpm_dfe_n_31), + .up_tx_rate (up_tx_rate_31), + .up_tx_sys_clk_sel (up_tx_sys_clk_sel_31), + .up_tx_out_clk_sel (up_tx_out_clk_sel_31), + .up_tx_diffctrl (up_tx_diffctrl_31), + .up_tx_postcursor (up_tx_postcursor_31), + .up_tx_precursor (up_tx_precursor_31), + .up_tx_enb (up_tx_enb_31), + .up_tx_addr (up_tx_addr_31), + .up_tx_wr (up_tx_wr_31), + .up_tx_wdata (up_tx_wdata_31), + .up_tx_rdata (up_tx_rdata_31), + .up_tx_ready (up_tx_ready_31)); + end else begin + assign rx_out_clk_31 = 1'd0; + assign rx_charisk_31 = 4'd0; + assign rx_disperr_31 = 4'd0; + assign rx_notintable_31 = 4'd0; + assign rx_data_31 = 32'd0; + assign tx_31_p = 1'd0; + assign tx_31_n = 1'd0; + assign tx_out_clk_31 = 1'd0; + assign up_es_rdata_31 = 16'd0; + assign up_es_ready_31 = 1'd0; + assign up_rx_pll_locked_31 = 1'd0; + assign up_rx_rst_done_31 = 1'd0; + assign up_rx_rdata_31 = 16'd0; + assign up_rx_ready_31 = 1'd0; + assign up_tx_pll_locked_31 = 1'd0; + assign up_tx_rst_done_31 = 1'd0; + assign up_tx_rdata_31 = 16'd0; + assign up_tx_ready_31 = 1'd0; + end + endgenerate + +endmodule diff --git a/adi_library/xilinx/util_adxcvr/util_adxcvr.xpr b/adi_library/xilinx/util_adxcvr/util_adxcvr.xpr new file mode 100644 index 00000000..8bac4c81 --- /dev/null +++ b/adi_library/xilinx/util_adxcvr/util_adxcvr.xpr @@ -0,0 +1,440 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/xilinx/util_adxcvr/util_adxcvr_constr.xdc b/adi_library/xilinx/util_adxcvr/util_adxcvr_constr.xdc new file mode 100644 index 00000000..58ed54f3 --- /dev/null +++ b/adi_library/xilinx/util_adxcvr/util_adxcvr_constr.xdc @@ -0,0 +1,44 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property ASYNC_REG TRUE -quiet [get_cells -hier -filter {name =~ *up_rx_rst_done*}] +set_property ASYNC_REG TRUE -quiet [get_cells -hier -filter {name =~ *up_tx_rst_done*}] +set_property ASYNC_REG TRUE -quiet [get_cells -hier -filter {name =~ *rx_rate*}] +set_property ASYNC_REG TRUE -quiet [get_cells -hier -filter {name =~ *tx_rate*}] + +set_false_path -to [get_cells -hier -filter {name =~ *up_rx_rst_done_m1_reg && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *up_tx_rst_done_m1_reg && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *rx_rate_m1_reg* && IS_SEQUENTIAL}] +set_false_path -to [get_cells -hier -filter {name =~ *tx_rate_m1_reg* && IS_SEQUENTIAL}] + +# sync bits i_sync_bits_tx_prbs_in +set_false_path \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_bits_tx_prbs_in* && IS_SEQUENTIAL} + ] + +# sync bits i_sync_bits_rx_prbs_in +set_false_path \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_bits_rx_prbs_in* && IS_SEQUENTIAL} + ] + +# sync bits i_sync_bits_rx_prbs_out +set_false_path \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_bits_rx_prbs_out* && IS_SEQUENTIAL} + ] + +# sync bits i_sync_bits_rx_bufstatus_in +set_false_path \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_bits_rx_bufstatus_in* && IS_SEQUENTIAL} + ] + +# sync bits i_sync_bits_bufstatus_out +set_false_path \ + -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \ + -filter {NAME =~ *i_sync_bits_bufstatus_out* && IS_SEQUENTIAL}] + \ No newline at end of file diff --git a/adi_library/xilinx/util_adxcvr/util_adxcvr_ip.tcl b/adi_library/xilinx/util_adxcvr/util_adxcvr_ip.tcl new file mode 100644 index 00000000..cacd0595 --- /dev/null +++ b/adi_library/xilinx/util_adxcvr/util_adxcvr_ip.tcl @@ -0,0 +1,2098 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +## AUTO GENERATED BY util_adxcvr.pl, DO NOT MODIFY! +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create util_adxcvr +adi_ip_files util_adxcvr [list \ + "$ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl" \ + "$ad_hdl_dir/library/jesd204/jesd204_common/sync_header_align.v" \ + "util_adxcvr_constr.xdc" \ + "util_adxcvr_xcm.v" \ + "util_adxcvr_xch.v" \ + "util_adxcvr.v" \ + "bd/bd.tcl" ] + +adi_ip_properties_lite util_adxcvr + +adi_ip_bd util_adxcvr "bd/bd.tcl" + +set_property company_url {https://wiki.analog.com/resources/fpga/docs/util_xcvr} [ipx::current_core] + +adi_ip_add_core_dependencies [list \ + analog.com:$VIVADO_IP_LIBRARY:util_cdc:1.0 \ +] +set cc [ipx::current_core] + +# Arrange GUI page layout +set page0 [ipgui::get_pagespec -name "Page 0" -component $cc] +# Link layer mode +set p [ipgui::get_guiparamspec -name "LINK_MODE" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $page0 +set_property -dict [list \ + "display_name" "Link Layer mode" \ + "tooltip" "Link Layer mode" \ + "widget" "comboBox" \ +] $p + +set_property -dict [list \ + value_validation_type pairs \ + value_validation_pairs {64B66B 2 8B10B 1} \ +] [ipx::get_user_parameters $p -of_objects $cc] + +# Data width selection +set param [ipx::get_user_parameters DATA_PATH_WIDTH -of_objects $cc] +set_property -dict [list \ + enablement_tcl_expr {$LINK_MODE==1} \ + value_tcl_expr {expr $LINK_MODE*4} \ +] $param + +set p [ipgui::get_guiparamspec -name "RX_LANE_RATE" -component $cc] +ipgui::move_param -component $cc -order 1 $p -parent $page0 +set_property -dict [list \ + display_name {Rx Lane Rate (Gbps)} \ + widget {textEdit} \ +] $p +set_property -dict [list \ + value_resolve_type user \ + value 12.5 \ + value_format float \ +] [ipx::get_user_parameters $p -of_objects $cc] + +set p [ipgui::get_guiparamspec -name "TX_LANE_RATE" -component $cc] +ipgui::move_param -component $cc -order 2 $p -parent $page0 +set_property -dict [list \ + display_name {Tx Lane Rate (Gbps)} \ + widget {textEdit} \ +] $p +set_property -dict [list \ + value_resolve_type user \ + value 12.5 \ + value_format float \ +] [ipx::get_user_parameters $p -of_objects $cc] + +ipx::remove_all_bus_interface [ipx::current_core] + +ipx::infer_bus_interface up_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + +for {set n 0} {$n < 32} {incr n} { + ipx::infer_bus_interface cpll_ref_clk_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interface rx_out_clk_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interface tx_out_clk_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interface rx_clk_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interface tx_clk_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + if {($n%4) == 0} { + ipx::infer_bus_interface qpll_ref_clk_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + } +} + +for {set n 0} {$n < 32} {incr n} { + ipx::infer_bus_interface rx_clk_2x_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interface tx_clk_2x_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interface rx_out_clk_div2_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interface tx_out_clk_div2_$n xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] +} +ipx::infer_bus_interface up_rstn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + +for {set n 0} {$n < 32} {incr n} { + ipx::infer_bus_interface up_rx_rst_$n xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interface up_tx_rst_$n xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + ipx::infer_bus_interface up_cpll_rst_$n xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + if {($n%4) == 0} { + ipx::infer_bus_interface up_qpll_rst_$n xilinx.com:signal:reset_rtl:1.0 [ipx::current_core] + } +} + +for {set n 0} {$n < 32} {incr n} { + + if {($n%4) == 0} { + ipx::associate_bus_interfaces -clock cpll_ref_clk_${n} -reset up_qpll_rst_${n} -remove [ipx::current_core] + } + ipx::associate_bus_interfaces -clock cpll_ref_clk_${n} -reset up_cpll_rst_${n} -remove [ipx::current_core] +} + +set_property driver_value 0 [ipx::get_ports -filter "direction==in" -of_objects [ipx::current_core]] + +for {set n 0} {$n < 32} {incr n} { + + if {($n%4) == 0} { + adi_if_infer_bus analog.com:interface:if_xcvr_cm slave up_cm_${n} [list \ + "enb up_cm_enb_${n} "\ + "addr up_cm_addr_${n} "\ + "wr up_cm_wr_${n} "\ + "wdata up_cm_wdata_${n} "\ + "rdata up_cm_rdata_${n} "\ + "ready up_cm_ready_${n} "] + } + + adi_if_infer_bus analog.com:interface:if_xcvr_cm slave up_es_${n} [list \ + "enb up_es_enb_${n} "\ + "addr up_es_addr_${n} "\ + "wr up_es_wr_${n} "\ + "wdata up_es_wdata_${n} "\ + "rdata up_es_rdata_${n} "\ + "reset up_es_reset_${n} "\ + "ready up_es_ready_${n} "] + + adi_if_infer_bus analog.com:interface:if_xcvr_ch slave up_rx_${n} [list \ + "pll_locked up_rx_pll_locked_${n} "\ + "rst up_rx_rst_${n} "\ + "user_ready up_rx_user_ready_${n} "\ + "rst_done up_rx_rst_done_${n} "\ + "prbssel up_rx_prbssel_${n} "\ + "prbscntreset up_rx_prbscntreset_${n}"\ + "prbserr up_rx_prbserr_${n} "\ + "prbslocked up_rx_prbslocked_${n} "\ + "bufstatus up_rx_bufstatus_${n} "\ + "bufstatus_rst up_rx_bufstatus_rst_${n}"\ + "lpm_dfe_n up_rx_lpm_dfe_n_${n} "\ + "rate up_rx_rate_${n} "\ + "sys_clk_sel up_rx_sys_clk_sel_${n} "\ + "out_clk_sel up_rx_out_clk_sel_${n} "\ + "enb up_rx_enb_${n} "\ + "addr up_rx_addr_${n} "\ + "wr up_rx_wr_${n} "\ + "wdata up_rx_wdata_${n} "\ + "rdata up_rx_rdata_${n} "\ + "ready up_rx_ready_${n} "] + + adi_if_infer_bus analog.com:interface:if_xcvr_ch slave up_tx_${n} [list \ + "pll_locked up_tx_pll_locked_${n} "\ + "rst up_tx_rst_${n} "\ + "user_ready up_tx_user_ready_${n} "\ + "rst_done up_tx_rst_done_${n} "\ + "prbsforceerr up_tx_prbsforceerr_${n}"\ + "prbssel up_tx_prbssel_${n} "\ + "bufstatus up_tx_bufstatus_${n} "\ + "lpm_dfe_n up_tx_lpm_dfe_n_${n} "\ + "rate up_tx_rate_${n} "\ + "sys_clk_sel up_tx_sys_clk_sel_${n} "\ + "out_clk_sel up_tx_out_clk_sel_${n} "\ + "tx_diffctrl up_tx_diffctrl_${n} "\ + "tx_postcursor up_tx_postcursor_${n} "\ + "tx_precursor up_tx_precursor_${n} "\ + "enb up_tx_enb_${n} "\ + "addr up_tx_addr_${n} "\ + "wr up_tx_wr_${n} "\ + "wdata up_tx_wdata_${n} "\ + "rdata up_tx_rdata_${n} "\ + "ready up_tx_ready_${n} "] + + ipx::add_bus_interface rx_${n} [ipx::current_core] + set_property abstraction_type_vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 \ + [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + set_property bus_type_vlnv xilinx.com:display_jesd204:jesd204_rx_bus:1.0 \ + [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + set_property interface_mode master [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + ipx::add_port_map rxcharisk [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + set_property physical_name rx_charisk_${n} [ipx::get_port_maps rxcharisk -of_objects \ + [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] + ipx::add_port_map rxnotintable [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + set_property physical_name rx_notintable_${n} [ipx::get_port_maps rxnotintable -of_objects \ + [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] + ipx::add_port_map rxdisperr [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + set_property physical_name rx_disperr_${n} [ipx::get_port_maps rxdisperr -of_objects \ + [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] + ipx::add_port_map rxdata [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + set_property physical_name rx_data_${n} [ipx::get_port_maps rxdata -of_objects \ + [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] + ipx::add_port_map rxheader [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + set_property physical_name rx_header_${n} [ipx::get_port_maps rxheader -of_objects \ + [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] + ipx::add_port_map rxblock_sync [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]] + set_property physical_name rx_block_sync_${n} [ipx::get_port_maps rxblock_sync -of_objects \ + [ipx::get_bus_interfaces rx_${n} -of_objects [ipx::current_core]]] + + ipx::add_bus_interface tx_${n} [ipx::current_core] + set_property abstraction_type_vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 \ + [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] + set_property bus_type_vlnv xilinx.com:display_jesd204:jesd204_tx_bus:1.0 \ + [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] + set_property interface_mode slave [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] + ipx::add_port_map txcharisk [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] + set_property physical_name tx_charisk_${n} [ipx::get_port_maps txcharisk -of_objects \ + [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]] + ipx::add_port_map txdata [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] + set_property physical_name tx_data_${n} [ipx::get_port_maps txdata -of_objects \ + [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]] + ipx::add_port_map txheader [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]] + set_property physical_name tx_header_${n} [ipx::get_port_maps txheader -of_objects \ + [ipx::get_bus_interfaces tx_${n} -of_objects [ipx::current_core]]] + +} + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ + [ipx::get_bus_interfaces up_es_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ + [ipx::get_bus_interfaces up_rx_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ + [ipx::get_bus_interfaces rx_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ + [ipx::get_ports rx_0_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_0 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_0 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0} \ + [ipx::get_ports up_rx_rst_0 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \ + [ipx::get_bus_interfaces up_tx_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \ + [ipx::get_bus_interfaces tx_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \ + [ipx::get_ports tx_0* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_0 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0} \ + [ipx::get_ports up_tx_rst_0 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0)} \ + [ipx::get_ports cpll_ref_clk_0 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_0 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_0 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_0 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_0 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)} \ + [ipx::get_ports qpll_ref_clk_0 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_qpll_rst_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 0) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 0)} \ + [ipx::get_bus_interfaces up_cm_0 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ + [ipx::get_bus_interfaces up_es_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ + [ipx::get_bus_interfaces up_rx_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ + [ipx::get_bus_interfaces rx_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ + [ipx::get_ports rx_1_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_1 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_1 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1} \ + [ipx::get_ports up_rx_rst_1 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \ + [ipx::get_bus_interfaces up_tx_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \ + [ipx::get_bus_interfaces tx_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \ + [ipx::get_ports tx_1* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_1 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1} \ + [ipx::get_ports up_tx_rst_1 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1)} \ + [ipx::get_ports cpll_ref_clk_1 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_1 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_1 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_1 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 1) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_1 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_1 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ + [ipx::get_bus_interfaces up_es_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ + [ipx::get_bus_interfaces up_rx_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ + [ipx::get_bus_interfaces rx_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ + [ipx::get_ports rx_2_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_2 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_2 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2} \ + [ipx::get_ports up_rx_rst_2 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \ + [ipx::get_bus_interfaces up_tx_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \ + [ipx::get_bus_interfaces tx_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \ + [ipx::get_ports tx_2* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_2 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2} \ + [ipx::get_ports up_tx_rst_2 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2)} \ + [ipx::get_ports cpll_ref_clk_2 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_2 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 2) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_2 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_2 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 2) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_2 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_2 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ + [ipx::get_bus_interfaces up_es_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ + [ipx::get_bus_interfaces up_rx_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ + [ipx::get_bus_interfaces rx_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ + [ipx::get_ports rx_3_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_3 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_3 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3} \ + [ipx::get_ports up_rx_rst_3 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \ + [ipx::get_bus_interfaces up_tx_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \ + [ipx::get_bus_interfaces tx_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \ + [ipx::get_ports tx_3* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_3 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3} \ + [ipx::get_ports up_tx_rst_3 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3)} \ + [ipx::get_ports cpll_ref_clk_3 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_3 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 3) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_3 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_3 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 3) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_3 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_3 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ + [ipx::get_bus_interfaces up_es_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ + [ipx::get_bus_interfaces up_rx_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ + [ipx::get_bus_interfaces rx_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ + [ipx::get_ports rx_4_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_4 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_4 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4} \ + [ipx::get_ports up_rx_rst_4 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \ + [ipx::get_bus_interfaces up_tx_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \ + [ipx::get_bus_interfaces tx_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \ + [ipx::get_ports tx_4* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_4 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4} \ + [ipx::get_ports up_tx_rst_4 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4)} \ + [ipx::get_ports cpll_ref_clk_4 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_4 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_4 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_4 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_4 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \ + [ipx::get_ports qpll_ref_clk_4 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_qpll_rst_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 4) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 4)} \ + [ipx::get_bus_interfaces up_cm_4 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ + [ipx::get_bus_interfaces up_es_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ + [ipx::get_bus_interfaces up_rx_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ + [ipx::get_bus_interfaces rx_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ + [ipx::get_ports rx_5_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_5 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_5 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5} \ + [ipx::get_ports up_rx_rst_5 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \ + [ipx::get_bus_interfaces up_tx_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \ + [ipx::get_bus_interfaces tx_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \ + [ipx::get_ports tx_5* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_5 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5} \ + [ipx::get_ports up_tx_rst_5 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5)} \ + [ipx::get_ports cpll_ref_clk_5 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_5 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 5) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_5 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_5 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 5) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_5 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_5 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ + [ipx::get_bus_interfaces up_es_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ + [ipx::get_bus_interfaces up_rx_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ + [ipx::get_bus_interfaces rx_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ + [ipx::get_ports rx_6_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_6 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_6 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6} \ + [ipx::get_ports up_rx_rst_6 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \ + [ipx::get_bus_interfaces up_tx_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \ + [ipx::get_bus_interfaces tx_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \ + [ipx::get_ports tx_6* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_6 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6} \ + [ipx::get_ports up_tx_rst_6 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6)} \ + [ipx::get_ports cpll_ref_clk_6 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_6 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 6) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_6 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_6 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 6) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_6 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_6 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ + [ipx::get_bus_interfaces up_es_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ + [ipx::get_bus_interfaces up_rx_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ + [ipx::get_bus_interfaces rx_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ + [ipx::get_ports rx_7_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_7 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_7 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7} \ + [ipx::get_ports up_rx_rst_7 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \ + [ipx::get_bus_interfaces up_tx_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \ + [ipx::get_bus_interfaces tx_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \ + [ipx::get_ports tx_7* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_7 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7} \ + [ipx::get_ports up_tx_rst_7 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7)} \ + [ipx::get_ports cpll_ref_clk_7 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_7 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 7) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_7 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_7 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 7) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_7 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_7 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \ + [ipx::get_bus_interfaces up_es_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \ + [ipx::get_bus_interfaces up_rx_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \ + [ipx::get_bus_interfaces rx_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \ + [ipx::get_ports rx_8_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_8 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_8 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8} \ + [ipx::get_ports up_rx_rst_8 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \ + [ipx::get_bus_interfaces up_tx_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \ + [ipx::get_bus_interfaces tx_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \ + [ipx::get_ports tx_8* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_8 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8} \ + [ipx::get_ports up_tx_rst_8 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8)} \ + [ipx::get_ports cpll_ref_clk_8 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_8 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_8 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_8 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_8 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \ + [ipx::get_ports qpll_ref_clk_8 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_qpll_rst_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 8) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 8)} \ + [ipx::get_bus_interfaces up_cm_8 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \ + [ipx::get_bus_interfaces up_es_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \ + [ipx::get_bus_interfaces up_rx_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \ + [ipx::get_bus_interfaces rx_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \ + [ipx::get_ports rx_9_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_9 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_9 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9} \ + [ipx::get_ports up_rx_rst_9 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \ + [ipx::get_bus_interfaces up_tx_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \ + [ipx::get_bus_interfaces tx_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \ + [ipx::get_ports tx_9* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_9 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9} \ + [ipx::get_ports up_tx_rst_9 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9)} \ + [ipx::get_ports cpll_ref_clk_9 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_9 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 9) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_9 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_9 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 9) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_9 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_9 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \ + [ipx::get_bus_interfaces up_es_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \ + [ipx::get_bus_interfaces up_rx_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \ + [ipx::get_bus_interfaces rx_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \ + [ipx::get_ports rx_10_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_10 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_10 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10} \ + [ipx::get_ports up_rx_rst_10 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \ + [ipx::get_bus_interfaces up_tx_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \ + [ipx::get_bus_interfaces tx_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \ + [ipx::get_ports tx_10* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_10 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10} \ + [ipx::get_ports up_tx_rst_10 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10)} \ + [ipx::get_ports cpll_ref_clk_10 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_10 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 10) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_10 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_10 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 10) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_10 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_10 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \ + [ipx::get_bus_interfaces up_es_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \ + [ipx::get_bus_interfaces up_rx_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \ + [ipx::get_bus_interfaces rx_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \ + [ipx::get_ports rx_11_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_11 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_11 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11} \ + [ipx::get_ports up_rx_rst_11 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \ + [ipx::get_bus_interfaces up_tx_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \ + [ipx::get_bus_interfaces tx_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \ + [ipx::get_ports tx_11* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_11 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11} \ + [ipx::get_ports up_tx_rst_11 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11)} \ + [ipx::get_ports cpll_ref_clk_11 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_11 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 11) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_11 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_11 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 11) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_11 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_11 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \ + [ipx::get_bus_interfaces up_es_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \ + [ipx::get_bus_interfaces up_rx_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \ + [ipx::get_bus_interfaces rx_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \ + [ipx::get_ports rx_12_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_12 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_12 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12} \ + [ipx::get_ports up_rx_rst_12 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \ + [ipx::get_bus_interfaces up_tx_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \ + [ipx::get_bus_interfaces tx_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \ + [ipx::get_ports tx_12* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_12 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12} \ + [ipx::get_ports up_tx_rst_12 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12)} \ + [ipx::get_ports cpll_ref_clk_12 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_12 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_12 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_12 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_12 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \ + [ipx::get_ports qpll_ref_clk_12 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_qpll_rst_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 12) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 12)} \ + [ipx::get_bus_interfaces up_cm_12 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \ + [ipx::get_bus_interfaces up_es_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \ + [ipx::get_bus_interfaces up_rx_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \ + [ipx::get_bus_interfaces rx_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \ + [ipx::get_ports rx_13_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_13 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_13 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13} \ + [ipx::get_ports up_rx_rst_13 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \ + [ipx::get_bus_interfaces up_tx_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \ + [ipx::get_bus_interfaces tx_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \ + [ipx::get_ports tx_13* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_13 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13} \ + [ipx::get_ports up_tx_rst_13 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13)} \ + [ipx::get_ports cpll_ref_clk_13 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_13 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 13) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_13 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_13 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 13) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_13 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_13 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \ + [ipx::get_bus_interfaces up_es_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \ + [ipx::get_bus_interfaces up_rx_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \ + [ipx::get_bus_interfaces rx_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \ + [ipx::get_ports rx_14_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_14 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_14 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14} \ + [ipx::get_ports up_rx_rst_14 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \ + [ipx::get_bus_interfaces up_tx_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \ + [ipx::get_bus_interfaces tx_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \ + [ipx::get_ports tx_14* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_14 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14} \ + [ipx::get_ports up_tx_rst_14 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14)} \ + [ipx::get_ports cpll_ref_clk_14 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_14 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 14) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_14 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_14 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 14) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_14 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_14 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \ + [ipx::get_bus_interfaces up_es_15 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \ + [ipx::get_bus_interfaces up_rx_15 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \ + [ipx::get_bus_interfaces rx_15 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \ + [ipx::get_ports rx_15_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_15 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_15 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_15 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15} \ + [ipx::get_ports up_rx_rst_15 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \ + [ipx::get_bus_interfaces up_tx_15 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \ + [ipx::get_bus_interfaces tx_15 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \ + [ipx::get_ports tx_15* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_15 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_15 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15} \ + [ipx::get_ports up_tx_rst_15 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15)} \ + [ipx::get_ports cpll_ref_clk_15 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_15 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 15) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_15 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_15 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 15) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_15 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_15 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 16} \ + [ipx::get_bus_interfaces up_es_16 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 16} \ + [ipx::get_bus_interfaces up_rx_16 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 16} \ + [ipx::get_bus_interfaces rx_16 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 16} \ + [ipx::get_ports rx_16_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_16 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_16 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_16 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 16} \ + [ipx::get_ports up_rx_rst_16 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 16} \ + [ipx::get_bus_interfaces up_tx_16 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 16} \ + [ipx::get_bus_interfaces tx_16 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 16} \ + [ipx::get_ports tx_16* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_16 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_16 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 16} \ + [ipx::get_ports up_tx_rst_16 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 16) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 16)} \ + [ipx::get_ports cpll_ref_clk_16 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_16 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 16) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_16 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_16 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 16) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_16 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_16 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 16) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 16)} \ + [ipx::get_ports qpll_ref_clk_16 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_qpll_rst_16 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 16) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 16)} \ + [ipx::get_bus_interfaces up_cm_16 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 17} \ + [ipx::get_bus_interfaces up_es_17 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 17} \ + [ipx::get_bus_interfaces up_rx_17 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 17} \ + [ipx::get_bus_interfaces rx_17 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 17} \ + [ipx::get_ports rx_17_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_17 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_17 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_17 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 17} \ + [ipx::get_ports up_rx_rst_17 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 17} \ + [ipx::get_bus_interfaces up_tx_17 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 17} \ + [ipx::get_bus_interfaces tx_17 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 17} \ + [ipx::get_ports tx_17* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_17 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_17 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 17} \ + [ipx::get_ports up_tx_rst_17 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 17) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 17)} \ + [ipx::get_ports cpll_ref_clk_17 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_17 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 17) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_17 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_17 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 17) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_17 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_17 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 18} \ + [ipx::get_bus_interfaces up_es_18 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 18} \ + [ipx::get_bus_interfaces up_rx_18 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 18} \ + [ipx::get_bus_interfaces rx_18 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 18} \ + [ipx::get_ports rx_18_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_18 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_18 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_18 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 18} \ + [ipx::get_ports up_rx_rst_18 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 18} \ + [ipx::get_bus_interfaces up_tx_18 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 18} \ + [ipx::get_bus_interfaces tx_18 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 18} \ + [ipx::get_ports tx_18* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_18 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_18 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 18} \ + [ipx::get_ports up_tx_rst_18 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 18) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 18)} \ + [ipx::get_ports cpll_ref_clk_18 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_18 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 18) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_18 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_18 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 18) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_18 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_18 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 19} \ + [ipx::get_bus_interfaces up_es_19 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 19} \ + [ipx::get_bus_interfaces up_rx_19 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 19} \ + [ipx::get_bus_interfaces rx_19 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 19} \ + [ipx::get_ports rx_19_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_19 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_19 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_19 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 19} \ + [ipx::get_ports up_rx_rst_19 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 19} \ + [ipx::get_bus_interfaces up_tx_19 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 19} \ + [ipx::get_bus_interfaces tx_19 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 19} \ + [ipx::get_ports tx_19* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_19 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_19 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 19} \ + [ipx::get_ports up_tx_rst_19 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 19) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 19)} \ + [ipx::get_ports cpll_ref_clk_19 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_19 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 19) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_19 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_19 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 19) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_19 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_19 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 20} \ + [ipx::get_bus_interfaces up_es_20 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 20} \ + [ipx::get_bus_interfaces up_rx_20 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 20} \ + [ipx::get_bus_interfaces rx_20 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 20} \ + [ipx::get_ports rx_20_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_20 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_20 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_20 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 20} \ + [ipx::get_ports up_rx_rst_20 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 20} \ + [ipx::get_bus_interfaces up_tx_20 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 20} \ + [ipx::get_bus_interfaces tx_20 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 20} \ + [ipx::get_ports tx_20* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_20 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_20 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 20} \ + [ipx::get_ports up_tx_rst_20 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 20) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 20)} \ + [ipx::get_ports cpll_ref_clk_20 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_20 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 20) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_20 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_20 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 20) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_20 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_20 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 20) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 20)} \ + [ipx::get_ports qpll_ref_clk_20 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_qpll_rst_20 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 20) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 20)} \ + [ipx::get_bus_interfaces up_cm_20 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 21} \ + [ipx::get_bus_interfaces up_es_21 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 21} \ + [ipx::get_bus_interfaces up_rx_21 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 21} \ + [ipx::get_bus_interfaces rx_21 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 21} \ + [ipx::get_ports rx_21_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_21 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_21 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_21 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 21} \ + [ipx::get_ports up_rx_rst_21 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 21} \ + [ipx::get_bus_interfaces up_tx_21 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 21} \ + [ipx::get_bus_interfaces tx_21 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 21} \ + [ipx::get_ports tx_21* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_21 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_21 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 21} \ + [ipx::get_ports up_tx_rst_21 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 21) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 21)} \ + [ipx::get_ports cpll_ref_clk_21 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_21 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 21) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_21 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_21 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 21) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_21 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_21 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 22} \ + [ipx::get_bus_interfaces up_es_22 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 22} \ + [ipx::get_bus_interfaces up_rx_22 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 22} \ + [ipx::get_bus_interfaces rx_22 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 22} \ + [ipx::get_ports rx_22_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_22 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_22 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_22 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 22} \ + [ipx::get_ports up_rx_rst_22 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 22} \ + [ipx::get_bus_interfaces up_tx_22 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 22} \ + [ipx::get_bus_interfaces tx_22 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 22} \ + [ipx::get_ports tx_22* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_22 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_22 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 22} \ + [ipx::get_ports up_tx_rst_22 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 22) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 22)} \ + [ipx::get_ports cpll_ref_clk_22 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_22 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 22) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_22 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_22 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 22) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_22 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_22 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 23} \ + [ipx::get_bus_interfaces up_es_23 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 23} \ + [ipx::get_bus_interfaces up_rx_23 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 23} \ + [ipx::get_bus_interfaces rx_23 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 23} \ + [ipx::get_ports rx_23_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_23 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_23 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_23 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 23} \ + [ipx::get_ports up_rx_rst_23 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 23} \ + [ipx::get_bus_interfaces up_tx_23 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 23} \ + [ipx::get_bus_interfaces tx_23 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 23} \ + [ipx::get_ports tx_23* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_23 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_23 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 23} \ + [ipx::get_ports up_tx_rst_23 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 23) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 23)} \ + [ipx::get_ports cpll_ref_clk_23 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_23 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 23) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_23 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_23 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 23) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_23 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_23 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24} \ + [ipx::get_bus_interfaces up_es_24 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24} \ + [ipx::get_bus_interfaces up_rx_24 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24} \ + [ipx::get_bus_interfaces rx_24 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24} \ + [ipx::get_ports rx_24_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_24 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_24 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_24 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24} \ + [ipx::get_ports up_rx_rst_24 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 24} \ + [ipx::get_bus_interfaces up_tx_24 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 24} \ + [ipx::get_bus_interfaces tx_24 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 24} \ + [ipx::get_ports tx_24* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_24 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_24 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 24} \ + [ipx::get_ports up_tx_rst_24 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 24) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24)} \ + [ipx::get_ports cpll_ref_clk_24 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_24 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_24 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_24 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 24) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_24 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_24 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 24)} \ + [ipx::get_ports qpll_ref_clk_24 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_qpll_rst_24 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 24) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 24)} \ + [ipx::get_bus_interfaces up_cm_24 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 25} \ + [ipx::get_bus_interfaces up_es_25 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 25} \ + [ipx::get_bus_interfaces up_rx_25 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 25} \ + [ipx::get_bus_interfaces rx_25 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 25} \ + [ipx::get_ports rx_25_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_25 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_25 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_25 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 25} \ + [ipx::get_ports up_rx_rst_25 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 25} \ + [ipx::get_bus_interfaces up_tx_25 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 25} \ + [ipx::get_bus_interfaces tx_25 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 25} \ + [ipx::get_ports tx_25* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_25 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_25 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 25} \ + [ipx::get_ports up_tx_rst_25 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 25) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 25)} \ + [ipx::get_ports cpll_ref_clk_25 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_25 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 25) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_25 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_25 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 25) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_25 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_25 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 26} \ + [ipx::get_bus_interfaces up_es_26 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 26} \ + [ipx::get_bus_interfaces up_rx_26 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 26} \ + [ipx::get_bus_interfaces rx_26 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 26} \ + [ipx::get_ports rx_26_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_26 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_26 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_26 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 26} \ + [ipx::get_ports up_rx_rst_26 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 26} \ + [ipx::get_bus_interfaces up_tx_26 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 26} \ + [ipx::get_bus_interfaces tx_26 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 26} \ + [ipx::get_ports tx_26* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_26 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_26 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 26} \ + [ipx::get_ports up_tx_rst_26 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 26) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 26)} \ + [ipx::get_ports cpll_ref_clk_26 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_26 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 26) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_26 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_26 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 26) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_26 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_26 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 27} \ + [ipx::get_bus_interfaces up_es_27 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 27} \ + [ipx::get_bus_interfaces up_rx_27 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 27} \ + [ipx::get_bus_interfaces rx_27 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 27} \ + [ipx::get_ports rx_27_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_27 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_27 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_27 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 27} \ + [ipx::get_ports up_rx_rst_27 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 27} \ + [ipx::get_bus_interfaces up_tx_27 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 27} \ + [ipx::get_bus_interfaces tx_27 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 27} \ + [ipx::get_ports tx_27* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_27 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_27 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 27} \ + [ipx::get_ports up_tx_rst_27 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 27) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 27)} \ + [ipx::get_ports cpll_ref_clk_27 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_27 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 27) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_27 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_27 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 27) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_27 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_27 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 28} \ + [ipx::get_bus_interfaces up_es_28 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 28} \ + [ipx::get_bus_interfaces up_rx_28 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 28} \ + [ipx::get_bus_interfaces rx_28 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 28} \ + [ipx::get_ports rx_28_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_28 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_28 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_28 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 28} \ + [ipx::get_ports up_rx_rst_28 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 28} \ + [ipx::get_bus_interfaces up_tx_28 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 28} \ + [ipx::get_bus_interfaces tx_28 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 28} \ + [ipx::get_ports tx_28* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_28 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_28 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 28} \ + [ipx::get_ports up_tx_rst_28 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 28) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 28)} \ + [ipx::get_ports cpll_ref_clk_28 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_28 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 28) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_28 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_28 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 28) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_28 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_28 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 28) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 28)} \ + [ipx::get_ports qpll_ref_clk_28 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_qpll_rst_28 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 28) or \ + (spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 28)} \ + [ipx::get_bus_interfaces up_cm_28 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 29} \ + [ipx::get_bus_interfaces up_es_29 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 29} \ + [ipx::get_bus_interfaces up_rx_29 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 29} \ + [ipx::get_bus_interfaces rx_29 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 29} \ + [ipx::get_ports rx_29_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_29 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_29 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_29 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 29} \ + [ipx::get_ports up_rx_rst_29 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 29} \ + [ipx::get_bus_interfaces up_tx_29 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 29} \ + [ipx::get_bus_interfaces tx_29 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 29} \ + [ipx::get_ports tx_29* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_29 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_29 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 29} \ + [ipx::get_ports up_tx_rst_29 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 29) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 29)} \ + [ipx::get_ports cpll_ref_clk_29 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_29 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 29) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_29 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_29 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 29) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_29 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_29 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 30} \ + [ipx::get_bus_interfaces up_es_30 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 30} \ + [ipx::get_bus_interfaces up_rx_30 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 30} \ + [ipx::get_bus_interfaces rx_30 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 30} \ + [ipx::get_ports rx_30_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_30 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_30 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_30 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 30} \ + [ipx::get_ports up_rx_rst_30 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 30} \ + [ipx::get_bus_interfaces up_tx_30 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 30} \ + [ipx::get_bus_interfaces tx_30 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 30} \ + [ipx::get_ports tx_30* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_30 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_30 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 30} \ + [ipx::get_ports up_tx_rst_30 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 30) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 30)} \ + [ipx::get_ports cpll_ref_clk_30 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_30 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 30) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_30 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_30 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 30) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_30 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_30 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 31} \ + [ipx::get_bus_interfaces up_es_31 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 31} \ + [ipx::get_bus_interfaces up_rx_31 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 31} \ + [ipx::get_bus_interfaces rx_31 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 31} \ + [ipx::get_ports rx_31_* -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_clk_31 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_calign_31 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_31 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 31} \ + [ipx::get_ports up_rx_rst_31 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 31} \ + [ipx::get_bus_interfaces up_tx_31 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 31} \ + [ipx::get_bus_interfaces tx_31 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 31} \ + [ipx::get_ports tx_31* -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_clk_31 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_31 -of_objects [ipx::current_core]] + +set_property enablement_dependency {spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 31} \ + [ipx::get_ports up_tx_rst_31 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 31) or \ + (spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 31)} \ + [ipx::get_ports cpll_ref_clk_31 -of_objects [ipx::current_core]] \ + [ipx::get_ports up_cpll_rst_31 -of_objects [ipx::current_core]] + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.RX_NUM_OF_LANES')) > 31) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports rx_clk_2x_31 -of_objects [ipx::current_core]] \ + [ipx::get_ports rx_out_clk_div2_31 -of_objects [ipx::current_core]] \ + +set_property enablement_dependency \ + {(spirit:decode(id('MODELPARAM_VALUE.TX_NUM_OF_LANES')) > 31) and \ + (spirit:decode(id('MODELPARAM_VALUE.LINK_MODE')) = 2) and \ + ((spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 5) or \ + (spirit:decode(id('MODELPARAM_VALUE.XCVR_TYPE')) = 8))} \ + [ipx::get_ports tx_clk_2x_31 -of_objects [ipx::current_core]] \ + [ipx::get_ports tx_out_clk_div2_31 -of_objects [ipx::current_core]] \ + +adi_add_auto_fpga_spec_params +set cc [ipx::current_core] +set param [ipx::get_user_parameters CH_HSPMUX -of_objects $cc] +set_property -dict [list \ + value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x2424 : \ + {$XCVR_TYPE == 9} ? 0x2020 : 0x0]]} \ +] $param + +set param [ipx::get_user_parameters PPF0_CFG -of_objects $cc] +set_property -dict [list \ + value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x800 : 0x600]]} \ +] $param + +set param [ipx::get_user_parameters RXPI_CFG0 -of_objects $cc] +set_property -dict [list \ + value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x2 : \ + {$XCVR_TYPE == 9} ? 0x100 : 0x0]]} \ +] $param + +set param [ipx::get_user_parameters RXPI_CFG1 -of_objects $cc] +set_property -dict [list \ + value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 8} ? 0x15 : 0x0]]} \ +] $param + +set param [ipx::get_user_parameters RTX_BUF_CML_CTRL -of_objects $cc] +set_property -dict [list \ + value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x3 : 0x0]]} \ +] $param + +set param [ipx::get_user_parameters QPLL_LPF -of_objects $cc] +set_property -dict [list \ + value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x37f : 0x137]]} \ +] $param + +set param [ipx::get_user_parameters RXCDR_CFG3_GEN2 -of_objects $cc] +set_property -dict [list \ + value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x12 : 0x1a ]]} \ +] $param + +set param [ipx::get_user_parameters RXCDR_CFG3_GEN4 -of_objects $cc] +set_property -dict [list \ + value_tcl_expr {[format "0x%x" [expr {$XCVR_TYPE == 9} ? 0x12 : 0x24 ]]} \ +] $param + +set param [ipx::get_user_parameters TX_PI_BIASSET -of_objects $cc] +set_property -dict [list \ + value_tcl_expr {expr {$XCVR_TYPE == 9} ? 0 : 1} \ +] $param + + +ipx::create_xgui_files [ipx::current_core] + +ipx::save_core [ipx::current_core] diff --git a/adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v b/adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v new file mode 100644 index 00000000..7f71c52e --- /dev/null +++ b/adi_library/xilinx/util_adxcvr/util_adxcvr_xch.v @@ -0,0 +1,3528 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module util_adxcvr_xch #( + + // parameters + + parameter integer XCVR_TYPE = 0, + + parameter LINK_MODE = 1, // 2 - 64B/66B; 1 - 8B/10B + /* Only 4 is supported at the moment for 8b/10b and 8 for 64b */ + parameter DATA_PATH_WIDTH = LINK_MODE == 2 ? 8 : 4, + + parameter integer CPLL_FBDIV = 2, + parameter integer CPLL_FBDIV_4_5 = 5, + parameter [15:0] CPLL_CFG0 = 16'b0000000111111010, + parameter [15:0] CPLL_CFG1 = 16'b0000000000100011, + parameter [15:0] CPLL_CFG2 = 16'b0000000000000010, + parameter [15:0] CPLL_CFG3 = 16'b0000000000000000, + + parameter [15:0] CH_HSPMUX = 16'b0010010000100100, + parameter integer PREIQ_FREQ_BST = 0, + parameter [15:0] RXPI_CFG0 = 16'b0000000000000010, + parameter [15:0] RXPI_CFG1 = 16'b0000000000010101, + + parameter [2:0] RTX_BUF_CML_CTRL = 3'b011, + + parameter integer TX_OUT_DIV = 1, + parameter integer TX_CLK25_DIV = 20, + parameter integer TX_POLARITY = 0, + parameter [15:0] TX_PI_BIASSET = 1, + parameter [15:0] TXPI_CFG = 16'b0000000001010100, + parameter [15:0] A_TXDIFFCTRL = 5'b10110, + + parameter integer RX_OUT_DIV = 1, + parameter integer RX_CLK25_DIV = 20, + parameter [15:0] RX_DFE_LPM_CFG = 16'h0104, + parameter [31:0] RX_PMA_CFG = 32'h001e7080, + parameter [72:0] RX_CDR_CFG = 72'h0b000023ff10400020, + parameter [15:0] RXCDR_CFG0 = 16'b0000000000000010, + parameter [15:0] RXCDR_CFG2 = 16'b0000001001101001, + parameter [ 9:0] RXCDR_CFG2_GEN2 = 10'b1001100101, + parameter [15:0] RXCDR_CFG2_GEN4 = 16'b0000000010110100, + parameter [15:0] RXCDR_CFG3 = 16'b0000000000010010, + parameter [ 5:0] RXCDR_CFG3_GEN2 = 6'b011010, + parameter [15:0] RXCDR_CFG3_GEN3 = 16'b0000000000010010, + parameter [15:0] RXCDR_CFG3_GEN4 = 16'b0000000000100100, + parameter [15:0] RXDFE_KH_CFG2 = 16'h0200, + parameter [15:0] RXDFE_KH_CFG3 = 16'h4101, + parameter [ 1:0] RX_WIDEMODE_CDR = 2'b00, + parameter [ 0:0] RX_XMODE_SEL = 1'b1, + parameter integer TXDRV_FREQBAND = 0, + parameter [15:0] TXFE_CFG0 = 16'b0000001111000010, + parameter [15:0] TXFE_CFG1 = 16'b0110110000000000, + parameter [15:0] TXFE_CFG2 = 16'b0110110000000000, + parameter [15:0] TXFE_CFG3 = 16'b0110110000000000, + parameter [15:0] TXPI_CFG0 = 16'b0000001100000000, + parameter [15:0] TXPI_CFG1 = 16'b0001000000000000, + parameter integer TXSWBST_EN = 0, + parameter integer RX_POLARITY = 0 +) ( + + // pll interface + + input qpll2ch_clk, + input qpll2ch_ref_clk, + input qpll2ch_locked, + input qpll1_clk, + input qpll1_ref_clk, + input qpll1_locked, + input cpll_ref_clk, + input up_cpll_rst, + + // receive + + input rx_p, + input rx_n, + + output rx_out_clk, + output rx_out_clk_div2, + input rx_clk, + input rx_clk_2x, + output [DATA_PATH_WIDTH-1:0] rx_charisk, + output [DATA_PATH_WIDTH-1:0] rx_disperr, + output [DATA_PATH_WIDTH-1:0] rx_notintable, + output [DATA_PATH_WIDTH*8-1:0] rx_data, + input rx_calign, + output [1:0] rx_header, + output rx_block_sync, + + // transmit + + output tx_p, + output tx_n, + + output tx_out_clk, + output tx_out_clk_div2, + input tx_clk, + input tx_clk_2x, + input [DATA_PATH_WIDTH-1:0] tx_charisk, + input [DATA_PATH_WIDTH*8-1:0] tx_data, + input [1:0] tx_header, + + // up interface + + input up_rstn, + input up_clk, + input up_es_enb, + input [11:0] up_es_addr, + input up_es_wr, + input [15:0] up_es_wdata, + output [15:0] up_es_rdata, + output up_es_ready, + input up_es_reset, + output up_rx_pll_locked, + input up_rx_rst, + input up_rx_user_ready, + output up_rx_rst_done, + input [ 3:0] up_rx_prbssel, + input up_rx_prbscntreset, + output up_rx_prbserr, + output up_rx_prbslocked, + output [ 1:0] up_rx_bufstatus, + input up_rx_bufstatus_rst, + input up_rx_lpm_dfe_n, + input [ 2:0] up_rx_rate, + input [ 1:0] up_rx_sys_clk_sel, + input [ 2:0] up_rx_out_clk_sel, + input up_rx_enb, + input [11:0] up_rx_addr, + input up_rx_wr, + input [15:0] up_rx_wdata, + output [15:0] up_rx_rdata, + output up_rx_ready, + output up_tx_pll_locked, + input up_tx_rst, + input up_tx_user_ready, + output up_tx_rst_done, + output [ 1:0] up_tx_bufstatus, + input up_tx_prbsforceerr, + input [ 3:0] up_tx_prbssel, + input up_tx_lpm_dfe_n, + input [ 2:0] up_tx_rate, + input [ 1:0] up_tx_sys_clk_sel, + input [ 2:0] up_tx_out_clk_sel, + input [ 4:0] up_tx_diffctrl, + input [ 4:0] up_tx_postcursor, + input [ 4:0] up_tx_precursor, + input up_tx_enb, + input [11:0] up_tx_addr, + input up_tx_wr, + input [15:0] up_tx_wdata, + output [15:0] up_tx_rdata, + output up_tx_ready +); + + localparam GTXE2_TRANSCEIVERS = 2; + localparam GTHE3_TRANSCEIVERS = 5; + localparam GTHE4_TRANSCEIVERS = 8; + localparam GTYE4_TRANSCEIVERS = 9; + + // internal registers + + reg [15:0] up_es_rdata_int = 'd0; + reg up_es_ready_int = 'd0; + reg [15:0] up_rx_rdata_int = 'd0; + reg up_rx_ready_int = 'd0; + reg [15:0] up_tx_rdata_int = 'd0; + reg up_tx_ready_int = 'd0; + reg [ 2:0] up_sel_int = 'd0; + reg up_enb_int = 'd0; + reg [11:0] up_addr_int = 'd0; + reg up_wr_int = 'd0; + reg [15:0] up_wdata_int = 'd0; + reg up_rx_rst_done_m1 = 'd0; + reg up_rx_rst_done_m2 = 'd0; + reg up_tx_rst_done_m1 = 'd0; + reg up_tx_rst_done_m2 = 'd0; + reg [ 2:0] rx_rate_m1 = 'd0; + reg [ 2:0] rx_rate_m2 = 'd0; + reg [ 2:0] tx_rate_m1 = 'd0; + reg [ 2:0] tx_rate_m2 = 'd0; + + // internal signals + + wire [15:0] up_rdata_s; + wire up_ready_s; + wire [ 1:0] rx_sys_clk_sel_s; + wire rx_out_clk_s; + wire rx_rst_done_s; + wire [ 1:0] tx_sys_clk_sel_s; + wire tx_out_clk_s; + wire tx_rst_done_s; + wire [ 1:0] rx_pll_clk_sel_s; + wire [ 1:0] tx_pll_clk_sel_s; + wire [11:0] rx_charisk_open_s; + wire [11:0] rx_disperr_open_s; + wire [ 3:0] rx_notintable_open_s; + wire [95:0] rx_data_open_s; + wire cpll_locked_s; + wire rx_usrclk; + wire rx_usrclk2; + wire tx_usrclk; + wire tx_usrclk2; + + // pll + + assign up_rx_pll_locked = (up_rx_sys_clk_sel == 2'd3) ? qpll2ch_locked : (up_rx_sys_clk_sel == 2'd2) ? qpll1_locked : cpll_locked_s; + assign up_tx_pll_locked = (up_tx_sys_clk_sel == 2'd3) ? qpll2ch_locked : (up_tx_sys_clk_sel == 2'd2) ? qpll1_locked : cpll_locked_s; + + // drp access + + assign up_es_rdata = up_es_rdata_int; + assign up_es_ready = up_es_ready_int; + assign up_rx_rdata = up_rx_rdata_int; + assign up_rx_ready = up_rx_ready_int; + assign up_tx_rdata = up_tx_rdata_int; + assign up_tx_ready = up_tx_ready_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_es_rdata_int <= 15'd0; + up_es_ready_int <= 1'd0; + up_rx_rdata_int <= 15'd0; + up_rx_ready_int <= 1'd0; + up_tx_rdata_int <= 15'd0; + up_tx_ready_int <= 1'd0; + up_sel_int <= 3'd0; + up_enb_int <= 1'd0; + up_addr_int <= 12'd0; + up_wr_int <= 1'd0; + up_wdata_int <= 15'd0; + end else begin + if (up_sel_int == 3'b100) begin + up_es_rdata_int <= up_rdata_s; + up_es_ready_int <= up_ready_s; + end else begin + up_es_rdata_int <= 15'd0; + up_es_ready_int <= 1'd0; + end + if (up_sel_int == 3'b101) begin + up_rx_rdata_int <= up_rdata_s; + up_rx_ready_int <= up_ready_s; + end else begin + up_rx_rdata_int <= 15'd0; + up_rx_ready_int <= 1'd0; + end + if (up_sel_int == 3'b110) begin + up_tx_rdata_int <= up_rdata_s; + up_tx_ready_int <= up_ready_s; + end else begin + up_tx_rdata_int <= 15'd0; + up_tx_ready_int <= 1'd0; + end + if (up_sel_int[2] == 1'b1) begin + if (up_ready_s == 1'b1) begin + up_sel_int <= 3'b000; + end + up_enb_int <= 1'b0; + up_addr_int <= 12'd0; + up_wr_int <= 1'd0; + up_wdata_int <= 15'd0; + end else if (up_es_enb == 1'b1) begin + up_sel_int <= 3'b100; + up_enb_int <= 1'b1; + up_addr_int <= up_es_addr; + up_wr_int <= up_es_wr; + up_wdata_int <= up_es_wdata; + end else if (up_rx_enb == 1'b1) begin + up_sel_int <= 3'b101; + up_enb_int <= 1'b1; + up_addr_int <= up_rx_addr; + up_wr_int <= up_rx_wr; + up_wdata_int <= up_rx_wdata; + end else if (up_tx_enb == 1'b1) begin + up_sel_int <= 3'b110; + up_enb_int <= 1'b1; + up_addr_int <= up_tx_addr; + up_wr_int <= up_tx_wr; + up_wdata_int <= up_tx_wdata; + end else begin + up_sel_int <= 3'b000; + up_enb_int <= 1'b0; + up_addr_int <= 12'd0; + up_wr_int <= 1'd0; + up_wdata_int <= 15'd0; + end + end + end + + assign up_rx_rst_done = up_rx_rst_done_m2; + assign up_tx_rst_done = up_tx_rst_done_m2; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_rx_rst_done_m1 <= 'd0; + up_rx_rst_done_m2 <= 'd0; + up_tx_rst_done_m1 <= 'd0; + up_tx_rst_done_m2 <= 'd0; + end else begin + up_rx_rst_done_m1 <= rx_rst_done_s; + up_rx_rst_done_m2 <= up_rx_rst_done_m1; + up_tx_rst_done_m1 <= tx_rst_done_s; + up_tx_rst_done_m2 <= up_tx_rst_done_m1; + end + end + + always @(posedge rx_clk) begin + rx_rate_m1 <= up_rx_rate; + rx_rate_m2 <= rx_rate_m1; + end + + always @(posedge tx_clk) begin + tx_rate_m1 <= up_tx_rate; + tx_rate_m2 <= tx_rate_m1; + end + + // Rx PRBS interface logic + wire rx_prbscntreset; + wire rx_prbserr; + wire rx_prbslocked; + wire [ 3:0] rx_prbssel; + reg rx_prbserr_sticky = 1'b0; + + sync_bits #( + .NUM_OF_BITS(5) + ) i_sync_bits_rx_prbs_in ( + .in_bits ({up_rx_prbssel, + up_rx_prbscntreset}), + .out_resetn (1'b1), + .out_clk (rx_clk), + .out_bits ({rx_prbssel, + rx_prbscntreset})); + + always @(posedge rx_clk) begin + if (rx_prbscntreset) begin + rx_prbserr_sticky <= 1'b0; + end else if (rx_prbserr) begin + rx_prbserr_sticky <= 1'b1; + end + end + + sync_bits #( + .NUM_OF_BITS(2) + ) i_sync_bits_rx_prbs_out ( + .in_bits ({rx_prbslocked, + rx_prbserr_sticky}), + .out_resetn (up_rstn), + .out_clk (up_clk), + .out_bits ({up_rx_prbslocked, + up_rx_prbserr})); + + // Tx PRBS interface logic + wire tx_prbsforceerr; + wire [ 3:0] tx_prbssel; + + sync_bits #( + .NUM_OF_BITS(5) + ) i_sync_bits_tx_prbs_in ( + .in_bits ({up_tx_prbssel, + up_tx_prbsforceerr}), + .out_resetn (1'b1), + .out_clk (tx_clk), + .out_bits ({tx_prbssel, + tx_prbsforceerr})); + + // Bufstatus + reg rx_bufstatus_sticky_0 = 1'b0; + reg rx_bufstatus_sticky_1 = 1'b0; + + wire rx_bufstatus_rst; + wire [ 1:0] rx_bufstatus; + wire [ 1:0] rx_bufstatus_s; + wire [ 1:0] tx_bufstatus; + wire [ 1:0] tx_bufstatus_s; + + sync_bits #( + .NUM_OF_BITS(1) + ) i_sync_bits_rx_bufstatus_in ( + .in_bits (up_rx_bufstatus_rst), + .out_resetn (1'b1), + .out_clk (rx_clk), + .out_bits (rx_bufstatus_rst)); + + always @(posedge rx_clk) begin + if (rx_bufstatus_rst) begin + rx_bufstatus_sticky_0 <= 1'b0; + end else if (rx_bufstatus_s[0]) begin + rx_bufstatus_sticky_0 <= 1'b1; + end + end + + always @(posedge rx_clk) begin + if (rx_bufstatus_rst) begin + rx_bufstatus_sticky_1 <= 1'b0; + end else if (rx_bufstatus_s[1]) begin + rx_bufstatus_sticky_1 <= 1'b1; + end + end + + sync_bits #( + .NUM_OF_BITS(4) + ) i_sync_bits_bufstatus_out ( + .in_bits ({rx_bufstatus, + tx_bufstatus}), + .out_resetn (up_rstn), + .out_clk (up_clk), + .out_bits ({up_rx_bufstatus, + up_tx_bufstatus})); + + // 204C specific logic + localparam ALIGN_COMMA_ENABLE = LINK_MODE[1] ? 10'b0000000000 : 10'b1111111111; + localparam ALIGN_MCOMMA_DET = LINK_MODE[1] ? "FALSE" : "TRUE"; + localparam ALIGN_PCOMMA_DET = LINK_MODE[1] ? "FALSE" : "TRUE"; + localparam CBCC_DATA_SOURCE_SEL = LINK_MODE[1] ? "ENCODED" : "DECODED"; + localparam DEC_MCOMMA_DETECT = LINK_MODE[1] ? "FALSE" : "TRUE"; + localparam DEC_PCOMMA_DETECT = LINK_MODE[1] ? "FALSE" : "TRUE"; + localparam RXBUF_EN = LINK_MODE[1] ? "FALSE" : "TRUE"; + localparam TXBUF_EN = LINK_MODE[1] ? "FALSE" : "TRUE"; + localparam RX_DATA_WIDTH = LINK_MODE[1] ? 64 : 40; + localparam TX_DATA_WIDTH = LINK_MODE[1] ? 64 : 40; + localparam GEARBOX_MODE = LINK_MODE[1] ? 5'b10001 : 5'b00000; + localparam RXGEARBOX_EN = LINK_MODE[1] ? "TRUE" : "FALSE"; + localparam TXGEARBOX_EN = LINK_MODE[1] ? "TRUE" : "FALSE"; + localparam RX_INT_DATAWIDTH = LINK_MODE[1] ? 2 : 1; + localparam TX_INT_DATAWIDTH = LINK_MODE[1] ? 2 : 1; + localparam RX8B10BEN = LINK_MODE[1] ? 0 : 1; + localparam TX8B10BEN = LINK_MODE[1] ? 0 : 1; + localparam RXGBOX_FIFO_INIT_RD_ADDR = LINK_MODE[1] ? 3 : 4; + localparam RXBUF_THRESH_UNDFLW = LINK_MODE[1] ? 4 : 3; + + wire [1:0] rx_header_s; + wire [127:0] rx_data_s; + wire [127:0] tx_data_s; + wire rx_bitslip_s; + + assign rx_usrclk2 = rx_clk; + assign tx_usrclk2 = tx_clk; + + generate + if (LINK_MODE[1]) begin + + reg [3:0] rx_bitslip_d = 'h0; + reg rx_bitslip_req_s_d = 1'b0; + always @(posedge rx_clk) begin + rx_bitslip_d <= {rx_bitslip_d,rx_bitslip_s}; + rx_bitslip_req_s_d <= rx_bitslip_req_s; + end + assign rx_bitslip_s = rx_bitslip_req_s & ~rx_bitslip_req_s_d; + + // Sync header alignment + sync_header_align i_sync_header_align ( + .clk(rx_clk), + .reset(~rx_rst_done_s), + .i_data({rx_header_s,rx_data_s[63:0]}), + .i_slip(rx_bitslip_req_s), + .i_slip_done(rx_bitslip_d[3]), + .o_data(rx_data), + .o_header(rx_header), + .o_block_sync(rx_block_sync)); + + assign tx_data_s = {64'd0, tx_data}; + + assign rx_usrclk = (XCVR_TYPE==GTHE3_TRANSCEIVERS) || + (XCVR_TYPE==GTHE4_TRANSCEIVERS) ? rx_clk_2x : rx_clk; + assign tx_usrclk = (XCVR_TYPE==GTHE3_TRANSCEIVERS) || + (XCVR_TYPE==GTHE4_TRANSCEIVERS) ? tx_clk_2x : tx_clk; + + assign rx_bufstatus[0] = rx_bufstatus_sticky_0; + assign rx_bufstatus[1] = rx_bufstatus_sticky_1; + + assign tx_bufstatus = tx_bufstatus_s; + + end else begin + + assign {rx_data_open_s, rx_data} = rx_data_s; + assign rx_bitslip_s = 1'b0; + assign tx_data_s = {96'd0, tx_data}; + + assign rx_usrclk = rx_clk; + assign tx_usrclk = tx_clk; + + assign rx_bufstatus[0] = rx_bufstatus_sticky_1; + assign rx_bufstatus[1] = rx_bufstatus_sticky_1; + + assign tx_bufstatus[0] = tx_bufstatus_s[1]; + assign tx_bufstatus[1] = tx_bufstatus_s[1]; + end + endgenerate + + // instantiations + + generate + if (XCVR_TYPE == GTXE2_TRANSCEIVERS) begin + BUFG i_rx_bufg ( + .I (rx_out_clk_s), + .O (rx_out_clk)); + + BUFG i_tx_bufg ( + .I (tx_out_clk_s), + .O (tx_out_clk)); + end + endgenerate + + generate + if (XCVR_TYPE == GTXE2_TRANSCEIVERS) begin + assign rx_sys_clk_sel_s = up_rx_sys_clk_sel; + assign tx_sys_clk_sel_s = up_tx_sys_clk_sel; + assign rx_pll_clk_sel_s = 2'd0; + assign tx_pll_clk_sel_s = 2'd0; + end + endgenerate + + generate + if (XCVR_TYPE == GTXE2_TRANSCEIVERS) begin + GTXE2_CHANNEL #( + .ALIGN_COMMA_DOUBLE ("FALSE"), + .ALIGN_COMMA_ENABLE (10'b1111111111), + .ALIGN_COMMA_WORD (4), + .ALIGN_MCOMMA_DET ("TRUE"), + .ALIGN_MCOMMA_VALUE (10'b1010000011), + .ALIGN_PCOMMA_DET ("TRUE"), + .ALIGN_PCOMMA_VALUE (10'b0101111100), + .CBCC_DATA_SOURCE_SEL ("DECODED"), + .CHAN_BOND_KEEP_ALIGN ("FALSE"), + .CHAN_BOND_MAX_SKEW (1), + .CHAN_BOND_SEQ_1_1 (10'b0000000000), + .CHAN_BOND_SEQ_1_2 (10'b0000000000), + .CHAN_BOND_SEQ_1_3 (10'b0000000000), + .CHAN_BOND_SEQ_1_4 (10'b0000000000), + .CHAN_BOND_SEQ_1_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_1 (10'b0000000000), + .CHAN_BOND_SEQ_2_2 (10'b0000000000), + .CHAN_BOND_SEQ_2_3 (10'b0000000000), + .CHAN_BOND_SEQ_2_4 (10'b0000000000), + .CHAN_BOND_SEQ_2_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_USE ("FALSE"), + .CHAN_BOND_SEQ_LEN (1), + .CLK_CORRECT_USE ("FALSE"), + .CLK_COR_KEEP_IDLE ("FALSE"), + .CLK_COR_MAX_LAT (12), + .CLK_COR_MIN_LAT (8), + .CLK_COR_PRECEDENCE ("TRUE"), + .CLK_COR_REPEAT_WAIT (0), + .CLK_COR_SEQ_1_1 (10'b0100000000), + .CLK_COR_SEQ_1_2 (10'b0000000000), + .CLK_COR_SEQ_1_3 (10'b0000000000), + .CLK_COR_SEQ_1_4 (10'b0000000000), + .CLK_COR_SEQ_1_ENABLE (4'b1111), + .CLK_COR_SEQ_2_1 (10'b0100000000), + .CLK_COR_SEQ_2_2 (10'b0000000000), + .CLK_COR_SEQ_2_3 (10'b0000000000), + .CLK_COR_SEQ_2_4 (10'b0000000000), + .CLK_COR_SEQ_2_ENABLE (4'b1111), + .CLK_COR_SEQ_2_USE ("FALSE"), + .CLK_COR_SEQ_LEN (1), + .CPLL_CFG (24'hBC07DC), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_45 (CPLL_FBDIV_4_5), + .CPLL_INIT_CFG (24'h00001E), + .CPLL_LOCK_CFG (16'h01E8), + .CPLL_REFCLK_DIV (1), + .DEC_MCOMMA_DETECT ("TRUE"), + .DEC_PCOMMA_DETECT ("TRUE"), + .DEC_VALID_COMMA_ONLY ("FALSE"), + .DMONITOR_CFG (24'h000A00), + .ES_CONTROL (6'b000000), + .ES_ERRDET_EN ("TRUE"), + .ES_EYE_SCAN_EN ("TRUE"), + .ES_HORZ_OFFSET (12'h000), + .ES_PMA_CFG (10'b0000000000), + .ES_PRESCALE (5'b00000), + .ES_QUALIFIER (80'h00000000000000000000), + .ES_QUAL_MASK (80'hffffffffffffffffffff), + .ES_SDATA_MASK (80'hffffffffff0000000000), + .ES_VERT_OFFSET (9'b000000000), + .FTS_DESKEW_SEQ_ENABLE (4'b1111), + .FTS_LANE_DESKEW_CFG (4'b1111), + .FTS_LANE_DESKEW_EN ("FALSE"), + .GEARBOX_MODE (3'b000), + .IS_CPLLLOCKDETCLK_INVERTED (1'b0), + .IS_DRPCLK_INVERTED (1'b0), + .IS_GTGREFCLK_INVERTED (1'b0), + .IS_RXUSRCLK2_INVERTED (1'b0), + .IS_RXUSRCLK_INVERTED (1'b0), + .IS_TXPHDLYTSTCLK_INVERTED (1'b0), + .IS_TXUSRCLK2_INVERTED (1'b0), + .IS_TXUSRCLK_INVERTED (1'b0), + .OUTREFCLK_SEL_INV (2'b11), + .PCS_PCIE_EN ("FALSE"), + .PCS_RSVD_ATTR (48'h000000000000), + .PD_TRANS_TIME_FROM_P2 (12'h03c), + .PD_TRANS_TIME_NONE_P2 (8'h3c), + .PD_TRANS_TIME_TO_P2 (8'h64), + .PMA_RSV (RX_PMA_CFG), + .PMA_RSV2 (16'h2070), + .PMA_RSV3 (2'b00), + .PMA_RSV4 (32'h00000000), + .RXBUFRESET_TIME (5'b00001), + .RXBUF_ADDR_MODE ("FAST"), + .RXBUF_EIDLE_HI_CNT (4'b1000), + .RXBUF_EIDLE_LO_CNT (4'b0000), + .RXBUF_EN ("TRUE"), + .RXBUF_RESET_ON_CB_CHANGE ("TRUE"), + .RXBUF_RESET_ON_COMMAALIGN ("FALSE"), + .RXBUF_RESET_ON_EIDLE ("FALSE"), + .RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), + .RXBUF_THRESH_OVFLW (57), + .RXBUF_THRESH_OVRD ("TRUE"), + .RXBUF_THRESH_UNDFLW (3), + .RXCDRFREQRESET_TIME (5'b00001), + .RXCDRPHRESET_TIME (5'b00001), + .RXCDR_CFG (RX_CDR_CFG), + .RXCDR_FR_RESET_ON_EIDLE (1'b0), + .RXCDR_HOLD_DURING_EIDLE (1'b0), + .RXCDR_LOCK_CFG (6'b010101), + .RXCDR_PH_RESET_ON_EIDLE (1'b0), + .RXDFELPMRESET_TIME (7'b0001111), + .RXDLY_CFG (16'h001F), + .RXDLY_LCFG (9'h030), + .RXDLY_TAP_CFG (16'h0000), + .RXGEARBOX_EN ("FALSE"), + .RXISCANRESET_TIME (5'b00001), + .RXLPM_HF_CFG (14'b00000011110000), + .RXLPM_LF_CFG (14'b00000011110000), + .RXOOB_CFG (7'b0000110), + .RXOUT_DIV (RX_OUT_DIV), + .RXPCSRESET_TIME (5'b00001), + .RXPHDLY_CFG (24'h084020), + .RXPH_CFG (24'h000000), + .RXPH_MONITOR_SEL (5'b00000), + .RXPMARESET_TIME (5'b00011), + .RXPRBS_ERR_LOOPBACK (1'b0), + .RXSLIDE_AUTO_WAIT (7), + .RXSLIDE_MODE ("OFF"), + .RX_BIAS_CFG (12'b000000000100), + .RX_BUFFER_CFG (6'b000000), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_CLKMUX_PD (1'b1), + .RX_CM_SEL (2'b11), + .RX_CM_TRIM (3'b010), + .RX_DATA_WIDTH (40), + .RX_DDI_SEL (6'b000000), + .RX_DEBUG_CFG (12'b000000000000), + .RX_DEFER_RESET_BUF_EN ("TRUE"), + .RX_DFE_GAIN_CFG (23'h020FEA), + .RX_DFE_H2_CFG (12'b000000000000), + .RX_DFE_H3_CFG (12'b000001000000), + .RX_DFE_H4_CFG (11'b00011110000), + .RX_DFE_H5_CFG (11'b00011100000), + .RX_DFE_KL_CFG (13'b0000011111110), + .RX_DFE_KL_CFG2 (32'h301148AC), + .RX_DFE_LPM_CFG (RX_DFE_LPM_CFG), + .RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0), + .RX_DFE_UT_CFG (17'b10001111000000000), + .RX_DFE_VP_CFG (17'b00011111100000011), + .RX_DFE_XYD_CFG (13'b0000000000000), + .RX_DISPERR_SEQ_MATCH ("TRUE"), + .RX_INT_DATAWIDTH (1), + .RX_OS_CFG (13'b0000010000000), + .RX_SIG_VALID_DLY (10), + .RX_XCLK_SEL ("RXREC"), + .SAS_MAX_COM (64), + .SAS_MIN_COM (36), + .SATA_BURST_SEQ_LEN (4'b0101), + .SATA_BURST_VAL (3'b111), + .SATA_CPLL_CFG ("VCO_3000MHZ"), + .SATA_EIDLE_VAL (3'b111), + .SATA_MAX_BURST (8), + .SATA_MAX_INIT (21), + .SATA_MAX_WAKE (7), + .SATA_MIN_BURST (4), + .SATA_MIN_INIT (12), + .SATA_MIN_WAKE (4), + .SHOW_REALIGN_COMMA ("TRUE"), + .SIM_CPLLREFCLK_SEL (3'b001), + .SIM_RECEIVER_DETECT_PASS ("TRUE"), + .SIM_RESET_SPEEDUP ("TRUE"), + .SIM_TX_EIDLE_DRIVE_LEVEL ("X"), + .SIM_VERSION ("4.0"), + .TERM_RCAL_CFG (5'b10000), + .TERM_RCAL_OVRD (1'b0), + .TRANS_TIME_RATE (8'h0E), + .TST_RSV (32'h00000000), + .TXBUF_EN ("TRUE"), + .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), + .TXDLY_CFG (16'h001F), + .TXDLY_LCFG (9'h030), + .TXDLY_TAP_CFG (16'h0000), + .TXGEARBOX_EN ("FALSE"), + .TXOUT_DIV (TX_OUT_DIV), + .TXPCSRESET_TIME (5'b00001), + .TXPHDLY_CFG (24'h084020), + .TXPH_CFG (16'h0780), + .TXPH_MONITOR_SEL (5'b00000), + .TXPMARESET_TIME (5'b00001), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_CLKMUX_PD (1'b1), + .TX_DATA_WIDTH (40), + .TX_DEEMPH0 (5'b00000), + .TX_DEEMPH1 (5'b00000), + .TX_DRIVE_MODE ("DIRECT"), + .TX_EIDLE_ASSERT_DELAY (3'b110), + .TX_EIDLE_DEASSERT_DELAY (3'b100), + .TX_INT_DATAWIDTH (1), + .TX_LOOPBACK_DRIVE_HIZ ("FALSE"), + .TX_MAINCURSOR_SEL (1'b0), + .TX_MARGIN_FULL_0 (7'b1001110), + .TX_MARGIN_FULL_1 (7'b1001001), + .TX_MARGIN_FULL_2 (7'b1000101), + .TX_MARGIN_FULL_3 (7'b1000010), + .TX_MARGIN_FULL_4 (7'b1000000), + .TX_MARGIN_LOW_0 (7'b1000110), + .TX_MARGIN_LOW_1 (7'b1000100), + .TX_MARGIN_LOW_2 (7'b1000010), + .TX_MARGIN_LOW_3 (7'b1000000), + .TX_MARGIN_LOW_4 (7'b1000000), + .TX_PREDRIVER_MODE (1'b0), + .TX_QPI_STATUS_EN (1'b0), + .TX_RXDETECT_CFG (14'h1832), + .TX_RXDETECT_REF (3'b100), + .TX_XCLK_SEL ("TXOUT"), + .UCODEER_CLR (1'b0) + ) i_gtxe2_channel ( + .RXOUTCLKPCS (), + .RXPHSLIPMONITOR (), + .PHYSTATUS (), + .RXCDRLOCK (), + .RXCHANBONDSEQ (), + .RXCHANISALIGNED (), + .RXCHANREALIGN (), + .RXCOMINITDET (), + .RXCOMSASDET (), + .RXCOMWAKEDET (), + .RXDATAVALID (), + .RXDLYSRESETDONE (), + .RXELECIDLE (), + .RXHEADERVALID (), + .RXPHALIGNDONE (), + .RXQPISENN (), + .RXQPISENP (), + .RXRATEDONE (), + .RXSTARTOFSEQ (), + .RXVALID (), + .TXCOMFINISH (), + .TXDLYSRESETDONE (), + .TXGEARBOXREADY (), + .TXPHALIGNDONE (), + .TXPHINITDONE (), + .TXQPISENN (), + .TXQPISENP (), + .TXRATEDONE (), + .PCSRSVDOUT (), + .RXCLKCORCNT (), + .RXHEADER (), + .RXCHBONDO (), + .RXPHMONITOR (), + .TSTOUT (), + .GTREFCLKMONITOR (), + .CFGRESET (1'h0), + .CLKRSVD (4'h0), + .CPLLFBCLKLOST (), + .CPLLLOCK (cpll_locked_s), + .CPLLLOCKDETCLK (up_clk), + .CPLLLOCKEN (1'h1), + .CPLLPD (1'h0), + .CPLLREFCLKLOST (), + .CPLLREFCLKSEL (3'h1), + .CPLLRESET (up_cpll_rst), + .DMONITOROUT (), + .DRPADDR (up_addr_int[8:0]), + .DRPCLK (up_clk), + .DRPDI (up_wdata_int), + .DRPDO (up_rdata_s), + .DRPEN (up_enb_int), + .DRPRDY (up_ready_s), + .DRPWE (up_wr_int), + .EYESCANDATAERROR (), + .EYESCANMODE (1'h0), + .EYESCANRESET (1'h0), + .EYESCANTRIGGER (1'h0), + .GTGREFCLK (1'h0), + .GTNORTHREFCLK0 (1'h0), + .GTNORTHREFCLK1 (1'h0), + .GTREFCLK0 (cpll_ref_clk), + .GTREFCLK1 (1'h0), + .GTRESETSEL (1'h0), + .GTRSVD (16'h0), + .GTRXRESET (up_rx_rst), + .GTSOUTHREFCLK0 (1'h0), + .GTSOUTHREFCLK1 (1'h0), + .GTTXRESET (up_tx_rst), + .GTXRXN (rx_n), + .GTXRXP (rx_p), + .GTXTXN (tx_n), + .GTXTXP (tx_p), + .LOOPBACK (3'h0), + .PCSRSVDIN (16'h0), + .PCSRSVDIN2 (5'h0), + .PMARSVDIN (5'h0), + .PMARSVDIN2 (5'h0), + .QPLLCLK (qpll2ch_clk), + .QPLLREFCLK (qpll2ch_ref_clk), + .RESETOVRD (1'h0), + .RX8B10BEN (1'h1), + .RXBUFRESET (1'h0), + .RXBUFSTATUS (rx_bufstatus_s), + .RXBYTEISALIGNED (), + .RXBYTEREALIGN (), + .RXCDRFREQRESET (1'h0), + .RXCDRHOLD (1'h0), + .RXCDROVRDEN (1'h0), + .RXCDRRESET (1'h0), + .RXCDRRESETRSV (1'h0), + .RXCHARISCOMMA (), + .RXCHARISK ({rx_charisk_open_s[3:0], rx_charisk}), + .RXCHBONDEN (1'h0), + .RXCHBONDI (5'h0), + .RXCHBONDLEVEL (3'h0), + .RXCHBONDMASTER (1'h1), + .RXCHBONDSLAVE (1'h0), + .RXCOMMADET (), + .RXCOMMADETEN (1'h1), + .RXDATA ({rx_data_open_s[31:0], rx_data}), + .RXDDIEN (1'h0), + .RXDFEAGCHOLD (1'h0), + .RXDFEAGCOVRDEN (1'h0), + .RXDFECM1EN (1'h0), + .RXDFELFHOLD (1'h0), + .RXDFELFOVRDEN (1'h0), + .RXDFELPMRESET (1'h0), + .RXDFETAP2HOLD (1'h0), + .RXDFETAP2OVRDEN (1'h0), + .RXDFETAP3HOLD (1'h0), + .RXDFETAP3OVRDEN (1'h0), + .RXDFETAP4HOLD (1'h0), + .RXDFETAP4OVRDEN (1'h0), + .RXDFETAP5HOLD (1'h0), + .RXDFETAP5OVRDEN (1'h0), + .RXDFEUTHOLD (1'h0), + .RXDFEUTOVRDEN (1'h0), + .RXDFEVPHOLD (1'h0), + .RXDFEVPOVRDEN (1'h0), + .RXDFEVSEN (1'h0), + .RXDFEXYDEN (1'h1), + .RXDFEXYDHOLD (1'h0), + .RXDFEXYDOVRDEN (1'h0), + .RXDISPERR ({rx_disperr_open_s[3:0], rx_disperr}), + .RXDLYBYPASS (1'h1), + .RXDLYEN (1'h0), + .RXDLYOVRDEN (1'h0), + .RXDLYSRESET (1'h0), + .RXELECIDLEMODE (2'h3), + .RXGEARBOXSLIP (1'h0), + .RXLPMEN (up_rx_lpm_dfe_n), + .RXLPMHFHOLD (1'h0), + .RXLPMHFOVRDEN (1'h0), + .RXLPMLFHOLD (1'h0), + .RXLPMLFKLOVRDEN (1'h0), + .RXMCOMMAALIGNEN (rx_calign), + .RXMONITOROUT (), + .RXMONITORSEL (2'h0), + .RXNOTINTABLE ({rx_notintable_open_s, rx_notintable}), + .RXOOBRESET (1'h0), + .RXOSHOLD (1'h0), + .RXOSOVRDEN (1'h0), + .RXOUTCLK (rx_out_clk_s), + .RXOUTCLKFABRIC (), + .RXOUTCLKSEL (up_rx_out_clk_sel), + .RXPCOMMAALIGNEN (rx_calign), + .RXPCSRESET (1'h0), + .RXPD (2'h0), + .RXPHALIGN (1'h0), + .RXPHALIGNEN (1'h0), + .RXPHDLYPD (1'h0), + .RXPHDLYRESET (1'h0), + .RXPHOVRDEN (1'h0), + .RXPMARESET (1'h0), + .RXPOLARITY (RX_POLARITY), + .RXPRBSCNTRESET (rx_prbscntreset), + .RXPRBSERR (rx_prbserr), + .RXPRBSSEL (rx_prbssel[2:0]), + .RXQPIEN (1'h0), + .RXRATE (rx_rate_m2), + .RXRESETDONE (rx_rst_done_s), + .RXSLIDE (1'h0), + .RXSTATUS (), + .RXSYSCLKSEL (rx_sys_clk_sel_s), + .RXUSERRDY (up_rx_user_ready), + .RXUSRCLK (rx_usrclk), + .RXUSRCLK2 (rx_usrclk2), + .SETERRSTATUS (1'h0), + .TSTIN (20'hfffff), + .TX8B10BBYPASS (8'h0), + .TX8B10BEN (1'h1), + .TXBUFDIFFCTRL (3'h4), + .TXBUFSTATUS (tx_bufstatus_s), + .TXCHARDISPMODE (8'h0), + .TXCHARDISPVAL (8'h0), + .TXCHARISK ({4'd0, tx_charisk}), + .TXCOMINIT (1'h0), + .TXCOMSAS (1'h0), + .TXCOMWAKE (1'h0), + .TXDATA ({32'd0, tx_data}), + .TXDEEMPH (1'h0), + .TXDETECTRX (1'h0), + .TXDIFFCTRL (up_tx_diffctrl[3:0]), + .TXDIFFPD (1'h0), + .TXDLYBYPASS (1'h1), + .TXDLYEN (1'h0), + .TXDLYHOLD (1'h0), + .TXDLYOVRDEN (1'h0), + .TXDLYSRESET (1'h0), + .TXDLYUPDOWN (1'h0), + .TXELECIDLE (1'h0), + .TXHEADER (3'h0), + .TXINHIBIT (1'h0), + .TXMAINCURSOR (7'h0), + .TXMARGIN (3'h0), + .TXOUTCLK (tx_out_clk_s), + .TXOUTCLKFABRIC (), + .TXOUTCLKPCS (), + .TXOUTCLKSEL (up_tx_out_clk_sel), + .TXPCSRESET (1'h0), + .TXPD (2'h0), + .TXPDELECIDLEMODE (1'h0), + .TXPHALIGN (1'h0), + .TXPHALIGNEN (1'h0), + .TXPHDLYPD (1'h0), + .TXPHDLYRESET (1'h0), + .TXPHDLYTSTCLK (1'h0), + .TXPHINIT (1'h0), + .TXPHOVRDEN (1'h0), + .TXPISOPD (1'h0), + .TXPMARESET (1'h0), + .TXPOLARITY (TX_POLARITY), + .TXPOSTCURSOR (up_tx_postcursor), + .TXPOSTCURSORINV (1'h0), + .TXPRBSFORCEERR (tx_prbsforceerr), + .TXPRBSSEL (tx_prbssel[2:0]), + .TXPRECURSOR (up_tx_precursor), + .TXPRECURSORINV (1'h0), + .TXQPIBIASEN (1'h0), + .TXQPISTRONGPDOWN (1'h0), + .TXQPIWEAKPUP (1'h0), + .TXRATE (tx_rate_m2), + .TXRESETDONE (tx_rst_done_s), + .TXSEQUENCE (7'h0), + .TXSTARTSEQ (1'h0), + .TXSWING (1'h0), + .TXSYSCLKSEL (tx_sys_clk_sel_s), + .TXUSERRDY (up_tx_user_ready), + .TXUSRCLK (tx_usrclk), + .TXUSRCLK2 (tx_usrclk2)); + // Emulate PRBS lock + assign rx_prbslocked = ~rx_prbserr_sticky; + end + endgenerate + + generate + if (XCVR_TYPE == GTHE3_TRANSCEIVERS) begin + BUFG_GT i_rx_bufg ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (1'b0), + .CLRMASK (1'b0), + .DIV (3'd0), + .I (rx_out_clk_s), + .O (rx_out_clk)); + + BUFG_GT i_tx_bufg ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (1'b0), + .CLRMASK (1'b0), + .DIV (3'd0), + .I (tx_out_clk_s), + .O (tx_out_clk)); + + BUFG_GT i_rx_div2_bufg ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (1'b0), + .CLRMASK (1'b0), + .DIV (3'd1), + .I (rx_out_clk_s), + .O (rx_out_clk_div2)); + + BUFG_GT i_tx_div2_bufg ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (1'b0), + .CLRMASK (1'b0), + .DIV (3'd1), + .I (tx_out_clk_s), + .O (tx_out_clk_div2)); + end + endgenerate + + generate + if (XCVR_TYPE == GTHE3_TRANSCEIVERS) begin + assign rx_sys_clk_sel_s = (up_rx_sys_clk_sel[1] == 0) ? 2'b00 : {1'b1,~up_rx_sys_clk_sel[0]}; + assign tx_sys_clk_sel_s = (up_tx_sys_clk_sel[1] == 0) ? 2'b00 : {1'b1,~up_tx_sys_clk_sel[0]}; + assign rx_pll_clk_sel_s = up_rx_sys_clk_sel; + assign tx_pll_clk_sel_s = up_tx_sys_clk_sel; + end + endgenerate + + generate + if (XCVR_TYPE == GTHE3_TRANSCEIVERS) begin + GTHE3_CHANNEL #( + .ACJTAG_DEBUG_MODE (1'b0), + .ACJTAG_MODE (1'b0), + .ACJTAG_RESET (1'b0), + .ADAPT_CFG0 (16'hf800), + .ADAPT_CFG1 (16'h0000), + .ALIGN_COMMA_DOUBLE ("FALSE"), + .ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE), + .ALIGN_COMMA_WORD (1), + .ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET), + .ALIGN_MCOMMA_VALUE (10'b1010000011), + .ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET), + .ALIGN_PCOMMA_VALUE (10'b0101111100), + .A_RXOSCALRESET (1'b0), + .A_RXPROGDIVRESET (1'b0), + .A_TXPROGDIVRESET (1'b0), + .CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL), + .CDR_SWAP_MODE_EN (1'b0), + .CHAN_BOND_KEEP_ALIGN ("FALSE"), + .CHAN_BOND_MAX_SKEW (1), + .CHAN_BOND_SEQ_1_1 (10'b0000000000), + .CHAN_BOND_SEQ_1_2 (10'b0000000000), + .CHAN_BOND_SEQ_1_3 (10'b0000000000), + .CHAN_BOND_SEQ_1_4 (10'b0000000000), + .CHAN_BOND_SEQ_1_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_1 (10'b0000000000), + .CHAN_BOND_SEQ_2_2 (10'b0000000000), + .CHAN_BOND_SEQ_2_3 (10'b0000000000), + .CHAN_BOND_SEQ_2_4 (10'b0000000000), + .CHAN_BOND_SEQ_2_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_USE ("FALSE"), + .CHAN_BOND_SEQ_LEN (1), + .CLK_CORRECT_USE ("FALSE"), + .CLK_COR_KEEP_IDLE ("FALSE"), + .CLK_COR_MAX_LAT (12), + .CLK_COR_MIN_LAT (8), + .CLK_COR_PRECEDENCE ("TRUE"), + .CLK_COR_REPEAT_WAIT (0), + .CLK_COR_SEQ_1_1 (10'b0100000000), + .CLK_COR_SEQ_1_2 (10'b0100000000), + .CLK_COR_SEQ_1_3 (10'b0100000000), + .CLK_COR_SEQ_1_4 (10'b0100000000), + .CLK_COR_SEQ_1_ENABLE (4'b1111), + .CLK_COR_SEQ_2_1 (10'b0100000000), + .CLK_COR_SEQ_2_2 (10'b0100000000), + .CLK_COR_SEQ_2_3 (10'b0100000000), + .CLK_COR_SEQ_2_4 (10'b0100000000), + .CLK_COR_SEQ_2_ENABLE (4'b1111), + .CLK_COR_SEQ_2_USE ("FALSE"), + .CLK_COR_SEQ_LEN (1), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3[5:0]), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_45 (CPLL_FBDIV_4_5), + .CPLL_INIT_CFG0 (16'h02b2), + .CPLL_INIT_CFG1 (8'h00), + .CPLL_LOCK_CFG (16'h01e8), + .CPLL_REFCLK_DIV (1), + .DDI_CTRL (2'b00), + .DDI_REALIGN_WAIT (15), + .DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT), + .DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT), + .DEC_VALID_COMMA_ONLY ("FALSE"), + .DFE_D_X_REL_POS (1'b0), + .DFE_VCM_COMP_EN (1'b0), + .DMONITOR_CFG0 (10'h000), + .DMONITOR_CFG1 (8'h00), + .ES_CLK_PHASE_SEL (1'b0), + .ES_CONTROL (6'b000000), + .ES_ERRDET_EN ("TRUE"), + .ES_EYE_SCAN_EN ("TRUE"), + .ES_HORZ_OFFSET (12'h000), + .ES_PMA_CFG (10'b0000000000), + .ES_PRESCALE (5'b00000), + .ES_QUALIFIER0 (16'h0000), + .ES_QUALIFIER1 (16'h0000), + .ES_QUALIFIER2 (16'h0000), + .ES_QUALIFIER3 (16'h0000), + .ES_QUALIFIER4 (16'h0000), + .ES_QUAL_MASK0 (16'hffff), + .ES_QUAL_MASK1 (16'hffff), + .ES_QUAL_MASK2 (16'hffff), + .ES_QUAL_MASK3 (16'hffff), + .ES_QUAL_MASK4 (16'hffff), + .ES_SDATA_MASK0 (16'h0000), + .ES_SDATA_MASK1 (16'h0000), + .ES_SDATA_MASK2 (16'hff00), + .ES_SDATA_MASK3 (16'hffff), + .ES_SDATA_MASK4 (16'hffff), + .EVODD_PHI_CFG (11'b00000000000), + .EYE_SCAN_SWAP_EN (1'b0), + .FTS_DESKEW_SEQ_ENABLE (4'b1111), + .FTS_LANE_DESKEW_CFG (4'b1111), + .FTS_LANE_DESKEW_EN ("FALSE"), + .GEARBOX_MODE (GEARBOX_MODE), + .GM_BIAS_SELECT (1'b0), + .LOCAL_MASTER (1'b1), + .OOBDIVCTL (2'b00), + .OOB_PWRUP (1'b0), + .PCI3_AUTO_REALIGN ("OVR_1K_BLK"), + .PCI3_PIPE_RX_ELECIDLE (1'b0), + .PCI3_RX_ASYNC_EBUF_BYPASS (2'b00), + .PCI3_RX_ELECIDLE_EI2_ENABLE (1'b0), + .PCI3_RX_ELECIDLE_H2L_COUNT (6'b000000), + .PCI3_RX_ELECIDLE_H2L_DISABLE (3'b000), + .PCI3_RX_ELECIDLE_HI_COUNT (6'b000000), + .PCI3_RX_ELECIDLE_LP4_DISABLE (1'b0), + .PCI3_RX_FIFO_DISABLE (1'b0), + .PCIE_BUFG_DIV_CTRL (16'h1000), + .PCIE_RXPCS_CFG_GEN3 (16'h02a4), + .PCIE_RXPMA_CFG (16'h000a), + .PCIE_TXPCS_CFG_GEN3 (16'h24a4), + .PCIE_TXPMA_CFG (16'h000a), + .PCS_PCIE_EN ("FALSE"), + .PCS_RSVD0 (16'b0000000000000000), + .PCS_RSVD1 (3'b000), + .PD_TRANS_TIME_FROM_P2 (12'h03c), + .PD_TRANS_TIME_NONE_P2 (8'h19), + .PD_TRANS_TIME_TO_P2 (8'h64), + .PLL_SEL_MODE_GEN12 (2'h3), + .PLL_SEL_MODE_GEN3 (2'h3), + .PMA_RSV1 (16'hf000), + .PROCESS_PAR (3'b010), + .RATE_SW_USE_DRP (1'b1), + .RESET_POWERSAVE_DISABLE (1'b0), + .RXBUFRESET_TIME (5'b00011), + .RXBUF_ADDR_MODE ("FAST"), + .RXBUF_EIDLE_HI_CNT (4'b1000), + .RXBUF_EIDLE_LO_CNT (4'b0000), + .RXBUF_EN (RXBUF_EN), + .RXBUF_RESET_ON_CB_CHANGE ("TRUE"), + .RXBUF_RESET_ON_COMMAALIGN ("FALSE"), + .RXBUF_RESET_ON_EIDLE ("FALSE"), + .RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), + .RXBUF_THRESH_OVFLW (57), + .RXBUF_THRESH_OVRD ("TRUE"), + .RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW), + .RXCDRFREQRESET_TIME (5'b00001), + .RXCDRPHRESET_TIME (5'b00001), + .RXCDR_CFG0 (16'h0000), + .RXCDR_CFG0_GEN3 (16'h0000), + .RXCDR_CFG1 (16'h0000), + .RXCDR_CFG1_GEN3 (16'h0000), + .RXCDR_CFG2 (16'h0766), + .RXCDR_CFG2_GEN3 (16'h07e6), + .RXCDR_CFG3 (16'h0000), + .RXCDR_CFG3_GEN3 (16'h0000), + .RXCDR_CFG4 (16'h0000), + .RXCDR_CFG4_GEN3 (16'h0000), + .RXCDR_CFG5 (16'h0000), + .RXCDR_CFG5_GEN3 (16'h0000), + .RXCDR_FR_RESET_ON_EIDLE (1'b0), + .RXCDR_HOLD_DURING_EIDLE (1'b0), + .RXCDR_LOCK_CFG0 (16'h4480), + .RXCDR_LOCK_CFG1 (16'h5fff), + .RXCDR_LOCK_CFG2 (16'h77c3), + .RXCDR_PH_RESET_ON_EIDLE (1'b0), + .RXCFOK_CFG0 (16'h4000), + .RXCFOK_CFG1 (16'h0065), + .RXCFOK_CFG2 (16'h002e), + .RXDFELPMRESET_TIME (7'b0001111), + .RXDFELPM_KL_CFG0 (16'h0000), + .RXDFELPM_KL_CFG1 (16'h0032), + .RXDFELPM_KL_CFG2 (16'h0000), + .RXDFE_CFG0 (16'h0a00), + .RXDFE_CFG1 (16'h0000), + .RXDFE_GC_CFG0 (16'h0000), + .RXDFE_GC_CFG1 (16'h7870), + .RXDFE_GC_CFG2 (16'h0000), + .RXDFE_H2_CFG0 (16'h0000), + .RXDFE_H2_CFG1 (16'h0000), + .RXDFE_H3_CFG0 (16'h4000), + .RXDFE_H3_CFG1 (16'h0000), + .RXDFE_H4_CFG0 (16'h2000), + .RXDFE_H4_CFG1 (16'h0003), + .RXDFE_H5_CFG0 (16'h2000), + .RXDFE_H5_CFG1 (16'h0003), + .RXDFE_H6_CFG0 (16'h2000), + .RXDFE_H6_CFG1 (16'h0000), + .RXDFE_H7_CFG0 (16'h2000), + .RXDFE_H7_CFG1 (16'h0000), + .RXDFE_H8_CFG0 (16'h2000), + .RXDFE_H8_CFG1 (16'h0000), + .RXDFE_H9_CFG0 (16'h2000), + .RXDFE_H9_CFG1 (16'h0000), + .RXDFE_HA_CFG0 (16'h2000), + .RXDFE_HA_CFG1 (16'h0000), + .RXDFE_HB_CFG0 (16'h2000), + .RXDFE_HB_CFG1 (16'h0000), + .RXDFE_HC_CFG0 (16'h0000), + .RXDFE_HC_CFG1 (16'h0000), + .RXDFE_HD_CFG0 (16'h0000), + .RXDFE_HD_CFG1 (16'h0000), + .RXDFE_HE_CFG0 (16'h0000), + .RXDFE_HE_CFG1 (16'h0000), + .RXDFE_HF_CFG0 (16'h0000), + .RXDFE_HF_CFG1 (16'h0000), + .RXDFE_OS_CFG0 (16'h8000), + .RXDFE_OS_CFG1 (16'h0000), + .RXDFE_UT_CFG0 (16'h8000), + .RXDFE_UT_CFG1 (16'h0003), + .RXDFE_VP_CFG0 (16'haa00), + .RXDFE_VP_CFG1 (16'h0033), + .RXDLY_CFG (16'h001f), + .RXDLY_LCFG (16'h0030), + .RXELECIDLE_CFG ("Sigcfg_4"), + .RXGBOX_FIFO_INIT_RD_ADDR (RXGBOX_FIFO_INIT_RD_ADDR), + .RXGEARBOX_EN (RXGEARBOX_EN), + .RXISCANRESET_TIME (5'b00001), + .RXLPM_CFG (16'h0000), + .RXLPM_GC_CFG (16'h1000), + .RXLPM_KH_CFG0 (16'h0000), + .RXLPM_KH_CFG1 (16'h0002), + .RXLPM_OS_CFG0 (16'h8000), + .RXLPM_OS_CFG1 (16'h0002), + .RXOOB_CFG (9'b000000110), + .RXOOB_CLK_CFG ("PMA"), + .RXOSCALRESET_TIME (5'b00011), + .RXOUT_DIV (RX_OUT_DIV), + .RXPCSRESET_TIME (5'b00011), + .RXPHBEACON_CFG (16'h0000), + .RXPHDLY_CFG (16'h2020), + .RXPHSAMP_CFG (16'h2100), + .RXPHSLIP_CFG (16'h6622), + .RXPH_MONITOR_SEL (5'b00000), + .RXPI_CFG0 (2'b01), + .RXPI_CFG1 (2'b01), + .RXPI_CFG2 (2'b01), + .RXPI_CFG3 (2'b01), + .RXPI_CFG4 (1'b0), + .RXPI_CFG5 (1'b1), + .RXPI_CFG6 (3'b011), + .RXPI_LPM (1'b0), + .RXPI_VREFSEL (1'b0), + .RXPMACLK_SEL ("DATA"), + .RXPMARESET_TIME (5'b00011), + .RXPRBS_ERR_LOOPBACK (1'b0), + .RXPRBS_LINKACQ_CNT (15), + .RXSLIDE_AUTO_WAIT (7), + .RXSLIDE_MODE ("OFF"), + .RXSYNC_MULTILANE (1'b1), + .RXSYNC_OVRD (1'b0), + .RXSYNC_SKIP_DA (1'b0), + .RX_AFE_CM_EN (1'b0), + .RX_BIAS_CFG0 (16'h0ab4), + .RX_BUFFER_CFG (6'b000000), + .RX_CAPFF_SARC_ENB (1'b0), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_CLKMUX_EN (1'b1), + .RX_CLK_SLIP_OVRD (5'b00000), + .RX_CM_BUF_CFG (4'b1010), + .RX_CM_BUF_PD (1'b0), + .RX_CM_SEL (2'b11), + .RX_CM_TRIM (4'b1010), + .RX_CTLE3_LPF (8'b00000001), + .RX_DATA_WIDTH (RX_DATA_WIDTH), + .RX_DDI_SEL (6'b000000), + .RX_DEFER_RESET_BUF_EN ("TRUE"), + .RX_DFELPM_CFG0 (4'b0110), + .RX_DFELPM_CFG1 (1'b1), + .RX_DFELPM_KLKH_AGC_STUP_EN (1'b1), + .RX_DFE_AGC_CFG0 (2'b10), + .RX_DFE_AGC_CFG1 (3'b000), + .RX_DFE_KL_LPM_KH_CFG0 (2'b01), + .RX_DFE_KL_LPM_KH_CFG1 (3'b000), + .RX_DFE_KL_LPM_KL_CFG0 (2'b01), + .RX_DFE_KL_LPM_KL_CFG1 (3'b000), + .RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0), + .RX_DISPERR_SEQ_MATCH ("TRUE"), + .RX_DIVRESET_TIME (5'b00001), + .RX_EN_HI_LR (1'b1), + .RX_EYESCAN_VS_CODE (7'b0000000), + .RX_EYESCAN_VS_NEG_DIR (1'b0), + .RX_EYESCAN_VS_RANGE (2'b00), + .RX_EYESCAN_VS_UT_SIGN (1'b0), + .RX_FABINT_USRCLK_FLOP (1'b0), + .RX_INT_DATAWIDTH (1), + .RX_PMA_POWER_SAVE (1'b0), + .RX_PROGDIV_CFG (0.000000), + .RX_SAMPLE_PERIOD (3'b111), + .RX_SIG_VALID_DLY (11), + .RX_SUM_DFETAPREP_EN (1'b0), + .RX_SUM_IREF_TUNE (4'b1100), + .RX_SUM_RES_CTRL (2'b11), + .RX_SUM_VCMTUNE (4'b0000), + .RX_SUM_VCM_OVWR (1'b0), + .RX_SUM_VREF_TUNE (3'b000), + .RX_TUNE_AFE_OS (2'b10), + .RX_WIDEMODE_CDR (1'b1), + .RX_XCLK_SEL ("RXDES"), + .SAS_MAX_COM (64), + .SAS_MIN_COM (36), + .SATA_BURST_SEQ_LEN (4'b1110), + .SATA_BURST_VAL (3'b100), + .SATA_CPLL_CFG ("VCO_3000MHZ"), + .SATA_EIDLE_VAL (3'b100), + .SATA_MAX_BURST (8), + .SATA_MAX_INIT (21), + .SATA_MAX_WAKE (7), + .SATA_MIN_BURST (4), + .SATA_MIN_INIT (12), + .SATA_MIN_WAKE (4), + .SHOW_REALIGN_COMMA ("TRUE"), + .SIM_MODE ("FAST"), + .SIM_RECEIVER_DETECT_PASS ("TRUE"), + .SIM_RESET_SPEEDUP ("TRUE"), + .SIM_TX_EIDLE_DRIVE_LEVEL (1'b0), + .SIM_VERSION (2), + .TAPDLY_SET_TX (2'h0), + .TEMPERATUR_PAR (4'b0010), + .TERM_RCAL_CFG (15'b100001000010000), + .TERM_RCAL_OVRD (3'b000), + .TRANS_TIME_RATE (8'h0e), + .TST_RSV0 (8'h00), + .TST_RSV1 (8'h00), + .TXBUF_EN (TXBUF_EN), + .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), + .TXDLY_CFG (16'h0009), + .TXDLY_LCFG (16'h0050), + .TXDRVBIAS_N (4'b1010), + .TXDRVBIAS_P (4'b1010), + .TXFIFO_ADDR_CFG ("LOW"), + .TXGBOX_FIFO_INIT_RD_ADDR (4), + .TXGEARBOX_EN (TXGEARBOX_EN), + .TXOUT_DIV (TX_OUT_DIV), + .TXPCSRESET_TIME (5'b00011), + .TXPHDLY_CFG0 (16'h2020), + .TXPHDLY_CFG1 (16'h0075), + .TXPH_CFG (16'h0980), + .TXPH_MONITOR_SEL (5'b00000), + .TXPI_CFG0 (2'b01), + .TXPI_CFG1 (2'b01), + .TXPI_CFG2 (2'b01), + .TXPI_CFG3 (1'b0), + .TXPI_CFG4 (1'b1), + .TXPI_CFG5 (3'b011), + .TXPI_GRAY_SEL (1'b0), + .TXPI_INVSTROBE_SEL (1'b0), + .TXPI_LPM (1'b0), + .TXPI_PPMCLK_SEL ("TXUSRCLK2"), + .TXPI_PPM_CFG (8'b00000000), + .TXPI_SYNFREQ_PPM (3'b001), + .TXPI_VREFSEL (1'b0), + .TXPMARESET_TIME (5'b00011), + .TXSYNC_MULTILANE (1'b1), + .TXSYNC_OVRD (1'b0), + .TXSYNC_SKIP_DA (1'b0), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_CLKMUX_EN (1'b1), + .TX_DATA_WIDTH (TX_DATA_WIDTH), + .TX_DCD_CFG (6'b000010), + .TX_DCD_EN (1'b0), + .TX_DEEMPH0 (6'b000000), + .TX_DEEMPH1 (6'b000000), + .TX_DIVRESET_TIME (5'b00001), + .TX_DRIVE_MODE ("DIRECT"), + .TX_EIDLE_ASSERT_DELAY (3'b100), + .TX_EIDLE_DEASSERT_DELAY (3'b011), + .TX_EML_PHI_TUNE (1'b0), + .TX_FABINT_USRCLK_FLOP (1'b0), + .TX_IDLE_DATA_ZERO (1'b0), + .TX_INT_DATAWIDTH (1), + .TX_LOOPBACK_DRIVE_HIZ ("FALSE"), + .TX_MAINCURSOR_SEL (1'b0), + .TX_MARGIN_FULL_0 (7'b1001111), + .TX_MARGIN_FULL_1 (7'b1001110), + .TX_MARGIN_FULL_2 (7'b1001100), + .TX_MARGIN_FULL_3 (7'b1001010), + .TX_MARGIN_FULL_4 (7'b1001000), + .TX_MARGIN_LOW_0 (7'b1000110), + .TX_MARGIN_LOW_1 (7'b1000101), + .TX_MARGIN_LOW_2 (7'b1000011), + .TX_MARGIN_LOW_3 (7'b1000010), + .TX_MARGIN_LOW_4 (7'b1000000), + .TX_MODE_SEL (3'b000), + .TX_PMADATA_OPT (1'b0), + .TX_PMA_POWER_SAVE (1'b0), + .TX_PROGCLK_SEL ("PREPI"), + .TX_PROGDIV_CFG (0.000000), + .TX_QPI_STATUS_EN (1'b0), + .TX_RXDETECT_CFG (14'h0032), + .TX_RXDETECT_REF (3'b100), + .TX_SAMPLE_PERIOD (3'b111), + .TX_SARC_LPBK_ENB (1'b0), + .TX_XCLK_SEL ("TXOUT"), + .USE_PCS_CLK_PHASE_SEL (1'b0), + .WB_MODE (2'b00) + ) i_gthe3_channel ( + .BUFGTCE (), + .BUFGTCEMASK (), + .BUFGTDIV (), + .BUFGTRESET (), + .BUFGTRSTMASK (), + .CFGRESET (1'h0), + .CLKRSVD0 (1'h0), + .CLKRSVD1 (1'h0), + .CPLLFBCLKLOST (), + .CPLLLOCK (cpll_locked_s), + .CPLLLOCKDETCLK (up_clk), + .CPLLLOCKEN (1'h1), + .CPLLPD (1'h0), + .CPLLREFCLKLOST (), + .CPLLREFCLKSEL (3'h1), + .CPLLRESET (up_cpll_rst), + .DMONFIFORESET (1'h0), + .DMONITORCLK (1'h0), + .DMONITOROUT (), + .DRPADDR (up_addr_int[8:0]), + .DRPCLK (up_clk), + .DRPDI (up_wdata_int), + .DRPDO (up_rdata_s), + .DRPEN (up_enb_int), + .DRPRDY (up_ready_s), + .DRPWE (up_wr_int), + .EVODDPHICALDONE (1'h0), + .EVODDPHICALSTART (1'h0), + .EVODDPHIDRDEN (1'h0), + .EVODDPHIDWREN (1'h0), + .EVODDPHIXRDEN (1'h0), + .EVODDPHIXWREN (1'h0), + .EYESCANDATAERROR (), + .EYESCANMODE (1'h0), + .EYESCANRESET (1'h0), + .EYESCANTRIGGER (1'h0), + .GTGREFCLK (1'h0), + .GTHRXN (rx_n), + .GTHRXP (rx_p), + .GTHTXN (tx_n), + .GTHTXP (tx_p), + .GTNORTHREFCLK0 (1'h0), + .GTNORTHREFCLK1 (1'h0), + .GTPOWERGOOD (), + .GTREFCLK0 (cpll_ref_clk), + .GTREFCLK1 (1'h0), + .GTREFCLKMONITOR (), + .GTRESETSEL (1'h0), + .GTRSVD (16'h0), + .GTRXRESET (up_rx_rst), + .GTSOUTHREFCLK0 (1'h0), + .GTSOUTHREFCLK1 (1'h0), + .GTTXRESET (up_tx_rst), + .LOOPBACK (3'h0), + .LPBKRXTXSEREN (1'h0), + .LPBKTXRXSEREN (1'h0), + .PCIEEQRXEQADAPTDONE (1'h0), + .PCIERATEGEN3 (), + .PCIERATEIDLE (), + .PCIERATEQPLLPD (), + .PCIERATEQPLLRESET (), + .PCIERSTIDLE (1'h0), + .PCIERSTTXSYNCSTART (1'h0), + .PCIESYNCTXSYNCDONE (), + .PCIEUSERGEN3RDY (), + .PCIEUSERPHYSTATUSRST (), + .PCIEUSERRATEDONE (1'h0), + .PCIEUSERRATESTART (), + .PCSRSVDIN (16'h0), + .PCSRSVDIN2 (5'h0), + .PCSRSVDOUT (), + .PHYSTATUS (), + .PINRSRVDAS (), + .PMARSVDIN (5'h0), + .QPLL0CLK (qpll2ch_clk), + .QPLL0REFCLK (qpll2ch_ref_clk), + .QPLL1CLK (qpll1_clk), + .QPLL1REFCLK (qpll1_ref_clk), + .RESETEXCEPTION (), + .RESETOVRD (1'h0), + .RSTCLKENTX (1'h0), + .RX8B10BEN (RX8B10BEN), + .RXBUFRESET (1'h0), + .RXBUFSTATUS (rx_bufstatus_s), + .RXBYTEISALIGNED (), + .RXBYTEREALIGN (), + .RXCDRFREQRESET (1'h0), + .RXCDRHOLD (1'h0), + .RXCDRLOCK (), + .RXCDROVRDEN (1'h0), + .RXCDRPHDONE (), + .RXCDRRESET (1'h0), + .RXCDRRESETRSV (1'h0), + .RXCHANBONDSEQ (), + .RXCHANISALIGNED (), + .RXCHANREALIGN (), + .RXCHBONDEN (1'h0), + .RXCHBONDI (5'h0), + .RXCHBONDLEVEL (3'h0), + .RXCHBONDMASTER (1'h0), + .RXCHBONDO (), + .RXCHBONDSLAVE (1'h0), + .RXCLKCORCNT (), + .RXCOMINITDET (), + .RXCOMMADET (), + .RXCOMMADETEN (1'h1), + .RXCOMSASDET (), + .RXCOMWAKEDET (), + .RXCTRL0 ({rx_charisk_open_s, rx_charisk}), + .RXCTRL1 ({rx_disperr_open_s, rx_disperr}), + .RXCTRL2 (), + .RXCTRL3 ({rx_notintable_open_s, rx_notintable}), + .RXDATA (rx_data_s), + .RXDATAEXTENDRSVD (), + .RXDATAVALID (), + .RXDFEAGCCTRL (2'h1), + .RXDFEAGCHOLD (1'h0), + .RXDFEAGCOVRDEN (1'h0), + .RXDFELFHOLD (1'h0), + .RXDFELFOVRDEN (1'h0), + .RXDFELPMRESET (1'h0), + .RXDFETAP10HOLD (1'h0), + .RXDFETAP10OVRDEN (1'h0), + .RXDFETAP11HOLD (1'h0), + .RXDFETAP11OVRDEN (1'h0), + .RXDFETAP12HOLD (1'h0), + .RXDFETAP12OVRDEN (1'h0), + .RXDFETAP13HOLD (1'h0), + .RXDFETAP13OVRDEN (1'h0), + .RXDFETAP14HOLD (1'h0), + .RXDFETAP14OVRDEN (1'h0), + .RXDFETAP15HOLD (1'h0), + .RXDFETAP15OVRDEN (1'h0), + .RXDFETAP2HOLD (1'h0), + .RXDFETAP2OVRDEN (1'h0), + .RXDFETAP3HOLD (1'h0), + .RXDFETAP3OVRDEN (1'h0), + .RXDFETAP4HOLD (1'h0), + .RXDFETAP4OVRDEN (1'h0), + .RXDFETAP5HOLD (1'h0), + .RXDFETAP5OVRDEN (1'h0), + .RXDFETAP6HOLD (1'h0), + .RXDFETAP6OVRDEN (1'h0), + .RXDFETAP7HOLD (1'h0), + .RXDFETAP7OVRDEN (1'h0), + .RXDFETAP8HOLD (1'h0), + .RXDFETAP8OVRDEN (1'h0), + .RXDFETAP9HOLD (1'h0), + .RXDFETAP9OVRDEN (1'h0), + .RXDFEUTHOLD (1'h0), + .RXDFEUTOVRDEN (1'h0), + .RXDFEVPHOLD (1'h0), + .RXDFEVPOVRDEN (1'h0), + .RXDFEVSEN (1'h0), + .RXDFEXYDEN (1'h1), + .RXDLYBYPASS (1'h1), + .RXDLYEN (1'h0), + .RXDLYOVRDEN (1'h0), + .RXDLYSRESET (1'h0), + .RXDLYSRESETDONE (), + .RXELECIDLE (), + .RXELECIDLEMODE (2'h3), + .RXGEARBOXSLIP (rx_bitslip_s), + .RXHEADER (rx_header_s), + .RXHEADERVALID (), + .RXLATCLK (1'h0), + .RXLPMEN (up_rx_lpm_dfe_n), + .RXLPMGCHOLD (1'h0), + .RXLPMGCOVRDEN (1'h0), + .RXLPMHFHOLD (1'h0), + .RXLPMHFOVRDEN (1'h0), + .RXLPMLFHOLD (1'h0), + .RXLPMLFKLOVRDEN (1'h0), + .RXLPMOSHOLD (1'h0), + .RXLPMOSOVRDEN (1'h0), + .RXMCOMMAALIGNEN (rx_calign), + .RXMONITOROUT (), + .RXMONITORSEL (2'h0), + .RXOOBRESET (1'h0), + .RXOSCALRESET (1'h0), + .RXOSHOLD (1'h0), + .RXOSINTCFG (4'hd), + .RXOSINTDONE (), + .RXOSINTEN (1'h1), + .RXOSINTHOLD (1'h0), + .RXOSINTOVRDEN (1'h0), + .RXOSINTSTARTED (), + .RXOSINTSTROBE (1'h0), + .RXOSINTSTROBEDONE (), + .RXOSINTSTROBESTARTED (), + .RXOSINTTESTOVRDEN (1'h0), + .RXOSOVRDEN (1'h0), + .RXOUTCLK (rx_out_clk_s), + .RXOUTCLKFABRIC (), + .RXOUTCLKPCS (), + .RXOUTCLKSEL (up_rx_out_clk_sel), + .RXPCOMMAALIGNEN (rx_calign), + .RXPCSRESET (1'h0), + .RXPD (2'h0), + .RXPHALIGN (1'h0), + .RXPHALIGNDONE (), + .RXPHALIGNEN (1'h0), + .RXPHALIGNERR (), + .RXPHDLYPD (1'h1), + .RXPHDLYRESET (1'h0), + .RXPHOVRDEN (1'h0), + .RXPLLCLKSEL (rx_pll_clk_sel_s), + .RXPMARESET (1'h0), + .RXPMARESETDONE (), + .RXPOLARITY (RX_POLARITY), + .RXPRBSCNTRESET (rx_prbscntreset), + .RXPRBSERR (rx_prbserr), + .RXPRBSLOCKED (rx_prbslocked), + .RXPRBSSEL (rx_prbssel), + .RXPRGDIVRESETDONE (), + .RXPROGDIVRESET (up_rx_rst), + .RXQPIEN (1'h0), + .RXQPISENN (), + .RXQPISENP (), + .RXRATE (rx_rate_m2), + .RXRATEDONE (), + .RXRATEMODE (1'h0), + .RXRECCLKOUT (), + .RXRESETDONE (rx_rst_done_s), + .RXSLIDE (1'h0), + .RXSLIDERDY (), + .RXSLIPDONE (), + .RXSLIPOUTCLK (1'h0), + .RXSLIPOUTCLKRDY (), + .RXSLIPPMA (1'h0), + .RXSLIPPMARDY (), + .RXSTARTOFSEQ (), + .RXSTATUS (), + .RXSYNCALLIN (1'h0), + .RXSYNCDONE (), + .RXSYNCIN (1'h0), + .RXSYNCMODE (1'h0), + .RXSYNCOUT (), + .RXSYSCLKSEL (rx_sys_clk_sel_s), + .RXUSERRDY (up_rx_user_ready), + .RXUSRCLK (rx_usrclk), + .RXUSRCLK2 (rx_usrclk2), + .RXVALID (), + .SIGVALIDCLK (1'h0), + .TSTIN (20'h0), + .TX8B10BBYPASS (8'h0), + .TX8B10BEN (TX8B10BEN), + .TXBUFDIFFCTRL (3'h0), + .TXBUFSTATUS (tx_bufstatus_s), + .TXCOMFINISH (), + .TXCOMINIT (1'h0), + .TXCOMSAS (1'h0), + .TXCOMWAKE (1'h0), + .TXCTRL0 (16'h0), + .TXCTRL1 (16'h0), + .TXCTRL2 ({4'd0, tx_charisk}), + .TXDATA (tx_data_s), + .TXDATAEXTENDRSVD (8'h0), + .TXDEEMPH (1'h0), + .TXDETECTRX (1'h0), + .TXDIFFCTRL (up_tx_diffctrl[3:0]), + .TXDIFFPD (1'h0), + .TXDLYBYPASS (1'h1), + .TXDLYEN (1'h0), + .TXDLYHOLD (1'h0), + .TXDLYOVRDEN (1'h0), + .TXDLYSRESET (1'h0), + .TXDLYSRESETDONE (), + .TXDLYUPDOWN (1'h0), + .TXELECIDLE (1'h0), + .TXHEADER ({4'b0,tx_header}), + .TXINHIBIT (1'h0), + .TXLATCLK (1'h0), + .TXMAINCURSOR (7'h40), + .TXMARGIN (3'h0), + .TXOUTCLK (tx_out_clk_s), + .TXOUTCLKFABRIC (), + .TXOUTCLKPCS (), + .TXOUTCLKSEL (up_tx_out_clk_sel), + .TXPCSRESET (1'h0), + .TXPD (2'h0), + .TXPDELECIDLEMODE (1'h0), + .TXPHALIGN (1'h0), + .TXPHALIGNDONE (), + .TXPHALIGNEN (1'h0), + .TXPHDLYPD (1'h1), + .TXPHDLYRESET (1'h0), + .TXPHDLYTSTCLK (1'h0), + .TXPHINIT (1'h0), + .TXPHINITDONE (), + .TXPHOVRDEN (1'h0), + .TXPIPPMEN (1'h0), + .TXPIPPMOVRDEN (1'h0), + .TXPIPPMPD (1'h0), + .TXPIPPMSEL (1'h0), + .TXPIPPMSTEPSIZE (5'h0), + .TXPISOPD (1'h0), + .TXPLLCLKSEL (tx_pll_clk_sel_s), + .TXPMARESET (1'h0), + .TXPMARESETDONE (), + .TXPOLARITY (TX_POLARITY), + .TXPOSTCURSOR (up_tx_postcursor), + .TXPOSTCURSORINV (1'h0), + .TXPRBSFORCEERR (tx_prbsforceerr), + .TXPRBSSEL (tx_prbssel), + .TXPRECURSOR (up_tx_precursor), + .TXPRECURSORINV (1'h0), + .TXPRGDIVRESETDONE (), + .TXPROGDIVRESET (up_tx_rst), + .TXQPIBIASEN (1'h0), + .TXQPISENN (), + .TXQPISENP (), + .TXQPISTRONGPDOWN (1'h0), + .TXQPIWEAKPUP (1'h0), + .TXRATE (tx_rate_m2), + .TXRATEDONE (), + .TXRATEMODE (1'h0), + .TXRESETDONE (tx_rst_done_s), + .TXSEQUENCE (7'h0), + .TXSWING (1'h0), + .TXSYNCALLIN (1'h0), + .TXSYNCDONE (), + .TXSYNCIN (1'h0), + .TXSYNCMODE (1'h0), + .TXSYNCOUT (), + .TXSYSCLKSEL (tx_sys_clk_sel_s), + .TXUSERRDY (up_tx_user_ready), + .TXUSRCLK (tx_usrclk), + .TXUSRCLK2 (tx_usrclk2)); + end + endgenerate + + generate + if (XCVR_TYPE == GTHE4_TRANSCEIVERS) begin + BUFG_GT i_rx_bufg ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (1'b0), + .CLRMASK (1'b0), + .DIV (3'd0), + .I (rx_out_clk_s), + .O (rx_out_clk)); + + BUFG_GT i_tx_bufg ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (1'b0), + .CLRMASK (1'b0), + .DIV (3'd0), + .I (tx_out_clk_s), + .O (tx_out_clk)); + + BUFG_GT i_rx_div2_bufg ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (1'b0), + .CLRMASK (1'b0), + .DIV (3'd1), + .I (rx_out_clk_s), + .O (rx_out_clk_div2)); + + BUFG_GT i_tx_div2_bufg ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (1'b0), + .CLRMASK (1'b0), + .DIV (3'd1), + .I (tx_out_clk_s), + .O (tx_out_clk_div2)); + end + endgenerate + + generate + if (XCVR_TYPE == GTHE4_TRANSCEIVERS) begin + assign rx_sys_clk_sel_s = (up_rx_sys_clk_sel[1] == 0) ? 2'b00 : {1'b1,~up_rx_sys_clk_sel[0]}; + assign tx_sys_clk_sel_s = (up_tx_sys_clk_sel[1] == 0) ? 2'b00 : {1'b1,~up_tx_sys_clk_sel[0]}; + assign rx_pll_clk_sel_s = up_rx_sys_clk_sel; + assign tx_pll_clk_sel_s = up_tx_sys_clk_sel; + end + endgenerate + + generate + if (XCVR_TYPE == GTHE4_TRANSCEIVERS) begin + GTHE4_CHANNEL #( + .ACJTAG_DEBUG_MODE (1'b0), + .ACJTAG_MODE (1'b0), + .ACJTAG_RESET (1'b0), + .ADAPT_CFG0 (16'b0001000000000000), + .ADAPT_CFG1 (16'b1100100000000000), + .ADAPT_CFG2 (16'b0000000000000000), + .ALIGN_COMMA_DOUBLE ("FALSE"), + .ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE), + .ALIGN_COMMA_WORD (1), + .ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET), + .ALIGN_MCOMMA_VALUE (10'b1010000011), + .ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET), + .ALIGN_PCOMMA_VALUE (10'b0101111100), + .A_RXOSCALRESET (1'b0), + .A_RXPROGDIVRESET (1'b0), + .A_RXTERMINATION (1'b1), + .A_TXDIFFCTRL (A_TXDIFFCTRL), + .A_TXPROGDIVRESET (1'b0), + .CAPBYPASS_FORCE (1'b0), + .CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL), + .CDR_SWAP_MODE_EN (1'b0), + .CFOK_PWRSVE_EN (1'b1), + .CHAN_BOND_KEEP_ALIGN ("FALSE"), + .CHAN_BOND_MAX_SKEW (1), + .CHAN_BOND_SEQ_1_1 (10'b0000000000), + .CHAN_BOND_SEQ_1_2 (10'b0000000000), + .CHAN_BOND_SEQ_1_3 (10'b0000000000), + .CHAN_BOND_SEQ_1_4 (10'b0000000000), + .CHAN_BOND_SEQ_1_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_1 (10'b0000000000), + .CHAN_BOND_SEQ_2_2 (10'b0000000000), + .CHAN_BOND_SEQ_2_3 (10'b0000000000), + .CHAN_BOND_SEQ_2_4 (10'b0000000000), + .CHAN_BOND_SEQ_2_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_USE ("FALSE"), + .CHAN_BOND_SEQ_LEN (1), + .CH_HSPMUX (CH_HSPMUX), + .CKCAL1_CFG_0 (16'b1100000011000000), + .CKCAL1_CFG_1 (16'b0101000011000000), + .CKCAL1_CFG_2 (16'b0000000000001010), + .CKCAL1_CFG_3 (16'b0000000000000000), + .CKCAL2_CFG_0 (16'b1100000011000000), + .CKCAL2_CFG_1 (16'b1000000011000000), + .CKCAL2_CFG_2 (16'b0000000000000000), + .CKCAL2_CFG_3 (16'b0000000000000000), + .CKCAL2_CFG_4 (16'b0000000000000000), + .CKCAL_RSVD0 (16'b0000000010000000), + .CKCAL_RSVD1 (16'b0000010000000000), + .CLK_CORRECT_USE ("FALSE"), + .CLK_COR_KEEP_IDLE ("FALSE"), + .CLK_COR_MAX_LAT (12), + .CLK_COR_MIN_LAT (8), + .CLK_COR_PRECEDENCE ("TRUE"), + .CLK_COR_REPEAT_WAIT (0), + .CLK_COR_SEQ_1_1 (10'b0100000000), + .CLK_COR_SEQ_1_2 (10'b0100000000), + .CLK_COR_SEQ_1_3 (10'b0100000000), + .CLK_COR_SEQ_1_4 (10'b0100000000), + .CLK_COR_SEQ_1_ENABLE (4'b1111), + .CLK_COR_SEQ_2_1 (10'b0100000000), + .CLK_COR_SEQ_2_2 (10'b0100000000), + .CLK_COR_SEQ_2_3 (10'b0100000000), + .CLK_COR_SEQ_2_4 (10'b0100000000), + .CLK_COR_SEQ_2_ENABLE (4'b1111), + .CLK_COR_SEQ_2_USE ("FALSE"), + .CLK_COR_SEQ_LEN (1), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_45 (CPLL_FBDIV_4_5), + .CPLL_INIT_CFG0 (16'b0000001010110010), + .CPLL_LOCK_CFG (16'b0000000111101000), + .CPLL_REFCLK_DIV (1), + .CTLE3_OCAP_EXT_CTRL (3'b000), + .CTLE3_OCAP_EXT_EN (1'b0), + .DDI_CTRL (2'b00), + .DDI_REALIGN_WAIT (15), + .DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT), + .DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT), + .DEC_VALID_COMMA_ONLY ("FALSE"), + .DELAY_ELEC (1'b0), + .DMONITOR_CFG0 (10'b0000000000), + .DMONITOR_CFG1 (8'b00000000), + .ES_CLK_PHASE_SEL (1'b0), + .ES_CONTROL (6'b000000), + .ES_ERRDET_EN ("TRUE"), + .ES_EYE_SCAN_EN ("TRUE"), + .ES_HORZ_OFFSET (12'b000000000000), + .ES_PRESCALE (5'b00000), + .ES_QUALIFIER0 (16'b0000000000000000), + .ES_QUALIFIER1 (16'b0000000000000000), + .ES_QUALIFIER2 (16'b0000000000000000), + .ES_QUALIFIER3 (16'b0000000000000000), + .ES_QUALIFIER4 (16'b0000000000000000), + .ES_QUALIFIER5 (16'b0000000000000000), + .ES_QUALIFIER6 (16'b0000000000000000), + .ES_QUALIFIER7 (16'b0000000000000000), + .ES_QUALIFIER8 (16'b0000000000000000), + .ES_QUALIFIER9 (16'b0000000000000000), + .ES_QUAL_MASK0 (16'b1111111111111111), + .ES_QUAL_MASK1 (16'b1111111111111111), + .ES_QUAL_MASK2 (16'b1111111111111111), + .ES_QUAL_MASK3 (16'b1111111111111111), + .ES_QUAL_MASK4 (16'b1111111111111111), + .ES_QUAL_MASK5 (16'b1111111111111111), + .ES_QUAL_MASK6 (16'b1111111111111111), + .ES_QUAL_MASK7 (16'b1111111111111111), + .ES_QUAL_MASK8 (16'b1111111111111111), + .ES_QUAL_MASK9 (16'b1111111111111111), + .ES_SDATA_MASK0 (16'b1111111111111111), + .ES_SDATA_MASK1 (16'b1111111111111111), + .ES_SDATA_MASK2 (16'b0000000011111111), + .ES_SDATA_MASK3 (16'b0000000000000000), + .ES_SDATA_MASK4 (16'b0000000000000000), + .ES_SDATA_MASK5 (16'b1111111111111111), + .ES_SDATA_MASK6 (16'b1111111111111111), + .ES_SDATA_MASK7 (16'b1111111111111111), + .ES_SDATA_MASK8 (16'b1111111111111111), + .ES_SDATA_MASK9 (16'b1111111111111111), + .EYE_SCAN_SWAP_EN (1'b0), + .FTS_DESKEW_SEQ_ENABLE (4'b1111), + .FTS_LANE_DESKEW_CFG (4'b1111), + .FTS_LANE_DESKEW_EN ("FALSE"), + .GEARBOX_MODE (GEARBOX_MODE), + .ISCAN_CK_PH_SEL2 (1'b0), + .LOCAL_MASTER (1'b1), + .LPBK_BIAS_CTRL (3'b100), + .LPBK_EN_RCAL_B (1'b0), + .LPBK_EXT_RCAL (4'b1000), + .LPBK_IND_CTRL0 (3'b000), + .LPBK_IND_CTRL1 (3'b000), + .LPBK_IND_CTRL2 (3'b000), + .LPBK_RG_CTRL (4'b1110), + .OOBDIVCTL (2'b00), + .OOB_PWRUP (1'b0), + .PCI3_AUTO_REALIGN ("OVR_1K_BLK"), + .PCI3_PIPE_RX_ELECIDLE (1'b0), + .PCI3_RX_ASYNC_EBUF_BYPASS (2'b00), + .PCI3_RX_ELECIDLE_EI2_ENABLE (1'b0), + .PCI3_RX_ELECIDLE_H2L_COUNT (6'b000000), + .PCI3_RX_ELECIDLE_H2L_DISABLE (3'b000), + .PCI3_RX_ELECIDLE_HI_COUNT (6'b000000), + .PCI3_RX_ELECIDLE_LP4_DISABLE (1'b0), + .PCI3_RX_FIFO_DISABLE (1'b0), + .PCIE3_CLK_COR_EMPTY_THRSH (5'b00000), + .PCIE3_CLK_COR_FULL_THRSH (6'b010000), + .PCIE3_CLK_COR_MAX_LAT (5'b00100), + .PCIE3_CLK_COR_MIN_LAT (5'b00000), + .PCIE3_CLK_COR_THRSH_TIMER (6'b001000), + .PCIE_BUFG_DIV_CTRL (16'b0011010100000000), + .PCIE_PLL_SEL_MODE_GEN12 (2'b10), + .PCIE_PLL_SEL_MODE_GEN3 (2'b10), + .PCIE_PLL_SEL_MODE_GEN4 (2'b10), + .PCIE_RXPCS_CFG_GEN3 (16'b0000101010100101), + .PCIE_RXPMA_CFG (16'b0010100000001010), + .PCIE_TXPCS_CFG_GEN3 (16'b0010010010100100), + .PCIE_TXPMA_CFG (16'b0010100000001010), + .PCS_PCIE_EN ("FALSE"), + .PCS_RSVD0 (16'b0000000000000000), + .PD_TRANS_TIME_FROM_P2 (12'b000000111100), + .PD_TRANS_TIME_NONE_P2 (8'b00011001), + .PD_TRANS_TIME_TO_P2 (8'b01100100), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .PROCESS_PAR (3'b010), + .RATE_SW_USE_DRP (1'b1), + .RCLK_SIPO_DLY_ENB (1'b0), + .RCLK_SIPO_INV_EN (1'b0), + .RESET_POWERSAVE_DISABLE (1'b0), + .RTX_BUF_CML_CTRL (3'b010), + .RTX_BUF_TERM_CTRL (2'b00), + .RXBUFRESET_TIME (5'b00011), + .RXBUF_ADDR_MODE ("FAST"), + .RXBUF_EIDLE_HI_CNT (4'b1000), + .RXBUF_EIDLE_LO_CNT (4'b0000), + .RXBUF_EN (RXBUF_EN), + .RXBUF_RESET_ON_CB_CHANGE ("TRUE"), + .RXBUF_RESET_ON_COMMAALIGN ("FALSE"), + .RXBUF_RESET_ON_EIDLE ("FALSE"), + .RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), + .RXBUF_THRESH_OVFLW (57), + .RXBUF_THRESH_OVRD ("TRUE"), + .RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW), + .RXCDRFREQRESET_TIME (5'b00001), + .RXCDRPHRESET_TIME (5'b00001), + .RXCDR_CFG0 (RXCDR_CFG0), + .RXCDR_CFG0_GEN3 (16'b0000000000000011), + .RXCDR_CFG1 (16'b0000000000000000), + .RXCDR_CFG1_GEN3 (16'b0000000000000000), + .RXCDR_CFG2 (16'b0000001001100101), + .RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2), + .RXCDR_CFG2_GEN3 (16'b0000001001100101), + .RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4), + .RXCDR_CFG3 (RXCDR_CFG3), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXCDR_CFG4 (16'b0101110011110110), + .RXCDR_CFG4_GEN3 (16'b0101110011110110), + .RXCDR_CFG5 (16'b1011010001101011), + .RXCDR_CFG5_GEN3 (16'b0001010001101011), + .RXCDR_FR_RESET_ON_EIDLE (1'b0), + .RXCDR_HOLD_DURING_EIDLE (1'b0), + .RXCDR_LOCK_CFG0 (16'b0010001000000001), + .RXCDR_LOCK_CFG1 (16'b1001111111111111), + .RXCDR_LOCK_CFG2 (16'b0111011111000011), + .RXCDR_LOCK_CFG3 (16'b0000000000000001), + .RXCDR_LOCK_CFG4 (16'b0000000000000000), + .RXCDR_PH_RESET_ON_EIDLE (1'b0), + .RXCFOK_CFG0 (16'b0000000000000000), + .RXCFOK_CFG1 (16'b1000000000010101), + .RXCFOK_CFG2 (16'b0000001010101110), + .RXCKCAL1_IQ_LOOP_RST_CFG (16'b0000000000000100), + .RXCKCAL1_I_LOOP_RST_CFG (16'b0000000000000100), + .RXCKCAL1_Q_LOOP_RST_CFG (16'b0000000000000100), + .RXCKCAL2_DX_LOOP_RST_CFG (16'b0000000000000100), + .RXCKCAL2_D_LOOP_RST_CFG (16'b0000000000000100), + .RXCKCAL2_S_LOOP_RST_CFG (16'b0000000000000100), + .RXCKCAL2_X_LOOP_RST_CFG (16'b0000000000000100), + .RXDFELPMRESET_TIME (7'b0001111), + .RXDFELPM_KL_CFG0 (16'b0000000000000000), + .RXDFELPM_KL_CFG1 (16'b1010000011100010), + .RXDFELPM_KL_CFG2 (16'b0000000100000000), + .RXDFE_CFG0 (16'b0000101000000000), + .RXDFE_CFG1 (16'b0000000000000000), + .RXDFE_GC_CFG0 (16'b0000000000000000), + .RXDFE_GC_CFG1 (16'b1000000000000000), + .RXDFE_GC_CFG2 (16'b1111111111100000), + .RXDFE_H2_CFG0 (16'b0000000000000000), + .RXDFE_H2_CFG1 (16'b0000000000000010), + .RXDFE_H3_CFG0 (16'b0000000000000000), + .RXDFE_H3_CFG1 (16'b1000000000000010), + .RXDFE_H4_CFG0 (16'b0000000000000000), + .RXDFE_H4_CFG1 (16'b1000000000000010), + .RXDFE_H5_CFG0 (16'b0000000000000000), + .RXDFE_H5_CFG1 (16'b1000000000000010), + .RXDFE_H6_CFG0 (16'b0000000000000000), + .RXDFE_H6_CFG1 (16'b1000000000000010), + .RXDFE_H7_CFG0 (16'b0000000000000000), + .RXDFE_H7_CFG1 (16'b1000000000000010), + .RXDFE_H8_CFG0 (16'b0000000000000000), + .RXDFE_H8_CFG1 (16'b1000000000000010), + .RXDFE_H9_CFG0 (16'b0000000000000000), + .RXDFE_H9_CFG1 (16'b1000000000000010), + .RXDFE_HA_CFG0 (16'b0000000000000000), + .RXDFE_HA_CFG1 (16'b1000000000000010), + .RXDFE_HB_CFG0 (16'b0000000000000000), + .RXDFE_HB_CFG1 (16'b1000000000000010), + .RXDFE_HC_CFG0 (16'b0000000000000000), + .RXDFE_HC_CFG1 (16'b1000000000000010), + .RXDFE_HD_CFG0 (16'b0000000000000000), + .RXDFE_HD_CFG1 (16'b1000000000000010), + .RXDFE_HE_CFG0 (16'b0000000000000000), + .RXDFE_HE_CFG1 (16'b1000000000000010), + .RXDFE_HF_CFG0 (16'b0000000000000000), + .RXDFE_HF_CFG1 (16'b1000000000000010), + .RXDFE_KH_CFG0 (16'b0000000000000000), + .RXDFE_KH_CFG1 (16'b1000000000000000), + .RXDFE_KH_CFG2 (16'b0010011000010011), + .RXDFE_KH_CFG3 (16'b0100000100011100), + .RXDFE_OS_CFG0 (16'b0000000000000000), + .RXDFE_OS_CFG1 (16'b1000000000000010), + .RXDFE_PWR_SAVING (1'b0), + .RXDFE_UT_CFG0 (16'b0000000000000000), + .RXDFE_UT_CFG1 (16'b0000000000000011), + .RXDFE_UT_CFG2 (16'b0000000000000000), + .RXDFE_VP_CFG0 (16'b0000000000000000), + .RXDFE_VP_CFG1 (16'b1000000000110011), + .RXDLY_CFG (16'b0000000000010000), + .RXDLY_LCFG (16'b0000000000110000), + .RXELECIDLE_CFG ("SIGCFG_4"), + .RXGBOX_FIFO_INIT_RD_ADDR (RXGBOX_FIFO_INIT_RD_ADDR), + .RXGEARBOX_EN (RXGEARBOX_EN), + .RXISCANRESET_TIME (5'b00001), + .RXLPM_CFG (16'b0000000000000000), + .RXLPM_GC_CFG (16'b1000000000000000), + .RXLPM_KH_CFG0 (16'b0000000000000000), + .RXLPM_KH_CFG1 (16'b0000000000000010), + .RXLPM_OS_CFG0 (16'b0000000000000000), + .RXLPM_OS_CFG1 (16'b1000000000000010), + .RXOOB_CFG (9'b000000110), + .RXOOB_CLK_CFG ("PMA"), + .RXOSCALRESET_TIME (5'b00011), + .RXOUT_DIV (RX_OUT_DIV), + .RXPCSRESET_TIME (5'b00011), + .RXPHBEACON_CFG (16'b0000000000000000), + .RXPHDLY_CFG (16'b0010000001110000), + .RXPHSAMP_CFG (16'b0010000100000000), + .RXPHSLIP_CFG (16'b1001100100110011), + .RXPH_MONITOR_SEL (5'b00000), + .RXPI_AUTO_BW_SEL_BYPASS (1'b0), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RXPI_LPM (1'b0), + .RXPI_SEL_LC (2'b00), + .RXPI_STARTCODE (2'b00), + .RXPI_VREFSEL (1'b0), + .RXPMACLK_SEL ("DATA"), + .RXPMARESET_TIME (5'b00011), + .RXPRBS_ERR_LOOPBACK (1'b0), + .RXPRBS_LINKACQ_CNT (15), + .RXREFCLKDIV2_SEL (1'b0), + .RXSLIDE_AUTO_WAIT (7), + .RXSLIDE_MODE ("OFF"), + .RXSYNC_MULTILANE (1'b1), + .RXSYNC_OVRD (1'b0), + .RXSYNC_SKIP_DA (1'b0), + .RX_AFE_CM_EN (1'b0), + .RX_BIAS_CFG0 (16'b0001010101010100), + .RX_BUFFER_CFG (6'b000000), + .RX_CAPFF_SARC_ENB (1'b0), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_CLKMUX_EN (1'b1), + .RX_CLK_SLIP_OVRD (5'b00000), + .RX_CM_BUF_CFG (4'b1010), + .RX_CM_BUF_PD (1'b0), + .RX_CM_SEL (3), + .RX_CM_TRIM (10), + .RX_CTLE3_LPF (8'b11111111), + .RX_DATA_WIDTH (RX_DATA_WIDTH), + .RX_DDI_SEL (6'b000000), + .RX_DEFER_RESET_BUF_EN ("TRUE"), + .RX_DEGEN_CTRL (3'b011), + .RX_DFELPM_CFG0 (6), + .RX_DFELPM_CFG1 (1'b1), + .RX_DFELPM_KLKH_AGC_STUP_EN (1'b1), + .RX_DFE_AGC_CFG0 (2'b10), + .RX_DFE_AGC_CFG1 (4), + .RX_DFE_KL_LPM_KH_CFG0 (1), + .RX_DFE_KL_LPM_KH_CFG1 (4), + .RX_DFE_KL_LPM_KL_CFG0 (2'b01), + .RX_DFE_KL_LPM_KL_CFG1 (4), + .RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0), + .RX_DISPERR_SEQ_MATCH ("TRUE"), + .RX_DIV2_MODE_B (1'b0), + .RX_DIVRESET_TIME (5'b00001), + .RX_EN_CTLE_RCAL_B (1'b0), + .RX_EN_HI_LR (1'b1), + .RX_EXT_RL_CTRL (9'b000000000), + .RX_EYESCAN_VS_CODE (7'b0000000), + .RX_EYESCAN_VS_NEG_DIR (1'b0), + .RX_EYESCAN_VS_RANGE (2'b00), + .RX_EYESCAN_VS_UT_SIGN (1'b0), + .RX_FABINT_USRCLK_FLOP (1'b0), + .RX_INT_DATAWIDTH (1), + .RX_PMA_POWER_SAVE (1'b0), + .RX_PMA_RSV0 (16'b0000000000000000), + .RX_PROGDIV_CFG (0.0), + .RX_PROGDIV_RATE (16'b0000000000000001), + .RX_RESLOAD_CTRL (4'b0000), + .RX_RESLOAD_OVRD (1'b0), + .RX_SAMPLE_PERIOD (3'b111), + .RX_SIG_VALID_DLY (11), + .RX_SUM_DFETAPREP_EN (1'b0), + .RX_SUM_IREF_TUNE (4'b0100), + .RX_SUM_RESLOAD_CTRL (4'b0011), + .RX_SUM_VCMTUNE (4'b0110), + .RX_SUM_VCM_OVWR (1'b0), + .RX_SUM_VREF_TUNE (3'b100), + .RX_TUNE_AFE_OS (2'b00), + .RX_VREG_CTRL (3'b101), + .RX_VREG_PDB (1'b1), + .RX_WIDEMODE_CDR (2'b01), + .RX_WIDEMODE_CDR_GEN3 (2'b00), + .RX_WIDEMODE_CDR_GEN4 (2'b01), + .RX_XCLK_SEL ("RXDES"), + .RX_XMODE_SEL (1'b0), + .SAMPLE_CLK_PHASE (1'b0), + .SAS_12G_MODE (1'b0), + .SATA_BURST_SEQ_LEN (4'b1111), + .SATA_BURST_VAL (3'b100), + .SATA_CPLL_CFG ("VCO_3000MHZ"), + .SATA_EIDLE_VAL (3'b100), + .SHOW_REALIGN_COMMA ("TRUE"), + .SIM_MODE ("FAST"), + .SIM_RECEIVER_DETECT_PASS ("TRUE"), + .SIM_RESET_SPEEDUP ("TRUE"), + .SIM_TX_EIDLE_DRIVE_LEVEL ("Z"), + .SRSTMODE (1'b0), + .TAPDLY_SET_TX (2'b00), + .TEMPERATURE_PAR (4'b0010), + .TERM_RCAL_CFG (15'b100001000010001), + .TERM_RCAL_OVRD (3'b000), + .TRANS_TIME_RATE (8'b00001110), + .TST_RSV0 (8'b00000000), + .TST_RSV1 (8'b00000000), + .TXBUF_EN (TXBUF_EN), + .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), + .TXDLY_CFG (16'b1000000000010000), + .TXDLY_LCFG (16'b0000000000110000), + .TXDRVBIAS_N (4'b1010), + .TXFIFO_ADDR_CFG ("LOW"), + .TXGBOX_FIFO_INIT_RD_ADDR (4), + .TXGEARBOX_EN (TXGEARBOX_EN), + .TXOUT_DIV (TX_OUT_DIV), + .TXPCSRESET_TIME (5'b00011), + .TXPHDLY_CFG0 (16'b0110000001110000), + .TXPHDLY_CFG1 (16'b0000000000001111), + .TXPH_CFG (16'b0000001100100011), + .TXPH_CFG2 (16'b0000000000000000), + .TXPH_MONITOR_SEL (5'b00000), + .TXPI_CFG (TXPI_CFG), + .TXPI_CFG0 (2'b00), + .TXPI_CFG1 (2'b00), + .TXPI_CFG2 (2'b00), + .TXPI_CFG3 (1'b0), + .TXPI_CFG4 (1'b0), + .TXPI_CFG5 (3'b000), + .TXPI_GRAY_SEL (1'b0), + .TXPI_INVSTROBE_SEL (1'b0), + .TXPI_LPM (1'b0), + .TXPI_PPM (1'b0), + .TXPI_PPMCLK_SEL ("TXUSRCLK2"), + .TXPI_PPM_CFG (8'b00000000), + .TXPI_SYNFREQ_PPM (3'b001), + .TXPI_VREFSEL (1'b0), + .TXPMARESET_TIME (5'b00011), + .TXREFCLKDIV2_SEL (1'b0), + .TXSYNC_MULTILANE (1'b1), + .TXSYNC_OVRD (1'b0), + .TXSYNC_SKIP_DA (1'b0), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_CLKMUX_EN (1'b1), + .TX_DATA_WIDTH (TX_DATA_WIDTH), + .TX_DCC_LOOP_RST_CFG (16'b0000000000000100), + .TX_DEEMPH0 (6'b000000), + .TX_DEEMPH1 (6'b000000), + .TX_DEEMPH2 (6'b000000), + .TX_DEEMPH3 (6'b000000), + .TX_DIVRESET_TIME (5'b00001), + .TX_DRIVE_MODE ("DIRECT"), + .TX_DRVMUX_CTRL (2), + .TX_EIDLE_ASSERT_DELAY (3'b100), + .TX_EIDLE_DEASSERT_DELAY (3'b011), + .TX_FABINT_USRCLK_FLOP (1'b0), + .TX_FIFO_BYP_EN (1'b0), + .TX_IDLE_DATA_ZERO (1'b0), + .TX_INT_DATAWIDTH (1), + .TX_LOOPBACK_DRIVE_HIZ ("FALSE"), + .TX_MAINCURSOR_SEL (1'b0), + .TX_MARGIN_FULL_0 (7'b1011111), + .TX_MARGIN_FULL_1 (7'b1011110), + .TX_MARGIN_FULL_2 (7'b1011100), + .TX_MARGIN_FULL_3 (7'b1011010), + .TX_MARGIN_FULL_4 (7'b1011000), + .TX_MARGIN_LOW_0 (7'b1000110), + .TX_MARGIN_LOW_1 (7'b1000101), + .TX_MARGIN_LOW_2 (7'b1000011), + .TX_MARGIN_LOW_3 (7'b1000010), + .TX_MARGIN_LOW_4 (7'b1000000), + .TX_PHICAL_CFG0 (16'b0000000000000000), + .TX_PHICAL_CFG1 (16'b0111111000000000), + .TX_PHICAL_CFG2 (16'b0000001000000001), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TX_PI_IBIAS_MID (2'b00), + .TX_PMADATA_OPT (1'b0), + .TX_PMA_POWER_SAVE (1'b0), + .TX_PMA_RSV0 (16'b0000000000001000), + .TX_PREDRV_CTRL (2), + .TX_PROGCLK_SEL ("PREPI"), + .TX_PROGDIV_CFG (0.0), + .TX_PROGDIV_RATE (16'b0000000000000001), + .TX_QPI_STATUS_EN (1'b0), + .TX_RXDETECT_CFG (14'b00000000110010), + .TX_RXDETECT_REF (4), + .TX_SAMPLE_PERIOD (3'b111), + .TX_SARC_LPBK_ENB (1'b0), + .TX_SW_MEAS (2'b00), + .TX_VREG_CTRL (3'b000), + .TX_VREG_PDB (1'b0), + .TX_VREG_VREFSEL (2'b00), + .TX_XCLK_SEL ("TXOUT"), + .USB_BOTH_BURST_IDLE (1'b0), + .USB_BURSTMAX_U3WAKE (7'b1111111), + .USB_BURSTMIN_U3WAKE (7'b1100011), + .USB_CLK_COR_EQ_EN (1'b0), + .USB_EXT_CNTL (1'b1), + .USB_IDLEMAX_POLLING (10'b1010111011), + .USB_IDLEMIN_POLLING (10'b0100101011), + .USB_LFPSPING_BURST (9'b000000101), + .USB_LFPSPOLLING_BURST (9'b000110001), + .USB_LFPSPOLLING_IDLE_MS (9'b000000100), + .USB_LFPSU1EXIT_BURST (9'b000011101), + .USB_LFPSU2LPEXIT_BURST_MS (9'b001100011), + .USB_LFPSU3WAKE_BURST_MS (9'b111110011), + .USB_LFPS_TPERIOD (4'b0011), + .USB_LFPS_TPERIOD_ACCURATE (1'b1), + .USB_MODE (1'b0), + .USB_PCIE_ERR_REP_DIS (1'b0), + .USB_PING_SATA_MAX_INIT (21), + .USB_PING_SATA_MIN_INIT (12), + .USB_POLL_SATA_MAX_BURST (8), + .USB_POLL_SATA_MIN_BURST (4), + .USB_RAW_ELEC (1'b0), + .USB_RXIDLE_P0_CTRL (1'b1), + .USB_TXIDLE_TUNE_ENABLE (1'b1), + .USB_U1_SATA_MAX_WAKE (7), + .USB_U1_SATA_MIN_WAKE (4), + .USB_U2_SAS_MAX_COM (64), + .USB_U2_SAS_MIN_COM (36), + .USE_PCS_CLK_PHASE_SEL (1'b0), + .Y_ALL_MODE (1'b0) + ) i_gthe4_channel ( + .BUFGTCE (), + .BUFGTCEMASK (), + .BUFGTDIV (), + .BUFGTRESET (), + .BUFGTRSTMASK (), + .CDRSTEPDIR (1'd0), + .CDRSTEPSQ (1'd0), + .CDRSTEPSX (1'd0), + .CFGRESET (1'd0), + .CLKRSVD0 (1'd0), + .CLKRSVD1 (1'd0), + .CPLLFBCLKLOST (), + .CPLLFREQLOCK (1'd0), + .CPLLLOCK (cpll_locked_s), + .CPLLLOCKDETCLK (up_clk), + .CPLLLOCKEN (1'd1), + .CPLLPD (up_cpll_rst), + .CPLLREFCLKLOST (), + .CPLLREFCLKSEL (3'b001), + .CPLLRESET (1'b0), + .DMONFIFORESET (1'd0), + .DMONITORCLK (1'd0), + .DMONITOROUT (), + .DMONITOROUTCLK (), + .DRPADDR (up_addr_int[9:0]), + .DRPCLK (up_clk), + .DRPDI (up_wdata_int), + .DRPDO (up_rdata_s), + .DRPEN (up_enb_int), + .DRPRDY (up_ready_s), + .DRPRST (1'd0), + .DRPWE (up_wr_int), + .EYESCANDATAERROR (), + .EYESCANRESET (up_es_reset), + .EYESCANTRIGGER (1'd0), + .FREQOS (1'd0), + .GTGREFCLK (1'd0), + .GTHRXN (rx_n), + .GTHRXP (rx_p), + .GTHTXN (tx_n), + .GTHTXP (tx_p), + .GTNORTHREFCLK0 (1'd0), + .GTNORTHREFCLK1 (1'd0), + .GTPOWERGOOD (), + .GTREFCLK0 (cpll_ref_clk), + .GTREFCLK1 (1'd0), + .GTREFCLKMONITOR (), + .GTRSVD (15'd0), + .GTRXRESET (up_rx_rst), + .GTRXRESETSEL (1'd0), + .GTSOUTHREFCLK0 (1'd0), + .GTSOUTHREFCLK1 (1'd0), + .GTTXRESET (up_tx_rst), + .GTTXRESETSEL (1'd0), + .INCPCTRL (1'd0), + .LOOPBACK (3'd0), + .PCIEEQRXEQADAPTDONE (1'd0), + .PCIERATEGEN3 (), + .PCIERATEIDLE (), + .PCIERATEQPLLPD (), + .PCIERATEQPLLRESET (), + .PCIERSTIDLE (1'd0), + .PCIERSTTXSYNCSTART (1'd0), + .PCIESYNCTXSYNCDONE (), + .PCIEUSERGEN3RDY (), + .PCIEUSERPHYSTATUSRST (), + .PCIEUSERRATEDONE (1'd0), + .PCIEUSERRATESTART (), + .PCSRSVDIN (16'd0), + .PCSRSVDOUT (), + .PHYSTATUS (), + .PINRSRVDAS (), + .POWERPRESENT (), + .QPLL0CLK (qpll2ch_clk), + .QPLL0FREQLOCK (1'd0), + .QPLL0REFCLK (qpll2ch_ref_clk), + .QPLL1CLK (qpll1_clk), + .QPLL1FREQLOCK (1'd0), + .QPLL1REFCLK (qpll1_ref_clk), + .RESETEXCEPTION (), + .RESETOVRD (1'd0), + .RX8B10BEN (RX8B10BEN), + .RXAFECFOKEN (1'b1), + .RXBUFRESET (1'd0), + .RXBUFSTATUS (rx_bufstatus_s), + .RXBYTEISALIGNED (), + .RXBYTEREALIGN (), + .RXCDRFREQRESET (1'd0), + .RXCDRHOLD (1'd0), + .RXCDRLOCK (), + .RXCDROVRDEN (1'd0), + .RXCDRPHDONE (), + .RXCDRRESET (1'd0), + .RXCHANBONDSEQ (), + .RXCHANISALIGNED (), + .RXCHANREALIGN (), + .RXCHBONDEN (1'd0), + .RXCHBONDI (5'd0), + .RXCHBONDLEVEL (3'd0), + .RXCHBONDMASTER (1'd0), + .RXCHBONDO (), + .RXCHBONDSLAVE (1'd0), + .RXCKCALDONE (), + .RXCKCALRESET (1'd0), + .RXCKCALSTART (7'd0), + .RXCLKCORCNT (), + .RXCOMINITDET (), + .RXCOMMADET (), + .RXCOMMADETEN (1'd1), + .RXCOMSASDET (), + .RXCOMWAKEDET (), + .RXCTRL0 ({rx_charisk_open_s, rx_charisk}), + .RXCTRL1 ({rx_disperr_open_s, rx_disperr}), + .RXCTRL2 (), + .RXCTRL3 ({rx_notintable_open_s, rx_notintable}), + .RXDATA (rx_data_s), + .RXDATAEXTENDRSVD (), + .RXDATAVALID (), + .RXDFEAGCCTRL (2'b01), + .RXDFEAGCHOLD (1'd0), + .RXDFEAGCOVRDEN (1'd0), + .RXDFECFOKFCNUM (4'b1101), + .RXDFECFOKFEN (1'd0), + .RXDFECFOKFPULSE (1'd0), + .RXDFECFOKHOLD (1'd0), + .RXDFECFOKOVREN (1'd0), + .RXDFEKHHOLD (1'd0), + .RXDFEKHOVRDEN (1'd0), + .RXDFELFHOLD (1'd0), + .RXDFELFOVRDEN (1'd0), + .RXDFELPMRESET (1'd0), + .RXDFETAP10HOLD (1'd0), + .RXDFETAP10OVRDEN (1'd0), + .RXDFETAP11HOLD (1'd0), + .RXDFETAP11OVRDEN (1'd0), + .RXDFETAP12HOLD (1'd0), + .RXDFETAP12OVRDEN (1'd0), + .RXDFETAP13HOLD (1'd0), + .RXDFETAP13OVRDEN (1'd0), + .RXDFETAP14HOLD (1'd0), + .RXDFETAP14OVRDEN (1'd0), + .RXDFETAP15HOLD (1'd0), + .RXDFETAP15OVRDEN (1'd0), + .RXDFETAP2HOLD (1'd0), + .RXDFETAP2OVRDEN (1'd0), + .RXDFETAP3HOLD (1'd0), + .RXDFETAP3OVRDEN (1'd0), + .RXDFETAP4HOLD (1'd0), + .RXDFETAP4OVRDEN (1'd0), + .RXDFETAP5HOLD (1'd0), + .RXDFETAP5OVRDEN (1'd0), + .RXDFETAP6HOLD (1'd0), + .RXDFETAP6OVRDEN (1'd0), + .RXDFETAP7HOLD (1'd0), + .RXDFETAP7OVRDEN (1'd0), + .RXDFETAP8HOLD (1'd0), + .RXDFETAP8OVRDEN (1'd0), + .RXDFETAP9HOLD (1'd0), + .RXDFETAP9OVRDEN (1'd0), + .RXDFEUTHOLD (1'd0), + .RXDFEUTOVRDEN (1'd0), + .RXDFEVPHOLD (1'd0), + .RXDFEVPOVRDEN (1'd0), + .RXDFEXYDEN (1'd1), + .RXDLYBYPASS (1'd1), + .RXDLYEN (1'd0), + .RXDLYOVRDEN (1'd0), + .RXDLYSRESET (1'd0), + .RXDLYSRESETDONE (), + .RXELECIDLE (), + .RXELECIDLEMODE (2'b11), + .RXEQTRAINING (1'd0), + .RXGEARBOXSLIP (rx_bitslip_s), + .RXHEADER (rx_header_s), + .RXHEADERVALID (), + .RXLATCLK (1'd0), + .RXLFPSTRESETDET (), + .RXLFPSU2LPEXITDET (), + .RXLFPSU3WAKEDET (), + .RXLPMEN (up_rx_lpm_dfe_n), + .RXLPMGCHOLD (1'd0), + .RXLPMGCOVRDEN (1'd0), + .RXLPMHFHOLD (1'd0), + .RXLPMHFOVRDEN (1'd0), + .RXLPMLFHOLD (1'd0), + .RXLPMLFKLOVRDEN (1'd0), + .RXLPMOSHOLD (1'd0), + .RXLPMOSOVRDEN (1'd0), + .RXMCOMMAALIGNEN (rx_calign), + .RXMONITOROUT (), + .RXMONITORSEL (2'd0), + .RXOOBRESET (1'd0), + .RXOSCALRESET (1'd0), + .RXOSHOLD (1'd0), + .RXOSINTDONE (), + .RXOSINTSTARTED (), + .RXOSINTSTROBEDONE (), + .RXOSINTSTROBESTARTED (), + .RXOSOVRDEN (1'd0), + .RXOUTCLK (rx_out_clk_s), + .RXOUTCLKFABRIC (), + .RXOUTCLKPCS (), + .RXOUTCLKSEL (up_rx_out_clk_sel), + .RXPCOMMAALIGNEN (rx_calign), + .RXPCSRESET (1'd0), + .RXPD (2'd0), + .RXPHALIGN (1'd0), + .RXPHALIGNDONE (), + .RXPHALIGNEN (1'd0), + .RXPHALIGNERR (), + .RXPHDLYPD (1'd1), + .RXPHDLYRESET (1'd0), + .RXPHOVRDEN (1'd0), + .RXPLLCLKSEL (rx_pll_clk_sel_s), + .RXPMARESET (1'd0), + .RXPMARESETDONE (), + .RXPOLARITY (RX_POLARITY), + .RXPRBSCNTRESET (rx_prbscntreset), + .RXPRBSERR (rx_prbserr), + .RXPRBSLOCKED (rx_prbslocked), + .RXPRBSSEL (rx_prbssel), + .RXPRGDIVRESETDONE (), + .RXPROGDIVRESET (up_rx_rst), + .RXQPIEN (1'd0), + .RXQPISENN (), + .RXQPISENP (), + .RXRATE (rx_rate_m2), + .RXRATEDONE (), + .RXRATEMODE (1'd0), + .RXRECCLKOUT (), + .RXRESETDONE (rx_rst_done_s), + .RXSLIDE (1'd0), + .RXSLIDERDY (), + .RXSLIPDONE (), + .RXSLIPOUTCLK (1'd0), + .RXSLIPOUTCLKRDY (), + .RXSLIPPMA (1'd0), + .RXSLIPPMARDY (), + .RXSTARTOFSEQ (), + .RXSTATUS (), + .RXSYNCALLIN (1'd0), + .RXSYNCDONE (), + .RXSYNCIN (1'd0), + .RXSYNCMODE (1'd0), + .RXSYNCOUT (), + .RXSYSCLKSEL (rx_sys_clk_sel_s), + .RXTERMINATION (1'd0), + .RXUSERRDY (up_rx_user_ready), + .RXUSRCLK (rx_usrclk), + .RXUSRCLK2 (rx_usrclk2), + .RXVALID (), + .SIGVALIDCLK (1'd0), + .TSTIN (20'd0), + .TX8B10BBYPASS (8'd0), + .TX8B10BEN (RX8B10BEN), + .TXBUFSTATUS (tx_bufstatus_s), + .TXCOMFINISH (), + .TXCOMINIT (1'd0), + .TXCOMSAS (1'd0), + .TXCOMWAKE (1'd0), + .TXCTRL0 (16'd0), + .TXCTRL1 (16'd0), + .TXCTRL2 ({4'd0, tx_charisk}), + .TXDATA (tx_data_s), + .TXDATAEXTENDRSVD (8'd0), + .TXDCCDONE (), + .TXDCCFORCESTART (1'd0), + .TXDCCRESET (1'd0), + .TXDEEMPH (2'd0), + .TXDETECTRX (1'd0), + .TXDIFFCTRL ({up_tx_diffctrl, 1'b0}), + .TXDLYBYPASS (1'd1), + .TXDLYEN (1'd0), + .TXDLYHOLD (1'd0), + .TXDLYOVRDEN (1'd0), + .TXDLYSRESET (1'd0), + .TXDLYSRESETDONE (), + .TXDLYUPDOWN (1'd0), + .TXELECIDLE (1'd0), + .TXHEADER ({4'b0,tx_header}), + .TXINHIBIT (1'd0), + .TXLATCLK (1'd0), + .TXLFPSTRESET (1'd0), + .TXLFPSU2LPEXIT (1'd0), + .TXLFPSU3WAKE (1'd0), + .TXMAINCURSOR (7'b1000000), + .TXMARGIN (3'd0), + .TXMUXDCDEXHOLD (1'd0), + .TXMUXDCDORWREN (1'd0), + .TXONESZEROS (1'd0), + .TXOUTCLK (tx_out_clk_s), + .TXOUTCLKFABRIC (), + .TXOUTCLKPCS (), + .TXOUTCLKSEL (up_tx_out_clk_sel), + .TXPCSRESET (1'd0), + .TXPD (2'd0), + .TXPDELECIDLEMODE (1'd0), + .TXPHALIGN (1'd0), + .TXPHALIGNDONE (), + .TXPHALIGNEN (1'd0), + .TXPHDLYPD (1'd1), + .TXPHDLYRESET (1'd0), + .TXPHDLYTSTCLK (1'd0), + .TXPHINIT (1'd0), + .TXPHINITDONE (), + .TXPHOVRDEN (1'd0), + .TXPIPPMEN (1'd0), + .TXPIPPMOVRDEN (1'd0), + .TXPIPPMPD (1'd0), + .TXPIPPMSEL (1'd0), + .TXPIPPMSTEPSIZE (5'd0), + .TXPISOPD (1'd0), + .TXPLLCLKSEL (tx_pll_clk_sel_s), + .TXPMARESET (1'd0), + .TXPMARESETDONE (), + .TXPOLARITY (TX_POLARITY), + .TXPOSTCURSOR (up_tx_postcursor), + .TXPRBSFORCEERR (tx_prbsforceerr), + .TXPRBSSEL (tx_prbssel), + .TXPRECURSOR (up_tx_precursor), + .TXPRGDIVRESETDONE (), + .TXPROGDIVRESET (up_tx_rst), + .TXQPIBIASEN (1'd0), + .TXQPISENN (), + .TXQPISENP (), + .TXQPIWEAKPUP (1'd0), + .TXRATE (tx_rate_m2), + .TXRATEDONE (), + .TXRATEMODE (1'd0), + .TXRESETDONE (tx_rst_done_s), + .TXSEQUENCE (7'd0), + .TXSWING (1'd0), + .TXSYNCALLIN (1'd0), + .TXSYNCDONE (), + .TXSYNCIN (1'd0), + .TXSYNCMODE (1'd0), + .TXSYNCOUT (), + .TXSYSCLKSEL (tx_sys_clk_sel_s), + .TXUSERRDY (up_tx_user_ready), + .TXUSRCLK (tx_usrclk), + .TXUSRCLK2 (tx_usrclk2)); + end + endgenerate + + generate + if (XCVR_TYPE == GTYE4_TRANSCEIVERS) begin + BUFG_GT i_rx_bufg ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (1'b0), + .CLRMASK (1'b0), + .DIV (3'd0), + .I (rx_out_clk_s), + .O (rx_out_clk)); + + BUFG_GT i_tx_bufg ( + .CE (1'b1), + .CEMASK (1'b0), + .CLR (1'b0), + .CLRMASK (1'b0), + .DIV (3'd0), + .I (tx_out_clk_s), + .O (tx_out_clk)); + end + endgenerate + + generate + if (XCVR_TYPE == GTYE4_TRANSCEIVERS) begin + assign rx_sys_clk_sel_s = (up_rx_sys_clk_sel[1] == 0) ? 2'b00 : {1'b1,~up_rx_sys_clk_sel[0]}; + assign tx_sys_clk_sel_s = (up_tx_sys_clk_sel[1] == 0) ? 2'b00 : {1'b1,~up_tx_sys_clk_sel[0]}; + assign rx_pll_clk_sel_s = up_rx_sys_clk_sel; + assign tx_pll_clk_sel_s = up_tx_sys_clk_sel; + end + endgenerate + + generate + if (XCVR_TYPE == GTYE4_TRANSCEIVERS) begin + + GTYE4_CHANNEL #( + .ACJTAG_DEBUG_MODE (1'b0), + .ACJTAG_MODE (1'b0), + .ACJTAG_RESET (1'b0), + .ADAPT_CFG0 (16'b0000000000000000), + .ADAPT_CFG1 (16'b1111101100011100), + .ADAPT_CFG2 (16'b0000000000000000), + .ALIGN_COMMA_DOUBLE ("FALSE"), + .ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE), + .ALIGN_COMMA_WORD (1), + .ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET), + .ALIGN_MCOMMA_VALUE (10'b1010000011), + .ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET), + .ALIGN_PCOMMA_VALUE (10'b0101111100), + .A_RXOSCALRESET (1'b0), + .A_RXPROGDIVRESET (1'b0), + .A_RXTERMINATION (1'b1), + .A_TXDIFFCTRL (5'b01100), + .A_TXPROGDIVRESET (1'b0), + .CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL), + .CDR_SWAP_MODE_EN (1'b0), + .CFOK_PWRSVE_EN (1'b1), + .CHAN_BOND_KEEP_ALIGN ("FALSE"), + .CHAN_BOND_MAX_SKEW (1), + .CHAN_BOND_SEQ_1_1 (10'b0000000000), + .CHAN_BOND_SEQ_1_2 (10'b0000000000), + .CHAN_BOND_SEQ_1_3 (10'b0000000000), + .CHAN_BOND_SEQ_1_4 (10'b0000000000), + .CHAN_BOND_SEQ_1_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_1 (10'b0000000000), + .CHAN_BOND_SEQ_2_2 (10'b0000000000), + .CHAN_BOND_SEQ_2_3 (10'b0000000000), + .CHAN_BOND_SEQ_2_4 (10'b0000000000), + .CHAN_BOND_SEQ_2_ENABLE (4'b1111), + .CHAN_BOND_SEQ_2_USE ("FALSE"), + .CHAN_BOND_SEQ_LEN (1), + .CH_HSPMUX (CH_HSPMUX), + .CKCAL1_CFG_0 (16'b1100000011000000), + .CKCAL1_CFG_1 (16'b0001000011000000), + .CKCAL1_CFG_2 (16'b0010000000001000), + .CKCAL1_CFG_3 (16'b0000000000000000), + .CKCAL2_CFG_0 (16'b1100000011000000), + .CKCAL2_CFG_1 (16'b1000000011000000), + .CKCAL2_CFG_2 (16'b0001000000000000), + .CKCAL2_CFG_3 (16'b0000000000000000), + .CKCAL2_CFG_4 (16'b0000000000000000), + .CLK_CORRECT_USE ("FALSE"), + .CLK_COR_KEEP_IDLE ("FALSE"), + .CLK_COR_MAX_LAT (12), + .CLK_COR_MIN_LAT (8), + .CLK_COR_PRECEDENCE ("TRUE"), + .CLK_COR_REPEAT_WAIT (0), + .CLK_COR_SEQ_1_1 (10'b0100000000), + .CLK_COR_SEQ_1_2 (10'b0100000000), + .CLK_COR_SEQ_1_3 (10'b0100000000), + .CLK_COR_SEQ_1_4 (10'b0100000000), + .CLK_COR_SEQ_1_ENABLE (4'b1111), + .CLK_COR_SEQ_2_1 (10'b0100000000), + .CLK_COR_SEQ_2_2 (10'b0100000000), + .CLK_COR_SEQ_2_3 (10'b0100000000), + .CLK_COR_SEQ_2_4 (10'b0100000000), + .CLK_COR_SEQ_2_ENABLE (4'b1111), + .CLK_COR_SEQ_2_USE ("FALSE"), + .CLK_COR_SEQ_LEN (1), + .CPLL_CFG0 (CPLL_CFG0), + .CPLL_CFG1 (CPLL_CFG1), + .CPLL_CFG2 (CPLL_CFG2), + .CPLL_CFG3 (CPLL_CFG3), + .CPLL_FBDIV (CPLL_FBDIV), + .CPLL_FBDIV_45 (CPLL_FBDIV_4_5), + .CPLL_INIT_CFG0 (16'b0000001010110010), + .CPLL_LOCK_CFG (16'b0000000111101000), + .CPLL_REFCLK_DIV (1), + .CTLE3_OCAP_EXT_CTRL (3'b000), + .CTLE3_OCAP_EXT_EN (1'b0), + .DDI_CTRL (2'b00), + .DDI_REALIGN_WAIT (15), + .DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT), + .DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT), + .DEC_VALID_COMMA_ONLY ("FALSE"), + .DELAY_ELEC (1'b0), + .DMONITOR_CFG0 (10'b0000000000), + .DMONITOR_CFG1 (8'b00000000), + .ES_CLK_PHASE_SEL (1'b0), + .ES_CONTROL (6'b000000), + .ES_ERRDET_EN ("TRUE"), + .ES_EYE_SCAN_EN ("TRUE"), + .ES_HORZ_OFFSET (12'b000000000000), + .ES_PRESCALE (5'b00000), + .ES_QUALIFIER0 (16'b0000000000000000), + .ES_QUALIFIER1 (16'b0000000000000000), + .ES_QUALIFIER2 (16'b0000000000000000), + .ES_QUALIFIER3 (16'b0000000000000000), + .ES_QUALIFIER4 (16'b0000000000000000), + .ES_QUALIFIER5 (16'b0000000000000000), + .ES_QUALIFIER6 (16'b0000000000000000), + .ES_QUALIFIER7 (16'b0000000000000000), + .ES_QUALIFIER8 (16'b0000000000000000), + .ES_QUALIFIER9 (16'b0000000000000000), + .ES_QUAL_MASK0 (16'b1111111111111111), + .ES_QUAL_MASK1 (16'b1111111111111111), + .ES_QUAL_MASK2 (16'b1111111111111111), + .ES_QUAL_MASK3 (16'b1111111111111111), + .ES_QUAL_MASK4 (16'b1111111111111111), + .ES_QUAL_MASK5 (16'b1111111111111111), + .ES_QUAL_MASK6 (16'b1111111111111111), + .ES_QUAL_MASK7 (16'b1111111111111111), + .ES_QUAL_MASK8 (16'b1111111111111111), + .ES_QUAL_MASK9 (16'b1111111111111111), + .ES_SDATA_MASK0 (16'b1111111111111111), + .ES_SDATA_MASK1 (16'b1111111111111111), + .ES_SDATA_MASK2 (16'b0000000011111111), + .ES_SDATA_MASK3 (16'b0000000000000000), + .ES_SDATA_MASK4 (16'b0000000000000000), + .ES_SDATA_MASK5 (16'b1111111111111111), + .ES_SDATA_MASK6 (16'b1111111111111111), + .ES_SDATA_MASK7 (16'b1111111111111111), + .ES_SDATA_MASK8 (16'b1111111111111111), + .ES_SDATA_MASK9 (16'b1111111111111111), + .EYESCAN_VP_RANGE (0), + .EYE_SCAN_SWAP_EN (1'b0), + .FTS_DESKEW_SEQ_ENABLE (4'b1111), + .FTS_LANE_DESKEW_CFG (4'b1111), + .FTS_LANE_DESKEW_EN ("FALSE"), + .GEARBOX_MODE (GEARBOX_MODE), + .ISCAN_CK_PH_SEL2 (1'b0), + .LOCAL_MASTER (1'b1), + .LPBK_BIAS_CTRL (4), + .LPBK_EN_RCAL_B (1'b0), + .LPBK_EXT_RCAL (4'b1000), + .LPBK_IND_CTRL0 (5), + .LPBK_IND_CTRL1 (5), + .LPBK_IND_CTRL2 (5), + .LPBK_RG_CTRL (2), + .OOBDIVCTL (2'b00), + .OOB_PWRUP (1'b0), + .PCI3_AUTO_REALIGN ("OVR_1K_BLK"), + .PCI3_PIPE_RX_ELECIDLE (1'b0), + .PCI3_RX_ASYNC_EBUF_BYPASS (2'b00), + .PCI3_RX_ELECIDLE_EI2_ENABLE (1'b0), + .PCI3_RX_ELECIDLE_H2L_COUNT (6'b000000), + .PCI3_RX_ELECIDLE_H2L_DISABLE (3'b000), + .PCI3_RX_ELECIDLE_HI_COUNT (6'b000000), + .PCI3_RX_ELECIDLE_LP4_DISABLE (1'b0), + .PCI3_RX_FIFO_DISABLE (1'b0), + .PCIE3_CLK_COR_EMPTY_THRSH (5'b00000), + .PCIE3_CLK_COR_FULL_THRSH (6'b010000), + .PCIE3_CLK_COR_MAX_LAT (5'b00100), + .PCIE3_CLK_COR_MIN_LAT (5'b00000), + .PCIE3_CLK_COR_THRSH_TIMER (6'b001000), + .PCIE_64B_DYN_CLKSW_DIS ("FALSE"), + .PCIE_BUFG_DIV_CTRL (16'b0011010100000000), + .PCIE_GEN4_64BIT_INT_EN ("FALSE"), + .PCIE_PLL_SEL_MODE_GEN12 (2'b10), + .PCIE_PLL_SEL_MODE_GEN3 (2'b10), + .PCIE_PLL_SEL_MODE_GEN4 (2'b10), + .PCIE_RXPCS_CFG_GEN3 (16'b0000101010100101), + .PCIE_RXPMA_CFG (16'b0010100000001010), + .PCIE_TXPCS_CFG_GEN3 (16'b0010010010100100), + .PCIE_TXPMA_CFG (16'b0010100000001010), + .PCS_PCIE_EN ("FALSE"), + .PCS_RSVD0 (16'b0000000000000000), + .PD_TRANS_TIME_FROM_P2 (12'b000000111100), + .PD_TRANS_TIME_NONE_P2 (8'b00011001), + .PD_TRANS_TIME_TO_P2 (8'b01100100), + .PREIQ_FREQ_BST (PREIQ_FREQ_BST), + .RATE_SW_USE_DRP (1'b1), + .RCLK_SIPO_DLY_ENB (1'b0), + .RCLK_SIPO_INV_EN (1'b0), + .RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL), + .RTX_BUF_TERM_CTRL (2'b00), + .RXBUFRESET_TIME (5'b00011), + .RXBUF_ADDR_MODE ("FAST"), + .RXBUF_EIDLE_HI_CNT (4'b1000), + .RXBUF_EIDLE_LO_CNT (4'b0000), + .RXBUF_EN (RXBUF_EN), + .RXBUF_RESET_ON_CB_CHANGE ("TRUE"), + .RXBUF_RESET_ON_COMMAALIGN ("FALSE"), + .RXBUF_RESET_ON_EIDLE ("FALSE"), + .RXBUF_RESET_ON_RATE_CHANGE ("TRUE"), + .RXBUF_THRESH_OVFLW (57), + .RXBUF_THRESH_OVRD ("TRUE"), + .RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW), + .RXCDRFREQRESET_TIME (5'b00001), + .RXCDRPHRESET_TIME (5'b00001), + .RXCDR_CFG0 (16'b0000000000000011), + .RXCDR_CFG0_GEN3 (16'b0000000000000011), + .RXCDR_CFG1 (16'b0000000000000000), + .RXCDR_CFG1_GEN3 (16'b0000000000000000), + .RXCDR_CFG2 (RXCDR_CFG2), + .RXCDR_CFG2_GEN2 (10'b1001101001), + .RXCDR_CFG2_GEN3 (16'b0000001001101001), + .RXCDR_CFG2_GEN4 (16'b0000000101100100), + .RXCDR_CFG3 (16'b0000000000010010), + .RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2), + .RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3), + .RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4), + .RXCDR_CFG4 (16'b0101110011110110), + .RXCDR_CFG4_GEN3 (16'b0101110011110110), + .RXCDR_CFG5 (16'b1011010001101011), + .RXCDR_CFG5_GEN3 (16'b0001010001101011), + .RXCDR_FR_RESET_ON_EIDLE (1'b0), + .RXCDR_HOLD_DURING_EIDLE (1'b0), + .RXCDR_LOCK_CFG0 (16'b0010001000000001), + .RXCDR_LOCK_CFG1 (16'b1001111111111111), + .RXCDR_LOCK_CFG2 (15'b000000000000000 ), + .RXCDR_LOCK_CFG3 (16'b0000000000000000), + .RXCDR_LOCK_CFG4 (16'b0000000000000000), + .RXCDR_PH_RESET_ON_EIDLE (1'b0), + .RXCFOK_CFG0 (16'b0000000000000000), + .RXCFOK_CFG1 (16'b1000000000010101), + .RXCFOK_CFG2 (16'b0000001010101110), + .RXCKCAL1_IQ_LOOP_RST_CFG (16'b0000000000000000), + .RXCKCAL1_I_LOOP_RST_CFG (16'b0000000000000000), + .RXCKCAL1_Q_LOOP_RST_CFG (16'b0000000000000000), + .RXCKCAL2_DX_LOOP_RST_CFG (16'b0000000000000000), + .RXCKCAL2_D_LOOP_RST_CFG (16'b0000000000000000), + .RXCKCAL2_S_LOOP_RST_CFG (16'b0000000000000000), + .RXCKCAL2_X_LOOP_RST_CFG (16'b0000000000000000), + .RXDFELPMRESET_TIME (7'b0001111), + .RXDFELPM_KL_CFG0 (15'b000000000000000), + .RXDFELPM_KL_CFG1 (16'b1010000010000010), + .RXDFELPM_KL_CFG2 (16'b0000000100000000), + .RXDFE_CFG0 (16'b0000101000000000), + .RXDFE_CFG1 (16'b0000000000000000), + .RXDFE_GC_CFG0 (16'b0000000000000000), + .RXDFE_GC_CFG1 (16'b1000000000000000), + .RXDFE_GC_CFG2 (16'b1111111111100000), + .RXDFE_H2_CFG0 (16'b0000000000000000), + .RXDFE_H2_CFG1 (16'b0000000000000010), + .RXDFE_H3_CFG0 (16'b0000000000000000), + .RXDFE_H3_CFG1 (16'b1000000000000010), + .RXDFE_H4_CFG0 (16'b0000000000000000), + .RXDFE_H4_CFG1 (16'b1000000000000010), + .RXDFE_H5_CFG0 (16'b0000000000000000), + .RXDFE_H5_CFG1 (16'b1000000000000010), + .RXDFE_H6_CFG0 (16'b0000000000000000), + .RXDFE_H6_CFG1 (16'b1000000000000010), + .RXDFE_H7_CFG0 (16'b0000000000000000), + .RXDFE_H7_CFG1 (16'b1000000000000010), + .RXDFE_H8_CFG0 (16'b0000000000000000), + .RXDFE_H8_CFG1 (16'b1000000000000010), + .RXDFE_H9_CFG0 (16'b0000000000000000), + .RXDFE_H9_CFG1 (16'b1000000000000010), + .RXDFE_HA_CFG0 (16'b0000000000000000), + .RXDFE_HA_CFG1 (16'b1000000000000010), + .RXDFE_HB_CFG0 (16'b0000000000000000), + .RXDFE_HB_CFG1 (16'b1000000000000010), + .RXDFE_HC_CFG0 (16'b0000000000000000), + .RXDFE_HC_CFG1 (16'b1000000000000010), + .RXDFE_HD_CFG0 (16'b0000000000000000), + .RXDFE_HD_CFG1 (16'b1000000000000010), + .RXDFE_HE_CFG0 (16'b0000000000000000), + .RXDFE_HE_CFG1 (16'b1000000000000010), + .RXDFE_HF_CFG0 (16'b0000000000000000), + .RXDFE_HF_CFG1 (16'b1000000000000010), + .RXDFE_KH_CFG0 (16'b1000000000000000), + .RXDFE_KH_CFG1 (16'b1111111000000000), + .RXDFE_KH_CFG2 (RXDFE_KH_CFG2), + .RXDFE_KH_CFG3 (RXDFE_KH_CFG3), + .RXDFE_OS_CFG0 (16'b0010000000000000), + .RXDFE_OS_CFG1 (16'b1000000000000000), + .RXDFE_UT_CFG0 (16'b0000000000000000), + .RXDFE_UT_CFG1 (16'b0000000000000011), + .RXDFE_UT_CFG2 (16'b0000000000000000), + .RXDFE_VP_CFG0 (16'b0000000000000000), + .RXDFE_VP_CFG1 (16'b0000000000110011), + .RXDLY_CFG (16'b0000000000010000), + .RXDLY_LCFG (16'b0000000000110000), + .RXELECIDLE_CFG ("SIGCFG_4"), + .RXGBOX_FIFO_INIT_RD_ADDR (RXGBOX_FIFO_INIT_RD_ADDR), + .RXGEARBOX_EN (RXGEARBOX_EN), + .RXISCANRESET_TIME (5'b00001), + .RXLPM_CFG (16'b0000000000000000), + .RXLPM_GC_CFG (16'b1111100000000000), + .RXLPM_KH_CFG0 (16'b0000000000000000), + .RXLPM_KH_CFG1 (16'b1010000000000010), + .RXLPM_OS_CFG0 (16'b0000000000000000), + .RXLPM_OS_CFG1 (16'b1000000000000010), + .RXOOB_CFG (9'b000000110), + .RXOOB_CLK_CFG ("PMA"), + .RXOSCALRESET_TIME (5'b00011), + .RXOUT_DIV (RX_OUT_DIV), + .RXPCSRESET_TIME (5'b00011), + .RXPHBEACON_CFG (16'b0000000000000000), + .RXPHDLY_CFG (16'b0010000001110000), + .RXPHSAMP_CFG (16'b0010000100000000), + .RXPHSLIP_CFG (16'b1001100100110011), + .RXPH_MONITOR_SEL (5'b00000), + .RXPI_CFG0 (RXPI_CFG0), + .RXPI_CFG1 (RXPI_CFG1), + .RXPMACLK_SEL ("DATA"), + .RXPMARESET_TIME (5'b00011), + .RXPRBS_ERR_LOOPBACK (1'b0), + .RXPRBS_LINKACQ_CNT (15), + .RXREFCLKDIV2_SEL (1'b0), + .RXSLIDE_AUTO_WAIT (7), + .RXSLIDE_MODE ("OFF"), + .RXSYNC_MULTILANE (1'b1), + .RXSYNC_OVRD (1'b0), + .RXSYNC_SKIP_DA (1'b0), + .RX_AFE_CM_EN (1'b0), + .RX_BIAS_CFG0 (16'b0001001010110000), + .RX_BUFFER_CFG (6'b000000), + .RX_CAPFF_SARC_ENB (1'b0), + .RX_CLK25_DIV (RX_CLK25_DIV), + .RX_CLKMUX_EN (1'b1), + .RX_CLK_SLIP_OVRD (5'b00000), + .RX_CM_BUF_CFG (4'b1010), + .RX_CM_BUF_PD (1'b0), + .RX_CM_SEL (3), + .RX_CM_TRIM (10), + .RX_CTLE_PWR_SAVING (1'b0), + .RX_CTLE_RES_CTRL (4'b0000), + .RX_DATA_WIDTH (RX_DATA_WIDTH), + .RX_DDI_SEL (6'b000000), + .RX_DEFER_RESET_BUF_EN ("TRUE"), + .RX_DEGEN_CTRL (3'b100), + .RX_DFELPM_CFG0 (10), + .RX_DFELPM_CFG1 (1'b1), + .RX_DFELPM_KLKH_AGC_STUP_EN (1'b1), + .RX_DFE_AGC_CFG1 (2), + .RX_DFE_KL_LPM_KH_CFG0 (3), + .RX_DFE_KL_LPM_KH_CFG1 (2), + .RX_DFE_KL_LPM_KL_CFG0 (2'b11), + .RX_DFE_KL_LPM_KL_CFG1 (2), + .RX_DFE_LPM_HOLD_DURING_EIDLE (1'b0), + .RX_DISPERR_SEQ_MATCH ("TRUE"), + .RX_DIVRESET_TIME (5'b00001), + .RX_EN_CTLE_RCAL_B (1'b0), + .RX_EN_SUM_RCAL_B (0), + .RX_EYESCAN_VS_CODE (7'b0000000), + .RX_EYESCAN_VS_NEG_DIR (1'b0), + .RX_EYESCAN_VS_RANGE (2'b00), + .RX_EYESCAN_VS_UT_SIGN (1'b0), + .RX_FABINT_USRCLK_FLOP (1'b0), + .RX_I2V_FILTER_EN (1'b1), + .RX_INT_DATAWIDTH (RX_INT_DATAWIDTH), + .RX_PMA_POWER_SAVE (1'b0), + .RX_PMA_RSV0 (16'b0000000000101111), + .RX_PROGDIV_CFG (0.0), + .RX_PROGDIV_RATE (16'b0000000000000001), + .RX_RESLOAD_CTRL (4'b0000), + .RX_RESLOAD_OVRD (1'b0), + .RX_SAMPLE_PERIOD (3'b111), + .RX_SIG_VALID_DLY (11), + .RX_SUM_DEGEN_AVTT_OVERITE (0), + .RX_SUM_DFETAPREP_EN (1'b0), + .RX_SUM_IREF_TUNE (4'b0000), + .RX_SUM_PWR_SAVING (0), + .RX_SUM_RES_CTRL (4'b0000), + .RX_SUM_VCMTUNE (4'b0011), + .RX_SUM_VCM_BIAS_TUNE_EN (1'b1), + .RX_SUM_VCM_OVWR (1'b0), + .RX_SUM_VREF_TUNE (3'b100), + .RX_TUNE_AFE_OS (2'b10), + .RX_VREG_CTRL (3'b010), + .RX_VREG_PDB (1'b1), + .RX_WIDEMODE_CDR (RX_WIDEMODE_CDR), + .RX_WIDEMODE_CDR_GEN3 (2'b00), + .RX_WIDEMODE_CDR_GEN4 (2'b01), + .RX_XCLK_SEL ("RXDES"), + .RX_XMODE_SEL (RX_XMODE_SEL), + .SAMPLE_CLK_PHASE (1'b0), + .SAS_12G_MODE (1'b0), + .SATA_BURST_SEQ_LEN (4'b1111), + .SATA_BURST_VAL (3'b100), + .SATA_CPLL_CFG ("VCO_3000MHZ"), + .SATA_EIDLE_VAL (3'b100), + .SHOW_REALIGN_COMMA ("TRUE"), + .SIM_MODE ("FAST"), + .SIM_RECEIVER_DETECT_PASS ("TRUE"), + .SIM_RESET_SPEEDUP ("TRUE"), + .SIM_TX_EIDLE_DRIVE_LEVEL ("Z"), + .SIM_DEVICE ("ULTRASCALE_PLUS"), + .SRSTMODE (1'b0), + .TAPDLY_SET_TX (2'b00), + .TERM_RCAL_CFG (15'b100001000000010), + .TERM_RCAL_OVRD (3'b001), + .TRANS_TIME_RATE (8'b00001110), + .TST_RSV0 (8'b00000000), + .TST_RSV1 (8'b00000000), + .TXBUF_EN (TXBUF_EN), + .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), + .TXDLY_CFG (16'b1000000000010000), + .TXDLY_LCFG (16'b0000000000110000), + .TXDRV_FREQBAND (TXDRV_FREQBAND), + .TXFE_CFG0 (TXFE_CFG0), + .TXFE_CFG1 (TXFE_CFG1), + .TXFE_CFG2 (TXFE_CFG2), + .TXFE_CFG3 (TXFE_CFG3), + .TXFIFO_ADDR_CFG ("LOW"), + .TXGBOX_FIFO_INIT_RD_ADDR (4), + .TXGEARBOX_EN (TXGEARBOX_EN), + .TXOUT_DIV (TX_OUT_DIV), + .TXPCSRESET_TIME (5'b00011), + .TXPHDLY_CFG0 (16'b0110000001110000), + .TXPHDLY_CFG1 (16'h000F), + .TXPH_CFG (16'h0323), + .TXPH_CFG2 (16'b0000000000000000), + .TXPH_MONITOR_SEL (5'b00000), + .TXPI_CFG0 (TXPI_CFG0), + .TXPI_CFG1 (TXPI_CFG1), + .TXPI_GRAY_SEL (1'b0), + .TXPI_INVSTROBE_SEL (1'b0), + .TXPI_PPM (1'b0), + .TXPI_PPM_CFG (8'b00000000), + .TXPI_SYNFREQ_PPM (3'b001), + .TXPMARESET_TIME (5'b00011), + .TXREFCLKDIV2_SEL (1'b0), + .TXSWBST_BST (1), + .TXSWBST_EN (TXSWBST_EN), + .TXSWBST_MAG (4), + .TXSYNC_MULTILANE (1'b1), + .TXSYNC_OVRD (1'b0), + .TXSYNC_SKIP_DA (1'b0), + .TX_CLK25_DIV (TX_CLK25_DIV), + .TX_CLKMUX_EN (1'b1), + .TX_DATA_WIDTH (TX_DATA_WIDTH), + .TX_DCC_LOOP_RST_CFG (16'b0000000000000100), + .TX_DEEMPH0 (6'b000000), + .TX_DEEMPH1 (6'b000000), + .TX_DEEMPH2 (6'b000000), + .TX_DEEMPH3 (6'b000000), + .TX_DIVRESET_TIME (5'b00001), + .TX_DRIVE_MODE ("DIRECT"), + .TX_EIDLE_ASSERT_DELAY (3'b100), + .TX_EIDLE_DEASSERT_DELAY (3'b011), + .TX_FABINT_USRCLK_FLOP (1'b0), + .TX_FIFO_BYP_EN (1'b0), + .TX_IDLE_DATA_ZERO (1'b0), + .TX_INT_DATAWIDTH (TX_INT_DATAWIDTH), + .TX_LOOPBACK_DRIVE_HIZ ("FALSE"), + .TX_MAINCURSOR_SEL (1'b0), + .TX_MARGIN_FULL_0 (7'b1011000), + .TX_MARGIN_FULL_1 (7'b1010111), + .TX_MARGIN_FULL_2 (7'b1010101), + .TX_MARGIN_FULL_3 (7'b1010011), + .TX_MARGIN_FULL_4 (7'b1010001), + .TX_MARGIN_LOW_0 (7'b1001100), + .TX_MARGIN_LOW_1 (7'b1001011), + .TX_MARGIN_LOW_2 (7'b1001000), + .TX_MARGIN_LOW_3 (7'b1000010), + .TX_MARGIN_LOW_4 (7'b1000000), + .TX_PHICAL_CFG0 (16'b0000000000100000), + .TX_PHICAL_CFG1 (16'b0000000001000000), + .TX_PI_BIASSET (TX_PI_BIASSET), + .TX_PMADATA_OPT (1'b0), + .TX_PMA_POWER_SAVE (1'b0), + .TX_PMA_RSV0 (16'b0000000000000000), + .TX_PMA_RSV1 (16'b0000000000000000), + .TX_PROGCLK_SEL ("PREPI"), + .TX_PROGDIV_CFG (0.0), + .TX_PROGDIV_RATE (16'b0000000000000001), + .TX_RXDETECT_CFG (14'h032), + .TX_RXDETECT_REF (5), + .TX_SAMPLE_PERIOD (3'b111), + .TX_SW_MEAS (2'b00), + .TX_VREG_CTRL (3'b011), + .TX_VREG_PDB (1'b1), + .TX_VREG_VREFSEL (2'b10), + .TX_XCLK_SEL ("TXOUT"), + .USB_BOTH_BURST_IDLE (1'b0), + .USB_BURSTMAX_U3WAKE (7'b1111111), + .USB_BURSTMIN_U3WAKE (7'b1100011), + .USB_CLK_COR_EQ_EN (1'b0), + .USB_EXT_CNTL (1'b1), + .USB_IDLEMAX_POLLING (10'b1010111011), + .USB_IDLEMIN_POLLING (10'b0100101011), + .USB_LFPSPING_BURST (9'b000000101), + .USB_LFPSPOLLING_BURST (9'b000110001), + .USB_LFPSPOLLING_IDLE_MS (9'b000000100), + .USB_LFPSU1EXIT_BURST (9'b000011101), + .USB_LFPSU2LPEXIT_BURST_MS (9'b001100011), + .USB_LFPSU3WAKE_BURST_MS (9'b111110011), + .USB_LFPS_TPERIOD (4'b0011), + .USB_LFPS_TPERIOD_ACCURATE (1'b1), + .USB_MODE (1'b0), + .USB_PCIE_ERR_REP_DIS (1'b0), + .USB_PING_SATA_MAX_INIT (21), + .USB_PING_SATA_MIN_INIT (12), + .USB_POLL_SATA_MAX_BURST (8), + .USB_POLL_SATA_MIN_BURST (4), + .USB_RAW_ELEC (1'b0), + .USB_RXIDLE_P0_CTRL (1'b1), + .USB_TXIDLE_TUNE_ENABLE (1'b1), + .USB_U1_SATA_MAX_WAKE (7), + .USB_U1_SATA_MIN_WAKE (4), + .USB_U2_SAS_MAX_COM (64), + .USB_U2_SAS_MIN_COM (36), + .USE_PCS_CLK_PHASE_SEL (1'b0), + .Y_ALL_MODE (1'b0) + ) i_gtye4_channel ( + .CDRSTEPDIR (1'b0), + .CDRSTEPSQ (1'b0), + .CDRSTEPSX (1'b0), + .CFGRESET (1'b0), + .CLKRSVD0 (1'b0), + .CLKRSVD1 (1'b0), + .CPLLFREQLOCK (1'b0), + .CPLLLOCKDETCLK (up_clk), + .CPLLLOCKEN (1'b1), + .CPLLPD (up_cpll_rst), + .CPLLREFCLKSEL (3'b001), + .CPLLRESET (1'b0), + .DMONFIFORESET (1'b0), + .DMONITORCLK (1'b0), + .DRPADDR (up_addr_int[9:0]), + .DRPCLK (up_clk), + .DRPDI (up_wdata_int), + .DRPEN (up_enb_int), + .DRPRST (1'd0), + .DRPWE (up_wr_int), + .EYESCANRESET (up_es_reset), + .EYESCANTRIGGER (1'b0), + .FREQOS (1'b0), + .GTGREFCLK (1'b0), + .GTNORTHREFCLK0 (1'b0), + .GTNORTHREFCLK1 (1'b0), + .GTREFCLK0 (cpll_ref_clk), + .GTREFCLK1 (1'b0), + .GTRSVD (16'b0000000000000000), + .GTRXRESET (up_rx_rst), + .GTRXRESETSEL (1'b0), + .GTSOUTHREFCLK0 (1'b0), + .GTSOUTHREFCLK1 (1'b0), + .GTTXRESET (up_tx_rst), + .GTTXRESETSEL (1'b0), + .GTYRXN (rx_n), + .GTYRXP (rx_p), + .INCPCTRL (1'b0), + .LOOPBACK (3'b000), + .PCIEEQRXEQADAPTDONE (1'b0), + .PCIERSTIDLE (1'b0), + .PCIERSTTXSYNCSTART (1'b0), + .PCIEUSERRATEDONE (1'b0), + .PCSRSVDIN (16'b0000000000000000), + .QPLL0CLK (qpll2ch_clk), + .QPLL0FREQLOCK (1'b0), + .QPLL0REFCLK (qpll2ch_ref_clk), + .QPLL1CLK (qpll1_clk), + .QPLL1FREQLOCK (1'b0), + .QPLL1REFCLK (qpll1_ref_clk), + .RESETOVRD (1'b0), + .RX8B10BEN (RX8B10BEN), + .RXAFECFOKEN (1'b1), + .RXBUFRESET (1'b0), + .RXCDRFREQRESET (1'b0), + .RXCDRHOLD (1'b0), + .RXCDROVRDEN (1'b0), + .RXCDRRESET (1'b0), + .RXCHBONDEN (1'b0), + .RXCHBONDI (5'b00000), + .RXCHBONDLEVEL (3'b000), + .RXCHBONDMASTER (1'b0), + .RXCHBONDSLAVE (1'b0), + .RXCKCALRESET (1'b0), + .RXCKCALSTART (7'b0000000), + .RXCOMMADETEN (1'b1), + .RXDFEAGCHOLD (1'b0), + .RXDFEAGCOVRDEN (1'b0), + .RXDFECFOKFCNUM (4'b1101), + .RXDFECFOKFEN (1'b0), + .RXDFECFOKFPULSE (1'b0), + .RXDFECFOKHOLD (1'b0), + .RXDFECFOKOVREN (1'b0), + .RXDFEKHHOLD (1'b0), + .RXDFEKHOVRDEN (1'b0), + .RXDFELFHOLD (1'b0), + .RXDFELFOVRDEN (1'b0), + .RXDFELPMRESET (1'b0), + .RXDFETAP10HOLD (1'b0), + .RXDFETAP10OVRDEN (1'b0), + .RXDFETAP11HOLD (1'b0), + .RXDFETAP11OVRDEN (1'b0), + .RXDFETAP12HOLD (1'b0), + .RXDFETAP12OVRDEN (1'b0), + .RXDFETAP13HOLD (1'b0), + .RXDFETAP13OVRDEN (1'b0), + .RXDFETAP14HOLD (1'b0), + .RXDFETAP14OVRDEN (1'b0), + .RXDFETAP15HOLD (1'b0), + .RXDFETAP15OVRDEN (1'b0), + .RXDFETAP2HOLD (1'b0), + .RXDFETAP2OVRDEN (1'b0), + .RXDFETAP3HOLD (1'b0), + .RXDFETAP3OVRDEN (1'b0), + .RXDFETAP4HOLD (1'b0), + .RXDFETAP4OVRDEN (1'b0), + .RXDFETAP5HOLD (1'b0), + .RXDFETAP5OVRDEN (1'b0), + .RXDFETAP6HOLD (1'b0), + .RXDFETAP6OVRDEN (1'b0), + .RXDFETAP7HOLD (1'b0), + .RXDFETAP7OVRDEN (1'b0), + .RXDFETAP8HOLD (1'b0), + .RXDFETAP8OVRDEN (1'b0), + .RXDFETAP9HOLD (1'b0), + .RXDFETAP9OVRDEN (1'b0), + .RXDFEUTHOLD (1'b0), + .RXDFEUTOVRDEN (1'b0), + .RXDFEVPHOLD (1'b0), + .RXDFEVPOVRDEN (1'b0), + .RXDFEXYDEN (1'b0), + .RXDLYBYPASS (1'b1), + .RXDLYEN (1'b0), + .RXDLYOVRDEN (1'b0), + .RXDLYSRESET (1'b0), + .RXELECIDLEMODE (2'b11), + .RXEQTRAINING (1'b0), + .RXGEARBOXSLIP (rx_bitslip_s), + .RXLATCLK (1'b0), + .RXLPMEN (up_rx_lpm_dfe_n), + .RXLPMGCHOLD (1'b0), + .RXLPMGCOVRDEN (1'b0), + .RXLPMHFHOLD (1'b0), + .RXLPMHFOVRDEN (1'b0), + .RXLPMLFHOLD (1'b0), + .RXLPMLFKLOVRDEN (1'b0), + .RXLPMOSHOLD (1'b0), + .RXLPMOSOVRDEN (1'b0), + .RXMCOMMAALIGNEN (rx_calign), + .RXMONITORSEL (2'b00), + .RXOOBRESET (1'b0), + .RXOSCALRESET (1'b0), + .RXOSHOLD (1'b0), + .RXOSOVRDEN (1'b0), + .RXOUTCLKSEL (up_rx_out_clk_sel), + .RXPCOMMAALIGNEN (rx_calign), + .RXPCSRESET (1'b0), + .RXPD (2'b0), + .RXPHALIGN (1'b0), + .RXPHALIGNEN (1'b0), + .RXPHDLYPD (1'b0), + .RXPHDLYRESET (1'b0), + .RXPLLCLKSEL (rx_pll_clk_sel_s), + .RXPMARESET (1'b0), + .RXPOLARITY (RX_POLARITY), + .RXPRBSCNTRESET (rx_prbscntreset), + .RXPRBSSEL (rx_prbssel), + .RXPROGDIVRESET (up_rx_rst), + .RXRATE (rx_rate_m2), + .RXRATEMODE (1'b0), + .RXSLIDE (1'b0), + .RXSLIPOUTCLK (1'b0), + .RXSLIPPMA (1'b0), + .RXSYNCALLIN (1'b0), + .RXSYNCIN (1'b0), + .RXSYNCMODE (1'b0), + .RXSYSCLKSEL (rx_sys_clk_sel_s), + .RXTERMINATION (1'b0), + .RXUSERRDY (up_rx_user_ready), + .RXUSRCLK (rx_usrclk), + .RXUSRCLK2 (rx_usrclk2), + .SIGVALIDCLK (1'b0), + .TSTIN (20'b00000000000000000000), + .TX8B10BBYPASS (8'b0), + .TX8B10BEN (TX8B10BEN), + .TXCOMINIT (1'b0), + .TXCOMSAS (1'b0), + .TXCOMWAKE (1'b0), + .TXCTRL0 (16'b0000000000000000), + .TXCTRL1 (16'b0000000000000000), + .TXCTRL2 ({4'd0, tx_charisk}), + .TXDATA (tx_data_s), + .TXDATAEXTENDRSVD (8'b00000000), + .TXDCCFORCESTART (1'b0), + .TXDCCRESET (1'b0), + .TXDEEMPH (2'b00), + .TXDETECTRX (1'b0), + .TXDIFFCTRL (up_tx_diffctrl), + .TXDLYBYPASS (1'b1), + .TXDLYEN (1'b0), + .TXDLYHOLD (1'b0), + .TXDLYOVRDEN (1'b0), + .TXDLYSRESET (1'b0), + .TXDLYUPDOWN (1'b0), + .TXELECIDLE (1'b0), + .TXHEADER ({4'b0,tx_header}), + .TXINHIBIT (1'b0), + .TXLATCLK (1'b0), + .TXLFPSTRESET (1'b0), + .TXLFPSU2LPEXIT (1'b0), + .TXLFPSU3WAKE (1'b0), + .TXMAINCURSOR (7'b1010000), + .TXMARGIN (3'b000), + .TXMUXDCDEXHOLD (1'b0), + .TXMUXDCDORWREN (1'b0), + .TXONESZEROS (1'b0), + .TXOUTCLKSEL (up_tx_out_clk_sel), + .TXPCSRESET (1'b0), + .TXPD (2'b0), + .TXPDELECIDLEMODE (1'b0), + .TXPHALIGN (1'b0), + .TXPHALIGNEN (1'b0), + .TXPHDLYPD (1'b1), + .TXPHDLYRESET (1'b0), + .TXPHDLYTSTCLK (1'b0), + .TXPHINIT (1'b0), + .TXPHOVRDEN (1'b0), + .TXPIPPMEN (1'b0), + .TXPIPPMOVRDEN (1'b0), + .TXPIPPMPD (1'b0), + .TXPIPPMSEL (1'b0), + .TXPIPPMSTEPSIZE (5'b00000), + .TXPISOPD (1'b0), + .TXPLLCLKSEL (tx_pll_clk_sel_s), + .TXPMARESET (1'b0), + .TXPOLARITY (TX_POLARITY), + .TXPOSTCURSOR (up_tx_postcursor), + .TXPRBSFORCEERR (tx_prbsforceerr), + .TXPRBSSEL (tx_prbssel), + .TXPRECURSOR (up_tx_precursor), + .TXPROGDIVRESET (up_tx_rst), + .TXRATE (tx_rate_m2), + .TXRATEMODE (1'b0), + .TXSEQUENCE (7'b0000000), + .TXSWING (1'b0), + .TXSYNCALLIN (1'b0), + .TXSYNCIN (1'b0), + .TXSYNCMODE (1'b0), + .TXSYSCLKSEL (tx_sys_clk_sel_s), + .TXUSERRDY (up_tx_user_ready), + .TXUSRCLK (tx_usrclk), + .TXUSRCLK2 (tx_usrclk2), + .BUFGTCE (), + .BUFGTCEMASK (), + .BUFGTDIV (), + .BUFGTRESET (), + .BUFGTRSTMASK (), + .CPLLFBCLKLOST (), + .CPLLLOCK (cpll_locked_s), + .CPLLREFCLKLOST (), + .DMONITOROUT (), + .DMONITOROUTCLK (), + .DRPDO (up_rdata_s), + .DRPRDY (up_ready_s), + .EYESCANDATAERROR (), + .GTPOWERGOOD (), + .GTREFCLKMONITOR (), + .GTYTXN (tx_n), + .GTYTXP (tx_p), + .PCIERATEGEN3 (), + .PCIERATEIDLE (), + .PCIERATEQPLLPD (), + .PCIERATEQPLLRESET (), + .PCIESYNCTXSYNCDONE (), + .PCIEUSERGEN3RDY (), + .PCIEUSERPHYSTATUSRST (), + .PCIEUSERRATESTART (), + .PCSRSVDOUT (), + .PHYSTATUS (), + .PINRSRVDAS (), + .POWERPRESENT (), + .RESETEXCEPTION (), + .RXBUFSTATUS (rx_bufstatus_s), + .RXBYTEISALIGNED (), + .RXBYTEREALIGN (), + .RXCDRLOCK (), + .RXCDRPHDONE (), + .RXCHANBONDSEQ (), + .RXCHANISALIGNED (), + .RXCHANREALIGN (), + .RXCHBONDO (), + .RXCKCALDONE (), + .RXCLKCORCNT (), + .RXCOMINITDET (), + .RXCOMMADET (), + .RXCOMSASDET (), + .RXCOMWAKEDET (), + .RXCTRL0 ({rx_charisk_open_s, rx_charisk}), + .RXCTRL1 ({rx_disperr_open_s, rx_disperr}), + .RXCTRL2 (), + .RXCTRL3 ({rx_notintable_open_s, rx_notintable}), + .RXDATA (rx_data_s), + .RXDATAEXTENDRSVD (), + .RXDATAVALID (), + .RXDLYSRESETDONE (), + .RXELECIDLE (), + .RXHEADER (rx_header_s), + .RXHEADERVALID (), + .RXLFPSTRESETDET (), + .RXLFPSU2LPEXITDET (), + .RXLFPSU3WAKEDET (), + .RXMONITOROUT (), + .RXOSINTDONE (), + .RXOSINTSTARTED (), + .RXOSINTSTROBEDONE (), + .RXOSINTSTROBESTARTED (), + .RXOUTCLK (rx_out_clk_s), + .RXOUTCLKFABRIC (), + .RXOUTCLKPCS (), + .RXPHALIGNDONE (), + .RXPHALIGNERR (), + .RXPMARESETDONE (), + .RXPRBSERR (rx_prbserr), + .RXPRBSLOCKED (rx_prbslocked), + .RXPRGDIVRESETDONE (), + .RXRATEDONE (), + .RXRECCLKOUT (), + .RXRESETDONE (rx_rst_done_s), + .RXSLIDERDY (), + .RXSLIPDONE (), + .RXSLIPOUTCLKRDY (), + .RXSLIPPMARDY (), + .RXSTARTOFSEQ (), + .RXSTATUS (), + .RXSYNCDONE (), + .RXSYNCOUT (), + .RXVALID (), + .TXBUFSTATUS (tx_bufstatus_s), + .TXCOMFINISH (), + .TXDCCDONE (), + .TXDLYSRESETDONE (), + .TXOUTCLK (tx_out_clk_s), + .TXOUTCLKFABRIC (), + .TXOUTCLKPCS (), + .TXPHALIGNDONE (), + .TXPHINITDONE (), + .TXPMARESETDONE (), + .TXPRGDIVRESETDONE (), + .TXRATEDONE (), + .TXRESETDONE (tx_rst_done_s), + .TXSYNCDONE (), + .TXSYNCOUT ()); + end + endgenerate +endmodule diff --git a/adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v b/adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v new file mode 100644 index 00000000..7b95fc54 --- /dev/null +++ b/adi_library/xilinx/util_adxcvr/util_adxcvr_xcm.v @@ -0,0 +1,740 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ps + +module util_adxcvr_xcm #( + + // parameters + + parameter integer XCVR_TYPE = 0, + parameter integer QPLL_REFCLK_DIV = 1, + parameter integer QPLL_FBDIV_RATIO = 1, + parameter [15:0] POR_CFG = 16'b0000000000000110, + parameter [15:0] PPF0_CFG = 16'b0000011000000000, + parameter [15:0] PPF1_CFG = 16'b0000011000000000, + parameter [26:0] QPLL_CFG = 27'h0680181, + parameter [ 9:0] QPLL_FBDIV = 10'b0000110000, + parameter [15:0] QPLL_CFG0 = 16'b0011001100011100, + parameter [15:0] QPLL_CFG1 = 16'b1101000000111000, + parameter [15:0] QPLL_CFG1_G3 = 16'b1101000000111000, + parameter [15:0] QPLL_CFG2 = 16'b0000111111000000, + parameter [15:0] QPLL_CFG2_G3 = 16'b0000111111000000, + parameter [15:0] QPLL_CFG3 = 16'b0000000100100000, + parameter [15:0] QPLL_CFG4 = 16'b0000000000000011, + parameter [15:0] QPLL_CP_G3 = 10'b0000011111, + parameter [15:0] QPLL_LPF = 10'b0100110111, + parameter [15:0] QPLL_CP = 10'b0001111111 +) ( + + // reset and clocks + + input qpll_ref_clk, + input qpll_sel, + output qpll2ch_clk, + output qpll2ch_ref_clk, + output qpll2ch_locked, + + output qpll1_clk, + output qpll1_ref_clk, + output qpll1_locked, + + // drp interface + + input up_rstn, + input up_clk, + input up_qpll_rst, + input up_cm_enb, + input [11:0] up_cm_addr, + input up_cm_wr, + input [15:0] up_cm_wdata, + output [15:0] up_cm_rdata, + output up_cm_ready +); + + localparam GTXE2_TRANSCEIVERS = 2; + localparam GTHE3_TRANSCEIVERS = 5; + localparam GTHE4_TRANSCEIVERS = 8; + localparam GTYE4_TRANSCEIVERS = 9; + + // internal registers + + reg up_enb_int = 'd0; + reg [11:0] up_addr_int = 'd0; + reg up_wr_int = 'd0; + reg [15:0] up_wdata_int = 'd0; + reg [15:0] up_rdata_int = 'd0; + reg up_ready_int = 'd0; + reg up_sel_int = 'd0; + + // internal signals + + wire [15:0] up_rdata_s; + wire up_ready_s; + + // drp access + + assign up_cm_rdata = up_rdata_int; + assign up_cm_ready = up_ready_int; + + always @(negedge up_rstn or posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_enb_int <= 1'd0; + up_addr_int <= 12'd0; + up_wr_int <= 1'd0; + up_wdata_int <= 16'd0; + up_rdata_int <= 16'd0; + up_ready_int <= 1'd0; + up_sel_int <= 1'b0; + end else begin + if (up_cm_enb == 1'b1) begin + up_enb_int <= up_cm_enb; + up_addr_int <= up_cm_addr; + up_wr_int <= up_cm_wr; + up_wdata_int <= up_cm_wdata; + end else begin + up_enb_int <= 1'd0; + up_addr_int <= 12'd0; + up_wr_int <= 1'd0; + up_wdata_int <= 16'd0; + end + + if (up_cm_enb == 1'b1) begin + up_sel_int <= 1'b1; + end else if (up_ready_s == 1'b1) begin + up_sel_int <= 1'b0; + end + + if (up_sel_int == 1'b1) begin + up_ready_int <= up_ready_s; + up_rdata_int <= up_rdata_s; + end else begin + up_ready_int <= 1'b0; + up_rdata_int <= 'h00; + end + end + end + + // instantiations + + generate + if (XCVR_TYPE == GTXE2_TRANSCEIVERS) begin + assign qpll1_locked = 1'b0; + assign qpll1_clk = 1'b0; + assign qpll1_ref_clk = 1'b0; + GTXE2_COMMON #( + .BIAS_CFG (64'h0000040000001000), + .COMMON_CFG (32'h00000000), + .IS_DRPCLK_INVERTED (1'b0), + .IS_GTGREFCLK_INVERTED (1'b0), + .IS_QPLLLOCKDETCLK_INVERTED (1'b0), + .QPLL_CFG (QPLL_CFG), + .QPLL_CLKOUT_CFG (4'b0000), + .QPLL_COARSE_FREQ_OVRD (6'b010000), + .QPLL_COARSE_FREQ_OVRD_EN (1'b0), + .QPLL_CP (10'b0000011111), + .QPLL_CP_MONITOR_EN (1'b0), + .QPLL_DMONITOR_SEL (1'b0), + .QPLL_FBDIV (QPLL_FBDIV), + .QPLL_FBDIV_MONITOR_EN (1'b0), + .QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO), + .QPLL_INIT_CFG (24'h000006), + .QPLL_LOCK_CFG (16'h21E8), + .QPLL_LPF (4'b1111), + .QPLL_REFCLK_DIV (QPLL_REFCLK_DIV), + .SIM_QPLLREFCLK_SEL (3'b001), + .SIM_RESET_SPEEDUP ("TRUE"), + .SIM_VERSION ("4.0")) + i_gtxe2_common ( + .QPLLDMONITOR (), + .QPLLFBCLKLOST (), + .REFCLKOUTMONITOR (), + .BGBYPASSB (1'h1), + .BGMONITORENB (1'h1), + .BGPDB (1'h1), + .BGRCALOVRD (5'h1f), + .DRPADDR (up_addr_int[7:0]), + .DRPCLK (up_clk), + .DRPDI (up_wdata_int), + .DRPDO (up_rdata_s), + .DRPEN (up_enb_int), + .DRPRDY (up_ready_s), + .DRPWE (up_wr_int), + .GTGREFCLK (1'h0), + .GTNORTHREFCLK0 (1'h0), + .GTNORTHREFCLK1 (1'h0), + .GTREFCLK0 (qpll_ref_clk), + .GTREFCLK1 (1'h0), + .GTSOUTHREFCLK0 (1'h0), + .GTSOUTHREFCLK1 (1'h0), + .PMARSVD (8'h0), + .QPLLLOCK (qpll2ch_locked), + .QPLLLOCKDETCLK (up_clk), + .QPLLLOCKEN (1'h1), + .QPLLOUTCLK (qpll2ch_clk), + .QPLLOUTREFCLK (qpll2ch_ref_clk), + .QPLLOUTRESET (1'h0), + .QPLLPD (1'h0), + .QPLLREFCLKLOST (), + .QPLLREFCLKSEL (3'h1), + .QPLLRESET (up_qpll_rst), + .QPLLRSVD1 (16'h0), + .QPLLRSVD2 (5'h1f), + .RCALENB (1'h1)); + end + endgenerate + + generate + if (XCVR_TYPE == GTHE3_TRANSCEIVERS) begin + GTHE3_COMMON #( + .BIAS_CFG0 (16'h0000), + .BIAS_CFG1 (16'h0000), + .BIAS_CFG2 (16'h0000), + .BIAS_CFG3 (16'h0040), + .BIAS_CFG4 (16'h0000), + .BIAS_CFG_RSVD (10'b0000000000), + .COMMON_CFG0 (16'h0000), + .COMMON_CFG1 (16'h0000), + .POR_CFG (16'h0004), + .QPLL0_CFG0 (16'h321c), + .QPLL0_CFG1 (16'h1018), + .QPLL0_CFG1_G3 (16'h1018), + .QPLL0_CFG2 (16'h0048), + .QPLL0_CFG2_G3 (16'h0048), + .QPLL0_CFG3 (16'h0120), + .QPLL0_CFG4 (16'h0000), + .QPLL0_CP (10'b0000011111), + .QPLL0_CP_G3 (10'b1111111111), + .QPLL0_FBDIV (QPLL_FBDIV), + .QPLL0_FBDIV_G3 (80), + .QPLL0_INIT_CFG0 (16'h02b2), + .QPLL0_INIT_CFG1 (8'h00), + .QPLL0_LOCK_CFG (16'h21e8), + .QPLL0_LOCK_CFG_G3 (16'h21e8), + .QPLL0_LPF (10'b1111111111), + .QPLL0_LPF_G3 (10'b0000010101), + .QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL0_SDM_CFG0 (16'b0000000000000000), + .QPLL0_SDM_CFG1 (16'b0000000000000000), + .QPLL0_SDM_CFG2 (16'b0000000000000000), + .QPLL1_CFG0 (16'h321c), + .QPLL1_CFG1 (16'h1018), + .QPLL1_CFG1_G3 (16'h1018), + .QPLL1_CFG2 (16'h0040), + .QPLL1_CFG2_G3 (16'h0040), + .QPLL1_CFG3 (16'h0120), + .QPLL1_CFG4 (16'h0000), + .QPLL1_CP (10'b0000011111), + .QPLL1_CP_G3 (10'b1111111111), + .QPLL1_FBDIV (QPLL_FBDIV), + .QPLL1_FBDIV_G3 (80), + .QPLL1_INIT_CFG0 (16'h02b2), + .QPLL1_INIT_CFG1 (8'h00), + .QPLL1_LOCK_CFG (16'h21e8), + .QPLL1_LOCK_CFG_G3 (16'h21e8), + .QPLL1_LPF (10'b1111111111), + .QPLL1_LPF_G3 (10'b0000010101), + .QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL1_SDM_CFG0 (16'b0000000000000000), + .QPLL1_SDM_CFG1 (16'b0000000000000000), + .QPLL1_SDM_CFG2 (16'b0000000000000000), + .RSVD_ATTR0 (16'h0000), + .RSVD_ATTR1 (16'h0000), + .RSVD_ATTR2 (16'h0000), + .RSVD_ATTR3 (16'h0000), + .RXRECCLKOUT0_SEL (2'b00), + .RXRECCLKOUT1_SEL (2'b00), + .SARC_EN (1'b1), + .SARC_SEL (1'b0), + .SDM0DATA1_0 (16'b0000000000000000), + .SDM0DATA1_1 (9'b000000000), + .SDM0INITSEED0_0 (16'b0000000000000000), + .SDM0INITSEED0_1 (9'b000000000), + .SDM0_DATA_PIN_SEL (1'b0), + .SDM0_WIDTH_PIN_SEL (1'b0), + .SDM1DATA1_0 (16'b0000000000000000), + .SDM1DATA1_1 (9'b000000000), + .SDM1INITSEED0_0 (16'b0000000000000000), + .SDM1INITSEED0_1 (9'b000000000), + .SDM1_DATA_PIN_SEL (1'b0), + .SDM1_WIDTH_PIN_SEL (1'b0), + .SIM_MODE ("FAST"), + .SIM_RESET_SPEEDUP ("TRUE"), + .SIM_VERSION (2)) + i_gthe3_common ( + .BGBYPASSB (1'h1), + .BGMONITORENB (1'h1), + .BGPDB (1'h1), + .BGRCALOVRD (5'h1f), + .BGRCALOVRDENB (1'h1), + .DRPADDR (up_addr_int[8:0]), + .DRPCLK (up_clk), + .DRPDI (up_wdata_int), + .DRPDO (up_rdata_s), + .DRPEN (up_enb_int), + .DRPRDY (up_ready_s), + .DRPWE (up_wr_int), + .GTGREFCLK0 (1'h0), + .GTGREFCLK1 (1'h0), + .GTNORTHREFCLK00 (1'h0), + .GTNORTHREFCLK01 (1'h0), + .GTNORTHREFCLK10 (1'h0), + .GTNORTHREFCLK11 (1'h0), + .GTREFCLK00 (qpll_ref_clk), + .GTREFCLK01 (1'h0), + .GTREFCLK10 (1'h0), + .GTREFCLK11 (1'h0), + .GTSOUTHREFCLK00 (1'h0), + .GTSOUTHREFCLK01 (1'h0), + .GTSOUTHREFCLK10 (1'h0), + .GTSOUTHREFCLK11 (1'h0), + .PMARSVD0 (8'h0), + .PMARSVD1 (8'h0), + .PMARSVDOUT0 (), + .PMARSVDOUT1 (), + .QPLL0CLKRSVD0 (1'h0), + .QPLL0CLKRSVD1 (1'h0), + .QPLL0FBCLKLOST (), + .QPLL0LOCK (qpll2ch_locked), + .QPLL0LOCKDETCLK (up_clk), + .QPLL0LOCKEN (1'h1), + .QPLL0OUTCLK (qpll2ch_clk), + .QPLL0OUTREFCLK (qpll2ch_ref_clk), + .QPLL0PD (1'h0), + .QPLL0REFCLKLOST (), + .QPLL0REFCLKSEL (3'h1), + .QPLL0RESET (up_qpll_rst), + .QPLL1CLKRSVD0 (1'h0), + .QPLL1CLKRSVD1 (1'h0), + .QPLL1FBCLKLOST (), + .QPLL1LOCK (qpll1_locked), + .QPLL1LOCKDETCLK (up_clk), + .QPLL1LOCKEN (1'h1), + .QPLL1OUTCLK (qpll1_clk), + .QPLL1OUTREFCLK (qpll1_ref_clk), + .QPLL1PD (~qpll_sel), + .QPLL1REFCLKLOST (), + .QPLL1REFCLKSEL (3'h1), + .QPLL1RESET (up_qpll_rst), + .QPLLDMONITOR0 (), + .QPLLDMONITOR1 (), + .QPLLRSVD1 (8'h0), + .QPLLRSVD2 (5'h0), + .QPLLRSVD3 (5'h0), + .QPLLRSVD4 (8'h0), + .RCALENB (1'h1), + .REFCLKOUTMONITOR0 (), + .REFCLKOUTMONITOR1 (), + .RXRECCLK0_SEL (), + .RXRECCLK1_SEL ()); + end + endgenerate + + generate + if (XCVR_TYPE == GTHE4_TRANSCEIVERS) begin + GTHE4_COMMON #( + .AEN_QPLL0_FBDIV (1'b1), + .AEN_QPLL1_FBDIV (1'b1), + .AEN_SDM0TOGGLE (1'b0), + .AEN_SDM1TOGGLE (1'b0), + .A_SDM0TOGGLE (1'b0), + .A_SDM1DATA_HIGH (9'b000000000), + .A_SDM1DATA_LOW (16'b0000000000000000), + .A_SDM1TOGGLE (1'b0), + .BIAS_CFG0 (16'b0000000000000000), + .BIAS_CFG1 (16'b0000000000000000), + .BIAS_CFG2 (16'b0000000100100100), + .BIAS_CFG3 (16'b0000000001000001), + .BIAS_CFG4 (16'b0000000000010000), + .BIAS_CFG_RSVD (16'b0000000000000000), + .COMMON_CFG0 (16'b0000000000000000), + .COMMON_CFG1 (16'b0000000000000000), + .POR_CFG (POR_CFG), + .PPF0_CFG (PPF0_CFG), + .PPF1_CFG (PPF1_CFG), + .QPLL0CLKOUT_RATE ("HALF"), + .QPLL0_CFG0 (QPLL_CFG0), + .QPLL0_CFG1 (QPLL_CFG1), + .QPLL0_CFG1_G3 (QPLL_CFG1_G3), + .QPLL0_CFG2 (QPLL_CFG2), + .QPLL0_CFG2_G3 (QPLL_CFG2_G3), + .QPLL0_CFG3 (QPLL_CFG3), + .QPLL0_CFG4 (QPLL_CFG4), + .QPLL0_CP (QPLL_CP), + .QPLL0_CP_G3 (QPLL_CP_G3), + .QPLL0_FBDIV (QPLL_FBDIV), + .QPLL0_FBDIV_G3 (160), + .QPLL0_INIT_CFG0 (16'b0000001010110010), + .QPLL0_INIT_CFG1 (8'b00000000), + .QPLL0_LOCK_CFG (16'b0010010111101000), + .QPLL0_LOCK_CFG_G3 (16'b0010010111101000), + .QPLL0_LPF (QPLL_LPF), + .QPLL0_LPF_G3 (10'b0111010101), + .QPLL0_PCI_EN (1'b0), + .QPLL0_RATE_SW_USE_DRP (1'b1), + .QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL0_SDM_CFG0 (16'b0000000010000000), + .QPLL0_SDM_CFG1 (16'b0000000000000000), + .QPLL0_SDM_CFG2 (16'b0000000000000000), + .QPLL1CLKOUT_RATE ("HALF"), + .QPLL1_CFG0 (QPLL_CFG0), + .QPLL1_CFG1 (QPLL_CFG1), + .QPLL1_CFG1_G3 (QPLL_CFG1_G3), + .QPLL1_CFG2 (QPLL_CFG2), + .QPLL1_CFG2_G3 (QPLL_CFG2_G3), + .QPLL1_CFG3 (QPLL_CFG3), + .QPLL1_CFG4 (QPLL_CFG4), + .QPLL1_CP (10'b1111111111), + .QPLL1_CP_G3 (10'b0011111111), + .QPLL1_FBDIV (QPLL_FBDIV), + .QPLL1_FBDIV_G3 (80), + .QPLL1_INIT_CFG0 (16'b0000001010110010), + .QPLL1_INIT_CFG1 (8'b00000000), + .QPLL1_LOCK_CFG (16'b0010010111101000), + .QPLL1_LOCK_CFG_G3 (16'b0010010111101000), + .QPLL1_LPF (10'b0100110101), + .QPLL1_LPF_G3 (10'b0111010100), + .QPLL1_PCI_EN (1'b0), + .QPLL1_RATE_SW_USE_DRP (1'b1), + .QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL1_SDM_CFG0 (16'b0000000010000000), + .QPLL1_SDM_CFG1 (16'b0000000000000000), + .QPLL1_SDM_CFG2 (16'b0000000000000000), + .RSVD_ATTR0 (16'b0000000000000000), + .RSVD_ATTR1 (16'b0000000000000000), + .RSVD_ATTR2 (16'b0000000000000000), + .RSVD_ATTR3 (16'b0000000000000000), + .RXRECCLKOUT0_SEL (2'b00), + .RXRECCLKOUT1_SEL (2'b00), + .SARC_ENB (1'b0), + .SARC_SEL (1'b0), + .SDM0INITSEED0_0 (16'b0000000100010001), + .SDM0INITSEED0_1 (9'b000010001), + .SDM1INITSEED0_0 (16'b0000000100010001), + .SDM1INITSEED0_1 (9'b000010001), + .SIM_MODE ("FAST"), + .SIM_RESET_SPEEDUP ("TRUE")) + i_gthe4_common ( + .BGBYPASSB (1'd1), + .BGMONITORENB (1'd1), + .BGPDB (1'd1), + .BGRCALOVRD (5'b11111), + .BGRCALOVRDENB (1'd1), + .DRPADDR ({4'd0, up_addr_int}), + .DRPCLK (up_clk), + .DRPDI (up_wdata_int), + .DRPDO (up_rdata_s), + .DRPEN (up_enb_int), + .DRPRDY (up_ready_s), + .DRPWE (up_wr_int), + .GTGREFCLK0 (1'd0), + .GTGREFCLK1 (1'd0), + .GTNORTHREFCLK00 (1'd0), + .GTNORTHREFCLK01 (1'd0), + .GTNORTHREFCLK10 (1'd0), + .GTNORTHREFCLK11 (1'd0), + .GTREFCLK00 (qpll_ref_clk), + .GTREFCLK01 (qpll_ref_clk), + .GTREFCLK10 (1'd0), + .GTREFCLK11 (1'd0), + .GTSOUTHREFCLK00 (1'd0), + .GTSOUTHREFCLK01 (1'd0), + .GTSOUTHREFCLK10 (1'd0), + .GTSOUTHREFCLK11 (1'd0), + .PCIERATEQPLL0 (3'd0), + .PCIERATEQPLL1 (3'd0), + .PMARSVD0 (8'd0), + .PMARSVD1 (8'd0), + .PMARSVDOUT0 (), + .PMARSVDOUT1 (), + .QPLL0CLKRSVD0 (1'd0), + .QPLL0CLKRSVD1 (1'd0), + .QPLL0FBCLKLOST (), + .QPLL0FBDIV (8'd0), + .QPLL0LOCK (qpll2ch_locked), + .QPLL0LOCKDETCLK (up_clk), + .QPLL0LOCKEN (1'd1), + .QPLL0OUTCLK (qpll2ch_clk), + .QPLL0OUTREFCLK (qpll2ch_ref_clk), + .QPLL0PD (qpll_sel), + .QPLL0REFCLKLOST (), + .QPLL0REFCLKSEL (3'b001), + .QPLL0RESET (up_qpll_rst), + .QPLL1CLKRSVD0 (1'd0), + .QPLL1CLKRSVD1 (1'd0), + .QPLL1FBCLKLOST (), + .QPLL1FBDIV (8'd0), + .QPLL1LOCK (qpll1_locked), + .QPLL1LOCKDETCLK (up_clk), + .QPLL1LOCKEN (1'd1), + .QPLL1OUTCLK (qpll1_clk), + .QPLL1OUTREFCLK (qpll1_ref_clk), + .QPLL1PD (~qpll_sel), + .QPLL1REFCLKLOST (), + .QPLL1REFCLKSEL (3'b001), + .QPLL1RESET (up_qpll_rst), + .QPLLDMONITOR0 (), + .QPLLDMONITOR1 (), + .QPLLRSVD1 (8'd0), + .QPLLRSVD2 (5'd0), + .QPLLRSVD3 (5'd0), + .QPLLRSVD4 (8'd0), + .RCALENB (1'd1), + .REFCLKOUTMONITOR0 (), + .REFCLKOUTMONITOR1 (), + .RXRECCLK0SEL (), + .RXRECCLK1SEL (), + .SDM0DATA (25'd0), + .SDM0FINALOUT (), + .SDM0RESET (1'd0), + .SDM0TESTDATA (), + .SDM0TOGGLE (1'd0), + .SDM0WIDTH (2'd0), + .SDM1DATA (25'd0), + .SDM1FINALOUT (), + .SDM1RESET (1'd0), + .SDM1TESTDATA (), + .SDM1TOGGLE (1'd0), + .SDM1WIDTH (2'd0), + .TCONGPI (10'd0), + .TCONGPO (), + .TCONPOWERUP (1'd0), + .TCONRESET (2'd0), + .TCONRSVDIN1 (2'd0), + .TCONRSVDOUT0 ()); + end + endgenerate + + generate + if (XCVR_TYPE == GTYE4_TRANSCEIVERS) begin + GTYE4_COMMON #( + .AEN_QPLL0_FBDIV (1'b1), + .AEN_QPLL1_FBDIV (1'b1), + .AEN_SDM0TOGGLE (1'b0), + .AEN_SDM1TOGGLE (1'b0), + .A_SDM0TOGGLE (1'b0), + .A_SDM1DATA_HIGH (9'b000000000), + .A_SDM1DATA_LOW (16'b0000000000000000), + .A_SDM1TOGGLE (1'b0), + .BIAS_CFG0 (16'b0000000000000000), + .BIAS_CFG1 (16'b0000000000000000), + .BIAS_CFG2 (16'b0000000100100100), + .BIAS_CFG3 (16'b0000000001000001), + .BIAS_CFG4 (16'b0000000000010000), + .BIAS_CFG_RSVD (16'b0000000000000000), + .COMMON_CFG0 (16'b0000000000000000), + .COMMON_CFG1 (16'b0000000000000000), + .POR_CFG (16'b0000000000000000), + .PPF0_CFG (PPF0_CFG), + .PPF1_CFG (PPF1_CFG), + .QPLL0CLKOUT_RATE ("HALF"), + .QPLL0_CFG0 (QPLL_CFG0), + .QPLL0_CFG1 (QPLL_CFG1), + .QPLL0_CFG1_G3 (QPLL_CFG1_G3), + .QPLL0_CFG2 (QPLL_CFG2), + .QPLL0_CFG2_G3 (QPLL_CFG2_G3), + .QPLL0_CFG3 (QPLL_CFG3), + .QPLL0_CFG4 (QPLL_CFG4), + .QPLL0_CP (10'b0011111111), + .QPLL0_CP_G3 (10'b0000001111), + .QPLL0_FBDIV (QPLL_FBDIV), + .QPLL0_FBDIV_G3 (160), + .QPLL0_INIT_CFG0 (16'b0000001010110010), + .QPLL0_INIT_CFG1 (8'b00000000), + .QPLL0_LOCK_CFG (16'b0010010111101000), + .QPLL0_LOCK_CFG_G3 (16'b0010010111101000), + .QPLL0_LPF (QPLL_LPF), + .QPLL0_LPF_G3 (10'b0111010101), + .QPLL0_PCI_EN (1'b0), + .QPLL0_RATE_SW_USE_DRP (1'b1), + .QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL0_SDM_CFG0 (16'b0000000010000000), + .QPLL0_SDM_CFG1 (16'b0000000000000000), + .QPLL0_SDM_CFG2 (16'b0000000000000000), + .QPLL1CLKOUT_RATE ("HALF"), + .QPLL1_CFG0 (QPLL_CFG0), + .QPLL1_CFG1 (QPLL_CFG1), + .QPLL1_CFG1_G3 (QPLL_CFG1_G3), + .QPLL1_CFG2 (QPLL_CFG2), + .QPLL1_CFG2_G3 (QPLL_CFG2_G3), + .QPLL1_CFG3 (QPLL_CFG3), + .QPLL1_CFG4 (QPLL_CFG4), + .QPLL1_CP (10'b0011111111), + .QPLL1_CP_G3 (10'b0001111111), + .QPLL1_FBDIV (QPLL_FBDIV), + .QPLL1_FBDIV_G3 (80), + .QPLL1_INIT_CFG0 (16'b0000001010110010), + .QPLL1_INIT_CFG1 (8'b00000000), + .QPLL1_LOCK_CFG (16'b0010010111101000), + .QPLL1_LOCK_CFG_G3 (16'b0010010111101000), + .QPLL1_LPF (10'b1000011111), + .QPLL1_LPF_G3 (10'b0111010100), + .QPLL1_PCI_EN (1'b0), + .QPLL1_RATE_SW_USE_DRP (1'b1), + .QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV), + .QPLL1_SDM_CFG0 (16'b0000000010000000), + .QPLL1_SDM_CFG1 (16'b0000000000000000), + .QPLL1_SDM_CFG2 (16'b0000000000000000), + .RSVD_ATTR0 (16'b0000000000000000), + .RSVD_ATTR1 (16'b0000000000000000), + .RSVD_ATTR2 (16'b0000000000000000), + .RSVD_ATTR3 (16'b0000000000000000), + .RXRECCLKOUT0_SEL (2'b00), + .RXRECCLKOUT1_SEL (2'b00), + .SARC_ENB (1'b0), + .SARC_SEL (1'b0), + .SDM0INITSEED0_0 (16'b0000000100010001), + .SDM0INITSEED0_1 (9'b000010001), + .SDM1INITSEED0_0 (16'b0000000100010001), + .SDM1INITSEED0_1 (9'b000010001), + .SIM_MODE ("FAST"), + .SIM_RESET_SPEEDUP ("TRUE"), + .SIM_DEVICE ("ULTRASCALE_PLUS"), + .UB_CFG0 (16'b0000000000000000), + .UB_CFG1 (16'b0000000000000000), + .UB_CFG2 (16'b0000000000000000), + .UB_CFG3 (16'b0000000000000000), + .UB_CFG4 (16'b0000000000000000), + .UB_CFG5 (16'b0000010000000000), + .UB_CFG6 (16'b0000000000000000)) + i_gtye4_common ( + .BGBYPASSB (1'b1), + .BGMONITORENB (1'b1), + .BGPDB (1'b1), + .BGRCALOVRD (5'b11111), + .BGRCALOVRDENB (1'b1), + .DRPADDR ({4'd0, up_addr_int}), + .DRPCLK (up_clk), + .DRPDI (up_wdata_int), + .DRPEN (up_enb_int), + .DRPWE (up_wr_int), + .GTGREFCLK0 (1'b0), + .GTGREFCLK1 (1'b0), + .GTNORTHREFCLK00 (1'b0), + .GTNORTHREFCLK01 (1'b0), + .GTNORTHREFCLK10 (1'b0), + .GTNORTHREFCLK11 (1'b0), + .GTREFCLK00 (qpll_ref_clk), + .GTREFCLK01 (qpll_ref_clk), + .GTREFCLK10 (1'b0), + .GTREFCLK11 (1'b0), + .GTSOUTHREFCLK00 (1'b0), + .GTSOUTHREFCLK01 (1'b0), + .GTSOUTHREFCLK10 (1'b0), + .GTSOUTHREFCLK11 (1'b0), + .PCIERATEQPLL0 (3'b0), + .PCIERATEQPLL1 (3'b0), + .PMARSVD0 (8'b0), + .PMARSVD1 (8'b0), + .QPLL0CLKRSVD0 (1'b0), + .QPLL0CLKRSVD1 (1'b0), + .QPLL0FBDIV (8'b0), + .QPLL0LOCKDETCLK (up_clk), + .QPLL0LOCKEN (1'b1), + .QPLL0PD (qpll_sel), + .QPLL0REFCLKSEL (3'b1), + .QPLL0RESET (up_qpll_rst), + .QPLL1CLKRSVD0 (1'b0), + .QPLL1CLKRSVD1 (1'b0), + .QPLL1FBDIV (8'b0), + .QPLL1LOCKDETCLK (up_clk), + .QPLL1LOCKEN (1'b1), + .QPLL1PD (~qpll_sel), + .QPLL1REFCLKSEL (3'b1), + .QPLL1RESET (up_qpll_rst), + .QPLLRSVD1 (8'b0), + .QPLLRSVD2 (5'b0), + .QPLLRSVD3 (5'b0), + .QPLLRSVD4 (8'b0), + .RCALENB (1'b1), + .SDM0DATA (25'b0), + .SDM0RESET (1'b0), + .SDM0TOGGLE (1'b0), + .SDM0WIDTH (2'b0), + .SDM1DATA (25'b0), + .SDM1RESET (1'b0), + .SDM1TOGGLE (1'b0), + .SDM1WIDTH (2'b0), + .UBCFGSTREAMEN (1'b0), + .UBDO (16'b0), + .UBDRDY (1'b0), + .UBENABLE (1'b0), + .UBGPI (2'b0), + .UBINTR (2'b0), + .UBIOLMBRST (1'b0), + .UBMBRST (1'b0), + .UBMDMCAPTURE (1'b0), + .UBMDMDBGRST (1'b0), + .UBMDMDBGUPDATE (1'b0), + .UBMDMREGEN (4'b0), + .UBMDMSHIFT (1'b0), + .UBMDMSYSRST (1'b0), + .UBMDMTCK (1'b0), + .UBMDMTDI (1'b0), + .DRPDO ( up_rdata_s), + .DRPRDY ( up_ready_s), + .PMARSVDOUT0 (), + .PMARSVDOUT1 (), + .QPLL0FBCLKLOST (), + .QPLL0LOCK ( qpll2ch_locked), + .QPLL0OUTCLK ( qpll2ch_clk), + .QPLL0OUTREFCLK ( qpll2ch_ref_clk), + .QPLL0REFCLKLOST (), + .QPLL1FBCLKLOST (), + .QPLL1LOCK ( qpll1_locked), + .QPLL1OUTCLK ( qpll1_clk), + .QPLL1OUTREFCLK ( qpll1_ref_clk), + .QPLL1REFCLKLOST (), + .QPLLDMONITOR0 (), + .QPLLDMONITOR1 (), + .REFCLKOUTMONITOR0 (), + .REFCLKOUTMONITOR1 (), + .RXRECCLK0SEL (), + .RXRECCLK1SEL (), + .SDM0FINALOUT (), + .SDM0TESTDATA (), + .SDM1FINALOUT (), + .SDM1TESTDATA (), + .UBDADDR (), + .UBDEN (), + .UBDI (), + .UBDWE (), + .UBMDMTDO (), + .UBRSVDOUT (), + .UBTXUART ()); + end + endgenerate + +endmodule diff --git a/adi_library/xilinx/util_adxcvr/xgui/util_adxcvr_v1_0.tcl b/adi_library/xilinx/util_adxcvr/xgui/util_adxcvr_v1_0.tcl new file mode 100644 index 00000000..2260a888 --- /dev/null +++ b/adi_library/xilinx/util_adxcvr/xgui/util_adxcvr_v1_0.tcl @@ -0,0 +1,1077 @@ + +# Loading additional proc with user specified bodies to compute parameter values. +source [file join [file dirname [file dirname [info script]]] gui/util_adxcvr_v1_0.gtcl] + +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "LINK_MODE" -parent ${Page_0} -widget comboBox + ipgui::add_param $IPINST -name "RX_LANE_RATE" -parent ${Page_0} + ipgui::add_param $IPINST -name "TX_LANE_RATE" -parent ${Page_0} + ipgui::add_param $IPINST -name "A_TXDIFFCTRL" -parent ${Page_0} + ipgui::add_param $IPINST -name "CH_HSPMUX" -parent ${Page_0} + ipgui::add_param $IPINST -name "CPLL_CFG0" -parent ${Page_0} + ipgui::add_param $IPINST -name "CPLL_CFG1" -parent ${Page_0} + ipgui::add_param $IPINST -name "CPLL_CFG2" -parent ${Page_0} + ipgui::add_param $IPINST -name "CPLL_CFG3" -parent ${Page_0} + ipgui::add_param $IPINST -name "CPLL_FBDIV" -parent ${Page_0} + ipgui::add_param $IPINST -name "CPLL_FBDIV_4_5" -parent ${Page_0} + ipgui::add_param $IPINST -name "DATA_PATH_WIDTH" -parent ${Page_0} + ipgui::add_param $IPINST -name "POR_CFG" -parent ${Page_0} + ipgui::add_param $IPINST -name "PPF0_CFG" -parent ${Page_0} + ipgui::add_param $IPINST -name "PPF1_CFG" -parent ${Page_0} + ipgui::add_param $IPINST -name "PREIQ_FREQ_BST" -parent ${Page_0} + ipgui::add_param $IPINST -name "QPLL_CFG" -parent ${Page_0} + ipgui::add_param $IPINST -name "QPLL_CFG0" -parent ${Page_0} + ipgui::add_param $IPINST -name "QPLL_CFG1" -parent ${Page_0} + ipgui::add_param $IPINST -name "QPLL_CFG1_G3" -parent ${Page_0} + ipgui::add_param $IPINST -name "QPLL_CFG2" -parent ${Page_0} + ipgui::add_param $IPINST -name "QPLL_CFG2_G3" -parent ${Page_0} + ipgui::add_param $IPINST -name "QPLL_CFG3" -parent ${Page_0} + ipgui::add_param $IPINST -name "QPLL_CFG4" -parent ${Page_0} + ipgui::add_param $IPINST -name "QPLL_CP" -parent ${Page_0} + ipgui::add_param $IPINST -name "QPLL_CP_G3" -parent ${Page_0} + ipgui::add_param $IPINST -name "QPLL_FBDIV" -parent ${Page_0} + ipgui::add_param $IPINST -name "QPLL_FBDIV_RATIO" -parent ${Page_0} + ipgui::add_param $IPINST -name "QPLL_LPF" -parent ${Page_0} + ipgui::add_param $IPINST -name "QPLL_REFCLK_DIV" -parent ${Page_0} + ipgui::add_param $IPINST -name "RTX_BUF_CML_CTRL" -parent ${Page_0} + ipgui::add_param $IPINST -name "RXCDR_CFG0" -parent ${Page_0} + ipgui::add_param $IPINST -name "RXCDR_CFG2" -parent ${Page_0} + ipgui::add_param $IPINST -name "RXCDR_CFG2_GEN2" -parent ${Page_0} + ipgui::add_param $IPINST -name "RXCDR_CFG2_GEN4" -parent ${Page_0} + ipgui::add_param $IPINST -name "RXCDR_CFG3" -parent ${Page_0} + ipgui::add_param $IPINST -name "RXCDR_CFG3_GEN2" -parent ${Page_0} + ipgui::add_param $IPINST -name "RXCDR_CFG3_GEN3" -parent ${Page_0} + ipgui::add_param $IPINST -name "RXCDR_CFG3_GEN4" -parent ${Page_0} + ipgui::add_param $IPINST -name "RXDFE_KH_CFG2" -parent ${Page_0} + ipgui::add_param $IPINST -name "RXDFE_KH_CFG3" -parent ${Page_0} + ipgui::add_param $IPINST -name "RXPI_CFG0" -parent ${Page_0} + ipgui::add_param $IPINST -name "RXPI_CFG1" -parent ${Page_0} + ipgui::add_param $IPINST -name "RX_CDR_CFG" -parent ${Page_0} + ipgui::add_param $IPINST -name "RX_CLK25_DIV" -parent ${Page_0} + ipgui::add_param $IPINST -name "RX_DFE_LPM_CFG" -parent ${Page_0} + ipgui::add_param $IPINST -name "RX_LANE_INVERT" -parent ${Page_0} + ipgui::add_param $IPINST -name "RX_NUM_OF_LANES" -parent ${Page_0} + ipgui::add_param $IPINST -name "RX_OUT_DIV" -parent ${Page_0} + ipgui::add_param $IPINST -name "RX_PMA_CFG" -parent ${Page_0} + ipgui::add_param $IPINST -name "RX_WIDEMODE_CDR" -parent ${Page_0} + ipgui::add_param $IPINST -name "RX_XMODE_SEL" -parent ${Page_0} + ipgui::add_param $IPINST -name "TXDRV_FREQBAND" -parent ${Page_0} + ipgui::add_param $IPINST -name "TXFE_CFG0" -parent ${Page_0} + ipgui::add_param $IPINST -name "TXFE_CFG1" -parent ${Page_0} + ipgui::add_param $IPINST -name "TXFE_CFG2" -parent ${Page_0} + ipgui::add_param $IPINST -name "TXFE_CFG3" -parent ${Page_0} + ipgui::add_param $IPINST -name "TXPI_CFG" -parent ${Page_0} + ipgui::add_param $IPINST -name "TXPI_CFG0" -parent ${Page_0} + ipgui::add_param $IPINST -name "TXPI_CFG1" -parent ${Page_0} + ipgui::add_param $IPINST -name "TXSWBST_EN" -parent ${Page_0} + ipgui::add_param $IPINST -name "TX_CLK25_DIV" -parent ${Page_0} + ipgui::add_param $IPINST -name "TX_LANE_INVERT" -parent ${Page_0} + ipgui::add_param $IPINST -name "TX_NUM_OF_LANES" -parent ${Page_0} + ipgui::add_param $IPINST -name "TX_OUT_DIV" -parent ${Page_0} + ipgui::add_param $IPINST -name "TX_PI_BIASSET" -parent ${Page_0} + #Adding Group + set FPGA_info [ipgui::add_group $IPINST -name "FPGA info" -parent ${Page_0}] + ipgui::add_param $IPINST -name "XCVR_TYPE" -parent ${FPGA_info} -widget comboBox + + + +} + +proc update_PARAM_VALUE.CH_HSPMUX { PARAM_VALUE.CH_HSPMUX PARAM_VALUE.XCVR_TYPE } { + # Procedure called to update CH_HSPMUX when any of the dependent parameters in the arguments change + + set CH_HSPMUX ${PARAM_VALUE.CH_HSPMUX} + set XCVR_TYPE ${PARAM_VALUE.XCVR_TYPE} + set values(XCVR_TYPE) [get_property value $XCVR_TYPE] + set_property value [gen_USERPARAMETER_CH_HSPMUX_VALUE $values(XCVR_TYPE)] $CH_HSPMUX +} + +proc validate_PARAM_VALUE.CH_HSPMUX { PARAM_VALUE.CH_HSPMUX } { + # Procedure called to validate CH_HSPMUX + return true +} + +proc update_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH PARAM_VALUE.LINK_MODE } { + # Procedure called to update DATA_PATH_WIDTH when any of the dependent parameters in the arguments change + + set DATA_PATH_WIDTH ${PARAM_VALUE.DATA_PATH_WIDTH} + set LINK_MODE ${PARAM_VALUE.LINK_MODE} + set values(LINK_MODE) [get_property value $LINK_MODE] + if { [gen_USERPARAMETER_DATA_PATH_WIDTH_ENABLEMENT $values(LINK_MODE)] } { + set_property enabled true $DATA_PATH_WIDTH + } else { + set_property enabled false $DATA_PATH_WIDTH + set_property value [gen_USERPARAMETER_DATA_PATH_WIDTH_VALUE $values(LINK_MODE)] $DATA_PATH_WIDTH + } +} + +proc validate_PARAM_VALUE.DATA_PATH_WIDTH { PARAM_VALUE.DATA_PATH_WIDTH } { + # Procedure called to validate DATA_PATH_WIDTH + return true +} + +proc update_PARAM_VALUE.PPF0_CFG { PARAM_VALUE.PPF0_CFG PARAM_VALUE.XCVR_TYPE } { + # Procedure called to update PPF0_CFG when any of the dependent parameters in the arguments change + + set PPF0_CFG ${PARAM_VALUE.PPF0_CFG} + set XCVR_TYPE ${PARAM_VALUE.XCVR_TYPE} + set values(XCVR_TYPE) [get_property value $XCVR_TYPE] + set_property value [gen_USERPARAMETER_PPF0_CFG_VALUE $values(XCVR_TYPE)] $PPF0_CFG +} + +proc validate_PARAM_VALUE.PPF0_CFG { PARAM_VALUE.PPF0_CFG } { + # Procedure called to validate PPF0_CFG + return true +} + +proc update_PARAM_VALUE.QPLL_LPF { PARAM_VALUE.QPLL_LPF PARAM_VALUE.XCVR_TYPE } { + # Procedure called to update QPLL_LPF when any of the dependent parameters in the arguments change + + set QPLL_LPF ${PARAM_VALUE.QPLL_LPF} + set XCVR_TYPE ${PARAM_VALUE.XCVR_TYPE} + set values(XCVR_TYPE) [get_property value $XCVR_TYPE] + set_property value [gen_USERPARAMETER_QPLL_LPF_VALUE $values(XCVR_TYPE)] $QPLL_LPF +} + +proc validate_PARAM_VALUE.QPLL_LPF { PARAM_VALUE.QPLL_LPF } { + # Procedure called to validate QPLL_LPF + return true +} + +proc update_PARAM_VALUE.RTX_BUF_CML_CTRL { PARAM_VALUE.RTX_BUF_CML_CTRL PARAM_VALUE.XCVR_TYPE } { + # Procedure called to update RTX_BUF_CML_CTRL when any of the dependent parameters in the arguments change + + set RTX_BUF_CML_CTRL ${PARAM_VALUE.RTX_BUF_CML_CTRL} + set XCVR_TYPE ${PARAM_VALUE.XCVR_TYPE} + set values(XCVR_TYPE) [get_property value $XCVR_TYPE] + set_property value [gen_USERPARAMETER_RTX_BUF_CML_CTRL_VALUE $values(XCVR_TYPE)] $RTX_BUF_CML_CTRL +} + +proc validate_PARAM_VALUE.RTX_BUF_CML_CTRL { PARAM_VALUE.RTX_BUF_CML_CTRL } { + # Procedure called to validate RTX_BUF_CML_CTRL + return true +} + +proc update_PARAM_VALUE.RXCDR_CFG3_GEN2 { PARAM_VALUE.RXCDR_CFG3_GEN2 PARAM_VALUE.XCVR_TYPE } { + # Procedure called to update RXCDR_CFG3_GEN2 when any of the dependent parameters in the arguments change + + set RXCDR_CFG3_GEN2 ${PARAM_VALUE.RXCDR_CFG3_GEN2} + set XCVR_TYPE ${PARAM_VALUE.XCVR_TYPE} + set values(XCVR_TYPE) [get_property value $XCVR_TYPE] + set_property value [gen_USERPARAMETER_RXCDR_CFG3_GEN2_VALUE $values(XCVR_TYPE)] $RXCDR_CFG3_GEN2 +} + +proc validate_PARAM_VALUE.RXCDR_CFG3_GEN2 { PARAM_VALUE.RXCDR_CFG3_GEN2 } { + # Procedure called to validate RXCDR_CFG3_GEN2 + return true +} + +proc update_PARAM_VALUE.RXCDR_CFG3_GEN4 { PARAM_VALUE.RXCDR_CFG3_GEN4 PARAM_VALUE.XCVR_TYPE } { + # Procedure called to update RXCDR_CFG3_GEN4 when any of the dependent parameters in the arguments change + + set RXCDR_CFG3_GEN4 ${PARAM_VALUE.RXCDR_CFG3_GEN4} + set XCVR_TYPE ${PARAM_VALUE.XCVR_TYPE} + set values(XCVR_TYPE) [get_property value $XCVR_TYPE] + set_property value [gen_USERPARAMETER_RXCDR_CFG3_GEN4_VALUE $values(XCVR_TYPE)] $RXCDR_CFG3_GEN4 +} + +proc validate_PARAM_VALUE.RXCDR_CFG3_GEN4 { PARAM_VALUE.RXCDR_CFG3_GEN4 } { + # Procedure called to validate RXCDR_CFG3_GEN4 + return true +} + +proc update_PARAM_VALUE.RXPI_CFG0 { PARAM_VALUE.RXPI_CFG0 PARAM_VALUE.XCVR_TYPE } { + # Procedure called to update RXPI_CFG0 when any of the dependent parameters in the arguments change + + set RXPI_CFG0 ${PARAM_VALUE.RXPI_CFG0} + set XCVR_TYPE ${PARAM_VALUE.XCVR_TYPE} + set values(XCVR_TYPE) [get_property value $XCVR_TYPE] + set_property value [gen_USERPARAMETER_RXPI_CFG0_VALUE $values(XCVR_TYPE)] $RXPI_CFG0 +} + +proc validate_PARAM_VALUE.RXPI_CFG0 { PARAM_VALUE.RXPI_CFG0 } { + # Procedure called to validate RXPI_CFG0 + return true +} + +proc update_PARAM_VALUE.RXPI_CFG1 { PARAM_VALUE.RXPI_CFG1 PARAM_VALUE.XCVR_TYPE } { + # Procedure called to update RXPI_CFG1 when any of the dependent parameters in the arguments change + + set RXPI_CFG1 ${PARAM_VALUE.RXPI_CFG1} + set XCVR_TYPE ${PARAM_VALUE.XCVR_TYPE} + set values(XCVR_TYPE) [get_property value $XCVR_TYPE] + set_property value [gen_USERPARAMETER_RXPI_CFG1_VALUE $values(XCVR_TYPE)] $RXPI_CFG1 +} + +proc validate_PARAM_VALUE.RXPI_CFG1 { PARAM_VALUE.RXPI_CFG1 } { + # Procedure called to validate RXPI_CFG1 + return true +} + +proc update_PARAM_VALUE.TX_PI_BIASSET { PARAM_VALUE.TX_PI_BIASSET PARAM_VALUE.XCVR_TYPE } { + # Procedure called to update TX_PI_BIASSET when any of the dependent parameters in the arguments change + + set TX_PI_BIASSET ${PARAM_VALUE.TX_PI_BIASSET} + set XCVR_TYPE ${PARAM_VALUE.XCVR_TYPE} + set values(XCVR_TYPE) [get_property value $XCVR_TYPE] + set_property value [gen_USERPARAMETER_TX_PI_BIASSET_VALUE $values(XCVR_TYPE)] $TX_PI_BIASSET +} + +proc validate_PARAM_VALUE.TX_PI_BIASSET { PARAM_VALUE.TX_PI_BIASSET } { + # Procedure called to validate TX_PI_BIASSET + return true +} + +proc update_PARAM_VALUE.A_TXDIFFCTRL { PARAM_VALUE.A_TXDIFFCTRL } { + # Procedure called to update A_TXDIFFCTRL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.A_TXDIFFCTRL { PARAM_VALUE.A_TXDIFFCTRL } { + # Procedure called to validate A_TXDIFFCTRL + return true +} + +proc update_PARAM_VALUE.CPLL_CFG0 { PARAM_VALUE.CPLL_CFG0 } { + # Procedure called to update CPLL_CFG0 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CPLL_CFG0 { PARAM_VALUE.CPLL_CFG0 } { + # Procedure called to validate CPLL_CFG0 + return true +} + +proc update_PARAM_VALUE.CPLL_CFG1 { PARAM_VALUE.CPLL_CFG1 } { + # Procedure called to update CPLL_CFG1 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CPLL_CFG1 { PARAM_VALUE.CPLL_CFG1 } { + # Procedure called to validate CPLL_CFG1 + return true +} + +proc update_PARAM_VALUE.CPLL_CFG2 { PARAM_VALUE.CPLL_CFG2 } { + # Procedure called to update CPLL_CFG2 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CPLL_CFG2 { PARAM_VALUE.CPLL_CFG2 } { + # Procedure called to validate CPLL_CFG2 + return true +} + +proc update_PARAM_VALUE.CPLL_CFG3 { PARAM_VALUE.CPLL_CFG3 } { + # Procedure called to update CPLL_CFG3 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CPLL_CFG3 { PARAM_VALUE.CPLL_CFG3 } { + # Procedure called to validate CPLL_CFG3 + return true +} + +proc update_PARAM_VALUE.CPLL_FBDIV { PARAM_VALUE.CPLL_FBDIV } { + # Procedure called to update CPLL_FBDIV when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CPLL_FBDIV { PARAM_VALUE.CPLL_FBDIV } { + # Procedure called to validate CPLL_FBDIV + return true +} + +proc update_PARAM_VALUE.CPLL_FBDIV_4_5 { PARAM_VALUE.CPLL_FBDIV_4_5 } { + # Procedure called to update CPLL_FBDIV_4_5 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.CPLL_FBDIV_4_5 { PARAM_VALUE.CPLL_FBDIV_4_5 } { + # Procedure called to validate CPLL_FBDIV_4_5 + return true +} + +proc update_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } { + # Procedure called to update LINK_MODE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.LINK_MODE { PARAM_VALUE.LINK_MODE } { + # Procedure called to validate LINK_MODE + return true +} + +proc update_PARAM_VALUE.POR_CFG { PARAM_VALUE.POR_CFG } { + # Procedure called to update POR_CFG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.POR_CFG { PARAM_VALUE.POR_CFG } { + # Procedure called to validate POR_CFG + return true +} + +proc update_PARAM_VALUE.PPF1_CFG { PARAM_VALUE.PPF1_CFG } { + # Procedure called to update PPF1_CFG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PPF1_CFG { PARAM_VALUE.PPF1_CFG } { + # Procedure called to validate PPF1_CFG + return true +} + +proc update_PARAM_VALUE.PREIQ_FREQ_BST { PARAM_VALUE.PREIQ_FREQ_BST } { + # Procedure called to update PREIQ_FREQ_BST when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.PREIQ_FREQ_BST { PARAM_VALUE.PREIQ_FREQ_BST } { + # Procedure called to validate PREIQ_FREQ_BST + return true +} + +proc update_PARAM_VALUE.QPLL_CFG { PARAM_VALUE.QPLL_CFG } { + # Procedure called to update QPLL_CFG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.QPLL_CFG { PARAM_VALUE.QPLL_CFG } { + # Procedure called to validate QPLL_CFG + return true +} + +proc update_PARAM_VALUE.QPLL_CFG0 { PARAM_VALUE.QPLL_CFG0 } { + # Procedure called to update QPLL_CFG0 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.QPLL_CFG0 { PARAM_VALUE.QPLL_CFG0 } { + # Procedure called to validate QPLL_CFG0 + return true +} + +proc update_PARAM_VALUE.QPLL_CFG1 { PARAM_VALUE.QPLL_CFG1 } { + # Procedure called to update QPLL_CFG1 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.QPLL_CFG1 { PARAM_VALUE.QPLL_CFG1 } { + # Procedure called to validate QPLL_CFG1 + return true +} + +proc update_PARAM_VALUE.QPLL_CFG1_G3 { PARAM_VALUE.QPLL_CFG1_G3 } { + # Procedure called to update QPLL_CFG1_G3 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.QPLL_CFG1_G3 { PARAM_VALUE.QPLL_CFG1_G3 } { + # Procedure called to validate QPLL_CFG1_G3 + return true +} + +proc update_PARAM_VALUE.QPLL_CFG2 { PARAM_VALUE.QPLL_CFG2 } { + # Procedure called to update QPLL_CFG2 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.QPLL_CFG2 { PARAM_VALUE.QPLL_CFG2 } { + # Procedure called to validate QPLL_CFG2 + return true +} + +proc update_PARAM_VALUE.QPLL_CFG2_G3 { PARAM_VALUE.QPLL_CFG2_G3 } { + # Procedure called to update QPLL_CFG2_G3 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.QPLL_CFG2_G3 { PARAM_VALUE.QPLL_CFG2_G3 } { + # Procedure called to validate QPLL_CFG2_G3 + return true +} + +proc update_PARAM_VALUE.QPLL_CFG3 { PARAM_VALUE.QPLL_CFG3 } { + # Procedure called to update QPLL_CFG3 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.QPLL_CFG3 { PARAM_VALUE.QPLL_CFG3 } { + # Procedure called to validate QPLL_CFG3 + return true +} + +proc update_PARAM_VALUE.QPLL_CFG4 { PARAM_VALUE.QPLL_CFG4 } { + # Procedure called to update QPLL_CFG4 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.QPLL_CFG4 { PARAM_VALUE.QPLL_CFG4 } { + # Procedure called to validate QPLL_CFG4 + return true +} + +proc update_PARAM_VALUE.QPLL_CP { PARAM_VALUE.QPLL_CP } { + # Procedure called to update QPLL_CP when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.QPLL_CP { PARAM_VALUE.QPLL_CP } { + # Procedure called to validate QPLL_CP + return true +} + +proc update_PARAM_VALUE.QPLL_CP_G3 { PARAM_VALUE.QPLL_CP_G3 } { + # Procedure called to update QPLL_CP_G3 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.QPLL_CP_G3 { PARAM_VALUE.QPLL_CP_G3 } { + # Procedure called to validate QPLL_CP_G3 + return true +} + +proc update_PARAM_VALUE.QPLL_FBDIV { PARAM_VALUE.QPLL_FBDIV } { + # Procedure called to update QPLL_FBDIV when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.QPLL_FBDIV { PARAM_VALUE.QPLL_FBDIV } { + # Procedure called to validate QPLL_FBDIV + return true +} + +proc update_PARAM_VALUE.QPLL_FBDIV_RATIO { PARAM_VALUE.QPLL_FBDIV_RATIO } { + # Procedure called to update QPLL_FBDIV_RATIO when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.QPLL_FBDIV_RATIO { PARAM_VALUE.QPLL_FBDIV_RATIO } { + # Procedure called to validate QPLL_FBDIV_RATIO + return true +} + +proc update_PARAM_VALUE.QPLL_REFCLK_DIV { PARAM_VALUE.QPLL_REFCLK_DIV } { + # Procedure called to update QPLL_REFCLK_DIV when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.QPLL_REFCLK_DIV { PARAM_VALUE.QPLL_REFCLK_DIV } { + # Procedure called to validate QPLL_REFCLK_DIV + return true +} + +proc update_PARAM_VALUE.RXCDR_CFG0 { PARAM_VALUE.RXCDR_CFG0 } { + # Procedure called to update RXCDR_CFG0 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RXCDR_CFG0 { PARAM_VALUE.RXCDR_CFG0 } { + # Procedure called to validate RXCDR_CFG0 + return true +} + +proc update_PARAM_VALUE.RXCDR_CFG2 { PARAM_VALUE.RXCDR_CFG2 } { + # Procedure called to update RXCDR_CFG2 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RXCDR_CFG2 { PARAM_VALUE.RXCDR_CFG2 } { + # Procedure called to validate RXCDR_CFG2 + return true +} + +proc update_PARAM_VALUE.RXCDR_CFG2_GEN2 { PARAM_VALUE.RXCDR_CFG2_GEN2 } { + # Procedure called to update RXCDR_CFG2_GEN2 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RXCDR_CFG2_GEN2 { PARAM_VALUE.RXCDR_CFG2_GEN2 } { + # Procedure called to validate RXCDR_CFG2_GEN2 + return true +} + +proc update_PARAM_VALUE.RXCDR_CFG2_GEN4 { PARAM_VALUE.RXCDR_CFG2_GEN4 } { + # Procedure called to update RXCDR_CFG2_GEN4 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RXCDR_CFG2_GEN4 { PARAM_VALUE.RXCDR_CFG2_GEN4 } { + # Procedure called to validate RXCDR_CFG2_GEN4 + return true +} + +proc update_PARAM_VALUE.RXCDR_CFG3 { PARAM_VALUE.RXCDR_CFG3 } { + # Procedure called to update RXCDR_CFG3 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RXCDR_CFG3 { PARAM_VALUE.RXCDR_CFG3 } { + # Procedure called to validate RXCDR_CFG3 + return true +} + +proc update_PARAM_VALUE.RXCDR_CFG3_GEN3 { PARAM_VALUE.RXCDR_CFG3_GEN3 } { + # Procedure called to update RXCDR_CFG3_GEN3 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RXCDR_CFG3_GEN3 { PARAM_VALUE.RXCDR_CFG3_GEN3 } { + # Procedure called to validate RXCDR_CFG3_GEN3 + return true +} + +proc update_PARAM_VALUE.RXDFE_KH_CFG2 { PARAM_VALUE.RXDFE_KH_CFG2 } { + # Procedure called to update RXDFE_KH_CFG2 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RXDFE_KH_CFG2 { PARAM_VALUE.RXDFE_KH_CFG2 } { + # Procedure called to validate RXDFE_KH_CFG2 + return true +} + +proc update_PARAM_VALUE.RXDFE_KH_CFG3 { PARAM_VALUE.RXDFE_KH_CFG3 } { + # Procedure called to update RXDFE_KH_CFG3 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RXDFE_KH_CFG3 { PARAM_VALUE.RXDFE_KH_CFG3 } { + # Procedure called to validate RXDFE_KH_CFG3 + return true +} + +proc update_PARAM_VALUE.RX_CDR_CFG { PARAM_VALUE.RX_CDR_CFG } { + # Procedure called to update RX_CDR_CFG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RX_CDR_CFG { PARAM_VALUE.RX_CDR_CFG } { + # Procedure called to validate RX_CDR_CFG + return true +} + +proc update_PARAM_VALUE.RX_CLK25_DIV { PARAM_VALUE.RX_CLK25_DIV } { + # Procedure called to update RX_CLK25_DIV when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RX_CLK25_DIV { PARAM_VALUE.RX_CLK25_DIV } { + # Procedure called to validate RX_CLK25_DIV + return true +} + +proc update_PARAM_VALUE.RX_DFE_LPM_CFG { PARAM_VALUE.RX_DFE_LPM_CFG } { + # Procedure called to update RX_DFE_LPM_CFG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RX_DFE_LPM_CFG { PARAM_VALUE.RX_DFE_LPM_CFG } { + # Procedure called to validate RX_DFE_LPM_CFG + return true +} + +proc update_PARAM_VALUE.RX_LANE_INVERT { PARAM_VALUE.RX_LANE_INVERT } { + # Procedure called to update RX_LANE_INVERT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RX_LANE_INVERT { PARAM_VALUE.RX_LANE_INVERT } { + # Procedure called to validate RX_LANE_INVERT + return true +} + +proc update_PARAM_VALUE.RX_LANE_RATE { PARAM_VALUE.RX_LANE_RATE } { + # Procedure called to update RX_LANE_RATE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RX_LANE_RATE { PARAM_VALUE.RX_LANE_RATE } { + # Procedure called to validate RX_LANE_RATE + return true +} + +proc update_PARAM_VALUE.RX_NUM_OF_LANES { PARAM_VALUE.RX_NUM_OF_LANES } { + # Procedure called to update RX_NUM_OF_LANES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RX_NUM_OF_LANES { PARAM_VALUE.RX_NUM_OF_LANES } { + # Procedure called to validate RX_NUM_OF_LANES + return true +} + +proc update_PARAM_VALUE.RX_OUT_DIV { PARAM_VALUE.RX_OUT_DIV } { + # Procedure called to update RX_OUT_DIV when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RX_OUT_DIV { PARAM_VALUE.RX_OUT_DIV } { + # Procedure called to validate RX_OUT_DIV + return true +} + +proc update_PARAM_VALUE.RX_PMA_CFG { PARAM_VALUE.RX_PMA_CFG } { + # Procedure called to update RX_PMA_CFG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RX_PMA_CFG { PARAM_VALUE.RX_PMA_CFG } { + # Procedure called to validate RX_PMA_CFG + return true +} + +proc update_PARAM_VALUE.RX_WIDEMODE_CDR { PARAM_VALUE.RX_WIDEMODE_CDR } { + # Procedure called to update RX_WIDEMODE_CDR when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RX_WIDEMODE_CDR { PARAM_VALUE.RX_WIDEMODE_CDR } { + # Procedure called to validate RX_WIDEMODE_CDR + return true +} + +proc update_PARAM_VALUE.RX_XMODE_SEL { PARAM_VALUE.RX_XMODE_SEL } { + # Procedure called to update RX_XMODE_SEL when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.RX_XMODE_SEL { PARAM_VALUE.RX_XMODE_SEL } { + # Procedure called to validate RX_XMODE_SEL + return true +} + +proc update_PARAM_VALUE.TXDRV_FREQBAND { PARAM_VALUE.TXDRV_FREQBAND } { + # Procedure called to update TXDRV_FREQBAND when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TXDRV_FREQBAND { PARAM_VALUE.TXDRV_FREQBAND } { + # Procedure called to validate TXDRV_FREQBAND + return true +} + +proc update_PARAM_VALUE.TXFE_CFG0 { PARAM_VALUE.TXFE_CFG0 } { + # Procedure called to update TXFE_CFG0 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TXFE_CFG0 { PARAM_VALUE.TXFE_CFG0 } { + # Procedure called to validate TXFE_CFG0 + return true +} + +proc update_PARAM_VALUE.TXFE_CFG1 { PARAM_VALUE.TXFE_CFG1 } { + # Procedure called to update TXFE_CFG1 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TXFE_CFG1 { PARAM_VALUE.TXFE_CFG1 } { + # Procedure called to validate TXFE_CFG1 + return true +} + +proc update_PARAM_VALUE.TXFE_CFG2 { PARAM_VALUE.TXFE_CFG2 } { + # Procedure called to update TXFE_CFG2 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TXFE_CFG2 { PARAM_VALUE.TXFE_CFG2 } { + # Procedure called to validate TXFE_CFG2 + return true +} + +proc update_PARAM_VALUE.TXFE_CFG3 { PARAM_VALUE.TXFE_CFG3 } { + # Procedure called to update TXFE_CFG3 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TXFE_CFG3 { PARAM_VALUE.TXFE_CFG3 } { + # Procedure called to validate TXFE_CFG3 + return true +} + +proc update_PARAM_VALUE.TXPI_CFG { PARAM_VALUE.TXPI_CFG } { + # Procedure called to update TXPI_CFG when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TXPI_CFG { PARAM_VALUE.TXPI_CFG } { + # Procedure called to validate TXPI_CFG + return true +} + +proc update_PARAM_VALUE.TXPI_CFG0 { PARAM_VALUE.TXPI_CFG0 } { + # Procedure called to update TXPI_CFG0 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TXPI_CFG0 { PARAM_VALUE.TXPI_CFG0 } { + # Procedure called to validate TXPI_CFG0 + return true +} + +proc update_PARAM_VALUE.TXPI_CFG1 { PARAM_VALUE.TXPI_CFG1 } { + # Procedure called to update TXPI_CFG1 when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TXPI_CFG1 { PARAM_VALUE.TXPI_CFG1 } { + # Procedure called to validate TXPI_CFG1 + return true +} + +proc update_PARAM_VALUE.TXSWBST_EN { PARAM_VALUE.TXSWBST_EN } { + # Procedure called to update TXSWBST_EN when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TXSWBST_EN { PARAM_VALUE.TXSWBST_EN } { + # Procedure called to validate TXSWBST_EN + return true +} + +proc update_PARAM_VALUE.TX_CLK25_DIV { PARAM_VALUE.TX_CLK25_DIV } { + # Procedure called to update TX_CLK25_DIV when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TX_CLK25_DIV { PARAM_VALUE.TX_CLK25_DIV } { + # Procedure called to validate TX_CLK25_DIV + return true +} + +proc update_PARAM_VALUE.TX_LANE_INVERT { PARAM_VALUE.TX_LANE_INVERT } { + # Procedure called to update TX_LANE_INVERT when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TX_LANE_INVERT { PARAM_VALUE.TX_LANE_INVERT } { + # Procedure called to validate TX_LANE_INVERT + return true +} + +proc update_PARAM_VALUE.TX_LANE_RATE { PARAM_VALUE.TX_LANE_RATE } { + # Procedure called to update TX_LANE_RATE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TX_LANE_RATE { PARAM_VALUE.TX_LANE_RATE } { + # Procedure called to validate TX_LANE_RATE + return true +} + +proc update_PARAM_VALUE.TX_NUM_OF_LANES { PARAM_VALUE.TX_NUM_OF_LANES } { + # Procedure called to update TX_NUM_OF_LANES when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TX_NUM_OF_LANES { PARAM_VALUE.TX_NUM_OF_LANES } { + # Procedure called to validate TX_NUM_OF_LANES + return true +} + +proc update_PARAM_VALUE.TX_OUT_DIV { PARAM_VALUE.TX_OUT_DIV } { + # Procedure called to update TX_OUT_DIV when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.TX_OUT_DIV { PARAM_VALUE.TX_OUT_DIV } { + # Procedure called to validate TX_OUT_DIV + return true +} + +proc update_PARAM_VALUE.XCVR_TYPE { PARAM_VALUE.XCVR_TYPE } { + # Procedure called to update XCVR_TYPE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.XCVR_TYPE { PARAM_VALUE.XCVR_TYPE } { + # Procedure called to validate XCVR_TYPE + return true +} + + +proc update_MODELPARAM_VALUE.XCVR_TYPE { MODELPARAM_VALUE.XCVR_TYPE PARAM_VALUE.XCVR_TYPE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.XCVR_TYPE}] ${MODELPARAM_VALUE.XCVR_TYPE} +} + +proc update_MODELPARAM_VALUE.RX_LANE_RATE { MODELPARAM_VALUE.RX_LANE_RATE PARAM_VALUE.RX_LANE_RATE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RX_LANE_RATE}] ${MODELPARAM_VALUE.RX_LANE_RATE} +} + +proc update_MODELPARAM_VALUE.TX_LANE_RATE { MODELPARAM_VALUE.TX_LANE_RATE PARAM_VALUE.TX_LANE_RATE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TX_LANE_RATE}] ${MODELPARAM_VALUE.TX_LANE_RATE} +} + +proc update_MODELPARAM_VALUE.LINK_MODE { MODELPARAM_VALUE.LINK_MODE PARAM_VALUE.LINK_MODE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.LINK_MODE}] ${MODELPARAM_VALUE.LINK_MODE} +} + +proc update_MODELPARAM_VALUE.DATA_PATH_WIDTH { MODELPARAM_VALUE.DATA_PATH_WIDTH PARAM_VALUE.DATA_PATH_WIDTH } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.DATA_PATH_WIDTH}] ${MODELPARAM_VALUE.DATA_PATH_WIDTH} +} + +proc update_MODELPARAM_VALUE.QPLL_REFCLK_DIV { MODELPARAM_VALUE.QPLL_REFCLK_DIV PARAM_VALUE.QPLL_REFCLK_DIV } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.QPLL_REFCLK_DIV}] ${MODELPARAM_VALUE.QPLL_REFCLK_DIV} +} + +proc update_MODELPARAM_VALUE.QPLL_FBDIV_RATIO { MODELPARAM_VALUE.QPLL_FBDIV_RATIO PARAM_VALUE.QPLL_FBDIV_RATIO } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.QPLL_FBDIV_RATIO}] ${MODELPARAM_VALUE.QPLL_FBDIV_RATIO} +} + +proc update_MODELPARAM_VALUE.POR_CFG { MODELPARAM_VALUE.POR_CFG PARAM_VALUE.POR_CFG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.POR_CFG}] ${MODELPARAM_VALUE.POR_CFG} +} + +proc update_MODELPARAM_VALUE.PPF0_CFG { MODELPARAM_VALUE.PPF0_CFG PARAM_VALUE.PPF0_CFG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PPF0_CFG}] ${MODELPARAM_VALUE.PPF0_CFG} +} + +proc update_MODELPARAM_VALUE.PPF1_CFG { MODELPARAM_VALUE.PPF1_CFG PARAM_VALUE.PPF1_CFG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PPF1_CFG}] ${MODELPARAM_VALUE.PPF1_CFG} +} + +proc update_MODELPARAM_VALUE.QPLL_CFG { MODELPARAM_VALUE.QPLL_CFG PARAM_VALUE.QPLL_CFG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.QPLL_CFG}] ${MODELPARAM_VALUE.QPLL_CFG} +} + +proc update_MODELPARAM_VALUE.QPLL_FBDIV { MODELPARAM_VALUE.QPLL_FBDIV PARAM_VALUE.QPLL_FBDIV } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.QPLL_FBDIV}] ${MODELPARAM_VALUE.QPLL_FBDIV} +} + +proc update_MODELPARAM_VALUE.QPLL_CFG0 { MODELPARAM_VALUE.QPLL_CFG0 PARAM_VALUE.QPLL_CFG0 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.QPLL_CFG0}] ${MODELPARAM_VALUE.QPLL_CFG0} +} + +proc update_MODELPARAM_VALUE.QPLL_CFG1 { MODELPARAM_VALUE.QPLL_CFG1 PARAM_VALUE.QPLL_CFG1 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.QPLL_CFG1}] ${MODELPARAM_VALUE.QPLL_CFG1} +} + +proc update_MODELPARAM_VALUE.QPLL_CFG1_G3 { MODELPARAM_VALUE.QPLL_CFG1_G3 PARAM_VALUE.QPLL_CFG1_G3 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.QPLL_CFG1_G3}] ${MODELPARAM_VALUE.QPLL_CFG1_G3} +} + +proc update_MODELPARAM_VALUE.QPLL_CFG2 { MODELPARAM_VALUE.QPLL_CFG2 PARAM_VALUE.QPLL_CFG2 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.QPLL_CFG2}] ${MODELPARAM_VALUE.QPLL_CFG2} +} + +proc update_MODELPARAM_VALUE.QPLL_CFG2_G3 { MODELPARAM_VALUE.QPLL_CFG2_G3 PARAM_VALUE.QPLL_CFG2_G3 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.QPLL_CFG2_G3}] ${MODELPARAM_VALUE.QPLL_CFG2_G3} +} + +proc update_MODELPARAM_VALUE.QPLL_CFG3 { MODELPARAM_VALUE.QPLL_CFG3 PARAM_VALUE.QPLL_CFG3 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.QPLL_CFG3}] ${MODELPARAM_VALUE.QPLL_CFG3} +} + +proc update_MODELPARAM_VALUE.QPLL_CFG4 { MODELPARAM_VALUE.QPLL_CFG4 PARAM_VALUE.QPLL_CFG4 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.QPLL_CFG4}] ${MODELPARAM_VALUE.QPLL_CFG4} +} + +proc update_MODELPARAM_VALUE.QPLL_CP_G3 { MODELPARAM_VALUE.QPLL_CP_G3 PARAM_VALUE.QPLL_CP_G3 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.QPLL_CP_G3}] ${MODELPARAM_VALUE.QPLL_CP_G3} +} + +proc update_MODELPARAM_VALUE.QPLL_LPF { MODELPARAM_VALUE.QPLL_LPF PARAM_VALUE.QPLL_LPF } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.QPLL_LPF}] ${MODELPARAM_VALUE.QPLL_LPF} +} + +proc update_MODELPARAM_VALUE.QPLL_CP { MODELPARAM_VALUE.QPLL_CP PARAM_VALUE.QPLL_CP } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.QPLL_CP}] ${MODELPARAM_VALUE.QPLL_CP} +} + +proc update_MODELPARAM_VALUE.CPLL_FBDIV { MODELPARAM_VALUE.CPLL_FBDIV PARAM_VALUE.CPLL_FBDIV } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CPLL_FBDIV}] ${MODELPARAM_VALUE.CPLL_FBDIV} +} + +proc update_MODELPARAM_VALUE.CPLL_FBDIV_4_5 { MODELPARAM_VALUE.CPLL_FBDIV_4_5 PARAM_VALUE.CPLL_FBDIV_4_5 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CPLL_FBDIV_4_5}] ${MODELPARAM_VALUE.CPLL_FBDIV_4_5} +} + +proc update_MODELPARAM_VALUE.CPLL_CFG0 { MODELPARAM_VALUE.CPLL_CFG0 PARAM_VALUE.CPLL_CFG0 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CPLL_CFG0}] ${MODELPARAM_VALUE.CPLL_CFG0} +} + +proc update_MODELPARAM_VALUE.CPLL_CFG1 { MODELPARAM_VALUE.CPLL_CFG1 PARAM_VALUE.CPLL_CFG1 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CPLL_CFG1}] ${MODELPARAM_VALUE.CPLL_CFG1} +} + +proc update_MODELPARAM_VALUE.CPLL_CFG2 { MODELPARAM_VALUE.CPLL_CFG2 PARAM_VALUE.CPLL_CFG2 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CPLL_CFG2}] ${MODELPARAM_VALUE.CPLL_CFG2} +} + +proc update_MODELPARAM_VALUE.CPLL_CFG3 { MODELPARAM_VALUE.CPLL_CFG3 PARAM_VALUE.CPLL_CFG3 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CPLL_CFG3}] ${MODELPARAM_VALUE.CPLL_CFG3} +} + +proc update_MODELPARAM_VALUE.CH_HSPMUX { MODELPARAM_VALUE.CH_HSPMUX PARAM_VALUE.CH_HSPMUX } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.CH_HSPMUX}] ${MODELPARAM_VALUE.CH_HSPMUX} +} + +proc update_MODELPARAM_VALUE.PREIQ_FREQ_BST { MODELPARAM_VALUE.PREIQ_FREQ_BST PARAM_VALUE.PREIQ_FREQ_BST } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.PREIQ_FREQ_BST}] ${MODELPARAM_VALUE.PREIQ_FREQ_BST} +} + +proc update_MODELPARAM_VALUE.RXPI_CFG0 { MODELPARAM_VALUE.RXPI_CFG0 PARAM_VALUE.RXPI_CFG0 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RXPI_CFG0}] ${MODELPARAM_VALUE.RXPI_CFG0} +} + +proc update_MODELPARAM_VALUE.RXPI_CFG1 { MODELPARAM_VALUE.RXPI_CFG1 PARAM_VALUE.RXPI_CFG1 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RXPI_CFG1}] ${MODELPARAM_VALUE.RXPI_CFG1} +} + +proc update_MODELPARAM_VALUE.RTX_BUF_CML_CTRL { MODELPARAM_VALUE.RTX_BUF_CML_CTRL PARAM_VALUE.RTX_BUF_CML_CTRL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RTX_BUF_CML_CTRL}] ${MODELPARAM_VALUE.RTX_BUF_CML_CTRL} +} + +proc update_MODELPARAM_VALUE.TX_NUM_OF_LANES { MODELPARAM_VALUE.TX_NUM_OF_LANES PARAM_VALUE.TX_NUM_OF_LANES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TX_NUM_OF_LANES}] ${MODELPARAM_VALUE.TX_NUM_OF_LANES} +} + +proc update_MODELPARAM_VALUE.TX_OUT_DIV { MODELPARAM_VALUE.TX_OUT_DIV PARAM_VALUE.TX_OUT_DIV } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TX_OUT_DIV}] ${MODELPARAM_VALUE.TX_OUT_DIV} +} + +proc update_MODELPARAM_VALUE.TX_CLK25_DIV { MODELPARAM_VALUE.TX_CLK25_DIV PARAM_VALUE.TX_CLK25_DIV } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TX_CLK25_DIV}] ${MODELPARAM_VALUE.TX_CLK25_DIV} +} + +proc update_MODELPARAM_VALUE.TX_LANE_INVERT { MODELPARAM_VALUE.TX_LANE_INVERT PARAM_VALUE.TX_LANE_INVERT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TX_LANE_INVERT}] ${MODELPARAM_VALUE.TX_LANE_INVERT} +} + +proc update_MODELPARAM_VALUE.TX_PI_BIASSET { MODELPARAM_VALUE.TX_PI_BIASSET PARAM_VALUE.TX_PI_BIASSET } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TX_PI_BIASSET}] ${MODELPARAM_VALUE.TX_PI_BIASSET} +} + +proc update_MODELPARAM_VALUE.TXPI_CFG { MODELPARAM_VALUE.TXPI_CFG PARAM_VALUE.TXPI_CFG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TXPI_CFG}] ${MODELPARAM_VALUE.TXPI_CFG} +} + +proc update_MODELPARAM_VALUE.A_TXDIFFCTRL { MODELPARAM_VALUE.A_TXDIFFCTRL PARAM_VALUE.A_TXDIFFCTRL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.A_TXDIFFCTRL}] ${MODELPARAM_VALUE.A_TXDIFFCTRL} +} + +proc update_MODELPARAM_VALUE.RX_NUM_OF_LANES { MODELPARAM_VALUE.RX_NUM_OF_LANES PARAM_VALUE.RX_NUM_OF_LANES } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RX_NUM_OF_LANES}] ${MODELPARAM_VALUE.RX_NUM_OF_LANES} +} + +proc update_MODELPARAM_VALUE.RX_OUT_DIV { MODELPARAM_VALUE.RX_OUT_DIV PARAM_VALUE.RX_OUT_DIV } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RX_OUT_DIV}] ${MODELPARAM_VALUE.RX_OUT_DIV} +} + +proc update_MODELPARAM_VALUE.RX_CLK25_DIV { MODELPARAM_VALUE.RX_CLK25_DIV PARAM_VALUE.RX_CLK25_DIV } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RX_CLK25_DIV}] ${MODELPARAM_VALUE.RX_CLK25_DIV} +} + +proc update_MODELPARAM_VALUE.RX_DFE_LPM_CFG { MODELPARAM_VALUE.RX_DFE_LPM_CFG PARAM_VALUE.RX_DFE_LPM_CFG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RX_DFE_LPM_CFG}] ${MODELPARAM_VALUE.RX_DFE_LPM_CFG} +} + +proc update_MODELPARAM_VALUE.RX_PMA_CFG { MODELPARAM_VALUE.RX_PMA_CFG PARAM_VALUE.RX_PMA_CFG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RX_PMA_CFG}] ${MODELPARAM_VALUE.RX_PMA_CFG} +} + +proc update_MODELPARAM_VALUE.RX_CDR_CFG { MODELPARAM_VALUE.RX_CDR_CFG PARAM_VALUE.RX_CDR_CFG } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RX_CDR_CFG}] ${MODELPARAM_VALUE.RX_CDR_CFG} +} + +proc update_MODELPARAM_VALUE.RXCDR_CFG0 { MODELPARAM_VALUE.RXCDR_CFG0 PARAM_VALUE.RXCDR_CFG0 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RXCDR_CFG0}] ${MODELPARAM_VALUE.RXCDR_CFG0} +} + +proc update_MODELPARAM_VALUE.RXCDR_CFG2 { MODELPARAM_VALUE.RXCDR_CFG2 PARAM_VALUE.RXCDR_CFG2 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RXCDR_CFG2}] ${MODELPARAM_VALUE.RXCDR_CFG2} +} + +proc update_MODELPARAM_VALUE.RXCDR_CFG2_GEN2 { MODELPARAM_VALUE.RXCDR_CFG2_GEN2 PARAM_VALUE.RXCDR_CFG2_GEN2 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RXCDR_CFG2_GEN2}] ${MODELPARAM_VALUE.RXCDR_CFG2_GEN2} +} + +proc update_MODELPARAM_VALUE.RXCDR_CFG2_GEN4 { MODELPARAM_VALUE.RXCDR_CFG2_GEN4 PARAM_VALUE.RXCDR_CFG2_GEN4 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RXCDR_CFG2_GEN4}] ${MODELPARAM_VALUE.RXCDR_CFG2_GEN4} +} + +proc update_MODELPARAM_VALUE.RXCDR_CFG3 { MODELPARAM_VALUE.RXCDR_CFG3 PARAM_VALUE.RXCDR_CFG3 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RXCDR_CFG3}] ${MODELPARAM_VALUE.RXCDR_CFG3} +} + +proc update_MODELPARAM_VALUE.RXCDR_CFG3_GEN2 { MODELPARAM_VALUE.RXCDR_CFG3_GEN2 PARAM_VALUE.RXCDR_CFG3_GEN2 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RXCDR_CFG3_GEN2}] ${MODELPARAM_VALUE.RXCDR_CFG3_GEN2} +} + +proc update_MODELPARAM_VALUE.RXCDR_CFG3_GEN3 { MODELPARAM_VALUE.RXCDR_CFG3_GEN3 PARAM_VALUE.RXCDR_CFG3_GEN3 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RXCDR_CFG3_GEN3}] ${MODELPARAM_VALUE.RXCDR_CFG3_GEN3} +} + +proc update_MODELPARAM_VALUE.RXCDR_CFG3_GEN4 { MODELPARAM_VALUE.RXCDR_CFG3_GEN4 PARAM_VALUE.RXCDR_CFG3_GEN4 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RXCDR_CFG3_GEN4}] ${MODELPARAM_VALUE.RXCDR_CFG3_GEN4} +} + +proc update_MODELPARAM_VALUE.RXDFE_KH_CFG2 { MODELPARAM_VALUE.RXDFE_KH_CFG2 PARAM_VALUE.RXDFE_KH_CFG2 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RXDFE_KH_CFG2}] ${MODELPARAM_VALUE.RXDFE_KH_CFG2} +} + +proc update_MODELPARAM_VALUE.RXDFE_KH_CFG3 { MODELPARAM_VALUE.RXDFE_KH_CFG3 PARAM_VALUE.RXDFE_KH_CFG3 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RXDFE_KH_CFG3}] ${MODELPARAM_VALUE.RXDFE_KH_CFG3} +} + +proc update_MODELPARAM_VALUE.RX_WIDEMODE_CDR { MODELPARAM_VALUE.RX_WIDEMODE_CDR PARAM_VALUE.RX_WIDEMODE_CDR } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RX_WIDEMODE_CDR}] ${MODELPARAM_VALUE.RX_WIDEMODE_CDR} +} + +proc update_MODELPARAM_VALUE.RX_XMODE_SEL { MODELPARAM_VALUE.RX_XMODE_SEL PARAM_VALUE.RX_XMODE_SEL } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RX_XMODE_SEL}] ${MODELPARAM_VALUE.RX_XMODE_SEL} +} + +proc update_MODELPARAM_VALUE.TXDRV_FREQBAND { MODELPARAM_VALUE.TXDRV_FREQBAND PARAM_VALUE.TXDRV_FREQBAND } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TXDRV_FREQBAND}] ${MODELPARAM_VALUE.TXDRV_FREQBAND} +} + +proc update_MODELPARAM_VALUE.TXFE_CFG0 { MODELPARAM_VALUE.TXFE_CFG0 PARAM_VALUE.TXFE_CFG0 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TXFE_CFG0}] ${MODELPARAM_VALUE.TXFE_CFG0} +} + +proc update_MODELPARAM_VALUE.TXFE_CFG1 { MODELPARAM_VALUE.TXFE_CFG1 PARAM_VALUE.TXFE_CFG1 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TXFE_CFG1}] ${MODELPARAM_VALUE.TXFE_CFG1} +} + +proc update_MODELPARAM_VALUE.TXFE_CFG2 { MODELPARAM_VALUE.TXFE_CFG2 PARAM_VALUE.TXFE_CFG2 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TXFE_CFG2}] ${MODELPARAM_VALUE.TXFE_CFG2} +} + +proc update_MODELPARAM_VALUE.TXFE_CFG3 { MODELPARAM_VALUE.TXFE_CFG3 PARAM_VALUE.TXFE_CFG3 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TXFE_CFG3}] ${MODELPARAM_VALUE.TXFE_CFG3} +} + +proc update_MODELPARAM_VALUE.TXPI_CFG0 { MODELPARAM_VALUE.TXPI_CFG0 PARAM_VALUE.TXPI_CFG0 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TXPI_CFG0}] ${MODELPARAM_VALUE.TXPI_CFG0} +} + +proc update_MODELPARAM_VALUE.TXPI_CFG1 { MODELPARAM_VALUE.TXPI_CFG1 PARAM_VALUE.TXPI_CFG1 } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TXPI_CFG1}] ${MODELPARAM_VALUE.TXPI_CFG1} +} + +proc update_MODELPARAM_VALUE.TXSWBST_EN { MODELPARAM_VALUE.TXSWBST_EN PARAM_VALUE.TXSWBST_EN } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.TXSWBST_EN}] ${MODELPARAM_VALUE.TXSWBST_EN} +} + +proc update_MODELPARAM_VALUE.RX_LANE_INVERT { MODELPARAM_VALUE.RX_LANE_INVERT PARAM_VALUE.RX_LANE_INVERT } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.RX_LANE_INVERT}] ${MODELPARAM_VALUE.RX_LANE_INVERT} +} + diff --git a/adi_library/xilinx/util_clkdiv/Makefile b/adi_library/xilinx/util_clkdiv/Makefile new file mode 100644 index 00000000..55a83b72 --- /dev/null +++ b/adi_library/xilinx/util_clkdiv/Makefile @@ -0,0 +1,14 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +LIBRARY_NAME := util_clkdiv + +XILINX_DEPS += util_clkdiv.v +XILINX_DEPS += util_clkdiv_constr.xdc +XILINX_DEPS += util_clkdiv_ip.tcl +XILINX_DEPS += util_clkdiv_ooc.ttcl + +include ../../scripts/library.mk diff --git a/adi_library/xilinx/util_clkdiv/component.xml b/adi_library/xilinx/util_clkdiv/component.xml new file mode 100644 index 00000000..cf893dbc --- /dev/null +++ b/adi_library/xilinx/util_clkdiv/component.xml @@ -0,0 +1,254 @@ + + + analog.com + user + util_clkdiv + 1.0 + + + clk_out + + + + + + + CLK + + + clk_out + + + + + + clk + + + + + + + CLK + + + clk + + + + + + + + + xilinx_anylanguagesynthesis + Synthesis + :vivado.xilinx.com:synthesis + Verilog + util_clkdiv + + xilinx_anylanguagesynthesis_view_fileset + + + + viewChecksum + e4784cb9 + + + + + xilinx_anylanguagebehavioralsimulation + Simulation + :vivado.xilinx.com:simulation + Verilog + util_clkdiv + + xilinx_anylanguagebehavioralsimulation_view_fileset + + + + viewChecksum + a019022f + + + + + xilinx_xpgui + UI Layout + :vivado.xilinx.com:xgui.ui + + xilinx_xpgui_view_fileset + + + + viewChecksum + ce93cd79 + + + + + + + clk + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + clk_sel + + in + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + 0 + + + + + clk_out + + out + + + std_logic + xilinx_anylanguagesynthesis + xilinx_anylanguagebehavioralsimulation + + + + + + + + SIM_DEVICE + Sim Device + 7SERIES + + + SEL_0_DIV + Sel 0 Div + 4 + + + SEL_1_DIV + Sel 1 Div + 2 + + + + + + choice_list_2fc66e08 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + + + choice_list_441fc920 + 7SERIES + ULTRASCALE + + + + + xilinx_anylanguagesynthesis_view_fileset + + util_clkdiv_ooc.ttcl + ttcl + + + util_clkdiv_constr.xdc + xdc + + processing_order + late + + + + util_clkdiv.v + verilogSource + CHECKSUM_a019022f + + + + xilinx_anylanguagebehavioralsimulation_view_fileset + + util_clkdiv.v + verilogSource + + + + xilinx_xpgui_view_fileset + + xgui/util_clkdiv_v1_0.tcl + tclSource + CHECKSUM_ce93cd79 + XGUI_VERSION_2 + + + + util_clkdiv_v1_0 + + + SIM_DEVICE + Sim Device + 7SERIES + + + SEL_0_DIV + Sel 0 Div + 4 + + + SEL_1_DIV + Sel 1 Div + 2 + + + Component_Name + util_clkdiv_v1_0 + + + + + + virtex7 + + + /Analog_Devices + + util_clkdiv_v1_0 + level_2 + package_project + Analog Devices + http://www.analog.com + 1 + 2024-01-14T03:58:15Z + + + 2023.2.1 + + + + + + + diff --git a/adi_library/xilinx/util_clkdiv/util_clkdiv.v b/adi_library/xilinx/util_clkdiv/util_clkdiv.v new file mode 100644 index 00000000..e1930e02 --- /dev/null +++ b/adi_library/xilinx/util_clkdiv/util_clkdiv.v @@ -0,0 +1,97 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module util_clkdiv ( + input clk, + input clk_sel, + output clk_out +); + + parameter SIM_DEVICE = "7SERIES"; + parameter SEL_0_DIV = "4"; + parameter SEL_1_DIV = "2"; + + wire clk_div_sel_0_s; + wire clk_div_sel_1_s; + + generate if (SIM_DEVICE == "7SERIES") begin + + BUFR #( + .BUFR_DIVIDE(SEL_0_DIV), + .SIM_DEVICE("7SERIES") + ) clk_divide_sel_0 ( + .I(clk), + .CE(1), + .CLR(0), + .O(clk_div_sel_0_s)); + + BUFR #( + .BUFR_DIVIDE(SEL_1_DIV), + .SIM_DEVICE("7SERIES") + ) clk_divide_sel_1 ( + .I(clk), + .CE(1), + .CLR(0), + .O(clk_div_sel_1_s)); + + end else if (SIM_DEVICE == "ULTRASCALE") begin + + BUFGCE_DIV #( + .BUFGCE_DIVIDE(SEL_0_DIV) + ) clk_divide_sel_0 ( + .I(clk), + .CE(1), + .CLR(0), + .O(clk_div_sel_0_s)); + + BUFGCE_DIV #( + .BUFGCE_DIVIDE(SEL_1_DIV) + ) clk_divide_sel_1 ( + .I(clk), + .CE(1), + .CLR(0), + .O(clk_div_sel_1_s)); + + end endgenerate + + BUFGMUX_CTRL i_div_clk_gbuf ( + .I0(clk_div_sel_0_s), // 1-bit input: Clock input (S=0) + .I1(clk_div_sel_1_s), // 1-bit input: Clock input (S=1) + .S(clk_sel), + .O (clk_out)); + +endmodule diff --git a/adi_library/xilinx/util_clkdiv/util_clkdiv.xpr b/adi_library/xilinx/util_clkdiv/util_clkdiv.xpr new file mode 100644 index 00000000..e4a59970 --- /dev/null +++ b/adi_library/xilinx/util_clkdiv/util_clkdiv.xpr @@ -0,0 +1,406 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/adi_library/xilinx/util_clkdiv/util_clkdiv_constr.xdc b/adi_library/xilinx/util_clkdiv/util_clkdiv_constr.xdc new file mode 100644 index 00000000..48d51777 --- /dev/null +++ b/adi_library/xilinx/util_clkdiv/util_clkdiv_constr.xdc @@ -0,0 +1,10 @@ +############################################################################### +## Copyright (C) 2017-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_clock_groups \ + -group [get_clocks -of_objects [get_pins clk_divide_sel_0/O]] \ + -group [get_clocks -of_objects [get_pins clk_divide_sel_1/O]] \ + -logically_exclusive +set_false_path -to [get_pins i_div_clk_gbuf/S*] diff --git a/adi_library/xilinx/util_clkdiv/util_clkdiv_ip.tcl b/adi_library/xilinx/util_clkdiv/util_clkdiv_ip.tcl new file mode 100644 index 00000000..41d89d82 --- /dev/null +++ b/adi_library/xilinx/util_clkdiv/util_clkdiv_ip.tcl @@ -0,0 +1,38 @@ +############################################################################### +## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +adi_ip_create util_clkdiv +adi_ip_files util_clkdiv [list \ + "util_clkdiv_constr.xdc" \ + "util_clkdiv_ooc.ttcl" \ + "util_clkdiv.v" ] + +adi_ip_properties_lite util_clkdiv + +adi_ip_ttcl util_clkdiv "util_clkdiv_ooc.ttcl" + +set_property processing_order LATE [ipx::get_files "util_clkdiv_constr.xdc" \ + -of_objects [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]] + +set_property driver_value 0 [ipx::get_ports clk_sel -of_objects [ipx::current_core]] + +set_property value_validation_type list [ipx::get_user_parameters SIM_DEVICE -of_objects [ipx::current_core]] +set_property value_validation_list {7SERIES ULTRASCALE} [ipx::get_user_parameters SIM_DEVICE -of_objects [ipx::current_core]] + +set_property value_validation_type list [ipx::get_user_parameters SEL_0_DIV -of_objects [ipx::current_core]] +set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_0_DIV -of_objects [ipx::current_core]] + +set_property value_validation_type list [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]] +set_property value_validation_list {1 2 3 4 5 6 7 8} [ipx::get_user_parameters SEL_1_DIV -of_objects [ipx::current_core]] + +adi_add_bus clk_out master "xilinx.com:signal:clock_rtl:1.0" "xilinx.com:signal:clock:1.0" \ + [list {"clk_out" "CLK"}] + +ipx::infer_bus_interface clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] diff --git a/adi_library/xilinx/util_clkdiv/util_clkdiv_ooc.ttcl b/adi_library/xilinx/util_clkdiv/util_clkdiv_ooc.ttcl new file mode 100644 index 00000000..b0deed4b --- /dev/null +++ b/adi_library/xilinx/util_clkdiv/util_clkdiv_ooc.ttcl @@ -0,0 +1,21 @@ +############################################################################### +## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +# SPDX short identifier: ADIBSD +############################################################################### + +<: setFileUsedIn { out_of_context synthesis implementation } :> +<: ;#Component and file information :> +<: set ComponentName [getComponentNameString] :> +<: setOutputDirectory "./" :> +<: setFileName $ComponentName :> +<: setFileExtension "_ooc.xdc" :> + +# This XDC is used only for OOC mode of synthesis, implementation. +# These are default values for timing driven synthesis during OOC flow. +# These values will be overwritten during implementation with information +# from top level. + +create_clock -name clk -period 10 [get_ports clk] + +################################################################################ + diff --git a/adi_library/xilinx/util_clkdiv/xgui/util_clkdiv_v1_0.tcl b/adi_library/xilinx/util_clkdiv/xgui/util_clkdiv_v1_0.tcl new file mode 100644 index 00000000..cefa367d --- /dev/null +++ b/adi_library/xilinx/util_clkdiv/xgui/util_clkdiv_v1_0.tcl @@ -0,0 +1,55 @@ +# Definitional proc to organize widgets for parameters. +proc init_gui { IPINST } { + ipgui::add_param $IPINST -name "Component_Name" + #Adding Page + set Page_0 [ipgui::add_page $IPINST -name "Page 0"] + ipgui::add_param $IPINST -name "SEL_0_DIV" -parent ${Page_0} + ipgui::add_param $IPINST -name "SEL_1_DIV" -parent ${Page_0} + ipgui::add_param $IPINST -name "SIM_DEVICE" -parent ${Page_0} + + +} + +proc update_PARAM_VALUE.SEL_0_DIV { PARAM_VALUE.SEL_0_DIV } { + # Procedure called to update SEL_0_DIV when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SEL_0_DIV { PARAM_VALUE.SEL_0_DIV } { + # Procedure called to validate SEL_0_DIV + return true +} + +proc update_PARAM_VALUE.SEL_1_DIV { PARAM_VALUE.SEL_1_DIV } { + # Procedure called to update SEL_1_DIV when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SEL_1_DIV { PARAM_VALUE.SEL_1_DIV } { + # Procedure called to validate SEL_1_DIV + return true +} + +proc update_PARAM_VALUE.SIM_DEVICE { PARAM_VALUE.SIM_DEVICE } { + # Procedure called to update SIM_DEVICE when any of the dependent parameters in the arguments change +} + +proc validate_PARAM_VALUE.SIM_DEVICE { PARAM_VALUE.SIM_DEVICE } { + # Procedure called to validate SIM_DEVICE + return true +} + + +proc update_MODELPARAM_VALUE.SIM_DEVICE { MODELPARAM_VALUE.SIM_DEVICE PARAM_VALUE.SIM_DEVICE } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SIM_DEVICE}] ${MODELPARAM_VALUE.SIM_DEVICE} +} + +proc update_MODELPARAM_VALUE.SEL_0_DIV { MODELPARAM_VALUE.SEL_0_DIV PARAM_VALUE.SEL_0_DIV } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SEL_0_DIV}] ${MODELPARAM_VALUE.SEL_0_DIV} +} + +proc update_MODELPARAM_VALUE.SEL_1_DIV { MODELPARAM_VALUE.SEL_1_DIV PARAM_VALUE.SEL_1_DIV } { + # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value + set_property value [get_property value ${PARAM_VALUE.SEL_1_DIV}] ${MODELPARAM_VALUE.SEL_1_DIV} +} + diff --git a/common/.gitkeep b/common/.gitkeep new file mode 100644 index 00000000..e69de29b diff --git a/common/ApproxAbs.v b/common/ApproxAbs.v new file mode 100644 index 00000000..172dfebe --- /dev/null +++ b/common/ApproxAbs.v @@ -0,0 +1,147 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2019/11/15 20:02:47 +// Design Name: +// Module Name: ApproxAbs +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ApproxAbs( + input clk, + + input Nd, + input [27:0] Dini, + input [27:0] Dinq, + + output reg Abs_Rdy = 1'b0, + output reg [28:0] Abs_Dout= 29'd0 + ); + + + // һӳ٣为ֵ + //=============================================================== + reg [27:0] Din_I_neg; + always @(posedge clk)begin + if(Dini==28'b1000_0000_0000_0000_0000_0000_0000)begin + Din_I_neg <= 28'b0111_1111_1111_1111_1111_1111_1111; + end else begin + Din_I_neg <= -Dini; + end + end + + reg [27:0] Din_Q_neg; + always @(posedge clk)begin + if(Dinq==28'b1000_0000_0000_0000_0000_0000_0000)begin + Din_Q_neg <= 28'b0111_1111_1111_1111_1111_1111_1111; + end else begin + Din_Q_neg <= -Dinq; + end + end + + // ڶӳ٣ֵ + //=============================================================== + reg [27:0] Din_I_D1; + reg [27:0] Din_Q_D1; + always @(posedge clk)begin + Din_I_D1 <= Dini; + Din_Q_D1 <= Dinq; + end + + reg [27:0] Abs_Din_I; + reg [27:0] Abs_Din_Q; + always @(posedge clk)begin + if(Din_I_D1[27]==1'b1) + Abs_Din_I <= Din_I_neg; + else + Abs_Din_I <= Din_I_D1; + + if(Din_Q_D1[27]==1'b1) + Abs_Din_Q <= Din_Q_neg; + else + Abs_Din_Q <= Din_Q_D1; + end + + // ӳ٣ȷI/Q·ֵĴСϵ + //=============================================================== + reg [27:0] AbsIQ_max; + reg [27:0] AbsIQ_min; + always @(posedge clk)begin + if (Abs_Din_I>=Abs_Din_Q) begin + AbsIQ_max <= Abs_Din_I; + AbsIQ_min <= Abs_Din_Q; + end else begin + AbsIQ_max <= Abs_Din_Q; + AbsIQ_min <= Abs_Din_I; + end + end + + // ļӳ٣MXQѡϵ7/81/2 + //=============================================================== + reg [27:0] AbsIQ_max_7by8; + reg [27:0] AbsIQ_min_1by2; + always @ (posedge clk) begin + AbsIQ_max_7by8[27:0] <= AbsIQ_max[27:0]-{3'b000,AbsIQ_max[27:3]}; + AbsIQ_min_1by2[27:0] <= {AbsIQ_min[27],AbsIQ_min[27:1]}; + end + + // 弶ӳ٣1bitλչͣ + // (MXQ)м佫ӳһclk Dout_Temp2,ʹ Dout_Temp2 Dout_Tempͬһclk½бȽϡ + //=============================================================== + reg [28:0] Dout_Temp; + reg [28:0] Dout_Temp1; + reg [28:0] Dout_Temp2; + always @(posedge clk) begin + Dout_Temp <= {1'b0,AbsIQ_max_7by8[27:0]}+{1'b0,AbsIQ_min_1by2[27:0]}; + Dout_Temp1 <= {1'b0,AbsIQ_max[27:0]}; + Dout_Temp2 <= Dout_Temp1[28:0]; + end + + // (MXQ)ӳ٣ֵI/Q·ֵֵȽֵ֮ + reg [28:0] Dout; + always @(posedge clk) begin + if(Dout_Temp[28:0]>=Dout_Temp2[27:0]) + Dout[28:0] <= Dout_Temp[28:0]; + else + Dout[28:0] <= Dout_Temp2[28:0]; + end + + + // Dout_validDin_valid߼ӳ٣ + reg Dout_valid_b6; + reg Dout_valid_b5; + reg Dout_valid_b4; + reg Dout_valid_b3; + reg Dout_valid_b2; + reg Dout_valid_b1; + always@(posedge clk) begin //(MXQ) posedge clk ,⣬ڴ + Dout_valid_b6 <= Nd; + Dout_valid_b5 <= Dout_valid_b6; + Dout_valid_b4 <= Dout_valid_b5; + Dout_valid_b3 <= Dout_valid_b4; + Dout_valid_b2 <= Dout_valid_b3; + Dout_valid_b1 <= Dout_valid_b2; + Abs_Rdy <= Dout_valid_b1; + end + + always @ (posedge clk) begin + if(Dout_valid_b1) + Abs_Dout <= Dout; + else + Abs_Dout <= 29'd0; + end + +endmodule diff --git a/common/ApproxModuli_26bit.v b/common/ApproxModuli_26bit.v new file mode 100644 index 00000000..4c137301 --- /dev/null +++ b/common/ApproxModuli_26bit.v @@ -0,0 +1,129 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2020/12/16 14:26:28 +// Design Name: +// Module Name: ApproxModuli_26bit +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ApproxModuli_26bit( + input clk, + input din_valid, + input [25:0] din_I, + input [25:0] din_Q, + output reg dout_valid = 0, + output reg [25:0] dout = 0 + ); + +reg [25:0] din_I_D1 = 0, din_Q_D1 = 0, din_I_D2 = 0, din_Q_D2 = 0; +reg [25:0] Sub1_s = 0; +reg [25:0] Xmax = 0, Xmin = 0; +always @(posedge clk) + begin + if(din_valid) + din_I_D1[25:0] <= (din_I[25]==1'b0)? din_I[25:0]:-din_I[25:0]; + else + din_I_D1[25:0] <= 26'd0; + + din_I_D2[25:0] <= din_I_D1[25:0]; + + if(din_valid) + din_Q_D1[25:0] <= (din_Q[25]==1'b0)? din_Q[25:0]:-din_Q[25:0]; + else + din_Q_D1[25:0] <= 26'd0; + + din_Q_D2[25:0] <= din_Q_D1[25:0]; + + Sub1_s[25:0] <= din_I_D1[25:0] - din_Q_D1[25:0]; + + if(Sub1_s[25]) + Xmax[25:0] <= din_Q_D2[25:0]; + else + Xmax[25:0] <= din_I_D2[25:0]; + + if(Sub1_s[25]) + Xmin[25:0] <= din_I_D2[25:0]; + else + Xmin[25:0] <= din_Q_D2[25:0]; + end + +reg [25:0] Xmax_D1 = 0, Xmax_31by32 = 0, Xmax_13by16 = 0; +reg [25:0] Xmin_9by32 = 0, Xmin_19by32 = 0; +always @(posedge clk) + begin + Xmax_D1[25:0] <= Xmax[25:0]; + Xmax_31by32[25:0] <= Xmax[25:0] - {5'd0, Xmax[25:5]}; + Xmax_13by16[25:0] <= Xmax[25:0] - {3'd0, Xmax[25:3]} - {4'd0, Xmax[25:4]}; + + Xmin_9by32[25:0] <= {2'd0, Xmin[25:2]} + {5'd0, Xmin[25:5]}; + Xmin_19by32[25:0] <= {1'd0, Xmin[25:1]} + {4'd0, Xmin[25:4]} + {5'd0, Xmin[25:5]}; + end + +reg [25:0] t1 = 0, t2 = 0, t3 = 0; +always @(posedge clk) + begin + t1[25:0] <= Xmax_D1[25:0]; + t2[25:0] <= Xmax_31by32[25:0] + Xmin_9by32[25:0]; + t3[25:0] <= Xmax_13by16[25:0] + Xmin_19by32[25:0]; + end + +reg [25:0] sub2_s = 0; +reg [25:0] sub3_a = 0, sub3_b = 0, sub3_s = 0; +reg [25:0] sub3_a_D1 = 0, sub3_b_D1 = 0; +reg [25:0] t1_D1 = 0, t2_D1 = 0, t3_D1 = 0; +always @(posedge clk) + begin + t1_D1[25:0] <= t1[25:0]; + t2_D1[25:0] <= t2[25:0]; + t3_D1[25:0] <= t3[25:0]; + + sub2_s[25:0] <= t1[25:0] - t2[25:0]; + + if(sub2_s[25]) + sub3_a[25:0] <= t2_D1[25:0]; + else + sub3_a[25:0] <= t1_D1[25:0]; + + sub3_b[25:0] <= t3_D1[25:0]; + + sub3_a_D1[25:0] <= sub3_a[25:0]; + sub3_b_D1[25:0] <= sub3_b[25:0]; + + sub3_s[25:0] <= sub3_a[25:0] - sub3_b[25:0]; + + if(sub3_s[25]) + dout[25:0] <= sub3_b_D1[25:0]; + else + dout[25:0] <= sub3_a_D1[25:0]; + end + +reg din_valid_D1 = 0, din_valid_D2 = 0, din_valid_D3 = 0, din_valid_D4 = 0; +reg din_valid_D5 = 0, din_valid_D6 = 0, din_valid_D7 = 0, din_valid_D8 = 0; +always @(posedge clk) + begin + din_valid_D1 <= din_valid; + din_valid_D2 <= din_valid_D1; + din_valid_D3 <= din_valid_D2; + din_valid_D4 <= din_valid_D3; + din_valid_D5 <= din_valid_D4; + din_valid_D6 <= din_valid_D5; + din_valid_D7 <= din_valid_D6; + din_valid_D8 <= din_valid_D7; + + dout_valid <= din_valid_D8; + end +endmodule diff --git a/common/adder_tree_ppl.v b/common/adder_tree_ppl.v new file mode 100644 index 00000000..bb4b0007 --- /dev/null +++ b/common/adder_tree_ppl.v @@ -0,0 +1,246 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/11/13 16:05:53 +// Design Name: +// Module Name: adder_tree_ppl +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// REF: https://blog.csdn.net/jiang1960034308/article/details/118078073 +// https://github.com/raiker/tarsier/tree/master/src/ +// +////////////////////////////////////////////////////////////////////////////////// + + +module adder_tree_ppl +#( + parameter DATA_I_WIDTH = 8, + parameter DATA_NUM = 5, + parameter DELAY_STAGE = $clog2(DATA_NUM), // necessary for pipeline delay stage + + localparam DATA_O_WIDTH = DATA_I_WIDTH + $clog2(DATA_NUM), + localparam DATA_NUM_A = DATA_NUM / 2, + localparam DATA_NUM_B = DATA_NUM - DATA_NUM_A, + localparam DATA_O_WIDTH_A = DATA_I_WIDTH + $clog2(DATA_NUM_A), + localparam DATA_O_WIDTH_B = DATA_I_WIDTH + $clog2(DATA_NUM_B) +) +( + // clock & reset + input clk, + input rst, + + // input data + input din_valid, + input signed [DATA_NUM*DATA_I_WIDTH-1 : 0] din_data, + + // output data + output dout_valid, + output signed [DATA_O_WIDTH-1 : 0] dout_data +); + +if (DATA_NUM == 1) begin + if (DELAY_STAGE == 1) begin + // buffer when an extra delay stage is needed + reg dout_valid_buf = 'b0; + reg signed [DATA_O_WIDTH-1 : 0] dout_data_buf = 'b0; + + always@(posedge clk) begin + dout_valid_buf <= (rst) ? 'b0 : din_valid; + dout_data_buf <= (rst) ? 'b0 : din_data; + end + + assign dout_valid = dout_valid_buf; + assign dout_data = dout_data_buf; + end + else begin + assign dout_valid = din_valid; + assign dout_data = din_data; + end +end +else begin + reg dout_valid_buf = 'b0; + reg signed [DATA_O_WIDTH-1 : 0] dout_data_buf = 'b0; + + wire din_valid_a; + wire din_valid_b; + wire signed [DATA_I_WIDTH * DATA_NUM_A - 1:0] din_data_a; + wire signed [DATA_I_WIDTH * DATA_NUM_B - 1:0] din_data_b; + + wire dout_valid_a; + wire dout_valid_b; + wire signed [DATA_O_WIDTH_A-1:0] dout_data_a; + wire signed [DATA_O_WIDTH_B-1:0] dout_data_b; + + assign din_valid_a = din_valid; + assign din_valid_b = din_valid; + assign din_data_a = din_data[DATA_I_WIDTH * DATA_NUM_A - 1: 0]; + assign din_data_b = din_data[DATA_NUM * DATA_I_WIDTH - 1: DATA_I_WIDTH * DATA_NUM_A]; + + //divide set into two chunks, conquer + adder_tree_ppl #( + .DATA_I_WIDTH (DATA_I_WIDTH ), + .DATA_NUM (DATA_NUM_A ), + .DELAY_STAGE (DELAY_STAGE - 1) + ) subtree_a ( + // clock & reset + .clk (clk ), + .rst (rst ), + + // input data + .din_valid (din_valid_a ), + .din_data (din_data_a ), + + // output data + .dout_valid (dout_valid_a ), + .dout_data (dout_data_a ) + ); + + adder_tree_ppl #( + .DATA_I_WIDTH (DATA_I_WIDTH ), + .DATA_NUM (DATA_NUM_B ), + .DELAY_STAGE (DELAY_STAGE - 1) + ) subtree_b ( + // clock & reset + .clk (clk ), + .rst (rst ), + + // input data + .din_valid (din_valid_b ), + .din_data (din_data_b ), + + // output data + .dout_valid (dout_valid_b ), + .dout_data (dout_data_b ) + ); + + always@(posedge clk) begin + if (rst) begin + dout_valid_buf <= 'b0; + dout_data_buf <= 'b0; + end + else begin + dout_valid_buf <= dout_valid_a & dout_valid_b; + dout_data_buf <= dout_data_a + dout_data_b; + end + end + + assign dout_valid = dout_valid_buf; + assign dout_data = dout_data_buf; +end + +endmodule + + +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/11/13 16:40:15 +// Last Modified Data: 2022/11/02 +// Design Name: +// Module Name: tb_adder_tree_pip +// Project Name: +// Target Devices: +// Tool Versions: +// Description: testbench for [adder_tree_ppl] +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +// module tb_adder_tree_ppl; + +// localparam DATA_I_WIDTH = 16; +// localparam DATA_NUM = 9; + +// reg clk = 1'b1; +// reg rst = 1'b1; +// reg din_valid = 1'b0; +// reg [DATA_NUM*DATA_I_WIDTH-1 : 0] din_data = 'b0; +// wire dout_valid; +// wire [DATA_I_WIDTH+$clog2(DATA_NUM)-1 : 0] dout_data; + +// adder_tree_ppl #( +// .DATA_I_WIDTH (DATA_I_WIDTH ), +// .DATA_NUM (DATA_NUM ) +// ) u_adder_tree_ppl +// ( +// // clock & reset +// .clk (clk ), +// .rst (rst ), + +// // input data +// .din_valid (din_valid ), +// .din_data (din_data ), + +// // output data +// .dout_valid (dout_valid ), +// .dout_data (dout_data ) +// ); + +// initial begin +// #102 +// rst = 1'b0; +// #200 +// @(posedge clk) begin +// din_valid = 1'b1; +// din_data = { +// 16'd1, +// 16'd2, +// 16'd3, +// 16'd4, +// 16'd5, +// 16'd6, +// 16'd7, +// 16'd8, +// 16'd9 +// }; +// end + +// @(posedge clk) begin +// din_valid = 1'b1; +// din_data = { +// 16'd1230, +// 16'd1231, +// 16'd1232, +// 16'd1233, +// 16'd1234, +// 16'd1235, +// 16'd1236, +// 16'd1237, +// 16'd1238 +// }; +// end + + +// @(posedge clk) din_valid = 1'b0; +// end + +// always #5 clk = ~clk; + +// endmodule diff --git a/common/trunc_32bit_to_12bit.v b/common/trunc_32bit_to_12bit.v new file mode 100644 index 00000000..797642fc --- /dev/null +++ b/common/trunc_32bit_to_12bit.v @@ -0,0 +1,515 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 2023/03/01 10:44:50 +// Design Name: +// Module Name: trunc_32bit_to_12bit +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module trunc_32bit_to_12bit( + input clk, + input rst, + input [31:0] trunc_32bit_in, + input [4:0] vio_trunc, + + output reg [11:0] trunc_12bit_out = 12'd0, + output reg trunc_overflow = 1'd0 + ); + + always @ (posedge clk) begin + if(rst) begin + trunc_12bit_out[11:0] <= 12'd0; + trunc_overflow <= 1'd0; + end else begin + case(vio_trunc[4:0]) + 5'd0:begin + if(trunc_32bit_in[31:31] == 1'd1 || trunc_32bit_in[31:31] == 1'd0) begin + if(trunc_32bit_in[31:31] == 1'd0 &&trunc_32bit_in[19] == 1'd1 && trunc_32bit_in[31:20] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[31:20] + 12'd1; + end + else begin + if(trunc_32bit_in[31:31] == 1'd1 && trunc_32bit_in[19:0] > 20'd524288) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[31:20] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[31:20]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd1:begin + if(trunc_32bit_in[31:30] == 2'd3 || trunc_32bit_in[31:30] == 2'd0) begin + if(trunc_32bit_in[31:30] == 2'd0 &&trunc_32bit_in[18] == 1'd1 && trunc_32bit_in[30:19] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[30:19] + 12'd1; + end + else begin + if(trunc_32bit_in[31:30] == 2'd3 && trunc_32bit_in[18:0] > 19'd262144) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[30:19] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[30:19]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd2:begin + if(trunc_32bit_in[31:29] == 3'd7 || trunc_32bit_in[31:29] == 3'd0) begin + if(trunc_32bit_in[31:29] == 3'd0 &&trunc_32bit_in[17] == 1'd1 && trunc_32bit_in[29:18] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[29:18] + 12'd1; + end + else begin + if(trunc_32bit_in[31:29] == 3'd7 && trunc_32bit_in[17:0] > 18'd131072) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[29:18] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[29:18]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd3:begin + if(trunc_32bit_in[31:28] == 4'd15 || trunc_32bit_in[31:28] == 4'd0) begin + if(trunc_32bit_in[31:28] == 4'd0 &&trunc_32bit_in[16] == 1'd1 && trunc_32bit_in[28:17] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[28:17] + 12'd1; + end + else begin + if(trunc_32bit_in[31:28] == 4'd15 && trunc_32bit_in[16:0] > 17'd65536) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[28:17] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[28:17]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd4:begin + if(trunc_32bit_in[31:27] == 5'd31 || trunc_32bit_in[31:27] == 5'd0) begin + if(trunc_32bit_in[31:27] == 5'd0 &&trunc_32bit_in[15] == 1'd1 && trunc_32bit_in[27:16] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[27:16] + 12'd1; + end + else begin + if(trunc_32bit_in[31:27] == 5'd31 && trunc_32bit_in[15:0] > 16'd32768) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[27:16] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[27:16]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd5:begin + if(trunc_32bit_in[31:26] == 6'd63 || trunc_32bit_in[31:26] == 6'd0) begin + if(trunc_32bit_in[31:26] == 6'd0 &&trunc_32bit_in[14] == 1'd1 && trunc_32bit_in[26:15] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[26:15] + 12'd1; + end + else begin + if(trunc_32bit_in[31:26] == 6'd63 && trunc_32bit_in[14:0] > 15'd16384) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[26:15] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[26:15]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd6:begin + if(trunc_32bit_in[31:25] == 7'd127 || trunc_32bit_in[31:25] == 7'd0) begin + if(trunc_32bit_in[31:25] == 7'd0 &&trunc_32bit_in[13] == 1'd1 && trunc_32bit_in[25:14] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[25:14] + 12'd1; + end + else begin + if(trunc_32bit_in[31:25] == 7'd127 && trunc_32bit_in[13:0] > 14'd8192) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[25:14] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[25:14]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd7:begin + if(trunc_32bit_in[31:24] == 8'd255 || trunc_32bit_in[31:24] == 8'd0) begin + if(trunc_32bit_in[31:24] == 8'd0 &&trunc_32bit_in[12] == 1'd1 && trunc_32bit_in[24:13] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[24:13] + 12'd1; + end + else begin + if(trunc_32bit_in[31:24] == 8'd255 && trunc_32bit_in[12:0] > 13'd4096) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[24:13] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[24:13]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd8:begin + if(trunc_32bit_in[31:23] == 9'd511 || trunc_32bit_in[31:23] == 9'd0) begin + if(trunc_32bit_in[31:23] == 9'd0 &&trunc_32bit_in[11] == 1'd1 && trunc_32bit_in[23:12] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[23:12] + 12'd1; + end + else begin + if(trunc_32bit_in[31:23] == 9'd511 && trunc_32bit_in[11:0] > 12'd2048) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[23:12] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[23:12]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd9:begin + if(trunc_32bit_in[31:22] == 10'd1023 || trunc_32bit_in[31:22] == 10'd0) begin + if(trunc_32bit_in[31:22] == 10'd0 &&trunc_32bit_in[10] == 1'd1 && trunc_32bit_in[22:11] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[22:11] + 12'd1; + end + else begin + if(trunc_32bit_in[31:22] == 10'd1023 && trunc_32bit_in[10:0] > 11'd1024) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[22:11] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[22:11]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd10:begin + if(trunc_32bit_in[31:21] == 11'd2047 || trunc_32bit_in[31:21] == 11'd0) begin + if(trunc_32bit_in[31:21] == 11'd0 &&trunc_32bit_in[9] == 1'd1 && trunc_32bit_in[21:10] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[21:10] + 12'd1; + end + else begin + if(trunc_32bit_in[31:21] == 11'd2047 && trunc_32bit_in[9:0] > 10'd512) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[21:10] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[21:10]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd11:begin + if(trunc_32bit_in[31:20] == 12'd4095 || trunc_32bit_in[31:20] == 12'd0) begin + if(trunc_32bit_in[31:20] == 12'd0 &&trunc_32bit_in[8] == 1'd1 && trunc_32bit_in[20:9] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[20:9] + 12'd1; + end + else begin + if(trunc_32bit_in[31:20] == 12'd4095 && trunc_32bit_in[8:0] > 9'd256) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[20:9] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[20:9]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd12:begin + if(trunc_32bit_in[31:19] == 13'd8191 || trunc_32bit_in[31:19] == 13'd0) begin + if(trunc_32bit_in[31:19] == 13'd0 &&trunc_32bit_in[7] == 1'd1 && trunc_32bit_in[19:8] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[19:8] + 12'd1; + end + else begin + if(trunc_32bit_in[31:19] == 13'd8191 && trunc_32bit_in[7:0] > 8'd128) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[19:8] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[19:8]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd13:begin + if(trunc_32bit_in[31:18] == 14'd16383 || trunc_32bit_in[31:18] == 14'd0) begin + if(trunc_32bit_in[31:18] == 14'd0 &&trunc_32bit_in[6] == 1'd1 && trunc_32bit_in[18:7] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[18:7] + 12'd1; + end + else begin + if(trunc_32bit_in[31:18] == 14'd16383 && trunc_32bit_in[6:0] > 7'd64) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[18:7] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[18:7]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd14:begin + if(trunc_32bit_in[31:17] == 15'd32767 || trunc_32bit_in[31:17] == 15'd0) begin + if(trunc_32bit_in[31:17] == 15'd0 &&trunc_32bit_in[5] == 1'd1 && trunc_32bit_in[17:6] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[17:6] + 12'd1; + end + else begin + if(trunc_32bit_in[31:17] == 15'd32767 && trunc_32bit_in[5:0] > 6'd32) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[17:6] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[17:6]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd15:begin + if(trunc_32bit_in[31:16] == 16'd65535 || trunc_32bit_in[31:16] == 16'd0) begin + if(trunc_32bit_in[31:16] == 16'd0 &&trunc_32bit_in[4] == 1'd1 && trunc_32bit_in[16:5] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[16:5] + 12'd1; + end + else begin + if(trunc_32bit_in[31:16] == 16'd65535 && trunc_32bit_in[4:0] > 5'd16) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[16:5] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[16:5]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd16:begin + if(trunc_32bit_in[31:15] == 17'd131071 || trunc_32bit_in[31:15] == 17'd0) begin + if(trunc_32bit_in[31:15] == 17'd0 &&trunc_32bit_in[3] == 1'd1 && trunc_32bit_in[15:4] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[15:4] + 12'd1; + end + else begin + if(trunc_32bit_in[31:15] == 17'd131071 && trunc_32bit_in[3:0] > 4'd8) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[15:4] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[15:4]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd17:begin + if(trunc_32bit_in[31:14] == 18'd262143 || trunc_32bit_in[31:14] == 18'd0) begin + if(trunc_32bit_in[31:14] == 18'd0 &&trunc_32bit_in[2] == 1'd1 && trunc_32bit_in[14:3] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[14:3] + 12'd1; + end + else begin + if(trunc_32bit_in[31:14] == 18'd262143 && trunc_32bit_in[2:0] > 3'd4) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[14:3] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[14:3]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd18:begin + if(trunc_32bit_in[31:13] == 19'd524287 || trunc_32bit_in[31:13] == 19'd0) begin + if(trunc_32bit_in[31:13] == 19'd0 &&trunc_32bit_in[1] == 1'd1 && trunc_32bit_in[13:2] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[13:2] + 12'd1; + end + else begin + if(trunc_32bit_in[31:13] == 19'd524287 && trunc_32bit_in[1:0] > 2'd2) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[13:2] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[13:2]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + 5'd19:begin + if(trunc_32bit_in[31:12] == 20'd1048575 || trunc_32bit_in[31:12] == 20'd0) begin + if(trunc_32bit_in[31:12] == 20'd0 &&trunc_32bit_in[0] == 1'd1 && trunc_32bit_in[12:1] != 12'd2047) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[12:1] + 12'd1; + end + else begin + if(trunc_32bit_in[31:12] == 20'd1048575 && trunc_32bit_in[0:0] > 1'd1) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[12:1] + 12'd1; + end + else begin + trunc_12bit_out[11:0] <= trunc_32bit_in[12:1]; + end + end + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + default:begin + if(trunc_32bit_in[31:11] == 21'd2097151 || trunc_32bit_in[31:11] == 21'd0) begin + trunc_12bit_out[11:0] <= trunc_32bit_in[11:0]; + trunc_overflow <= 1'd0; + end else begin + if(trunc_32bit_in[31] == 1'd1) begin + trunc_12bit_out[11:0] <= -12'd2048; + end else begin + trunc_12bit_out[11:0] <= 12'd2047; + end + trunc_overflow <= 1'd1; + end + end + endcase + end + end +endmodule \ No newline at end of file diff --git a/common/truncate_manual.v b/common/truncate_manual.v new file mode 100644 index 00000000..eb967614 --- /dev/null +++ b/common/truncate_manual.v @@ -0,0 +1,43 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 04/21/2023 11:37:14 AM +// Design Name: +// Module Name: truncate_manual +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module truncate_manual +#( + DATA_I_WIDTH = 30, + DATA_O_WIDTH = 12 +) +( + input clk, + input rst, + + input [DATA_I_WIDTH-1 : 0] data_in, + input data_in_valid, + + input [$clog2(DATA_I_WIDTH)-1 : 0] trunc_pos, + + output [DATA_O_WIDTH-1 : 0] data_out, + output data_out_valid +); + +assign data_out = data_in[trunc_pos -: DATA_O_WIDTH]; + +endmodule diff --git a/custom_ips/.gitkeep b/custom_ips/.gitkeep new file mode 100644 index 00000000..e69de29b diff --git a/modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.srcs/sim_1/new/tb_addr_to_wave.v b/modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.srcs/sim_1/new/tb_addr_to_wave.v new file mode 100644 index 00000000..2e5b3c4b --- /dev/null +++ b/modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.srcs/sim_1/new/tb_addr_to_wave.v @@ -0,0 +1,70 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 01/14/2024 03:49:29 PM +// Design Name: +// Module Name: tb_addr_to_wave +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb_addr_to_wave; + +localparam PHASE_WIDTH = 12; +localparam WAVE_WIDTH = 12; + +// ports +reg clk = 1'b0; +reg rst = 1'b1; + +reg [PHASE_WIDTH-1 : 0] phase = 'b0; +wire [WAVE_WIDTH-1 : 0] cos_wave, sin_wave; + +// module instantiation +addr_to_wave +#( + .PHASE_WIDTH (PHASE_WIDTH), + .WAVE_WIDTH (WAVE_WIDTH ) +) u_addr_to_wave +( + // clock & reset + .clk (clk ), + .rst (rst ), + + .phase (phase ), + + .cos_wave (cos_wave ), + .sin_wave (sin_wave ) +); + +// stimulus +always @(posedge clk) begin + if (rst) begin + phase = 'b0; + end + else begin + phase <= phase + 1'b1; + end +end + +initial begin + rst = 1'b1; + #102; + rst = 1'b0; +end + +always #5 clk = ~clk; + +endmodule diff --git a/modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.srcs/sim_1/new/tb_dds_par.v b/modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.srcs/sim_1/new/tb_dds_par.v new file mode 100644 index 00000000..746a2cf8 --- /dev/null +++ b/modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.srcs/sim_1/new/tb_dds_par.v @@ -0,0 +1,123 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 01/14/2024 08:11:00 PM +// Design Name: +// Module Name: tb_dds_par +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb_dds_par; + +localparam PHASE_WIDTH = 16; +localparam WAVE_WIDTH = 16; +localparam PARALLEL_NUM = 7; + +// ports +wire clk; +reg clk_fast = 1'b0; +reg rst = 1'b1; +reg rst_fast = 1'b1; + +reg [PHASE_WIDTH-1 : 0] phase_inc = 'b0; +wire [WAVE_WIDTH*PARALLEL_NUM-1 : 0] cos_wave, sin_wave; + +// module instantiation +dds_par +#( + .PHASE_WIDTH (PHASE_WIDTH ), + .WAVE_WIDTH (WAVE_WIDTH ), + .PARALLEL_NUM (PARALLEL_NUM ) +) u_dds_par +( + // clock & reset + .clk (clk ), + .rst (rst ), + + .phase_inc (phase_inc ), + + .cos_wave (cos_wave ), + .sin_wave (sin_wave ) +); + +// stimulus +initial begin + rst = 1'b1; + rst_fast = 1'b1; + #102; + rst_fast = 1'b0; + #302; + rst = 1'b0; + #1000 + phase_inc = 16'd1029; +end + +always #5 clk_fast = ~clk_fast; + +if (PARALLEL_NUM > 1) begin + reg [$clog2(PARALLEL_NUM)-1 : 0] par_cnt = 'b0; + + always @(posedge clk_fast) begin + if (rst_fast) begin + par_cnt <= 'b0; + end + else begin + par_cnt <= (par_cnt == PARALLEL_NUM-1) ? 'b0 : par_cnt + 1'b1; + end + end + + assign clk = par_cnt[$clog2(PARALLEL_NUM)-1]; + + // parallel to serial + reg [WAVE_WIDTH*PARALLEL_NUM-1 : 0] cos_wave_buf = 'b0; + reg [WAVE_WIDTH*PARALLEL_NUM-1 : 0] sin_wave_buf = 'b0; + reg [WAVE_WIDTH-1 : 0] cos_wave_ser = 'b0; + reg [WAVE_WIDTH-1 : 0] sin_wave_ser = 'b0; + + always @(posedge clk_fast) begin + if (rst_fast) begin + cos_wave_buf <= 'b0; + sin_wave_buf <= 'b0; + cos_wave_ser <= 'b0; + sin_wave_ser <= 'b0; + end + else begin + if (par_cnt == PARALLEL_NUM-1) begin + cos_wave_buf <= cos_wave; + sin_wave_buf <= sin_wave; + end + else begin + cos_wave_buf <= cos_wave_buf; + sin_wave_buf <= sin_wave_buf; + end + + cos_wave_ser <= cos_wave_buf[WAVE_WIDTH*par_cnt +: WAVE_WIDTH]; + sin_wave_ser <= sin_wave_buf[WAVE_WIDTH*par_cnt +: WAVE_WIDTH]; + end + end +end +else begin + assign clk = clk_fast; + + wire [WAVE_WIDTH-1 : 0] cos_wave_ser; + wire [WAVE_WIDTH-1 : 0] sin_wave_ser; + + assign cos_wave_ser = cos_wave; + assign sin_wave_ser = sin_wave; + +end + +endmodule diff --git a/modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.srcs/sources_1/ip/coe/cos_16384_16b.coe b/modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.srcs/sources_1/ip/coe/cos_16384_16b.coe new file mode 100644 index 00000000..ab086589 --- /dev/null +++ b/modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.srcs/sources_1/ip/coe/cos_16384_16b.coe @@ -0,0 +1,16391 @@ +; XILINX CORE Generator v1.0 +; Copyright 2023 Gatsby Van +; generated by MATLAB 23.2 (R2023b) +; generated at: 14-Jan-2024 15:14:26 +0800 + +MEMORY_INITIALIZATION_RADIX = 10; +MEMORY_INITIALIZATION_VECTOR = +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, +32767, 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"resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "ADDR": [ { "physical_name": "addrb" } ], + "CLK": [ { "physical_name": "clkb" } ], + "DOUT": [ { "physical_name": "doutb" } ] + } + } + }, + "memory_maps": { + "S_1": { + "address_blocks": { + "Mem0": { + "base_address": "0", + "range": "4096", + "usage": "memory", + "access": "read-write", + "parameters": { + "OFFSET_BASE_PARAM": [ { "value": "C_BASEADDR" } ], + "OFFSET_HIGH_PARAM": [ { "value": "C_HIGHADDR" } ] + } + } + } + } + } + } + } +} \ No newline at end of file diff --git a/modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.srcs/sources_1/new/addr_to_wave.v b/modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.srcs/sources_1/new/addr_to_wave.v new file mode 100644 index 00000000..44a84d6d --- /dev/null +++ b/modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.srcs/sources_1/new/addr_to_wave.v @@ -0,0 +1,199 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/03/23 11:36:49 +// Design Name: +// Module Name: addr_to_wave +// Project Name: +// Target Devices: +// Tool Versions: +// Description: This module generates look-up-table-based sine/cosine wave, +// with 1/4 cycles of cosine wave. +// Parameter: +// PHASE_WIDTH: Bit width of input phase address. +// WAVE_WIDTH: Bit width of output sine/cosine wave. +// Total latency: 4 clock cycles, including 1 clock cycle for rom read +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// 2024/01/14 - Josh: +// 1. 修改 ROM 的宽度和深度为 16 bit，后续修改 IP 时需要同时修改本文件的 localparam。 +// 2. 输入输出改为可调位宽，但是模块内部仍按照 IP 核的位宽进行运算。 +// Additional Comments: The code below generates sine and cosine wave by +// circularly reading 1/4 cycle of cosine data from the LUT based on the phase +// address. +// +// -- -- +// --- --- -- +// -- -- --- +// - - -- +// - - - +// - - ----> - +// - - +// - - addr(cos): -->, <--, -->, <-- +// -- -- data(cos): + , - , - , + +// --- --- addr(sin): <--, -->, <--, --> +// ---- data(sin): + , + , - , - +// +// one cycle of cosine wave 1/4 cycle of cosine wave +// +////////////////////////////////////////////////////////////////////////////////// + +module addr_to_wave +#( + parameter PHASE_WIDTH = 16, + parameter WAVE_WIDTH = 16 +) +( + // clock & reset + input clk , + input rst , + + input [PHASE_WIDTH-1 : 0] phase , + + output [WAVE_WIDTH-1 : 0] cos_wave, + output [WAVE_WIDTH-1 : 0] sin_wave +); + +integer i; + +localparam ADDR_WIDTH = 16; +localparam DATA_WIDTH = 16; +localparam ROM_ADDR_WIDTH = ADDR_WIDTH - 2; // 1/4 cycle is stored +localparam ROM_DATA_WIDTH = DATA_WIDTH - 1; // only positive data +localparam ROM_MAX_INDEX = 2**ROM_ADDR_WIDTH-1; +localparam DELAY = 3; + +// mapping phase address to local format +wire [ADDR_WIDTH-1 : 0] phase_addr; + +if (PHASE_WIDTH >= ADDR_WIDTH) begin + assign phase_addr = phase[PHASE_WIDTH-1 -: ADDR_WIDTH]; +end +else begin + assign phase_addr = {phase,{(ADDR_WIDTH-PHASE_WIDTH){1'b0}}}; +end + + +// d1: buffer/stabilize input address +// d2: phase segment decision +// d3: wait for lut output data - [cos_lut_dout] & [sin_lut_dout] +reg [ADDR_WIDTH-1 : 0] phase_addr_d [1 : DELAY]; + +always @(posedge clk) begin + if (rst) begin + for (i = 1; i <= DELAY ; i = i + 1) begin + phase_addr_d[i] <= 'b0; + end + end + else begin + phase_addr_d[1] <= phase_addr; + + for (i = 2; i <= DELAY ; i = i + 1) begin + phase_addr_d[i] <= phase_addr_d[i-1]; + end + end +end + + +// Generate cosine and sine address based on current phase segment +reg [ROM_ADDR_WIDTH-1 : 0] cos_addr = 'b0; +reg [ROM_ADDR_WIDTH-1 : 0] sin_addr = 'b0; + +always @(posedge clk) begin + if (rst) begin + cos_addr <= 'b0; + sin_addr <= 'b0; + end + else begin + case (phase_addr_d[1][ADDR_WIDTH-1 -: 2]) + 2'b00, 2'b10: begin + cos_addr <= phase_addr_d[1]; + sin_addr <= ROM_MAX_INDEX - phase_addr_d[1]; + end + 2'b01, 2'b11: begin + cos_addr <= ROM_MAX_INDEX - phase_addr_d[1]; + sin_addr <= phase_addr_d[1]; + end + default: begin + cos_addr <= 'b0; + sin_addr <= 'b0; + end + endcase + end +end + +// Read 1/4 cycle of cosine data from BRAM. The Primitives Output Register and +// the the Core Output Register are enabled, to provide better delay and latency +// performance, so the output latency of both ports have reached 3 clock cycles. +wire [ROM_DATA_WIDTH-1 : 0] cos_lut_dout; +wire [ROM_DATA_WIDTH-1 : 0] sin_lut_dout; + +cos_16384_16b u_cos_16384_16b +( + .clka (clk ), // input wire clka + .addra (cos_addr ), // input wire [13 : 0] addra + .douta (cos_lut_dout ), // output wire [14 : 0] douta + .clkb (clk ), // input wire clkb + .addrb (sin_addr ), // input wire [13 : 0] addrb + .doutb (sin_lut_dout ) // output wire [14 : 0] doutb +); + +// Correct the sign of output data (above or below zero). +reg signed [DATA_WIDTH-1 : 0] cos_dout; +reg signed [DATA_WIDTH-1 : 0] sin_dout; + +always @(posedge clk) begin + if (rst) begin + cos_dout <= 'b0; + sin_dout <= 'b0; + end + else begin + case (phase_addr_d[DELAY][ADDR_WIDTH-1 -: 2]) + 2'b00: begin + cos_dout <= cos_lut_dout; + sin_dout <= sin_lut_dout; + end + 2'b01: begin + cos_dout <= -cos_lut_dout; + sin_dout <= sin_lut_dout; + end + 2'b10: begin + cos_dout <= -cos_lut_dout; + sin_dout <= -sin_lut_dout; + end + 2'b11: begin + cos_dout <= cos_lut_dout; + sin_dout <= -sin_lut_dout; + end + default: begin + cos_dout <= 'b0; + sin_dout <= 'b0; + end + endcase + end +end + +// Output data to port +/* FIXME: The truncation should be done by rounding operation, to avoid extra + * DC component. + */ +if (WAVE_WIDTH <= DATA_WIDTH) begin + assign cos_wave = cos_dout[DATA_WIDTH-1 -: WAVE_WIDTH]; + assign sin_wave = sin_dout[DATA_WIDTH-1 -: WAVE_WIDTH]; +end +else begin + assign cos_wave = {cos_dout,{(WAVE_WIDTH-DATA_WIDTH){1'b0}}}; + assign sin_wave = {sin_dout,{(WAVE_WIDTH-DATA_WIDTH){1'b0}}}; +end + +endmodule diff --git a/modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.srcs/sources_1/new/dds_par.v b/modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.srcs/sources_1/new/dds_par.v new file mode 100644 index 00000000..a74393da --- /dev/null +++ b/modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.srcs/sources_1/new/dds_par.v @@ -0,0 +1,175 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 01/14/2024 02:50:34 PM +// Design Name: +// Module Name: dds_par +// Project Name: +// Target Devices: +// Tool Versions: +// Description: This module generates parallel sine/cosine wave with continuous +// phase, which can be used as polyphase adjustable carrier wave. +// Parameter: +// PHASE_WIDTH: Bit width of input phase address. +// WAVE_WIDTH: Bit width of output sine/cosine wave. +// PARALLEL_NUM: Number of parallel paths. The optimal wave is generated when +// this number is power of 2, however the module should work fine with any +// number of parallel paths. +// Data format: +// cos_wave/sin_wave: Suppose the samples are s = [s0, s1, ..., sN], then +// cos_wave/sin_wave = {sN, ..., s1, s0} +// Total latency: [PARALLEL_NUM+6] clock cycles, including 4 clock cycles for +// addr_to_wave +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module dds_par +#( + parameter PHASE_WIDTH = 16, + parameter WAVE_WIDTH = 16, + parameter PARALLEL_NUM = 8 +) +( + input clk, + input rst, + + input [PHASE_WIDTH-1 : 0] phase_inc, + + output [WAVE_WIDTH*PARALLEL_NUM-1 : 0] cos_wave, + output [WAVE_WIDTH*PARALLEL_NUM-1 : 0] sin_wave +); + +localparam PARALLEL_NUM_LOG = $clog2(PARALLEL_NUM); +localparam PHASE_CONFIG_DELAY = PARALLEL_NUM + 1; + +genvar m; +integer i; + +// buffer +reg [PHASE_WIDTH-1 : 0] phase_inc_d [1:2]; + +always @(posedge clk) begin + if (rst) begin + for (i = 1; i <= 2 ; i = i + 1) begin + phase_inc_d[i] <= 'b0; + end + end + else begin + phase_inc_d[1] <= phase_inc; + phase_inc_d[2] <= phase_inc_d[1]; + end +end + +// phase increment change identification +reg phase_config_flag [0:PHASE_CONFIG_DELAY-1]; + +always @(posedge clk) begin + if (rst) begin + for (i = 0; i < PHASE_CONFIG_DELAY; i = i + 1) begin + phase_config_flag[i] <= 'b0; + end + end + else begin + phase_config_flag[0] <= (phase_inc_d[2] != phase_inc_d[1]) ? 1'b1 : 'b0; + for (i = 1; i < PHASE_CONFIG_DELAY; i = i + 1) begin + phase_config_flag[i] <= phase_config_flag[i-1]; + end + end +end + +// offset counter +reg [$clog2(PARALLEL_NUM)-1 : 0] phase_config_cnt = 'b0; + +always @(posedge clk) begin + if (rst) begin + phase_config_cnt <= 'b0; + end + else if (phase_config_flag[0]) begin + phase_config_cnt <= phase_config_cnt + 1'b1; + end + else begin + phase_config_cnt <= (phase_config_cnt == 'b0) ? 'b0 : phase_config_cnt + 1'b1; + end +end + +// phase offset generation based on new phase increment +reg [PHASE_WIDTH-1 : 0] phase_off [0 : PARALLEL_NUM-1]; + +always @(posedge clk) begin + if (rst) begin + for (i = 0; i < PARALLEL_NUM; i = i + 1) begin + phase_off[i] <= 'b0; + end + end + else if (phase_config_cnt != 'b0) begin + phase_off[phase_config_cnt] <= phase_off[phase_config_cnt-1] + phase_inc_d[2]; + end +end + +// phase generation +reg [PHASE_WIDTH-1 : 0] phase [0 : PARALLEL_NUM-1]; + +always @(posedge clk) begin + if (rst) begin + for (i = 0; i < PARALLEL_NUM; i = i + 1) begin + phase[i] <= 'b0; + end + end + else if (phase_config_flag[PHASE_CONFIG_DELAY-1]) begin + for (i = 0; i < PARALLEL_NUM; i = i + 1) begin + phase[i] <= phase_off[i]; + end + end + else begin + for (i = 0; i < PARALLEL_NUM; i = i + 1) begin + phase[i] <= phase[i] + (phase_inc << PARALLEL_NUM_LOG); + end + end +end + +// phase to wave +wire [WAVE_WIDTH-1 : 0] cos_wave_par [0 : PARALLEL_NUM-1]; +wire [WAVE_WIDTH-1 : 0] sin_wave_par [0 : PARALLEL_NUM-1]; + +generate +for (m = 0; m < PARALLEL_NUM; m = m + 1) begin: phase_to_wave + + addr_to_wave + #( + .PHASE_WIDTH (PHASE_WIDTH), + .WAVE_WIDTH (WAVE_WIDTH ) + ) u_addr_to_wave + ( + // clock & reset + .clk (clk ), + .rst (rst ), + + .phase (phase[m] ), + + .cos_wave (cos_wave_par[m]), + .sin_wave (sin_wave_par[m]) + ); + + // output to port + assign cos_wave[WAVE_WIDTH*m +: WAVE_WIDTH] = cos_wave_par[m]; + assign sin_wave[WAVE_WIDTH*m +: WAVE_WIDTH] = sin_wave_par[m]; + +end + +endgenerate + +endmodule diff --git a/modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.xpr b/modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.xpr new file mode 100644 index 00000000..1d6956bd --- /dev/null +++ b/modules/xczu48dr-fsvg1517-2-i/dds_par/dds_par.xpr @@ -0,0 +1,292 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + +