add var_cal module for xc7k410tffg900-2
This commit is contained in:
+212
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{
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"schema": "xilinx.com:schema:json_instance:1.0",
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"ip_inst": {
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"xci_name": "cmpy_18x18_mult",
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"component_reference": "xilinx.com:ip:cmpy:6.0",
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"ip_revision": "22",
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"gen_directory": "../../../../var_cal.gen/sources_1/ip/cmpy_18x18_mult",
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"parameters": {
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"component_parameters": {
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"Component_Name": [ { "value": "cmpy_18x18_mult", "resolve_type": "user", "usage": "all" } ],
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"APortWidth": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"HasATLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"HasATUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"ATUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"BPortWidth": [ { "value": "18", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"HasBTLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"HasBTUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"BTUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"MultType": [ { "value": "Use_Mults", "resolve_type": "user", "usage": "all" } ],
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"OptimizeGoal": [ { "value": "Resources", "resolve_type": "user", "usage": "all" } ],
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"FlowControl": [ { "value": "NonBlocking", "resolve_type": "user", "usage": "all" } ],
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"RoundMode": [ { "value": "Truncate", "resolve_type": "user", "usage": "all" } ],
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"OutputWidth": [ { "value": "37", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"HasCTRLTLAST": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"HasCTRLTUSER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"CTRLTUSERWidth": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"OutTLASTBehv": [ { "value": "Null", "resolve_type": "user", "usage": "all" } ],
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"LatencyConfig": [ { "value": "Automatic", "resolve_type": "user", "usage": "all" } ],
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"MinimumLatency": [ { "value": "6", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
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"ARESETN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
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},
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"model_parameters": {
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"C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_XDEVICEFAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ],
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"C_XDEVICE": [ { "value": "xc7k410t", "resolve_type": "generated", "usage": "all" } ],
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"C_A_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_B_WIDTH": [ { "value": "18", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_OUT_WIDTH": [ { "value": "37", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_LATENCY": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_MULT_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_OPTIMIZE_GOAL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"HAS_NEGATE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"SINGLE_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"ROUND": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"USE_DSP_CASCADES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_THROTTLE_SCHEME": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_HAS_ARESETN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_HAS_S_AXIS_A_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_HAS_S_AXIS_A_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_HAS_S_AXIS_B_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_HAS_S_AXIS_B_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_HAS_S_AXIS_CTRL_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_HAS_S_AXIS_CTRL_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_TLAST_RESOLUTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_S_AXIS_A_TDATA_WIDTH": [ { "value": "48", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_S_AXIS_A_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_S_AXIS_B_TDATA_WIDTH": [ { "value": "48", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_S_AXIS_B_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_S_AXIS_CTRL_TDATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_S_AXIS_CTRL_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_M_AXIS_DOUT_TDATA_WIDTH": [ { "value": "80", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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"C_M_AXIS_DOUT_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ]
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},
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"project_parameters": {
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"ARCHITECTURE": [ { "value": "kintex7" } ],
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"BASE_BOARD_PART": [ { "value": "" } ],
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"BOARD_CONNECTIONS": [ { "value": "" } ],
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"DEVICE": [ { "value": "xc7k410t" } ],
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"PACKAGE": [ { "value": "ffg900" } ],
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"PREFHDL": [ { "value": "VERILOG" } ],
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"SILICON_REVISION": [ { "value": "" } ],
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"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
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"SPEEDGRADE": [ { "value": "-2" } ],
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"STATIC_POWER": [ { "value": "" } ],
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"TEMPERATURE_GRADE": [ { "value": "" } ]
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},
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"runtime_parameters": {
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"IPCONTEXT": [ { "value": "IP_Flow" } ],
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"IPREVISION": [ { "value": "22" } ],
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"MANAGED": [ { "value": "TRUE" } ],
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"OUTPUTDIR": [ { "value": "../../../../var_cal.gen/sources_1/ip/cmpy_18x18_mult" } ],
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"SELECTEDSIMMODEL": [ { "value": "" } ],
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"SHAREDDIR": [ { "value": "." } ],
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"SWVERSION": [ { "value": "2023.2.1" } ],
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"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
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}
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},
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"boundary": {
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"ports": {
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"aclk": [ { "direction": "in", "driver_value": "0x0" } ],
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"s_axis_a_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
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"s_axis_a_tdata": [ { "direction": "in", "size_left": "47", "size_right": "0", "driver_value": "0" } ],
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"s_axis_b_tvalid": [ { "direction": "in", "driver_value": "0x0" } ],
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"s_axis_b_tdata": [ { "direction": "in", "size_left": "47", "size_right": "0", "driver_value": "0" } ],
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"m_axis_dout_tvalid": [ { "direction": "out", "driver_value": "0x0" } ],
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"m_axis_dout_tdata": [ { "direction": "out", "size_left": "79", "size_right": "0", "driver_value": "0" } ]
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},
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"interfaces": {
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"M_AXIS_DOUT": {
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"vlnv": "xilinx.com:interface:axis:1.0",
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"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
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"mode": "master",
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"parameters": {
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"TDATA_NUM_BYTES": [ { "value": "10", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
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"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
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},
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"port_maps": {
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"TDATA": [ { "physical_name": "m_axis_dout_tdata" } ],
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"TVALID": [ { "physical_name": "m_axis_dout_tvalid" } ]
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}
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},
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"aclk_intf": {
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"vlnv": "xilinx.com:signal:clock:1.0",
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"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
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"mode": "slave",
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"parameters": {
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"ASSOCIATED_BUSIF": [ { "value": "S_AXIS_CTRL:S_AXIS_B:S_AXIS_A:M_AXIS_DOUT", "value_src": "constant", "usage": "all" } ],
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"ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "usage": "all" } ],
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"ASSOCIATED_CLKEN": [ { "value": "aclken", "value_src": "constant", "usage": "all" } ],
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"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
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"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
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"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
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},
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"port_maps": {
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"CLK": [ { "physical_name": "aclk" } ]
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}
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},
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"aresetn_intf": {
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"vlnv": "xilinx.com:signal:reset:1.0",
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"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
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"mode": "slave",
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"parameters": {
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"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
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"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
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}
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},
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"aclken_intf": {
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"vlnv": "xilinx.com:signal:clockenable:1.0",
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"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
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"mode": "slave",
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"parameters": {
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"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
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}
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},
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"S_AXIS_A": {
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"vlnv": "xilinx.com:interface:axis:1.0",
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"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
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"mode": "slave",
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"parameters": {
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"TDATA_NUM_BYTES": [ { "value": "6", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
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"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
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"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
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"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
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"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
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},
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"port_maps": {
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"TDATA": [ { "physical_name": "s_axis_a_tdata" } ],
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"TVALID": [ { "physical_name": "s_axis_a_tvalid" } ]
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}
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},
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"S_AXIS_B": {
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"vlnv": "xilinx.com:interface:axis:1.0",
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"abstraction_type": "xilinx.com:interface:axis_rtl:1.0",
|
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"mode": "slave",
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||||
"parameters": {
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||||
"TDATA_NUM_BYTES": [ { "value": "6", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TDEST_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"TUSER_WIDTH": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TREADY": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TSTRB": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TKEEP": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"HAS_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
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},
|
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"port_maps": {
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"TDATA": [ { "physical_name": "s_axis_b_tdata" } ],
|
||||
"TVALID": [ { "physical_name": "s_axis_b_tvalid" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
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||||
}
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||||
}
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@@ -0,0 +1,258 @@
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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// _ _ ____
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// | | ___ ___| |__ / ___| __ _ ___
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// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \
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// | |_| | (_) \__ \ | | | | |_| | (_| | (_) |
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// \___/ \___/|___/_| |_| \____|\__,_|\___/
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//
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// Create Date: 06/11/2023 02:41:47 PM
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// Design Name:
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// Module Name: var_cal
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// Project Name:
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// Target Devices:
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// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// 20230730-1427 - 修改输入位宽小于乘法器位宽时的处理，由补零变为符号位扩展；
|
||||
// 修改；修改累加和输出截位方式，依托原始数据位宽进行处理。
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module var_cal
|
||||
#(
|
||||
parameter ACCUM_NUM = 16384,
|
||||
parameter DATA_I_WIDTH = 30,
|
||||
parameter DATA_O_WIDTH = 32,
|
||||
parameter CMPY_I_WIDTH = 18
|
||||
)
|
||||
(
|
||||
input clk ,
|
||||
input rst ,
|
||||
|
||||
input cal_start ,
|
||||
input cal_auto_en ,
|
||||
output cal_busy ,
|
||||
|
||||
input din_valid ,
|
||||
input [DATA_I_WIDTH-1 : 0] din_real ,
|
||||
input [DATA_I_WIDTH-1 : 0] din_imag ,
|
||||
|
||||
output var_valid ,
|
||||
output [DATA_O_WIDTH-1 : 0] var
|
||||
);
|
||||
|
||||
integer i;
|
||||
|
||||
localparam CMPY_P_WIDTH = 2*CMPY_I_WIDTH+1;
|
||||
localparam AXIS_CMPY_I_WIDTH = 8*((CMPY_I_WIDTH-1)/8+1) ; // axis data width of input real/image data
|
||||
localparam AXIS_CMPY_P_WIDTH = 8*((CMPY_P_WIDTH-1)/8+1); // axis data width of cmpy output real/image data
|
||||
localparam CMPY_P_VALID_WIDTH = (DATA_I_WIDTH > CMPY_I_WIDTH) ? 2*CMPY_I_WIDTH : 2*DATA_I_WIDTH;
|
||||
|
||||
|
||||
localparam ACCUM_WIDTH = CMPY_P_VALID_WIDTH + $clog2(ACCUM_NUM);
|
||||
|
||||
// status control
|
||||
reg cal_start_auto = 'b0;
|
||||
reg cal_start_d1 = 'b0;
|
||||
reg cal_start_d2 = 'b0;
|
||||
reg cal_busy_buf = 'b0;
|
||||
reg [$clog2(ACCUM_NUM)-1 : 0] cnt_accum = 'b0;
|
||||
reg last_data = 'b0;
|
||||
reg [6:0] last_data_d = 'b0; // 1 for register input, 6 for cmpy, 1 for register output
|
||||
|
||||
assign cal_busy = cal_busy_buf;
|
||||
assign var_valid = last_data_d[6];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cal_start_auto <= 'b0;
|
||||
end
|
||||
else begin
|
||||
if (cal_auto_en) begin
|
||||
if (~cal_busy_buf) begin
|
||||
cal_start_auto <= ~cal_start_auto;
|
||||
end
|
||||
else begin
|
||||
cal_start_auto <= cal_start_auto;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
cal_start_auto <= 'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
cal_start_d1 <= cal_auto_en ? cal_start_auto : cal_start;
|
||||
cal_start_d2 <= cal_start_d1;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cal_busy_buf <= 'b0;
|
||||
end
|
||||
else begin
|
||||
if ((cal_start_d1 ^ cal_start_d2) && din_valid) begin
|
||||
cal_busy_buf <= 1'b1;
|
||||
end
|
||||
else if (cnt_accum == ACCUM_NUM-1) begin
|
||||
cal_busy_buf <= 'b0;
|
||||
end
|
||||
else begin
|
||||
cal_busy_buf <= cal_busy_buf;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cnt_accum <= 'b0;
|
||||
end
|
||||
else begin
|
||||
cnt_accum <= cal_busy ? (cnt_accum + 1'b1) : 'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
last_data <= 'b0;
|
||||
end
|
||||
else begin
|
||||
last_data <= (cnt_accum == ACCUM_NUM-1) ? 1'b1 : 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
last_data_d[6:0] <= 'b0;
|
||||
end
|
||||
else begin
|
||||
last_data_d[6:0] <= {last_data_d[5:0],last_data};
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// cmpy
|
||||
reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_a_real = 'b0;
|
||||
reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_a_imag = 'b0;
|
||||
reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_b_real = 'b0;
|
||||
reg [AXIS_CMPY_I_WIDTH-1 : 0] cmpy_b_imag = 'b0;
|
||||
wire [AXIS_CMPY_P_WIDTH-1 : 0] cmpy_p_raw_real;
|
||||
wire [AXIS_CMPY_P_WIDTH-1 : 0] cmpy_p_raw_imag;
|
||||
wire [CMPY_P_VALID_WIDTH-1 : 0] cmpy_p_real;
|
||||
wire [CMPY_P_VALID_WIDTH-1 : 0] cmpy_p_imag;
|
||||
|
||||
if (CMPY_I_WIDTH > DATA_I_WIDTH) begin
|
||||
// sign-bit extension to fit cmpy input data width
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cmpy_a_real <= 'b0;
|
||||
cmpy_a_imag <= 'b0;
|
||||
cmpy_b_real <= 'b0;
|
||||
cmpy_b_imag <= 'b0;
|
||||
end
|
||||
else begin
|
||||
cmpy_a_real <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real};
|
||||
cmpy_a_imag <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag};
|
||||
cmpy_b_real <= {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real};
|
||||
cmpy_b_imag <= (din_imag == {1'b1,{(DATA_I_WIDTH-1){1'b0}}}) ? {{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH+1){1'b0}},{(DATA_I_WIDTH-1){1'b1}}} : -{{(AXIS_CMPY_I_WIDTH-DATA_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag};
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin
|
||||
// truncate msb
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
cmpy_a_real <= 'b0;
|
||||
cmpy_a_imag <= 'b0;
|
||||
cmpy_b_real <= 'b0;
|
||||
cmpy_b_imag <= 'b0;
|
||||
end
|
||||
else begin
|
||||
cmpy_a_real <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
|
||||
cmpy_a_imag <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
|
||||
cmpy_b_real <= {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_real[DATA_I_WIDTH-1]}},din_real[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
|
||||
cmpy_b_imag <= (din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH] == {1'b1,{(CMPY_I_WIDTH-1){1'b0}}}) ? {{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH+1){1'b0}},{(CMPY_I_WIDTH-1){1'b1}}} : -{{(AXIS_CMPY_I_WIDTH-CMPY_I_WIDTH){din_imag[DATA_I_WIDTH-1]}},din_imag[DATA_I_WIDTH-1 -: CMPY_I_WIDTH]};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// truncate valid bits
|
||||
assign cmpy_p_real = cmpy_p_raw_real[0 +: CMPY_P_VALID_WIDTH];
|
||||
assign cmpy_p_imag = cmpy_p_raw_imag[0 +: CMPY_P_VALID_WIDTH];
|
||||
|
||||
|
||||
wire [2*AXIS_CMPY_I_WIDTH-1:0] cmpy_a;
|
||||
wire [2*AXIS_CMPY_I_WIDTH-1:0] cmpy_b;
|
||||
wire [2*AXIS_CMPY_P_WIDTH-1:0] cmpy_p;
|
||||
wire cmpy_p_vld;
|
||||
|
||||
assign cmpy_a = {cmpy_a_imag,cmpy_a_real};
|
||||
assign cmpy_b = {cmpy_b_imag,cmpy_b_real};
|
||||
assign {cmpy_p_raw_imag,cmpy_p_raw_real} = cmpy_p;
|
||||
|
||||
cmpy_18x18_mult u_cmpy_18x18
|
||||
(
|
||||
.aclk (clk ), // input wire aclk
|
||||
.s_axis_a_tvalid (cal_busy ), // input wire s_axis_a_tvalid
|
||||
.s_axis_a_tdata (cmpy_a ), // input wire [31 : 0] s_axis_a_tdata
|
||||
.s_axis_b_tvalid (cal_busy ), // input wire s_axis_b_tvalid
|
||||
.s_axis_b_tdata (cmpy_b ), // input wire [31 : 0] s_axis_b_tdata
|
||||
.m_axis_dout_tvalid (cmpy_p_vld ), // output wire m_axis_dout_tvalid
|
||||
.m_axis_dout_tdata (cmpy_p ) // output wire [63 : 0] m_axis_dout_tdata
|
||||
);
|
||||
|
||||
|
||||
// accumulation
|
||||
reg [ACCUM_WIDTH-1 : 0] accum = 'b0;
|
||||
reg [DATA_O_WIDTH-1 : 0] var_buf = 'b0;
|
||||
|
||||
assign var = var_buf;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
accum <= 'b0;
|
||||
end
|
||||
else begin
|
||||
if (cmpy_p_vld) begin
|
||||
accum <= accum + cmpy_p_real;
|
||||
end
|
||||
else begin
|
||||
accum <= 'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
if (DATA_O_WIDTH > ACCUM_WIDTH) begin
|
||||
// sign-bit extension to fit output data width
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
var_buf <= 'b0;
|
||||
end
|
||||
else if (last_data_d[5]) begin
|
||||
var_buf <= {{(DATA_O_WIDTH-ACCUM_WIDTH){accum[ACCUM_WIDTH-1]}},accum};
|
||||
end
|
||||
end
|
||||
end
|
||||
else begin
|
||||
// truncate msb
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
var_buf <= 'b0;
|
||||
end
|
||||
else if (last_data_d[5]) begin
|
||||
var_buf <= accum[ACCUM_WIDTH-1 -: DATA_O_WIDTH];
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user