From 5defedcc88667551e84797533e72824b9f499430 Mon Sep 17 00:00:00 2001 From: Josh Gao Date: Tue, 30 Jan 2024 10:34:36 +0800 Subject: [PATCH] add ad9361_mapping module for xc7k410tffg900-2 --- .../sources_1/ip/ad9361_fifo/ad9361_fifo.xci | 479 ++++++++++++++++++ .../sources_1/new/ad9361_rx_map_cmos_dual.v | 196 +++++++ .../sources_1/new/ad9361_rx_map_cmos_single.v | 124 +++++ .../sources_1/new/ad9361_rx_map_lvds_dual.v | 277 ++++++++++ .../sources_1/new/ad9361_tx_map_cmos_dual.v | 183 +++++++ .../sources_1/new/ad9361_tx_map_cmos_single.v | 119 +++++ .../sources_1/new/ad9361_tx_map_lvds_dual.v | 246 +++++++++ .../ad9361_mapping/ad9361_mapping.xpr | 303 +++++++++++ 8 files changed, 1927 insertions(+) create mode 100644 modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/ip/ad9361_fifo/ad9361_fifo.xci create mode 100644 modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_dual.v create mode 100644 modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_single.v create mode 100644 modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_lvds_dual.v create mode 100644 modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_dual.v create mode 100644 modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_single.v create mode 100644 modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_lvds_dual.v create mode 100644 modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.xpr diff --git a/modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/ip/ad9361_fifo/ad9361_fifo.xci b/modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/ip/ad9361_fifo/ad9361_fifo.xci new file mode 100644 index 00000000..2a0a1d29 --- /dev/null +++ b/modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/ip/ad9361_fifo/ad9361_fifo.xci @@ -0,0 +1,479 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "ad9361_fifo", + "component_reference": "xilinx.com:ip:fifo_generator:13.2", + "ip_revision": "9", + "gen_directory": "../../../../ad9361_mapping.gen/sources_1/ip/ad9361_fifo", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "ad9361_fifo", "resolve_type": "user", "usage": "all" } ], + "Fifo_Implementation": [ { "value": "Independent_Clocks_Distributed_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "synchronization_stages": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "synchronization_stages_axi": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ], + "INTERFACE_TYPE": [ { "value": "Native", "resolve_type": "user", "usage": "all" } ], + "Performance_Options": [ { "value": "Standard_FIFO", "resolve_type": "user", "usage": "all" } ], + "asymmetric_port_width": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Input_Data_Width": [ { "value": "12", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Input_Depth": [ { "value": "16", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "Output_Data_Width": [ { "value": "12", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Output_Depth": [ { "value": "16", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "Enable_ECC": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Use_Embedded_Registers": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Reset_Pin": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Enable_Reset_Synchronization": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Reset_Type": [ { "value": "Asynchronous_Reset", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Full_Flags_Reset_Value": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], + "Use_Dout_Reset": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Dout_Reset_Value": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "dynamic_power_saving": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Almost_Full_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Almost_Empty_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Valid_Flag": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Valid_Sense": [ { "value": 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"resolve_type": "user", "format": "bool", "usage": "all" } ], + "Read_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "Write_Clock_Frequency": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "Programmable_Full_Type": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "usage": "all" } ], + "Full_Threshold_Assert_Value": [ { "value": "13", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "Full_Threshold_Negate_Value": [ { "value": "12", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "Programmable_Empty_Type": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "usage": "all" } ], + "Empty_Threshold_Assert_Value": [ { "value": "2", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "Empty_Threshold_Negate_Value": [ { "value": "3", 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"resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Inject_Sbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Inject_Dbit_Error_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Input_Depth_wach": [ { "value": "16", "resolve_type": "user", "usage": "all" } ], + "Enable_Data_Counts_wach": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Programmable_Full_Type_wach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Full_Threshold_Assert_Value_wach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "Programmable_Empty_Type_wach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ], + 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"all" } ], + "Programmable_Full_Type_rach": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Full_Threshold_Assert_Value_rach": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "Programmable_Empty_Type_rach": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Empty_Threshold_Assert_Value_rach": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "rdch_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ], + "FIFO_Implementation_rdch": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ], + "FIFO_Application_Type_rdch": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Enable_ECC_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Inject_Sbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Inject_Dbit_Error_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Input_Depth_rdch": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ], + "Enable_Data_Counts_rdch": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Programmable_Full_Type_rdch": [ { "value": "No_Programmable_Full_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Full_Threshold_Assert_Value_rdch": [ { "value": "1023", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "Programmable_Empty_Type_rdch": [ { "value": "No_Programmable_Empty_Threshold", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Empty_Threshold_Assert_Value_rdch": [ { "value": "1022", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "axis_type": [ { "value": "FIFO", "resolve_type": "user", "usage": "all" } ], + "FIFO_Implementation_axis": [ { "value": "Common_Clock_Block_RAM", "resolve_type": "user", "usage": "all" } ], + "FIFO_Application_Type_axis": [ { "value": "Data_FIFO", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Enable_ECC_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Inject_Sbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Inject_Dbit_Error_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "Input_Depth_axis": [ { "value": "1024", "resolve_type": "user", "usage": "all" } ], + "Enable_Data_Counts_axis": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + 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| | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/07/01 17:37:27 +// Last Modified Date: 2023/03/06 11:26 +// Design Name: +// Module Name: ad9361_rx_map_cmos_dual +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ad9361_rx_map_cmos_dual +( + input clk_2x_in , + input clk_in_rst , + + input rx_data_clk , // sync to output data + input rx_data_clk_rst , + + input rx_fifo_rst , // async fifo reset + + input rx_frame , + input [11:0] rx_data , + + output [11:0] rx_ch1_i , + output [11:0] rx_ch1_q , + output [11:0] rx_ch2_i , + output [11:0] rx_ch2_q +); + +genvar m; + +// rx data +wire [11:0] rx_data_i, rx_data_q; + +generate +for (m=0; m<12; m=m+1) begin : rx_data_iddr + +IDDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT_Q1 (1'b0 ), + .INIT_Q2 (1'b0 ), + .SRTYPE ("ASYNC" ) +) i_rx_data_iddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_2x_in ), + .D (rx_data[m] ), + .Q1 (rx_data_q[m] ), + .Q2 (rx_data_i[m] ) +); + +end +endgenerate + +// rx frame +wire rx_frame_i; +wire rx_frame_q; + +IDDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT_Q1 (1'b0 ), + .INIT_Q2 (1'b0 ), + .SRTYPE ("ASYNC" ) +) i_rx_frame_iddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_2x_in ), + .D (rx_frame ), + .Q1 (rx_frame_q ), + .Q2 (rx_frame_i ) +); + +// divide rx_data to dual channel +reg [11:0] rx1_data_i = 'b0; +reg [11:0] rx1_data_q = 'b0; +reg [11:0] rx2_data_i = 'b0; +reg [11:0] rx2_data_q = 'b0; + +wire rx_fifo_wr_en; +reg rx_fifo_rd_en = 'b0; + +wire rx_fifo_empty_1; +wire rx_fifo_empty_2; +wire rx_fifo_empty_3; +wire rx_fifo_empty_4; + +assign rx_fifo_wr_en = rx_frame_i; // align data & write enable + +always @ (posedge clk_2x_in) begin + if (clk_in_rst) begin + rx1_data_i <= 'b0; + rx2_data_i <= 'b0; + end + else if(rx_frame_i) begin + rx1_data_i <= rx_data_i; + end + else begin + rx2_data_i <= rx_data_i; + end +end + +always @ (posedge clk_2x_in) begin + if (clk_in_rst) begin + rx1_data_q <= 'b0; + rx2_data_q <= 'b0; + end + else if(rx_frame_q) begin + rx1_data_q <= rx_data_q; + end + else begin + rx2_data_q <= rx_data_q; + end +end + +always @(posedge rx_data_clk) begin + if (rx_data_clk_rst) begin + rx_fifo_rd_en <= 'b0; + end + else begin + rx_fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4}; + end +end + +ad9361_fifo u_rx_fifo_ch1_i +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_2x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx1_data_i ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_ch1_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_1) // output wire empty +); + +ad9361_fifo u_rx_fifo_ch1_q +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_2x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx1_data_q ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_ch1_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_2) // output wire empty +); + +ad9361_fifo u_rx_fifo_ch2_i +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_2x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx2_data_i ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_ch2_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_3) // output wire empty +); + +ad9361_fifo u_rx_fifo_ch2_q +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_2x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx2_data_q ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_ch2_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_4) // output wire empty +); + +endmodule diff --git a/modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_single.v b/modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_single.v new file mode 100644 index 00000000..c5bb387a --- /dev/null +++ b/modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_single.v @@ -0,0 +1,124 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/07/01 17:37:27 +// Last Modified Date: 2023/03/03 13:01 +// Design Name: +// Module Name: ad9361_rx_map_cmos_single +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ad9361_rx_map_cmos_single +( + input clk_in , + input clk_in_rst , + + input rx_data_clk , + input rx_data_clk_rst , + + input rx_fifo_rst , + + input rx_frame , + input [11:0] rx_data , + + output [11:0] rx_data_i , + output [11:0] rx_data_q +); + +genvar m; + +// rx data +wire [11:0] rx_raw_i, rx_raw_q; + +generate +for (m=0; m<12; m=m+1) begin : rx_data_iddr + +IDDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT_Q1 (1'b0 ), + .INIT_Q2 (1'b0 ), + .SRTYPE ("ASYNC" ) +) i_rx_data_iddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_in ), + .D (rx_data[m] ), + .Q1 (rx_raw_q[m] ), + .Q2 (rx_raw_i[m] ) +); + +end +endgenerate + + +// divide rx_data to dual channel +reg rx_fifo_wr_en = 1'b0; +reg rx_fifo_rd_en = 'b0; + +wire rx_fifo_empty_1; +wire rx_fifo_empty_2; + +always @(posedge clk_in) begin + if (clk_in_rst) begin + rx_fifo_wr_en <= 1'b0; + end + else begin + rx_fifo_wr_en <= 1'b1; + end +end + +always @(posedge rx_data_clk) begin + if (rx_data_clk_rst) begin + rx_fifo_rd_en <= 'b0; + end + else begin + rx_fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2}; + end +end + +ad9361_fifo u_rx_fifo_i +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx_raw_i ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_data_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_1) // output wire empty +); + +ad9361_fifo u_rx_fifo_q +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx_raw_q ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_data_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_2) // output wire empty +); + +endmodule diff --git a/modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_lvds_dual.v b/modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_lvds_dual.v new file mode 100644 index 00000000..026330d0 --- /dev/null +++ b/modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_lvds_dual.v @@ -0,0 +1,277 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/07/01 17:37:27 +// Last Modified Date: 2023/03/06 10:54 +// Design Name: +// Module Name: ad9361_rx_mapping_dual +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ad9361_rx_map_lvds_dual +( + input clk_4x_in , // sync to input data + input clk_in_rst , + + input rx_data_clk , // sync to output data + input rx_data_clk_rst , + + input rx_fifo_rst , // async fifo reset + + input rx_frame_p , + input rx_frame_n , + input [ 5:0] rx_data_p , // data from ad9361 p1 port + input [ 5:0] rx_data_n , + + output [11:0] rx_ch1_i , + output [11:0] rx_ch1_q , + output [11:0] rx_ch2_i , + output [11:0] rx_ch2_q +); + +genvar m; + +// rx data +wire [5:0] rx_data; +wire [5:0] rx_data_i, rx_data_q; + +generate +for (m=0; m<6; m=m+1) begin : rx_data_iddr + +IBUFDS #( + .DIFF_TERM ("TRUE" ) +) u_ibufds_rx_data +( + .I (rx_data_p[m] ), + .IB (rx_data_n[m] ), + .O (rx_data[m] ) +); + +IDDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT_Q1 (1'b0 ), + .INIT_Q2 (1'b0 ), + .SRTYPE ("ASYNC" ) +) u_rx_data_iddr ( + .CE (1'b1 ), // clock enable + .R (1'b0 ), // iddr reset + .S (1'b0 ), // iddr set + .C (clk_4x_in ), // iddr clock + .D (rx_data[m] ), // ddr data + .Q1 (rx_data_q[m] ), // sdr data at rising edge + .Q2 (rx_data_i[m] ) // sdr data at falling edge +); + +end +endgenerate + +// rx frame +wire rx_frame; +wire rx_frame_i; +wire rx_frame_q; + +IBUFDS #( + .DIFF_TERM ("TRUE" ) +) u_ibufds_rx_frame +( + .I (rx_frame_p ), + .IB (rx_frame_n ), + .O (rx_frame ) +); + +IDDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT_Q1 (1'b0 ), + .INIT_Q2 (1'b0 ), + .SRTYPE ("ASYNC" ) +) u_rx_frame_iddr ( + .CE (1'b1 ), // clock enable + .R (1'b0 ), // iddr reset + .S (1'b0 ), // iddr set + .C (clk_4x_in ), // iddr clock + .D (rx_frame ), // ddr data + .Q1 (rx_frame_q ), // sdr data at rising edge + .Q2 (rx_frame_i ) // sdr data at falling edge +); + +// unpack rx frame & data +reg rx_frame_i_d1 = 'b0; +reg [ 5:0] rx_data_i_d1 = 'b0; +reg [ 5:0] rx_data_q_d1 = 'b0; +reg rx_flag = 'b0; // rx frame rising edge indicator +reg [ 1:0] rx_cnt = 'b0; // unpack stage counter + +always @(posedge clk_4x_in) begin + // wait for [rx_flag] + rx_frame_i_d1 <= rx_frame_i; + rx_data_i_d1 <= rx_data_i; + rx_data_q_d1 <= rx_data_q; +end + +always @(posedge clk_4x_in) begin + if (clk_in_rst) begin + rx_flag <= 'b0; + end + else if (~rx_frame_i_d1 & rx_frame_i) begin + // assert when rising edge of rx frame is detected + rx_flag <= 'b1; + end + else begin + rx_flag <= rx_flag; + end +end + +always @(posedge clk_4x_in) begin + if (clk_in_rst) begin + rx_cnt <= 'b0; + end + else begin + rx_cnt <= (rx_flag) ? rx_cnt + 1'b1 : rx_cnt; + end +end + +reg [11:0] rx1_data_i = 'b0; +reg [11:0] rx1_data_q = 'b0; +reg [11:0] rx2_data_i = 'b0; +reg [11:0] rx2_data_q = 'b0; + +always @(posedge clk_4x_in) begin + if (clk_in_rst) begin + rx1_data_i <= 'b0; + rx1_data_q <= 'b0; + rx2_data_i <= 'b0; + rx2_data_q <= 'b0; + end + else begin + case (rx_cnt) + 3'd0: begin + // 1st clock cycle: upper 6-bit of rx ch1 inphase/quadrature data + rx1_data_i[11:6] <= rx_data_i_d1; + rx1_data_q[11:6] <= rx_data_q_d1; + end + 3'd1: begin + // 2nd clock cycle: lower 6-bit of rx ch1 inphase/quadrature data + rx1_data_i[ 5:0] <= rx_data_i_d1; + rx1_data_q[ 5:0] <= rx_data_q_d1; + end + 3'd2: begin + // 3rd clock cycle: upper 6-bit of rx ch2 inphase/quadrature data + rx2_data_i[11:6] <= rx_data_i_d1; + rx2_data_q[11:6] <= rx_data_q_d1; + end + 3'd3: begin + // 4th clock cycle: lower 6-bit of rx ch2 inphase/quadrature data + rx2_data_i[ 5:0] <= rx_data_i_d1; + rx2_data_q[ 5:0] <= rx_data_q_d1; + end + default: begin + rx1_data_i <= 'b0; + rx1_data_q <= 'b0; + rx2_data_i <= 'b0; + rx2_data_q <= 'b0; + end + endcase + end +end + +// write fifo when rx1/2_data_i/q are all prepared with 192MHz clock +// read fifo at every clock cycle with 48MHz clock +reg fifo_wr_en = 'b0; +reg fifo_rd_en = 'b0; +wire rx_fifo_empty_1; +wire rx_fifo_empty_2; +wire rx_fifo_empty_3; +wire rx_fifo_empty_4; + +always @(posedge clk_4x_in) begin + if (clk_in_rst) begin + fifo_wr_en <= 'b0; + end + else if (rx_cnt == 2'd3) begin + fifo_wr_en <= 1'b1; + end + else begin + fifo_wr_en <= 'b0; + end +end + +always @(posedge rx_data_clk) begin + if (rx_data_clk_rst) begin + fifo_rd_en <= 1'b0; + end + else begin + fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4}; + end +end + +ad9361_fifo u_rx_fifo_ch1_i +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_4x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx1_data_i ), // input wire [11 : 0] din + .wr_en (fifo_wr_en ), // input wire wr_en + .rd_en (fifo_rd_en ), // input wire rd_en + .dout (rx_ch1_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_1) // output wire empty +); + +ad9361_fifo u_rx_fifo_ch1_q +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_4x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx1_data_q ), // input wire [11 : 0] din + .wr_en (fifo_wr_en ), // input wire wr_en + .rd_en (fifo_rd_en ), // input wire rd_en + .dout (rx_ch1_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_2) // output wire empty +); + +ad9361_fifo u_rx_fifo_ch2_i +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_4x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx2_data_i ), // input wire [11 : 0] din + .wr_en (fifo_wr_en ), // input wire wr_en + .rd_en (fifo_rd_en ), // input wire rd_en + .dout (rx_ch2_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_3) // output wire empty +); + +ad9361_fifo u_rx_fifo_ch2_q +( + .rst (rx_fifo_rst ), // input wire rst + .wr_clk (clk_4x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx2_data_q ), // input wire [11 : 0] din + .wr_en (fifo_wr_en ), // input wire wr_en + .rd_en (fifo_rd_en ), // input wire rd_en + .dout (rx_ch2_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_4) // output wire empty +); + +endmodule diff --git a/modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_dual.v b/modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_dual.v new file mode 100644 index 00000000..7fb0b8a8 --- /dev/null +++ b/modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_dual.v @@ -0,0 +1,183 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/07/01 16:39:19 +// Last Modified Date: 2023/03/06 11:45 +// Design Name: +// Module Name: ad9361_tx_map_cmos_dual +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ad9361_tx_map_cmos_dual +( + input clk_2x_in , + input clk_in_rst , + + input tx_data_clk , + input tx_data_clk_rst , + + input [11:0] tx_ch1_i , + input [11:0] tx_ch1_q , + input [11:0] tx_ch2_i , + input [11:0] tx_ch2_q , + + output clk_out , + output tx_frame , + output [11:0] tx_data +); + +genvar m; + +// input data fifo +reg rx_fifo_rd_en = 'b0; +wire [11:0] tx_fifo_ch1_i; +wire [11:0] tx_fifo_ch1_q; +wire [11:0] tx_fifo_ch2_i; +wire [11:0] tx_fifo_ch2_q; + +always @(posedge clk_2x_in) begin + if (clk_in_rst) begin + rx_fifo_rd_en <= 'b0; + end + else begin + rx_fifo_rd_en <= ~rx_fifo_rd_en; + end +end + +ad9361_fifo u_tx_fifo_ch1_i +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_2x_in ), // input wire rd_clk + .din (tx_ch1_i ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (tx_fifo_ch1_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +ad9361_fifo u_tx_fifo_ch1_q +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_2x_in ), // input wire rd_clk + .din (tx_ch1_q ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (tx_fifo_ch1_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +ad9361_fifo u_tx_fifo_ch2_i +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_2x_in ), // input wire rd_clk + .din (tx_ch2_i ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (tx_fifo_ch2_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +ad9361_fifo u_tx_fifo_ch2_q +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_2x_in ), // input wire rd_clk + .din (tx_ch2_q ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (tx_fifo_ch2_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +// frame and data control +reg tx_frame_i = 'b0; +reg tx_frame_q = 'b0; +reg [11:0] tx_data_i = 'b0; +reg [11:0] tx_data_q = 'b0; + +always @(posedge clk_2x_in) begin + if (clk_in_rst) begin + tx_frame_i <= 'b0; + tx_frame_q <= 'b0; + tx_data_i <= 'b0; + tx_data_q <= 'b0; + end + else if (rx_fifo_rd_en == 1'b0) begin + tx_frame_i <= 1'b1; + tx_frame_q <= 1'b1; + tx_data_i <= tx_fifo_ch1_i; + tx_data_q <= tx_fifo_ch1_q; + end + else begin + tx_frame_i <= 1'b0; + tx_frame_q <= 1'b0; + tx_data_i <= tx_fifo_ch2_i; + tx_data_q <= tx_fifo_ch2_q; + end +end + +// output clock to port +assign clk_out = clk_2x_in; + +// output tx frame to port +ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT (1'b0 ), + .SRTYPE ("ASYNC" ) +) u_tx_frame_oddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_2x_in ), + .D1 (tx_frame_i ), + .D2 (tx_frame_q ), + .Q (tx_frame ) +); + +// output tx data to port +generate +for (m=0; m<12; m=m+1) begin: tx_data_oddr + +ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT (1'b0 ), + .SRTYPE ("ASYNC" ) +) u_tx_data_oddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_2x_in ), + .D1 (tx_data_i[m] ), + .D2 (tx_data_q[m] ), + .Q (tx_data[m] ) +); + +end +endgenerate + +endmodule diff --git a/modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_single.v b/modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_single.v new file mode 100644 index 00000000..ad614384 --- /dev/null +++ b/modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_single.v @@ -0,0 +1,119 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/07/01 16:39:19 +// Design Name: +// Module Name: ad9361_tx_mapping_single +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ad9361_tx_map_cmos_single +( + input clk_in , + input clk_in_rst , + + input tx_data_clk , + input tx_data_clk_rst , + + input [11:0] tx_data_i , + input [11:0] tx_data_q , + + output clk_out , + output tx_frame , + output [11:0] tx_data +); + +genvar m; + +// inout data fifo +wire [11:0] tx_fifo_i; +wire [11:0] tx_fifo_q; + +ad9361_fifo u_tx_fifo_i +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_in ), // input wire rd_clk + .din (tx_data_i ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (1'b1 ), // input wire rd_en + .dout (tx_fifo_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +ad9361_fifo u_tx_fifo_q +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_in ), // input wire rd_clk + .din (tx_data_q ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (1'b1 ), // input wire rd_en + .dout (tx_fifo_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +// frame and data control +assign tx_frame_i = 1'b1; +assign tx_frame_q = 1'b0; + +// output clock to port +assign clk_out = clk_in; + +// output tx frame to port +ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT (1'b0 ), + .SRTYPE ("ASYNC" ) +) u_tx_frame_oddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_in ), + .D1 (tx_frame_i ), + .D2 (tx_frame_q ), + .Q (tx_frame ) +); + +// output tx data to port +generate +for (m=0; m<12; m=m+1) begin: tx_data_oddr + +ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT (1'b0 ), + .SRTYPE ("ASYNC" ) +) u_tx_data_oddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_in ), + .D1 (tx_fifo_i[m] ), + .D2 (tx_fifo_q[m] ), + .Q (tx_data[m] ) +); + +end +endgenerate + +endmodule diff --git a/modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_lvds_dual.v b/modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_lvds_dual.v new file mode 100644 index 00000000..0775eb88 --- /dev/null +++ b/modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_lvds_dual.v @@ -0,0 +1,246 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2023/03/05 23:21:27 +// Last Modified Date: 2023/03/06 11:01 +// Design Name: +// Module Name: ad9361_tx_map_lvds_dual +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ad9361_tx_map_lvds_dual +( + input clk_4x_in , + input clk_in_rst , + + input tx_data_clk , + input tx_data_clk_rst , + + input [11:0] tx_ch1_i , + input [11:0] tx_ch1_q , + input [11:0] tx_ch2_i , + input [11:0] tx_ch2_q , + + output clk_out_p , + output clk_out_n , + output tx_frame_p , + output tx_frame_n , + output [ 5:0] tx_data_p , + output [ 5:0] tx_data_n +); + +genvar m; + +// input data fifo +reg [1:0] tx_control_cnt = 'b0; +reg rx_fifo_rd_en = 'b0; +wire [11:0] tx_fifo_ch1_i; +wire [11:0] tx_fifo_ch1_q; +wire [11:0] tx_fifo_ch2_i; +wire [11:0] tx_fifo_ch2_q; + +always @(posedge clk_4x_in) begin + if (clk_in_rst) begin + tx_control_cnt <= 'b0; + end + else begin + tx_control_cnt <= tx_control_cnt + 1'b1; + end +end + +always @(posedge clk_4x_in) begin + if (clk_in_rst) begin + rx_fifo_rd_en <= 'b0; + end + else if (tx_control_cnt == 2'd2) begin + rx_fifo_rd_en <= 1'b1; + end + else begin + rx_fifo_rd_en <= 'b0; + end +end + +ad9361_fifo u_tx_fifo_ch1_i +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_4x_in ), // input wire rd_clk + .din (tx_ch1_i ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (tx_fifo_ch1_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +ad9361_fifo u_tx_fifo_ch1_q +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_4x_in ), // input wire rd_clk + .din (tx_ch1_q ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (tx_fifo_ch1_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +ad9361_fifo u_tx_fifo_ch2_i +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_4x_in ), // input wire rd_clk + .din (tx_ch2_i ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (tx_fifo_ch2_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + +ad9361_fifo u_tx_fifo_ch2_q +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_4x_in ), // input wire rd_clk + .din (tx_ch2_q ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (tx_fifo_ch2_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty ( ) // output wire empty +); + + +// frame and data control +reg tx_frame_r = 'b0; // rising edge data +reg tx_frame_f = 'b0; // falling edge data +reg [5:0] tx_data_r = 'b0; +reg [5:0] tx_data_f = 'b0; + +always @(posedge clk_4x_in) begin + if (clk_in_rst) begin + tx_frame_r <= 'b0; + tx_frame_f <= 'b0; + tx_data_r <= 'b0; + tx_data_f <= 'b0; + end + else begin + case (tx_control_cnt) + 2'd0: begin + tx_frame_r <= 1'b1; + tx_frame_f <= 1'b1; + tx_data_r <= tx_fifo_ch1_i[11: 6]; + tx_data_f <= tx_fifo_ch1_q[11: 6]; + end + 2'd1: begin + tx_frame_r <= 1'b1; + tx_frame_f <= 1'b1; + tx_data_r <= tx_fifo_ch1_i[5:0]; + tx_data_f <= tx_fifo_ch1_q[5:0]; + end + 2'd2: begin + tx_frame_r <= 1'b0; + tx_frame_f <= 1'b0; + tx_data_r <= tx_fifo_ch2_i[11:6]; + tx_data_f <= tx_fifo_ch2_q[11:6]; + end + 2'd3: begin + tx_frame_r <= 1'b0; + tx_frame_f <= 1'b0; + tx_data_r <= tx_fifo_ch2_i[5:0]; + tx_data_f <= tx_fifo_ch2_q[5:0]; + end + default: begin + tx_frame_r <= 'b0; + tx_frame_f <= 'b0; + tx_data_r <= 'b0; + tx_data_f <= 'b0; + end + endcase + end +end + +// output clock to port +wire clk_out; +assign clk_out = clk_4x_in; + +OBUFDS u_obufds_clk_out +( + .I (clk_out ), + .O (clk_out_p ), + .OB (clk_out_n ) +); + +// output tx frame to port +ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT (1'b0 ), + .SRTYPE ("ASYNC" ) +) u_tx_frame_oddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_4x_in ), + .D1 (tx_frame_r ), + .D2 (tx_frame_f ), + .Q (tx_frame ) +); + +OBUFDS u_obufds_tx_frame +( + .I (tx_frame ), + .O (tx_frame_p ), + .OB (tx_frame_n ) +); + +// output tx data to port +wire [5:0] tx_data; + +generate +for (m=0; m<6; m=m+1) begin: tx_data_oddr + +ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT (1'b0 ), + .SRTYPE ("ASYNC" ) +) u_tx_data_oddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_4x_in ), + .D1 (tx_data_r[m] ), + .D2 (tx_data_f[m] ), + .Q (tx_data[m] ) +); + +OBUFDS u_obufds_tx_data +( + .I (tx_data[m] ), + .O (tx_data_p[m] ), + .OB (tx_data_n[m] ) +); + +end +endgenerate + +endmodule diff --git a/modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.xpr b/modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.xpr new file mode 100644 index 00000000..d2d1cd83 --- /dev/null +++ b/modules/xc7k410tffg900-2/ad9361_mapping/ad9361_mapping.xpr @@ -0,0 +1,303 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + +