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update dj_47dr_lmx vivado project

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change axi spi engine miso line number to 1, miso is now selected based on cs
This commit is contained in:
josh
2024-07-05 11:35:10 +08:00
parent 81467ace82
commit 5f6348942f
13 changed files with 100 additions and 4484 deletions
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projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.runs/impl_1/debug_nets.ltx
+6 -201
View File
@@ -1229,201 +1229,6 @@
}
]
},
{
"type": "ILA_V3",
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/ila_lib",
"spec": "labtools_ila_v6",
"ipName": "ila",
"core_location": {
"user_chain": 1,
"slave_index": 2,
"bscan_switch_index": 0
},
"uuid": "70C55759E8A95195A6F1EB0CB46DBEDA",
"pins": [
{
"name": "probe0",
"id": 18,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": false,
"leftIndex": 0,
"rightIndex": 0,
"portIndex": 0,
"nets": [
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_sclk_1",
"isBus": false
}
]
},
{
"name": "probe1",
"id": 19,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": true,
"leftIndex": 0,
"rightIndex": 2,
"portIndex": 1,
"nets": [
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_sdi_1",
"isBus": true,
"subnets": [
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_sdi_1[2]"
},
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_sdi_1[1]"
},
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_sdi_1[0]"
}
]
}
]
},
{
"name": "probe2",
"id": 20,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": false,
"leftIndex": 0,
"rightIndex": 0,
"portIndex": 2,
"nets": [
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_sdo_1",
"isBus": false
}
]
},
{
"name": "probe3",
"id": 21,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": false,
"leftIndex": 0,
"rightIndex": 0,
"portIndex": 3,
"nets": [
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_sdo_t_1",
"isBus": false
}
]
},
{
"name": "probe4",
"id": 22,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": false,
"leftIndex": 0,
"rightIndex": 0,
"portIndex": 4,
"nets": [
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_three_wire_1",
"isBus": false
}
]
},
{
"name": "probe5",
"id": 23,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": true,
"leftIndex": 0,
"rightIndex": 2,
"portIndex": 5,
"nets": [
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_cs_1",
"isBus": true,
"subnets": [
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_cs_1[2]"
},
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_cs_1[1]"
},
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_cs_1[0]"
}
]
}
]
}
],
"bus_interfaces": [
{
"name": "SLOT_0_SPI_ENGINE",
"vlnv": "analog.com:interface:spi_engine:1.0",
"connectedBus": "adi_spi_engine_spi_0",
"port_maps": [
{
"logical_port": "cs",
"physical_pin": {
"id": 23,
"name": "probe5",
"leftBit": 0,
"width": 3
}
},
{
"logical_port": "sclk",
"physical_pin": {
"id": 18,
"name": "probe0",
"leftBit": 0,
"width": 1
}
},
{
"logical_port": "sdi",
"physical_pin": {
"id": 19,
"name": "probe1",
"leftBit": 0,
"width": 3
}
},
{
"logical_port": "sdo",
"physical_pin": {
"id": 20,
"name": "probe2",
"leftBit": 0,
"width": 1
}
},
{
"logical_port": "sdo_t",
"physical_pin": {
"id": 21,
"name": "probe3",
"leftBit": 0,
"width": 1
}
},
{
"logical_port": "three_wire",
"physical_pin": {
"id": 22,
"name": "probe4",
"leftBit": 0,
"width": 1
}
}
]
}
]
},
{
"type": "VIO_V2",
"name": "u_vio_manual_ctrl",
@@ -1431,14 +1236,14 @@
"ipName": "vio",
"core_location": {
"user_chain": 1,
"slave_index": 3,
"slave_index": 2,
"bscan_switch_index": 0
},
"uuid": "6DFBBD640CB857419C054C66C7EA7B27",
"pins": [
{
"name": "probe_out0",
"id": 24,
"id": 18,
"type": "DATA",
"direction": "OUT",
"isVector": true,
@@ -1462,7 +1267,7 @@
},
{
"name": "probe_out1",
"id": 25,
"id": 19,
"type": "DATA",
"direction": "OUT",
"isVector": false,
@@ -1478,7 +1283,7 @@
},
{
"name": "probe_out2",
"id": 26,
"id": 20,
"type": "DATA",
"direction": "OUT",
"isVector": true,
@@ -1592,7 +1397,7 @@
},
{
"name": "probe_out3",
"id": 27,
"id": 21,
"type": "DATA",
"direction": "OUT",
"isVector": true,
@@ -1616,7 +1421,7 @@
},
{
"name": "probe_out4",
"id": 28,
"id": 22,
"type": "DATA",
"direction": "OUT",
"isVector": true,
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.runs/impl_1/system_top.bit
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projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.runs/impl_1/system_top.ltx
+6 -201
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@@ -1229,201 +1229,6 @@
}
]
},
{
"type": "ILA_V3",
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/ila_lib",
"spec": "labtools_ila_v6",
"ipName": "ila",
"core_location": {
"user_chain": 1,
"slave_index": 2,
"bscan_switch_index": 0
},
"uuid": "70C55759E8A95195A6F1EB0CB46DBEDA",
"pins": [
{
"name": "probe0",
"id": 18,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": false,
"leftIndex": 0,
"rightIndex": 0,
"portIndex": 0,
"nets": [
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_sclk_1",
"isBus": false
}
]
},
{
"name": "probe1",
"id": 19,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": true,
"leftIndex": 0,
"rightIndex": 2,
"portIndex": 1,
"nets": [
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_sdi_1",
"isBus": true,
"subnets": [
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_sdi_1[2]"
},
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_sdi_1[1]"
},
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_sdi_1[0]"
}
]
}
]
},
{
"name": "probe2",
"id": 20,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": false,
"leftIndex": 0,
"rightIndex": 0,
"portIndex": 2,
"nets": [
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_sdo_1",
"isBus": false
}
]
},
{
"name": "probe3",
"id": 21,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": false,
"leftIndex": 0,
"rightIndex": 0,
"portIndex": 3,
"nets": [
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_sdo_t_1",
"isBus": false
}
]
},
{
"name": "probe4",
"id": 22,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": false,
"leftIndex": 0,
"rightIndex": 0,
"portIndex": 4,
"nets": [
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_three_wire_1",
"isBus": false
}
]
},
{
"name": "probe5",
"id": 23,
"type": "DATA_TRIGGER",
"direction": "IN",
"isVector": true,
"leftIndex": 0,
"rightIndex": 2,
"portIndex": 5,
"nets": [
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_cs_1",
"isBus": true,
"subnets": [
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_cs_1[2]"
},
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_cs_1[1]"
},
{
"name": "u_system_bd_wrapper/system_bd_i/system_ila_0/inst/SLOT_0_SPI_ENGINE_cs_1[0]"
}
]
}
]
}
],
"bus_interfaces": [
{
"name": "SLOT_0_SPI_ENGINE",
"vlnv": "analog.com:interface:spi_engine:1.0",
"connectedBus": "adi_spi_engine_spi_0",
"port_maps": [
{
"logical_port": "cs",
"physical_pin": {
"id": 23,
"name": "probe5",
"leftBit": 0,
"width": 3
}
},
{
"logical_port": "sclk",
"physical_pin": {
"id": 18,
"name": "probe0",
"leftBit": 0,
"width": 1
}
},
{
"logical_port": "sdi",
"physical_pin": {
"id": 19,
"name": "probe1",
"leftBit": 0,
"width": 3
}
},
{
"logical_port": "sdo",
"physical_pin": {
"id": 20,
"name": "probe2",
"leftBit": 0,
"width": 1
}
},
{
"logical_port": "sdo_t",
"physical_pin": {
"id": 21,
"name": "probe3",
"leftBit": 0,
"width": 1
}
},
{
"logical_port": "three_wire",
"physical_pin": {
"id": 22,
"name": "probe4",
"leftBit": 0,
"width": 1
}
}
]
}
]
},
{
"type": "VIO_V2",
"name": "u_vio_manual_ctrl",
@@ -1431,14 +1236,14 @@
"ipName": "vio",
"core_location": {
"user_chain": 1,
"slave_index": 3,
"slave_index": 2,
"bscan_switch_index": 0
},
"uuid": "6DFBBD640CB857419C054C66C7EA7B27",
"pins": [
{
"name": "probe_out0",
"id": 24,
"id": 18,
"type": "DATA",
"direction": "OUT",
"isVector": true,
@@ -1462,7 +1267,7 @@
},
{
"name": "probe_out1",
"id": 25,
"id": 19,
"type": "DATA",
"direction": "OUT",
"isVector": false,
@@ -1478,7 +1283,7 @@
},
{
"name": "probe_out2",
"id": 26,
"id": 20,
"type": "DATA",
"direction": "OUT",
"isVector": true,
@@ -1592,7 +1397,7 @@
},
{
"name": "probe_out3",
"id": 27,
"id": 21,
"type": "DATA",
"direction": "OUT",
"isVector": true,
@@ -1616,7 +1421,7 @@
},
{
"name": "probe_out4",
"id": 28,
"id": 22,
"type": "DATA",
"direction": "OUT",
"isVector": true,
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci
+4 -4
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@@ -19,7 +19,7 @@
"OFFLOAD0_SDO_MEM_ADDRESS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
"ID": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
"NUM_OF_SDI": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
"NUM_OF_SDI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"CFG_INFO_0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"CFG_INFO_1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"CFG_INFO_2": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
@@ -115,17 +115,17 @@
"mode": "slave",
"memory_map_ref": "s_axi",
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "96968727", "value_src": "user_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "16", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd_and_user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci
+4 -4
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@@ -12,7 +12,7 @@
"DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"DATA_WIDTH": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ],
"NUM_OF_SDI": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"NUM_OF_SDI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "user", "format": "bitString", "usage": "all" } ],
"ECHO_SCLK": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"SDI_DELAY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
@@ -23,7 +23,7 @@
"DEFAULT_SPI_CFG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"DEFAULT_CLK_DIV": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"DATA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"NUM_OF_SDI": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"NUM_OF_SDI": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"SDO_DEFAULT": [ { "value": "\"0\"", "resolve_type": "generated", "format": "bitString", "usage": "all" } ],
"ECHO_SCLK": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
"SDI_DELAY": [ { "value": "false", "resolve_type": "generated", "format": "bool", "usage": "all" } ]
@@ -66,14 +66,14 @@
"sdo_data": [ { "direction": "in", "size_left": "7", "size_right": "0" } ],
"sdi_data_ready": [ { "direction": "in", "driver_value": "0" } ],
"sdi_data_valid": [ { "direction": "out" } ],
"sdi_data": [ { "direction": "out", "size_left": "23", "size_right": "0" } ],
"sdi_data": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
"sync_ready": [ { "direction": "in" } ],
"sync_valid": [ { "direction": "out" } ],
"sync": [ { "direction": "out", "size_left": "7", "size_right": "0" } ],
"sclk": [ { "direction": "out" } ],
"sdo": [ { "direction": "out" } ],
"sdo_t": [ { "direction": "out" } ],
"sdi": [ { "direction": "in", "size_left": "2", "size_right": "0" } ],
"sdi": [ { "direction": "in", "size_left": "0", "size_right": "0" } ],
"cs": [ { "direction": "out", "size_left": "2", "size_right": "0" } ],
"three_wire": [ { "direction": "out" } ]
},
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ip/system_bd_system_ila_0_0/system_bd_system_ila_0_0.xci
-3911
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projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/system_bd.bd
+14 -62
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@@ -1,7 +1,7 @@
{
"design": {
"design_info": {
"boundary_crc": "0x9F3174A6C2346610",
"boundary_crc": "0x7879DD10C9E21201",
"device": "xczu47dr-ffve1156-2-i",
"gen_directory": "../../../../dj_47dr_lmx.gen/sources_1/bd/system_bd",
"name": "system_bd",
@@ -35,8 +35,7 @@
"xlconstant_0": ""
},
"xlconcat_0": "",
"zynq_ultra_ps_e": "",
"system_ila_0": ""
"zynq_ultra_ps_e": ""
},
"interface_ports": {
"spi": {
@@ -51,7 +50,7 @@
"sdi": {
"physical_name": "spi_sdi",
"direction": "I",
"left": "2",
"left": "0",
"right": "0"
},
"sdo": {
@@ -3173,7 +3172,12 @@
"ip_revision": "1",
"xci_name": "system_bd_axi_spi_engine_0_0",
"xci_path": "ip/system_bd_axi_spi_engine_0_0/system_bd_axi_spi_engine_0_0.xci",
"inst_hier_path": "axi_spi_engine/axi_spi_engine"
"inst_hier_path": "axi_spi_engine/axi_spi_engine",
"parameters": {
"NUM_OF_SDI": {
"value": "1"
}
}
},
"spi_engine_execution": {
"vlnv": "analog.com:user:spi_engine_execution:1.0",
@@ -3186,7 +3190,7 @@
"value": "3"
},
"NUM_OF_SDI": {
"value": "3"
"value": "1"
}
}
}
@@ -3202,12 +3206,7 @@
"interface_ports": [
"spi_engine_execution/spi",
"spi"
],
"hdl_attributes": {
"DEBUG": {
"value": "true"
}
}
]
},
"axi_spi_engine_spi_engine_ctrl": {
"interface_ports": [
@@ -4366,43 +4365,6 @@
}
}
}
},
"system_ila_0": {
"vlnv": "xilinx.com:ip:system_ila:1.1",
"ip_revision": "17",
"xci_name": "system_bd_system_ila_0_0",
"xci_path": "ip/system_bd_system_ila_0_0/system_bd_system_ila_0_0.xci",
"inst_hier_path": "system_ila_0",
"parameters": {
"C_ADV_TRIGGER": {
"value": "true"
},
"C_DATA_DEPTH": {
"value": "131072"
},
"C_EN_STRG_QUAL": {
"value": "1"
},
"C_MON_TYPE": {
"value": "INTERFACE"
},
"C_NUM_MONITOR_SLOTS": {
"value": "1"
},
"C_SLOT_0_INTF_TYPE": {
"value": "analog.com:interface:spi_engine_rtl:1.0"
},
"C_SLOT_0_TYPE": {
"value": "0"
}
},
"interface_ports": {
"SLOT_0_SPI_ENGINE": {
"mode": "Monitor",
"vlnv_bus_definition": "analog.com:interface:spi_engine:1.0",
"vlnv": "analog.com:interface:spi_engine_rtl:1.0"
}
}
}
},
"interface_nets": {
@@ -4415,17 +4377,8 @@
"adi_spi_engine_spi_0": {
"interface_ports": [
"spi",
"axi_spi_engine/spi",
"system_ila_0/SLOT_0_SPI_ENGINE"
],
"hdl_attributes": {
"DEBUG": {
"value": "true"
},
"MARK_DEBUG": {
"value": "true"
}
}
"axi_spi_engine/spi"
]
},
"dac2_clk_1": {
"interface_ports": [
@@ -4920,8 +4873,7 @@
"ps8_0_axi_periph/ACLK",
"usp_rf_data_converter/s_axi_aclk",
"ps8_0_axi_periph/M01_ACLK",
"zynq_ultra_ps_e/maxihpm0_lpd_aclk",
"system_ila_0/clk"
"zynq_ultra_ps_e/maxihpm0_lpd_aclk"
]
},
"zynq_ultra_ps_e_pl_resetn0": {
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_c6d0cb12.ui
+46 -47
View File
@@ -1,31 +1,31 @@
{
"ActiveEmotionalView":"Default View",
"Default View_ScaleFactor":"0.872851",
"Default View_TopLeft":"416,27",
"Default View_ScaleFactor":"0.537304",
"Default View_TopLeft":"-1158,4",
"ExpandedHierarchyInLayout":"",
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
# -string -flagsOSRD
preplace port spi -pg 1 -lvl 4 -x 1380 -y 330 -defaultsOSRD
preplace port spi -pg 1 -lvl 4 -x 1120 -y 330 -defaultsOSRD
preplace port pl_clk -pg 1 -lvl 0 -x 0 -y 1450 -defaultsOSRD
preplace port pl_sysref -pg 1 -lvl 0 -x 0 -y 1470 -defaultsOSRD
preplace port adc2_clk -pg 1 -lvl 0 -x 0 -y 700 -defaultsOSRD
preplace port dac2_clk -pg 1 -lvl 0 -x 0 -y 720 -defaultsOSRD
preplace port m00_axis -pg 1 -lvl 4 -x 1380 -y 590 -defaultsOSRD
preplace port m01_axis -pg 1 -lvl 4 -x 1380 -y 610 -defaultsOSRD
preplace port m02_axis -pg 1 -lvl 4 -x 1380 -y 630 -defaultsOSRD
preplace port m03_axis -pg 1 -lvl 4 -x 1380 -y 650 -defaultsOSRD
preplace port m10_axis -pg 1 -lvl 4 -x 1380 -y 670 -defaultsOSRD
preplace port m11_axis -pg 1 -lvl 4 -x 1380 -y 690 -defaultsOSRD
preplace port m12_axis -pg 1 -lvl 4 -x 1380 -y 710 -defaultsOSRD
preplace port m13_axis -pg 1 -lvl 4 -x 1380 -y 730 -defaultsOSRD
preplace port m20_axis -pg 1 -lvl 4 -x 1380 -y 750 -defaultsOSRD
preplace port m21_axis -pg 1 -lvl 4 -x 1380 -y 770 -defaultsOSRD
preplace port m22_axis -pg 1 -lvl 4 -x 1380 -y 790 -defaultsOSRD
preplace port m23_axis -pg 1 -lvl 4 -x 1380 -y 810 -defaultsOSRD
preplace port m30_axis -pg 1 -lvl 4 -x 1380 -y 830 -defaultsOSRD
preplace port m31_axis -pg 1 -lvl 4 -x 1380 -y 850 -defaultsOSRD
preplace port m32_axis -pg 1 -lvl 4 -x 1380 -y 870 -defaultsOSRD
preplace port m33_axis -pg 1 -lvl 4 -x 1380 -y 890 -defaultsOSRD
preplace port m00_axis -pg 1 -lvl 4 -x 1120 -y 590 -defaultsOSRD
preplace port m01_axis -pg 1 -lvl 4 -x 1120 -y 610 -defaultsOSRD
preplace port m02_axis -pg 1 -lvl 4 -x 1120 -y 630 -defaultsOSRD
preplace port m03_axis -pg 1 -lvl 4 -x 1120 -y 650 -defaultsOSRD
preplace port m10_axis -pg 1 -lvl 4 -x 1120 -y 670 -defaultsOSRD
preplace port m11_axis -pg 1 -lvl 4 -x 1120 -y 690 -defaultsOSRD
preplace port m12_axis -pg 1 -lvl 4 -x 1120 -y 710 -defaultsOSRD
preplace port m13_axis -pg 1 -lvl 4 -x 1120 -y 730 -defaultsOSRD
preplace port m20_axis -pg 1 -lvl 4 -x 1120 -y 750 -defaultsOSRD
preplace port m21_axis -pg 1 -lvl 4 -x 1120 -y 770 -defaultsOSRD
preplace port m22_axis -pg 1 -lvl 4 -x 1120 -y 790 -defaultsOSRD
preplace port m23_axis -pg 1 -lvl 4 -x 1120 -y 810 -defaultsOSRD
preplace port m30_axis -pg 1 -lvl 4 -x 1120 -y 830 -defaultsOSRD
preplace port m31_axis -pg 1 -lvl 4 -x 1120 -y 850 -defaultsOSRD
preplace port m32_axis -pg 1 -lvl 4 -x 1120 -y 870 -defaultsOSRD
preplace port m33_axis -pg 1 -lvl 4 -x 1120 -y 890 -defaultsOSRD
preplace port s00_axis -pg 1 -lvl 0 -x 0 -y 540 -defaultsOSRD
preplace port s02_axis -pg 1 -lvl 0 -x 0 -y 560 -defaultsOSRD
preplace port s10_axis -pg 1 -lvl 0 -x 0 -y 580 -defaultsOSRD
@@ -43,26 +43,26 @@ preplace port vin2_01 -pg 1 -lvl 0 -x 0 -y 820 -defaultsOSRD
preplace port vin2_23 -pg 1 -lvl 0 -x 0 -y 840 -defaultsOSRD
preplace port vin3_01 -pg 1 -lvl 0 -x 0 -y 860 -defaultsOSRD
preplace port vin3_23 -pg 1 -lvl 0 -x 0 -y 880 -defaultsOSRD
preplace port vout00 -pg 1 -lvl 4 -x 1380 -y 910 -defaultsOSRD
preplace port vout02 -pg 1 -lvl 4 -x 1380 -y 930 -defaultsOSRD
preplace port vout10 -pg 1 -lvl 4 -x 1380 -y 950 -defaultsOSRD
preplace port vout12 -pg 1 -lvl 4 -x 1380 -y 970 -defaultsOSRD
preplace port vout20 -pg 1 -lvl 4 -x 1380 -y 990 -defaultsOSRD
preplace port vout22 -pg 1 -lvl 4 -x 1380 -y 1010 -defaultsOSRD
preplace port vout30 -pg 1 -lvl 4 -x 1380 -y 1030 -defaultsOSRD
preplace port vout32 -pg 1 -lvl 4 -x 1380 -y 1050 -defaultsOSRD
preplace port port-id_spi_active -pg 1 -lvl 4 -x 1380 -y 350 -defaultsOSRD
preplace port port-id_sys_rstn -pg 1 -lvl 4 -x 1380 -y 1460 -defaultsOSRD
preplace port port-id_sys_clk -pg 1 -lvl 4 -x 1380 -y 1480 -defaultsOSRD
preplace port port-id_ps_clk0 -pg 1 -lvl 4 -x 1380 -y 540 -defaultsOSRD
preplace port port-id_clk_adc0 -pg 1 -lvl 4 -x 1380 -y 1070 -defaultsOSRD
preplace port port-id_clk_adc1 -pg 1 -lvl 4 -x 1380 -y 1090 -defaultsOSRD
preplace port port-id_clk_adc2 -pg 1 -lvl 4 -x 1380 -y 1110 -defaultsOSRD
preplace port port-id_clk_adc3 -pg 1 -lvl 4 -x 1380 -y 1130 -defaultsOSRD
preplace port port-id_clk_dac0 -pg 1 -lvl 4 -x 1380 -y 1150 -defaultsOSRD
preplace port port-id_clk_dac1 -pg 1 -lvl 4 -x 1380 -y 1170 -defaultsOSRD
preplace port port-id_clk_dac2 -pg 1 -lvl 4 -x 1380 -y 1190 -defaultsOSRD
preplace port port-id_clk_dac3 -pg 1 -lvl 4 -x 1380 -y 1210 -defaultsOSRD
preplace port vout00 -pg 1 -lvl 4 -x 1120 -y 910 -defaultsOSRD
preplace port vout02 -pg 1 -lvl 4 -x 1120 -y 930 -defaultsOSRD
preplace port vout10 -pg 1 -lvl 4 -x 1120 -y 950 -defaultsOSRD
preplace port vout12 -pg 1 -lvl 4 -x 1120 -y 970 -defaultsOSRD
preplace port vout20 -pg 1 -lvl 4 -x 1120 -y 990 -defaultsOSRD
preplace port vout22 -pg 1 -lvl 4 -x 1120 -y 1010 -defaultsOSRD
preplace port vout30 -pg 1 -lvl 4 -x 1120 -y 1030 -defaultsOSRD
preplace port vout32 -pg 1 -lvl 4 -x 1120 -y 1050 -defaultsOSRD
preplace port port-id_spi_active -pg 1 -lvl 4 -x 1120 -y 350 -defaultsOSRD
preplace port port-id_sys_rstn -pg 1 -lvl 4 -x 1120 -y 1460 -defaultsOSRD
preplace port port-id_sys_clk -pg 1 -lvl 4 -x 1120 -y 1480 -defaultsOSRD
preplace port port-id_ps_clk0 -pg 1 -lvl 4 -x 1120 -y 540 -defaultsOSRD
preplace port port-id_clk_adc0 -pg 1 -lvl 4 -x 1120 -y 1070 -defaultsOSRD
preplace port port-id_clk_adc1 -pg 1 -lvl 4 -x 1120 -y 1090 -defaultsOSRD
preplace port port-id_clk_adc2 -pg 1 -lvl 4 -x 1120 -y 1110 -defaultsOSRD
preplace port port-id_clk_adc3 -pg 1 -lvl 4 -x 1120 -y 1130 -defaultsOSRD
preplace port port-id_clk_dac0 -pg 1 -lvl 4 -x 1120 -y 1150 -defaultsOSRD
preplace port port-id_clk_dac1 -pg 1 -lvl 4 -x 1120 -y 1170 -defaultsOSRD
preplace port port-id_clk_dac2 -pg 1 -lvl 4 -x 1120 -y 1190 -defaultsOSRD
preplace port port-id_clk_dac3 -pg 1 -lvl 4 -x 1120 -y 1210 -defaultsOSRD
preplace port port-id_m0_axis_aclk -pg 1 -lvl 0 -x 0 -y 1020 -defaultsOSRD
preplace port port-id_m0_axis_aresetn -pg 1 -lvl 0 -x 0 -y 1000 -defaultsOSRD
preplace port port-id_m1_axis_aclk -pg 1 -lvl 0 -x 0 -y 1060 -defaultsOSRD
@@ -86,8 +86,7 @@ preplace inst rst_ps8_0_96M -pg 1 -lvl 2 -x 880 -y 170 -defaultsOSRD
preplace inst mts_clk_gen -pg 1 -lvl 1 -x 360 -y 1460 -defaultsOSRD
preplace inst xlconcat_0 -pg 1 -lvl 2 -x 880 -y 470 -defaultsOSRD -orient R180
preplace inst zynq_ultra_ps_e -pg 1 -lvl 1 -x 360 -y 110 -defaultsOSRD
preplace inst system_ila_0 -pg 1 -lvl 3 -x 1200 -y 280 -defaultsOSRD
preplace netloc adi_spi_engine_active_0 1 2 2 1060 360 1340
preplace netloc adi_spi_engine_active_0 1 2 2 N 350 N
preplace netloc adi_spi_engine_irq 1 2 1 1060 370n
preplace netloc m0_axis_aclk_0_1 1 0 1 NJ 1020
preplace netloc m0_axis_aresetn_0_1 1 0 1 NJ 1000
@@ -119,9 +118,11 @@ preplace netloc usp_rf_data_converter_clk_dac2 1 1 3 N 1190 NJ 1190 N
preplace netloc usp_rf_data_converter_clk_dac3 1 1 3 N 1210 NJ 1210 N
preplace netloc usp_rf_data_converter_irq 1 1 2 N 1230 1060
preplace netloc xlconcat_0_dout 1 0 2 20 10 680J
preplace netloc zynq_ultra_ps_e_pl_clk0 1 0 4 30 1370 690J 70 1070J 210 1330
preplace netloc zynq_ultra_ps_e_pl_clk0 1 0 4 30 1370 690J 540 NJ 540 N
preplace netloc zynq_ultra_ps_e_pl_resetn0 1 1 1 670 110n
preplace netloc adi_spi_engine_spi_0 1 2 2 1080 350 1320
preplace netloc adc2_clk_1 1 0 1 N 700
preplace netloc adi_spi_engine_spi_0 1 2 2 N 330 N
preplace netloc dac2_clk_1 1 0 1 N 720
preplace netloc pl_clk_0_1 1 0 1 N 1450
preplace netloc pl_sysref_0_1 1 0 1 N 1470
preplace netloc ps8_0_axi_periph_M00_AXI 1 1 1 NJ 330
@@ -168,10 +169,8 @@ preplace netloc vin2_23_0_1 1 0 1 NJ 840
preplace netloc vin3_01_0_1 1 0 1 NJ 860
preplace netloc vin3_23_0_1 1 0 1 NJ 880
preplace netloc zynq_ultra_ps_e_M_AXI_HPM0_LPD 1 0 2 40 20 670
preplace netloc adc2_clk_1 1 0 1 N 700
preplace netloc dac2_clk_1 1 0 1 N 720
levelinfo -pg 1 0 360 880 1200 1380
pagesize -pg 1 -db -bbox -sgen -170 0 1860 1610
levelinfo -pg 1 0 360 880 1080 1120
pagesize -pg 1 -db -bbox -sgen -170 0 1240 1530
"
}
{
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/bd/system_bd/ui/bd_e4e34314.ui
+5 -5
View File
@@ -6,11 +6,11 @@
"guistr":"# # String gsaved with Nlview 7.7.1 2023-07-26 3bc4126617 VDI=43 GEI=38 GUI=JA:21.0 TLS
# -string -flagsOSRD
preplace port s_axi -pg 1 -lvl 0 -x 0 -y -270 -defaultsOSRD
preplace port spi -pg 1 -lvl 3 -x 730 -y -250 -defaultsOSRD
preplace port spi -pg 1 -lvl 3 -x 740 -y -250 -defaultsOSRD
preplace port port-id_s_axi_aclk -pg 1 -lvl 0 -x 0 -y -250 -defaultsOSRD
preplace port port-id_s_axi_aresetn -pg 1 -lvl 0 -x 0 -y -230 -defaultsOSRD
preplace port port-id_active -pg 1 -lvl 3 -x 730 -y -230 -defaultsOSRD
preplace port port-id_irq -pg 1 -lvl 3 -x 730 -y -320 -defaultsOSRD
preplace port port-id_active -pg 1 -lvl 3 -x 740 -y -230 -defaultsOSRD
preplace port port-id_irq -pg 1 -lvl 3 -x 740 -y -320 -defaultsOSRD
preplace inst axi_spi_engine -pg 1 -lvl 1 -x 340 -y -240 -defaultsOSRD
preplace inst spi_engine_execution -pg 1 -lvl 2 -x 600 -y -240 -defaultsOSRD
preplace netloc axi_spi_engine_irq 1 1 2 480J -320 NJ
@@ -21,8 +21,8 @@ preplace netloc spi_engine_execution_active 1 2 1 NJ -230
preplace netloc Conn1 1 0 1 NJ -270
preplace netloc Conn2 1 2 1 NJ -250
preplace netloc axi_spi_engine_spi_engine_ctrl 1 1 1 N -260
levelinfo -pg 1 0 340 600 730
pagesize -pg 1 -db -bbox -sgen -150 -630 830 180
levelinfo -pg 1 0 340 600 740
pagesize -pg 1 -db -bbox -sgen -150 -630 840 180
"
}
0
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/sources_1/new/system_top.v
+10 -4
View File
@@ -113,7 +113,7 @@ wire sys_rstn;
// spi interface
wire spi_sclk ;
wire [2:0] spi_cs ;
wire [2:0] spi_sdi ;
reg spi_sdi ;
wire spi_sdo ;
wire spi_sdo_t ;
wire spi_three_wire;
@@ -121,19 +121,25 @@ wire spi_active ;
assign lmk_spi_sck = spi_sclk;
assign lmk_spi_cs = spi_cs[0];
assign spi_sdi[0] = spi_three_wire ? lmk_spi_mosi : lmk_spi_miso;
assign lmk_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
assign lmx_adc_spi_sck = spi_sclk;
assign lmx_adc_spi_cs = spi_cs[1];
assign spi_sdi[1] = spi_three_wire ? lmx_adc_spi_mosi : lmx_adc_spi_miso;
assign lmx_adc_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
assign lmx_dac_spi_sck = spi_sclk;
assign lmx_dac_spi_cs = spi_cs[2];
assign spi_sdi[2] = spi_three_wire ? lmx_dac_spi_mosi : lmx_dac_spi_miso;
assign lmx_dac_spi_mosi = spi_sdo_t ? 1'bz : spi_sdo;
always @(*) begin
case (spi_cs)
3'b110: spi_sdi = spi_three_wire ? lmk_spi_mosi : lmk_spi_miso;
3'b101: spi_sdi = spi_three_wire ? lmx_adc_spi_mosi : lmx_adc_spi_miso;
3'b011: spi_sdi = spi_three_wire ? lmx_dac_spi_mosi : lmx_dac_spi_miso;
default: spi_sdi = 1'bz;
endcase
end
// -----------------------------------------------------------------------------
// ADC Tile & Channel Mapping (Dual RF-ADC)
// -----------------------------------------------------------------------------
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.srcs/utils_1/imports/synth_1/system_top.dcp
LFS
BIN
View File
Binary file not shown.
projects/dj_47dr/dj_47dr_lmx/dj_47dr_lmx.xpr
-40
View File
@@ -108,9 +108,6 @@
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_spi_engine_execution_0_0/system_bd_spi_engine_execution_0_0.xci">
<Proxy FileSetName="system_bd_spi_engine_execution_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_system_ila_0_0/system_bd_system_ila_0_0.xci">
<Proxy FileSetName="system_bd_system_ila_0_0"/>
</CompFileExtendedInfo>
<CompFileExtendedInfo CompFileName="system_bd.bd" FileRelPathName="ip/system_bd_usp_rf_data_converter_0_0/system_bd_usp_rf_data_converter_0_0.xci">
<Proxy FileSetName="system_bd_usp_rf_data_converter_0_0"/>
</CompFileExtendedInfo>
@@ -395,12 +392,6 @@
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="system_bd_system_ila_0_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/system_bd_system_ila_0_0" RelGenDir="$PGENDIR/system_bd_system_ila_0_0">
<Config>
<Option Name="TopModule" Val="system_bd_system_ila_0_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
@@ -624,18 +615,6 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_system_ila_0_0_synth_1" Type="Ft3:Synth" SrcSet="system_bd_system_ila_0_0" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_system_ila_0_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/system_bd_system_ila_0_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_system_ila_0_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_system_ila_0_0_synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 18 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
@@ -977,25 +956,6 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="system_bd_system_ila_0_0_impl_1" Type="Ft2:EntireDesign" Part="xczu47dr-ffve1156-2-i" ConstrsSet="system_bd_system_ila_0_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="system_bd_system_ila_0_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/system_bd_system_ila_0_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/system_bd_system_ila_0_0_impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<Board/>
<DashboardSummary Version="1" Minor="0">
projects/dj_47dr/dj_47dr_lmx/system_top.xsa
LFS
BIN
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