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"u_mclk_delay/MCLK_DELAY_CURVALUE2[3]" + }, + { + "name": "u_mclk_delay/MCLK_DELAY_CURVALUE2[2]" + }, + { + "name": "u_mclk_delay/MCLK_DELAY_CURVALUE2[1]" + }, + { + "name": "u_mclk_delay/MCLK_DELAY_CURVALUE2[0]" + } + ] + } + ] + }, + { + "name": "probe_out0", + "id": 18, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 4, + "portIndex": 0, + "nets": [ + { + "name": "u_mclk_delay/MCLK_DELAY_SETVALUE0", + "isBus": true, + "subnets": [ + { + "name": "u_mclk_delay/MCLK_DELAY_SETVALUE0[4]" + }, + { + "name": "u_mclk_delay/MCLK_DELAY_SETVALUE0[3]" + }, + { + "name": "u_mclk_delay/MCLK_DELAY_SETVALUE0[2]" + }, + { + "name": "u_mclk_delay/MCLK_DELAY_SETVALUE0[1]" + }, + { + "name": "u_mclk_delay/MCLK_DELAY_SETVALUE0[0]" + } + ] + } + ] + }, + { + "name": "probe_out1", + "id": 19, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 4, + "portIndex": 1, + "nets": [ + { + "name": "u_mclk_delay/MCLK_DELAY_SETVALUE1", + "isBus": true, + "subnets": [ + { + "name": "u_mclk_delay/MCLK_DELAY_SETVALUE1[4]" + }, + { + "name": "u_mclk_delay/MCLK_DELAY_SETVALUE1[3]" + }, + { + "name": "u_mclk_delay/MCLK_DELAY_SETVALUE1[2]" + }, + { + "name": "u_mclk_delay/MCLK_DELAY_SETVALUE1[1]" + }, + { + "name": "u_mclk_delay/MCLK_DELAY_SETVALUE1[0]" + } + ] + } + ] + }, + { + "name": "probe_out2", + "id": 20, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 4, + "portIndex": 2, + "nets": [ + { + "name": "u_mclk_delay/MCLK_DELAY_SETVALUE2", + "isBus": true, + "subnets": [ + { + "name": "u_mclk_delay/MCLK_DELAY_SETVALUE2[4]" + }, + { + "name": "u_mclk_delay/MCLK_DELAY_SETVALUE2[3]" + }, + { + "name": "u_mclk_delay/MCLK_DELAY_SETVALUE2[2]" + }, + { + "name": "u_mclk_delay/MCLK_DELAY_SETVALUE2[1]" + }, + { + "name": "u_mclk_delay/MCLK_DELAY_SETVALUE2[0]" + } + ] + } + ] + } + ] + }, + { + "type": "VIO_V2", + "name": "u_vio_hop_int", + "spec": "labtools_vio_v3", + "ipName": "vio", + "core_location": { + "user_chain": 1, + "slave_index": 4, + "bscan_switch_index": 0 + }, + "uuid": "72FCB788790F5E07BEE4653694C9B105", + "pins": [ + { + "name": "probe_out0", + "id": 21, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 31, + "portIndex": 0, + "nets": [ + { + "name": "hop_int", + "isBus": true, + "subnets": [ + { + "name": "hop_int[31]" + }, + { + "name": "hop_int[30]" + }, + { + "name": "hop_int[29]" + }, + { + "name": "hop_int[28]" + }, + { + "name": "hop_int[27]" + }, + { + "name": "hop_int[26]" + }, + { + "name": "hop_int[25]" + }, + { + "name": "hop_int[24]" + }, + { + "name": "hop_int[23]" + }, + { + "name": "hop_int[22]" + }, + { + "name": "hop_int[21]" + }, + { + "name": "hop_int[20]" + }, + { + "name": "hop_int[19]" + }, + { + "name": "hop_int[18]" + }, + { + "name": "hop_int[17]" + }, + { + "name": "hop_int[16]" + }, + { + "name": "hop_int[15]" + }, + { + "name": "hop_int[14]" + }, + { + "name": "hop_int[13]" + }, + { + "name": "hop_int[12]" + }, + { + "name": "hop_int[11]" + }, + { + "name": "hop_int[10]" + }, + { + "name": "hop_int[9]" + }, + { + "name": "hop_int[8]" + }, + { + "name": "hop_int[7]" + }, + { + "name": "hop_int[6]" + }, + { + "name": "hop_int[5]" + }, + { + "name": "hop_int[4]" + }, + { + "name": "hop_int[3]" + }, + { + "name": "hop_int[2]" + }, + { + "name": "hop_int[1]" + }, + { + "name": "hop_int[0]" + } + ] + } + ] + } + ] + }, + { + "type": "VIO_V2", + "name": "u_vio_manual_ctrl_1", + "spec": "labtools_vio_v3", + "ipName": "vio", + "core_location": { + "user_chain": 1, + "slave_index": 5, + "bscan_switch_index": 0 + }, + "uuid": "3A4AD62DDC3A546EB5F2A986B350E154", + "pins": [ + { + "name": "probe_out0", + "id": 22, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 1, + "portIndex": 0, + "nets": [ + { + "name": "waveform_sel_1", + "isBus": true, + "subnets": [ + { + "name": "waveform_sel_1[1]" + }, + { + "name": "waveform_sel_1[0]" + } + ] + } + ] + }, + { + "name": "probe_out1", + "id": 23, + "type": "DATA", + "direction": "OUT", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 1, + "nets": [ + { + "name": "sweep_on_1", + "isBus": false + } + ] + }, + { + "name": "probe_out2", + "id": 24, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 31, + "portIndex": 2, + "nets": [ + { + "name": "freq_set_1", + "isBus": true, + "subnets": [ + { + "name": "freq_set_1[31]" + }, + { + "name": "freq_set_1[30]" + }, + { + "name": "freq_set_1[29]" + }, + { + "name": "freq_set_1[28]" + }, + { + "name": "freq_set_1[27]" + }, + { + "name": "freq_set_1[26]" + }, + { + "name": "freq_set_1[25]" + }, + { + "name": "freq_set_1[24]" + }, + { + "name": "freq_set_1[23]" + }, + { + "name": "freq_set_1[22]" + }, + { + "name": "freq_set_1[21]" + }, + { + "name": "freq_set_1[20]" + }, + { + "name": "freq_set_1[19]" + }, + { + "name": "freq_set_1[18]" + }, + { + "name": "freq_set_1[17]" + }, + { + "name": "freq_set_1[16]" + }, + { + "name": "freq_set_1[15]" + }, + { + "name": "freq_set_1[14]" + }, + { + "name": "freq_set_1[13]" + }, + { + "name": "freq_set_1[12]" + }, + { + "name": "freq_set_1[11]" + }, + { + "name": "freq_set_1[10]" + }, + { + "name": "freq_set_1[9]" + }, + { + "name": "freq_set_1[8]" + }, + { + "name": "freq_set_1[7]" + }, + { + "name": "freq_set_1[6]" + }, + { + "name": "freq_set_1[5]" + }, + { + "name": "freq_set_1[4]" + }, + { + "name": "freq_set_1[3]" + }, + { + "name": "freq_set_1[2]" + }, + { + "name": "freq_set_1[1]" + }, + { + "name": "freq_set_1[0]" + } + ] + } + ] + }, + { + "name": "probe_out3", + "id": 25, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 1, + "portIndex": 3, + "nets": [ + { + "name": "iq_sel_1", + "isBus": true, + "subnets": [ + { + "name": "iq_sel_1[1]" + }, + { + "name": "iq_sel_1[0]" + } + ] + } + ] + }, + { + "name": "probe_out4", + "id": 26, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 3, + "portIndex": 4, + "nets": [ + { + "name": "bb_rshift_1", + "isBus": true, + "subnets": [ + { + "name": "bb_rshift_1[3]" + }, + { + "name": "bb_rshift_1[2]" + }, + { + "name": "bb_rshift_1[1]" + }, + { + "name": "bb_rshift_1[0]" + } + ] + } + ] + } + ] + }, + { + "type": "VIO_V2", + "name": "u_vio_manual_ctrl_2", + "spec": "labtools_vio_v3", + "ipName": "vio", + "core_location": { + "user_chain": 1, + "slave_index": 6, + "bscan_switch_index": 0 + }, + "uuid": "09D2047C4D375ED8AEA61ABD4F4AF334", + "pins": [ + { + "name": "probe_out0", + "id": 27, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 1, + "portIndex": 0, + "nets": [ + { + "name": "waveform_sel_2", + "isBus": true, + "subnets": [ + { + "name": "waveform_sel_2[1]" + }, + { + "name": "waveform_sel_2[0]" + } + ] + } + ] + }, + { + "name": "probe_out1", + "id": 28, + "type": "DATA", + "direction": "OUT", + "isVector": false, + "leftIndex": 0, + "rightIndex": 0, + "portIndex": 1, + "nets": [ + { + "name": "sweep_on_2", + "isBus": false + } + ] + }, + { + "name": "probe_out2", + "id": 29, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 31, + "portIndex": 2, + "nets": [ + { + "name": "freq_set_2", + "isBus": true, + "subnets": [ + { + "name": "freq_set_2[31]" + }, + { + "name": "freq_set_2[30]" + }, + { + "name": "freq_set_2[29]" + }, + { + "name": "freq_set_2[28]" + }, + { + "name": "freq_set_2[27]" + }, + { + "name": "freq_set_2[26]" + }, + { + "name": "freq_set_2[25]" + }, + { + "name": "freq_set_2[24]" + }, + { + "name": "freq_set_2[23]" + }, + { + "name": "freq_set_2[22]" + }, + { + "name": "freq_set_2[21]" + }, + { + "name": "freq_set_2[20]" + }, + { + "name": "freq_set_2[19]" + }, + { + "name": "freq_set_2[18]" + }, + { + "name": "freq_set_2[17]" + }, + { + "name": "freq_set_2[16]" + }, + { + "name": "freq_set_2[15]" + }, + { + "name": "freq_set_2[14]" + }, + { + "name": "freq_set_2[13]" + }, + { + "name": "freq_set_2[12]" + }, + { + "name": "freq_set_2[11]" + }, + { + "name": "freq_set_2[10]" + }, + { + "name": "freq_set_2[9]" + }, + { + "name": "freq_set_2[8]" + }, + { + "name": "freq_set_2[7]" + }, + { + "name": "freq_set_2[6]" + }, + { + "name": "freq_set_2[5]" + }, + { + "name": "freq_set_2[4]" + }, + { + "name": "freq_set_2[3]" + }, + { + "name": "freq_set_2[2]" + }, + { + "name": "freq_set_2[1]" + }, + { + "name": "freq_set_2[0]" + } + ] + } + ] + }, + { + "name": "probe_out3", + "id": 30, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 1, + "portIndex": 3, + "nets": [ + { + "name": "iq_sel_2", + "isBus": true, + "subnets": [ + { + "name": "iq_sel_2[1]" + }, + { + "name": "iq_sel_2[0]" + } + ] + } + ] + }, + { + "name": "probe_out4", + "id": 31, + "type": "DATA", + "direction": "OUT", + "isVector": true, + "leftIndex": 0, + "rightIndex": 3, + "portIndex": 4, + "nets": [ + { + "name": "bb_rshift_2", + "isBus": true, + "subnets": [ + { + "name": "bb_rshift_2[3]" + }, + { + "name": "bb_rshift_2[2]" + }, + { + "name": "bb_rshift_2[1]" + }, + { + "name": "bb_rshift_2[0]" + } + ] + } + ] + } + ] + } + ] + } + ] + } +} \ No newline at end of file diff --git a/projects/cx9261a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/constrs_1/new/zc706_cx9261a_demo_physical.xdc b/projects/cx9261a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/constrs_1/new/zc706_cx9261a_demo_physical.xdc new file mode 100644 index 00000000..88a822da --- /dev/null +++ b/projects/cx9261a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/constrs_1/new/zc706_cx9261a_demo_physical.xdc @@ -0,0 +1,97 @@ +# zc706_cx9261a_demo + +## Physical Constraints Section + +# CX9261A Interface +set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS25} [get_ports cx9261a_osc_out ] +set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVCMOS25} [get_ports cx9261a_nrst ] + +set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVCMOS25} [get_ports cx9261a_spi_sclk ] +set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS25} [get_ports cx9261a_spi_csb ] +set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports cx9261a_spi_miso ] +set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS25} [get_ports cx9261a_spi_mosi ] + +set_property -dict {PACKAGE_PIN P29 IOSTANDARD LVCMOS25} [get_ports cx9261a_txnrx_trx1 ] +set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS25} [get_ports cx9261a_txnrx_trx2 ] +set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVCMOS25} [get_ports cx9261a_txnrx_rxfb ] +set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVCMOS25} [get_ports cx9261a_enable_trx1 ] +set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS25} [get_ports cx9261a_enable_trx2 ] +set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVCMOS25} [get_ports cx9261a_enable_rxfb ] + +set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS25} [get_ports cx9261a_tx1_fclk ] +set_property -dict {PACKAGE_PIN R25 IOSTANDARD LVCMOS25} [get_ports cx9261a_tx2_fclk ] +set_property -dict {PACKAGE_PIN AF22 IOSTANDARD LVCMOS25} [get_ports cx9261a_rx1_mclk ] +set_property -dict {PACKAGE_PIN AE22 IOSTANDARD LVCMOS25} [get_ports cx9261a_rx2_mclk ] +set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25} [get_ports cx9261a_rxfb_mclk ] + +set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS25} [get_ports cx9261a_tx1_frame ] +set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS25} [get_ports cx9261a_tx2_frame ] +set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports cx9261a_rx1_frame ] +set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVCMOS25} [get_ports cx9261a_rx2_frame ] +set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports cx9261a_rxfb_frame ] + +set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVCMOS25} [get_ports cx9261a_rxfb_rx_data[7]] +set_property -dict {PACKAGE_PIN R30 IOSTANDARD LVCMOS25} [get_ports cx9261a_rxfb_rx_data[6]] +set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS25} [get_ports cx9261a_rxfb_rx_data[5]] +set_property -dict {PACKAGE_PIN P24 IOSTANDARD LVCMOS25} [get_ports cx9261a_rxfb_rx_data[4]] +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports cx9261a_rxfb_rx_data[3]] +set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports cx9261a_rxfb_rx_data[2]] +set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports cx9261a_rxfb_rx_data[1]] +set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVCMOS25} [get_ports cx9261a_rxfb_rx_data[0]] + +set_property -dict {PACKAGE_PIN U25 IOSTANDARD LVCMOS25} [get_ports cx9261a_rxfb_tx_data[7]] +set_property -dict {PACKAGE_PIN V26 IOSTANDARD LVCMOS25} [get_ports cx9261a_rxfb_tx_data[6]] +set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports cx9261a_rxfb_tx_data[5]] +set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports cx9261a_rxfb_tx_data[4]] +set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVCMOS25} [get_ports cx9261a_rxfb_tx_data[3]] +set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVCMOS25} [get_ports cx9261a_rxfb_tx_data[2]] +set_property -dict {PACKAGE_PIN T30 IOSTANDARD LVCMOS25} [get_ports cx9261a_rxfb_tx_data[1]] +set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVCMOS25} [get_ports cx9261a_rxfb_tx_data[0]] + +set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS25} [get_ports cx9261a_rx1_fdd_data[7]] +set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports cx9261a_rx1_fdd_data[6]] +set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS25} [get_ports cx9261a_rx1_fdd_data[5]] +set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVCMOS25} [get_ports cx9261a_rx1_fdd_data[4]] +set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVCMOS25} [get_ports cx9261a_rx1_fdd_data[3]] +set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVCMOS25} [get_ports cx9261a_rx1_fdd_data[2]] +set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports cx9261a_rx1_fdd_data[1]] +set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVCMOS25} [get_ports cx9261a_rx1_fdd_data[0]] + +set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVCMOS25} [get_ports cx9261a_rx2_fdd_data[7]] +set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVCMOS25} [get_ports cx9261a_rx2_fdd_data[6]] +set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVCMOS25} [get_ports cx9261a_rx2_fdd_data[5]] +set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVCMOS25} [get_ports cx9261a_rx2_fdd_data[4]] +set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVCMOS25} [get_ports cx9261a_rx2_fdd_data[3]] +set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVCMOS25} [get_ports cx9261a_rx2_fdd_data[2]] +set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS25} [get_ports cx9261a_rx2_fdd_data[1]] +set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVCMOS25} [get_ports cx9261a_rx2_fdd_data[0]] + +set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVCMOS25} [get_ports cx9261a_tx1_fdd_data[7]] +set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVCMOS25} [get_ports cx9261a_tx1_fdd_data[6]] +set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVCMOS25} [get_ports cx9261a_tx1_fdd_data[5]] +set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVCMOS25} [get_ports cx9261a_tx1_fdd_data[4]] +set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVCMOS25} [get_ports cx9261a_tx1_fdd_data[3]] +set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVCMOS25} [get_ports cx9261a_tx1_fdd_data[2]] +set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVCMOS25} [get_ports cx9261a_tx1_fdd_data[1]] +set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVCMOS25} [get_ports cx9261a_tx1_fdd_data[0]] + +set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports cx9261a_tx2_fdd_data[7]] +set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVCMOS25} [get_ports cx9261a_tx2_fdd_data[6]] +set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVCMOS25} [get_ports cx9261a_tx2_fdd_data[5]] +set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVCMOS25} [get_ports cx9261a_tx2_fdd_data[4]] +set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVCMOS25} [get_ports cx9261a_tx2_fdd_data[3]] +set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVCMOS25} [get_ports cx9261a_tx2_fdd_data[2]] +set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports cx9261a_tx2_fdd_data[1]] +set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVCMOS25} [get_ports cx9261a_tx2_fdd_data[0]] + + +## Timing Assertions Section +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_mclk_delay/MCLK1] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_mclk_delay/MCLK2] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_mclk_delay/MCLK3] + +create_clock -period 6.25 -name RX1_MCLK_IN_N -waveform {0.000 3.125} [get_ports cx9261a_rx1_mclk ] +create_clock -period 6.25 -name RX2_MCLK_IN_P -waveform {0.000 3.125} [get_ports cx9261a_rx2_mclk ] +create_clock -period 6.25 -name RXFB_MCLK_IN -waveform {0.000 3.125} [get_ports cx9261a_rxfb_mclk] + +set_clock_groups -asynchronous -group [get_clocks RX1_MCLK_IN_N] -group [get_clocks RX2_MCLK_IN_P] -group [get_clocks RXFB_MCLK_IN] -group [get_clocks [list clk_fpga_0 clk_fpga_1 ]] \ No newline at end of file diff --git a/projects/cx9261a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/common/ad_rst.v b/projects/cx9261a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/common/ad_rst.v new file mode 100755 index 00000000..43109633 --- /dev/null +++ b/projects/cx9261a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/common/ad_rst.v @@ -0,0 +1,77 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module ad_rst ( + + // clock reset + + input rst_async, + input clk, + output rstn, + output reg rst); + + // internal registers + reg rst_async_d1 = 1'd1; + reg rst_async_d2 = 1'd1; + reg rst_sync = 1'd1; + reg rst_sync_d = 1'd1; + + // simple reset synchronizer + always @(posedge clk or posedge rst_async) begin + if (rst_async) begin + rst_async_d1 <= 1'b1; + rst_async_d2 <= 1'b1; + rst_sync <= 1'b1; + end else begin + rst_async_d1 <= 1'b0; + rst_async_d2 <= rst_async_d1; + rst_sync <= rst_async_d2; + end + end + + // two-stage synchronizer to prevent metastability on the falling edge + always @(posedge clk) begin + rst_sync_d <= rst_sync; + rst <= rst_sync_d; + end + + assign rstn = ~rst; + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/cx9261a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/common/up_axi.v b/projects/cx9261a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/common/up_axi.v new file mode 100755 index 00000000..40acb17b --- /dev/null +++ b/projects/cx9261a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/common/up_axi.v @@ -0,0 +1,239 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module up_axi #( + + parameter AXI_ADDRESS_WIDTH = 16) ( + + // reset and clocks + + input up_rstn, + input up_clk, + + // axi4 interface + + input up_axi_awvalid, + input [(AXI_ADDRESS_WIDTH-1):0] up_axi_awaddr, + output up_axi_awready, + input up_axi_wvalid, + input [31:0] up_axi_wdata, + input [ 3:0] up_axi_wstrb, + output up_axi_wready, + output up_axi_bvalid, + output [ 1:0] up_axi_bresp, + input up_axi_bready, + input up_axi_arvalid, + input [(AXI_ADDRESS_WIDTH-1):0] up_axi_araddr, + output up_axi_arready, + output up_axi_rvalid, + output [ 1:0] up_axi_rresp, + output [31:0] up_axi_rdata, + input up_axi_rready, + + // pcore interface + + output up_wreq, + output [(AXI_ADDRESS_WIDTH-3):0] up_waddr, + output [31:0] up_wdata, + input up_wack, + output up_rreq, + output [(AXI_ADDRESS_WIDTH-3):0] up_raddr, + input [31:0] up_rdata, + input up_rack); + + // internal registers + + reg up_axi_awready_int = 'd0; + reg up_axi_wready_int = 'd0; + reg up_axi_bvalid_int = 'd0; + reg up_wack_d = 'd0; + reg up_wsel = 'd0; + reg up_wreq_int = 'd0; + reg [(AXI_ADDRESS_WIDTH-3):0] up_waddr_int = 'd0; + reg [31:0] up_wdata_int = 'd0; + reg [ 4:0] up_wcount = 'd0; + reg up_axi_arready_int = 'd0; + reg up_axi_rvalid_int = 'd0; + reg [31:0] up_axi_rdata_int = 'd0; + reg up_rack_d = 'd0; + reg [31:0] up_rdata_d = 'd0; + reg up_rsel = 'd0; + reg up_rreq_int = 'd0; + reg [(AXI_ADDRESS_WIDTH-3):0] up_raddr_int = 'd0; + reg [ 4:0] up_rcount = 'd0; + + // internal signals + + wire up_wack_s; + wire up_rack_s; + wire [31:0] up_rdata_s; + + // write channel interface + + assign up_axi_awready = up_axi_awready_int; + assign up_axi_wready = up_axi_wready_int; + assign up_axi_bvalid = up_axi_bvalid_int; + assign up_axi_bresp = 2'd0; + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_axi_awready_int <= 'd0; + up_axi_wready_int <= 'd0; + up_axi_bvalid_int <= 'd0; + end else begin + if (up_axi_awready_int == 1'b1) begin + up_axi_awready_int <= 1'b0; + end else if (up_wack_s == 1'b1) begin + up_axi_awready_int <= 1'b1; + end + if (up_axi_wready_int == 1'b1) begin + up_axi_wready_int <= 1'b0; + end else if (up_wack_s == 1'b1) begin + up_axi_wready_int <= 1'b1; + end + if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin + up_axi_bvalid_int <= 1'b0; + end else if (up_wack_d == 1'b1) begin + up_axi_bvalid_int <= 1'b1; + end + end + end + + assign up_wreq = up_wreq_int; + assign up_waddr = up_waddr_int; + assign up_wdata = up_wdata_int; + assign up_wack_s = (up_wcount == 5'h1f) ? 1'b1 : (up_wcount[4] & up_wack); + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_wack_d <= 'd0; + up_wsel <= 'd0; + up_wreq_int <= 'd0; + up_waddr_int <= 'd0; + up_wdata_int <= 'd0; + up_wcount <= 'd0; + end else begin + up_wack_d <= up_wack_s; + if (up_wsel == 1'b1) begin + if ((up_axi_bready == 1'b1) && (up_axi_bvalid_int == 1'b1)) begin + up_wsel <= 1'b0; + end + up_wreq_int <= 1'b0; + end else begin + up_wsel <= up_axi_awvalid & up_axi_wvalid; + up_wreq_int <= up_axi_awvalid & up_axi_wvalid; + up_waddr_int <= up_axi_awaddr[(AXI_ADDRESS_WIDTH-1):2]; + up_wdata_int <= up_axi_wdata; + end + if (up_wack_s == 1'b1) begin + up_wcount <= 5'h00; + end else if (up_wcount[4] == 1'b1) begin + up_wcount <= up_wcount + 1'b1; + end else if (up_wreq_int == 1'b1) begin + up_wcount <= 5'h10; + end + end + end + + // read channel interface + + assign up_axi_arready = up_axi_arready_int; + assign up_axi_rvalid = up_axi_rvalid_int; + assign up_axi_rdata = up_axi_rdata_int; + assign up_axi_rresp = 2'd0; + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_axi_arready_int <= 'd0; + up_axi_rvalid_int <= 'd0; + up_axi_rdata_int <= 'd0; + end else begin + if (up_axi_arready_int == 1'b1) begin + up_axi_arready_int <= 1'b0; + end else if (up_rack_s == 1'b1) begin + up_axi_arready_int <= 1'b1; + end + if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin + up_axi_rvalid_int <= 1'b0; + up_axi_rdata_int <= 32'd0; + end else if (up_rack_d == 1'b1) begin + up_axi_rvalid_int <= 1'b1; + up_axi_rdata_int <= up_rdata_d; + end + end + end + + assign up_rreq = up_rreq_int; + assign up_raddr = up_raddr_int; + assign up_rack_s = (up_rcount == 5'h1f) ? 1'b1 : (up_rcount[4] & up_rack); + assign up_rdata_s = (up_rcount == 5'h1f) ? {2{16'hdead}} : up_rdata; + + always @(posedge up_clk) begin + if (up_rstn == 1'b0) begin + up_rack_d <= 'd0; + up_rdata_d <= 'd0; + up_rsel <= 'd0; + up_rreq_int <= 'd0; + up_raddr_int <= 'd0; + up_rcount <= 'd0; + end else begin + up_rack_d <= up_rack_s; + up_rdata_d <= up_rdata_s; + if (up_rsel == 1'b1) begin + if ((up_axi_rready == 1'b1) && (up_axi_rvalid_int == 1'b1)) begin + up_rsel <= 1'b0; + end + up_rreq_int <= 1'b0; + end else begin + up_rsel <= up_axi_arvalid; + up_rreq_int <= up_axi_arvalid; + up_raddr_int <= up_axi_araddr[(AXI_ADDRESS_WIDTH-1):2]; + end + if (up_rack_s == 1'b1) begin + up_rcount <= 5'h00; + end else if (up_rcount[4] == 1'b1) begin + up_rcount <= up_rcount + 1'b1; + end else if (up_rreq_int == 1'b1) begin + up_rcount <= 5'h10; + end + end + end + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/cx9261a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci b/projects/cx9261a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci new file mode 100644 index 00000000..9e6482ce --- /dev/null +++ b/projects/cx9261a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_auto_pc_0/system_bd_auto_pc_0.xci @@ -0,0 +1,302 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "system_bd_auto_pc_0", + "cell_name": "axi_interconnect/s00_couplers/auto_pc", + "component_reference": "xilinx.com:ip:axi_protocol_converter:2.1", + "ip_revision": "31", + "gen_directory": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0", + "parameters": { + "component_parameters": { + "SI_PROTOCOL": [ { "value": "AXI3", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], + "MI_PROTOCOL": [ { "value": "AXI4LITE", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], + "TRANSLATION_MODE": [ { "value": "2", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ADDR_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ID_WIDTH": [ { "value": "12", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Component_Name": [ { "value": "system_bd_auto_pc_0", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ], + "C_M_AXI_PROTOCOL": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXI_PROTOCOL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_IGNORE_ID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_ID_WIDTH": [ { "value": "12", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_SUPPORTS_WRITE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_SUPPORTS_READ": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TRANSLATION_MODE": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "zynq" } ], + "BASE_BOARD_PART": [ { "value": "xilinx.com:zc706:part0:1.4" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7z045" } ], + "NEXTGEN_VERSAL": [ { "value": "0" } ], + "PACKAGE": [ { "value": "ffg900" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "31" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_auto_pc_0" } ], + "SELECTEDSIMMODEL": [ { "value": "rtl" } ], + "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SWVERSION": [ { "value": "2024.1" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "aclk": [ { "direction": "in" } ], + "aresetn": [ { "direction": "in" } ], + "s_axi_awid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ], + "s_axi_awaddr": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ], + "s_axi_awlen": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awburst": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x1" } ], + "s_axi_awlock": [ { "direction": "in", "size_left": "1", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awcache": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_awvalid": [ { "direction": "in", "driver_value": "0x0" } ], + "s_axi_awready": [ { "direction": "out" } ], + "s_axi_wid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ], + "s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0x00000000" } ], + "s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0xF" } ], + "s_axi_wlast": [ { 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"is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ], + "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "aresetn" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/projects/cx9261a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_gpio_0_0/system_bd_axi_gpio_0_0.xci b/projects/cx9261a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_gpio_0_0/system_bd_axi_gpio_0_0.xci new file mode 100644 index 00000000..23e2193f --- /dev/null +++ b/projects/cx9261a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_gpio_0_0/system_bd_axi_gpio_0_0.xci @@ -0,0 +1,376 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "system_bd_axi_gpio_0_0", + "cell_name": "axi_gpio_hop", + "component_reference": "xilinx.com:ip:axi_gpio:2.0", + "ip_revision": "33", + "gen_directory": "../../../../../../zc706_cx9261a_demo.gen/sources_1/bd/system_bd/ip/system_bd_axi_gpio_0_0", + "parameters": { + "component_parameters": { + "C_TRI_DEFAULT": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "C_GPIO_WIDTH": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "C_GPIO2_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "C_IS_DUAL": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "C_ALL_INPUTS": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "C_TRI_DEFAULT_2": [ { "value": "0xFFFFFFFF", "resolve_type": "user", "format": "bitString", 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"slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "s_axi_aresetn" } ] + } + }, + "IP2INTC_IRQ": { + "vlnv": "xilinx.com:signal:interrupt:1.0", + "abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0", + "mode": "master", + "parameters": { + "SENSITIVITY": [ { "value": "LEVEL_HIGH", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "PortWidth": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "INTERRUPT": [ { "physical_name": "ip2intc_irpt" } ] + } + }, + "GPIO": { + "vlnv": "xilinx.com:interface:gpio:1.0", + "abstraction_type": "xilinx.com:interface:gpio_rtl:1.0", + "mode": "master", + "parameters": { + "BOARD.ASSOCIATED_PARAM": [ { "value": "GPIO_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ] + }, + "port_maps": { + "TRI_I": [ { "physical_name": "gpio_io_i" } ] + } + } + }, + "memory_maps": { + "S_AXI": { + "display_name": "S_AXI_MEM", + "description": "Memory Map for S_AXI", + "address_blocks": { + "Reg": { + "base_address": "0", + "range": "4096", + "display_name": "Reg", + "description": "Register Block", + "usage": "register", + "access": "read-write", + "registers": { + "GPIO_DATA": { + "address_offset": "0x0", + "size": 1, + "display_name": "Channel_1_GPIO_DATA", + "description": "Channel-1 AXI GPIO Data register", + "is_volatile": true, + "access": "read-write", + "reset_value": "0x0", + "fields": { + "CH1_DATA": { + "bit_offset": 0, + "bit_width": 1, + "display_name": "Channel_1_GPIO_DATA", + "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n", + "is_volatile": true, + "access": "read-write" + } + } + }, + "GPIO_TRI": { + "address_offset": "0x4", + "size": 1, + "display_name": "Channel_1_GPIO_TRI", + "description": "Channel-1 AXI GPIO 3-State Control register", + "is_volatile": true, + "access": "read-write", + "reset_value": "0x0", + "fields": { + "CH1_TRI": { + "bit_offset": 0, + "bit_width": 1, + "display_name": "Channel_1_GPIO_DATA", + "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n", + "is_volatile": true, + "access": "read-write" + } + } + }, + "GPIO2_DATA": { + "address_offset": "0x8", + "size": 32, + "display_name": "Channel_2_GPIO_DATA", + "description": "Channel-2 AXI GPIO Data register", + "is_volatile": true, + "access": "read-write", + "reset_value": "0x0", + "fields": { + "CH2_DATA": { + "bit_offset": 0, + "bit_width": 32, + "display_name": "Channel_2_GPIO_DATA", + "description": "AXI GPIO Data Register.\nFor each I/O bit programmed as input\n R - Reads value on the input pin.\n W - No effect.\nFor each I/O bit programmed as output\n R - Reads value on GPIO_O pins\n W - Writes value to the corresponding AXI GPIO \n data register bit and output pin\n", + "is_volatile": true, + "access": "read-write" + } + } + }, + "GPIO2_TRI": { + "address_offset": "0xC", + "size": 32, + "display_name": "Channel_2_GPIO_TRI", + "description": "Channel-2 AXI GPIO 3-State Control register", + "is_volatile": true, + "access": "read-write", + "reset_value": "0x0", + "fields": { + "CH2_TRI": { + "bit_offset": 0, + "bit_width": 32, + "display_name": "Channel_2_GPIO_DATA", + "description": "AXI GPIO 3-State Control Register\nEach I/O pin of the AXI GPIO is individually programmable as an input or output For each of the bits 0 - I/O pin configured as output 1 - I/O pin configured as input\n", + "is_volatile": true, + "access": "read-write" + } + } + }, + "GIER": { + "address_offset": "0x11C", + "size": 32, + "display_name": "Global_Interrupt_Enable register", + "description": "Global_Interrupt_Enable register", + "is_volatile": true, + "access": "read-write", + "reset_value": "0x0", + "fields": { + "INT_EN": { + "bit_offset": 31, + "bit_width": 1, + "display_name": "Global_Interrupt_Enable", + "description": "Master enable for the device interrupt output\n 0 - Disabled\n 1 - Enabled\n", + "is_volatile": true, + "access": "read-write" + } + } + }, + "IP_IER": { + "address_offset": "0x128", + "size": 32, + "display_name": "IP Interrupt Enable register", + "description": "IP Interrupt Enable register", + "is_volatile": true, + "access": "read-write", + "reset_value": "0x0", + "fields": { + "CH1_INT_EN": { + "bit_offset": 0, + "bit_width": 1, + "display_name": "Channel_1_Interrupt_Enable", + "description": "Enable Channel 1 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n", + "is_volatile": true, + "access": "read-write" + }, + "CH2_INT_EN": { + "bit_offset": 1, + "bit_width": 1, + "display_name": "Channel_2_Interrupt_Enable", + "description": "Enable Channel 2 Interrupt\n 0 - Disabled (masked)\n 1 - Enabled\n", + "is_volatile": true, + "access": "read-write" + } + } + }, + "IP_ISR": { + "address_offset": "0x120", + "size": 32, + "display_name": "IP Interrupt Status register", + "description": "IP Interrupt Status register", + "is_volatile": true, + "access": "read-write", + "reset_value": "0x0", + "fields": { + "CH1_INT_S": { + "bit_offset": 0, + "bit_width": 1, + "display_name": "Channel_1_Interrupt_Status", + "description": "Channel 1 Interrupt Status\n 0 - No Channel 1 input interrupt\n 1 - Channel 1 input interrupt\n", + "is_volatile": true, + "access": "read-write" + }, + "CH2_INT_S": { + "bit_offset": 1, + "bit_width": 1, + "display_name": "Channel_2_Interrupt_Status", + "description": "Channel 2 Interrupt Status\n 0 - No Channel 2 input interrupt\n 1 - Channel 2 input interrupt\n", + "is_volatile": true, + "access": "read-write" + } + } + } + } + } + } + } + } + } + } +} \ No newline at end of file diff --git a/projects/cx9261a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_interconnect_0_0/system_bd_axi_interconnect_0_0.xci b/projects/cx9261a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_interconnect_0_0/system_bd_axi_interconnect_0_0.xci new file mode 100644 index 00000000..cb6496cc --- /dev/null +++ b/projects/cx9261a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_axi_interconnect_0_0/system_bd_axi_interconnect_0_0.xci @@ -0,0 +1,353 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + 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"value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "s_axi_aclk" } ] + } + }, + "s_axi_aresetn": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "s_axi_aresetn" } ] + } + }, + "spi_engine_ctrl": { + "vlnv": "analog.com:interface:spi_engine_ctrl:1.0", + "abstraction_type": "analog.com:interface:spi_engine_ctrl_rtl:1.0", + "mode": "master", + "port_maps": { + "CMD_READY": [ { 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"value_permission": "bd_and_user", "resolve_type": "generated", "format": "float", "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "system_bd_processing_system7_0_0_FCLK_CLK0", "value_src": "default_prop", "value_permission": "bd_and_user", "resolve_type": "generated", "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "s_axi_aclk" } ] + } + }, + "spi_engine_offload_ctrl0_s_axi_signal_reset": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd_and_user", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "s_axi_aresetn" } ] + } + } + }, + "memory_maps": { + "s_axi": { + "address_blocks": { + "axi_lite": { + "base_address": "0", + "range": "65536" + } + } + } + } + } + } +} \ No newline at end of file diff --git a/projects/cx9261a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/ps7_parameters.xml b/projects/cx9261a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/ps7_parameters.xml new file mode 100644 index 00000000..7b35b68d --- /dev/null +++ b/projects/cx9261a/zc706_cx9261a_demo/zc706_cx9261a_demo.srcs/sources_1/bd/system_bd/ip/system_bd_processing_system7_0_0/ps7_parameters.xml @@ -0,0 +1,643 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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"PCW_DDR_RAM_BASEADDR": [ { "value": "0x00100000", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_DDR_RAM_HIGHADDR": [ { "value": "0x3FFFFFFF", "value_src": "user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_UART0_BASEADDR": [ { "value": "0xE0000000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_UART0_HIGHADDR": [ { "value": "0xE0000FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_UART1_BASEADDR": [ { "value": "0xE0001000", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_UART1_HIGHADDR": [ { "value": "0xE0001FFF", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_I2C0_BASEADDR": [ { "value": "0xE0004000", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_I2C0_HIGHADDR": [ { "value": "0xE0004FFF", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_I2C1_BASEADDR": [ { "value": "0xE0005000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_I2C1_HIGHADDR": [ { "value": "0xE0005FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SPI0_BASEADDR": [ { "value": "0xE0006000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SPI0_HIGHADDR": [ { "value": "0xE0006FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SPI1_BASEADDR": [ { "value": "0xE0007000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_SPI1_HIGHADDR": [ { "value": "0xE0007FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_CAN0_BASEADDR": [ { "value": "0xE0008000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_CAN0_HIGHADDR": [ { "value": "0xE0008FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_CAN1_BASEADDR": [ { "value": "0xE0009000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_CAN1_HIGHADDR": [ { "value": "0xE0009FFF", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_GPIO_BASEADDR": [ { "value": "0xE000A000", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_GPIO_HIGHADDR": [ { "value": "0xE000AFFF", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_ENET0_BASEADDR": [ { "value": "0xE000B000", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_ENET0_HIGHADDR": [ { "value": "0xE000BFFF", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_ENET1_BASEADDR": [ { "value": "0xE000C000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_ENET1_HIGHADDR": [ { "value": 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{ "value": "0xE0103fff", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_TTC0_BASEADDR": [ { "value": "0xE0104000", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_TTC0_HIGHADDR": [ { "value": "0xE0104fff", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "PCW_TTC1_BASEADDR": [ { "value": "0xE0105000", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_TTC1_HIGHADDR": [ { "value": "0xE0105fff", "resolve_type": "user", "format": "bitString", "enabled": false, "usage": "all" } ], + "PCW_FCLK_CLK0_BUF": [ { "value": "TRUE", "resolve_type": "user", "usage": "all" } ], + "PCW_FCLK_CLK1_BUF": [ { "value": "TRUE", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_FCLK_CLK2_BUF": [ { "value": "FALSE", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_FCLK_CLK3_BUF": [ { "value": "FALSE", "resolve_type": "user", "enabled": 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"resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_MODEM_UART0": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_MODEM_UART1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_TTC0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_TTC1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_WDT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_TRACE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_USB0": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_USB1": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_DQ_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_DQS_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_DM_WIDTH": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_MIO_PRIMITIVE": [ { "value": "54", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CLK0_PORT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CLK1_PORT": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CLK2_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CLK3_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_RST0_PORT": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_RST1_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_RST2_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_RST3_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CLKTRIG0_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CLKTRIG1_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CLKTRIG2_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_EN_CLKTRIG3_PORT": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_P2F_DMAC_ABORT_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC2_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC3_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC4_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC5_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC6_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_DMAC7_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_SMC_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_QSPI_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_P2F_CTI_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_GPIO_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_P2F_USB0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_P2F_ENET0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_P2F_SDIO0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_P2F_I2C0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_P2F_SPI0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_UART0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_CAN0_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_USB1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_ENET1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_SDIO1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_I2C1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_SPI1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_P2F_UART1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_P2F_CAN1_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "PCW_IRQ_F2P_INTR": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_IRQ_F2P_MODE": [ { "value": "DIRECT", "resolve_type": "user", "usage": "all" } ], + "PCW_CORE0_FIQ_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_CORE0_IRQ_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_CORE1_FIQ_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_CORE1_IRQ_INTR": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_VALUE_SILVERSION": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_GP0_EN_MODIFIABLE_TXN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_GP1_EN_MODIFIABLE_TXN": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PCW_IMPORT_BOARD_PRESET": [ { "value": "None", "resolve_type": "user", "usage": "all" } ], + "PCW_PERIPHERAL_BOARD_PRESET": [ { "value": "part0", "resolve_type": "user", "usage": "all" } ], + "PCW_PRESET_BANK0_VOLTAGE": [ { "value": "LVCMOS 1.8V", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_PRESET_BANK1_VOLTAGE": [ { "value": "LVCMOS 1.8V", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_ENABLE": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_ADV_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_MEMORY_TYPE": [ { "value": "DDR 3", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_ECC": [ { "value": "Disabled", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UIPARAM_DDR_BUS_WIDTH": [ { "value": "32 Bit", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_BL": [ { "value": "8", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_HIGH_TEMP": [ { "value": "Normal (0-85)", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_PARTNO": [ { "value": "Custom", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_DRAM_WIDTH": [ { "value": "8 Bits", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_DEVICE_CAPACITY": [ { "value": "2048 MBits", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_SPEED_BIN": [ { "value": "DDR3_1066F", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_TRAIN_READ_GATE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_TRAIN_DATA_EYE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_CLOCK_STOP_EN": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_UIPARAM_DDR_USE_INTERNAL_VREF": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_DDR_PRIORITY_WRITEPORT_0": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_PRIORITY_WRITEPORT_2": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_PRIORITY_READPORT_0": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_PRIORITY_READPORT_2": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_PORT0_HPR_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_PORT1_HPR_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_PORT2_HPR_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_PORT3_HPR_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_HPRLPR_QUEUE_PARTITION": [ { "value": "HPR(0)/LPR(32)", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL": [ { "value": "2", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL": [ { "value": "15", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL": [ { "value": "2", "resolve_type": "user", "format": "float", "enabled": false, "usage": "all" } ], + "PCW_NAND_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NAND_NAND_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_NOR_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_GRP_CS0_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_GRP_CS0_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_GRP_CS1_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_GRP_CS1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_GRP_SRAM_INT_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_NOR_GRP_SRAM_INT_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_QSPI_GRP_SS1_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_QSPI_GRP_SS1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_DUAL_STACK_QSPI_DATA_MODE": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_ENET1_GRP_MDIO_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_ENET1_GRP_MDIO_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SD0_PERIPHERAL_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_SD0_SD0_IO": [ { "value": "MIO 40 .. 45", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_SD0_GRP_CD_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_SD0_GRP_CD_IO": [ { "value": "MIO 14", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_SD0_GRP_WP_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_SD0_GRP_WP_IO": [ { "value": "MIO 15", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_SD0_GRP_POW_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_SD0_GRP_POW_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SD1_GRP_CD_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SD1_GRP_CD_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SD1_GRP_POW_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SD1_GRP_POW_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UART0_GRP_FULL_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_UART0_GRP_FULL_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SPI0_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_SPI0_SPI0_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SPI0_GRP_SS1_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SPI0_GRP_SS1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SPI1_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_SPI1_SPI1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SPI1_GRP_SS1_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_SPI1_GRP_SS1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_CAN0_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_CAN0_CAN0_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_CAN1_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_CAN1_CAN1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_TRACE_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_TRACE_TRACE_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_TRACE_GRP_4BIT_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_TRACE_GRP_4BIT_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_TRACE_GRP_16BIT_ENABLE": [ { "value": "0", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_TRACE_GRP_16BIT_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_TRACE_INTERNAL_WIDTH": [ { "value": "2", "resolve_type": "user", "usage": "all" } ], + "PCW_WDT_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_WDT_WDT_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_PJTAG_PERIPHERAL_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_PJTAG_PJTAG_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_USB1_RESET_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_USB1_RESET_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C0_RESET_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_I2C0_RESET_IO": [ { "value": "MIO 46", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_I2C1_PERIPHERAL_ENABLE": [ { "value": "0", "resolve_type": "user", "usage": "all" } ], + "PCW_I2C1_I2C1_IO": [ { "value": "", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C_RESET_ENABLE": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_I2C_RESET_SELECT": [ { "value": "Share reset pin", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "PCW_I2C1_RESET_ENABLE": [ { "value": "0", "value_src": "user", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "PCW_I2C1_RESET_IO": [ { "value": "