From a9c307dab31ffe70a9fde31b7a3b6c27588810e4 Mon Sep 17 00:00:00 2001 From: Josh Gao Date: Fri, 11 Oct 2024 19:22:14 +0800 Subject: [PATCH] update ad9361 mapping cmos mode works fine, but the timing of lvds mode needs more test --- .../sim_1/new/tb_ad9361_trx_cmos_dual.v | 109 ++++++ .../sim_1/new/tb_ad9361_trx_cmos_single.v | 94 ++++++ .../sim_1/new/tb_ad9361_trx_lvds_dual.v | 123 +++++++ .../sim_1/new/tb_ad9361_trx_lvds_single.v | 105 ++++++ .../sources_1/new/ad9361_rx_map_cmos_dual.v | 150 +++++---- .../sources_1/new/ad9361_rx_map_cmos_single.v | 107 ++++-- .../sources_1/new/ad9361_rx_map_lvds_dual.v | 315 ++++++++---------- .../sources_1/new/ad9361_rx_map_lvds_single.v | 182 ++++++++++ .../sources_1/new/ad9361_tx_map_cmos_dual.v | 50 +-- .../sources_1/new/ad9361_tx_map_cmos_single.v | 46 +-- .../sources_1/new/ad9361_tx_map_lvds_dual.v | 144 ++++---- .../sources_1/new/ad9361_tx_map_lvds_single.v | 187 +++++++++++ .../synth_1/ad9361_rx_map_cmos_dual.dcp | 3 + .../ad9361_mapping/ad9361_mapping.xpr | 68 +++- 14 files changed, 1288 insertions(+), 395 deletions(-) create mode 100644 modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_cmos_dual.v create mode 100644 modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_cmos_single.v create mode 100644 modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_lvds_dual.v create mode 100644 modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_lvds_single.v create mode 100644 modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_lvds_single.v create mode 100644 modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_lvds_single.v create mode 100755 modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/utils_1/imports/synth_1/ad9361_rx_map_cmos_dual.dcp diff --git a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_cmos_dual.v b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_cmos_dual.v new file mode 100644 index 00000000..f6492c8e --- /dev/null +++ b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_cmos_dual.v @@ -0,0 +1,109 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 09/27/2024 04:42:03 PM +// Design Name: +// Module Name: tb_ad9361_trx_cmos_dual +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb_ad9361_trx_cmos_dual; + +reg clk_2x_in = 'b0; +reg clk_in_rst = 'b0; +reg data_clk = 'b0; +reg data_clk_rst = 'b0; +reg [11:0] tx_ch1_i = 'b0; +reg [11:0] tx_ch1_q = 'b0; +reg [11:0] tx_ch2_i = 'b0; +reg [11:0] tx_ch2_q = 'b0; +wire [11:0] rx_ch1_i; +wire [11:0] rx_ch1_q; +wire [11:0] rx_ch2_i; +wire [11:0] rx_ch2_q; + +wire clk_out; +wire tx_frame; +wire [11:0] tx_data; + +ad9361_tx_map_cmos_dual dut_tx +( + .clk_2x_in (clk_2x_in ), + .clk_in_rst (clk_in_rst ), + + .tx_data_clk (data_clk ), + .tx_data_clk_rst(data_clk_rst ), + + .tx_ch1_i (tx_ch1_i ), + .tx_ch1_q (tx_ch1_q ), + .tx_ch2_i (tx_ch2_i ), + .tx_ch2_q (tx_ch2_q ), + + .clk_out (clk_out ), + .tx_frame (tx_frame ), + .tx_data (tx_data ) +); + +ad9361_rx_map_cmos_dual dut_rx +( + .clk_2x_in (clk_2x_in ), + .clk_in_rst (clk_in_rst ), + + .rx_data_clk (data_clk ), // sync to output data + .rx_data_clk_rst(data_clk_rst ), + + .rx_fifo_rst (1'b0 ), // async fifo reset + + .rx_frame (tx_frame ), + .rx_data (tx_data ), + + .rx_ch1_i (rx_ch1_i ), + .rx_ch1_q (rx_ch1_q ), + .rx_ch2_i (rx_ch2_i ), + .rx_ch2_q (rx_ch2_q ) +); + +initial begin + clk_in_rst = 1'b1; + data_clk_rst = 1'b1; + #102 + clk_in_rst = 'b0; + #333 + data_clk_rst = 'b0; +end + +always #20 clk_2x_in = ~clk_2x_in; + +always @(posedge clk_2x_in) begin + #7 data_clk <= ~data_clk; +end + +always @(posedge data_clk) begin + if (data_clk_rst) begin + tx_ch1_i <= 'b0; + tx_ch1_q <= 'b0; + tx_ch2_i <= 'b0; + tx_ch2_q <= 'b0; + end + else begin + tx_ch1_i <= tx_ch1_i + 3'd1; + tx_ch1_q <= tx_ch1_q + 3'd2; + tx_ch2_i <= tx_ch2_i + 3'd3; + tx_ch2_q <= tx_ch2_q + 3'd4; + end +end + +endmodule diff --git a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_cmos_single.v b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_cmos_single.v new file mode 100644 index 00000000..72af1e3a --- /dev/null +++ b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_cmos_single.v @@ -0,0 +1,94 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 09/27/2024 04:34:43 PM +// Design Name: +// Module Name: tb_ad9361_trx_cmos_single +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb_ad9361_trx_cmos_single; + +reg clk_in = 'b0; +reg clk_in_rst = 'b0; +wire data_clk; +reg data_clk_rst = 'b0; +reg [11:0] tx_data_i = 'b0; +reg [11:0] tx_data_q = 'b0; +wire [11:0] rx_data_i; +wire [11:0] rx_data_q; + +wire clk_out; +wire tx_frame; +wire [11:0] tx_data; + +ad9361_tx_map_cmos_single dut_tx +( + .clk_in (clk_in ), + .clk_in_rst (clk_in_rst ), + + .tx_data_clk (data_clk ), + .tx_data_clk_rst(data_clk_rst ), + + .tx_data_i (tx_data_i ), + .tx_data_q (tx_data_q ), + + .clk_out (clk_out ), + .tx_frame (tx_frame ), + .tx_data (tx_data ) +); + +ad9361_rx_map_cmos_single dut_rx +( + .clk_in (clk_in ), + .clk_in_rst (clk_in_rst ), + + .rx_data_clk (data_clk ), + .rx_data_clk_rst(data_clk_rst ), + + .rx_fifo_rst (1'b0 ), + + .rx_frame (tx_frame ), + .rx_data (tx_data ), + + .rx_data_i (rx_data_i ), + .rx_data_q (rx_data_q ) +); + +initial begin + clk_in_rst = 1'b1; + data_clk_rst = 1'b1; + #102 + clk_in_rst = 'b0; + #333 + data_clk_rst = 'b0; +end + +always #20 clk_in = ~clk_in; +assign #7 data_clk = clk_in; + +always @(posedge data_clk) begin + if (data_clk_rst) begin + tx_data_i <= 'b0; + tx_data_q <= 'b0; + end + else begin + tx_data_i <= tx_data_i + 2'd1; + tx_data_q <= tx_data_q + 2'd2; + end +end + +endmodule diff --git a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_lvds_dual.v b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_lvds_dual.v new file mode 100644 index 00000000..75c69c51 --- /dev/null +++ b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_lvds_dual.v @@ -0,0 +1,123 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 09/27/2024 05:23:01 PM +// Design Name: +// Module Name: tb_ad9361_trx_lvds_dual +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb_ad9361_trx_lvds_dual; + +reg clk_4x_in = 'b0; +reg clk_in_rst = 'b0; +reg data_clk = 'b0; +reg data_clk_rst = 'b0; +reg [11:0] tx_ch1_i = 'b0; +reg [11:0] tx_ch1_q = 'b0; +reg [11:0] tx_ch2_i = 'b0; +reg [11:0] tx_ch2_q = 'b0; +wire [11:0] rx_ch1_i; +wire [11:0] rx_ch1_q; +wire [11:0] rx_ch2_i; +wire [11:0] rx_ch2_q; + +wire clk_out_p; +wire clk_out_n; +wire tx_frame_p; +wire tx_frame_n; +wire [5:0] tx_data_p; +wire [5:0] tx_data_n; + +ad9361_tx_map_lvds_dual dut_tx +( + .clk_4x_in (clk_4x_in ), + .clk_in_rst (clk_in_rst ), + + .tx_data_clk (data_clk ), + .tx_data_clk_rst(data_clk_rst ), + + .tx_ch1_i (tx_ch1_i ), + .tx_ch1_q (tx_ch1_q ), + .tx_ch2_i (tx_ch2_i ), + .tx_ch2_q (tx_ch2_q ), + + .clk_out_p (clk_out_p ), + .clk_out_n (clk_out_n ), + .tx_frame_p (tx_frame_p ), + .tx_frame_n (tx_frame_n ), + .tx_data_p (tx_data_p ), + .tx_data_n (tx_data_n ) +); + +ad9361_rx_map_lvds_dual dut_rx +( + .clk_4x_in (clk_4x_in ), + .clk_in_rst (clk_in_rst ), + + .rx_data_clk (data_clk ), + .rx_data_clk_rst(data_clk_rst ), + + .rx_fifo_rst (1'b0 ), + + .rx_frame_p (tx_frame_p ), + .rx_frame_n (tx_frame_n ), + .rx_data_p (tx_data_p ), + .rx_data_n (tx_data_n ), + + .rx_ch1_i (rx_ch1_i ), + .rx_ch1_q (rx_ch1_q ), + .rx_ch2_i (rx_ch2_i ), + .rx_ch2_q (rx_ch2_q ) +); + +initial begin + clk_in_rst = 1'b1; + data_clk_rst = 1'b1; + #102 + clk_in_rst = 'b0; + #333 + data_clk_rst = 'b0; +end + +reg clk_2x_in = 'b0; + +always #40 clk_4x_in = ~clk_4x_in; + +always @(posedge clk_4x_in) begin + clk_2x_in <= ~clk_2x_in; +end + +always @(posedge clk_2x_in) begin + #7 data_clk <= ~data_clk; +end + +always @(posedge data_clk) begin + if (data_clk_rst) begin + tx_ch1_i <= 'b0; + tx_ch1_q <= 'b0; + tx_ch2_i <= 'b0; + tx_ch2_q <= 'b0; + end + else begin + tx_ch1_i <= tx_ch1_i + 3'd1; + tx_ch1_q <= tx_ch1_q + 3'd2; + tx_ch2_i <= tx_ch2_i + 3'd3; + tx_ch2_q <= tx_ch2_q + 3'd4; + end +end + +endmodule diff --git a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_lvds_single.v b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_lvds_single.v new file mode 100644 index 00000000..76e6db9b --- /dev/null +++ b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sim_1/new/tb_ad9361_trx_lvds_single.v @@ -0,0 +1,105 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 09/27/2024 03:43:52 PM +// Design Name: +// Module Name: tb_ad9361_trx_lvds_single +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module tb_ad9361_trx_lvds_single; + +reg clk_2x_in = 'b0; +reg clk_in_rst = 'b0; +reg data_clk = 'b0; +reg data_clk_rst = 'b0; +reg [11:0] tx_data_i = 'b0; +reg [11:0] tx_data_q = 'b0; +wire [11:0] rx_data_i; +wire [11:0] rx_data_q; + +wire clk_out_p; +wire clk_out_n; +wire tx_frame_p; +wire tx_frame_n; +wire [5:0] tx_data_p; +wire [5:0] tx_data_n; + +ad9361_tx_map_lvds_single dut_tx +( + .clk_2x_in (clk_2x_in ), + .clk_in_rst (clk_in_rst ), + + .tx_data_clk (data_clk ), + .tx_data_clk_rst(data_clk_rst ), + + .tx_data_i (tx_data_i ), + .tx_data_q (tx_data_q ), + + .clk_out_p (clk_out_p ), + .clk_out_n (clk_out_n ), + .tx_frame_p (tx_frame_p ), + .tx_frame_n (tx_frame_n ), + .tx_data_p (tx_data_p ), + .tx_data_n (tx_data_n ) +); + +ad9361_rx_map_lvds_single dut_rx +( + .clk_2x_in (clk_2x_in ), + .clk_in_rst (clk_in_rst ), + + .rx_data_clk (data_clk ), + .rx_data_clk_rst(data_clk_rst ), + + .rx_fifo_rst (1'b0 ), + + .rx_frame_p (tx_frame_p ), + .rx_frame_n (tx_frame_n ), + .rx_data_p (tx_data_p ), + .rx_data_n (tx_data_n ), + + .rx_data_i (rx_data_i ), + .rx_data_q (rx_data_q ) +); + +initial begin + clk_in_rst = 1'b1; + data_clk_rst = 1'b1; + #102 + clk_in_rst = 'b0; + #333 + data_clk_rst = 'b0; +end + +always #20 clk_2x_in = ~clk_2x_in; + +always @(posedge clk_2x_in) begin + #7 data_clk <= ~data_clk; +end + +always @(posedge data_clk) begin + if (data_clk_rst) begin + tx_data_i <= 'b0; + tx_data_q <= 'b0; + end + else begin + tx_data_i <= tx_data_i + 2'd1; + tx_data_q <= tx_data_q + 2'd2; + end +end + +endmodule diff --git a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_dual.v b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_dual.v index 5e308fa1..6a6b1eee 100644 --- a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_dual.v +++ b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_dual.v @@ -45,13 +45,14 @@ module ad9361_rx_map_cmos_dual output [11:0] rx_ch2_q ); -genvar m; +genvar mm; // rx data -wire [11:0] rx_data_i, rx_data_q; +wire [11:0] rx_data_pos; +wire [11:0] rx_data_neg; generate -for (m=0; m<12; m=m+1) begin : rx_data_iddr +for (mm = 0; mm < 12; mm = mm + 1) begin IDDR #( .DDR_CLK_EDGE ("SAME_EDGE" ), @@ -63,17 +64,17 @@ IDDR #( .R (1'b0 ), .S (1'b0 ), .C (clk_2x_in ), - .D (rx_data[m] ), - .Q1 (rx_data_q[m] ), - .Q2 (rx_data_i[m] ) + .D (rx_data[mm] ), + .Q1 (rx_data_pos[mm]), + .Q2 (rx_data_neg[mm]) ); end endgenerate // rx frame -wire rx_frame_i; -wire rx_frame_q; +wire rx_frame_pos; +wire rx_frame_neg; IDDR #( .DDR_CLK_EDGE ("SAME_EDGE" ), @@ -86,49 +87,52 @@ IDDR #( .S (1'b0 ), .C (clk_2x_in ), .D (rx_frame ), - .Q1 (rx_frame_q ), - .Q2 (rx_frame_i ) + .Q1 (rx_frame_pos ), + .Q2 (rx_frame_neg ) ); // divide rx_data to dual channel -reg [11:0] rx1_data_i = 'b0; -reg [11:0] rx1_data_q = 'b0; -reg [11:0] rx2_data_i = 'b0; -reg [11:0] rx2_data_q = 'b0; +reg [11:0] rx1_data_i = 'b0; +reg [11:0] rx1_data_q = 'b0; +reg [11:0] rx2_data_i = 'b0; +reg [11:0] rx2_data_q = 'b0; -wire rx_fifo_wr_en; -reg rx_fifo_rd_en = 'b0; +reg rx_fifo_wr_en = 'b0; +reg rx_fifo_rd_en = 'b0; -wire rx_fifo_empty_1; -wire rx_fifo_empty_2; -wire rx_fifo_empty_3; -wire rx_fifo_empty_4; - -assign rx_fifo_wr_en = rx_frame_i; // align data & write enable +wire rx_fifo_empty_1; +wire rx_fifo_empty_2; +wire rx_fifo_empty_3; +wire rx_fifo_empty_4; always @ (posedge clk_2x_in) begin if (clk_in_rst) begin rx1_data_i <= 'b0; - rx2_data_i <= 'b0; - end - else if(rx_frame_i) begin - rx1_data_i <= rx_data_i; - end - else begin - rx2_data_i <= rx_data_i; - end -end - -always @ (posedge clk_2x_in) begin - if (clk_in_rst) begin rx1_data_q <= 'b0; + rx2_data_i <= 'b0; rx2_data_q <= 'b0; + rx_fifo_wr_en <= 'b0; end - else if(rx_frame_q) begin - rx1_data_q <= rx_data_q; + else if({rx_frame_neg,rx_frame_pos} == 2'b11) begin + rx1_data_i <= rx_data_neg; + rx1_data_q <= rx_data_pos; + rx2_data_i <= rx2_data_i; + rx2_data_q <= rx2_data_q; + rx_fifo_wr_en <= 'b0; + end + else if({rx_frame_neg,rx_frame_pos} == 2'b00) begin + rx1_data_i <= rx1_data_i; + rx1_data_q <= rx1_data_q; + rx2_data_i <= rx_data_neg; + rx2_data_q <= rx_data_pos; + rx_fifo_wr_en <= 'b1; end else begin - rx2_data_q <= rx_data_q; + rx1_data_i <= 'd1234; // error + rx1_data_q <= 'd4321; // error + rx2_data_i <= 'd5678; // error + rx2_data_q <= 'd8765; // error + rx_fifo_wr_en <= 'b0; end end @@ -143,54 +147,54 @@ end ad9361_fifo u_rx_fifo_ch1_i ( - .rst (rx_fifo_rst ), // input wire rst - .wr_clk (clk_2x_in ), // input wire wr_clk - .rd_clk (rx_data_clk ), // input wire rd_clk - .din (rx1_data_i ), // input wire [11 : 0] din - .wr_en (rx_fifo_wr_en ), // input wire wr_en - .rd_en (rx_fifo_rd_en ), // input wire rd_en - .dout (rx_ch1_i ), // output wire [11 : 0] dout - .full ( ), // output wire full - .empty (rx_fifo_empty_1) // output wire empty + .rst (clk_in_rst || rx_fifo_rst ), // input wire rst + .wr_clk (clk_2x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx1_data_i ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_ch1_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_1 ) // output wire empty ); ad9361_fifo u_rx_fifo_ch1_q ( - .rst (rx_fifo_rst ), // input wire rst - .wr_clk (clk_2x_in ), // input wire wr_clk - .rd_clk (rx_data_clk ), // input wire rd_clk - .din (rx1_data_q ), // input wire [11 : 0] din - .wr_en (rx_fifo_wr_en ), // input wire wr_en - .rd_en (rx_fifo_rd_en ), // input wire rd_en - .dout (rx_ch1_q ), // output wire [11 : 0] dout - .full ( ), // output wire full - .empty (rx_fifo_empty_2) // output wire empty + .rst (clk_in_rst || rx_fifo_rst ), // input wire rst + .wr_clk (clk_2x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx1_data_q ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_ch1_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_2 ) // output wire empty ); ad9361_fifo u_rx_fifo_ch2_i ( - .rst (rx_fifo_rst ), // input wire rst - .wr_clk (clk_2x_in ), // input wire wr_clk - .rd_clk (rx_data_clk ), // input wire rd_clk - .din (rx2_data_i ), // input wire [11 : 0] din - .wr_en (rx_fifo_wr_en ), // input wire wr_en - .rd_en (rx_fifo_rd_en ), // input wire rd_en - .dout (rx_ch2_i ), // output wire [11 : 0] dout - .full ( ), // output wire full - .empty (rx_fifo_empty_3) // output wire empty + .rst (clk_in_rst || rx_fifo_rst ), // input wire rst + .wr_clk (clk_2x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx2_data_i ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_ch2_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_3 ) // output wire empty ); ad9361_fifo u_rx_fifo_ch2_q ( - .rst (rx_fifo_rst ), // input wire rst - .wr_clk (clk_2x_in ), // input wire wr_clk - .rd_clk (rx_data_clk ), // input wire rd_clk - .din (rx2_data_q ), // input wire [11 : 0] din - .wr_en (rx_fifo_wr_en ), // input wire wr_en - .rd_en (rx_fifo_rd_en ), // input wire rd_en - .dout (rx_ch2_q ), // output wire [11 : 0] dout - .full ( ), // output wire full - .empty (rx_fifo_empty_4) // output wire empty + .rst (clk_in_rst || rx_fifo_rst ), // input wire rst + .wr_clk (clk_2x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx2_data_q ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_ch2_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_4 ) // output wire empty ); endmodule diff --git a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_single.v b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_single.v index c5bb387a..bc888123 100644 --- a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_single.v +++ b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_cmos_single.v @@ -43,32 +43,71 @@ module ad9361_rx_map_cmos_single output [11:0] rx_data_q ); -genvar m; +genvar mm; -// rx data -wire [11:0] rx_raw_i, rx_raw_q; +// rx data from port +wire [11:0] rx_data_pos; +wire [11:0] rx_data_neg; generate -for (m=0; m<12; m=m+1) begin : rx_data_iddr - +for (mm = 0; mm < 12; mm = mm + 1) begin : rx_data_iddr IDDR #( - .DDR_CLK_EDGE ("SAME_EDGE" ), - .INIT_Q1 (1'b0 ), - .INIT_Q2 (1'b0 ), - .SRTYPE ("ASYNC" ) + .DDR_CLK_EDGE ("SAME_EDGE" ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED" + .INIT_Q1 (1'b0 ), // Initial value of Q1: 1'b0 or 1'b1 + .INIT_Q2 (1'b0 ), // Initial value of Q2: 1'b0 or 1'b1 + .SRTYPE ("ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC" ) i_rx_data_iddr ( - .CE (1'b1 ), - .R (1'b0 ), - .S (1'b0 ), - .C (clk_in ), - .D (rx_data[m] ), - .Q1 (rx_raw_q[m] ), - .Q2 (rx_raw_i[m] ) + .CE (1'b1 ), // 1-bit clock enable input + .R (1'b0 ), // 1-bit reset + .S (1'b0 ), // 1-bit set + .C (clk_in ), // 1-bit clock input + .D (rx_data[mm] ), // 1-bit DDR data input + .Q1 (rx_data_pos[mm]), // 1-bit output for positive edge of clock + .Q2 (rx_data_neg[mm]) // 1-bit output for negative edge of clock ); end endgenerate +// rx frame from port +wire rx_frame_pos; +wire rx_frame_neg; + +IDDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED" + .INIT_Q1 (1'b0 ), // Initial value of Q1: 1'b0 or 1'b1 + .INIT_Q2 (1'b0 ), // Initial value of Q2: 1'b0 or 1'b1 + .SRTYPE ("ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC" +) i_rx_frame_iddr ( + .CE (1'b1 ), // 1-bit clock enable input + .R (1'b0 ), // 1-bit reset + .S (1'b0 ), // 1-bit set + .C (clk_in ), // 1-bit clock input + .D (rx_frame ), // 1-bit DDR data input + .Q1 (rx_frame_pos ), // 1-bit output for positive edge of clock + .Q2 (rx_frame_neg ) // 1-bit output for negative edge of clock +); + +// rx data +reg [11:0] rx_fifo_i = 'b0; +reg [11:0] rx_fifo_q = 'b0; + +always @(posedge clk_in) begin + if (clk_in_rst) begin + rx_fifo_i <= 'b0; + rx_fifo_q <= 'b0; + end + else begin + if ({rx_frame_neg,rx_frame_pos} == 2'b10) begin + rx_fifo_i <= rx_data_neg; + rx_fifo_q <= rx_data_pos; + end + else begin + rx_fifo_i <= 'd1234; // error + rx_fifo_q <= 'd4321; // error + end + end +end // divide rx_data to dual channel reg rx_fifo_wr_en = 1'b0; @@ -97,28 +136,28 @@ end ad9361_fifo u_rx_fifo_i ( - .rst (rx_fifo_rst ), // input wire rst - .wr_clk (clk_in ), // input wire wr_clk - .rd_clk (rx_data_clk ), // input wire rd_clk - .din (rx_raw_i ), // input wire [11 : 0] din - .wr_en (rx_fifo_wr_en ), // input wire wr_en - .rd_en (rx_fifo_rd_en ), // input wire rd_en - .dout (rx_data_i ), // output wire [11 : 0] dout - .full ( ), // output wire full - .empty (rx_fifo_empty_1) // output wire empty + .rst (clk_in_rst || rx_fifo_rst ), // input wire rst + .wr_clk (clk_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx_fifo_i ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_data_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_1 ) // output wire empty ); ad9361_fifo u_rx_fifo_q ( - .rst (rx_fifo_rst ), // input wire rst - .wr_clk (clk_in ), // input wire wr_clk - .rd_clk (rx_data_clk ), // input wire rd_clk - .din (rx_raw_q ), // input wire [11 : 0] din - .wr_en (rx_fifo_wr_en ), // input wire wr_en - .rd_en (rx_fifo_rd_en ), // input wire rd_en - .dout (rx_data_q ), // output wire [11 : 0] dout - .full ( ), // output wire full - .empty (rx_fifo_empty_2) // output wire empty + .rst (clk_in_rst || rx_fifo_rst ), // input wire rst + .wr_clk (clk_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx_fifo_q ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_data_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_2 ) // output wire empty ); endmodule diff --git a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_lvds_dual.v b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_lvds_dual.v index 026330d0..26b5d60b 100644 --- a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_lvds_dual.v +++ b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_lvds_dual.v @@ -8,10 +8,9 @@ // | |_| | (_) \__ \ | | | | |_| | (_| | (_) | // \___/ \___/|___/_| |_| \____|\__,_|\___/ // -// Create Date: 2022/07/01 17:37:27 -// Last Modified Date: 2023/03/06 10:54 +// Create Date: 09/27/2024 04:49:13 PM // Design Name: -// Module Name: ad9361_rx_mapping_dual +// Module Name: ad9361_rx_map_lvds_dual // Project Name: // Target Devices: // Tool Versions: @@ -47,155 +46,84 @@ module ad9361_rx_map_lvds_dual output [11:0] rx_ch2_q ); -genvar m; +genvar mm; -// rx data +// rx data from port wire [5:0] rx_data; -wire [5:0] rx_data_i, rx_data_q; +wire [5:0] rx_data_pos; +wire [5:0] rx_data_neg; generate -for (m=0; m<6; m=m+1) begin : rx_data_iddr +for (mm = 0; mm < 6; mm = mm + 1) begin IBUFDS #( - .DIFF_TERM ("TRUE" ) -) u_ibufds_rx_data + .DIFF_TERM ("TRUE" ) // Differential Termination +) u_rx_data_ibufds ( - .I (rx_data_p[m] ), - .IB (rx_data_n[m] ), - .O (rx_data[m] ) + .I (rx_data_p[mm] ), // Diff_p buffer input (connect directly to top-level port) + .IB (rx_data_n[mm] ), // Diff_n buffer input (connect directly to top-level port) + .O (rx_data[mm] ) // Buffer output ); IDDR #( - .DDR_CLK_EDGE ("SAME_EDGE" ), - .INIT_Q1 (1'b0 ), - .INIT_Q2 (1'b0 ), - .SRTYPE ("ASYNC" ) -) u_rx_data_iddr ( - .CE (1'b1 ), // clock enable - .R (1'b0 ), // iddr reset - .S (1'b0 ), // iddr set - .C (clk_4x_in ), // iddr clock - .D (rx_data[m] ), // ddr data - .Q1 (rx_data_q[m] ), // sdr data at rising edge - .Q2 (rx_data_i[m] ) // sdr data at falling edge + .DDR_CLK_EDGE ("SAME_EDGE" ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED" + .INIT_Q1 (1'b0 ), // Initial value of Q1: 1'b0 or 1'b1 + .INIT_Q2 (1'b0 ), // Initial value of Q2: 1'b0 or 1'b1 + .SRTYPE ("ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC" +) i_rx_data_iddr ( + .CE (1'b1 ), // 1-bit clock enable input + .R (1'b0 ), // 1-bit reset + .S (1'b0 ), // 1-bit set + .C (clk_4x_in ), // 1-bit clock input + .D (rx_data[mm] ), // 1-bit DDR data input + .Q1 (rx_data_pos[mm]), // 1-bit output for positive edge of clock + .Q2 (rx_data_neg[mm]) // 1-bit output for negative edge of clock ); end endgenerate -// rx frame -wire rx_frame; -wire rx_frame_i; -wire rx_frame_q; +// rx frame from port +wire rx_frame; +wire rx_frame_pos; +wire rx_frame_neg; IBUFDS #( - .DIFF_TERM ("TRUE" ) -) u_ibufds_rx_frame + .DIFF_TERM ("TRUE" ) // Differential Termination +) u_rx_frame_ibufds ( - .I (rx_frame_p ), - .IB (rx_frame_n ), - .O (rx_frame ) + .I (rx_frame_p ), // Diff_p buffer input (connect directly to top-level port) + .IB (rx_frame_n ), // Diff_n buffer input (connect directly to top-level port) + .O (rx_frame ) // Buffer output ); IDDR #( - .DDR_CLK_EDGE ("SAME_EDGE" ), - .INIT_Q1 (1'b0 ), - .INIT_Q2 (1'b0 ), - .SRTYPE ("ASYNC" ) -) u_rx_frame_iddr ( - .CE (1'b1 ), // clock enable - .R (1'b0 ), // iddr reset - .S (1'b0 ), // iddr set - .C (clk_4x_in ), // iddr clock - .D (rx_frame ), // ddr data - .Q1 (rx_frame_q ), // sdr data at rising edge - .Q2 (rx_frame_i ) // sdr data at falling edge + .DDR_CLK_EDGE ("SAME_EDGE" ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED" + .INIT_Q1 (1'b0 ), // Initial value of Q1: 1'b0 or 1'b1 + .INIT_Q2 (1'b0 ), // Initial value of Q2: 1'b0 or 1'b1 + .SRTYPE ("ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC" +) i_rx_frame_iddr ( + .CE (1'b1 ), // 1-bit clock enable input + .R (1'b0 ), // 1-bit reset + .S (1'b0 ), // 1-bit set + .C (clk_4x_in ), // 1-bit clock input + .D (rx_frame ), // 1-bit DDR data input + .Q1 (rx_frame_pos ), // 1-bit output for positive edge of clock + .Q2 (rx_frame_neg ) // 1-bit output for negative edge of clock ); // unpack rx frame & data -reg rx_frame_i_d1 = 'b0; -reg [ 5:0] rx_data_i_d1 = 'b0; -reg [ 5:0] rx_data_q_d1 = 'b0; -reg rx_flag = 'b0; // rx frame rising edge indicator -reg [ 1:0] rx_cnt = 'b0; // unpack stage counter +reg rx_frame_pos_d = 'b0; +reg rx_frame_neg_d = 'b0; -always @(posedge clk_4x_in) begin - // wait for [rx_flag] - rx_frame_i_d1 <= rx_frame_i; - rx_data_i_d1 <= rx_data_i; - rx_data_q_d1 <= rx_data_q; -end +reg [11:0] rx_fifo_ch1_i = 'b0; +reg [11:0] rx_fifo_ch1_q = 'b0; +reg [11:0] rx_fifo_ch2_i = 'b0; +reg [11:0] rx_fifo_ch2_q = 'b0; -always @(posedge clk_4x_in) begin - if (clk_in_rst) begin - rx_flag <= 'b0; - end - else if (~rx_frame_i_d1 & rx_frame_i) begin - // assert when rising edge of rx frame is detected - rx_flag <= 'b1; - end - else begin - rx_flag <= rx_flag; - end -end +reg rx_fifo_wr_en = 'b0; +reg rx_fifo_rd_en = 'b0; -always @(posedge clk_4x_in) begin - if (clk_in_rst) begin - rx_cnt <= 'b0; - end - else begin - rx_cnt <= (rx_flag) ? rx_cnt + 1'b1 : rx_cnt; - end -end - -reg [11:0] rx1_data_i = 'b0; -reg [11:0] rx1_data_q = 'b0; -reg [11:0] rx2_data_i = 'b0; -reg [11:0] rx2_data_q = 'b0; - -always @(posedge clk_4x_in) begin - if (clk_in_rst) begin - rx1_data_i <= 'b0; - rx1_data_q <= 'b0; - rx2_data_i <= 'b0; - rx2_data_q <= 'b0; - end - else begin - case (rx_cnt) - 3'd0: begin - // 1st clock cycle: upper 6-bit of rx ch1 inphase/quadrature data - rx1_data_i[11:6] <= rx_data_i_d1; - rx1_data_q[11:6] <= rx_data_q_d1; - end - 3'd1: begin - // 2nd clock cycle: lower 6-bit of rx ch1 inphase/quadrature data - rx1_data_i[ 5:0] <= rx_data_i_d1; - rx1_data_q[ 5:0] <= rx_data_q_d1; - end - 3'd2: begin - // 3rd clock cycle: upper 6-bit of rx ch2 inphase/quadrature data - rx2_data_i[11:6] <= rx_data_i_d1; - rx2_data_q[11:6] <= rx_data_q_d1; - end - 3'd3: begin - // 4th clock cycle: lower 6-bit of rx ch2 inphase/quadrature data - rx2_data_i[ 5:0] <= rx_data_i_d1; - rx2_data_q[ 5:0] <= rx_data_q_d1; - end - default: begin - rx1_data_i <= 'b0; - rx1_data_q <= 'b0; - rx2_data_i <= 'b0; - rx2_data_q <= 'b0; - end - endcase - end -end - -// write fifo when rx1/2_data_i/q are all prepared with 192MHz clock -// read fifo at every clock cycle with 48MHz clock -reg fifo_wr_en = 'b0; -reg fifo_rd_en = 'b0; wire rx_fifo_empty_1; wire rx_fifo_empty_2; wire rx_fifo_empty_3; @@ -203,75 +131,122 @@ wire rx_fifo_empty_4; always @(posedge clk_4x_in) begin if (clk_in_rst) begin - fifo_wr_en <= 'b0; - end - else if (rx_cnt == 2'd3) begin - fifo_wr_en <= 1'b1; + rx_frame_pos_d <= 'b0; + rx_frame_neg_d <= 'b0; end else begin - fifo_wr_en <= 'b0; + rx_frame_pos_d <= rx_frame_pos; + rx_frame_neg_d <= rx_frame_neg; end end -always @(posedge rx_data_clk) begin - if (rx_data_clk_rst) begin - fifo_rd_en <= 1'b0; +always @(posedge clk_4x_in) begin + if (clk_in_rst) begin + rx_fifo_ch1_i <= 'b0; + rx_fifo_ch1_q <= 'b0; + rx_fifo_ch2_i <= 'b0; + rx_fifo_ch2_q <= 'b0; + rx_fifo_wr_en <= 'b0; end else begin - fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4}; + case ({rx_frame_neg_d,rx_frame_pos_d,rx_frame_neg,rx_frame_pos}) + 4'b0011: begin + rx_fifo_ch1_i[11:6] <= rx_data_neg; + rx_fifo_ch1_q[11:6] <= rx_data_pos; + rx_fifo_ch2_i <= rx_fifo_ch2_i; + rx_fifo_ch2_q <= rx_fifo_ch2_q; + rx_fifo_wr_en <= 'b0; + end + 4'b1111: begin + rx_fifo_ch1_i[5:0] <= rx_data_neg; + rx_fifo_ch1_q[5:0] <= rx_data_pos; + rx_fifo_ch2_i <= rx_fifo_ch2_i; + rx_fifo_ch2_q <= rx_fifo_ch2_q; + rx_fifo_wr_en <= 'b0; + end + 4'b1100: begin + rx_fifo_ch1_i <= rx_fifo_ch1_i; + rx_fifo_ch1_q <= rx_fifo_ch1_q; + rx_fifo_ch2_i[11:6] <= rx_data_neg; + rx_fifo_ch2_q[11:6] <= rx_data_pos; + rx_fifo_wr_en <= 'b0; + end + 4'b0000: begin + rx_fifo_ch1_i <= rx_fifo_ch1_i; + rx_fifo_ch1_q <= rx_fifo_ch1_q; + rx_fifo_ch2_i[5:0] <= rx_data_neg; + rx_fifo_ch2_q[5:0] <= rx_data_pos; + rx_fifo_wr_en <= 1'b1; + end + default: begin + rx_fifo_ch1_i <= 'd1234; // error + rx_fifo_ch1_q <= 'd4321; // error + rx_fifo_ch2_i <= 'd5678; // error + rx_fifo_ch2_q <= 'd8765; // error + rx_fifo_wr_en <= 'b0; + end + endcase + end +end +always @(posedge rx_data_clk) begin + if (rx_data_clk_rst) begin + rx_fifo_rd_en <= 'b0; + end + else begin + rx_fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2,~rx_fifo_empty_3, ~rx_fifo_empty_4}; end end ad9361_fifo u_rx_fifo_ch1_i ( - .rst (rx_fifo_rst ), // input wire rst - .wr_clk (clk_4x_in ), // input wire wr_clk - .rd_clk (rx_data_clk ), // input wire rd_clk - .din (rx1_data_i ), // input wire [11 : 0] din - .wr_en (fifo_wr_en ), // input wire wr_en - .rd_en (fifo_rd_en ), // input wire rd_en - .dout (rx_ch1_i ), // output wire [11 : 0] dout - .full ( ), // output wire full - .empty (rx_fifo_empty_1) // output wire empty + .rst (clk_in_rst || rx_fifo_rst ), // input wire rst + .wr_clk (clk_4x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx_fifo_ch1_i ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_ch1_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_1 ) // output wire empty ); ad9361_fifo u_rx_fifo_ch1_q ( - .rst (rx_fifo_rst ), // input wire rst - .wr_clk (clk_4x_in ), // input wire wr_clk - .rd_clk (rx_data_clk ), // input wire rd_clk - .din (rx1_data_q ), // input wire [11 : 0] din - .wr_en (fifo_wr_en ), // input wire wr_en - .rd_en (fifo_rd_en ), // input wire rd_en - .dout (rx_ch1_q ), // output wire [11 : 0] dout - .full ( ), // output wire full - .empty (rx_fifo_empty_2) // output wire empty + .rst (clk_in_rst || rx_fifo_rst ), // input wire rst + .wr_clk (clk_4x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx_fifo_ch1_q ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_ch1_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_2 ) // output wire empty ); ad9361_fifo u_rx_fifo_ch2_i ( - .rst (rx_fifo_rst ), // input wire rst - .wr_clk (clk_4x_in ), // input wire wr_clk - .rd_clk (rx_data_clk ), // input wire rd_clk - .din (rx2_data_i ), // input wire [11 : 0] din - .wr_en (fifo_wr_en ), // input wire wr_en - .rd_en (fifo_rd_en ), // input wire rd_en - .dout (rx_ch2_i ), // output wire [11 : 0] dout - .full ( ), // output wire full - .empty (rx_fifo_empty_3) // output wire empty + .rst (clk_in_rst || rx_fifo_rst ), // input wire rst + .wr_clk (clk_4x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx_fifo_ch2_i ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_ch2_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_3 ) // output wire empty ); ad9361_fifo u_rx_fifo_ch2_q ( - .rst (rx_fifo_rst ), // input wire rst - .wr_clk (clk_4x_in ), // input wire wr_clk - .rd_clk (rx_data_clk ), // input wire rd_clk - .din (rx2_data_q ), // input wire [11 : 0] din - .wr_en (fifo_wr_en ), // input wire wr_en - .rd_en (fifo_rd_en ), // input wire rd_en - .dout (rx_ch2_q ), // output wire [11 : 0] dout - .full ( ), // output wire full - .empty (rx_fifo_empty_4) // output wire empty + .rst (clk_in_rst || rx_fifo_rst ), // input wire rst + .wr_clk (clk_4x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx_fifo_ch2_q ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_ch2_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_4 ) // output wire empty ); endmodule diff --git a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_lvds_single.v b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_lvds_single.v new file mode 100644 index 00000000..2e5a9fd0 --- /dev/null +++ b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_rx_map_lvds_single.v @@ -0,0 +1,182 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// _ _ ____ +// | | ___ ___| |__ / ___| __ _ ___ +// _ | |/ _ \/ __| '_ \ | | _ / _` |/ _ \ +// | |_| | (_) \__ \ | | | | |_| | (_| | (_) | +// \___/ \___/|___/_| |_| \____|\__,_|\___/ +// +// Create Date: 2022/07/01 17:37:27 +// Last Modified Date: 2023/03/03 13:01 +// Design Name: +// Module Name: ad9361_rx_map_lvds_single +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ad9361_rx_map_lvds_single +( + input clk_2x_in , + input clk_in_rst , + + input rx_data_clk , + input rx_data_clk_rst , + + input rx_fifo_rst , + + input rx_frame_p , + input rx_frame_n , + input [ 5:0] rx_data_p , + input [ 5:0] rx_data_n , + + output [11:0] rx_data_i , + output [11:0] rx_data_q +); + +genvar mm; + +// rx data from port +wire [5:0] rx_data; +wire [5:0] rx_data_pos; +wire [5:0] rx_data_neg; + +generate +for (mm = 0; mm < 6; mm = mm + 1) begin + +IBUFDS #( + .DIFF_TERM ("TRUE" ) // Differential Termination +) u_rx_data_ibufds +( + .I (rx_data_p[mm] ), // Diff_p buffer input (connect directly to top-level port) + .IB (rx_data_n[mm] ), // Diff_n buffer input (connect directly to top-level port) + .O (rx_data[mm] ) // Buffer output +); + +IDDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED" + .INIT_Q1 (1'b0 ), // Initial value of Q1: 1'b0 or 1'b1 + .INIT_Q2 (1'b0 ), // Initial value of Q2: 1'b0 or 1'b1 + .SRTYPE ("ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC" +) i_rx_data_iddr ( + .CE (1'b1 ), // 1-bit clock enable input + .R (1'b0 ), // 1-bit reset + .S (1'b0 ), // 1-bit set + .C (clk_2x_in ), // 1-bit clock input + .D (rx_data[mm] ), // 1-bit DDR data input + .Q1 (rx_data_pos[mm]), // 1-bit output for positive edge of clock + .Q2 (rx_data_neg[mm]) // 1-bit output for negative edge of clock +); + +end +endgenerate + +// rx frame from port +wire rx_frame; +wire rx_frame_pos; +wire rx_frame_neg; + +IBUFDS #( + .DIFF_TERM ("TRUE" ) // Differential Termination +) u_rx_frame_ibufds +( + .I (rx_frame_p ), // Diff_p buffer input (connect directly to top-level port) + .IB (rx_frame_n ), // Diff_n buffer input (connect directly to top-level port) + .O (rx_frame ) // Buffer output +); + +IDDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), // "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED" + .INIT_Q1 (1'b0 ), // Initial value of Q1: 1'b0 or 1'b1 + .INIT_Q2 (1'b0 ), // Initial value of Q2: 1'b0 or 1'b1 + .SRTYPE ("ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC" +) i_rx_frame_iddr ( + .CE (1'b1 ), // 1-bit clock enable input + .R (1'b0 ), // 1-bit reset + .S (1'b0 ), // 1-bit set + .C (clk_2x_in ), // 1-bit clock input + .D (rx_frame ), // 1-bit DDR data input + .Q1 (rx_frame_pos ), // 1-bit output for positive edge of clock + .Q2 (rx_frame_neg ) // 1-bit output for negative edge of clock +); + +// unpack rx frame & data +reg [11:0] rx_fifo_i = 'b0; +reg [11:0] rx_fifo_q = 'b0; +reg rx_fifo_wr_en = 'b0; +reg rx_fifo_rd_en = 'b0; +wire rx_fifo_empty_1; +wire rx_fifo_empty_2; + +always @(posedge clk_2x_in) begin + if (clk_in_rst) begin + rx_fifo_i <= 'b0; + rx_fifo_q <= 'b0; + rx_fifo_wr_en <= 'b0; + end + else begin + if ({rx_frame_neg,rx_frame_pos} == 2'b11) begin + rx_fifo_i[11:6] <= rx_data_neg; + rx_fifo_q[11:6] <= rx_data_pos; + rx_fifo_wr_en <= 'b0; + end + else if ({rx_frame_neg,rx_frame_pos} == 2'b00) begin + rx_fifo_i[5:0] <= rx_data_neg; + rx_fifo_q[5:0] <= rx_data_pos; + rx_fifo_wr_en <= 1'b1; + end + else begin + rx_fifo_i <= 'd1234; // error + rx_fifo_q <= 'd4321; // error + rx_fifo_wr_en <= 'b0; + end + end +end + +always @(posedge rx_data_clk) begin + if (rx_data_clk_rst) begin + rx_fifo_rd_en <= 'b0; + end + else begin + rx_fifo_rd_en <= &{~rx_fifo_empty_1, ~rx_fifo_empty_2}; + end +end + +ad9361_fifo u_rx_fifo_i +( + .rst (clk_in_rst || rx_fifo_rst ), // input wire rst + .wr_clk (clk_2x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx_fifo_i ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (1'b1 ), // input wire rd_en + .dout (rx_data_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_1 ) // output wire empty +); + +ad9361_fifo u_rx_fifo_q +( + .rst (clk_in_rst || rx_fifo_rst ), // input wire rst + .wr_clk (clk_2x_in ), // input wire wr_clk + .rd_clk (rx_data_clk ), // input wire rd_clk + .din (rx_fifo_q ), // input wire [11 : 0] din + .wr_en (rx_fifo_wr_en ), // input wire wr_en + .rd_en (rx_fifo_rd_en ), // input wire rd_en + .dout (rx_data_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_2 ) // output wire empty +); + +endmodule \ No newline at end of file diff --git a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_dual.v b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_dual.v index 7fb0b8a8..bfb8f8a3 100644 --- a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_dual.v +++ b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_dual.v @@ -9,7 +9,7 @@ // \___/ \___/|___/_| |_| \____|\__,_|\___/ // // Create Date: 2022/07/01 16:39:19 -// Last Modified Date: 2023/03/06 11:45 +// Last Modified Date: 2024/09/27 16:22 // Design Name: // Module Name: ad9361_tx_map_cmos_dual // Project Name: @@ -44,21 +44,31 @@ module ad9361_tx_map_cmos_dual output [11:0] tx_data ); -genvar m; +genvar mm; // input data fifo -reg rx_fifo_rd_en = 'b0; +reg tx_fifo_rd_en = 'b0; wire [11:0] tx_fifo_ch1_i; wire [11:0] tx_fifo_ch1_q; wire [11:0] tx_fifo_ch2_i; wire [11:0] tx_fifo_ch2_q; +wire rx_fifo_empty_1; +wire rx_fifo_empty_2; +wire rx_fifo_empty_3; +wire rx_fifo_empty_4; + always @(posedge clk_2x_in) begin if (clk_in_rst) begin - rx_fifo_rd_en <= 'b0; + tx_fifo_rd_en <= 'b0; end else begin - rx_fifo_rd_en <= ~rx_fifo_rd_en; + if (&{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4}) begin + tx_fifo_rd_en <= ~tx_fifo_rd_en; + end + else begin + tx_fifo_rd_en <= 'b0; + end end end @@ -69,10 +79,10 @@ ad9361_fifo u_tx_fifo_ch1_i .rd_clk (clk_2x_in ), // input wire rd_clk .din (tx_ch1_i ), // input wire [11 : 0] din .wr_en (1'b1 ), // input wire wr_en - .rd_en (rx_fifo_rd_en ), // input wire rd_en + .rd_en (tx_fifo_rd_en ), // input wire rd_en .dout (tx_fifo_ch1_i ), // output wire [11 : 0] dout .full ( ), // output wire full - .empty ( ) // output wire empty + .empty (rx_fifo_empty_1) // output wire empty ); ad9361_fifo u_tx_fifo_ch1_q @@ -82,10 +92,10 @@ ad9361_fifo u_tx_fifo_ch1_q .rd_clk (clk_2x_in ), // input wire rd_clk .din (tx_ch1_q ), // input wire [11 : 0] din .wr_en (1'b1 ), // input wire wr_en - .rd_en (rx_fifo_rd_en ), // input wire rd_en + .rd_en (tx_fifo_rd_en ), // input wire rd_en .dout (tx_fifo_ch1_q ), // output wire [11 : 0] dout .full ( ), // output wire full - .empty ( ) // output wire empty + .empty (rx_fifo_empty_2) // output wire empty ); ad9361_fifo u_tx_fifo_ch2_i @@ -95,10 +105,10 @@ ad9361_fifo u_tx_fifo_ch2_i .rd_clk (clk_2x_in ), // input wire rd_clk .din (tx_ch2_i ), // input wire [11 : 0] din .wr_en (1'b1 ), // input wire wr_en - .rd_en (rx_fifo_rd_en ), // input wire rd_en + .rd_en (tx_fifo_rd_en ), // input wire rd_en .dout (tx_fifo_ch2_i ), // output wire [11 : 0] dout .full ( ), // output wire full - .empty ( ) // output wire empty + .empty (rx_fifo_empty_3) // output wire empty ); ad9361_fifo u_tx_fifo_ch2_q @@ -108,10 +118,10 @@ ad9361_fifo u_tx_fifo_ch2_q .rd_clk (clk_2x_in ), // input wire rd_clk .din (tx_ch2_q ), // input wire [11 : 0] din .wr_en (1'b1 ), // input wire wr_en - .rd_en (rx_fifo_rd_en ), // input wire rd_en + .rd_en (tx_fifo_rd_en ), // input wire rd_en .dout (tx_fifo_ch2_q ), // output wire [11 : 0] dout .full ( ), // output wire full - .empty ( ) // output wire empty + .empty (rx_fifo_empty_4) // output wire empty ); // frame and data control @@ -127,7 +137,7 @@ always @(posedge clk_2x_in) begin tx_data_i <= 'b0; tx_data_q <= 'b0; end - else if (rx_fifo_rd_en == 1'b0) begin + else if (tx_fifo_rd_en == 1'b0) begin tx_frame_i <= 1'b1; tx_frame_q <= 1'b1; tx_data_i <= tx_fifo_ch1_i; @@ -159,22 +169,22 @@ ODDR #( .Q (tx_frame ) ); -// output tx data to port generate -for (m=0; m<12; m=m+1) begin: tx_data_oddr +for (mm = 0; mm < 12; mm = mm + 1) begin +// output tx data to port ODDR #( .DDR_CLK_EDGE ("SAME_EDGE" ), .INIT (1'b0 ), .SRTYPE ("ASYNC" ) -) u_tx_data_oddr ( +) u_tx_data_oddr ( .CE (1'b1 ), .R (1'b0 ), .S (1'b0 ), .C (clk_2x_in ), - .D1 (tx_data_i[m] ), - .D2 (tx_data_q[m] ), - .Q (tx_data[m] ) + .D1 (tx_data_i[mm] ), + .D2 (tx_data_q[mm] ), + .Q (tx_data[mm] ) ); end diff --git a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_single.v b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_single.v index ad614384..f8a75078 100644 --- a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_single.v +++ b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_cmos_single.v @@ -41,7 +41,7 @@ module ad9361_tx_map_cmos_single output [11:0] tx_data ); -genvar m; +genvar mm; // inout data fifo wire [11:0] tx_fifo_i; @@ -82,35 +82,35 @@ assign clk_out = clk_in; // output tx frame to port ODDR #( - .DDR_CLK_EDGE ("SAME_EDGE" ), - .INIT (1'b0 ), - .SRTYPE ("ASYNC" ) + .DDR_CLK_EDGE ("SAME_EDGE" ), // "OPPOSITE_EDGE" or "SAME_EDGE" + .INIT (1'b0 ), // Initial value of Q: 1'b0 or 1'b1 + .SRTYPE ("ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC" ) u_tx_frame_oddr ( - .CE (1'b1 ), - .R (1'b0 ), - .S (1'b0 ), - .C (clk_in ), - .D1 (tx_frame_i ), - .D2 (tx_frame_q ), - .Q (tx_frame ) + .CE (1'b1 ), // 1-bit clock enable input + .R (1'b0 ), // 1-bit reset + .S (1'b0 ), // 1-bit set + .C (clk_in ), // 1-bit clock input + .D1 (tx_frame_i ), // 1-bit data input (positive edge) + .D2 (tx_frame_q ), // 1-bit data input (negative edge) + .Q (tx_frame ) // 1-bit DDR output ); // output tx data to port generate -for (m=0; m<12; m=m+1) begin: tx_data_oddr +for (mm = 0; mm < 12; mm = mm + 1) begin: tx_data_oddr ODDR #( - .DDR_CLK_EDGE ("SAME_EDGE" ), - .INIT (1'b0 ), - .SRTYPE ("ASYNC" ) -) u_tx_data_oddr ( - .CE (1'b1 ), - .R (1'b0 ), - .S (1'b0 ), - .C (clk_in ), - .D1 (tx_fifo_i[m] ), - .D2 (tx_fifo_q[m] ), - .Q (tx_data[m] ) + .DDR_CLK_EDGE ("SAME_EDGE" ), // "OPPOSITE_EDGE" or "SAME_EDGE" + .INIT (1'b0 ), // Initial value of Q: 1'b0 or 1'b1 + .SRTYPE ("ASYNC" ) // Set/Reset type: "SYNC" or "ASYNC" +) u_tx_data_oddr ( + .CE (1'b1 ), // 1-bit clock enable input + .R (1'b0 ), // 1-bit reset + .S (1'b0 ), // 1-bit set + .C (clk_in ), // 1-bit clock input + .D1 (tx_fifo_i[mm] ), // 1-bit data input (positive edge) + .D2 (tx_fifo_q[mm] ), // 1-bit data input (negative edge) + .Q (tx_data[mm] ) // 1-bit DDR output ); end diff --git a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_lvds_dual.v b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_lvds_dual.v index 0775eb88..f0779256 100644 --- a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_lvds_dual.v +++ b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_lvds_dual.v @@ -8,8 +8,7 @@ // | |_| | (_) \__ \ | | | | |_| | (_| | (_) | // \___/ \___/|___/_| |_| \____|\__,_|\___/ // -// Create Date: 2023/03/05 23:21:27 -// Last Modified Date: 2023/03/06 11:01 +// Create Date: 09/27/2024 03:26:45 PM // Design Name: // Module Name: ad9361_tx_map_lvds_dual // Project Name: @@ -47,34 +46,41 @@ module ad9361_tx_map_lvds_dual output [ 5:0] tx_data_n ); -genvar m; +genvar mm; // input data fifo -reg [1:0] tx_control_cnt = 'b0; -reg rx_fifo_rd_en = 'b0; +reg [1:0] tx_fifo_rd_en_cnt = 'b0; +reg tx_fifo_rd_en = 'b0; wire [11:0] tx_fifo_ch1_i; wire [11:0] tx_fifo_ch1_q; wire [11:0] tx_fifo_ch2_i; wire [11:0] tx_fifo_ch2_q; +wire rx_fifo_empty_1; +wire rx_fifo_empty_2; +wire rx_fifo_empty_3; +wire rx_fifo_empty_4; + always @(posedge clk_4x_in) begin if (clk_in_rst) begin - tx_control_cnt <= 'b0; + tx_fifo_rd_en_cnt <= 'b0; end else begin - tx_control_cnt <= tx_control_cnt + 1'b1; + tx_fifo_rd_en_cnt <= tx_fifo_rd_en_cnt + 1'b1; end end always @(posedge clk_4x_in) begin if (clk_in_rst) begin - rx_fifo_rd_en <= 'b0; - end - else if (tx_control_cnt == 2'd2) begin - rx_fifo_rd_en <= 1'b1; + tx_fifo_rd_en <= 'b0; end else begin - rx_fifo_rd_en <= 'b0; + if (&{~rx_fifo_empty_1, ~rx_fifo_empty_2, ~rx_fifo_empty_3, ~rx_fifo_empty_4}) begin + tx_fifo_rd_en <= (tx_fifo_rd_en_cnt == 2'd3) ? 1'b1 : 'b0; + end + else begin + tx_fifo_rd_en <= 'b0; + end end end @@ -85,10 +91,10 @@ ad9361_fifo u_tx_fifo_ch1_i .rd_clk (clk_4x_in ), // input wire rd_clk .din (tx_ch1_i ), // input wire [11 : 0] din .wr_en (1'b1 ), // input wire wr_en - .rd_en (rx_fifo_rd_en ), // input wire rd_en + .rd_en (tx_fifo_rd_en ), // input wire rd_en .dout (tx_fifo_ch1_i ), // output wire [11 : 0] dout .full ( ), // output wire full - .empty ( ) // output wire empty + .empty (rx_fifo_empty_1) // output wire empty ); ad9361_fifo u_tx_fifo_ch1_q @@ -98,10 +104,10 @@ ad9361_fifo u_tx_fifo_ch1_q .rd_clk (clk_4x_in ), // input wire rd_clk .din (tx_ch1_q ), // input wire [11 : 0] din .wr_en (1'b1 ), // input wire wr_en - .rd_en (rx_fifo_rd_en ), // input wire rd_en + .rd_en (tx_fifo_rd_en ), // input wire rd_en .dout (tx_fifo_ch1_q ), // output wire [11 : 0] dout .full ( ), // output wire full - .empty ( ) // output wire empty + .empty (rx_fifo_empty_2) // output wire empty ); ad9361_fifo u_tx_fifo_ch2_i @@ -111,10 +117,10 @@ ad9361_fifo u_tx_fifo_ch2_i .rd_clk (clk_4x_in ), // input wire rd_clk .din (tx_ch2_i ), // input wire [11 : 0] din .wr_en (1'b1 ), // input wire wr_en - .rd_en (rx_fifo_rd_en ), // input wire rd_en + .rd_en (tx_fifo_rd_en ), // input wire rd_en .dout (tx_fifo_ch2_i ), // output wire [11 : 0] dout .full ( ), // output wire full - .empty ( ) // output wire empty + .empty (rx_fifo_empty_3) // output wire empty ); ad9361_fifo u_tx_fifo_ch2_q @@ -124,57 +130,56 @@ ad9361_fifo u_tx_fifo_ch2_q .rd_clk (clk_4x_in ), // input wire rd_clk .din (tx_ch2_q ), // input wire [11 : 0] din .wr_en (1'b1 ), // input wire wr_en - .rd_en (rx_fifo_rd_en ), // input wire rd_en + .rd_en (tx_fifo_rd_en ), // input wire rd_en .dout (tx_fifo_ch2_q ), // output wire [11 : 0] dout .full ( ), // output wire full - .empty ( ) // output wire empty + .empty (rx_fifo_empty_4) // output wire empty ); - // frame and data control -reg tx_frame_r = 'b0; // rising edge data -reg tx_frame_f = 'b0; // falling edge data -reg [5:0] tx_data_r = 'b0; -reg [5:0] tx_data_f = 'b0; +reg tx_frame_i = 'b0; +reg tx_frame_q = 'b0; +reg [5:0] tx_buf_i = 'b0; +reg [5:0] tx_buf_q = 'b0; always @(posedge clk_4x_in) begin if (clk_in_rst) begin - tx_frame_r <= 'b0; - tx_frame_f <= 'b0; - tx_data_r <= 'b0; - tx_data_f <= 'b0; + tx_frame_i <= 'b0; + tx_frame_q <= 'b0; + tx_buf_i <= 'b0; + tx_buf_q <= 'b0; end else begin - case (tx_control_cnt) + case (tx_fifo_rd_en_cnt) 2'd0: begin - tx_frame_r <= 1'b1; - tx_frame_f <= 1'b1; - tx_data_r <= tx_fifo_ch1_i[11: 6]; - tx_data_f <= tx_fifo_ch1_q[11: 6]; + tx_frame_i <= 1'b1; + tx_frame_q <= 1'b1; + tx_buf_i <= tx_fifo_ch1_i[11:6]; + tx_buf_q <= tx_fifo_ch1_q[11:6]; end 2'd1: begin - tx_frame_r <= 1'b1; - tx_frame_f <= 1'b1; - tx_data_r <= tx_fifo_ch1_i[5:0]; - tx_data_f <= tx_fifo_ch1_q[5:0]; + tx_frame_i <= 1'b1; + tx_frame_q <= 1'b1; + tx_buf_i <= tx_fifo_ch1_i[5:0]; + tx_buf_q <= tx_fifo_ch1_q[5:0]; end 2'd2: begin - tx_frame_r <= 1'b0; - tx_frame_f <= 1'b0; - tx_data_r <= tx_fifo_ch2_i[11:6]; - tx_data_f <= tx_fifo_ch2_q[11:6]; + tx_frame_i <= 1'b0; + tx_frame_q <= 1'b0; + tx_buf_i <= tx_fifo_ch2_i[11:6]; + tx_buf_q <= tx_fifo_ch2_q[11:6]; end 2'd3: begin - tx_frame_r <= 1'b0; - tx_frame_f <= 1'b0; - tx_data_r <= tx_fifo_ch2_i[5:0]; - tx_data_f <= tx_fifo_ch2_q[5:0]; + tx_frame_i <= 1'b0; + tx_frame_q <= 1'b0; + tx_buf_i <= tx_fifo_ch2_i[5:0]; + tx_buf_q <= tx_fifo_ch2_q[5:0]; end default: begin - tx_frame_r <= 'b0; - tx_frame_f <= 'b0; - tx_data_r <= 'b0; - tx_data_f <= 'b0; + tx_frame_i <= 'b0; // error + tx_frame_q <= 'b0; // error + tx_buf_i <= 'b0; // error + tx_buf_q <= 'b0; // error end endcase end @@ -182,9 +187,10 @@ end // output clock to port wire clk_out; + assign clk_out = clk_4x_in; -OBUFDS u_obufds_clk_out +OBUFDS u_clk_out_obufds ( .I (clk_out ), .O (clk_out_p ), @@ -192,6 +198,8 @@ OBUFDS u_obufds_clk_out ); // output tx frame to port +wire tx_frame; + ODDR #( .DDR_CLK_EDGE ("SAME_EDGE" ), .INIT (1'b0 ), @@ -201,46 +209,46 @@ ODDR #( .R (1'b0 ), .S (1'b0 ), .C (clk_4x_in ), - .D1 (tx_frame_r ), - .D2 (tx_frame_f ), + .D1 (tx_frame_i ), + .D2 (tx_frame_q ), .Q (tx_frame ) ); -OBUFDS u_obufds_tx_frame +OBUFDS u_tx_frame_obufds ( - .I (tx_frame ), - .O (tx_frame_p ), - .OB (tx_frame_n ) + .O (tx_frame_p ), // Diff_p output (connect directly to top-level port) + .OB (tx_frame_n ), // Diff_n output (connect directly to top-level port) + .I (tx_frame ) // Buffer input ); -// output tx data to port +// ouput tx data to port wire [5:0] tx_data; generate -for (m=0; m<6; m=m+1) begin: tx_data_oddr +for (mm = 0; mm < 6; mm = mm + 1) begin ODDR #( .DDR_CLK_EDGE ("SAME_EDGE" ), .INIT (1'b0 ), .SRTYPE ("ASYNC" ) -) u_tx_data_oddr ( +) u_tx_data_oddr ( .CE (1'b1 ), .R (1'b0 ), .S (1'b0 ), .C (clk_4x_in ), - .D1 (tx_data_r[m] ), - .D2 (tx_data_f[m] ), - .Q (tx_data[m] ) + .D1 (tx_buf_i[mm] ), + .D2 (tx_buf_q[mm] ), + .Q (tx_data[mm] ) ); -OBUFDS u_obufds_tx_data +OBUFDS u_tx_data_obufds ( - .I (tx_data[m] ), - .O (tx_data_p[m] ), - .OB (tx_data_n[m] ) + .O (tx_data_p[mm] ), // Diff_p output (connect directly to top-level port) + .OB (tx_data_n[mm] ), // Diff_n output (connect directly to top-level port) + .I (tx_data[mm] ) // Buffer input ); end endgenerate -endmodule +endmodule \ No newline at end of file diff --git a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_lvds_single.v b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_lvds_single.v new file mode 100644 index 00000000..897cf1a0 --- /dev/null +++ b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/sources_1/new/ad9361_tx_map_lvds_single.v @@ -0,0 +1,187 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 09/27/2024 03:26:45 PM +// Design Name: +// Module Name: ad9361_tx_map_lvds_single +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ad9361_tx_map_lvds_single +( + input clk_2x_in , + input clk_in_rst , + + input tx_data_clk , + input tx_data_clk_rst , + + input [11:0] tx_data_i , + input [11:0] tx_data_q , + + output clk_out_p , + output clk_out_n , + output tx_frame_p , + output tx_frame_n , + output [ 5:0] tx_data_p , + output [ 5:0] tx_data_n +); + +genvar mm; + +// input data fifo +reg tx_fifo_rd_en = 'b0; +wire [11:0] tx_fifo_i; +wire [11:0] tx_fifo_q; + +wire rx_fifo_empty_1; +wire rx_fifo_empty_2; + +always @(posedge clk_2x_in) begin + if (clk_in_rst) begin + tx_fifo_rd_en <= 'b0; + end + else begin + if (&{~rx_fifo_empty_1, ~rx_fifo_empty_2}) begin + tx_fifo_rd_en <= ~tx_fifo_rd_en; + end + else begin + tx_fifo_rd_en <= 'b0; + end + end +end + +ad9361_fifo u_tx_fifo_i +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_2x_in ), // input wire rd_clk + .din (tx_data_i ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (tx_fifo_rd_en ), // input wire rd_en + .dout (tx_fifo_i ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_1) // output wire empty +); + +ad9361_fifo u_tx_fifo_q +( + .rst (clk_in_rst ), // input wire rst + .wr_clk (tx_data_clk ), // input wire wr_clk + .rd_clk (clk_2x_in ), // input wire rd_clk + .din (tx_data_q ), // input wire [11 : 0] din + .wr_en (1'b1 ), // input wire wr_en + .rd_en (tx_fifo_rd_en ), // input wire rd_en + .dout (tx_fifo_q ), // output wire [11 : 0] dout + .full ( ), // output wire full + .empty (rx_fifo_empty_2) // output wire empty +); + +// frame and data control +reg tx_frame_i = 'b0; +reg tx_frame_q = 'b0; +reg [ 5:0] tx_buf_i = 'b0; +reg [ 5:0] tx_buf_q = 'b0; + +always @(posedge clk_2x_in) begin + if (clk_in_rst) begin + tx_frame_i <= 'b0; + tx_frame_q <= 'b0; + tx_buf_i <= 'b0; + tx_buf_q <= 'b0; + end + else begin + if (tx_fifo_rd_en == 1'b0) begin + tx_frame_i <= 1'b1; + tx_frame_q <= 1'b1; + tx_buf_i <= tx_fifo_i[11:6]; + tx_buf_q <= tx_fifo_q[11:6]; + end + else begin + tx_frame_i <= 1'b0; + tx_frame_q <= 1'b0; + tx_buf_i <= tx_fifo_i[5:0]; + tx_buf_q <= tx_fifo_q[5:0]; + end + end +end + +// output clock to port +wire clk_out; + +assign clk_out = clk_2x_in; + +OBUFDS u_clk_out_obufds +( + .I (clk_out ), + .O (clk_out_p ), + .OB (clk_out_n ) +); + +// output tx frame to port +wire tx_frame; + +ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT (1'b0 ), + .SRTYPE ("ASYNC" ) +) u_tx_frame_oddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_2x_in ), + .D1 (tx_frame_i ), + .D2 (tx_frame_q ), + .Q (tx_frame ) +); + +OBUFDS u_tx_frame_obufds +( + .O (tx_frame_p ), // Diff_p output (connect directly to top-level port) + .OB (tx_frame_n ), // Diff_n output (connect directly to top-level port) + .I (tx_frame ) // Buffer input +); + +// ouput tx data to port +wire [5:0] tx_data; + +generate +for (mm = 0; mm < 6; mm = mm + 1) begin + +ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE" ), + .INIT (1'b0 ), + .SRTYPE ("ASYNC" ) +) u_tx_data_oddr ( + .CE (1'b1 ), + .R (1'b0 ), + .S (1'b0 ), + .C (clk_2x_in ), + .D1 (tx_buf_i[mm] ), + .D2 (tx_buf_q[mm] ), + .Q (tx_data[mm] ) +); + +OBUFDS u_tx_data_obufds +( + .O (tx_data_p[mm] ), // Diff_p output (connect directly to top-level port) + .OB (tx_data_n[mm] ), // Diff_n output (connect directly to top-level port) + .I (tx_data[mm] ) // Buffer input +); + +end +endgenerate + +endmodule diff --git a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/utils_1/imports/synth_1/ad9361_rx_map_cmos_dual.dcp b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/utils_1/imports/synth_1/ad9361_rx_map_cmos_dual.dcp new file mode 100755 index 00000000..53bf6ab3 --- /dev/null +++ b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.srcs/utils_1/imports/synth_1/ad9361_rx_map_cmos_dual.dcp @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:bc8604ed906d7d3cb81139ade8bee4f76335cac18ae199030341be3b1267be71 +size 24041 diff --git a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.xpr b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.xpr index 21e51e2d..d742a5aa 100644 --- a/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.xpr +++ b/modules/xc7z100ffg900-2/ad9361_mapping/ad9361_mapping.xpr @@ -89,13 +89,29 @@ - + + + + + + + + + + + + + + + + + @@ -104,7 +120,7 @@ - + @@ -112,7 +128,7 @@ - + @@ -138,8 +154,7 @@ @@ -150,9 +165,40 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -207,7 +261,7 @@ - +