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update dj_47dr_lmx vitis project

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decrease spi speed to garantee valid readback, disable lmx2594 ramp config, update some comments
This commit is contained in:
josh
2024-07-05 11:39:44 +08:00
parent 5f6348942f
commit bbc5e544a1
17 changed files with 123 additions and 112 deletions
Download Patch File Download Diff File Expand all files Collapse all files
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/_ide/bitstream/system_top.bit
LFS
BIN
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Binary file not shown.
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/_ide/hwspec.checksum
+1 -1
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@@ -1 +1 @@
1960514743
2311224066
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/README.md
+3 -3
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@@ -6,9 +6,9 @@
>
> Board: RFSOC_47DR_Z7045
>
> Device: xczu47dr-2ffve1156i(u15), lmk04828(u66), lmk2594(u67), lmk2594(u68)
> Device: xczu47dr-2ffve1156i(u15), lmk04828(u66), lmx2594(u67), lmx2594(u68)
>
> Date: 2024/07/04
> Date: 2024/07/05
>
> Archiver: Josh Gao
@@ -23,8 +23,8 @@
- 配置了 LMK04828，使用 10 MHz 输入时钟和 122.88 MHz VCXO 完成配置，PLL2 锁定，输出时钟频率为 245.76 MHz。
- 配置了两片 LMK2594，RF 部分使用外部采样时钟，采样率为 4.9152 Gbps。
- 初始化了 RF Data Converter，自发自收测试 ch5 发 ch5 收正常，信号功率和 EVM 等未测量。
- 降低 SPI 速率后 LMX2594 回读正常。
3. 存在的问题
- LMK04828 PLL1 锁定时间较长（约 1 分钟），单独配置 LMK04828 时同样存在该问题。
- LMK2594 SPI 回读异常，ILA 可以看见回读，但是 PS 程序中无回读，问题待查；通过 LED 灯判断两片 LMK2594 均锁定。
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/dev_profile/lmx2594_profile.c
+29 -29
View File
@@ -31,7 +31,7 @@ struct lmx2594_init_param lmx2594_dac_init_param = {
.spi_init = &lmx2594_dac_spi_init
};
const uint32_t lmx2594_default_config_len = 110;
const uint32_t lmx2594_default_config_len = 82;
const struct lmx2594_config lmx2594_default_config[] = {
// 0 ~ 78: General configuration
// 79 ~ 106: Ramping configuration
@@ -53,34 +53,34 @@ const struct lmx2594_config lmx2594_default_config[] = {
{ 0, 0x0000},
// Reverse order programming
{106, 0x0000},
{105, 0x0021},
{104, 0x0000},
{103, 0xD555},
{102, 0x3F97},
{101, 0x0011},
{100, 0x0000},
{ 99, 0x2AAB},
{ 98, 0x01A0},
{ 97, 0x0888},
{ 96, 0x0000},
{ 95, 0x0000}, // fixed
{ 94, 0x0000}, // fixed
{ 93, 0x0000}, // fixed
{ 92, 0x0000}, // fixed
{ 91, 0x0000}, // fixed
{ 90, 0x0000}, // fixed
{ 89, 0x0000}, // fixed
{ 88, 0x0000}, // fixed
{ 87, 0x0000}, // fixed
{ 86, 0x5879},
{ 85, 0xEC58},
{ 84, 0x0001},
{ 83, 0x54C9},
{ 82, 0x2961},
{ 81, 0x0000},
{ 80, 0x4000},
{ 79, 0x001F},
// {106, 0x0000},
// {105, 0x0021},
// {104, 0x0000},
// {103, 0xD555},
// {102, 0x3F97},
// {101, 0x0011},
// {100, 0x0000},
// { 99, 0x2AAB},
// { 98, 0x01A0},
// { 97, 0x0888},
// { 96, 0x0000},
// { 95, 0x0000}, // fixed
// { 94, 0x0000}, // fixed
// { 93, 0x0000}, // fixed
// { 92, 0x0000}, // fixed
// { 91, 0x0000}, // fixed
// { 90, 0x0000}, // fixed
// { 89, 0x0000}, // fixed
// { 88, 0x0000}, // fixed
// { 87, 0x0000}, // fixed
// { 86, 0x5879},
// { 85, 0xEC58},
// { 84, 0x0001},
// { 83, 0x54C9},
// { 82, 0x2961},
// { 81, 0x0000},
// { 80, 0x4000},
// { 79, 0x001F},
{ 78, 0x0003}, // [8:1] VCO_CAPCTRL_STRT
{ 77, 0x0000}, // fixed
{ 76, 0x000C}, // fixed
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/main.c
+14 -11
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@@ -118,21 +118,22 @@ int main(void)
}
}
// check pll2 lock status
// check pll1 lock status
Status = lmk04828_read(lmk04828_inst, 0x0182, &Lmk04828Read);
if ((Lmk04828Read & 0x02) == 0x02) {
xil_printf("LMK04828 PLL1 Locked.\r\n");
xil_printf("[LMK04828] PLL1 Locked.\r\n");
}
else {
xil_printf("LMK04828 PLL1 NOT lock!\r\n");
xil_printf("[LMK04828] PLL1 NOT lock. It takes a while for PLL1 to lock. Lock status is shown on LED.\r\n");
}
// check pll2 lock status
Status = lmk04828_read(lmk04828_inst, 0x0183, &Lmk04828Read);
if ((Lmk04828Read & 0x02) == 0x02) {
xil_printf("LMK04828 PLL2 Locked.\r\n");
xil_printf("[LMK04828] PLL2 Locked.\r\n");
}
else {
xil_printf("LMK04828 PLL2 NOT lock!\r\n");
xil_printf("[LMK04828] PLL2 NOT lock!\r\n");
}
/**********************************************************/
@@ -151,13 +152,15 @@ int main(void)
// check vco lock status
Status = lmx2594_read(lmx2594_dac_inst, 110, &Lmx2594Read);
if (((Lmx2594Read >> 9) & 0x03) == 0x02) {
xil_printf("LMX2594 for DAC Config Done.\r\n");
xil_printf("[DAC LMX2594] Config Done.\r\n");
}
else {
xil_printf("LMX2594 for DAC not lock!\r\n");
xil_printf("[DAC LMX2594] not lock!\r\n");
}
// set mux out to lock status
Status = lmx2594_write(lmx2594_dac_inst, 0x00, 0x259C);
xil_printf("[DAC LMX2594] SPI readback disabled, lock status is shown on LED.\r\n");
/**********************************************************/
/************* LMX2594 for ADC Configuration **************/
@@ -172,18 +175,18 @@ int main(void)
}
}
Status = lmx2594_read(lmx2594_adc_inst, 0, &Lmx2594Read);
// check vco lock status
Status = lmx2594_read(lmx2594_adc_inst, 110, &Lmx2594Read);
if (((Lmx2594Read >> 9) & 0x03) == 0x02) {
xil_printf("LMX2594 for ADC Config Done.\r\n");
xil_printf("[ADC LMX2594] Config Done.\r\n");
}
else {
xil_printf("LMX2594 for ADC not lock!\r\n");
xil_printf("[ADC LMX2594] not lock!\r\n");
}
// set mux out to lock status
Status = lmx2594_write(lmx2594_adc_inst, 0x00, 0x259C);
xil_printf("[ADC LMX2594] SPI readback disabled, lock status is shown on LED.\r\n");
print("Done.\n");
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/src/parameters.h
+1 -1
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@@ -64,7 +64,7 @@
#define SPI_DEVICE_ID 0
#define SPI_ENGINE_REF_CLK FCLK_CLK0_HZ
#define SPI_ENGINE_MAX_SPEED 2500000
#define SPI_ENGINE_MAX_SPEED 1000000
#define SPI_ENGINE_BASEADDR XPAR_AXI_SPI_ENGINE_AXI_SPI_ENGINE_BASEADDR
#define SPI_ENGINE_DATA_WIDTH 8
#define SPI_ENGINE_CS_DELAY 3
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic_system/_ide/scripts/debugger_dj_47dr_basic-default.tcl
+2 -2
View File
@@ -24,9 +24,9 @@ set mode [expr [mrd -value 0xFF5E0200] & 0xf]
targets -set -nocase -filter {name =~ "*A53*#0" && jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-5ba00477-0"}
rst -processor
dow /home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_platform/export/dj_47dr_platform/sw/dj_47dr_platform/boot/fsbl.elf
set bp_15_4_fsbl_bp [bpadd -addr &XFsbl_Exit]
set bp_8_53_fsbl_bp [bpadd -addr &XFsbl_Exit]
con -block -timeout 60
bpremove $bp_15_4_fsbl_bp
bpremove $bp_8_53_fsbl_bp
targets -set -nocase -filter {name =~ "*A53*#0" && jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-5ba00477-0"}
rst -processor
dow /home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_basic/Debug/dj_47dr_basic.elf
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_mts/_ide/bitstream/system_top.bit
LFS
BIN
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Binary file not shown.
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_mts/_ide/hwspec.checksum
+1 -1
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@@ -1 +1 @@
1960514743
2311224066
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_mts/src/README.md
+2 -2
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@@ -6,7 +6,7 @@
>
> Board: RFSOC_47DR_Z7045
>
> Device: xczu47dr-2ffve1156i(u15), lmk04828(u66), lmk2594(u67), lmk2594(u68)
> Device: xczu47dr-2ffve1156i(u15), lmk04828(u66), lmx2594(u67), lmx2594(u68)
>
> Date: 2024/07/04
>
@@ -23,8 +23,8 @@
- 配置了 LMK04828，使用 10 MHz 输入时钟和 122.88 MHz VCXO 完成配置，PLL2 锁定，输出时钟频率为 245.76 MHz。
- 配置了两片 LMK2594，RF 部分使用外部采样时钟，采样率为 4.9152 Gbps。
- 参考 RFSoC Eval 板卡完成了多通道同步，输出结果显示 RF-ADC 和 RF-DAC 均完成同步。
- 降低 SPI 速率后 LMX2594 回读正常。
3. 存在的问题
- LMK04828 PLL1 锁定时间较长（约 1 分钟），单独配置 LMK04828 时同样存在该问题。
- LMK2594 SPI 回读异常，ILA 可以看见回读，但是 PS 程序中无回读，问题待查；通过 LED 灯判断两片 LMK2594 均锁定。
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_mts/src/main.c
+55 -52
View File
@@ -200,22 +200,23 @@ int main(void)
}
}
// check pll2 lock status
Status = lmk04828_read(lmk04828_inst, 0x0182, &Lmk04828Read);
// check pll1 lock status
Status = lmk04828_read(lmk04828_inst, 0x0182, &Lmk04828Read);
if ((Lmk04828Read & 0x02) == 0x02) {
xil_printf("LMK04828 PLL1 Locked.\r\n");
xil_printf("[LMK04828] PLL1 Locked.\r\n");
}
else {
xil_printf("LMK04828 PLL1 NOT lock!\r\n");
xil_printf("[LMK04828] PLL1 NOT lock. It takes a while for PLL1 to lock. Lock status is shown on LED.\r\n");
}
Status = lmk04828_read(lmk04828_inst, 0x0183, &Lmk04828Read);
if ((Lmk04828Read & 0x02) == 0x02) {
xil_printf("LMK04828 PLL2 Locked.\r\n");
}
else {
xil_printf("LMK04828 PLL2 NOT lock!\r\n");
}
// check pll2 lock status
Status = lmk04828_read(lmk04828_inst, 0x0183, &Lmk04828Read);
if ((Lmk04828Read & 0x02) == 0x02) {
xil_printf("[LMK04828] PLL2 Locked.\r\n");
}
else {
xil_printf("[LMK04828] PLL2 NOT lock!\r\n");
}
/**********************************************************/
/************* LMX2594 for DAC Configuration **************/
@@ -230,16 +231,18 @@ int main(void)
}
}
// check vco lock status
Status = lmx2594_read(lmx2594_dac_inst, 110, &Lmx2594Read);
if (((Lmx2594Read >> 9) & 0x03) == 0x02) {
xil_printf("LMX2594 for DAC Config Done.\r\n");
}
else {
xil_printf("LMX2594 for DAC not lock!\r\n");
}
// check vco lock status
Status = lmx2594_read(lmx2594_dac_inst, 110, &Lmx2594Read);
if (((Lmx2594Read >> 9) & 0x03) == 0x02) {
xil_printf("[DAC LMX2594] Config Done.\r\n");
}
else {
xil_printf("[DAC LMX2594] not lock!\r\n");
}
Status = lmx2594_write(lmx2594_dac_inst, 0x00, 0x259C);
// set mux out to lock status
Status = lmx2594_write(lmx2594_dac_inst, 0x00, 0x259C);
xil_printf("[DAC LMX2594] SPI readback disabled, lock status is shown on LED.\r\n");
/**********************************************************/
/************* LMX2594 for ADC Configuration **************/
@@ -254,21 +257,21 @@ int main(void)
}
}
Status = lmx2594_read(lmx2594_adc_inst, 0, &Lmx2594Read);
// check vco lock status
Status = lmx2594_read(lmx2594_adc_inst, 110, &Lmx2594Read);
if (((Lmx2594Read >> 9) & 0x03) == 0x02) {
xil_printf("[ADC LMX2594] Config Done.\r\n");
}
else {
xil_printf("[ADC LMX2594] not lock!\r\n");
}
// check vco lock status
Status = lmx2594_read(lmx2594_adc_inst, 110, &Lmx2594Read);
if (((Lmx2594Read >> 9) & 0x03) == 0x02) {
xil_printf("LMX2594 for ADC Config Done.\r\n");
}
else {
xil_printf("LMX2594 for ADC not lock!\r\n");
}
Status = lmx2594_write(lmx2594_adc_inst, 0x00, 0x259C);
// set mux out to lock status
Status = lmx2594_write(lmx2594_adc_inst, 0x00, 0x259C);
xil_printf("[ADC LMX2594] SPI readback disabled, lock status is shown on LED.\r\n");
//add
// Mts Example
printf("RFdc MTS Example Test\r\n");
/*
* Specify the Device ID that is generated in xparameters.h.
@@ -286,7 +289,7 @@ int main(void)
//end add
print("Done.\n");
print("Done.\r\n");
return 0;
}
@@ -325,7 +328,7 @@ int RFdcMTS_Example(u16 RFdcDeviceId)
struct metal_init_params init_param = METAL_INIT_DEFAULTS;
if (metal_init(&init_param)) {
printf("ERROR: Failed to run metal initialization\n");
printf("ERROR: Failed to run metal initialization\r\n");
return XRFDC_FAILURE;
}
metal_set_log_handler(my_log_handler);
@@ -346,7 +349,7 @@ int RFdcMTS_Example(u16 RFdcDeviceId)
status = XRFdc_CfgInitialize(RFdcInstPtr, ConfigPtr);
if (status != XRFDC_SUCCESS) {
printf("RFdc Init Failure\n\r");
printf("RFdc Init Failure\r\n\r");
}
//add
@@ -354,7 +357,7 @@ int RFdcMTS_Example(u16 RFdcDeviceId)
//end add
printf("=== RFdc Initialized - Running Multi-tile Sync ===\n");
printf("=== RFdc Initialized - Running Multi-tile Sync ===\r\n");
/* ADC MTS Settings */
XRFdc_MultiConverter_Sync_Config ADC_Sync_Config;
@@ -366,7 +369,7 @@ int RFdcMTS_Example(u16 RFdcDeviceId)
/* Run MTS for the ADC & DAC */
printf("\n=== Run DAC Sync ===\n");
printf("\r\n=== Run DAC Sync ===\r\n");
/* Initialize DAC MTS Settings */
XRFdc_MultiConverter_Init (&DAC_Sync_Config, 0, 0, XRFDC_TILE_ID0);
@@ -375,13 +378,13 @@ int RFdcMTS_Example(u16 RFdcDeviceId)
status_dac = XRFdc_MultiConverter_Sync(RFdcInstPtr, XRFDC_DAC_TILE,
&DAC_Sync_Config);
if(status_dac == XRFDC_MTS_OK){
printf("INFO : DAC Multi-Tile-Sync completed successfully\n");
printf("INFO : DAC Multi-Tile-Sync completed successfully\r\n");
}else{
printf("ERROR : DAC Multi-Tile-Sync did not complete successfully. Error code is %u \n",status_dac);
printf("ERROR : DAC Multi-Tile-Sync did not complete successfully. Error code is %u \r\n",status_dac);
return status_dac;
}
printf("\n=== Run ADC Sync ===\n");
printf("\r\n=== Run ADC Sync ===\r\n");
/* Initialize ADC MTS Settings */
XRFdc_MultiConverter_Init (&ADC_Sync_Config, 0, 0, XRFDC_TILE_ID0);
@@ -390,9 +393,9 @@ int RFdcMTS_Example(u16 RFdcDeviceId)
status_adc = XRFdc_MultiConverter_Sync(RFdcInstPtr, XRFDC_ADC_TILE,
&ADC_Sync_Config);
if(status_adc == XRFDC_MTS_OK){
printf("INFO : ADC Multi-Tile-Sync completed successfully\n");
printf("INFO : ADC Multi-Tile-Sync completed successfully\r\n");
}else{
printf("ERROR : ADC Multi-Tile-Sync did not complete successfully. Error code is %u \n",status_adc);
printf("ERROR : ADC Multi-Tile-Sync did not complete successfully. Error code is %u \r\n",status_adc);
return status_adc;
}
@@ -400,12 +403,12 @@ int RFdcMTS_Example(u16 RFdcDeviceId)
* Report Overall Latency in T1 (Sample Clocks) and
* Offsets (in terms of PL words) added to each FIFO
*/
printf("\n\n=== Multi-Tile Sync Report ===\n");
printf("\r\n\r\n=== Multi-Tile Sync Report ===\r\n");
for(i=0; i<4; i++) {
if((1<<i)&DAC_Sync_Config.Tiles) {
XRFdc_GetInterpolationFactor(RFdcInstPtr, i, 0, &factor);
printf("DAC%d: Latency(T1) =%3d, Adjusted Delay"
"Offset(T%d) =%3d\n", i, DAC_Sync_Config.Latency[i],
"Offset(T%d) =%3d\r\n", i, DAC_Sync_Config.Latency[i],
factor, DAC_Sync_Config.Offset[i]);
}
}
@@ -413,7 +416,7 @@ int RFdcMTS_Example(u16 RFdcDeviceId)
if((1<<i)&ADC_Sync_Config.Tiles) {
XRFdc_GetDecimationFactor(RFdcInstPtr, i, 0, &factor);
printf("ADC%d: Latency(T1) =%3d, Adjusted Delay"
"Offset(T%d) =%3d\n", i, ADC_Sync_Config.Latency[i],
"Offset(T%d) =%3d\r\n", i, ADC_Sync_Config.Latency[i],
factor, ADC_Sync_Config.Offset[i]);
}
}
@@ -443,7 +446,7 @@ int RFdcMTS_Example(u16 RFdcDeviceId)
// for(Tile_Id=0; Tile_Id<4; Tile_Id++) {
// status = XRFdc_DynamicPLLConfig(RFdcInstPtr, 1, Tile_Id, XRFDC_EXTERNAL_CLK, 3932.16, 3932.16);
// if (status != XRFDC_SUCCESS) {
// printf("XRFdc DAC DynamicPLLConfig Failure\n\r");
// printf("XRFdc DAC DynamicPLLConfig Failure\r\n\r");
// }
// }
@@ -453,7 +456,7 @@ int RFdcMTS_Example(u16 RFdcDeviceId)
// {
// status = XRFdc_SetInterpolationFactor(RFdcInstPtr, i, j, XRFDC_INTERP_DECIM_16X);
// if (status != XRFDC_SUCCESS) {
// printf("XRFdc DAC SetInterpolationFactor Failure\n\r");
// printf("XRFdc DAC SetInterpolationFactor Failure\r\n\r");
// }
// }
// }
@@ -466,12 +469,12 @@ int RFdcMTS_Example(u16 RFdcDeviceId)
{
status = XRFdc_SetMixerSettings(RFdcInstPtr, XRFDC_DAC_TILE, i, j, &DAC_Mixer_Settings);
if (status != XRFDC_SUCCESS) {
printf("XRFdc_SetMixerSettings FAILED \n\n");
printf("XRFdc_SetMixerSettings FAILED \r\n\r\n");
//return XRFDC_FAILURE;
}
status = XRFdc_ResetNCOPhase(RFdcInstPtr, XRFDC_DAC_TILE, i, j);
if (status != XRFDC_SUCCESS) {
printf("XRFdc_ResetNCOPhase FAILED \n\n");
printf("XRFdc_ResetNCOPhase FAILED \r\n\r\n");
//return XRFDC_FAILURE;
}
}
@@ -493,7 +496,7 @@ int RFdcMTS_Example(u16 RFdcDeviceId)
// for(Tile_Id=0; Tile_Id<4; Tile_Id++) {
// status = XRFdc_DynamicPLLConfig(RFdcInstPtr, 0, Tile_Id, XRFDC_EXTERNAL_CLK, 3932.16, 3932.16);
// if (status != XRFDC_SUCCESS) {
// printf("XRFdc ADC DynamicPLLConfig Failure\n\r");
// printf("XRFdc ADC DynamicPLLConfig Failure\r\n\r");
// }
// }
@@ -504,12 +507,12 @@ int RFdcMTS_Example(u16 RFdcDeviceId)
{
status = XRFdc_SetMixerSettings(RFdcInstPtr, XRFDC_ADC_TILE, i, j, &ADC_Mixer_Settings);
if (status != XRFDC_SUCCESS) {
printf("XRFdc_SetMixerSettings FAILED \n\n");
printf("XRFdc_SetMixerSettings FAILED \r\n\r\n");
//return XRFDC_FAILURE;
}
status = XRFdc_ResetNCOPhase(RFdcInstPtr, XRFDC_ADC_TILE, i, j);
if (status != XRFDC_SUCCESS) {
printf("XRFdc_ResetNCOPhase FAILED \n\n");
printf("XRFdc_ResetNCOPhase FAILED \r\n\r\n");
//return XRFDC_FAILURE;
}
}
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_mts_system/_ide/scripts/debugger_dj_47dr_mts-default.tcl
+2 -2
View File
@@ -24,9 +24,9 @@ set mode [expr [mrd -value 0xFF5E0200] & 0xf]
targets -set -nocase -filter {name =~ "*A53*#0" && jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-5ba00477-0"}
rst -processor
dow /home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_platform/export/dj_47dr_platform/sw/dj_47dr_platform/boot/fsbl.elf
set bp_17_50_fsbl_bp [bpadd -addr &XFsbl_Exit]
set bp_15_53_fsbl_bp [bpadd -addr &XFsbl_Exit]
con -block -timeout 60
bpremove $bp_17_50_fsbl_bp
bpremove $bp_15_53_fsbl_bp
targets -set -nocase -filter {name =~ "*A53*#0" && jtag_cable_name =~ "Digilent JTAG-HS1 210512180081" && jtag_device_ctx=="jsn-JTAG-HS1-210512180081-5ba00477-0"}
rst -processor
dow /home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_mts/Debug/dj_47dr_mts.elf
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_platform/hw/system_top.bit
LFS
BIN
View File
Binary file not shown.
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_platform/hw/system_top.xsa
LFS
BIN
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Binary file not shown.
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_platform/platform.tcl
+5
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@@ -30,3 +30,8 @@ platform generate
platform generate -domains zynqmp_fsbl
platform config -updatehw {/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_lmx/system_top.xsa}
platform generate -domains
platform active {dj_47dr_platform}
platform config -updatehw {/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_lmx/system_top.xsa}
platform generate -domains
platform config -updatehw {/home/josh/Workspace/vivado/vivado_pub/projects/dj_47dr/dj_47dr_lmx/system_top.xsa}
platform generate -domains
projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_platform/tempdsa/system_top.bit
LFS
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projects/dj_47dr/dj_47dr_lmx/vitis_classic/dj_47dr_platform/tempdsa/system_top.xsa
LFS
BIN
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